diff --git a/Logic/68030-68000-bus.vhd b/Logic/68030-68000-bus.vhd index 4ddbdb3..6a74d26 100644 --- a/Logic/68030-68000-bus.vhd +++ b/Logic/68030-68000-bus.vhd @@ -268,16 +268,12 @@ begin --interrupt buffering to avoid ghost interrupts - --if(CLK_000_NE='1')then - IPL_D0<=IPL; - if(IPL = IPL_D0)then - IPL_030<=IPL; - end if; - --end if; + IPL_D0<=IPL; + if(IPL = IPL_D0 and CLK_000_PE = '1')then + IPL_030<=IPL; + end if; -- as030-sampling and FPU-Select - - if(AS_030 ='1') then -- "async" reset of various signals AS_030_000_SYNC <= '1'; DSACK1_INT <= '1'; @@ -323,7 +319,7 @@ begin case (SM_AMIGA) is when IDLE_P => --68000:S0 wait for a falling edge RW_000_INT <= '1'; - if( CLK_000_D(4)='0' and CLK_000_D(5)= '1' and AS_030_000_SYNC = '0' and nEXP_SPACE ='1')then -- if this a delayed expansion space detection, do not start an amiga cycle! + if( CLK_000_D(3)='0' and CLK_000_D(4)= '1' and AS_030_000_SYNC = '0' and nEXP_SPACE ='1')then -- if this a delayed expansion space detection, do not start an amiga cycle! SM_AMIGA<=IDLE_N; --go to s1 end if; when IDLE_N => --68000:S1 place Adress on bus and wait for rising edge, on a rising CLK_000 look for a amiga adressrobe @@ -365,8 +361,8 @@ begin --end if; --go to s7 dsack is sampled at the falling edge of the 030-clock - if(CLK_000_D(2)='0' and CLK_000_D(3)='1')then - --if( CLK_000_NE ='1') then + --if(CLK_000_D(0)='0' and CLK_000_D(1)='1')then + if( CLK_000_NE ='1') then SM_AMIGA<=END_CYCLE_N; DSACK1_INT <='0'; end if; @@ -463,7 +459,7 @@ begin -- bus drivers AMIGA_ADDR_ENABLE <= '0'; - AMIGA_BUS_ENABLE_HIGH <= '0' WHEN BGACK_030_INT ='1' and AS_030_000_SYNC='0' else --not (SM_AMIGA = IDLE_P or (SM_AMIGA = END_CYCLE_N and CLK_000 = '1')) ELSE + AMIGA_BUS_ENABLE_HIGH <= '0' WHEN BGACK_030_INT ='1' and AS_030_000_SYNC='0' and AS_030 = '0' else --not (SM_AMIGA = IDLE_P or (SM_AMIGA = END_CYCLE_N and CLK_000 = '1')) ELSE '0' WHEN BGACK_030_INT ='0' AND AMIGA_BUS_ENABLE_DMA_HIGH = '0' ELSE '1'; AMIGA_BUS_ENABLE_LOW <= '0' WHEN BGACK_030_INT ='0' AND AMIGA_BUS_ENABLE_DMA_LOW = '0' ELSE diff --git a/Logic/68030_TK.STY b/Logic/68030_TK.STY index b15bf23..a807e4b 100644 --- a/Logic/68030_TK.STY +++ b/Logic/68030_TK.STY @@ -1,4 +1,6 @@ [STRATEGY-LIST] Normal=True, 1412327082 +[TOUCHED-REPORT] +Design.tt4File=1475958360 [synthesis-type] tool=Synplify diff --git a/Logic/68030_TK.SVF b/Logic/68030_TK.SVF deleted file mode 100644 index 9f4a4c6..0000000 --- a/Logic/68030_TK.SVF +++ /dev/null @@ -1,2803 +0,0 @@ - - -! Lattice Semiconductor Corp. -! Serial Vector Format (.SVF) File. -! User information: -! File name: C:\USERS\MATZE\AMIGA\HARDWAREHACKS\68030-TK\GITHUB\LOGIC\68030_TK.SVF -! CREATED BY: ispVM System Version 18.1 -! CREATION DATE: Fri Sep 23 23:32:23 2016 -! Device: M4A5-128/64 Erase,Program,Verify C:\Users\Matze\Amiga\Hardwarehacks\68030-TK\GitHub\Logic\68030_tk.jed -! LATTICE_NOTE "Device" "M4A5-128/64" -! LATTICE_NOTE "Checksum" "D04F" - - - - - - -! Initialize - -! Row_Width :792 -! Address_Length :80 -HDR 0; -HIR 0; -TDR 0; -TIR 0; -ENDDR IDLE; -ENDIR IDLE; -FREQUENCY 9.00e+005 HZ; -STATE IDLE; - - -! Check the IDCODE - -! Shift in IDCODE(0x01) instruction -SIR 6 TDI (01); -SDR 32 TDI (00000000) - TDO (2756A157) - MASK (0FFFFFFF); - - -! Program Bscan register - -! Shift in Preload(0x02) instruction -SIR 6 TDI (02); -SDR 198 TDI (00000000000000000000000000000000000000000000000000); - - -! Enable the programming mode - -! Shift in PROGRAM MODE(0x0F) instruction -SIR 6 TDI (0F); -RUNTEST IDLE 3 TCK 2.00E-002 SEC; -! Shift in Password(0x08) -SDR 5 TDI (08); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000000000); - - -! Erase the device - -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (FFFFFFFFFFFFFFFFFFFF); -! Shift in ERASE ALL(0x05) instruction -SIR 6 TDI (05); -RUNTEST IDLE 3 TCK 1.00E-001 SEC; - - -! Full Address Program Fuse Map - -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -! Prog Init/shift row all 0s -SDR 80 TDI (00000000000000000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Prog Init/shift col all 0s -SDR 792 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (80000000000000000000); -! Data Row = 1 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FF800FFD703E003EF8210BFE7DFFFA7EF5E9FFFF7AF420FFCFFC7F3E7FFD3FFEF7E7841FF9FF8FF - FC67FDF3BC2FC719FFF3FFFFFFFC3F3FF7BEFFE307FE7FEF81FFBE07FEF9DFFBDF7FCF8C7FFE7BCF - F8CF1BE7847DF9FFCFFFFE1FFFFFE5FFE0BDFF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (40000000000000000000); -! Data Row = 2 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDE1BE77FEF8E109FE7DFFFA7F6BE9FF07B5F420FDCFF87F3E7FFD3FFEF7E7841FB9FF8FF - FC67FFF3FC1FC719F7F3FFFFFFFC3FBFF7FEFFE305FE7FEF8DFFBE37FEF99FFBFE3FCF8C7FFE3BCF - F8CF1BE7847FF9FFCFF7FF1FFFFBE7FFE0BD7F); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (20000000000000000000); -! Data Row = 3 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDF1BE77FEF8E109FE7DFFFA7FFFE9FFFFFFF420FFCFFC773E7FFD3FFEF7E7841FF9FF8FF - FC67FFF3FC3FC718EFF3FFFFFFFC3FBFF7FEFFE303FE7FEF8DFFBE37FEF9DFFBFF7FCF8C3FFE7BCF - F8CF1BE7847EF9FFCFFFFF1FFFFFE7FFE03DFF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (10000000000000000000); -! Data Row = 4 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDD1BE77BEF8E10BFE7DFFFA7FFFE9FFFFFFF420FFCFFC7F3E7FFD3FFEF7E7841FB9FF8FF - FC67FFF3FC3FC7193FF3FFFFFFFC3FBFF7FEFFE307EE7FEF85FFBE37FEF9DFFBFF7F8F8C7FFE7BCF - F8CF1BE7847FF9FFCFFFFF1FFFFFE7FFE0BDF7); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (08000000000000000000); -! Data Row = 5 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFA7C7FFA7FFFE8FFFFFFF420FFCFFC7F3E7FFD3FFEF7E7841FB9FF8DF - FC27FFF1FC3FC319FFB3FFFFFFFC3FBFF7FEFFE307FE7FEF8DFFBE37FEF9DFFBFF7FCF8C7F7E7BCF - F8CF1BE7847FB9FFCFFFFF1FFFFFE7FFE0BDF7); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (04000000000000000000); -! Data Row = 6 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDD1BE77BEF8E10BFE7DFFFA7FFFE9FFFFFFF420F7CFFC7F3E7FFD3FFEF7E5841FF9FF8FF - FC47FFF3FC3FC719FFF3FFFFFFFC3FBFF7FEFFE205FE7FEF8DFFBE17FEF9DFFBFF7ECF8C7FFE7BCF - F8CF1BE7847FF9FFCFEFFF1FFFFFE7FFE0BDFF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (02000000000000000000); -! Data Row = 7 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FF3CEFFDF13E77FEF8E10B7E7DFF7A7FFFE9FFFFFFF420FF8FFC7F3E7FFC3FDEF3E7040DF9FF8FF - FC67FFF3FC3FC719FFF3FFFFFFFC3FBFF7FEFFE305FE7FEF89FFBE37FEF9DFFBFF7FCF8C7FFE5BCB - F8CF1BE7845FF9FFCFFFFF1FFFFFE7FFE0BDFD); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (01000000000000000000); -! Data Row = 8 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7FFFE9FFFFFFF420FFCFFC7F3E7FFD3FFEF7E7841FF9FF0FF - FC67FFF3FC3FC719FFB3FFFFFFFC3FBFF7FCFFE307FE7FEF8DFFBE27FEF9DFFBFF7BCF8C7FFE7BCF - F8CF1BE7847BF9FFCFFFFF1FBFFFE7FFE0BDFF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00800000000000000000); -! Data Row = 9 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFACEFFC90BE123EF8A10BFE7DFFFA77E7E9DF9FFFF420FFCFFC7F3E7FFD3FFEF7E7841FF9FF8FF - FC67FFF3FC3FC719FFD3FFFFFFFC3FBFF7FEFFE307F67FEF8DFFBE37FEF9DFFAFF7FCF8C2FFE79CF - F88D1BE6847FF9FFCFFFFF1FFFFFE1FFE03DDF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00400000000000000000); -! Data Row = 10 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFB88FFD71BE77FEF8E10AFE7DFFFA7BF9E9EFE7E0F420FECFFC7F3E7EFD333EF7E7841FF1FF8FF - FC67FFF3FC3FC701FFF3FFFFDFFC2FBFF7FEFFE307FE7FEF8DFFBE37FEF9DFFB7F7F8F8C7FFE7B4F - F8CB1BE5847BF9FFCFFFFF1FFFFFE7FFE0BDFF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00200000000000000000); -! Data Row = 11 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFA7C7FFA7FFFE8FFFFFFF420FF4FFC7F3E7FFD3FFEF7E7841FE9FF8FF - FC67FFF3FC3FC711FFD3FFFFFFFC3FBFF7FEFFE307F67FEF8DFFBE37FEF9DFF97F7FCF8C7FFE7BCF - F8CF1BE7847FE9FFCFFFFF1FFFFFE7FFE0BDFF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00100000000000000000); -! Data Row = 12 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FF3CEFFDF1BE77FEF8E10BFE7DFFF87FBFE1FFFFFFF420FFCFFC7B3E7FFC3FDEF3E7040FF9FF8FF - FC67FFF3FC3FC719FFF3FFFFDFFC2FBFF7FEFFE307FE7FEF8DFFBE37FEF9DFFBFF7BCF8C7FFE73CE - F8CF1BE7847FF9FFCFFFFF17FFFFE7FFE0BDBF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00080000000000000000); -! Data Row = 13 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7FFFE9FFFFFFF420FF4FFC773E7FFD3FFEF7E7841FF9FF8FF - FC67FFF3FC3FC719FFF3FFFFFFFC3FBFF7FEFFE207FE7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE7BCF - F8CF1BE7847FF9FFCFFFFF1FFFFFE7FFE0BDFF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00040000000000000000); -! Data Row = 14 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA705FE9FFFFFFF420FFCFFC7F3E7FFD3FFEF7E7841FD9FF8FF - FC67FFF3FC3FC719FFF3FFFFFFFC3FBFF7FEFFE1077E7FEF8DFFBE37FEF8DFFBFF77CF8C7FFE7BCF - F8CF1BE7843DF9FFCFFFFF1FFFFFE7FFE0A0FF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00020000000000000000); -! Data Row = 15 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDD1BE77BEF8E10B7E7DFFFA7F75E9FFFFBAF420FF8FFC7F3E7FFD3FFEF7E7841FF9FF8FF - FC647FF3FC3FC719FBF3FFFFFFFC3FBFF7FEFFE307DE7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE7BCF - F8CF0BE7847DF9FFC3FFFF1FFFFFE7FFE0BDFF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00010000000000000000); -! Data Row = 16 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7EEBE9FD8775F420FFCFFC7F3E7FFD3FFEF7E7841FF9FF8FF - FC67FFF3FC3FC7187FF3FFFFDFFC2FBFF7FEFFE307FE7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE79CF - F8CF13E7847FF9FFCFFFFF1FFFFFE7FFE08DDF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00008000000000000000); -! Data Row = 17 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7BE7E9EF9FFFF420FF4FFC7F3E3FFD3FFEF7E7841BF9FF8FF - FC67FFF3FC3FC711FFF3FFFFFFFC3FBFF7FEFFE301FE7FEF8DFFBE37FEF9DFFBBF5FCF8C7FFE7BC7 - F8CF1BE7847BF9FFCFFFFF1FFFFFE7FFE0BCFF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00004000000000000000); -! Data Row = 18 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA77F9E9DFE3F0F420FFCFFC7F3E7FFD3C3EF7E3841FF9FF8FF - FC67FFF37C3FC519FBF3FFFFFFFC3FBFF7FEFFE307FE7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE3BCF - F8CF1BE7847FF9FFCFFFFF1FFFFFE7FFE03DFF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00002000000000000000); -! Data Row = 19 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDF1BE77FEF8E109FE7D9FFA7FFFE9FFFFFFF420FF8FFC3F3E7FFD3FFEF7E7841FF1FF8FF - FC67FFF2FC3FC719FFF3FFFFDFFC2FBFF7FEFFE307FE7FEF8DFFBE37FEF9DFFAFF7ECF847FFE7BCF - F8CF1BE78477F9FFCDFFFF0FFFFFE7FFE0BDDF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00001000000000000000); -! Data Row = 20 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDF1BE77FEF8E00BFE7C7FFA7FFFE8FFFFFFF420FFCFFC7F3E7FFD3FFEF7E7841FF9FF8FF - FC67FFF3FC3FC719FFE3FFFFFFFC3FBFF7FEFFE305FE7FEF8DFFBE37FEF9DFF9FF7FCF887FFE7BCF - F8CF1BE7847FF9FFCFFFFF1FFFFFE7FFE0BDFF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000800000000000000); -! Data Row = 21 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFB44FFD71BE77FEF8E10BFC7DDFFA5FFFE9FFFFFFF420FF8FFC7F3E7FFD3FFEF7E7841FF9FF85F - FC65FFF0FC3FC3117FE3FFFFFFFC3FBFF7FEFFE307FE7FEF8DFFBE37FEF9DFFBFF3FCF8C7FFE7ACF - F8CB1BE5847FF1FFCFFFFF1FFFFFC3FFE09DFE); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000400000000000000); -! Data Row = 22 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFACEFFC90BE113EF8A10BFE7CFFFA3FFFE97FFFFFF420FFCFFC7F3E7FFD3FFEF7E7841FF9FF8FF - FC63FFF3FC3FC718FFF3FFFFFFFC3FBFF7FEFFE307FE7FEF8DFFBE37FEF9DFFBDF7FCF8C1FFE79CF - F8871BE3847FF9FFC5FFFF0FFFFFE7FFE0B5FF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000200000000000000); -! Data Row = 23 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7FFFE9FFFFFFF420FF8FFC7F3E7FFD3FFEF7E7841DF9FF8FF - FC67FFF3FC2FC719FFE3FFFFFFFC3FBFF7FEFFE307EE7FEF8DFFBE37FEF8DFFBFF7ECF887FFE7BCF - F8CF1BE7847FF9FFCFFFFF1FFFFFE7FFC0BDFF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000100000000000000); -! Data Row = 24 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7C7FFA7FFFE8FFFFFFF420FFCFFC773E7FFD3FFEF7E7841FF9FF8FF - FC67FFF3FC3FC719FFF3FFFFDFFC2FBFF7FEFFE307FE7FEF8DFFBE37FEF95FFBFF7FCF847FFE7BCF - F8CF1BE7847FF1FFCFFFFF1FFFFFE7FFE0BDFE); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000080000000000000); -! Data Row = 25 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFD71BE77FEF8E10BFE7DFFFA4FFFE9FFFFFFF420FF4FFC7F3E7FFD3FFEF7E7841EF9FF8FF - FC63FFF3FC3FC718FFF3FFFFFFFC3FBFF7FEFFE307BE7FEF8DFFBE37FEF9DFFBFF7FCF8C4FFE7BCF - F8CF1BE7847FF9FFCFFFFF1FFFFFE7FFE0BDDF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000040000000000000); -! Data Row = 26 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFC7DFFFA3FFFE9FFFFFFF420FFCFFC773E7FFD3FFEF7E7841FF9FF8FF - FC67FFF3FC3FC7197FD3FFFFFFFC3FBFF7FEFFE303FE7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE7BCF - F8CF1BE7847FF1FFCFFFFF1FFFFFE7FFE03DFF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000020000000000000); -! Data Row = 27 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA3FFFE9BFFFFFF420FFCFFC7F3E7EFD3FFEF7E7841FE9FF8FF - FC63FFF3FC3FC718FFF3FFFFFFFC3FBFF7FEFFE303FE7FEF8DFFBE37FEF9DFFAFF7F4F8C7FFE7BCB - F8CF1BE7847FF9FFCFFFFF1FFFFFE7FFE03DFF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000010000000000000); -! Data Row = 28 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7C5FFA6FFFE8FFFFFFF420DFCFFC7F3E7FFD333EF7E7841FF9FF89F - FC66FFF0FC3FC31977F3FFFFFFFC3FBFF7FEFFE307EE7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE7BCF - F8CF1BE7847FD9FFCFFFFF1FFFFFE7FFE0BDF7); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000008000000000000); -! Data Row = 29 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7FFFE9FFFFFFF400FFCFFC7F3E7FFD3FFEF7E7841FF9FF8FF - FC67FFF3FC3FC719FFF3FFFFEFFC3FBFF7FEFFE307FE7FEF8DFFBE37FEF95FFBFF7FCF8C7FFE7BCF - F8CF1BE7807FF9FFCFFFFF1FFFFFE7FFE0BDBF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000004000000000000); -! Data Row = 30 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7FFFE9FFFFFFF420BFCFFC5F3E7FFD3FFEF7E6841BF9FF8FE - FC67FFF3FC3FC719FF73FFFFFFFC3FBFF7FEFFE3077E7FEF8DFFBE37FEF9DFFBFF7DCF8C7FFE7BCF - F8CF1BE78477F9FFCFFFFF1FFFF7E7FFE0BDFF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000002000000000000); -! Data Row = 31 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FF9CEFFDF0BE67FEF8A10B7E7DFFFA7FFFE9FFFFFFF420FFCFFC7F3E7FFD3FFEF7E7841FF9FF8FF - FC67FFF3FC3FC719FFF3FFFFDFFC2FBFF7FEFFE306FE7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE7BCF - F8CF1BE7847FF9FFCFFFFF1FDFFFE7FFE0BDFD); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000001000000000000); -! Data Row = 32 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDF1BE37FEF8E10BFE7DFFFA7FFFE9FFFFFFF420FFCFFC7F3E7FFD3FFEF7E7841FF9FF8FF - FC67FFF3FC3FC718FEF3FFFFFFFC3FBFF7FEFFE307FE7FEF8DFFBE37FEF8DFFBFF7ECF8C7FFE7BCF - F8CF1BE7847FF9FFCFF7FF1FFFFBE7FFE0BDFF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000800000000000); -! Data Row = 33 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7FFFE9FFFFFFF420FFCFFC7D3E7FFD3FFEF7E7841FF9FF8FE - FC67FBF37C3FC719F7F3FFFFFFFC3FBFF7FEFFE307FE7FEF8DFFBE37FEF9DFFBEF7FCF8C7FFE7BCF - F8CF1BE7847FF9FFCFFFFF1FFFFFE3FFE0BDFF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000400000000000); -! Data Row = 34 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDF1BE77FEF8E101FE7DFFFA7FFFE9FFFFFFF420FFCFFC7F3E7FFD3FFEF7E7841DF9FF8FF - FC67FFF3FC3FC719FFF3FFFFDFFC2FBFF7FEFFE3077E7FEF8DFFBE37FEF9DFFBFF3FCF8C7FFE7BCF - F8C01BE08477F9FFCFFFFF1FBFFFE7FFE0BCFF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000200000000000); -! Data Row = 35 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7FFFE9FBB6FCF420FBCFFC7F3E7FFD3FFEF7E7841DF9FF8FF - FC67FFF3FC3FC719EFF3FFFFFFFC3FBFF7FEFFE307EE7FEF8DFFBE37FEF8DFFBFF7FCF8C7FFE7BCF - F8CF1BE7847FF9FFCFFFFF1FFFFFE7FFE03DFF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000100000000000); -! Data Row = 36 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFCF1BE73FEF8E109FE7DFFFA7DE1E9F7CDF3F420FFCFFC773E7FFD3FFEF7E7841FF9FF8FF - FC67FFF3FC3FC709FFF3FFFFDFFC2FBFF7FEFFE307FE7FEF8DFFBE37FEF9DFFBFF7F4F8C7FFE7BCF - F8CF1BE7845F79FFCFFFFF1FFFFFE7FFE0BDFB); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000080000000000); -! Data Row = 37 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCCFFDF1BE74FEF8E10AFE7DFFF87FBFE1FFFFFFF420EFCFFC7F3E7FFD0CFEF7E7841FD9FF8FF - FC67FFF3FC3FC719FFF3FFFFFFFC3FBFF7FEFFE303BE7FEF8DFFBE37FEF9DFFBFF7FCF8C7FBE7BCE - F8CF1BE7847DF9FFCFFFFE1FFFFBE7FFE0BDBF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000040000000000); -! Data Row = 38 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBC2FFDF1BE77FEF8E10BFE7DEFFA7FFFE9FFFFFFF420FFCFFC7F3E7FFD3FFEF7E7841FF9FF8FF - FC27FFF3FC3FC719FFB3FFFFFFFC3FBFF7FEFFE307FE7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE7BCF - F8CF1BE7847FF9FFCFFFFF1FFFFFE7FFE0BDFF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000020000000000); -! Data Row = 39 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFC81BE733EF8E10B7E7DDFFA7FFFE9FFFFFFF420FFCFFC7F3E7FFD3FFEF7E7841FF9FF8FF - FC67FFF3FC3FC719FFF3FFFFFFFC3FBFF7FEFFE307FE7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE7BCF - F8CF1BE7847FF9FFCFFFFF1FFFFFE7FFE0BDFF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000010000000000); -! Data Row = 40 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFD71BE77FEF8E10BFE7D7FFA7FFFE9FFFFFFF420F7CFFC7F3E7FFD3FFEF7E7841FF9FF8FF - FC67FFF3FC3FC719FFF3FFFFFFFC3F3FF7FCFFE302FE7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE7BCF - F8CF1BE7847FF9FFCFFFFF1FFFFFE7FFE03D7F); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000008000000000); -! Data Row = 41 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7FFFE9FFFFFFF420FFCFFC7F3E7F7D3FFEF7E4841FF9FF8FF - FC67FFF3FC3FC719FDF3FFFFFFFC3FBFF7FEFFC107FE7FEF85FFBE17FEF9DFFBFD7FCF8C7FFE5BCB - F8CF1BE7845FF9FFCFFFFF1FFFFFE7FFE081FE); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000004000000000); -! Data Row = 42 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FF3CEFFDF1BE77FEF8E10AFE7DFFF87FBFE1FFFFFFF420DFCFFC6F3E7FFC001EF3E3000BF9FF8FF - FC47FBF3FC3FC719FFF3FFFFFFFC3FBFF7BEFFE206FE7FEF89FFBE27FEF9DFFBFF5FCF8C7FBE33C6 - F8C01BE0843BF9FFCFFFFF1FFFFFE7FFE0BDFF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000002000000000); -! Data Row = 43 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7FFFE9F7B5FCF420FFCFF87F3E6FFD003EF7E0841FF9FF01F - FC07FFF07C3FC100FFF3FFFFFFFC1FBFF7FEFFE307FA7FEF8DFFBE37FEF9DFFBFF7FCF8C0FFE7BCF - F8C01BE0841FF9FFC1FFFF07FFF7E7FFE081FF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000001000000000); -! Data Row = 44 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDB1BE777EF8E10AFE7DFFFA7FC1E9FBCEF3F420FECFFC7E3E7FBD3FFEF7E78417F9FF8FF - FC67FFF3FC3FC719AFF3FFFFFFFC3FBFF7FEFFE207FE7FEF8DFFBE37FEF9DFF87F6FCF8C7FFE6BCD - F8CF1BE78477F9FFCFFFFF1FFFFFE6FFE0BCFF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000800000000); -! Data Row = 45 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FF9CEFFDF0BE77FEF86109FE7DFFFA7FFFE9FFFFFFF420FFCFFC7F3E7FFD3FFEF7E7841FF9FF8FF - FC67FFF3FC3FC719FFF3FFFFFFFC3FBFF7FEFFE307F67FEF8DFFBE37FEF9DFFBFB7FCF8C7FFE5BCF - F8CF1BE7847FF9FFCFEFFF1FFFFFE7FFE0BDFF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000400000000); -! Data Row = 46 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDF1BE57FEF8E10BFE7DFFFA7FFFE9FFFFFFF420FFCFFC7F3E6FFD3FFEF7E7841FD9FF8FF - FC67FFF3FC3FC719FFF3FFFFDFFC2FBFF7FEFFE307FE7FEF8DFFBE37FEF9DFFBF77DCF8C7F7E7BCF - F8CF1BE7847FE9FFCFFFFF1FFFFFE7FFE0BDFD); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000200000000); -! Data Row = 47 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7FFFE93FFFFFF420FECFFC7F3E7DFD157EF7E7841FF9FF8FF - FC63FFF3FC3FC719FFF3FFFFFFFC3FBFF7FEFFE307FE7FEF8DFFBE37FEF9DFFBFB7FCF8C7FFE7BCF - F84F13E7847FF9FFCFFFFF1FFFFFE7FFE09DFB); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000100000000); -! Data Row = 48 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDD1BE77BEF8E10BF67DFFFA7FFFE8FFFFFFF420FFCFFC7F3E7BFD2ABEF7E7841FB9FF8FF - FC677FF3FC3FC7187FB3FFFFFFFC3FBFF7FEFFE307FE7FEF8DFFBE37FEF9DFFBF77DCF8C7FFE7BCF - F8CF0BE7847FD9FFCFFFFF1FFFFFE7FFE0ADFF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000080000000); -! Data Row = 49 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBC2FFDF1BE77FEF8E10BBE7C1FFA7041E8010020F420FFCFFC7F3E3FFD3FFEF7E7841DF9FF8FF - FC63FFF3FC3FC718FFD3FFFFFFFC3FBFF7FEFFE303FE7FEF8DFFBE37FEF9DFFBBF6FCF8C7FFE79CF - F88F1BE7847FE9FFCFFFFF1FFFFFE7FFE0BDFF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000040000000); -! Data Row = 50 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7FFFE9FFFFFFF420BFCFFC7F3E7FFD03FEF7E3841FF9FF8FF - FC677FF3FC3FC7197FF3FFFFFFFC3FBFF7FEFFE307F67FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE7B8F - F8CF1BE7847FF9FFCFFFFF1FFFFFE7FFE0BDFF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000020000000); -! Data Row = 51 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FF90EFFDF0BE17FEF8A10BBE7DFFFA7FFFE9FFFFFFF420FFCFFC7F3E7FFD3FFEF7E7841FF9FF8FF - FC67FFF1FC3FC719FFF3FFFFFFFC3FBFF7FEFFE307FA7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE7BCF - F8CF1BE7847FF9FFCFFFFF1FFFFFE7FFE0BDFF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000010000000); -! Data Row = 52 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFACEFFDF1BE77FEF8E10BFE7DFFFA7FFFE9FFFFFFF420FFCFFC7F3E7FFD3FFEF7E7841FF9FF8FF - FC67FFF3FC3FC719FFD3FFFFDFFC2FBFF7FEFFE307FE7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE7BCF - F8CF1BE7847FF9FFCFFFFF1FFFFFE7FFE09DFD); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000008000000); -! Data Row = 53 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7FFFE9FFFFFFF420FFCFFC7F3E5FFD3FFEF7E7841FF9FF8FF - FC67FFF3FC3FC719FFF3FFFFFFFC3FBFF7FEFFE3077E7FEF85FFBE17FEF9DFFBFF7FCF8C7FFE7BCF - F8CF1BE7847FF9FFCFFFFF1FFFFFE7FFE0BDBF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000004000000); -! Data Row = 54 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7FFFE9FFFFFFF420FFCFFC7F3E7FFD003EF7E78417F9FF8FF - FC67FFF3FC3FC719FFF3FFFFFFFC3FBFF7FEFFE303FE7FEF8DFFBE37FEF9DFFBFF5FCF8C7FFE7BCF - F8CF1BE7847FF9FFCFFFFF1FFFFFE7FFE03DFF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000002000000); -! Data Row = 55 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7FFFE9FFFFFFF420FDCFFC773E7FFD3FFEF7E7841FF9FF8FF - FC67FFF3FC3FC719FFF3FFFBFFFC3FBFF7FEFFE307FE7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE7A0F - F88F13E7847FF9FFC9FFFF0FFFFFE7FFE0B9FF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000001000000); -! Data Row = 56 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDD1BE77BEF8E10BFA7DFFFA7FFFE9FFF82FF420FFCFFC7F3E7FFD3FFEF7E7841FB9FF8FF - FC67FFF3FC3FC719FFF3FFFFFFFC3FBFF7FEFFE306FE7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE79CF - F8CF0BE7847FE9FFCFFFFF1FFFFFE3FFE09D7F); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000800000); -! Data Row = 57 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7FFFE9FFFFFFF420FECFFC7F3E7FFD3FFEF7E7841FF9FF8FF - FC67FFF3FC3FC719EFF3FFFFFFFC3FBFF7FEFFE307FA7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE7BCF - F8CF1BE7847FF9FFCFFFFF1FFFFFE7FFE0BDFF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000400000); -! Data Row = 58 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7FFFE9C17FFFF420FFCFFC7F3E7FFD3FFEF7E7841FF9FF8FF - FC67FFF3FC3FC519FFF3FFFFDFFC2FBFF7FEFFE307FE7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE7BCF - F8CF1BE7847FF9FFCFFFFF1FFFFFE7FFE0BDFF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000200000); -! Data Row = 59 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7FFFE9FFFFFFF420FFCFFC7F3E7FFD3FFEF7E7841FF9FF83F - FC67FFF3FC3FC719FDF3FFFFDFFC2FBFF7FEFFE306FE7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE7BCF - F8CF1BE7847FF9FFCFFFFF1FFFFFE7FFE0BDFF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000100000); -! Data Row = 60 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7FFFE9FFFFFFF420FFCFFC7F3E7FFD3FFEF7E7841FF9FF8FF - FC67FFF3FC3FC719FFF3FFFFFFFC3FBFF7FEFFE307FE7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE7BCF - F8CF1BE7847FF9FFCFFFFF1FFFFFE7FFE0BDFF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000080000); -! Data Row = 61 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFCB1BE737EF8E10BFE7DFFFA7FFFE9FFFFFFF420FFCFFC033E7FFD3FFEF7E7841FF1FF8FF - FC67FDF3BC3FC719FBF3FFFFFFFC3FBFF7FEFFC3077E7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE7BCF - F8CF1BE7847FF9FFCFFFFF1FFFFFE7FFE0BDFF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000040000); -! Data Row = 62 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDD1BE77BEF8E10BDE7DFFFA7FFFE9FFFFFFF420FFCFFC7F3E7FFD3FFEF7E7841FF9FF8FF - FC67FFF3FC3FC719FFF3FFFFFFFC3FBFF7FEFFE307FE7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE7BCF - F8CF1BE7847FF9FFCFFFFF17FFFFE7FFE0BDBF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000020000); -! Data Row = 63 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7FFFE9FFFFFFF420FFCFFC7F3E7FFD3FFEF7E7841FF9FF8FF - FC67FFF3FC3FC719FFF3FFFFFFFC3FBFF7FEFFE3077E7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE7BCF - F8CB1BE2847FF9FFCFFFFF1FFFFFE7FFE0BDBF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000010000); -! Data Row = 64 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDF1BE77FEF8E103DE7DFFFA7FFFE9FFFFFFF420FFCFFC7F3E7FFD3FFEF7E7801FF1FF8FF - FC67FFF3FC3FC719FFF3FFFFFFFC3FBFF7FEFFE303FE7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE7BCF - F8CE1BE5847FB9FFCFFFFF1FFFFFE7FFE03DFF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000008000); -! Data Row = 65 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7FFFE9FFFFFFF420FFCFFC7F3E7DFD2ABEF7E7841FF9FF8FF - FC67FFF3FC1FC719FFF3FFFFDFFC2FBFF7FEFFE307FE7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE7BCF - F8C41BE7847FF9FFCFFFFF1FFFFFE7FFE0BDFF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000004000); -! Data Row = 66 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7FFFE9FFFFFFF420FFCFFC7F3E7BFD157EF7E7841FB9FF8FF - FC67FFF3FC3FC719FFB3FFFFFFFC3FBFF7FEFFE305FE7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE7BCF - F8CB1BE7847FB9FFCFFFFF1FFFFFE7FFE0BDFF); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000002000); -! Data Row = 67 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (0300600C0180200400C000000040000180200600C010000000080100200400C00003000000010020 - 060080180100600C0000300000C0100300000C0100000600C0180300600C0180100000C010030060 - 08018030020000180200600801001004004000); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000001000); -! Data Row = 68 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (0300000C00002000008008000040000100200400C0100000000C0000300000800003004000018010 - 06004010000060080000300000C0080300600C0000000600C0180300600801802000008000020000 - 08000020020000180000600C0180000400C000); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000000800); -! Data Row = 69 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (020060080180300600C018000060040180300600C000030000080100300600C00803006000010030 - 0600C0180100600C000020020080180200200801800006004018010060040100300000C018030060 - 0C018030060000100300400C0100100400C000); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000000400); -! Data Row = 70 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (0300000C000000020000000000000401801006000018000000040080100200800800000000008010 - 00004000000000000000300200C0080300200C000000060000180000600001802000000008000000 - 00000000000000180100600400800002000000); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000000200); -! Data Row = 71 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (01000008000020000080000000000401000004000010000000080080000200000802004000000010 - 04000010030000000000200200400000002004010000040080080200400801800000008000020000 - 00008000000000100100400400000004008000); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000000100); -! Data Row = 72 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (01006000018010040040100000200C0080200200C0100200000C0100100600400003004000008030 - 020080080100200C0000300400401801006000010000060040080100400400803000004010030060 - 04018010060000000300000C00803002004000); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000000080); -! Data Row = 73 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (0300600C0180300600C0180000600C0180300600C0180300000C0180300600C01803006000018030 - 0600C0180300600C0000300600C0180300600C0180000600C0180300600C0180300000C018030060 - 0C018030060000180300600C0180300600C000); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000000040); -! Data Row = 74 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (0300000C010020020080080000400401001004000018010000080080200200801802006000010010 - 04004010030040040000300200C0100300200C018000060080180200600801800000008008020000 - 08008020000000180100600401000004008000); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000000020); -! Data Row = 75 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (0300000C000020020080080000400401001004000018010000080080200200801802006000010010 - 04004010030040000000300200C0100300200C018000060080180200600801800000008008020000 - 08008020000000180100600401000004008000); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000000010); -! Data Row = 76 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (0300600C0180300600C0180020600C0180300600C0180300040C0180300600C01803006000818030 - 0600C0180300600C0010300600C0180300600C0180020600C0180300600C0180300040C018030060 - 0C018030060008180300600C0180300600C001); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000000008); -! Data Row = 77 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (0200000000000002008008000040000000000600C010030000080080300000000001000000000030 - 000000000300400800003004008010020060000000000600C0180100200400801000008000000000 - 00008020060000180000000C00002000004000); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000000004); -! Data Row = 78 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (030000000000000000C0000000400000800006008018020000080000300000400001000000000020 - 000000080200600800003004008010020040040000000600C0180100200400801000008000010000 - 00000030040000180000200800802000004000); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000000002); -! Data Row = 79 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (02004008010020040080100000600801802004008010020000080100300400C01002004000010030 - 0400C0100200400800002004008010020040080100000600C0180300600C01803000008018020040 - 08010020040000100200600801002004008000); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000000001); -! Data Row = 80 -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Data -SDR 792 TDI (0300000C0100300000C0100000600001802000008018020004080180200600001000004000018000 - 06000010030040000000200600800002006000010000000080180000600001000000008018020000 - 08018020000000100300400001800006000000); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; - - -! Program Efuse row - -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -! Prog Init/shift row all 0s -SDR 80 TDI (00000000000000000000); -! Shift in PROGRAM MODE(0x0F) instruction -SIR 6 TDI (0F); -! Shift in Password(0x09) -SDR 5 TDI (09); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -! Shift in Efuse Data Row = 1 -SDR 792 TDI (00080100200400801002004000010020040080100200400800002004008010020040080100000400 - 80100200400801002000008010020040080100200400001002004008010020040080000200400801 - 00200400801000004008010020040080100200); -! Shift in PROGRAM(0x06) instruction -SIR 6 TDI (06); -RUNTEST IDLE 3 TCK 5.00E-002 SEC; - - -! Full Address Verify Fuse Map - -! Shift in PROGRAM MODE(0x0F) instruction -SIR 6 TDI (0F); -RUNTEST IDLE 3 TCK 2.00E-002 SEC; -! Shift in Password(0x08) -SDR 5 TDI (08); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (80000000000000000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 1 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FFBD07FFA7FFFFF87FFFF3FF9FBE21E7D8F31FF3DE7FFE31F3FEFBDFFB9F7FE07DFF81F7FE7FE0C7 - FF7DEFFCFC3FFFFFFFCFFF98E3F43DCFBFE63FFF1FF9FF821E7EF7FFCBFFE7CFE3FF3FF042F5EFFF - F97AF7E5FFFBE7FD0841F7C007C0EBFF001FFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (40000000000000000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 2 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FEBD07FFE7DFFFF8FFEFF3FF9FFE21E7D8F31FF3DC7FFE31F3FC7FDFF99F7FEC7DFFB1F7FE7FA0C7 - FF7FEFFDFC3FFFFFFFCFEF98E3F83FCFFFE63FFF1FF9DF821E7EF7FFCBFFE7CFE1FF3BF042FADE0F - F97D6FE5FFFBE7F90871F7FEE7D87BFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (20000000000000000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 3 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FFBC07FFE7FFFFF8FFFFF3FF9F7E21E7D8F31FF3DE7FFC31F3FEFFDFFB9F7FEC7DFFB1F7FE7FC0C7 - FF7FEFFDFC3FFFFFFFCFF718E3FC3FCFFFE63FFF1FF9FF821E7EF7FFCBFFE7CEE3FF3FF042FFFFFF - F97FFFE5FFFBE7F90871F7FEE7D8FBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (10000000000000000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 4 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (EFBD07FFE7FFFFF8FFFFF3FF9FFE21E7D8F31FF3DE7FFE31F1FEFFDFFB9F7FEC7DFFA1F7FE77E0C7 - FF7FEFFDFC3FFFFFFFCFFC98E3FC3FCFFFE63FFF1FF9DF821E7EF7FFCBFFE7CFE3FF3FF042FFFFFF - F97FFFE5FFFBE7FD0871F7DEE7D8BBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (08000000000000000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 5 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (EFBD07FFE7FFFFF8FFFFF3FF9DFE21E7D8F31FF3DE7EFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7FE0C7 - FF7FEFFDFC3FFFFFFFCDFF98C3FC3F8FFFE43FFB1FF9DF821E7EF7FFCBFFE7CFE3FF3FF042FFFFFF - F17FFFE5FFE3E5FD0871F7FEE7D8FBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (04000000000000000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 6 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FFBD07FFE7FFFFF8FFF7F3FF9FFE21E7D8F31FF3DE7FFE31F37EFFDFFB9F7FE87DFFB1F7FE7FA047 - FF7FEFFDFC3FFFFFFFCFFF98E3FC3FCFFFE23FFF1FF9FF821A7EF7FFCBFFE7CFE3FF3EF042FFFFFF - F97FFFE5FFFBE7FD0871F7DEE7D8BBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (02000000000000000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 7 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (BFBD07FFE7FFFFF8FFFFF3FF9FFA21E7D8F31FD3DA7FFE31F3FEFFDFFB9F7FEC7DFF91F7FE7FA0C7 - FF7FEFFDFC3FFFFFFFCFFF98E3FC3FCFFFE63FFF1FF9FB020E7CF7BFC3FFE7CFE3FF1FF042FFFFFF - F97FFFE5EFFBE7ED0871F7FEE7C8FBFF73CFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (01000000000000000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 8 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FFBD07FFE7FFFDF8FFFFF3FF9FDE21E7D8F31FF3DE7FFE31F3DEFFDFFB9F7FE47DFFB1F7FE7FE0C7 - FF3FEFFDFC3FFFFFFFCDFF98E3FC3FCFFFE63FFF0FF9FF821E7EF7FFCBFFE7CFE3FF3FF042FFFFFF - F97FFFE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00800000000000000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 9 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FBBC07FF87FFFFF8FFFFF3FF9FFE2167D8B11FF39E7FF431F3FEFF5FFB9F7FEC7DFFB1F7FE6FE0C7 - FF7FEFFDFC3FFFFFFFCBFF98E3FC3FCFFFE63FFF1FF9FF821E7EF7FFCBFFE7CFE3FF3FF042FFFF9F - B97E7EE5FFFBE7FD0851F7C487D093FF735FFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00400000000000000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 10 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FFBD07FFE7FFFFF8FFFFF3FF9FDE21A7D8D31FF2DE7FFE31F1FEFEDFFB9F7FEC7DFFB1F7FE7FE0C7 - FF7FEFFDF43FFBFFFFCFFF80E3FC3FCFFFE63FFF1FF8FF821E7EF7CCCBF7E7CFE3FF37F042F07E7F - 7979FDE5FFFBE7F50871F7FEE7D8EBFF11DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00200000000000000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 11 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FFBD07FFE7FFFFF8FFFFF3FF97FE21E7D8F31FF3DE7FFE31F3FEFE9FFB9F7FEC7DFFB1F7FE6FE0C7 - FF7FEFFDFC3FFFFFFFCBFF88E3FC3FCFFFE63FFF1FF97F821E7EF7FFCBFFE7CFE3FF2FF042FFFFFF - F17FFFE5FFE3E5FD0871F7FEE7D8FBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00100000000000000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 12 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FDBD07FFE7FFFFE8FFFFF3FF9FFE21E7D8F31F73CE7FFE31F3DEFFDFFB9F7FEC7DFFB1F7FE7FE0C7 - FF7FEFFDF43FFBFFFFCFFF98E3FC3FCFFFE63FFF1FF9FF020E7CF7BFC3FFE7CDE3FF3FF042FFFFFF - F87FDFE1FFFBE7FD0871F7FEE7D8FBFF73CFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00080000000000000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 13 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FFBD07FFE7FFFFF8FFFFF3FF9FFE21E7D8F31FF3DE7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7FE047 - FF7FEFFDFC3FFFFFFFCFFF98E3FC3FCFFFE63FFF1FF9FF821E7EF7FFCBFFE7CEE3FF2FF042FFFFFF - F97FFFE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00040000000000000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 14 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FF0507FFE7FFFFF8FFFFF3FF9FBC21E7D8F31FF3DE7FFE31F3EEFFDFFB1F7FEC7DFFB1F7FE7EE087 - FF7FEFFDFC3FFFFFFFCFFF98E3FC3FCFFFE63FFF1FF9BF821E7EF7FFCBFFE7CFE3FF3FF042FFFFFF - F97FA0E5FFFBE7FD0871F7FEE7D8FBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00020000000000000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 15 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FFBD07FFE7FFFFF8FFFFC3FF9FBE21E7D0F31FF3DE7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7BE0C7 - FF7FEFFDFC3FFFFFFFCFDF98E3FC3FCFFE263FFF1FF9FF821E7EF7FFCBFFE7CFE3FF1FF042F5DFFF - F97AEFE5FFFBE7ED0871F7DEE7D8BBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00010000000000000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 16 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FBB107FFE7FFFFF8FFFFF3FF9FFE21E7C8F31FF39E7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7FE0C7 - FF7FEFFDF43FFBFFFFCFFE18E3FC3FCFFFE63FFF1FF9FF821E7EF7FFCBFFE7CFE3FF3FF042FAEE1B - F97D77E5FFFBE7FD0871F7FEE7D8FBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00008000000000000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 17 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FF3D07FFE7FFFFF8FFFFF3FF9FDE21E7D8F31FE3DE7FFE31F3FAFDDFFB9F7FEC7DFFB1F7FE7F80C7 - FF7FEFFDFC3FFFFFFFCFFF88E3FC3FCFFFE63FFF1FF9FD821E7EF7FFCBFFC7CFE3FF2FF042FFFF9F - 797E7DE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00004000000000000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 18 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FFBC07FFE7FFFFF8FFFFF3FF9FFE21E7D8F31FF3DC7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7FE0C7 - FF7FEFFDFC3FFFFFFFCFDF98A3FC3ECFFFE63FFF1FF9FF821C7EF7C3CBFFE7CFE3FF3FF042F0FC7F - B979FEE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00002000000000000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 19 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FBBD07FFE7FFFFF0FFFFB3FF9FEE21E7D8F31FF3DE7FFE21F37EFF5FFB9F7FEC7DFFB1F7FE7FE0C7 - FF7FEFFDF43FFBFFFFCFFF98E3FC3F4FFFE63FFF1FF8FF821E7EF7FFCBFFE7CFC3FF1FF042FFFFFF - F97FFFE5FF9BE7F90871F7FEE7D8FBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00001000000000000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 20 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FFBD07FFE7FFFFF8FFFFF3FF9FFE21E7D8F31FF3DE7FFE11F3FEFF9FFB9F7FEC7DFFB1F7FE7FA0C7 - FF7FEFFDFC3FFFFFFFC7FF98E3FC3FCFFFE63FFF1FF9FF821E7EF7FFCBFFE7CFE3FF3FF042FFFFFF - F17FFFE5FFE3E7FD0071F7FEE7D8FBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000800000000000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 21 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (7FB907FFC3FFFFF8FFFFF3FF8FFE21A7D8D31FF35E7FFE31F3FCFFDFFB9F7FEC7DFFB1F7FE7FE0C7 - FF7FEFFDFC3FFFFFFFC7FE88C3FC3F0FFFA63FFA1FF9FF821E7EF7FFCBFFE7CFE3FF1FF042FFFFFF - F97FFFA5FFBBE3FD0871F7FEE7D8EBFF22DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000400000000000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 22 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FFAD07FFE7FFFFF0FFFFA3FF9FFE21C7D8E11FF39E7FF831F3FEFBDFFB9F7FEC7DFFB1F7FE7FE0C7 - FF7FEFFDFC3FFFFFFFCFFF18E3FC3FCFFFC63FFF1FF9FF821E7EF7FFCBFFE7CFE3FF3FF042FFFFFF - E97FFFC5FFF3E7FD0851F7C887D093FF735FFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000200000000000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 23 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FFBD03FFE7FFFFF8FFFFF3FF9FFE21E7D8F31FF3DE7FFE11F37EFFDFFB1F7FEC7DFFB1F7FE77E0C7 - FF7FEFFDFC3FFFFFFFC7FF98E3F43FCFFFE63FFF1FF9FB821E7EF7FFCBFFE7CFE3FF1FF042FFFFFF - F97FFFE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000100000000000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 24 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (7FBD07FFE7FFFFF8FFFFF3FF8FFE21E7D8F31FF3DE7FFE21F3FEFFDFFA9F7FEC7DFFB1F7FE7FE0C7 - FF7FEFFDF43FFBFFFFCFFF98E3FC3FCFFFE63FFF1FF9FF821E7EF7FFCBFFE7CEE3FF3FF042FFFFFF - F17FFFE5FFE3E7FD0871F7FEE7D8FBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000080000000000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 25 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FBBD07FFE7FFFFF8FFFFF3FF9FFE21E7D8F31FF3DE7FF231F3FEFFDFFB9F7FEC7DFFB1F7FE7DE0C7 - FF7FEFFDFC3FFFFFFFCFFF18E3FC3FCFFFC63FFF1FF9F7821E7EF7FFCBFFE7CFE3FF2FF042FFFFFF - F97FFF25FFFBE7FD0871F7FEE7D8EBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000040000000000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 26 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FFBC07FFE7FFFFF8FFFFF3FF8FFE21E7D8F31FF3DE7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7FC0C7 - FF7FEFFDFC3FFFFFFFCBFE98E3FC3FCFFFE63FFF1FF9FF821E7EF7FFCBFFE7CEE3FF3FF042FFFFFF - F97FFFC5FFFBE3FD0871F7FEE7D8FBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000020000000000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 27 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FFBC07FFE7FFFFF8FFFFF3FF9FFE21E7D8F31FD3DE7FFE31F2FEFF5FFB9F7FEC7DFFB1F7FE7FC0C7 - FF7FEFFDFC3FFFFFFFCFFF18E3FC3FCFFFC63FFF1FF97F821E7EF7FFCBF7E7CFE3FF3FF042FFFFFF - D97FFFC5FFFBE7FD0871F7FEE7D8FBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000010000000000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 28 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (EFBD07FFE7FFFFF8FFFFF3FF9BFE21E7D8F31FF3DE7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE77E0C7 - FF7FEFFDFC3FFFFFFFCFEE98C3FC3F0FFF663FF91FF9FF821E7EF7CCCBFFE7CFE3FF3FB042FFFFFF - F17FFF65FFA3E7FD0871F7FEE7D8FBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000008000000000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 29 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FDBD07FFE7FFFFF8FFFFF3FF9FFE01E7D8F31FF3DE7FFE31F3FEFFDFFA9F7FEC7DFFB1F7FE7FE0C7 - FF7FEFFDFC3FF7FFFFCFFF98E3FC3FCFFFE63FFF1FF9FF821E7EF7FFCBFFE7CFE3FF3FF002FFFFFF - F97FFFE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000004000000000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 30 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FFBD07FFE7EFFFF8FFFFF3FF9FEE21E7D8F31FF3DE7FFE31F3BEFFDFFB9F7FEC7DFFB1F7FE7EE0C7 - FF7FEFFDFC3FFFFFFFCEFF98E3FC3FCFFFE63F7F1FF9FD82167EF7FFCBFFE7CFA3FF3FD042FFFFFF - F97FFFE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000002000000000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 31 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (BFBD07FFE7FFFBF8FFFFF3FF9FFE21E7D8F31FF3DE7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7F60C7 - FF7FEFFDF43FFBFFFFCFFF98E3FC3FCFFFE63FFF1FF9FF821E7EF7FFCBFFE7CFE3FF3FF042FFFFFF - F97FFFE5FFFBE7ED0851F7FE67D0FBFF739FFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000001000000000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 32 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FFBD07FFE7DFFFF8FFEFF3FF9FFE21E7D8F31FF3DE7FFE31F37EFFDFFB1F7FEC7DFFB1F7FE7FE0C7 - FF7FEFFDFC3FFFFFFFCF7F18E3FC3FCFFFE63FFF1FF9FF821E7EF7FFCBFFE7CFE3FF3FF042FFFFFF - F97FFFE5FFFBE7FD0871F7FEC7D8FBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000800000000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 33 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FFBD07FFC7FFFFF8FFFFF3FF9FFE21E7D8F31FF3DE7FFE31F3FEF7DFFB9F7FEC7DFFB1F7FE7FE0C7 - FF7FEFFDFC3FFFFFFFCFEF98E3FC3ECFDFE63F7F1FF9FF821E7EF7FFCBFFE7CBE3FF3FF042FFFFFF - F97FFFE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000400000000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 34 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FF3D07FFE7FFFDF8FFFFF3FF9FEE2107D8031FF3DE7FFE31F3FCFFDFFB9F7FEC7DFFB1F7FE7EE0C7 - FF7FEFFDF43FFBFFFFCFFF98E3FC3FCFFFE63FFF1FF9FB821E7EF7FFCBFFE7CFE3FF3FF042FFFFFF - F97FFFE5FFFBE7F80871F7FEE7D8FBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000200000000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 35 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FFBC07FFE7FFFFF8FFFFF3FF9FFE21E7D8F31FF3DE7FFE31F3FEFFDFFB1F7FEC7DFFB1F7FE77E0C7 - FF7FEFFDFC3FFFFFFFCFF798E3FC3FCFFFE63FFF1FF9FB821E7EF7FFCBFFE7CFE3FF3DF042F3F6DD - F97FFFE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000100000000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 36 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (DFBD07FFE7FFFFF8FFFFF3FF9EFA21E7D8F31FF3DE7FFE31F2FEFFDFFB9F7FEC7DFFB1F7FE7FE0C7 - FF7FEFFDF43FFBFFFFCFFF90E3FC3FCFFFE63FFF1FF9FF821E7EF7FFCBFFE7CEE3FF3FF042FCFB3E - F9787BE5FFFBE7F90871F7FCE7D8F3FF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000080000000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 37 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FDBD07FFE7DFFFF87FFFF3FF9FBE21E7D8F31F73DE7DFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7DC0C7 - FF7FEFFDFC3FFFFFFFCFFF98E3FC3FCFFFE63FFF1FF9BF821E7EF7F30BFFE7CFE3FF3F7042FFFFFF - F87FDFE1FFFBE7F50871F7F2E7D8FBFF33DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000040000000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 38 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FFBD07FFE7FFFFF8FFFFF3FF9FFE21E7D8F31FF3DE7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7FE0C7 - FF7FEFFDFC3FFFFFFFCDFF98E3FC3FCFFFE43FFF1FF9FF821E7EF7FFCBFFE7CFE3FF3FF042FFFFFF - F97FFFE5FF7BE7FD0871F7FEE7D8FBFF43DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000020000000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 39 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FFBD07FFE7FFFFF8FFFFF3FF9FFE21E7D8F31FF3DE7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7FE0C7 - FF7FEFFDFC3FFFFFFFCFFF98E3FC3FCFFFE63FFF1FF9FF821E7EF7FFCBFFE7CFE3FF3FF042FFFFFF - F97FFFE5FFBBE7ED0871F7CCE7D813FF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000010000000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 40 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FEBC07FFE7FFFFF8FFFFF3FF9FFE21E7D8F31FF3DE7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7F40C7 - FF3FEFFCFC3FFFFFFFCFFF98E3FC3FCFFFE63FFF1FF9FF821E7EF7FFCBFFE7CFE3FF3EF042FFFFFF - F97FFFE5FFEBE7FD0871F7FEE7D8EBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000008000000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 41 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (7F8107FFE7FFFFF8FFFFF3FF9FFA21E7D8F31FD3DA7FFE31F3FEBFDFFB9F7FE87DFFA1F7FE7FE083 - FF7FEFFDFC3FFFFFFFCFBF98E3FC3FCFFFE63FFF1FF9FF82127EF7FFCBEFE7CFE3FF3FF042FFFFFF - F97FFFE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000004000000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 42 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FFBD07FFE7FFFFF8FFFFF3FF9FDC2107D8031F63CC7DFE31F3FAFFDFFB9F7FE47DFF91F7FE7F6047 - FF7DEFFDFC3FFFFFFFCFFF98E3FC3FCFDFE23FFF1FF9FD000C7CF78003FFE7CF63FF3FB042FFFFFF - F87FDFE1FFFBE7F50871F7FEE7D8FBFF73CFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000002000000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 43 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FF8107FFE7EFFFE0FFFF83FF9FF82107D8031FF3DE7FF031F3FEFFDFFB9F7FEC7DFFB1F7FE5FE0C7 - FF7FEFFDF83FFFFFFFCFFF0083FC3E0FFFE03FF80FF9FF82107EF7C00BFF67CFE1FF3FF042F3FADE - F97FFFE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000001000000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 44 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FF3D07FF67FFFFF8FFFFF3FF9FEE21E7D8F31FB3D67FFE31F3F6FE1FFB9F7FEC7DFFB1F7FE7FE047 - FF7FEFFDFC3FFFFFFFCFF598E3FC3FCFFFE63FFF1FF9FE821E7EF7FFCBDFE7C7E3FF37F042FCF73D - F9783FE5FFFBE7F50871F7EEE7D8DBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000800000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 45 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FFBD07FFE7FFFFF8FFF7F3FF9FFE21E7D8F31FF3DA7FFE31F3FEDFDFFB9F7FEC7DFFB1F7FE6FE0C7 - FF7FEFFDFC3FFFFFFFCFFF98E3FC3FCFFFE63FFF1FF9FF821E7EF7FFCBFFE7CFE3FF3FF042FFFFFF - F97FFFE5FFFBE7F90861F7FEE7D0FBFF739FFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000400000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 46 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (BFBD07FFE7FFFFF8FFFFF3FF97FE21E7D8F31FF3DE7EFE31F3BEEFDFFB9F7FEC7DFFB1F7FE7FE0C7 - FF7FEFFDF43FFBFFFFCFFF98E3FC3FCFFFE63FFF1FF9BF821E7EF7FFCBFF67CFE3FF3FF042FFFFFF - F97FFFE5FFFBE7FD0871F7FEA7D8FBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000200000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 47 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (DFB907FFE7FFFFF8FFFFF3FF9FFE21E7C8F21FF3DE7FFE31F3FEDFDFFB9F7FEC7DFFB1F7FE7FE0C7 - FF7FEFFDFC3FFFFFFFCFFF98E3FC3FCFFFC63FFF1FF9FF821E7EF7EA8BFBE7CFE3FF37F042FFFFFF - C97FFFE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000100000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 48 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FFB507FFE7FFFFF8FFFFF3FF9BFE21E7D0F31FF3DE7FFE31F3BEEFDFFB9F7FEC7DFFB1F7FE7FE0C7 - FF7FEFFDFC3FFFFFFFCDFE18E3FC3FCFFEE63FFF1FF9DF821E7EF7D54BFDE7CFE3FF3FF042FFFFFF - F17FFFE5FFFBE6FD0871F7DEE7D8BBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000080000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 49 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FFBD07FFE7FFFFF8FFFFF3FF97FE21E7D8F11FF39E7FFE31F3F6FDDFFB9F7FEC7DFFB1F7FE7FC0C7 - FF7FEFFDFC3FFFFFFFCBFF18E3FC3FCFFFC63FFF1FF9FB821E7EF7FFCBFFC7CFE3FF3FF042F04008 - 017820E5FF83E7DD0871F7FEE7D8FBFF43DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000040000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 50 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FFBD07FFE7FFFFF8FFFFF3FF9FFE21E7D8F31FF1DE7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE6FE0C7 - FF7FEFFDFC3FFFFFFFCFFE98E3FC3FCFFEE63FFF1FF9FF821C7EF7FC0BFFE7CFE3FF3FD042FFFFFF - F97FFFE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000020000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 51 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FFBD07FFE7FFFFF8FFFFF3FF9FFE21E7D8F31FF3DE7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE5FE0C7 - FF7FEFFDFC3FFFFFFFCFFF98E3FC3F8FFFE63FFF1FF9FF821E7EF7FFCBFFE7CFE3FF3FF042FFFFFF - F97FFFE5FFFBE7DD0851F7FE87D0FBFF709FFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000010000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 52 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (BFB907FFE7FFFFF8FFFFF3FF9FFE21E7D8F31FF3DE7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7FE0C7 - FF7FEFFDF43FFBFFFFCBFF98E3FC3FCFFFE63FFF1FF9FF821E7EF7FFCBFFE7CFE3FF3FF042FFFFFF - F97FFFE5FFFBE7FD0871F7FEE7D8FBFF735FFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000008000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 53 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FDBD07FFE7FFFFF8FFFFF3FF9FFE21E7D8F31FF3DE7FFE31F3FEFFDFFB9F7FE87DFFA1F7FE7EE0C7 - FF7FEFFDFC3FFFFFFFCFFF98E3FC3FCFFFE63FFF1FF9FF821E7EF7FFCBFFA7CFE3FF3FF042FFFFFF - F97FFFE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000004000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 54 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FFBC07FFE7FFFFF8FFFFF3FF9FFE21E7D8F31FF3DE7FFE31F3FAFFDFFB9F7FEC7DFFB1F7FE7FC0C7 - FF7FEFFDFC3FFFFFFFCFFF98E3FC3FCFFFE63FFF1FF9FE821E7EF7C00BFFE7CFE3FF3FF042FFFFFF - F97FFFE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000002000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 55 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FF9D07FFE7FFFFF0FFFF93FF9FFE21E7C8F11FF05E7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7FE0C7 - FF7FEFFDFC3FFFDFFFCFFF98E3FC3FCFFFE63FFF1FF9FF821E7EF7FFCBFFE7CEE3FF3BF042FFFFFF - F97FFFE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000001000000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 56 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FEB907FFC7FFFFF8FFFFF3FF97FE21E7D0F31FF39E7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7F60C7 - FF7FEFFDFC3FFFFFFFCFFF98E3FC3FCFFFE63FFF1FF9DF821E7EF7FFCBFFE7CFE3FF3FF042FF41FF - F97FFFE5FFFBE5FD0871F7DEE7D8BBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000800000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 57 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FFBD07FFE7FFFFF8FFFFF3FF9FFE21E7D8F31FF3DE7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE5FE0C7 - FF7FEFFDFC3FFFFFFFCFF798E3FC3FCFFFE63FFF1FF9FF821E7EF7FFCBFFE7CFE3FF37F042FFFFFF - F97FFFE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000400000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 58 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FFBD07FFE7FFFFF8FFFFF3FF9FFE21E7D8F31FF3DE7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7FE0C7 - FF7FEFFDF43FFBFFFFCFFF98A3FC3FCFFFE63FFF1FF9FF821E7EF7FFCBFFE7CFE3FF3FF042FFFFE8 - 397FFFE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000200000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 59 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FFBD07FFE7FFFFF8FFFFF3FF9FFE21E7D8F31FF3DE7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7F60C7 - FF7FEFFDF43FFBFFFFCFBF98E3FC3FCFFFE63FFC1FF9FF821E7EF7FFCBFFE7CFE3FF3FF042FFFFFF - F97FFFE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000100000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 60 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FFBD07FFE7FFFFF8FFFFF3FF9FFE21E7D8F31FF3DE7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7FE0C7 - FF7FEFFDFC3FFFFFFFCFFF98E3FC3FCFFFE63FFF1FF9FF821E7EF7FFCBFFE7CFE3FF3FF042FFFFFF - F97FFFE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000080000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 61 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FFBD07FFE7FFFFF8FFFFF3FF9FFE21E7D8F31FF3DE7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7EE0C3 - FF7FEFFDFC3FFFFFFFCFDF98E3FC3DCFBFE63FFF1FF8FF821E7EF7FFCBFFE7CC03FF3FF042FFFFFF - F97FFFE5FFFBE7FD0871F7ECE7D8D3FF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000040000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 62 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FDBD07FFE7FFFFE8FFFFF3FF9FFE21E7D8F31FF3DE7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7FE0C7 - FF7FEFFDFC3FFFFFFFCFFF98E3FC3FCFFFE63FFF1FF9FF821E7EF7FFCBFFE7CFE3FF3FF042FFFFFF - F97FFFE5FFFBE7BD0871F7DEE7D8BBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000020000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 63 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FDBD07FFE7FFFFF8FFFFF3FF9FFE2147D8D31FF3DE7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7EE0C7 - FF7FEFFDFC3FFFFFFFCFFF98E3FC3FCFFFE63FFF1FF9FF821E7EF7FFCBFFE7CFE3FF3FF042FFFFFF - F97FFFE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000010000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 64 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FFBC07FFE7FFFFF8FFFFF3FF9DFE21A7D8731FF3DE7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7FC0C7 - FF7FEFFDFC3FFFFFFFCFFF98E3FC3FCFFFE63FFF1FF8FF801E7EF7FFCBFFE7CFE3FF3FF042FFFFFF - F97FFFE5FFFBE7BC0871F7FEE7D8FBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000008000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 65 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FFBD07FFE7FFFFF8FFFFF3FF9FFE21E7D8231FF3DE7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7FE0C7 - FF7FEFFDF43FFBFFFFCFFF98E3F83FCFFFE63FFF1FF9FF821E7EF7D54BFBE7CFE3FF3FF042FFFFFF - F97FFFE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000004000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 66 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (FFBD07FFE7FFFFF8FFFFF3FF9DFE21E7D8D31FF3DE7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7FA0C7 - FF7FEFFDFC3FFFFFFFCDFF98E3FC3FCFFFE63FFF1FF9DF821E7EF7EA8BFDE7CFE3FF3FF042FFFFFF - F97FFFE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) - MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF - FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000002000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 67 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (00020002080008010420041080004008410801042084008210000801082104208410821042000008 - 21000084008210000840002104208010801042004008000000840002100200400801000000008210 - 42004108000020000002100200410821042084) - MASK (00021042084108210420841080004208410821042084108210000841082104208410821042000108 - 21042084108210420840002104208410821042084108000420841082104208410821000084108210 - 42084108210420001082104208410821042084); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000001000); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 68 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (00021002000108210420001080004000400001000004000010000041080104208410821042000000 - 21042084100210000840000104200000820042080108000020840000100008400021000000008210 - 02004008000020001000100000400021000084) - MASK (00021042084108210420841080004208410821042084108210000841082104208410821042000108 - 21042084108210420840002104208410821042084108000420841082104208410821000084108210 - 42084108210420001082104208410821042084); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000000800); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 69 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (00021002080008210020840080004208410821042084108210000840082004208010820042000108 - 01040004108010400040002104208010821042084008000420841002104208400801000084000210 - 42084108200420001082104208410801042004) - MASK (00021042084108210420841080004208410821042084108210000841082104208410821042000108 - 21042084108210420840002104208410821042084108000420841082104208410821000084108210 - 42084108210420001082104208410821042084); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000000400); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 70 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (00000040000100200420801080000000000000000000100000000041080004200010800042000000 - 21040084100210400840000000000000020000080100000000001000104008010020000000108000 - 42080108200000000000004000000021000084) - MASK (80021042084108210420841090004208410821042084108212000841082104208410821042400108 - 21042084108210420848002104208410821042084109000420841082104208410821200084108210 - 42084108210424001082104208410821042084); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000000200); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 71 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (00001002000000200020800080000000010000000004000010000001080100200410001002000008 - 20040000000200400040000000008400800002080000000020041000004000010001000000008000 - 02000008200000000000100000400001000080) - MASK (00021042084108210420841080004208410821042084108210000841082104208410821042000108 - 21042084108210420840002104208410821042084108000420841082104208410821000084108210 - 42084108210420001082104208410821042084); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000000100); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 72 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (00020040084100210000840000004208010820042084008200000841002000208010020042000008 - 00042080108200020840002104008010001040084100000020840002004208000821000004008210 - 40004100210400000082000208010800042080) - MASK (00021042084108210420841080004208410821042084108210000841082104208410821042000108 - 21042084108210420840002104208410821042084108000420841082104208410821000084108210 - 42084108210420001082104208410821042084); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000000080); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 73 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (00021042084108210420841080004208410821042084108210000841082104208410821042000108 - 21042084108210420840002104208410821042084108000420841082104208410821000084108210 - 42084108210420001082104208410821042084) - MASK (00021042084108210420841080004208410821042084108210000841082104208410821042000108 - 21042084108210420840002104208410821042084108000420841082104208410821000084108210 - 42084108210420001082104208410821042084); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000000040); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 74 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (00001002000008200420801080000000410001000004100010000001080104200410801042000108 - 21040084008210400840002000208400820002080008000420041080104000410001000080108000 - 02080008200020001000104000400821000084) - MASK (80021042084108210420841090004208410821042084108212000841082104208410821042400108 - 21042084108210420848002104208410821042084109000420841082104208410821200084108210 - 42084108210424001082104208410821042084); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000000020); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 75 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (00001002000008200420801080000000410001000004100010000001080104200410801042000108 - 21040084008210400840000000208400820002080008000420041080104000410001000080108000 - 02080008200020001000104000400021000084) - MASK (00021042084108210420841080004208410821042084108210000841082104208410821042000108 - 21042084108210420840002104208410821042084108000420841082104208410821000084108210 - 42084108210420001082104208410821042084); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000000010); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 76 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (80021042084108210420841090004208410821042084108212000841082104208410821042400108 - 21042084108210420848002104208410821042084109000420841082104208410821200084108210 - 42084108210424001082104208410821042084) - MASK (80021042084108210420841090004208410821042084108212000841082104208410821042400108 - 21042084108210420848002104208410821042084109000420841082104208410821200084108210 - 42084108210424001082104208410821042084); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000000008); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 77 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (00020000004000210000001080004200410000000000000010000801002004008010821042000000 - 00042004008010020840000100208400000000084000000000800000000008410001000084008210 - 42000000000020001000104000000000000004) - MASK (00021042084108210420841080004208410821042084108210000841082104208410821042000108 - 21042084108210420840002104208410821042084108000420841082104208410821000084108210 - 42084108210420001082104208410821042084); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000000004); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 78 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (00020000004100010400001080000208400000000080000010000801002004008010821042000000 - 20002004008010020840000104200410000000004000000000800002000008400001000004108010 - 42000100000020000002100000000000000084) - MASK (80021042084108210420841090004208410821042084108212000841082104208410821042400108 - 21042084108210420848002104208410821042084109000420841082104208410821200084108210 - 42084108210424001082104208410821042084); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000000002); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 79 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (00001002004008010420040080000200400801002004108010000841082104208410821042000008 - 01002004008010020040000100200400821002084008000020040082100208400801000004008010 - 02004108010420000080100200400801002004) - MASK (00021042084108210420841080004208410821042084108210000841082104208410821042000108 - 21042084108210420840002104208410821042084108000420841082104208410821000084108210 - 42084108210420001082104208410821042084); -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -SDR 80 TDI (00000000000000000001); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift Out Data Row = 80 -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (00000042000108000020840080000000410801000004108010000000080004200010801000000008 - 00042004000010420040000000208400800042000108000020000080004200410801200004108010 - 00004108000420000082100008400821000084) - MASK (00021042084108210420841080004208410821042084108210000841082104208410821042000108 - 21042084108210420840002104208410821042084108000420841082104208410821200084108210 - 42084108210420001082104208410821042084); - - -! Verify Efuse row - -! Shift in ROW(0x03) instruction -SIR 6 TDI (03); -! Prog Init/shift row all 0s -SDR 80 TDI (00000000000000000000); -! Shift in PROGRAM MODE(0x0F) instruction -SIR 6 TDI (0F); -! Shift in Password(0x09) -SDR 5 TDI (09); -! Shift in COLUMN(0x04) instruction -SIR 6 TDI (04); -SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000); -! Shift in VERIFY(0x07) instruction -SIR 6 TDI (07); -! Shift in Efuse Data Row = 1 -SDR 792 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - 00000000000000000000000000000000000000) - TDO (00400801002004008010020000080100200400801002004000010020040080100200400800002004 - 00801002004008010000040080100200400801002000008010020040080100200400001002004008 - 01002004008000020040080100200400801000) - MASK (00400801002004008010020020080100200400801002004004010020040080100200400800802004 - 00801002004008010010040080100200400801002002008010020040080100200400601002004008 - 01002004008008020040080100200400801001); - - -!Verify USERCODE - -! Shift in PROGRAM MODE(0x0F) instruction -SIR 6 TDI (0F); -! Shift in Password(0x0C) -SDR 5 TDI (0C); -! Shift in READ USERCODE(0x10) instruction -SIR 6 TDI (10); -RUNTEST IDLE 3 TCK 1.00E-003 SEC; -! Shift in READ USERCODE(0x10) instruction -SDR 32 TDI (00000000) - TDO (00000000) - MASK (FFFFFFFF); - - -! Exit the programming mode - -STATE IDLE; diff --git a/Logic/68030_TK.cmi b/Logic/68030_TK.cmi index 8e924d6..d4146cd 100644 --- a/Logic/68030_TK.cmi +++ b/Logic/68030_TK.cmi @@ -1,9 +1,9 @@ [WINDOWS] -MAIN_WINDOW_POSITION=0,0,967,1167 +MAIN_WINDOW_POSITION=-8,-8,1928,1168 LEFT_PANE_WIDTH=245 -CHILD_FRAME_STATE=Normal -CHILD_WINDOW_SIZE=473,867 -CHILD_WINDOW_POS=473,0 +CHILD_FRAME_STATE=Maximal +CHILD_WINDOW_SIZE=1936,919 +CHILD_WINDOW_POS=-8,-31 PV_FRAME_STATE=Normal PV_WINDOW_SIZE=473,867 PV_WINDOW_POS=0,0 @@ -11,8 +11,8 @@ PV_WINDOW_POS=0,0 Remember_Setting=1 Open_PV_Opt=2 Open_PV=1 -PV_IS_ACTIVE=1 -ACTIVE_SHEET=Pin Attributes +PV_IS_ACTIVE=0 +ACTIVE_SHEET=Global Constraints Show_Def_Opt=2 Show_Def_Val=1 Expand_All_Column=0 diff --git a/Logic/68030_TK.lci b/Logic/68030_TK.lci index a11a0f7..b80db18 100644 --- a/Logic/68030_TK.lci +++ b/Logic/68030_TK.lci @@ -12,8 +12,8 @@ EN_PinMacrocell = Yes; [Revision] Parent = m4a5.lci; -DATE = 08/23/2016; -TIME = 20:07:14; +DATE = 10/08/2016; +TIME = 22:26:00; Source_Format = Pure_VHDL; Synthesis = Synplify; @@ -149,7 +149,7 @@ NetList = VHDL; layer = OFF; [Pullup] -Default = UP; +Default = HOLD; [Slewrate] FAST = CLK_DIV_OUT, CLK_EXP, FPU_CS, AMIGA_BUS_DATA_DIR, AMIGA_BUS_ENABLE_LOW, diff --git a/Logic/68030_TK.lct b/Logic/68030_TK.lct index a11a0f7..b80db18 100644 --- a/Logic/68030_TK.lct +++ b/Logic/68030_TK.lct @@ -12,8 +12,8 @@ EN_PinMacrocell = Yes; [Revision] Parent = m4a5.lci; -DATE = 08/23/2016; -TIME = 20:07:14; +DATE = 10/08/2016; +TIME = 22:26:00; Source_Format = Pure_VHDL; Synthesis = Synplify; @@ -149,7 +149,7 @@ NetList = VHDL; layer = OFF; [Pullup] -Default = UP; +Default = HOLD; [Slewrate] FAST = CLK_DIV_OUT, CLK_EXP, FPU_CS, AMIGA_BUS_DATA_DIR, AMIGA_BUS_ENABLE_LOW, diff --git a/Logic/68030_TK.tcl b/Logic/68030_TK.tcl index e79e02d..2997e61 100644 --- a/Logic/68030_TK.tcl +++ b/Logic/68030_TK.tcl @@ -409145,3 +409145,5920 @@ if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 6 ########## Tcl recorder end at 10/06/16 22:03:43 ########### + +########## Tcl recorder starts at 10/07/16 16:25:31 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/07/16 16:25:31 ########### + + +########## Tcl recorder starts at 10/07/16 16:25:31 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/07/16 16:25:31 ########### + + +########## Tcl recorder starts at 10/07/16 16:37:52 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/07/16 16:37:52 ########### + + +########## Tcl recorder starts at 10/07/16 16:37:52 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/07/16 16:37:52 ########### + + +########## Tcl recorder starts at 10/07/16 17:04:15 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/07/16 17:04:15 ########### + + +########## Tcl recorder starts at 10/07/16 17:04:16 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/07/16 17:04:16 ########### + + +########## Tcl recorder starts at 10/07/16 17:05:16 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/07/16 17:05:16 ########### + + +########## Tcl recorder starts at 10/07/16 17:05:16 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/07/16 17:05:16 ########### + + +########## Tcl recorder starts at 10/07/16 17:05:51 ########## + +# Commands to make the Process: +# Constraint Editor +# - none - +# Application to view the Process: +# Constraint Editor +if [catch {open lattice_cmd.rs2 w} rspFile] { + puts stderr "Cannot create response file lattice_cmd.rs2: $rspFile" +} else { + puts $rspFile "-src 68030_tk.tt4 -type PLA -devfile \"$install_dir/ispcpld/dat/mach4a/mach447ace.dev\" -lci \"68030_tk.lct\" -touch \"68030_tk.tt4\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/lciedit\" @lattice_cmd.rs2"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/07/16 17:05:51 ########### + + +########## Tcl recorder starts at 10/07/16 17:06:56 ########## + +# Commands to make the Process: +# JEDEC File +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/07/16 17:06:56 ########### + + +########## Tcl recorder starts at 10/07/16 17:07:30 ########## + +# Commands to make the Process: +# JEDEC File +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/07/16 17:07:30 ########### + + +########## Tcl recorder starts at 10/07/16 17:08:01 ########## + +# Commands to make the Process: +# JEDEC File +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/07/16 17:08:01 ########### + + +########## Tcl recorder starts at 10/07/16 21:29:11 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/07/16 21:29:11 ########### + + +########## Tcl recorder starts at 10/07/16 21:29:12 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/07/16 21:29:12 ########### + + +########## Tcl recorder starts at 10/07/16 21:55:09 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/07/16 21:55:09 ########### + + +########## Tcl recorder starts at 10/07/16 21:55:09 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/07/16 21:55:09 ########### + + +########## Tcl recorder starts at 10/07/16 21:55:59 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/07/16 21:55:59 ########### + + +########## Tcl recorder starts at 10/07/16 21:57:31 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/07/16 21:57:31 ########### + + +########## Tcl recorder starts at 10/07/16 21:57:31 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/07/16 21:57:31 ########### + + +########## Tcl recorder starts at 10/07/16 22:01:26 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/07/16 22:01:26 ########### + + +########## Tcl recorder starts at 10/07/16 22:01:26 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/07/16 22:01:26 ########### + + +########## Tcl recorder starts at 10/07/16 22:04:30 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/07/16 22:04:30 ########### + + +########## Tcl recorder starts at 10/07/16 22:04:30 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/07/16 22:04:30 ########### + + +########## Tcl recorder starts at 10/07/16 23:20:01 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/07/16 23:20:01 ########### + + +########## Tcl recorder starts at 10/07/16 23:20:02 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/07/16 23:20:02 ########### + + +########## Tcl recorder starts at 10/07/16 23:21:17 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/07/16 23:21:17 ########### + + +########## Tcl recorder starts at 10/07/16 23:21:17 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/07/16 23:21:17 ########### + + +########## Tcl recorder starts at 10/07/16 23:24:50 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/07/16 23:24:50 ########### + + +########## Tcl recorder starts at 10/07/16 23:24:50 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/07/16 23:24:50 ########### + + +########## Tcl recorder starts at 10/08/16 19:45:07 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/08/16 19:45:07 ########### + + +########## Tcl recorder starts at 10/08/16 19:45:08 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/08/16 19:45:08 ########### + + +########## Tcl recorder starts at 10/08/16 19:45:43 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/08/16 19:45:43 ########### + + +########## Tcl recorder starts at 10/08/16 19:47:01 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/08/16 19:47:01 ########### + + +########## Tcl recorder starts at 10/08/16 19:47:01 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/08/16 19:47:01 ########### + + +########## Tcl recorder starts at 10/08/16 19:48:20 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/08/16 19:48:20 ########### + + +########## Tcl recorder starts at 10/08/16 19:48:20 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/08/16 19:48:20 ########### + + +########## Tcl recorder starts at 10/08/16 19:52:13 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/08/16 19:52:13 ########### + + +########## Tcl recorder starts at 10/08/16 19:52:13 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/08/16 19:52:13 ########### + + +########## Tcl recorder starts at 10/08/16 22:25:45 ########## + +# Commands to make the Process: +# Constraint Editor +# - none - +# Application to view the Process: +# Constraint Editor +if [catch {open lattice_cmd.rs2 w} rspFile] { + puts stderr "Cannot create response file lattice_cmd.rs2: $rspFile" +} else { + puts $rspFile "-src 68030_tk.tt4 -type PLA -devfile \"$install_dir/ispcpld/dat/mach4a/mach447ace.dev\" -lci \"68030_tk.lct\" -touch \"68030_tk.tt4\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/lciedit\" @lattice_cmd.rs2"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/08/16 22:25:45 ########### + + +########## Tcl recorder starts at 10/08/16 22:26:03 ########## + +# Commands to make the Process: +# JEDEC File +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/08/16 22:26:03 ########### + + +########## Tcl recorder starts at 10/10/16 23:34:19 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/10/16 23:34:19 ########### + + +########## Tcl recorder starts at 10/10/16 23:34:19 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/10/16 23:34:19 ########### + + +########## Tcl recorder starts at 10/10/16 23:35:07 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/10/16 23:35:07 ########### + + +########## Tcl recorder starts at 10/10/16 23:35:07 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/10/16 23:35:07 ########### + + +########## Tcl recorder starts at 10/10/16 23:37:17 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/10/16 23:37:17 ########### + + +########## Tcl recorder starts at 10/10/16 23:37:17 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/10/16 23:37:17 ########### + + +########## Tcl recorder starts at 10/10/16 23:37:50 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/10/16 23:37:50 ########### + + +########## Tcl recorder starts at 10/10/16 23:37:50 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/10/16 23:37:50 ########### + + +########## Tcl recorder starts at 10/10/16 23:41:19 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/10/16 23:41:19 ########### + + +########## Tcl recorder starts at 10/10/16 23:41:19 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/10/16 23:41:19 ########### + + +########## Tcl recorder starts at 10/10/16 23:46:09 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/10/16 23:46:09 ########### + + +########## Tcl recorder starts at 10/10/16 23:46:09 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/10/16 23:46:09 ########### + + +########## Tcl recorder starts at 10/10/16 23:48:40 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/10/16 23:48:40 ########### + + +########## Tcl recorder starts at 10/10/16 23:48:41 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/10/16 23:48:41 ########### + + +########## Tcl recorder starts at 10/10/16 23:50:57 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/10/16 23:50:57 ########### + + +########## Tcl recorder starts at 10/10/16 23:50:57 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/10/16 23:50:57 ########### + + +########## Tcl recorder starts at 10/10/16 23:52:07 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/10/16 23:52:07 ########### + + +########## Tcl recorder starts at 10/10/16 23:52:07 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/10/16 23:52:07 ########### + + +########## Tcl recorder starts at 10/10/16 23:53:12 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/10/16 23:53:12 ########### + + +########## Tcl recorder starts at 10/10/16 23:53:12 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/10/16 23:53:12 ########### + + +########## Tcl recorder starts at 10/14/16 21:58:44 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/14/16 21:58:44 ########### + + +########## Tcl recorder starts at 10/14/16 21:58:45 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/14/16 21:58:45 ########### + + +########## Tcl recorder starts at 10/15/16 23:24:46 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/15/16 23:24:46 ########### + + +########## Tcl recorder starts at 10/15/16 23:24:46 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/15/16 23:24:46 ########### + + +########## Tcl recorder starts at 10/15/16 23:47:55 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/15/16 23:47:55 ########### + + +########## Tcl recorder starts at 10/15/16 23:47:55 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/15/16 23:47:55 ########### + diff --git a/Logic/68030_tk.bl2 b/Logic/68030_tk.bl2 index 1c99faf..c12c52b 100644 --- a/Logic/68030_tk.bl2 +++ b/Logic/68030_tk.bl2 @@ -1,109 +1,108 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Thu Oct 06 22:04:11 2016 +#$ DATE Sat Oct 15 23:48:24 2016 #$ MODULE 68030_tk #$ PINS 75 SIZE_1_ AHIGH_31_ A_DECODE_23_ IPL_030_2_ IPL_2_ FC_1_ AS_030 AS_000 RW_000 \ -# DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 SIZE_0_ CLK_030 \ -# AHIGH_30_ CLK_000 AHIGH_29_ CLK_OSZI AHIGH_28_ CLK_DIV_OUT AHIGH_27_ CLK_EXP AHIGH_26_ \ -# FPU_CS AHIGH_25_ FPU_SENSE AHIGH_24_ DSACK1 A_DECODE_22_ DTACK A_DECODE_21_ AVEC \ -# A_DECODE_20_ E A_DECODE_19_ VPA A_DECODE_18_ VMA A_DECODE_17_ RST A_DECODE_16_ RESET \ -# A_DECODE_15_ RW A_DECODE_14_ AMIGA_ADDR_ENABLE A_DECODE_13_ AMIGA_BUS_DATA_DIR \ -# A_DECODE_12_ AMIGA_BUS_ENABLE_LOW A_DECODE_11_ AMIGA_BUS_ENABLE_HIGH A_DECODE_10_ \ -# CIIN A_DECODE_9_ A_DECODE_8_ A_DECODE_7_ A_DECODE_6_ A_DECODE_5_ A_DECODE_4_ \ -# A_DECODE_3_ A_DECODE_2_ A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ IPL_0_ FC_0_ A_1_ -#$ NODES 600 rst_dly_i_1__n N_41_0 sm_amiga_i_5__n a_c_i_0__n rst_dly_i_0__n \ -# size_c_i_1__n sm_amiga_i_i_7__n pos_clk_un10_sm_amiga_i_n AS_030_D0_i un1_as_000_i \ -# AS_000_INT_i un10_ciin_i a_i_1__n N_260_0 a_decode_i_16__n N_229_i \ -# inst_BGACK_030_INTreg a_decode_i_18__n N_230_i vcc_n_n a_decode_i_19__n N_298_0 \ -# inst_VMA_INTreg ahigh_i_30__n N_48_0 gnd_n_n ahigh_i_31__n N_299_i \ -# un1_amiga_bus_enable_low ahigh_i_28__n N_345_i un7_as_030 ahigh_i_29__n N_349_i \ -# un1_UDS_000_INT ahigh_i_26__n un1_DS_000_ENABLE_0_sqmuxa_i un1_LDS_000_INT \ -# ahigh_i_27__n N_180_i un1_SM_AMIGA_0_sqmuxa_1 ahigh_i_24__n N_181_i un10_ciin \ -# ahigh_i_25__n N_326_i un21_fpu_cs N_206_i un21_berr N_207_i N_186_i un6_ds_030 N_208_i \ -# N_163_i cpu_est_2_ N_197_0 cpu_est_3_ N_79_i N_213_i cpu_est_0_ N_78_i N_214_i \ -# cpu_est_1_ un6_ds_030_i N_215_i inst_AMIGA_BUS_ENABLE_DMA_LOW N_165_i \ -# inst_AS_030_D0 N_169_i N_199_i inst_AS_030_000_SYNC un7_as_030_i N_191_0 \ -# inst_BGACK_030_INT_D AMIGA_BUS_ENABLE_DMA_LOW_i N_275_i inst_AS_000_DMA AS_030_c \ -# N_187_0 inst_DS_000_DMA LDS_000_c_i CYCLE_DMA_0_ AS_000_c UDS_000_c_i CYCLE_DMA_1_ \ -# N_184_i inst_VPA_D RW_000_c clk_000_d_i_4__n CLK_000_D_2_ N_171_i CLK_000_D_4_ \ -# AS_030_000_SYNC_i inst_DTACK_D0 UDS_000_c N_161_i inst_RESET_OUT CLK_000_D_1_ \ -# LDS_000_c N_113_0 CLK_000_D_0_ N_338_i inst_CLK_OUT_PRE_50 size_c_0__n N_339_i \ -# inst_CLK_OUT_PRE_D IPL_D0_0_ size_c_1__n N_335_i IPL_D0_1_ N_336_i IPL_D0_2_ \ -# ahigh_c_24__n CLK_000_D_3_ N_334_i CLK_000_D_5_ ahigh_c_25__n \ -# pos_clk_size_dma_6_0_1__n pos_clk_un6_bg_030_n N_333_i \ -# inst_AMIGA_BUS_ENABLE_DMA_HIGH ahigh_c_26__n pos_clk_size_dma_6_0_0__n \ -# pos_clk_ipl_n N_295_i SM_AMIGA_1_ ahigh_c_27__n N_332_i inst_UDS_000_INT \ -# inst_DS_000_ENABLE ahigh_c_28__n N_292_i inst_LDS_000_INT N_302_0 \ -# pos_clk_un9_bg_030_n ahigh_c_29__n N_300_0 SM_AMIGA_6_ N_290_i SM_AMIGA_4_ \ -# ahigh_c_30__n SM_AMIGA_0_ N_273_i SIZE_DMA_0_ ahigh_c_31__n SIZE_DMA_1_ N_327_i \ -# inst_RW_000_INT inst_RW_000_DMA N_270_i RST_DLY_0_ RST_DLY_1_ N_269_i RST_DLY_2_ \ -# inst_A0_DMA N_267_i pos_clk_a0_dma_3_n N_324_i inst_CLK_030_H \ -# pos_clk_rw_000_int_5_n un1_SM_AMIGA_0_sqmuxa_1_0 inst_DSACK1_INT N_319_i \ -# inst_AS_000_INT N_320_i SM_AMIGA_5_ SM_AMIGA_3_ RW_c_i SM_AMIGA_2_ \ -# pos_clk_rw_000_int_5_0_n N_227_i N_297_0 N_15_i N_40_0 N_16_i N_15 N_39_0 N_16 N_19_i \ -# N_19 N_36_0 N_20 N_20_i N_22 N_35_0 N_23 N_22_i N_24 N_33_0 N_23_i N_32_0 a_decode_c_16__n \ -# N_24_i N_31_0 a_decode_c_17__n BG_030_c_i pos_clk_un6_bg_030_i_n a_decode_c_18__n \ -# pos_clk_un9_bg_030_0_n N_161_i_1 a_decode_c_19__n N_161_i_2 N_161_i_3 \ -# a_decode_c_20__n N_161_i_4 N_233_i_1 a_decode_c_21__n N_233_i_2 N_180_i_1 \ -# a_decode_c_22__n N_180_i_2 pos_clk_un10_sm_amiga_i_1_n a_decode_c_23__n N_196_0_1 \ -# N_188_i_1 a_c_0__n un10_ciin_1 un10_ciin_2 a_c_1__n un10_ciin_3 un10_ciin_4 \ -# nEXP_SPACE_c un10_ciin_5 SM_AMIGA_i_7_ un10_ciin_6 pos_clk_size_dma_6_0__n BERR_c \ -# un10_ciin_7 pos_clk_size_dma_6_1__n un10_ciin_8 G_107 BG_030_c un10_ciin_9 G_108 \ -# un10_ciin_10 G_109 BG_000DFFreg un10_ciin_11 N_171_i_1 N_78 N_171_i_2 N_79 BGACK_000_c \ -# N_227_1 N_260 N_227_2 N_139 CLK_030_c N_227_3 N_141 un21_fpu_cs_1 N_165 un21_berr_1_0 \ -# N_169 N_235_i_1 N_297 CLK_OSZI_c N_235_i_2 N_256_1 N_300 N_256_2 N_302 CLK_OUT_INTreg \ -# N_232_i_1 N_113 N_232_i_2 N_305 N_219_1 N_155 FPU_SENSE_c N_219_2 N_163 N_218_1 N_166 \ -# IPL_030DFF_0_reg N_218_2 N_171 N_347_1 N_180 IPL_030DFF_1_reg N_347_2 N_184 N_136_i_1 \ -# N_191 IPL_030DFF_2_reg N_146_i_1 N_199 N_142_i_1 N_205 ipl_c_0__n N_234_i_1 N_306 \ -# N_302_0_1 N_215 ipl_c_1__n N_63_i_1 N_221 N_154_i_1 N_227 ipl_c_2__n N_152_i_1 N_230 \ -# N_148_i_1 N_319 N_144_i_1 N_320 DTACK_c N_140_i_1 N_267 pos_clk_un6_bg_030_1_n N_324 \ -# N_230_1 N_269 N_221_1 N_270 VPA_c N_215_1 N_327 N_306_1 N_273 pos_clk_ipl_1_n N_275 RST_c \ -# ipl_030_0_2__un3_n N_290 ipl_030_0_2__un1_n N_292 ipl_030_0_2__un0_n N_295 RW_c \ -# ipl_030_0_1__un3_n N_332 ipl_030_0_1__un1_n N_333 fc_c_0__n ipl_030_0_1__un0_n N_334 \ -# ipl_030_0_0__un3_n N_335 fc_c_1__n ipl_030_0_0__un1_n N_336 ipl_030_0_0__un0_n N_338 \ -# cpu_est_0_3__un3_n N_339 AMIGA_BUS_DATA_DIR_c cpu_est_0_3__un1_n N_350 \ -# cpu_est_0_3__un0_n pos_clk_CYCLE_DMA_5_1_i_x2 vma_int_0_un3_n N_161 \ -# vma_int_0_un1_n N_213 vma_int_0_un0_n N_214 VPA_c_i cpu_est_0_1__un3_n N_197 N_52_0 \ -# cpu_est_0_1__un1_n N_159 DTACK_c_i cpu_est_0_1__un0_n N_326 N_53_0 \ -# cpu_est_0_2__un3_n un21_berr_1 ipl_c_i_0__n cpu_est_0_2__un1_n N_181 N_49_0 \ -# cpu_est_0_2__un0_n pos_clk_un21_bgack_030_int_i_i_a2_i_x2 ipl_c_i_1__n \ -# ds_000_dma_0_un3_n un1_DS_000_ENABLE_0_sqmuxa N_50_0 ds_000_dma_0_un1_n N_349 \ -# ipl_c_i_2__n ds_000_dma_0_un0_n N_345 N_51_0 as_000_dma_0_un3_n N_229 N_25_i \ -# as_000_dma_0_un1_n N_14 N_28_0 as_000_dma_0_un0_n N_21 N_26_i bgack_030_int_0_un3_n \ -# N_3 N_29_0 bgack_030_int_0_un1_n N_301 N_27_i bgack_030_int_0_un0_n N_4 N_30_0 \ -# ds_000_enable_0_un3_n N_303 N_222_i ds_000_enable_0_un1_n N_8 N_223_i \ -# ds_000_enable_0_un0_n pos_clk_un6_bgack_000_n N_192_i uds_000_int_0_un3_n N_9 \ -# N_231_i uds_000_int_0_un1_n N_65 N_237_i uds_000_int_0_un0_n N_217 \ -# lds_000_int_0_un3_n N_216 N_342_i lds_000_int_0_un1_n N_248 N_341_i \ -# lds_000_int_0_un0_n N_198 un1_amiga_bus_enable_dma_high_i_m2_0__un3_n N_291 \ -# N_160_0 un1_amiga_bus_enable_dma_high_i_m2_0__un1_n N_353 N_164_i \ -# un1_amiga_bus_enable_dma_high_i_m2_0__un0_n N_256 VMA_INT_i \ -# amiga_bus_enable_dma_high_0_un3_n N_18 N_347_i amiga_bus_enable_dma_high_0_un1_n \ -# pos_clk_un9_clk_000_pe_n N_348_i amiga_bus_enable_dma_high_0_un0_n cpu_est_2_1__n \ -# N_188_i bg_000_0_un3_n cpu_est_2_2__n N_245_0 bg_000_0_un1_n N_209 N_194_0 \ -# bg_000_0_un0_n N_211 N_196_0 size_dma_0_0__un3_n N_220 size_dma_0_0__un1_n N_222 \ -# N_211_i size_dma_0_0__un0_n N_162 N_209_i size_dma_0_1__un3_n N_224 N_306_i \ -# size_dma_0_1__un1_n N_193 N_193_0 size_dma_0_1__un0_n N_225 N_190_0 \ -# as_030_000_sync_0_un3_n N_190 N_183_i as_030_000_sync_0_un1_n N_346 N_162_i \ -# as_030_000_sync_0_un0_n N_352 N_346_i rw_000_int_0_un3_n N_219 N_159_0 \ -# rw_000_int_0_un1_n N_218 N_305_i rw_000_int_0_un0_n N_183 N_210_i rw_000_dma_0_un3_n \ -# N_196 N_225_i rw_000_dma_0_un1_n N_188 N_224_i rw_000_dma_0_un0_n N_194 N_296_i \ -# a0_dma_0_un3_n N_347 N_352_i a0_dma_0_un1_n N_348 cpu_est_2_0_2__n a0_dma_0_un0_n \ -# N_160 N_220_i amiga_bus_enable_dma_low_0_un3_n N_341 N_221_i \ -# amiga_bus_enable_dma_low_0_un1_n N_342 cpu_est_2_0_1__n \ -# amiga_bus_enable_dma_low_0_un0_n N_231 N_219_i a_decode_15__n N_237 N_218_i N_223 \ -# pos_clk_un9_clk_000_pe_0_n a_decode_14__n N_27 clk_000_d_i_2__n N_26 N_157_i \ -# a_decode_13__n N_25 N_18_i un1_amiga_bus_enable_low_i N_37_0 a_decode_12__n \ -# un21_fpu_cs_i cpu_est_i_2__n N_217_i a_decode_11__n sm_amiga_i_0__n N_216_i \ -# sm_amiga_i_2__n CLK_030_c_i a_decode_10__n sm_amiga_i_1__n N_198_0 cpu_est_i_0__n \ -# N_166_i a_decode_9__n VPA_D_i N_155_i DTACK_D0_i N_303_0 a_decode_8__n AS_030_i \ -# N_291_i DSACK1_INT_i N_301_0 a_decode_7__n cpu_est_i_3__n N_256_i sm_amiga_i_3__n \ -# N_248_i a_decode_6__n cpu_est_i_1__n AMIGA_BUS_DATA_DIR_c_0 clk_000_d_i_1__n \ -# N_353_i a_decode_5__n N_350_i_0 pos_clk_un6_bgack_000_0_n rst_dly_i_2__n N_65_0 \ -# a_decode_4__n nEXP_SPACE_i N_3_i AS_000_i N_45_0 a_decode_3__n BGACK_030_INT_i N_4_i \ -# sm_amiga_i_6__n N_44_0 a_decode_2__n clk_000_d_i_0__n N_8_i RW_000_i N_42_0 \ -# CLK_030_H_i UDS_000_INT_i AS_000_DMA_i un1_UDS_000_INT_0 cycle_dma_i_0__n \ -# LDS_000_INT_i DS_000_DMA_i un1_LDS_000_INT_0 RESET_OUT_i N_21_i sm_amiga_i_4__n \ -# N_34_0 FPU_SENSE_i N_14_i +# DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BG_000 SIZE_0_ BGACK_030 AHIGH_30_ \ +# BGACK_000 AHIGH_29_ CLK_030 AHIGH_28_ CLK_000 AHIGH_27_ CLK_OSZI AHIGH_26_ CLK_DIV_OUT \ +# AHIGH_25_ CLK_EXP AHIGH_24_ FPU_CS A_DECODE_22_ FPU_SENSE A_DECODE_21_ DSACK1 \ +# A_DECODE_20_ DTACK A_DECODE_19_ AVEC A_DECODE_18_ E A_DECODE_17_ VPA A_DECODE_16_ VMA \ +# A_DECODE_15_ RST A_DECODE_14_ RESET A_DECODE_13_ RW A_DECODE_12_ AMIGA_ADDR_ENABLE \ +# A_DECODE_11_ AMIGA_BUS_DATA_DIR A_DECODE_10_ AMIGA_BUS_ENABLE_LOW A_DECODE_9_ \ +# AMIGA_BUS_ENABLE_HIGH A_DECODE_8_ CIIN A_DECODE_7_ A_DECODE_6_ A_DECODE_5_ \ +# A_DECODE_4_ A_DECODE_3_ A_DECODE_2_ A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ IPL_0_ FC_0_ A_1_ +#$ NODES 598 ipl_i_2__n N_233_0 ipl_i_1__n N_360_i ipl_i_0__n N_191_i_i a_i_1__n \ +# N_192_i_i AS_000_DMA_i AS_000_i N_199_i CLK_030_H_i N_204_i AS_030_000_SYNC_i \ +# inst_BGACK_030_INTreg AMIGA_BUS_ENABLE_DMA_HIGH_i N_282_i vcc_n_n cycle_dma_i_0__n \ +# N_278_i inst_VMA_INTreg ahigh_i_30__n N_186_i gnd_n_n ahigh_i_31__n N_185_i \ +# un1_amiga_bus_enable_low ahigh_i_28__n CLK_030_c_i un7_as_030 ahigh_i_29__n N_184_0 \ +# un1_LDS_000_INT ahigh_i_26__n N_179_0 un1_UDS_000_INT ahigh_i_27__n N_251_i \ +# un10_ciin ahigh_i_24__n LDS_000_c_i un21_fpu_cs ahigh_i_25__n UDS_000_c_i un21_berr \ +# N_172_i un6_ds_030 pos_clk_un21_bgack_030_int_i_0_0_n cpu_est_2_ N_163_i cpu_est_3_ \ +# clk_000_d_i_3__n cpu_est_0_ N_115_i N_350_i cpu_est_1_ N_114_i un1_rw_i \ +# inst_AMIGA_BUS_ENABLE_DMA_HIGH un6_ds_030_i N_126_0 inst_AMIGA_BUS_ENABLE_DMA_LOW \ +# DS_000_DMA_i N_313_i inst_AS_030_D0 N_132_i N_231_i inst_AS_030_000_SYNC N_133_i \ +# N_291_i inst_BGACK_030_INT_D un7_as_030_i inst_AS_000_DMA \ +# AMIGA_BUS_ENABLE_DMA_LOW_i N_288_i inst_DS_000_DMA AS_030_c CYCLE_DMA_0_ N_287_i \ +# CYCLE_DMA_1_ AS_000_c N_340_i inst_VPA_D CLK_000_D_3_ RW_000_c N_284_i inst_DTACK_D0 \ +# inst_RESET_OUT N_275_i CLK_000_D_1_ UDS_000_c pos_clk_size_dma_6_0_1__n \ +# CLK_000_D_0_ N_268_i inst_CLK_OUT_PRE_50 LDS_000_c pos_clk_size_dma_6_0_0__n \ +# inst_CLK_OUT_PRE_D N_265_i IPL_D0_0_ size_c_0__n N_267_i IPL_D0_1_ IPL_D0_2_ \ +# size_c_1__n N_337_i CLK_000_D_2_ N_338_i CLK_000_D_4_ ahigh_c_24__n N_55_0 \ +# inst_LDS_000_INT un1_as_000_i inst_DS_000_ENABLE ahigh_c_25__n N_245_0 \ +# inst_UDS_000_INT N_229_i pos_clk_un9_bg_030_n ahigh_c_26__n SM_AMIGA_6_ N_227_i \ +# SM_AMIGA_4_ ahigh_c_27__n SM_AMIGA_1_ N_226_i SM_AMIGA_0_ ahigh_c_28__n N_246_0 \ +# SIZE_DMA_0_ N_332_i SIZE_DMA_1_ ahigh_c_29__n pos_clk_ds_000_dma_4_0_n \ +# inst_RW_000_INT N_48_0 inst_RW_000_DMA ahigh_c_30__n pos_clk_rw_000_dma_3_0_n \ +# RST_DLY_0_ N_218_i RST_DLY_1_ ahigh_c_31__n RST_DLY_2_ inst_A0_DMA un10_ciin_i \ +# pos_clk_a0_dma_3_n N_62_0 pos_clk_rw_000_dma_3_n N_215_i inst_CLK_030_H N_216_i \ +# inst_DSACK1_INT un10_amiga_bus_enable_high_i inst_AS_000_INT N_214_i SM_AMIGA_5_ \ +# N_310_0 SM_AMIGA_3_ N_24_i SM_AMIGA_2_ N_33_0 pos_clk_ds_000_dma_4_n N_23_i N_3 N_32_0 \ +# N_4 N_22_i N_31_0 N_3_i N_45_0 N_4_i N_44_0 N_15 N_15_i N_19 N_40_0 N_20 N_19_i N_22 N_36_0 \ +# N_23 N_20_i N_24 N_35_0 N_25 N_25_i N_26 N_30_0 N_27 N_26_i N_29_0 N_27_i a_decode_c_16__n \ +# N_28_0 BG_030_c_i a_decode_c_17__n pos_clk_un9_bg_030_0_n N_235_i_1 \ +# a_decode_c_18__n N_235_i_2 N_156_i_1 a_decode_c_19__n N_156_i_2 N_156_i_3 \ +# a_decode_c_20__n N_156_i_4 pos_clk_un10_sm_amiga_i_1_n a_decode_c_21__n N_176_i_1 \ +# un10_ciin_1 a_decode_c_22__n un10_ciin_2 un10_ciin_3 a_decode_c_23__n un10_ciin_4 \ +# un10_ciin_5 a_c_0__n un10_ciin_6 un10_ciin_7 a_c_1__n un10_ciin_8 SM_AMIGA_i_7_ \ +# un10_ciin_9 pos_clk_size_dma_6_0__n nEXP_SPACE_c un10_ciin_10 \ +# pos_clk_size_dma_6_1__n un10_ciin_11 N_199 BERR_c N_163_i_1 \ +# pos_clk_un21_bgack_030_int_i_0_n N_163_i_2 N_231 BG_030_c \ +# pos_clk_un21_bgack_030_int_i_0_0_1_n N_233 pos_clk_un21_bgack_030_int_i_0_0_2_n \ +# N_111 BG_000DFFreg N_138_i_1 N_112 N_138_i_2 N_113 N_59_i_1 N_114 BGACK_000_c N_59_i_2 \ +# N_115 N_233_0_1 N_245 CLK_030_c N_233_0_2 N_246 N_214_1 N_62 N_214_2 N_214_3 N_132 \ +# CLK_OSZI_c un21_fpu_cs_1 N_133 un21_berr_1_0 N_310 N_182_0_1 N_126 CLK_OUT_INTreg \ +# N_234_i_1 N_149 N_234_i_2 N_150 N_206_1 N_158 FPU_SENSE_c N_206_2 N_160 N_205_1 N_163 \ +# IPL_030DFF_0_reg N_205_2 N_172 N_352_1 N_179 IPL_030DFF_1_reg N_352_2 N_184 N_231_i_1 \ +# N_185 IPL_030DFF_2_reg N_152_i_1 N_196 N_144_i_1 N_203 ipl_c_0__n N_142_i_1 N_204 \ +# N_312_i_1 N_209 ipl_c_1__n N_236_i_1 N_214 N_148_i_1 N_215 ipl_c_2__n N_136_i_1 N_216 \ +# N_246_0_1 N_218 N_249_i_1 N_224 DTACK_c N_57_i_1 N_332 N_338_1 N_226 N_224_1 N_227 \ +# N_216_1 N_229 VPA_c N_209_1 N_337 N_203_1 N_338 N_196_1 N_265 RST_c cpu_est_0_3__un3_n \ +# N_267 cpu_est_0_3__un1_n N_268 cpu_est_0_3__un0_n N_275 RW_c rw_000_int_0_un3_n N_278 \ +# rw_000_int_0_un1_n N_282 fc_c_0__n rw_000_int_0_un0_n N_284 vma_int_0_un3_n N_340 \ +# fc_c_1__n vma_int_0_un1_n N_287 vma_int_0_un0_n N_288 cpu_est_0_1__un3_n N_291 \ +# AMIGA_BUS_DATA_DIR_c cpu_est_0_1__un1_n N_293 cpu_est_0_1__un0_n N_350 \ +# cpu_est_0_2__un3_n N_355 cpu_est_0_2__un1_n \ +# pos_clk_un21_bgack_030_int_i_0_o3_0_x2 cpu_est_0_2__un0_n pos_clk_un1_ipl_i_0_x2 \ +# N_16_i uds_000_int_0_un3_n pos_clk_un1_ipl_i_0_x2_0 N_39_0 uds_000_int_0_un1_n \ +# pos_clk_un1_ipl_i_0_x2_1 VPA_c_i uds_000_int_0_un0_n pos_clk_CYCLE_DMA_5_1_i_0_x2 \ +# N_52_0 lds_000_int_0_un3_n N_156 DTACK_c_i lds_000_int_0_un1_n N_201 N_53_0 \ +# lds_000_int_0_un0_n N_202 N_210_i bgack_030_int_0_un3_n N_154 N_211_i \ +# bgack_030_int_0_un1_n un21_berr_1 N_189_i bgack_030_int_0_un0_n N_174 \ +# un1_SM_AMIGA_0_sqmuxa_1_0 ds_000_enable_0_un3_n N_223 RW_c_i ds_000_enable_0_un1_n \ +# N_221 N_311_0 ds_000_enable_0_un0_n N_222 N_336_i size_dma_0_0__un3_n N_219 N_244_i \ +# size_dma_0_0__un1_n N_220 size_dma_0_0__un0_n pos_clk_un6_bgack_000_n N_314_0 \ +# size_dma_0_1__un3_n N_359 N_159_i size_dma_0_1__un1_n N_8 VMA_INT_i \ +# size_dma_0_1__un0_n N_14 N_352_i ipl_030_0_0__un3_n N_21 N_353_i ipl_030_0_0__un1_n \ +# N_9 N_293_i ipl_030_0_0__un0_n un1_DS_000_ENABLE_0_sqmuxa N_175_i \ +# ipl_030_0_1__un3_n N_66 N_176_i ipl_030_0_1__un1_n N_171 ipl_030_0_1__un0_n N_354 \ +# N_198_i ipl_030_0_2__un3_n N_18 N_197_i ipl_030_0_2__un1_n pos_clk_un9_clk_000_pe_n \ +# N_196_i ipl_030_0_2__un0_n cpu_est_2_1__n N_183_0 a0_dma_0_un3_n cpu_est_2_2__n \ +# N_182_0 a0_dma_0_un1_n N_197 N_180_0 a0_dma_0_un0_n N_198 N_178_0 \ +# amiga_bus_enable_dma_low_0_un3_n N_208 N_82_i amiga_bus_enable_dma_low_0_un1_n \ +# N_210 N_315_i amiga_bus_enable_dma_low_0_un0_n N_315 N_351_i \ +# amiga_bus_enable_dma_high_0_un3_n N_212 N_154_0 amiga_bus_enable_dma_high_0_un1_n \ +# N_180 N_149_i amiga_bus_enable_dma_high_0_un0_n N_213 N_207_i bg_000_0_un3_n N_178 \ +# N_228_i bg_000_0_un1_n N_228 bg_000_0_un0_n N_182 N_213_i ds_000_dma_0_un3_n N_176 \ +# N_212_i ds_000_dma_0_un1_n N_183 N_309_i ds_000_dma_0_un0_n N_351 N_357_i \ +# as_000_dma_0_un3_n N_357 cpu_est_2_0_2__n as_000_dma_0_un1_n N_206 N_208_i \ +# as_000_dma_0_un0_n N_205 N_209_i as_030_000_sync_0_un3_n N_352 cpu_est_2_0_1__n \ +# as_030_000_sync_0_un1_n N_353 N_206_i as_030_000_sync_0_un0_n N_314 N_205_i \ +# rw_000_dma_0_un3_n N_244 pos_clk_un9_clk_000_pe_0_n rw_000_dma_0_un1_n N_336 N_18_i \ +# rw_000_dma_0_un0_n N_311 N_37_0 a_decode_15__n un1_SM_AMIGA_0_sqmuxa_1 N_171_i N_211 \ +# N_354_i a_decode_14__n N_16 un1_DS_000_ENABLE_0_sqmuxa_0 \ +# un1_amiga_bus_enable_low_i N_66_0 a_decode_13__n un21_fpu_cs_i UDS_000_INT_i \ +# cpu_est_i_2__n un1_UDS_000_INT_0 a_decode_12__n cpu_est_i_0__n LDS_000_INT_i \ +# VPA_D_i un1_LDS_000_INT_0 a_decode_11__n DTACK_D0_i N_21_i cpu_est_i_3__n N_34_0 \ +# a_decode_10__n sm_amiga_i_i_7__n N_14_i sm_amiga_i_5__n N_41_0 a_decode_9__n \ +# sm_amiga_i_3__n N_8_i cpu_est_i_1__n N_42_0 a_decode_8__n clk_000_d_i_1__n \ +# a_c_i_0__n N_355_i_0 size_c_i_1__n a_decode_7__n sm_amiga_i_4__n \ +# pos_clk_un10_sm_amiga_i_n sm_amiga_i_2__n N_359_i a_decode_6__n rst_dly_i_0__n \ +# pos_clk_un6_bgack_000_0_n rst_dly_i_2__n N_220_i a_decode_5__n a_decode_i_19__n \ +# N_219_i a_decode_i_18__n a_decode_4__n a_decode_i_16__n N_222_i RW_000_i N_221_i \ +# a_decode_3__n sm_amiga_i_0__n AS_030_i N_223_i a_decode_2__n AS_000_INT_i N_224_i \ +# DSACK1_INT_i AMIGA_BUS_DATA_DIR_c_0 clk_000_d_i_0__n N_150_i sm_amiga_i_6__n \ +# N_156_i sm_amiga_i_1__n N_160_i FPU_SENSE_i N_174_i rst_dly_i_1__n N_158_i \ +# AS_030_D0_i N_201_i BGACK_030_INT_i N_202_i nEXP_SPACE_i N_203_i RESET_OUT_i .model bus68030 .inputs A_DECODE_23_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF \ BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF FPU_SENSE.BLIF \ @@ -116,323 +115,305 @@ A_DECODE_4_.BLIF A_DECODE_3_.BLIF A_DECODE_2_.BLIF IPL_1_.BLIF IPL_0_.BLIF \ FC_0_.BLIF A_1_.BLIF SIZE_1_.BLIF AHIGH_31_.BLIF AS_030.BLIF AS_000.BLIF \ RW_000.BLIF UDS_000.BLIF LDS_000.BLIF BERR.BLIF RW.BLIF SIZE_0_.BLIF \ AHIGH_30_.BLIF AHIGH_29_.BLIF AHIGH_28_.BLIF AHIGH_27_.BLIF AHIGH_26_.BLIF \ -AHIGH_25_.BLIF AHIGH_24_.BLIF A_0_.BLIF rst_dly_i_1__n.BLIF N_41_0.BLIF \ -sm_amiga_i_5__n.BLIF a_c_i_0__n.BLIF rst_dly_i_0__n.BLIF size_c_i_1__n.BLIF \ -sm_amiga_i_i_7__n.BLIF pos_clk_un10_sm_amiga_i_n.BLIF AS_030_D0_i.BLIF \ -un1_as_000_i.BLIF AS_000_INT_i.BLIF un10_ciin_i.BLIF a_i_1__n.BLIF \ -N_260_0.BLIF a_decode_i_16__n.BLIF N_229_i.BLIF inst_BGACK_030_INTreg.BLIF \ -a_decode_i_18__n.BLIF N_230_i.BLIF vcc_n_n.BLIF a_decode_i_19__n.BLIF \ -N_298_0.BLIF inst_VMA_INTreg.BLIF ahigh_i_30__n.BLIF N_48_0.BLIF gnd_n_n.BLIF \ -ahigh_i_31__n.BLIF N_299_i.BLIF un1_amiga_bus_enable_low.BLIF \ -ahigh_i_28__n.BLIF N_345_i.BLIF un7_as_030.BLIF ahigh_i_29__n.BLIF \ -N_349_i.BLIF un1_UDS_000_INT.BLIF ahigh_i_26__n.BLIF \ -un1_DS_000_ENABLE_0_sqmuxa_i.BLIF un1_LDS_000_INT.BLIF ahigh_i_27__n.BLIF \ -N_180_i.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF ahigh_i_24__n.BLIF N_181_i.BLIF \ -un10_ciin.BLIF ahigh_i_25__n.BLIF N_326_i.BLIF un21_fpu_cs.BLIF N_206_i.BLIF \ -un21_berr.BLIF N_207_i.BLIF N_186_i.BLIF un6_ds_030.BLIF N_208_i.BLIF \ -N_163_i.BLIF cpu_est_2_.BLIF N_197_0.BLIF cpu_est_3_.BLIF N_79_i.BLIF \ -N_213_i.BLIF cpu_est_0_.BLIF N_78_i.BLIF N_214_i.BLIF cpu_est_1_.BLIF \ -un6_ds_030_i.BLIF N_215_i.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF N_165_i.BLIF \ -inst_AS_030_D0.BLIF N_169_i.BLIF N_199_i.BLIF inst_AS_030_000_SYNC.BLIF \ -un7_as_030_i.BLIF N_191_0.BLIF inst_BGACK_030_INT_D.BLIF \ -AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF N_275_i.BLIF inst_AS_000_DMA.BLIF \ -AS_030_c.BLIF N_187_0.BLIF inst_DS_000_DMA.BLIF LDS_000_c_i.BLIF \ -CYCLE_DMA_0_.BLIF AS_000_c.BLIF UDS_000_c_i.BLIF CYCLE_DMA_1_.BLIF \ -N_184_i.BLIF inst_VPA_D.BLIF RW_000_c.BLIF clk_000_d_i_4__n.BLIF \ -CLK_000_D_2_.BLIF N_171_i.BLIF CLK_000_D_4_.BLIF AS_030_000_SYNC_i.BLIF \ -inst_DTACK_D0.BLIF UDS_000_c.BLIF N_161_i.BLIF inst_RESET_OUT.BLIF \ -CLK_000_D_1_.BLIF LDS_000_c.BLIF N_113_0.BLIF CLK_000_D_0_.BLIF N_338_i.BLIF \ -inst_CLK_OUT_PRE_50.BLIF size_c_0__n.BLIF N_339_i.BLIF inst_CLK_OUT_PRE_D.BLIF \ -IPL_D0_0_.BLIF size_c_1__n.BLIF N_335_i.BLIF IPL_D0_1_.BLIF N_336_i.BLIF \ -IPL_D0_2_.BLIF ahigh_c_24__n.BLIF CLK_000_D_3_.BLIF N_334_i.BLIF \ -CLK_000_D_5_.BLIF ahigh_c_25__n.BLIF pos_clk_size_dma_6_0_1__n.BLIF \ -pos_clk_un6_bg_030_n.BLIF N_333_i.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ -ahigh_c_26__n.BLIF pos_clk_size_dma_6_0_0__n.BLIF pos_clk_ipl_n.BLIF \ -N_295_i.BLIF SM_AMIGA_1_.BLIF ahigh_c_27__n.BLIF N_332_i.BLIF \ -inst_UDS_000_INT.BLIF inst_DS_000_ENABLE.BLIF ahigh_c_28__n.BLIF N_292_i.BLIF \ -inst_LDS_000_INT.BLIF N_302_0.BLIF pos_clk_un9_bg_030_n.BLIF \ -ahigh_c_29__n.BLIF N_300_0.BLIF SM_AMIGA_6_.BLIF N_290_i.BLIF SM_AMIGA_4_.BLIF \ -ahigh_c_30__n.BLIF SM_AMIGA_0_.BLIF N_273_i.BLIF SIZE_DMA_0_.BLIF \ -ahigh_c_31__n.BLIF SIZE_DMA_1_.BLIF N_327_i.BLIF inst_RW_000_INT.BLIF \ -inst_RW_000_DMA.BLIF N_270_i.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF N_269_i.BLIF \ -RST_DLY_2_.BLIF inst_A0_DMA.BLIF N_267_i.BLIF pos_clk_a0_dma_3_n.BLIF \ -N_324_i.BLIF inst_CLK_030_H.BLIF pos_clk_rw_000_int_5_n.BLIF \ -un1_SM_AMIGA_0_sqmuxa_1_0.BLIF inst_DSACK1_INT.BLIF N_319_i.BLIF \ -inst_AS_000_INT.BLIF N_320_i.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_3_.BLIF \ -RW_c_i.BLIF SM_AMIGA_2_.BLIF pos_clk_rw_000_int_5_0_n.BLIF N_227_i.BLIF \ -N_297_0.BLIF N_15_i.BLIF N_40_0.BLIF N_16_i.BLIF N_15.BLIF N_39_0.BLIF \ -N_16.BLIF N_19_i.BLIF N_19.BLIF N_36_0.BLIF N_20.BLIF N_20_i.BLIF N_22.BLIF \ -N_35_0.BLIF N_23.BLIF N_22_i.BLIF N_24.BLIF N_33_0.BLIF N_23_i.BLIF \ -N_32_0.BLIF a_decode_c_16__n.BLIF N_24_i.BLIF N_31_0.BLIF \ -a_decode_c_17__n.BLIF BG_030_c_i.BLIF pos_clk_un6_bg_030_i_n.BLIF \ -a_decode_c_18__n.BLIF pos_clk_un9_bg_030_0_n.BLIF N_161_i_1.BLIF \ -a_decode_c_19__n.BLIF N_161_i_2.BLIF N_161_i_3.BLIF a_decode_c_20__n.BLIF \ -N_161_i_4.BLIF N_233_i_1.BLIF a_decode_c_21__n.BLIF N_233_i_2.BLIF \ -N_180_i_1.BLIF a_decode_c_22__n.BLIF N_180_i_2.BLIF \ -pos_clk_un10_sm_amiga_i_1_n.BLIF a_decode_c_23__n.BLIF N_196_0_1.BLIF \ -N_188_i_1.BLIF a_c_0__n.BLIF un10_ciin_1.BLIF un10_ciin_2.BLIF a_c_1__n.BLIF \ -un10_ciin_3.BLIF un10_ciin_4.BLIF nEXP_SPACE_c.BLIF un10_ciin_5.BLIF \ -SM_AMIGA_i_7_.BLIF un10_ciin_6.BLIF pos_clk_size_dma_6_0__n.BLIF BERR_c.BLIF \ -un10_ciin_7.BLIF pos_clk_size_dma_6_1__n.BLIF un10_ciin_8.BLIF G_107.BLIF \ -BG_030_c.BLIF un10_ciin_9.BLIF G_108.BLIF un10_ciin_10.BLIF G_109.BLIF \ -BG_000DFFreg.BLIF un10_ciin_11.BLIF N_171_i_1.BLIF N_78.BLIF N_171_i_2.BLIF \ -N_79.BLIF BGACK_000_c.BLIF N_227_1.BLIF N_260.BLIF N_227_2.BLIF N_139.BLIF \ -CLK_030_c.BLIF N_227_3.BLIF N_141.BLIF un21_fpu_cs_1.BLIF N_165.BLIF \ -un21_berr_1_0.BLIF N_169.BLIF N_235_i_1.BLIF N_297.BLIF CLK_OSZI_c.BLIF \ -N_235_i_2.BLIF N_256_1.BLIF N_300.BLIF N_256_2.BLIF N_302.BLIF \ -CLK_OUT_INTreg.BLIF N_232_i_1.BLIF N_113.BLIF N_232_i_2.BLIF N_305.BLIF \ -N_219_1.BLIF N_155.BLIF FPU_SENSE_c.BLIF N_219_2.BLIF N_163.BLIF N_218_1.BLIF \ -N_166.BLIF IPL_030DFF_0_reg.BLIF N_218_2.BLIF N_171.BLIF N_347_1.BLIF \ -N_180.BLIF IPL_030DFF_1_reg.BLIF N_347_2.BLIF N_184.BLIF N_136_i_1.BLIF \ -N_191.BLIF IPL_030DFF_2_reg.BLIF N_146_i_1.BLIF N_199.BLIF N_142_i_1.BLIF \ -N_205.BLIF ipl_c_0__n.BLIF N_234_i_1.BLIF N_306.BLIF N_302_0_1.BLIF N_215.BLIF \ -ipl_c_1__n.BLIF N_63_i_1.BLIF N_221.BLIF N_154_i_1.BLIF N_227.BLIF \ -ipl_c_2__n.BLIF N_152_i_1.BLIF N_230.BLIF N_148_i_1.BLIF N_319.BLIF \ -N_144_i_1.BLIF N_320.BLIF DTACK_c.BLIF N_140_i_1.BLIF N_267.BLIF \ -pos_clk_un6_bg_030_1_n.BLIF N_324.BLIF N_230_1.BLIF N_269.BLIF N_221_1.BLIF \ -N_270.BLIF VPA_c.BLIF N_215_1.BLIF N_327.BLIF N_306_1.BLIF N_273.BLIF \ -pos_clk_ipl_1_n.BLIF N_275.BLIF RST_c.BLIF ipl_030_0_2__un3_n.BLIF N_290.BLIF \ -ipl_030_0_2__un1_n.BLIF N_292.BLIF ipl_030_0_2__un0_n.BLIF N_295.BLIF \ -RW_c.BLIF ipl_030_0_1__un3_n.BLIF N_332.BLIF ipl_030_0_1__un1_n.BLIF \ -N_333.BLIF fc_c_0__n.BLIF ipl_030_0_1__un0_n.BLIF N_334.BLIF \ -ipl_030_0_0__un3_n.BLIF N_335.BLIF fc_c_1__n.BLIF ipl_030_0_0__un1_n.BLIF \ -N_336.BLIF ipl_030_0_0__un0_n.BLIF N_338.BLIF cpu_est_0_3__un3_n.BLIF \ -N_339.BLIF AMIGA_BUS_DATA_DIR_c.BLIF cpu_est_0_3__un1_n.BLIF N_350.BLIF \ -cpu_est_0_3__un0_n.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.BLIF vma_int_0_un3_n.BLIF \ -N_161.BLIF vma_int_0_un1_n.BLIF N_213.BLIF vma_int_0_un0_n.BLIF N_214.BLIF \ -VPA_c_i.BLIF cpu_est_0_1__un3_n.BLIF N_197.BLIF N_52_0.BLIF \ -cpu_est_0_1__un1_n.BLIF N_159.BLIF DTACK_c_i.BLIF cpu_est_0_1__un0_n.BLIF \ -N_326.BLIF N_53_0.BLIF cpu_est_0_2__un3_n.BLIF un21_berr_1.BLIF \ -ipl_c_i_0__n.BLIF cpu_est_0_2__un1_n.BLIF N_181.BLIF N_49_0.BLIF \ -cpu_est_0_2__un0_n.BLIF pos_clk_un21_bgack_030_int_i_i_a2_i_x2.BLIF \ -ipl_c_i_1__n.BLIF ds_000_dma_0_un3_n.BLIF un1_DS_000_ENABLE_0_sqmuxa.BLIF \ -N_50_0.BLIF ds_000_dma_0_un1_n.BLIF N_349.BLIF ipl_c_i_2__n.BLIF \ -ds_000_dma_0_un0_n.BLIF N_345.BLIF N_51_0.BLIF as_000_dma_0_un3_n.BLIF \ -N_229.BLIF N_25_i.BLIF as_000_dma_0_un1_n.BLIF N_14.BLIF N_28_0.BLIF \ -as_000_dma_0_un0_n.BLIF N_21.BLIF N_26_i.BLIF bgack_030_int_0_un3_n.BLIF \ -N_3.BLIF N_29_0.BLIF bgack_030_int_0_un1_n.BLIF N_301.BLIF N_27_i.BLIF \ -bgack_030_int_0_un0_n.BLIF N_4.BLIF N_30_0.BLIF ds_000_enable_0_un3_n.BLIF \ -N_303.BLIF N_222_i.BLIF ds_000_enable_0_un1_n.BLIF N_8.BLIF N_223_i.BLIF \ -ds_000_enable_0_un0_n.BLIF pos_clk_un6_bgack_000_n.BLIF N_192_i.BLIF \ -uds_000_int_0_un3_n.BLIF N_9.BLIF N_231_i.BLIF uds_000_int_0_un1_n.BLIF \ -N_65.BLIF N_237_i.BLIF uds_000_int_0_un0_n.BLIF N_217.BLIF \ -lds_000_int_0_un3_n.BLIF N_216.BLIF N_342_i.BLIF lds_000_int_0_un1_n.BLIF \ -N_248.BLIF N_341_i.BLIF lds_000_int_0_un0_n.BLIF N_198.BLIF \ -un1_amiga_bus_enable_dma_high_i_m2_0__un3_n.BLIF N_291.BLIF N_160_0.BLIF \ -un1_amiga_bus_enable_dma_high_i_m2_0__un1_n.BLIF N_353.BLIF N_164_i.BLIF \ -un1_amiga_bus_enable_dma_high_i_m2_0__un0_n.BLIF N_256.BLIF VMA_INT_i.BLIF \ -amiga_bus_enable_dma_high_0_un3_n.BLIF N_18.BLIF N_347_i.BLIF \ -amiga_bus_enable_dma_high_0_un1_n.BLIF pos_clk_un9_clk_000_pe_n.BLIF \ -N_348_i.BLIF amiga_bus_enable_dma_high_0_un0_n.BLIF cpu_est_2_1__n.BLIF \ -N_188_i.BLIF bg_000_0_un3_n.BLIF cpu_est_2_2__n.BLIF N_245_0.BLIF \ -bg_000_0_un1_n.BLIF N_209.BLIF N_194_0.BLIF bg_000_0_un0_n.BLIF N_211.BLIF \ -N_196_0.BLIF size_dma_0_0__un3_n.BLIF N_220.BLIF size_dma_0_0__un1_n.BLIF \ -N_222.BLIF N_211_i.BLIF size_dma_0_0__un0_n.BLIF N_162.BLIF N_209_i.BLIF \ -size_dma_0_1__un3_n.BLIF N_224.BLIF N_306_i.BLIF size_dma_0_1__un1_n.BLIF \ -N_193.BLIF N_193_0.BLIF size_dma_0_1__un0_n.BLIF N_225.BLIF N_190_0.BLIF \ -as_030_000_sync_0_un3_n.BLIF N_190.BLIF N_183_i.BLIF \ -as_030_000_sync_0_un1_n.BLIF N_346.BLIF N_162_i.BLIF \ -as_030_000_sync_0_un0_n.BLIF N_352.BLIF N_346_i.BLIF rw_000_int_0_un3_n.BLIF \ -N_219.BLIF N_159_0.BLIF rw_000_int_0_un1_n.BLIF N_218.BLIF N_305_i.BLIF \ -rw_000_int_0_un0_n.BLIF N_183.BLIF N_210_i.BLIF rw_000_dma_0_un3_n.BLIF \ -N_196.BLIF N_225_i.BLIF rw_000_dma_0_un1_n.BLIF N_188.BLIF N_224_i.BLIF \ -rw_000_dma_0_un0_n.BLIF N_194.BLIF N_296_i.BLIF a0_dma_0_un3_n.BLIF N_347.BLIF \ -N_352_i.BLIF a0_dma_0_un1_n.BLIF N_348.BLIF cpu_est_2_0_2__n.BLIF \ -a0_dma_0_un0_n.BLIF N_160.BLIF N_220_i.BLIF \ -amiga_bus_enable_dma_low_0_un3_n.BLIF N_341.BLIF N_221_i.BLIF \ -amiga_bus_enable_dma_low_0_un1_n.BLIF N_342.BLIF cpu_est_2_0_1__n.BLIF \ -amiga_bus_enable_dma_low_0_un0_n.BLIF N_231.BLIF N_219_i.BLIF \ -a_decode_15__n.BLIF N_237.BLIF N_218_i.BLIF N_223.BLIF \ -pos_clk_un9_clk_000_pe_0_n.BLIF a_decode_14__n.BLIF N_27.BLIF \ -clk_000_d_i_2__n.BLIF N_26.BLIF N_157_i.BLIF a_decode_13__n.BLIF N_25.BLIF \ -N_18_i.BLIF un1_amiga_bus_enable_low_i.BLIF N_37_0.BLIF a_decode_12__n.BLIF \ -un21_fpu_cs_i.BLIF cpu_est_i_2__n.BLIF N_217_i.BLIF a_decode_11__n.BLIF \ -sm_amiga_i_0__n.BLIF N_216_i.BLIF sm_amiga_i_2__n.BLIF CLK_030_c_i.BLIF \ -a_decode_10__n.BLIF sm_amiga_i_1__n.BLIF N_198_0.BLIF cpu_est_i_0__n.BLIF \ -N_166_i.BLIF a_decode_9__n.BLIF VPA_D_i.BLIF N_155_i.BLIF DTACK_D0_i.BLIF \ -N_303_0.BLIF a_decode_8__n.BLIF AS_030_i.BLIF N_291_i.BLIF DSACK1_INT_i.BLIF \ -N_301_0.BLIF a_decode_7__n.BLIF cpu_est_i_3__n.BLIF N_256_i.BLIF \ -sm_amiga_i_3__n.BLIF N_248_i.BLIF a_decode_6__n.BLIF cpu_est_i_1__n.BLIF \ -AMIGA_BUS_DATA_DIR_c_0.BLIF clk_000_d_i_1__n.BLIF N_353_i.BLIF \ -a_decode_5__n.BLIF N_350_i_0.BLIF pos_clk_un6_bgack_000_0_n.BLIF \ -rst_dly_i_2__n.BLIF N_65_0.BLIF a_decode_4__n.BLIF nEXP_SPACE_i.BLIF \ -N_3_i.BLIF AS_000_i.BLIF N_45_0.BLIF a_decode_3__n.BLIF BGACK_030_INT_i.BLIF \ -N_4_i.BLIF sm_amiga_i_6__n.BLIF N_44_0.BLIF a_decode_2__n.BLIF \ -clk_000_d_i_0__n.BLIF N_8_i.BLIF RW_000_i.BLIF N_42_0.BLIF CLK_030_H_i.BLIF \ -UDS_000_INT_i.BLIF AS_000_DMA_i.BLIF un1_UDS_000_INT_0.BLIF \ -cycle_dma_i_0__n.BLIF LDS_000_INT_i.BLIF DS_000_DMA_i.BLIF \ -un1_LDS_000_INT_0.BLIF RESET_OUT_i.BLIF N_21_i.BLIF sm_amiga_i_4__n.BLIF \ -N_34_0.BLIF FPU_SENSE_i.BLIF N_14_i.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF \ -RW_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF \ -SIZE_1_.PIN.BLIF AHIGH_24_.PIN.BLIF AHIGH_25_.PIN.BLIF AHIGH_26_.PIN.BLIF \ -AHIGH_27_.PIN.BLIF AHIGH_28_.PIN.BLIF AHIGH_29_.PIN.BLIF AHIGH_30_.PIN.BLIF \ -AHIGH_31_.PIN.BLIF A_0_.PIN.BLIF BERR.PIN.BLIF RW.PIN.BLIF +AHIGH_25_.BLIF AHIGH_24_.BLIF A_0_.BLIF ipl_i_2__n.BLIF N_233_0.BLIF \ +ipl_i_1__n.BLIF N_360_i.BLIF ipl_i_0__n.BLIF N_191_i_i.BLIF a_i_1__n.BLIF \ +N_192_i_i.BLIF AS_000_DMA_i.BLIF AS_000_i.BLIF N_199_i.BLIF CLK_030_H_i.BLIF \ +N_204_i.BLIF AS_030_000_SYNC_i.BLIF inst_BGACK_030_INTreg.BLIF \ +AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF N_282_i.BLIF vcc_n_n.BLIF \ +cycle_dma_i_0__n.BLIF N_278_i.BLIF inst_VMA_INTreg.BLIF ahigh_i_30__n.BLIF \ +N_186_i.BLIF gnd_n_n.BLIF ahigh_i_31__n.BLIF N_185_i.BLIF \ +un1_amiga_bus_enable_low.BLIF ahigh_i_28__n.BLIF CLK_030_c_i.BLIF \ +un7_as_030.BLIF ahigh_i_29__n.BLIF N_184_0.BLIF un1_LDS_000_INT.BLIF \ +ahigh_i_26__n.BLIF N_179_0.BLIF un1_UDS_000_INT.BLIF ahigh_i_27__n.BLIF \ +N_251_i.BLIF un10_ciin.BLIF ahigh_i_24__n.BLIF LDS_000_c_i.BLIF \ +un21_fpu_cs.BLIF ahigh_i_25__n.BLIF UDS_000_c_i.BLIF un21_berr.BLIF \ +N_172_i.BLIF un6_ds_030.BLIF pos_clk_un21_bgack_030_int_i_0_0_n.BLIF \ +cpu_est_2_.BLIF N_163_i.BLIF cpu_est_3_.BLIF clk_000_d_i_3__n.BLIF \ +cpu_est_0_.BLIF N_115_i.BLIF N_350_i.BLIF cpu_est_1_.BLIF N_114_i.BLIF \ +un1_rw_i.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF un6_ds_030_i.BLIF \ +N_126_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF DS_000_DMA_i.BLIF N_313_i.BLIF \ +inst_AS_030_D0.BLIF N_132_i.BLIF N_231_i.BLIF inst_AS_030_000_SYNC.BLIF \ +N_133_i.BLIF N_291_i.BLIF inst_BGACK_030_INT_D.BLIF un7_as_030_i.BLIF \ +inst_AS_000_DMA.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF N_288_i.BLIF \ +inst_DS_000_DMA.BLIF AS_030_c.BLIF CYCLE_DMA_0_.BLIF N_287_i.BLIF \ +CYCLE_DMA_1_.BLIF AS_000_c.BLIF N_340_i.BLIF inst_VPA_D.BLIF CLK_000_D_3_.BLIF \ +RW_000_c.BLIF N_284_i.BLIF inst_DTACK_D0.BLIF inst_RESET_OUT.BLIF N_275_i.BLIF \ +CLK_000_D_1_.BLIF UDS_000_c.BLIF pos_clk_size_dma_6_0_1__n.BLIF \ +CLK_000_D_0_.BLIF N_268_i.BLIF inst_CLK_OUT_PRE_50.BLIF LDS_000_c.BLIF \ +pos_clk_size_dma_6_0_0__n.BLIF inst_CLK_OUT_PRE_D.BLIF N_265_i.BLIF \ +IPL_D0_0_.BLIF size_c_0__n.BLIF N_267_i.BLIF IPL_D0_1_.BLIF IPL_D0_2_.BLIF \ +size_c_1__n.BLIF N_337_i.BLIF CLK_000_D_2_.BLIF N_338_i.BLIF CLK_000_D_4_.BLIF \ +ahigh_c_24__n.BLIF N_55_0.BLIF inst_LDS_000_INT.BLIF un1_as_000_i.BLIF \ +inst_DS_000_ENABLE.BLIF ahigh_c_25__n.BLIF N_245_0.BLIF inst_UDS_000_INT.BLIF \ +N_229_i.BLIF pos_clk_un9_bg_030_n.BLIF ahigh_c_26__n.BLIF SM_AMIGA_6_.BLIF \ +N_227_i.BLIF SM_AMIGA_4_.BLIF ahigh_c_27__n.BLIF SM_AMIGA_1_.BLIF N_226_i.BLIF \ +SM_AMIGA_0_.BLIF ahigh_c_28__n.BLIF N_246_0.BLIF SIZE_DMA_0_.BLIF N_332_i.BLIF \ +SIZE_DMA_1_.BLIF ahigh_c_29__n.BLIF pos_clk_ds_000_dma_4_0_n.BLIF \ +inst_RW_000_INT.BLIF N_48_0.BLIF inst_RW_000_DMA.BLIF ahigh_c_30__n.BLIF \ +pos_clk_rw_000_dma_3_0_n.BLIF RST_DLY_0_.BLIF N_218_i.BLIF RST_DLY_1_.BLIF \ +ahigh_c_31__n.BLIF RST_DLY_2_.BLIF inst_A0_DMA.BLIF un10_ciin_i.BLIF \ +pos_clk_a0_dma_3_n.BLIF N_62_0.BLIF pos_clk_rw_000_dma_3_n.BLIF N_215_i.BLIF \ +inst_CLK_030_H.BLIF N_216_i.BLIF inst_DSACK1_INT.BLIF \ +un10_amiga_bus_enable_high_i.BLIF inst_AS_000_INT.BLIF N_214_i.BLIF \ +SM_AMIGA_5_.BLIF N_310_0.BLIF SM_AMIGA_3_.BLIF N_24_i.BLIF SM_AMIGA_2_.BLIF \ +N_33_0.BLIF pos_clk_ds_000_dma_4_n.BLIF N_23_i.BLIF N_3.BLIF N_32_0.BLIF \ +N_4.BLIF N_22_i.BLIF N_31_0.BLIF N_3_i.BLIF N_45_0.BLIF N_4_i.BLIF N_44_0.BLIF \ +N_15.BLIF N_15_i.BLIF N_19.BLIF N_40_0.BLIF N_20.BLIF N_19_i.BLIF N_22.BLIF \ +N_36_0.BLIF N_23.BLIF N_20_i.BLIF N_24.BLIF N_35_0.BLIF N_25.BLIF N_25_i.BLIF \ +N_26.BLIF N_30_0.BLIF N_27.BLIF N_26_i.BLIF N_29_0.BLIF N_27_i.BLIF \ +a_decode_c_16__n.BLIF N_28_0.BLIF BG_030_c_i.BLIF a_decode_c_17__n.BLIF \ +pos_clk_un9_bg_030_0_n.BLIF N_235_i_1.BLIF a_decode_c_18__n.BLIF \ +N_235_i_2.BLIF N_156_i_1.BLIF a_decode_c_19__n.BLIF N_156_i_2.BLIF \ +N_156_i_3.BLIF a_decode_c_20__n.BLIF N_156_i_4.BLIF \ +pos_clk_un10_sm_amiga_i_1_n.BLIF a_decode_c_21__n.BLIF N_176_i_1.BLIF \ +un10_ciin_1.BLIF a_decode_c_22__n.BLIF un10_ciin_2.BLIF un10_ciin_3.BLIF \ +a_decode_c_23__n.BLIF un10_ciin_4.BLIF un10_ciin_5.BLIF a_c_0__n.BLIF \ +un10_ciin_6.BLIF un10_ciin_7.BLIF a_c_1__n.BLIF un10_ciin_8.BLIF \ +SM_AMIGA_i_7_.BLIF un10_ciin_9.BLIF pos_clk_size_dma_6_0__n.BLIF \ +nEXP_SPACE_c.BLIF un10_ciin_10.BLIF pos_clk_size_dma_6_1__n.BLIF \ +un10_ciin_11.BLIF N_199.BLIF BERR_c.BLIF N_163_i_1.BLIF \ +pos_clk_un21_bgack_030_int_i_0_n.BLIF N_163_i_2.BLIF N_231.BLIF BG_030_c.BLIF \ +pos_clk_un21_bgack_030_int_i_0_0_1_n.BLIF N_233.BLIF \ +pos_clk_un21_bgack_030_int_i_0_0_2_n.BLIF N_111.BLIF BG_000DFFreg.BLIF \ +N_138_i_1.BLIF N_112.BLIF N_138_i_2.BLIF N_113.BLIF N_59_i_1.BLIF N_114.BLIF \ +BGACK_000_c.BLIF N_59_i_2.BLIF N_115.BLIF N_233_0_1.BLIF N_245.BLIF \ +CLK_030_c.BLIF N_233_0_2.BLIF N_246.BLIF N_214_1.BLIF N_62.BLIF N_214_2.BLIF \ +N_214_3.BLIF N_132.BLIF CLK_OSZI_c.BLIF un21_fpu_cs_1.BLIF N_133.BLIF \ +un21_berr_1_0.BLIF N_310.BLIF N_182_0_1.BLIF N_126.BLIF CLK_OUT_INTreg.BLIF \ +N_234_i_1.BLIF N_149.BLIF N_234_i_2.BLIF N_150.BLIF N_206_1.BLIF N_158.BLIF \ +FPU_SENSE_c.BLIF N_206_2.BLIF N_160.BLIF N_205_1.BLIF N_163.BLIF \ +IPL_030DFF_0_reg.BLIF N_205_2.BLIF N_172.BLIF N_352_1.BLIF N_179.BLIF \ +IPL_030DFF_1_reg.BLIF N_352_2.BLIF N_184.BLIF N_231_i_1.BLIF N_185.BLIF \ +IPL_030DFF_2_reg.BLIF N_152_i_1.BLIF N_196.BLIF N_144_i_1.BLIF N_203.BLIF \ +ipl_c_0__n.BLIF N_142_i_1.BLIF N_204.BLIF N_312_i_1.BLIF N_209.BLIF \ +ipl_c_1__n.BLIF N_236_i_1.BLIF N_214.BLIF N_148_i_1.BLIF N_215.BLIF \ +ipl_c_2__n.BLIF N_136_i_1.BLIF N_216.BLIF N_246_0_1.BLIF N_218.BLIF \ +N_249_i_1.BLIF N_224.BLIF DTACK_c.BLIF N_57_i_1.BLIF N_332.BLIF N_338_1.BLIF \ +N_226.BLIF N_224_1.BLIF N_227.BLIF N_216_1.BLIF N_229.BLIF VPA_c.BLIF \ +N_209_1.BLIF N_337.BLIF N_203_1.BLIF N_338.BLIF N_196_1.BLIF N_265.BLIF \ +RST_c.BLIF cpu_est_0_3__un3_n.BLIF N_267.BLIF cpu_est_0_3__un1_n.BLIF \ +N_268.BLIF cpu_est_0_3__un0_n.BLIF N_275.BLIF RW_c.BLIF \ +rw_000_int_0_un3_n.BLIF N_278.BLIF rw_000_int_0_un1_n.BLIF N_282.BLIF \ +fc_c_0__n.BLIF rw_000_int_0_un0_n.BLIF N_284.BLIF vma_int_0_un3_n.BLIF \ +N_340.BLIF fc_c_1__n.BLIF vma_int_0_un1_n.BLIF N_287.BLIF vma_int_0_un0_n.BLIF \ +N_288.BLIF cpu_est_0_1__un3_n.BLIF N_291.BLIF AMIGA_BUS_DATA_DIR_c.BLIF \ +cpu_est_0_1__un1_n.BLIF N_293.BLIF cpu_est_0_1__un0_n.BLIF N_350.BLIF \ +cpu_est_0_2__un3_n.BLIF N_355.BLIF cpu_est_0_2__un1_n.BLIF \ +pos_clk_un21_bgack_030_int_i_0_o3_0_x2.BLIF cpu_est_0_2__un0_n.BLIF \ +pos_clk_un1_ipl_i_0_x2.BLIF N_16_i.BLIF uds_000_int_0_un3_n.BLIF \ +pos_clk_un1_ipl_i_0_x2_0.BLIF N_39_0.BLIF uds_000_int_0_un1_n.BLIF \ +pos_clk_un1_ipl_i_0_x2_1.BLIF VPA_c_i.BLIF uds_000_int_0_un0_n.BLIF \ +pos_clk_CYCLE_DMA_5_1_i_0_x2.BLIF N_52_0.BLIF lds_000_int_0_un3_n.BLIF \ +N_156.BLIF DTACK_c_i.BLIF lds_000_int_0_un1_n.BLIF N_201.BLIF N_53_0.BLIF \ +lds_000_int_0_un0_n.BLIF N_202.BLIF N_210_i.BLIF bgack_030_int_0_un3_n.BLIF \ +N_154.BLIF N_211_i.BLIF bgack_030_int_0_un1_n.BLIF un21_berr_1.BLIF \ +N_189_i.BLIF bgack_030_int_0_un0_n.BLIF N_174.BLIF \ +un1_SM_AMIGA_0_sqmuxa_1_0.BLIF ds_000_enable_0_un3_n.BLIF N_223.BLIF \ +RW_c_i.BLIF ds_000_enable_0_un1_n.BLIF N_221.BLIF N_311_0.BLIF \ +ds_000_enable_0_un0_n.BLIF N_222.BLIF N_336_i.BLIF size_dma_0_0__un3_n.BLIF \ +N_219.BLIF N_244_i.BLIF size_dma_0_0__un1_n.BLIF N_220.BLIF \ +size_dma_0_0__un0_n.BLIF pos_clk_un6_bgack_000_n.BLIF N_314_0.BLIF \ +size_dma_0_1__un3_n.BLIF N_359.BLIF N_159_i.BLIF size_dma_0_1__un1_n.BLIF \ +N_8.BLIF VMA_INT_i.BLIF size_dma_0_1__un0_n.BLIF N_14.BLIF N_352_i.BLIF \ +ipl_030_0_0__un3_n.BLIF N_21.BLIF N_353_i.BLIF ipl_030_0_0__un1_n.BLIF \ +N_9.BLIF N_293_i.BLIF ipl_030_0_0__un0_n.BLIF un1_DS_000_ENABLE_0_sqmuxa.BLIF \ +N_175_i.BLIF ipl_030_0_1__un3_n.BLIF N_66.BLIF N_176_i.BLIF \ +ipl_030_0_1__un1_n.BLIF N_171.BLIF ipl_030_0_1__un0_n.BLIF N_354.BLIF \ +N_198_i.BLIF ipl_030_0_2__un3_n.BLIF N_18.BLIF N_197_i.BLIF \ +ipl_030_0_2__un1_n.BLIF pos_clk_un9_clk_000_pe_n.BLIF N_196_i.BLIF \ +ipl_030_0_2__un0_n.BLIF cpu_est_2_1__n.BLIF N_183_0.BLIF a0_dma_0_un3_n.BLIF \ +cpu_est_2_2__n.BLIF N_182_0.BLIF a0_dma_0_un1_n.BLIF N_197.BLIF N_180_0.BLIF \ +a0_dma_0_un0_n.BLIF N_198.BLIF N_178_0.BLIF \ +amiga_bus_enable_dma_low_0_un3_n.BLIF N_208.BLIF N_82_i.BLIF \ +amiga_bus_enable_dma_low_0_un1_n.BLIF N_210.BLIF N_315_i.BLIF \ +amiga_bus_enable_dma_low_0_un0_n.BLIF N_315.BLIF N_351_i.BLIF \ +amiga_bus_enable_dma_high_0_un3_n.BLIF N_212.BLIF N_154_0.BLIF \ +amiga_bus_enable_dma_high_0_un1_n.BLIF N_180.BLIF N_149_i.BLIF \ +amiga_bus_enable_dma_high_0_un0_n.BLIF N_213.BLIF N_207_i.BLIF \ +bg_000_0_un3_n.BLIF N_178.BLIF N_228_i.BLIF bg_000_0_un1_n.BLIF N_228.BLIF \ +bg_000_0_un0_n.BLIF N_182.BLIF N_213_i.BLIF ds_000_dma_0_un3_n.BLIF N_176.BLIF \ +N_212_i.BLIF ds_000_dma_0_un1_n.BLIF N_183.BLIF N_309_i.BLIF \ +ds_000_dma_0_un0_n.BLIF N_351.BLIF N_357_i.BLIF as_000_dma_0_un3_n.BLIF \ +N_357.BLIF cpu_est_2_0_2__n.BLIF as_000_dma_0_un1_n.BLIF N_206.BLIF \ +N_208_i.BLIF as_000_dma_0_un0_n.BLIF N_205.BLIF N_209_i.BLIF \ +as_030_000_sync_0_un3_n.BLIF N_352.BLIF cpu_est_2_0_1__n.BLIF \ +as_030_000_sync_0_un1_n.BLIF N_353.BLIF N_206_i.BLIF \ +as_030_000_sync_0_un0_n.BLIF N_314.BLIF N_205_i.BLIF rw_000_dma_0_un3_n.BLIF \ +N_244.BLIF pos_clk_un9_clk_000_pe_0_n.BLIF rw_000_dma_0_un1_n.BLIF N_336.BLIF \ +N_18_i.BLIF rw_000_dma_0_un0_n.BLIF N_311.BLIF N_37_0.BLIF a_decode_15__n.BLIF \ +un1_SM_AMIGA_0_sqmuxa_1.BLIF N_171_i.BLIF N_211.BLIF N_354_i.BLIF \ +a_decode_14__n.BLIF N_16.BLIF un1_DS_000_ENABLE_0_sqmuxa_0.BLIF \ +un1_amiga_bus_enable_low_i.BLIF N_66_0.BLIF a_decode_13__n.BLIF \ +un21_fpu_cs_i.BLIF UDS_000_INT_i.BLIF cpu_est_i_2__n.BLIF \ +un1_UDS_000_INT_0.BLIF a_decode_12__n.BLIF cpu_est_i_0__n.BLIF \ +LDS_000_INT_i.BLIF VPA_D_i.BLIF un1_LDS_000_INT_0.BLIF a_decode_11__n.BLIF \ +DTACK_D0_i.BLIF N_21_i.BLIF cpu_est_i_3__n.BLIF N_34_0.BLIF \ +a_decode_10__n.BLIF sm_amiga_i_i_7__n.BLIF N_14_i.BLIF sm_amiga_i_5__n.BLIF \ +N_41_0.BLIF a_decode_9__n.BLIF sm_amiga_i_3__n.BLIF N_8_i.BLIF \ +cpu_est_i_1__n.BLIF N_42_0.BLIF a_decode_8__n.BLIF clk_000_d_i_1__n.BLIF \ +a_c_i_0__n.BLIF N_355_i_0.BLIF size_c_i_1__n.BLIF a_decode_7__n.BLIF \ +sm_amiga_i_4__n.BLIF pos_clk_un10_sm_amiga_i_n.BLIF sm_amiga_i_2__n.BLIF \ +N_359_i.BLIF a_decode_6__n.BLIF rst_dly_i_0__n.BLIF \ +pos_clk_un6_bgack_000_0_n.BLIF rst_dly_i_2__n.BLIF N_220_i.BLIF \ +a_decode_5__n.BLIF a_decode_i_19__n.BLIF N_219_i.BLIF a_decode_i_18__n.BLIF \ +a_decode_4__n.BLIF a_decode_i_16__n.BLIF N_222_i.BLIF RW_000_i.BLIF \ +N_221_i.BLIF a_decode_3__n.BLIF sm_amiga_i_0__n.BLIF AS_030_i.BLIF \ +N_223_i.BLIF a_decode_2__n.BLIF AS_000_INT_i.BLIF N_224_i.BLIF \ +DSACK1_INT_i.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF clk_000_d_i_0__n.BLIF \ +N_150_i.BLIF sm_amiga_i_6__n.BLIF N_156_i.BLIF sm_amiga_i_1__n.BLIF \ +N_160_i.BLIF FPU_SENSE_i.BLIF N_174_i.BLIF rst_dly_i_1__n.BLIF N_158_i.BLIF \ +AS_030_D0_i.BLIF N_201_i.BLIF BGACK_030_INT_i.BLIF N_202_i.BLIF \ +nEXP_SPACE_i.BLIF N_203_i.BLIF RESET_OUT_i.BLIF AS_030.PIN.BLIF \ +AS_000.PIN.BLIF RW_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF \ +SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF AHIGH_24_.PIN.BLIF AHIGH_25_.PIN.BLIF \ +AHIGH_26_.PIN.BLIF AHIGH_27_.PIN.BLIF AHIGH_28_.PIN.BLIF AHIGH_29_.PIN.BLIF \ +AHIGH_30_.PIN.BLIF AHIGH_31_.PIN.BLIF A_0_.PIN.BLIF BERR.PIN.BLIF RW.PIN.BLIF .outputs IPL_030_2_ DS_030 BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 \ AVEC E VMA RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ -AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_i_7_.D \ +AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ IPL_D0_0_.D IPL_D0_0_.C \ +IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C SM_AMIGA_i_7_.D \ SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_5_.D SM_AMIGA_5_.C \ SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_2_.D \ SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C \ +cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C \ cpu_est_3_.D cpu_est_3_.C IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C \ IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D IPL_030DFF_2_reg.C \ -IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C \ -CLK_000_D_0_.D CLK_000_D_0_.C CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_2_.D \ -CLK_000_D_2_.C CLK_000_D_3_.D CLK_000_D_3_.C CLK_000_D_4_.D CLK_000_D_4_.C \ -CLK_000_D_5_.D CLK_000_D_5_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D \ +RST_DLY_2_.D RST_DLY_2_.C CLK_000_D_0_.D CLK_000_D_0_.C CLK_000_D_1_.D \ +CLK_000_D_1_.C CLK_000_D_2_.D CLK_000_D_2_.C CLK_000_D_3_.D CLK_000_D_3_.C \ +CLK_000_D_4_.D CLK_000_D_4_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D \ CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C \ -cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C \ -RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C \ -inst_DS_000_DMA.D inst_DS_000_DMA.C inst_DSACK1_INT.D inst_DSACK1_INT.C \ -inst_AS_000_INT.D inst_AS_000_INT.C inst_AS_030_D0.D inst_AS_030_D0.C \ -inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D inst_DTACK_D0.C inst_CLK_030_H.D \ -inst_CLK_030_H.C inst_RESET_OUT.D inst_RESET_OUT.C inst_DS_000_ENABLE.D \ -inst_DS_000_ENABLE.C BG_000DFFreg.D BG_000DFFreg.C \ -inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.C \ -inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AMIGA_BUS_ENABLE_DMA_LOW.C \ -inst_UDS_000_INT.D inst_UDS_000_INT.C inst_A0_DMA.D inst_A0_DMA.C \ -inst_RW_000_DMA.D inst_RW_000_DMA.C inst_VMA_INTreg.D inst_VMA_INTreg.C \ -inst_RW_000_INT.D inst_RW_000_INT.C inst_AS_030_000_SYNC.D \ -inst_AS_030_000_SYNC.C inst_LDS_000_INT.D inst_LDS_000_INT.C \ -inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_AS_000_DMA.D \ -inst_AS_000_DMA.C inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C \ -CLK_OUT_INTreg.D CLK_OUT_INTreg.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C \ -inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C SIZE_1_ AHIGH_31_ AS_030 AS_000 \ -RW_000 UDS_000 LDS_000 BERR RW SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ \ -AHIGH_26_ AHIGH_25_ AHIGH_24_ A_0_ rst_dly_i_1__n N_41_0 sm_amiga_i_5__n \ -a_c_i_0__n rst_dly_i_0__n size_c_i_1__n sm_amiga_i_i_7__n \ -pos_clk_un10_sm_amiga_i_n AS_030_D0_i un1_as_000_i AS_000_INT_i un10_ciin_i \ -a_i_1__n N_260_0 a_decode_i_16__n N_229_i a_decode_i_18__n N_230_i vcc_n_n \ -a_decode_i_19__n N_298_0 ahigh_i_30__n N_48_0 gnd_n_n ahigh_i_31__n N_299_i \ -un1_amiga_bus_enable_low ahigh_i_28__n N_345_i un7_as_030 ahigh_i_29__n \ -N_349_i un1_UDS_000_INT ahigh_i_26__n un1_DS_000_ENABLE_0_sqmuxa_i \ -un1_LDS_000_INT ahigh_i_27__n N_180_i un1_SM_AMIGA_0_sqmuxa_1 ahigh_i_24__n \ -N_181_i un10_ciin ahigh_i_25__n N_326_i un21_fpu_cs N_206_i un21_berr N_207_i \ -N_186_i un6_ds_030 N_208_i N_163_i N_197_0 N_79_i N_213_i N_78_i N_214_i \ -un6_ds_030_i N_215_i N_165_i N_169_i N_199_i un7_as_030_i N_191_0 \ -AMIGA_BUS_ENABLE_DMA_LOW_i N_275_i AS_030_c N_187_0 LDS_000_c_i AS_000_c \ -UDS_000_c_i N_184_i RW_000_c clk_000_d_i_4__n N_171_i AS_030_000_SYNC_i \ -UDS_000_c N_161_i LDS_000_c N_113_0 N_338_i size_c_0__n N_339_i size_c_1__n \ -N_335_i N_336_i ahigh_c_24__n N_334_i ahigh_c_25__n pos_clk_size_dma_6_0_1__n \ -pos_clk_un6_bg_030_n N_333_i ahigh_c_26__n pos_clk_size_dma_6_0_0__n \ -pos_clk_ipl_n N_295_i ahigh_c_27__n N_332_i ahigh_c_28__n N_292_i N_302_0 \ -pos_clk_un9_bg_030_n ahigh_c_29__n N_300_0 N_290_i ahigh_c_30__n N_273_i \ -ahigh_c_31__n N_327_i N_270_i N_269_i N_267_i pos_clk_a0_dma_3_n N_324_i \ -pos_clk_rw_000_int_5_n un1_SM_AMIGA_0_sqmuxa_1_0 N_319_i N_320_i RW_c_i \ -pos_clk_rw_000_int_5_0_n N_227_i N_297_0 N_15_i N_40_0 N_16_i N_15 N_39_0 N_16 \ -N_19_i N_19 N_36_0 N_20 N_20_i N_22 N_35_0 N_23 N_22_i N_24 N_33_0 N_23_i \ -N_32_0 a_decode_c_16__n N_24_i N_31_0 a_decode_c_17__n BG_030_c_i \ -pos_clk_un6_bg_030_i_n a_decode_c_18__n pos_clk_un9_bg_030_0_n N_161_i_1 \ -a_decode_c_19__n N_161_i_2 N_161_i_3 a_decode_c_20__n N_161_i_4 N_233_i_1 \ -a_decode_c_21__n N_233_i_2 N_180_i_1 a_decode_c_22__n N_180_i_2 \ -pos_clk_un10_sm_amiga_i_1_n a_decode_c_23__n N_196_0_1 N_188_i_1 a_c_0__n \ -un10_ciin_1 un10_ciin_2 a_c_1__n un10_ciin_3 un10_ciin_4 nEXP_SPACE_c \ -un10_ciin_5 un10_ciin_6 pos_clk_size_dma_6_0__n BERR_c un10_ciin_7 \ -pos_clk_size_dma_6_1__n un10_ciin_8 BG_030_c un10_ciin_9 un10_ciin_10 \ -un10_ciin_11 N_171_i_1 N_78 N_171_i_2 N_79 BGACK_000_c N_227_1 N_260 N_227_2 \ -N_139 CLK_030_c N_227_3 N_141 un21_fpu_cs_1 N_165 un21_berr_1_0 N_169 \ -N_235_i_1 N_297 CLK_OSZI_c N_235_i_2 N_256_1 N_300 N_256_2 N_302 N_232_i_1 \ -N_113 N_232_i_2 N_305 N_219_1 N_155 FPU_SENSE_c N_219_2 N_163 N_218_1 N_166 \ -N_218_2 N_171 N_347_1 N_180 N_347_2 N_184 N_136_i_1 N_191 N_146_i_1 N_199 \ -N_142_i_1 N_205 ipl_c_0__n N_234_i_1 N_306 N_302_0_1 N_215 ipl_c_1__n N_63_i_1 \ -N_221 N_154_i_1 N_227 ipl_c_2__n N_152_i_1 N_230 N_148_i_1 N_319 N_144_i_1 \ -N_320 DTACK_c N_140_i_1 N_267 pos_clk_un6_bg_030_1_n N_324 N_230_1 N_269 \ -N_221_1 N_270 VPA_c N_215_1 N_327 N_306_1 N_273 pos_clk_ipl_1_n N_275 RST_c \ -ipl_030_0_2__un3_n N_290 ipl_030_0_2__un1_n N_292 ipl_030_0_2__un0_n N_295 \ -RW_c ipl_030_0_1__un3_n N_332 ipl_030_0_1__un1_n N_333 fc_c_0__n \ -ipl_030_0_1__un0_n N_334 ipl_030_0_0__un3_n N_335 fc_c_1__n ipl_030_0_0__un1_n \ -N_336 ipl_030_0_0__un0_n N_338 cpu_est_0_3__un3_n N_339 AMIGA_BUS_DATA_DIR_c \ -cpu_est_0_3__un1_n N_350 cpu_est_0_3__un0_n vma_int_0_un3_n N_161 \ -vma_int_0_un1_n N_213 vma_int_0_un0_n N_214 VPA_c_i cpu_est_0_1__un3_n N_197 \ -N_52_0 cpu_est_0_1__un1_n N_159 DTACK_c_i cpu_est_0_1__un0_n N_326 N_53_0 \ -cpu_est_0_2__un3_n un21_berr_1 ipl_c_i_0__n cpu_est_0_2__un1_n N_181 N_49_0 \ -cpu_est_0_2__un0_n ipl_c_i_1__n ds_000_dma_0_un3_n un1_DS_000_ENABLE_0_sqmuxa \ -N_50_0 ds_000_dma_0_un1_n N_349 ipl_c_i_2__n ds_000_dma_0_un0_n N_345 N_51_0 \ -as_000_dma_0_un3_n N_229 N_25_i as_000_dma_0_un1_n N_14 N_28_0 \ -as_000_dma_0_un0_n N_21 N_26_i bgack_030_int_0_un3_n N_3 N_29_0 \ -bgack_030_int_0_un1_n N_301 N_27_i bgack_030_int_0_un0_n N_4 N_30_0 \ -ds_000_enable_0_un3_n N_303 N_222_i ds_000_enable_0_un1_n N_8 N_223_i \ -ds_000_enable_0_un0_n pos_clk_un6_bgack_000_n N_192_i uds_000_int_0_un3_n N_9 \ -N_231_i uds_000_int_0_un1_n N_65 N_237_i uds_000_int_0_un0_n N_217 \ -lds_000_int_0_un3_n N_216 N_342_i lds_000_int_0_un1_n N_248 N_341_i \ -lds_000_int_0_un0_n N_198 un1_amiga_bus_enable_dma_high_i_m2_0__un3_n N_291 \ -N_160_0 un1_amiga_bus_enable_dma_high_i_m2_0__un1_n N_353 N_164_i \ -un1_amiga_bus_enable_dma_high_i_m2_0__un0_n N_256 VMA_INT_i \ -amiga_bus_enable_dma_high_0_un3_n N_18 N_347_i \ -amiga_bus_enable_dma_high_0_un1_n pos_clk_un9_clk_000_pe_n N_348_i \ -amiga_bus_enable_dma_high_0_un0_n cpu_est_2_1__n N_188_i bg_000_0_un3_n \ -cpu_est_2_2__n N_245_0 bg_000_0_un1_n N_209 N_194_0 bg_000_0_un0_n N_211 \ -N_196_0 size_dma_0_0__un3_n N_220 size_dma_0_0__un1_n N_222 N_211_i \ -size_dma_0_0__un0_n N_162 N_209_i size_dma_0_1__un3_n N_224 N_306_i \ -size_dma_0_1__un1_n N_193 N_193_0 size_dma_0_1__un0_n N_225 N_190_0 \ -as_030_000_sync_0_un3_n N_190 N_183_i as_030_000_sync_0_un1_n N_346 N_162_i \ -as_030_000_sync_0_un0_n N_352 N_346_i rw_000_int_0_un3_n N_219 N_159_0 \ -rw_000_int_0_un1_n N_218 N_305_i rw_000_int_0_un0_n N_183 N_210_i \ -rw_000_dma_0_un3_n N_196 N_225_i rw_000_dma_0_un1_n N_188 N_224_i \ -rw_000_dma_0_un0_n N_194 N_296_i a0_dma_0_un3_n N_347 N_352_i a0_dma_0_un1_n \ -N_348 cpu_est_2_0_2__n a0_dma_0_un0_n N_160 N_220_i \ -amiga_bus_enable_dma_low_0_un3_n N_341 N_221_i \ -amiga_bus_enable_dma_low_0_un1_n N_342 cpu_est_2_0_1__n \ -amiga_bus_enable_dma_low_0_un0_n N_231 N_219_i a_decode_15__n N_237 N_218_i \ -N_223 pos_clk_un9_clk_000_pe_0_n a_decode_14__n N_27 clk_000_d_i_2__n N_26 \ -N_157_i a_decode_13__n N_25 N_18_i un1_amiga_bus_enable_low_i N_37_0 \ -a_decode_12__n un21_fpu_cs_i cpu_est_i_2__n N_217_i a_decode_11__n \ -sm_amiga_i_0__n N_216_i sm_amiga_i_2__n CLK_030_c_i a_decode_10__n \ -sm_amiga_i_1__n N_198_0 cpu_est_i_0__n N_166_i a_decode_9__n VPA_D_i N_155_i \ -DTACK_D0_i N_303_0 a_decode_8__n AS_030_i N_291_i DSACK1_INT_i N_301_0 \ -a_decode_7__n cpu_est_i_3__n N_256_i sm_amiga_i_3__n N_248_i a_decode_6__n \ -cpu_est_i_1__n AMIGA_BUS_DATA_DIR_c_0 clk_000_d_i_1__n N_353_i a_decode_5__n \ -N_350_i_0 pos_clk_un6_bgack_000_0_n rst_dly_i_2__n N_65_0 a_decode_4__n \ -nEXP_SPACE_i N_3_i AS_000_i N_45_0 a_decode_3__n BGACK_030_INT_i N_4_i \ -sm_amiga_i_6__n N_44_0 a_decode_2__n clk_000_d_i_0__n N_8_i RW_000_i N_42_0 \ -CLK_030_H_i UDS_000_INT_i AS_000_DMA_i un1_UDS_000_INT_0 cycle_dma_i_0__n \ -LDS_000_INT_i DS_000_DMA_i un1_LDS_000_INT_0 RESET_OUT_i N_21_i \ -sm_amiga_i_4__n N_34_0 FPU_SENSE_i N_14_i AS_030.OE AS_000.OE RW_000.OE \ -UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE \ -AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE \ -A_0_.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE G_107 G_108 G_109 \ -pos_clk_CYCLE_DMA_5_1_i_x2 pos_clk_un21_bgack_030_int_i_i_a2_i_x2 -.names N_154_i_1.BLIF RST_c.BLIF SM_AMIGA_i_7_.D -11 1 -.names N_152_i_1.BLIF RST_c.BLIF SM_AMIGA_6_.D -11 1 -.names N_186_i.BLIF N_326_i.BLIF SM_AMIGA_5_.D -11 1 -.names N_148_i_1.BLIF RST_c.BLIF SM_AMIGA_4_.D -11 1 -.names N_146_i_1.BLIF RST_c.BLIF SM_AMIGA_3_.D -11 1 -.names N_144_i_1.BLIF RST_c.BLIF SM_AMIGA_2_.D -11 1 -.names N_142_i_1.BLIF RST_c.BLIF SM_AMIGA_1_.D -11 1 -.names N_140_i_1.BLIF RST_c.BLIF SM_AMIGA_0_.D -11 1 -.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_.D -1- 1 --1 1 -.names N_28_0.BLIF IPL_030DFF_0_reg.D +RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C inst_RW_000_INT.D \ +inst_RW_000_INT.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \ +inst_LDS_000_INT.D inst_LDS_000_INT.C inst_BGACK_030_INTreg.D \ +inst_BGACK_030_INTreg.C inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D \ +inst_DS_000_DMA.C inst_DSACK1_INT.D inst_DSACK1_INT.C inst_AS_000_INT.D \ +inst_AS_000_INT.C inst_AS_030_D0.D inst_AS_030_D0.C inst_VPA_D.D inst_VPA_D.C \ +inst_DTACK_D0.D inst_DTACK_D0.C inst_CLK_030_H.D inst_CLK_030_H.C \ +inst_RESET_OUT.D inst_RESET_OUT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C \ +BG_000DFFreg.D BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D \ +inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D \ +inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_UDS_000_INT.D inst_UDS_000_INT.C \ +inst_A0_DMA.D inst_A0_DMA.C inst_RW_000_DMA.D inst_RW_000_DMA.C \ +inst_VMA_INTreg.D inst_VMA_INTreg.C inst_BGACK_030_INT_D.D \ +inst_BGACK_030_INT_D.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C inst_CLK_OUT_PRE_50.D \ +inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C SIZE_1_ \ +AHIGH_31_ AS_030 AS_000 RW_000 UDS_000 LDS_000 BERR RW SIZE_0_ AHIGH_30_ \ +AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ A_0_ ipl_i_2__n \ +N_233_0 ipl_i_1__n N_360_i ipl_i_0__n N_191_i_i a_i_1__n N_192_i_i \ +AS_000_DMA_i AS_000_i N_199_i CLK_030_H_i N_204_i AS_030_000_SYNC_i \ +AMIGA_BUS_ENABLE_DMA_HIGH_i N_282_i vcc_n_n cycle_dma_i_0__n N_278_i \ +ahigh_i_30__n N_186_i gnd_n_n ahigh_i_31__n N_185_i un1_amiga_bus_enable_low \ +ahigh_i_28__n CLK_030_c_i un7_as_030 ahigh_i_29__n N_184_0 un1_LDS_000_INT \ +ahigh_i_26__n N_179_0 un1_UDS_000_INT ahigh_i_27__n N_251_i un10_ciin \ +ahigh_i_24__n LDS_000_c_i un21_fpu_cs ahigh_i_25__n UDS_000_c_i un21_berr \ +N_172_i un6_ds_030 pos_clk_un21_bgack_030_int_i_0_0_n N_163_i clk_000_d_i_3__n \ +N_115_i N_350_i N_114_i un1_rw_i un6_ds_030_i N_126_0 DS_000_DMA_i N_313_i \ +N_132_i N_231_i N_133_i N_291_i un7_as_030_i AMIGA_BUS_ENABLE_DMA_LOW_i \ +N_288_i AS_030_c N_287_i AS_000_c N_340_i RW_000_c N_284_i N_275_i UDS_000_c \ +pos_clk_size_dma_6_0_1__n N_268_i LDS_000_c pos_clk_size_dma_6_0_0__n N_265_i \ +size_c_0__n N_267_i size_c_1__n N_337_i N_338_i ahigh_c_24__n N_55_0 \ +un1_as_000_i ahigh_c_25__n N_245_0 N_229_i pos_clk_un9_bg_030_n ahigh_c_26__n \ +N_227_i ahigh_c_27__n N_226_i ahigh_c_28__n N_246_0 N_332_i ahigh_c_29__n \ +pos_clk_ds_000_dma_4_0_n N_48_0 ahigh_c_30__n pos_clk_rw_000_dma_3_0_n N_218_i \ +ahigh_c_31__n un10_ciin_i pos_clk_a0_dma_3_n N_62_0 pos_clk_rw_000_dma_3_n \ +N_215_i N_216_i un10_amiga_bus_enable_high_i N_214_i N_310_0 N_24_i N_33_0 \ +pos_clk_ds_000_dma_4_n N_23_i N_3 N_32_0 N_4 N_22_i N_31_0 N_3_i N_45_0 N_4_i \ +N_44_0 N_15 N_15_i N_19 N_40_0 N_20 N_19_i N_22 N_36_0 N_23 N_20_i N_24 N_35_0 \ +N_25 N_25_i N_26 N_30_0 N_27 N_26_i N_29_0 N_27_i a_decode_c_16__n N_28_0 \ +BG_030_c_i a_decode_c_17__n pos_clk_un9_bg_030_0_n N_235_i_1 a_decode_c_18__n \ +N_235_i_2 N_156_i_1 a_decode_c_19__n N_156_i_2 N_156_i_3 a_decode_c_20__n \ +N_156_i_4 pos_clk_un10_sm_amiga_i_1_n a_decode_c_21__n N_176_i_1 un10_ciin_1 \ +a_decode_c_22__n un10_ciin_2 un10_ciin_3 a_decode_c_23__n un10_ciin_4 \ +un10_ciin_5 a_c_0__n un10_ciin_6 un10_ciin_7 a_c_1__n un10_ciin_8 un10_ciin_9 \ +pos_clk_size_dma_6_0__n nEXP_SPACE_c un10_ciin_10 pos_clk_size_dma_6_1__n \ +un10_ciin_11 N_199 BERR_c N_163_i_1 pos_clk_un21_bgack_030_int_i_0_n N_163_i_2 \ +N_231 BG_030_c pos_clk_un21_bgack_030_int_i_0_0_1_n N_233 \ +pos_clk_un21_bgack_030_int_i_0_0_2_n N_111 N_138_i_1 N_112 N_138_i_2 N_113 \ +N_59_i_1 N_114 BGACK_000_c N_59_i_2 N_115 N_233_0_1 N_245 CLK_030_c N_233_0_2 \ +N_246 N_214_1 N_62 N_214_2 N_214_3 N_132 CLK_OSZI_c un21_fpu_cs_1 N_133 \ +un21_berr_1_0 N_310 N_182_0_1 N_126 N_234_i_1 N_149 N_234_i_2 N_150 N_206_1 \ +N_158 FPU_SENSE_c N_206_2 N_160 N_205_1 N_163 N_205_2 N_172 N_352_1 N_179 \ +N_352_2 N_184 N_231_i_1 N_185 N_152_i_1 N_196 N_144_i_1 N_203 ipl_c_0__n \ +N_142_i_1 N_204 N_312_i_1 N_209 ipl_c_1__n N_236_i_1 N_214 N_148_i_1 N_215 \ +ipl_c_2__n N_136_i_1 N_216 N_246_0_1 N_218 N_249_i_1 N_224 DTACK_c N_57_i_1 \ +N_332 N_338_1 N_226 N_224_1 N_227 N_216_1 N_229 VPA_c N_209_1 N_337 N_203_1 \ +N_338 N_196_1 N_265 RST_c cpu_est_0_3__un3_n N_267 cpu_est_0_3__un1_n N_268 \ +cpu_est_0_3__un0_n N_275 RW_c rw_000_int_0_un3_n N_278 rw_000_int_0_un1_n \ +N_282 fc_c_0__n rw_000_int_0_un0_n N_284 vma_int_0_un3_n N_340 fc_c_1__n \ +vma_int_0_un1_n N_287 vma_int_0_un0_n N_288 cpu_est_0_1__un3_n N_291 \ +AMIGA_BUS_DATA_DIR_c cpu_est_0_1__un1_n N_293 cpu_est_0_1__un0_n N_350 \ +cpu_est_0_2__un3_n N_355 cpu_est_0_2__un1_n cpu_est_0_2__un0_n N_16_i \ +uds_000_int_0_un3_n N_39_0 uds_000_int_0_un1_n VPA_c_i uds_000_int_0_un0_n \ +N_52_0 lds_000_int_0_un3_n N_156 DTACK_c_i lds_000_int_0_un1_n N_201 N_53_0 \ +lds_000_int_0_un0_n N_202 N_210_i bgack_030_int_0_un3_n N_154 N_211_i \ +bgack_030_int_0_un1_n un21_berr_1 N_189_i bgack_030_int_0_un0_n N_174 \ +un1_SM_AMIGA_0_sqmuxa_1_0 ds_000_enable_0_un3_n N_223 RW_c_i \ +ds_000_enable_0_un1_n N_221 N_311_0 ds_000_enable_0_un0_n N_222 N_336_i \ +size_dma_0_0__un3_n N_219 N_244_i size_dma_0_0__un1_n N_220 \ +size_dma_0_0__un0_n pos_clk_un6_bgack_000_n N_314_0 size_dma_0_1__un3_n N_359 \ +N_159_i size_dma_0_1__un1_n N_8 VMA_INT_i size_dma_0_1__un0_n N_14 N_352_i \ +ipl_030_0_0__un3_n N_21 N_353_i ipl_030_0_0__un1_n N_9 N_293_i \ +ipl_030_0_0__un0_n un1_DS_000_ENABLE_0_sqmuxa N_175_i ipl_030_0_1__un3_n N_66 \ +N_176_i ipl_030_0_1__un1_n N_171 ipl_030_0_1__un0_n N_354 N_198_i \ +ipl_030_0_2__un3_n N_18 N_197_i ipl_030_0_2__un1_n pos_clk_un9_clk_000_pe_n \ +N_196_i ipl_030_0_2__un0_n cpu_est_2_1__n N_183_0 a0_dma_0_un3_n \ +cpu_est_2_2__n N_182_0 a0_dma_0_un1_n N_197 N_180_0 a0_dma_0_un0_n N_198 \ +N_178_0 amiga_bus_enable_dma_low_0_un3_n N_208 N_82_i \ +amiga_bus_enable_dma_low_0_un1_n N_210 N_315_i \ +amiga_bus_enable_dma_low_0_un0_n N_315 N_351_i \ +amiga_bus_enable_dma_high_0_un3_n N_212 N_154_0 \ +amiga_bus_enable_dma_high_0_un1_n N_180 N_149_i \ +amiga_bus_enable_dma_high_0_un0_n N_213 N_207_i bg_000_0_un3_n N_178 N_228_i \ +bg_000_0_un1_n N_228 bg_000_0_un0_n N_182 N_213_i ds_000_dma_0_un3_n N_176 \ +N_212_i ds_000_dma_0_un1_n N_183 N_309_i ds_000_dma_0_un0_n N_351 N_357_i \ +as_000_dma_0_un3_n N_357 cpu_est_2_0_2__n as_000_dma_0_un1_n N_206 N_208_i \ +as_000_dma_0_un0_n N_205 N_209_i as_030_000_sync_0_un3_n N_352 \ +cpu_est_2_0_1__n as_030_000_sync_0_un1_n N_353 N_206_i as_030_000_sync_0_un0_n \ +N_314 N_205_i rw_000_dma_0_un3_n N_244 pos_clk_un9_clk_000_pe_0_n \ +rw_000_dma_0_un1_n N_336 N_18_i rw_000_dma_0_un0_n N_311 N_37_0 a_decode_15__n \ +un1_SM_AMIGA_0_sqmuxa_1 N_171_i N_211 N_354_i a_decode_14__n N_16 \ +un1_DS_000_ENABLE_0_sqmuxa_0 un1_amiga_bus_enable_low_i N_66_0 a_decode_13__n \ +un21_fpu_cs_i UDS_000_INT_i cpu_est_i_2__n un1_UDS_000_INT_0 a_decode_12__n \ +cpu_est_i_0__n LDS_000_INT_i VPA_D_i un1_LDS_000_INT_0 a_decode_11__n \ +DTACK_D0_i N_21_i cpu_est_i_3__n N_34_0 a_decode_10__n sm_amiga_i_i_7__n \ +N_14_i sm_amiga_i_5__n N_41_0 a_decode_9__n sm_amiga_i_3__n N_8_i \ +cpu_est_i_1__n N_42_0 a_decode_8__n clk_000_d_i_1__n a_c_i_0__n N_355_i_0 \ +size_c_i_1__n a_decode_7__n sm_amiga_i_4__n pos_clk_un10_sm_amiga_i_n \ +sm_amiga_i_2__n N_359_i a_decode_6__n rst_dly_i_0__n pos_clk_un6_bgack_000_0_n \ +rst_dly_i_2__n N_220_i a_decode_5__n a_decode_i_19__n N_219_i a_decode_i_18__n \ +a_decode_4__n a_decode_i_16__n N_222_i RW_000_i N_221_i a_decode_3__n \ +sm_amiga_i_0__n AS_030_i N_223_i a_decode_2__n AS_000_INT_i N_224_i \ +DSACK1_INT_i AMIGA_BUS_DATA_DIR_c_0 clk_000_d_i_0__n N_150_i sm_amiga_i_6__n \ +N_156_i sm_amiga_i_1__n N_160_i FPU_SENSE_i N_174_i rst_dly_i_1__n N_158_i \ +AS_030_D0_i N_201_i BGACK_030_INT_i N_202_i nEXP_SPACE_i N_203_i RESET_OUT_i \ +AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE \ +AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE \ +AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE \ +CIIN.OE pos_clk_un21_bgack_030_int_i_0_o3_0_x2 pos_clk_un1_ipl_i_0_x2 \ +pos_clk_un1_ipl_i_0_x2_0 pos_clk_un1_ipl_i_0_x2_1 pos_clk_CYCLE_DMA_5_1_i_0_x2 +.names N_113.BLIF IPL_D0_0_.D 0 1 -.names N_29_0.BLIF IPL_030DFF_1_reg.D +.names N_112.BLIF IPL_D0_1_.D 0 1 -.names N_30_0.BLIF IPL_030DFF_2_reg.D +.names N_111.BLIF IPL_D0_2_.D 0 1 -.names N_49_0.BLIF IPL_D0_0_.D -0 1 -.names N_50_0.BLIF IPL_D0_1_.D -0 1 -.names N_51_0.BLIF IPL_D0_2_.D -0 1 -.names N_235_i_1.BLIF N_235_i_2.BLIF CYCLE_DMA_0_.D +.names N_152_i_1.BLIF RST_c.BLIF SM_AMIGA_i_7_.D 11 1 -.names N_136_i_1.BLIF N_245_0.BLIF CYCLE_DMA_1_.D +.names N_148_i_1.BLIF RST_c.BLIF SM_AMIGA_6_.D 11 1 -.names size_dma_0_0__un1_n.BLIF size_dma_0_0__un0_n.BLIF SIZE_DMA_0_.D -1- 1 --1 1 -.names size_dma_0_1__un1_n.BLIF size_dma_0_1__un0_n.BLIF SIZE_DMA_1_.D -1- 1 --1 1 -.names N_341_i.BLIF N_342_i.BLIF cpu_est_0_.D +.names N_82_i.BLIF N_228_i.BLIF SM_AMIGA_5_.D +11 1 +.names N_144_i_1.BLIF RST_c.BLIF SM_AMIGA_4_.D +11 1 +.names N_142_i_1.BLIF RST_c.BLIF SM_AMIGA_3_.D +11 1 +.names N_312_i_1.BLIF RST_c.BLIF SM_AMIGA_2_.D +11 1 +.names N_138_i_1.BLIF N_138_i_2.BLIF SM_AMIGA_1_.D +11 1 +.names N_136_i_1.BLIF RST_c.BLIF SM_AMIGA_0_.D +11 1 +.names N_244_i.BLIF N_336_i.BLIF cpu_est_0_.D 11 1 .names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D 1- 1 @@ -440,44 +421,31 @@ pos_clk_CYCLE_DMA_5_1_i_x2 pos_clk_un21_bgack_030_int_i_i_a2_i_x2 .names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D 1- 1 -1 1 -.names N_234_i_1.BLIF RST_c.BLIF RST_DLY_0_.D +.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_.D +1- 1 +-1 1 +.names N_31_0.BLIF IPL_030DFF_0_reg.D +0 1 +.names N_32_0.BLIF IPL_030DFF_1_reg.D +0 1 +.names N_33_0.BLIF IPL_030DFF_2_reg.D +0 1 +.names N_234_i_1.BLIF N_234_i_2.BLIF RST_DLY_2_.D 11 1 -.names N_233_i_1.BLIF N_233_i_2.BLIF RST_DLY_1_.D +.names N_59_i_1.BLIF N_59_i_2.BLIF CYCLE_DMA_0_.D 11 1 -.names N_232_i_1.BLIF N_232_i_2.BLIF RST_DLY_2_.D +.names N_57_i_1.BLIF N_251_i.BLIF CYCLE_DMA_1_.D 11 1 -.names N_45_0.BLIF inst_DS_000_DMA.D -0 1 -.names N_231_i.BLIF N_237_i.BLIF inst_DSACK1_INT.D +.names size_dma_0_0__un1_n.BLIF size_dma_0_0__un0_n.BLIF SIZE_DMA_0_.D +1- 1 +-1 1 +.names size_dma_0_1__un1_n.BLIF size_dma_0_1__un0_n.BLIF SIZE_DMA_1_.D +1- 1 +-1 1 +.names N_236_i_1.BLIF RST_c.BLIF RST_DLY_0_.D 11 1 -.names N_319_i.BLIF N_320_i.BLIF inst_AS_000_INT.D +.names N_235_i_1.BLIF N_235_i_2.BLIF RST_DLY_1_.D 11 1 -.names N_48_0.BLIF inst_AS_030_D0.D -0 1 -.names N_52_0.BLIF inst_VPA_D.D -0 1 -.names N_53_0.BLIF inst_DTACK_D0.D -0 1 -.names N_63_i_1.BLIF RST_c.BLIF inst_CLK_030_H.D -11 1 -.names N_298_0.BLIF inst_RESET_OUT.D -0 1 -.names N_9.BLIF RST_c.BLIF inst_DS_000_ENABLE.D -11 1 -.names N_31_0.BLIF BG_000DFFreg.D -0 1 -.names N_32_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D -0 1 -.names N_33_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D -0 1 -.names N_34_0.BLIF inst_UDS_000_INT.D -0 1 -.names N_35_0.BLIF inst_A0_DMA.D -0 1 -.names N_36_0.BLIF inst_RW_000_DMA.D -0 1 -.names N_37_0.BLIF inst_VMA_INTreg.D -0 1 .names N_39_0.BLIF inst_RW_000_INT.D 0 1 .names N_40_0.BLIF inst_AS_030_000_SYNC.D @@ -488,303 +456,336 @@ pos_clk_CYCLE_DMA_5_1_i_x2 pos_clk_un21_bgack_030_int_i_i_a2_i_x2 0 1 .names N_44_0.BLIF inst_AS_000_DMA.D 0 1 -.names N_245_0.BLIF inst_BGACK_030_INT_D.D +.names N_45_0.BLIF inst_DS_000_DMA.D +0 1 +.names N_219_i.BLIF N_220_i.BLIF inst_DSACK1_INT.D +11 1 +.names N_221_i.BLIF N_222_i.BLIF inst_AS_000_INT.D +11 1 +.names N_48_0.BLIF inst_AS_030_D0.D +0 1 +.names N_52_0.BLIF inst_VPA_D.D +0 1 +.names N_53_0.BLIF inst_DTACK_D0.D +0 1 +.names N_249_i_1.BLIF pos_clk_un21_bgack_030_int_i_0_0_n.BLIF inst_CLK_030_H.D +11 1 +.names N_55_0.BLIF inst_RESET_OUT.D +0 1 +.names N_9.BLIF RST_c.BLIF inst_DS_000_ENABLE.D +11 1 +.names N_28_0.BLIF BG_000DFFreg.D +0 1 +.names N_29_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D +0 1 +.names N_30_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D +0 1 +.names N_34_0.BLIF inst_UDS_000_INT.D +0 1 +.names N_35_0.BLIF inst_A0_DMA.D +0 1 +.names N_36_0.BLIF inst_RW_000_DMA.D +0 1 +.names N_37_0.BLIF inst_VMA_INTreg.D +0 1 +.names N_251_i.BLIF inst_BGACK_030_INT_D.D 0 1 .names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D 0 1 -.names RST_DLY_1_.BLIF rst_dly_i_1__n +.names ipl_c_2__n.BLIF ipl_i_2__n 0 1 -.names N_14_i.BLIF RST_c.BLIF N_41_0 +.names N_233_0_1.BLIF N_233_0_2.BLIF N_233_0 11 1 -.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +.names ipl_c_1__n.BLIF ipl_i_1__n 0 1 -.names a_c_0__n.BLIF a_c_i_0__n +.names pos_clk_un1_ipl_i_0_x2.BLIF N_360_i 0 1 -.names RST_DLY_0_.BLIF rst_dly_i_0__n +.names ipl_c_0__n.BLIF ipl_i_0__n 0 1 -.names size_c_1__n.BLIF size_c_i_1__n -0 1 -.names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n -0 1 -.names pos_clk_un10_sm_amiga_i_1_n.BLIF size_c_i_1__n.BLIF \ -pos_clk_un10_sm_amiga_i_n -11 1 -.names inst_AS_030_D0.BLIF AS_030_D0_i -0 1 -.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF un1_as_000_i -11 1 -.names inst_AS_000_INT.BLIF AS_000_INT_i -0 1 -.names un10_ciin.BLIF un10_ciin_i +.names pos_clk_un1_ipl_i_0_x2_0.BLIF N_191_i_i 0 1 .names a_c_1__n.BLIF a_i_1__n 0 1 -.names nEXP_SPACE_i.BLIF un10_ciin_i.BLIF N_260_0 -11 1 -.names a_decode_c_16__n.BLIF a_decode_i_16__n +.names pos_clk_un1_ipl_i_0_x2_1.BLIF N_192_i_i 0 1 -.names N_229.BLIF N_229_i +.names inst_AS_000_DMA.BLIF AS_000_DMA_i 0 1 -.names a_decode_c_18__n.BLIF a_decode_i_18__n +.names AS_000_c.BLIF AS_000_i 0 1 -.names N_230.BLIF N_230_i +.names N_199.BLIF N_199_i +0 1 +.names inst_CLK_030_H.BLIF CLK_030_H_i +0 1 +.names N_204.BLIF N_204_i +0 1 +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +0 1 +.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i +0 1 +.names N_282.BLIF N_282_i 0 1 .names vcc_n_n 1 -.names a_decode_c_19__n.BLIF a_decode_i_19__n +.names CYCLE_DMA_0_.BLIF cycle_dma_i_0__n +0 1 +.names N_278.BLIF N_278_i 0 1 -.names N_229_i.BLIF N_230_i.BLIF N_298_0 -11 1 .names ahigh_c_30__n.BLIF ahigh_i_30__n 0 1 -.names AS_030_i.BLIF RST_c.BLIF N_48_0 +.names BGACK_030_INT_i.BLIF nEXP_SPACE_i.BLIF N_186_i 11 1 .names gnd_n_n .names ahigh_c_31__n.BLIF ahigh_i_31__n 0 1 -.names BGACK_030_INT_i.BLIF nEXP_SPACE_i.BLIF N_299_i +.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF N_185_i 11 1 .names AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF BGACK_030_INT_i.BLIF \ un1_amiga_bus_enable_low 11 1 .names ahigh_c_28__n.BLIF ahigh_i_28__n 0 1 -.names N_345.BLIF N_345_i +.names CLK_030_c.BLIF CLK_030_c_i 0 1 .names AS_000_DMA_i.BLIF AS_000_i.BLIF un7_as_030 11 1 .names ahigh_c_29__n.BLIF ahigh_i_29__n 0 1 -.names N_349.BLIF N_349_i -0 1 -.names un1_UDS_000_INT_0.BLIF un1_UDS_000_INT -0 1 -.names ahigh_c_26__n.BLIF ahigh_i_26__n -0 1 -.names N_181.BLIF N_349_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_i +.names AS_000_DMA_i.BLIF CLK_030_c_i.BLIF N_184_0 11 1 .names un1_LDS_000_INT_0.BLIF un1_LDS_000_INT 0 1 +.names ahigh_c_26__n.BLIF ahigh_i_26__n +0 1 +.names N_163_i.BLIF sm_amiga_i_i_7__n.BLIF N_179_0 +11 1 +.names un1_UDS_000_INT_0.BLIF un1_UDS_000_INT +0 1 .names ahigh_c_27__n.BLIF ahigh_i_27__n 0 1 -.names N_180_i_1.BLIF N_180_i_2.BLIF N_180_i -11 1 -.names un1_SM_AMIGA_0_sqmuxa_1_0.BLIF un1_SM_AMIGA_0_sqmuxa_1 -0 1 -.names ahigh_c_24__n.BLIF ahigh_i_24__n -0 1 -.names N_155_i.BLIF SM_AMIGA_4_.BLIF N_181_i +.names BGACK_030_INT_i.BLIF RST_c.BLIF N_251_i 11 1 .names un10_ciin_10.BLIF un10_ciin_11.BLIF un10_ciin 11 1 -.names ahigh_c_25__n.BLIF ahigh_i_25__n +.names ahigh_c_24__n.BLIF ahigh_i_24__n 0 1 -.names N_326.BLIF N_326_i -0 1 -.names un21_fpu_cs_1.BLIF N_161_i.BLIF un21_fpu_cs -11 1 -.names G_107.BLIF N_206_i -0 1 -.names un21_berr_1_0.BLIF N_161_i.BLIF un21_berr -11 1 -.names G_108.BLIF N_207_i -0 1 -.names N_305.BLIF RST_c.BLIF N_186_i -11 1 -.names AS_000_i.BLIF DS_000_DMA_i.BLIF un6_ds_030 -11 1 -.names G_109.BLIF N_208_i -0 1 -.names RST_DLY_0_.BLIF RST_DLY_1_.BLIF N_163_i -11 1 -.names N_305_i.BLIF SM_AMIGA_5_.BLIF N_197_0 -11 1 -.names N_79.BLIF N_79_i -0 1 -.names N_213.BLIF N_213_i -0 1 -.names N_78.BLIF N_78_i -0 1 -.names N_214.BLIF N_214_i -0 1 -.names un6_ds_030.BLIF un6_ds_030_i -0 1 -.names N_215.BLIF N_215_i -0 1 -.names N_165.BLIF N_165_i -0 1 -.names N_169.BLIF N_169_i -0 1 -.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF N_199_i -11 1 -.names un7_as_030.BLIF un7_as_030_i -0 1 -.names N_171_i.BLIF sm_amiga_i_i_7__n.BLIF N_191_0 -11 1 -.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i -0 1 -.names N_275.BLIF N_275_i -0 1 -.names N_275_i.BLIF SM_AMIGA_i_7_.BLIF N_187_0 -11 1 .names LDS_000_c.BLIF LDS_000_c_i 0 1 +.names un21_fpu_cs_1.BLIF N_156_i.BLIF un21_fpu_cs +11 1 +.names ahigh_c_25__n.BLIF ahigh_i_25__n +0 1 .names UDS_000_c.BLIF UDS_000_c_i 0 1 -.names LDS_000_c_i.BLIF UDS_000_c_i.BLIF N_184_i +.names un21_berr_1_0.BLIF N_156_i.BLIF un21_berr 11 1 -.names CLK_000_D_4_.BLIF clk_000_d_i_4__n -0 1 -.names N_171_i_1.BLIF N_171_i_2.BLIF N_171_i +.names LDS_000_c_i.BLIF UDS_000_c_i.BLIF N_172_i 11 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i -0 1 -.names N_161_i_4.BLIF N_161_i_3.BLIF N_161_i +.names AS_000_i.BLIF DS_000_DMA_i.BLIF un6_ds_030 11 1 -.names N_199_i.BLIF RST_c.BLIF N_113_0 +.names pos_clk_un21_bgack_030_int_i_0_0_1_n.BLIF \ +pos_clk_un21_bgack_030_int_i_0_0_2_n.BLIF pos_clk_un21_bgack_030_int_i_0_0_n 11 1 -.names N_338.BLIF N_338_i -0 1 -.names N_339.BLIF N_339_i -0 1 -.names N_335.BLIF N_335_i -0 1 -.names N_336.BLIF N_336_i -0 1 -.names N_334.BLIF N_334_i -0 1 -.names N_334_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n +.names N_163_i_1.BLIF N_163_i_2.BLIF N_163_i 11 1 -.names pos_clk_un6_bg_030_1_n.BLIF CLK_000_D_0_.BLIF pos_clk_un6_bg_030_n +.names CLK_000_D_3_.BLIF clk_000_d_i_3__n +0 1 +.names N_115.BLIF N_115_i +0 1 +.names N_350.BLIF N_350_i +0 1 +.names N_114.BLIF N_114_i +0 1 +.names BGACK_030_INT_i.BLIF inst_RESET_OUT.BLIF un1_rw_i 11 1 -.names N_333.BLIF N_333_i +.names un6_ds_030.BLIF un6_ds_030_i 0 1 -.names N_333_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n +.names N_185_i.BLIF RST_c.BLIF N_126_0 11 1 -.names pos_clk_ipl_1_n.BLIF N_207_i.BLIF pos_clk_ipl_n +.names inst_DS_000_DMA.BLIF DS_000_DMA_i +0 1 +.names N_186_i.BLIF inst_RESET_OUT.BLIF N_313_i 11 1 -.names N_295.BLIF N_295_i +.names N_132.BLIF N_132_i 0 1 -.names N_332.BLIF N_332_i -0 1 -.names N_292.BLIF N_292_i -0 1 -.names N_302_0_1.BLIF RW_000_i.BLIF N_302_0 +.names N_231_i_1.BLIF nEXP_SPACE_c.BLIF N_231_i 11 1 -.names pos_clk_un9_bg_030_0_n.BLIF pos_clk_un9_bg_030_n +.names N_133.BLIF N_133_i 0 1 -.names BGACK_030_INT_i.BLIF RW_000_i.BLIF N_300_0 +.names N_291.BLIF N_291_i +0 1 +.names un7_as_030.BLIF un7_as_030_i +0 1 +.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i +0 1 +.names N_288.BLIF N_288_i +0 1 +.names N_287.BLIF N_287_i +0 1 +.names N_340.BLIF N_340_i +0 1 +.names N_284.BLIF N_284_i +0 1 +.names N_275.BLIF N_275_i +0 1 +.names N_275_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n 11 1 -.names N_290.BLIF N_290_i +.names N_268.BLIF N_268_i 0 1 -.names N_273.BLIF N_273_i -0 1 -.names N_327.BLIF N_327_i -0 1 -.names N_270.BLIF N_270_i -0 1 -.names N_269.BLIF N_269_i +.names N_268_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n +11 1 +.names N_265.BLIF N_265_i 0 1 .names N_267.BLIF N_267_i 0 1 -.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF pos_clk_a0_dma_3_n +.names N_337.BLIF N_337_i +0 1 +.names N_338.BLIF N_338_i +0 1 +.names N_337_i.BLIF N_338_i.BLIF N_55_0 11 1 -.names N_324.BLIF N_324_i -0 1 -.names pos_clk_rw_000_int_5_0_n.BLIF pos_clk_rw_000_int_5_n -0 1 -.names N_166.BLIF N_187_0.BLIF un1_SM_AMIGA_0_sqmuxa_1_0 +.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF un1_as_000_i 11 1 -.names N_319.BLIF N_319_i -0 1 -.names N_320.BLIF N_320_i -0 1 -.names RW_c.BLIF RW_c_i -0 1 -.names N_187_0.BLIF RW_c_i.BLIF pos_clk_rw_000_int_5_0_n +.names CLK_030_c_i.BLIF pos_clk_un21_bgack_030_int_i_0_0_n.BLIF N_245_0 11 1 +.names N_229.BLIF N_229_i +0 1 +.names pos_clk_un9_bg_030_0_n.BLIF pos_clk_un9_bg_030_n +0 1 .names N_227.BLIF N_227_i 0 1 -.names AS_030_i.BLIF N_227_i.BLIF N_297_0 -11 1 -.names N_15.BLIF N_15_i +.names N_226.BLIF N_226_i 0 1 -.names N_15_i.BLIF RST_c.BLIF N_40_0 +.names N_246_0_1.BLIF pos_clk_un21_bgack_030_int_i_0_0_n.BLIF N_246_0 11 1 -.names N_16.BLIF N_16_i +.names N_332.BLIF N_332_i 0 1 -.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF N_15 -1- 1 --1 1 -.names N_16_i.BLIF RST_c.BLIF N_39_0 +.names N_332_i.BLIF pos_clk_un21_bgack_030_int_i_0_0_n.BLIF \ +pos_clk_ds_000_dma_4_0_n 11 1 -.names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF N_16 -1- 1 --1 1 -.names N_19.BLIF N_19_i +.names AS_030_i.BLIF RST_c.BLIF N_48_0 +11 1 +.names BGACK_030_INT_i.BLIF RW_000_i.BLIF pos_clk_rw_000_dma_3_0_n +11 1 +.names N_218.BLIF N_218_i 0 1 -.names rw_000_dma_0_un1_n.BLIF rw_000_dma_0_un0_n.BLIF N_19 -1- 1 --1 1 -.names N_19_i.BLIF RST_c.BLIF N_36_0 -11 1 -.names a0_dma_0_un1_n.BLIF a0_dma_0_un0_n.BLIF N_20 -1- 1 --1 1 -.names N_20.BLIF N_20_i +.names un10_ciin.BLIF un10_ciin_i 0 1 -.names amiga_bus_enable_dma_low_0_un1_n.BLIF \ -amiga_bus_enable_dma_low_0_un0_n.BLIF N_22 +.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF pos_clk_a0_dma_3_n +11 1 +.names nEXP_SPACE_i.BLIF un10_ciin_i.BLIF N_62_0 +11 1 +.names pos_clk_rw_000_dma_3_0_n.BLIF pos_clk_rw_000_dma_3_n +0 1 +.names N_215.BLIF N_215_i +0 1 +.names N_216.BLIF N_216_i +0 1 +.names N_215_i.BLIF N_216_i.BLIF un10_amiga_bus_enable_high_i +11 1 +.names N_214.BLIF N_214_i +0 1 +.names AS_030_i.BLIF N_214_i.BLIF N_310_0 +11 1 +.names N_24.BLIF N_24_i +0 1 +.names N_24_i.BLIF RST_c.BLIF N_33_0 +11 1 +.names pos_clk_ds_000_dma_4_0_n.BLIF pos_clk_ds_000_dma_4_n +0 1 +.names N_23.BLIF N_23_i +0 1 +.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3 1- 1 -1 1 -.names N_20_i.BLIF RST_c.BLIF N_35_0 +.names N_23_i.BLIF RST_c.BLIF N_32_0 11 1 -.names amiga_bus_enable_dma_high_0_un1_n.BLIF \ -amiga_bus_enable_dma_high_0_un0_n.BLIF N_23 +.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF N_4 1- 1 -1 1 .names N_22.BLIF N_22_i 0 1 -.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF N_24 +.names N_22_i.BLIF RST_c.BLIF N_31_0 +11 1 +.names N_3.BLIF N_3_i +0 1 +.names N_3_i.BLIF RST_c.BLIF N_45_0 +11 1 +.names N_4.BLIF N_4_i +0 1 +.names N_4_i.BLIF RST_c.BLIF N_44_0 +11 1 +.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF N_15 1- 1 -1 1 -.names N_22_i.BLIF RST_c.BLIF N_33_0 -11 1 -.names N_23.BLIF N_23_i +.names N_15.BLIF N_15_i 0 1 -.names N_23_i.BLIF RST_c.BLIF N_32_0 +.names rw_000_dma_0_un1_n.BLIF rw_000_dma_0_un0_n.BLIF N_19 +1- 1 +-1 1 +.names N_15_i.BLIF RST_c.BLIF N_40_0 11 1 -.names N_24.BLIF N_24_i +.names a0_dma_0_un1_n.BLIF a0_dma_0_un0_n.BLIF N_20 +1- 1 +-1 1 +.names N_19.BLIF N_19_i 0 1 -.names N_24_i.BLIF RST_c.BLIF N_31_0 +.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF N_22 +1- 1 +-1 1 +.names N_19_i.BLIF RST_c.BLIF N_36_0 +11 1 +.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF N_23 +1- 1 +-1 1 +.names N_20.BLIF N_20_i +0 1 +.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_24 +1- 1 +-1 1 +.names N_20_i.BLIF RST_c.BLIF N_35_0 +11 1 +.names amiga_bus_enable_dma_low_0_un1_n.BLIF \ +amiga_bus_enable_dma_low_0_un0_n.BLIF N_25 +1- 1 +-1 1 +.names N_25.BLIF N_25_i +0 1 +.names amiga_bus_enable_dma_high_0_un1_n.BLIF \ +amiga_bus_enable_dma_high_0_un0_n.BLIF N_26 +1- 1 +-1 1 +.names N_25_i.BLIF RST_c.BLIF N_30_0 +11 1 +.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF N_27 +1- 1 +-1 1 +.names N_26.BLIF N_26_i +0 1 +.names N_26_i.BLIF RST_c.BLIF N_29_0 +11 1 +.names N_27.BLIF N_27_i +0 1 +.names N_27_i.BLIF RST_c.BLIF N_28_0 11 1 .names BG_030_c.BLIF BG_030_c_i 0 1 -.names pos_clk_un6_bg_030_n.BLIF pos_clk_un6_bg_030_i_n -0 1 -.names BG_030_c_i.BLIF pos_clk_un6_bg_030_i_n.BLIF pos_clk_un9_bg_030_0_n +.names BG_030_c_i.BLIF N_231.BLIF pos_clk_un9_bg_030_0_n 11 1 -.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_161_i_1 +.names N_201_i.BLIF N_202_i.BLIF N_235_i_1 11 1 -.names a_decode_c_17__n.BLIF a_decode_i_16__n.BLIF N_161_i_2 +.names N_203_i.BLIF RST_c.BLIF N_235_i_2 11 1 -.names a_decode_i_18__n.BLIF a_decode_i_19__n.BLIF N_161_i_3 +.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_156_i_1 11 1 -.names N_161_i_1.BLIF N_161_i_2.BLIF N_161_i_4 +.names a_decode_c_17__n.BLIF a_decode_i_16__n.BLIF N_156_i_2 11 1 -.names N_213_i.BLIF N_214_i.BLIF N_233_i_1 +.names a_decode_i_18__n.BLIF a_decode_i_19__n.BLIF N_156_i_3 11 1 -.names N_215_i.BLIF RST_c.BLIF N_233_i_2 -11 1 -.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_180_i_1 -11 1 -.names N_345_i.BLIF pos_clk_un21_bgack_030_int_i_i_a2_i_x2.BLIF N_180_i_2 +.names N_156_i_1.BLIF N_156_i_2.BLIF N_156_i_4 11 1 .names size_c_0__n.BLIF a_c_i_0__n.BLIF pos_clk_un10_sm_amiga_i_1_n 11 1 -.names N_188.BLIF N_305_i.BLIF N_196_0_1 -11 1 -.names BERR_c.BLIF N_347_i.BLIF N_188_i_1 +.names BERR_c.BLIF N_352_i.BLIF N_176_i_1 11 1 .names ahigh_i_24__n.BLIF ahigh_i_25__n.BLIF un10_ciin_1 11 1 @@ -798,721 +799,716 @@ amiga_bus_enable_dma_high_0_un0_n.BLIF N_23 11 1 .names a_decode_c_20__n.BLIF a_decode_c_21__n.BLIF un10_ciin_6 11 1 -.names pos_clk_size_dma_6_0_0__n.BLIF pos_clk_size_dma_6_0__n -0 1 .names un10_ciin_1.BLIF un10_ciin_2.BLIF un10_ciin_7 11 1 -.names pos_clk_size_dma_6_0_1__n.BLIF pos_clk_size_dma_6_1__n -0 1 .names un10_ciin_3.BLIF un10_ciin_4.BLIF un10_ciin_8 11 1 .names un10_ciin_5.BLIF un10_ciin_6.BLIF un10_ciin_9 11 1 +.names pos_clk_size_dma_6_0_0__n.BLIF pos_clk_size_dma_6_0__n +0 1 .names un10_ciin_7.BLIF un10_ciin_8.BLIF un10_ciin_10 11 1 +.names pos_clk_size_dma_6_0_1__n.BLIF pos_clk_size_dma_6_1__n +0 1 .names un10_ciin_9.BLIF a_decode_c_22__n.BLIF un10_ciin_11 11 1 -.names AS_030_000_SYNC_i.BLIF CLK_000_D_5_.BLIF N_171_i_1 +.names CYCLE_DMA_0_.BLIF N_150_i.BLIF N_199 11 1 -.names a_c_1__n.BLIF BGACK_030_INT_i.BLIF N_78 +.names AS_030_000_SYNC_i.BLIF CLK_000_D_4_.BLIF N_163_i_1 11 1 -.names clk_000_d_i_4__n.BLIF nEXP_SPACE_c.BLIF N_171_i_2 -11 1 -.names a_i_1__n.BLIF BGACK_030_INT_i.BLIF N_79 -11 1 -.names AS_030_D0_i.BLIF N_161.BLIF N_227_1 -11 1 -.names N_260_0.BLIF N_260 +.names pos_clk_un21_bgack_030_int_i_0_0_n.BLIF \ +pos_clk_un21_bgack_030_int_i_0_n 0 1 -.names N_199_i.BLIF sm_amiga_i_i_7__n.BLIF N_227_2 +.names clk_000_d_i_3__n.BLIF nEXP_SPACE_c.BLIF N_163_i_2 11 1 -.names N_141.BLIF nEXP_SPACE_i.BLIF N_139 +.names N_231_i.BLIF N_231 +0 1 +.names AS_000_i.BLIF BGACK_030_INT_i.BLIF pos_clk_un21_bgack_030_int_i_0_0_1_n 11 1 -.names N_227_1.BLIF N_227_2.BLIF N_227_3 +.names N_233_0.BLIF N_233 +0 1 +.names pos_clk_un21_bgack_030_int_i_0_o3_0_x2.BLIF N_350_i.BLIF \ +pos_clk_un21_bgack_030_int_i_0_0_2_n 11 1 -.names BGACK_030_INT_i.BLIF inst_RESET_OUT.BLIF N_141 +.names ipl_i_2__n.BLIF RST_c.BLIF N_111 +11 1 +.names N_149.BLIF N_278_i.BLIF N_138_i_1 +11 1 +.names ipl_i_1__n.BLIF RST_c.BLIF N_112 +11 1 +.names N_282_i.BLIF RST_c.BLIF N_138_i_2 +11 1 +.names ipl_i_0__n.BLIF RST_c.BLIF N_113 +11 1 +.names AS_000_i.BLIF N_199_i.BLIF N_59_i_1 +11 1 +.names a_c_1__n.BLIF BGACK_030_INT_i.BLIF N_114 +11 1 +.names N_204_i.BLIF N_251_i.BLIF N_59_i_2 +11 1 +.names a_i_1__n.BLIF BGACK_030_INT_i.BLIF N_115 +11 1 +.names N_150_i.BLIF N_191_i_i.BLIF N_233_0_1 +11 1 +.names N_245_0.BLIF N_245 +0 1 +.names N_192_i_i.BLIF N_360_i.BLIF N_233_0_2 +11 1 +.names N_246_0.BLIF N_246 +0 1 +.names AS_030_D0_i.BLIF N_156.BLIF N_214_1 +11 1 +.names N_62_0.BLIF N_62 +0 1 +.names N_185_i.BLIF sm_amiga_i_i_7__n.BLIF N_214_2 +11 1 +.names N_214_1.BLIF N_214_2.BLIF N_214_3 +11 1 +.names AS_030_i.BLIF DSACK1_INT_i.BLIF N_132 11 1 .names un21_berr_1.BLIF FPU_SENSE_i.BLIF un21_fpu_cs_1 11 1 -.names AS_030_i.BLIF DSACK1_INT_i.BLIF N_165 +.names AS_000_INT_i.BLIF AS_030_i.BLIF N_133 11 1 .names un21_berr_1.BLIF FPU_SENSE_c.BLIF un21_berr_1_0 11 1 -.names AS_000_INT_i.BLIF AS_030_i.BLIF N_169 -11 1 -.names AS_000_i.BLIF N_216_i.BLIF N_235_i_1 -11 1 -.names N_297_0.BLIF N_297 +.names N_310_0.BLIF N_310 0 1 -.names N_217_i.BLIF N_245_0.BLIF N_235_i_2 +.names N_149_i.BLIF N_176.BLIF N_182_0_1 11 1 -.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_256_1 -11 1 -.names N_300_0.BLIF N_300 +.names N_126_0.BLIF N_126 0 1 -.names RW_000_c.BLIF nEXP_SPACE_i.BLIF N_256_2 +.names N_196_i.BLIF N_197_i.BLIF N_234_i_1 11 1 -.names N_302_0.BLIF N_302 +.names N_149_i.BLIF N_149 0 1 -.names N_209_i.BLIF N_211_i.BLIF N_232_i_1 +.names N_198_i.BLIF RST_c.BLIF N_234_i_2 11 1 -.names N_113_0.BLIF N_113 +.names N_150_i.BLIF N_150 0 1 -.names N_306_i.BLIF RST_c.BLIF N_232_i_2 +.names N_149_i.BLIF N_357.BLIF N_206_1 11 1 -.names N_305_i.BLIF N_305 +.names N_158_i.BLIF N_158 0 1 -.names N_305_i.BLIF N_352.BLIF N_219_1 +.names VPA_D_i.BLIF cpu_est_i_3__n.BLIF N_206_2 11 1 -.names N_155_i.BLIF N_155 +.names N_160_i.BLIF N_160 0 1 -.names VPA_D_i.BLIF cpu_est_i_3__n.BLIF N_219_2 +.names N_150_i.BLIF N_159_i.BLIF N_205_1 11 1 .names N_163_i.BLIF N_163 0 1 -.names N_155_i.BLIF N_164_i.BLIF N_218_1 +.names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF N_205_2 11 1 -.names N_166_i.BLIF N_166 +.names N_172_i.BLIF N_172 0 1 -.names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF N_218_2 +.names N_159_i.BLIF N_314_0.BLIF N_352_1 11 1 -.names N_171_i.BLIF N_171 +.names N_179_0.BLIF N_179 0 1 -.names N_160_0.BLIF N_164_i.BLIF N_347_1 +.names VMA_INT_i.BLIF VPA_D_i.BLIF N_352_2 11 1 -.names N_180_i.BLIF N_180 +.names N_184_0.BLIF N_184 0 1 -.names VMA_INT_i.BLIF VPA_D_i.BLIF N_347_2 +.names inst_AS_030_D0.BLIF CLK_000_D_0_.BLIF N_231_i_1 11 1 -.names N_184_i.BLIF N_184 +.names N_185_i.BLIF N_185 0 1 -.names AS_000_i.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.BLIF N_136_i_1 +.names N_291_i.BLIF N_293_i.BLIF N_152_i_1 11 1 -.names N_191_0.BLIF N_191 +.names N_196_1.BLIF rst_dly_i_2__n.BLIF N_196 +11 1 +.names N_150.BLIF N_288_i.BLIF N_144_i_1 +11 1 +.names N_203_1.BLIF rst_dly_i_1__n.BLIF N_203 +11 1 +.names N_287_i.BLIF N_340_i.BLIF N_142_i_1 +11 1 +.names cycle_dma_i_0__n.BLIF N_150.BLIF N_204 +11 1 +.names N_150.BLIF N_284_i.BLIF N_312_i_1 +11 1 +.names N_209_1.BLIF cpu_est_i_3__n.BLIF N_209 +11 1 +.names N_265_i.BLIF N_267_i.BLIF N_236_i_1 +11 1 +.names N_214_3.BLIF nEXP_SPACE_c.BLIF N_214 +11 1 +.names N_160.BLIF N_229_i.BLIF N_148_i_1 +11 1 +.names AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF BGACK_030_INT_i.BLIF N_215 +11 1 +.names N_150.BLIF N_227_i.BLIF N_136_i_1 +11 1 +.names N_216_1.BLIF AS_030_i.BLIF N_216 +11 1 +.names N_226_i.BLIF RW_000_i.BLIF N_246_0_1 +11 1 +.names CLK_030_H_i.BLIF N_184.BLIF N_218 +11 1 +.names N_218_i.BLIF RST_c.BLIF N_249_i_1 +11 1 +.names N_224_1.BLIF RW_000_c.BLIF N_224 +11 1 +.names AS_000_i.BLIF pos_clk_CYCLE_DMA_5_1_i_0_x2.BLIF N_57_i_1 +11 1 +.names inst_AS_000_DMA.BLIF RW_000_i.BLIF N_332 +11 1 +.names N_149_i.BLIF N_355.BLIF N_338_1 +11 1 +.names inst_CLK_030_H.BLIF CLK_030_c.BLIF N_226 +11 1 +.names AS_000_i.BLIF N_186_i.BLIF N_224_1 +11 1 +.names N_174.BLIF sm_amiga_i_0__n.BLIF N_227 +11 1 +.names inst_BGACK_030_INTreg.BLIF AS_030_000_SYNC_i.BLIF N_216_1 +11 1 +.names N_179.BLIF sm_amiga_i_6__n.BLIF N_229 +11 1 +.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_209_1 +11 1 +.names inst_RESET_OUT.BLIF RST_c.BLIF N_337 +11 1 +.names N_207_i.BLIF rst_dly_i_0__n.BLIF N_203_1 +11 1 +.names N_338_1.BLIF RST_c.BLIF N_338 +11 1 +.names N_158.BLIF N_207_i.BLIF N_196_1 +11 1 +.names N_154.BLIF RST_DLY_0_.BLIF N_265 +11 1 +.names N_149.BLIF cpu_est_0_3__un3_n 0 1 -.names N_338_i.BLIF N_339_i.BLIF N_146_i_1 +.names N_82_i.BLIF rst_dly_i_0__n.BLIF N_267 11 1 -.names N_199_i.BLIF N_199 +.names cpu_est_3_.BLIF N_149.BLIF cpu_est_0_3__un1_n +11 1 +.names BGACK_030_INT_i.BLIF N_172.BLIF N_268 +11 1 +.names N_189_i.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n +11 1 +.names BGACK_030_INT_i.BLIF N_172_i.BLIF N_275 +11 1 +.names un1_SM_AMIGA_0_sqmuxa_1.BLIF rw_000_int_0_un3_n 0 1 -.names N_335_i.BLIF N_336_i.BLIF N_142_i_1 +.names N_150.BLIF SM_AMIGA_2_.BLIF N_278 11 1 -.names un1_amiga_bus_enable_dma_high_i_m2_0__un1_n.BLIF \ -un1_amiga_bus_enable_dma_high_i_m2_0__un0_n.BLIF N_205 -1- 1 --1 1 -.names N_295_i.BLIF N_332_i.BLIF N_234_i_1 +.names N_311.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF rw_000_int_0_un1_n 11 1 -.names N_306_1.BLIF rst_dly_i_2__n.BLIF N_306 +.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_282 11 1 -.names N_180_i.BLIF N_292_i.BLIF N_302_0_1 +.names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n 11 1 -.names N_215_1.BLIF rst_dly_i_1__n.BLIF N_215 -11 1 -.names N_180_i.BLIF N_290_i.BLIF N_63_i_1 -11 1 -.names N_221_1.BLIF cpu_est_i_3__n.BLIF N_221 -11 1 -.names N_273_i.BLIF N_275_i.BLIF N_154_i_1 -11 1 -.names N_227_3.BLIF nEXP_SPACE_c.BLIF N_227 -11 1 -.names N_166.BLIF N_327_i.BLIF N_152_i_1 -11 1 -.names N_230_1.BLIF RST_c.BLIF N_230 -11 1 -.names N_155.BLIF N_270_i.BLIF N_148_i_1 -11 1 -.names N_169.BLIF RST_c.BLIF N_319 -11 1 -.names N_155.BLIF N_269_i.BLIF N_144_i_1 -11 1 -.names N_166_i.BLIF RST_c.BLIF N_320 -11 1 -.names N_267_i.BLIF N_324_i.BLIF N_140_i_1 -11 1 -.names N_183.BLIF sm_amiga_i_0__n.BLIF N_267 -11 1 -.names nEXP_SPACE_c.BLIF inst_AS_030_D0.BLIF pos_clk_un6_bg_030_1_n -11 1 -.names N_155_i.BLIF sm_amiga_i_1__n.BLIF N_324 -11 1 -.names N_305_i.BLIF N_350.BLIF N_230_1 -11 1 -.names N_196.BLIF sm_amiga_i_2__n.BLIF N_269 -11 1 -.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_221_1 -11 1 -.names N_197.BLIF sm_amiga_i_4__n.BLIF N_270 -11 1 -.names N_210_i.BLIF rst_dly_i_0__n.BLIF N_215_1 -11 1 -.names N_191.BLIF sm_amiga_i_6__n.BLIF N_327 -11 1 -.names N_163.BLIF N_210_i.BLIF N_306_1 -11 1 -.names N_171.BLIF sm_amiga_i_i_7__n.BLIF N_273 -11 1 -.names N_208_i.BLIF N_206_i.BLIF pos_clk_ipl_1_n -11 1 -.names N_155_i.BLIF SM_AMIGA_0_.BLIF N_275 -11 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_2__un3_n -0 1 -.names CLK_030_H_i.BLIF N_198.BLIF N_290 -11 1 -.names ipl_c_2__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_2__un1_n -11 1 -.names inst_CLK_030_H.BLIF CLK_030_c.BLIF N_292 -11 1 -.names IPL_030DFF_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n -11 1 -.names N_159.BLIF RST_DLY_0_.BLIF N_295 -11 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_1__un3_n -0 1 -.names N_186_i.BLIF rst_dly_i_0__n.BLIF N_332 -11 1 -.names ipl_c_1__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_1__un1_n -11 1 -.names BGACK_030_INT_i.BLIF N_184.BLIF N_333 -11 1 -.names IPL_030DFF_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n -11 1 -.names BGACK_030_INT_i.BLIF N_184_i.BLIF N_334 -11 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_0__un3_n -0 1 -.names N_194.BLIF sm_amiga_i_1__n.BLIF N_335 -11 1 -.names ipl_c_0__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_0__un1_n -11 1 -.names N_157_i.BLIF sm_amiga_i_2__n.BLIF N_336 -11 1 -.names IPL_030DFF_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n -11 1 -.names N_188.BLIF N_305_i.BLIF N_338 -11 1 -.names N_305.BLIF cpu_est_0_3__un3_n -0 1 -.names N_181.BLIF sm_amiga_i_3__n.BLIF N_339 -11 1 -.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c -0 1 -.names cpu_est_3_.BLIF N_305.BLIF cpu_est_0_3__un1_n -11 1 -.names N_163_i.BLIF RST_DLY_2_.BLIF N_350 -11 1 -.names N_192_i.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n +.names N_182.BLIF sm_amiga_i_2__n.BLIF N_284 11 1 .names pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un3_n 0 1 -.names N_161_i.BLIF N_161 -0 1 +.names N_149_i.BLIF N_176.BLIF N_340 +11 1 .names cpu_est_i_1__n.BLIF pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un1_n 11 1 -.names N_159.BLIF N_163_i.BLIF N_213 +.names N_171.BLIF sm_amiga_i_3__n.BLIF N_287 11 1 .names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n 11 1 -.names N_186_i.BLIF rst_dly_i_1__n.BLIF N_214 +.names N_183.BLIF sm_amiga_i_4__n.BLIF N_288 11 1 -.names VPA_c.BLIF VPA_c_i +.names N_149.BLIF cpu_est_0_1__un3_n 0 1 -.names N_305.BLIF cpu_est_0_1__un3_n -0 1 -.names N_197_0.BLIF N_197 -0 1 -.names RST_c.BLIF VPA_c_i.BLIF N_52_0 +.names N_163.BLIF sm_amiga_i_i_7__n.BLIF N_291 11 1 -.names cpu_est_1_.BLIF N_305.BLIF cpu_est_0_1__un1_n +.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c +0 1 +.names cpu_est_1_.BLIF N_149.BLIF cpu_est_0_1__un1_n +11 1 +.names N_150_i.BLIF SM_AMIGA_0_.BLIF N_293 11 1 -.names N_159_0.BLIF N_159 -0 1 -.names DTACK_c.BLIF DTACK_c_i -0 1 .names cpu_est_2_1__n.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n 11 1 -.names N_166.BLIF sm_amiga_i_5__n.BLIF N_326 +.names LDS_000_c.BLIF UDS_000_c.BLIF N_350 11 1 -.names DTACK_c_i.BLIF RST_c.BLIF N_53_0 -11 1 -.names N_305.BLIF cpu_est_0_2__un3_n +.names N_149.BLIF cpu_est_0_2__un3_n 0 1 -.names AS_030_i.BLIF BGACK_000_c.BLIF un21_berr_1 +.names N_158_i.BLIF RST_DLY_2_.BLIF N_355 11 1 -.names ipl_c_0__n.BLIF ipl_c_i_0__n -0 1 -.names cpu_est_2_.BLIF N_305.BLIF cpu_est_0_2__un1_n -11 1 -.names N_181_i.BLIF N_181 -0 1 -.names ipl_c_i_0__n.BLIF RST_c.BLIF N_49_0 +.names cpu_est_2_.BLIF N_149.BLIF cpu_est_0_2__un1_n 11 1 .names cpu_est_2_2__n.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n 11 1 -.names ipl_c_1__n.BLIF ipl_c_i_1__n +.names N_16.BLIF N_16_i 0 1 -.names N_302.BLIF ds_000_dma_0_un3_n +.names SM_AMIGA_6_.BLIF uds_000_int_0_un3_n 0 1 -.names un1_DS_000_ENABLE_0_sqmuxa_i.BLIF un1_DS_000_ENABLE_0_sqmuxa +.names N_16_i.BLIF RST_c.BLIF N_39_0 +11 1 +.names a_c_0__n.BLIF SM_AMIGA_6_.BLIF uds_000_int_0_un1_n +11 1 +.names VPA_c.BLIF VPA_c_i 0 1 -.names ipl_c_i_1__n.BLIF RST_c.BLIF N_50_0 +.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n 11 1 -.names N_301.BLIF N_302.BLIF ds_000_dma_0_un1_n +.names RST_c.BLIF VPA_c_i.BLIF N_52_0 11 1 -.names N_166_i.BLIF RW_c.BLIF N_349 -11 1 -.names ipl_c_2__n.BLIF ipl_c_i_2__n +.names SM_AMIGA_6_.BLIF lds_000_int_0_un3_n 0 1 -.names inst_DS_000_DMA.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n -11 1 -.names LDS_000_c.BLIF UDS_000_c.BLIF N_345 -11 1 -.names ipl_c_i_2__n.BLIF RST_c.BLIF N_51_0 -11 1 -.names N_303.BLIF as_000_dma_0_un3_n +.names N_156_i.BLIF N_156 0 1 -.names inst_RESET_OUT.BLIF RST_c.BLIF N_229 -11 1 -.names N_25.BLIF N_25_i +.names DTACK_c.BLIF DTACK_c_i 0 1 -.names N_180.BLIF N_303.BLIF as_000_dma_0_un1_n +.names pos_clk_un10_sm_amiga_i_n.BLIF SM_AMIGA_6_.BLIF lds_000_int_0_un1_n 11 1 -.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF N_14 -1- 1 --1 1 -.names N_25_i.BLIF RST_c.BLIF N_28_0 +.names N_154.BLIF N_158_i.BLIF N_201 11 1 -.names inst_AS_000_DMA.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n +.names DTACK_c_i.BLIF RST_c.BLIF N_53_0 11 1 -.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_21 -1- 1 --1 1 -.names N_26.BLIF N_26_i +.names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n +11 1 +.names N_82_i.BLIF rst_dly_i_1__n.BLIF N_202 +11 1 +.names N_210.BLIF N_210_i 0 1 .names pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n 0 1 -.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3 -1- 1 --1 1 -.names N_26_i.BLIF RST_c.BLIF N_29_0 -11 1 +.names N_154_0.BLIF N_154 +0 1 +.names N_211.BLIF N_211_i +0 1 .names BGACK_000_c.BLIF pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n 11 1 -.names N_301_0.BLIF N_301 -0 1 -.names N_27.BLIF N_27_i -0 1 +.names AS_030_i.BLIF BGACK_000_c.BLIF un21_berr_1 +11 1 +.names N_210_i.BLIF N_211_i.BLIF N_189_i +11 1 .names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \ bgack_030_int_0_un0_n 11 1 -.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF N_4 -1- 1 --1 1 -.names N_27_i.BLIF RST_c.BLIF N_30_0 +.names N_174_i.BLIF N_174 +0 1 +.names N_160.BLIF N_175_i.BLIF un1_SM_AMIGA_0_sqmuxa_1_0 11 1 -.names N_65.BLIF ds_000_enable_0_un3_n +.names N_66.BLIF ds_000_enable_0_un3_n 0 1 -.names N_303_0.BLIF N_303 +.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_223 +11 1 +.names RW_c.BLIF RW_c_i 0 1 -.names N_222.BLIF N_222_i +.names un1_DS_000_ENABLE_0_sqmuxa.BLIF N_66.BLIF ds_000_enable_0_un1_n +11 1 +.names N_133.BLIF RST_c.BLIF N_221 +11 1 +.names N_175_i.BLIF RW_c_i.BLIF N_311_0 +11 1 +.names inst_DS_000_ENABLE.BLIF ds_000_enable_0_un3_n.BLIF \ +ds_000_enable_0_un0_n +11 1 +.names N_160_i.BLIF RST_c.BLIF N_222 +11 1 +.names N_336.BLIF N_336_i 0 1 -.names un1_DS_000_ENABLE_0_sqmuxa.BLIF N_65.BLIF ds_000_enable_0_un1_n +.names N_126.BLIF size_dma_0_0__un3_n +0 1 +.names N_132.BLIF RST_c.BLIF N_219 +11 1 +.names N_244.BLIF N_244_i +0 1 +.names pos_clk_size_dma_6_0__n.BLIF N_126.BLIF size_dma_0_0__un1_n +11 1 +.names N_174_i.BLIF RST_c.BLIF N_220 +11 1 +.names SIZE_DMA_0_.BLIF size_dma_0_0__un3_n.BLIF size_dma_0_0__un0_n +11 1 +.names pos_clk_un6_bgack_000_0_n.BLIF pos_clk_un6_bgack_000_n +0 1 +.names cpu_est_3_.BLIF cpu_est_i_0__n.BLIF N_314_0 +11 1 +.names N_126.BLIF size_dma_0_1__un3_n +0 1 +.names AS_000_c.BLIF N_150_i.BLIF N_359 +11 1 +.names cpu_est_i_1__n.BLIF cpu_est_i_2__n.BLIF N_159_i +11 1 +.names pos_clk_size_dma_6_1__n.BLIF N_126.BLIF size_dma_0_1__un1_n 11 1 .names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF N_8 1- 1 -1 1 -.names N_223.BLIF N_223_i +.names inst_VMA_INTreg.BLIF VMA_INT_i 0 1 -.names inst_DS_000_ENABLE.BLIF ds_000_enable_0_un3_n.BLIF \ -ds_000_enable_0_un0_n +.names SIZE_DMA_1_.BLIF size_dma_0_1__un3_n.BLIF size_dma_0_1__un0_n 11 1 -.names pos_clk_un6_bgack_000_0_n.BLIF pos_clk_un6_bgack_000_n +.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF N_14 +1- 1 +-1 1 +.names N_352.BLIF N_352_i 0 1 -.names N_222_i.BLIF N_223_i.BLIF N_192_i +.names N_233.BLIF ipl_030_0_0__un3_n +0 1 +.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_21 +1- 1 +-1 1 +.names N_353.BLIF N_353_i +0 1 +.names IPL_030DFF_0_reg.BLIF N_233.BLIF ipl_030_0_0__un1_n 11 1 -.names SM_AMIGA_6_.BLIF uds_000_int_0_un3_n -0 1 .names ds_000_enable_0_un1_n.BLIF ds_000_enable_0_un0_n.BLIF N_9 1- 1 -1 1 -.names N_231.BLIF N_231_i +.names N_293.BLIF N_293_i 0 1 -.names a_c_0__n.BLIF SM_AMIGA_6_.BLIF uds_000_int_0_un1_n +.names ipl_c_0__n.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n 11 1 -.names N_65_0.BLIF N_65 +.names un1_DS_000_ENABLE_0_sqmuxa_0.BLIF un1_DS_000_ENABLE_0_sqmuxa 0 1 -.names N_237.BLIF N_237_i +.names N_293_i.BLIF SM_AMIGA_i_7_.BLIF N_175_i +11 1 +.names N_233.BLIF ipl_030_0_1__un3_n 0 1 -.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n -11 1 -.names CYCLE_DMA_0_.BLIF N_155_i.BLIF N_217 -11 1 -.names SM_AMIGA_6_.BLIF lds_000_int_0_un3_n +.names N_66_0.BLIF N_66 0 1 -.names cycle_dma_i_0__n.BLIF N_155.BLIF N_216 +.names N_176_i_1.BLIF N_353_i.BLIF N_176_i 11 1 -.names N_342.BLIF N_342_i +.names IPL_030DFF_1_reg.BLIF N_233.BLIF ipl_030_0_1__un1_n +11 1 +.names N_171_i.BLIF N_171 0 1 -.names pos_clk_un10_sm_amiga_i_n.BLIF SM_AMIGA_6_.BLIF lds_000_int_0_un1_n +.names ipl_c_1__n.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n 11 1 -.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_248 +.names N_160_i.BLIF RW_c.BLIF N_354 11 1 -.names N_341.BLIF N_341_i +.names N_198.BLIF N_198_i 0 1 -.names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n -11 1 -.names N_198_0.BLIF N_198 -0 1 -.names inst_BGACK_030_INTreg.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un3_n -0 1 -.names inst_AS_000_DMA.BLIF RW_000_i.BLIF N_291 -11 1 -.names cpu_est_3_.BLIF cpu_est_i_0__n.BLIF N_160_0 -11 1 -.names inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INTreg.BLIF \ -un1_amiga_bus_enable_dma_high_i_m2_0__un1_n -11 1 -.names AS_000_c.BLIF N_155_i.BLIF N_353 -11 1 -.names cpu_est_i_1__n.BLIF cpu_est_i_2__n.BLIF N_164_i -11 1 -.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ -un1_amiga_bus_enable_dma_high_i_m2_0__un3_n.BLIF \ -un1_amiga_bus_enable_dma_high_i_m2_0__un0_n -11 1 -.names N_256_1.BLIF N_256_2.BLIF N_256 -11 1 -.names inst_VMA_INTreg.BLIF VMA_INT_i -0 1 -.names N_199.BLIF amiga_bus_enable_dma_high_0_un3_n +.names N_233.BLIF ipl_030_0_2__un3_n 0 1 .names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF N_18 1- 1 -1 1 -.names N_347.BLIF N_347_i +.names N_197.BLIF N_197_i 0 1 -.names N_79_i.BLIF N_199.BLIF amiga_bus_enable_dma_high_0_un1_n +.names IPL_030DFF_2_reg.BLIF N_233.BLIF ipl_030_0_2__un1_n 11 1 .names pos_clk_un9_clk_000_pe_0_n.BLIF pos_clk_un9_clk_000_pe_n 0 1 -.names N_348.BLIF N_348_i +.names N_196.BLIF N_196_i 0 1 -.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ -amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n +.names ipl_c_2__n.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n 11 1 .names cpu_est_2_0_1__n.BLIF cpu_est_2_1__n 0 1 -.names N_188_i_1.BLIF N_348_i.BLIF N_188_i +.names N_149_i.BLIF SM_AMIGA_5_.BLIF N_183_0 11 1 -.names pos_clk_un9_bg_030_n.BLIF bg_000_0_un3_n +.names N_185.BLIF a0_dma_0_un3_n 0 1 .names cpu_est_2_0_2__n.BLIF cpu_est_2_2__n 0 1 -.names BGACK_030_INT_i.BLIF RST_c.BLIF N_245_0 +.names N_182_0_1.BLIF SM_AMIGA_3_.BLIF N_182_0 11 1 -.names BG_030_c.BLIF pos_clk_un9_bg_030_n.BLIF bg_000_0_un1_n +.names pos_clk_a0_dma_3_n.BLIF N_185.BLIF a0_dma_0_un1_n 11 1 -.names N_159.BLIF N_350.BLIF N_209 +.names N_154.BLIF N_355.BLIF N_197 11 1 -.names N_155_i.BLIF SM_AMIGA_2_.BLIF N_194_0 -11 1 -.names BG_000DFFreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n -11 1 -.names N_305.BLIF rst_dly_i_2__n.BLIF N_211 -11 1 -.names N_196_0_1.BLIF SM_AMIGA_3_.BLIF N_196_0 -11 1 -.names N_113.BLIF size_dma_0_0__un3_n -0 1 -.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_220 -11 1 -.names pos_clk_size_dma_6_0__n.BLIF N_113.BLIF size_dma_0_0__un1_n -11 1 -.names N_162.BLIF cpu_est_2_.BLIF N_222 -11 1 -.names N_211.BLIF N_211_i -0 1 -.names SIZE_DMA_0_.BLIF size_dma_0_0__un3_n.BLIF size_dma_0_0__un0_n -11 1 -.names N_162_i.BLIF N_162 -0 1 -.names N_209.BLIF N_209_i -0 1 -.names N_113.BLIF size_dma_0_1__un3_n -0 1 -.names N_193.BLIF cpu_est_i_2__n.BLIF N_224 -11 1 -.names N_306.BLIF N_306_i -0 1 -.names pos_clk_size_dma_6_1__n.BLIF N_113.BLIF size_dma_0_1__un1_n -11 1 -.names N_193_0.BLIF N_193 -0 1 -.names cpu_est_3_.BLIF cpu_est_i_1__n.BLIF N_193_0 -11 1 -.names SIZE_DMA_1_.BLIF size_dma_0_1__un3_n.BLIF size_dma_0_1__un0_n -11 1 -.names N_190.BLIF cpu_est_2_.BLIF N_225 -11 1 -.names cpu_est_1_.BLIF cpu_est_i_3__n.BLIF N_190_0 -11 1 -.names N_297.BLIF as_030_000_sync_0_un3_n -0 1 -.names N_190_0.BLIF N_190 -0 1 -.names N_157_i.BLIF SM_AMIGA_1_.BLIF N_183_i -11 1 -.names AS_030_c.BLIF N_297.BLIF as_030_000_sync_0_un1_n -11 1 -.names N_305_i.BLIF N_350_i_0.BLIF N_346 -11 1 -.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_162_i -11 1 -.names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF \ -as_030_000_sync_0_un0_n -11 1 -.names N_162_i.BLIF cpu_est_i_2__n.BLIF N_352 -11 1 -.names N_346.BLIF N_346_i -0 1 -.names un1_SM_AMIGA_0_sqmuxa_1.BLIF rw_000_int_0_un3_n -0 1 -.names N_219_1.BLIF N_219_2.BLIF N_219 -11 1 -.names N_346_i.BLIF RST_c.BLIF N_159_0 -11 1 -.names pos_clk_rw_000_int_5_n.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF \ -rw_000_int_0_un1_n -11 1 -.names N_218_1.BLIF N_218_2.BLIF N_218 -11 1 -.names CLK_000_D_1_.BLIF clk_000_d_i_0__n.BLIF N_305_i -11 1 -.names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n -11 1 -.names N_183_i.BLIF N_183 -0 1 -.names N_350_i_0.BLIF RST_c.BLIF N_210_i -11 1 -.names N_199.BLIF rw_000_dma_0_un3_n -0 1 -.names N_196_0.BLIF N_196 -0 1 -.names N_225.BLIF N_225_i -0 1 -.names N_300.BLIF N_199.BLIF rw_000_dma_0_un1_n -11 1 -.names N_188_i.BLIF N_188 -0 1 -.names N_224.BLIF N_224_i -0 1 -.names inst_RW_000_DMA.BLIF rw_000_dma_0_un3_n.BLIF rw_000_dma_0_un0_n -11 1 -.names N_194_0.BLIF N_194 -0 1 -.names N_224_i.BLIF N_225_i.BLIF N_296_i -11 1 -.names N_199.BLIF a0_dma_0_un3_n -0 1 -.names N_347_1.BLIF N_347_2.BLIF N_347 -11 1 -.names N_352.BLIF N_352_i -0 1 -.names pos_clk_a0_dma_3_n.BLIF N_199.BLIF a0_dma_0_un1_n -11 1 -.names DTACK_D0_i.BLIF inst_VPA_D.BLIF N_348 -11 1 -.names N_222_i.BLIF N_352_i.BLIF cpu_est_2_0_2__n +.names cpu_est_3_.BLIF cpu_est_i_1__n.BLIF N_180_0 11 1 .names inst_A0_DMA.BLIF a0_dma_0_un3_n.BLIF a0_dma_0_un0_n 11 1 -.names N_160_0.BLIF N_160 -0 1 -.names N_220.BLIF N_220_i -0 1 -.names N_199.BLIF amiga_bus_enable_dma_low_0_un3_n -0 1 -.names N_305.BLIF cpu_est_i_0__n.BLIF N_341 +.names N_149.BLIF rst_dly_i_2__n.BLIF N_198 11 1 -.names N_221.BLIF N_221_i +.names cpu_est_1_.BLIF cpu_est_i_3__n.BLIF N_178_0 +11 1 +.names N_185.BLIF amiga_bus_enable_dma_low_0_un3_n 0 1 -.names N_78_i.BLIF N_199.BLIF amiga_bus_enable_dma_low_0_un1_n +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_208 11 1 -.names N_305_i.BLIF cpu_est_0_.BLIF N_342 +.names N_149.BLIF RST_c.BLIF N_82_i 11 1 -.names N_220_i.BLIF N_221_i.BLIF cpu_est_2_0_1__n +.names N_114_i.BLIF N_185.BLIF amiga_bus_enable_dma_low_0_un1_n +11 1 +.names N_315.BLIF cpu_est_2_.BLIF N_210 +11 1 +.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_315_i 11 1 .names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF \ amiga_bus_enable_dma_low_0_un3_n.BLIF amiga_bus_enable_dma_low_0_un0_n 11 1 -.names N_183_i.BLIF RST_c.BLIF N_231 -11 1 -.names N_219.BLIF N_219_i +.names N_315_i.BLIF N_315 0 1 -.names N_165.BLIF RST_c.BLIF N_237 -11 1 -.names N_218.BLIF N_218_i +.names N_351.BLIF N_351_i 0 1 -.names N_160.BLIF cpu_est_i_2__n.BLIF N_223 -11 1 -.names N_218_i.BLIF N_219_i.BLIF pos_clk_un9_clk_000_pe_0_n -11 1 -.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_27 -1- 1 --1 1 -.names CLK_000_D_2_.BLIF clk_000_d_i_2__n +.names N_185.BLIF amiga_bus_enable_dma_high_0_un3_n 0 1 -.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF N_26 -1- 1 --1 1 -.names CLK_000_D_3_.BLIF clk_000_d_i_2__n.BLIF N_157_i +.names N_180.BLIF cpu_est_i_2__n.BLIF N_212 +11 1 +.names N_351_i.BLIF RST_c.BLIF N_154_0 +11 1 +.names N_115_i.BLIF N_185.BLIF amiga_bus_enable_dma_high_0_un1_n +11 1 +.names N_180_0.BLIF N_180 +0 1 +.names CLK_000_D_1_.BLIF clk_000_d_i_0__n.BLIF N_149_i +11 1 +.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ +amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n +11 1 +.names N_178.BLIF cpu_est_2_.BLIF N_213 +11 1 +.names N_355_i_0.BLIF RST_c.BLIF N_207_i +11 1 +.names pos_clk_un9_bg_030_n.BLIF bg_000_0_un3_n +0 1 +.names N_178_0.BLIF N_178 +0 1 +.names N_228.BLIF N_228_i +0 1 +.names BG_030_c.BLIF pos_clk_un9_bg_030_n.BLIF bg_000_0_un1_n +11 1 +.names N_160.BLIF sm_amiga_i_5__n.BLIF N_228 +11 1 +.names BG_000DFFreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n +11 1 +.names N_182_0.BLIF N_182 +0 1 +.names N_213.BLIF N_213_i +0 1 +.names N_246.BLIF ds_000_dma_0_un3_n +0 1 +.names N_176_i.BLIF N_176 +0 1 +.names N_212.BLIF N_212_i +0 1 +.names pos_clk_ds_000_dma_4_n.BLIF N_246.BLIF ds_000_dma_0_un1_n +11 1 +.names N_183_0.BLIF N_183 +0 1 +.names N_212_i.BLIF N_213_i.BLIF N_309_i +11 1 +.names inst_DS_000_DMA.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n +11 1 +.names N_149_i.BLIF N_355_i_0.BLIF N_351 +11 1 +.names N_357.BLIF N_357_i +0 1 +.names N_245.BLIF as_000_dma_0_un3_n +0 1 +.names N_315_i.BLIF cpu_est_i_2__n.BLIF N_357 +11 1 +.names N_210_i.BLIF N_357_i.BLIF cpu_est_2_0_2__n +11 1 +.names pos_clk_un21_bgack_030_int_i_0_n.BLIF N_245.BLIF as_000_dma_0_un1_n +11 1 +.names N_206_1.BLIF N_206_2.BLIF N_206 +11 1 +.names N_208.BLIF N_208_i +0 1 +.names inst_AS_000_DMA.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n +11 1 +.names N_205_1.BLIF N_205_2.BLIF N_205 +11 1 +.names N_209.BLIF N_209_i +0 1 +.names N_310.BLIF as_030_000_sync_0_un3_n +0 1 +.names N_352_1.BLIF N_352_2.BLIF N_352 +11 1 +.names N_208_i.BLIF N_209_i.BLIF cpu_est_2_0_1__n +11 1 +.names AS_030_c.BLIF N_310.BLIF as_030_000_sync_0_un1_n +11 1 +.names DTACK_D0_i.BLIF inst_VPA_D.BLIF N_353 +11 1 +.names N_206.BLIF N_206_i +0 1 +.names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF \ +as_030_000_sync_0_un0_n +11 1 +.names N_314_0.BLIF N_314 +0 1 +.names N_205.BLIF N_205_i +0 1 +.names N_185.BLIF rw_000_dma_0_un3_n +0 1 +.names N_149_i.BLIF cpu_est_0_.BLIF N_244 +11 1 +.names N_205_i.BLIF N_206_i.BLIF pos_clk_un9_clk_000_pe_0_n +11 1 +.names pos_clk_rw_000_dma_3_n.BLIF N_185.BLIF rw_000_dma_0_un1_n +11 1 +.names N_149.BLIF cpu_est_i_0__n.BLIF N_336 11 1 -.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF N_25 -1- 1 --1 1 .names N_18.BLIF N_18_i 0 1 -.names un1_amiga_bus_enable_low.BLIF un1_amiga_bus_enable_low_i +.names inst_RW_000_DMA.BLIF rw_000_dma_0_un3_n.BLIF rw_000_dma_0_un0_n +11 1 +.names N_311_0.BLIF N_311 0 1 .names N_18_i.BLIF RST_c.BLIF N_37_0 11 1 +.names un1_SM_AMIGA_0_sqmuxa_1_0.BLIF un1_SM_AMIGA_0_sqmuxa_1 +0 1 +.names N_150_i.BLIF SM_AMIGA_4_.BLIF N_171_i +11 1 +.names N_314.BLIF cpu_est_i_2__n.BLIF N_211 +11 1 +.names N_354.BLIF N_354_i +0 1 +.names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF N_16 +1- 1 +-1 1 +.names N_171.BLIF N_354_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_0 +11 1 +.names un1_amiga_bus_enable_low.BLIF un1_amiga_bus_enable_low_i +0 1 +.names AS_030_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_0.BLIF N_66_0 +11 1 .names un21_fpu_cs.BLIF un21_fpu_cs_i 0 1 -.names cpu_est_2_.BLIF cpu_est_i_2__n -0 1 -.names N_217.BLIF N_217_i -0 1 -.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n -0 1 -.names N_216.BLIF N_216_i -0 1 -.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n -0 1 -.names CLK_030_c.BLIF CLK_030_c_i -0 1 -.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n -0 1 -.names AS_000_DMA_i.BLIF CLK_030_c_i.BLIF N_198_0 -11 1 -.names cpu_est_0_.BLIF cpu_est_i_0__n -0 1 -.names N_155_i.BLIF SM_AMIGA_6_.BLIF N_166_i -11 1 -.names inst_VPA_D.BLIF VPA_D_i -0 1 -.names CLK_000_D_0_.BLIF clk_000_d_i_1__n.BLIF N_155_i -11 1 -.names inst_DTACK_D0.BLIF DTACK_D0_i -0 1 -.names CLK_030_c_i.BLIF N_180_i.BLIF N_303_0 -11 1 -.names AS_030_c.BLIF AS_030_i -0 1 -.names N_291.BLIF N_291_i -0 1 -.names inst_DSACK1_INT.BLIF DSACK1_INT_i -0 1 -.names N_180_i.BLIF N_291_i.BLIF N_301_0 -11 1 -.names cpu_est_3_.BLIF cpu_est_i_3__n -0 1 -.names N_256.BLIF N_256_i -0 1 -.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n -0 1 -.names N_248.BLIF N_248_i -0 1 -.names cpu_est_1_.BLIF cpu_est_i_1__n -0 1 -.names N_248_i.BLIF N_256_i.BLIF AMIGA_BUS_DATA_DIR_c_0 -11 1 -.names CLK_000_D_1_.BLIF clk_000_d_i_1__n -0 1 -.names N_353.BLIF N_353_i -0 1 -.names N_350.BLIF N_350_i_0 -0 1 -.names BGACK_000_c.BLIF N_353_i.BLIF pos_clk_un6_bgack_000_0_n -11 1 -.names RST_DLY_2_.BLIF rst_dly_i_2__n -0 1 -.names AS_030_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_i.BLIF N_65_0 -11 1 -.names nEXP_SPACE_c.BLIF nEXP_SPACE_i -0 1 -.names N_3.BLIF N_3_i -0 1 -.names AS_000_c.BLIF AS_000_i -0 1 -.names N_3_i.BLIF RST_c.BLIF N_45_0 -11 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i -0 1 -.names N_4.BLIF N_4_i -0 1 -.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n -0 1 -.names N_4_i.BLIF RST_c.BLIF N_44_0 -11 1 -.names CLK_000_D_0_.BLIF clk_000_d_i_0__n -0 1 -.names N_8.BLIF N_8_i -0 1 -.names RW_000_c.BLIF RW_000_i -0 1 -.names N_8_i.BLIF RST_c.BLIF N_42_0 -11 1 -.names inst_CLK_030_H.BLIF CLK_030_H_i -0 1 .names inst_UDS_000_INT.BLIF UDS_000_INT_i 0 1 -.names inst_AS_000_DMA.BLIF AS_000_DMA_i +.names cpu_est_2_.BLIF cpu_est_i_2__n 0 1 .names inst_DS_000_ENABLE.BLIF UDS_000_INT_i.BLIF un1_UDS_000_INT_0 11 1 -.names CYCLE_DMA_0_.BLIF cycle_dma_i_0__n +.names cpu_est_0_.BLIF cpu_est_i_0__n 0 1 .names inst_LDS_000_INT.BLIF LDS_000_INT_i 0 1 -.names inst_DS_000_DMA.BLIF DS_000_DMA_i +.names inst_VPA_D.BLIF VPA_D_i 0 1 .names inst_DS_000_ENABLE.BLIF LDS_000_INT_i.BLIF un1_LDS_000_INT_0 11 1 -.names inst_RESET_OUT.BLIF RESET_OUT_i +.names inst_DTACK_D0.BLIF DTACK_D0_i 0 1 .names N_21.BLIF N_21_i 0 1 -.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n +.names cpu_est_3_.BLIF cpu_est_i_3__n 0 1 .names N_21_i.BLIF RST_c.BLIF N_34_0 11 1 -.names FPU_SENSE_c.BLIF FPU_SENSE_i +.names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n 0 1 .names N_14.BLIF N_14_i 0 1 -.names IPL_D0_0_.BLIF ipl_c_0__n.BLIF G_107 -01 1 -10 1 -11 0 -00 0 -.names IPL_D0_1_.BLIF ipl_c_1__n.BLIF G_108 -01 1 -10 1 -11 0 -00 0 -.names IPL_D0_2_.BLIF ipl_c_2__n.BLIF G_109 -01 1 -10 1 -11 0 -00 0 -.names CYCLE_DMA_1_.BLIF N_217.BLIF pos_clk_CYCLE_DMA_5_1_i_x2 -01 1 -10 1 -11 0 -00 0 +.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +0 1 +.names N_14_i.BLIF RST_c.BLIF N_41_0 +11 1 +.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n +0 1 +.names N_8.BLIF N_8_i +0 1 +.names cpu_est_1_.BLIF cpu_est_i_1__n +0 1 +.names N_8_i.BLIF RST_c.BLIF N_42_0 +11 1 +.names CLK_000_D_1_.BLIF clk_000_d_i_1__n +0 1 +.names a_c_0__n.BLIF a_c_i_0__n +0 1 +.names N_355.BLIF N_355_i_0 +0 1 +.names size_c_1__n.BLIF size_c_i_1__n +0 1 +.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n +0 1 +.names pos_clk_un10_sm_amiga_i_1_n.BLIF size_c_i_1__n.BLIF \ +pos_clk_un10_sm_amiga_i_n +11 1 +.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n +0 1 +.names N_359.BLIF N_359_i +0 1 +.names RST_DLY_0_.BLIF rst_dly_i_0__n +0 1 +.names BGACK_000_c.BLIF N_359_i.BLIF pos_clk_un6_bgack_000_0_n +11 1 +.names RST_DLY_2_.BLIF rst_dly_i_2__n +0 1 +.names N_220.BLIF N_220_i +0 1 +.names a_decode_c_19__n.BLIF a_decode_i_19__n +0 1 +.names N_219.BLIF N_219_i +0 1 +.names a_decode_c_18__n.BLIF a_decode_i_18__n +0 1 +.names a_decode_c_16__n.BLIF a_decode_i_16__n +0 1 +.names N_222.BLIF N_222_i +0 1 +.names RW_000_c.BLIF RW_000_i +0 1 +.names N_221.BLIF N_221_i +0 1 +.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n +0 1 +.names AS_030_c.BLIF AS_030_i +0 1 +.names N_223.BLIF N_223_i +0 1 +.names inst_AS_000_INT.BLIF AS_000_INT_i +0 1 +.names N_224.BLIF N_224_i +0 1 +.names inst_DSACK1_INT.BLIF DSACK1_INT_i +0 1 +.names N_223_i.BLIF N_224_i.BLIF AMIGA_BUS_DATA_DIR_c_0 +11 1 +.names CLK_000_D_0_.BLIF clk_000_d_i_0__n +0 1 +.names CLK_000_D_0_.BLIF clk_000_d_i_1__n.BLIF N_150_i +11 1 +.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n +0 1 +.names N_156_i_4.BLIF N_156_i_3.BLIF N_156_i +11 1 +.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n +0 1 +.names N_150_i.BLIF SM_AMIGA_6_.BLIF N_160_i +11 1 +.names FPU_SENSE_c.BLIF FPU_SENSE_i +0 1 +.names N_149_i.BLIF SM_AMIGA_1_.BLIF N_174_i +11 1 +.names RST_DLY_1_.BLIF rst_dly_i_1__n +0 1 +.names RST_DLY_0_.BLIF RST_DLY_1_.BLIF N_158_i +11 1 +.names inst_AS_030_D0.BLIF AS_030_D0_i +0 1 +.names N_201.BLIF N_201_i +0 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i +0 1 +.names N_202.BLIF N_202_i +0 1 +.names nEXP_SPACE_c.BLIF nEXP_SPACE_i +0 1 +.names N_203.BLIF N_203_i +0 1 +.names inst_RESET_OUT.BLIF RESET_OUT_i +0 1 .names CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF \ -pos_clk_un21_bgack_030_int_i_i_a2_i_x2 +pos_clk_un21_bgack_030_int_i_0_o3_0_x2 +01 1 +10 1 +11 0 +00 0 +.names IPL_D0_0_.BLIF ipl_c_0__n.BLIF pos_clk_un1_ipl_i_0_x2 +01 1 +10 1 +11 0 +00 0 +.names IPL_D0_1_.BLIF ipl_c_1__n.BLIF pos_clk_un1_ipl_i_0_x2_0 +01 1 +10 1 +11 0 +00 0 +.names IPL_D0_2_.BLIF ipl_c_2__n.BLIF pos_clk_un1_ipl_i_0_x2_1 +01 1 +10 1 +11 0 +00 0 +.names CYCLE_DMA_1_.BLIF N_199.BLIF pos_clk_CYCLE_DMA_5_1_i_0_x2 01 1 10 1 11 0 @@ -1538,13 +1534,13 @@ pos_clk_un21_bgack_030_int_i_i_a2_i_x2 .names un21_fpu_cs_i.BLIF FPU_CS 1 1 0 0 -.names N_165_i.BLIF DSACK1 +.names N_132_i.BLIF DSACK1 1 1 0 0 .names vcc_n_n.BLIF AVEC 1 1 0 0 -.names N_296_i.BLIF E +.names N_309_i.BLIF E 1 1 0 0 .names inst_VMA_INTreg.BLIF VMA @@ -1562,7 +1558,7 @@ pos_clk_un21_bgack_030_int_i_i_a2_i_x2 .names un1_amiga_bus_enable_low_i.BLIF AMIGA_BUS_ENABLE_LOW 1 1 0 0 -.names N_205.BLIF AMIGA_BUS_ENABLE_HIGH +.names un10_amiga_bus_enable_high_i.BLIF AMIGA_BUS_ENABLE_HIGH 1 1 0 0 .names un10_ciin.BLIF CIIN @@ -1574,6 +1570,15 @@ pos_clk_un21_bgack_030_int_i_i_a2_i_x2 .names IPL_030DFF_0_reg.BLIF IPL_030_0_ 1 1 0 0 +.names CLK_OSZI_c.BLIF IPL_D0_0_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF IPL_D0_1_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF IPL_D0_2_.C +1 1 +0 0 .names CLK_OSZI_c.BLIF SM_AMIGA_i_7_.C 1 1 0 0 @@ -1598,6 +1603,15 @@ pos_clk_un21_bgack_030_int_i_i_a2_i_x2 .names CLK_OSZI_c.BLIF SM_AMIGA_0_.C 1 1 0 0 +.names CLK_OSZI_c.BLIF cpu_est_0_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF cpu_est_1_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF cpu_est_2_.C +1 1 +0 0 .names CLK_OSZI_c.BLIF cpu_est_3_.C 1 1 0 0 @@ -1610,13 +1624,7 @@ pos_clk_un21_bgack_030_int_i_i_a2_i_x2 .names CLK_OSZI_c.BLIF IPL_030DFF_2_reg.C 1 1 0 0 -.names CLK_OSZI_c.BLIF IPL_D0_0_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF IPL_D0_1_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF IPL_D0_2_.C +.names CLK_OSZI_c.BLIF RST_DLY_2_.C 1 1 0 0 .names CLK_000.BLIF CLK_000_D_0_.D @@ -1649,12 +1657,6 @@ pos_clk_un21_bgack_030_int_i_i_a2_i_x2 .names CLK_OSZI_c.BLIF CLK_000_D_4_.C 1 1 0 0 -.names CLK_000_D_4_.BLIF CLK_000_D_5_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_D_5_.C -1 1 -0 0 .names CLK_OSZI_c.BLIF CYCLE_DMA_0_.C 1 1 0 0 @@ -1667,22 +1669,25 @@ pos_clk_un21_bgack_030_int_i_i_a2_i_x2 .names CLK_OSZI_c.BLIF SIZE_DMA_1_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF cpu_est_0_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF cpu_est_1_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF cpu_est_2_.C -1 1 -0 0 .names CLK_OSZI_c.BLIF RST_DLY_0_.C 1 1 0 0 .names CLK_OSZI_c.BLIF RST_DLY_1_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF RST_DLY_2_.C +.names CLK_OSZI_c.BLIF inst_RW_000_INT.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C 1 1 0 0 .names CLK_OSZI_c.BLIF inst_DS_000_DMA.C @@ -1733,21 +1738,6 @@ pos_clk_un21_bgack_030_int_i_i_a2_i_x2 .names CLK_OSZI_c.BLIF inst_VMA_INTreg.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_RW_000_INT.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C -1 1 -0 0 .names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C 1 1 0 0 @@ -1775,7 +1765,7 @@ pos_clk_un21_bgack_030_int_i_i_a2_i_x2 .names un7_as_030_i.BLIF AS_030 1 1 0 0 -.names N_169_i.BLIF AS_000 +.names N_133_i.BLIF AS_000 1 1 0 0 .names inst_RW_000_INT.BLIF RW_000 @@ -1985,7 +1975,7 @@ pos_clk_un21_bgack_030_int_i_i_a2_i_x2 .names A_DECODE_2_.BLIF a_decode_2__n 1 1 0 0 -.names N_139.BLIF AS_030.OE +.names N_313_i.BLIF AS_030.OE 1 1 0 0 .names un1_as_000_i.BLIF AS_000.OE @@ -2000,46 +1990,46 @@ pos_clk_un21_bgack_030_int_i_i_a2_i_x2 .names un1_as_000_i.BLIF LDS_000.OE 1 1 0 0 -.names N_299_i.BLIF SIZE_0_.OE +.names N_186_i.BLIF SIZE_0_.OE 1 1 0 0 -.names N_299_i.BLIF SIZE_1_.OE +.names N_186_i.BLIF SIZE_1_.OE 1 1 0 0 -.names N_139.BLIF AHIGH_24_.OE +.names N_313_i.BLIF AHIGH_24_.OE 1 1 0 0 -.names N_139.BLIF AHIGH_25_.OE +.names N_313_i.BLIF AHIGH_25_.OE 1 1 0 0 -.names N_139.BLIF AHIGH_26_.OE +.names N_313_i.BLIF AHIGH_26_.OE 1 1 0 0 -.names N_139.BLIF AHIGH_27_.OE +.names N_313_i.BLIF AHIGH_27_.OE 1 1 0 0 -.names N_139.BLIF AHIGH_28_.OE +.names N_313_i.BLIF AHIGH_28_.OE 1 1 0 0 -.names N_139.BLIF AHIGH_29_.OE +.names N_313_i.BLIF AHIGH_29_.OE 1 1 0 0 -.names N_139.BLIF AHIGH_30_.OE +.names N_313_i.BLIF AHIGH_30_.OE 1 1 0 0 -.names N_139.BLIF AHIGH_31_.OE +.names N_313_i.BLIF AHIGH_31_.OE 1 1 0 0 -.names N_139.BLIF A_0_.OE +.names N_313_i.BLIF A_0_.OE 1 1 0 0 .names un21_berr.BLIF BERR.OE 1 1 0 0 -.names N_141.BLIF RW.OE +.names un1_rw_i.BLIF RW.OE 1 1 0 0 -.names N_139.BLIF DS_030.OE +.names N_313_i.BLIF DS_030.OE 1 1 0 0 .names nEXP_SPACE_c.BLIF DSACK1.OE @@ -2048,7 +2038,7 @@ pos_clk_un21_bgack_030_int_i_i_a2_i_x2 .names RESET_OUT_i.BLIF RESET.OE 1 1 0 0 -.names N_260.BLIF CIIN.OE +.names N_62.BLIF CIIN.OE 1 1 0 0 .end diff --git a/Logic/68030_tk.bl3 b/Logic/68030_tk.bl3 index 8ac2210..8a57165 100644 --- a/Logic/68030_tk.bl3 +++ b/Logic/68030_tk.bl3 @@ -1,24 +1,24 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Thu Oct 06 22:04:11 2016 +#$ DATE Sat Oct 15 23:48:24 2016 #$ MODULE 68030_tk #$ PINS 61 SIZE_1_ AHIGH_31_ A_DECODE_23_ IPL_030_2_ IPL_2_ FC_1_ AS_030 AS_000 RW_000 \ -# DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 SIZE_0_ CLK_030 \ -# AHIGH_30_ CLK_000 AHIGH_29_ CLK_OSZI AHIGH_28_ CLK_DIV_OUT AHIGH_27_ CLK_EXP AHIGH_26_ \ -# FPU_CS AHIGH_25_ FPU_SENSE AHIGH_24_ DSACK1 A_DECODE_22_ DTACK A_DECODE_21_ AVEC \ -# A_DECODE_20_ E A_DECODE_19_ VPA A_DECODE_18_ VMA A_DECODE_17_ RST A_DECODE_16_ RESET RW \ -# AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH \ -# CIIN A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ IPL_0_ FC_0_ A_1_ -#$ NODES 56 inst_BGACK_030_INTreg inst_VMA_INTreg cpu_est_2_ cpu_est_3_ cpu_est_0_ \ -# cpu_est_1_ inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_000_SYNC \ -# inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ \ -# inst_VPA_D CLK_000_D_2_ CLK_000_D_4_ inst_DTACK_D0 inst_RESET_OUT CLK_000_D_1_ \ -# CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_D IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ \ -# CLK_000_D_3_ CLK_000_D_5_ inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_1_ \ -# inst_UDS_000_INT inst_DS_000_ENABLE inst_LDS_000_INT SM_AMIGA_6_ SM_AMIGA_4_ \ -# SM_AMIGA_0_ SIZE_DMA_0_ SIZE_DMA_1_ inst_RW_000_INT inst_RW_000_DMA RST_DLY_0_ \ -# RST_DLY_1_ RST_DLY_2_ inst_A0_DMA inst_CLK_030_H inst_DSACK1_INT inst_AS_000_INT \ -# SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ BG_000DFFreg CLK_OUT_INTreg \ -# IPL_030DFF_0_reg IPL_030DFF_1_reg IPL_030DFF_2_reg +# DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BG_000 SIZE_0_ BGACK_030 AHIGH_30_ \ +# BGACK_000 AHIGH_29_ CLK_030 AHIGH_28_ CLK_000 AHIGH_27_ CLK_OSZI AHIGH_26_ CLK_DIV_OUT \ +# AHIGH_25_ CLK_EXP AHIGH_24_ FPU_CS A_DECODE_22_ FPU_SENSE A_DECODE_21_ DSACK1 \ +# A_DECODE_20_ DTACK A_DECODE_19_ AVEC A_DECODE_18_ E A_DECODE_17_ VPA A_DECODE_16_ VMA \ +# RST RESET RW AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ +# AMIGA_BUS_ENABLE_HIGH CIIN A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ IPL_0_ FC_0_ A_1_ +#$ NODES 55 inst_BGACK_030_INTreg inst_VMA_INTreg cpu_est_2_ cpu_est_3_ cpu_est_0_ \ +# cpu_est_1_ inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_AMIGA_BUS_ENABLE_DMA_LOW \ +# inst_AS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA \ +# inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ inst_VPA_D CLK_000_D_3_ inst_DTACK_D0 \ +# inst_RESET_OUT CLK_000_D_1_ CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_D \ +# IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ CLK_000_D_4_ inst_LDS_000_INT \ +# inst_DS_000_ENABLE inst_UDS_000_INT SM_AMIGA_6_ SM_AMIGA_4_ SM_AMIGA_1_ SM_AMIGA_0_ \ +# SIZE_DMA_0_ SIZE_DMA_1_ inst_RW_000_INT inst_RW_000_DMA RST_DLY_0_ RST_DLY_1_ \ +# RST_DLY_2_ inst_A0_DMA inst_CLK_030_H inst_DSACK1_INT inst_AS_000_INT SM_AMIGA_5_ \ +# SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ BG_000DFFreg CLK_OUT_INTreg IPL_030DFF_0_reg \ +# IPL_030DFF_1_reg IPL_030DFF_2_reg .model bus68030 .inputs A_DECODE_23_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF \ BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF FPU_SENSE.BLIF \ @@ -27,51 +27,51 @@ A_DECODE_20_.BLIF A_DECODE_19_.BLIF A_DECODE_18_.BLIF A_DECODE_17_.BLIF \ A_DECODE_16_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF A_1_.BLIF \ inst_BGACK_030_INTreg.BLIF inst_VMA_INTreg.BLIF cpu_est_2_.BLIF \ cpu_est_3_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \ -inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF inst_AS_030_D0.BLIF \ -inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INT_D.BLIF inst_AS_000_DMA.BLIF \ -inst_DS_000_DMA.BLIF CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF inst_VPA_D.BLIF \ -CLK_000_D_2_.BLIF CLK_000_D_4_.BLIF inst_DTACK_D0.BLIF inst_RESET_OUT.BLIF \ +inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF \ +inst_AS_030_D0.BLIF inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INT_D.BLIF \ +inst_AS_000_DMA.BLIF inst_DS_000_DMA.BLIF CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF \ +inst_VPA_D.BLIF CLK_000_D_3_.BLIF inst_DTACK_D0.BLIF inst_RESET_OUT.BLIF \ CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF inst_CLK_OUT_PRE_50.BLIF \ inst_CLK_OUT_PRE_D.BLIF IPL_D0_0_.BLIF IPL_D0_1_.BLIF IPL_D0_2_.BLIF \ -CLK_000_D_3_.BLIF CLK_000_D_5_.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ -SM_AMIGA_1_.BLIF inst_UDS_000_INT.BLIF inst_DS_000_ENABLE.BLIF \ -inst_LDS_000_INT.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_0_.BLIF \ -SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF inst_RW_000_INT.BLIF inst_RW_000_DMA.BLIF \ -RST_DLY_0_.BLIF RST_DLY_1_.BLIF RST_DLY_2_.BLIF inst_A0_DMA.BLIF \ -inst_CLK_030_H.BLIF inst_DSACK1_INT.BLIF inst_AS_000_INT.BLIF SM_AMIGA_5_.BLIF \ -SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_i_7_.BLIF BG_000DFFreg.BLIF \ -CLK_OUT_INTreg.BLIF IPL_030DFF_0_reg.BLIF IPL_030DFF_1_reg.BLIF \ -IPL_030DFF_2_reg.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF \ -UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF \ -AHIGH_24_.PIN.BLIF AHIGH_25_.PIN.BLIF AHIGH_26_.PIN.BLIF AHIGH_27_.PIN.BLIF \ -AHIGH_28_.PIN.BLIF AHIGH_29_.PIN.BLIF AHIGH_30_.PIN.BLIF AHIGH_31_.PIN.BLIF \ -A_0_.PIN.BLIF BERR.PIN.BLIF RW.PIN.BLIF +CLK_000_D_2_.BLIF CLK_000_D_4_.BLIF inst_LDS_000_INT.BLIF \ +inst_DS_000_ENABLE.BLIF inst_UDS_000_INT.BLIF SM_AMIGA_6_.BLIF \ +SM_AMIGA_4_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_0_.BLIF SIZE_DMA_0_.BLIF \ +SIZE_DMA_1_.BLIF inst_RW_000_INT.BLIF inst_RW_000_DMA.BLIF RST_DLY_0_.BLIF \ +RST_DLY_1_.BLIF RST_DLY_2_.BLIF inst_A0_DMA.BLIF inst_CLK_030_H.BLIF \ +inst_DSACK1_INT.BLIF inst_AS_000_INT.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_3_.BLIF \ +SM_AMIGA_2_.BLIF SM_AMIGA_i_7_.BLIF BG_000DFFreg.BLIF CLK_OUT_INTreg.BLIF \ +IPL_030DFF_0_reg.BLIF IPL_030DFF_1_reg.BLIF IPL_030DFF_2_reg.BLIF \ +AS_030.PIN.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF UDS_000.PIN.BLIF \ +LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF AHIGH_24_.PIN.BLIF \ +AHIGH_25_.PIN.BLIF AHIGH_26_.PIN.BLIF AHIGH_27_.PIN.BLIF AHIGH_28_.PIN.BLIF \ +AHIGH_29_.PIN.BLIF AHIGH_30_.PIN.BLIF AHIGH_31_.PIN.BLIF A_0_.PIN.BLIF \ +BERR.PIN.BLIF RW.PIN.BLIF .outputs IPL_030_2_ DS_030 BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 \ AVEC E VMA RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ -AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_i_7_.C SM_AMIGA_6_.D \ +AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ IPL_D0_0_.D IPL_D0_0_.C \ +IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C SM_AMIGA_i_7_.C SM_AMIGA_6_.D \ SM_AMIGA_6_.C SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_4_.D SM_AMIGA_4_.C \ SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C \ -SM_AMIGA_0_.D SM_AMIGA_0_.C cpu_est_3_.D cpu_est_3_.C IPL_030DFF_0_reg.D \ +SM_AMIGA_0_.D SM_AMIGA_0_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D \ +cpu_est_1_.C cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C IPL_030DFF_0_reg.D \ IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D \ -IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D \ -IPL_D0_2_.C CLK_000_D_0_.D CLK_000_D_0_.C CLK_000_D_1_.D CLK_000_D_1_.C \ -CLK_000_D_2_.D CLK_000_D_2_.C CLK_000_D_3_.D CLK_000_D_3_.C CLK_000_D_4_.D \ -CLK_000_D_4_.C CLK_000_D_5_.D CLK_000_D_5_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C \ +IPL_030DFF_2_reg.C RST_DLY_2_.D RST_DLY_2_.C CLK_000_D_0_.D CLK_000_D_0_.C \ +CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_2_.D CLK_000_D_2_.C CLK_000_D_3_.D \ +CLK_000_D_3_.C CLK_000_D_4_.D CLK_000_D_4_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C \ CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D \ -SIZE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.C \ -RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C \ -inst_DS_000_DMA.D inst_DS_000_DMA.C inst_DSACK1_INT.D inst_DSACK1_INT.C \ -inst_AS_000_INT.D inst_AS_000_INT.C inst_AS_030_D0.D inst_AS_030_D0.C \ -inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D inst_DTACK_D0.C inst_CLK_030_H.C \ -inst_RESET_OUT.D inst_RESET_OUT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C \ -BG_000DFFreg.D BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D \ +SIZE_DMA_1_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.C inst_RW_000_INT.D \ +inst_RW_000_INT.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \ +inst_LDS_000_INT.D inst_LDS_000_INT.C inst_BGACK_030_INTreg.D \ +inst_BGACK_030_INTreg.C inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D \ +inst_DS_000_DMA.C inst_DSACK1_INT.D inst_DSACK1_INT.C inst_AS_000_INT.D \ +inst_AS_000_INT.C inst_AS_030_D0.D inst_AS_030_D0.C inst_VPA_D.D inst_VPA_D.C \ +inst_DTACK_D0.D inst_DTACK_D0.C inst_CLK_030_H.C inst_RESET_OUT.D \ +inst_RESET_OUT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C BG_000DFFreg.D \ +BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D \ inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D \ inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_UDS_000_INT.D inst_UDS_000_INT.C \ inst_A0_DMA.D inst_A0_DMA.C inst_RW_000_DMA.D inst_RW_000_DMA.C \ -inst_VMA_INTreg.D inst_VMA_INTreg.C inst_RW_000_INT.D inst_RW_000_INT.C \ -inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_LDS_000_INT.D \ -inst_LDS_000_INT.C inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C \ -inst_AS_000_DMA.D inst_AS_000_DMA.C inst_BGACK_030_INT_D.D \ +inst_VMA_INTreg.D inst_VMA_INTreg.C inst_BGACK_030_INT_D.D \ inst_BGACK_030_INT_D.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C inst_CLK_OUT_PRE_50.D \ inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C SIZE_1_ \ AHIGH_31_ AS_030 AS_000 RW_000 UDS_000 LDS_000 BERR RW SIZE_0_ AHIGH_30_ \ @@ -82,8 +82,20 @@ AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE \ cpu_est_2_.D.X1 cpu_est_2_.D.X2 RST_DLY_1_.D.X1 RST_DLY_1_.D.X2 \ inst_CLK_030_H.D.X1 inst_CLK_030_H.D.X2 SM_AMIGA_3_.D.X1 SM_AMIGA_3_.D.X2 \ SM_AMIGA_i_7_.D.X1 SM_AMIGA_i_7_.D.X2 -.names nEXP_SPACE.BLIF RST.BLIF inst_AS_030_000_SYNC.BLIF CLK_000_D_4_.BLIF \ -CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF CLK_000_D_5_.BLIF SM_AMIGA_6_.BLIF \ +.names RST.BLIF IPL_0_.BLIF IPL_D0_0_.D +0- 1 +-1 1 +10 0 +.names RST.BLIF IPL_1_.BLIF IPL_D0_1_.D +0- 1 +-1 1 +10 0 +.names IPL_2_.BLIF RST.BLIF IPL_D0_2_.D +1- 1 +-0 1 +01 0 +.names nEXP_SPACE.BLIF RST.BLIF inst_AS_030_000_SYNC.BLIF CLK_000_D_3_.BLIF \ +CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF CLK_000_D_4_.BLIF SM_AMIGA_6_.BLIF \ SM_AMIGA_i_7_.BLIF SM_AMIGA_6_.D 1100--100 1 -1---0-1- 1 @@ -135,28 +147,44 @@ BERR.PIN.BLIF SM_AMIGA_2_.D ---------1-0- 0 --------0--0- 0 0------------ 0 -.names RST.BLIF CLK_000_D_2_.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF \ -CLK_000_D_3_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_1_.D -1-01--1 1 -1---01- 1 -11---1- 1 -1----11 1 --0--1-0 0 ----0-0- 0 ---1--0- 0 -0------ 0 ------00 0 -.names RST.BLIF CLK_000_D_2_.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF \ -CLK_000_D_3_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_0_.D -10--11- 1 -1--0--1 1 -1-1---1 1 -1----11 1 ---01-0- 0 -0------ 0 -----0-0 0 --1----0 0 ------00 0 +.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_1_.BLIF \ +SM_AMIGA_2_.BLIF SM_AMIGA_1_.D +101-1 1 +1-110 1 +10-10 1 +-10-- 0 +---00 0 +0---- 0 +--0-1 0 +-1--1 0 +.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_1_.BLIF \ +SM_AMIGA_0_.BLIF SM_AMIGA_0_.D +1101- 1 +1-0-1 1 +11--1 1 +-01-- 0 +0---- 0 +---00 0 +--1-0 0 +-0--0 0 +.names cpu_est_0_.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF cpu_est_0_.D +010 1 +10- 1 +1-1 1 +110 0 +00- 0 +0-1 0 +.names cpu_est_3_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF CLK_000_D_1_.BLIF \ +CLK_000_D_0_.BLIF cpu_est_1_.D +01010 1 +-01-- 1 +--10- 1 +--1-1 1 +1-0-- 0 +-1110 0 +--00- 0 +-00-- 0 +--0-1 0 .names cpu_est_2_.BLIF cpu_est_3_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \ CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF cpu_est_3_.D 1-1110 1 @@ -169,87 +197,99 @@ CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF cpu_est_3_.D 0-1-10 0 -0--0- 0 -0---1 0 -.names IPL_2_.BLIF RST.BLIF IPL_1_.BLIF IPL_0_.BLIF IPL_D0_0_.BLIF \ -IPL_D0_1_.BLIF IPL_D0_2_.BLIF IPL_030DFF_0_reg.BLIF IPL_030DFF_0_reg.D -0-01100- 1 -0-11110- 1 -1-01101- 1 -1-11111- 1 -1-----01 1 -0-----11 1 ---1--0-1 1 ---0--1-1 1 ----1---1 1 -----1--1 1 --0------ 1 -0100000- 0 -0110010- 0 -1100001- 0 -1110011- 0 -11----00 0 -01----10 0 --11--0-0 0 --10--1-0 0 --1--0--0 0 --1-0---0 0 -.names IPL_2_.BLIF RST.BLIF IPL_1_.BLIF IPL_0_.BLIF IPL_D0_0_.BLIF \ -IPL_D0_1_.BLIF IPL_D0_2_.BLIF IPL_030DFF_1_reg.BLIF IPL_030DFF_1_reg.D -0-10010- 1 -0-11110- 1 -1-10011- 1 -1-11111- 1 -1-----01 1 -0-----11 1 ---1----1 1 ------1-1 1 ----10--1 1 ----01--1 1 --0------ 1 -0100000- 0 -0101100- 0 -1100001- 0 -1101101- 0 -11----00 0 -01----10 0 --1-10--0 0 --1-01--0 0 --1---0-0 0 --10----0 0 -.names IPL_2_.BLIF RST.BLIF IPL_1_.BLIF IPL_0_.BLIF IPL_D0_0_.BLIF \ -IPL_D0_1_.BLIF IPL_D0_2_.BLIF IPL_030DFF_2_reg.BLIF IPL_030DFF_2_reg.D -1-00001- 1 -1-01101- 1 -1-10011- 1 -1-11111- 1 -1------1 1 -------11 1 ---1--0-1 1 ---0--1-1 1 ----10--1 1 ----01--1 1 --0------ 1 -0100000- 0 -0101100- 0 -0110010- 0 -0111110- 0 --11--0-0 0 --10--1-0 0 --1-10--0 0 --1-01--0 0 --1----00 0 -01-----0 0 -.names RST.BLIF IPL_0_.BLIF IPL_D0_0_.D -0- 1 --1 1 -10 0 -.names RST.BLIF IPL_1_.BLIF IPL_D0_1_.D -0- 1 --1 1 -10 0 -.names IPL_2_.BLIF RST.BLIF IPL_D0_2_.D -1- 1 --0 1 -01 0 +.names IPL_2_.BLIF RST.BLIF IPL_1_.BLIF IPL_0_.BLIF CLK_000_D_1_.BLIF \ +CLK_000_D_0_.BLIF IPL_D0_0_.BLIF IPL_D0_1_.BLIF IPL_D0_2_.BLIF \ +IPL_030DFF_0_reg.BLIF IPL_030DFF_0_reg.D +0-0101100- 1 +0-1101110- 1 +1-0101101- 1 +1-1101111- 1 +1-------01 1 +0-------11 1 +--1----0-1 1 +--0----1-1 1 +---1-----1 1 +------1--1 1 +-0-------- 1 +-----0---1 1 +----1----1 1 +010001000- 0 +011001010- 0 +110001001- 0 +111001011- 0 +11------00 0 +01------10 0 +-11----0-0 0 +-10----1-0 0 +-1---0---0 0 +-1--1----0 0 +-1----0--0 0 +-1-0-----0 0 +.names IPL_2_.BLIF RST.BLIF IPL_1_.BLIF IPL_0_.BLIF CLK_000_D_1_.BLIF \ +CLK_000_D_0_.BLIF IPL_D0_0_.BLIF IPL_D0_1_.BLIF IPL_D0_2_.BLIF \ +IPL_030DFF_1_reg.BLIF IPL_030DFF_1_reg.D +0-1001010- 1 +0-1101110- 1 +1-1001011- 1 +1-1101111- 1 +1-------01 1 +0-------11 1 +--1------1 1 +-------1-1 1 +---1--0--1 1 +---0--1--1 1 +-0-------- 1 +-----0---1 1 +----1----1 1 +010001000- 0 +010101100- 0 +110001001- 0 +110101101- 0 +11------00 0 +01------10 0 +-1-1--0--0 0 +-1-0--1--0 0 +-1---0---0 0 +-1--1----0 0 +-1-----0-0 0 +-10------0 0 +.names IPL_2_.BLIF RST.BLIF IPL_1_.BLIF IPL_0_.BLIF CLK_000_D_1_.BLIF \ +CLK_000_D_0_.BLIF IPL_D0_0_.BLIF IPL_D0_1_.BLIF IPL_D0_2_.BLIF \ +IPL_030DFF_2_reg.BLIF IPL_030DFF_2_reg.D +1-0001001- 1 +1-0101101- 1 +1-1001011- 1 +1-1101111- 1 +1--------1 1 +--------11 1 +--1----0-1 1 +--0----1-1 1 +---1--0--1 1 +---0--1--1 1 +-0-------- 1 +-----0---1 1 +----1----1 1 +010001000- 0 +010101100- 0 +011001010- 0 +011101110- 0 +-11----0-0 0 +-10----1-0 0 +-1-1--0--0 0 +-1-0--1--0 0 +-1---0---0 0 +-1--1----0 0 +-1------00 0 +01-------0 0 +.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF RST_DLY_0_.BLIF \ +RST_DLY_1_.BLIF RST_DLY_2_.BLIF RST_DLY_2_.D +11011- 1 +1----1 1 +0----- 0 +----00 0 +---0-0 0 +--1--0 0 +-0---0 0 .names RST.BLIF inst_BGACK_030_INTreg.BLIF CYCLE_DMA_0_.BLIF CLK_000_D_1_.BLIF \ CLK_000_D_0_.BLIF AS_000.PIN.BLIF CYCLE_DMA_0_.D 100010 1 @@ -292,24 +332,6 @@ SIZE_DMA_1_.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_DMA_1_.D 11-0-- 0 110--- 0 10---1 0 -.names cpu_est_0_.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF cpu_est_0_.D -010 1 -10- 1 -1-1 1 -110 0 -00- 0 -0-1 0 -.names cpu_est_3_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF CLK_000_D_1_.BLIF \ -CLK_000_D_0_.BLIF cpu_est_1_.D -01010 1 --01-- 1 ---10- 1 ---1-1 1 -1-0-- 0 --1110 0 ---00- 0 --00-- 0 ---0-1 0 .names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF RST_DLY_0_.BLIF \ RST_DLY_1_.BLIF RST_DLY_2_.BLIF RST_DLY_0_.D 1--111 1 @@ -321,171 +343,6 @@ RST_DLY_1_.BLIF RST_DLY_2_.BLIF RST_DLY_0_.D --10-- 0 -0-0-- 0 0----- 0 -.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF RST_DLY_0_.BLIF \ -RST_DLY_1_.BLIF RST_DLY_2_.BLIF RST_DLY_2_.D -11011- 1 -1----1 1 -0----- 0 -----00 0 ----0-0 0 ---1--0 0 --0---0 0 -.names CLK_030.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \ -inst_DS_000_DMA.BLIF CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF inst_CLK_030_H.BLIF \ -AS_000.PIN.BLIF RW_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF \ -inst_DS_000_DMA.D -1--1---1-0-- 1 -----1--0-0-- 1 -0---1----0-- 1 ------00----- 1 ------11----- 1 ---------1--- 1 ---1--------- 1 --0---------- 1 -----------11 1 -1100-1010-0- 0 -1100-0110-0- 0 -1100-1010--0 0 -1100-0110--0 0 --10-01000-0- 0 --10-00100-0- 0 -010-010-0-0- 0 -010-001-0-0- 0 --10-01000--0 0 --10-00100--0 0 -010-010-0--0 0 -010-001-0--0 0 --10--10-010- 0 --10--01-010- 0 --10--10-01-0 0 --10--01-01-0 0 -.names RST.BLIF CLK_000_D_2_.BLIF CLK_000_D_3_.BLIF SM_AMIGA_1_.BLIF \ -inst_DSACK1_INT.BLIF AS_030.PIN.BLIF inst_DSACK1_INT.D ----01- 1 ---0-1- 1 --1--1- 1 -0----- 1 ----0-1 1 ---0--1 1 --1---1 1 -1011-- 0 -1---00 0 -.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_6_.BLIF \ -inst_AS_000_INT.BLIF AS_030.PIN.BLIF inst_AS_000_INT.D ----01- 1 ---0-1- 1 --1--1- 1 -0----- 1 ----0-1 1 ---0--1 1 --1---1 1 -1011-- 0 -1---00 0 -.names RST.BLIF AS_030.PIN.BLIF inst_AS_030_D0.D -0- 1 --1 1 -10 0 -.names VPA.BLIF RST.BLIF inst_VPA_D.D -1- 1 --0 1 -01 0 -.names DTACK.BLIF RST.BLIF inst_DTACK_D0.D -1- 1 --0 1 -01 0 -.names RST.BLIF inst_RESET_OUT.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF \ -RST_DLY_0_.BLIF RST_DLY_1_.BLIF RST_DLY_2_.BLIF inst_RESET_OUT.D -1-10111 1 -11----- 1 -0------ 0 --0---0- 0 --0--0-- 0 --0-1--- 0 --00---- 0 --0----0 0 -.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF inst_DS_000_ENABLE.BLIF \ -SM_AMIGA_6_.BLIF SM_AMIGA_4_.BLIF AS_030.PIN.BLIF RW.PIN.BLIF \ -inst_DS_000_ENABLE.D -101--1-- 1 -101-1--1 1 -1--1--0- 1 -----001- 0 ----000-- 0 ------010 0 ---0---1- 0 --1----1- 0 ----0-0-0 0 ---00---- 0 --1-0---- 0 -0------- 0 -.names nEXP_SPACE.BLIF BG_030.BLIF RST.BLIF inst_AS_030_D0.BLIF \ -CLK_000_D_0_.BLIF BG_000DFFreg.BLIF BG_000DFFreg.D -----01 1 ----0-1 1 -0----1 1 ---0--- 1 --1---- 1 -10111- 0 --01--0 0 -.names RST.BLIF A_1_.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ -inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D ---1-1 1 --10-- 1 ---10- 1 -0---- 1 -1-110 0 -100-- 0 -.names RST.BLIF A_1_.BLIF inst_BGACK_030_INTreg.BLIF \ -inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF inst_BGACK_030_INT_D.BLIF \ -inst_AMIGA_BUS_ENABLE_DMA_LOW.D ---11- 1 --00-- 1 ---1-0 1 -0---- 1 -1-101 0 -110-- 0 -.names RST.BLIF inst_UDS_000_INT.BLIF SM_AMIGA_6_.BLIF A_0_.PIN.BLIF \ -inst_UDS_000_INT.D --10- 1 -0--- 1 ---11 1 -100- 0 -1-10 0 -.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ -inst_A0_DMA.BLIF UDS_000.PIN.BLIF inst_A0_DMA.D --111- 1 -0---- 1 --0--1 1 -11-0- 0 -110-- 0 -10--0 0 -.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ -inst_RW_000_DMA.BLIF RW_000.PIN.BLIF inst_RW_000_DMA.D --1-1- 1 --10-- 1 -0---- 1 --0--1 1 -1110- 0 -10--0 0 -.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_2_.BLIF cpu_est_3_.BLIF \ -cpu_est_0_.BLIF cpu_est_1_.BLIF inst_VPA_D.BLIF CLK_000_D_1_.BLIF \ -CLK_000_D_0_.BLIF inst_VMA_INTreg.D ---0000-01 1 --1----1-- 1 --1-1----- 1 --11------ 1 -0-------- 1 --1-----0- 1 --1---0--- 1 --1--0---- 1 --1------1 1 -1-0011010 0 -10-1----- 0 -101------ 0 -10-----1- 0 -10---1--- 0 -10--1---- 0 -10------0 0 .names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_6_.BLIF \ SM_AMIGA_0_.BLIF inst_RW_000_INT.BLIF SM_AMIGA_i_7_.BLIF RW.PIN.BLIF \ inst_RW_000_INT.D @@ -555,6 +412,163 @@ LDS_000.PIN.BLIF inst_AS_000_DMA.D 110-100-0 0 -100010-0 0 110-010-0 0 +.names CLK_030.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \ +inst_DS_000_DMA.BLIF CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF inst_CLK_030_H.BLIF \ +AS_000.PIN.BLIF RW_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF \ +inst_DS_000_DMA.D +1--1---1-0-- 1 +----1--0-0-- 1 +0---1----0-- 1 +-----00----- 1 +-----11----- 1 +--------1--- 1 +--1--------- 1 +-0---------- 1 +----------11 1 +1100-1010-0- 0 +1100-0110-0- 0 +1100-1010--0 0 +1100-0110--0 0 +-10-01000-0- 0 +-10-00100-0- 0 +010-010-0-0- 0 +010-001-0-0- 0 +-10-01000--0 0 +-10-00100--0 0 +010-010-0--0 0 +010-001-0--0 0 +-10--10-010- 0 +-10--01-010- 0 +-10--10-01-0 0 +-10--01-01-0 0 +.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_1_.BLIF \ +inst_DSACK1_INT.BLIF AS_030.PIN.BLIF inst_DSACK1_INT.D +---01- 1 +--1-1- 1 +-0--1- 1 +0----- 1 +---0-1 1 +--1--1 1 +-0---1 1 +1101-- 0 +1---00 0 +.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_6_.BLIF \ +inst_AS_000_INT.BLIF AS_030.PIN.BLIF inst_AS_000_INT.D +---01- 1 +--0-1- 1 +-1--1- 1 +0----- 1 +---0-1 1 +--0--1 1 +-1---1 1 +1011-- 0 +1---00 0 +.names RST.BLIF AS_030.PIN.BLIF inst_AS_030_D0.D +0- 1 +-1 1 +10 0 +.names VPA.BLIF RST.BLIF inst_VPA_D.D +1- 1 +-0 1 +01 0 +.names DTACK.BLIF RST.BLIF inst_DTACK_D0.D +1- 1 +-0 1 +01 0 +.names RST.BLIF inst_RESET_OUT.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF \ +RST_DLY_0_.BLIF RST_DLY_1_.BLIF RST_DLY_2_.BLIF inst_RESET_OUT.D +1-10111 1 +11----- 1 +0------ 0 +-0---0- 0 +-0--0-- 0 +-0-1--- 0 +-00---- 0 +-0----0 0 +.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF inst_DS_000_ENABLE.BLIF \ +SM_AMIGA_6_.BLIF SM_AMIGA_4_.BLIF AS_030.PIN.BLIF RW.PIN.BLIF \ +inst_DS_000_ENABLE.D +101--1-- 1 +101-1--1 1 +1--1--0- 1 +----001- 0 +---000-- 0 +-----010 0 +--0---1- 0 +-1----1- 0 +---0-0-0 0 +--00---- 0 +-1-0---- 0 +0------- 0 +.names nEXP_SPACE.BLIF BG_030.BLIF RST.BLIF inst_AS_030_D0.BLIF \ +CLK_000_D_0_.BLIF BG_000DFFreg.BLIF BG_000DFFreg.D +----01 1 +---0-1 1 +0----1 1 +--0--- 1 +-1---- 1 +10111- 0 +-01--0 0 +.names RST.BLIF A_1_.BLIF inst_BGACK_030_INTreg.BLIF \ +inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF inst_BGACK_030_INT_D.BLIF \ +inst_AMIGA_BUS_ENABLE_DMA_HIGH.D +--11- 1 +-10-- 1 +--1-0 1 +0---- 1 +1-101 0 +100-- 0 +.names RST.BLIF A_1_.BLIF inst_BGACK_030_INTreg.BLIF \ +inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF inst_BGACK_030_INT_D.BLIF \ +inst_AMIGA_BUS_ENABLE_DMA_LOW.D +--11- 1 +-00-- 1 +--1-0 1 +0---- 1 +1-101 0 +110-- 0 +.names RST.BLIF inst_UDS_000_INT.BLIF SM_AMIGA_6_.BLIF A_0_.PIN.BLIF \ +inst_UDS_000_INT.D +-10- 1 +0--- 1 +--11 1 +100- 0 +1-10 0 +.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ +inst_A0_DMA.BLIF UDS_000.PIN.BLIF inst_A0_DMA.D +-111- 1 +0---- 1 +-0--1 1 +11-0- 0 +110-- 0 +10--0 0 +.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ +inst_RW_000_DMA.BLIF RW_000.PIN.BLIF inst_RW_000_DMA.D +-1-1- 1 +-10-- 1 +0---- 1 +-0--1 1 +1110- 0 +10--0 0 +.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_2_.BLIF cpu_est_3_.BLIF \ +cpu_est_0_.BLIF cpu_est_1_.BLIF inst_VPA_D.BLIF CLK_000_D_1_.BLIF \ +CLK_000_D_0_.BLIF inst_VMA_INTreg.D +--0000-01 1 +-1----1-- 1 +-1------1 1 +-1-----0- 1 +-1---0--- 1 +-1--0---- 1 +-1-1----- 1 +-11------ 1 +0-------- 1 +1-0011010 0 +10-1----- 0 +101------ 0 +10-----1- 0 +10---1--- 0 +10--1---- 0 +10------0 0 .names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.D 0- 1 -1 1 @@ -626,12 +640,13 @@ AMIGA_BUS_ENABLE_LOW 1- 1 -1 1 00 0 -.names inst_BGACK_030_INTreg.BLIF inst_AS_030_000_SYNC.BLIF \ -inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF AMIGA_BUS_ENABLE_HIGH -11- 1 -0-1 1 -10- 0 -0-0 0 +.names inst_BGACK_030_INTreg.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ +inst_AS_030_000_SYNC.BLIF AS_030.PIN.BLIF AMIGA_BUS_ENABLE_HIGH +1-1- 1 +01-- 1 +1--1 1 +1-00 0 +00-- 0 .names A_DECODE_23_.BLIF A_DECODE_22_.BLIF A_DECODE_21_.BLIF A_DECODE_20_.BLIF \ inst_AS_030_D0.BLIF AHIGH_24_.PIN.BLIF AHIGH_25_.PIN.BLIF AHIGH_26_.PIN.BLIF \ AHIGH_27_.PIN.BLIF AHIGH_28_.PIN.BLIF AHIGH_29_.PIN.BLIF AHIGH_30_.PIN.BLIF \ @@ -656,6 +671,15 @@ AHIGH_31_.PIN.BLIF CIIN .names IPL_030DFF_0_reg.BLIF IPL_030_0_ 1 1 0 0 +.names CLK_OSZI.BLIF IPL_D0_0_.C +1 1 +0 0 +.names CLK_OSZI.BLIF IPL_D0_1_.C +1 1 +0 0 +.names CLK_OSZI.BLIF IPL_D0_2_.C +1 1 +0 0 .names CLK_OSZI.BLIF SM_AMIGA_i_7_.C 1 1 0 0 @@ -680,6 +704,15 @@ AHIGH_31_.PIN.BLIF CIIN .names CLK_OSZI.BLIF SM_AMIGA_0_.C 1 1 0 0 +.names CLK_OSZI.BLIF cpu_est_0_.C +1 1 +0 0 +.names CLK_OSZI.BLIF cpu_est_1_.C +1 1 +0 0 +.names CLK_OSZI.BLIF cpu_est_2_.C +1 1 +0 0 .names CLK_OSZI.BLIF cpu_est_3_.C 1 1 0 0 @@ -692,13 +725,7 @@ AHIGH_31_.PIN.BLIF CIIN .names CLK_OSZI.BLIF IPL_030DFF_2_reg.C 1 1 0 0 -.names CLK_OSZI.BLIF IPL_D0_0_.C -1 1 -0 0 -.names CLK_OSZI.BLIF IPL_D0_1_.C -1 1 -0 0 -.names CLK_OSZI.BLIF IPL_D0_2_.C +.names CLK_OSZI.BLIF RST_DLY_2_.C 1 1 0 0 .names CLK_000.BLIF CLK_000_D_0_.D @@ -731,12 +758,6 @@ AHIGH_31_.PIN.BLIF CIIN .names CLK_OSZI.BLIF CLK_000_D_4_.C 1 1 0 0 -.names CLK_000_D_4_.BLIF CLK_000_D_5_.D -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_000_D_5_.C -1 1 -0 0 .names CLK_OSZI.BLIF CYCLE_DMA_0_.C 1 1 0 0 @@ -749,22 +770,25 @@ AHIGH_31_.PIN.BLIF CIIN .names CLK_OSZI.BLIF SIZE_DMA_1_.C 1 1 0 0 -.names CLK_OSZI.BLIF cpu_est_0_.C -1 1 -0 0 -.names CLK_OSZI.BLIF cpu_est_1_.C -1 1 -0 0 -.names CLK_OSZI.BLIF cpu_est_2_.C -1 1 -0 0 .names CLK_OSZI.BLIF RST_DLY_0_.C 1 1 0 0 .names CLK_OSZI.BLIF RST_DLY_1_.C 1 1 0 0 -.names CLK_OSZI.BLIF RST_DLY_2_.C +.names CLK_OSZI.BLIF inst_RW_000_INT.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_AS_030_000_SYNC.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_LDS_000_INT.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_BGACK_030_INTreg.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_AS_000_DMA.C 1 1 0 0 .names CLK_OSZI.BLIF inst_DS_000_DMA.C @@ -815,21 +839,6 @@ AHIGH_31_.PIN.BLIF CIIN .names CLK_OSZI.BLIF inst_VMA_INTreg.C 1 1 0 0 -.names CLK_OSZI.BLIF inst_RW_000_INT.C -1 1 -0 0 -.names CLK_OSZI.BLIF inst_AS_030_000_SYNC.C -1 1 -0 0 -.names CLK_OSZI.BLIF inst_LDS_000_INT.C -1 1 -0 0 -.names CLK_OSZI.BLIF inst_BGACK_030_INTreg.C -1 1 -0 0 -.names CLK_OSZI.BLIF inst_AS_000_DMA.C -1 1 -0 0 .names CLK_OSZI.BLIF inst_BGACK_030_INT_D.C 1 1 0 0 @@ -864,14 +873,14 @@ AHIGH_31_.PIN.BLIF CIIN .names inst_RW_000_INT.BLIF RW_000 1 1 0 0 -.names inst_UDS_000_INT.BLIF inst_DS_000_ENABLE.BLIF UDS_000 -1- 1 --0 1 -01 0 -.names inst_DS_000_ENABLE.BLIF inst_LDS_000_INT.BLIF LDS_000 +.names inst_DS_000_ENABLE.BLIF inst_UDS_000_INT.BLIF UDS_000 0- 1 -1 1 10 0 +.names inst_LDS_000_INT.BLIF inst_DS_000_ENABLE.BLIF LDS_000 +1- 1 +-0 1 +01 0 .names BERR 0 .names inst_RW_000_DMA.BLIF RW @@ -1105,8 +1114,8 @@ BERR.PIN.BLIF SM_AMIGA_3_.D.X2 11 1 0- 0 -0 0 -.names nEXP_SPACE.BLIF RST.BLIF inst_AS_030_000_SYNC.BLIF CLK_000_D_4_.BLIF \ -CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF CLK_000_D_5_.BLIF SM_AMIGA_0_.BLIF \ +.names nEXP_SPACE.BLIF RST.BLIF inst_AS_030_000_SYNC.BLIF CLK_000_D_3_.BLIF \ +CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF CLK_000_D_4_.BLIF SM_AMIGA_0_.BLIF \ SM_AMIGA_i_7_.BLIF SM_AMIGA_i_7_.D.X2 11001-1-0 1 1100-01-0 1 diff --git a/Logic/68030_tk.crf b/Logic/68030_tk.crf index 7898436..96a545f 100644 --- a/Logic/68030_tk.crf +++ b/Logic/68030_tk.crf @@ -1,7 +1,7 @@ // Signal Name Cross Reference File // ispLEVER Classic 2.0.00.17.20.15 -// Design '68030_tk' created Thu Oct 06 22:04:11 2016 +// Design '68030_tk' created Sat Oct 15 23:48:24 2016 // LEGEND: '>' Functional Block Port Separator diff --git a/Logic/68030_tk.eq3 b/Logic/68030_tk.eq3 index 16ed26f..cf2f283 100644 --- a/Logic/68030_tk.eq3 +++ b/Logic/68030_tk.eq3 @@ -2,7 +2,7 @@ Copyright(C), 1992-2015, Lattice Semiconductor Corp. All Rights Reserved. -Design bus68030 created Thu Oct 06 22:04:11 2016 +Design bus68030 created Sat Oct 15 23:48:24 2016 P-Terms Fan-in Fan-out Type Name (attributes) @@ -27,17 +27,17 @@ Design bus68030 created Thu Oct 06 22:04:11 2016 1 3 1 Pin AHIGH_29_.OE 0 0 1 Pin AHIGH_28_ 1 3 1 Pin AHIGH_28_.OE - 1 1 1 Pin CLK_DIV_OUT.D - 1 1 1 Pin CLK_DIV_OUT.C 0 0 1 Pin AHIGH_27_ 1 3 1 Pin AHIGH_27_.OE 0 0 1 Pin AHIGH_26_ 1 3 1 Pin AHIGH_26_.OE - 1 9 1 Pin FPU_CS- + 1 1 1 Pin CLK_DIV_OUT.D + 1 1 1 Pin CLK_DIV_OUT.C 0 0 1 Pin AHIGH_25_ 1 3 1 Pin AHIGH_25_.OE 0 0 1 Pin AHIGH_24_ 1 3 1 Pin AHIGH_24_.OE + 1 9 1 Pin FPU_CS- 1 2 1 Pin DSACK1- 1 1 1 Pin DSACK1.OE 1 0 1 Pin AVEC @@ -47,24 +47,24 @@ Design bus68030 created Thu Oct 06 22:04:11 2016 0 0 1 Pin AMIGA_ADDR_ENABLE 2 4 1 Pin AMIGA_BUS_DATA_DIR 1 2 1 Pin AMIGA_BUS_ENABLE_LOW- - 2 3 1 Pin AMIGA_BUS_ENABLE_HIGH + 2 4 1 Pin AMIGA_BUS_ENABLE_HIGH- 1 13 1 Pin CIIN 1 1 1 Pin CIIN.OE 1 2 1 Pin SIZE_1_.OE 3 6 1 Pin SIZE_1_.D 1 1 1 Pin SIZE_1_.C - 10 8 1 Pin IPL_030_2_.D- + 9 10 1 Pin IPL_030_2_.T 1 1 1 Pin IPL_030_2_.C 1 2 1 Pin RW_000.OE 4 8 1 Pin RW_000.D- 1 1 1 Pin RW_000.C 2 6 1 Pin BG_000.D- 1 1 1 Pin BG_000.C - 3 6 1 Pin BGACK_030.D - 1 1 1 Pin BGACK_030.C 1 2 1 Pin SIZE_0_.OE 3 6 1 Pin SIZE_0_.D- 1 1 1 Pin SIZE_0_.C + 3 6 1 Pin BGACK_030.D + 1 1 1 Pin BGACK_030.C 1 1 1 Pin CLK_EXP.D 1 1 1 Pin CLK_EXP.C 3 9 1 Pin VMA.T @@ -75,9 +75,9 @@ Design bus68030 created Thu Oct 06 22:04:11 2016 1 3 1 Pin A_0_.OE 3 5 1 Pin A_0_.D 1 1 1 Pin A_0_.C - 10 8 1 Pin IPL_030_1_.D- + 9 10 1 Pin IPL_030_1_.T 1 1 1 Pin IPL_030_1_.C - 10 8 1 Pin IPL_030_0_.D- + 9 10 1 Pin IPL_030_0_.T 1 1 1 Pin IPL_030_0_.C 1 1 1 NodeX1 cpu_est_2_.D.X1 1 4 1 NodeX2 cpu_est_2_.D.X2 @@ -88,6 +88,8 @@ Design bus68030 created Thu Oct 06 22:04:11 2016 1 1 1 Node cpu_est_0_.C 4 5 1 Node cpu_est_1_.D 1 1 1 Node cpu_est_1_.C + 2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- + 1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.C 2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.D- 1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.C 1 2 1 Node inst_AS_030_D0.D- @@ -106,10 +108,8 @@ Design bus68030 created Thu Oct 06 22:04:11 2016 1 1 1 Node CYCLE_DMA_1_.C 1 2 1 Node inst_VPA_D.D- 1 1 1 Node inst_VPA_D.C - 1 1 1 Node CLK_000_D_2_.D - 1 1 1 Node CLK_000_D_2_.C - 1 1 1 Node CLK_000_D_4_.D - 1 1 1 Node CLK_000_D_4_.C + 1 1 1 Node CLK_000_D_3_.D + 1 1 1 Node CLK_000_D_3_.C 1 2 1 Node inst_DTACK_D0.D- 1 1 1 Node inst_DTACK_D0.C 2 7 1 Node inst_RESET_OUT.D @@ -128,25 +128,23 @@ Design bus68030 created Thu Oct 06 22:04:11 2016 1 1 1 Node IPL_D0_1_.C 1 2 1 Node IPL_D0_2_.D- 1 1 1 Node IPL_D0_2_.C - 1 1 1 Node CLK_000_D_3_.D - 1 1 1 Node CLK_000_D_3_.C - 1 1 1 Node CLK_000_D_5_.D - 1 1 1 Node CLK_000_D_5_.C - 2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- - 1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.C - 4 7 1 Node SM_AMIGA_1_.D - 1 1 1 Node SM_AMIGA_1_.C - 2 4 1 Node inst_UDS_000_INT.D- - 1 1 1 Node inst_UDS_000_INT.C - 3 8 1 Node inst_DS_000_ENABLE.D - 1 1 1 Node inst_DS_000_ENABLE.C + 1 1 1 Node CLK_000_D_2_.D + 1 1 1 Node CLK_000_D_2_.C + 1 1 1 Node CLK_000_D_4_.D + 1 1 1 Node CLK_000_D_4_.C 3 6 1 Node inst_LDS_000_INT.D 1 1 1 Node inst_LDS_000_INT.C + 3 8 1 Node inst_DS_000_ENABLE.D + 1 1 1 Node inst_DS_000_ENABLE.C + 2 4 1 Node inst_UDS_000_INT.D- + 1 1 1 Node inst_UDS_000_INT.C 3 9 1 Node SM_AMIGA_6_.D 1 1 1 Node SM_AMIGA_6_.C 3 5 1 Node SM_AMIGA_4_.D 1 1 1 Node SM_AMIGA_4_.C - 4 7 1 Node SM_AMIGA_0_.D + 3 5 1 Node SM_AMIGA_1_.D + 1 1 1 Node SM_AMIGA_1_.C + 3 5 1 Node SM_AMIGA_0_.D 1 1 1 Node SM_AMIGA_0_.C 4 6 1 Node RST_DLY_0_.D 1 1 1 Node RST_DLY_0_.C @@ -172,9 +170,9 @@ Design bus68030 created Thu Oct 06 22:04:11 2016 1 1 1 Node SM_AMIGA_i_7_.C 2 14 1 Node CIIN_0 ========= - 276 P-Term Total: 276 + 269 P-Term Total: 269 Total Pins: 61 - Total Nodes: 45 + Total Nodes: 44 Average P-Term/Output: 2 @@ -196,11 +194,11 @@ AS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q); DS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); -!UDS_000 = (!inst_UDS_000_INT.Q & inst_DS_000_ENABLE.Q); +!UDS_000 = (inst_DS_000_ENABLE.Q & !inst_UDS_000_INT.Q); UDS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q); -!LDS_000 = (inst_DS_000_ENABLE.Q & !inst_LDS_000_INT.Q); +!LDS_000 = (!inst_LDS_000_INT.Q & inst_DS_000_ENABLE.Q); LDS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q); @@ -220,10 +218,6 @@ AHIGH_28_ = (0); AHIGH_28_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); -CLK_DIV_OUT.D = (inst_CLK_OUT_PRE_D.Q); - -CLK_DIV_OUT.C = (CLK_OSZI); - AHIGH_27_ = (0); AHIGH_27_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); @@ -232,7 +226,9 @@ AHIGH_26_ = (0); AHIGH_26_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); -!FPU_CS = (FC_1_ & BGACK_000 & !FPU_SENSE & !A_DECODE_19_ & !A_DECODE_18_ & A_DECODE_17_ & !A_DECODE_16_ & FC_0_ & !AS_030.PIN); +CLK_DIV_OUT.D = (inst_CLK_OUT_PRE_D.Q); + +CLK_DIV_OUT.C = (CLK_OSZI); AHIGH_25_ = (0); @@ -242,6 +238,8 @@ AHIGH_24_ = (0); AHIGH_24_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); +!FPU_CS = (FC_1_ & BGACK_000 & !FPU_SENSE & !A_DECODE_19_ & !A_DECODE_18_ & A_DECODE_17_ & !A_DECODE_16_ & FC_0_ & !AS_030.PIN); + !DSACK1 = (!inst_DSACK1_INT.Q & !AS_030.PIN); DSACK1.OE = (nEXP_SPACE); @@ -262,8 +260,8 @@ AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW_000.PIN !AMIGA_BUS_ENABLE_LOW = (!BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_LOW.Q); -AMIGA_BUS_ENABLE_HIGH = (BGACK_030.Q & inst_AS_030_000_SYNC.Q - # !BGACK_030.Q & inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q); +!AMIGA_BUS_ENABLE_HIGH = (!BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q + # BGACK_030.Q & !inst_AS_030_000_SYNC.Q & !AS_030.PIN); CIIN = (A_DECODE_23_ & A_DECODE_22_ & A_DECODE_21_ & A_DECODE_20_ & !inst_AS_030_D0.Q & !AHIGH_24_.PIN & !AHIGH_25_.PIN & !AHIGH_26_.PIN & !AHIGH_27_.PIN & !AHIGH_28_.PIN & !AHIGH_29_.PIN & !AHIGH_30_.PIN & !AHIGH_31_.PIN); @@ -277,16 +275,15 @@ SIZE_1_.D = (!RST SIZE_1_.C = (CLK_OSZI); -!IPL_030_2_.D = (!IPL_2_ & RST & !IPL_030_2_.Q - # RST & !IPL_D0_2_.Q & !IPL_030_2_.Q - # RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_2_.Q - # RST & IPL_0_ & !IPL_D0_0_.Q & !IPL_030_2_.Q - # RST & !IPL_1_ & IPL_D0_1_.Q & !IPL_030_2_.Q - # RST & IPL_1_ & !IPL_D0_1_.Q & !IPL_030_2_.Q - # !IPL_2_ & RST & IPL_1_ & IPL_0_ & IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q - # !IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q - # !IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q - # !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q); +IPL_030_2_.T = (!RST & !IPL_030_2_.Q + # IPL_2_ & IPL_1_ & IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & IPL_D0_0_.Q & IPL_D0_1_.Q & IPL_D0_2_.Q & !IPL_030_2_.Q + # IPL_2_ & IPL_1_ & !IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !IPL_D0_0_.Q & IPL_D0_1_.Q & IPL_D0_2_.Q & !IPL_030_2_.Q + # IPL_2_ & !IPL_1_ & IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q & !IPL_030_2_.Q + # IPL_2_ & !IPL_1_ & !IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q & !IPL_030_2_.Q + # !IPL_2_ & RST & IPL_1_ & IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q & IPL_030_2_.Q + # !IPL_2_ & RST & IPL_1_ & !IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q & IPL_030_2_.Q + # !IPL_2_ & RST & !IPL_1_ & IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q & IPL_030_2_.Q + # !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q & IPL_030_2_.Q); IPL_030_2_.C = (CLK_OSZI); @@ -304,12 +301,6 @@ RW_000.C = (CLK_OSZI); BG_000.C = (CLK_OSZI); -BGACK_030.D = (!RST - # BGACK_000 & BGACK_030.Q - # BGACK_000 & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & AS_000.PIN); - -BGACK_030.C = (CLK_OSZI); - SIZE_0_.OE = (!nEXP_SPACE & !BGACK_030.Q); !SIZE_0_.D = (RST & BGACK_030.Q & !inst_BGACK_030_INT_D.Q @@ -318,6 +309,12 @@ SIZE_0_.OE = (!nEXP_SPACE & !BGACK_030.Q); SIZE_0_.C = (CLK_OSZI); +BGACK_030.D = (!RST + # BGACK_000 & BGACK_030.Q + # BGACK_000 & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & AS_000.PIN); + +BGACK_030.C = (CLK_OSZI); + CLK_EXP.D = (inst_CLK_OUT_PRE_D.Q); CLK_EXP.C = (CLK_OSZI); @@ -343,29 +340,27 @@ A_0_.D = (!RST A_0_.C = (CLK_OSZI); -!IPL_030_1_.D = (RST & !IPL_1_ & !IPL_030_1_.Q - # RST & !IPL_D0_1_.Q & !IPL_030_1_.Q - # RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_1_.Q - # RST & IPL_0_ & !IPL_D0_0_.Q & !IPL_030_1_.Q - # !IPL_2_ & RST & IPL_D0_2_.Q & !IPL_030_1_.Q - # IPL_2_ & RST & !IPL_D0_2_.Q & !IPL_030_1_.Q - # IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q - # IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q - # !IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q - # !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q); +IPL_030_1_.T = (!RST & !IPL_030_1_.Q + # IPL_2_ & IPL_1_ & IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & IPL_D0_0_.Q & IPL_D0_1_.Q & IPL_D0_2_.Q & !IPL_030_1_.Q + # IPL_2_ & IPL_1_ & !IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !IPL_D0_0_.Q & IPL_D0_1_.Q & IPL_D0_2_.Q & !IPL_030_1_.Q + # !IPL_2_ & IPL_1_ & IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q & !IPL_030_1_.Q + # !IPL_2_ & IPL_1_ & !IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q & !IPL_030_1_.Q + # IPL_2_ & RST & !IPL_1_ & IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q & IPL_030_1_.Q + # IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q & IPL_030_1_.Q + # !IPL_2_ & RST & !IPL_1_ & IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q & IPL_030_1_.Q + # !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q & IPL_030_1_.Q); IPL_030_1_.C = (CLK_OSZI); -!IPL_030_0_.D = (RST & !IPL_0_ & !IPL_030_0_.Q - # RST & !IPL_D0_0_.Q & !IPL_030_0_.Q - # RST & !IPL_1_ & IPL_D0_1_.Q & !IPL_030_0_.Q - # RST & IPL_1_ & !IPL_D0_1_.Q & !IPL_030_0_.Q - # !IPL_2_ & RST & IPL_D0_2_.Q & !IPL_030_0_.Q - # IPL_2_ & RST & !IPL_D0_2_.Q & !IPL_030_0_.Q - # IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & IPL_D0_2_.Q - # IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q - # !IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q - # !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q); +IPL_030_0_.T = (!RST & !IPL_030_0_.Q + # IPL_2_ & IPL_1_ & IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & IPL_D0_0_.Q & IPL_D0_1_.Q & IPL_D0_2_.Q & !IPL_030_0_.Q + # IPL_2_ & !IPL_1_ & IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q & !IPL_030_0_.Q + # !IPL_2_ & IPL_1_ & IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q & !IPL_030_0_.Q + # !IPL_2_ & !IPL_1_ & IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q & !IPL_030_0_.Q + # IPL_2_ & RST & IPL_1_ & !IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !IPL_D0_0_.Q & IPL_D0_1_.Q & IPL_D0_2_.Q & IPL_030_0_.Q + # IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q & IPL_030_0_.Q + # !IPL_2_ & RST & IPL_1_ & !IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q & IPL_030_0_.Q + # !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q & IPL_030_0_.Q); IPL_030_0_.C = (CLK_OSZI); @@ -395,6 +390,11 @@ cpu_est_1_.D = (!cpu_est_0_.Q & cpu_est_1_.Q cpu_est_1_.C = (CLK_OSZI); +!inst_AMIGA_BUS_ENABLE_DMA_HIGH.D = (RST & !A_1_ & !BGACK_030.Q + # RST & BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q & inst_BGACK_030_INT_D.Q); + +inst_AMIGA_BUS_ENABLE_DMA_HIGH.C = (CLK_OSZI); + !inst_AMIGA_BUS_ENABLE_DMA_LOW.D = (RST & A_1_ & !BGACK_030.Q # RST & BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_LOW.Q & inst_BGACK_030_INT_D.Q); @@ -457,13 +457,9 @@ CYCLE_DMA_1_.C = (CLK_OSZI); inst_VPA_D.C = (CLK_OSZI); -CLK_000_D_2_.D = (CLK_000_D_1_.Q); +CLK_000_D_3_.D = (CLK_000_D_2_.Q); -CLK_000_D_2_.C = (CLK_OSZI); - -CLK_000_D_4_.D = (CLK_000_D_3_.Q); - -CLK_000_D_4_.C = (CLK_OSZI); +CLK_000_D_3_.C = (CLK_OSZI); !inst_DTACK_D0.D = (!DTACK & RST); @@ -502,36 +498,13 @@ IPL_D0_1_.C = (CLK_OSZI); IPL_D0_2_.C = (CLK_OSZI); -CLK_000_D_3_.D = (CLK_000_D_2_.Q); +CLK_000_D_2_.D = (CLK_000_D_1_.Q); -CLK_000_D_3_.C = (CLK_OSZI); +CLK_000_D_2_.C = (CLK_OSZI); -CLK_000_D_5_.D = (CLK_000_D_4_.Q); +CLK_000_D_4_.D = (CLK_000_D_3_.Q); -CLK_000_D_5_.C = (CLK_OSZI); - -!inst_AMIGA_BUS_ENABLE_DMA_HIGH.D = (RST & !A_1_ & !BGACK_030.Q - # RST & BGACK_030.Q & inst_BGACK_030_INT_D.Q & !inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q); - -inst_AMIGA_BUS_ENABLE_DMA_HIGH.C = (CLK_OSZI); - -SM_AMIGA_1_.D = (RST & CLK_000_D_2_.Q & SM_AMIGA_1_.Q - # RST & !CLK_000_D_3_.Q & SM_AMIGA_1_.Q - # RST & SM_AMIGA_1_.Q & SM_AMIGA_2_.Q - # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_2_.Q); - -SM_AMIGA_1_.C = (CLK_OSZI); - -!inst_UDS_000_INT.D = (RST & !inst_UDS_000_INT.Q & !SM_AMIGA_6_.Q - # RST & SM_AMIGA_6_.Q & !A_0_.PIN); - -inst_UDS_000_INT.C = (CLK_OSZI); - -inst_DS_000_ENABLE.D = (RST & inst_DS_000_ENABLE.Q & !AS_030.PIN - # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_4_.Q - # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q & RW.PIN); - -inst_DS_000_ENABLE.C = (CLK_OSZI); +CLK_000_D_4_.C = (CLK_OSZI); inst_LDS_000_INT.D = (!RST # inst_LDS_000_INT.Q & !SM_AMIGA_6_.Q @@ -539,9 +512,20 @@ inst_LDS_000_INT.D = (!RST inst_LDS_000_INT.C = (CLK_OSZI); +inst_DS_000_ENABLE.D = (RST & inst_DS_000_ENABLE.Q & !AS_030.PIN + # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_4_.Q + # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q & RW.PIN); + +inst_DS_000_ENABLE.C = (CLK_OSZI); + +!inst_UDS_000_INT.D = (RST & !inst_UDS_000_INT.Q & !SM_AMIGA_6_.Q + # RST & SM_AMIGA_6_.Q & !A_0_.PIN); + +inst_UDS_000_INT.C = (CLK_OSZI); + SM_AMIGA_6_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_6_.Q # RST & !CLK_000_D_0_.Q & SM_AMIGA_6_.Q - # nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_4_.Q & CLK_000_D_5_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_i_7_.Q); + # nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_3_.Q & CLK_000_D_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_i_7_.Q); SM_AMIGA_6_.C = (CLK_OSZI); @@ -551,10 +535,15 @@ SM_AMIGA_4_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_4_.Q SM_AMIGA_4_.C = (CLK_OSZI); +SM_AMIGA_1_.D = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_2_.Q + # RST & !CLK_000_D_1_.Q & SM_AMIGA_1_.Q & !SM_AMIGA_2_.Q + # RST & CLK_000_D_0_.Q & SM_AMIGA_1_.Q & !SM_AMIGA_2_.Q); + +SM_AMIGA_1_.C = (CLK_OSZI); + SM_AMIGA_0_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_0_.Q # RST & !CLK_000_D_0_.Q & SM_AMIGA_0_.Q - # RST & SM_AMIGA_1_.Q & SM_AMIGA_0_.Q - # RST & !CLK_000_D_2_.Q & CLK_000_D_3_.Q & SM_AMIGA_1_.Q); + # RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_1_.Q); SM_AMIGA_0_.C = (CLK_OSZI); @@ -589,7 +578,7 @@ inst_CLK_030_H.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & inst inst_CLK_030_H.C = (CLK_OSZI); !inst_DSACK1_INT.D = (RST & !inst_DSACK1_INT.Q & !AS_030.PIN - # RST & !CLK_000_D_2_.Q & CLK_000_D_3_.Q & SM_AMIGA_1_.Q); + # RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_1_.Q); inst_DSACK1_INT.C = (CLK_OSZI); @@ -622,9 +611,9 @@ SM_AMIGA_2_.C = (CLK_OSZI); SM_AMIGA_i_7_.T.X1 = (!RST & SM_AMIGA_i_7_.Q # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_0_.Q & SM_AMIGA_i_7_.Q - # nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_4_.Q & CLK_000_D_5_.Q & !SM_AMIGA_i_7_.Q); + # nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_3_.Q & CLK_000_D_4_.Q & !SM_AMIGA_i_7_.Q); -SM_AMIGA_i_7_.T.X2 = (nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_4_.Q & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & CLK_000_D_5_.Q & SM_AMIGA_0_.Q & !SM_AMIGA_i_7_.Q); +SM_AMIGA_i_7_.T.X2 = (nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_3_.Q & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & CLK_000_D_4_.Q & SM_AMIGA_0_.Q & !SM_AMIGA_i_7_.Q); SM_AMIGA_i_7_.C = (CLK_OSZI); diff --git a/Logic/68030_tk.fti b/Logic/68030_tk.fti index 01d4be2..64be994 100644 --- a/Logic/68030_tk.fti +++ b/Logic/68030_tk.fti @@ -1,5 +1,5 @@ #PLAFILE 68030_tk.tt4 -#DATE 08/23/2016 +#DATE 10/08/2016 #DESIGN #DEVICE mach447a @@ -34,20 +34,19 @@ DATA LOCATION BGACK_030:H_4_83 // IO {RN_BGACK_030} DATA LOCATION BG_000:D_1_29 // IO {RN_BG_000} DATA LOCATION BG_030:C_*_21 // INP DATA LOCATION CIIN:E_12_47 // OUT -DATA LOCATION CIIN_0:E_5 // NOD +DATA LOCATION CIIN_0:E_9 // NOD DATA LOCATION CLK_000:*_*_11 // INP -DATA LOCATION CLK_000_D_0_:D_9 // NOD +DATA LOCATION CLK_000_D_0_:C_9 // NOD DATA LOCATION CLK_000_D_1_:H_5 // NOD -DATA LOCATION CLK_000_D_2_:H_2 // NOD -DATA LOCATION CLK_000_D_3_:A_13 // NOD -DATA LOCATION CLK_000_D_4_:A_2 // NOD -DATA LOCATION CLK_000_D_5_:G_10 // NOD +DATA LOCATION CLK_000_D_2_:H_6 // NOD +DATA LOCATION CLK_000_D_3_:D_10 // NOD +DATA LOCATION CLK_000_D_4_:B_10 // NOD DATA LOCATION CLK_030:*_*_64 // INP DATA LOCATION CLK_DIV_OUT:G_1_65 // OUT DATA LOCATION CLK_EXP:B_1_10 // OUT DATA LOCATION CLK_OSZI:*_*_61 // Cin -DATA LOCATION CYCLE_DMA_0_:D_10 // NOD -DATA LOCATION CYCLE_DMA_1_:D_6 // NOD +DATA LOCATION CYCLE_DMA_0_:A_10 // NOD +DATA LOCATION CYCLE_DMA_1_:A_6 // NOD DATA LOCATION DSACK1:H_9_81 // OUT DATA LOCATION DS_030:A_0_98 // OUT DATA LOCATION DTACK:D_*_30 // INP @@ -62,9 +61,9 @@ DATA LOCATION IPL_030_2_:B_4_9 // IO {RN_IPL_030_2_} DATA LOCATION IPL_0_:G_*_67 // INP DATA LOCATION IPL_1_:F_*_56 // INP DATA LOCATION IPL_2_:G_*_68 // INP -DATA LOCATION IPL_D0_0_:A_14 // NOD -DATA LOCATION IPL_D0_1_:B_14 // NOD -DATA LOCATION IPL_D0_2_:G_14 // NOD +DATA LOCATION IPL_D0_0_:G_14 // NOD +DATA LOCATION IPL_D0_1_:D_14 // NOD +DATA LOCATION IPL_D0_2_:B_14 // NOD DATA LOCATION LDS_000:D_12_31 // IO DATA LOCATION RESET:B_2_3 // OUT DATA LOCATION RN_A_0_:G_8 // NOD {A_0_} @@ -79,46 +78,46 @@ DATA LOCATION RN_SIZE_0_:G_12 // NOD {SIZE_0_} DATA LOCATION RN_SIZE_1_:H_12 // NOD {SIZE_1_} DATA LOCATION RN_VMA:D_0 // NOD {VMA} DATA LOCATION RST:*_*_86 // INP -DATA LOCATION RST_DLY_0_:G_9 // NOD -DATA LOCATION RST_DLY_1_:B_10 // NOD -DATA LOCATION RST_DLY_2_:G_13 // NOD +DATA LOCATION RST_DLY_0_:G_2 // NOD +DATA LOCATION RST_DLY_1_:G_10 // NOD +DATA LOCATION RST_DLY_2_:G_6 // NOD DATA LOCATION RW:G_0_71 // IO {RN_RW} DATA LOCATION RW_000:H_0_80 // IO {RN_RW_000} DATA LOCATION SIZE_0_:G_12_70 // IO {RN_SIZE_0_} DATA LOCATION SIZE_1_:H_12_79 // IO {RN_SIZE_1_} -DATA LOCATION SM_AMIGA_0_:A_8 // NOD -DATA LOCATION SM_AMIGA_1_:A_5 // NOD -DATA LOCATION SM_AMIGA_2_:A_6 // NOD -DATA LOCATION SM_AMIGA_3_:A_10 // NOD -DATA LOCATION SM_AMIGA_4_:A_9 // NOD -DATA LOCATION SM_AMIGA_5_:B_13 // NOD -DATA LOCATION SM_AMIGA_6_:F_0 // NOD -DATA LOCATION SM_AMIGA_i_7_:F_8 // NOD +DATA LOCATION SM_AMIGA_0_:H_13 // NOD +DATA LOCATION SM_AMIGA_1_:F_4 // NOD +DATA LOCATION SM_AMIGA_2_:A_5 // NOD +DATA LOCATION SM_AMIGA_3_:D_13 // NOD +DATA LOCATION SM_AMIGA_4_:D_2 // NOD +DATA LOCATION SM_AMIGA_5_:C_6 // NOD +DATA LOCATION SM_AMIGA_6_:C_13 // NOD +DATA LOCATION SM_AMIGA_i_7_:C_2 // NOD DATA LOCATION UDS_000:D_8_32 // IO DATA LOCATION VMA:D_0_35 // IO {RN_VMA} DATA LOCATION VPA:*_*_36 // INP -DATA LOCATION cpu_est_0_:D_14 // NOD -DATA LOCATION cpu_est_1_:D_13 // NOD -DATA LOCATION cpu_est_2_:D_2 // NOD -DATA LOCATION cpu_est_3_:A_12 // NOD -DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_HIGH:G_2 // NOD -DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_LOW:G_6 // NOD -DATA LOCATION inst_AS_000_DMA:C_13 // NOD -DATA LOCATION inst_AS_000_INT:C_6 // NOD -DATA LOCATION inst_AS_030_000_SYNC:F_4 // NOD -DATA LOCATION inst_AS_030_D0:H_13 // NOD -DATA LOCATION inst_BGACK_030_INT_D:A_1 // NOD -DATA LOCATION inst_CLK_030_H:C_14 // NOD -DATA LOCATION inst_CLK_OUT_PRE_50:E_9 // NOD -DATA LOCATION inst_CLK_OUT_PRE_D:E_8 // NOD -DATA LOCATION inst_DSACK1_INT:F_12 // NOD -DATA LOCATION inst_DS_000_DMA:C_9 // NOD -DATA LOCATION inst_DS_000_ENABLE:B_6 // NOD -DATA LOCATION inst_DTACK_D0:H_6 // NOD -DATA LOCATION inst_LDS_000_INT:C_2 // NOD +DATA LOCATION cpu_est_0_:G_9 // NOD +DATA LOCATION cpu_est_1_:A_8 // NOD +DATA LOCATION cpu_est_2_:A_12 // NOD +DATA LOCATION cpu_est_3_:D_9 // NOD +DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_HIGH:C_14 // NOD +DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_LOW:F_1 // NOD +DATA LOCATION inst_AS_000_DMA:A_1 // NOD +DATA LOCATION inst_AS_000_INT:C_10 // NOD +DATA LOCATION inst_AS_030_000_SYNC:F_0 // NOD +DATA LOCATION inst_AS_030_D0:E_5 // NOD +DATA LOCATION inst_BGACK_030_INT_D:E_8 // NOD +DATA LOCATION inst_CLK_030_H:A_2 // NOD +DATA LOCATION inst_CLK_OUT_PRE_50:G_13 // NOD +DATA LOCATION inst_CLK_OUT_PRE_D:D_6 // NOD +DATA LOCATION inst_DSACK1_INT:H_2 // NOD +DATA LOCATION inst_DS_000_DMA:A_13 // NOD +DATA LOCATION inst_DS_000_ENABLE:B_13 // NOD +DATA LOCATION inst_DTACK_D0:B_6 // NOD +DATA LOCATION inst_LDS_000_INT:F_8 // NOD DATA LOCATION inst_RESET_OUT:G_5 // NOD -DATA LOCATION inst_UDS_000_INT:F_1 // NOD -DATA LOCATION inst_VPA_D:C_10 // NOD +DATA LOCATION inst_UDS_000_INT:F_12 // NOD +DATA LOCATION inst_VPA_D:A_9 // NOD DATA LOCATION nEXP_SPACE:*_*_14 // INP DATA IO_DIR AHIGH_24_:BI DATA IO_DIR AHIGH_25_:BI @@ -205,55 +204,55 @@ DATA PW_LEVEL BERR:1 DATA SLEW BERR:0 DATA PW_LEVEL BG_030:1 DATA SLEW BG_030:1 -DATA PW_LEVEL BGACK_000:1 -DATA SLEW BGACK_000:1 -DATA SLEW CLK_030:1 DATA PW_LEVEL AHIGH_30_:1 DATA SLEW AHIGH_30_:0 -DATA SLEW CLK_000:1 +DATA PW_LEVEL BGACK_000:1 +DATA SLEW BGACK_000:1 DATA PW_LEVEL AHIGH_29_:1 DATA SLEW AHIGH_29_:0 -DATA SLEW CLK_OSZI:1 +DATA SLEW CLK_030:1 DATA PW_LEVEL AHIGH_28_:1 DATA SLEW AHIGH_28_:0 -DATA PW_LEVEL CLK_DIV_OUT:1 -DATA SLEW CLK_DIV_OUT:0 +DATA SLEW CLK_000:1 DATA PW_LEVEL AHIGH_27_:1 DATA SLEW AHIGH_27_:0 +DATA SLEW CLK_OSZI:1 DATA PW_LEVEL AHIGH_26_:1 DATA SLEW AHIGH_26_:0 -DATA PW_LEVEL FPU_CS:1 -DATA SLEW FPU_CS:0 +DATA PW_LEVEL CLK_DIV_OUT:1 +DATA SLEW CLK_DIV_OUT:0 DATA PW_LEVEL AHIGH_25_:1 DATA SLEW AHIGH_25_:0 -DATA PW_LEVEL FPU_SENSE:1 -DATA SLEW FPU_SENSE:1 DATA PW_LEVEL AHIGH_24_:1 DATA SLEW AHIGH_24_:0 -DATA PW_LEVEL DSACK1:1 -DATA SLEW DSACK1:0 +DATA PW_LEVEL FPU_CS:1 +DATA SLEW FPU_CS:0 DATA PW_LEVEL A_DECODE_22_:1 DATA SLEW A_DECODE_22_:1 -DATA PW_LEVEL DTACK:1 -DATA SLEW DTACK:1 +DATA PW_LEVEL FPU_SENSE:1 +DATA SLEW FPU_SENSE:1 DATA PW_LEVEL A_DECODE_21_:1 DATA SLEW A_DECODE_21_:1 -DATA PW_LEVEL AVEC:1 -DATA SLEW AVEC:0 +DATA PW_LEVEL DSACK1:1 +DATA SLEW DSACK1:0 DATA PW_LEVEL A_DECODE_20_:1 DATA SLEW A_DECODE_20_:1 -DATA PW_LEVEL E:1 -DATA SLEW E:0 +DATA PW_LEVEL DTACK:1 +DATA SLEW DTACK:1 DATA PW_LEVEL A_DECODE_19_:1 DATA SLEW A_DECODE_19_:1 -DATA SLEW VPA:1 +DATA PW_LEVEL AVEC:1 +DATA SLEW AVEC:0 DATA PW_LEVEL A_DECODE_18_:1 DATA SLEW A_DECODE_18_:1 +DATA PW_LEVEL E:1 +DATA SLEW E:0 DATA PW_LEVEL A_DECODE_17_:1 DATA SLEW A_DECODE_17_:1 -DATA SLEW RST:1 +DATA SLEW VPA:1 DATA PW_LEVEL A_DECODE_16_:1 DATA SLEW A_DECODE_16_:1 +DATA SLEW RST:1 DATA PW_LEVEL RESET:1 DATA SLEW RESET:0 DATA PW_LEVEL AMIGA_ADDR_ENABLE:1 @@ -282,10 +281,10 @@ DATA PW_LEVEL RW_000:1 DATA SLEW RW_000:0 DATA PW_LEVEL BG_000:1 DATA SLEW BG_000:0 -DATA PW_LEVEL BGACK_030:1 -DATA SLEW BGACK_030:0 DATA PW_LEVEL SIZE_0_:1 DATA SLEW SIZE_0_:0 +DATA PW_LEVEL BGACK_030:1 +DATA SLEW BGACK_030:0 DATA PW_LEVEL CLK_EXP:1 DATA SLEW CLK_EXP:0 DATA PW_LEVEL VMA:1 @@ -306,6 +305,8 @@ DATA PW_LEVEL cpu_est_0_:1 DATA SLEW cpu_est_0_:1 DATA PW_LEVEL cpu_est_1_:1 DATA SLEW cpu_est_1_:1 +DATA PW_LEVEL inst_AMIGA_BUS_ENABLE_DMA_HIGH:1 +DATA SLEW inst_AMIGA_BUS_ENABLE_DMA_HIGH:1 DATA PW_LEVEL inst_AMIGA_BUS_ENABLE_DMA_LOW:1 DATA SLEW inst_AMIGA_BUS_ENABLE_DMA_LOW:1 DATA PW_LEVEL inst_AS_030_D0:1 @@ -324,10 +325,8 @@ DATA PW_LEVEL CYCLE_DMA_1_:1 DATA SLEW CYCLE_DMA_1_:1 DATA PW_LEVEL inst_VPA_D:1 DATA SLEW inst_VPA_D:1 -DATA PW_LEVEL CLK_000_D_2_:1 -DATA SLEW CLK_000_D_2_:1 -DATA PW_LEVEL CLK_000_D_4_:1 -DATA SLEW CLK_000_D_4_:1 +DATA PW_LEVEL CLK_000_D_3_:1 +DATA SLEW CLK_000_D_3_:1 DATA PW_LEVEL inst_DTACK_D0:1 DATA SLEW inst_DTACK_D0:1 DATA PW_LEVEL inst_RESET_OUT:1 @@ -346,24 +345,22 @@ DATA PW_LEVEL IPL_D0_1_:1 DATA SLEW IPL_D0_1_:1 DATA PW_LEVEL IPL_D0_2_:1 DATA SLEW IPL_D0_2_:1 -DATA PW_LEVEL CLK_000_D_3_:1 -DATA SLEW CLK_000_D_3_:1 -DATA PW_LEVEL CLK_000_D_5_:1 -DATA SLEW CLK_000_D_5_:1 -DATA PW_LEVEL inst_AMIGA_BUS_ENABLE_DMA_HIGH:1 -DATA SLEW inst_AMIGA_BUS_ENABLE_DMA_HIGH:1 -DATA PW_LEVEL SM_AMIGA_1_:1 -DATA SLEW SM_AMIGA_1_:1 -DATA PW_LEVEL inst_UDS_000_INT:1 -DATA SLEW inst_UDS_000_INT:1 -DATA PW_LEVEL inst_DS_000_ENABLE:1 -DATA SLEW inst_DS_000_ENABLE:1 +DATA PW_LEVEL CLK_000_D_2_:1 +DATA SLEW CLK_000_D_2_:1 +DATA PW_LEVEL CLK_000_D_4_:1 +DATA SLEW CLK_000_D_4_:1 DATA PW_LEVEL inst_LDS_000_INT:1 DATA SLEW inst_LDS_000_INT:1 +DATA PW_LEVEL inst_DS_000_ENABLE:1 +DATA SLEW inst_DS_000_ENABLE:1 +DATA PW_LEVEL inst_UDS_000_INT:1 +DATA SLEW inst_UDS_000_INT:1 DATA PW_LEVEL SM_AMIGA_6_:1 DATA SLEW SM_AMIGA_6_:1 DATA PW_LEVEL SM_AMIGA_4_:1 DATA SLEW SM_AMIGA_4_:1 +DATA PW_LEVEL SM_AMIGA_1_:1 +DATA SLEW SM_AMIGA_1_:1 DATA PW_LEVEL SM_AMIGA_0_:1 DATA SLEW SM_AMIGA_0_:1 DATA PW_LEVEL RST_DLY_0_:1 @@ -392,8 +389,8 @@ DATA PW_LEVEL RN_SIZE_1_:1 DATA PW_LEVEL RN_IPL_030_2_:1 DATA PW_LEVEL RN_RW_000:1 DATA PW_LEVEL RN_BG_000:1 -DATA PW_LEVEL RN_BGACK_030:1 DATA PW_LEVEL RN_SIZE_0_:1 +DATA PW_LEVEL RN_BGACK_030:1 DATA PW_LEVEL RN_VMA:1 DATA PW_LEVEL RN_RW:1 DATA PW_LEVEL RN_A_0_:1 diff --git a/Logic/68030_tk.grp b/Logic/68030_tk.grp index eb06fec..5f92eba 100644 --- a/Logic/68030_tk.grp +++ b/Logic/68030_tk.grp @@ -1,23 +1,23 @@ -GROUP MACH_SEG_A DS_030 AVEC SM_AMIGA_2_ SM_AMIGA_3_ SM_AMIGA_1_ SM_AMIGA_0_ - cpu_est_3_ SM_AMIGA_4_ IPL_D0_0_ inst_BGACK_030_INT_D CLK_000_D_4_ - CLK_000_D_3_ +GROUP MACH_SEG_A DS_030 AVEC SM_AMIGA_2_ inst_DS_000_DMA inst_CLK_030_H + inst_AS_000_DMA CYCLE_DMA_1_ CYCLE_DMA_0_ cpu_est_2_ cpu_est_1_ inst_VPA_D + GROUP MACH_SEG_B IPL_030_1_ RN_IPL_030_1_ IPL_030_0_ RN_IPL_030_0_ IPL_030_2_ RN_IPL_030_2_ AHIGH_31_ AHIGH_30_ AHIGH_29_ CLK_EXP RESET inst_DS_000_ENABLE - RST_DLY_1_ SM_AMIGA_5_ IPL_D0_1_ + inst_DTACK_D0 IPL_D0_2_ CLK_000_D_4_ GROUP MACH_SEG_C AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ AMIGA_BUS_ENABLE_LOW - inst_DS_000_DMA inst_CLK_030_H inst_AS_000_DMA inst_LDS_000_INT inst_AS_000_INT - inst_VPA_D -GROUP MACH_SEG_D VMA RN_VMA BG_000 RN_BG_000 LDS_000 UDS_000 AMIGA_BUS_ENABLE_HIGH - AMIGA_ADDR_ENABLE CYCLE_DMA_1_ CYCLE_DMA_0_ cpu_est_2_ cpu_est_1_ - cpu_est_0_ CLK_000_D_0_ -GROUP MACH_SEG_E CIIN BERR AMIGA_BUS_DATA_DIR AS_000 CIIN_0 inst_CLK_OUT_PRE_50 - inst_CLK_OUT_PRE_D -GROUP MACH_SEG_F inst_AS_030_000_SYNC SM_AMIGA_i_7_ SM_AMIGA_6_ inst_DSACK1_INT - inst_UDS_000_INT + SM_AMIGA_i_7_ SM_AMIGA_6_ inst_AS_000_INT inst_AMIGA_BUS_ENABLE_DMA_HIGH + SM_AMIGA_5_ CLK_000_D_0_ +GROUP MACH_SEG_D VMA RN_VMA BG_000 RN_BG_000 AMIGA_BUS_ENABLE_HIGH LDS_000 + UDS_000 AMIGA_ADDR_ENABLE SM_AMIGA_3_ cpu_est_3_ SM_AMIGA_4_ IPL_D0_1_ + CLK_000_D_3_ inst_CLK_OUT_PRE_D +GROUP MACH_SEG_E CIIN BERR AMIGA_BUS_DATA_DIR AS_000 CIIN_0 inst_AS_030_D0 + inst_BGACK_030_INT_D +GROUP MACH_SEG_F inst_AS_030_000_SYNC inst_LDS_000_INT inst_AMIGA_BUS_ENABLE_DMA_LOW + SM_AMIGA_1_ inst_UDS_000_INT GROUP MACH_SEG_G SIZE_0_ RN_SIZE_0_ A_0_ RN_A_0_ RW RN_RW E CLK_DIV_OUT - inst_RESET_OUT RST_DLY_0_ RST_DLY_2_ inst_AMIGA_BUS_ENABLE_DMA_LOW - inst_AMIGA_BUS_ENABLE_DMA_HIGH IPL_D0_2_ CLK_000_D_5_ + inst_RESET_OUT RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ cpu_est_0_ IPL_D0_0_ + inst_CLK_OUT_PRE_50 GROUP MACH_SEG_H RW_000 RN_RW_000 FPU_CS SIZE_1_ RN_SIZE_1_ BGACK_030 RN_BGACK_030 - AS_030 DSACK1 inst_DTACK_D0 inst_AS_030_D0 CLK_000_D_2_ CLK_000_D_1_ + AS_030 DSACK1 inst_DSACK1_INT SM_AMIGA_0_ CLK_000_D_2_ CLK_000_D_1_ \ No newline at end of file diff --git a/Logic/68030_tk.ipr b/Logic/68030_tk.ipr index a05006a..c87fa85 100644 --- a/Logic/68030_tk.ipr +++ b/Logic/68030_tk.ipr @@ -1 +1 @@ -2407<23z>bW P \ No newline at end of file +513;200c7,FKup \ No newline at end of file diff --git a/Logic/68030_tk.jed b/Logic/68030_tk.jed index 9912c4e..2cdfb67 100644 --- a/Logic/68030_tk.jed +++ b/Logic/68030_tk.jed @@ -10,7 +10,7 @@ AUTHOR: PATTERN: COMPANY: REVISION: -DATE: Thu Oct 06 22:04:16 2016 +DATE: Sat Oct 15 23:48:29 2016 ABEL mach447a * @@ -33,17 +33,17 @@ NOTE Zero Hold Time For Input Registers? Y * NOTE Table of pin names and numbers* NOTE PINS AHIGH_31_:4 A_DECODE_23_:85 IPL_2_:68 FC_1_:58* NOTE PINS AS_030:82 AS_000:42 DS_030:98 UDS_000:32 LDS_000:31* -NOTE PINS nEXP_SPACE:14 BERR:41 BG_030:21 BGACK_000:28 CLK_030:64* -NOTE PINS AHIGH_30_:5 CLK_000:11 AHIGH_29_:6 CLK_OSZI:61* -NOTE PINS AHIGH_28_:15 CLK_DIV_OUT:65 AHIGH_27_:16 AHIGH_26_:17* -NOTE PINS FPU_CS:78 AHIGH_25_:18 FPU_SENSE:91 AHIGH_24_:19* -NOTE PINS DSACK1:81 A_DECODE_22_:84 DTACK:30 A_DECODE_21_:94* -NOTE PINS AVEC:92 A_DECODE_20_:93 E:66 A_DECODE_19_:97 VPA:36* -NOTE PINS A_DECODE_18_:95 A_DECODE_17_:59 RST:86 A_DECODE_16_:96* +NOTE PINS nEXP_SPACE:14 BERR:41 BG_030:21 AHIGH_30_:5 BGACK_000:28* +NOTE PINS AHIGH_29_:6 CLK_030:64 AHIGH_28_:15 CLK_000:11* +NOTE PINS AHIGH_27_:16 CLK_OSZI:61 AHIGH_26_:17 CLK_DIV_OUT:65* +NOTE PINS AHIGH_25_:18 AHIGH_24_:19 FPU_CS:78 A_DECODE_22_:84* +NOTE PINS FPU_SENSE:91 A_DECODE_21_:94 DSACK1:81 A_DECODE_20_:93* +NOTE PINS DTACK:30 A_DECODE_19_:97 AVEC:92 A_DECODE_18_:95* +NOTE PINS E:66 A_DECODE_17_:59 VPA:36 A_DECODE_16_:96 RST:86* NOTE PINS RESET:3 AMIGA_ADDR_ENABLE:33 AMIGA_BUS_DATA_DIR:48* NOTE PINS AMIGA_BUS_ENABLE_LOW:20 AMIGA_BUS_ENABLE_HIGH:34* NOTE PINS CIIN:47 IPL_1_:56 IPL_0_:67 FC_0_:57 A_1_:60 SIZE_1_:79* -NOTE PINS IPL_030_2_:9 RW_000:80 BG_000:29 BGACK_030:83 SIZE_0_:70* +NOTE PINS IPL_030_2_:9 RW_000:80 BG_000:29 SIZE_0_:70 BGACK_030:83* NOTE PINS CLK_EXP:10 VMA:35 RW:71 A_0_:69 IPL_030_1_:7 IPL_030_0_:8* NOTE Table of node names and numbers* NOTE NODES RN_AHIGH_31_:143 RN_AS_030:281 RN_AS_000:203 * @@ -51,54 +51,54 @@ NOTE NODES RN_UDS_000:185 RN_LDS_000:191 RN_BERR:197 RN_AHIGH_30_:125 * NOTE NODES RN_AHIGH_29_:137 RN_AHIGH_28_:149 RN_AHIGH_27_:157 * NOTE NODES RN_AHIGH_26_:155 RN_AHIGH_25_:167 RN_AHIGH_24_:161 * NOTE NODES RN_SIZE_1_:287 RN_IPL_030_2_:131 RN_RW_000:269 * -NOTE NODES RN_BG_000:175 RN_BGACK_030:275 RN_SIZE_0_:263 * +NOTE NODES RN_BG_000:175 RN_SIZE_0_:263 RN_BGACK_030:275 * NOTE NODES RN_VMA:173 RN_RW:245 RN_A_0_:257 RN_IPL_030_1_:139 * -NOTE NODES RN_IPL_030_0_:133 cpu_est_2_:176 cpu_est_3_:119 * -NOTE NODES cpu_est_0_:194 cpu_est_1_:193 inst_AMIGA_BUS_ENABLE_DMA_LOW:254 * -NOTE NODES inst_AS_030_D0:289 inst_AS_030_000_SYNC:227 inst_BGACK_030_INT_D:103 * -NOTE NODES inst_AS_000_DMA:169 inst_DS_000_DMA:163 CYCLE_DMA_0_:188 * -NOTE NODES CYCLE_DMA_1_:182 inst_VPA_D:164 CLK_000_D_2_:272 * -NOTE NODES CLK_000_D_4_:104 inst_DTACK_D0:278 inst_RESET_OUT:253 * -NOTE NODES CLK_000_D_1_:277 CLK_000_D_0_:187 inst_CLK_OUT_PRE_50:211 * -NOTE NODES inst_CLK_OUT_PRE_D:209 IPL_D0_0_:122 IPL_D0_1_:146 * -NOTE NODES IPL_D0_2_:266 CLK_000_D_3_:121 CLK_000_D_5_:260 * -NOTE NODES inst_AMIGA_BUS_ENABLE_DMA_HIGH:248 SM_AMIGA_1_:109 * -NOTE NODES inst_UDS_000_INT:223 inst_DS_000_ENABLE:134 inst_LDS_000_INT:152 * -NOTE NODES SM_AMIGA_6_:221 SM_AMIGA_4_:115 SM_AMIGA_0_:113 * -NOTE NODES RST_DLY_0_:259 RST_DLY_1_:140 RST_DLY_2_:265 * -NOTE NODES inst_CLK_030_H:170 inst_DSACK1_INT:239 inst_AS_000_INT:158 * -NOTE NODES SM_AMIGA_5_:145 SM_AMIGA_3_:116 SM_AMIGA_2_:110 * -NOTE NODES SM_AMIGA_i_7_:233 CIIN_0:205 * +NOTE NODES RN_IPL_030_0_:133 cpu_est_2_:119 cpu_est_3_:187 * +NOTE NODES cpu_est_0_:259 cpu_est_1_:113 inst_AMIGA_BUS_ENABLE_DMA_HIGH:170 * +NOTE NODES inst_AMIGA_BUS_ENABLE_DMA_LOW:223 inst_AS_030_D0:205 * +NOTE NODES inst_AS_030_000_SYNC:221 inst_BGACK_030_INT_D:209 * +NOTE NODES inst_AS_000_DMA:103 inst_DS_000_DMA:121 CYCLE_DMA_0_:116 * +NOTE NODES CYCLE_DMA_1_:110 inst_VPA_D:115 CLK_000_D_3_:188 * +NOTE NODES inst_DTACK_D0:134 inst_RESET_OUT:253 CLK_000_D_1_:277 * +NOTE NODES CLK_000_D_0_:163 inst_CLK_OUT_PRE_50:265 inst_CLK_OUT_PRE_D:182 * +NOTE NODES IPL_D0_0_:266 IPL_D0_1_:194 IPL_D0_2_:146 CLK_000_D_2_:278 * +NOTE NODES CLK_000_D_4_:140 inst_LDS_000_INT:233 inst_DS_000_ENABLE:145 * +NOTE NODES inst_UDS_000_INT:239 SM_AMIGA_6_:169 SM_AMIGA_4_:176 * +NOTE NODES SM_AMIGA_1_:227 SM_AMIGA_0_:289 RST_DLY_0_:248 * +NOTE NODES RST_DLY_1_:260 RST_DLY_2_:254 inst_CLK_030_H:104 * +NOTE NODES inst_DSACK1_INT:272 inst_AS_000_INT:164 SM_AMIGA_5_:158 * +NOTE NODES SM_AMIGA_3_:193 SM_AMIGA_2_:109 SM_AMIGA_i_7_:152 * +NOTE NODES CIIN_0:211 * NOTE BLOCK 0 * L000000 - 111111111111111111111111111111111111111111111111111111110111111111 - 111111011101111101111111111111111111111111111111111111111111111111 + 111111111011111111111111111111111111111111111111111111111111111111 + 111111111101111111111111101111111111111111111101111111111111111111 + 111111111111111111111101111111111111111111111111111111111111111111 + 111111111111111111111111111111111111111111111111111111111111111110 111111111111111111111111111111111111111111111111111111111111111111 - 101111111111111111111111111111111111111111111011111111111111111111 - 111111111111111111111111111111111101111111111111111111111111111111 - 111111111111111111011111111101111111111111111111110111111101111111 - 111111111111111111110111011111111111110111111111111111111111011111 - 111101111111111011111111111011111111111110111111111111111111111111 - 111011111011111111111111111111110111011111101111111110111111111111* + 111111111111111111111111111101111111111111011111010111111111111111 + 111101011111100111111111111111011111111111111111111111011111111111 + 111111111111111101111111111011111111011110111111111111111111111111 + 100111111111111111010111111111111010111111110111111111111111111111* L000594 000000000000000000000000000000000000000000000000000000000000000000* -L000660 111111101111111111111111111111111111111111111111111110111111111111* -L000726 000000000000000000000000000000000000000000000000000000000000000000* -L000792 000000000000000000000000000000000000000000000000000000000000000000* -L000858 000000000000000000000000000000000000000000000000000000000000000000* -L000924 000000000000000000000000000000000000000000000000000000000000000000* -L000990 111111111111111111111111111111111111111110011111111111111111111111* -L001056 000000000000000000000000000000000000000000000000000000000000000000* -L001122 000000000000000000000000000000000000000000000000000000000000000000* +L000660 111111111111111111111111111111111011111111111111111011111111111111* +L000726 101111111111111111111111111111111111111111111111111111111111111111* +L000792 111111111111111111111111111111111111111101111111111111111111111111* +L000858 111111111011111111011111111111111111111111111111111111111111111111* +L000924 111111111111111111111111111101011111111111111111111111111111111111* +L000990 111111111111111111111111111110101111111111111111111111111111111111* +L001056 111111111111111111111111111111110111111111111111111111111111111111* +L001122 111111111111111101111111111111111111111111111111111111011111111111* L001188 000000000000000000000000000000000000000000000000000000000000000000* L001254 000000000000000000000000000000000000000000000000000000000000000000* L001320 111111111111111111111111111111111111111111111111111111111111111111* -L001386 111111111111111111111111111111111111111111111111110111111111111111* -L001452 111111111111111111111111111111111111111111111111111111111111111111* -L001518 111111111111111111111111111111111111111111111111111111111111111111* -L001584 111111111111111111111111111111111111111111111111111111111111111111* -L001650 111111111111111111111111111111111111111111111111111111111111111111* +L001386 011111111011111110101111111110011011111110111111111111111111111111* +L001452 011111111011111110101111111101101011111110111111111111111111111111* +L001518 011111111111111110111111111110011011111110110111111111111111111111* +L001584 011111111111111110111111111101101011111110110111111111111111111111* +L001650 011111111011111111101111111110011011111110111111111111101111111111* L001716 111111111111111111111111111111111111111111111111111111111111111111* L001782 111111111111111111111111111111111111111111111111111111111111111111* L001848 111111111111111111111111111111111111111111111111111111111111111111* @@ -107,22 +107,22 @@ L001980 111111111111111111111111111111111111111111111111111111111111111111* L002046 000000000000000000000000000000000000000000000000000000000000000000* L002112 111111111111111111111111111111111111111111111111111111111111111111* -L002178 111111111111111111111111111111111111111111111111111111111111111111* -L002244 111111111111111111111111111111111111111111111111111111111111111111* -L002310 111111111111111111111111111111111111111111111111111111111111111111* -L002376 111111111111111111111111111111111111111111111111111111111111111111* -L002442 111101110111111111111111111111111111111111011111111111111111111111* -L002508 111101111111111111111111111111111111111111011111111011111111111111* -L002574 111111111111111111110111011011111111111111011111111111111111111111* -L002640 111101111111111111110111111111111111111111011111111111111111111111* -L002706 000000000000000000000000000000000000000000000000000000000000000000* +L002178 011111111011111111101111111101101011111110111111111111101111111111* +L002244 011111111111111111111111111110011011111110110111111111101111111111* +L002310 011111111111111111111111111101101011111110110111111111101111111111* +L002376 000000000000000000000000000000000000000000000000000000000000000000* +L002442 011010101111110111111111100111111111111111011110101111111111111111* +L002508 011101111111111111111110110111111111111111011110111111111111111111* +L002574 011111111111111111111111110111111111011111111111111111111111111111* +L002640 011111111111111111111111111111111111011111111110111111111111111111* +L002706 011111111111111111111111110111111110111111011110111111111111111111* L002772 000000000000000000000000000000000000000000000000000000000000000000* -L002838 111111111111111110011111100101111010101111011111111111111110111111* -L002904 111111111111111001111111100101111111111111011111111111111111111111* -L002970 111111111111111111110111110111111111111111011111111111111111111111* -L003036 111111111111111111110111101111111111111111011111111111111111111111* -L003102 111011111111111111111111100101111111111111011111111111111111111111* +L002838 011111111111111111111111111110011011111110111111111111111111111111* +L002904 011111111111111111111111110111011011111110111111111111111111111111* +L002970 011111111111111111111111111001101011111110111101111111111111111111* +L003036 011111111111111111111111111111011011111110111110111111111111111111* +L003102 000000000000000000000000000000000000000000000000000000000000000000* L003168 111111111111111111111111111111111111111111111111111111111111111111* L003234 111111111111111111111111111111111111111111111111111111111111111111* L003300 111111111111111111111111111111111111111111111111111111111111111111* @@ -130,23 +130,23 @@ L003366 111111111111111111111111111111111111111111111111111111111111111111* L003432 111111111111111111111111111111111111111111111111111111111111111111* L003498 000000000000000000000000000000000000000000000000000000000000000000* -L003564 111101111011111111111111111111111111111111011111110111111111111111* -L003630 111111111111111111111111110111111111111111011111111111111111011111* -L003696 111111111111111111111111101111111111111111011111111111111111011111* -L003762 111101111111111111111111111111111111111111011111111111111111011111* -L003828 000000000000000000000000000000000000000000000000000000000000000000* -L003894 111111111111111111111111110111111111110111011111111111111111111111* -L003960 111111111111111111111111101111111111110111011111111111111111111111* -L004026 111111111111111111111111100111111111111111011111111111110111111111* -L004092 000000000000000000000000000000000000000000000000000000000000000000* -L004158 000000000000000000000000000000000000000000000000000000000000000000* +L003564 111111111111111111111111111111111111111111111111111111111111111111* +L003630 111111111111111111111111111111111111111111111111111111111111111111* +L003696 111111111111111111111111111111111111111111111111111111111111111111* +L003762 111111111111111111111111111111111111111111111111111111111111111111* +L003828 111111111111111111111111111111111111111111111111111111111111111111* +L003894 011111111111111111111011111111111111111111111111111111111111111111* +L003960 111111011111111111111111101111111111111111111111111111111111111111* +L004026 111111011111111111111111111011111111111111111111111111111111111111* +L004092 111111011111111111111111111111111111111111111101111111111111111111* +L004158 111111101111111011111111010111111111111111111110111111111111111111* L004224 000000000000000000000000000000000000000000000000000000000000000000* -L004290 111111111111111111111111111101111111111111101111111111111111111111* -L004356 111111111111111110011111100101111010101111111111111111111110111111* -L004422 111111111111111001111111100101111111111111111111111111111111111111* -L004488 111111111111111111111111011010111111110111011111111111111111111111* -L004554 111011111111111111111111100101111111111111111111111111111111111111* +L004290 011111111111111111111111110101111011111110111111111111111111111111* +L004356 011111111111111111111111111010111011111110111101111111111111111111* +L004422 011111111111111111111111111101111011111110111110111111111111111111* +L004488 000000000000000000000000000000000000000000000000000000000000000000* +L004554 000000000000000000000000000000000000000000000000000000000000000000* L004620 111111111111111111111111111111111111111111111111111111111111111111* L004686 111111111111111111111111111111111111111111111111111111111111111111* L004752 111111111111111111111111111111111111111111111111111111111111111111* @@ -154,23 +154,23 @@ L004818 111111111111111111111111111111111111111111111111111111111111111111* L004884 111111111111111111111111111111111111111111111111111111111111111111* L004950 000000000000000000000000000000000000000000000000000000000000000000* -L005016 111111111111111111011111111111111010111111111111111111111111111111* -L005082 111111111111111111011111111011111111111111111111111111111111111111* -L005148 111111111111111111011111011111111111111111111111111111111111111111* -L005214 111111111111111111111111100111110101111111111111111111111101111111* +L005016 111111011111111111111111010111111111111111111110111111111111111111* +L005082 111111111111111111111111111111111111111111111111011111111111111111* +L005148 000000000000000000000000000000000000000000000000000000000000000000* +L005214 000000000000000000000000000000000000000000000000000000000000000000* L005280 000000000000000000000000000000000000000000000000000000000000000000* -L005346 111111110111111111111111111111111111111111111111111111111111111111* -L005412 111111111111111111111111111111111111111111111111111111111111111111* -L005478 111111111111111111111111111111111111111111111111111111111111111111* -L005544 111111111111111111111111111111111111111111111111111111111111111111* -L005610 111111111111111111111111111111111111111111111111111111111111111111* +L005346 101111111111111111111111111111111111111111111111111111111111111111* +L005412 111111111111111111111111111111111111111101111111111111111111111111* +L005478 111111111111111111111111111101011111111111111111111111111111111111* +L005544 111111111111111111111111111110101111111111111111111111111111111111* +L005610 111111111111111111111111111111110111111111111111111111111111111111* L005676 - 111111111110111111111111111111111111111110110111111111111111111111* -L005742 101111111111111111111111111111111111111111011111111111111111111111* -L005808 111111111111111111111111111111111111111111111111111111111111111111* -L005874 111111111111111111111111111111111111111111111111111111111111111111* -L005940 111111111111111111111111111111111111111111111111111111111111111111* -L006006 111111111111111111111111111111111111111111111111111111111111111111* + 111111111110111111111111111111111111111110111111111111111111111101* +L005742 111111111111111101111111111111111111111111111111111111011111111111* +L005808 111111111011101111111111111111111111111111111111110111111111111111* +L005874 111111110111101111011111111111111111111111110111111111111111111111* +L005940 111111111111101111111111111111111111111111111011110111111111111111* +L006006 000000000000000000000000000000000000000000000000000000000000000000* L006072 111111111111111111111111111111111111111111111111111111111111111111* L006138 111111111111111111111111111111111111111111111111111111111111111111* L006204 111111111111111111111111111111111111111111111111111111111111111111* @@ -180,33 +180,33 @@ L006402 000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000* L006534 0010* -L006538 01100011111000* -L006552 01100110010011* -L006566 00010110010101* +L006538 01010011111000* +L006552 10100110010011* +L006566 10100110010101* L006580 11101011111111* -L006594 00110011111000* +L006594 00000011111000* L006608 10100110010010* L006622 10100110010001* L006636 11101011110011* -L006650 10100110010000* -L006664 10100110010011* -L006678 10100111010001* +L006650 10110110010000* +L006664 01110110010011* +L006678 10100110010001* L006692 11100011110011* -L006706 10100110010000* -L006720 00000110010010* -L006734 01010110010101* -L006748 11101011111111* +L006706 00100110010000* +L006720 10100110010010* +L006734 11111011110101* +L006748 11111111111111* NOTE BLOCK 1 * L006762 - 111111111111111111100111111111111111111101111111111110111111111111 - 111101111101011110111111101111111111111111111111111111111111111111 - 111111111011111111111101111111111111111111111111111111110111111011 - 101111111111111111111111111111111111111111111011111111011111111111 - 111111011111111111111111111111111111111111111111111011111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111110111111111111111111011110111111111111111111111111111 - 111111111111111111111111111011111111111111111110111111111111111110 - 111111111111111111111111111111111111111111101111111111111111111111* + 111111111111111111110110111111111111111101111111111111111111011111 + 111111111101011110111111111111111111111111111101111111111111111111 + 111111111111111111111111111111111111111111101011111111111111110111 + 111111101111111111111111111111111011111111111111111111011111111111 + 111111111111111111111111111111111101111111111111111111111111111111 + 111101111111111111111111111111111111111111111111111111111111111111 + 111111111111111111011111111111111111111111111111111111111111111111 + 101111110111111111111111111011111111111011111111111111111111111111 + 111111111111111111111111111111111111111111111111101111110111111111* L007356 111111111111111111111111111111111111111111111111111111111111111111* L007422 000000000000000000000000000000000000000000000000000000000000000000* @@ -214,7 +214,7 @@ L007488 000000000000000000000000000000000000000000000000000000000000000000* L007554 000000000000000000000000000000000000000000000000000000000000000000* L007620 000000000000000000000000000000000000000000000000000000000000000000* L007686 000000000000000000000000000000000000000000000000000000000000000000* -L007752 111111111111111111111111111111110111111111111111111111111111111111* +L007752 111111110111111111111111111111111111111111111111111111111111111111* L007818 000000000000000000000000000000000000000000000000000000000000000000* L007884 000000000000000000000000000000000000000000000000000000000000000000* L007950 000000000000000000000000000000000000000000000000000000000000000000* @@ -226,74 +226,74 @@ L008214 111111111111111111111111111111111111111111111111111111111111111111* L008280 111111111111111111111111111111111111111111111111111111111111111111* L008346 111111111111111111111111111111111111111111111111111111111111111111* L008412 111111111111111111111111111111111111111111111111111111111111111111* -L008478 011111011011111111111111111111111111111101011111111110111111110111* -L008544 101111101011111111111111111111111111111101011111111110111111110111* -L008610 011111011011111111111111111111111111111110011111111110111111111011* -L008676 101111101011111111111111111111111111111110011111111110111111111011* -L008742 111111111011111111111111111111111111111111011111111111101111111111* +L008478 111111111111111111111101111011110101111110011001011111011111111111* +L008544 111111111111111111111110111011111001111110011001011111011111111111* +L008610 111111111111111111111101111011110110111110101001011111011111111111* +L008676 111111111111111111111110111011111010111110101001011111011111111111* +L008742 111111111111111111111111111111111111111111111111101111101111111111* L008808 111111111111111111111111111111111111111111111111111111111111111111* -L008874 101111011111111111111111111111111111111111011111111111101111111111* -L008940 011111101111111111111111111111111111111111011111111111101111111111* -L009006 111111111111111111111111111111111111111101011111111111101111111011* -L009072 111111111111111111111111111111111111111110011111111111101111110111* -L009138 111111111111111111111111111111111111111111011111111110101111111111* -L009204 101111101011111111111111111111111111111101011111111110111111110111* -L009270 101111101011111111111111111111111111111110011111111110111111111011* -L009336 101111100111111111111111111111111111111110011111111101111111111011* -L009402 101111100111111111111111111111111111111101011111111101111111110111* -L009468 101111111111111111111111111111111111111111011111111111111011111111* +L008874 111111111111111111111101111011110101111101010101111111101111111111* +L008940 111111111111111111111110111011111001111101010101111111101111111111* +L009006 111111111111111111111101111011110110111101100101111111101111111111* +L009072 111111111111111111111110111011111010111101100101111111101111111111* +L009138 000000000000000000000000000000000000000000000000000000000000000000* +L009204 111111111111111111111110111011111001111101010101011111111111110111* +L009270 111111111111111111111110111011111010111101100101011111111111110111* +L009336 111111111111111111111110111011111001111110011001011111111111110111* +L009402 111111111111111111111110111011111010111110101001011111111111110111* +L009468 111111111111111111111111111111111111111111111111101111111111111011* L009534 111111111111111111111111111111111111111111111111111111111111111111* -L009600 111111101111111111111111111111111111111111011111111111111011111111* -L009666 111111111111111111111111111111111111111101011111111111111011111011* -L009732 111111111111111111111111111111111111111110011111111111111011110111* -L009798 111111111011111111111111111111111111111111011111111101111011111111* -L009864 111111110111111111111111111111111111111111011111111110111011111111* +L009600 111111111111111111101111111111111111111111111111011111111111111111* +L009666 111111111111111111111101111011110101111101010101111111111111111011* +L009732 111111111111111111111101111011110110111101100101111111111111111011* +L009798 111111111111111111111101111011110101111110011001111111111111111011* +L009864 111111111111111111111101111011110110111110101001111111111111111011* L009930 111111111111111111111111111111111111111111111111111111111111111111* L009996 111111111111111111111111111111111111111111111111111111111111111111* L010062 111111111111111111111111111111111111111111111111111111111111111111* L010128 111111111111111111111111111111111111111111111111111111111111111111* L010194 111111111111111111111111111111111111111111111111111111111111111111* L010260 - 111111111110111111111111111111111111111111110110111111111111111111* + 101111011110111111111111111111111111111111111111111111111111111111* L010326 000000000000000000000000000000000000000000000000000000000000000000* -L010392 111111111111110111111111111011111111110111011111111111111111111111* -L010458 111111111111111111111101111111111111111111011111111111111111111110* -L010524 111111111111110101111111111011111111111111011111110111111111111111* -L010590 000000000000000000000000000000000000000000000000000000000000000000* -L010656 011111011011111111111111111111111111111110011111111110111111111011* -L010722 101111101011111111111111111111111111111110011111111110111111111011* -L010788 011111010111111111111111111111111111111110011111111101111111111011* -L010854 101111100111111111111111111111111111111110011111111101111111111011* -L010920 111111111111101111111111111111111111111111011111111111111111111011* +L010392 111111111111111111111111111111111111111111111111111111111111111111* +L010458 111111111111111111111111111111111111111111111111111111111111111111* +L010524 111111111111111111111111111111111111111111111111111111111111111111* +L010590 111111111111111111111111111111111111111111111111111111111111111111* +L010656 111111111111011111111101111011110110111101100101011111111111111111* +L010722 111111111111011111111110111011111010111101100101011111111111111111* +L010788 111111111111011111111101111011110110111110101001011111111111111111* +L010854 111111111111011111111110111011111010111110101001011111111111111111* +L010920 111111111111101111111111111111111111111111111111101111111111111111* L010986 - 111111111110111111111111111111111111111111110110111111111111111111* -L011052 111101111111111111111111111111111111111111011111111111111111111111* -L011118 101111011111101111111111111111111111111111011111111111111111111111* -L011184 011111101111101111111111111111111111111111011111111111111111111111* -L011250 111111111111101111111111111111111111111110011111111111111111111111* -L011316 111111111011101111111111111111111111111111011111111101111111111111* -L011382 111111110111101111111111111111111111111111011111111110111111111111* -L011448 000000000000000000000000000000000000000000000000000000000000000000* -L011514 000000000000000000000000000000000000000000000000000000000000000000* -L011580 000000000000000000000000000000000000000000000000000000000000000000* -L011646 000000000000000000000000000000000000000000000000000000000000000000* + 101111011110111111111111111111111111111111111111111111111111111111* +L011052 111101111111111111111111111111111111111111111111111111111111111111* +L011118 111111111111101111111101111011110101111101010101111111111111111111* +L011184 111111111111101111111110111011111001111101010101111111111111111111* +L011250 111111111111101111111101111011110101111110011001111111111111111111* +L011316 111111111111101111111110111011111001111110011001111111111111111111* +L011382 111111111111111111111111111111111111111111111111111111111111111111* +L011448 111111111111111111111111111111111111111111111111111111111111111111* +L011514 111111111111111111111111111111111111111111111111111111111111111111* +L011580 111111111111111111111111111111111111111111111111111111111111111111* +L011646 111111111111111111111111111111111111111111111111111111111111111111* L011712 - 111111111110111111111111111111111111111111110110111111111111111111* + 101111011110111111111111111111111111111111111111111111111111111111* L011778 000000000000000000000000000000000000000000000000000000000000000000* -L011844 111111111111111011101111010111111111111111011111111111111111111111* -L011910 111110111111111011111111010111111111111111011111111111111111111111* -L011976 000000000000000000000000000000000000000000000000000000000000000000* -L012042 000000000000000000000000000000000000000000000000000000000000000000* -L012108 111111111111110111111111111011111111111111011111110111111111111111* -L012174 111111111111111111110111111011111111111111011111111111111111111111* -L012240 111111111111110111110111111111111111111111011111111111111111111111* +L011844 111111111111111111111111111111111111111111111111111111111111111111* +L011910 111111111111111111111111111111111111111111111111111111111111111111* +L011976 111111111111111111111111111111111111111111111111111111111111111111* +L012042 111111111111111111111111111111111111111111111111111111111111111111* +L012108 111111111111111111111111111011111111111111111101011111110111111111* +L012174 111111111111111111110111111111111111111011111111011111111111111111* +L012240 111111111111111101111111111011111111111111111101011111111111011111* L012306 000000000000000000000000000000000000000000000000000000000000000000* L012372 000000000000000000000000000000000000000000000000000000000000000000* L012438 - 111111111111111111111111111111111111111111111011111111111111111111* -L012504 111111111111111111111111111111111111111111011111111111111111111011* + 111111101111111111111111111111111111111111111111111111111111111111* +L012504 111111111111111111111111111111111111111111111011011111111111111111* L012570 111111111111111111111111111111111111111111111111111111111111111111* L012636 111111111111111111111111111111111111111111111111111111111111111111* L012702 111111111111111111111111111111111111111111111111111111111111111111* @@ -311,47 +311,47 @@ L013300 00100011111000* L013314 00100110011111* L013328 00010011110101* L013342 11011111111111* -L013356 11100110011000* -L013370 11100110011111* -L013384 10110110011100* +L013356 10100111011000* +L013370 10100111011111* +L013384 01110110011100* L013398 11101011111110* -L013412 00000011110000* -L013426 11100110010011* +L013412 00110011110000* +L013426 10100111010011* L013440 00110110010111* -L013454 11001011110011* -L013468 00001111110000* +L013454 11101011110011* +L013468 00111111110000* L013482 10100110010010* L013496 01010110010011* L013510 11100011111111* NOTE BLOCK 2 * L013524 - 111111111011110111111101111111111111111111111111111111111111111111 - 111111011101111111111111111110111111111111111111111111111111111111 - 111111111111111111011111111111101111111111111110111111111111111111 + 111111011111110111111111111111111111111111111111111111111111011111 + 111101111101111101111111110111111111111111111111111111111111111111 + 111111111111111111111111111111111111011111111111111111111111111111 111111111111111111111111111111111111111111110111111111111111111110 - 111111111111111111111111111111111111111111111111111011111111111111 - 111101111111101111111111111111111111111111111111111111111111111111 - 111111111111111111111111011111111111111111101111011111111111111111 - 111111111111111101111111111011110111111010111111111111111111111111 - 101111111111111111110111111111111111111111111111111110111111111111* + 111111111111111111111010111111111111111111111111111011111111111111 + 111111111111111111111111111111111111111001111111111111111111111111 + 111111111111111111111111111111111011111111111111111111111111111111 + 111111111011111111101111111111111111111111111110111111111111111111 + 101111111111111111111111111111111111111111111111111111111111111111* L014118 - 111111111110111111111111111111111111111110111111111111111111111101* + 111111111110111111111111111111111111111111111110111111111111111101* L014184 000000000000000000000000000000000000000000000000000000000000000000* L014250 000000000000000000000000000000000000000000000000000000000000000000* L014316 000000000000000000000000000000000000000000000000000000000000000000* L014382 000000000000000000000000000000000000000000000000000000000000000000* L014448 000000000000000000000000000000000000000000000000000000000000000000* -L014514 111111111111111111111111111111111111111110111110111111111111111111* +L014514 111111111111111111111011111111111111111111111110111111111111111111* L014580 000000000000000000000000000000000000000000000000000000000000000000* L014646 000000000000000000000000000000000000000000000000000000000000000000* L014712 000000000000000000000000000000000000000000000000000000000000000000* L014778 000000000000000000000000000000000000000000000000000000000000000000* L014844 - 111111111110111111111111111111111111111110111111111111111111111101* -L014910 101111111111111111111111111111111111111111111111111111111111111111* -L014976 111111111111111111111111111111111111111111110111111011111111111111* -L015042 111111111111101111111111111101101111111111111111110111111111111111* -L015108 000000000000000000000000000000000000000000000000000000000000000000* + 111111111110111111111111111111111111111111111110111111111111111101* +L014910 011101111001111111111111110111111111110110111011111011111111111111* +L014976 101111111111111111111111111111111111111111110111111111111111111111* +L015042 011111111011111111111111110111111111110111110111111111111111111111* +L015108 011101111101111111111111111111111111111110111011111011111111111111* L015174 000000000000000000000000000000000000000000000000000000000000000000* L015240 111111111111111111111111111111111111111111111111111111111111111111* L015306 111111111111111111111111111111111111111111111111111111111111111111* @@ -359,7 +359,7 @@ L015372 111111111111111111111111111111111111111111111111111111111111111111* L015438 111111111111111111111111111111111111111111111111111111111111111111* L015504 111111111111111111111111111111111111111111111111111111111111111111* L015570 - 111111111110111111111111111111111111111110111111111111111111111101* + 111111111110111111111111111111111111111111111110111111111111111101* L015636 000000000000000000000000000000000000000000000000000000000000000000* L015702 111111111111111111111111111111111111111111111111111111111111111111* L015768 111111111111111111111111111111111111111111111111111111111111111111* @@ -371,10 +371,10 @@ L016098 111111111111111111111111111111111111111111111111111111111111111111* L016164 111111111111111111111111111111111111111111111111111111111111111111* L016230 111111111111111111111111111111111111111111111111111111111111111111* L016296 - 111111111110111111111111111111111111111110111111111111111111111101* -L016362 011111111111111111111111011011111111111111111111110111111111111111* -L016428 011111111111111111101111111111111111111011111111111111111111111111* -L016494 000000000000000000000000000000000000000000000000000000000000000000* + 111111111110111111111111111111111111111111111110111111111111111101* +L016362 011111111011111111111111110111111111111111111111111111111111011111* +L016428 011111111011111111111111111111111111011111111111111111111111111111* +L016494 011111111111111111111111110111111111011111111111111111111111111111* L016560 000000000000000000000000000000000000000000000000000000000000000000* L016626 000000000000000000000000000000000000000000000000000000000000000000* L016692 111111111111111111111111111111111111111111111111111111111111111111* @@ -383,24 +383,24 @@ L016824 111111111111111111111111111111111111111111111111111111111111111111* L016890 111111111111111111111111111111111111111111111111111111111111111111* L016956 111111111111111111111111111111111111111111111111111111111111111111* L017022 - 111111111110111111111111111111111111111110111111111111111111111101* + 111111111110111111111111111111111111111111111110111111111111111101* L017088 000000000000000000000000000000000000000000000000000000000000000000* L017154 111111111111111111111111111111111111111111111111111111111111111111* L017220 111111111111111111111111111111111111111111111111111111111111111111* L017286 111111111111111111111111111111111111111111111111111111111111111111* L017352 111111111111111111111111111111111111111111111111111111111111111111* -L017418 101111111111111111111111111111111111111111111111111111111111111111* -L017484 111111111111111111111111111111111111111101111111111111111111111111* -L017550 111101111111111111111111111111110111111111111111111111111111111111* -L017616 111110111111111111111111111111111011111111111111111111111111111111* -L017682 111111111111111111111111111111111111111111111111111101111111111111* +L017418 111111011111111111111111111111111111111111111111111111111111111111* +L017484 111111111111111111111111111111111111111111111111111111111111111111* +L017550 111111111111111111111111111111111111111111111111111111111111111111* +L017616 111111111111111111111111111111111111111111111111111111111111111111* +L017682 111111111111111111111111111111111111111111111111111111111111111111* L017748 111111111111111111111111111111111111111111111111111111111111111111* -L017814 011111111111111111111011111111111111111111111111111111111111111111* -L017880 111111111111111101111111111111111111111111111111011111111111111111* -L017946 111111011011111111111111111111111111111111101111111111111111111111* -L018012 111111110111110111111101111111111111111111101111111111111111111111* -L018078 111111011111111011111111111111111111111111101111111111111111111111* +L017814 011111111011111111111111110111111111111111111111111111111111011111* +L017880 011111111111111110101111111111111111111111111111111111111111111111* +L017946 000000000000000000000000000000000000000000000000000000000000000000* +L018012 000000000000000000000000000000000000000000000000000000000000000000* +L018078 000000000000000000000000000000000000000000000000000000000000000000* L018144 111111111111111111111111111111111111111111111111111111111111111111* L018210 111111111111111111111111111111111111111111111111111111111111111111* L018276 111111111111111111111111111111111111111111111111111111111111111111* @@ -409,75 +409,75 @@ L018408 111111111111111111111111111111111111111111111111111111111111111111* L018474 000000000000000000000000000000000000000000000000000000000000000000* L018540 000000000000000000000000000000000000000000000000000000000000000000* -L018606 101111111111111111111111111111111111111111111111111111111111111111* -L018672 111111111111111111111111111111111111111101111111111111111111111111* -L018738 111111111011111111111101111111111111111111111111111111111111111111* -L018804 111101111111111111111111111111110111111111111111111111111111111111* -L018870 111110111111111111111111111111111011111111111111111111111111111111* -L018936 111111111111111111111111111111111111111111111111111101111111111111* -L019002 111111111111111101111111111111111111111111111111011111111111111111* +L018606 111111111111111111111111111111111111111111111111111111111111111111* +L018672 111111111111111111111111111111111111111111111111111111111111111111* +L018738 111111111111111111111111111111111111111111111111111111111111111111* +L018804 111111111111111111111111111111111111111111111111111111111111111111* +L018870 011111110111111111111111111111111111111111111111111111111111011111* +L018936 011111111111111111111111111011111111111111111111111111111111011111* +L019002 011101111101111111111111111111111111111110111011111011111111101111* L019068 000000000000000000000000000000000000000000000000000000000000000000* L019134 000000000000000000000000000000000000000000000000000000000000000000* L019200 000000000000000000000000000000000000000000000000000000000000000000* -L019266 011110111011111110111110111111110111111110111111111110111111111111* -L019332 011101111011111110111110111111111011111110111111111110111111111111* -L019398 011110111111110110111111111111110111111110111111111110111111111111* -L019464 011101111111110110111111111111111011111110111111111110111111111111* -L019530 011110111011111111111110111111110111111110111111101110111111111111* -L019596 011101111011111111111110111111111011111110111111101110111111111111* -L019662 011110111111110111111111111111110111111110111111101110111111111111* -L019728 011101111111110111111111111111111011111110111111101110111111111111* -L019794 000000000000000000000000000000000000000000000000000000000000000000* -L019860 000000000000000000000000000000000000000000000000000000000000000000* +L019266 011111111111111111111110111111111111111111111110111111111111111111* +L019332 011111111111111011111111111111110111111111111101111111111111111111* +L019398 000000000000000000000000000000000000000000000000000000000000000000* +L019464 000000000000000000000000000000000000000000000000000000000000000000* +L019530 000000000000000000000000000000000000000000000000000000000000000000* +L019596 111111111111111111111111111111111111111111111111111111111111111111* +L019662 111111111111111111111111111111111111111111111111111111111111111111* +L019728 111111111111111111111111111111111111111111111111111111111111111111* +L019794 111111111111111111111111111111111111111111111111111111111111111111* +L019860 111111111111111111111111111111111111111111111111111111111111111111* L019926 000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000* L020058 0010* L020062 00100011110000* L020076 01101111110011* -L020090 10100110011100* +L020090 00100111011100* L020104 11101111110010* L020118 00111011110000* L020132 00000011110011* -L020146 11100110010110* +L020146 10100110010110* L020160 11100011110010* L020174 00111111110001* -L020188 10100110010011* -L020202 01110110011110* +L020188 00000110010011* +L020202 11100110011110* L020216 11100011111111* -L020230 00011011111001* +L020230 00111011111001* L020244 10100110010011* -L020258 10100110010000* -L020272 11111111111111* +L020258 11100110010000* +L020272 11101111111111* NOTE BLOCK 3 * L020286 - 111111011111111111111111111111111111111111111111111111111111111111 - 111111110101111101111111111111111111111111111111111111111111111111 - 111111111111111111111101111111111111111111111111111111111111111111 - 111111111111111111111111111110111111111111110110111111111111111110 - 111111111111111111111011111111111101111111111111111111111111111111 - 110111111111111011011111111111111111111101111111111111111111111111 - 111111111111111111111111011111111111111111111111111111111111111111 - 101111111111111111111111111011110111111111111111111111111111111111 - 111101111111111111111111111111111111011111101111111110110111111111* + 111111111111111111111111101111111110011111111111111111110111111111 + 111111110111111111111011111111011111111111111101111111111111111111 + 111111111111111111111101111111111111111110111111111111011111111011 + 111111111111111111111111111111111111111111111011111111111111111111 + 111111111110111111111111111111111111111111111111111111111111111111 + 110111111111111111011111111111111111111111111111111111111111111111 + 111111011111110111111111111111111111110111111111111111111111111111 + 101111111111111111111111111010111111111111111111111111111111101110 + 111101111111111111111111111111110111111111101111111001111111111111* L020880 111111111111111111111111111111111111111111111111111111111111111111* -L020946 111111111111111111111111111111111111101111101111111111111111111111* -L021012 111011111111111111101111011011111110101111111111111111111011111111* -L021078 110111111111111110101111100111111101011111011111111111111011111111* +L020946 111111111111111111111111111111111111111111101111111110111111111111* +L021012 111111101111111011101011111011111111111111111101111110111111111111* +L021078 111111011111111011100111110111111111111011011110111101111111111111* L021144 000000000000000000000000000000000000000000000000000000000000000000* L021210 000000000000000000000000000000000000000000000000000000000000000000* -L021276 111111111001110111111111011111111111111111011111111111111111111111* +L021276 111111111011111111111111111101011111111111011101111111111111111111* L021342 111110111011111111111111111111111111111111011111111111111111111111* L021408 000000000000000000000000000000000000000000000000000000000000000000* L021474 000000000000000000000000000000000000000000000000000000000000000000* L021540 000000000000000000000000000000000000000000000000000000000000000000* L021606 111111111111111111111111111111111111111111111111111111111111111111* -L021672 110111111111111111111111100111111101111111111111111111111111111111* -L021738 111111111111111111111111111111111111111111111111111111110111111111* -L021804 000000000000000000000000000000000000000000000000000000000000000000* +L021672 111111111111111111111111110111110111111111011111111111111111111111* +L021738 111111111111111111111111111111110111111111011110111111111111111111* +L021804 111111111111111111111111110111111111111111011110111111011111111111* L021870 000000000000000000000000000000000000000000000000000000000000000000* L021936 000000000000000000000000000000000000000000000000000000000000000000* L022002 111111111111111111111111111111111111111111111111111111111111111111* @@ -487,8 +487,8 @@ L022200 111111111111111111111111111111111111111111111111111111111111111111* L022266 111111111111111111111111111111111111111111111111111111111111111111* L022332 111111111111111111111111111111111111111111111111111111111111111111* -L022398 011111111111111111111111111101111111111111111111111111111111111111* -L022464 101111111111111111111111111111111111111111111101111111111111111111* +L022398 101111111111111111111111111111111111101111111111111111111111111111* +L022464 011111111110111111111111111111111111111111111111111111111111111110* L022530 000000000000000000000000000000000000000000000000000000000000000000* L022596 000000000000000000000000000000000000000000000000000000000000000000* L022662 000000000000000000000000000000000000000000000000000000000000000000* @@ -498,36 +498,36 @@ L022860 111111111111111111111111111111111111111111111111111111111111111111* L022926 111111111111111111111111111111111111111111111111111111111111111111* L022992 111111111111111111111111111111111111111111111111111111111111111111* L023058 - 011111111111111111111111111111111111111111111111111111111111111101* -L023124 101111111111111111111111111111110111111110011111111110111111111111* -L023190 101111111111111111111111110111110111111111011111111110111111111111* -L023256 101111111111111111111111011011111011111101011111111110111111111111* -L023322 101111111111111111111111101111110111111111011111111110111111111111* -L023388 000000000000000000000000000000000000000000000000000000000000000000* + 011111111111111111111111111111111111111111110111111111111111111111* +L023124 111111111111111111111111011111111111111111111111111111111111111111* +L023190 111111111111111111111111111111111111111111111111111111111111111111* +L023256 111111111111111111111111111111111111111111111111111111111111111111* +L023322 111111111111111111111111111111111111111111111111111111111111111111* +L023388 111111111111111111111111111111111111111111111111111111111111111111* L023454 111111111111111111111111111111111111111111111111111111111111111111* L023520 111111111111111111111111111111111111111111111111111111111111111111* L023586 111111111111111111111111111111111111111111111111111111111111111111* L023652 111111111111111111111111111111111111111111111111111111111111111111* L023718 111111111111111111111111111111111111111111111111111111111111111111* L023784 - 011111111111111111111111111111111111111111111111111111111111111101* -L023850 111111111111111111111001111111111111111111111111111111111111111111* + 011111111111111111111111111111111111111111110111111111111111111111* +L023850 111111111111111111111111111111111110111111111111111111110111111111* L023916 111111111111111111111111111111111111111111111111111111111111111111* L023982 111111111111111111111111111111111111111111111111111111111111111111* L024048 111111111111111111111111111111111111111111111111111111111111111111* L024114 111111111111111111111111111111111111111111111111111111111111111111* -L024180 111111011111111111111111111111111111111111111111111111111111111111* -L024246 111111111111111111111111111111111111111111111111111111111111111111* -L024312 111111111111111111111111111111111111111111111111111111111111111111* -L024378 111111111111111111111111111111111111111111111111111111111111111111* -L024444 111111111111111111111111111111111111111111111111111111111111111111* +L024180 111111111111110111101011111111111111111111111111111111111111111111* +L024246 111111111111110111111111111011111111111111111111111111111111111111* +L024312 111111111111110111111111111111111111111111111101111111111111111111* +L024378 111111011111111111010111110111111111111111111110111111111111111111* +L024444 000000000000000000000000000000000000000000000000000000000000000000* L024510 000000000000000000000000000000000000000000000000000000000000000000* -L024576 101111111111111111111111110111111111111101011111111110111111111111* -L024642 101111111111111111111111011011111111111110011111111110111111111111* -L024708 101111111111111111111111101111111111111101011111111110111111111111* -L024774 000000000000000000000000000000000000000000000000000000000000000000* -L024840 000000000000000000000000000000000000000000000000000000000000000000* +L024576 111111111111111111111111111111111111111111111111111111111111011111* +L024642 111111111111111111111111111111111111111111111111111111111111111111* +L024708 111111111111111111111111111111111111111111111111111111111111111111* +L024774 111111111111111111111111111111111111111111111111111111111111111111* +L024840 111111111111111111111111111111111111111111111111111111111111111111* L024906 111111111111111111111111111111111111111111111111111111111111111111* L024972 111111111111111111111111111111111111111111111111111111111111111111* L025038 111111111111111111111111111111111111111111111111111111111111111111* @@ -535,23 +535,23 @@ L025104 111111111111111111111111111111111111111111111111111111111111111111* L025170 111111111111111111111111111111111111111111111111111111111111111111* L025236 111111111111111111111111111111111111111111111111111111111111111111* -L025302 111111111111111111111101111111111111111111111011111111111111111111* +L025302 111111111111111111111111111111111111111110111111111111110111111111* L025368 111111111111111111111111111111111111111111111111111111111111111111* L025434 111111111111111111111111111111111111111111111111111111111111111111* L025500 111111111111111111111111111111111111111111111111111111111111111111* L025566 111111111111111111111111111111111111111111111111111111111111111111* -L025632 110111111111111111111111111111111110111111111111111111111111111111* -L025698 110111111111111111111111111011111111111111111111111111111111111111* -L025764 110111111111111111111111011111111111111111111111111111111111111111* -L025830 111011111111111111101111100111111101111111111111111111111111111111* -L025896 000000000000000000000000000000000000000000000000000000000000000000* +L025632 110111111111111111111111111111111111111111101111111111111111111111* +L025698 110111101111110111101011110111111111111011111110111110111111111111* +L025764 110111111111111111111110110111111111110111111110111111111111111111* +L025830 111011111111111111111111111011110111111111011101111111111111111111* +L025896 110111111111111111111111110111111111111111111110111011111111111111* L025962 000000000000000000000000000000000000000000000000000000000000000000* -L026028 111111111111111111111111111011111101111111111111111111111111111111* -L026094 111111111111111111111111011111111101111111111111111111111111111111* -L026160 111111111111111111111111100111111110111111111111111111111111111111* -L026226 000000000000000000000000000000000000000000000000000000000000000000* -L026292 000000000000000000000000000000000000000000000000000000000000000000* +L026028 111111111111111111111111111111111111111111011111111111111111111011* +L026094 111111111111111111111111111111111111111111111111111111111111111111* +L026160 111111111111111111111111111111111111111111111111111111111111111111* +L026226 111111111111111111111111111111111111111111111111111111111111111111* +L026292 111111111111111111111111111111111111111111111111111111111111111111* L026358 111111111111111111111111111111111111111111111111111111111111111111* L026424 111111111111111111111111111111111111111111111111111111111111111111* L026490 111111111111111111111111111111111111111111111111111111111111111111* @@ -563,45 +563,45 @@ L026688 L026820 0010* L026824 10100111010000* L026838 11100110011110* -L026852 00100110010100* +L026852 10100110010100* L026866 11100011111111* -L026880 10101111111001* +L026880 11101111111001* L026894 00001011111111* -L026908 10100110010100* +L026908 00010110010100* L026922 11101011110011* L026936 01110011110010* -L026950 00000110010010* -L026964 10100110010001* +L026950 10100110010010* +L026964 00010110010001* L026978 11101011110011* L026992 01111111111010* -L027006 10100110011110* -L027020 10100110010001* +L027006 10100111011110* +L027020 01010110010001* L027034 11100011110011* NOTE BLOCK 4 * L027048 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111011111111111111111110111110111111111 - 111111011101111111111111111111111111011111011111101111111111111111 - 111011111111111111011101111011111111111111111011111111111111111111 - 111111111111111111111111111111111111111111111111111111011111111111 - 111111110111111011111111011111111111111111111111111111111111111111 - 111110111111101111111111111111111101111111111111111101111111111111 - 101111111111111111111111111110111111111011111111111111111101110111 - 111111111111111101111111111111111011111110111111111111111111111110* + 111111111111111101011111111111111111111111011111110111111111111111 + 111111111101111111111111010111111111111111111111101111111111111111 + 111011011111111111111111111111111101111111111011111111101111111111 + 111111111111110111111111111111111111111111111111111111111111111111 + 111111111111011111111111111111111111011111111111111111111111111111 + 111110110111111111111111111111111111111111111111111101111011111111 + 111111111111111111111111111110011111111011111110111111111101111111 + 101111111111111111111101111111111011111110111111111111111111111110* L027642 - 110111110111111101111111100111111110111011111111011110111111111111* + 110111111011101111111101111111111111011011111111011110011111111111* L027708 000000000000000000000000000000000000000000000000000000000000000000* L027774 000000000000000000000000000000000000000000000000000000000000000000* L027840 000000000000000000000000000000000000000000000000000000000000000000* L027906 000000000000000000000000000000000000000000000000000000000000000000* L027972 000000000000000000000000000000000000000000000000000000000000000000* -L028038 101111111111011111111111111111101011111111111111111111111111111111* -L028104 011111111111101111111111111111111111111111111111111111111111111111* +L028038 111111111111111111111111111111111011111111101110111111110111111111* +L028104 111111111111111111111111111111111111111111111101111111111011111111* L028170 000000000000000000000000000000000000000000000000000000000000000000* L028236 000000000000000000000000000000000000000000000000000000000000000000* L028302 000000000000000000000000000000000000000000000000000000000000000000* L028368 - 011111111111111111111111111111111111111111110111111111111111111111* + 111111111111111111111111111111111111111111110101111111111111111111* L028434 111111111111111111111111111111111111111111111111111111111111111111* L028500 111111111111111111111111111111111111111111111111111111111111111111* L028566 111111111111111111111111111111111111111111111111111111111111111111* @@ -614,16 +614,16 @@ L028962 111111111111111111111111111111111111111111111111111111111111111111* L029028 111111111111111111111111111111111111111111111111111111111111111111* L029094 000000000000000000000000000000000000000000000000000000000000000000* -L029160 111111111111111111111111111111111111101011111111111111111111111111* +L029160 111111111111111110111111111111111111111011111111111111111111111111* L029226 111111111111111111111111111111111111111111111111111111111111111111* L029292 111111111111111111111111111111111111111111111111111111111111111111* L029358 111111111111111111111111111111111111111111111111111111111111111111* L029424 111111111111111111111111111111111111111111111111111111111111111111* -L029490 111111111111111111111111111111011111111111111111111111111111111111* -L029556 111111101110111011101110111111111111111101101111111011101001110101* -L029622 000000000000000000000000000000000000000000000000000000000000000000* -L029688 000000000000000000000000000000000000000000000000000000000000000000* -L029754 000000000000000000000000000000000000000000000000000000000000000000* +L029490 011111111111111111111111111111111111111011111111111111111111111111* +L029556 111111111111111111111111111111111111111111111111111111111111111111* +L029622 111111111111111111111111111111111111111111111111111111111111111111* +L029688 111111111111111111111111111111111111111111111111111111111111111111* +L029754 111111111111111111111111111111111111111111111111111111111111111111* L029820 000000000000000000000000000000000000000000000000000000000000000000* L029886 111111111111111111111111111111111111111111111111111111111111111111* @@ -638,16 +638,16 @@ L030414 111111111111111111111111111111111111111111111111111111111111111111* L030480 111111111111111111111111111111111111111111111111111111111111111111* L030546 000000000000000000000000000000000000000000000000000000000000000000* -L030612 111101111111111111111111111111111111111111111111111111111111111111* +L030612 011111111111111111111111111111111111111111111110111111111111111111* L030678 111111111111111111111111111111111111111111111111111111111111111111* L030744 111111111111111111111111111111111111111111111111111111111111111111* L030810 111111111111111111111111111111111111111111111111111111111111111111* L030876 111111111111111111111111111111111111111111111111111111111111111111* -L030942 111110111111111111111111111111111111111111111111111111111111111111* -L031008 111111111111111111111111111111111111111111111111111111111111111111* -L031074 111111111111111111111111111111111111111111111111111111111111111111* -L031140 111111111111111111111111111111111111111111111111111111111111111111* -L031206 111111111111111111111111111111111111111111111111111111111111111111* +L030942 111111111111111111111111111111111111111111011111111111111111111111* +L031008 111111101110111011101111101010011110111101111111111011111101111101* +L031074 000000000000000000000000000000000000000000000000000000000000000000* +L031140 000000000000000000000000000000000000000000000000000000000000000000* +L031206 000000000000000000000000000000000000000000000000000000000000000000* L031272 000000000000000000000000000000000000000000000000000000000000000000* L031338 111111111111111111111111111111111111111111111111111111111111111111* @@ -661,8 +661,8 @@ L031800 111111111111111111111111111111111111111111111111111111111111111111* L031866 111111111111111111111111111111111111111111111111111111111111111111* L031932 111111111111111111111111111111111111111111111111111111111111111111* L031998 - 111111111111111111111111111101111111111111111111111111111111111111* -L032064 111111101110111011101110111111111111111101101111111011101001110101* + 111101111111111111111111111111111111111111111111111111111111111111* +L032064 111111101110111011101111101010011110111101111111111011111101111101* L032130 111111111111111111111111111111111111111111111111111111111111111111* L032196 111111111111111111111111111111111111111111111111111111111111111111* L032262 111111111111111111111111111111111111111111111111111111111111111111* @@ -693,47 +693,47 @@ L033600 10101111110011* L033614 11011011110100* L033628 11110011110010* L033642 01110111111001* -L033656 10100011111111* -L033670 11010111110000* -L033684 11110011111111* -L033698 00110110010001* -L033712 00000110011111* +L033656 01000110011111* +L033670 11011011110000* +L033684 11111111111111* +L033698 01110110010001* +L033712 10101011111111* L033726 11010111110000* -L033740 11111111111111* +L033740 11111111111110* L033754 00110011110001* -L033768 11001011111111* +L033768 11001011111110* L033782 11110111111100* -L033796 11111111111111* +L033796 11111111111110* NOTE BLOCK 5 * L033810 - 111011111111111111111111111111111111111111111111111111111111111111 - 111111111101111111111111111111111111111111111011111111111111111111 - 111110111111111111111111111111101110111111111111111111111111111111 - 111111111111111110111111111111111111111110111111111111111110111111 - 111111111111111111111011111111111111111111111111111111111111111011 - 111111111111011111111111111111111111111011111111111111110111111111 - 111111010111110111111101111111111111111111111111111111111111111111 - 101111111111111111101111111011111111011111111111111111111111111111 - 111111111111111111111111011110111111111111101111110111111111111111* + 111111111111111111111111111111111110111111111111111111111111011111 + 101111111101111111111111111111111111111111111101111111111111111111 + 111110111111101111111111111111101111111111111111111111111111111111 + 111011111111111110111111111110111111111111110111111111111111111111 + 111111101111111111111011111111111111111111111111111011111111111111 + 111111111111111111111111011111111111111111111111111111101111111111 + 111111110111111111111101111111111011111111111111111111111111111111 + 111111111111111111101111111011111111011110111111111110111111111111 + 111111111111111111111111111111111111111111101111111111111111111111* L034404 000000000000000000000000000000000000000000000000000000000000000000* -L034470 111111111111111111111111110111111111111111011111111111111111110111* -L034536 111111111111111011111111111111111111111111011111111111111111110111* -L034602 111110111101111111111111111111111111111111010111111011111110111011* -L034668 000000000000000000000000000000000000000000000000000000000000000000* -L034734 000000000000000000000000000000000000000000000000000000000000000000* -L034800 111111111111111111111011111111111111111111011111111111111111111011* -L034866 111111111111111111111111111111101111111111011111111111111111110111* +L034470 111111111111111111101111111111111111111111011111111011111111111111* +L034536 111011111101111111101111111111110111111101011011111110111111111111* +L034602 111111111101111111101111011111110111111101011011111110111111111111* +L034668 111111110101111111101111111111110111111101011011111110111111111111* +L034734 111111111101111110101111111111110111111101011011111110111111111111* +L034800 111111011111111111111111111111111111111110011111111111111111111111* +L034866 111111111111111111111011111111110111111101011111111111111111111111* L034932 000000000000000000000000000000000000000000000000000000000000000000* L034998 000000000000000000000000000000000000000000000000000000000000000000* L035064 000000000000000000000000000000000000000000000000000000000000000000* L035130 000000000000000000000000000000000000000000000000000000000000000000* -L035196 111111111111111111111111111111111111111111111111111111111111111111* -L035262 111111111111111111111111111111111111111111111111111111111111111111* -L035328 111111111111111111111111111111111111111111111111111111111111111111* -L035394 111111111111111111111111111111111111111111111111111111111111111111* -L035460 111111111111111111111111111111111111111111111111111111111111111111* +L035196 111111111101111111101101111111110111111101011011111110111111111111* +L035262 111111111101101111101111111111110111111101011011111110111111111111* +L035328 000000000000000000000000000000000000000000000000000000000000000000* +L035394 000000000000000000000000000000000000000000000000000000000000000000* +L035460 000000000000000000000000000000000000000000000000000000000000000000* L035526 111111111111111111111111111111111111111111111111111111111111111111* L035592 111111111111111111111111111111111111111111111111111111111111111111* L035658 111111111111111111111111111111111111111111111111111111111111111111* @@ -741,16 +741,16 @@ L035724 111111111111111111111111111111111111111111111111111111111111111111* L035790 111111111111111111111111111111111111111111111111111111111111111111* L035856 000000000000000000000000000000000000000000000000000000000000000000* -L035922 111111111111111111101111111111111111111111011111111111111110111111* -L035988 011110111101111111101111011111111111111010011111111111111111111111* -L036054 011110111101011111101111011111111111111011011111111111111111111111* -L036120 011110110101111111101111011111111111111011011111111111111111111111* -L036186 011110111101111110101111011111111111111011011111111111111111111111* -L036252 011110111101111111101101011111111111111011011111111111111111111111* -L036318 011110111101111111101111011111111110111011011111111111111111111111* -L036384 000000000000000000000000000000000000000000000000000000000000000000* -L036450 000000000000000000000000000000000000000000000000000000000000000000* -L036516 000000000000000000000000000000000000000000000000000000000000000000* +L035922 111111111111111111111111111011111111011111011101111111111111111111* +L035988 111111111111111111111111111001111111101111011111111111111111111111* +L036054 111111111111111111111111111101111111101111011101111111111111111111* +L036120 000000000000000000000000000000000000000000000000000000000000000000* +L036186 000000000000000000000000000000000000000000000000000000000000000000* +L036252 111111111111111111111111111111111111111111111111111111111111111111* +L036318 111111111111111111111111111111111111111111111111111111111111111111* +L036384 111111111111111111111111111111111111111111111111111111111111111111* +L036450 111111111111111111111111111111111111111111111111111111111111111111* +L036516 111111111111111111111111111111111111111111111111111111111111111111* L036582 000000000000000000000000000000000000000000000000000000000000000000* L036648 111111111111111111111111111111111111111111111111111111111111111111* @@ -765,10 +765,10 @@ L037176 111111111111111111111111111111111111111111111111111111111111111111* L037242 111111111111111111111111111111111111111111111111111111111111111111* L037308 000000000000000000000000000000000000000000000000000000000000000000* -L037374 111110011101110111111111111011111111111111010111111011111110111111* -L037440 111101111111111111111111111111111111111111101111111111111111111111* -L037506 111101011111110111111111111011111111111111011111111111111111111111* -L037572 111110111101111111111111111111111111111111010111111011111110111111* +L037374 111111111111111111111111111111111111111111101111111111111111111111* +L037440 111101111111111111111111111111111111111111111111111111111111101111* +L037506 011111111111111111111111111111101111111111111111111111101111011111* +L037572 000000000000000000000000000000000000000000000000000000000000000000* L037638 000000000000000000000000000000000000000000000000000000000000000000* L037704 111111111111111111111111111111111111111111111111111111111111111111* L037770 111111111111111111111111111111111111111111111111111111111111111111* @@ -789,8 +789,8 @@ L038628 111111111111111111111111111111111111111111111111111111111111111111* L038694 111111111111111111111111111111111111111111111111111111111111111111* L038760 000000000000000000000000000000000000000000000000000000000000000000* -L038826 111111111111111111111111111110111111011111011111111111110111111111* -L038892 111011111111111111101111111111111111111111011111111111111111111111* +L038826 111111111111111111111111111111111110111111011111111111111111101111* +L038892 111111111111111111111111111111101111111111011111111111111111011111* L038958 000000000000000000000000000000000000000000000000000000000000000000* L039024 000000000000000000000000000000000000000000000000000000000000000000* L039090 000000000000000000000000000000000000000000000000000000000000000000* @@ -815,15 +815,15 @@ L040212 000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000* L040344 0010* -L040348 10100110011110* +L040348 11100110011110* L040362 11100110010010* -L040376 11011111111110* +L040376 11001111111110* L040390 11111011110011* -L040404 11100110011110* -L040418 11111011110010* +L040404 10100110011110* +L040418 11001011110010* L040432 11110011111111* L040446 11111111110011* -L040460 00100111011110* +L040460 10100110011110* L040474 11001011110010* L040488 11111111111111* L040502 11110011111111* @@ -833,33 +833,33 @@ L040544 11110111111110* L040558 11111111111110* NOTE BLOCK 6 * L040572 - 111111111111111011101111111111111111111111111111111111111111111111 - 111101111101111111111111101111111111111111111111111111111111111111 - 111111111011111111111011111111111111111111111110111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111010 - 111111111111111111111110111111111110111111111111111111111111111111 - 110111111111111111111111111111011111111111111111111111111111111111 - 111111111111101111111111111111111011111111111111010111111111111111 - 111111111111111101111111111011111111111110111111111111111111111111 - 101111011111111111111111111111111111111111010111111111111111111111* + 111111111111111011111111101111111111111111111111111111111111111111 + 111111011111111111111011111111011111111111111011111111111111111111 + 111111111110111111111111111011111111111111111111111111111111111111 + 101111111111111111111111111111111111111111111110111111111111111110 + 111111111111111111111111111111111110111111111111111111111111111111 + 111111111111111111011111111111111111111111111111111111111111111111 + 111111111111101111111111111111111011011111111111010111111111111111 + 111111110111111101111111111111111111111110111111111111101111111111 + 111111111111111111111111111111111111111111101111111111111111111111* L041166 111111111111111111111111111111111111111111111111111111111111111111* -L041232 011111111111111111111111111111111110111101011111111111111111111111* -L041298 011111111111101111111111111111111111111110111111111111111111111111* +L041232 111111111111111111111111111111110110111101011111111111111111111111* +L041298 111111111111101111111111111111111111111110011111111111111111111111* L041364 000000000000000000000000000000000000000000000000000000000000000000* L041430 000000000000000000000000000000000000000000000000000000000000000000* L041496 000000000000000000000000000000000000000000000000000000000000000000* -L041562 111111111111111111111111111111110111111111111111111111111111111111* +L041562 111111110111111111111111111111111111111111111111111111111111111111* L041628 000000000000000000000000000000000000000000000000000000000000000000* L041694 000000000000000000000000000000000000000000000000000000000000000000* L041760 000000000000000000000000000000000000000000000000000000000000000000* L041826 000000000000000000000000000000000000000000000000000000000000000000* L041892 111111111111111111111111111111111111111111111111111111111111111111* -L041958 011111111111111111111110111111111111111110111111111111111111111111* -L042024 011111111111111111111111111111111111111101011111111111111111111011* -L042090 000000000000000000000000000000000000000000000000000000000000000000* -L042156 000000000000000000000000000000000000000000000000000000000000000000* +L041958 111111111111111111111111111111111111111111011101111111101111111111* +L042024 111111011111111111111111111111111111111111011101111111111111111111* +L042090 111111101111111111111111111111111111111111011110111111011111111111* +L042156 111111111101111111111111111111111111111111010101111111111111111111* L042222 000000000000000000000000000000000000000000000000000000000000000000* L042288 111111111111111111111111111111111111111111111111111111111111111111* L042354 111111111111111111111111111111111111111111111111111111111111111111* @@ -868,20 +868,20 @@ L042486 111111111111111111111111111111111111111111111111111111111111111111* L042552 111111111111111111111111111111111111111111111111111111111111111111* L042618 000000000000000000000000000000000000000000000000000000000000000000* -L042684 110111011111111111111111111111101111111111111111111111111111111111* -L042750 111011101111111111111111111111011111111111111111111111111111111111* +L042684 111111111111111111011111111111111111011111111111111011111111111111* +L042750 111111111111111111101111111111111111101111111111110111111111111111* L042816 000000000000000000000000000000000000000000000000000000000000000000* L042882 000000000000000000000000000000000000000000000000000000000000000000* L042948 000000000000000000000000000000000000000000000000000000000000000000* -L043014 011111111111111111111111111111111111111111111111111111111111111101* -L043080 011101111111111111011111010111111111111111111111111011111111111111* +L043014 111111111111111111111111111111111111111111011111111111111111111101* +L043080 111111101101111111111111111111111111111111010101111111011111111111* L043146 000000000000000000000000000000000000000000000000000000000000000000* L043212 000000000000000000000000000000000000000000000000000000000000000000* L043278 000000000000000000000000000000000000000000000000000000000000000000* L043344 000000000000000000000000000000000000000000000000000000000000000000* -L043410 011111111111111111111101111111111111111110111111111111111111111111* -L043476 011111111111111111111111111111111111111101011110111111111111111111* +L043410 111111101111111111111111111111111111111111010101111111011111111111* +L043476 111111111101111111111111111111111111111111011111111111111111111111* L043542 000000000000000000000000000000000000000000000000000000000000000000* L043608 000000000000000000000000000000000000000000000000000000000000000000* L043674 000000000000000000000000000000000000000000000000000000000000000000* @@ -891,24 +891,24 @@ L043872 111111111111111111111111111111111111111111111111111111111111111111* L043938 111111111111111111111111111111111111111111111111111111111111111111* L044004 111111111111111111111111111111111111111111111111111111111111111111* L044070 - 111111111110111111111111111111111111111110111111111111111111111101* -L044136 101111111111111111111111111111111111111111111111111111111111111111* -L044202 111111111111111111110111111111111111111101011111111111111111111111* + 111111111111111111111111111111101111111110111111111111111111111101* +L044136 111111111111111111111111111111111111111111101111111111111111111111* +L044202 111111111111111111111111110111110111111101111111111111111111111111* L044268 111111111111111101111111111111111111111110111111111111111111111111* L044334 000000000000000000000000000000000000000000000000000000000000000000* L044400 000000000000000000000000000000000000000000000000000000000000000000* -L044466 011111111111111111111111011011111111111111111111111111111111111111* -L044532 011111111111111111111111011111111111111111111111110111111111111111* -L044598 011111111111111111111111100111111111111111111111111011111111111111* -L044664 011101111111111111011111011111111111111111111111111111111111111111* +L044466 111111111111111111110111111111111111111111111111111111101111111111* +L044532 111111011111111111110111111111111111111111111111111111111111111111* +L044598 111111101111111111111011111111111111111111111111111111011111111111* +L044664 000000000000000000000000000000000000000000000000000000000000000000* L044730 000000000000000000000000000000000000000000000000000000000000000000* L044796 - 111111111110111111111111111111111111111110111111111111111111111111* -L044862 111111111111111111111111111111111111111111110111111111111111111111* -L044928 111111111111111111111111111111111111111111111111111111111111111111* -L044994 111111111111111111111111111111111111111111111111111111111111111111* -L045060 111111111111111111111111111111111111111111111111111111111111111111* -L045126 111111111111111111111111111111111111111111111111111111111111111111* + 111111111111111111111111111111101111111110111111111111111111111111* +L044862 111111111111111111111111111111111111111111010111111111111111111111* +L044928 111111101110111111111111111111111111111111011101111111011111111111* +L044994 111111101111111111111111111111111111111111011001111111011111111111* +L045060 000000000000000000000000000000000000000000000000000000000000000000* +L045126 000000000000000000000000000000000000000000000000000000000000000000* L045192 111111111111111111111111111111111111111111111111111111111111111111* L045258 111111111111111111111111111111111111111111111111111111111111111111* L045324 111111111111111111111111111111111111111111111111111111111111111111* @@ -916,19 +916,19 @@ L045390 111111111111111111111111111111111111111111111111111111111111111111* L045456 111111111111111111111111111111111111111111111111111111111111111111* L045522 111111111111111111111111111111111111111110111111111111111111111101* -L045588 011111111111111111111111111111111111111101101111111111111111111111* -L045654 011111111111111011111111111111111111111101111111111111111111111111* -L045720 011111111111111110111111111111111111111110111111101111111111111111* +L045588 111111111111111111111111111111111011111101011111111111111111111111* +L045654 111111111111111011111111111111111111111101011111111111111111111111* +L045720 111111111111111110111111111111111111111110011111101111111111111111* L045786 000000000000000000000000000000000000000000000000000000000000000000* L045852 000000000000000000000000000000000000000000000000000000000000000000* -L045918 011101111111111111111111010111111111111111111111111011111111111111* -L045984 011111111111111111011111111111111111111111111111111111111111111111* -L046050 000000000000000000000000000000000000000000000000000000000000000000* -L046116 000000000000000000000000000000000000000000000000000000000000000000* -L046182 000000000000000000000000000000000000000000000000000000000000000000* +L045918 111111111111111111111111101111111111111111111111111111111111111111* +L045984 111111111111111111111111111111111111111111111111111111111111111111* +L046050 111111111111111111111111111111111111111111111111111111111111111111* +L046116 111111111111111111111111111111111111111111111111111111111111111111* +L046182 111111111111111111111111111111111111111111111111111111111111111111* L046248 000000000000000000000000000000000000000000000000000000000000000000* -L046314 011111111011111111111111111111111111111111111111111111111111111111* +L046314 101111111111111111111111111111111111111111011111111111111111111111* L046380 111111111111111111111111111111111111111111111111111111111111111111* L046446 111111111111111111111111111111111111111111111111111111111111111111* L046512 111111111111111111111111111111111111111111111111111111111111111111* @@ -944,50 +944,50 @@ L046974 L047106 0010* L047110 11100110011000* L047124 00100110011110* -L047138 11100110010100* +L047138 10100110010100* L047152 11100011111111* L047166 10101111111001* L047180 10100110010011* -L047194 11100110010000* +L047194 10100110010000* L047208 11100011110011* L047222 10100110010000* L047236 10100110010010* -L047250 00010110010100* +L047250 00100110010100* L047264 11101111110011* L047278 11100110010011* -L047292 10100110010011* +L047292 00000110010011* L047306 01010110010000* L047320 11100011111111* NOTE BLOCK 7 * L047334 - 111111111111111111111111111111111111111111111111111111111111011011 - 111111111101111111111110111111111111111111111111111111111111111111 - 111110111111111111111111111111111110111111111111111111111111111111 - 111011111111111111111111111011111111111111111011111111111111111111 - 111111111111111111111111111111111111111111111111111011111111111111 - 111111111111111111111111011111101111011111111111111111111111111111 - 111111010111010111111111111101111111111111111111011111111111111111 - 111111111111111101101111111111111111111110111111111111101111111111 - 101111111111111111111111111111111011110111011110111111111111111111* + 111111111111111111111111111111111111111111111111111111111111011111 + 111111011101111111111111111111111111111111111111111011111111111111 + 111111111111111111111111111111111110111111111111111111111111111111 + 111001111111111111111011111011111111111111111011111111111111111111 + 111111111111111111111111111111111111111111111111111111111111111111 + 111111111111111011111111011111101111011111111111111111111111111111 + 111111110111011111111111111111111011111111111111011111111111111111 + 111111111111111101111111111111111111111010111111111111101111111111 + 101111111111111111011101111110111111111111111110111110111111111111* L047928 000000000000000000000000000000000000000000000000000000000000000000* L047994 011101111111111111111111111111111111111111111110111111011111111111* -L048060 011101111111111011111111111111111111111111111110111111111111111111* -L048126 011101101111111111111111111111111111111111111110111011111111111111* -L048192 011101101111110111111110111111111111111111111111110111101111111111* +L048060 011101101111111111111111111111111111111111111110111111111111111111* +L048126 011101111111111011111111111111111111111111111110111111111111101111* +L048192 011101011111111011111111111111111111111111111111111011101111011111* L048258 000000000000000000000000000000000000000000000000000000000000000000* -L048324 110111111011101111101111100111111101011011111111111111111111111111* +L048324 110111111011101111111110100111111101011011111111111111111111111111* L048390 000000000000000000000000000000000000000000000000000000000000000000* L048456 000000000000000000000000000000000000000000000000000000000000000000* L048522 000000000000000000000000000000000000000000000000000000000000000000* L048588 000000000000000000000000000000000000000000000000000000000000000000* L048654 000000000000000000000000000000000000000000000000000000000000000000* -L048720 111111111111111111111111111111111111111111111111111111011111111111* -L048786 111111111111111111111111111111111111111111111111111111111111111111* -L048852 111111111111111111111111111111111111111111111111111111111111111111* -L048918 111111111111111111111111111111111111111111111111111111111111111111* -L048984 111111111111111111111111111111111111111111111111111111111111111111* +L048720 011111101111111111110111111111111111111111111111111111011111111111* +L048786 011111111111111111111111111110111111111011111111111111111111111111* +L048852 000000000000000000000000000000000000000000000000000000000000000000* +L048918 000000000000000000000000000000000000000000000000000000000000000000* +L048984 000000000000000000000000000000000000000000000000000000000000000000* L049050 111111111111111111111111111111111111111111111111111111111111111111* L049116 111111111111111111111111111111111111111111111111111111111111111111* L049182 111111111111111111111111111111111111111111111111111111111111111111* @@ -997,17 +997,17 @@ L049380 111111111111111111111111111111111111111111111111111111111111111111* L049446 101111111111111111111111111111111111111111111111111111111111111111* L049512 111111111111111111111111111111111111011101111111111111111111111111* -L049578 111111111111110111111111111111110111011111111111111111101111111111* +L049578 111111011111111111111111111111111111011111111111111101101111111111* L049644 000000000000000000000000000000000000000000000000000000000000000000* L049710 000000000000000000000000000000000000000000000000000000000000000000* -L049776 111111111111110111111111111111111111111111111111111111111111111111* +L049776 111111011111111111111111111111111111111111111111111111111111111111* L049842 111111111111111111111111111111111111111111111111111111111111111111* L049908 111111111111111111111111111111111111111111111111111111111111111111* L049974 111111111111111111111111111111111111111111111111111111111111111111* L050040 111111111111111111111111111111111111111111111111111111111111111111* L050106 111111111110111111111111111111111111111110110111111111111111111111* -L050172 011111111111111111111111111110111111111111111111111111111111111111* +L050172 111111111111111111111111111111111111111111111111111111011111111111* L050238 111111111111111111111111111111111111111111111111111111111111111111* L050304 111111111111111111111111111111111111111111111111111111111111111111* L050370 111111111111111111111111111111111111111111111111111111111111111111* @@ -1019,12 +1019,12 @@ L050700 111111111111111111111111111111111111111111111111111111111111111111* L050766 111111111111111111111111111111111111111111111111111111111111111111* L050832 111111111101111111111111111111111111111111111111111111111111111111* -L050898 111111111111111111111111111111111011111111111111111111111111101111* +L050898 111111111111111111101111111111111111111111111111111110111111111111* L050964 111111111111111111111111111111111111111111111111111111111111111111* L051030 111111111111111111111111111111111111111111111111111111111111111111* L051096 111111111111111111111111111111111111111111111111111111111111111111* L051162 111111111111111111111111111111111111111111111111111111111111111111* -L051228 111111111111111111101111111111111111111111111111111111111111111011* +L051228 111111111111111111111111111110111111111011111111111111111111111111* L051294 111111111111111111111111111111111111111111111111111111111111111111* L051360 111111111111111111111111111111111111111111111111111111111111111111* L051426 111111111111111111111111111111111111111111111111111111111111111111* @@ -1044,15 +1044,15 @@ L052218 111111111111111111111111111111111111111111111111111111111111111111* L052284 111111111110111111111111111111111111111110111111111111111111111111* L052350 101111111111111111111111111111111111111111111111111111111111111111* -L052416 111111111111111111111111111111011111111101011111111111111111111111* +L052416 111111111111111111111111111111010111111101111111111111111111111111* L052482 111111111111111110111111111111111111111110111111101111111111111111* L052548 000000000000000000000000000000000000000000000000000000000000000000* L052614 000000000000000000000000000000000000000000000000000000000000000000* -L052680 011111111111111111101111111111111111111111111111111111111111111111* -L052746 111111111111111111111111111111111111111111111111111111111111111111* -L052812 111111111111111111111111111111111111111111111111111111111111111111* -L052878 111111111111111111111111111111111111111111111111111111111111111111* -L052944 111111111111111111111111111111111111111111111111111111111111111111* +L052680 011111101111111111110111111111111111111111111111111111011111111111* +L052746 011111111111110111111111111111111111111111111111111111011111111111* +L052812 011111101111110111111111111111111111111111111111111111111111111111* +L052878 000000000000000000000000000000000000000000000000000000000000000000* +L052944 000000000000000000000000000000000000000000000000000000000000000000* L053010 111111111111111111111111111111111111111111111111111111111111111111* L053076 111111111111111111111111111111111111111111111111111111111111111111* @@ -1071,18 +1071,18 @@ L053736 L053868 0010* L053872 11100110011100* L053886 01101011110010* -L053900 00010110010001* +L053900 11100110010001* L053914 11101011110011* L053928 10100110010000* L053942 00000110011110* -L053956 01010110010101* +L053956 00010110010101* L053970 11100011110011* L053984 01111111111000* L053998 01000011111110* L054012 11011011110110* L054026 11111111110011* L054040 10100110010001* -L054054 01000110010011* +L054054 10100110010011* L054068 11010011111100* L054082 11111011111111* E1 @@ -1102,8 +1102,8 @@ E1 00000000 1 00000000 -1 +0 * -CC62C* +C1315* U00000000000000000000000000000000* -9AF2 +988D diff --git a/Logic/68030_tk.lco b/Logic/68030_tk.lco index 206387f..133c717 100644 --- a/Logic/68030_tk.lco +++ b/Logic/68030_tk.lco @@ -16,8 +16,8 @@ RCS = "$Revision: 1.2 $"; Parent = m4a5.lci; SDS_File = m4a5.sds; Design = 68030_tk.tt4; -DATE = 10/6/16; -TIME = 22:04:16; +DATE = 10/15/16; +TIME = 23:48:29; Source_Format = Pure_VHDL; Type = TT2; Pre_Fit_Time = 1; @@ -88,33 +88,33 @@ LDS_000 = pin,31,-,D,-; nEXP_SPACE = pin,14,-,-,-; BERR = pin,41,-,E,-; BG_030 = pin,21,-,C,-; -BGACK_000 = pin,28,-,D,-; -CLK_030 = pin,64,-,-,-; AHIGH_30_ = pin,5,-,B,-; -CLK_000 = pin,11,-,-,-; +BGACK_000 = pin,28,-,D,-; AHIGH_29_ = pin,6,-,B,-; -CLK_OSZI = pin,61,-,-,-; +CLK_030 = pin,64,-,-,-; AHIGH_28_ = pin,15,-,C,-; -CLK_DIV_OUT = pin,65,-,G,-; +CLK_000 = pin,11,-,-,-; AHIGH_27_ = pin,16,-,C,-; +CLK_OSZI = pin,61,-,-,-; AHIGH_26_ = pin,17,-,C,-; -FPU_CS = pin,78,-,H,-; +CLK_DIV_OUT = pin,65,-,G,-; AHIGH_25_ = pin,18,-,C,-; -FPU_SENSE = pin,91,-,A,-; AHIGH_24_ = pin,19,-,C,-; -DSACK1 = pin,81,-,H,-; +FPU_CS = pin,78,-,H,-; A_DECODE_22_ = pin,84,-,H,-; -DTACK = pin,30,-,D,-; +FPU_SENSE = pin,91,-,A,-; A_DECODE_21_ = pin,94,-,A,-; -AVEC = pin,92,-,A,-; +DSACK1 = pin,81,-,H,-; A_DECODE_20_ = pin,93,-,A,-; -E = pin,66,-,G,-; +DTACK = pin,30,-,D,-; A_DECODE_19_ = pin,97,-,A,-; -VPA = pin,36,-,-,-; +AVEC = pin,92,-,A,-; A_DECODE_18_ = pin,95,-,A,-; +E = pin,66,-,G,-; A_DECODE_17_ = pin,59,-,F,-; -RST = pin,86,-,-,-; +VPA = pin,36,-,-,-; A_DECODE_16_ = pin,96,-,A,-; +RST = pin,86,-,-,-; RESET = pin,3,-,B,-; AMIGA_ADDR_ENABLE = pin,33,-,D,-; AMIGA_BUS_DATA_DIR = pin,48,-,E,-; @@ -129,59 +129,58 @@ SIZE_1_ = pin,79,-,H,-; IPL_030_2_ = pin,9,-,B,-; RW_000 = pin,80,-,H,-; BG_000 = pin,29,-,D,-; -BGACK_030 = pin,83,-,H,-; SIZE_0_ = pin,70,-,G,-; +BGACK_030 = pin,83,-,H,-; CLK_EXP = pin,10,-,B,-; VMA = pin,35,-,D,-; RW = pin,71,-,G,-; A_0_ = pin,69,-,G,-; IPL_030_1_ = pin,7,-,B,-; IPL_030_0_ = pin,8,-,B,-; -cpu_est_2_ = node,-,-,D,2; -cpu_est_3_ = node,-,-,A,12; -cpu_est_0_ = node,-,-,D,14; -cpu_est_1_ = node,-,-,D,13; -inst_AMIGA_BUS_ENABLE_DMA_LOW = node,-,-,G,6; -inst_AS_030_D0 = node,-,-,H,13; -inst_AS_030_000_SYNC = node,-,-,F,4; -inst_BGACK_030_INT_D = node,-,-,A,1; -inst_AS_000_DMA = node,-,-,C,13; -inst_DS_000_DMA = node,-,-,C,9; -CYCLE_DMA_0_ = node,-,-,D,10; -CYCLE_DMA_1_ = node,-,-,D,6; -inst_VPA_D = node,-,-,C,10; -CLK_000_D_2_ = node,-,-,H,2; -CLK_000_D_4_ = node,-,-,A,2; -inst_DTACK_D0 = node,-,-,H,6; +cpu_est_2_ = node,-,-,A,12; +cpu_est_3_ = node,-,-,D,9; +cpu_est_0_ = node,-,-,G,9; +cpu_est_1_ = node,-,-,A,8; +inst_AMIGA_BUS_ENABLE_DMA_HIGH = node,-,-,C,14; +inst_AMIGA_BUS_ENABLE_DMA_LOW = node,-,-,F,1; +inst_AS_030_D0 = node,-,-,E,5; +inst_AS_030_000_SYNC = node,-,-,F,0; +inst_BGACK_030_INT_D = node,-,-,E,8; +inst_AS_000_DMA = node,-,-,A,1; +inst_DS_000_DMA = node,-,-,A,13; +CYCLE_DMA_0_ = node,-,-,A,10; +CYCLE_DMA_1_ = node,-,-,A,6; +inst_VPA_D = node,-,-,A,9; +CLK_000_D_3_ = node,-,-,D,10; +inst_DTACK_D0 = node,-,-,B,6; inst_RESET_OUT = node,-,-,G,5; CLK_000_D_1_ = node,-,-,H,5; -CLK_000_D_0_ = node,-,-,D,9; -inst_CLK_OUT_PRE_50 = node,-,-,E,9; -inst_CLK_OUT_PRE_D = node,-,-,E,8; -IPL_D0_0_ = node,-,-,A,14; -IPL_D0_1_ = node,-,-,B,14; -IPL_D0_2_ = node,-,-,G,14; -CLK_000_D_3_ = node,-,-,A,13; -CLK_000_D_5_ = node,-,-,G,10; -inst_AMIGA_BUS_ENABLE_DMA_HIGH = node,-,-,G,2; -SM_AMIGA_1_ = node,-,-,A,5; -inst_UDS_000_INT = node,-,-,F,1; -inst_DS_000_ENABLE = node,-,-,B,6; -inst_LDS_000_INT = node,-,-,C,2; -SM_AMIGA_6_ = node,-,-,F,0; -SM_AMIGA_4_ = node,-,-,A,9; -SM_AMIGA_0_ = node,-,-,A,8; -RST_DLY_0_ = node,-,-,G,9; -RST_DLY_1_ = node,-,-,B,10; -RST_DLY_2_ = node,-,-,G,13; -inst_CLK_030_H = node,-,-,C,14; -inst_DSACK1_INT = node,-,-,F,12; -inst_AS_000_INT = node,-,-,C,6; -SM_AMIGA_5_ = node,-,-,B,13; -SM_AMIGA_3_ = node,-,-,A,10; -SM_AMIGA_2_ = node,-,-,A,6; -SM_AMIGA_i_7_ = node,-,-,F,8; -CIIN_0 = node,-,-,E,5; +CLK_000_D_0_ = node,-,-,C,9; +inst_CLK_OUT_PRE_50 = node,-,-,G,13; +inst_CLK_OUT_PRE_D = node,-,-,D,6; +IPL_D0_0_ = node,-,-,G,14; +IPL_D0_1_ = node,-,-,D,14; +IPL_D0_2_ = node,-,-,B,14; +CLK_000_D_2_ = node,-,-,H,6; +CLK_000_D_4_ = node,-,-,B,10; +inst_LDS_000_INT = node,-,-,F,8; +inst_DS_000_ENABLE = node,-,-,B,13; +inst_UDS_000_INT = node,-,-,F,12; +SM_AMIGA_6_ = node,-,-,C,13; +SM_AMIGA_4_ = node,-,-,D,2; +SM_AMIGA_1_ = node,-,-,F,4; +SM_AMIGA_0_ = node,-,-,H,13; +RST_DLY_0_ = node,-,-,G,2; +RST_DLY_1_ = node,-,-,G,10; +RST_DLY_2_ = node,-,-,G,6; +inst_CLK_030_H = node,-,-,A,2; +inst_DSACK1_INT = node,-,-,H,2; +inst_AS_000_INT = node,-,-,C,10; +SM_AMIGA_5_ = node,-,-,C,6; +SM_AMIGA_3_ = node,-,-,D,13; +SM_AMIGA_2_ = node,-,-,A,5; +SM_AMIGA_i_7_ = node,-,-,C,2; +CIIN_0 = node,-,-,E,9; [GROUP ASSIGNMENTS] Layer = OFF; @@ -194,7 +193,7 @@ Default = SLOW; FAST = CLK_DIV_OUT,CLK_EXP,FPU_CS,AMIGA_BUS_DATA_DIR,AMIGA_BUS_ENABLE_LOW,AMIGA_ADDR_ENABLE,AMIGA_BUS_ENABLE_HIGH,AS_030,A_16_,A_17_,A_18_,A_19_,RW,SIZE_1_,SIZE_0_,AVEC,BGACK_030,BG_000,E,IPL_030_0_,IPL_030_1_,IPL_030_2_,LDS_000,UDS_000,VMA,RESET,CIIN,A_20_,A_21_,A_22_,A_24_,A_25_,A_26_,A_27_,A_28_,A_29_,A_30_,A_31_,DS_030,BERR,A0,DSACK1,RW_000,AS_000,A_23_,A1,A_3_,A_2_,AHIGH_24_,AHIGH_25_,AHIGH_26_,AHIGH_27_,AHIGH_28_,AHIGH_29_,AHIGH_30_,AHIGH_31_,A_0_; [PULLUP] -Default = Up; +Default = Hold; [NETLIST/DELAY FORMAT] Delay_File = SDF; diff --git a/Logic/68030_tk.out b/Logic/68030_tk.out index ac9259f..616e8f6 100644 --- a/Logic/68030_tk.out +++ b/Logic/68030_tk.out @@ -1,2922 +1,19 @@ -113 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 79 RW_000 5 336 7 3 0 4 6 79 -1 4 0 21 - 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 - 68 A_0_ 5 342 6 2 0 2 68 -1 3 0 21 - 70 RW 5 341 6 2 5 7 70 -1 2 0 21 - 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 - 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 - 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 - 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 - 40 BERR 5 -1 4 1 2 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 335 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 344 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 343 1 0 6 -1 10 0 21 - 82 BGACK_030 5 338 7 0 82 -1 3 0 21 - 34 VMA 5 340 3 0 34 -1 3 0 21 - 80 DSACK1 5 339 7 0 80 -1 2 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 337 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 338 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 310 inst_RESET_OUT 3 -1 5 8 0 1 2 3 4 5 6 7 -1 -1 2 0 21 - 312 CLK_000_D_0_ 3 -1 1 6 0 2 3 5 6 7 -1 -1 1 0 21 - 311 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 4 5 0 3 4 5 7 -1 -1 1 0 21 - 333 SM_AMIGA_i_7_ 3 -1 3 4 2 3 5 7 -1 -1 4 0 21 - 322 SM_AMIGA_6_ 3 -1 2 4 0 2 5 7 -1 -1 3 0 21 - 300 inst_AS_030_000_SYNC 3 -1 5 3 2 3 5 -1 -1 7 0 21 - 296 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 - 294 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 - 323 SM_AMIGA_4_ 3 -1 0 3 0 2 5 -1 -1 3 0 21 - 295 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 1 1 21 - 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 - 332 SM_AMIGA_2_ 3 -1 2 2 2 3 -1 -1 5 0 21 - 326 RST_DLY_0_ 3 -1 5 2 5 6 -1 -1 4 0 21 - 340 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 - 330 SM_AMIGA_5_ 3 -1 2 2 0 2 -1 -1 3 0 21 - 325 SM_AMIGA_0_ 3 -1 7 2 3 7 -1 -1 3 0 21 - 324 SM_AMIGA_1_ 3 -1 3 2 3 7 -1 -1 3 0 21 - 320 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 319 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 - 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 293 cpu_est_0_ 3 -1 3 2 2 3 -1 -1 3 0 21 - 328 RST_DLY_2_ 3 -1 6 2 5 6 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 6 2 5 6 -1 -1 2 1 21 - 321 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 - 318 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 297 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21 - 314 inst_CLK_OUT_PRE_D 3 -1 7 2 1 6 -1 -1 1 0 21 - 313 inst_CLK_OUT_PRE_50 3 -1 1 2 1 7 -1 -1 1 0 21 - 308 inst_VPA_D 3 -1 7 2 2 3 -1 -1 1 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 2 5 6 -1 -1 1 0 21 - 344 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 343 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 335 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 - 329 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 - 331 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 - 336 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 - 342 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 - 341 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 339 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 - 337 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 334 N_68 3 -1 4 1 4 -1 -1 2 0 21 - 317 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 - 316 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 315 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 - 309 inst_DTACK_D0 3 -1 5 1 2 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 67 IPL_2_ 1 -1 -1 1 1 67 -1 - 63 CLK_030 1 -1 -1 1 0 63 -1 - 59 A_1_ 1 -1 -1 1 6 59 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 7 35 -1 - 29 DTACK 1 -1 -1 1 5 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 1 10 -1 -114 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 41 AS_000 5 -1 4 5 0 1 4 5 7 41 -1 1 0 21 - 79 RW_000 5 337 7 3 4 5 6 79 -1 4 0 21 - 70 RW 5 342 6 2 0 7 70 -1 2 0 21 - 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 - 31 UDS_000 5 -1 3 2 5 6 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 5 6 30 -1 1 0 21 - 68 A_0_ 5 343 6 1 5 68 -1 3 0 21 - 78 SIZE_1_ 5 -1 7 1 5 78 -1 1 0 21 - 69 SIZE_0_ 5 -1 6 1 5 69 -1 1 0 21 - 40 BERR 5 -1 4 1 3 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 336 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 345 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 344 1 0 6 -1 10 0 21 - 82 BGACK_030 5 339 7 0 82 -1 3 0 21 - 34 VMA 5 341 3 0 34 -1 3 0 21 - 80 DSACK1 5 340 7 0 80 -1 2 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 338 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 339 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 311 inst_RESET_OUT 3 -1 2 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 312 CLK_000_D_0_ 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 1 0 21 - 309 CLK_000_D_1_ 3 -1 4 6 0 1 2 3 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 4 6 0 1 2 3 4 7 -1 -1 1 0 21 - 323 SM_AMIGA_6_ 3 -1 0 4 0 1 5 7 -1 -1 3 0 21 - 300 inst_AS_030_000_SYNC 3 -1 2 3 0 2 3 -1 -1 7 0 21 - 334 SM_AMIGA_i_7_ 3 -1 0 3 0 2 7 -1 -1 3 1 21 - 304 CYCLE_DMA_0_ 3 -1 1 3 0 1 5 -1 -1 3 0 21 - 303 inst_DS_000_DMA 3 -1 5 2 0 5 -1 -1 9 0 21 - 302 inst_AS_000_DMA 3 -1 5 2 5 7 -1 -1 7 0 21 - 305 CYCLE_DMA_1_ 3 -1 0 2 0 5 -1 -1 4 0 21 - 295 cpu_est_1_ 3 -1 6 2 3 6 -1 -1 4 0 21 - 293 cpu_est_3_ 3 -1 3 2 3 6 -1 -1 4 0 21 - 331 SM_AMIGA_5_ 3 -1 1 2 0 1 -1 -1 3 0 21 - 326 SM_AMIGA_0_ 3 -1 7 2 0 7 -1 -1 3 0 21 - 325 SM_AMIGA_1_ 3 -1 3 2 3 7 -1 -1 3 0 21 - 324 SM_AMIGA_4_ 3 -1 0 2 0 3 -1 -1 3 0 21 - 321 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21 - 320 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 294 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 21 - 322 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 - 319 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 297 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21 - 314 inst_CLK_OUT_PRE_D 3 -1 7 2 1 6 -1 -1 1 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 2 2 6 -1 -1 1 0 21 - 296 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 1 1 21 - 345 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 344 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 336 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 330 inst_CLK_030_H 3 -1 5 1 5 -1 -1 8 0 21 - 333 SM_AMIGA_2_ 3 -1 3 1 3 -1 -1 5 0 21 - 332 SM_AMIGA_3_ 3 -1 3 1 3 -1 -1 5 0 21 - 337 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 327 RST_DLY_0_ 3 -1 2 1 2 -1 -1 4 0 21 - 343 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 341 RN_VMA 3 34 3 1 3 34 -1 3 0 21 - 342 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 340 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 - 338 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 335 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 329 RST_DLY_2_ 3 -1 2 1 2 -1 -1 2 0 21 - 328 RST_DLY_1_ 3 -1 2 1 2 -1 -1 2 1 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 - 318 CLK_000_D_2_ 3 -1 7 1 0 -1 -1 1 0 21 - 317 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21 - 316 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 - 315 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 - 313 inst_CLK_OUT_PRE_50 3 -1 7 1 7 -1 -1 1 0 21 - 310 inst_DTACK_D0 3 -1 0 1 3 -1 -1 1 0 21 - 308 inst_VPA_D 3 -1 0 1 3 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 0 1 67 -1 - 59 A_1_ 1 -1 -1 2 2 6 59 -1 - 55 IPL_1_ 1 -1 -1 2 1 6 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 66 IPL_0_ 1 -1 -1 1 1 66 -1 - 63 CLK_030 1 -1 -1 1 5 63 -1 - 35 VPA 1 -1 -1 1 0 35 -1 - 29 DTACK 1 -1 -1 1 0 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 6 10 -1 -113 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 79 RW_000 5 336 7 3 0 4 6 79 -1 4 0 21 - 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 - 68 A_0_ 5 342 6 2 0 2 68 -1 3 0 21 - 70 RW 5 341 6 2 5 7 70 -1 2 0 21 - 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 - 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 - 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 - 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 - 40 BERR 5 -1 4 1 2 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 335 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 344 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 343 1 0 6 -1 10 0 21 - 82 BGACK_030 5 338 7 0 82 -1 3 0 21 - 34 VMA 5 340 3 0 34 -1 3 0 21 - 80 DSACK1 5 339 7 0 80 -1 2 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 337 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 338 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 310 inst_RESET_OUT 3 -1 5 8 0 1 2 3 4 5 6 7 -1 -1 2 0 21 - 312 CLK_000_D_0_ 3 -1 1 6 0 2 3 5 6 7 -1 -1 1 0 21 - 311 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 4 5 0 3 4 5 7 -1 -1 1 0 21 - 333 SM_AMIGA_i_7_ 3 -1 3 4 2 3 5 7 -1 -1 4 0 21 - 322 SM_AMIGA_6_ 3 -1 2 4 0 2 5 7 -1 -1 3 0 21 - 300 inst_AS_030_000_SYNC 3 -1 5 3 2 3 5 -1 -1 7 0 21 - 296 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 - 294 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 - 323 SM_AMIGA_4_ 3 -1 0 3 0 2 5 -1 -1 3 0 21 - 295 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 1 1 21 - 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 - 332 SM_AMIGA_2_ 3 -1 2 2 2 3 -1 -1 5 0 21 - 326 RST_DLY_0_ 3 -1 5 2 5 6 -1 -1 4 0 21 - 340 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 - 330 SM_AMIGA_5_ 3 -1 2 2 0 2 -1 -1 3 0 21 - 325 SM_AMIGA_0_ 3 -1 7 2 3 7 -1 -1 3 0 21 - 324 SM_AMIGA_1_ 3 -1 3 2 3 7 -1 -1 3 0 21 - 320 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 319 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 - 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 293 cpu_est_0_ 3 -1 3 2 2 3 -1 -1 3 0 21 - 328 RST_DLY_2_ 3 -1 6 2 5 6 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 6 2 5 6 -1 -1 2 1 21 - 321 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 - 318 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 297 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21 - 314 inst_CLK_OUT_PRE_D 3 -1 7 2 1 6 -1 -1 1 0 21 - 313 inst_CLK_OUT_PRE_50 3 -1 1 2 1 7 -1 -1 1 0 21 - 308 inst_VPA_D 3 -1 7 2 2 3 -1 -1 1 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 2 5 6 -1 -1 1 0 21 - 344 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 343 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 335 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 - 329 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 - 331 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 - 336 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 - 342 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 - 341 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 339 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 - 337 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 334 N_68 3 -1 4 1 4 -1 -1 2 0 21 - 317 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 - 316 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 315 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 - 309 inst_DTACK_D0 3 -1 5 1 2 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 67 IPL_2_ 1 -1 -1 1 1 67 -1 - 63 CLK_030 1 -1 -1 1 0 63 -1 - 59 A_1_ 1 -1 -1 1 6 59 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 7 35 -1 - 29 DTACK 1 -1 -1 1 5 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 1 10 -1 -113 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 79 RW_000 5 336 7 3 0 4 6 79 -1 4 0 21 - 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 - 68 A_0_ 5 342 6 2 0 2 68 -1 3 0 21 - 70 RW 5 341 6 2 5 7 70 -1 2 0 21 - 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 - 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 - 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 - 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 - 40 BERR 5 -1 4 1 2 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 335 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 344 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 343 1 0 6 -1 10 0 21 - 82 BGACK_030 5 338 7 0 82 -1 3 0 21 - 34 VMA 5 340 3 0 34 -1 3 0 21 - 80 DSACK1 5 339 7 0 80 -1 2 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 337 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 338 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 310 inst_RESET_OUT 3 -1 5 8 0 1 2 3 4 5 6 7 -1 -1 2 0 21 - 312 CLK_000_D_0_ 3 -1 1 6 0 2 3 5 6 7 -1 -1 1 0 21 - 311 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 4 5 0 3 4 5 7 -1 -1 1 0 21 - 333 SM_AMIGA_i_7_ 3 -1 3 4 2 3 5 7 -1 -1 4 0 21 - 322 SM_AMIGA_6_ 3 -1 2 4 0 2 5 7 -1 -1 3 0 21 - 300 inst_AS_030_000_SYNC 3 -1 5 3 2 3 5 -1 -1 7 0 21 - 296 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 - 294 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 - 323 SM_AMIGA_4_ 3 -1 0 3 0 2 5 -1 -1 3 0 21 - 295 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 1 1 21 - 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 - 332 SM_AMIGA_2_ 3 -1 2 2 2 3 -1 -1 5 0 21 - 326 RST_DLY_0_ 3 -1 5 2 5 6 -1 -1 4 0 21 - 340 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 - 330 SM_AMIGA_5_ 3 -1 2 2 0 2 -1 -1 3 0 21 - 325 SM_AMIGA_0_ 3 -1 7 2 3 7 -1 -1 3 0 21 - 324 SM_AMIGA_1_ 3 -1 3 2 3 7 -1 -1 3 0 21 - 320 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 319 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 - 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 293 cpu_est_0_ 3 -1 3 2 2 3 -1 -1 3 0 21 - 328 RST_DLY_2_ 3 -1 6 2 5 6 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 6 2 5 6 -1 -1 2 1 21 - 321 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 - 318 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 297 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21 - 314 inst_CLK_OUT_PRE_D 3 -1 7 2 1 6 -1 -1 1 0 21 - 313 inst_CLK_OUT_PRE_50 3 -1 1 2 1 7 -1 -1 1 0 21 - 308 inst_VPA_D 3 -1 7 2 2 3 -1 -1 1 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 2 5 6 -1 -1 1 0 21 - 344 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 343 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 335 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 - 329 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 - 331 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 - 336 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 - 342 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 - 341 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 339 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 - 337 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 334 N_68 3 -1 4 1 4 -1 -1 2 0 21 - 317 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 - 316 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 315 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 - 309 inst_DTACK_D0 3 -1 5 1 2 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 67 IPL_2_ 1 -1 -1 1 1 67 -1 - 63 CLK_030 1 -1 -1 1 0 63 -1 - 59 A_1_ 1 -1 -1 1 6 59 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 7 35 -1 - 29 DTACK 1 -1 -1 1 5 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 1 10 -1 -114 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21 - 79 RW_000 5 337 7 3 2 4 6 79 -1 4 0 21 - 81 AS_030 5 -1 7 3 3 4 7 81 -1 1 0 21 - 70 RW 5 342 6 2 0 7 70 -1 2 0 21 - 31 UDS_000 5 -1 3 2 2 6 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 2 6 30 -1 1 0 21 - 68 A_0_ 5 343 6 1 5 68 -1 3 0 21 - 78 SIZE_1_ 5 -1 7 1 5 78 -1 1 0 21 - 69 SIZE_0_ 5 -1 6 1 5 69 -1 1 0 21 - 40 BERR 5 -1 4 1 5 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 336 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 345 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 344 1 0 6 -1 10 0 21 - 82 BGACK_030 5 339 7 0 82 -1 3 0 21 - 34 VMA 5 341 3 0 34 -1 3 0 21 - 80 DSACK1 5 340 7 0 80 -1 2 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 338 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 339 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 - 311 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 309 CLK_000_D_1_ 3 -1 7 7 0 2 3 4 5 6 7 -1 -1 1 0 21 - 312 CLK_000_D_0_ 3 -1 0 6 0 2 3 5 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 3 5 0 1 3 4 7 -1 -1 1 0 21 - 324 SM_AMIGA_6_ 3 -1 0 4 0 3 5 7 -1 -1 3 0 21 - 300 inst_AS_030_000_SYNC 3 -1 1 3 0 1 3 -1 -1 7 0 21 - 295 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 - 293 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 - 334 SM_AMIGA_i_7_ 3 -1 0 3 0 1 7 -1 -1 3 1 21 - 326 SM_AMIGA_0_ 3 -1 5 3 0 5 7 -1 -1 3 0 21 - 320 SM_AMIGA_1_ 3 -1 0 3 0 5 7 -1 -1 3 0 21 - 306 SIZE_DMA_0_ 3 -1 2 3 2 6 7 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 7 3 1 2 6 -1 -1 1 0 21 - 296 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 1 1 21 - 303 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 - 302 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21 - 333 SM_AMIGA_2_ 3 -1 5 2 0 5 -1 -1 5 0 21 - 341 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 - 331 SM_AMIGA_5_ 3 -1 3 2 0 3 -1 -1 3 0 21 - 325 SM_AMIGA_4_ 3 -1 0 2 0 5 -1 -1 3 0 21 - 323 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 322 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21 - 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 0 2 0 2 -1 -1 3 0 21 - 294 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 3 0 21 - 321 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 - 319 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21 - 297 inst_AS_000_INT 3 -1 3 2 3 4 -1 -1 2 0 21 - 314 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 - 308 inst_VPA_D 3 -1 6 2 3 5 -1 -1 1 0 21 - 345 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 344 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 336 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 330 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21 - 332 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 - 337 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 327 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 - 305 CYCLE_DMA_1_ 3 -1 2 1 2 -1 -1 4 0 21 - 343 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 342 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 340 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 - 338 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 335 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 329 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 - 328 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 - 318 CLK_000_D_2_ 3 -1 4 1 0 -1 -1 1 0 21 - 317 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 - 316 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 315 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 - 313 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 - 310 inst_DTACK_D0 3 -1 0 1 5 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 - 63 CLK_030 1 -1 -1 4 0 2 5 7 63 -1 - 96 A_DECODE_19_ 1 -1 -1 3 1 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 1 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 1 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 1 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 1 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 1 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 - 59 A_1_ 1 -1 -1 2 1 2 59 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 66 IPL_0_ 1 -1 -1 1 1 66 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 6 35 -1 - 29 DTACK 1 -1 -1 1 0 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 0 10 -1 -113 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 41 AS_000 5 -1 4 6 0 1 4 5 6 7 41 -1 1 0 21 - 79 RW_000 5 336 7 3 4 5 6 79 -1 4 0 21 - 68 A_0_ 5 342 6 2 2 3 68 -1 3 0 21 - 70 RW 5 341 6 2 2 7 70 -1 2 0 21 - 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 - 31 UDS_000 5 -1 3 2 5 6 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 5 6 30 -1 1 0 21 - 78 SIZE_1_ 5 -1 7 1 2 78 -1 1 0 21 - 69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21 - 40 BERR 5 -1 4 1 0 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 335 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 344 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 343 1 0 6 -1 10 0 21 - 82 BGACK_030 5 338 7 0 82 -1 3 0 21 - 34 VMA 5 340 3 0 34 -1 3 0 21 - 80 DSACK1 5 339 7 0 80 -1 2 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 337 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 338 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 310 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 312 CLK_000_D_0_ 3 -1 2 6 0 1 2 3 6 7 -1 -1 1 0 21 - 311 CLK_000_D_1_ 3 -1 7 6 0 1 2 3 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 7 5 2 3 4 5 7 -1 -1 1 0 21 - 333 SM_AMIGA_i_7_ 3 -1 2 4 2 3 5 7 -1 -1 4 0 21 - 323 SM_AMIGA_6_ 3 -1 3 4 0 2 3 7 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 7 4 1 2 5 6 -1 -1 1 0 21 - 300 inst_AS_030_000_SYNC 3 -1 5 3 2 3 5 -1 -1 7 0 21 - 296 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 - 294 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 304 CYCLE_DMA_0_ 3 -1 6 3 1 5 6 -1 -1 3 0 21 - 295 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 - 303 inst_DS_000_DMA 3 -1 5 2 0 5 -1 -1 9 0 21 - 302 inst_AS_000_DMA 3 -1 5 2 5 7 -1 -1 7 0 21 - 305 CYCLE_DMA_1_ 3 -1 1 2 1 5 -1 -1 4 0 21 - 340 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 325 SM_AMIGA_0_ 3 -1 7 2 2 7 -1 -1 3 0 21 - 324 SM_AMIGA_4_ 3 -1 0 2 0 2 -1 -1 3 0 21 - 322 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 - 321 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 - 319 SM_AMIGA_1_ 3 -1 0 2 0 7 -1 -1 3 0 21 - 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 293 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21 - 318 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 - 297 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 - 314 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 - 308 inst_VPA_D 3 -1 1 2 0 3 -1 -1 1 0 21 - 344 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 343 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 335 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 329 inst_CLK_030_H 3 -1 5 1 5 -1 -1 8 0 21 - 332 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 5 0 21 - 331 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 336 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 326 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 - 342 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 330 SM_AMIGA_5_ 3 -1 0 1 0 -1 -1 3 0 21 - 341 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 339 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 - 337 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 334 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 - 320 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 - 317 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 - 316 IPL_D0_1_ 3 -1 5 1 1 -1 -1 1 0 21 - 315 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 - 313 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 - 309 inst_DTACK_D0 3 -1 0 1 0 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 63 CLK_030 1 -1 -1 3 0 5 7 63 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 - 59 A_1_ 1 -1 -1 2 1 2 59 -1 - 55 IPL_1_ 1 -1 -1 2 1 5 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 67 IPL_2_ 1 -1 -1 1 1 67 -1 - 35 VPA 1 -1 -1 1 1 35 -1 - 29 DTACK 1 -1 -1 1 0 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 2 10 -1 -113 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 79 RW_000 5 336 7 3 0 4 6 79 -1 4 0 21 - 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 - 68 A_0_ 5 342 6 2 0 2 68 -1 3 0 21 - 70 RW 5 341 6 2 5 7 70 -1 2 0 21 - 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 - 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 - 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 - 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 - 40 BERR 5 -1 4 1 2 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 335 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 344 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 343 1 0 6 -1 10 0 21 - 82 BGACK_030 5 338 7 0 82 -1 3 0 21 - 34 VMA 5 340 3 0 34 -1 3 0 21 - 80 DSACK1 5 339 7 0 80 -1 2 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 337 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 338 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 310 inst_RESET_OUT 3 -1 5 8 0 1 2 3 4 5 6 7 -1 -1 2 0 21 - 312 CLK_000_D_0_ 3 -1 1 6 0 2 3 5 6 7 -1 -1 1 0 21 - 311 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 4 5 0 3 4 5 7 -1 -1 1 0 21 - 333 SM_AMIGA_i_7_ 3 -1 3 4 2 3 5 7 -1 -1 4 0 21 - 322 SM_AMIGA_6_ 3 -1 2 4 0 2 5 7 -1 -1 3 0 21 - 300 inst_AS_030_000_SYNC 3 -1 5 3 2 3 5 -1 -1 7 0 21 - 296 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 - 294 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 - 323 SM_AMIGA_4_ 3 -1 0 3 0 2 5 -1 -1 3 0 21 - 295 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 1 1 21 - 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 - 332 SM_AMIGA_2_ 3 -1 2 2 2 3 -1 -1 5 0 21 - 326 RST_DLY_0_ 3 -1 5 2 5 6 -1 -1 4 0 21 - 340 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 - 330 SM_AMIGA_5_ 3 -1 2 2 0 2 -1 -1 3 0 21 - 325 SM_AMIGA_0_ 3 -1 7 2 3 7 -1 -1 3 0 21 - 324 SM_AMIGA_1_ 3 -1 3 2 3 7 -1 -1 3 0 21 - 320 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 319 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 - 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 293 cpu_est_0_ 3 -1 3 2 2 3 -1 -1 3 0 21 - 328 RST_DLY_2_ 3 -1 6 2 5 6 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 6 2 5 6 -1 -1 2 1 21 - 321 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 - 318 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 297 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21 - 314 inst_CLK_OUT_PRE_D 3 -1 7 2 1 6 -1 -1 1 0 21 - 313 inst_CLK_OUT_PRE_50 3 -1 1 2 1 7 -1 -1 1 0 21 - 308 inst_VPA_D 3 -1 7 2 2 3 -1 -1 1 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 2 5 6 -1 -1 1 0 21 - 344 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 343 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 335 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 - 329 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 - 331 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 - 336 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 - 342 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 - 341 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 339 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 - 337 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 334 N_68 3 -1 4 1 4 -1 -1 2 0 21 - 317 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 - 316 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 315 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 - 309 inst_DTACK_D0 3 -1 5 1 2 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 67 IPL_2_ 1 -1 -1 1 1 67 -1 - 63 CLK_030 1 -1 -1 1 0 63 -1 - 59 A_1_ 1 -1 -1 1 6 59 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 7 35 -1 - 29 DTACK 1 -1 -1 1 5 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 1 10 -1 -113 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 79 RW_000 5 336 7 3 0 4 6 79 -1 4 0 21 - 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 - 68 A_0_ 5 342 6 2 0 2 68 -1 3 0 21 - 70 RW 5 341 6 2 5 7 70 -1 2 0 21 - 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 - 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 - 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 - 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 - 40 BERR 5 -1 4 1 2 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 335 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 344 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 343 1 0 6 -1 10 0 21 - 82 BGACK_030 5 338 7 0 82 -1 3 0 21 - 34 VMA 5 340 3 0 34 -1 3 0 21 - 80 DSACK1 5 339 7 0 80 -1 2 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 337 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 338 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 310 inst_RESET_OUT 3 -1 5 8 0 1 2 3 4 5 6 7 -1 -1 2 0 21 - 312 CLK_000_D_0_ 3 -1 1 6 0 2 3 5 6 7 -1 -1 1 0 21 - 311 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 4 5 0 3 4 5 7 -1 -1 1 0 21 - 333 SM_AMIGA_i_7_ 3 -1 3 4 2 3 5 7 -1 -1 4 0 21 - 322 SM_AMIGA_6_ 3 -1 2 4 0 2 5 7 -1 -1 3 0 21 - 300 inst_AS_030_000_SYNC 3 -1 5 3 2 3 5 -1 -1 7 0 21 - 296 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 - 294 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 - 323 SM_AMIGA_4_ 3 -1 0 3 0 2 5 -1 -1 3 0 21 - 295 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 1 1 21 - 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 - 332 SM_AMIGA_2_ 3 -1 2 2 2 3 -1 -1 5 0 21 - 326 RST_DLY_0_ 3 -1 5 2 5 6 -1 -1 4 0 21 - 340 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 - 330 SM_AMIGA_5_ 3 -1 2 2 0 2 -1 -1 3 0 21 - 325 SM_AMIGA_0_ 3 -1 7 2 3 7 -1 -1 3 0 21 - 324 SM_AMIGA_1_ 3 -1 3 2 3 7 -1 -1 3 0 21 - 321 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 - 320 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 293 cpu_est_0_ 3 -1 3 2 2 3 -1 -1 3 0 21 - 328 RST_DLY_2_ 3 -1 6 2 5 6 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 6 2 5 6 -1 -1 2 1 21 - 319 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 - 318 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 297 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21 - 314 inst_CLK_OUT_PRE_D 3 -1 7 2 1 6 -1 -1 1 0 21 - 313 inst_CLK_OUT_PRE_50 3 -1 1 2 1 7 -1 -1 1 0 21 - 308 inst_VPA_D 3 -1 7 2 2 3 -1 -1 1 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 2 5 6 -1 -1 1 0 21 - 344 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 343 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 335 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 - 329 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 - 331 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 - 336 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 - 342 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 - 341 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 339 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 - 337 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 334 N_68 3 -1 4 1 4 -1 -1 2 0 21 - 317 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 - 316 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 315 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 - 309 inst_DTACK_D0 3 -1 5 1 2 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 67 IPL_2_ 1 -1 -1 1 1 67 -1 - 63 CLK_030 1 -1 -1 1 0 63 -1 - 59 A_1_ 1 -1 -1 1 6 59 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 7 35 -1 - 29 DTACK 1 -1 -1 1 5 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 1 10 -1 -114 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 41 AS_000 5 -1 4 5 0 1 4 5 7 41 -1 1 0 21 - 79 RW_000 5 337 7 3 4 5 6 79 -1 4 0 21 - 70 RW 5 342 6 2 0 7 70 -1 2 0 21 - 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 - 31 UDS_000 5 -1 3 2 5 6 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 5 6 30 -1 1 0 21 - 68 A_0_ 5 343 6 1 5 68 -1 3 0 21 - 78 SIZE_1_ 5 -1 7 1 5 78 -1 1 0 21 - 69 SIZE_0_ 5 -1 6 1 5 69 -1 1 0 21 - 40 BERR 5 -1 4 1 3 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 336 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 345 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 344 1 0 6 -1 10 0 21 - 82 BGACK_030 5 339 7 0 82 -1 3 0 21 - 34 VMA 5 341 3 0 34 -1 3 0 21 - 80 DSACK1 5 340 7 0 80 -1 2 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 338 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 339 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 311 inst_RESET_OUT 3 -1 2 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 312 CLK_000_D_0_ 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 1 0 21 - 309 CLK_000_D_1_ 3 -1 4 6 0 1 2 3 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 4 6 0 1 2 3 4 7 -1 -1 1 0 21 - 323 SM_AMIGA_6_ 3 -1 0 4 0 1 5 7 -1 -1 3 0 21 - 300 inst_AS_030_000_SYNC 3 -1 2 3 0 2 3 -1 -1 7 0 21 - 334 SM_AMIGA_i_7_ 3 -1 0 3 0 2 7 -1 -1 3 1 21 - 304 CYCLE_DMA_0_ 3 -1 1 3 0 1 5 -1 -1 3 0 21 - 303 inst_DS_000_DMA 3 -1 5 2 0 5 -1 -1 9 0 21 - 302 inst_AS_000_DMA 3 -1 5 2 5 7 -1 -1 7 0 21 - 305 CYCLE_DMA_1_ 3 -1 0 2 0 5 -1 -1 4 0 21 - 295 cpu_est_1_ 3 -1 6 2 3 6 -1 -1 4 0 21 - 293 cpu_est_3_ 3 -1 3 2 3 6 -1 -1 4 0 21 - 331 SM_AMIGA_5_ 3 -1 1 2 0 1 -1 -1 3 0 21 - 326 SM_AMIGA_0_ 3 -1 7 2 0 7 -1 -1 3 0 21 - 325 SM_AMIGA_1_ 3 -1 3 2 3 7 -1 -1 3 0 21 - 324 SM_AMIGA_4_ 3 -1 0 2 0 3 -1 -1 3 0 21 - 322 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 321 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21 - 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 294 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 21 - 320 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 - 319 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 297 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21 - 314 inst_CLK_OUT_PRE_D 3 -1 7 2 1 6 -1 -1 1 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 2 2 6 -1 -1 1 0 21 - 296 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 1 1 21 - 345 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 344 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 336 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 330 inst_CLK_030_H 3 -1 5 1 5 -1 -1 8 0 21 - 333 SM_AMIGA_2_ 3 -1 3 1 3 -1 -1 5 0 21 - 332 SM_AMIGA_3_ 3 -1 3 1 3 -1 -1 5 0 21 - 337 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 327 RST_DLY_0_ 3 -1 2 1 2 -1 -1 4 0 21 - 343 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 341 RN_VMA 3 34 3 1 3 34 -1 3 0 21 - 342 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 340 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 - 338 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 335 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 329 RST_DLY_2_ 3 -1 2 1 2 -1 -1 2 0 21 - 328 RST_DLY_1_ 3 -1 2 1 2 -1 -1 2 1 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 - 318 CLK_000_D_2_ 3 -1 7 1 0 -1 -1 1 0 21 - 317 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21 - 316 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 - 315 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 - 313 inst_CLK_OUT_PRE_50 3 -1 7 1 7 -1 -1 1 0 21 - 310 inst_DTACK_D0 3 -1 0 1 3 -1 -1 1 0 21 - 308 inst_VPA_D 3 -1 0 1 3 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 0 1 67 -1 - 59 A_1_ 1 -1 -1 2 2 6 59 -1 - 55 IPL_1_ 1 -1 -1 2 1 6 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 66 IPL_0_ 1 -1 -1 1 1 66 -1 - 63 CLK_030 1 -1 -1 1 5 63 -1 - 35 VPA 1 -1 -1 1 0 35 -1 - 29 DTACK 1 -1 -1 1 0 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 6 10 -1 -115 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 79 RW_000 5 338 7 3 0 4 6 79 -1 4 0 21 - 81 AS_030 5 -1 7 3 0 4 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 - 68 A_0_ 5 344 6 2 1 5 68 -1 3 0 21 - 70 RW 5 343 6 2 2 7 70 -1 2 0 21 - 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 - 78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21 - 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 - 40 BERR 5 -1 4 1 2 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 337 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 346 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 345 1 0 6 -1 10 0 21 - 82 BGACK_030 5 340 7 0 82 -1 3 0 21 - 34 VMA 5 342 3 0 34 -1 3 0 21 - 80 DSACK1 5 341 7 0 80 -1 2 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 339 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 340 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 313 CLK_000_D_0_ 3 -1 1 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21 - 311 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 312 CLK_000_D_1_ 3 -1 4 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 0 5 2 3 4 5 7 -1 -1 1 0 21 - 324 SM_AMIGA_6_ 3 -1 5 4 1 2 5 7 -1 -1 3 0 21 - 295 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 - 293 cpu_est_3_ 3 -1 2 3 2 3 6 -1 -1 4 0 21 - 296 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 1 1 21 - 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 - 300 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 - 334 SM_AMIGA_2_ 3 -1 2 2 2 6 -1 -1 5 0 21 - 328 RST_DLY_0_ 3 -1 3 2 0 3 -1 -1 4 0 21 - 342 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 - 335 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 - 332 SM_AMIGA_5_ 3 -1 1 2 1 5 -1 -1 3 0 21 - 327 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21 - 326 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 325 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21 - 323 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 - 322 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 - 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 294 cpu_est_0_ 3 -1 3 2 2 3 -1 -1 3 0 21 - 330 RST_DLY_2_ 3 -1 3 2 0 3 -1 -1 2 0 21 - 329 RST_DLY_1_ 3 -1 0 2 0 3 -1 -1 2 1 21 - 321 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 - 320 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 297 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 - 315 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 - 309 CLK_000_D_2_ 3 -1 7 2 5 7 -1 -1 1 0 21 - 308 inst_VPA_D 3 -1 0 2 2 3 -1 -1 1 0 21 - 301 inst_BGACK_030_INT_D 3 -1 7 2 5 6 -1 -1 1 0 21 - 346 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 345 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 337 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 - 331 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 - 333 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 - 338 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 - 344 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 - 343 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 341 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 - 339 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 319 CLK_000_D_3_ 3 -1 7 1 5 -1 -1 1 0 21 - 318 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21 - 317 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 316 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 - 314 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 - 310 inst_DTACK_D0 3 -1 0 1 2 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 3 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 0 63 -1 - 59 A_1_ 1 -1 -1 1 6 59 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 0 35 -1 - 29 DTACK 1 -1 -1 1 0 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 1 10 -1 116 "number of signals after reading design file" "sig sig sig pair blk fan PT xor sync" "num name type sig num out pin node cnt PT type" "--- ---- ---- ---- --- --- --- ---- --- --- ----" - 41 AS_000 5 -1 4 5 0 4 5 6 7 41 -1 1 0 21 - 79 RW_000 5 339 7 3 4 5 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 3 0 5 6 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 0 5 6 30 -1 1 0 21 - 68 A_0_ 5 345 6 2 2 5 68 -1 3 0 21 + 81 AS_030 5 -1 7 4 0 4 5 7 81 -1 1 0 21 + 41 AS_000 5 -1 4 4 0 4 6 7 41 -1 1 0 21 + 79 RW_000 5 339 7 2 4 6 79 -1 4 0 21 70 RW 5 344 6 2 5 7 70 -1 2 0 21 - 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 - 78 SIZE_1_ 5 -1 7 1 5 78 -1 1 0 21 - 69 SIZE_0_ 5 -1 6 1 5 69 -1 1 0 21 - 40 BERR 5 -1 4 1 0 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 338 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 - 82 BGACK_030 5 341 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 - 80 DSACK1 5 342 7 0 80 -1 2 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 340 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 341 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 311 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 313 CLK_000_D_0_ 3 -1 3 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 312 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 4 5 2 3 4 5 7 -1 -1 1 0 21 - 325 SM_AMIGA_6_ 3 -1 2 4 2 5 6 7 -1 -1 3 0 21 - 302 inst_AS_000_DMA 3 -1 0 3 0 5 7 -1 -1 7 0 21 - 300 inst_AS_030_000_SYNC 3 -1 2 3 1 2 3 -1 -1 7 0 21 - 295 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 293 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 336 SM_AMIGA_i_7_ 3 -1 1 3 1 2 7 -1 -1 3 1 21 - 326 SM_AMIGA_4_ 3 -1 1 3 0 1 5 -1 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 6 3 0 5 6 -1 -1 3 0 21 - 296 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 1 1 21 - 303 inst_DS_000_DMA 3 -1 5 2 0 5 -1 -1 9 0 21 - 332 inst_CLK_030_H 3 -1 0 2 0 5 -1 -1 8 0 21 - 335 SM_AMIGA_2_ 3 -1 0 2 0 6 -1 -1 5 0 21 - 305 CYCLE_DMA_1_ 3 -1 0 2 0 5 -1 -1 4 0 21 - 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 333 SM_AMIGA_5_ 3 -1 6 2 1 6 -1 -1 3 0 21 - 328 SM_AMIGA_0_ 3 -1 7 2 1 7 -1 -1 3 0 21 - 327 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 324 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 323 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 294 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21 - 322 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 - 321 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21 - 297 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 - 320 CLK_000_D_4_ 3 -1 2 2 1 2 -1 -1 1 0 21 - 315 inst_CLK_OUT_PRE_D 3 -1 1 2 1 6 -1 -1 1 0 21 - 314 inst_CLK_OUT_PRE_50 3 -1 7 2 1 7 -1 -1 1 0 21 - 309 CLK_000_D_3_ 3 -1 5 2 1 2 -1 -1 1 0 21 - 308 inst_VPA_D 3 -1 6 2 0 3 -1 -1 1 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 2 2 6 -1 -1 1 0 21 - 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 334 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 329 RST_DLY_0_ 3 -1 3 1 3 -1 -1 4 0 21 - 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 342 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 - 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 337 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 331 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21 - 330 RST_DLY_1_ 3 -1 3 1 3 -1 -1 2 1 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 - 319 CLK_000_D_2_ 3 -1 7 1 5 -1 -1 1 0 21 - 318 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 - 317 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 316 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21 - 310 inst_DTACK_D0 3 -1 4 1 0 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 - 66 IPL_0_ 1 -1 -1 2 0 1 66 -1 - 63 CLK_030 1 -1 -1 2 0 5 63 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 59 A_1_ 1 -1 -1 1 2 59 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 6 35 -1 - 29 DTACK 1 -1 -1 1 4 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 3 10 -1 -116 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 79 RW_000 5 339 7 3 0 4 6 79 -1 4 0 21 - 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 - 68 A_0_ 5 345 6 2 1 5 68 -1 3 0 21 - 70 RW 5 344 6 2 5 7 70 -1 2 0 21 - 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 - 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 - 78 SIZE_1_ 5 -1 7 1 5 78 -1 1 0 21 - 69 SIZE_0_ 5 -1 6 1 5 69 -1 1 0 21 - 40 BERR 5 -1 4 1 0 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 338 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 - 82 BGACK_030 5 341 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 - 80 DSACK1 5 342 7 0 80 -1 2 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 340 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 341 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 - 312 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 313 CLK_000_D_0_ 3 -1 6 6 0 2 3 5 6 7 -1 -1 1 0 21 - 309 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 4 5 2 3 4 5 7 -1 -1 1 0 21 - 326 SM_AMIGA_6_ 3 -1 5 4 1 2 5 7 -1 -1 3 0 21 - 300 inst_AS_030_000_SYNC 3 -1 2 3 2 3 5 -1 -1 7 0 21 - 296 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 - 294 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 336 SM_AMIGA_i_7_ 3 -1 5 3 2 5 7 -1 -1 3 1 21 - 327 SM_AMIGA_4_ 3 -1 2 3 0 2 5 -1 -1 3 0 21 - 319 CLK_000_D_2_ 3 -1 7 3 4 6 7 -1 -1 1 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 3 1 2 6 -1 -1 1 0 21 - 293 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 - 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 - 335 SM_AMIGA_2_ 3 -1 0 2 0 6 -1 -1 5 0 21 - 329 RST_DLY_0_ 3 -1 6 2 2 6 -1 -1 4 0 21 - 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 328 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21 - 325 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 324 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 322 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 295 cpu_est_0_ 3 -1 0 2 0 3 -1 -1 3 0 21 - 331 RST_DLY_2_ 3 -1 2 2 2 6 -1 -1 2 0 21 - 330 RST_DLY_1_ 3 -1 2 2 2 6 -1 -1 2 1 21 - 323 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 - 321 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21 - 297 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 - 315 inst_CLK_OUT_PRE_D 3 -1 5 2 1 6 -1 -1 1 0 21 - 314 inst_CLK_OUT_PRE_50 3 -1 3 2 3 5 -1 -1 1 0 21 - 310 CLK_000_D_3_ 3 -1 4 2 5 6 -1 -1 1 0 21 - 308 inst_VPA_D 3 -1 3 2 0 3 -1 -1 1 0 21 - 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 - 332 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 - 334 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 - 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 333 SM_AMIGA_5_ 3 -1 2 1 2 -1 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 - 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 342 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 - 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 337 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 320 CLK_000_D_4_ 3 -1 6 1 5 -1 -1 1 0 21 - 318 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21 - 317 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 316 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 - 311 inst_DTACK_D0 3 -1 3 1 0 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 3 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 0 63 -1 - 59 A_1_ 1 -1 -1 1 1 59 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 3 35 -1 - 29 DTACK 1 -1 -1 1 3 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 6 10 -1 -116 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 41 AS_000 5 -1 4 4 0 4 5 7 41 -1 1 0 21 - 79 RW_000 5 339 7 3 4 5 6 79 -1 4 0 21 - 68 A_0_ 5 345 6 2 3 5 68 -1 3 0 21 - 70 RW 5 344 6 2 1 7 70 -1 2 0 21 - 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 - 31 UDS_000 5 -1 3 2 5 6 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 5 6 30 -1 1 0 21 - 78 SIZE_1_ 5 -1 7 1 5 78 -1 1 0 21 - 69 SIZE_0_ 5 -1 6 1 5 69 -1 1 0 21 - 40 BERR 5 -1 4 1 0 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 338 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 - 82 BGACK_030 5 341 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 - 80 DSACK1 5 342 7 0 80 -1 2 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 340 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 341 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 312 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 314 CLK_000_D_0_ 3 -1 1 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 313 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 326 SM_AMIGA_6_ 3 -1 2 5 1 2 3 5 7 -1 -1 3 0 21 - 310 CLK_000_D_3_ 3 -1 7 5 1 2 4 5 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 4 5 1 2 3 4 7 -1 -1 1 0 21 - 328 SM_AMIGA_0_ 3 -1 1 3 1 2 7 -1 -1 4 0 21 - 322 SM_AMIGA_1_ 3 -1 5 3 1 5 7 -1 -1 4 0 21 - 295 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 - 293 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 - 309 CLK_000_D_2_ 3 -1 7 3 1 5 7 -1 -1 1 0 21 - 296 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 - 303 inst_DS_000_DMA 3 -1 5 2 0 5 -1 -1 9 0 21 - 302 inst_AS_000_DMA 3 -1 5 2 5 7 -1 -1 7 0 21 - 300 inst_AS_030_000_SYNC 3 -1 2 2 2 3 -1 -1 7 0 21 - 335 SM_AMIGA_2_ 3 -1 0 2 0 5 -1 -1 5 0 21 - 305 CYCLE_DMA_1_ 3 -1 0 2 0 5 -1 -1 4 0 21 - 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 336 SM_AMIGA_i_7_ 3 -1 2 2 2 7 -1 -1 3 1 21 - 333 SM_AMIGA_5_ 3 -1 3 2 0 3 -1 -1 3 0 21 - 327 SM_AMIGA_4_ 3 -1 0 2 0 1 -1 -1 3 0 21 - 325 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 324 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21 - 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 0 2 0 5 -1 -1 3 0 21 - 294 cpu_est_0_ 3 -1 0 2 0 3 -1 -1 3 0 21 - 321 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21 - 297 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21 - 316 inst_CLK_OUT_PRE_D 3 -1 7 2 1 6 -1 -1 1 0 21 - 308 inst_VPA_D 3 -1 2 2 0 3 -1 -1 1 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 2 2 6 -1 -1 1 0 21 - 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 332 inst_CLK_030_H 3 -1 5 1 5 -1 -1 8 0 21 - 334 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 329 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 - 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 342 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 - 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 337 N_264 3 -1 4 1 4 -1 -1 2 0 21 - 331 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 - 330 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 - 323 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 - 320 CLK_000_D_4_ 3 -1 4 1 2 -1 -1 1 0 21 - 319 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21 - 318 IPL_D0_1_ 3 -1 0 1 1 -1 -1 1 0 21 - 317 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21 - 315 inst_CLK_OUT_PRE_50 3 -1 7 1 7 -1 -1 1 0 21 - 311 inst_DTACK_D0 3 -1 0 1 0 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 3 67 -1 - 66 IPL_0_ 1 -1 -1 2 0 1 66 -1 - 55 IPL_1_ 1 -1 -1 2 0 1 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 5 63 -1 - 59 A_1_ 1 -1 -1 1 2 59 -1 - 35 VPA 1 -1 -1 1 2 35 -1 - 29 DTACK 1 -1 -1 1 0 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 1 10 -1 -116 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 79 RW_000 5 339 7 3 0 4 6 79 -1 4 0 21 - 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 - 68 A_0_ 5 345 6 2 1 5 68 -1 3 0 21 - 70 RW 5 344 6 2 5 7 70 -1 2 0 21 - 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 - 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 - 78 SIZE_1_ 5 -1 7 1 5 78 -1 1 0 21 - 69 SIZE_0_ 5 -1 6 1 5 69 -1 1 0 21 - 40 BERR 5 -1 4 1 0 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 338 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 - 82 BGACK_030 5 341 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 - 80 DSACK1 5 342 7 0 80 -1 2 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 340 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 341 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 - 312 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 313 CLK_000_D_0_ 3 -1 6 6 0 2 3 5 6 7 -1 -1 1 0 21 - 309 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 4 5 2 3 4 5 7 -1 -1 1 0 21 - 326 SM_AMIGA_6_ 3 -1 5 4 1 2 5 7 -1 -1 3 0 21 - 300 inst_AS_030_000_SYNC 3 -1 2 3 2 3 5 -1 -1 7 0 21 - 296 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 - 294 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 336 SM_AMIGA_i_7_ 3 -1 5 3 2 5 7 -1 -1 3 1 21 - 327 SM_AMIGA_4_ 3 -1 2 3 0 2 5 -1 -1 3 0 21 - 319 CLK_000_D_2_ 3 -1 7 3 4 6 7 -1 -1 1 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 3 1 2 6 -1 -1 1 0 21 - 293 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 - 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 - 335 SM_AMIGA_2_ 3 -1 0 2 0 6 -1 -1 5 0 21 - 329 RST_DLY_0_ 3 -1 6 2 2 6 -1 -1 4 0 21 - 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 328 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21 - 325 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 324 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 322 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 295 cpu_est_0_ 3 -1 0 2 0 3 -1 -1 3 0 21 - 331 RST_DLY_2_ 3 -1 2 2 2 6 -1 -1 2 0 21 - 330 RST_DLY_1_ 3 -1 2 2 2 6 -1 -1 2 1 21 - 323 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 - 321 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21 - 297 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 - 315 inst_CLK_OUT_PRE_D 3 -1 5 2 1 6 -1 -1 1 0 21 - 314 inst_CLK_OUT_PRE_50 3 -1 3 2 3 5 -1 -1 1 0 21 - 310 CLK_000_D_3_ 3 -1 4 2 5 6 -1 -1 1 0 21 - 308 inst_VPA_D 3 -1 3 2 0 3 -1 -1 1 0 21 - 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 - 332 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 - 334 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 - 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 333 SM_AMIGA_5_ 3 -1 2 1 2 -1 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 - 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 342 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 - 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 337 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 320 CLK_000_D_4_ 3 -1 6 1 5 -1 -1 1 0 21 - 318 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21 - 317 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 316 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 - 311 inst_DTACK_D0 3 -1 3 1 0 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 3 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 0 63 -1 - 59 A_1_ 1 -1 -1 1 1 59 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 3 35 -1 - 29 DTACK 1 -1 -1 1 3 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 6 10 -1 -116 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 4 1 4 5 7 81 -1 1 0 21 - 79 RW_000 5 339 7 3 0 4 6 79 -1 4 0 21 - 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 - 68 A_0_ 5 345 6 2 0 5 68 -1 3 0 21 - 70 RW 5 344 6 2 1 7 70 -1 2 0 21 - 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 - 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 - 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 - 40 BERR 5 -1 4 1 2 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 338 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 - 82 BGACK_030 5 341 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 - 80 DSACK1 5 342 7 0 80 -1 2 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 340 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 341 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 311 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 312 CLK_000_D_0_ 3 -1 6 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 308 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 325 SM_AMIGA_6_ 3 -1 5 5 0 1 2 5 7 -1 -1 3 0 21 - 293 cpu_est_0_ 3 -1 7 4 2 3 6 7 -1 -1 3 0 21 - 296 cpu_est_3_ 3 -1 6 3 2 3 6 -1 -1 4 0 21 - 294 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 - 298 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 - 295 cpu_est_2_ 3 -1 3 3 2 3 6 -1 -1 1 1 21 - 301 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 - 299 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 - 335 SM_AMIGA_2_ 3 -1 2 2 2 6 -1 -1 5 0 21 - 343 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 - 336 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 - 333 SM_AMIGA_5_ 3 -1 2 2 1 2 -1 -1 3 0 21 - 327 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21 - 326 SM_AMIGA_4_ 3 -1 1 2 1 2 -1 -1 3 0 21 - 324 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 - 323 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21 - 321 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 306 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 305 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 332 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21 - 322 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 - 320 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21 - 318 CLK_000_D_2_ 3 -1 7 2 6 7 -1 -1 1 0 21 - 314 inst_CLK_OUT_PRE_D 3 -1 0 2 1 6 -1 -1 1 0 21 - 313 inst_CLK_OUT_PRE_50 3 -1 2 2 0 2 -1 -1 1 0 21 - 309 CLK_000_D_3_ 3 -1 7 2 1 5 -1 -1 1 0 21 - 307 inst_VPA_D 3 -1 6 2 2 3 -1 -1 1 0 21 - 300 inst_BGACK_030_INT_D 3 -1 4 2 5 6 -1 -1 1 0 21 - 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 302 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 - 331 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 - 334 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 - 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 328 RST_DLY_0_ 3 -1 3 1 3 -1 -1 4 0 21 - 304 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 - 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 303 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 - 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 342 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 - 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 337 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 330 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21 - 329 RST_DLY_1_ 3 -1 3 1 3 -1 -1 2 1 21 - 319 CLK_000_D_4_ 3 -1 1 1 5 -1 -1 1 0 21 - 317 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21 - 316 IPL_D0_1_ 3 -1 0 1 1 -1 -1 1 0 21 - 315 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21 - 310 inst_DTACK_D0 3 -1 0 1 2 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 2 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 2 66 -1 - 59 A_1_ 1 -1 -1 2 5 6 59 -1 - 55 IPL_1_ 1 -1 -1 2 0 1 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 0 63 -1 - 35 VPA 1 -1 -1 1 6 35 -1 - 29 DTACK 1 -1 -1 1 0 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 6 10 -1 -116 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 6 2 3 4 5 6 7 81 -1 1 0 21 - 79 RW_000 5 339 7 3 0 4 6 79 -1 4 0 21 - 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 - 68 A_0_ 5 345 6 2 1 2 68 -1 3 0 21 - 70 RW 5 344 6 2 2 7 70 -1 2 0 21 - 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 - 78 SIZE_1_ 5 -1 7 1 2 78 -1 1 0 21 - 69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21 - 40 BERR 5 -1 4 1 0 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 338 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 - 82 BGACK_030 5 341 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 - 80 DSACK1 5 342 7 0 80 -1 2 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 340 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 341 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 312 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 313 CLK_000_D_0_ 3 -1 3 6 0 2 3 5 6 7 -1 -1 1 0 21 - 309 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 - 325 SM_AMIGA_6_ 3 -1 5 5 1 2 5 6 7 -1 -1 3 0 21 - 295 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 293 cpu_est_3_ 3 -1 6 3 0 3 6 -1 -1 4 0 21 - 327 SM_AMIGA_0_ 3 -1 3 3 3 5 7 -1 -1 3 0 21 - 321 SM_AMIGA_1_ 3 -1 2 3 2 3 7 -1 -1 3 0 21 - 294 cpu_est_0_ 3 -1 3 3 0 3 6 -1 -1 3 0 21 - 319 CLK_000_D_2_ 3 -1 2 3 2 3 7 -1 -1 1 0 21 - 301 inst_BGACK_030_INT_D 3 -1 7 3 1 5 6 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 7 3 3 4 5 -1 -1 1 0 21 - 296 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 1 1 21 - 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 - 300 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 - 335 SM_AMIGA_2_ 3 -1 0 2 0 2 -1 -1 5 0 21 - 328 RST_DLY_0_ 3 -1 5 2 3 5 -1 -1 4 0 21 - 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 336 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 - 326 SM_AMIGA_4_ 3 -1 2 2 0 2 -1 -1 3 0 21 - 324 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 - 323 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 - 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 332 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21 - 330 RST_DLY_2_ 3 -1 3 2 3 5 -1 -1 2 0 21 - 329 RST_DLY_1_ 3 -1 3 2 3 5 -1 -1 2 1 21 - 322 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 - 315 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 - 310 CLK_000_D_3_ 3 -1 7 2 1 5 -1 -1 1 0 21 - 308 inst_VPA_D 3 -1 6 2 0 3 -1 -1 1 0 21 - 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 - 331 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 - 334 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 - 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 333 SM_AMIGA_5_ 3 -1 2 1 2 -1 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 - 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 342 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 - 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 337 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 320 CLK_000_D_4_ 3 -1 1 1 5 -1 -1 1 0 21 - 318 IPL_D0_2_ 3 -1 7 1 1 -1 -1 1 0 21 - 317 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 - 316 IPL_D0_0_ 3 -1 5 1 1 -1 -1 1 0 21 - 314 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 - 311 inst_DTACK_D0 3 -1 6 1 0 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 7 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 5 66 -1 - 55 IPL_1_ 1 -1 -1 2 1 6 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 0 63 -1 - 59 A_1_ 1 -1 -1 1 1 59 -1 - 35 VPA 1 -1 -1 1 6 35 -1 - 29 DTACK 1 -1 -1 1 6 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 3 10 -1 -116 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 5 0 3 4 5 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21 - 79 RW_000 5 341 7 3 0 4 6 79 -1 4 0 21 - 70 RW 5 346 6 3 0 3 7 70 -1 2 0 21 - 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 - 68 A_0_ 5 347 6 1 5 68 -1 3 0 21 - 78 SIZE_1_ 5 -1 7 1 5 78 -1 1 0 21 - 69 SIZE_0_ 5 -1 6 1 5 69 -1 1 0 21 - 40 BERR 5 -1 4 1 2 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 340 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 339 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 338 1 0 6 -1 10 0 21 - 82 BGACK_030 5 343 7 0 82 -1 3 0 21 - 34 VMA 5 345 3 0 34 -1 3 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 3 0 21 - 80 DSACK1 5 344 7 0 80 -1 2 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 28 BG_000 5 342 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 343 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 312 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 313 CLK_000_D_0_ 3 -1 6 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 309 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 325 SM_AMIGA_6_ 3 -1 5 4 0 5 6 7 -1 -1 3 0 21 - 295 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 - 293 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 - 294 cpu_est_0_ 3 -1 6 3 2 3 6 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 3 1 5 6 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 - 296 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 1 1 21 - 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 - 300 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 - 335 SM_AMIGA_2_ 3 -1 2 2 1 2 -1 -1 5 0 21 - 328 RST_DLY_0_ 3 -1 3 2 1 3 -1 -1 4 0 21 - 305 CYCLE_DMA_1_ 3 -1 2 2 0 2 -1 -1 4 0 21 - 345 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 - 336 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 - 333 SM_AMIGA_5_ 3 -1 6 2 2 6 -1 -1 3 0 21 - 327 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21 - 326 SM_AMIGA_4_ 3 -1 2 2 0 2 -1 -1 3 0 21 - 324 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 323 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21 - 321 SM_AMIGA_1_ 3 -1 1 2 1 7 -1 -1 3 0 21 - 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 2 2 0 2 -1 -1 3 0 21 - 332 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21 - 330 RST_DLY_2_ 3 -1 1 2 1 3 -1 -1 2 0 21 - 329 RST_DLY_1_ 3 -1 3 2 1 3 -1 -1 2 1 21 - 322 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 - 319 CLK_000_D_2_ 3 -1 7 2 1 7 -1 -1 1 0 21 - 315 inst_CLK_OUT_PRE_D 3 -1 7 2 1 6 -1 -1 1 0 21 - 310 CLK_000_D_3_ 3 -1 7 2 0 5 -1 -1 1 0 21 - 308 inst_VPA_D 3 -1 0 2 2 3 -1 -1 1 0 21 - 340 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 339 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 338 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 - 331 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 - 334 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 - 341 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 347 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 346 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 344 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 - 342 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 337 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 320 CLK_000_D_4_ 3 -1 0 1 5 -1 -1 1 0 21 - 318 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 - 317 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 316 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21 - 314 inst_CLK_OUT_PRE_50 3 -1 7 1 7 -1 -1 1 0 21 - 311 inst_DTACK_D0 3 -1 0 1 2 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 - 66 IPL_0_ 1 -1 -1 2 0 1 66 -1 - 59 A_1_ 1 -1 -1 2 1 6 59 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 0 63 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 0 35 -1 - 29 DTACK 1 -1 -1 1 0 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 6 10 -1 -116 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 4 1 4 5 7 81 -1 1 0 21 - 79 RW_000 5 339 7 3 0 4 6 79 -1 4 0 21 - 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 - 68 A_0_ 5 345 6 2 0 5 68 -1 3 0 21 - 70 RW 5 344 6 2 1 7 70 -1 2 0 21 - 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 - 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 - 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 - 40 BERR 5 -1 4 1 2 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 338 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 - 82 BGACK_030 5 341 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 - 80 DSACK1 5 342 7 0 80 -1 2 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 340 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 341 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 311 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 312 CLK_000_D_0_ 3 -1 6 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 308 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 325 SM_AMIGA_6_ 3 -1 5 5 0 1 2 5 7 -1 -1 3 0 21 - 293 cpu_est_0_ 3 -1 7 4 2 3 6 7 -1 -1 3 0 21 - 296 cpu_est_3_ 3 -1 6 3 2 3 6 -1 -1 4 0 21 - 294 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 - 298 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 - 295 cpu_est_2_ 3 -1 3 3 2 3 6 -1 -1 1 1 21 - 301 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 - 299 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 - 335 SM_AMIGA_2_ 3 -1 2 2 2 6 -1 -1 5 0 21 - 343 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 - 336 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 - 333 SM_AMIGA_5_ 3 -1 2 2 1 2 -1 -1 3 0 21 - 327 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21 - 326 SM_AMIGA_4_ 3 -1 1 2 1 2 -1 -1 3 0 21 - 324 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 - 323 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21 - 321 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 306 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 305 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 332 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21 - 322 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 - 320 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21 - 318 CLK_000_D_2_ 3 -1 7 2 6 7 -1 -1 1 0 21 - 314 inst_CLK_OUT_PRE_D 3 -1 0 2 1 6 -1 -1 1 0 21 - 313 inst_CLK_OUT_PRE_50 3 -1 2 2 0 2 -1 -1 1 0 21 - 309 CLK_000_D_3_ 3 -1 7 2 1 5 -1 -1 1 0 21 - 307 inst_VPA_D 3 -1 6 2 2 3 -1 -1 1 0 21 - 300 inst_BGACK_030_INT_D 3 -1 4 2 5 6 -1 -1 1 0 21 - 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 302 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 - 331 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 - 334 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 - 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 328 RST_DLY_0_ 3 -1 3 1 3 -1 -1 4 0 21 - 304 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 - 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 303 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 - 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 342 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 - 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 337 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 330 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21 - 329 RST_DLY_1_ 3 -1 3 1 3 -1 -1 2 1 21 - 319 CLK_000_D_4_ 3 -1 1 1 5 -1 -1 1 0 21 - 317 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21 - 316 IPL_D0_1_ 3 -1 0 1 1 -1 -1 1 0 21 - 315 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21 - 310 inst_DTACK_D0 3 -1 0 1 2 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 2 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 2 66 -1 - 59 A_1_ 1 -1 -1 2 5 6 59 -1 - 55 IPL_1_ 1 -1 -1 2 0 1 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 0 63 -1 - 35 VPA 1 -1 -1 1 6 35 -1 - 29 DTACK 1 -1 -1 1 0 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 6 10 -1 -116 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 4 1 4 5 7 81 -1 1 0 21 - 79 RW_000 5 339 7 3 0 4 6 79 -1 4 0 21 - 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 - 68 A_0_ 5 345 6 2 0 5 68 -1 3 0 21 - 70 RW 5 344 6 2 1 7 70 -1 2 0 21 - 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 - 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 - 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 - 40 BERR 5 -1 4 1 2 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 338 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 - 82 BGACK_030 5 341 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 - 80 DSACK1 5 342 7 0 80 -1 2 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 340 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 341 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 311 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 312 CLK_000_D_0_ 3 -1 6 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 308 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 325 SM_AMIGA_6_ 3 -1 5 5 0 1 2 5 7 -1 -1 3 0 21 - 293 cpu_est_0_ 3 -1 7 4 2 3 6 7 -1 -1 3 0 21 - 296 cpu_est_3_ 3 -1 6 3 2 3 6 -1 -1 4 0 21 - 294 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 - 298 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 - 295 cpu_est_2_ 3 -1 3 3 2 3 6 -1 -1 1 1 21 - 301 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 - 299 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 - 335 SM_AMIGA_2_ 3 -1 2 2 2 6 -1 -1 5 0 21 - 343 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 - 336 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 - 333 SM_AMIGA_5_ 3 -1 2 2 1 2 -1 -1 3 0 21 - 327 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21 - 326 SM_AMIGA_4_ 3 -1 1 2 1 2 -1 -1 3 0 21 - 324 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 - 323 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21 - 321 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 306 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 305 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 332 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21 - 322 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 - 320 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21 - 318 CLK_000_D_2_ 3 -1 7 2 6 7 -1 -1 1 0 21 - 314 inst_CLK_OUT_PRE_D 3 -1 0 2 1 6 -1 -1 1 0 21 - 313 inst_CLK_OUT_PRE_50 3 -1 2 2 0 2 -1 -1 1 0 21 - 309 CLK_000_D_3_ 3 -1 7 2 1 5 -1 -1 1 0 21 - 307 inst_VPA_D 3 -1 6 2 2 3 -1 -1 1 0 21 - 300 inst_BGACK_030_INT_D 3 -1 4 2 5 6 -1 -1 1 0 21 - 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 302 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 - 331 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 - 334 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 - 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 328 RST_DLY_0_ 3 -1 3 1 3 -1 -1 4 0 21 - 304 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 - 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 303 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 - 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 342 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 - 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 337 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 330 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21 - 329 RST_DLY_1_ 3 -1 3 1 3 -1 -1 2 1 21 - 319 CLK_000_D_4_ 3 -1 1 1 5 -1 -1 1 0 21 - 317 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21 - 316 IPL_D0_1_ 3 -1 0 1 1 -1 -1 1 0 21 - 315 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21 - 310 inst_DTACK_D0 3 -1 0 1 2 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 2 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 2 66 -1 - 59 A_1_ 1 -1 -1 2 5 6 59 -1 - 55 IPL_1_ 1 -1 -1 2 0 1 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 0 63 -1 - 35 VPA 1 -1 -1 1 6 35 -1 - 29 DTACK 1 -1 -1 1 0 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 6 10 -1 -116 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 79 RW_000 5 339 7 3 0 4 6 79 -1 4 0 21 - 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 - 68 A_0_ 5 345 6 2 1 5 68 -1 3 0 21 - 70 RW 5 344 6 2 5 7 70 -1 2 0 21 - 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 - 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 - 78 SIZE_1_ 5 -1 7 1 5 78 -1 1 0 21 - 69 SIZE_0_ 5 -1 6 1 5 69 -1 1 0 21 - 40 BERR 5 -1 4 1 0 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 338 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 - 82 BGACK_030 5 341 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 - 80 DSACK1 5 342 7 0 80 -1 2 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 340 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 341 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 - 312 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 313 CLK_000_D_0_ 3 -1 6 6 0 2 3 5 6 7 -1 -1 1 0 21 - 309 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 4 5 2 3 4 5 7 -1 -1 1 0 21 - 326 SM_AMIGA_6_ 3 -1 5 4 1 2 5 7 -1 -1 3 0 21 - 300 inst_AS_030_000_SYNC 3 -1 2 3 2 3 5 -1 -1 7 0 21 - 296 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 - 294 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 336 SM_AMIGA_i_7_ 3 -1 5 3 2 5 7 -1 -1 3 1 21 - 327 SM_AMIGA_4_ 3 -1 2 3 0 2 5 -1 -1 3 0 21 - 319 CLK_000_D_2_ 3 -1 7 3 4 6 7 -1 -1 1 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 3 1 2 6 -1 -1 1 0 21 - 293 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 - 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 - 335 SM_AMIGA_2_ 3 -1 0 2 0 6 -1 -1 5 0 21 - 329 RST_DLY_0_ 3 -1 6 2 2 6 -1 -1 4 0 21 - 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 328 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21 - 325 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 324 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 322 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 295 cpu_est_0_ 3 -1 0 2 0 3 -1 -1 3 0 21 - 331 RST_DLY_2_ 3 -1 2 2 2 6 -1 -1 2 0 21 - 330 RST_DLY_1_ 3 -1 2 2 2 6 -1 -1 2 1 21 - 323 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 - 321 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21 - 297 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 - 315 inst_CLK_OUT_PRE_D 3 -1 5 2 1 6 -1 -1 1 0 21 - 314 inst_CLK_OUT_PRE_50 3 -1 3 2 3 5 -1 -1 1 0 21 - 310 CLK_000_D_3_ 3 -1 4 2 5 6 -1 -1 1 0 21 - 308 inst_VPA_D 3 -1 3 2 0 3 -1 -1 1 0 21 - 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 - 332 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 - 334 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 - 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 333 SM_AMIGA_5_ 3 -1 2 1 2 -1 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 - 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 342 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 - 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 337 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 320 CLK_000_D_4_ 3 -1 6 1 5 -1 -1 1 0 21 - 318 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21 - 317 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 316 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 - 311 inst_DTACK_D0 3 -1 3 1 0 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 3 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 0 63 -1 - 59 A_1_ 1 -1 -1 1 1 59 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 3 35 -1 - 29 DTACK 1 -1 -1 1 3 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 6 10 -1 -116 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21 - 79 RW_000 5 338 7 3 2 4 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 3 2 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 2 6 7 30 -1 1 0 21 - 68 A_0_ 5 345 6 2 2 6 68 -1 3 0 21 - 70 RW 5 344 6 2 3 7 70 -1 2 0 21 - 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 - 78 SIZE_1_ 5 336 7 1 2 78 -1 3 0 21 - 69 SIZE_0_ 5 341 6 1 2 69 -1 3 0 21 - 40 BERR 5 -1 4 1 0 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 337 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 - 82 BGACK_030 5 340 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 - 80 DSACK1 5 342 7 0 80 -1 2 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 339 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 340 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 - 310 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 311 CLK_000_D_0_ 3 -1 6 6 0 1 2 3 5 7 -1 -1 1 0 21 - 307 CLK_000_D_1_ 3 -1 7 6 0 1 2 3 5 7 -1 -1 1 0 21 - 324 SM_AMIGA_6_ 3 -1 5 5 2 3 5 6 7 -1 -1 3 0 21 - 300 inst_AS_030_000_SYNC 3 -1 7 4 1 3 5 7 -1 -1 7 0 21 - 317 CLK_000_D_2_ 3 -1 7 4 0 3 5 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 4 4 3 4 5 7 -1 -1 1 0 21 - 296 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 - 294 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 334 SM_AMIGA_i_7_ 3 -1 1 3 1 5 7 -1 -1 3 1 21 - 326 SM_AMIGA_0_ 3 -1 5 3 1 5 7 -1 -1 3 0 21 - 325 SM_AMIGA_4_ 3 -1 1 3 0 1 3 -1 -1 3 0 21 - 320 SM_AMIGA_1_ 3 -1 0 3 0 5 7 -1 -1 3 0 21 - 295 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 - 303 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 - 302 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21 - 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 331 SM_AMIGA_5_ 3 -1 3 2 1 3 -1 -1 3 0 21 - 323 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 - 293 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21 - 321 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21 - 319 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 297 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 - 318 CLK_000_D_4_ 3 -1 1 2 1 5 -1 -1 1 0 21 - 313 inst_CLK_OUT_PRE_D 3 -1 6 2 1 6 -1 -1 1 0 21 - 312 inst_CLK_OUT_PRE_50 3 -1 5 2 5 6 -1 -1 1 0 21 - 308 CLK_000_D_3_ 3 -1 3 2 1 5 -1 -1 1 0 21 - 306 inst_VPA_D 3 -1 0 2 0 3 -1 -1 1 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 2 6 7 -1 -1 1 0 21 - 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 337 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 330 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21 - 333 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 5 0 21 - 332 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 338 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 327 RST_DLY_0_ 3 -1 0 1 0 -1 -1 4 0 21 - 305 CYCLE_DMA_1_ 3 -1 2 1 2 -1 -1 4 0 21 - 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 341 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 336 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 322 inst_DS_000_ENABLE 3 -1 3 1 3 -1 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 2 1 2 -1 -1 3 0 21 - 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 342 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 - 339 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 335 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 329 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21 - 328 RST_DLY_1_ 3 -1 0 1 0 -1 -1 2 1 21 - 316 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 - 315 IPL_D0_1_ 3 -1 4 1 1 -1 -1 1 0 21 - 314 IPL_D0_0_ 3 -1 5 1 1 -1 -1 1 0 21 - 309 inst_DTACK_D0 3 -1 1 1 0 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 2 4 7 94 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 5 66 -1 - 58 A_DECODE_17_ 1 -1 -1 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 2 4 7 56 -1 - 55 IPL_1_ 1 -1 -1 2 1 4 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 2 63 -1 - 59 A_1_ 1 -1 -1 1 6 59 -1 - 35 VPA 1 -1 -1 1 0 35 -1 - 29 DTACK 1 -1 -1 1 1 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 6 10 -1 -117 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 41 AS_000 5 -1 4 4 0 1 4 7 41 -1 1 0 21 - 79 RW_000 5 339 7 3 0 4 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 - 70 RW 5 345 6 2 2 7 70 -1 2 0 21 - 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 - 78 SIZE_1_ 5 337 7 1 5 78 -1 3 0 21 - 69 SIZE_0_ 5 342 6 1 5 69 -1 3 0 21 - 68 A_0_ 5 346 6 1 5 68 -1 3 0 21 - 40 BERR 5 -1 4 1 0 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 338 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 348 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 347 1 0 6 -1 10 0 21 - 82 BGACK_030 5 341 7 0 82 -1 3 0 21 - 34 VMA 5 344 3 0 34 -1 3 0 21 - 80 DSACK1 5 343 7 0 80 -1 2 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 340 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 341 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 310 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 311 CLK_000_D_0_ 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 1 0 21 - 307 CLK_000_D_1_ 3 -1 4 6 0 1 2 3 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 7 6 1 2 3 4 5 7 -1 -1 1 0 21 - 325 SM_AMIGA_6_ 3 -1 2 4 1 2 5 7 -1 -1 3 0 21 - 300 inst_AS_030_000_SYNC 3 -1 5 3 2 3 5 -1 -1 7 0 21 - 296 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 - 294 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 335 SM_AMIGA_i_7_ 3 -1 2 3 2 5 7 -1 -1 3 1 21 - 327 SM_AMIGA_0_ 3 -1 6 3 2 6 7 -1 -1 3 0 21 - 326 SM_AMIGA_4_ 3 -1 1 3 0 1 2 -1 -1 3 0 21 - 321 SM_AMIGA_1_ 3 -1 2 3 2 6 7 -1 -1 3 0 21 - 317 CLK_000_D_2_ 3 -1 0 3 2 6 7 -1 -1 1 0 21 - 301 inst_BGACK_030_INT_D 3 -1 7 3 5 6 7 -1 -1 1 0 21 - 295 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 1 1 21 - 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 - 334 SM_AMIGA_2_ 3 -1 0 2 0 2 -1 -1 5 0 21 - 344 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 324 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 323 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 1 2 0 1 -1 -1 3 0 21 - 293 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21 - 322 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 - 320 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 2 3 5 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21 - 297 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21 - 313 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 - 306 inst_VPA_D 3 -1 6 2 0 3 -1 -1 1 0 21 - 348 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 347 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 - 331 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 - 333 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 328 RST_DLY_0_ 3 -1 3 1 3 -1 -1 4 0 21 - 305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 - 346 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 342 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 332 SM_AMIGA_5_ 3 -1 1 1 1 -1 -1 3 0 21 - 345 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 343 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 - 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 330 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21 - 329 RST_DLY_1_ 3 -1 3 1 3 -1 -1 2 1 21 - 319 CLK_000_D_5_ 3 -1 2 1 2 -1 -1 1 0 21 - 318 CLK_000_D_3_ 3 -1 7 1 3 -1 -1 1 0 21 - 316 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 - 315 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 - 314 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21 - 312 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 - 309 inst_DTACK_D0 3 -1 6 1 0 -1 -1 1 0 21 - 308 CLK_000_D_4_ 3 -1 3 1 2 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 2 66 -1 - 55 IPL_1_ 1 -1 -1 2 1 6 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 0 63 -1 - 59 A_1_ 1 -1 -1 1 5 59 -1 - 35 VPA 1 -1 -1 1 6 35 -1 - 29 DTACK 1 -1 -1 1 6 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 6 10 -1 -115 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21 - 79 RW_000 5 337 7 3 2 4 6 79 -1 4 0 21 - 81 AS_030 5 -1 7 3 4 6 7 81 -1 1 0 21 - 31 UDS_000 5 -1 3 3 2 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 2 6 7 30 -1 1 0 21 - 70 RW 5 343 6 2 0 7 70 -1 2 0 21 - 78 SIZE_1_ 5 335 7 1 5 78 -1 3 0 21 - 69 SIZE_0_ 5 340 6 1 5 69 -1 3 0 21 - 68 A_0_ 5 344 6 1 5 68 -1 3 0 21 - 40 BERR 5 -1 4 1 5 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 336 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 346 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 345 1 0 6 -1 10 0 21 - 82 BGACK_030 5 339 7 0 82 -1 3 0 21 - 34 VMA 5 342 3 0 34 -1 3 0 21 - 80 DSACK1 5 341 7 0 80 -1 2 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 338 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 339 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 - 310 inst_RESET_OUT 3 -1 2 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 311 CLK_000_D_0_ 3 -1 4 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 307 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 323 SM_AMIGA_6_ 3 -1 0 4 0 3 5 7 -1 -1 3 0 21 - 308 CLK_000_D_2_ 3 -1 7 4 0 1 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 6 4 0 3 4 7 -1 -1 1 0 21 - 326 RST_DLY_0_ 3 -1 0 3 0 1 2 -1 -1 4 0 21 - 295 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 - 293 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 - 325 SM_AMIGA_0_ 3 -1 6 3 0 6 7 -1 -1 3 0 21 - 324 SM_AMIGA_4_ 3 -1 2 3 0 2 5 -1 -1 3 0 21 - 319 SM_AMIGA_1_ 3 -1 1 3 1 6 7 -1 -1 3 0 21 - 296 cpu_est_0_ 3 -1 6 3 3 5 6 -1 -1 3 0 21 - 328 RST_DLY_2_ 3 -1 2 3 0 1 2 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 1 3 0 1 2 -1 -1 2 1 21 - 301 inst_BGACK_030_INT_D 3 -1 7 3 0 6 7 -1 -1 1 0 21 - 294 cpu_est_2_ 3 -1 6 3 3 5 6 -1 -1 1 1 21 - 303 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 - 302 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21 - 300 inst_AS_030_000_SYNC 3 -1 0 2 0 3 -1 -1 7 0 21 - 332 SM_AMIGA_2_ 3 -1 5 2 1 5 -1 -1 5 0 21 - 305 CYCLE_DMA_1_ 3 -1 0 2 0 2 -1 -1 4 0 21 - 342 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 - 333 SM_AMIGA_i_7_ 3 -1 0 2 0 7 -1 -1 3 1 21 - 330 SM_AMIGA_5_ 3 -1 3 2 2 3 -1 -1 3 0 21 - 322 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 321 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 0 2 0 2 -1 -1 3 0 21 - 320 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 - 318 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 297 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21 - 313 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 - 306 inst_VPA_D 3 -1 1 2 3 5 -1 -1 1 0 21 - 346 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 345 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 336 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 329 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21 - 331 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 - 337 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 344 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 340 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 335 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 343 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 341 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 - 338 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 334 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 317 CLK_000_D_3_ 3 -1 7 1 0 -1 -1 1 0 21 - 316 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 - 315 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21 - 314 IPL_D0_0_ 3 -1 5 1 1 -1 -1 1 0 21 - 312 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 - 309 inst_DTACK_D0 3 -1 3 1 5 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 0 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 0 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 0 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 0 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 0 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 0 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 66 IPL_0_ 1 -1 -1 2 1 5 66 -1 - 55 IPL_1_ 1 -1 -1 2 1 3 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 67 IPL_2_ 1 -1 -1 1 1 67 -1 - 63 CLK_030 1 -1 -1 1 2 63 -1 - 59 A_1_ 1 -1 -1 1 6 59 -1 - 35 VPA 1 -1 -1 1 1 35 -1 - 29 DTACK 1 -1 -1 1 3 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 4 10 -1 -116 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21 - 79 RW_000 5 338 7 3 2 4 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 3 2 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 2 6 7 30 -1 1 0 21 - 68 A_0_ 5 345 6 2 2 6 68 -1 3 0 21 - 70 RW 5 344 6 2 3 7 70 -1 2 0 21 - 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 - 78 SIZE_1_ 5 336 7 1 2 78 -1 3 0 21 - 69 SIZE_0_ 5 341 6 1 2 69 -1 3 0 21 - 40 BERR 5 -1 4 1 0 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 337 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 - 82 BGACK_030 5 340 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 - 80 DSACK1 5 342 7 0 80 -1 2 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 339 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 340 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 - 310 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 311 CLK_000_D_0_ 3 -1 6 6 0 1 2 3 5 7 -1 -1 1 0 21 - 307 CLK_000_D_1_ 3 -1 7 6 0 1 2 3 5 7 -1 -1 1 0 21 - 324 SM_AMIGA_6_ 3 -1 5 5 2 3 5 6 7 -1 -1 3 0 21 - 300 inst_AS_030_000_SYNC 3 -1 7 4 1 3 5 7 -1 -1 7 0 21 - 317 CLK_000_D_2_ 3 -1 7 4 0 3 5 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 4 4 3 4 5 7 -1 -1 1 0 21 - 296 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 - 294 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 334 SM_AMIGA_i_7_ 3 -1 1 3 1 5 7 -1 -1 3 1 21 - 326 SM_AMIGA_0_ 3 -1 5 3 1 5 7 -1 -1 3 0 21 - 325 SM_AMIGA_4_ 3 -1 1 3 0 1 3 -1 -1 3 0 21 - 320 SM_AMIGA_1_ 3 -1 0 3 0 5 7 -1 -1 3 0 21 - 295 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 - 303 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 - 302 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21 - 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 331 SM_AMIGA_5_ 3 -1 3 2 1 3 -1 -1 3 0 21 - 323 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 - 293 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21 - 321 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21 - 319 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 297 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 - 318 CLK_000_D_4_ 3 -1 1 2 1 5 -1 -1 1 0 21 - 313 inst_CLK_OUT_PRE_D 3 -1 6 2 1 6 -1 -1 1 0 21 - 312 inst_CLK_OUT_PRE_50 3 -1 5 2 5 6 -1 -1 1 0 21 - 308 CLK_000_D_3_ 3 -1 3 2 1 5 -1 -1 1 0 21 - 306 inst_VPA_D 3 -1 0 2 0 3 -1 -1 1 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 2 6 7 -1 -1 1 0 21 - 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 337 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 330 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21 - 333 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 5 0 21 - 332 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 338 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 327 RST_DLY_0_ 3 -1 0 1 0 -1 -1 4 0 21 - 305 CYCLE_DMA_1_ 3 -1 2 1 2 -1 -1 4 0 21 - 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 341 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 336 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 322 inst_DS_000_ENABLE 3 -1 3 1 3 -1 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 2 1 2 -1 -1 3 0 21 - 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 342 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 - 339 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 335 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 329 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21 - 328 RST_DLY_1_ 3 -1 0 1 0 -1 -1 2 1 21 - 316 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 - 315 IPL_D0_1_ 3 -1 4 1 1 -1 -1 1 0 21 - 314 IPL_D0_0_ 3 -1 5 1 1 -1 -1 1 0 21 - 309 inst_DTACK_D0 3 -1 1 1 0 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 2 4 7 94 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 5 66 -1 - 58 A_DECODE_17_ 1 -1 -1 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 2 4 7 56 -1 - 55 IPL_1_ 1 -1 -1 2 1 4 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 2 63 -1 - 59 A_1_ 1 -1 -1 1 6 59 -1 - 35 VPA 1 -1 -1 1 0 35 -1 - 29 DTACK 1 -1 -1 1 1 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 6 10 -1 -116 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 79 RW_000 5 339 7 3 0 4 6 79 -1 4 0 21 - 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 - 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 - 70 RW 5 344 6 2 0 7 70 -1 2 0 21 - 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 - 78 SIZE_1_ 5 337 7 1 5 78 -1 3 0 21 - 69 SIZE_0_ 5 342 6 1 5 69 -1 3 0 21 - 68 A_0_ 5 345 6 1 5 68 -1 3 0 21 + 31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21 + 78 SIZE_1_ 5 337 7 1 1 78 -1 3 0 21 + 69 SIZE_0_ 5 342 6 1 1 69 -1 3 0 21 + 68 A_0_ 5 345 6 1 1 68 -1 3 0 21 40 BERR 5 -1 4 1 2 40 -1 1 0 21 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 @@ -2946,60 +43,303 @@ 9 CLK_EXP 0 1 0 9 -1 1 0 21 2 RESET 0 1 0 2 -1 1 0 21 341 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 310 inst_RESET_OUT 3 -1 1 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 311 CLK_000_D_0_ 3 -1 6 6 0 1 2 3 5 7 -1 -1 1 0 21 - 307 CLK_000_D_1_ 3 -1 7 6 0 1 2 3 5 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 4 5 0 2 3 4 5 -1 -1 1 0 21 - 324 SM_AMIGA_6_ 3 -1 1 4 0 1 5 7 -1 -1 3 0 21 - 300 inst_AS_030_000_SYNC 3 -1 5 3 1 3 5 -1 -1 7 0 21 - 296 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 - 294 cpu_est_1_ 3 -1 2 3 2 3 6 -1 -1 4 0 21 - 335 SM_AMIGA_i_7_ 3 -1 1 3 1 5 7 -1 -1 3 1 21 - 326 SM_AMIGA_0_ 3 -1 0 3 0 1 7 -1 -1 3 0 21 - 325 SM_AMIGA_4_ 3 -1 5 3 0 2 5 -1 -1 3 0 21 - 317 CLK_000_D_2_ 3 -1 7 3 0 2 6 -1 -1 1 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 3 5 6 7 -1 -1 1 0 21 - 295 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 1 1 21 - 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 - 334 SM_AMIGA_2_ 3 -1 2 2 0 2 -1 -1 5 0 21 - 327 RST_DLY_0_ 3 -1 3 2 1 3 -1 -1 4 0 21 + 309 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 311 CLK_000_D_0_ 3 -1 1 6 0 2 3 5 6 7 -1 -1 1 0 21 + 310 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 + 323 SM_AMIGA_6_ 3 -1 5 4 1 3 5 7 -1 -1 3 0 21 + 307 CLK_000_D_3_ 3 -1 3 4 0 2 3 5 -1 -1 1 0 21 + 300 inst_BGACK_030_INT_D 3 -1 7 4 0 5 6 7 -1 -1 1 0 21 + 325 SM_AMIGA_0_ 3 -1 0 3 0 5 7 -1 -1 4 0 21 + 295 cpu_est_1_ 3 -1 6 3 2 3 6 -1 -1 4 0 21 + 293 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 + 294 cpu_est_0_ 3 -1 6 3 2 3 6 -1 -1 3 0 21 + 306 CLK_000_D_2_ 3 -1 7 3 0 2 3 -1 -1 1 0 21 + 298 inst_AS_030_D0 3 -1 7 3 3 4 5 -1 -1 1 0 21 + 296 cpu_est_2_ 3 -1 3 3 2 3 6 -1 -1 1 1 21 + 302 inst_DS_000_DMA 3 -1 6 2 0 6 -1 -1 9 0 21 + 301 inst_AS_000_DMA 3 -1 6 2 6 7 -1 -1 7 0 21 + 299 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 + 326 RST_DLY_0_ 3 -1 2 2 0 2 -1 -1 4 0 21 + 319 SM_AMIGA_1_ 3 -1 2 2 0 2 -1 -1 4 0 21 343 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 - 332 SM_AMIGA_5_ 3 -1 1 2 1 5 -1 -1 3 0 21 - 323 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 322 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21 - 320 SM_AMIGA_1_ 3 -1 0 2 0 2 -1 -1 3 0 21 - 293 cpu_est_0_ 3 -1 3 2 2 3 -1 -1 3 0 21 - 330 inst_DSACK1_INT 3 -1 2 2 2 7 -1 -1 2 0 21 - 329 RST_DLY_2_ 3 -1 3 2 1 3 -1 -1 2 0 21 - 328 RST_DLY_1_ 3 -1 3 2 1 3 -1 -1 2 1 21 - 321 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 - 319 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 297 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21 - 313 inst_CLK_OUT_PRE_D 3 -1 5 2 1 6 -1 -1 1 0 21 - 312 inst_CLK_OUT_PRE_50 3 -1 6 2 5 6 -1 -1 1 0 21 - 308 CLK_000_D_3_ 3 -1 6 2 1 7 -1 -1 1 0 21 - 306 inst_VPA_D 3 -1 3 2 2 3 -1 -1 1 0 21 + 335 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 + 332 SM_AMIGA_5_ 3 -1 3 2 2 3 -1 -1 3 0 21 + 324 SM_AMIGA_4_ 3 -1 2 2 2 5 -1 -1 3 0 21 + 322 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 + 321 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 + 303 CYCLE_DMA_0_ 3 -1 0 2 0 6 -1 -1 3 0 21 + 331 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 + 330 inst_DSACK1_INT 3 -1 0 2 0 7 -1 -1 2 0 21 + 328 RST_DLY_2_ 3 -1 0 2 0 2 -1 -1 2 0 21 + 327 RST_DLY_1_ 3 -1 0 2 0 2 -1 -1 2 1 21 + 320 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 318 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 2 0 3 -1 -1 2 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 + 305 inst_VPA_D 3 -1 0 2 2 3 -1 -1 1 0 21 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 - 331 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 329 inst_CLK_030_H 3 -1 6 1 6 -1 -1 8 0 21 + 334 SM_AMIGA_2_ 3 -1 2 1 2 -1 -1 5 0 21 333 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 + 304 CYCLE_DMA_1_ 3 -1 6 1 6 -1 -1 4 0 21 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 342 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 318 CLK_000_D_4_ 3 -1 7 1 1 -1 -1 1 0 21 - 316 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21 - 315 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 - 314 IPL_D0_0_ 3 -1 4 1 1 -1 -1 1 0 21 - 309 inst_DTACK_D0 3 -1 6 1 2 -1 -1 1 0 21 + 317 CLK_000_D_4_ 3 -1 3 1 5 -1 -1 1 0 21 + 316 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 + 315 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 314 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 + 312 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 308 inst_DTACK_D0 3 -1 2 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 63 CLK_030 1 -1 -1 1 6 63 -1 + 59 A_1_ 1 -1 -1 1 0 59 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 29 DTACK 1 -1 -1 1 2 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 1 10 -1 +116 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 -1 7 4 2 4 5 7 81 -1 1 0 21 + 41 AS_000 5 -1 4 4 0 3 4 7 41 -1 1 0 21 + 79 RW_000 5 339 7 3 0 4 6 79 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 68 A_0_ 5 345 6 2 3 5 68 -1 3 0 21 + 70 RW 5 344 6 2 5 7 70 -1 2 0 21 + 40 BERR 5 -1 4 2 0 5 40 -1 1 0 21 + 78 SIZE_1_ 5 337 7 1 5 78 -1 3 0 21 + 69 SIZE_0_ 5 340 6 1 5 69 -1 3 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 338 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 + 82 BGACK_030 5 342 7 0 82 -1 3 0 21 + 34 VMA 5 343 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 341 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 80 DSACK1 0 7 0 80 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 342 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 308 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 310 CLK_000_D_0_ 3 -1 3 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 309 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 322 SM_AMIGA_6_ 3 -1 2 5 2 3 5 6 7 -1 -1 3 0 21 + 295 cpu_est_1_ 3 -1 0 4 0 3 5 6 -1 -1 4 0 21 + 293 cpu_est_3_ 3 -1 0 4 0 3 5 6 -1 -1 4 0 21 + 300 inst_BGACK_030_INT_D 3 -1 6 4 1 2 6 7 -1 -1 1 0 21 + 296 cpu_est_2_ 3 -1 3 4 0 3 5 6 -1 -1 1 1 21 + 343 RN_VMA 3 34 3 3 0 3 5 34 -1 3 0 21 + 325 SM_AMIGA_0_ 3 -1 6 3 2 6 7 -1 -1 3 0 21 + 294 cpu_est_0_ 3 -1 0 3 0 3 5 -1 -1 3 0 21 + 305 inst_VPA_D 3 -1 2 3 0 3 5 -1 -1 1 0 21 + 298 inst_AS_030_D0 3 -1 4 3 2 3 4 -1 -1 1 0 21 + 301 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 299 inst_AS_030_000_SYNC 3 -1 2 2 2 3 -1 -1 7 0 21 + 334 SM_AMIGA_2_ 3 -1 0 2 0 6 -1 -1 5 0 21 + 333 SM_AMIGA_3_ 3 -1 5 2 0 5 -1 -1 5 0 21 + 326 RST_DLY_0_ 3 -1 6 2 1 6 -1 -1 4 0 21 + 335 SM_AMIGA_i_7_ 3 -1 2 2 2 7 -1 -1 3 1 21 + 332 SM_AMIGA_5_ 3 -1 6 2 5 6 -1 -1 3 0 21 + 324 SM_AMIGA_1_ 3 -1 6 2 5 6 -1 -1 3 0 21 + 321 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 + 320 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 + 303 CYCLE_DMA_0_ 3 -1 3 2 0 3 -1 -1 3 0 21 + 331 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 330 inst_DSACK1_INT 3 -1 5 2 5 7 -1 -1 2 0 21 + 328 RST_DLY_2_ 3 -1 6 2 1 6 -1 -1 2 0 21 + 327 RST_DLY_1_ 3 -1 1 2 1 6 -1 -1 2 1 21 + 318 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21 + 312 inst_CLK_OUT_PRE_D 3 -1 1 2 1 6 -1 -1 1 0 21 + 311 inst_CLK_OUT_PRE_50 3 -1 3 2 1 3 -1 -1 1 0 21 + 307 inst_DTACK_D0 3 -1 2 2 0 5 -1 -1 1 0 21 + 306 CLK_000_D_3_ 3 -1 4 2 2 7 -1 -1 1 0 21 + 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 302 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 329 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 304 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 + 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 340 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 + 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 + 323 SM_AMIGA_4_ 3 -1 5 1 5 -1 -1 3 0 21 + 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 341 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 319 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21 + 317 CLK_000_D_4_ 3 -1 7 1 2 -1 -1 1 0 21 + 316 CLK_000_D_2_ 3 -1 7 1 4 -1 -1 1 0 21 + 315 IPL_D0_2_ 3 -1 7 1 1 -1 -1 1 0 21 + 314 IPL_D0_1_ 3 -1 0 1 1 -1 -1 1 0 21 + 313 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 + 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 7 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 + 55 IPL_1_ 1 -1 -1 2 0 1 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 63 CLK_030 1 -1 -1 1 0 63 -1 + 59 A_1_ 1 -1 -1 1 1 59 -1 + 35 VPA 1 -1 -1 1 2 35 -1 + 29 DTACK 1 -1 -1 1 2 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 +115 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 -1 7 4 2 4 5 7 81 -1 1 0 21 + 41 AS_000 5 -1 4 4 0 1 4 7 41 -1 1 0 21 + 79 RW_000 5 338 7 3 0 4 6 79 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 68 A_0_ 5 344 6 2 2 6 68 -1 3 0 21 + 70 RW 5 343 6 2 2 7 70 -1 2 0 21 + 78 SIZE_1_ 5 336 7 1 2 78 -1 3 0 21 + 69 SIZE_0_ 5 339 6 1 2 69 -1 3 0 21 + 40 BERR 5 -1 4 1 0 40 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 337 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 346 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 345 1 0 6 -1 10 0 21 + 82 BGACK_030 5 341 7 0 82 -1 3 0 21 + 34 VMA 5 342 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 340 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 80 DSACK1 0 7 0 80 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 341 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 308 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 310 CLK_000_D_0_ 3 -1 6 6 0 1 2 3 5 7 -1 -1 1 0 21 + 309 CLK_000_D_1_ 3 -1 7 6 0 1 2 3 5 7 -1 -1 1 0 21 + 321 SM_AMIGA_6_ 3 -1 5 5 1 2 5 6 7 -1 -1 3 0 21 + 300 inst_BGACK_030_INT_D 3 -1 4 4 2 5 6 7 -1 -1 1 0 21 + 295 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 + 293 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 + 298 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 + 296 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 1 1 21 + 301 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 299 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 + 333 SM_AMIGA_2_ 3 -1 0 2 0 2 -1 -1 5 0 21 + 325 RST_DLY_0_ 3 -1 3 2 1 3 -1 -1 4 0 21 + 342 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 + 334 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 + 331 SM_AMIGA_5_ 3 -1 1 2 1 2 -1 -1 3 0 21 + 324 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 323 SM_AMIGA_1_ 3 -1 2 2 2 5 -1 -1 3 0 21 + 322 SM_AMIGA_4_ 3 -1 2 2 0 2 -1 -1 3 0 21 + 320 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 + 319 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 + 303 CYCLE_DMA_0_ 3 -1 1 2 0 1 -1 -1 3 0 21 + 294 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21 + 330 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 329 inst_DSACK1_INT 3 -1 5 2 5 7 -1 -1 2 0 21 + 327 RST_DLY_2_ 3 -1 1 2 1 3 -1 -1 2 0 21 + 326 RST_DLY_1_ 3 -1 3 2 1 3 -1 -1 2 1 21 + 318 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21 + 317 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 + 312 inst_CLK_OUT_PRE_D 3 -1 7 2 1 6 -1 -1 1 0 21 + 306 CLK_000_D_2_ 3 -1 7 2 1 5 -1 -1 1 0 21 + 305 inst_VPA_D 3 -1 6 2 0 3 -1 -1 1 0 21 + 346 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 345 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 337 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 302 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 328 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 332 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 + 338 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 304 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 + 344 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 339 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 + 336 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 + 343 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 335 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 316 CLK_000_D_3_ 3 -1 1 1 5 -1 -1 1 0 21 + 315 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21 + 314 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 + 313 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 + 311 inst_CLK_OUT_PRE_50 3 -1 7 1 7 -1 -1 1 0 21 + 307 inst_DTACK_D0 3 -1 6 1 0 -1 -1 1 0 21 60 CLK_OSZI 9 -1 0 60 -1 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 @@ -3010,8 +350,9 @@ 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 2 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 4 66 -1 + 67 IPL_2_ 1 -1 -1 2 1 3 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 + 59 A_1_ 1 -1 -1 2 2 6 59 -1 55 IPL_1_ 1 -1 -1 2 1 6 55 -1 27 BGACK_000 1 -1 -1 2 4 7 27 -1 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 @@ -3019,8 +360,7 @@ 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 63 CLK_030 1 -1 -1 1 0 63 -1 - 59 A_1_ 1 -1 -1 1 6 59 -1 - 35 VPA 1 -1 -1 1 3 35 -1 + 35 VPA 1 -1 -1 1 6 35 -1 29 DTACK 1 -1 -1 1 6 29 -1 20 BG_030 1 -1 -1 1 3 20 -1 10 CLK_000 1 -1 -1 1 6 10 -1 @@ -3152,16 +492,16 @@ "num name type sig num out pin node cnt PT type" "--- ---- ---- ---- --- --- --- ---- --- --- ----" - 81 AS_030 5 -1 7 4 0 4 5 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 4 0 4 6 7 41 -1 1 0 21 - 79 RW_000 5 339 7 2 4 6 79 -1 4 0 21 - 70 RW 5 344 6 2 5 7 70 -1 2 0 21 - 31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21 - 78 SIZE_1_ 5 337 7 1 1 78 -1 3 0 21 - 69 SIZE_0_ 5 342 6 1 1 69 -1 3 0 21 - 68 A_0_ 5 345 6 1 1 68 -1 3 0 21 - 40 BERR 5 -1 4 1 2 40 -1 1 0 21 + 81 AS_030 5 -1 7 5 2 4 5 6 7 81 -1 1 0 21 + 41 AS_000 5 -1 4 5 0 1 4 6 7 41 -1 1 0 21 + 79 RW_000 5 339 7 3 1 4 6 79 -1 4 0 21 + 31 UDS_000 5 -1 3 3 1 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 1 6 7 30 -1 1 0 21 + 68 A_0_ 5 345 6 2 2 3 68 -1 3 0 21 + 70 RW 5 344 6 2 2 7 70 -1 2 0 21 + 78 SIZE_1_ 5 337 7 1 2 78 -1 3 0 21 + 69 SIZE_0_ 5 340 6 1 2 69 -1 3 0 21 + 40 BERR 5 -1 4 1 0 40 -1 1 0 21 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 @@ -3173,130 +513,8 @@ 8 IPL_030_2_ 5 338 1 0 8 -1 10 0 21 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 - 82 BGACK_030 5 341 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 340 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 341 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 309 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 311 CLK_000_D_0_ 3 -1 1 6 0 2 3 5 6 7 -1 -1 1 0 21 - 310 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 - 323 SM_AMIGA_6_ 3 -1 5 4 1 3 5 7 -1 -1 3 0 21 - 307 CLK_000_D_3_ 3 -1 3 4 0 2 3 5 -1 -1 1 0 21 - 300 inst_BGACK_030_INT_D 3 -1 7 4 0 5 6 7 -1 -1 1 0 21 - 325 SM_AMIGA_0_ 3 -1 0 3 0 5 7 -1 -1 4 0 21 - 295 cpu_est_1_ 3 -1 6 3 2 3 6 -1 -1 4 0 21 - 293 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 - 294 cpu_est_0_ 3 -1 6 3 2 3 6 -1 -1 3 0 21 - 306 CLK_000_D_2_ 3 -1 7 3 0 2 3 -1 -1 1 0 21 - 298 inst_AS_030_D0 3 -1 7 3 3 4 5 -1 -1 1 0 21 - 296 cpu_est_2_ 3 -1 3 3 2 3 6 -1 -1 1 1 21 - 302 inst_DS_000_DMA 3 -1 6 2 0 6 -1 -1 9 0 21 - 301 inst_AS_000_DMA 3 -1 6 2 6 7 -1 -1 7 0 21 - 299 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 - 326 RST_DLY_0_ 3 -1 2 2 0 2 -1 -1 4 0 21 - 319 SM_AMIGA_1_ 3 -1 2 2 0 2 -1 -1 4 0 21 - 343 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 - 335 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 - 332 SM_AMIGA_5_ 3 -1 3 2 2 3 -1 -1 3 0 21 - 324 SM_AMIGA_4_ 3 -1 2 2 2 5 -1 -1 3 0 21 - 322 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 - 321 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 303 CYCLE_DMA_0_ 3 -1 0 2 0 6 -1 -1 3 0 21 - 331 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 - 330 inst_DSACK1_INT 3 -1 0 2 0 7 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 0 2 0 2 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 0 2 0 2 -1 -1 2 1 21 - 320 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 - 318 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 2 0 3 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21 - 313 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 - 305 inst_VPA_D 3 -1 0 2 2 3 -1 -1 1 0 21 - 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 329 inst_CLK_030_H 3 -1 6 1 6 -1 -1 8 0 21 - 334 SM_AMIGA_2_ 3 -1 2 1 2 -1 -1 5 0 21 - 333 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 - 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 304 CYCLE_DMA_1_ 3 -1 6 1 6 -1 -1 4 0 21 - 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 342 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 317 CLK_000_D_4_ 3 -1 3 1 5 -1 -1 1 0 21 - 316 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 - 315 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 314 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 - 312 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 - 308 inst_DTACK_D0 3 -1 2 1 2 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 6 63 -1 - 59 A_1_ 1 -1 -1 1 0 59 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 0 35 -1 - 29 DTACK 1 -1 -1 1 2 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 1 10 -1 -117 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 5 1 2 4 5 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 5 0 2 3 4 7 41 -1 1 0 21 - 79 RW_000 5 340 7 3 2 4 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 3 2 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 2 6 7 30 -1 1 0 21 - 68 A_0_ 5 346 6 2 2 5 68 -1 3 0 21 - 70 RW 5 345 6 2 1 7 70 -1 2 0 21 - 78 SIZE_1_ 5 338 7 1 2 78 -1 3 0 21 - 69 SIZE_0_ 5 343 6 1 2 69 -1 3 0 21 - 40 BERR 5 -1 4 1 0 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 339 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 348 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 347 1 0 6 -1 10 0 21 82 BGACK_030 5 342 7 0 82 -1 3 0 21 - 34 VMA 5 344 3 0 34 -1 3 0 21 + 34 VMA 5 343 3 0 34 -1 3 0 21 65 E 0 6 0 65 -1 2 0 21 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 @@ -3312,64 +530,63 @@ 9 CLK_EXP 0 1 0 9 -1 1 0 21 2 RESET 0 1 0 2 -1 1 0 21 342 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 309 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 311 CLK_000_D_0_ 3 -1 3 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 310 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 324 SM_AMIGA_6_ 3 -1 5 4 1 2 5 7 -1 -1 3 0 21 - 326 SM_AMIGA_0_ 3 -1 0 3 0 5 7 -1 -1 4 0 21 - 296 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 + 309 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 310 CLK_000_D_0_ 3 -1 1 6 0 2 3 5 6 7 -1 -1 1 0 21 + 306 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 + 323 SM_AMIGA_6_ 3 -1 2 4 2 3 6 7 -1 -1 3 0 21 + 300 inst_BGACK_030_INT_D 3 -1 4 4 2 5 6 7 -1 -1 1 0 21 + 299 inst_AS_030_000_SYNC 3 -1 5 3 2 3 5 -1 -1 7 0 21 + 296 cpu_est_1_ 3 -1 6 3 0 3 6 -1 -1 4 0 21 294 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 300 inst_BGACK_030_INT_D 3 -1 0 3 5 6 7 -1 -1 1 0 21 - 298 inst_AS_030_D0 3 -1 7 3 3 4 5 -1 -1 1 0 21 + 335 SM_AMIGA_i_7_ 3 -1 2 3 2 5 7 -1 -1 3 1 21 + 325 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 + 324 SM_AMIGA_4_ 3 -1 3 3 0 2 3 -1 -1 3 0 21 + 295 cpu_est_0_ 3 -1 6 3 0 3 6 -1 -1 3 0 21 + 298 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 293 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 - 302 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 - 301 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21 - 299 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 - 327 RST_DLY_0_ 3 -1 6 2 1 6 -1 -1 4 0 21 - 320 SM_AMIGA_1_ 3 -1 0 2 0 5 -1 -1 4 0 21 - 304 CYCLE_DMA_1_ 3 -1 3 2 2 3 -1 -1 4 0 21 - 344 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 336 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 - 333 SM_AMIGA_5_ 3 -1 1 2 0 1 -1 -1 3 0 21 - 325 SM_AMIGA_4_ 3 -1 0 2 0 1 -1 -1 3 0 21 - 323 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 - 322 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21 - 303 CYCLE_DMA_0_ 3 -1 3 2 2 3 -1 -1 3 0 21 - 295 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21 - 332 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 - 331 inst_DSACK1_INT 3 -1 5 2 5 7 -1 -1 2 0 21 - 329 RST_DLY_2_ 3 -1 6 2 1 6 -1 -1 2 0 21 - 328 RST_DLY_1_ 3 -1 1 2 1 6 -1 -1 2 1 21 - 321 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 - 319 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 317 CLK_000_D_3_ 3 -1 0 2 0 5 -1 -1 1 0 21 - 313 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 - 307 CLK_000_D_4_ 3 -1 0 2 5 6 -1 -1 1 0 21 - 306 CLK_000_D_2_ 3 -1 7 2 0 5 -1 -1 1 0 21 - 305 inst_VPA_D 3 -1 2 2 0 3 -1 -1 1 0 21 - 348 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 347 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 339 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 330 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21 - 335 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 5 0 21 - 334 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 340 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 346 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 343 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 338 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 345 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 302 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 9 0 21 + 301 inst_AS_000_DMA 3 -1 1 2 1 7 -1 -1 7 0 21 + 334 SM_AMIGA_2_ 3 -1 0 2 0 5 -1 -1 5 0 21 + 304 CYCLE_DMA_1_ 3 -1 6 2 1 6 -1 -1 4 0 21 + 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 + 322 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 + 321 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 + 303 CYCLE_DMA_0_ 3 -1 6 2 1 6 -1 -1 3 0 21 + 331 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21 + 330 inst_DSACK1_INT 3 -1 5 2 5 7 -1 -1 2 0 21 + 318 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 316 CLK_000_D_2_ 3 -1 7 2 0 5 -1 -1 1 0 21 + 312 inst_CLK_OUT_PRE_D 3 -1 3 2 1 6 -1 -1 1 0 21 + 311 inst_CLK_OUT_PRE_50 3 -1 6 2 3 6 -1 -1 1 0 21 + 307 CLK_000_D_3_ 3 -1 0 2 2 5 -1 -1 1 0 21 + 305 inst_VPA_D 3 -1 7 2 0 3 -1 -1 1 0 21 + 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 329 inst_CLK_030_H 3 -1 1 1 1 -1 -1 8 0 21 + 333 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 + 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 326 RST_DLY_0_ 3 -1 0 1 0 -1 -1 4 0 21 + 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 340 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 + 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 + 332 SM_AMIGA_5_ 3 -1 3 1 3 -1 -1 3 0 21 + 319 SM_AMIGA_1_ 3 -1 5 1 5 -1 -1 3 0 21 + 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 341 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 337 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 318 CLK_000_D_5_ 3 -1 6 1 5 -1 -1 1 0 21 - 316 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 - 315 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 314 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21 - 312 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 - 308 inst_DTACK_D0 3 -1 7 1 0 -1 -1 1 0 21 + 336 N_262 3 -1 4 1 4 -1 -1 2 0 21 + 328 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21 + 327 RST_DLY_1_ 3 -1 0 1 0 -1 -1 2 1 21 + 320 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 + 317 CLK_000_D_4_ 3 -1 5 1 2 -1 -1 1 0 21 + 315 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21 + 314 IPL_D0_1_ 3 -1 7 1 1 -1 -1 1 0 21 + 313 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 + 308 inst_DTACK_D0 3 -1 0 1 0 -1 -1 1 0 21 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 @@ -3377,36 +594,36 @@ 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 - 66 IPL_0_ 1 -1 -1 2 0 1 66 -1 + 67 IPL_2_ 1 -1 -1 2 1 2 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 + 59 A_1_ 1 -1 -1 2 2 6 59 -1 + 55 IPL_1_ 1 -1 -1 2 1 7 55 -1 27 BGACK_000 1 -1 -1 2 4 7 27 -1 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 2 63 -1 - 59 A_1_ 1 -1 -1 1 6 59 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 2 35 -1 - 29 DTACK 1 -1 -1 1 7 29 -1 + 63 CLK_030 1 -1 -1 1 1 63 -1 + 35 VPA 1 -1 -1 1 7 35 -1 + 29 DTACK 1 -1 -1 1 0 29 -1 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 3 10 -1 + 10 CLK_000 1 -1 -1 1 1 10 -1 116 "number of signals after reading design file" "sig sig sig pair blk fan PT xor sync" "num name type sig num out pin node cnt PT type" "--- ---- ---- ---- --- --- --- ---- --- --- ----" - 81 AS_030 5 -1 7 4 0 4 5 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 4 0 4 6 7 41 -1 1 0 21 - 79 RW_000 5 339 7 2 4 6 79 -1 4 0 21 - 70 RW 5 344 6 2 5 7 70 -1 2 0 21 - 31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21 - 78 SIZE_1_ 5 337 7 1 1 78 -1 3 0 21 - 69 SIZE_0_ 5 342 6 1 1 69 -1 3 0 21 - 68 A_0_ 5 345 6 1 1 68 -1 3 0 21 - 40 BERR 5 -1 4 1 2 40 -1 1 0 21 + 81 AS_030 5 -1 7 5 0 2 4 5 7 81 -1 1 0 21 + 41 AS_000 5 -1 4 5 0 1 4 5 7 41 -1 1 0 21 + 79 RW_000 5 339 7 3 1 4 6 79 -1 4 0 21 + 31 UDS_000 5 -1 3 3 1 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 1 6 7 30 -1 1 0 21 + 70 RW 5 344 6 2 2 7 70 -1 2 0 21 + 78 SIZE_1_ 5 337 7 1 2 78 -1 3 0 21 + 69 SIZE_0_ 5 342 6 1 2 69 -1 3 0 21 + 68 A_0_ 5 345 6 1 2 68 -1 3 0 21 + 40 BERR 5 -1 4 1 0 40 -1 1 0 21 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 @@ -3435,100 +652,100 @@ 9 CLK_EXP 0 1 0 9 -1 1 0 21 2 RESET 0 1 0 2 -1 1 0 21 341 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 309 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 311 CLK_000_D_0_ 3 -1 1 6 0 2 3 5 6 7 -1 -1 1 0 21 - 310 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 - 323 SM_AMIGA_6_ 3 -1 5 4 1 3 5 7 -1 -1 3 0 21 - 307 CLK_000_D_3_ 3 -1 3 4 0 2 3 5 -1 -1 1 0 21 - 300 inst_BGACK_030_INT_D 3 -1 7 4 0 5 6 7 -1 -1 1 0 21 - 325 SM_AMIGA_0_ 3 -1 0 3 0 5 7 -1 -1 4 0 21 - 295 cpu_est_1_ 3 -1 6 3 2 3 6 -1 -1 4 0 21 - 293 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 - 294 cpu_est_0_ 3 -1 6 3 2 3 6 -1 -1 3 0 21 - 306 CLK_000_D_2_ 3 -1 7 3 0 2 3 -1 -1 1 0 21 - 298 inst_AS_030_D0 3 -1 7 3 3 4 5 -1 -1 1 0 21 - 296 cpu_est_2_ 3 -1 3 3 2 3 6 -1 -1 1 1 21 - 302 inst_DS_000_DMA 3 -1 6 2 0 6 -1 -1 9 0 21 - 301 inst_AS_000_DMA 3 -1 6 2 6 7 -1 -1 7 0 21 - 299 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 - 326 RST_DLY_0_ 3 -1 2 2 0 2 -1 -1 4 0 21 - 319 SM_AMIGA_1_ 3 -1 2 2 0 2 -1 -1 4 0 21 - 343 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 - 335 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 - 332 SM_AMIGA_5_ 3 -1 3 2 2 3 -1 -1 3 0 21 - 324 SM_AMIGA_4_ 3 -1 2 2 2 5 -1 -1 3 0 21 - 322 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 - 321 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 303 CYCLE_DMA_0_ 3 -1 0 2 0 6 -1 -1 3 0 21 - 331 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 - 330 inst_DSACK1_INT 3 -1 0 2 0 7 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 0 2 0 2 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 0 2 0 2 -1 -1 2 1 21 - 320 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 - 318 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 2 0 3 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21 - 313 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 - 305 inst_VPA_D 3 -1 0 2 2 3 -1 -1 1 0 21 + 309 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 310 CLK_000_D_0_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 + 306 CLK_000_D_1_ 3 -1 7 5 0 2 3 5 7 -1 -1 1 0 21 + 299 inst_AS_030_000_SYNC 3 -1 5 3 2 3 5 -1 -1 7 0 21 + 295 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 + 293 cpu_est_1_ 3 -1 6 3 0 3 6 -1 -1 4 0 21 + 335 SM_AMIGA_i_7_ 3 -1 2 3 2 5 7 -1 -1 3 1 21 + 325 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 + 323 SM_AMIGA_6_ 3 -1 2 3 0 2 7 -1 -1 3 0 21 + 296 cpu_est_0_ 3 -1 6 3 0 3 6 -1 -1 3 0 21 + 316 CLK_000_D_2_ 3 -1 7 3 1 2 5 -1 -1 1 0 21 + 300 inst_BGACK_030_INT_D 3 -1 4 3 5 6 7 -1 -1 1 0 21 + 298 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 + 294 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 1 1 21 + 302 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 9 0 21 + 301 inst_AS_000_DMA 3 -1 1 2 1 7 -1 -1 7 0 21 + 334 SM_AMIGA_2_ 3 -1 0 2 0 5 -1 -1 5 0 21 + 304 CYCLE_DMA_1_ 3 -1 5 2 1 5 -1 -1 4 0 21 + 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 + 324 SM_AMIGA_4_ 3 -1 0 2 0 2 -1 -1 3 0 21 + 322 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 + 321 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 + 319 SM_AMIGA_1_ 3 -1 5 2 2 5 -1 -1 3 0 21 + 303 CYCLE_DMA_0_ 3 -1 5 2 1 5 -1 -1 3 0 21 + 331 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21 + 330 inst_DSACK1_INT 3 -1 2 2 2 7 -1 -1 2 0 21 + 320 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 318 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 + 312 inst_CLK_OUT_PRE_D 3 -1 3 2 1 6 -1 -1 1 0 21 + 311 inst_CLK_OUT_PRE_50 3 -1 7 2 3 7 -1 -1 1 0 21 + 307 CLK_000_D_3_ 3 -1 1 2 0 2 -1 -1 1 0 21 + 305 inst_VPA_D 3 -1 6 2 0 3 -1 -1 1 0 21 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 329 inst_CLK_030_H 3 -1 6 1 6 -1 -1 8 0 21 - 334 SM_AMIGA_2_ 3 -1 2 1 2 -1 -1 5 0 21 - 333 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 + 329 inst_CLK_030_H 3 -1 1 1 1 -1 -1 8 0 21 + 333 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 304 CYCLE_DMA_1_ 3 -1 6 1 6 -1 -1 4 0 21 + 326 RST_DLY_0_ 3 -1 3 1 3 -1 -1 4 0 21 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 342 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 + 332 SM_AMIGA_5_ 3 -1 0 1 0 -1 -1 3 0 21 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 317 CLK_000_D_4_ 3 -1 3 1 5 -1 -1 1 0 21 - 316 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 - 315 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 314 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 - 312 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 - 308 inst_DTACK_D0 3 -1 2 1 2 -1 -1 1 0 21 + 328 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21 + 327 RST_DLY_1_ 3 -1 3 1 3 -1 -1 2 1 21 + 317 CLK_000_D_4_ 3 -1 0 1 2 -1 -1 1 0 21 + 315 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 + 314 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21 + 313 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21 + 308 inst_DTACK_D0 3 -1 6 1 0 -1 -1 1 0 21 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 10 CLK_000 1 -1 -1 3 0 6 7 10 -1 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 + 66 IPL_0_ 1 -1 -1 2 0 1 66 -1 + 55 IPL_1_ 1 -1 -1 2 1 3 55 -1 27 BGACK_000 1 -1 -1 2 4 7 27 -1 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 6 63 -1 - 59 A_1_ 1 -1 -1 1 0 59 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 0 35 -1 - 29 DTACK 1 -1 -1 1 2 29 -1 + 63 CLK_030 1 -1 -1 1 1 63 -1 + 59 A_1_ 1 -1 -1 1 6 59 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 29 DTACK 1 -1 -1 1 6 29 -1 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 1 10 -1 -118 "number of signals after reading design file" +116 "number of signals after reading design file" "sig sig sig pair blk fan PT xor sync" "num name type sig num out pin node cnt PT type" "--- ---- ---- ---- --- --- --- ---- --- --- ----" - 81 AS_030 5 -1 7 6 0 1 2 4 5 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 4 0 1 4 7 41 -1 1 0 21 - 79 RW_000 5 341 7 3 0 4 6 79 -1 4 0 21 + 81 AS_030 5 -1 7 4 1 2 4 7 81 -1 1 0 21 + 79 RW_000 5 339 7 3 0 4 6 79 -1 4 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 - 68 A_0_ 5 347 6 2 1 2 68 -1 3 0 21 - 70 RW 5 346 6 2 1 7 70 -1 2 0 21 - 78 SIZE_1_ 5 339 7 1 2 78 -1 3 0 21 - 69 SIZE_0_ 5 344 6 1 2 69 -1 3 0 21 - 40 BERR 5 -1 4 1 3 40 -1 1 0 21 + 70 RW 5 344 6 2 1 7 70 -1 2 0 21 + 78 SIZE_1_ 5 337 7 1 0 78 -1 3 0 21 + 69 SIZE_0_ 5 340 6 1 0 69 -1 3 0 21 + 68 A_0_ 5 345 6 1 0 68 -1 3 0 21 + 40 BERR 5 -1 4 1 5 40 -1 1 0 21 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 @@ -3537,507 +754,11 @@ 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 340 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 349 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 348 1 0 6 -1 10 0 21 - 82 BGACK_030 5 343 7 0 82 -1 3 0 21 - 34 VMA 5 345 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 342 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 343 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 309 inst_RESET_OUT 3 -1 5 8 0 1 2 3 4 5 6 7 -1 -1 2 0 21 - 311 CLK_000_D_0_ 3 -1 6 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 310 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 325 SM_AMIGA_6_ 3 -1 5 5 0 1 2 5 7 -1 -1 3 0 21 - 300 inst_BGACK_030_INT_D 3 -1 4 4 0 5 6 7 -1 -1 1 0 21 - 328 RST_DLY_0_ 3 -1 7 3 2 5 7 -1 -1 4 0 21 - 327 SM_AMIGA_0_ 3 -1 6 3 5 6 7 -1 -1 4 0 21 - 326 SM_AMIGA_4_ 3 -1 2 3 1 2 3 -1 -1 3 0 21 - 330 RST_DLY_2_ 3 -1 2 3 2 5 7 -1 -1 2 0 21 - 329 RST_DLY_1_ 3 -1 7 3 2 5 7 -1 -1 2 1 21 - 298 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 - 301 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 - 299 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 - 336 SM_AMIGA_2_ 3 -1 3 2 2 3 -1 -1 5 0 21 - 321 SM_AMIGA_1_ 3 -1 2 2 2 6 -1 -1 4 0 21 - 296 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 21 - 294 cpu_est_3_ 3 -1 3 2 3 6 -1 -1 4 0 21 - 337 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 - 334 SM_AMIGA_5_ 3 -1 0 2 0 2 -1 -1 3 0 21 - 324 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 - 323 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21 - 303 CYCLE_DMA_0_ 3 -1 1 2 0 1 -1 -1 3 0 21 - 333 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21 - 332 inst_DSACK1_INT 3 -1 2 2 2 7 -1 -1 2 0 21 - 322 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 - 320 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 2 0 3 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21 - 317 CLK_000_D_3_ 3 -1 6 2 2 6 -1 -1 1 0 21 - 313 inst_CLK_OUT_PRE_D 3 -1 5 2 1 6 -1 -1 1 0 21 - 312 inst_CLK_OUT_PRE_50 3 -1 3 2 3 5 -1 -1 1 0 21 - 307 CLK_000_D_5_ 3 -1 6 2 5 6 -1 -1 1 0 21 - 306 CLK_000_D_2_ 3 -1 7 2 2 6 -1 -1 1 0 21 - 293 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 1 1 21 - 349 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 348 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 340 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 302 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 - 331 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 - 335 SM_AMIGA_3_ 3 -1 3 1 3 -1 -1 5 0 21 - 341 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 304 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 - 347 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 345 RN_VMA 3 34 3 1 3 34 -1 3 0 21 - 344 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 339 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 295 cpu_est_0_ 3 -1 3 1 3 -1 -1 3 0 21 - 346 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 342 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 338 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 319 CLK_000_D_6_ 3 -1 6 1 5 -1 -1 1 0 21 - 318 CLK_000_D_4_ 3 -1 6 1 6 -1 -1 1 0 21 - 316 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21 - 315 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 314 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21 - 308 inst_DTACK_D0 3 -1 2 1 3 -1 -1 1 0 21 - 305 inst_VPA_D 3 -1 6 1 3 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 0 1 67 -1 - 66 IPL_0_ 1 -1 -1 2 0 1 66 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 0 63 -1 - 59 A_1_ 1 -1 -1 1 0 59 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 6 35 -1 - 29 DTACK 1 -1 -1 1 2 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 6 10 -1 -118 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 5 0 2 4 5 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 4 0 4 6 7 41 -1 1 0 21 - 79 RW_000 5 341 7 2 4 6 79 -1 4 0 21 - 68 A_0_ 5 347 6 2 0 2 68 -1 3 0 21 - 70 RW 5 346 6 2 2 7 70 -1 2 0 21 - 31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21 - 78 SIZE_1_ 5 339 7 1 0 78 -1 3 0 21 - 69 SIZE_0_ 5 344 6 1 0 69 -1 3 0 21 - 40 BERR 5 -1 4 1 3 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 340 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 349 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 348 1 0 6 -1 10 0 21 - 82 BGACK_030 5 343 7 0 82 -1 3 0 21 - 34 VMA 5 345 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 342 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 343 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 308 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 310 CLK_000_D_0_ 3 -1 0 6 0 1 2 3 5 7 -1 -1 1 0 21 - 309 CLK_000_D_1_ 3 -1 7 6 0 1 2 3 5 7 -1 -1 1 0 21 - 319 inst_BGACK_030_INT_D 3 -1 4 4 1 5 6 7 -1 -1 1 0 21 - 299 inst_AS_030_000_SYNC 3 -1 5 3 0 3 5 -1 -1 7 0 21 - 328 RST_DLY_0_ 3 -1 7 3 1 3 7 -1 -1 4 0 21 - 327 SM_AMIGA_0_ 3 -1 2 3 0 2 7 -1 -1 4 0 21 - 295 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 - 337 SM_AMIGA_i_7_ 3 -1 0 3 0 5 7 -1 -1 3 1 21 - 326 SM_AMIGA_4_ 3 -1 5 3 2 3 5 -1 -1 3 0 21 - 325 SM_AMIGA_6_ 3 -1 0 3 0 2 7 -1 -1 3 0 21 - 330 RST_DLY_2_ 3 -1 7 3 1 3 7 -1 -1 2 0 21 - 329 RST_DLY_1_ 3 -1 1 3 1 3 7 -1 -1 2 1 21 - 296 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 1 1 21 - 301 inst_DS_000_DMA 3 -1 6 2 0 6 -1 -1 9 0 21 - 300 inst_AS_000_DMA 3 -1 6 2 6 7 -1 -1 7 0 21 - 336 SM_AMIGA_2_ 3 -1 3 2 2 3 -1 -1 5 0 21 - 303 CYCLE_DMA_1_ 3 -1 0 2 0 6 -1 -1 4 0 21 - 293 cpu_est_3_ 3 -1 3 2 3 6 -1 -1 4 0 21 - 334 SM_AMIGA_5_ 3 -1 0 2 0 5 -1 -1 3 0 21 - 324 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 - 323 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 - 302 CYCLE_DMA_0_ 3 -1 0 2 0 6 -1 -1 3 0 21 - 294 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 3 0 21 - 333 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21 - 332 inst_DSACK1_INT 3 -1 2 2 2 7 -1 -1 2 0 21 - 322 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 - 320 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21 - 316 CLK_000_D_3_ 3 -1 6 2 2 6 -1 -1 1 0 21 - 312 inst_CLK_OUT_PRE_D 3 -1 5 2 1 6 -1 -1 1 0 21 - 311 inst_CLK_OUT_PRE_50 3 -1 0 2 0 5 -1 -1 1 0 21 - 306 CLK_000_D_5_ 3 -1 6 2 0 5 -1 -1 1 0 21 - 305 CLK_000_D_2_ 3 -1 7 2 2 6 -1 -1 1 0 21 - 298 inst_AS_030_D0 3 -1 4 2 3 4 -1 -1 1 0 21 - 349 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 348 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 340 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 331 inst_CLK_030_H 3 -1 6 1 6 -1 -1 8 0 21 - 335 SM_AMIGA_3_ 3 -1 3 1 3 -1 -1 5 0 21 - 341 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 321 SM_AMIGA_1_ 3 -1 2 1 2 -1 -1 4 0 21 - 347 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 345 RN_VMA 3 34 3 1 3 34 -1 3 0 21 - 344 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 339 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 346 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 342 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 338 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 318 CLK_000_D_6_ 3 -1 5 1 0 -1 -1 1 0 21 - 317 CLK_000_D_4_ 3 -1 6 1 6 -1 -1 1 0 21 - 315 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21 - 314 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 - 313 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 - 307 inst_DTACK_D0 3 -1 1 1 3 -1 -1 1 0 21 - 304 inst_VPA_D 3 -1 2 1 3 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 0 1 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 - 55 IPL_1_ 1 -1 -1 2 1 6 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 6 63 -1 - 59 A_1_ 1 -1 -1 1 1 59 -1 - 35 VPA 1 -1 -1 1 2 35 -1 - 29 DTACK 1 -1 -1 1 1 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 0 10 -1 -118 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 5 1 2 4 5 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 4 0 4 5 7 41 -1 1 0 21 - 31 UDS_000 5 -1 3 4 0 5 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 4 0 5 6 7 30 -1 1 0 21 - 79 RW_000 5 341 7 3 4 5 6 79 -1 4 0 21 - 68 A_0_ 5 347 6 2 2 5 68 -1 3 0 21 - 70 RW 5 346 6 2 5 7 70 -1 2 0 21 - 78 SIZE_1_ 5 339 7 1 2 78 -1 3 0 21 - 69 SIZE_0_ 5 343 6 1 2 69 -1 3 0 21 - 40 BERR 5 -1 4 1 0 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 340 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 349 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 348 1 0 6 -1 10 0 21 - 82 BGACK_030 5 344 7 0 82 -1 3 0 21 - 34 VMA 5 345 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 342 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 344 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 309 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 311 CLK_000_D_0_ 3 -1 3 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 310 CLK_000_D_1_ 3 -1 2 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 325 SM_AMIGA_6_ 3 -1 2 4 1 2 5 7 -1 -1 3 0 21 - 300 inst_BGACK_030_INT_D 3 -1 4 4 2 3 6 7 -1 -1 1 0 21 - 301 inst_AS_000_DMA 3 -1 0 3 0 5 7 -1 -1 7 0 21 - 327 SM_AMIGA_0_ 3 -1 1 3 1 2 7 -1 -1 4 0 21 - 296 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 - 294 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 295 cpu_est_0_ 3 -1 6 3 0 3 6 -1 -1 3 0 21 - 293 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 1 1 21 - 302 inst_DS_000_DMA 3 -1 5 2 0 5 -1 -1 9 0 21 - 331 inst_CLK_030_H 3 -1 0 2 0 5 -1 -1 8 0 21 - 299 inst_AS_030_000_SYNC 3 -1 2 2 2 3 -1 -1 7 0 21 - 336 SM_AMIGA_2_ 3 -1 0 2 0 1 -1 -1 5 0 21 - 304 CYCLE_DMA_1_ 3 -1 0 2 0 5 -1 -1 4 0 21 - 345 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 337 SM_AMIGA_i_7_ 3 -1 2 2 2 7 -1 -1 3 1 21 - 334 SM_AMIGA_5_ 3 -1 7 2 0 7 -1 -1 3 0 21 - 326 SM_AMIGA_4_ 3 -1 0 2 0 5 -1 -1 3 0 21 - 324 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 - 323 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 303 CYCLE_DMA_0_ 3 -1 0 2 0 5 -1 -1 3 0 21 - 333 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21 - 332 inst_DSACK1_INT 3 -1 1 2 1 7 -1 -1 2 0 21 - 322 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 - 317 CLK_000_D_3_ 3 -1 7 2 1 3 -1 -1 1 0 21 - 313 inst_CLK_OUT_PRE_D 3 -1 3 2 1 6 -1 -1 1 0 21 - 312 inst_CLK_OUT_PRE_50 3 -1 6 2 3 6 -1 -1 1 0 21 - 307 CLK_000_D_5_ 3 -1 5 2 2 3 -1 -1 1 0 21 - 306 CLK_000_D_2_ 3 -1 7 2 1 7 -1 -1 1 0 21 - 305 inst_VPA_D 3 -1 5 2 0 3 -1 -1 1 0 21 - 298 inst_AS_030_D0 3 -1 4 2 3 4 -1 -1 1 0 21 - 349 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 348 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 340 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 335 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 341 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 328 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 - 321 SM_AMIGA_1_ 3 -1 1 1 1 -1 -1 4 0 21 - 347 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 343 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 339 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 346 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 342 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 338 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 330 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 - 329 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 - 320 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 3 1 3 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 - 319 CLK_000_D_6_ 3 -1 3 1 2 -1 -1 1 0 21 - 318 CLK_000_D_4_ 3 -1 3 1 5 -1 -1 1 0 21 - 316 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21 - 315 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 - 314 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 - 308 inst_DTACK_D0 3 -1 7 1 0 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 - 63 CLK_030 1 -1 -1 3 0 2 5 63 -1 - 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 0 1 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 - 59 A_1_ 1 -1 -1 2 2 3 59 -1 - 55 IPL_1_ 1 -1 -1 2 1 6 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 35 VPA 1 -1 -1 1 5 35 -1 - 29 DTACK 1 -1 -1 1 7 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 3 10 -1 -118 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 6 0 1 2 4 5 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 4 0 1 4 7 41 -1 1 0 21 - 79 RW_000 5 341 7 3 0 4 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 - 68 A_0_ 5 347 6 2 1 2 68 -1 3 0 21 - 70 RW 5 346 6 2 1 7 70 -1 2 0 21 - 78 SIZE_1_ 5 339 7 1 2 78 -1 3 0 21 - 69 SIZE_0_ 5 344 6 1 2 69 -1 3 0 21 - 40 BERR 5 -1 4 1 3 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 340 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 349 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 348 1 0 6 -1 10 0 21 - 82 BGACK_030 5 343 7 0 82 -1 3 0 21 - 34 VMA 5 345 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 342 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 343 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 309 inst_RESET_OUT 3 -1 5 8 0 1 2 3 4 5 6 7 -1 -1 2 0 21 - 311 CLK_000_D_0_ 3 -1 6 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 310 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 325 SM_AMIGA_6_ 3 -1 5 5 0 1 2 5 7 -1 -1 3 0 21 - 300 inst_BGACK_030_INT_D 3 -1 4 4 0 5 6 7 -1 -1 1 0 21 - 328 RST_DLY_0_ 3 -1 7 3 2 5 7 -1 -1 4 0 21 - 327 SM_AMIGA_0_ 3 -1 6 3 5 6 7 -1 -1 4 0 21 - 326 SM_AMIGA_4_ 3 -1 2 3 1 2 3 -1 -1 3 0 21 - 330 RST_DLY_2_ 3 -1 2 3 2 5 7 -1 -1 2 0 21 - 329 RST_DLY_1_ 3 -1 7 3 2 5 7 -1 -1 2 1 21 - 298 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 - 301 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 - 299 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 - 336 SM_AMIGA_2_ 3 -1 3 2 2 3 -1 -1 5 0 21 - 321 SM_AMIGA_1_ 3 -1 2 2 2 6 -1 -1 4 0 21 - 296 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 21 - 294 cpu_est_3_ 3 -1 3 2 3 6 -1 -1 4 0 21 - 337 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 - 334 SM_AMIGA_5_ 3 -1 0 2 0 2 -1 -1 3 0 21 - 324 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 - 323 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21 - 303 CYCLE_DMA_0_ 3 -1 1 2 0 1 -1 -1 3 0 21 - 333 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21 - 332 inst_DSACK1_INT 3 -1 2 2 2 7 -1 -1 2 0 21 - 322 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 - 320 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 2 0 3 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21 - 317 CLK_000_D_3_ 3 -1 6 2 2 6 -1 -1 1 0 21 - 313 inst_CLK_OUT_PRE_D 3 -1 5 2 1 6 -1 -1 1 0 21 - 312 inst_CLK_OUT_PRE_50 3 -1 3 2 3 5 -1 -1 1 0 21 - 307 CLK_000_D_5_ 3 -1 6 2 5 6 -1 -1 1 0 21 - 306 CLK_000_D_2_ 3 -1 7 2 2 6 -1 -1 1 0 21 - 293 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 1 1 21 - 349 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 348 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 340 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 302 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 - 331 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 - 335 SM_AMIGA_3_ 3 -1 3 1 3 -1 -1 5 0 21 - 341 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 304 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 - 347 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 345 RN_VMA 3 34 3 1 3 34 -1 3 0 21 - 344 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 339 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 295 cpu_est_0_ 3 -1 3 1 3 -1 -1 3 0 21 - 346 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 342 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 338 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 319 CLK_000_D_6_ 3 -1 6 1 5 -1 -1 1 0 21 - 318 CLK_000_D_4_ 3 -1 6 1 6 -1 -1 1 0 21 - 316 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21 - 315 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 314 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21 - 308 inst_DTACK_D0 3 -1 2 1 3 -1 -1 1 0 21 - 305 inst_VPA_D 3 -1 6 1 3 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 0 1 67 -1 - 66 IPL_0_ 1 -1 -1 2 0 1 66 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 0 63 -1 - 59 A_1_ 1 -1 -1 1 0 59 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 6 35 -1 - 29 DTACK 1 -1 -1 1 2 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 6 10 -1 -117 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 5 1 2 4 5 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 5 0 2 3 4 7 41 -1 1 0 21 - 79 RW_000 5 340 7 3 2 4 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 3 2 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 2 6 7 30 -1 1 0 21 - 68 A_0_ 5 346 6 2 2 5 68 -1 3 0 21 - 70 RW 5 345 6 2 1 7 70 -1 2 0 21 - 78 SIZE_1_ 5 338 7 1 2 78 -1 3 0 21 - 69 SIZE_0_ 5 343 6 1 2 69 -1 3 0 21 - 40 BERR 5 -1 4 1 0 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 339 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 348 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 347 1 0 6 -1 10 0 21 + 8 IPL_030_2_ 5 338 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 82 BGACK_030 5 342 7 0 82 -1 3 0 21 - 34 VMA 5 344 3 0 34 -1 3 0 21 + 34 VMA 5 343 3 0 34 -1 3 0 21 65 E 0 6 0 65 -1 2 0 21 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 @@ -4052,86 +773,85 @@ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 9 CLK_EXP 0 1 0 9 -1 1 0 21 2 RESET 0 1 0 2 -1 1 0 21 - 342 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 342 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 309 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 311 CLK_000_D_0_ 3 -1 3 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 310 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 324 SM_AMIGA_6_ 3 -1 5 4 1 2 5 7 -1 -1 3 0 21 - 326 SM_AMIGA_0_ 3 -1 0 3 0 5 7 -1 -1 4 0 21 - 296 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 - 294 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 300 inst_BGACK_030_INT_D 3 -1 0 3 5 6 7 -1 -1 1 0 21 - 298 inst_AS_030_D0 3 -1 7 3 3 4 5 -1 -1 1 0 21 - 293 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 - 302 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 - 301 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21 - 299 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 - 327 RST_DLY_0_ 3 -1 6 2 1 6 -1 -1 4 0 21 - 320 SM_AMIGA_1_ 3 -1 0 2 0 5 -1 -1 4 0 21 - 304 CYCLE_DMA_1_ 3 -1 3 2 2 3 -1 -1 4 0 21 - 344 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 336 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 - 333 SM_AMIGA_5_ 3 -1 1 2 0 1 -1 -1 3 0 21 - 325 SM_AMIGA_4_ 3 -1 0 2 0 1 -1 -1 3 0 21 - 323 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 - 322 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21 - 303 CYCLE_DMA_0_ 3 -1 3 2 2 3 -1 -1 3 0 21 - 295 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21 - 332 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 - 331 inst_DSACK1_INT 3 -1 5 2 5 7 -1 -1 2 0 21 - 329 RST_DLY_2_ 3 -1 6 2 1 6 -1 -1 2 0 21 - 328 RST_DLY_1_ 3 -1 1 2 1 6 -1 -1 2 1 21 - 321 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 - 319 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 310 CLK_000_D_0_ 3 -1 2 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 306 CLK_000_D_1_ 3 -1 1 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 322 SM_AMIGA_6_ 3 -1 2 5 0 1 2 5 7 -1 -1 3 0 21 + 316 CLK_000_D_2_ 3 -1 7 4 1 3 5 7 -1 -1 1 0 21 + 296 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 + 294 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 + 323 SM_AMIGA_4_ 3 -1 3 3 1 3 5 -1 -1 3 0 21 + 295 cpu_est_0_ 3 -1 1 3 1 3 5 -1 -1 3 0 21 + 300 inst_BGACK_030_INT_D 3 -1 2 3 2 6 7 -1 -1 1 0 21 + 298 inst_AS_030_D0 3 -1 7 3 2 3 4 -1 -1 1 0 21 + 293 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 1 1 21 + 301 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 299 inst_AS_030_000_SYNC 3 -1 2 2 2 3 -1 -1 7 0 21 + 343 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 335 SM_AMIGA_i_7_ 3 -1 2 2 2 7 -1 -1 3 1 21 + 332 SM_AMIGA_5_ 3 -1 5 2 3 5 -1 -1 3 0 21 + 325 SM_AMIGA_0_ 3 -1 7 2 2 7 -1 -1 3 0 21 + 324 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 321 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 + 320 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21 + 331 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21 + 319 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 + 318 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 317 CLK_000_D_3_ 3 -1 0 2 0 5 -1 -1 1 0 21 - 313 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 - 307 CLK_000_D_4_ 3 -1 0 2 5 6 -1 -1 1 0 21 - 306 CLK_000_D_2_ 3 -1 7 2 0 5 -1 -1 1 0 21 - 305 inst_VPA_D 3 -1 2 2 0 3 -1 -1 1 0 21 - 348 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 347 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 339 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 330 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21 - 335 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 5 0 21 - 334 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 340 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 346 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 343 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 338 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 345 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 312 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 + 305 inst_VPA_D 3 -1 0 2 3 5 -1 -1 1 0 21 + 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 302 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 329 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 334 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 5 0 21 + 333 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 + 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 326 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 + 304 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 + 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 340 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 + 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 + 303 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 + 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 341 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 337 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 318 CLK_000_D_5_ 3 -1 6 1 5 -1 -1 1 0 21 - 316 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 - 315 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 314 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21 - 312 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 - 308 inst_DTACK_D0 3 -1 7 1 0 -1 -1 1 0 21 + 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 330 inst_DSACK1_INT 3 -1 7 1 7 -1 -1 2 0 21 + 328 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 + 327 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 + 317 CLK_000_D_4_ 3 -1 2 1 2 -1 -1 1 0 21 + 315 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 + 314 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21 + 313 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21 + 311 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 308 inst_DTACK_D0 3 -1 5 1 5 -1 -1 1 0 21 + 307 CLK_000_D_3_ 3 -1 7 1 2 -1 -1 1 0 21 60 CLK_OSZI 9 -1 0 60 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 + 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 66 IPL_0_ 1 -1 -1 2 0 1 66 -1 + 55 IPL_1_ 1 -1 -1 2 1 3 55 -1 27 BGACK_000 1 -1 -1 2 4 7 27 -1 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 2 63 -1 + 63 CLK_030 1 -1 -1 1 0 63 -1 59 A_1_ 1 -1 -1 1 6 59 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 2 35 -1 - 29 DTACK 1 -1 -1 1 7 29 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 29 DTACK 1 -1 -1 1 5 29 -1 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 3 10 -1 + 10 CLK_000 1 -1 -1 1 2 10 -1 117 "number of signals after reading design file" "sig sig sig pair blk fan PT xor sync" @@ -4255,21 +975,21 @@ 29 DTACK 1 -1 -1 1 6 29 -1 20 BG_030 1 -1 -1 1 3 20 -1 10 CLK_000 1 -1 -1 1 3 10 -1 -117 "number of signals after reading design file" +116 "number of signals after reading design file" "sig sig sig pair blk fan PT xor sync" "num name type sig num out pin node cnt PT type" "--- ---- ---- ---- --- --- --- ---- --- --- ----" - 81 AS_030 5 -1 7 5 1 2 4 5 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 5 0 2 3 4 7 41 -1 1 0 21 - 79 RW_000 5 340 7 3 2 4 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 3 2 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 2 6 7 30 -1 1 0 21 - 68 A_0_ 5 346 6 2 2 5 68 -1 3 0 21 - 70 RW 5 345 6 2 1 7 70 -1 2 0 21 - 78 SIZE_1_ 5 338 7 1 2 78 -1 3 0 21 - 69 SIZE_0_ 5 343 6 1 2 69 -1 3 0 21 + 81 AS_030 5 -1 7 5 2 4 5 6 7 81 -1 1 0 21 + 41 AS_000 5 -1 4 5 0 1 4 6 7 41 -1 1 0 21 + 79 RW_000 5 339 7 3 1 4 6 79 -1 4 0 21 + 31 UDS_000 5 -1 3 3 1 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 1 6 7 30 -1 1 0 21 + 68 A_0_ 5 345 6 2 2 3 68 -1 3 0 21 + 70 RW 5 344 6 2 2 7 70 -1 2 0 21 + 78 SIZE_1_ 5 337 7 1 2 78 -1 3 0 21 + 69 SIZE_0_ 5 340 6 1 2 69 -1 3 0 21 40 BERR 5 -1 4 1 0 40 -1 1 0 21 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 @@ -4279,11 +999,499 @@ 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 339 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 348 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 347 1 0 6 -1 10 0 21 + 8 IPL_030_2_ 5 338 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 82 BGACK_030 5 342 7 0 82 -1 3 0 21 - 34 VMA 5 344 3 0 34 -1 3 0 21 + 34 VMA 5 343 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 341 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 80 DSACK1 0 7 0 80 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 342 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 309 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 310 CLK_000_D_0_ 3 -1 1 6 0 2 3 5 6 7 -1 -1 1 0 21 + 306 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 + 323 SM_AMIGA_6_ 3 -1 2 4 2 3 6 7 -1 -1 3 0 21 + 300 inst_BGACK_030_INT_D 3 -1 4 4 2 5 6 7 -1 -1 1 0 21 + 299 inst_AS_030_000_SYNC 3 -1 5 3 2 3 5 -1 -1 7 0 21 + 296 cpu_est_1_ 3 -1 6 3 0 3 6 -1 -1 4 0 21 + 294 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 + 335 SM_AMIGA_i_7_ 3 -1 2 3 2 5 7 -1 -1 3 1 21 + 325 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 + 324 SM_AMIGA_4_ 3 -1 3 3 0 2 3 -1 -1 3 0 21 + 295 cpu_est_0_ 3 -1 6 3 0 3 6 -1 -1 3 0 21 + 298 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 + 293 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 + 302 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 9 0 21 + 301 inst_AS_000_DMA 3 -1 1 2 1 7 -1 -1 7 0 21 + 334 SM_AMIGA_2_ 3 -1 0 2 0 5 -1 -1 5 0 21 + 304 CYCLE_DMA_1_ 3 -1 6 2 1 6 -1 -1 4 0 21 + 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 + 322 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 + 321 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 + 303 CYCLE_DMA_0_ 3 -1 6 2 1 6 -1 -1 3 0 21 + 331 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21 + 330 inst_DSACK1_INT 3 -1 5 2 5 7 -1 -1 2 0 21 + 318 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 316 CLK_000_D_2_ 3 -1 7 2 0 5 -1 -1 1 0 21 + 312 inst_CLK_OUT_PRE_D 3 -1 3 2 1 6 -1 -1 1 0 21 + 311 inst_CLK_OUT_PRE_50 3 -1 6 2 3 6 -1 -1 1 0 21 + 307 CLK_000_D_3_ 3 -1 0 2 2 5 -1 -1 1 0 21 + 305 inst_VPA_D 3 -1 7 2 0 3 -1 -1 1 0 21 + 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 329 inst_CLK_030_H 3 -1 1 1 1 -1 -1 8 0 21 + 333 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 + 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 326 RST_DLY_0_ 3 -1 0 1 0 -1 -1 4 0 21 + 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 340 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 + 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 + 332 SM_AMIGA_5_ 3 -1 3 1 3 -1 -1 3 0 21 + 319 SM_AMIGA_1_ 3 -1 5 1 5 -1 -1 3 0 21 + 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 341 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 336 N_262 3 -1 4 1 4 -1 -1 2 0 21 + 328 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21 + 327 RST_DLY_1_ 3 -1 0 1 0 -1 -1 2 1 21 + 320 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 + 317 CLK_000_D_4_ 3 -1 5 1 2 -1 -1 1 0 21 + 315 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21 + 314 IPL_D0_1_ 3 -1 7 1 1 -1 -1 1 0 21 + 313 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 + 308 inst_DTACK_D0 3 -1 0 1 0 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 + 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 2 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 + 59 A_1_ 1 -1 -1 2 2 6 59 -1 + 55 IPL_1_ 1 -1 -1 2 1 7 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 63 CLK_030 1 -1 -1 1 1 63 -1 + 35 VPA 1 -1 -1 1 7 35 -1 + 29 DTACK 1 -1 -1 1 0 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 1 10 -1 +116 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 -1 7 5 2 4 5 6 7 81 -1 1 0 21 + 41 AS_000 5 -1 4 5 0 1 4 6 7 41 -1 1 0 21 + 79 RW_000 5 339 7 3 1 4 6 79 -1 4 0 21 + 31 UDS_000 5 -1 3 3 1 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 1 6 7 30 -1 1 0 21 + 68 A_0_ 5 345 6 2 2 3 68 -1 3 0 21 + 70 RW 5 344 6 2 2 7 70 -1 2 0 21 + 78 SIZE_1_ 5 337 7 1 2 78 -1 3 0 21 + 69 SIZE_0_ 5 341 6 1 2 69 -1 3 0 21 + 40 BERR 5 -1 4 1 0 40 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 338 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 + 82 BGACK_030 5 342 7 0 82 -1 3 0 21 + 34 VMA 5 343 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 340 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 80 DSACK1 0 7 0 80 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 342 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 308 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 310 CLK_000_D_0_ 3 -1 0 6 0 2 3 5 6 7 -1 -1 1 0 21 + 309 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 + 323 SM_AMIGA_6_ 3 -1 2 4 2 3 6 7 -1 -1 3 0 21 + 300 inst_BGACK_030_INT_D 3 -1 4 4 2 5 6 7 -1 -1 1 0 21 + 299 inst_AS_030_000_SYNC 3 -1 5 3 2 3 5 -1 -1 7 0 21 + 296 cpu_est_1_ 3 -1 6 3 0 3 6 -1 -1 4 0 21 + 294 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 + 335 SM_AMIGA_i_7_ 3 -1 2 3 2 5 7 -1 -1 3 1 21 + 325 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 + 324 SM_AMIGA_4_ 3 -1 3 3 0 2 3 -1 -1 3 0 21 + 295 cpu_est_0_ 3 -1 6 3 0 3 6 -1 -1 3 0 21 + 298 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 + 293 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 + 302 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 9 0 21 + 301 inst_AS_000_DMA 3 -1 1 2 1 7 -1 -1 7 0 21 + 334 SM_AMIGA_2_ 3 -1 0 2 0 5 -1 -1 5 0 21 + 304 CYCLE_DMA_1_ 3 -1 6 2 1 6 -1 -1 4 0 21 + 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 + 322 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 + 321 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 + 303 CYCLE_DMA_0_ 3 -1 6 2 1 6 -1 -1 3 0 21 + 331 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21 + 330 inst_DSACK1_INT 3 -1 5 2 5 7 -1 -1 2 0 21 + 318 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 312 inst_CLK_OUT_PRE_D 3 -1 3 2 1 6 -1 -1 1 0 21 + 311 inst_CLK_OUT_PRE_50 3 -1 6 2 3 6 -1 -1 1 0 21 + 306 CLK_000_D_3_ 3 -1 1 2 2 5 -1 -1 1 0 21 + 305 inst_VPA_D 3 -1 7 2 0 3 -1 -1 1 0 21 + 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 329 inst_CLK_030_H 3 -1 1 1 1 -1 -1 8 0 21 + 333 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 + 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 326 RST_DLY_0_ 3 -1 0 1 0 -1 -1 4 0 21 + 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 341 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 + 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 + 332 SM_AMIGA_5_ 3 -1 3 1 3 -1 -1 3 0 21 + 319 SM_AMIGA_1_ 3 -1 5 1 5 -1 -1 3 0 21 + 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 328 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21 + 327 RST_DLY_1_ 3 -1 0 1 0 -1 -1 2 1 21 + 320 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 + 317 CLK_000_D_4_ 3 -1 5 1 2 -1 -1 1 0 21 + 316 CLK_000_D_2_ 3 -1 7 1 1 -1 -1 1 0 21 + 315 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21 + 314 IPL_D0_1_ 3 -1 7 1 1 -1 -1 1 0 21 + 313 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 + 307 inst_DTACK_D0 3 -1 0 1 0 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 + 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 2 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 + 59 A_1_ 1 -1 -1 2 2 6 59 -1 + 55 IPL_1_ 1 -1 -1 2 1 7 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 10 CLK_000 1 -1 -1 2 0 5 10 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 63 CLK_030 1 -1 -1 1 1 63 -1 + 35 VPA 1 -1 -1 1 7 35 -1 + 29 DTACK 1 -1 -1 1 0 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 +116 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 -1 7 6 0 2 3 4 5 7 81 -1 1 0 21 + 41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21 + 79 RW_000 5 339 7 3 0 4 6 79 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 68 A_0_ 5 345 6 2 1 5 68 -1 3 0 21 + 70 RW 5 344 6 2 3 7 70 -1 2 0 21 + 78 SIZE_1_ 5 337 7 1 5 78 -1 3 0 21 + 69 SIZE_0_ 5 342 6 1 5 69 -1 3 0 21 + 40 BERR 5 -1 4 1 5 40 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 338 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 + 82 BGACK_030 5 341 7 0 82 -1 3 0 21 + 34 VMA 5 343 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 340 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 80 DSACK1 0 7 0 80 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 341 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 309 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 311 CLK_000_D_0_ 3 -1 3 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 310 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 323 SM_AMIGA_6_ 3 -1 1 5 0 1 3 5 7 -1 -1 3 0 21 + 300 inst_AS_030_000_SYNC 3 -1 2 3 1 2 3 -1 -1 7 0 21 + 295 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 + 293 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 + 335 SM_AMIGA_i_7_ 3 -1 1 3 1 2 7 -1 -1 3 1 21 + 325 SM_AMIGA_0_ 3 -1 6 3 1 6 7 -1 -1 3 0 21 + 324 SM_AMIGA_4_ 3 -1 2 3 2 3 5 -1 -1 3 0 21 + 301 inst_BGACK_030_INT_D 3 -1 4 3 2 6 7 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 4 3 2 3 4 -1 -1 1 0 21 + 294 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 1 1 21 + 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 334 SM_AMIGA_2_ 3 -1 5 2 0 5 -1 -1 5 0 21 + 326 RST_DLY_0_ 3 -1 6 2 5 6 -1 -1 4 0 21 + 343 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 332 SM_AMIGA_5_ 3 -1 0 2 0 2 -1 -1 3 0 21 + 322 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 + 319 SM_AMIGA_1_ 3 -1 0 2 0 6 -1 -1 3 0 21 + 304 CYCLE_DMA_0_ 3 -1 2 2 0 2 -1 -1 3 0 21 + 296 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 3 0 21 + 331 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 + 330 inst_DSACK1_INT 3 -1 0 2 0 7 -1 -1 2 0 21 + 328 RST_DLY_2_ 3 -1 5 2 5 6 -1 -1 2 0 21 + 327 RST_DLY_1_ 3 -1 6 2 5 6 -1 -1 2 1 21 + 320 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 7 2 1 6 -1 -1 1 0 21 + 307 CLK_000_D_3_ 3 -1 0 2 1 6 -1 -1 1 0 21 + 306 inst_VPA_D 3 -1 2 2 3 5 -1 -1 1 0 21 + 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 329 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 333 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 + 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 + 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 342 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 + 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 + 321 inst_DS_000_ENABLE 3 -1 3 1 3 -1 -1 3 0 21 + 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 + 318 CLK_000_D_4_ 3 -1 6 1 1 -1 -1 1 0 21 + 317 CLK_000_D_2_ 3 -1 7 1 0 -1 -1 1 0 21 + 316 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 + 315 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 + 314 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21 + 312 inst_CLK_OUT_PRE_50 3 -1 7 1 7 -1 -1 1 0 21 + 308 inst_DTACK_D0 3 -1 1 1 5 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 + 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 10 CLK_000 1 -1 -1 3 0 3 6 10 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 + 66 IPL_0_ 1 -1 -1 2 0 1 66 -1 + 55 IPL_1_ 1 -1 -1 2 1 6 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 63 CLK_030 1 -1 -1 1 0 63 -1 + 59 A_1_ 1 -1 -1 1 2 59 -1 + 35 VPA 1 -1 -1 1 2 35 -1 + 29 DTACK 1 -1 -1 1 1 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 +116 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 -1 7 5 2 4 5 6 7 81 -1 1 0 21 + 41 AS_000 5 -1 4 5 0 1 4 6 7 41 -1 1 0 21 + 79 RW_000 5 339 7 3 1 4 6 79 -1 4 0 21 + 31 UDS_000 5 -1 3 3 1 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 1 6 7 30 -1 1 0 21 + 68 A_0_ 5 345 6 2 2 3 68 -1 3 0 21 + 70 RW 5 344 6 2 2 7 70 -1 2 0 21 + 78 SIZE_1_ 5 337 7 1 2 78 -1 3 0 21 + 69 SIZE_0_ 5 341 6 1 2 69 -1 3 0 21 + 40 BERR 5 -1 4 1 0 40 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 338 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 + 82 BGACK_030 5 342 7 0 82 -1 3 0 21 + 34 VMA 5 343 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 340 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 80 DSACK1 0 7 0 80 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 342 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 308 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 310 CLK_000_D_0_ 3 -1 0 6 0 2 3 5 6 7 -1 -1 1 0 21 + 309 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 + 323 SM_AMIGA_6_ 3 -1 2 4 2 3 6 7 -1 -1 3 0 21 + 300 inst_BGACK_030_INT_D 3 -1 4 4 2 5 6 7 -1 -1 1 0 21 + 299 inst_AS_030_000_SYNC 3 -1 5 3 2 3 5 -1 -1 7 0 21 + 296 cpu_est_1_ 3 -1 6 3 0 3 6 -1 -1 4 0 21 + 294 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 + 335 SM_AMIGA_i_7_ 3 -1 2 3 2 5 7 -1 -1 3 1 21 + 325 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 + 324 SM_AMIGA_4_ 3 -1 3 3 0 2 3 -1 -1 3 0 21 + 295 cpu_est_0_ 3 -1 6 3 0 3 6 -1 -1 3 0 21 + 298 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 + 293 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 + 302 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 9 0 21 + 301 inst_AS_000_DMA 3 -1 1 2 1 7 -1 -1 7 0 21 + 334 SM_AMIGA_2_ 3 -1 0 2 0 5 -1 -1 5 0 21 + 304 CYCLE_DMA_1_ 3 -1 6 2 1 6 -1 -1 4 0 21 + 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 + 322 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 + 321 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 + 303 CYCLE_DMA_0_ 3 -1 6 2 1 6 -1 -1 3 0 21 + 331 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21 + 330 inst_DSACK1_INT 3 -1 5 2 5 7 -1 -1 2 0 21 + 318 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 312 inst_CLK_OUT_PRE_D 3 -1 3 2 1 6 -1 -1 1 0 21 + 311 inst_CLK_OUT_PRE_50 3 -1 6 2 3 6 -1 -1 1 0 21 + 306 CLK_000_D_3_ 3 -1 1 2 2 5 -1 -1 1 0 21 + 305 inst_VPA_D 3 -1 7 2 0 3 -1 -1 1 0 21 + 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 329 inst_CLK_030_H 3 -1 1 1 1 -1 -1 8 0 21 + 333 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 + 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 326 RST_DLY_0_ 3 -1 0 1 0 -1 -1 4 0 21 + 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 341 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 + 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 + 332 SM_AMIGA_5_ 3 -1 3 1 3 -1 -1 3 0 21 + 319 SM_AMIGA_1_ 3 -1 5 1 5 -1 -1 3 0 21 + 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 328 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21 + 327 RST_DLY_1_ 3 -1 0 1 0 -1 -1 2 1 21 + 320 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 + 317 CLK_000_D_4_ 3 -1 5 1 2 -1 -1 1 0 21 + 316 CLK_000_D_2_ 3 -1 7 1 1 -1 -1 1 0 21 + 315 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21 + 314 IPL_D0_1_ 3 -1 7 1 1 -1 -1 1 0 21 + 313 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 + 307 inst_DTACK_D0 3 -1 0 1 0 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 + 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 2 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 + 59 A_1_ 1 -1 -1 2 2 6 59 -1 + 55 IPL_1_ 1 -1 -1 2 1 7 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 10 CLK_000 1 -1 -1 2 0 5 10 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 63 CLK_030 1 -1 -1 1 1 63 -1 + 35 VPA 1 -1 -1 1 7 35 -1 + 29 DTACK 1 -1 -1 1 0 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 +116 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 -1 7 5 2 3 4 5 7 81 -1 1 0 21 + 41 AS_000 5 -1 4 5 0 4 5 6 7 41 -1 1 0 21 + 79 RW_000 5 339 7 3 4 5 6 79 -1 4 0 21 + 31 UDS_000 5 -1 3 3 5 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 5 6 7 30 -1 1 0 21 + 68 A_0_ 5 345 6 2 1 5 68 -1 3 0 21 + 70 RW 5 344 6 2 5 7 70 -1 2 0 21 + 78 SIZE_1_ 5 337 7 1 5 78 -1 3 0 21 + 69 SIZE_0_ 5 340 6 1 5 69 -1 3 0 21 + 40 BERR 5 -1 4 1 0 40 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 338 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 + 82 BGACK_030 5 342 7 0 82 -1 3 0 21 + 34 VMA 5 343 3 0 34 -1 3 0 21 65 E 0 6 0 65 -1 2 0 21 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 @@ -4300,63 +1508,184 @@ 2 RESET 0 1 0 2 -1 1 0 21 342 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 309 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 311 CLK_000_D_0_ 3 -1 3 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 310 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 324 SM_AMIGA_6_ 3 -1 5 4 1 2 5 7 -1 -1 3 0 21 - 326 SM_AMIGA_0_ 3 -1 0 3 0 5 7 -1 -1 4 0 21 + 311 CLK_000_D_0_ 3 -1 0 6 0 2 3 5 6 7 -1 -1 1 0 21 + 310 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 + 322 SM_AMIGA_6_ 3 -1 2 5 0 1 2 5 7 -1 -1 3 0 21 + 301 inst_BGACK_030_INT_D 3 -1 4 4 1 2 6 7 -1 -1 1 0 21 296 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 - 294 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 300 inst_BGACK_030_INT_D 3 -1 0 3 5 6 7 -1 -1 1 0 21 - 298 inst_AS_030_D0 3 -1 7 3 3 4 5 -1 -1 1 0 21 + 294 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 + 299 inst_AS_030_D0 3 -1 4 3 2 3 4 -1 -1 1 0 21 293 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 - 302 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 - 301 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21 - 299 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 - 327 RST_DLY_0_ 3 -1 6 2 1 6 -1 -1 4 0 21 - 320 SM_AMIGA_1_ 3 -1 0 2 0 5 -1 -1 4 0 21 - 304 CYCLE_DMA_1_ 3 -1 3 2 2 3 -1 -1 4 0 21 - 344 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 336 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 - 333 SM_AMIGA_5_ 3 -1 1 2 0 1 -1 -1 3 0 21 - 325 SM_AMIGA_4_ 3 -1 0 2 0 1 -1 -1 3 0 21 - 323 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 - 322 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21 - 303 CYCLE_DMA_0_ 3 -1 3 2 2 3 -1 -1 3 0 21 + 303 inst_DS_000_DMA 3 -1 5 2 0 5 -1 -1 9 0 21 + 302 inst_AS_000_DMA 3 -1 5 2 5 7 -1 -1 7 0 21 + 300 inst_AS_030_000_SYNC 3 -1 2 2 2 3 -1 -1 7 0 21 + 305 CYCLE_DMA_1_ 3 -1 6 2 5 6 -1 -1 4 0 21 + 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 + 335 SM_AMIGA_i_7_ 3 -1 2 2 2 7 -1 -1 3 1 21 + 325 SM_AMIGA_0_ 3 -1 7 2 2 7 -1 -1 3 0 21 + 324 SM_AMIGA_1_ 3 -1 0 2 0 7 -1 -1 3 0 21 + 323 SM_AMIGA_4_ 3 -1 0 2 0 5 -1 -1 3 0 21 + 320 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 + 319 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 + 304 CYCLE_DMA_0_ 3 -1 6 2 5 6 -1 -1 3 0 21 295 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21 - 332 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 - 331 inst_DSACK1_INT 3 -1 5 2 5 7 -1 -1 2 0 21 - 329 RST_DLY_2_ 3 -1 6 2 1 6 -1 -1 2 0 21 - 328 RST_DLY_1_ 3 -1 1 2 1 6 -1 -1 2 1 21 - 321 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 - 319 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 317 CLK_000_D_3_ 3 -1 0 2 0 5 -1 -1 1 0 21 - 313 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 - 307 CLK_000_D_4_ 3 -1 0 2 5 6 -1 -1 1 0 21 - 306 CLK_000_D_2_ 3 -1 7 2 0 5 -1 -1 1 0 21 - 305 inst_VPA_D 3 -1 2 2 0 3 -1 -1 1 0 21 - 348 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 347 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 339 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 330 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21 - 335 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 5 0 21 - 334 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 340 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 346 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 343 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 338 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 345 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 331 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 321 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 1 2 1 6 -1 -1 1 0 21 + 312 inst_CLK_OUT_PRE_50 3 -1 2 2 1 2 -1 -1 1 0 21 + 306 inst_VPA_D 3 -1 3 2 0 3 -1 -1 1 0 21 + 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 329 inst_CLK_030_H 3 -1 5 1 5 -1 -1 8 0 21 + 334 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 5 0 21 + 333 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 + 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 326 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 + 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 340 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 + 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 + 332 SM_AMIGA_5_ 3 -1 0 1 0 -1 -1 3 0 21 + 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 341 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 337 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 318 CLK_000_D_5_ 3 -1 6 1 5 -1 -1 1 0 21 - 316 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 - 315 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 330 inst_DSACK1_INT 3 -1 7 1 7 -1 -1 2 0 21 + 328 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 + 327 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 + 318 CLK_000_D_4_ 3 -1 2 1 2 -1 -1 1 0 21 + 317 CLK_000_D_2_ 3 -1 7 1 0 -1 -1 1 0 21 + 316 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21 + 315 IPL_D0_1_ 3 -1 0 1 1 -1 -1 1 0 21 314 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21 - 312 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 - 308 inst_DTACK_D0 3 -1 7 1 0 -1 -1 1 0 21 + 308 inst_DTACK_D0 3 -1 6 1 0 -1 -1 1 0 21 + 307 CLK_000_D_3_ 3 -1 0 1 2 -1 -1 1 0 21 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 + 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 3 67 -1 + 66 IPL_0_ 1 -1 -1 2 0 1 66 -1 + 55 IPL_1_ 1 -1 -1 2 0 1 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 63 CLK_030 1 -1 -1 1 5 63 -1 + 59 A_1_ 1 -1 -1 1 1 59 -1 + 35 VPA 1 -1 -1 1 3 35 -1 + 29 DTACK 1 -1 -1 1 6 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 0 10 -1 +116 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 -1 7 6 1 2 3 4 5 7 81 -1 1 0 21 + 79 RW_000 5 339 7 3 0 4 6 79 -1 4 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 70 RW 5 344 6 2 1 7 70 -1 2 0 21 + 40 BERR 5 -1 4 2 0 3 40 -1 1 0 21 + 78 SIZE_1_ 5 337 7 1 5 78 -1 3 0 21 + 69 SIZE_0_ 5 341 6 1 5 69 -1 3 0 21 + 68 A_0_ 5 345 6 1 5 68 -1 3 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 338 1 0 8 -1 9 0 21 + 7 IPL_030_0_ 5 347 1 0 7 -1 9 0 21 + 6 IPL_030_1_ 5 346 1 0 6 -1 9 0 21 + 82 BGACK_030 5 342 7 0 82 -1 3 0 21 + 34 VMA 5 343 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 340 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 80 DSACK1 0 7 0 80 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 342 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 309 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 311 CLK_000_D_0_ 3 -1 2 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 310 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 322 SM_AMIGA_6_ 3 -1 2 4 1 2 5 7 -1 -1 3 0 21 + 301 inst_BGACK_030_INT_D 3 -1 4 4 2 5 6 7 -1 -1 1 0 21 + 300 inst_AS_030_000_SYNC 3 -1 5 3 2 3 5 -1 -1 7 0 21 + 296 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 + 294 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 + 335 SM_AMIGA_i_7_ 3 -1 2 3 2 5 7 -1 -1 3 1 21 + 295 cpu_est_0_ 3 -1 6 3 0 3 6 -1 -1 3 0 21 + 299 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 + 293 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 1 1 21 + 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 334 SM_AMIGA_2_ 3 -1 0 2 0 5 -1 -1 5 0 21 + 333 SM_AMIGA_3_ 3 -1 3 2 0 3 -1 -1 5 0 21 + 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 + 332 SM_AMIGA_5_ 3 -1 2 2 2 3 -1 -1 3 0 21 + 325 SM_AMIGA_0_ 3 -1 7 2 2 7 -1 -1 3 0 21 + 324 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 323 SM_AMIGA_4_ 3 -1 3 2 1 3 -1 -1 3 0 21 + 320 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21 + 319 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 + 331 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 321 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 3 2 1 6 -1 -1 1 0 21 + 312 inst_CLK_OUT_PRE_50 3 -1 6 2 3 6 -1 -1 1 0 21 + 308 inst_DTACK_D0 3 -1 1 2 0 3 -1 -1 1 0 21 + 307 CLK_000_D_3_ 3 -1 3 2 1 2 -1 -1 1 0 21 + 306 inst_VPA_D 3 -1 0 2 0 3 -1 -1 1 0 21 + 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 + 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 + 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 + 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 329 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 326 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 + 305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 + 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 341 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 + 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 + 304 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 + 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 330 inst_DSACK1_INT 3 -1 7 1 7 -1 -1 2 0 21 + 328 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 + 327 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 + 318 CLK_000_D_4_ 3 -1 1 1 2 -1 -1 1 0 21 + 317 CLK_000_D_2_ 3 -1 7 1 3 -1 -1 1 0 21 + 316 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 315 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21 + 314 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 @@ -4364,17 +1693,261 @@ 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 - 66 IPL_0_ 1 -1 -1 2 0 1 66 -1 + 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 + 59 A_1_ 1 -1 -1 2 2 5 59 -1 + 55 IPL_1_ 1 -1 -1 2 1 3 55 -1 27 BGACK_000 1 -1 -1 2 4 7 27 -1 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 2 63 -1 - 59 A_1_ 1 -1 -1 1 6 59 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 2 35 -1 - 29 DTACK 1 -1 -1 1 7 29 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 63 CLK_030 1 -1 -1 1 0 63 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 29 DTACK 1 -1 -1 1 1 29 -1 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 3 10 -1 \ No newline at end of file + 10 CLK_000 1 -1 -1 1 2 10 -1 +116 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 -1 7 5 2 3 4 5 7 81 -1 1 0 21 + 41 AS_000 5 -1 4 5 0 4 5 6 7 41 -1 1 0 21 + 79 RW_000 5 339 7 3 4 5 6 79 -1 4 0 21 + 31 UDS_000 5 -1 3 3 5 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 5 6 7 30 -1 1 0 21 + 68 A_0_ 5 345 6 2 1 5 68 -1 3 0 21 + 70 RW 5 344 6 2 5 7 70 -1 2 0 21 + 78 SIZE_1_ 5 337 7 1 5 78 -1 3 0 21 + 69 SIZE_0_ 5 340 6 1 5 69 -1 3 0 21 + 40 BERR 5 -1 4 1 0 40 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 338 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 + 82 BGACK_030 5 342 7 0 82 -1 3 0 21 + 34 VMA 5 343 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 341 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 80 DSACK1 0 7 0 80 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 342 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 309 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 311 CLK_000_D_0_ 3 -1 0 6 0 2 3 5 6 7 -1 -1 1 0 21 + 310 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 + 322 SM_AMIGA_6_ 3 -1 2 5 0 1 2 5 7 -1 -1 3 0 21 + 301 inst_BGACK_030_INT_D 3 -1 4 4 1 2 6 7 -1 -1 1 0 21 + 296 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 + 294 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 + 299 inst_AS_030_D0 3 -1 4 3 2 3 4 -1 -1 1 0 21 + 293 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 + 303 inst_DS_000_DMA 3 -1 5 2 0 5 -1 -1 9 0 21 + 302 inst_AS_000_DMA 3 -1 5 2 5 7 -1 -1 7 0 21 + 300 inst_AS_030_000_SYNC 3 -1 2 2 2 3 -1 -1 7 0 21 + 305 CYCLE_DMA_1_ 3 -1 6 2 5 6 -1 -1 4 0 21 + 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 + 335 SM_AMIGA_i_7_ 3 -1 2 2 2 7 -1 -1 3 1 21 + 325 SM_AMIGA_0_ 3 -1 7 2 2 7 -1 -1 3 0 21 + 324 SM_AMIGA_1_ 3 -1 0 2 0 7 -1 -1 3 0 21 + 323 SM_AMIGA_4_ 3 -1 0 2 0 5 -1 -1 3 0 21 + 320 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 + 319 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 + 304 CYCLE_DMA_0_ 3 -1 6 2 5 6 -1 -1 3 0 21 + 295 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21 + 331 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 321 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 1 2 1 6 -1 -1 1 0 21 + 312 inst_CLK_OUT_PRE_50 3 -1 2 2 1 2 -1 -1 1 0 21 + 306 inst_VPA_D 3 -1 3 2 0 3 -1 -1 1 0 21 + 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 329 inst_CLK_030_H 3 -1 5 1 5 -1 -1 8 0 21 + 334 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 5 0 21 + 333 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 + 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 326 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 + 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 340 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 + 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 + 332 SM_AMIGA_5_ 3 -1 0 1 0 -1 -1 3 0 21 + 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 341 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 330 inst_DSACK1_INT 3 -1 7 1 7 -1 -1 2 0 21 + 328 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 + 327 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 + 318 CLK_000_D_4_ 3 -1 2 1 2 -1 -1 1 0 21 + 317 CLK_000_D_2_ 3 -1 7 1 0 -1 -1 1 0 21 + 316 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21 + 315 IPL_D0_1_ 3 -1 0 1 1 -1 -1 1 0 21 + 314 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21 + 308 inst_DTACK_D0 3 -1 6 1 0 -1 -1 1 0 21 + 307 CLK_000_D_3_ 3 -1 0 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 + 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 3 67 -1 + 66 IPL_0_ 1 -1 -1 2 0 1 66 -1 + 55 IPL_1_ 1 -1 -1 2 0 1 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 63 CLK_030 1 -1 -1 1 5 63 -1 + 59 A_1_ 1 -1 -1 1 1 59 -1 + 35 VPA 1 -1 -1 1 3 35 -1 + 29 DTACK 1 -1 -1 1 6 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 0 10 -1 +116 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 -1 7 6 1 2 3 4 5 7 81 -1 1 0 21 + 79 RW_000 5 339 7 3 0 4 6 79 -1 4 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 70 RW 5 344 6 2 1 7 70 -1 2 0 21 + 40 BERR 5 -1 4 2 0 3 40 -1 1 0 21 + 78 SIZE_1_ 5 337 7 1 5 78 -1 3 0 21 + 69 SIZE_0_ 5 341 6 1 5 69 -1 3 0 21 + 68 A_0_ 5 345 6 1 5 68 -1 3 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 338 1 0 8 -1 9 0 21 + 7 IPL_030_0_ 5 347 1 0 7 -1 9 0 21 + 6 IPL_030_1_ 5 346 1 0 6 -1 9 0 21 + 82 BGACK_030 5 342 7 0 82 -1 3 0 21 + 34 VMA 5 343 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 340 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 80 DSACK1 0 7 0 80 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 342 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 309 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 311 CLK_000_D_0_ 3 -1 2 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 310 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 322 SM_AMIGA_6_ 3 -1 2 4 1 2 5 7 -1 -1 3 0 21 + 301 inst_BGACK_030_INT_D 3 -1 4 4 2 5 6 7 -1 -1 1 0 21 + 300 inst_AS_030_000_SYNC 3 -1 5 3 2 3 5 -1 -1 7 0 21 + 296 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 + 294 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 + 335 SM_AMIGA_i_7_ 3 -1 2 3 2 5 7 -1 -1 3 1 21 + 295 cpu_est_0_ 3 -1 6 3 0 3 6 -1 -1 3 0 21 + 299 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 + 293 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 1 1 21 + 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 334 SM_AMIGA_2_ 3 -1 0 2 0 5 -1 -1 5 0 21 + 333 SM_AMIGA_3_ 3 -1 3 2 0 3 -1 -1 5 0 21 + 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 + 332 SM_AMIGA_5_ 3 -1 2 2 2 3 -1 -1 3 0 21 + 325 SM_AMIGA_0_ 3 -1 7 2 2 7 -1 -1 3 0 21 + 324 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 323 SM_AMIGA_4_ 3 -1 3 2 1 3 -1 -1 3 0 21 + 320 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21 + 319 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 + 331 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 321 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 3 2 1 6 -1 -1 1 0 21 + 312 inst_CLK_OUT_PRE_50 3 -1 6 2 3 6 -1 -1 1 0 21 + 308 inst_DTACK_D0 3 -1 1 2 0 3 -1 -1 1 0 21 + 307 CLK_000_D_3_ 3 -1 3 2 1 2 -1 -1 1 0 21 + 306 inst_VPA_D 3 -1 0 2 0 3 -1 -1 1 0 21 + 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 + 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 + 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 + 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 329 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 326 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 + 305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 + 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 341 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 + 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 + 304 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 + 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 330 inst_DSACK1_INT 3 -1 7 1 7 -1 -1 2 0 21 + 328 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 + 327 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 + 318 CLK_000_D_4_ 3 -1 1 1 2 -1 -1 1 0 21 + 317 CLK_000_D_2_ 3 -1 7 1 3 -1 -1 1 0 21 + 316 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 315 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21 + 314 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 + 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 + 59 A_1_ 1 -1 -1 2 2 5 59 -1 + 55 IPL_1_ 1 -1 -1 2 1 3 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 63 CLK_030 1 -1 -1 1 0 63 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 29 DTACK 1 -1 -1 1 1 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 2 10 -1 \ No newline at end of file diff --git a/Logic/68030_tk.plc b/Logic/68030_tk.plc index 54dc384..0e51750 100644 --- a/Logic/68030_tk.plc +++ b/Logic/68030_tk.plc @@ -8,7 +8,7 @@ ; Source file 68030_tk.tt4 ; FITTER-generated Placements. ; DEVICE mach447a -; DATE Thu Oct 06 22:04:16 2016 +; DATE Sat Oct 15 23:48:29 2016 Pin 4 AHIGH_31_ Comb ; S6=1 S9=1 Pair 143 @@ -23,33 +23,33 @@ Pin 31 LDS_000 Comb ; S6=1 S9=1 Pair 191 Pin 14 nEXP_SPACE Pin 41 BERR Comb ; S6=1 S9=1 Pair 197 Pin 21 BG_030 -Pin 28 BGACK_000 -Pin 64 CLK_030 Pin 5 AHIGH_30_ Comb ; S6=1 S9=1 Pair 125 -Pin 11 CLK_000 +Pin 28 BGACK_000 Pin 6 AHIGH_29_ Comb ; S6=1 S9=1 Pair 137 -Pin 61 CLK_OSZI +Pin 64 CLK_030 Pin 15 AHIGH_28_ Comb ; S6=1 S9=1 Pair 149 -Pin 65 CLK_DIV_OUT Reg ; S6=1 S9=1 Pair 247 +Pin 11 CLK_000 Pin 16 AHIGH_27_ Comb ; S6=1 S9=1 Pair 157 +Pin 61 CLK_OSZI Pin 17 AHIGH_26_ Comb ; S6=1 S9=1 Pair 155 -Pin 78 FPU_CS Comb ; S6=1 S9=1 Pair 271 +Pin 65 CLK_DIV_OUT Reg ; S6=1 S9=1 Pair 247 Pin 18 AHIGH_25_ Comb ; S6=1 S9=1 Pair 167 -Pin 91 FPU_SENSE Pin 19 AHIGH_24_ Comb ; S6=1 S9=1 Pair 161 -Pin 81 DSACK1 Comb ; S6=1 S9=1 Pair 283 +Pin 78 FPU_CS Comb ; S6=1 S9=1 Pair 271 Pin 84 A_DECODE_22_ -Pin 30 DTACK +Pin 91 FPU_SENSE Pin 94 A_DECODE_21_ -Pin 92 AVEC Comb ; S6=1 S9=1 Pair 107 +Pin 81 DSACK1 Comb ; S6=1 S9=1 Pair 283 Pin 93 A_DECODE_20_ -Pin 66 E Comb ; S6=1 S9=1 Pair 251 +Pin 30 DTACK Pin 97 A_DECODE_19_ -Pin 36 VPA +Pin 92 AVEC Comb ; S6=1 S9=1 Pair 107 Pin 95 A_DECODE_18_ +Pin 66 E Comb ; S6=1 S9=1 Pair 251 Pin 59 A_DECODE_17_ -Pin 86 RST +Pin 36 VPA Pin 96 A_DECODE_16_ +Pin 86 RST Pin 3 RESET Comb ; S6=1 S9=1 Pair 128 Pin 33 AMIGA_ADDR_ENABLE Comb ; S6=1 S9=1 Pair 181 Pin 48 AMIGA_BUS_DATA_DIR Comb ; S6=1 S9=1 Pair 199 @@ -64,8 +64,8 @@ Pin 79 SIZE_1_ Reg ; S6=1 S9=1 Pair 287 Pin 9 IPL_030_2_ Reg ; S6=1 S9=1 Pair 131 Pin 80 RW_000 Reg ; S6=1 S9=1 Pair 269 Pin 29 BG_000 Reg ; S6=1 S9=1 Pair 175 -Pin 83 BGACK_030 Reg ; S6=1 S9=1 Pair 275 Pin 70 SIZE_0_ Reg ; S6=1 S9=1 Pair 263 +Pin 83 BGACK_030 Reg ; S6=1 S9=1 Pair 275 Pin 10 CLK_EXP Reg ; S6=1 S9=1 Pair 127 Pin 35 VMA Reg ; S6=1 S9=1 Pair 173 Pin 71 RW Reg ; S6=1 S9=1 Pair 245 @@ -89,57 +89,56 @@ Node 287 RN_SIZE_1_ Reg ; S6=1 S9=1 Node 131 RN_IPL_030_2_ Reg ; S6=1 S9=1 Node 269 RN_RW_000 Reg ; S6=1 S9=1 Node 175 RN_BG_000 Reg ; S6=1 S9=1 -Node 275 RN_BGACK_030 Reg ; S6=1 S9=1 Node 263 RN_SIZE_0_ Reg ; S6=1 S9=1 +Node 275 RN_BGACK_030 Reg ; S6=1 S9=1 Node 173 RN_VMA Reg ; S6=1 S9=1 Node 245 RN_RW Reg ; S6=1 S9=1 Node 257 RN_A_0_ Reg ; S6=1 S9=1 Node 139 RN_IPL_030_1_ Reg ; S6=1 S9=1 Node 133 RN_IPL_030_0_ Reg ; S6=1 S9=1 -Node 176 cpu_est_2_ Reg ; S6=1 S9=1 -Node 119 cpu_est_3_ Reg ; S6=1 S9=1 -Node 194 cpu_est_0_ Reg ; S6=1 S9=1 -Node 193 cpu_est_1_ Reg ; S6=1 S9=1 -Node 254 inst_AMIGA_BUS_ENABLE_DMA_LOW Reg ; S6=1 S9=1 -Node 289 inst_AS_030_D0 Reg ; S6=1 S9=1 -Node 227 inst_AS_030_000_SYNC Reg ; S6=1 S9=1 -Node 103 inst_BGACK_030_INT_D Reg ; S6=1 S9=1 -Node 169 inst_AS_000_DMA Reg ; S6=1 S9=1 -Node 163 inst_DS_000_DMA Reg ; S6=1 S9=1 -Node 188 CYCLE_DMA_0_ Reg ; S6=1 S9=1 -Node 182 CYCLE_DMA_1_ Reg ; S6=1 S9=1 -Node 164 inst_VPA_D Reg ; S6=1 S9=1 -Node 272 CLK_000_D_2_ Reg ; S6=1 S9=1 -Node 104 CLK_000_D_4_ Reg ; S6=1 S9=1 -Node 278 inst_DTACK_D0 Reg ; S6=1 S9=1 +Node 119 cpu_est_2_ Reg ; S6=1 S9=1 +Node 187 cpu_est_3_ Reg ; S6=1 S9=1 +Node 259 cpu_est_0_ Reg ; S6=1 S9=1 +Node 113 cpu_est_1_ Reg ; S6=1 S9=1 +Node 170 inst_AMIGA_BUS_ENABLE_DMA_HIGH Reg ; S6=1 S9=1 +Node 223 inst_AMIGA_BUS_ENABLE_DMA_LOW Reg ; S6=1 S9=1 +Node 205 inst_AS_030_D0 Reg ; S6=1 S9=1 +Node 221 inst_AS_030_000_SYNC Reg ; S6=1 S9=1 +Node 209 inst_BGACK_030_INT_D Reg ; S6=1 S9=1 +Node 103 inst_AS_000_DMA Reg ; S6=1 S9=1 +Node 121 inst_DS_000_DMA Reg ; S6=1 S9=1 +Node 116 CYCLE_DMA_0_ Reg ; S6=1 S9=1 +Node 110 CYCLE_DMA_1_ Reg ; S6=1 S9=1 +Node 115 inst_VPA_D Reg ; S6=1 S9=1 +Node 188 CLK_000_D_3_ Reg ; S6=1 S9=1 +Node 134 inst_DTACK_D0 Reg ; S6=1 S9=1 Node 253 inst_RESET_OUT Reg ; S6=1 S9=1 Node 277 CLK_000_D_1_ Reg ; S6=1 S9=1 -Node 187 CLK_000_D_0_ Reg ; S6=1 S9=1 -Node 211 inst_CLK_OUT_PRE_50 Reg ; S6=1 S9=1 -Node 209 inst_CLK_OUT_PRE_D Reg ; S6=1 S9=1 -Node 122 IPL_D0_0_ Reg ; S6=1 S9=1 -Node 146 IPL_D0_1_ Reg ; S6=1 S9=1 -Node 266 IPL_D0_2_ Reg ; S6=1 S9=1 -Node 121 CLK_000_D_3_ Reg ; S6=1 S9=1 -Node 260 CLK_000_D_5_ Reg ; S6=1 S9=1 -Node 248 inst_AMIGA_BUS_ENABLE_DMA_HIGH Reg ; S6=1 S9=1 -Node 109 SM_AMIGA_1_ Reg ; S6=1 S9=1 -Node 223 inst_UDS_000_INT Reg ; S6=1 S9=1 -Node 134 inst_DS_000_ENABLE Reg ; S6=1 S9=1 -Node 152 inst_LDS_000_INT Reg ; S6=1 S9=1 -Node 221 SM_AMIGA_6_ Reg ; S6=1 S9=1 -Node 115 SM_AMIGA_4_ Reg ; S6=1 S9=1 -Node 113 SM_AMIGA_0_ Reg ; S6=1 S9=1 -Node 259 RST_DLY_0_ Reg ; S6=1 S9=1 -Node 140 RST_DLY_1_ Reg ; S6=1 S9=1 -Node 265 RST_DLY_2_ Reg ; S6=1 S9=1 -Node 170 inst_CLK_030_H Reg ; S6=1 S9=1 -Node 239 inst_DSACK1_INT Reg ; S6=1 S9=1 -Node 158 inst_AS_000_INT Reg ; S6=1 S9=1 -Node 145 SM_AMIGA_5_ Reg ; S6=1 S9=1 -Node 116 SM_AMIGA_3_ Reg ; S6=1 S9=1 -Node 110 SM_AMIGA_2_ Reg ; S6=1 S9=1 -Node 233 SM_AMIGA_i_7_ Reg ; S6=1 S9=1 -Node 205 CIIN_0 Comb ; S6=1 S9=1 +Node 163 CLK_000_D_0_ Reg ; S6=1 S9=1 +Node 265 inst_CLK_OUT_PRE_50 Reg ; S6=1 S9=1 +Node 182 inst_CLK_OUT_PRE_D Reg ; S6=1 S9=1 +Node 266 IPL_D0_0_ Reg ; S6=1 S9=1 +Node 194 IPL_D0_1_ Reg ; S6=1 S9=1 +Node 146 IPL_D0_2_ Reg ; S6=1 S9=1 +Node 278 CLK_000_D_2_ Reg ; S6=1 S9=1 +Node 140 CLK_000_D_4_ Reg ; S6=1 S9=1 +Node 233 inst_LDS_000_INT Reg ; S6=1 S9=1 +Node 145 inst_DS_000_ENABLE Reg ; S6=1 S9=1 +Node 239 inst_UDS_000_INT Reg ; S6=1 S9=1 +Node 169 SM_AMIGA_6_ Reg ; S6=1 S9=1 +Node 176 SM_AMIGA_4_ Reg ; S6=1 S9=1 +Node 227 SM_AMIGA_1_ Reg ; S6=1 S9=1 +Node 289 SM_AMIGA_0_ Reg ; S6=1 S9=1 +Node 248 RST_DLY_0_ Reg ; S6=1 S9=1 +Node 260 RST_DLY_1_ Reg ; S6=1 S9=1 +Node 254 RST_DLY_2_ Reg ; S6=1 S9=1 +Node 104 inst_CLK_030_H Reg ; S6=1 S9=1 +Node 272 inst_DSACK1_INT Reg ; S6=1 S9=1 +Node 164 inst_AS_000_INT Reg ; S6=1 S9=1 +Node 158 SM_AMIGA_5_ Reg ; S6=1 S9=1 +Node 193 SM_AMIGA_3_ Reg ; S6=1 S9=1 +Node 109 SM_AMIGA_2_ Reg ; S6=1 S9=1 +Node 152 SM_AMIGA_i_7_ Reg ; S6=1 S9=1 +Node 211 CIIN_0 Comb ; S6=1 S9=1 ; Unused Pins & Nodes ; -> None Found. diff --git a/Logic/68030_tk.prd b/Logic/68030_tk.prd index 0482085..3db660e 100644 --- a/Logic/68030_tk.prd +++ b/Logic/68030_tk.prd @@ -5,8 +5,8 @@ |--------------------------------------------| -Start: Thu Oct 06 22:04:16 2016 -End : Thu Oct 06 22:04:16 2016 $$$ Elapsed time: 00:00:00 +Start: Sat Oct 15 23:48:29 2016 +End : Sat Oct 15 23:48:29 2016 $$$ Elapsed time: 00:00:00 =========================================================================== Part [E:/ispLEVER_Classic2_0/ispcpld/dat/mach4a/mach447a] Design [68030_tk.tt4] @@ -21,16 +21,16 @@ Part [E:/ispLEVER_Classic2_0/ispcpld/dat/mach4a/mach447a] Design [68030_tk.tt4] | | +- Signals to Place | | +----- Logic Array Inputs | | | +- Placed | | | +- Array Inputs Used _|____|____|____|_______________|____|_____________|___|________________ - 0 | 16 | 12 | 12 => 100% | 8 | 8 => 100% | 33 | 25 => 75% - 1 | 16 | 12 | 12 => 100% | 8 | 8 => 100% | 33 | 25 => 75% - 2 | 16 | 12 | 12 => 100% | 8 | 7 => 87% | 33 | 25 => 75% - 3 | 16 | 12 | 12 => 100% | 8 | 8 => 100% | 33 | 24 => 72% + 0 | 16 | 11 | 11 => 100% | 8 | 8 => 100% | 33 | 27 => 81% + 1 | 16 | 12 | 12 => 100% | 8 | 8 => 100% | 33 | 23 => 69% + 2 | 16 | 12 | 12 => 100% | 8 | 7 => 87% | 33 | 20 => 60% + 3 | 16 | 12 | 12 => 100% | 8 | 8 => 100% | 33 | 29 => 87% 4 | 16 | 7 | 7 => 100% | 8 | 4 => 50% | 33 | 30 => 90% 5 | 16 | 5 | 5 => 100% | 8 | 5 => 62% | 33 | 26 => 78% - 6 | 16 | 12 | 12 => 100% | 8 | 7 => 87% | 33 | 25 => 75% + 6 | 16 | 12 | 12 => 100% | 8 | 7 => 87% | 33 | 23 => 69% 7 | 16 | 10 | 10 => 100% | 8 | 8 => 100% | 33 | 28 => 84% ---|----|----|------------|-------|------------|-----|------------------ - | Avg number of array inputs in used blocks : 26.00 => 78% + | Avg number of array inputs in used blocks : 25.75 => 78% * Input/Clock Signal count: 24 -> placed: 24 = 100% @@ -41,13 +41,13 @@ _|____|____|____|_______________|____|_____________|___|________________ Clock Only Pins : 0 0 => 0% Clock/Input Pins : 4 4 => 100% Logic Blocks : 8 8 => 100% - Macrocells : 128 82 => 64% - PT Clusters : 128 52 => 40% - - Single PT Clusters : 128 38 => 29% + Macrocells : 128 81 => 63% + PT Clusters : 128 51 => 39% + - Single PT Clusters : 128 37 => 28% Input Registers : 0 * Routing Completion: 100% -* Attempts: Place [ 117] Route [ 0] +* Attempts: Place [ 116] Route [ 0] =========================================================================== Signal Fanout Table =========================================================================== @@ -69,12 +69,12 @@ ___|__|__|____|____________________________________________________________ 10| 4|OUT| 48|=> ....|....| AMIGA_BUS_DATA_DIR 11| 3|OUT| 34|=> ....|....| AMIGA_BUS_ENABLE_HIGH 12| 2|OUT| 20|=> ....|....| AMIGA_BUS_ENABLE_LOW - 13| 4| IO| 42|=> 0.23|4..7| AS_000 - 14| 7| IO| 82|=> .12.|45.7| AS_030 + 13| 4| IO| 42|=> 0...|4..7| AS_000 + 14| 7| IO| 82|=> .123|45.7| AS_030 15| 0|OUT| 92|=> ....|....| AVEC - 16| 6| IO| 69|=> ..2.|.5..| A_0_ + 16| 6| IO| 69|=> ....|.5..| A_0_ |=> Paired w/: RN_A_0_ - 17| 5|INP| 60|=> ....|..6.| A_1_ + 17| 5|INP| 60|=> ..2.|.5..| A_1_ 18| 0|INP| 96|=> ....|45.7| A_DECODE_16_ 19| 5|INP| 59|=> ....|45.7| A_DECODE_17_ 20| 0|INP| 95|=> ....|45.7| A_DECODE_18_ @@ -83,7 +83,7 @@ ___|__|__|____|____________________________________________________________ 23| 0|INP| 94|=> ....|4...| A_DECODE_21_ 24| 7|INP| 84|=> ....|4...| A_DECODE_22_ 25| 7|INP| 85|=> ....|4...| A_DECODE_23_ - 26| 4| IO| 41|=> 0...|....| BERR + 26| 4| IO| 41|=> 0..3|....| BERR 27| 3|INP| 28|=> ....|4..7| BGACK_000 28| 7| IO| 83|=> ....|....| BGACK_030 |=> Paired w/: RN_BGACK_030 @@ -92,110 +92,109 @@ ___|__|__|____|____________________________________________________________ 30| 2|INP| 21|=> ...3|....| BG_030 31| 4|OUT| 47|=> ....|....| CIIN 32| 4|NOD| . |=> ....|4...| CIIN_0 - 33| +|INP| 11|=> ...3|....| CLK_000 - 34| 3|NOD| . |=> 0123|.567| CLK_000_D_0_ + 33| +|INP| 11|=> ..2.|....| CLK_000 + 34| 2|NOD| . |=> 0123|.567| CLK_000_D_0_ 35| 7|NOD| . |=> 0123|.567| CLK_000_D_1_ - 36| 7|NOD| . |=> 0...|.5..| CLK_000_D_2_ - 37| 0|NOD| . |=> 0...|.5..| CLK_000_D_3_ - 38| 0|NOD| . |=> ....|.56.| CLK_000_D_4_ - 39| 6|NOD| . |=> ....|.5..| CLK_000_D_5_ - 40| +|INP| 64|=> ..2.|....| CLK_030 - 41| 6|OUT| 65|=> ....|....| CLK_DIV_OUT - 42| 1|OUT| 10|=> ....|....| CLK_EXP - 43| +|Cin| 61|=> ....|....| CLK_OSZI - 44| 3|NOD| . |=> ..23|....| CYCLE_DMA_0_ - 45| 3|NOD| . |=> ..23|....| CYCLE_DMA_1_ - 46| 7|OUT| 81|=> ....|....| DSACK1 - 47| 0|OUT| 98|=> ....|....| DS_030 - 48| 3|INP| 30|=> ....|...7| DTACK - 49| 6|OUT| 66|=> ....|....| E - 50| 5|INP| 57|=> ....|45.7| FC_0_ - 51| 5|INP| 58|=> ....|45.7| FC_1_ - 52| 7|OUT| 78|=> ....|....| FPU_CS - 53| 0|INP| 91|=> ....|4..7| FPU_SENSE - 54| 1| IO| 8|=> ....|....| IPL_030_0_ + 36| 7|NOD| . |=> ...3|....| CLK_000_D_2_ + 37| 3|NOD| . |=> .12.|....| CLK_000_D_3_ + 38| 1|NOD| . |=> ..2.|....| CLK_000_D_4_ + 39| +|INP| 64|=> 0...|....| CLK_030 + 40| 6|OUT| 65|=> ....|....| CLK_DIV_OUT + 41| 1|OUT| 10|=> ....|....| CLK_EXP + 42| +|Cin| 61|=> ....|....| CLK_OSZI + 43| 0|NOD| . |=> 0...|....| CYCLE_DMA_0_ + 44| 0|NOD| . |=> 0...|....| CYCLE_DMA_1_ + 45| 7|OUT| 81|=> ....|....| DSACK1 + 46| 0|OUT| 98|=> ....|....| DS_030 + 47| 3|INP| 30|=> .1..|....| DTACK + 48| 6|OUT| 66|=> ....|....| E + 49| 5|INP| 57|=> ....|45.7| FC_0_ + 50| 5|INP| 58|=> ....|45.7| FC_1_ + 51| 7|OUT| 78|=> ....|....| FPU_CS + 52| 0|INP| 91|=> ....|4..7| FPU_SENSE + 53| 1| IO| 8|=> ....|....| IPL_030_0_ |=> Paired w/: RN_IPL_030_0_ - 55| 1| IO| 7|=> ....|....| IPL_030_1_ + 54| 1| IO| 7|=> ....|....| IPL_030_1_ |=> Paired w/: RN_IPL_030_1_ - 56| 1| IO| 9|=> ....|....| IPL_030_2_ + 55| 1| IO| 9|=> ....|....| IPL_030_2_ |=> Paired w/: RN_IPL_030_2_ - 57| 6|INP| 67|=> 01..|....| IPL_0_ - 58| 5|INP| 56|=> .1..|....| IPL_1_ - 59| 6|INP| 68|=> .1..|..6.| IPL_2_ - 60| 0|NOD| . |=> .1..|....| IPL_D0_0_ - 61| 1|NOD| . |=> .1..|....| IPL_D0_1_ - 62| 6|NOD| . |=> .1..|....| IPL_D0_2_ - 63| 3| IO| 31|=> ..2.|..67| LDS_000 - 64| 1|OUT| 3|=> ....|....| RESET - 65| 6|NOD| . |=> ....|..6.| RN_A_0_ + 56| 6|INP| 67|=> .1..|..6.| IPL_0_ + 57| 5|INP| 56|=> .1.3|....| IPL_1_ + 58| 6|INP| 68|=> .1..|....| IPL_2_ + 59| 6|NOD| . |=> .1..|....| IPL_D0_0_ + 60| 3|NOD| . |=> .1..|....| IPL_D0_1_ + 61| 1|NOD| . |=> .1..|....| IPL_D0_2_ + 62| 3| IO| 31|=> 0...|..67| LDS_000 + 63| 1|OUT| 3|=> ....|....| RESET + 64| 6|NOD| . |=> ....|..6.| RN_A_0_ |=> Paired w/: A_0_ - 66| 7|NOD| . |=> 0123|4567| RN_BGACK_030 + 65| 7|NOD| . |=> 0123|4567| RN_BGACK_030 |=> Paired w/: BGACK_030 - 67| 3|NOD| . |=> ...3|....| RN_BG_000 + 66| 3|NOD| . |=> ...3|....| RN_BG_000 |=> Paired w/: BG_000 - 68| 1|NOD| . |=> .1..|....| RN_IPL_030_0_ + 67| 1|NOD| . |=> .1..|....| RN_IPL_030_0_ |=> Paired w/: IPL_030_0_ - 69| 1|NOD| . |=> .1..|....| RN_IPL_030_1_ + 68| 1|NOD| . |=> .1..|....| RN_IPL_030_1_ |=> Paired w/: IPL_030_1_ - 70| 1|NOD| . |=> .1..|....| RN_IPL_030_2_ + 69| 1|NOD| . |=> .1..|....| RN_IPL_030_2_ |=> Paired w/: IPL_030_2_ - 71| 6|NOD| . |=> ....|..6.| RN_RW + 70| 6|NOD| . |=> ....|..6.| RN_RW |=> Paired w/: RW - 72| 7|NOD| . |=> ....|...7| RN_RW_000 + 71| 7|NOD| . |=> ....|...7| RN_RW_000 |=> Paired w/: RW_000 - 73| 6|NOD| . |=> ....|..6.| RN_SIZE_0_ + 72| 6|NOD| . |=> ....|..6.| RN_SIZE_0_ |=> Paired w/: SIZE_0_ - 74| 7|NOD| . |=> ....|...7| RN_SIZE_1_ + 73| 7|NOD| . |=> ....|...7| RN_SIZE_1_ |=> Paired w/: SIZE_1_ - 75| 3|NOD| . |=> 0..3|....| RN_VMA + 74| 3|NOD| . |=> 0..3|....| RN_VMA |=> Paired w/: VMA - 76| +|INP| 86|=> 0123|.567| RST - 77| 6|NOD| . |=> .1..|..6.| RST_DLY_0_ - 78| 1|NOD| . |=> .1..|..6.| RST_DLY_1_ - 79| 6|NOD| . |=> .1..|..6.| RST_DLY_2_ - 80| 6| IO| 71|=> .1..|...7| RW + 75| +|INP| 86|=> 0123|4567| RST + 76| 6|NOD| . |=> ....|..6.| RST_DLY_0_ + 77| 6|NOD| . |=> ....|..6.| RST_DLY_1_ + 78| 6|NOD| . |=> ....|..6.| RST_DLY_2_ + 79| 6| IO| 71|=> .1..|...7| RW |=> Paired w/: RN_RW - 81| 7| IO| 80|=> ..2.|4.6.| RW_000 + 80| 7| IO| 80|=> 0...|4.6.| RW_000 |=> Paired w/: RN_RW_000 - 82| 6| IO| 70|=> ..2.|....| SIZE_0_ + 81| 6| IO| 70|=> ....|.5..| SIZE_0_ |=> Paired w/: RN_SIZE_0_ - 83| 7| IO| 79|=> ..2.|....| SIZE_1_ + 82| 7| IO| 79|=> ....|.5..| SIZE_1_ |=> Paired w/: RN_SIZE_1_ - 84| 0|NOD| . |=> 0...|.5.7| SM_AMIGA_0_ - 85| 0|NOD| . |=> 0...|.5..| SM_AMIGA_1_ - 86| 0|NOD| . |=> 0...|....| SM_AMIGA_2_ - 87| 0|NOD| . |=> 0...|....| SM_AMIGA_3_ - 88| 0|NOD| . |=> 01..|....| SM_AMIGA_4_ - 89| 1|NOD| . |=> 01..|....| SM_AMIGA_5_ - 90| 5|NOD| . |=> .12.|.5.7| SM_AMIGA_6_ - 91| 5|NOD| . |=> ....|.5.7| SM_AMIGA_i_7_ - 92| 3| IO| 32|=> ..2.|..67| UDS_000 - 93| 3| IO| 35|=> ....|....| VMA + 83| 7|NOD| . |=> ..2.|...7| SM_AMIGA_0_ + 84| 5|NOD| . |=> ....|.5.7| SM_AMIGA_1_ + 85| 0|NOD| . |=> 0...|.5..| SM_AMIGA_2_ + 86| 3|NOD| . |=> 0..3|....| SM_AMIGA_3_ + 87| 3|NOD| . |=> .1.3|....| SM_AMIGA_4_ + 88| 2|NOD| . |=> ..23|....| SM_AMIGA_5_ + 89| 2|NOD| . |=> .12.|.5.7| SM_AMIGA_6_ + 90| 2|NOD| . |=> ..2.|.5.7| SM_AMIGA_i_7_ + 91| 3| IO| 32|=> 0...|..67| UDS_000 + 92| 3| IO| 35|=> ....|....| VMA |=> Paired w/: RN_VMA - 94| +|INP| 36|=> ..2.|....| VPA - 95| 3|NOD| . |=> 0..3|....| cpu_est_0_ - 96| 3|NOD| . |=> 0..3|..6.| cpu_est_1_ - 97| 3|NOD| . |=> 0..3|..6.| cpu_est_2_ - 98| 0|NOD| . |=> 0..3|..6.| cpu_est_3_ - 99| 6|NOD| . |=> ...3|..6.| inst_AMIGA_BUS_ENABLE_DMA_HIGH - 100| 6|NOD| . |=> ..2.|..6.| inst_AMIGA_BUS_ENABLE_DMA_LOW - 101| 2|NOD| . |=> ..2.|...7| inst_AS_000_DMA - 102| 2|NOD| . |=> ..2.|4...| inst_AS_000_INT - 103| 5|NOD| . |=> ...3|.5..| inst_AS_030_000_SYNC - 104| 7|NOD| . |=> ...3|45..| inst_AS_030_D0 - 105| 0|NOD| . |=> ....|.567| inst_BGACK_030_INT_D - 106| 2|NOD| . |=> ..2.|....| inst_CLK_030_H - 107| 4|NOD| . |=> ....|4...| inst_CLK_OUT_PRE_50 - 108| 4|NOD| . |=> .1..|..6.| inst_CLK_OUT_PRE_D - 109| 5|NOD| . |=> ....|.5.7| inst_DSACK1_INT - 110| 2|NOD| . |=> 0.2.|....| inst_DS_000_DMA - 111| 1|NOD| . |=> .1.3|....| inst_DS_000_ENABLE - 112| 7|NOD| . |=> 0...|....| inst_DTACK_D0 - 113| 2|NOD| . |=> ..23|....| inst_LDS_000_INT - 114| 6|NOD| . |=> 0123|4.67| inst_RESET_OUT - 115| 5|NOD| . |=> ...3|.5..| inst_UDS_000_INT - 116| 2|NOD| . |=> 0..3|....| inst_VPA_D - 117| +|INP| 14|=> 0123|4567| nEXP_SPACE + 93| +|INP| 36|=> 0...|....| VPA + 94| 6|NOD| . |=> 0..3|..6.| cpu_est_0_ + 95| 0|NOD| . |=> 0..3|..6.| cpu_est_1_ + 96| 0|NOD| . |=> 0..3|..6.| cpu_est_2_ + 97| 3|NOD| . |=> 0..3|..6.| cpu_est_3_ + 98| 2|NOD| . |=> ..23|....| inst_AMIGA_BUS_ENABLE_DMA_HIGH + 99| 5|NOD| . |=> ..2.|.5..| inst_AMIGA_BUS_ENABLE_DMA_LOW + 100| 0|NOD| . |=> 0...|...7| inst_AS_000_DMA + 101| 2|NOD| . |=> ..2.|4...| inst_AS_000_INT + 102| 5|NOD| . |=> ..23|.5..| inst_AS_030_000_SYNC + 103| 4|NOD| . |=> ...3|45..| inst_AS_030_D0 + 104| 4|NOD| . |=> ..2.|.567| inst_BGACK_030_INT_D + 105| 0|NOD| . |=> 0...|....| inst_CLK_030_H + 106| 6|NOD| . |=> ...3|..6.| inst_CLK_OUT_PRE_50 + 107| 3|NOD| . |=> .1..|..6.| inst_CLK_OUT_PRE_D + 108| 7|NOD| . |=> ....|...7| inst_DSACK1_INT + 109| 0|NOD| . |=> 0...|....| inst_DS_000_DMA + 110| 1|NOD| . |=> .1.3|....| inst_DS_000_ENABLE + 111| 1|NOD| . |=> 0..3|....| inst_DTACK_D0 + 112| 5|NOD| . |=> ...3|.5..| inst_LDS_000_INT + 113| 6|NOD| . |=> 0123|4.67| inst_RESET_OUT + 114| 5|NOD| . |=> ...3|.5..| inst_UDS_000_INT + 115| 0|NOD| . |=> 0..3|....| inst_VPA_D + 116| +|INP| 14|=> 0123|4567| nEXP_SPACE --------------------------------------------------------------------------- =========================================================================== < E:/ispLEVER_Classic2_0/ispcpld/dat/mach4a/mach447a Device Pin Assignments > @@ -315,21 +314,21 @@ ____|_____|_________|______________________________________________________ | Sig Type-+ | | | | | | | XOR to Mcell Assignment | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ - 0| DS_030|OUT| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig - 1|inst_BGACK_030_INT_D|NOD| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig - 2| CLK_000_D_4_|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig + 0| DS_030|OUT| | S | 1 | 4 to [ 1]| 1 XOR to [ 0] for 1 PT sig + 1|inst_AS_000_DMA|NOD| | S | 7 | 4 to [ 1]| 1 XOR to [ 1] as logic PT + 2|inst_CLK_030_H|NOD| | S | 8 | 4 to [ 2]| 1 XOR to [ 2] as logic PT 3| | ? | | S | | 4 free | 1 XOR free - 4| AVEC|OUT| | S | 1 | 4 free | 1 XOR to [ 4] for 1 PT sig - 5| SM_AMIGA_1_|NOD| | S | 4 | 4 to [ 5]| 1 XOR free - 6| SM_AMIGA_2_|NOD| | S | 5 | 4 to [ 6]| 1 XOR to [ 6] as logic PT + 4| AVEC|OUT| | S | 1 | 4 to [ 2]| 1 XOR to [ 4] for 1 PT sig + 5| SM_AMIGA_2_|NOD| | S | 5 | 4 to [ 5]| 1 XOR to [ 5] as logic PT + 6| CYCLE_DMA_1_|NOD| | S | 4 | 4 to [ 6]| 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free - 8| SM_AMIGA_0_|NOD| | S | 4 | 4 to [ 8]| 1 XOR free - 9| SM_AMIGA_4_|NOD| | S | 3 | 4 to [ 9]| 1 XOR free -10| SM_AMIGA_3_|NOD| | S | 5 | 4 to [10]| 1 XOR to [10] as logic PT + 8| cpu_est_1_|NOD| | S | 4 | 4 free | 1 XOR free + 9| inst_VPA_D|NOD| | S | 1 | 4 to [ 8]| 1 XOR to [ 9] for 1 PT sig +10| CYCLE_DMA_0_|NOD| | S | 3 | 4 to [10]| 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free -12| cpu_est_3_|NOD| | S | 4 | 4 to [12]| 1 XOR free -13| CLK_000_D_3_|NOD| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig -14| IPL_D0_0_|NOD| | S | 1 | 4 free | 1 XOR to [14] for 1 PT sig +12| cpu_est_2_|NOD| | S | 1 :+: 1| 4 to [12]| 1 XOR to [12] +13|inst_DS_000_DMA|NOD| | S | 9 | 4 to [13]| 1 XOR to [13] as logic PT +14| | ? | | S | | 4 to [13]| 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== @@ -342,22 +341,22 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| DS_030|OUT| | S | 1 |=> can support up to [ 13] logic PT(s) - 1|inst_BGACK_030_INT_D|NOD| | S | 1 |=> can support up to [ 18] logic PT(s) - 2| CLK_000_D_4_|NOD| | S | 1 |=> can support up to [ 18] logic PT(s) - 3| | ? | | S | |=> can support up to [ 13] logic PT(s) - 4| AVEC|OUT| | S | 1 |=> can support up to [ 10] logic PT(s) - 5| SM_AMIGA_1_|NOD| | S | 4 |=> can support up to [ 14] logic PT(s) - 6| SM_AMIGA_2_|NOD| | S | 5 |=> can support up to [ 10] logic PT(s) - 7| | ? | | S | |=> can support up to [ 5] logic PT(s) - 8| SM_AMIGA_0_|NOD| | S | 4 |=> can support up to [ 10] logic PT(s) - 9| SM_AMIGA_4_|NOD| | S | 3 |=> can support up to [ 10] logic PT(s) -10| SM_AMIGA_3_|NOD| | S | 5 |=> can support up to [ 10] logic PT(s) -11| | ? | | S | |=> can support up to [ 9] logic PT(s) -12| cpu_est_3_|NOD| | S | 4 |=> can support up to [ 18] logic PT(s) -13| CLK_000_D_3_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) -14| IPL_D0_0_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) -15| | ? | | S | |=> can support up to [ 9] logic PT(s) + 0| DS_030|OUT| | S | 1 |=> can support up to [ 1] logic PT(s) + 1|inst_AS_000_DMA|NOD| | S | 7 |=> can support up to [ 14] logic PT(s) + 2|inst_CLK_030_H|NOD| | S | 8 |=> can support up to [ 14] logic PT(s) + 3| | ? | | S | |=> can support up to [ 5] logic PT(s) + 4| AVEC|OUT| | S | 1 |=> can support up to [ 6] logic PT(s) + 5| SM_AMIGA_2_|NOD| | S | 5 |=> can support up to [ 10] logic PT(s) + 6| CYCLE_DMA_1_|NOD| | S | 4 |=> can support up to [ 15] logic PT(s) + 7| | ? | | S | |=> can support up to [ 10] logic PT(s) + 8| cpu_est_1_|NOD| | S | 4 |=> can support up to [ 14] logic PT(s) + 9| inst_VPA_D|NOD| | S | 1 |=> can support up to [ 11] logic PT(s) +10| CYCLE_DMA_0_|NOD| | S | 3 |=> can support up to [ 10] logic PT(s) +11| | ? | | S | |=> can support up to [ 5] logic PT(s) +12| cpu_est_2_|NOD| | S | 1 :+: 1|=> can support up to [ 9] logic PT(s) +13|inst_DS_000_DMA|NOD| | S | 9 |=> can support up to [ 15] logic PT(s) +14| | ? | | S | |=> can support up to [ 6] logic PT(s) +15| | ? | | S | |=> can support up to [ 5] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 0] > Node-Pin Assignments @@ -368,20 +367,20 @@ _|_________________|__|__|___|_____|_______________________________________ | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ 0| DS_030|OUT| | => | 5 6 ( 7) 0 | 96 97 ( 98) 91 - 1|inst_BGACK_030_INT_D|NOD| | => | 5 6 7 0 | 96 97 98 91 - 2| CLK_000_D_4_|NOD| | => | 6 7 0 1 | 97 98 91 92 + 1|inst_AS_000_DMA|NOD| | => | 5 6 7 0 | 96 97 98 91 + 2|inst_CLK_030_H|NOD| | => | 6 7 0 1 | 97 98 91 92 3| | | | => | 6 7 0 1 | 97 98 91 92 4| AVEC|OUT| | => | 7 0 ( 1) 2 | 98 91 ( 92) 93 - 5| SM_AMIGA_1_|NOD| | => | 7 0 1 2 | 98 91 92 93 - 6| SM_AMIGA_2_|NOD| | => | 0 1 2 3 | 91 92 93 94 + 5| SM_AMIGA_2_|NOD| | => | 7 0 1 2 | 98 91 92 93 + 6| CYCLE_DMA_1_|NOD| | => | 0 1 2 3 | 91 92 93 94 7| | | | => | 0 1 2 3 | 91 92 93 94 - 8| SM_AMIGA_0_|NOD| | => | 1 2 3 4 | 92 93 94 95 - 9| SM_AMIGA_4_|NOD| | => | 1 2 3 4 | 92 93 94 95 -10| SM_AMIGA_3_|NOD| | => | 2 3 4 5 | 93 94 95 96 + 8| cpu_est_1_|NOD| | => | 1 2 3 4 | 92 93 94 95 + 9| inst_VPA_D|NOD| | => | 1 2 3 4 | 92 93 94 95 +10| CYCLE_DMA_0_|NOD| | => | 2 3 4 5 | 93 94 95 96 11| | | | => | 2 3 4 5 | 93 94 95 96 -12| cpu_est_3_|NOD| | => | 3 4 5 6 | 94 95 96 97 -13| CLK_000_D_3_|NOD| | => | 3 4 5 6 | 94 95 96 97 -14| IPL_D0_0_|NOD| | => | 4 5 6 7 | 95 96 97 98 +12| cpu_est_2_|NOD| | => | 3 4 5 6 | 94 95 96 97 +13|inst_DS_000_DMA|NOD| | => | 3 4 5 6 | 94 95 96 97 +14| | | | => | 4 5 6 7 | 95 96 97 98 15| | | | => | 4 5 6 7 | 95 96 97 98 --------------------------------------------------------------------------- =========================================================================== @@ -432,41 +431,41 @@ IMX No. | +---- Block IO Pin or Macrocell Number 0 [IOpin 0 | 91|INP FPU_SENSE|*|*] [RegIn 0 |102| -| | ] [MCell 0 |101|OUT DS_030| | ] - [MCell 1 |103|NOD inst_BGACK_030_INT_D| |*] + [MCell 1 |103|NOD inst_AS_000_DMA| |*] 1 [IOpin 1 | 92|OUT AVEC|*| ] [RegIn 1 |105| -| | ] - [MCell 2 |104|NOD CLK_000_D_4_| |*] + [MCell 2 |104|NOD inst_CLK_030_H| |*] [MCell 3 |106| -| | ] 2 [IOpin 2 | 93|INP A_DECODE_20_|*|*] [RegIn 2 |108| -| | ] [MCell 4 |107|OUT AVEC| | ] - [MCell 5 |109|NOD SM_AMIGA_1_| |*] + [MCell 5 |109|NOD SM_AMIGA_2_| |*] 3 [IOpin 3 | 94|INP A_DECODE_21_|*|*] [RegIn 3 |111| -| | ] - [MCell 6 |110|NOD SM_AMIGA_2_| |*] + [MCell 6 |110|NOD CYCLE_DMA_1_| |*] [MCell 7 |112| -| | ] 4 [IOpin 4 | 95|INP A_DECODE_18_|*|*] [RegIn 4 |114| -| | ] - [MCell 8 |113|NOD SM_AMIGA_0_| |*] - [MCell 9 |115|NOD SM_AMIGA_4_| |*] + [MCell 8 |113|NOD cpu_est_1_| |*] + [MCell 9 |115|NOD inst_VPA_D| |*] 5 [IOpin 5 | 96|INP A_DECODE_16_|*|*] [RegIn 5 |117| -| | ] - [MCell 10 |116|NOD SM_AMIGA_3_| |*] + [MCell 10 |116|NOD CYCLE_DMA_0_| |*] [MCell 11 |118| -| | ] 6 [IOpin 6 | 97|INP A_DECODE_19_|*|*] [RegIn 6 |120| -| | ] - [MCell 12 |119|NOD cpu_est_3_| |*] - [MCell 13 |121|NOD CLK_000_D_3_| |*] + [MCell 12 |119|NOD cpu_est_2_| |*] + [MCell 13 |121|NOD inst_DS_000_DMA| |*] 7 [IOpin 7 | 98|OUT DS_030|*| ] [RegIn 7 |123| -| | ] - [MCell 14 |122|NOD IPL_D0_0_| |*] + [MCell 14 |122| -| | ] [MCell 15 |124| -| | ] --------------------------------------------------------------------------- =========================================================================== @@ -475,39 +474,39 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| IOPin 6 2 ( 67)| IPL_0_ -Mux01| IOPin 4 0 ( 41)| BERR -Mux02| Mcel 0 5 ( 109)| SM_AMIGA_1_ -Mux03| Mcel 2 9 ( 163)| inst_DS_000_DMA -Mux04| Mcel 7 2 ( 272)| CLK_000_D_2_ +Mux00| Input Pin ( 86)| RST +Mux01| Mcel 3 0 ( 173)| RN_VMA +Mux02| Mcel 0 9 ( 115)| inst_VPA_D +Mux03| Mcel 0 8 ( 113)| cpu_est_1_ +Mux04| Input Pin ( 64)| CLK_030 Mux05| Input Pin ( 14)| nEXP_SPACE -Mux06| ... | ... -Mux07| Mcel 7 6 ( 278)| inst_DTACK_D0 -Mux08| Mcel 2 10 ( 164)| inst_VPA_D -Mux09| Mcel 0 12 ( 119)| cpu_est_3_ -Mux10| Mcel 0 6 ( 110)| SM_AMIGA_2_ -Mux11| ... | ... -Mux12| Mcel 3 9 ( 187)| CLK_000_D_0_ +Mux06| IOPin 7 5 ( 80)| RW_000 +Mux07| Mcel 3 9 ( 187)| cpu_est_3_ +Mux08| IOPin 3 3 ( 32)| UDS_000 +Mux09| Mcel 0 1 ( 103)| inst_AS_000_DMA +Mux10| Input Pin ( 36)| VPA +Mux11| Mcel 1 6 ( 134)| inst_DTACK_D0 +Mux12| Mcel 6 9 ( 259)| cpu_est_0_ Mux13| Mcel 7 5 ( 277)| CLK_000_D_1_ -Mux14| Mcel 0 10 ( 116)| SM_AMIGA_3_ -Mux15| ... | ... -Mux16| Mcel 3 2 ( 176)| cpu_est_2_ -Mux17| Mcel 3 14 ( 194)| cpu_est_0_ -Mux18| Mcel 3 0 ( 173)| RN_VMA -Mux19| Mcel 0 9 ( 115)| SM_AMIGA_4_ +Mux14| Mcel 0 10 ( 116)| CYCLE_DMA_0_ +Mux15| Mcel 0 6 ( 110)| CYCLE_DMA_1_ +Mux16| IOPin 4 1 ( 42)| AS_000 +Mux17| IOPin 4 0 ( 41)| BERR +Mux18| Mcel 0 5 ( 109)| SM_AMIGA_2_ +Mux19| ... | ... Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux21| Input Pin ( 86)| RST -Mux22| Mcel 6 5 ( 253)| inst_RESET_OUT -Mux23| ... | ... -Mux24| ... | ... -Mux25| Mcel 0 13 ( 121)| CLK_000_D_3_ -Mux26| IOPin 4 1 ( 42)| AS_000 -Mux27| ... | ... -Mux28| Mcel 1 13 ( 145)| SM_AMIGA_5_ -Mux29| Mcel 3 13 ( 193)| cpu_est_1_ -Mux30| Mcel 0 8 ( 113)| SM_AMIGA_0_ +Mux21| Mcel 3 13 ( 193)| SM_AMIGA_3_ +Mux22| Mcel 0 2 ( 104)| inst_CLK_030_H +Mux23| Mcel 2 9 ( 163)| CLK_000_D_0_ +Mux24| Mcel 0 12 ( 119)| cpu_est_2_ +Mux25| Mcel 0 13 ( 121)| inst_DS_000_DMA +Mux26| ... | ... +Mux27| IOPin 3 4 ( 31)| LDS_000 +Mux28| ... | ... +Mux29| ... | ... +Mux30| ... | ... Mux31| ... | ... -Mux32| ... | ... +Mux32| Mcel 6 5 ( 253)| inst_RESET_OUT --------------------------------------------------------------------------- =========================================================================== < Block [ 1] > Macrocell (MCell) Cluster Assignments @@ -522,18 +521,18 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| AHIGH_30_| IO| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig 1| CLK_EXP|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig 2| RESET|OUT| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig - 3| | ? | | S | | 4 to [ 4]| 1 XOR to [ 4] as logic PT - 4| IPL_030_2_| IO| | S |10 | 4 to [ 4]| 1 XOR to [ 4] as logic PT - 5| IPL_030_0_| IO| | S |10 | 4 to [ 5]| 1 XOR to [ 5] as logic PT - 6|inst_DS_000_ENABLE|NOD| | S | 3 | 4 to [ 5]| 1 XOR to [ 5] as logic PT + 3| | ? | | S | | 4 to [ 4]| 1 XOR free + 4| IPL_030_2_| IO| | S | 9 | 4 to [ 4]| 1 XOR to [ 4] as logic PT + 5| IPL_030_0_| IO| | S | 9 | 4 to [ 5]| 1 XOR to [ 5] as logic PT + 6| inst_DTACK_D0|NOD| | S | 1 | 4 to [ 5]| 1 XOR to [ 6] for 1 PT sig 7| | ? | | S | | 4 free | 1 XOR free - 8| AHIGH_29_| IO| | S | 1 | 4 to [ 6]| 1 XOR to [ 8] for 1 PT sig - 9| IPL_030_1_| IO| | S |10 | 4 to [ 9]| 1 XOR to [ 9] as logic PT -10| RST_DLY_1_|NOD| | S | 2 :+: 1| 4 to [ 9]| 1 XOR to [10] -11| | ? | | S | | 4 to [ 9]| 1 XOR free -12| AHIGH_31_| IO| | S | 1 | 4 to [10]| 1 XOR to [12] for 1 PT sig -13| SM_AMIGA_5_|NOD| | S | 3 | 4 to [13]| 1 XOR free -14| IPL_D0_1_|NOD| | S | 1 | 4 free | 1 XOR to [14] for 1 PT sig + 8| AHIGH_29_| IO| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig + 9| IPL_030_1_| IO| | S | 9 | 4 to [ 9]| 1 XOR to [ 9] as logic PT +10| CLK_000_D_4_|NOD| | S | 1 | 4 to [ 9]| 1 XOR to [10] for 1 PT sig +11| | ? | | S | | 4 free | 1 XOR free +12| AHIGH_31_| IO| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig +13|inst_DS_000_ENABLE|NOD| | S | 3 | 4 to [13]| 1 XOR free +14| IPL_D0_2_|NOD| | S | 1 | 4 free | 1 XOR to [14] for 1 PT sig 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== @@ -549,18 +548,18 @@ _|_________________|__|__|___|_____|_______________________________________ 0| AHIGH_30_| IO| | S | 1 |=> can support up to [ 13] logic PT(s) 1| CLK_EXP|OUT| | S | 1 |=> can support up to [ 13] logic PT(s) 2| RESET|OUT| | S | 1 |=> can support up to [ 9] logic PT(s) - 3| | ? | | S | |=> can support up to [ 4] logic PT(s) - 4| IPL_030_2_| IO| | S |10 |=> can support up to [ 10] logic PT(s) - 5| IPL_030_0_| IO| | S |10 |=> can support up to [ 15] logic PT(s) - 6|inst_DS_000_ENABLE|NOD| | S | 3 |=> can support up to [ 9] logic PT(s) - 7| | ? | | S | |=> can support up to [ 5] logic PT(s) - 8| AHIGH_29_| IO| | S | 1 |=> can support up to [ 6] logic PT(s) - 9| IPL_030_1_| IO| | S |10 |=> can support up to [ 14] logic PT(s) -10| RST_DLY_1_|NOD| | S | 2 :+: 1|=> can support up to [ 4] logic PT(s) -11| | ? | | S | |=> can support up to [ 1] logic PT(s) -12| AHIGH_31_| IO| | S | 1 |=> can support up to [ 5] logic PT(s) -13| SM_AMIGA_5_|NOD| | S | 3 |=> can support up to [ 14] logic PT(s) -14| IPL_D0_1_|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) + 3| | ? | | S | |=> can support up to [ 5] logic PT(s) + 4| IPL_030_2_| IO| | S | 9 |=> can support up to [ 10] logic PT(s) + 5| IPL_030_0_| IO| | S | 9 |=> can support up to [ 14] logic PT(s) + 6| inst_DTACK_D0|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) + 7| | ? | | S | |=> can support up to [ 9] logic PT(s) + 8| AHIGH_29_| IO| | S | 1 |=> can support up to [ 10] logic PT(s) + 9| IPL_030_1_| IO| | S | 9 |=> can support up to [ 18] logic PT(s) +10| CLK_000_D_4_|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) +11| | ? | | S | |=> can support up to [ 9] logic PT(s) +12| AHIGH_31_| IO| | S | 1 |=> can support up to [ 14] logic PT(s) +13|inst_DS_000_ENABLE|NOD| | S | 3 |=> can support up to [ 18] logic PT(s) +14| IPL_D0_2_|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) 15| | ? | | S | |=> can support up to [ 9] logic PT(s) --------------------------------------------------------------------------- =========================================================================== @@ -577,15 +576,15 @@ _|_________________|__|_____|____________________|________________________ 3| | | | => | 6 7 0 1 | 4 3 10 9 4| IPL_030_2_| IO| | => | 7 0 ( 1) 2 | 3 10 ( 9) 8 5| IPL_030_0_| IO| | => | 7 0 1 ( 2)| 3 10 9 ( 8) - 6|inst_DS_000_ENABLE|NOD| | => | 0 1 2 3 | 10 9 8 7 + 6| inst_DTACK_D0|NOD| | => | 0 1 2 3 | 10 9 8 7 7| | | | => | 0 1 2 3 | 10 9 8 7 8| AHIGH_29_| IO| | => | 1 2 3 ( 4)| 9 8 7 ( 6) 9| IPL_030_1_| IO| | => | 1 2 ( 3) 4 | 9 8 ( 7) 6 -10| RST_DLY_1_|NOD| | => | 2 3 4 5 | 8 7 6 5 +10| CLK_000_D_4_|NOD| | => | 2 3 4 5 | 8 7 6 5 11| | | | => | 2 3 4 5 | 8 7 6 5 12| AHIGH_31_| IO| | => | 3 4 5 ( 6)| 7 6 5 ( 4) -13| SM_AMIGA_5_|NOD| | => | 3 4 5 6 | 7 6 5 4 -14| IPL_D0_1_|NOD| | => | 4 5 6 7 | 6 5 4 3 +13|inst_DS_000_ENABLE|NOD| | => | 3 4 5 6 | 7 6 5 4 +14| IPL_D0_2_|NOD| | => | 4 5 6 7 | 6 5 4 3 15| | | | => | 4 5 6 7 | 6 5 4 3 --------------------------------------------------------------------------- =========================================================================== @@ -653,7 +652,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 3 [IOpin 3 | 7| IO IPL_030_1_|*| ] paired w/[ RN_IPL_030_1_] [RegIn 3 |135| -| | ] - [MCell 6 |134|NOD inst_DS_000_ENABLE| |*] + [MCell 6 |134|NOD inst_DTACK_D0| |*] [MCell 7 |136| -| | ] 4 [IOpin 4 | 6| IO AHIGH_29_|*|*] @@ -663,17 +662,17 @@ IMX No. | +---- Block IO Pin or Macrocell Number 5 [IOpin 5 | 5| IO AHIGH_30_|*|*] [RegIn 5 |141| -| | ] - [MCell 10 |140|NOD RST_DLY_1_| |*] + [MCell 10 |140|NOD CLK_000_D_4_| |*] [MCell 11 |142| -| | ] 6 [IOpin 6 | 4| IO AHIGH_31_|*|*] [RegIn 6 |144| -| | ] [MCell 12 |143| IO AHIGH_31_| | ] - [MCell 13 |145|NOD SM_AMIGA_5_| |*] + [MCell 13 |145|NOD inst_DS_000_ENABLE| |*] 7 [IOpin 7 | 3|OUT RESET|*| ] [RegIn 7 |147| -| | ] - [MCell 14 |146|NOD IPL_D0_1_| |*] + [MCell 14 |146|NOD IPL_D0_2_| |*] [MCell 15 |148| -| | ] --------------------------------------------------------------------------- =========================================================================== @@ -682,39 +681,39 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| IOPin 6 2 ( 67)| IPL_0_ +Mux00| Mcel 7 4 ( 275)| RN_BGACK_030 Mux01| ... | ... -Mux02| Mcel 1 10 ( 140)| RST_DLY_1_ -Mux03| Mcel 0 14 ( 122)| IPL_D0_0_ -Mux04| IOPin 6 3 ( 68)| IPL_2_ +Mux02| Mcel 3 10 ( 188)| CLK_000_D_3_ +Mux03| Mcel 6 5 ( 253)| inst_RESET_OUT +Mux04| Mcel 3 6 ( 182)| inst_CLK_OUT_PRE_D Mux05| Input Pin ( 14)| nEXP_SPACE Mux06| Mcel 1 9 ( 139)| RN_IPL_030_1_ -Mux07| Mcel 3 9 ( 187)| CLK_000_D_0_ +Mux07| ... | ... Mux08| IOPin 6 6 ( 71)| RW -Mux09| Mcel 6 13 ( 265)| RST_DLY_2_ -Mux10| Mcel 1 13 ( 145)| SM_AMIGA_5_ -Mux11| Mcel 1 6 ( 134)| inst_DS_000_ENABLE -Mux12| Mcel 6 9 ( 259)| RST_DLY_0_ +Mux09| IOPin 3 5 ( 30)| DTACK +Mux10| Mcel 1 13 ( 145)| inst_DS_000_ENABLE +Mux11| Mcel 6 14 ( 266)| IPL_D0_0_ +Mux12| ... | ... Mux13| Mcel 7 5 ( 277)| CLK_000_D_1_ Mux14| ... | ... Mux15| ... | ... -Mux16| Mcel 4 8 ( 209)| inst_CLK_OUT_PRE_D -Mux17| ... | ... +Mux16| IOPin 6 2 ( 67)| IPL_0_ +Mux17| Mcel 3 14 ( 194)| IPL_D0_1_ Mux18| ... | ... -Mux19| Mcel 0 9 ( 115)| SM_AMIGA_4_ -Mux20| Mcel 1 14 ( 146)| IPL_D0_1_ -Mux21| Input Pin ( 86)| RST -Mux22| Mcel 6 5 ( 253)| inst_RESET_OUT -Mux23| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux24| ... | ... -Mux25| Mcel 5 0 ( 221)| SM_AMIGA_6_ -Mux26| Mcel 6 14 ( 266)| IPL_D0_2_ +Mux19| IOPin 7 3 ( 82)| AS_030 +Mux20| Mcel 1 14 ( 146)| IPL_D0_2_ +Mux21| IOPin 5 4 ( 56)| IPL_1_ +Mux22| IOPin 6 3 ( 68)| IPL_2_ +Mux23| Mcel 2 9 ( 163)| CLK_000_D_0_ +Mux24| Input Pin ( 86)| RST +Mux25| ... | ... +Mux26| ... | ... Mux27| Mcel 1 4 ( 131)| RN_IPL_030_2_ -Mux28| Mcel 1 5 ( 133)| RN_IPL_030_0_ +Mux28| Mcel 3 2 ( 176)| SM_AMIGA_4_ Mux29| ... | ... -Mux30| ... | ... -Mux31| IOPin 5 4 ( 56)| IPL_1_ -Mux32| IOPin 7 3 ( 82)| AS_030 +Mux30| Mcel 2 13 ( 169)| SM_AMIGA_6_ +Mux31| Mcel 1 5 ( 133)| RN_IPL_030_0_ +Mux32| ... | ... --------------------------------------------------------------------------- =========================================================================== < Block [ 2] > Macrocell (MCell) Cluster Assignments @@ -728,20 +727,20 @@ Mux32| IOPin 7 3 ( 82)| AS_030 _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| AHIGH_28_| IO| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig 1|AMIGA_BUS_ENABLE_LOW|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig - 2|inst_LDS_000_INT|NOD| | S | 3 | 4 to [ 2]| 1 XOR free + 2| SM_AMIGA_i_7_|NOD| | S | 3 :+: 1| 4 to [ 2]| 1 XOR to [ 2] 3| | ? | | S | | 4 free | 1 XOR free 4| AHIGH_26_| IO| | S | 1 | 4 free | 1 XOR to [ 4] for 1 PT sig 5| AHIGH_27_| IO| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig - 6|inst_AS_000_INT|NOD| | S | 2 | 4 to [ 6]| 1 XOR free + 6| SM_AMIGA_5_|NOD| | S | 3 | 4 to [ 6]| 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free 8| AHIGH_24_| IO| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig - 9|inst_DS_000_DMA|NOD| | S | 9 | 4 to [ 9]| 1 XOR to [ 9] as logic PT -10| inst_VPA_D|NOD| | S | 1 | 4 to [ 9]| 1 XOR to [10] for 1 PT sig + 9| CLK_000_D_0_|NOD| | S | 1 | 4 free | 1 XOR to [ 9] for 1 PT sig +10|inst_AS_000_INT|NOD| | S | 2 | 4 to [10]| 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free -12| AHIGH_25_| IO| | S | 1 | 4 to [13]| 1 XOR to [12] for 1 PT sig -13|inst_AS_000_DMA|NOD| | S | 7 | 4 to [13]| 1 XOR to [13] as logic PT -14|inst_CLK_030_H|NOD| | S | 8 | 4 to [14]| 1 XOR to [14] as logic PT -15| | ? | | S | | 4 to [14]| 1 XOR free +12| AHIGH_25_| IO| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig +13| SM_AMIGA_6_|NOD| | S | 3 | 4 to [13]| 1 XOR free +14|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | S | 2 | 4 to [14]| 1 XOR free +15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== < Block [ 2] > Maximum PT Capacity @@ -755,20 +754,20 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ _|_________________|__|__|___|_____|_______________________________________ 0| AHIGH_28_| IO| | S | 1 |=> can support up to [ 9] logic PT(s) 1|AMIGA_BUS_ENABLE_LOW|OUT| | S | 1 |=> can support up to [ 14] logic PT(s) - 2|inst_LDS_000_INT|NOD| | S | 3 |=> can support up to [ 18] logic PT(s) + 2| SM_AMIGA_i_7_|NOD| | S | 3 :+: 1|=> can support up to [ 17] logic PT(s) 3| | ? | | S | |=> can support up to [ 13] logic PT(s) 4| AHIGH_26_| IO| | S | 1 |=> can support up to [ 14] logic PT(s) 5| AHIGH_27_| IO| | S | 1 |=> can support up to [ 14] logic PT(s) - 6|inst_AS_000_INT|NOD| | S | 2 |=> can support up to [ 18] logic PT(s) - 7| | ? | | S | |=> can support up to [ 9] logic PT(s) - 8| AHIGH_24_| IO| | S | 1 |=> can support up to [ 10] logic PT(s) - 9|inst_DS_000_DMA|NOD| | S | 9 |=> can support up to [ 18] logic PT(s) -10| inst_VPA_D|NOD| | S | 1 |=> can support up to [ 6] logic PT(s) -11| | ? | | S | |=> can support up to [ 5] logic PT(s) -12| AHIGH_25_| IO| | S | 1 |=> can support up to [ 6] logic PT(s) -13|inst_AS_000_DMA|NOD| | S | 7 |=> can support up to [ 9] logic PT(s) -14|inst_CLK_030_H|NOD| | S | 8 |=> can support up to [ 10] logic PT(s) -15| | ? | | S | |=> can support up to [ 1] logic PT(s) + 6| SM_AMIGA_5_|NOD| | S | 3 |=> can support up to [ 18] logic PT(s) + 7| | ? | | S | |=> can support up to [ 13] logic PT(s) + 8| AHIGH_24_| IO| | S | 1 |=> can support up to [ 14] logic PT(s) + 9| CLK_000_D_0_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) +10|inst_AS_000_INT|NOD| | S | 2 |=> can support up to [ 18] logic PT(s) +11| | ? | | S | |=> can support up to [ 9] logic PT(s) +12| AHIGH_25_| IO| | S | 1 |=> can support up to [ 10] logic PT(s) +13| SM_AMIGA_6_|NOD| | S | 3 |=> can support up to [ 14] logic PT(s) +14|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | S | 2 |=> can support up to [ 10] logic PT(s) +15| | ? | | S | |=> can support up to [ 5] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 2] > Node-Pin Assignments @@ -780,19 +779,19 @@ _|_________________|__|__|___|_____|_______________________________________ _|_________________|__|_____|____________________|________________________ 0| AHIGH_28_| IO| | => | 5 6 7 ( 0)| 20 21 22 ( 15) 1|AMIGA_BUS_ENABLE_LOW|OUT| | => |( 5) 6 7 0 |( 20) 21 22 15 - 2|inst_LDS_000_INT|NOD| | => | 6 7 0 1 | 21 22 15 16 + 2| SM_AMIGA_i_7_|NOD| | => | 6 7 0 1 | 21 22 15 16 3| | | | => | 6 7 0 1 | 21 22 15 16 4| AHIGH_26_| IO| | => | 7 0 1 ( 2)| 22 15 16 ( 17) 5| AHIGH_27_| IO| | => | 7 0 ( 1) 2 | 22 15 ( 16) 17 - 6|inst_AS_000_INT|NOD| | => | 0 1 2 3 | 15 16 17 18 + 6| SM_AMIGA_5_|NOD| | => | 0 1 2 3 | 15 16 17 18 7| | | | => | 0 1 2 3 | 15 16 17 18 8| AHIGH_24_| IO| | => | 1 2 3 ( 4)| 16 17 18 ( 19) - 9|inst_DS_000_DMA|NOD| | => | 1 2 3 4 | 16 17 18 19 -10| inst_VPA_D|NOD| | => | 2 3 4 5 | 17 18 19 20 + 9| CLK_000_D_0_|NOD| | => | 1 2 3 4 | 16 17 18 19 +10|inst_AS_000_INT|NOD| | => | 2 3 4 5 | 17 18 19 20 11| | | | => | 2 3 4 5 | 17 18 19 20 12| AHIGH_25_| IO| | => |( 3) 4 5 6 |( 18) 19 20 21 -13|inst_AS_000_DMA|NOD| | => | 3 4 5 6 | 18 19 20 21 -14|inst_CLK_030_H|NOD| | => | 4 5 6 7 | 19 20 21 22 +13| SM_AMIGA_6_|NOD| | => | 3 4 5 6 | 18 19 20 21 +14|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | => | 4 5 6 7 | 19 20 21 22 15| | | | => | 4 5 6 7 | 19 20 21 22 --------------------------------------------------------------------------- =========================================================================== @@ -847,7 +846,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 1 [IOpin 1 | 16| IO AHIGH_27_|*|*] [RegIn 1 |153| -| | ] - [MCell 2 |152|NOD inst_LDS_000_INT| |*] + [MCell 2 |152|NOD SM_AMIGA_i_7_| |*] [MCell 3 |154| -| | ] 2 [IOpin 2 | 17| IO AHIGH_26_|*|*] @@ -857,27 +856,27 @@ IMX No. | +---- Block IO Pin or Macrocell Number 3 [IOpin 3 | 18| IO AHIGH_25_|*|*] [RegIn 3 |159| -| | ] - [MCell 6 |158|NOD inst_AS_000_INT| |*] + [MCell 6 |158|NOD SM_AMIGA_5_| |*] [MCell 7 |160| -| | ] 4 [IOpin 4 | 19| IO AHIGH_24_|*|*] [RegIn 4 |162| -| | ] [MCell 8 |161| IO AHIGH_24_| | ] - [MCell 9 |163|NOD inst_DS_000_DMA| |*] + [MCell 9 |163|NOD CLK_000_D_0_| |*] 5 [IOpin 5 | 20|OUT AMIGA_BUS_ENABLE_LOW|*| ] [RegIn 5 |165| -| | ] - [MCell 10 |164|NOD inst_VPA_D| |*] + [MCell 10 |164|NOD inst_AS_000_INT| |*] [MCell 11 |166| -| | ] 6 [IOpin 6 | 21|INP BG_030|*|*] [RegIn 6 |168| -| | ] [MCell 12 |167| IO AHIGH_25_| | ] - [MCell 13 |169|NOD inst_AS_000_DMA| |*] + [MCell 13 |169|NOD SM_AMIGA_6_| |*] 7 [IOpin 7 | 22| -| | ] [RegIn 7 |171| -| | ] - [MCell 14 |170|NOD inst_CLK_030_H| |*] + [MCell 14 |170|NOD inst_AMIGA_BUS_ENABLE_DMA_HIGH| |*] [MCell 15 |172| -| | ] --------------------------------------------------------------------------- =========================================================================== @@ -888,35 +887,35 @@ IMX No. | +---- Block IO Pin or Macrocell Number --|--|--------------------|--------------------------------------------------- Mux00| Input Pin ( 86)| RST Mux01| ... | ... -Mux02| Mcel 3 10 ( 188)| CYCLE_DMA_0_ -Mux03| Mcel 2 9 ( 163)| inst_DS_000_DMA -Mux04| Input Pin ( 64)| CLK_030 +Mux02| Mcel 1 10 ( 140)| CLK_000_D_4_ +Mux03| Input Pin ( 11)| CLK_000 +Mux04| Mcel 7 5 ( 277)| CLK_000_D_1_ Mux05| Input Pin ( 14)| nEXP_SPACE -Mux06| IOPin 7 6 ( 79)| SIZE_1_ -Mux07| Mcel 2 14 ( 170)| inst_CLK_030_H -Mux08| IOPin 3 3 ( 32)| UDS_000 -Mux09| Mcel 2 6 ( 158)| inst_AS_000_INT -Mux10| Input Pin ( 36)| VPA -Mux11| Mcel 2 13 ( 169)| inst_AS_000_DMA -Mux12| Mcel 3 9 ( 187)| CLK_000_D_0_ -Mux13| Mcel 7 5 ( 277)| CLK_000_D_1_ -Mux14| IOPin 6 5 ( 70)| SIZE_0_ -Mux15| IOPin 6 4 ( 69)| A_0_ -Mux16| Mcel 3 6 ( 182)| CYCLE_DMA_1_ +Mux06| ... | ... +Mux07| Mcel 2 14 ( 170)| inst_AMIGA_BUS_ENABLE_DMA_HIGH +Mux08| Mcel 2 10 ( 164)| inst_AS_000_INT +Mux09| IOPin 7 3 ( 82)| AS_030 +Mux10| Mcel 5 1 ( 223)| inst_AMIGA_BUS_ENABLE_DMA_LOW +Mux11| IOPin 5 0 ( 60)| A_1_ +Mux12| ... | ... +Mux13| Mcel 2 9 ( 163)| CLK_000_D_0_ +Mux14| ... | ... +Mux15| ... | ... +Mux16| Mcel 4 8 ( 209)| inst_BGACK_030_INT_D Mux17| ... | ... -Mux18| ... | ... -Mux19| IOPin 7 3 ( 82)| AS_030 -Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux21| IOPin 7 5 ( 80)| RW_000 -Mux22| Mcel 2 2 ( 152)| inst_LDS_000_INT -Mux23| Mcel 6 6 ( 254)| inst_AMIGA_BUS_ENABLE_DMA_LOW -Mux24| IOPin 3 4 ( 31)| LDS_000 -Mux25| Mcel 5 0 ( 221)| SM_AMIGA_6_ -Mux26| IOPin 4 1 ( 42)| AS_000 +Mux18| Mcel 2 6 ( 158)| SM_AMIGA_5_ +Mux19| Mcel 7 13 ( 289)| SM_AMIGA_0_ +Mux20| Mcel 3 10 ( 188)| CLK_000_D_3_ +Mux21| ... | ... +Mux22| Mcel 2 2 ( 152)| SM_AMIGA_i_7_ +Mux23| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux24| ... | ... +Mux25| Mcel 5 0 ( 221)| inst_AS_030_000_SYNC +Mux26| ... | ... Mux27| ... | ... Mux28| ... | ... Mux29| ... | ... -Mux30| ... | ... +Mux30| Mcel 2 13 ( 169)| SM_AMIGA_6_ Mux31| ... | ... Mux32| Mcel 6 5 ( 253)| inst_RESET_OUT --------------------------------------------------------------------------- @@ -932,19 +931,19 @@ Mux32| Mcel 6 5 ( 253)| inst_RESET_OUT _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| VMA| IO| | S | 3 | 4 to [ 0]| 1 XOR free 1| BG_000| IO| | S | 2 | 4 to [ 1]| 1 XOR free - 2| cpu_est_2_|NOD| | S | 1 :+: 1| 4 to [ 2]| 1 XOR to [ 2] + 2| SM_AMIGA_4_|NOD| | S | 3 | 4 to [ 2]| 1 XOR free 3| | ? | | S | | 4 free | 1 XOR free 4|AMIGA_BUS_ENABLE_HIGH|OUT| | S | 2 | 4 to [ 4]| 1 XOR free 5|AMIGA_ADDR_ENABLE|OUT| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig - 6| CYCLE_DMA_1_|NOD| | S | 4 | 4 to [ 6]| 1 XOR free + 6|inst_CLK_OUT_PRE_D|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig 7| | ? | | S | | 4 free | 1 XOR free 8| UDS_000| IO| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig - 9| CLK_000_D_0_|NOD| | S | 1 | 4 free | 1 XOR to [ 9] for 1 PT sig -10| CYCLE_DMA_0_|NOD| | S | 3 | 4 to [10]| 1 XOR free + 9| cpu_est_3_|NOD| | S | 4 | 4 to [ 9]| 1 XOR free +10| CLK_000_D_3_|NOD| | S | 1 | 4 free | 1 XOR to [10] for 1 PT sig 11| | ? | | S | | 4 free | 1 XOR free 12| LDS_000| IO| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig -13| cpu_est_1_|NOD| | S | 4 | 4 to [13]| 1 XOR free -14| cpu_est_0_|NOD| | S | 3 | 4 to [14]| 1 XOR free +13| SM_AMIGA_3_|NOD| | S | 5 | 4 to [13]| 1 XOR to [13] as logic PT +14| IPL_D0_1_|NOD| | S | 1 | 4 free | 1 XOR to [14] for 1 PT sig 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== @@ -959,20 +958,20 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ _|_________________|__|__|___|_____|_______________________________________ 0| VMA| IO| | S | 3 |=> can support up to [ 5] logic PT(s) 1| BG_000| IO| | S | 2 |=> can support up to [ 10] logic PT(s) - 2| cpu_est_2_|NOD| | S | 1 :+: 1|=> can support up to [ 9] logic PT(s) + 2| SM_AMIGA_4_|NOD| | S | 3 |=> can support up to [ 10] logic PT(s) 3| | ? | | S | |=> can support up to [ 9] logic PT(s) - 4|AMIGA_BUS_ENABLE_HIGH|OUT| | S | 2 |=> can support up to [ 14] logic PT(s) - 5|AMIGA_ADDR_ENABLE|OUT| | S | 1 |=> can support up to [ 10] logic PT(s) - 6| CYCLE_DMA_1_|NOD| | S | 4 |=> can support up to [ 18] logic PT(s) + 4|AMIGA_BUS_ENABLE_HIGH|OUT| | S | 2 |=> can support up to [ 18] logic PT(s) + 5|AMIGA_ADDR_ENABLE|OUT| | S | 1 |=> can support up to [ 14] logic PT(s) + 6|inst_CLK_OUT_PRE_D|NOD| | S | 1 |=> can support up to [ 18] logic PT(s) 7| | ? | | S | |=> can support up to [ 13] logic PT(s) 8| UDS_000| IO| | S | 1 |=> can support up to [ 14] logic PT(s) - 9| CLK_000_D_0_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) -10| CYCLE_DMA_0_|NOD| | S | 3 |=> can support up to [ 18] logic PT(s) -11| | ? | | S | |=> can support up to [ 9] logic PT(s) -12| LDS_000| IO| | S | 1 |=> can support up to [ 10] logic PT(s) -13| cpu_est_1_|NOD| | S | 4 |=> can support up to [ 14] logic PT(s) -14| cpu_est_0_|NOD| | S | 3 |=> can support up to [ 10] logic PT(s) -15| | ? | | S | |=> can support up to [ 5] logic PT(s) + 9| cpu_est_3_|NOD| | S | 4 |=> can support up to [ 18] logic PT(s) +10| CLK_000_D_3_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) +11| | ? | | S | |=> can support up to [ 13] logic PT(s) +12| LDS_000| IO| | S | 1 |=> can support up to [ 14] logic PT(s) +13| SM_AMIGA_3_|NOD| | S | 5 |=> can support up to [ 18] logic PT(s) +14| IPL_D0_1_|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) +15| | ? | | S | |=> can support up to [ 9] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 3] > Node-Pin Assignments @@ -984,19 +983,19 @@ _|_________________|__|__|___|_____|_______________________________________ _|_________________|__|_____|____________________|________________________ 0| VMA| IO| | => | 5 6 7 ( 0)| 30 29 28 ( 35) 1| BG_000| IO| | => | 5 ( 6) 7 0 | 30 ( 29) 28 35 - 2| cpu_est_2_|NOD| | => | 6 7 0 1 | 29 28 35 34 + 2| SM_AMIGA_4_|NOD| | => | 6 7 0 1 | 29 28 35 34 3| | | | => | 6 7 0 1 | 29 28 35 34 4|AMIGA_BUS_ENABLE_HIGH|OUT| | => | 7 0 ( 1) 2 | 28 35 ( 34) 33 5|AMIGA_ADDR_ENABLE|OUT| | => | 7 0 1 ( 2)| 28 35 34 ( 33) - 6| CYCLE_DMA_1_|NOD| | => | 0 1 2 3 | 35 34 33 32 + 6|inst_CLK_OUT_PRE_D|NOD| | => | 0 1 2 3 | 35 34 33 32 7| | | | => | 0 1 2 3 | 35 34 33 32 8| UDS_000| IO| | => | 1 2 ( 3) 4 | 34 33 ( 32) 31 - 9| CLK_000_D_0_|NOD| | => | 1 2 3 4 | 34 33 32 31 -10| CYCLE_DMA_0_|NOD| | => | 2 3 4 5 | 33 32 31 30 + 9| cpu_est_3_|NOD| | => | 1 2 3 4 | 34 33 32 31 +10| CLK_000_D_3_|NOD| | => | 2 3 4 5 | 33 32 31 30 11| | | | => | 2 3 4 5 | 33 32 31 30 12| LDS_000| IO| | => | 3 ( 4) 5 6 | 32 ( 31) 30 29 -13| cpu_est_1_|NOD| | => | 3 4 5 6 | 32 31 30 29 -14| cpu_est_0_|NOD| | => | 4 5 6 7 | 31 30 29 28 +13| SM_AMIGA_3_|NOD| | => | 3 4 5 6 | 32 31 30 29 +14| IPL_D0_1_|NOD| | => | 4 5 6 7 | 31 30 29 28 15| | | | => | 4 5 6 7 | 31 30 29 28 --------------------------------------------------------------------------- =========================================================================== @@ -1053,7 +1052,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 1 [IOpin 1 | 34|OUT AMIGA_BUS_ENABLE_HIGH|*| ] [RegIn 1 |177| -| | ] - [MCell 2 |176|NOD cpu_est_2_| |*] + [MCell 2 |176|NOD SM_AMIGA_4_| |*] [MCell 3 |178| -| | ] 2 [IOpin 2 | 33|OUT AMIGA_ADDR_ENABLE|*| ] @@ -1063,27 +1062,27 @@ IMX No. | +---- Block IO Pin or Macrocell Number 3 [IOpin 3 | 32| IO UDS_000|*|*] [RegIn 3 |183| -| | ] - [MCell 6 |182|NOD CYCLE_DMA_1_| |*] + [MCell 6 |182|NOD inst_CLK_OUT_PRE_D| |*] [MCell 7 |184| -| | ] 4 [IOpin 4 | 31| IO LDS_000|*|*] [RegIn 4 |186| -| | ] [MCell 8 |185| IO UDS_000| | ] - [MCell 9 |187|NOD CLK_000_D_0_| |*] + [MCell 9 |187|NOD cpu_est_3_| |*] 5 [IOpin 5 | 30|INP DTACK|*|*] [RegIn 5 |189| -| | ] - [MCell 10 |188|NOD CYCLE_DMA_0_| |*] + [MCell 10 |188|NOD CLK_000_D_3_| |*] [MCell 11 |190| -| | ] 6 [IOpin 6 | 29| IO BG_000|*| ] paired w/[ RN_BG_000] [RegIn 6 |192| -| | ] [MCell 12 |191| IO LDS_000| | ] - [MCell 13 |193|NOD cpu_est_1_| |*] + [MCell 13 |193|NOD SM_AMIGA_3_| |*] 7 [IOpin 7 | 28|INP BGACK_000|*|*] [RegIn 7 |195| -| | ] - [MCell 14 |194|NOD cpu_est_0_| |*] + [MCell 14 |194|NOD IPL_D0_1_| |*] [MCell 15 |196| -| | ] --------------------------------------------------------------------------- =========================================================================== @@ -1093,38 +1092,38 @@ IMX No. | +---- Block IO Pin or Macrocell Number | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- Mux00| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux01| Mcel 3 13 ( 193)| cpu_est_1_ +Mux01| Mcel 3 13 ( 193)| SM_AMIGA_3_ Mux02| Mcel 3 1 ( 175)| RN_BG_000 -Mux03| Input Pin ( 11)| CLK_000 +Mux03| Mcel 0 8 ( 113)| cpu_est_1_ Mux04| IOPin 2 6 ( 21)| BG_030 -Mux05| Input Pin ( 14)| nEXP_SPACE +Mux05| Mcel 5 0 ( 221)| inst_AS_030_000_SYNC Mux06| ... | ... -Mux07| Mcel 7 13 ( 289)| inst_AS_030_D0 -Mux08| Mcel 2 10 ( 164)| inst_VPA_D -Mux09| Mcel 0 12 ( 119)| cpu_est_3_ -Mux10| Mcel 5 1 ( 223)| inst_UDS_000_INT -Mux11| Mcel 1 6 ( 134)| inst_DS_000_ENABLE -Mux12| Mcel 3 9 ( 187)| CLK_000_D_0_ +Mux07| Mcel 3 9 ( 187)| cpu_est_3_ +Mux08| ... | ... +Mux09| Mcel 0 12 ( 119)| cpu_est_2_ +Mux10| Mcel 6 9 ( 259)| cpu_est_0_ +Mux11| Mcel 1 6 ( 134)| inst_DTACK_D0 +Mux12| Mcel 6 13 ( 265)| inst_CLK_OUT_PRE_50 Mux13| Mcel 7 5 ( 277)| CLK_000_D_1_ -Mux14| Mcel 5 4 ( 227)| inst_AS_030_000_SYNC -Mux15| ... | ... -Mux16| Mcel 3 6 ( 182)| CYCLE_DMA_1_ -Mux17| Mcel 3 14 ( 194)| cpu_est_0_ -Mux18| Mcel 3 0 ( 173)| RN_VMA -Mux19| ... | ... -Mux20| Mcel 3 10 ( 188)| CYCLE_DMA_0_ +Mux14| Mcel 4 5 ( 205)| inst_AS_030_D0 +Mux15| Input Pin ( 14)| nEXP_SPACE +Mux16| Mcel 3 2 ( 176)| SM_AMIGA_4_ +Mux17| Mcel 5 12 ( 239)| inst_UDS_000_INT +Mux18| Mcel 2 14 ( 170)| inst_AMIGA_BUS_ENABLE_DMA_HIGH +Mux19| Mcel 0 9 ( 115)| inst_VPA_D +Mux20| Mcel 5 8 ( 233)| inst_LDS_000_INT Mux21| Input Pin ( 86)| RST -Mux22| Mcel 2 2 ( 152)| inst_LDS_000_INT -Mux23| Mcel 6 2 ( 248)| inst_AMIGA_BUS_ENABLE_DMA_HIGH +Mux22| Mcel 6 5 ( 253)| inst_RESET_OUT +Mux23| Mcel 2 9 ( 163)| CLK_000_D_0_ Mux24| ... | ... -Mux25| ... | ... -Mux26| IOPin 4 1 ( 42)| AS_000 -Mux27| ... | ... -Mux28| Mcel 3 2 ( 176)| cpu_est_2_ +Mux25| IOPin 4 0 ( 41)| BERR +Mux26| Mcel 3 0 ( 173)| RN_VMA +Mux27| Mcel 2 6 ( 158)| SM_AMIGA_5_ +Mux28| Mcel 1 13 ( 145)| inst_DS_000_ENABLE Mux29| ... | ... -Mux30| ... | ... -Mux31| ... | ... -Mux32| Mcel 6 5 ( 253)| inst_RESET_OUT +Mux30| Mcel 7 6 ( 278)| CLK_000_D_2_ +Mux31| IOPin 5 4 ( 56)| IPL_1_ +Mux32| IOPin 7 3 ( 82)| AS_030 --------------------------------------------------------------------------- =========================================================================== < Block [ 4] > Macrocell (MCell) Cluster Assignments @@ -1141,11 +1140,11 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ 2| | ? | | S | | 4 free | 1 XOR free 3| | ? | | S | | 4 free | 1 XOR free 4| AS_000| IO| | S | 1 | 4 free | 1 XOR to [ 4] for 1 PT sig - 5| CIIN_0|NOD| | S | 2 | 4 to [ 5]| 1 XOR free + 5|inst_AS_030_D0|NOD| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig 6| | ? | | S | | 4 free | 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free - 8|inst_CLK_OUT_PRE_D|NOD| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig - 9|inst_CLK_OUT_PRE_50|NOD| | S | 1 | 4 free | 1 XOR to [ 9] for 1 PT sig + 8|inst_BGACK_030_INT_D|NOD| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig + 9| CIIN_0|NOD| | S | 2 | 4 to [ 9]| 1 XOR free 10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free 12| CIIN|OUT| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig @@ -1166,14 +1165,14 @@ _|_________________|__|__|___|_____|_______________________________________ 0| BERR| IO| | S | 1 |=> can support up to [ 10] logic PT(s) 1|AMIGA_BUS_DATA_DIR|OUT| | S | 2 |=> can support up to [ 19] logic PT(s) 2| | ? | | S | |=> can support up to [ 14] logic PT(s) - 3| | ? | | S | |=> can support up to [ 14] logic PT(s) - 4| AS_000| IO| | S | 1 |=> can support up to [ 15] logic PT(s) - 5| CIIN_0|NOD| | S | 2 |=> can support up to [ 19] logic PT(s) - 6| | ? | | S | |=> can support up to [ 14] logic PT(s) - 7| | ? | | S | |=> can support up to [ 18] logic PT(s) - 8|inst_CLK_OUT_PRE_D|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) - 9|inst_CLK_OUT_PRE_50|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) -10| | ? | | S | |=> can support up to [ 18] logic PT(s) + 3| | ? | | S | |=> can support up to [ 18] logic PT(s) + 4| AS_000| IO| | S | 1 |=> can support up to [ 19] logic PT(s) + 5|inst_AS_030_D0|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) + 6| | ? | | S | |=> can support up to [ 18] logic PT(s) + 7| | ? | | S | |=> can support up to [ 14] logic PT(s) + 8|inst_BGACK_030_INT_D|NOD| | S | 1 |=> can support up to [ 15] logic PT(s) + 9| CIIN_0|NOD| | S | 2 |=> can support up to [ 19] logic PT(s) +10| | ? | | S | |=> can support up to [ 14] logic PT(s) 11| | ? | | S | |=> can support up to [ 19] logic PT(s) 12| CIIN|OUT| | S | 1 |=> can support up to [ 20] logic PT(s) 13| | ? | | S | |=> can support up to [ 19] logic PT(s) @@ -1193,11 +1192,11 @@ _|_________________|__|_____|____________________|________________________ 2| | | | => | 6 7 0 1 | 47 48 41 42 3| | | | => | 6 7 0 1 | 47 48 41 42 4| AS_000| IO| | => | 7 0 ( 1) 2 | 48 41 ( 42) 43 - 5| CIIN_0|NOD| | => | 7 0 1 2 | 48 41 42 43 + 5|inst_AS_030_D0|NOD| | => | 7 0 1 2 | 48 41 42 43 6| | | | => | 0 1 2 3 | 41 42 43 44 7| | | | => | 0 1 2 3 | 41 42 43 44 - 8|inst_CLK_OUT_PRE_D|NOD| | => | 1 2 3 4 | 42 43 44 45 - 9|inst_CLK_OUT_PRE_50|NOD| | => | 1 2 3 4 | 42 43 44 45 + 8|inst_BGACK_030_INT_D|NOD| | => | 1 2 3 4 | 42 43 44 45 + 9| CIIN_0|NOD| | => | 1 2 3 4 | 42 43 44 45 10| | | | => | 2 3 4 5 | 43 44 45 46 11| | | | => | 2 3 4 5 | 43 44 45 46 12| CIIN|OUT| | => | 3 4 5 ( 6)| 44 45 46 ( 47) @@ -1263,7 +1262,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 2 [IOpin 2 | 43| -| | ] [RegIn 2 |204| -| | ] [MCell 4 |203| IO AS_000| | ] - [MCell 5 |205|NOD CIIN_0| |*] + [MCell 5 |205|NOD inst_AS_030_D0| |*] 3 [IOpin 3 | 44| -| | ] [RegIn 3 |207| -| | ] @@ -1272,8 +1271,8 @@ IMX No. | +---- Block IO Pin or Macrocell Number 4 [IOpin 4 | 45| -| | ] [RegIn 4 |210| -| | ] - [MCell 8 |209|NOD inst_CLK_OUT_PRE_D| |*] - [MCell 9 |211|NOD inst_CLK_OUT_PRE_50| |*] + [MCell 8 |209|NOD inst_BGACK_030_INT_D| |*] + [MCell 9 |211|NOD CIIN_0| |*] 5 [IOpin 5 | 46| -| | ] [RegIn 5 |213| -| | ] @@ -1296,38 +1295,38 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux00| Input Pin ( 86)| RST Mux01| IOPin 5 2 ( 58)| FC_1_ -Mux02| Mcel 4 9 ( 211)| inst_CLK_OUT_PRE_50 -Mux03| IOPin 2 3 ( 18)| AHIGH_25_ -Mux04| IOPin 3 7 ( 28)| BGACK_000 +Mux02| Mcel 4 9 ( 211)| CIIN_0 +Mux03| IOPin 2 1 ( 16)| AHIGH_27_ +Mux04| IOPin 0 4 ( 95)| A_DECODE_18_ Mux05| IOPin 2 4 ( 19)| AHIGH_24_ -Mux06| IOPin 7 5 ( 80)| RW_000 -Mux07| Mcel 7 13 ( 289)| inst_AS_030_D0 -Mux08| IOPin 0 0 ( 91)| FPU_SENSE -Mux09| IOPin 2 2 ( 17)| AHIGH_26_ +Mux06| IOPin 0 6 ( 97)| A_DECODE_19_ +Mux07| IOPin 2 0 ( 15)| AHIGH_28_ +Mux08| Mcel 2 10 ( 164)| inst_AS_000_INT +Mux09| IOPin 1 5 ( 5)| AHIGH_30_ Mux10| ... | ... -Mux11| IOPin 2 1 ( 16)| AHIGH_27_ -Mux12| IOPin 0 6 ( 97)| A_DECODE_19_ -Mux13| IOPin 5 1 ( 59)| A_DECODE_17_ -Mux14| Mcel 4 5 ( 205)| CIIN_0 -Mux15| Input Pin ( 14)| nEXP_SPACE +Mux11| IOPin 0 0 ( 91)| FPU_SENSE +Mux12| IOPin 2 3 ( 18)| AHIGH_25_ +Mux13| IOPin 1 4 ( 6)| AHIGH_29_ +Mux14| Mcel 4 5 ( 205)| inst_AS_030_D0 +Mux15| IOPin 0 3 ( 94)| A_DECODE_21_ Mux16| IOPin 4 1 ( 42)| AS_000 -Mux17| IOPin 0 4 ( 95)| A_DECODE_18_ -Mux18| Mcel 2 6 ( 158)| inst_AS_000_INT +Mux17| IOPin 2 2 ( 17)| AHIGH_26_ +Mux18| IOPin 3 7 ( 28)| BGACK_000 Mux19| IOPin 7 3 ( 82)| AS_030 Mux20| IOPin 7 1 ( 84)| A_DECODE_22_ -Mux21| IOPin 1 4 ( 6)| AHIGH_29_ +Mux21| Input Pin ( 14)| nEXP_SPACE Mux22| Mcel 6 5 ( 253)| inst_RESET_OUT -Mux23| ... | ... +Mux23| Mcel 7 4 ( 275)| RN_BGACK_030 Mux24| IOPin 5 3 ( 57)| FC_0_ Mux25| IOPin 1 6 ( 4)| AHIGH_31_ Mux26| IOPin 0 5 ( 96)| A_DECODE_16_ -Mux27| IOPin 2 0 ( 15)| AHIGH_28_ -Mux28| IOPin 1 5 ( 5)| AHIGH_30_ +Mux27| IOPin 5 1 ( 59)| A_DECODE_17_ +Mux28| IOPin 7 5 ( 80)| RW_000 Mux29| IOPin 0 2 ( 93)| A_DECODE_20_ Mux30| ... | ... -Mux31| IOPin 0 3 ( 94)| A_DECODE_21_ +Mux31| ... | ... Mux32| IOPin 7 0 ( 85)| A_DECODE_23_ --------------------------------------------------------------------------- =========================================================================== @@ -1340,19 +1339,19 @@ Mux32| IOPin 7 0 ( 85)| A_DECODE_23_ | Sig Type-+ | | | | | | | XOR to Mcell Assignment | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ - 0| SM_AMIGA_6_|NOD| | S | 3 | 4 to [ 0]| 1 XOR free - 1|inst_UDS_000_INT|NOD| | S | 2 | 4 to [ 1]| 1 XOR free - 2| | ? | | S | | 4 free | 1 XOR free + 0|inst_AS_030_000_SYNC|NOD| | S | 7 | 4 to [ 0]| 1 XOR to [ 0] as logic PT + 1|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | S | 2 | 4 to [ 1]| 1 XOR free + 2| | ? | | S | | 4 to [ 0]| 1 XOR free 3| | ? | | S | | 4 free | 1 XOR free - 4|inst_AS_030_000_SYNC|NOD| | S | 7 | 4 to [ 4]| 1 XOR to [ 4] as logic PT - 5| | ? | | S | | 4 to [ 4]| 1 XOR free + 4| SM_AMIGA_1_|NOD| | S | 3 | 4 to [ 4]| 1 XOR free + 5| | ? | | S | | 4 free | 1 XOR free 6| | ? | | S | | 4 free | 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free - 8| SM_AMIGA_i_7_|NOD| | S | 3 :+: 1| 4 to [ 8]| 1 XOR to [ 8] + 8|inst_LDS_000_INT|NOD| | S | 3 | 4 to [ 8]| 1 XOR free 9| | ? | | S | | 4 free | 1 XOR free 10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free -12|inst_DSACK1_INT|NOD| | S | 2 | 4 to [12]| 1 XOR free +12|inst_UDS_000_INT|NOD| | S | 2 | 4 to [12]| 1 XOR free 13| | ? | | S | | 4 free | 1 XOR free 14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free @@ -1367,19 +1366,19 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| SM_AMIGA_6_|NOD| | S | 3 |=> can support up to [ 10] logic PT(s) - 1|inst_UDS_000_INT|NOD| | S | 2 |=> can support up to [ 15] logic PT(s) - 2| | ? | | S | |=> can support up to [ 10] logic PT(s) + 0|inst_AS_030_000_SYNC|NOD| | S | 7 |=> can support up to [ 10] logic PT(s) + 1|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | S | 2 |=> can support up to [ 10] logic PT(s) + 2| | ? | | S | |=> can support up to [ 6] logic PT(s) 3| | ? | | S | |=> can support up to [ 10] logic PT(s) - 4|inst_AS_030_000_SYNC|NOD| | S | 7 |=> can support up to [ 20] logic PT(s) - 5| | ? | | S | |=> can support up to [ 11] logic PT(s) - 6| | ? | | S | |=> can support up to [ 10] logic PT(s) + 4| SM_AMIGA_1_|NOD| | S | 3 |=> can support up to [ 20] logic PT(s) + 5| | ? | | S | |=> can support up to [ 15] logic PT(s) + 6| | ? | | S | |=> can support up to [ 15] logic PT(s) 7| | ? | | S | |=> can support up to [ 15] logic PT(s) - 8| SM_AMIGA_i_7_|NOD| | S | 3 :+: 1|=> can support up to [ 19] logic PT(s) + 8|inst_LDS_000_INT|NOD| | S | 3 |=> can support up to [ 20] logic PT(s) 9| | ? | | S | |=> can support up to [ 15] logic PT(s) 10| | ? | | S | |=> can support up to [ 15] logic PT(s) 11| | ? | | S | |=> can support up to [ 15] logic PT(s) -12|inst_DSACK1_INT|NOD| | S | 2 |=> can support up to [ 20] logic PT(s) +12|inst_UDS_000_INT|NOD| | S | 2 |=> can support up to [ 20] logic PT(s) 13| | ? | | S | |=> can support up to [ 15] logic PT(s) 14| | ? | | S | |=> can support up to [ 15] logic PT(s) 15| | ? | | S | |=> can support up to [ 10] logic PT(s) @@ -1392,19 +1391,19 @@ _|_________________|__|__|___|_____|_______________________________________ | Sig Type---+ | to | Block [ 5] IO Pin | Device Pin | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ - 0| SM_AMIGA_6_|NOD| | => | 5 6 7 0 | 55 54 53 60 - 1|inst_UDS_000_INT|NOD| | => | 5 6 7 0 | 55 54 53 60 + 0|inst_AS_030_000_SYNC|NOD| | => | 5 6 7 0 | 55 54 53 60 + 1|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | => | 5 6 7 0 | 55 54 53 60 2| | | | => | 6 7 0 1 | 54 53 60 59 3| | | | => | 6 7 0 1 | 54 53 60 59 - 4|inst_AS_030_000_SYNC|NOD| | => | 7 0 1 2 | 53 60 59 58 + 4| SM_AMIGA_1_|NOD| | => | 7 0 1 2 | 53 60 59 58 5| | | | => | 7 0 1 2 | 53 60 59 58 6| | | | => | 0 1 2 3 | 60 59 58 57 7| | | | => | 0 1 2 3 | 60 59 58 57 - 8| SM_AMIGA_i_7_|NOD| | => | 1 2 3 4 | 59 58 57 56 + 8|inst_LDS_000_INT|NOD| | => | 1 2 3 4 | 59 58 57 56 9| | | | => | 1 2 3 4 | 59 58 57 56 10| | | | => | 2 3 4 5 | 58 57 56 55 11| | | | => | 2 3 4 5 | 58 57 56 55 -12|inst_DSACK1_INT|NOD| | => | 3 4 5 6 | 57 56 55 54 +12|inst_UDS_000_INT|NOD| | => | 3 4 5 6 | 57 56 55 54 13| | | | => | 3 4 5 6 | 57 56 55 54 14| | | | => | 4 5 6 7 | 56 55 54 53 15| | | | => | 4 5 6 7 | 56 55 54 53 @@ -1456,8 +1455,8 @@ IMX No. | +---- Block IO Pin or Macrocell Number ---|-------|----|---|---|----------|------|-|------------------------------ 0 [IOpin 0 | 60|INP A_1_|*|*] [RegIn 0 |222| -| | ] - [MCell 0 |221|NOD SM_AMIGA_6_| |*] - [MCell 1 |223|NOD inst_UDS_000_INT| |*] + [MCell 0 |221|NOD inst_AS_030_000_SYNC| |*] + [MCell 1 |223|NOD inst_AMIGA_BUS_ENABLE_DMA_LOW| |*] 1 [IOpin 1 | 59|INP A_DECODE_17_|*|*] [RegIn 1 |225| -| | ] @@ -1466,7 +1465,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 2 [IOpin 2 | 58|INP FC_1_|*|*] [RegIn 2 |228| -| | ] - [MCell 4 |227|NOD inst_AS_030_000_SYNC| |*] + [MCell 4 |227|NOD SM_AMIGA_1_| |*] [MCell 5 |229| -| | ] 3 [IOpin 3 | 57|INP FC_0_|*|*] @@ -1476,7 +1475,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 4 [IOpin 4 | 56|INP IPL_1_|*|*] [RegIn 4 |234| -| | ] - [MCell 8 |233|NOD SM_AMIGA_i_7_| |*] + [MCell 8 |233|NOD inst_LDS_000_INT| |*] [MCell 9 |235| -| | ] 5 [IOpin 5 | 55| -| | ] @@ -1486,7 +1485,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 6 [IOpin 6 | 54| -| | ] [RegIn 6 |240| -| | ] - [MCell 12 |239|NOD inst_DSACK1_INT| |*] + [MCell 12 |239|NOD inst_UDS_000_INT| |*] [MCell 13 |241| -| | ] 7 [IOpin 7 | 53| -| | ] @@ -1500,38 +1499,38 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux01| Mcel 5 12 ( 239)| inst_DSACK1_INT -Mux02| Mcel 5 8 ( 233)| SM_AMIGA_i_7_ -Mux03| Mcel 0 8 ( 113)| SM_AMIGA_0_ +Mux00| IOPin 6 5 ( 70)| SIZE_0_ +Mux01| IOPin 5 2 ( 58)| FC_1_ +Mux02| Mcel 5 8 ( 233)| inst_LDS_000_INT +Mux03| IOPin 5 0 ( 60)| A_1_ Mux04| IOPin 0 4 ( 95)| A_DECODE_18_ Mux05| Input Pin ( 14)| nEXP_SPACE -Mux06| IOPin 0 6 ( 97)| A_DECODE_19_ -Mux07| Mcel 3 9 ( 187)| CLK_000_D_0_ +Mux06| IOPin 5 3 ( 57)| FC_0_ +Mux07| ... | ... Mux08| IOPin 5 1 ( 59)| A_DECODE_17_ Mux09| IOPin 7 3 ( 82)| AS_030 -Mux10| Mcel 5 1 ( 223)| inst_UDS_000_INT +Mux10| Mcel 5 1 ( 223)| inst_AMIGA_BUS_ENABLE_DMA_LOW Mux11| IOPin 0 5 ( 96)| A_DECODE_16_ -Mux12| Mcel 0 1 ( 103)| inst_BGACK_030_INT_D +Mux12| IOPin 0 6 ( 97)| A_DECODE_19_ Mux13| Mcel 7 5 ( 277)| CLK_000_D_1_ -Mux14| Mcel 7 2 ( 272)| CLK_000_D_2_ +Mux14| Mcel 5 4 ( 227)| SM_AMIGA_1_ Mux15| IOPin 6 4 ( 69)| A_0_ -Mux16| ... | ... -Mux17| IOPin 5 3 ( 57)| FC_0_ -Mux18| Mcel 0 5 ( 109)| SM_AMIGA_1_ -Mux19| Mcel 7 13 ( 289)| inst_AS_030_D0 -Mux20| IOPin 5 2 ( 58)| FC_1_ +Mux16| Mcel 4 8 ( 209)| inst_BGACK_030_INT_D +Mux17| Mcel 5 12 ( 239)| inst_UDS_000_INT +Mux18| Mcel 0 5 ( 109)| SM_AMIGA_2_ +Mux19| ... | ... +Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 Mux21| Input Pin ( 86)| RST -Mux22| Mcel 6 10 ( 260)| CLK_000_D_5_ -Mux23| ... | ... +Mux22| Mcel 2 2 ( 152)| SM_AMIGA_i_7_ +Mux23| Mcel 2 9 ( 163)| CLK_000_D_0_ Mux24| ... | ... -Mux25| Mcel 0 2 ( 104)| CLK_000_D_4_ -Mux26| ... | ... -Mux27| ... | ... -Mux28| Mcel 0 13 ( 121)| CLK_000_D_3_ -Mux29| Mcel 5 4 ( 227)| inst_AS_030_000_SYNC -Mux30| ... | ... -Mux31| Mcel 5 0 ( 221)| SM_AMIGA_6_ +Mux25| Mcel 5 0 ( 221)| inst_AS_030_000_SYNC +Mux26| Mcel 4 5 ( 205)| inst_AS_030_D0 +Mux27| IOPin 7 6 ( 79)| SIZE_1_ +Mux28| ... | ... +Mux29| ... | ... +Mux30| Mcel 2 13 ( 169)| SM_AMIGA_6_ +Mux31| ... | ... Mux32| ... | ... --------------------------------------------------------------------------- =========================================================================== @@ -1546,19 +1545,19 @@ Mux32| ... | ... _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| RW| IO| | S | 2 | 4 to [ 0]| 1 XOR free 1| CLK_DIV_OUT|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig - 2|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | S | 2 | 4 to [ 2]| 1 XOR free + 2| RST_DLY_0_|NOD| | S | 4 | 4 to [ 2]| 1 XOR free 3| | ? | | S | | 4 free | 1 XOR free 4| E|OUT| | S | 2 | 4 to [ 4]| 1 XOR free 5|inst_RESET_OUT|NOD| | S | 2 | 4 to [ 5]| 1 XOR free - 6|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | S | 2 | 4 to [ 6]| 1 XOR free + 6| RST_DLY_2_|NOD| | S | 2 | 4 to [ 6]| 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free 8| A_0_| IO| | S | 3 | 4 to [ 8]| 1 XOR free - 9| RST_DLY_0_|NOD| | S | 4 | 4 to [ 9]| 1 XOR free -10| CLK_000_D_5_|NOD| | S | 1 | 4 free | 1 XOR to [10] for 1 PT sig + 9| cpu_est_0_|NOD| | S | 3 | 4 to [ 9]| 1 XOR free +10| RST_DLY_1_|NOD| | S | 2 :+: 1| 4 to [10]| 1 XOR to [10] 11| | ? | | S | | 4 free | 1 XOR free 12| SIZE_0_| IO| | S | 3 | 4 to [12]| 1 XOR free -13| RST_DLY_2_|NOD| | S | 2 | 4 to [13]| 1 XOR free -14| IPL_D0_2_|NOD| | S | 1 | 4 free | 1 XOR to [14] for 1 PT sig +13|inst_CLK_OUT_PRE_50|NOD| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig +14| IPL_D0_0_|NOD| | S | 1 | 4 free | 1 XOR to [14] for 1 PT sig 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== @@ -1573,19 +1572,19 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ _|_________________|__|__|___|_____|_______________________________________ 0| RW| IO| | S | 2 |=> can support up to [ 9] logic PT(s) 1| CLK_DIV_OUT|OUT| | S | 1 |=> can support up to [ 10] logic PT(s) - 2|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | S | 2 |=> can support up to [ 14] logic PT(s) + 2| RST_DLY_0_|NOD| | S | 4 |=> can support up to [ 14] logic PT(s) 3| | ? | | S | |=> can support up to [ 5] logic PT(s) 4| E|OUT| | S | 2 |=> can support up to [ 10] logic PT(s) 5|inst_RESET_OUT|NOD| | S | 2 |=> can support up to [ 10] logic PT(s) - 6|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | S | 2 |=> can support up to [ 10] logic PT(s) + 6| RST_DLY_2_|NOD| | S | 2 |=> can support up to [ 10] logic PT(s) 7| | ? | | S | |=> can support up to [ 5] logic PT(s) - 8| A_0_| IO| | S | 3 |=> can support up to [ 14] logic PT(s) - 9| RST_DLY_0_|NOD| | S | 4 |=> can support up to [ 14] logic PT(s) -10| CLK_000_D_5_|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) + 8| A_0_| IO| | S | 3 |=> can support up to [ 10] logic PT(s) + 9| cpu_est_0_|NOD| | S | 3 |=> can support up to [ 10] logic PT(s) +10| RST_DLY_1_|NOD| | S | 2 :+: 1|=> can support up to [ 9] logic PT(s) 11| | ? | | S | |=> can support up to [ 9] logic PT(s) -12| SIZE_0_| IO| | S | 3 |=> can support up to [ 14] logic PT(s) -13| RST_DLY_2_|NOD| | S | 2 |=> can support up to [ 14] logic PT(s) -14| IPL_D0_2_|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) +12| SIZE_0_| IO| | S | 3 |=> can support up to [ 18] logic PT(s) +13|inst_CLK_OUT_PRE_50|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) +14| IPL_D0_0_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) 15| | ? | | S | |=> can support up to [ 9] logic PT(s) --------------------------------------------------------------------------- =========================================================================== @@ -1598,19 +1597,19 @@ _|_________________|__|__|___|_____|_______________________________________ _|_________________|__|_____|____________________|________________________ 0| RW| IO| | => | 5 ( 6) 7 0 | 70 ( 71) 72 65 1| CLK_DIV_OUT|OUT| | => | 5 6 7 ( 0)| 70 71 72 ( 65) - 2|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | => | 6 7 0 1 | 71 72 65 66 + 2| RST_DLY_0_|NOD| | => | 6 7 0 1 | 71 72 65 66 3| | | | => | 6 7 0 1 | 71 72 65 66 4| E|OUT| | => | 7 0 ( 1) 2 | 72 65 ( 66) 67 5|inst_RESET_OUT|NOD| | => | 7 0 1 2 | 72 65 66 67 - 6|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | => | 0 1 2 3 | 65 66 67 68 + 6| RST_DLY_2_|NOD| | => | 0 1 2 3 | 65 66 67 68 7| | | | => | 0 1 2 3 | 65 66 67 68 8| A_0_| IO| | => | 1 2 3 ( 4)| 66 67 68 ( 69) - 9| RST_DLY_0_|NOD| | => | 1 2 3 4 | 66 67 68 69 -10| CLK_000_D_5_|NOD| | => | 2 3 4 5 | 67 68 69 70 + 9| cpu_est_0_|NOD| | => | 1 2 3 4 | 66 67 68 69 +10| RST_DLY_1_|NOD| | => | 2 3 4 5 | 67 68 69 70 11| | | | => | 2 3 4 5 | 67 68 69 70 12| SIZE_0_| IO| | => | 3 4 ( 5) 6 | 68 69 ( 70) 71 -13| RST_DLY_2_|NOD| | => | 3 4 5 6 | 68 69 70 71 -14| IPL_D0_2_|NOD| | => | 4 5 6 7 | 69 70 71 72 +13|inst_CLK_OUT_PRE_50|NOD| | => | 3 4 5 6 | 68 69 70 71 +14| IPL_D0_0_|NOD| | => | 4 5 6 7 | 69 70 71 72 15| | | | => | 4 5 6 7 | 69 70 71 72 --------------------------------------------------------------------------- =========================================================================== @@ -1668,7 +1667,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 1 [IOpin 1 | 66|OUT E|*| ] [RegIn 1 |249| -| | ] - [MCell 2 |248|NOD inst_AMIGA_BUS_ENABLE_DMA_HIGH| |*] + [MCell 2 |248|NOD RST_DLY_0_| |*] [MCell 3 |250| -| | ] 2 [IOpin 2 | 67|INP IPL_0_|*|*] @@ -1678,27 +1677,27 @@ IMX No. | +---- Block IO Pin or Macrocell Number 3 [IOpin 3 | 68|INP IPL_2_|*|*] [RegIn 3 |255| -| | ] - [MCell 6 |254|NOD inst_AMIGA_BUS_ENABLE_DMA_LOW| |*] + [MCell 6 |254|NOD RST_DLY_2_| |*] [MCell 7 |256| -| | ] 4 [IOpin 4 | 69| IO A_0_|*|*] paired w/[ RN_A_0_] [RegIn 4 |258| -| | ] [MCell 8 |257|NOD RN_A_0_| |*] paired w/[ A_0_] - [MCell 9 |259|NOD RST_DLY_0_| |*] + [MCell 9 |259|NOD cpu_est_0_| |*] 5 [IOpin 5 | 70| IO SIZE_0_|*|*] paired w/[ RN_SIZE_0_] [RegIn 5 |261| -| | ] - [MCell 10 |260|NOD CLK_000_D_5_| |*] + [MCell 10 |260|NOD RST_DLY_1_| |*] [MCell 11 |262| -| | ] 6 [IOpin 6 | 71| IO RW|*|*] paired w/[ RN_RW] [RegIn 6 |264| -| | ] [MCell 12 |263|NOD RN_SIZE_0_| |*] paired w/[ SIZE_0_] - [MCell 13 |265|NOD RST_DLY_2_| |*] + [MCell 13 |265|NOD inst_CLK_OUT_PRE_50| |*] 7 [IOpin 7 | 72| -| | ] [RegIn 7 |267| -| | ] - [MCell 14 |266|NOD IPL_D0_2_| |*] + [MCell 14 |266|NOD IPL_D0_0_| |*] [MCell 15 |268| -| | ] --------------------------------------------------------------------------- =========================================================================== @@ -1707,38 +1706,38 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| Input Pin ( 86)| RST -Mux01| Mcel 3 13 ( 193)| cpu_est_1_ -Mux02| Mcel 1 10 ( 140)| RST_DLY_1_ -Mux03| Mcel 3 2 ( 176)| cpu_est_2_ -Mux04| IOPin 6 3 ( 68)| IPL_2_ -Mux05| Input Pin ( 14)| nEXP_SPACE +Mux00| IOPin 6 2 ( 67)| IPL_0_ +Mux01| ... | ... +Mux02| ... | ... +Mux03| Mcel 2 9 ( 163)| CLK_000_D_0_ +Mux04| Mcel 3 6 ( 182)| inst_CLK_OUT_PRE_D +Mux05| Mcel 6 6 ( 254)| RST_DLY_2_ Mux06| IOPin 7 5 ( 80)| RW_000 Mux07| Mcel 6 12 ( 263)| RN_SIZE_0_ Mux08| IOPin 3 3 ( 32)| UDS_000 -Mux09| Mcel 6 13 ( 265)| RST_DLY_2_ -Mux10| Mcel 6 8 ( 257)| RN_A_0_ -Mux11| IOPin 5 0 ( 60)| A_1_ -Mux12| Mcel 6 9 ( 259)| RST_DLY_0_ -Mux13| Mcel 7 5 ( 277)| CLK_000_D_1_ +Mux09| Mcel 0 12 ( 119)| cpu_est_2_ +Mux10| Mcel 6 9 ( 259)| cpu_est_0_ +Mux11| ... | ... +Mux12| Mcel 6 13 ( 265)| inst_CLK_OUT_PRE_50 +Mux13| Mcel 6 8 ( 257)| RN_A_0_ Mux14| ... | ... -Mux15| Mcel 0 12 ( 119)| cpu_est_3_ -Mux16| Mcel 4 8 ( 209)| inst_CLK_OUT_PRE_D +Mux15| Input Pin ( 14)| nEXP_SPACE +Mux16| Mcel 4 8 ( 209)| inst_BGACK_030_INT_D Mux17| Mcel 6 0 ( 245)| RN_RW -Mux18| ... | ... +Mux18| Mcel 0 8 ( 113)| cpu_est_1_ Mux19| ... | ... Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux21| Mcel 0 1 ( 103)| inst_BGACK_030_INT_D -Mux22| Mcel 0 2 ( 104)| CLK_000_D_4_ -Mux23| Mcel 6 6 ( 254)| inst_AMIGA_BUS_ENABLE_DMA_LOW +Mux21| Input Pin ( 86)| RST +Mux22| Mcel 6 10 ( 260)| RST_DLY_1_ +Mux23| Mcel 6 2 ( 248)| RST_DLY_0_ Mux24| IOPin 3 4 ( 31)| LDS_000 -Mux25| Mcel 3 9 ( 187)| CLK_000_D_0_ +Mux25| Mcel 3 9 ( 187)| cpu_est_3_ Mux26| ... | ... -Mux27| ... | ... +Mux27| Mcel 7 5 ( 277)| CLK_000_D_1_ Mux28| ... | ... Mux29| ... | ... Mux30| ... | ... -Mux31| Mcel 6 2 ( 248)| inst_AMIGA_BUS_ENABLE_DMA_HIGH +Mux31| ... | ... Mux32| Mcel 6 5 ( 253)| inst_RESET_OUT --------------------------------------------------------------------------- =========================================================================== @@ -1753,18 +1752,18 @@ Mux32| Mcel 6 5 ( 253)| inst_RESET_OUT _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| RW_000| IO| | S | 4 | 4 to [ 0]| 1 XOR free 1| FPU_CS|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig - 2| CLK_000_D_2_|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig + 2|inst_DSACK1_INT|NOD| | S | 2 | 4 to [ 2]| 1 XOR free 3| | ? | | S | | 4 free | 1 XOR free 4| BGACK_030| IO| | S | 3 | 4 to [ 4]| 1 XOR free 5| CLK_000_D_1_|NOD| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig - 6| inst_DTACK_D0|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig + 6| CLK_000_D_2_|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig 7| | ? | | S | | 4 free | 1 XOR free 8| AS_030| IO| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig 9| DSACK1|OUT| | S | 1 | 4 free | 1 XOR to [ 9] for 1 PT sig 10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free 12| SIZE_1_| IO| | S | 3 | 4 to [12]| 1 XOR free -13|inst_AS_030_D0|NOD| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig +13| SM_AMIGA_0_|NOD| | S | 3 | 4 to [13]| 1 XOR free 14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- @@ -1778,21 +1777,21 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| RW_000| IO| | S | 4 |=> can support up to [ 13] logic PT(s) - 1| FPU_CS|OUT| | S | 1 |=> can support up to [ 14] logic PT(s) - 2| CLK_000_D_2_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) - 3| | ? | | S | |=> can support up to [ 13] logic PT(s) + 0| RW_000| IO| | S | 4 |=> can support up to [ 9] logic PT(s) + 1| FPU_CS|OUT| | S | 1 |=> can support up to [ 10] logic PT(s) + 2|inst_DSACK1_INT|NOD| | S | 2 |=> can support up to [ 14] logic PT(s) + 3| | ? | | S | |=> can support up to [ 9] logic PT(s) 4| BGACK_030| IO| | S | 3 |=> can support up to [ 18] logic PT(s) 5| CLK_000_D_1_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) - 6| inst_DTACK_D0|NOD| | S | 1 |=> can support up to [ 18] logic PT(s) + 6| CLK_000_D_2_|NOD| | S | 1 |=> can support up to [ 18] logic PT(s) 7| | ? | | S | |=> can support up to [ 17] logic PT(s) 8| AS_030| IO| | S | 1 |=> can support up to [ 19] logic PT(s) 9| DSACK1|OUT| | S | 1 |=> can support up to [ 19] logic PT(s) 10| | ? | | S | |=> can support up to [ 14] logic PT(s) -11| | ? | | S | |=> can support up to [ 14] logic PT(s) -12| SIZE_1_| IO| | S | 3 |=> can support up to [ 19] logic PT(s) -13|inst_AS_030_D0|NOD| | S | 1 |=> can support up to [ 15] logic PT(s) -14| | ? | | S | |=> can support up to [ 14] logic PT(s) +11| | ? | | S | |=> can support up to [ 10] logic PT(s) +12| SIZE_1_| IO| | S | 3 |=> can support up to [ 15] logic PT(s) +13| SM_AMIGA_0_|NOD| | S | 3 |=> can support up to [ 15] logic PT(s) +14| | ? | | S | |=> can support up to [ 10] logic PT(s) 15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- =========================================================================== @@ -1805,18 +1804,18 @@ _|_________________|__|__|___|_____|_______________________________________ _|_________________|__|_____|____________________|________________________ 0| RW_000| IO| | => |( 5) 6 7 0 |( 80) 79 78 85 1| FPU_CS|OUT| | => | 5 6 ( 7) 0 | 80 79 ( 78) 85 - 2| CLK_000_D_2_|NOD| | => | 6 7 0 1 | 79 78 85 84 + 2|inst_DSACK1_INT|NOD| | => | 6 7 0 1 | 79 78 85 84 3| | | | => | 6 7 0 1 | 79 78 85 84 4| BGACK_030| IO| | => | 7 0 1 ( 2)| 78 85 84 ( 83) 5| CLK_000_D_1_|NOD| | => | 7 0 1 2 | 78 85 84 83 - 6| inst_DTACK_D0|NOD| | => | 0 1 2 3 | 85 84 83 82 + 6| CLK_000_D_2_|NOD| | => | 0 1 2 3 | 85 84 83 82 7| | | | => | 0 1 2 3 | 85 84 83 82 8| AS_030| IO| | => | 1 2 ( 3) 4 | 84 83 ( 82) 81 9| DSACK1|OUT| | => | 1 2 3 ( 4)| 84 83 82 ( 81) 10| | | | => | 2 3 4 5 | 83 82 81 80 11| | | | => | 2 3 4 5 | 83 82 81 80 12| SIZE_1_| IO| | => | 3 4 5 ( 6)| 82 81 80 ( 79) -13|inst_AS_030_D0|NOD| | => | 3 4 5 6 | 82 81 80 79 +13| SM_AMIGA_0_|NOD| | => | 3 4 5 6 | 82 81 80 79 14| | | | => | 4 5 6 7 | 81 80 79 78 15| | | | => | 4 5 6 7 | 81 80 79 78 --------------------------------------------------------------------------- @@ -1875,7 +1874,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 1 [IOpin 1 | 84|INP A_DECODE_22_|*|*] [RegIn 1 |273| -| | ] - [MCell 2 |272|NOD CLK_000_D_2_| |*] + [MCell 2 |272|NOD inst_DSACK1_INT| |*] [MCell 3 |274| -| | ] 2 [IOpin 2 | 83| IO BGACK_030|*| ] paired w/[ RN_BGACK_030] @@ -1885,7 +1884,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 3 [IOpin 3 | 82| IO AS_030|*|*] [RegIn 3 |279| -| | ] - [MCell 6 |278|NOD inst_DTACK_D0| |*] + [MCell 6 |278|NOD CLK_000_D_2_| |*] [MCell 7 |280| -| | ] 4 [IOpin 4 | 81|OUT DSACK1|*| ] @@ -1901,7 +1900,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 6 [IOpin 6 | 79| IO SIZE_1_|*|*] paired w/[ RN_SIZE_1_] [RegIn 6 |288| -| | ] [MCell 12 |287|NOD RN_SIZE_1_| |*] paired w/[ SIZE_1_] - [MCell 13 |289|NOD inst_AS_030_D0| |*] + [MCell 13 |289|NOD SM_AMIGA_0_| |*] 7 [IOpin 7 | 78|OUT FPU_CS|*| ] [RegIn 7 |291| -| | ] @@ -1916,35 +1915,35 @@ IMX No. | +---- Block IO Pin or Macrocell Number --|--|--------------------|--------------------------------------------------- Mux00| Input Pin ( 86)| RST Mux01| IOPin 5 2 ( 58)| FC_1_ -Mux02| Mcel 5 8 ( 233)| SM_AMIGA_i_7_ -Mux03| Mcel 0 8 ( 113)| SM_AMIGA_0_ +Mux02| Mcel 2 2 ( 152)| SM_AMIGA_i_7_ +Mux03| Mcel 2 9 ( 163)| CLK_000_D_0_ Mux04| IOPin 0 4 ( 95)| A_DECODE_18_ Mux05| Input Pin ( 14)| nEXP_SPACE Mux06| IOPin 0 5 ( 96)| A_DECODE_16_ -Mux07| Mcel 3 9 ( 187)| CLK_000_D_0_ +Mux07| Mcel 7 13 ( 289)| SM_AMIGA_0_ Mux08| IOPin 3 3 ( 32)| UDS_000 -Mux09| IOPin 7 3 ( 82)| AS_030 -Mux10| ... | ... -Mux11| IOPin 6 6 ( 71)| RW +Mux09| Mcel 0 1 ( 103)| inst_AS_000_DMA +Mux10| Mcel 5 4 ( 227)| SM_AMIGA_1_ +Mux11| IOPin 0 0 ( 91)| FPU_SENSE Mux12| IOPin 0 6 ( 97)| A_DECODE_19_ Mux13| IOPin 5 1 ( 59)| A_DECODE_17_ -Mux14| IOPin 3 5 ( 30)| DTACK +Mux14| Mcel 7 2 ( 272)| inst_DSACK1_INT Mux15| Mcel 7 12 ( 287)| RN_SIZE_1_ -Mux16| IOPin 4 1 ( 42)| AS_000 +Mux16| Mcel 4 8 ( 209)| inst_BGACK_030_INT_D Mux17| IOPin 5 3 ( 57)| FC_0_ Mux18| IOPin 3 7 ( 28)| BGACK_000 -Mux19| IOPin 0 0 ( 91)| FPU_SENSE +Mux19| IOPin 7 3 ( 82)| AS_030 Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux21| Mcel 0 1 ( 103)| inst_BGACK_030_INT_D +Mux21| ... | ... Mux22| Mcel 6 5 ( 253)| inst_RESET_OUT Mux23| Mcel 7 0 ( 269)| RN_RW_000 Mux24| IOPin 3 4 ( 31)| LDS_000 -Mux25| Mcel 5 0 ( 221)| SM_AMIGA_6_ -Mux26| ... | ... +Mux25| IOPin 6 6 ( 71)| RW +Mux26| IOPin 4 1 ( 42)| AS_000 Mux27| Mcel 7 5 ( 277)| CLK_000_D_1_ Mux28| ... | ... Mux29| ... | ... -Mux30| Mcel 2 13 ( 169)| inst_AS_000_DMA -Mux31| Mcel 5 12 ( 239)| inst_DSACK1_INT +Mux30| Mcel 2 13 ( 169)| SM_AMIGA_6_ +Mux31| ... | ... Mux32| ... | ... --------------------------------------------------------------------------- \ No newline at end of file diff --git a/Logic/68030_tk.rpt b/Logic/68030_tk.rpt index c4e9ae4..63f533c 100644 --- a/Logic/68030_tk.rpt +++ b/Logic/68030_tk.rpt @@ -12,7 +12,7 @@ Project_Summary Project Name : 68030_tk Project Path : C:\Users\Matze\Amiga\Hardwarehacks\68030-TK\GitHub\Logic -Project Fitted on : Thu Oct 06 22:04:16 2016 +Project Fitted on : Sat Oct 15 23:48:29 2016 Device : M4A5-128/64 Package : 100TQFP @@ -40,8 +40,8 @@ Design_Summary Total Input Pins : 24 Total Output Pins : 19 Total Bidir I/O Pins : 18 - Total Flip-Flops : 57 - Total Product Terms : 205 + Total Flip-Flops : 56 + Total Product Terms : 199 Total Reserved Pins : 0 Total Reserved Blocks : 0 @@ -54,12 +54,12 @@ Dedicated Pins Input-Only Pins 2 2 0 --> 100% Clock/Input Pins 4 4 0 --> 100% I/O Pins 64 55 9 --> 85% -Logic Macrocells 128 82 46 --> 64% +Logic Macrocells 128 81 47 --> 63% Input Registers 64 0 64 --> 0% Unusable Macrocells .. 0 .. -CSM Outputs/Total Block Inputs 264 208 56 --> 78% -Logical Product Terms 640 208 432 --> 32% +CSM Outputs/Total Block Inputs 264 206 58 --> 78% +Logical Product Terms 640 202 438 --> 31% Product Term Clusters 128 51 77 --> 39%  @@ -71,14 +71,14 @@ Blocks_Resource_Summary --------------------------------------------------------------------------------- Maximum 33 8 8 -- -- 16 80 16 - --------------------------------------------------------------------------------- -Block A 25 8 0 12 0 4 31 10 Lo -Block B 25 8 0 12 0 4 45 6 Lo -Block C 25 7 0 12 0 4 36 8 Lo -Block D 24 8 0 12 0 4 27 8 Lo +Block A 27 8 0 11 0 5 45 5 Lo +Block B 23 8 0 12 0 4 38 9 Lo +Block C 20 7 0 12 0 4 21 11 Lo +Block D 29 8 0 12 0 4 25 10 Lo Block E 30 4 0 7 0 9 9 14 Lo -Block F 26 5 0 5 0 11 18 10 Lo -Block G 25 7 0 12 0 4 25 7 Lo -Block H 28 8 0 10 0 6 17 13 Lo +Block F 26 5 0 5 0 11 17 10 Lo +Block G 23 7 0 12 0 4 27 7 Lo +Block H 28 8 0 10 0 6 20 11 Lo --------------------------------------------------------------------------------- Four rightmost columns above reflect last status of the placement process. @@ -144,7 +144,7 @@ Block Reservation : No @Zero_Hold_Time Yes -@Pull_up Yes +@Pull_up No @User_Signature #H0 @@ -287,7 +287,7 @@ Input_Signal_List Pin r e O Input Pin Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- - 60 F . I/O ------G- Low Slow A_1_ + 60 F . I/O --C--F-- Low Slow A_1_ 96 A . I/O ----EF-H Low Slow A_DECODE_16_ 59 F . I/O ----EF-H Low Slow A_DECODE_17_ 95 A . I/O ----EF-H Low Slow A_DECODE_18_ @@ -298,19 +298,19 @@ Pin Blk PTs Type e s E Fanout Pwr Slew Signal 85 H . I/O ----E--- Low Slow A_DECODE_23_ 28 D . I/O ----E--H Low Slow BGACK_000 21 C . I/O ---D---- Low Slow BG_030 - 30 D . I/O -------H Low Slow DTACK + 30 D . I/O -B------ Low Slow DTACK 57 F . I/O ----EF-H Low Slow FC_0_ 58 F . I/O ----EF-H Low Slow FC_1_ 91 A . I/O ----E--H Low Slow FPU_SENSE - 67 G . I/O AB------ Low Slow IPL_0_ - 56 F . I/O -B------ Low Slow IPL_1_ - 68 G . I/O -B----G- Low Slow IPL_2_ - 11 . . Ck/I ---D---- - Slow CLK_000 + 67 G . I/O -B----G- Low Slow IPL_0_ + 56 F . I/O -B-D---- Low Slow IPL_1_ + 68 G . I/O -B------ Low Slow IPL_2_ + 11 . . Ck/I --C----- - Slow CLK_000 14 . . Ck/I ABCDEFGH - Slow nEXP_SPACE - 36 . . Ded --C----- - Slow VPA + 36 . . Ded A------- - Slow VPA 61 . . Ck/I ABCDEFGH - Slow CLK_OSZI - 64 . . Ck/I --C----- - Slow CLK_030 - 86 . . Ded ABCD-FGH - Slow RST + 64 . . Ck/I A------- - Slow CLK_030 + 86 . . Ded ABCDEFGH - Slow RST ---------------------------------------------------------------------- Power : Hi = High @@ -340,9 +340,9 @@ Pin Blk PTs Type e s E Fanout Pwr Slew Signal 98 A 1 COM -------- Low Fast DS_030 66 G 2 COM -------- Low Fast E 78 H 1 COM -------- Low Fast FPU_CS - 8 B 10 DFF -------- Low Fast IPL_030_0_ - 7 B 10 DFF -------- Low Fast IPL_030_1_ - 9 B 10 DFF -------- Low Fast IPL_030_2_ + 8 B 9 TFF -------- Low Fast IPL_030_0_ + 7 B 9 TFF -------- Low Fast IPL_030_1_ + 9 B 9 TFF -------- Low Fast IPL_030_2_ 3 B 1 COM -------- Low Fast RESET 35 D 3 TFF -------- Low Fast VMA ---------------------------------------------------------------------- @@ -368,16 +368,16 @@ Pin Blk PTs Type e s E Fanout Pwr Slew Signal 6 B 1 COM ----E--- Low Fast AHIGH_29_ 5 B 1 COM ----E--- Low Fast AHIGH_30_ 4 B 1 COM ----E--- Low Fast AHIGH_31_ - 42 E 1 COM A-CDE--H Low Fast AS_000 - 82 H 1 COM -BC-EF-H Low Fast AS_030 - 69 G 3 DFF --C--F-- Low Fast A_0_ - 41 E 1 COM A------- Low Fast BERR - 31 D 1 COM --C---GH Low Fast LDS_000 + 42 E 1 COM A---E--H Low Fast AS_000 + 82 H 1 COM -BCDEF-H Low Fast AS_030 + 69 G 3 DFF -----F-- Low Fast A_0_ + 41 E 1 COM A--D---- Low Fast BERR + 31 D 1 COM A-----GH Low Fast LDS_000 71 G 2 DFF -B-----H Low Fast RW - 80 H 4 DFF --C-E-G- Low Fast RW_000 - 70 G 3 DFF --C----- Low Fast SIZE_0_ - 79 H 3 DFF --C----- Low Fast SIZE_1_ - 32 D 1 COM --C---GH Low Fast UDS_000 + 80 H 4 DFF A---E-G- Low Fast RW_000 + 70 G 3 DFF -----F-- Low Fast SIZE_0_ + 79 H 3 DFF -----F-- Low Fast SIZE_1_ + 32 D 1 COM A-----GH Low Fast UDS_000 ---------------------------------------------------------------------- Power : Hi = High @@ -393,62 +393,61 @@ Buried_Signal_List Pin r e O Node #Mc Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- - E5 E 2 COM ----E--- Low Slow CIIN_0 - D9 D 1 DFF ABCD-FGH Low Slow CLK_000_D_0_ + E9 E 2 COM ----E--- Low Slow CIIN_0 + C9 C 1 DFF ABCD-FGH Low Slow CLK_000_D_0_ H5 H 1 DFF ABCD-FGH Low Slow CLK_000_D_1_ - H2 H 1 DFF A----F-- Low Slow CLK_000_D_2_ - A13 A 1 DFF A----F-- Low Slow CLK_000_D_3_ - A2 A 1 DFF -----FG- Low Slow CLK_000_D_4_ - G10 G 1 DFF -----F-- Low Slow CLK_000_D_5_ - D10 D 3 DFF --CD---- Low Slow CYCLE_DMA_0_ - D6 D 4 DFF --CD---- Low Slow CYCLE_DMA_1_ - A14 A 1 DFF -B------ Low Slow IPL_D0_0_ - B14 B 1 DFF -B------ Low Slow IPL_D0_1_ - G14 G 1 DFF -B------ Low Slow IPL_D0_2_ + H6 H 1 DFF ---D---- Low Slow CLK_000_D_2_ + D10 D 1 DFF -BC----- Low Slow CLK_000_D_3_ + B10 B 1 DFF --C----- Low Slow CLK_000_D_4_ + A10 A 3 DFF A------- Low Slow CYCLE_DMA_0_ + A6 A 4 DFF A------- Low Slow CYCLE_DMA_1_ + G14 G 1 DFF -B------ Low Slow IPL_D0_0_ + D14 D 1 DFF -B------ Low Slow IPL_D0_1_ + B14 B 1 DFF -B------ Low Slow IPL_D0_2_ G8 G 3 DFF ------G- Low - RN_A_0_ --> A_0_ H4 H 3 DFF ABCDEFGH Low - RN_BGACK_030 --> BGACK_030 D1 D 2 DFF ---D---- Low - RN_BG_000 --> BG_000 - B5 B 10 DFF -B------ Low - RN_IPL_030_0_ --> IPL_030_0_ - B9 B 10 DFF -B------ Low - RN_IPL_030_1_ --> IPL_030_1_ - B4 B 10 DFF -B------ Low - RN_IPL_030_2_ --> IPL_030_2_ + B5 B 9 TFF -B------ Low - RN_IPL_030_0_ --> IPL_030_0_ + B9 B 9 TFF -B------ Low - RN_IPL_030_1_ --> IPL_030_1_ + B4 B 9 TFF -B------ Low - RN_IPL_030_2_ --> IPL_030_2_ G0 G 2 DFF ------G- Low - RN_RW --> RW H0 H 4 DFF -------H Low - RN_RW_000 --> RW_000 G12 G 3 DFF ------G- Low - RN_SIZE_0_ --> SIZE_0_ H12 H 3 DFF -------H Low - RN_SIZE_1_ --> SIZE_1_ D0 D 3 TFF A--D---- Low - RN_VMA --> VMA - G9 G 4 DFF -B----G- Low Slow RST_DLY_0_ - B10 B 2 DFF -B----G- Low Slow RST_DLY_1_ - G13 G 2 DFF -B----G- Low Slow RST_DLY_2_ - A8 A 4 DFF A----F-H Low Slow SM_AMIGA_0_ - A5 A 4 DFF A----F-- Low Slow SM_AMIGA_1_ - A6 A 5 DFF A------- Low Slow SM_AMIGA_2_ - A10 A 5 TFF A------- Low Slow SM_AMIGA_3_ - A9 A 3 DFF AB------ Low Slow SM_AMIGA_4_ - B13 B 3 DFF AB------ Low Slow SM_AMIGA_5_ - F0 F 3 DFF -BC--F-H Low Slow SM_AMIGA_6_ - F8 F 3 TFF -----F-H Low Slow SM_AMIGA_i_7_ - D14 D 3 DFF A--D---- Low Slow cpu_est_0_ - D13 D 4 DFF A--D--G- Low Slow cpu_est_1_ - D2 D 1 DFF A--D--G- Low Slow cpu_est_2_ - A12 A 4 DFF A--D--G- Low Slow cpu_est_3_ - G2 G 2 DFF ---D--G- Low Slow inst_AMIGA_BUS_ENABLE_DMA_HIGH - G6 G 2 DFF --C---G- Low Slow inst_AMIGA_BUS_ENABLE_DMA_LOW - C13 C 7 DFF --C----H Low Slow inst_AS_000_DMA - C6 C 2 DFF --C-E--- Low Slow inst_AS_000_INT - F4 F 7 DFF ---D-F-- Low Slow inst_AS_030_000_SYNC - H13 H 1 DFF ---DEF-- Low Slow inst_AS_030_D0 - A1 A 1 DFF -----FGH Low Slow inst_BGACK_030_INT_D - C14 C 8 DFF --C----- Low Slow inst_CLK_030_H - E9 E 1 DFF ----E--- Low Slow inst_CLK_OUT_PRE_50 - E8 E 1 DFF -B----G- Low Slow inst_CLK_OUT_PRE_D - F12 F 2 DFF -----F-H Low Slow inst_DSACK1_INT - C9 C 9 DFF A-C----- Low Slow inst_DS_000_DMA - B6 B 3 DFF -B-D---- Low Slow inst_DS_000_ENABLE - H6 H 1 DFF A------- Low Slow inst_DTACK_D0 - C2 C 3 DFF --CD---- Low Slow inst_LDS_000_INT + G2 G 4 DFF ------G- Low Slow RST_DLY_0_ + G10 G 2 DFF ------G- Low Slow RST_DLY_1_ + G6 G 2 DFF ------G- Low Slow RST_DLY_2_ + H13 H 3 DFF --C----H Low Slow SM_AMIGA_0_ + F4 F 3 DFF -----F-H Low Slow SM_AMIGA_1_ + A5 A 5 DFF A----F-- Low Slow SM_AMIGA_2_ + D13 D 5 TFF A--D---- Low Slow SM_AMIGA_3_ + D2 D 3 DFF -B-D---- Low Slow SM_AMIGA_4_ + C6 C 3 DFF --CD---- Low Slow SM_AMIGA_5_ + C13 C 3 DFF -BC--F-H Low Slow SM_AMIGA_6_ + C2 C 3 TFF --C--F-H Low Slow SM_AMIGA_i_7_ + G9 G 3 DFF A--D--G- Low Slow cpu_est_0_ + A8 A 4 DFF A--D--G- Low Slow cpu_est_1_ + A12 A 1 DFF A--D--G- Low Slow cpu_est_2_ + D9 D 4 DFF A--D--G- Low Slow cpu_est_3_ + C14 C 2 DFF --CD---- Low Slow inst_AMIGA_BUS_ENABLE_DMA_HIGH + F1 F 2 DFF --C--F-- Low Slow inst_AMIGA_BUS_ENABLE_DMA_LOW + A1 A 7 DFF A------H Low Slow inst_AS_000_DMA + C10 C 2 DFF --C-E--- Low Slow inst_AS_000_INT + F0 F 7 DFF --CD-F-- Low Slow inst_AS_030_000_SYNC + E5 E 1 DFF ---DEF-- Low Slow inst_AS_030_D0 + E8 E 1 DFF --C--FGH Low Slow inst_BGACK_030_INT_D + A2 A 8 DFF A------- Low Slow inst_CLK_030_H + G13 G 1 DFF ---D--G- Low Slow inst_CLK_OUT_PRE_50 + D6 D 1 DFF -B----G- Low Slow inst_CLK_OUT_PRE_D + H2 H 2 DFF -------H Low Slow inst_DSACK1_INT + A13 A 9 DFF A------- Low Slow inst_DS_000_DMA + B13 B 3 DFF -B-D---- Low Slow inst_DS_000_ENABLE + B6 B 1 DFF A--D---- Low Slow inst_DTACK_D0 + F8 F 3 DFF ---D-F-- Low Slow inst_LDS_000_INT G5 G 2 DFF ABCDE-GH Low Slow inst_RESET_OUT - F1 F 2 DFF ---D-F-- Low Slow inst_UDS_000_INT - C10 C 1 DFF A--D---- Low Slow inst_VPA_D + F12 F 2 DFF ---D-F-- Low Slow inst_UDS_000_INT + A9 A 1 DFF A--D---- Low Slow inst_VPA_D ---------------------------------------------------------------------- Power : Hi = High @@ -466,179 +465,180 @@ Signal Source : Fanout List AHIGH_31_{ C}: CIIN{ E} CIIN_0{ E} A_DECODE_23_{ I}: CIIN{ E} CIIN_0{ E} IPL_2_{ H}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} - : IPL_D0_2_{ G} + : IPL_D0_2_{ B} FC_1_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ F} AS_030{ I}: AS_000{ E} BERR{ E} FPU_CS{ H} - : DSACK1{ H} inst_AS_030_D0{ H}inst_AS_030_000_SYNC{ F} - :inst_DS_000_ENABLE{ B}inst_DSACK1_INT{ F}inst_AS_000_INT{ C} + : DSACK1{ H}AMIGA_BUS_ENABLE_HIGH{ D} inst_AS_030_D0{ E} + :inst_AS_030_000_SYNC{ F}inst_DS_000_ENABLE{ B}inst_DSACK1_INT{ H} + :inst_AS_000_INT{ C} AS_000{ F}: AS_030{ H} DS_030{ A}AMIGA_BUS_DATA_DIR{ E} - : BGACK_030{ H}inst_AS_000_DMA{ C}inst_DS_000_DMA{ C} - : CYCLE_DMA_0_{ D} CYCLE_DMA_1_{ D} inst_CLK_030_H{ C} + : BGACK_030{ H}inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} + : CYCLE_DMA_0_{ A} CYCLE_DMA_1_{ A} inst_CLK_030_H{ A} UDS_000{ E}: SIZE_1_{ H} SIZE_0_{ G} A_0_{ G} - :inst_AS_000_DMA{ C}inst_DS_000_DMA{ C} inst_CLK_030_H{ C} - LDS_000{ E}: SIZE_1_{ H} SIZE_0_{ G}inst_AS_000_DMA{ C} - :inst_DS_000_DMA{ C} inst_CLK_030_H{ C} + :inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} inst_CLK_030_H{ A} + LDS_000{ E}: SIZE_1_{ H} SIZE_0_{ G}inst_AS_000_DMA{ A} + :inst_DS_000_DMA{ A} inst_CLK_030_H{ A} nEXP_SPACE{. }: AHIGH_31_{ B} AS_030{ H} DS_030{ A} : AHIGH_30_{ B} AHIGH_29_{ B} AHIGH_28_{ C} : AHIGH_27_{ C} AHIGH_26_{ C} AHIGH_25_{ C} : AHIGH_24_{ C} DSACK1{ H}AMIGA_BUS_DATA_DIR{ E} : SIZE_1_{ H} BG_000{ D} SIZE_0_{ G} - : A_0_{ G}inst_AS_030_000_SYNC{ F} SM_AMIGA_6_{ F} - : SM_AMIGA_i_7_{ F} CIIN_0{ E} - BERR{ F}: SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} + : A_0_{ G}inst_AS_030_000_SYNC{ F} SM_AMIGA_6_{ C} + : SM_AMIGA_i_7_{ C} CIIN_0{ E} + BERR{ F}: SM_AMIGA_3_{ D} SM_AMIGA_2_{ A} BG_030{ D}: BG_000{ D} - BGACK_000{ E}: BERR{ E} FPU_CS{ H} BGACK_030{ H} - CLK_030{. }:inst_AS_000_DMA{ C}inst_DS_000_DMA{ C} inst_CLK_030_H{ C} AHIGH_30_{ C}: CIIN{ E} CIIN_0{ E} - CLK_000{. }: CLK_000_D_0_{ D} + BGACK_000{ E}: BERR{ E} FPU_CS{ H} BGACK_030{ H} AHIGH_29_{ C}: CIIN{ E} CIIN_0{ E} + CLK_030{. }:inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} inst_CLK_030_H{ A} AHIGH_28_{ D}: CIIN{ E} CIIN_0{ E} + CLK_000{. }: CLK_000_D_0_{ C} AHIGH_27_{ D}: CIIN{ E} CIIN_0{ E} AHIGH_26_{ D}: CIIN{ E} CIIN_0{ E} AHIGH_25_{ D}: CIIN{ E} CIIN_0{ E} - FPU_SENSE{ B}: BERR{ E} FPU_CS{ H} AHIGH_24_{ D}: CIIN{ E} CIIN_0{ E} A_DECODE_22_{ I}: CIIN{ E} CIIN_0{ E} - DTACK{ E}: inst_DTACK_D0{ H} + FPU_SENSE{ B}: BERR{ E} FPU_CS{ H} A_DECODE_21_{ B}: CIIN{ E} CIIN_0{ E} A_DECODE_20_{ B}: CIIN{ E} CIIN_0{ E} + DTACK{ E}: inst_DTACK_D0{ B} A_DECODE_19_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ F} - VPA{. }: inst_VPA_D{ C} A_DECODE_18_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ F} A_DECODE_17_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ F} - RST{. }: SIZE_1_{ H} IPL_030_2_{ B} RW_000{ H} - : BG_000{ D} BGACK_030{ H} SIZE_0_{ G} - : VMA{ D} RW{ G} A_0_{ G} - : IPL_030_1_{ B} IPL_030_0_{ B}inst_AMIGA_BUS_ENABLE_DMA_LOW{ G} - : inst_AS_030_D0{ H}inst_AS_030_000_SYNC{ F}inst_BGACK_030_INT_D{ A} - :inst_AS_000_DMA{ C}inst_DS_000_DMA{ C} CYCLE_DMA_0_{ D} - : CYCLE_DMA_1_{ D} inst_VPA_D{ C} inst_DTACK_D0{ H} - : inst_RESET_OUT{ G} IPL_D0_0_{ A} IPL_D0_1_{ B} - : IPL_D0_2_{ G}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ G} SM_AMIGA_1_{ A} - :inst_UDS_000_INT{ F}inst_DS_000_ENABLE{ B}inst_LDS_000_INT{ C} - : SM_AMIGA_6_{ F} SM_AMIGA_4_{ A} SM_AMIGA_0_{ A} - : RST_DLY_0_{ G} RST_DLY_1_{ B} RST_DLY_2_{ G} - : inst_CLK_030_H{ C}inst_DSACK1_INT{ F}inst_AS_000_INT{ C} - : SM_AMIGA_5_{ B} SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} - : SM_AMIGA_i_7_{ F} + VPA{. }: inst_VPA_D{ A} A_DECODE_16_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ F} + RST{. }: SIZE_1_{ H} IPL_030_2_{ B} RW_000{ H} + : BG_000{ D} SIZE_0_{ G} BGACK_030{ H} + : VMA{ D} RW{ G} A_0_{ G} + : IPL_030_1_{ B} IPL_030_0_{ B}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ C} + :inst_AMIGA_BUS_ENABLE_DMA_LOW{ F} inst_AS_030_D0{ E}inst_AS_030_000_SYNC{ F} + :inst_BGACK_030_INT_D{ E}inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} + : CYCLE_DMA_0_{ A} CYCLE_DMA_1_{ A} inst_VPA_D{ A} + : inst_DTACK_D0{ B} inst_RESET_OUT{ G} IPL_D0_0_{ G} + : IPL_D0_1_{ D} IPL_D0_2_{ B}inst_LDS_000_INT{ F} + :inst_DS_000_ENABLE{ B}inst_UDS_000_INT{ F} SM_AMIGA_6_{ C} + : SM_AMIGA_4_{ D} SM_AMIGA_1_{ F} SM_AMIGA_0_{ H} + : RST_DLY_0_{ G} RST_DLY_1_{ G} RST_DLY_2_{ G} + : inst_CLK_030_H{ A}inst_DSACK1_INT{ H}inst_AS_000_INT{ C} + : SM_AMIGA_5_{ C} SM_AMIGA_3_{ D} SM_AMIGA_2_{ A} + : SM_AMIGA_i_7_{ C} IPL_1_{ G}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} - : IPL_D0_1_{ B} + : IPL_D0_1_{ D} IPL_0_{ H}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} - : IPL_D0_0_{ A} + : IPL_D0_0_{ G} FC_0_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ F} - A_1_{ G}:inst_AMIGA_BUS_ENABLE_DMA_LOW{ G}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ G} - SIZE_1_{ I}:inst_LDS_000_INT{ C} + A_1_{ G}:inst_AMIGA_BUS_ENABLE_DMA_HIGH{ C}inst_AMIGA_BUS_ENABLE_DMA_LOW{ F} + SIZE_1_{ I}:inst_LDS_000_INT{ F} RN_SIZE_1_{ I}: SIZE_1_{ H} RN_IPL_030_2_{ C}: IPL_030_2_{ B} - RW_000{ I}:AMIGA_BUS_DATA_DIR{ E} RW{ G}inst_DS_000_DMA{ C} + RW_000{ I}:AMIGA_BUS_DATA_DIR{ E} RW{ G}inst_DS_000_DMA{ A} RN_RW_000{ I}: RW_000{ H} RN_BG_000{ E}: BG_000{ D} + SIZE_0_{ H}:inst_LDS_000_INT{ F} + RN_SIZE_0_{ H}: SIZE_0_{ G} RN_BGACK_030{ I}: AHIGH_31_{ B} AS_030{ H} AS_000{ E} : DS_030{ A} UDS_000{ D} LDS_000{ D} : AHIGH_30_{ B} AHIGH_29_{ B} AHIGH_28_{ C} : AHIGH_27_{ C} AHIGH_26_{ C} AHIGH_25_{ C} : AHIGH_24_{ C}AMIGA_BUS_DATA_DIR{ E}AMIGA_BUS_ENABLE_LOW{ C} :AMIGA_BUS_ENABLE_HIGH{ D} SIZE_1_{ H} RW_000{ H} - : BGACK_030{ H} SIZE_0_{ G} RW{ G} - : A_0_{ G}inst_AMIGA_BUS_ENABLE_DMA_LOW{ G}inst_AS_030_000_SYNC{ F} - :inst_BGACK_030_INT_D{ A}inst_AS_000_DMA{ C}inst_DS_000_DMA{ C} - : CYCLE_DMA_0_{ D} CYCLE_DMA_1_{ D}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ G} - : inst_CLK_030_H{ C} - SIZE_0_{ H}:inst_LDS_000_INT{ C} - RN_SIZE_0_{ H}: SIZE_0_{ G} - RN_VMA{ E}: VMA{ D} SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} + : SIZE_0_{ G} BGACK_030{ H} RW{ G} + : A_0_{ G}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ C}inst_AMIGA_BUS_ENABLE_DMA_LOW{ F} + :inst_AS_030_000_SYNC{ F}inst_BGACK_030_INT_D{ E}inst_AS_000_DMA{ A} + :inst_DS_000_DMA{ A} CYCLE_DMA_0_{ A} CYCLE_DMA_1_{ A} + : inst_CLK_030_H{ A} + RN_VMA{ E}: VMA{ D} SM_AMIGA_3_{ D} SM_AMIGA_2_{ A} RW{ H}: RW_000{ H}inst_DS_000_ENABLE{ B} RN_RW{ H}: RW{ G} - A_0_{ H}:inst_UDS_000_INT{ F}inst_LDS_000_INT{ C} + A_0_{ H}:inst_LDS_000_INT{ F}inst_UDS_000_INT{ F} RN_A_0_{ H}: A_0_{ G} RN_IPL_030_1_{ C}: IPL_030_1_{ B} RN_IPL_030_0_{ C}: IPL_030_0_{ B} - cpu_est_2_{ E}: E{ G} VMA{ D} cpu_est_2_{ D} - : cpu_est_3_{ A} SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} - cpu_est_3_{ B}: E{ G} VMA{ D} cpu_est_3_{ A} - : cpu_est_1_{ D} SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} - cpu_est_0_{ E}: VMA{ D} cpu_est_2_{ D} cpu_est_3_{ A} - : cpu_est_0_{ D} cpu_est_1_{ D} SM_AMIGA_3_{ A} + cpu_est_2_{ B}: E{ G} VMA{ D} cpu_est_2_{ A} + : cpu_est_3_{ D} SM_AMIGA_3_{ D} SM_AMIGA_2_{ A} + cpu_est_3_{ E}: E{ G} VMA{ D} cpu_est_3_{ D} + : cpu_est_1_{ A} SM_AMIGA_3_{ D} SM_AMIGA_2_{ A} + cpu_est_0_{ H}: VMA{ D} cpu_est_2_{ A} cpu_est_3_{ D} + : cpu_est_0_{ G} cpu_est_1_{ A} SM_AMIGA_3_{ D} : SM_AMIGA_2_{ A} - cpu_est_1_{ E}: E{ G} VMA{ D} cpu_est_2_{ D} - : cpu_est_3_{ A} cpu_est_1_{ D} SM_AMIGA_3_{ A} + cpu_est_1_{ B}: E{ G} VMA{ D} cpu_est_2_{ A} + : cpu_est_3_{ D} cpu_est_1_{ A} SM_AMIGA_3_{ D} : SM_AMIGA_2_{ A} -inst_AMIGA_BUS_ENABLE_DMA_LOW{ H}:AMIGA_BUS_ENABLE_LOW{ C}inst_AMIGA_BUS_ENABLE_DMA_LOW{ G} -inst_AS_030_D0{ I}: CIIN{ E} BG_000{ D}inst_AS_030_000_SYNC{ F} +inst_AMIGA_BUS_ENABLE_DMA_HIGH{ D}:AMIGA_BUS_ENABLE_HIGH{ D}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ C} +inst_AMIGA_BUS_ENABLE_DMA_LOW{ G}:AMIGA_BUS_ENABLE_LOW{ C}inst_AMIGA_BUS_ENABLE_DMA_LOW{ F} +inst_AS_030_D0{ F}: CIIN{ E} BG_000{ D}inst_AS_030_000_SYNC{ F} : CIIN_0{ E} -inst_AS_030_000_SYNC{ G}:AMIGA_BUS_ENABLE_HIGH{ D}inst_AS_030_000_SYNC{ F} SM_AMIGA_6_{ F} - : SM_AMIGA_i_7_{ F} -inst_BGACK_030_INT_D{ B}: SIZE_1_{ H} SIZE_0_{ G} RW{ G} - : A_0_{ G}inst_AMIGA_BUS_ENABLE_DMA_LOW{ G}inst_AS_030_000_SYNC{ F} - :inst_AMIGA_BUS_ENABLE_DMA_HIGH{ G} -inst_AS_000_DMA{ D}: AS_030{ H}inst_AS_000_DMA{ C}inst_DS_000_DMA{ C} - : inst_CLK_030_H{ C} -inst_DS_000_DMA{ D}: DS_030{ A}inst_DS_000_DMA{ C} -CYCLE_DMA_0_{ E}:inst_AS_000_DMA{ C}inst_DS_000_DMA{ C} CYCLE_DMA_0_{ D} - : CYCLE_DMA_1_{ D} inst_CLK_030_H{ C} -CYCLE_DMA_1_{ E}:inst_AS_000_DMA{ C}inst_DS_000_DMA{ C} CYCLE_DMA_1_{ D} - : inst_CLK_030_H{ C} - inst_VPA_D{ D}: VMA{ D} SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} -CLK_000_D_2_{ I}: CLK_000_D_3_{ A} SM_AMIGA_1_{ A} SM_AMIGA_0_{ A} - :inst_DSACK1_INT{ F} -CLK_000_D_4_{ B}: CLK_000_D_5_{ G} SM_AMIGA_6_{ F} SM_AMIGA_i_7_{ F} -inst_DTACK_D0{ I}: SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} +inst_AS_030_000_SYNC{ G}:AMIGA_BUS_ENABLE_HIGH{ D}inst_AS_030_000_SYNC{ F} SM_AMIGA_6_{ C} + : SM_AMIGA_i_7_{ C} +inst_BGACK_030_INT_D{ F}: SIZE_1_{ H} SIZE_0_{ G} RW{ G} + : A_0_{ G}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ C}inst_AMIGA_BUS_ENABLE_DMA_LOW{ F} + :inst_AS_030_000_SYNC{ F} +inst_AS_000_DMA{ B}: AS_030{ H}inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} + : inst_CLK_030_H{ A} +inst_DS_000_DMA{ B}: DS_030{ A}inst_DS_000_DMA{ A} +CYCLE_DMA_0_{ B}:inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} CYCLE_DMA_0_{ A} + : CYCLE_DMA_1_{ A} inst_CLK_030_H{ A} +CYCLE_DMA_1_{ B}:inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} CYCLE_DMA_1_{ A} + : inst_CLK_030_H{ A} + inst_VPA_D{ B}: VMA{ D} SM_AMIGA_3_{ D} SM_AMIGA_2_{ A} +CLK_000_D_3_{ E}: CLK_000_D_4_{ B} SM_AMIGA_6_{ C} SM_AMIGA_i_7_{ C} +inst_DTACK_D0{ C}: SM_AMIGA_3_{ D} SM_AMIGA_2_{ A} inst_RESET_OUT{ H}: AHIGH_31_{ B} AS_030{ H} AS_000{ E} : DS_030{ A} UDS_000{ D} LDS_000{ D} : AHIGH_30_{ B} AHIGH_29_{ B} AHIGH_28_{ C} : AHIGH_27_{ C} AHIGH_26_{ C} AHIGH_25_{ C} : AHIGH_24_{ C} RESET{ B} RW_000{ H} : RW{ G} A_0_{ G} inst_RESET_OUT{ G} -CLK_000_D_1_{ I}: RW_000{ H} BGACK_030{ H} VMA{ D} - : cpu_est_2_{ D} cpu_est_3_{ A} cpu_est_0_{ D} - : cpu_est_1_{ D} CYCLE_DMA_0_{ D} CYCLE_DMA_1_{ D} - : CLK_000_D_2_{ H} inst_RESET_OUT{ G} SM_AMIGA_1_{ A} - :inst_DS_000_ENABLE{ B} SM_AMIGA_6_{ F} SM_AMIGA_4_{ A} - : SM_AMIGA_0_{ A} RST_DLY_0_{ G} RST_DLY_1_{ B} - : RST_DLY_2_{ G}inst_AS_000_INT{ C} SM_AMIGA_5_{ B} - : SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} SM_AMIGA_i_7_{ F} -CLK_000_D_0_{ E}: RW_000{ H} BG_000{ D} BGACK_030{ H} - : VMA{ D} cpu_est_2_{ D} cpu_est_3_{ A} - : cpu_est_0_{ D} cpu_est_1_{ D} CYCLE_DMA_0_{ D} - : CYCLE_DMA_1_{ D} inst_RESET_OUT{ G} CLK_000_D_1_{ H} - : SM_AMIGA_1_{ A}inst_DS_000_ENABLE{ B} SM_AMIGA_6_{ F} - : SM_AMIGA_4_{ A} SM_AMIGA_0_{ A} RST_DLY_0_{ G} - : RST_DLY_1_{ B} RST_DLY_2_{ G}inst_AS_000_INT{ C} - : SM_AMIGA_5_{ B} SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} - : SM_AMIGA_i_7_{ F} -inst_CLK_OUT_PRE_50{ F}:inst_CLK_OUT_PRE_50{ E}inst_CLK_OUT_PRE_D{ E} -inst_CLK_OUT_PRE_D{ F}: CLK_DIV_OUT{ G} CLK_EXP{ B} - IPL_D0_0_{ B}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} - IPL_D0_1_{ C}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} - IPL_D0_2_{ H}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} -CLK_000_D_3_{ B}: CLK_000_D_4_{ A} SM_AMIGA_1_{ A} SM_AMIGA_0_{ A} - :inst_DSACK1_INT{ F} -CLK_000_D_5_{ H}: SM_AMIGA_6_{ F} SM_AMIGA_i_7_{ F} -inst_AMIGA_BUS_ENABLE_DMA_HIGH{ H}:AMIGA_BUS_ENABLE_HIGH{ D}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ G} -SM_AMIGA_1_{ B}: SM_AMIGA_1_{ A} SM_AMIGA_0_{ A}inst_DSACK1_INT{ F} -inst_UDS_000_INT{ G}: UDS_000{ D}inst_UDS_000_INT{ F} +CLK_000_D_1_{ I}: IPL_030_2_{ B} RW_000{ H} BGACK_030{ H} + : VMA{ D} IPL_030_1_{ B} IPL_030_0_{ B} + : cpu_est_2_{ A} cpu_est_3_{ D} cpu_est_0_{ G} + : cpu_est_1_{ A} CYCLE_DMA_0_{ A} CYCLE_DMA_1_{ A} + : inst_RESET_OUT{ G} CLK_000_D_2_{ H}inst_DS_000_ENABLE{ B} + : SM_AMIGA_6_{ C} SM_AMIGA_4_{ D} SM_AMIGA_1_{ F} + : SM_AMIGA_0_{ H} RST_DLY_0_{ G} RST_DLY_1_{ G} + : RST_DLY_2_{ G}inst_DSACK1_INT{ H}inst_AS_000_INT{ C} + : SM_AMIGA_5_{ C} SM_AMIGA_3_{ D} SM_AMIGA_2_{ A} + : SM_AMIGA_i_7_{ C} +CLK_000_D_0_{ D}: IPL_030_2_{ B} RW_000{ H} BG_000{ D} + : BGACK_030{ H} VMA{ D} IPL_030_1_{ B} + : IPL_030_0_{ B} cpu_est_2_{ A} cpu_est_3_{ D} + : cpu_est_0_{ G} cpu_est_1_{ A} CYCLE_DMA_0_{ A} + : CYCLE_DMA_1_{ A} inst_RESET_OUT{ G} CLK_000_D_1_{ H} + :inst_DS_000_ENABLE{ B} SM_AMIGA_6_{ C} SM_AMIGA_4_{ D} + : SM_AMIGA_1_{ F} SM_AMIGA_0_{ H} RST_DLY_0_{ G} + : RST_DLY_1_{ G} RST_DLY_2_{ G}inst_DSACK1_INT{ H} + :inst_AS_000_INT{ C} SM_AMIGA_5_{ C} SM_AMIGA_3_{ D} + : SM_AMIGA_2_{ A} SM_AMIGA_i_7_{ C} +inst_CLK_OUT_PRE_50{ H}:inst_CLK_OUT_PRE_50{ G}inst_CLK_OUT_PRE_D{ D} +inst_CLK_OUT_PRE_D{ E}: CLK_DIV_OUT{ G} CLK_EXP{ B} + IPL_D0_0_{ H}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} + IPL_D0_1_{ E}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} + IPL_D0_2_{ C}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} +CLK_000_D_2_{ I}: CLK_000_D_3_{ D} +CLK_000_D_4_{ C}: SM_AMIGA_6_{ C} SM_AMIGA_i_7_{ C} +inst_LDS_000_INT{ G}: LDS_000{ D}inst_LDS_000_INT{ F} inst_DS_000_ENABLE{ C}: UDS_000{ D} LDS_000{ D}inst_DS_000_ENABLE{ B} -inst_LDS_000_INT{ D}: LDS_000{ D}inst_LDS_000_INT{ C} -SM_AMIGA_6_{ G}: RW_000{ H}inst_UDS_000_INT{ F}inst_DS_000_ENABLE{ B} - :inst_LDS_000_INT{ C} SM_AMIGA_6_{ F}inst_AS_000_INT{ C} - : SM_AMIGA_5_{ B} -SM_AMIGA_4_{ B}:inst_DS_000_ENABLE{ B} SM_AMIGA_4_{ A} SM_AMIGA_3_{ A} -SM_AMIGA_0_{ B}: RW_000{ H} SM_AMIGA_0_{ A} SM_AMIGA_i_7_{ F} - RST_DLY_0_{ H}: inst_RESET_OUT{ G} RST_DLY_0_{ G} RST_DLY_1_{ B} +inst_UDS_000_INT{ G}: UDS_000{ D}inst_UDS_000_INT{ F} +SM_AMIGA_6_{ D}: RW_000{ H}inst_LDS_000_INT{ F}inst_DS_000_ENABLE{ B} + :inst_UDS_000_INT{ F} SM_AMIGA_6_{ C}inst_AS_000_INT{ C} + : SM_AMIGA_5_{ C} +SM_AMIGA_4_{ E}:inst_DS_000_ENABLE{ B} SM_AMIGA_4_{ D} SM_AMIGA_3_{ D} +SM_AMIGA_1_{ G}: SM_AMIGA_1_{ F} SM_AMIGA_0_{ H}inst_DSACK1_INT{ H} +SM_AMIGA_0_{ I}: RW_000{ H} SM_AMIGA_0_{ H} SM_AMIGA_i_7_{ C} + RST_DLY_0_{ H}: inst_RESET_OUT{ G} RST_DLY_0_{ G} RST_DLY_1_{ G} : RST_DLY_2_{ G} - RST_DLY_1_{ C}: inst_RESET_OUT{ G} RST_DLY_0_{ G} RST_DLY_1_{ B} + RST_DLY_1_{ H}: inst_RESET_OUT{ G} RST_DLY_0_{ G} RST_DLY_1_{ G} : RST_DLY_2_{ G} - RST_DLY_2_{ H}: inst_RESET_OUT{ G} RST_DLY_0_{ G} RST_DLY_1_{ B} + RST_DLY_2_{ H}: inst_RESET_OUT{ G} RST_DLY_0_{ G} RST_DLY_1_{ G} : RST_DLY_2_{ G} -inst_CLK_030_H{ D}:inst_DS_000_DMA{ C} inst_CLK_030_H{ C} -inst_DSACK1_INT{ G}: DSACK1{ H}inst_DSACK1_INT{ F} +inst_CLK_030_H{ B}:inst_DS_000_DMA{ A} inst_CLK_030_H{ A} +inst_DSACK1_INT{ I}: DSACK1{ H}inst_DSACK1_INT{ H} inst_AS_000_INT{ D}: AS_000{ E}inst_AS_000_INT{ C} -SM_AMIGA_5_{ C}: SM_AMIGA_4_{ A} SM_AMIGA_5_{ B} -SM_AMIGA_3_{ B}: SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} -SM_AMIGA_2_{ B}: SM_AMIGA_1_{ A} SM_AMIGA_2_{ A} -SM_AMIGA_i_7_{ G}: RW_000{ H}inst_AS_030_000_SYNC{ F} SM_AMIGA_6_{ F} - : SM_AMIGA_i_7_{ F} +SM_AMIGA_5_{ D}: SM_AMIGA_4_{ D} SM_AMIGA_5_{ C} +SM_AMIGA_3_{ E}: SM_AMIGA_3_{ D} SM_AMIGA_2_{ A} +SM_AMIGA_2_{ B}: SM_AMIGA_1_{ F} SM_AMIGA_2_{ A} +SM_AMIGA_i_7_{ D}: RW_000{ H}inst_AS_030_000_SYNC{ F} SM_AMIGA_6_{ C} + : SM_AMIGA_i_7_{ C} CIIN_0{ F}: CIIN{ E} ----------------------------------------------------------------------------- @@ -657,16 +657,15 @@ Equations : +-----+-----+-----+-----+------------------------ | | | | | DS_030 | | | | | AVEC -| * | S | BS | BR | SM_AMIGA_0_ -| * | S | BS | BR | cpu_est_3_ -| * | S | BS | BR | inst_BGACK_030_INT_D -| * | S | BS | BR | SM_AMIGA_1_ -| * | S | BS | BR | SM_AMIGA_4_ -| * | S | BS | BR | CLK_000_D_3_ -| * | S | BS | BR | CLK_000_D_4_ +| * | S | BS | BR | cpu_est_1_ +| * | S | BS | BR | cpu_est_2_ +| * | S | BS | BR | inst_AS_000_DMA | * | S | BS | BR | SM_AMIGA_2_ -| * | S | BS | BR | SM_AMIGA_3_ -| * | S | BS | BR | IPL_D0_0_ +| * | S | BS | BR | inst_VPA_D +| * | S | BS | BR | inst_DS_000_DMA +| * | S | BS | BR | inst_CLK_030_H +| * | S | BS | BR | CYCLE_DMA_1_ +| * | S | BS | BR | CYCLE_DMA_0_ | | | | | A_DECODE_19_ | | | | | A_DECODE_16_ | | | | | A_DECODE_18_ @@ -690,13 +689,13 @@ Equations : | * | S | BS | BR | IPL_030_1_ | * | S | BS | BR | CLK_EXP | | | | | RESET -| * | S | BS | BR | SM_AMIGA_5_ | * | S | BS | BR | inst_DS_000_ENABLE -| * | S | BS | BR | RST_DLY_1_ +| * | S | BS | BR | inst_DTACK_D0 | * | S | BS | BR | RN_IPL_030_0_ | * | S | BS | BR | RN_IPL_030_1_ | * | S | BS | BR | RN_IPL_030_2_ -| * | S | BS | BR | IPL_D0_1_ +| * | S | BS | BR | CLK_000_D_4_ +| * | S | BS | BR | IPL_D0_2_ Block C @@ -712,12 +711,12 @@ Equations : | | | | | AHIGH_27_ | | | | | AHIGH_28_ | | | | | AMIGA_BUS_ENABLE_LOW -| * | S | BS | BR | inst_DS_000_DMA -| * | S | BS | BR | inst_AS_000_DMA -| * | S | BS | BR | inst_LDS_000_INT +| * | S | BS | BR | CLK_000_D_0_ +| * | S | BS | BR | SM_AMIGA_6_ +| * | S | BS | BR | SM_AMIGA_i_7_ +| * | S | BS | BR | SM_AMIGA_5_ | * | S | BS | BR | inst_AS_000_INT -| * | S | BS | BR | inst_VPA_D -| * | S | BS | BR | inst_CLK_030_H +| * | S | BS | BR | inst_AMIGA_BUS_ENABLE_DMA_HIGH | | | | | BG_030 @@ -734,14 +733,14 @@ Equations : | | | | | AMIGA_BUS_ENABLE_HIGH | * | S | BS | BR | BG_000 | | | | | AMIGA_ADDR_ENABLE -| * | S | BS | BR | CLK_000_D_0_ -| * | S | BS | BR | cpu_est_1_ -| * | S | BS | BR | cpu_est_2_ -| * | S | BS | BR | CYCLE_DMA_1_ +| * | S | BS | BR | cpu_est_3_ +| * | S | BS | BR | SM_AMIGA_3_ | * | S | BS | BR | RN_VMA -| * | S | BS | BR | CYCLE_DMA_0_ -| * | S | BS | BR | cpu_est_0_ +| * | S | BS | BR | SM_AMIGA_4_ +| * | S | BS | BR | inst_CLK_OUT_PRE_D +| * | S | BS | BR | CLK_000_D_3_ | * | S | BS | BR | RN_BG_000 +| * | S | BS | BR | IPL_D0_1_ | | | | | BGACK_000 | | | | | DTACK @@ -757,9 +756,9 @@ Equations : | | | | | BERR | | | | | AMIGA_BUS_DATA_DIR | | | | | CIIN -| * | S | BS | BR | inst_CLK_OUT_PRE_D +| * | S | BS | BR | inst_BGACK_030_INT_D +| * | S | BS | BR | inst_AS_030_D0 | | | | | CIIN_0 -| * | S | BS | BR | inst_CLK_OUT_PRE_50 Block F @@ -769,11 +768,11 @@ Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ -| * | S | BS | BR | SM_AMIGA_6_ | * | S | BS | BR | inst_AS_030_000_SYNC -| * | S | BS | BR | SM_AMIGA_i_7_ -| * | S | BS | BR | inst_DSACK1_INT +| * | S | BS | BR | SM_AMIGA_1_ +| * | S | BS | BR | inst_LDS_000_INT | * | S | BS | BR | inst_UDS_000_INT +| * | S | BS | BR | inst_AMIGA_BUS_ENABLE_DMA_LOW | | | | | A_DECODE_17_ | | | | | FC_1_ | | | | | FC_0_ @@ -788,23 +787,23 @@ Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ -| * | S | BS | BR | A_0_ | * | S | BS | BR | RW | * | S | BS | BR | SIZE_0_ +| * | S | BS | BR | A_0_ | | | | | E | * | S | BS | BR | CLK_DIV_OUT | * | S | BS | BR | inst_RESET_OUT +| * | S | BS | BR | cpu_est_0_ +| * | S | BS | BR | inst_CLK_OUT_PRE_50 | * | S | BS | BR | RST_DLY_0_ -| * | S | BS | BR | RST_DLY_2_ -| * | S | BS | BR | inst_AMIGA_BUS_ENABLE_DMA_HIGH -| * | S | BS | BR | inst_AMIGA_BUS_ENABLE_DMA_LOW | * | S | BS | BR | RN_A_0_ | * | S | BS | BR | RN_SIZE_0_ | * | S | BS | BR | RN_RW -| * | S | BS | BR | CLK_000_D_5_ -| * | S | BS | BR | IPL_D0_2_ -| | | | | IPL_2_ +| * | S | BS | BR | RST_DLY_2_ +| * | S | BS | BR | RST_DLY_1_ +| * | S | BS | BR | IPL_D0_0_ | | | | | IPL_0_ +| | | | | IPL_2_ Block H @@ -822,11 +821,11 @@ Equations : | | | | | FPU_CS | * | S | BS | BR | RN_BGACK_030 | * | S | BS | BR | CLK_000_D_1_ -| * | S | BS | BR | inst_AS_030_D0 -| * | S | BS | BR | CLK_000_D_2_ +| * | S | BS | BR | SM_AMIGA_0_ | * | S | BS | BR | RN_RW_000 | * | S | BS | BR | RN_SIZE_1_ -| * | S | BS | BR | inst_DTACK_D0 +| * | S | BS | BR | inst_DSACK1_INT +| * | S | BS | BR | CLK_000_D_2_ | | | | | A_DECODE_23_ | | | | | A_DECODE_22_ @@ -845,23 +844,23 @@ BLOCK_A_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx A0 IPL_0_ pin 67 mx A17 cpu_est_0_ mcell D14 -mx A1 BERR pin 41 mx A18 RN_VMA mcell D0 -mx A2 SM_AMIGA_1_ mcell A5 mx A19 SM_AMIGA_4_ mcell A9 -mx A3 inst_DS_000_DMA mcell C9 mx A20 RN_BGACK_030 mcell H4 -mx A4 CLK_000_D_2_ mcell H2 mx A21 RST pin 86 -mx A5 nEXP_SPACE pin 14 mx A22 inst_RESET_OUT mcell G5 -mx A6 ... ... mx A23 ... ... -mx A7 inst_DTACK_D0 mcell H6 mx A24 ... ... -mx A8 inst_VPA_D mcell C10 mx A25 CLK_000_D_3_ mcell A13 -mx A9 cpu_est_3_ mcell A12 mx A26 AS_000 pin 42 -mx A10 SM_AMIGA_2_ mcell A6 mx A27 ... ... -mx A11 ... ... mx A28 SM_AMIGA_5_ mcell B13 -mx A12 CLK_000_D_0_ mcell D9 mx A29 cpu_est_1_ mcell D13 -mx A13 CLK_000_D_1_ mcell H5 mx A30 SM_AMIGA_0_ mcell A8 -mx A14 SM_AMIGA_3_ mcell A10 mx A31 ... ... -mx A15 ... ... mx A32 ... ... -mx A16 cpu_est_2_ mcell D2 +mx A0 RST pin 86 mx A17 BERR pin 41 +mx A1 RN_VMA mcell D0 mx A18 SM_AMIGA_2_ mcell A5 +mx A2 inst_VPA_D mcell A9 mx A19 ... ... +mx A3 cpu_est_1_ mcell A8 mx A20 RN_BGACK_030 mcell H4 +mx A4 CLK_030 pin 64 mx A21 SM_AMIGA_3_ mcell D13 +mx A5 nEXP_SPACE pin 14 mx A22 inst_CLK_030_H mcell A2 +mx A6 RW_000 pin 80 mx A23 CLK_000_D_0_ mcell C9 +mx A7 cpu_est_3_ mcell D9 mx A24 cpu_est_2_ mcell A12 +mx A8 UDS_000 pin 32 mx A25 inst_DS_000_DMA mcell A13 +mx A9 inst_AS_000_DMA mcell A1 mx A26 ... ... +mx A10 VPA pin 36 mx A27 LDS_000 pin 31 +mx A11 inst_DTACK_D0 mcell B6 mx A28 ... ... +mx A12 cpu_est_0_ mcell G9 mx A29 ... ... +mx A13 CLK_000_D_1_ mcell H5 mx A30 ... ... +mx A14 CYCLE_DMA_0_ mcell A10 mx A31 ... ... +mx A15 CYCLE_DMA_1_ mcell A6 mx A32 inst_RESET_OUT mcell G5 +mx A16 AS_000 pin 42 ---------------------------------------------------------------------------- @@ -869,23 +868,23 @@ BLOCK_B_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx B0 IPL_0_ pin 67 mx B17 ... ... +mx B0 RN_BGACK_030 mcell H4 mx B17 IPL_D0_1_ mcell D14 mx B1 ... ... mx B18 ... ... -mx B2 RST_DLY_1_ mcell B10 mx B19 SM_AMIGA_4_ mcell A9 -mx B3 IPL_D0_0_ mcell A14 mx B20 IPL_D0_1_ mcell B14 -mx B4 IPL_2_ pin 68 mx B21 RST pin 86 -mx B5 nEXP_SPACE pin 14 mx B22 inst_RESET_OUT mcell G5 -mx B6 RN_IPL_030_1_ mcell B9 mx B23 RN_BGACK_030 mcell H4 -mx B7 CLK_000_D_0_ mcell D9 mx B24 ... ... -mx B8 RW pin 71 mx B25 SM_AMIGA_6_ mcell F0 -mx B9 RST_DLY_2_ mcell G13 mx B26 IPL_D0_2_ mcell G14 -mx B10 SM_AMIGA_5_ mcell B13 mx B27 RN_IPL_030_2_ mcell B4 -mx B11inst_DS_000_ENABLE mcell B6 mx B28 RN_IPL_030_0_ mcell B5 -mx B12 RST_DLY_0_ mcell G9 mx B29 ... ... -mx B13 CLK_000_D_1_ mcell H5 mx B30 ... ... -mx B14 ... ... mx B31 IPL_1_ pin 56 -mx B15 ... ... mx B32 AS_030 pin 82 -mx B16inst_CLK_OUT_PRE_D mcell E8 +mx B2 CLK_000_D_3_ mcell D10 mx B19 AS_030 pin 82 +mx B3 inst_RESET_OUT mcell G5 mx B20 IPL_D0_2_ mcell B14 +mx B4inst_CLK_OUT_PRE_D mcell D6 mx B21 IPL_1_ pin 56 +mx B5 nEXP_SPACE pin 14 mx B22 IPL_2_ pin 68 +mx B6 RN_IPL_030_1_ mcell B9 mx B23 CLK_000_D_0_ mcell C9 +mx B7 ... ... mx B24 RST pin 86 +mx B8 RW pin 71 mx B25 ... ... +mx B9 DTACK pin 30 mx B26 ... ... +mx B10inst_DS_000_ENABLE mcell B13 mx B27 RN_IPL_030_2_ mcell B4 +mx B11 IPL_D0_0_ mcell G14 mx B28 SM_AMIGA_4_ mcell D2 +mx B12 ... ... mx B29 ... ... +mx B13 CLK_000_D_1_ mcell H5 mx B30 SM_AMIGA_6_ mcell C13 +mx B14 ... ... mx B31 RN_IPL_030_0_ mcell B5 +mx B15 ... ... mx B32 ... ... +mx B16 IPL_0_ pin 67 ---------------------------------------------------------------------------- @@ -894,22 +893,22 @@ BLOCK_C_LOGIC_ARRAY_FANIN CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ mx C0 RST pin 86 mx C17 ... ... -mx C1 ... ... mx C18 ... ... -mx C2 CYCLE_DMA_0_ mcell D10 mx C19 AS_030 pin 82 -mx C3 inst_DS_000_DMA mcell C9 mx C20 RN_BGACK_030 mcell H4 -mx C4 CLK_030 pin 64 mx C21 RW_000 pin 80 -mx C5 nEXP_SPACE pin 14 mx C22inst_LDS_000_INT mcell C2 -mx C6 SIZE_1_ pin 79 mx C23inst_AMIGA_BUS_ENABLE_DMA_LOW mcell G6 -mx C7 inst_CLK_030_H mcell C14 mx C24 LDS_000 pin 31 -mx C8 UDS_000 pin 32 mx C25 SM_AMIGA_6_ mcell F0 -mx C9 inst_AS_000_INT mcell C6 mx C26 AS_000 pin 42 -mx C10 VPA pin 36 mx C27 ... ... -mx C11 inst_AS_000_DMA mcell C13 mx C28 ... ... -mx C12 CLK_000_D_0_ mcell D9 mx C29 ... ... -mx C13 CLK_000_D_1_ mcell H5 mx C30 ... ... -mx C14 SIZE_0_ pin 70 mx C31 ... ... -mx C15 A_0_ pin 69 mx C32 inst_RESET_OUT mcell G5 -mx C16 CYCLE_DMA_1_ mcell D6 +mx C1 ... ... mx C18 SM_AMIGA_5_ mcell C6 +mx C2 CLK_000_D_4_ mcell B10 mx C19 SM_AMIGA_0_ mcell H13 +mx C3 CLK_000 pin 11 mx C20 CLK_000_D_3_ mcell D10 +mx C4 CLK_000_D_1_ mcell H5 mx C21 ... ... +mx C5 nEXP_SPACE pin 14 mx C22 SM_AMIGA_i_7_ mcell C2 +mx C6 ... ... mx C23 RN_BGACK_030 mcell H4 +mx C7inst_AMIGA_BUS_ENABLE_DMA_HIGH mcell C14 mx C24 ... ... +mx C8 inst_AS_000_INT mcell C10 mx C25inst_AS_030_000_SYNC mcell F0 +mx C9 AS_030 pin 82 mx C26 ... ... +mx C10inst_AMIGA_BUS_ENABLE_DMA_LOW mcell F1 mx C27 ... ... +mx C11 A_1_ pin 60 mx C28 ... ... +mx C12 ... ... mx C29 ... ... +mx C13 CLK_000_D_0_ mcell C9 mx C30 SM_AMIGA_6_ mcell C13 +mx C14 ... ... mx C31 ... ... +mx C15 ... ... mx C32 inst_RESET_OUT mcell G5 +mx C16inst_BGACK_030_INT_D mcell E8 ---------------------------------------------------------------------------- @@ -917,23 +916,23 @@ BLOCK_D_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx D0 RN_BGACK_030 mcell H4 mx D17 cpu_est_0_ mcell D14 -mx D1 cpu_est_1_ mcell D13 mx D18 RN_VMA mcell D0 -mx D2 RN_BG_000 mcell D1 mx D19 ... ... -mx D3 CLK_000 pin 11 mx D20 CYCLE_DMA_0_ mcell D10 +mx D0 RN_BGACK_030 mcell H4 mx D17inst_UDS_000_INT mcell F12 +mx D1 SM_AMIGA_3_ mcell D13 mx D18inst_AMIGA_BUS_ENABLE_DMA_HIGH mcell C14 +mx D2 RN_BG_000 mcell D1 mx D19 inst_VPA_D mcell A9 +mx D3 cpu_est_1_ mcell A8 mx D20inst_LDS_000_INT mcell F8 mx D4 BG_030 pin 21 mx D21 RST pin 86 -mx D5 nEXP_SPACE pin 14 mx D22inst_LDS_000_INT mcell C2 -mx D6 ... ... mx D23inst_AMIGA_BUS_ENABLE_DMA_HIGH mcell G2 -mx D7 inst_AS_030_D0 mcell H13 mx D24 ... ... -mx D8 inst_VPA_D mcell C10 mx D25 ... ... -mx D9 cpu_est_3_ mcell A12 mx D26 AS_000 pin 42 -mx D10inst_UDS_000_INT mcell F1 mx D27 ... ... -mx D11inst_DS_000_ENABLE mcell B6 mx D28 cpu_est_2_ mcell D2 -mx D12 CLK_000_D_0_ mcell D9 mx D29 ... ... -mx D13 CLK_000_D_1_ mcell H5 mx D30 ... ... -mx D14inst_AS_030_000_SYNC mcell F4 mx D31 ... ... -mx D15 ... ... mx D32 inst_RESET_OUT mcell G5 -mx D16 CYCLE_DMA_1_ mcell D6 +mx D5inst_AS_030_000_SYNC mcell F0 mx D22 inst_RESET_OUT mcell G5 +mx D6 ... ... mx D23 CLK_000_D_0_ mcell C9 +mx D7 cpu_est_3_ mcell D9 mx D24 ... ... +mx D8 ... ... mx D25 BERR pin 41 +mx D9 cpu_est_2_ mcell A12 mx D26 RN_VMA mcell D0 +mx D10 cpu_est_0_ mcell G9 mx D27 SM_AMIGA_5_ mcell C6 +mx D11 inst_DTACK_D0 mcell B6 mx D28inst_DS_000_ENABLE mcell B13 +mx D12inst_CLK_OUT_PRE_50 mcell G13 mx D29 ... ... +mx D13 CLK_000_D_1_ mcell H5 mx D30 CLK_000_D_2_ mcell H6 +mx D14 inst_AS_030_D0 mcell E5 mx D31 IPL_1_ pin 56 +mx D15 nEXP_SPACE pin 14 mx D32 AS_030 pin 82 +mx D16 SM_AMIGA_4_ mcell D2 ---------------------------------------------------------------------------- @@ -941,22 +940,22 @@ BLOCK_E_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx E0 RN_BGACK_030 mcell H4 mx E17 A_DECODE_18_ pin 95 -mx E1 FC_1_ pin 58 mx E18 inst_AS_000_INT mcell C6 -mx E2inst_CLK_OUT_PRE_50 mcell E9 mx E19 AS_030 pin 82 -mx E3 AHIGH_25_ pin 18 mx E20 A_DECODE_22_ pin 84 -mx E4 BGACK_000 pin 28 mx E21 AHIGH_29_ pin 6 +mx E0 RST pin 86 mx E17 AHIGH_26_ pin 17 +mx E1 FC_1_ pin 58 mx E18 BGACK_000 pin 28 +mx E2 CIIN_0 mcell E9 mx E19 AS_030 pin 82 +mx E3 AHIGH_27_ pin 16 mx E20 A_DECODE_22_ pin 84 +mx E4 A_DECODE_18_ pin 95 mx E21 nEXP_SPACE pin 14 mx E5 AHIGH_24_ pin 19 mx E22 inst_RESET_OUT mcell G5 -mx E6 RW_000 pin 80 mx E23 ... ... -mx E7 inst_AS_030_D0 mcell H13 mx E24 FC_0_ pin 57 -mx E8 FPU_SENSE pin 91 mx E25 AHIGH_31_ pin 4 -mx E9 AHIGH_26_ pin 17 mx E26 A_DECODE_16_ pin 96 -mx E10 ... ... mx E27 AHIGH_28_ pin 15 -mx E11 AHIGH_27_ pin 16 mx E28 AHIGH_30_ pin 5 -mx E12 A_DECODE_19_ pin 97 mx E29 A_DECODE_20_ pin 93 -mx E13 A_DECODE_17_ pin 59 mx E30 ... ... -mx E14 CIIN_0 mcell E5 mx E31 A_DECODE_21_ pin 94 -mx E15 nEXP_SPACE pin 14 mx E32 A_DECODE_23_ pin 85 +mx E6 A_DECODE_19_ pin 97 mx E23 RN_BGACK_030 mcell H4 +mx E7 AHIGH_28_ pin 15 mx E24 FC_0_ pin 57 +mx E8 inst_AS_000_INT mcell C10 mx E25 AHIGH_31_ pin 4 +mx E9 AHIGH_30_ pin 5 mx E26 A_DECODE_16_ pin 96 +mx E10 ... ... mx E27 A_DECODE_17_ pin 59 +mx E11 FPU_SENSE pin 91 mx E28 RW_000 pin 80 +mx E12 AHIGH_25_ pin 18 mx E29 A_DECODE_20_ pin 93 +mx E13 AHIGH_29_ pin 6 mx E30 ... ... +mx E14 inst_AS_030_D0 mcell E5 mx E31 ... ... +mx E15 A_DECODE_21_ pin 94 mx E32 A_DECODE_23_ pin 85 mx E16 AS_000 pin 42 ---------------------------------------------------------------------------- @@ -965,23 +964,23 @@ BLOCK_F_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx F0 RN_BGACK_030 mcell H4 mx F17 FC_0_ pin 57 -mx F1 inst_DSACK1_INT mcell F12 mx F18 SM_AMIGA_1_ mcell A5 -mx F2 SM_AMIGA_i_7_ mcell F8 mx F19 inst_AS_030_D0 mcell H13 -mx F3 SM_AMIGA_0_ mcell A8 mx F20 FC_1_ pin 58 +mx F0 SIZE_0_ pin 70 mx F17inst_UDS_000_INT mcell F12 +mx F1 FC_1_ pin 58 mx F18 SM_AMIGA_2_ mcell A5 +mx F2inst_LDS_000_INT mcell F8 mx F19 ... ... +mx F3 A_1_ pin 60 mx F20 RN_BGACK_030 mcell H4 mx F4 A_DECODE_18_ pin 95 mx F21 RST pin 86 -mx F5 nEXP_SPACE pin 14 mx F22 CLK_000_D_5_ mcell G10 -mx F6 A_DECODE_19_ pin 97 mx F23 ... ... -mx F7 CLK_000_D_0_ mcell D9 mx F24 ... ... -mx F8 A_DECODE_17_ pin 59 mx F25 CLK_000_D_4_ mcell A2 -mx F9 AS_030 pin 82 mx F26 ... ... -mx F10inst_UDS_000_INT mcell F1 mx F27 ... ... -mx F11 A_DECODE_16_ pin 96 mx F28 CLK_000_D_3_ mcell A13 -mx F12inst_BGACK_030_INT_D mcell A1 mx F29inst_AS_030_000_SYNC mcell F4 -mx F13 CLK_000_D_1_ mcell H5 mx F30 ... ... -mx F14 CLK_000_D_2_ mcell H2 mx F31 SM_AMIGA_6_ mcell F0 +mx F5 nEXP_SPACE pin 14 mx F22 SM_AMIGA_i_7_ mcell C2 +mx F6 FC_0_ pin 57 mx F23 CLK_000_D_0_ mcell C9 +mx F7 ... ... mx F24 ... ... +mx F8 A_DECODE_17_ pin 59 mx F25inst_AS_030_000_SYNC mcell F0 +mx F9 AS_030 pin 82 mx F26 inst_AS_030_D0 mcell E5 +mx F10inst_AMIGA_BUS_ENABLE_DMA_LOW mcell F1 mx F27 SIZE_1_ pin 79 +mx F11 A_DECODE_16_ pin 96 mx F28 ... ... +mx F12 A_DECODE_19_ pin 97 mx F29 ... ... +mx F13 CLK_000_D_1_ mcell H5 mx F30 SM_AMIGA_6_ mcell C13 +mx F14 SM_AMIGA_1_ mcell F4 mx F31 ... ... mx F15 A_0_ pin 69 mx F32 ... ... -mx F16 ... ... +mx F16inst_BGACK_030_INT_D mcell E8 ---------------------------------------------------------------------------- @@ -989,23 +988,23 @@ BLOCK_G_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx G0 RST pin 86 mx G17 RN_RW mcell G0 -mx G1 cpu_est_1_ mcell D13 mx G18 ... ... -mx G2 RST_DLY_1_ mcell B10 mx G19 ... ... -mx G3 cpu_est_2_ mcell D2 mx G20 RN_BGACK_030 mcell H4 -mx G4 IPL_2_ pin 68 mx G21inst_BGACK_030_INT_D mcell A1 -mx G5 nEXP_SPACE pin 14 mx G22 CLK_000_D_4_ mcell A2 -mx G6 RW_000 pin 80 mx G23inst_AMIGA_BUS_ENABLE_DMA_LOW mcell G6 +mx G0 IPL_0_ pin 67 mx G17 RN_RW mcell G0 +mx G1 ... ... mx G18 cpu_est_1_ mcell A8 +mx G2 ... ... mx G19 ... ... +mx G3 CLK_000_D_0_ mcell C9 mx G20 RN_BGACK_030 mcell H4 +mx G4inst_CLK_OUT_PRE_D mcell D6 mx G21 RST pin 86 +mx G5 RST_DLY_2_ mcell G6 mx G22 RST_DLY_1_ mcell G10 +mx G6 RW_000 pin 80 mx G23 RST_DLY_0_ mcell G2 mx G7 RN_SIZE_0_ mcell G12 mx G24 LDS_000 pin 31 -mx G8 UDS_000 pin 32 mx G25 CLK_000_D_0_ mcell D9 -mx G9 RST_DLY_2_ mcell G13 mx G26 ... ... -mx G10 RN_A_0_ mcell G8 mx G27 ... ... -mx G11 A_1_ pin 60 mx G28 ... ... -mx G12 RST_DLY_0_ mcell G9 mx G29 ... ... -mx G13 CLK_000_D_1_ mcell H5 mx G30 ... ... -mx G14 ... ... mx G31inst_AMIGA_BUS_ENABLE_DMA_HIGH mcell G2 -mx G15 cpu_est_3_ mcell A12 mx G32 inst_RESET_OUT mcell G5 -mx G16inst_CLK_OUT_PRE_D mcell E8 +mx G8 UDS_000 pin 32 mx G25 cpu_est_3_ mcell D9 +mx G9 cpu_est_2_ mcell A12 mx G26 ... ... +mx G10 cpu_est_0_ mcell G9 mx G27 CLK_000_D_1_ mcell H5 +mx G11 ... ... mx G28 ... ... +mx G12inst_CLK_OUT_PRE_50 mcell G13 mx G29 ... ... +mx G13 RN_A_0_ mcell G8 mx G30 ... ... +mx G14 ... ... mx G31 ... ... +mx G15 nEXP_SPACE pin 14 mx G32 inst_RESET_OUT mcell G5 +mx G16inst_BGACK_030_INT_D mcell E8 ---------------------------------------------------------------------------- @@ -1015,21 +1014,21 @@ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ mx H0 RST pin 86 mx H17 FC_0_ pin 57 mx H1 FC_1_ pin 58 mx H18 BGACK_000 pin 28 -mx H2 SM_AMIGA_i_7_ mcell F8 mx H19 FPU_SENSE pin 91 -mx H3 SM_AMIGA_0_ mcell A8 mx H20 RN_BGACK_030 mcell H4 -mx H4 A_DECODE_18_ pin 95 mx H21inst_BGACK_030_INT_D mcell A1 +mx H2 SM_AMIGA_i_7_ mcell C2 mx H19 AS_030 pin 82 +mx H3 CLK_000_D_0_ mcell C9 mx H20 RN_BGACK_030 mcell H4 +mx H4 A_DECODE_18_ pin 95 mx H21 ... ... mx H5 nEXP_SPACE pin 14 mx H22 inst_RESET_OUT mcell G5 mx H6 A_DECODE_16_ pin 96 mx H23 RN_RW_000 mcell H0 -mx H7 CLK_000_D_0_ mcell D9 mx H24 LDS_000 pin 31 -mx H8 UDS_000 pin 32 mx H25 SM_AMIGA_6_ mcell F0 -mx H9 AS_030 pin 82 mx H26 ... ... -mx H10 ... ... mx H27 CLK_000_D_1_ mcell H5 -mx H11 RW pin 71 mx H28 ... ... +mx H7 SM_AMIGA_0_ mcell H13 mx H24 LDS_000 pin 31 +mx H8 UDS_000 pin 32 mx H25 RW pin 71 +mx H9 inst_AS_000_DMA mcell A1 mx H26 AS_000 pin 42 +mx H10 SM_AMIGA_1_ mcell F4 mx H27 CLK_000_D_1_ mcell H5 +mx H11 FPU_SENSE pin 91 mx H28 ... ... mx H12 A_DECODE_19_ pin 97 mx H29 ... ... -mx H13 A_DECODE_17_ pin 59 mx H30 inst_AS_000_DMA mcell C13 -mx H14 DTACK pin 30 mx H31 inst_DSACK1_INT mcell F12 +mx H13 A_DECODE_17_ pin 59 mx H30 SM_AMIGA_6_ mcell C13 +mx H14 inst_DSACK1_INT mcell H2 mx H31 ... ... mx H15 RN_SIZE_1_ mcell H12 mx H32 ... ... -mx H16 AS_000 pin 42 +mx H16inst_BGACK_030_INT_D mcell E8 ---------------------------------------------------------------------------- CSM indicates the mux inputs from the Central Switch Matrix. @@ -1064,17 +1063,17 @@ PostFit_Equations 1 3 1 Pin AHIGH_29_.OE 0 0 1 Pin AHIGH_28_ 1 3 1 Pin AHIGH_28_.OE - 1 1 1 Pin CLK_DIV_OUT.D - 1 1 1 Pin CLK_DIV_OUT.C 0 0 1 Pin AHIGH_27_ 1 3 1 Pin AHIGH_27_.OE 0 0 1 Pin AHIGH_26_ 1 3 1 Pin AHIGH_26_.OE - 1 9 1 Pin FPU_CS- + 1 1 1 Pin CLK_DIV_OUT.D + 1 1 1 Pin CLK_DIV_OUT.C 0 0 1 Pin AHIGH_25_ 1 3 1 Pin AHIGH_25_.OE 0 0 1 Pin AHIGH_24_ 1 3 1 Pin AHIGH_24_.OE + 1 9 1 Pin FPU_CS- 1 2 1 Pin DSACK1- 1 1 1 Pin DSACK1.OE 1 0 1 Pin AVEC @@ -1084,24 +1083,24 @@ PostFit_Equations 0 0 1 Pin AMIGA_ADDR_ENABLE 2 4 1 Pin AMIGA_BUS_DATA_DIR 1 2 1 Pin AMIGA_BUS_ENABLE_LOW- - 2 3 1 Pin AMIGA_BUS_ENABLE_HIGH + 2 4 1 Pin AMIGA_BUS_ENABLE_HIGH- 1 13 1 Pin CIIN 1 1 1 Pin CIIN.OE 1 2 1 Pin SIZE_1_.OE 3 6 1 Pin SIZE_1_.D 1 1 1 Pin SIZE_1_.C - 10 8 1 Pin IPL_030_2_.D- + 9 10 1 Pin IPL_030_2_.T 1 1 1 Pin IPL_030_2_.C 1 2 1 Pin RW_000.OE 4 8 1 Pin RW_000.D- 1 1 1 Pin RW_000.C 2 6 1 Pin BG_000.D- 1 1 1 Pin BG_000.C - 3 6 1 Pin BGACK_030.D - 1 1 1 Pin BGACK_030.C 1 2 1 Pin SIZE_0_.OE 3 6 1 Pin SIZE_0_.D- 1 1 1 Pin SIZE_0_.C + 3 6 1 Pin BGACK_030.D + 1 1 1 Pin BGACK_030.C 1 1 1 Pin CLK_EXP.D 1 1 1 Pin CLK_EXP.C 3 9 1 Pin VMA.T @@ -1112,9 +1111,9 @@ PostFit_Equations 1 3 1 Pin A_0_.OE 3 5 1 Pin A_0_.D 1 1 1 Pin A_0_.C - 10 8 1 Pin IPL_030_1_.D- + 9 10 1 Pin IPL_030_1_.T 1 1 1 Pin IPL_030_1_.C - 10 8 1 Pin IPL_030_0_.D- + 9 10 1 Pin IPL_030_0_.T 1 1 1 Pin IPL_030_0_.C 1 1 1 NodeX1 cpu_est_2_.D.X1 1 4 1 NodeX2 cpu_est_2_.D.X2 @@ -1125,6 +1124,8 @@ PostFit_Equations 1 1 1 Node cpu_est_0_.C 4 5 1 Node cpu_est_1_.D 1 1 1 Node cpu_est_1_.C + 2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- + 1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.C 2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.D- 1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.C 1 2 1 Node inst_AS_030_D0.D- @@ -1143,10 +1144,8 @@ PostFit_Equations 1 1 1 Node CYCLE_DMA_1_.C 1 2 1 Node inst_VPA_D.D- 1 1 1 Node inst_VPA_D.C - 1 1 1 Node CLK_000_D_2_.D - 1 1 1 Node CLK_000_D_2_.C - 1 1 1 Node CLK_000_D_4_.D - 1 1 1 Node CLK_000_D_4_.C + 1 1 1 Node CLK_000_D_3_.D + 1 1 1 Node CLK_000_D_3_.C 1 2 1 Node inst_DTACK_D0.D- 1 1 1 Node inst_DTACK_D0.C 2 7 1 Node inst_RESET_OUT.D @@ -1165,25 +1164,23 @@ PostFit_Equations 1 1 1 Node IPL_D0_1_.C 1 2 1 Node IPL_D0_2_.D- 1 1 1 Node IPL_D0_2_.C - 1 1 1 Node CLK_000_D_3_.D - 1 1 1 Node CLK_000_D_3_.C - 1 1 1 Node CLK_000_D_5_.D - 1 1 1 Node CLK_000_D_5_.C - 2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- - 1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.C - 4 7 1 Node SM_AMIGA_1_.D - 1 1 1 Node SM_AMIGA_1_.C - 2 4 1 Node inst_UDS_000_INT.D- - 1 1 1 Node inst_UDS_000_INT.C - 3 8 1 Node inst_DS_000_ENABLE.D - 1 1 1 Node inst_DS_000_ENABLE.C + 1 1 1 Node CLK_000_D_2_.D + 1 1 1 Node CLK_000_D_2_.C + 1 1 1 Node CLK_000_D_4_.D + 1 1 1 Node CLK_000_D_4_.C 3 6 1 Node inst_LDS_000_INT.D 1 1 1 Node inst_LDS_000_INT.C + 3 8 1 Node inst_DS_000_ENABLE.D + 1 1 1 Node inst_DS_000_ENABLE.C + 2 4 1 Node inst_UDS_000_INT.D- + 1 1 1 Node inst_UDS_000_INT.C 3 9 1 Node SM_AMIGA_6_.D 1 1 1 Node SM_AMIGA_6_.C 3 5 1 Node SM_AMIGA_4_.D 1 1 1 Node SM_AMIGA_4_.C - 4 7 1 Node SM_AMIGA_0_.D + 3 5 1 Node SM_AMIGA_1_.D + 1 1 1 Node SM_AMIGA_1_.C + 3 5 1 Node SM_AMIGA_0_.D 1 1 1 Node SM_AMIGA_0_.C 4 6 1 Node RST_DLY_0_.D 1 1 1 Node RST_DLY_0_.C @@ -1209,9 +1206,9 @@ PostFit_Equations 1 1 1 Node SM_AMIGA_i_7_.C 2 14 1 Node CIIN_0 ========= - 276 P-Term Total: 276 + 269 P-Term Total: 269 Total Pins: 61 - Total Nodes: 45 + Total Nodes: 44 Average P-Term/Output: 2 @@ -1233,11 +1230,11 @@ AS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q); DS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); -!UDS_000 = (!inst_UDS_000_INT.Q & inst_DS_000_ENABLE.Q); +!UDS_000 = (inst_DS_000_ENABLE.Q & !inst_UDS_000_INT.Q); UDS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q); -!LDS_000 = (inst_DS_000_ENABLE.Q & !inst_LDS_000_INT.Q); +!LDS_000 = (!inst_LDS_000_INT.Q & inst_DS_000_ENABLE.Q); LDS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q); @@ -1257,10 +1254,6 @@ AHIGH_28_ = (0); AHIGH_28_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); -CLK_DIV_OUT.D = (inst_CLK_OUT_PRE_D.Q); - -CLK_DIV_OUT.C = (CLK_OSZI); - AHIGH_27_ = (0); AHIGH_27_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); @@ -1269,7 +1262,9 @@ AHIGH_26_ = (0); AHIGH_26_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); -!FPU_CS = (FC_1_ & BGACK_000 & !FPU_SENSE & !A_DECODE_19_ & !A_DECODE_18_ & A_DECODE_17_ & !A_DECODE_16_ & FC_0_ & !AS_030.PIN); +CLK_DIV_OUT.D = (inst_CLK_OUT_PRE_D.Q); + +CLK_DIV_OUT.C = (CLK_OSZI); AHIGH_25_ = (0); @@ -1279,6 +1274,8 @@ AHIGH_24_ = (0); AHIGH_24_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); +!FPU_CS = (FC_1_ & BGACK_000 & !FPU_SENSE & !A_DECODE_19_ & !A_DECODE_18_ & A_DECODE_17_ & !A_DECODE_16_ & FC_0_ & !AS_030.PIN); + !DSACK1 = (!inst_DSACK1_INT.Q & !AS_030.PIN); DSACK1.OE = (nEXP_SPACE); @@ -1299,8 +1296,8 @@ AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW_000.PIN !AMIGA_BUS_ENABLE_LOW = (!BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_LOW.Q); -AMIGA_BUS_ENABLE_HIGH = (BGACK_030.Q & inst_AS_030_000_SYNC.Q - # !BGACK_030.Q & inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q); +!AMIGA_BUS_ENABLE_HIGH = (!BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q + # BGACK_030.Q & !inst_AS_030_000_SYNC.Q & !AS_030.PIN); CIIN = (A_DECODE_23_ & A_DECODE_22_ & A_DECODE_21_ & A_DECODE_20_ & !inst_AS_030_D0.Q & !AHIGH_24_.PIN & !AHIGH_25_.PIN & !AHIGH_26_.PIN & !AHIGH_27_.PIN & !AHIGH_28_.PIN & !AHIGH_29_.PIN & !AHIGH_30_.PIN & !AHIGH_31_.PIN); @@ -1314,16 +1311,15 @@ SIZE_1_.D = (!RST SIZE_1_.C = (CLK_OSZI); -!IPL_030_2_.D = (!IPL_2_ & RST & !IPL_030_2_.Q - # RST & !IPL_D0_2_.Q & !IPL_030_2_.Q - # RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_2_.Q - # RST & IPL_0_ & !IPL_D0_0_.Q & !IPL_030_2_.Q - # RST & !IPL_1_ & IPL_D0_1_.Q & !IPL_030_2_.Q - # RST & IPL_1_ & !IPL_D0_1_.Q & !IPL_030_2_.Q - # !IPL_2_ & RST & IPL_1_ & IPL_0_ & IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q - # !IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q - # !IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q - # !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q); +IPL_030_2_.T = (!RST & !IPL_030_2_.Q + # IPL_2_ & IPL_1_ & IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & IPL_D0_0_.Q & IPL_D0_1_.Q & IPL_D0_2_.Q & !IPL_030_2_.Q + # IPL_2_ & IPL_1_ & !IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !IPL_D0_0_.Q & IPL_D0_1_.Q & IPL_D0_2_.Q & !IPL_030_2_.Q + # IPL_2_ & !IPL_1_ & IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q & !IPL_030_2_.Q + # IPL_2_ & !IPL_1_ & !IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q & !IPL_030_2_.Q + # !IPL_2_ & RST & IPL_1_ & IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q & IPL_030_2_.Q + # !IPL_2_ & RST & IPL_1_ & !IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q & IPL_030_2_.Q + # !IPL_2_ & RST & !IPL_1_ & IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q & IPL_030_2_.Q + # !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q & IPL_030_2_.Q); IPL_030_2_.C = (CLK_OSZI); @@ -1341,12 +1337,6 @@ RW_000.C = (CLK_OSZI); BG_000.C = (CLK_OSZI); -BGACK_030.D = (!RST - # BGACK_000 & BGACK_030.Q - # BGACK_000 & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & AS_000.PIN); - -BGACK_030.C = (CLK_OSZI); - SIZE_0_.OE = (!nEXP_SPACE & !BGACK_030.Q); !SIZE_0_.D = (RST & BGACK_030.Q & !inst_BGACK_030_INT_D.Q @@ -1355,6 +1345,12 @@ SIZE_0_.OE = (!nEXP_SPACE & !BGACK_030.Q); SIZE_0_.C = (CLK_OSZI); +BGACK_030.D = (!RST + # BGACK_000 & BGACK_030.Q + # BGACK_000 & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & AS_000.PIN); + +BGACK_030.C = (CLK_OSZI); + CLK_EXP.D = (inst_CLK_OUT_PRE_D.Q); CLK_EXP.C = (CLK_OSZI); @@ -1380,29 +1376,27 @@ A_0_.D = (!RST A_0_.C = (CLK_OSZI); -!IPL_030_1_.D = (RST & !IPL_1_ & !IPL_030_1_.Q - # RST & !IPL_D0_1_.Q & !IPL_030_1_.Q - # RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_1_.Q - # RST & IPL_0_ & !IPL_D0_0_.Q & !IPL_030_1_.Q - # !IPL_2_ & RST & IPL_D0_2_.Q & !IPL_030_1_.Q - # IPL_2_ & RST & !IPL_D0_2_.Q & !IPL_030_1_.Q - # IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q - # IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q - # !IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q - # !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q); +IPL_030_1_.T = (!RST & !IPL_030_1_.Q + # IPL_2_ & IPL_1_ & IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & IPL_D0_0_.Q & IPL_D0_1_.Q & IPL_D0_2_.Q & !IPL_030_1_.Q + # IPL_2_ & IPL_1_ & !IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !IPL_D0_0_.Q & IPL_D0_1_.Q & IPL_D0_2_.Q & !IPL_030_1_.Q + # !IPL_2_ & IPL_1_ & IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q & !IPL_030_1_.Q + # !IPL_2_ & IPL_1_ & !IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q & !IPL_030_1_.Q + # IPL_2_ & RST & !IPL_1_ & IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q & IPL_030_1_.Q + # IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q & IPL_030_1_.Q + # !IPL_2_ & RST & !IPL_1_ & IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q & IPL_030_1_.Q + # !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q & IPL_030_1_.Q); IPL_030_1_.C = (CLK_OSZI); -!IPL_030_0_.D = (RST & !IPL_0_ & !IPL_030_0_.Q - # RST & !IPL_D0_0_.Q & !IPL_030_0_.Q - # RST & !IPL_1_ & IPL_D0_1_.Q & !IPL_030_0_.Q - # RST & IPL_1_ & !IPL_D0_1_.Q & !IPL_030_0_.Q - # !IPL_2_ & RST & IPL_D0_2_.Q & !IPL_030_0_.Q - # IPL_2_ & RST & !IPL_D0_2_.Q & !IPL_030_0_.Q - # IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & IPL_D0_2_.Q - # IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q - # !IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q - # !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q); +IPL_030_0_.T = (!RST & !IPL_030_0_.Q + # IPL_2_ & IPL_1_ & IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & IPL_D0_0_.Q & IPL_D0_1_.Q & IPL_D0_2_.Q & !IPL_030_0_.Q + # IPL_2_ & !IPL_1_ & IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q & !IPL_030_0_.Q + # !IPL_2_ & IPL_1_ & IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q & !IPL_030_0_.Q + # !IPL_2_ & !IPL_1_ & IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q & !IPL_030_0_.Q + # IPL_2_ & RST & IPL_1_ & !IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !IPL_D0_0_.Q & IPL_D0_1_.Q & IPL_D0_2_.Q & IPL_030_0_.Q + # IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q & IPL_030_0_.Q + # !IPL_2_ & RST & IPL_1_ & !IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q & IPL_030_0_.Q + # !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q & IPL_030_0_.Q); IPL_030_0_.C = (CLK_OSZI); @@ -1432,6 +1426,11 @@ cpu_est_1_.D = (!cpu_est_0_.Q & cpu_est_1_.Q cpu_est_1_.C = (CLK_OSZI); +!inst_AMIGA_BUS_ENABLE_DMA_HIGH.D = (RST & !A_1_ & !BGACK_030.Q + # RST & BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q & inst_BGACK_030_INT_D.Q); + +inst_AMIGA_BUS_ENABLE_DMA_HIGH.C = (CLK_OSZI); + !inst_AMIGA_BUS_ENABLE_DMA_LOW.D = (RST & A_1_ & !BGACK_030.Q # RST & BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_LOW.Q & inst_BGACK_030_INT_D.Q); @@ -1494,13 +1493,9 @@ CYCLE_DMA_1_.C = (CLK_OSZI); inst_VPA_D.C = (CLK_OSZI); -CLK_000_D_2_.D = (CLK_000_D_1_.Q); +CLK_000_D_3_.D = (CLK_000_D_2_.Q); -CLK_000_D_2_.C = (CLK_OSZI); - -CLK_000_D_4_.D = (CLK_000_D_3_.Q); - -CLK_000_D_4_.C = (CLK_OSZI); +CLK_000_D_3_.C = (CLK_OSZI); !inst_DTACK_D0.D = (!DTACK & RST); @@ -1539,36 +1534,13 @@ IPL_D0_1_.C = (CLK_OSZI); IPL_D0_2_.C = (CLK_OSZI); -CLK_000_D_3_.D = (CLK_000_D_2_.Q); +CLK_000_D_2_.D = (CLK_000_D_1_.Q); -CLK_000_D_3_.C = (CLK_OSZI); +CLK_000_D_2_.C = (CLK_OSZI); -CLK_000_D_5_.D = (CLK_000_D_4_.Q); +CLK_000_D_4_.D = (CLK_000_D_3_.Q); -CLK_000_D_5_.C = (CLK_OSZI); - -!inst_AMIGA_BUS_ENABLE_DMA_HIGH.D = (RST & !A_1_ & !BGACK_030.Q - # RST & BGACK_030.Q & inst_BGACK_030_INT_D.Q & !inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q); - -inst_AMIGA_BUS_ENABLE_DMA_HIGH.C = (CLK_OSZI); - -SM_AMIGA_1_.D = (RST & CLK_000_D_2_.Q & SM_AMIGA_1_.Q - # RST & !CLK_000_D_3_.Q & SM_AMIGA_1_.Q - # RST & SM_AMIGA_1_.Q & SM_AMIGA_2_.Q - # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_2_.Q); - -SM_AMIGA_1_.C = (CLK_OSZI); - -!inst_UDS_000_INT.D = (RST & !inst_UDS_000_INT.Q & !SM_AMIGA_6_.Q - # RST & SM_AMIGA_6_.Q & !A_0_.PIN); - -inst_UDS_000_INT.C = (CLK_OSZI); - -inst_DS_000_ENABLE.D = (RST & inst_DS_000_ENABLE.Q & !AS_030.PIN - # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_4_.Q - # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q & RW.PIN); - -inst_DS_000_ENABLE.C = (CLK_OSZI); +CLK_000_D_4_.C = (CLK_OSZI); inst_LDS_000_INT.D = (!RST # inst_LDS_000_INT.Q & !SM_AMIGA_6_.Q @@ -1576,9 +1548,20 @@ inst_LDS_000_INT.D = (!RST inst_LDS_000_INT.C = (CLK_OSZI); +inst_DS_000_ENABLE.D = (RST & inst_DS_000_ENABLE.Q & !AS_030.PIN + # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_4_.Q + # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q & RW.PIN); + +inst_DS_000_ENABLE.C = (CLK_OSZI); + +!inst_UDS_000_INT.D = (RST & !inst_UDS_000_INT.Q & !SM_AMIGA_6_.Q + # RST & SM_AMIGA_6_.Q & !A_0_.PIN); + +inst_UDS_000_INT.C = (CLK_OSZI); + SM_AMIGA_6_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_6_.Q # RST & !CLK_000_D_0_.Q & SM_AMIGA_6_.Q - # nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_4_.Q & CLK_000_D_5_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_i_7_.Q); + # nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_3_.Q & CLK_000_D_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_i_7_.Q); SM_AMIGA_6_.C = (CLK_OSZI); @@ -1588,10 +1571,15 @@ SM_AMIGA_4_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_4_.Q SM_AMIGA_4_.C = (CLK_OSZI); +SM_AMIGA_1_.D = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_2_.Q + # RST & !CLK_000_D_1_.Q & SM_AMIGA_1_.Q & !SM_AMIGA_2_.Q + # RST & CLK_000_D_0_.Q & SM_AMIGA_1_.Q & !SM_AMIGA_2_.Q); + +SM_AMIGA_1_.C = (CLK_OSZI); + SM_AMIGA_0_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_0_.Q # RST & !CLK_000_D_0_.Q & SM_AMIGA_0_.Q - # RST & SM_AMIGA_1_.Q & SM_AMIGA_0_.Q - # RST & !CLK_000_D_2_.Q & CLK_000_D_3_.Q & SM_AMIGA_1_.Q); + # RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_1_.Q); SM_AMIGA_0_.C = (CLK_OSZI); @@ -1626,7 +1614,7 @@ inst_CLK_030_H.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & inst inst_CLK_030_H.C = (CLK_OSZI); !inst_DSACK1_INT.D = (RST & !inst_DSACK1_INT.Q & !AS_030.PIN - # RST & !CLK_000_D_2_.Q & CLK_000_D_3_.Q & SM_AMIGA_1_.Q); + # RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_1_.Q); inst_DSACK1_INT.C = (CLK_OSZI); @@ -1659,9 +1647,9 @@ SM_AMIGA_2_.C = (CLK_OSZI); SM_AMIGA_i_7_.T.X1 = (!RST & SM_AMIGA_i_7_.Q # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_0_.Q & SM_AMIGA_i_7_.Q - # nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_4_.Q & CLK_000_D_5_.Q & !SM_AMIGA_i_7_.Q); + # nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_3_.Q & CLK_000_D_4_.Q & !SM_AMIGA_i_7_.Q); -SM_AMIGA_i_7_.T.X2 = (nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_4_.Q & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & CLK_000_D_5_.Q & SM_AMIGA_0_.Q & !SM_AMIGA_i_7_.Q); +SM_AMIGA_i_7_.T.X2 = (nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_3_.Q & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & CLK_000_D_4_.Q & SM_AMIGA_0_.Q & !SM_AMIGA_i_7_.Q); SM_AMIGA_i_7_.C = (CLK_OSZI); diff --git a/Logic/68030_tk.tal b/Logic/68030_tk.tal index 0359c8e..eb85c47 100644 --- a/Logic/68030_tk.tal +++ b/Logic/68030_tk.tal @@ -38,6 +38,7 @@ SIGNAL NAME min max min max min max min max FPU_CS .. .. .. .. 1 2 .. .. DSACK1 .. .. .. .. 1 2 .. .. AMIGA_BUS_DATA_DIR .. .. .. .. 1 2 .. .. +AMIGA_BUS_ENABLE_HIGH .. .. .. .. 1 2 .. .. BGACK_030 1 2 0 1 .. .. 1 1 RN_BGACK_030 1 2 0 1 .. .. 1 1 inst_AS_030_D0 1 2 1 1 .. .. 1 1 @@ -45,9 +46,9 @@ inst_AS_030_000_SYNC 1 2 1 1 .. .. 1 1 inst_DS_000_DMA 1 2 1 1 .. .. .. .. CYCLE_DMA_0_ 1 2 .. .. .. .. 1 1 CYCLE_DMA_1_ 1 2 .. .. .. .. 1 1 -inst_UDS_000_INT 1 1 1 1 .. .. 2 2 -inst_DS_000_ENABLE 1 2 1 1 .. .. 2 2 inst_LDS_000_INT 1 1 1 1 .. .. 2 2 +inst_DS_000_ENABLE 1 2 1 1 .. .. 2 2 +inst_UDS_000_INT 1 1 1 1 .. .. 2 2 inst_CLK_030_H 1 2 .. .. .. .. 1 1 inst_DSACK1_INT 1 2 1 1 .. .. .. .. AS_030 .. .. .. .. 1 1 .. .. @@ -77,11 +78,11 @@ inst_LDS_000_INT 1 1 1 1 .. .. 2 2 cpu_est_3_ .. .. 1 1 .. .. 1 1 cpu_est_0_ .. .. .. .. .. .. 1 1 cpu_est_1_ .. .. 1 1 .. .. 1 1 +inst_AMIGA_BUS_ENABLE_DMA_HIGH 1 1 1 1 .. .. .. .. inst_AMIGA_BUS_ENABLE_DMA_LOW 1 1 1 1 .. .. .. .. inst_BGACK_030_INT_D 1 1 .. .. .. .. 1 1 inst_VPA_D 1 1 .. .. .. .. 1 1 - CLK_000_D_2_ .. .. .. .. .. .. 1 1 - CLK_000_D_4_ .. .. .. .. .. .. 1 1 + CLK_000_D_3_ .. .. .. .. .. .. 1 1 inst_DTACK_D0 1 1 .. .. .. .. 1 1 inst_RESET_OUT 1 1 .. .. .. .. .. .. CLK_000_D_1_ .. .. .. .. .. .. 1 1 @@ -91,12 +92,11 @@ inst_CLK_OUT_PRE_D .. .. .. .. .. .. 1 1 IPL_D0_0_ 1 1 .. .. .. .. 1 1 IPL_D0_1_ 1 1 .. .. .. .. 1 1 IPL_D0_2_ 1 1 .. .. .. .. 1 1 - CLK_000_D_3_ .. .. .. .. .. .. 1 1 - CLK_000_D_5_ .. .. .. .. .. .. 1 1 -inst_AMIGA_BUS_ENABLE_DMA_HIGH 1 1 1 1 .. .. .. .. - SM_AMIGA_1_ 1 1 .. .. .. .. 1 1 + CLK_000_D_2_ .. .. .. .. .. .. 1 1 + CLK_000_D_4_ .. .. .. .. .. .. 1 1 SM_AMIGA_6_ 1 1 .. .. .. .. 1 1 SM_AMIGA_4_ 1 1 .. .. .. .. 1 1 + SM_AMIGA_1_ 1 1 .. .. .. .. 1 1 SM_AMIGA_0_ 1 1 .. .. .. .. 1 1 RST_DLY_0_ 1 1 .. .. .. .. 1 1 RST_DLY_1_ 1 1 .. .. .. .. 1 1 diff --git a/Logic/68030_tk.tt2 b/Logic/68030_tk.tt2 index 56c2fbd..40e5df8 100644 --- a/Logic/68030_tk.tt2 +++ b/Logic/68030_tk.tt2 @@ -1,506 +1,495 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Thu Oct 06 22:04:11 2016 +#$ DATE Sat Oct 15 23:48:24 2016 #$ MODULE 68030_tk -#$ PINS 61 AHIGH_31_ A_DECODE_23_ IPL_2_ FC_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 AHIGH_30_ CLK_000 AHIGH_29_ CLK_OSZI AHIGH_28_ CLK_DIV_OUT AHIGH_27_ AHIGH_26_ FPU_CS AHIGH_25_ FPU_SENSE AHIGH_24_ DSACK1 A_DECODE_22_ DTACK A_DECODE_21_ AVEC A_DECODE_20_ E A_DECODE_19_ VPA A_DECODE_18_ A_DECODE_17_ RST A_DECODE_16_ RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_1_ IPL_0_ FC_0_ A_1_ SIZE_1_ IPL_030_2_ RW_000 BG_000 BGACK_030 SIZE_0_ CLK_EXP VMA RW A_0_ IPL_030_1_ IPL_030_0_ -#$ NODES 44 cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_ inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ inst_VPA_D CLK_000_D_2_ CLK_000_D_4_ inst_DTACK_D0 inst_RESET_OUT CLK_000_D_1_ CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_D IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_3_ CLK_000_D_5_ inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_1_ inst_UDS_000_INT inst_DS_000_ENABLE inst_LDS_000_INT SM_AMIGA_6_ SM_AMIGA_4_ SM_AMIGA_0_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ inst_CLK_030_H inst_DSACK1_INT inst_AS_000_INT SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ +#$ PINS 61 AHIGH_31_ A_DECODE_23_ IPL_2_ FC_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 AHIGH_30_ BGACK_000 AHIGH_29_ CLK_030 AHIGH_28_ CLK_000 AHIGH_27_ CLK_OSZI AHIGH_26_ CLK_DIV_OUT AHIGH_25_ AHIGH_24_ FPU_CS A_DECODE_22_ FPU_SENSE A_DECODE_21_ DSACK1 A_DECODE_20_ DTACK A_DECODE_19_ AVEC A_DECODE_18_ E A_DECODE_17_ VPA A_DECODE_16_ RST RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_1_ IPL_0_ FC_0_ A_1_ SIZE_1_ IPL_030_2_ RW_000 BG_000 SIZE_0_ BGACK_030 CLK_EXP VMA RW A_0_ IPL_030_1_ IPL_030_0_ +#$ NODES 43 cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_ inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ inst_VPA_D CLK_000_D_3_ inst_DTACK_D0 inst_RESET_OUT CLK_000_D_1_ CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_D IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ CLK_000_D_4_ inst_LDS_000_INT inst_DS_000_ENABLE inst_UDS_000_INT SM_AMIGA_6_ SM_AMIGA_4_ SM_AMIGA_1_ SM_AMIGA_0_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ inst_CLK_030_H inst_DSACK1_INT inst_AS_000_INT SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ .type fr -.i 97 -.o 160 -.ilb A_DECODE_23_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_DECODE_22_ A_DECODE_21_ A_DECODE_20_ A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_1_ IPL_0_ FC_0_ A_1_ BGACK_030.Q VMA.Q cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q inst_VPA_D.Q CLK_000_D_2_.Q CLK_000_D_4_.Q inst_DTACK_D0.Q inst_RESET_OUT.Q CLK_000_D_1_.Q CLK_000_D_0_.Q inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_D.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q CLK_000_D_3_.Q CLK_000_D_5_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q SM_AMIGA_1_.Q inst_UDS_000_INT.Q inst_DS_000_ENABLE.Q inst_LDS_000_INT.Q SM_AMIGA_6_.Q SM_AMIGA_4_.Q SM_AMIGA_0_.Q SIZE_0_.Q SIZE_1_.Q RW_000.Q RW.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q A_0_.Q inst_CLK_030_H.Q inst_DSACK1_INT.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN -.ob DS_030 FPU_CS DSACK1 AVEC E RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SM_AMIGA_i_7_.C SM_AMIGA_6_.C SM_AMIGA_5_.C SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.C SM_AMIGA_1_.C SM_AMIGA_0_.C cpu_est_3_.C IPL_030_0_.C IPL_030_1_.C IPL_030_2_.C IPL_D0_0_.C IPL_D0_1_.C IPL_D0_2_.C CLK_000_D_0_.C CLK_000_D_1_.C CLK_000_D_2_.C CLK_000_D_3_.C CLK_000_D_4_.C CLK_000_D_5_.C CYCLE_DMA_0_.C CYCLE_DMA_1_.C SIZE_0_.C SIZE_1_.C cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C RST_DLY_0_.C RST_DLY_1_.C RST_DLY_2_.C inst_DS_000_DMA.C inst_DSACK1_INT.C inst_AS_000_INT.C inst_AS_030_D0.C inst_VPA_D.C inst_DTACK_D0.C inst_CLK_030_H.C inst_RESET_OUT.C inst_DS_000_ENABLE.C BG_000.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_UDS_000_INT.C A_0_.C RW.C VMA.C RW_000.C inst_AS_030_000_SYNC.C inst_LDS_000_INT.C BGACK_030.C inst_AS_000_DMA.C inst_BGACK_030_INT_D.C CLK_EXP.C inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_D.C AHIGH_31_ AS_030 AS_000 UDS_000 LDS_000 BERR AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE CLK_DIV_OUT.C CLK_DIV_OUT.D BGACK_030.D VMA.T cpu_est_2_.D cpu_est_3_.D cpu_est_0_.D cpu_est_1_.D inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AS_030_D0.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D inst_AS_000_DMA.D inst_DS_000_DMA.D CYCLE_DMA_0_.D CYCLE_DMA_1_.D inst_VPA_D.D CLK_000_D_2_.D CLK_000_D_4_.D inst_DTACK_D0.D inst_RESET_OUT.D CLK_000_D_1_.D CLK_000_D_0_.D inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_D.D IPL_D0_0_.D IPL_D0_1_.D IPL_D0_2_.D CLK_000_D_3_.D CLK_000_D_5_.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.D SM_AMIGA_1_.D inst_UDS_000_INT.D inst_DS_000_ENABLE.D inst_LDS_000_INT.D SM_AMIGA_6_.D SM_AMIGA_4_.D SM_AMIGA_0_.D SIZE_0_.D SIZE_1_.D RW_000.D RW.D RST_DLY_0_.D RST_DLY_1_.D RST_DLY_2_.D A_0_.D inst_CLK_030_H.D inst_DSACK1_INT.D inst_AS_000_INT.D SM_AMIGA_5_.D SM_AMIGA_3_.T SM_AMIGA_2_.D SM_AMIGA_i_7_.T BG_000.D CLK_EXP.D IPL_030_0_.D IPL_030_1_.D IPL_030_2_.D -.p 494 -------------------------------------------------------------------------------------------------- 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-------------1-------------1-----------0-----0--------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ -------------1--------------0----------0-----0--------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ -------------1---------------1---------0-----0--------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ -------------1----------------1--------0-----0--------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ -------------1-------------------------1--1--0--------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ --------------------------1------------0----------------------------------0---------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ ---------------------------1-----------0----------------------------------0---------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ ----------------------------0----------0----------------------------------0---------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ -----------------------------1---------0----------------------------------0---------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ ------------------------------1--------0----------------------------------0---------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ ---------------------------------------1--1-------------------------------0---------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ --------------------------------------------------------0--0-------------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~ -------------1------------------------------01------------1-0--------------1---------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ -----------------------------------------------------------0--------------------1----------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~ +.i 96 +.o 158 +.ilb A_DECODE_23_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_DECODE_22_ A_DECODE_21_ A_DECODE_20_ A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_1_ IPL_0_ FC_0_ A_1_ BGACK_030.Q VMA.Q cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q inst_VPA_D.Q CLK_000_D_3_.Q inst_DTACK_D0.Q inst_RESET_OUT.Q CLK_000_D_1_.Q CLK_000_D_0_.Q inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_D.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q CLK_000_D_2_.Q CLK_000_D_4_.Q inst_LDS_000_INT.Q inst_DS_000_ENABLE.Q inst_UDS_000_INT.Q SM_AMIGA_6_.Q SM_AMIGA_4_.Q SM_AMIGA_1_.Q SM_AMIGA_0_.Q SIZE_0_.Q SIZE_1_.Q RW_000.Q RW.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q A_0_.Q inst_CLK_030_H.Q inst_DSACK1_INT.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN +.ob DS_030 FPU_CS DSACK1 AVEC E RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_D0_0_.C IPL_D0_1_.C IPL_D0_2_.C SM_AMIGA_i_7_.C SM_AMIGA_6_.C SM_AMIGA_5_.C SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.C SM_AMIGA_1_.C SM_AMIGA_0_.C cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C cpu_est_3_.C IPL_030_0_.C IPL_030_1_.C IPL_030_2_.C RST_DLY_2_.C CLK_000_D_0_.C CLK_000_D_1_.C CLK_000_D_2_.C CLK_000_D_3_.C CLK_000_D_4_.C CYCLE_DMA_0_.C CYCLE_DMA_1_.C SIZE_0_.C SIZE_1_.C RST_DLY_0_.C RST_DLY_1_.C RW_000.C inst_AS_030_000_SYNC.C inst_LDS_000_INT.C BGACK_030.C inst_AS_000_DMA.C inst_DS_000_DMA.C inst_DSACK1_INT.C inst_AS_000_INT.C inst_AS_030_D0.C inst_VPA_D.C inst_DTACK_D0.C inst_CLK_030_H.C inst_RESET_OUT.C inst_DS_000_ENABLE.C BG_000.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_UDS_000_INT.C A_0_.C RW.C VMA.C inst_BGACK_030_INT_D.C CLK_EXP.C inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_D.C AHIGH_31_ AS_030 AS_000 UDS_000 LDS_000 BERR AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE CLK_DIV_OUT.C CLK_DIV_OUT.D BGACK_030.D VMA.T cpu_est_2_.D cpu_est_3_.D cpu_est_0_.D cpu_est_1_.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AS_030_D0.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D inst_AS_000_DMA.D inst_DS_000_DMA.D CYCLE_DMA_0_.D CYCLE_DMA_1_.D inst_VPA_D.D CLK_000_D_3_.D inst_DTACK_D0.D inst_RESET_OUT.D CLK_000_D_1_.D CLK_000_D_0_.D inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_D.D IPL_D0_0_.D IPL_D0_1_.D IPL_D0_2_.D CLK_000_D_2_.D CLK_000_D_4_.D inst_LDS_000_INT.D inst_DS_000_ENABLE.D inst_UDS_000_INT.D SM_AMIGA_6_.D SM_AMIGA_4_.D SM_AMIGA_1_.D SM_AMIGA_0_.D SIZE_0_.D SIZE_1_.D RW_000.D RW.D RST_DLY_0_.D RST_DLY_1_.D RST_DLY_2_.D A_0_.D inst_CLK_030_H.D inst_DSACK1_INT.D inst_AS_000_INT.D SM_AMIGA_5_.D SM_AMIGA_3_.T SM_AMIGA_2_.D SM_AMIGA_i_7_.T BG_000.D CLK_EXP.D IPL_030_0_.T IPL_030_1_.T IPL_030_2_.T +.p 483 +------------------------------------------------------------------------------------------------ ~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-1---------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +--------------------------1------------0--------------------------------0---------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +---------------------------0-----------0--------------------------------0---------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +----------------------------1----------0--------------------------------0---------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +-----------------------------1---------0--------------------------------0---------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +---------------------------------------1-1------------------------------0---------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +-----------------------------------------------------0--0--------------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ +------------1------------------------------01----------1--0--------------1---------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ +--------------------------------------------------------0---------------------1----------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ .end diff --git a/Logic/68030_tk.tt3 b/Logic/68030_tk.tt3 index 23f251e..bcc3de9 100644 --- a/Logic/68030_tk.tt3 +++ b/Logic/68030_tk.tt3 @@ -1,506 +1,495 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Thu Oct 06 22:04:11 2016 +#$ DATE Sat Oct 15 23:48:24 2016 #$ MODULE 68030_tk -#$ PINS 61 AHIGH_31_ A_DECODE_23_ IPL_2_ FC_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 AHIGH_30_ CLK_000 AHIGH_29_ CLK_OSZI AHIGH_28_ CLK_DIV_OUT AHIGH_27_ AHIGH_26_ FPU_CS AHIGH_25_ FPU_SENSE AHIGH_24_ DSACK1 A_DECODE_22_ DTACK A_DECODE_21_ AVEC A_DECODE_20_ E A_DECODE_19_ VPA A_DECODE_18_ A_DECODE_17_ RST A_DECODE_16_ RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_1_ IPL_0_ FC_0_ A_1_ SIZE_1_ IPL_030_2_ RW_000 BG_000 BGACK_030 SIZE_0_ CLK_EXP VMA RW A_0_ IPL_030_1_ IPL_030_0_ -#$ NODES 44 cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_ inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ inst_VPA_D CLK_000_D_2_ CLK_000_D_4_ inst_DTACK_D0 inst_RESET_OUT CLK_000_D_1_ CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_D IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_3_ CLK_000_D_5_ inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_1_ inst_UDS_000_INT inst_DS_000_ENABLE inst_LDS_000_INT SM_AMIGA_6_ SM_AMIGA_4_ SM_AMIGA_0_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ inst_CLK_030_H inst_DSACK1_INT inst_AS_000_INT SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ +#$ PINS 61 AHIGH_31_ A_DECODE_23_ IPL_2_ FC_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 AHIGH_30_ BGACK_000 AHIGH_29_ CLK_030 AHIGH_28_ CLK_000 AHIGH_27_ CLK_OSZI AHIGH_26_ CLK_DIV_OUT AHIGH_25_ AHIGH_24_ FPU_CS A_DECODE_22_ FPU_SENSE A_DECODE_21_ DSACK1 A_DECODE_20_ DTACK A_DECODE_19_ AVEC A_DECODE_18_ E A_DECODE_17_ VPA A_DECODE_16_ RST RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_1_ IPL_0_ FC_0_ A_1_ SIZE_1_ IPL_030_2_ RW_000 BG_000 SIZE_0_ BGACK_030 CLK_EXP VMA RW A_0_ IPL_030_1_ IPL_030_0_ +#$ NODES 43 cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_ inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ inst_VPA_D CLK_000_D_3_ inst_DTACK_D0 inst_RESET_OUT CLK_000_D_1_ CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_D IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ CLK_000_D_4_ inst_LDS_000_INT inst_DS_000_ENABLE inst_UDS_000_INT SM_AMIGA_6_ SM_AMIGA_4_ SM_AMIGA_1_ SM_AMIGA_0_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ inst_CLK_030_H inst_DSACK1_INT inst_AS_000_INT SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ .type fr -.i 97 -.o 160 -.ilb A_DECODE_23_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_DECODE_22_ A_DECODE_21_ A_DECODE_20_ A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_1_ IPL_0_ FC_0_ A_1_ BGACK_030.Q VMA.Q cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q inst_VPA_D.Q CLK_000_D_2_.Q CLK_000_D_4_.Q inst_DTACK_D0.Q inst_RESET_OUT.Q CLK_000_D_1_.Q CLK_000_D_0_.Q inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_D.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q CLK_000_D_3_.Q CLK_000_D_5_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q SM_AMIGA_1_.Q inst_UDS_000_INT.Q inst_DS_000_ENABLE.Q inst_LDS_000_INT.Q SM_AMIGA_6_.Q SM_AMIGA_4_.Q SM_AMIGA_0_.Q SIZE_0_.Q SIZE_1_.Q RW_000.Q RW.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q A_0_.Q inst_CLK_030_H.Q inst_DSACK1_INT.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN -.ob DS_030 FPU_CS DSACK1 AVEC E RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SM_AMIGA_i_7_.C SM_AMIGA_6_.C SM_AMIGA_5_.C SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.C SM_AMIGA_1_.C SM_AMIGA_0_.C cpu_est_3_.C IPL_030_0_.C IPL_030_1_.C IPL_030_2_.C IPL_D0_0_.C IPL_D0_1_.C IPL_D0_2_.C CLK_000_D_0_.C CLK_000_D_1_.C CLK_000_D_2_.C CLK_000_D_3_.C CLK_000_D_4_.C CLK_000_D_5_.C CYCLE_DMA_0_.C CYCLE_DMA_1_.C SIZE_0_.C SIZE_1_.C cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C RST_DLY_0_.C RST_DLY_1_.C RST_DLY_2_.C inst_DS_000_DMA.C inst_DSACK1_INT.C inst_AS_000_INT.C inst_AS_030_D0.C inst_VPA_D.C inst_DTACK_D0.C inst_CLK_030_H.C inst_RESET_OUT.C inst_DS_000_ENABLE.C BG_000.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_UDS_000_INT.C A_0_.C RW.C VMA.C RW_000.C inst_AS_030_000_SYNC.C inst_LDS_000_INT.C BGACK_030.C inst_AS_000_DMA.C inst_BGACK_030_INT_D.C CLK_EXP.C inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_D.C AHIGH_31_ AS_030 AS_000 UDS_000 LDS_000 BERR AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE CLK_DIV_OUT.C CLK_DIV_OUT.D BGACK_030.D VMA.T cpu_est_2_.D cpu_est_3_.D cpu_est_0_.D cpu_est_1_.D inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AS_030_D0.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D inst_AS_000_DMA.D inst_DS_000_DMA.D CYCLE_DMA_0_.D CYCLE_DMA_1_.D inst_VPA_D.D CLK_000_D_2_.D CLK_000_D_4_.D inst_DTACK_D0.D inst_RESET_OUT.D CLK_000_D_1_.D CLK_000_D_0_.D inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_D.D IPL_D0_0_.D IPL_D0_1_.D IPL_D0_2_.D CLK_000_D_3_.D CLK_000_D_5_.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.D SM_AMIGA_1_.D inst_UDS_000_INT.D inst_DS_000_ENABLE.D inst_LDS_000_INT.D SM_AMIGA_6_.D SM_AMIGA_4_.D SM_AMIGA_0_.D SIZE_0_.D SIZE_1_.D RW_000.D RW.D RST_DLY_0_.D RST_DLY_1_.D RST_DLY_2_.D A_0_.D inst_CLK_030_H.D inst_DSACK1_INT.D inst_AS_000_INT.D SM_AMIGA_5_.D SM_AMIGA_3_.T SM_AMIGA_2_.D SM_AMIGA_i_7_.T BG_000.D CLK_EXP.D IPL_030_0_.D IPL_030_1_.D IPL_030_2_.D -.p 494 -------------------------------------------------------------------------------------------------- ~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --1----------------------------------------------------------------------------------------------- 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------------------------------------------------------------------------------------------1------- ~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----0-------------------------------------------------------------------------------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------------------------------------------------1------ ~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----0--------------------------------------------------------------------------------------1------ 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----0----------------------------------------------------------------------------------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------------------------------------------------1--- ~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----0-----------------------------------------------------------------------------------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------1--------------------------------------------1------------------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~ -------------1--------------------------------------------1------------------------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ -------------1------------1------------0-----0--------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ -------------1-------------1-----------0-----0--------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ -------------1--------------0----------0-----0--------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ -------------1---------------1---------0-----0--------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ -------------1----------------1--------0-----0--------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ -------------1-------------------------1--1--0--------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ --------------------------1------------0----------------------------------0---------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ ---------------------------1-----------0----------------------------------0---------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ ----------------------------0----------0----------------------------------0---------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ -----------------------------1---------0----------------------------------0---------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ ------------------------------1--------0----------------------------------0---------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ ---------------------------------------1--1-------------------------------0---------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ --------------------------------------------------------0--0-------------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~ -------------1------------------------------01------------1-0--------------1---------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ -----------------------------------------------------------0--------------------1----------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~ +.i 96 +.o 158 +.ilb A_DECODE_23_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_DECODE_22_ A_DECODE_21_ A_DECODE_20_ A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_1_ IPL_0_ FC_0_ A_1_ BGACK_030.Q VMA.Q cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q inst_VPA_D.Q CLK_000_D_3_.Q inst_DTACK_D0.Q inst_RESET_OUT.Q CLK_000_D_1_.Q CLK_000_D_0_.Q inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_D.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q CLK_000_D_2_.Q CLK_000_D_4_.Q inst_LDS_000_INT.Q inst_DS_000_ENABLE.Q inst_UDS_000_INT.Q SM_AMIGA_6_.Q SM_AMIGA_4_.Q SM_AMIGA_1_.Q SM_AMIGA_0_.Q SIZE_0_.Q SIZE_1_.Q RW_000.Q RW.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q A_0_.Q inst_CLK_030_H.Q inst_DSACK1_INT.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN +.ob DS_030 FPU_CS DSACK1 AVEC E RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_D0_0_.C IPL_D0_1_.C IPL_D0_2_.C SM_AMIGA_i_7_.C SM_AMIGA_6_.C SM_AMIGA_5_.C SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.C SM_AMIGA_1_.C SM_AMIGA_0_.C cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C cpu_est_3_.C IPL_030_0_.C IPL_030_1_.C IPL_030_2_.C RST_DLY_2_.C CLK_000_D_0_.C CLK_000_D_1_.C CLK_000_D_2_.C CLK_000_D_3_.C CLK_000_D_4_.C CYCLE_DMA_0_.C CYCLE_DMA_1_.C SIZE_0_.C SIZE_1_.C RST_DLY_0_.C RST_DLY_1_.C RW_000.C inst_AS_030_000_SYNC.C inst_LDS_000_INT.C BGACK_030.C inst_AS_000_DMA.C inst_DS_000_DMA.C inst_DSACK1_INT.C inst_AS_000_INT.C inst_AS_030_D0.C inst_VPA_D.C inst_DTACK_D0.C inst_CLK_030_H.C inst_RESET_OUT.C inst_DS_000_ENABLE.C BG_000.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_UDS_000_INT.C A_0_.C RW.C VMA.C inst_BGACK_030_INT_D.C CLK_EXP.C inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_D.C AHIGH_31_ AS_030 AS_000 UDS_000 LDS_000 BERR AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE CLK_DIV_OUT.C CLK_DIV_OUT.D BGACK_030.D VMA.T cpu_est_2_.D cpu_est_3_.D cpu_est_0_.D cpu_est_1_.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AS_030_D0.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D inst_AS_000_DMA.D inst_DS_000_DMA.D CYCLE_DMA_0_.D CYCLE_DMA_1_.D inst_VPA_D.D CLK_000_D_3_.D inst_DTACK_D0.D inst_RESET_OUT.D CLK_000_D_1_.D CLK_000_D_0_.D inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_D.D IPL_D0_0_.D IPL_D0_1_.D IPL_D0_2_.D CLK_000_D_2_.D CLK_000_D_4_.D inst_LDS_000_INT.D inst_DS_000_ENABLE.D inst_UDS_000_INT.D SM_AMIGA_6_.D SM_AMIGA_4_.D SM_AMIGA_1_.D SM_AMIGA_0_.D SIZE_0_.D SIZE_1_.D RW_000.D RW.D RST_DLY_0_.D RST_DLY_1_.D RST_DLY_2_.D A_0_.D inst_CLK_030_H.D inst_DSACK1_INT.D inst_AS_000_INT.D SM_AMIGA_5_.D SM_AMIGA_3_.T SM_AMIGA_2_.D SM_AMIGA_i_7_.T BG_000.D CLK_EXP.D IPL_030_0_.T IPL_030_1_.T IPL_030_2_.T +.p 483 +------------------------------------------------------------------------------------------------ ~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-1---------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--0--------------------------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1-------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ +-----0------------------------------------------------------------------------------------------ ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------1---------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------1--------------------------------------------------------------------------------------- ~~~~~~~~~~~1111111111111111111111111111111111111111111111111111111~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1-------------------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------1------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1------------------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------0----------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~1111111~~1~1~~~~~111~~1~1~~~~1111~~~1~11~~~~1~~~~ +----------------1------------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------1------------------------------------------------------------------------------ ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------0----------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------1---------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------1--------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------1-------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------0------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------1----------------------------------------------------------------------- ~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~111~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----1------------------1----------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---0--------------------0----------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------10----------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------00----------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------0------------0---------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------1-0------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------010------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------10-1------------------------------------------------------------------ ~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------01------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------1--0------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------01-0------------------------------------------------------------------ ~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------1-----1----------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------0-----1----------------------------------------------------------------- ~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------1---------------------------------------------------------------- ~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------1------1---------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---0-----------------------------1-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--1-------------0010--1----------1-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------1--------1-------------------------------------------------------------- ~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------0--------1-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------11-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------1---------0------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~ +---------------------------------10------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------1------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------0----------------------------1------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------1----------------------------------------------------------- 1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------11--------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------00--------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------1------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------1-----------------------------1----------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------1-----------------1----------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1111~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------0-----------------1----------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---0--------------------0-----------------1----------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~111111111~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------0----------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------1---------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------1----------------0---------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------1---------------0---------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------1--------------0---------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1-------------0---------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------1--------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------1-----------------1--------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------1----------------1--------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------1---------------1--------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1--------------1--------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------00000-------------01--------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------0--------------10--------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------1-11-------------10--------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------0-11-------------10--------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------010-------------10--------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------1------------10011---------0---10--------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------1-------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------0-------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------1------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ +--------------------------------------------------1--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------------1------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------0------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------------1----------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------1------------------------------1-----------1---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ +------------1------------------------------01----------1---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~ +------------1-------------------------------0----------1---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------------1--0---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~ 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+---------------------------------------1-1------------------------------0---------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +-----------------------------------------------------0--0--------------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ +------------1------------------------------01----------1--0--------------1---------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ +--------------------------------------------------------0---------------------1----------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ .end diff --git a/Logic/68030_tk.tt4 b/Logic/68030_tk.tt4 index e93d336..9d3b4b1 100644 --- a/Logic/68030_tk.tt4 +++ b/Logic/68030_tk.tt4 @@ -1,262 +1,259 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Thu Oct 06 22:04:11 2016 +#$ DATE Sat Oct 15 23:48:24 2016 #$ MODULE BUS68030 #$ PINS 61 AHIGH_31_ A_DECODE_23_ IPL_2_ FC_1_ AS_030 AS_000 DS_030 UDS_000 - LDS_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 AHIGH_30_ CLK_000 AHIGH_29_ - CLK_OSZI AHIGH_28_ CLK_DIV_OUT AHIGH_27_ AHIGH_26_ FPU_CS AHIGH_25_ FPU_SENSE - AHIGH_24_ DSACK1 A_DECODE_22_ DTACK A_DECODE_21_ AVEC A_DECODE_20_ E - A_DECODE_19_ VPA A_DECODE_18_ A_DECODE_17_ RST A_DECODE_16_ RESET - AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH - CIIN IPL_1_ IPL_0_ FC_0_ A_1_ SIZE_1_ IPL_030_2_ RW_000 BG_000 BGACK_030 SIZE_0_ - CLK_EXP VMA RW A_0_ IPL_030_1_ IPL_030_0_ -#$ NODES 45 cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_ - inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_000_SYNC - inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ - inst_VPA_D CLK_000_D_2_ CLK_000_D_4_ inst_DTACK_D0 inst_RESET_OUT CLK_000_D_1_ - CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_D IPL_D0_0_ IPL_D0_1_ - IPL_D0_2_ CLK_000_D_3_ CLK_000_D_5_ inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_1_ - inst_UDS_000_INT inst_DS_000_ENABLE inst_LDS_000_INT SM_AMIGA_6_ SM_AMIGA_4_ + LDS_000 nEXP_SPACE BERR BG_030 AHIGH_30_ BGACK_000 AHIGH_29_ CLK_030 AHIGH_28_ + CLK_000 AHIGH_27_ CLK_OSZI AHIGH_26_ CLK_DIV_OUT AHIGH_25_ AHIGH_24_ FPU_CS + A_DECODE_22_ FPU_SENSE A_DECODE_21_ DSACK1 A_DECODE_20_ DTACK A_DECODE_19_ AVEC + A_DECODE_18_ E A_DECODE_17_ VPA A_DECODE_16_ RST RESET AMIGA_ADDR_ENABLE + AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_1_ IPL_0_ + FC_0_ A_1_ SIZE_1_ IPL_030_2_ RW_000 BG_000 SIZE_0_ BGACK_030 CLK_EXP VMA RW + A_0_ IPL_030_1_ IPL_030_0_ +#$ NODES 44 cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_ + inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 + inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA + CYCLE_DMA_0_ CYCLE_DMA_1_ inst_VPA_D CLK_000_D_3_ inst_DTACK_D0 inst_RESET_OUT + CLK_000_D_1_ CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_D IPL_D0_0_ + IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ CLK_000_D_4_ inst_LDS_000_INT + inst_DS_000_ENABLE inst_UDS_000_INT SM_AMIGA_6_ SM_AMIGA_4_ SM_AMIGA_1_ SM_AMIGA_0_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ inst_CLK_030_H inst_DSACK1_INT inst_AS_000_INT SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ CIIN_0 .type f -.i 98 -.o 164 +.i 97 +.o 162 .ilb A_DECODE_23_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_DECODE_22_ A_DECODE_21_ A_DECODE_20_ A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_1_ IPL_0_ FC_0_ A_1_ BGACK_030.Q VMA.Q cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q - inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_AS_030_000_SYNC.Q - inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q - CYCLE_DMA_1_.Q inst_VPA_D.Q CLK_000_D_2_.Q CLK_000_D_4_.Q inst_DTACK_D0.Q - inst_RESET_OUT.Q CLK_000_D_1_.Q CLK_000_D_0_.Q inst_CLK_OUT_PRE_50.Q - inst_CLK_OUT_PRE_D.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q CLK_000_D_3_.Q - CLK_000_D_5_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q SM_AMIGA_1_.Q inst_UDS_000_INT.Q - inst_DS_000_ENABLE.Q inst_LDS_000_INT.Q SM_AMIGA_6_.Q SM_AMIGA_4_.Q - SM_AMIGA_0_.Q SIZE_0_.Q SIZE_1_.Q RW_000.Q RW.Q RST_DLY_0_.Q RST_DLY_1_.Q - RST_DLY_2_.Q A_0_.Q inst_CLK_030_H.Q inst_DSACK1_INT.Q inst_AS_000_INT.Q - SM_AMIGA_5_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q - IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN - LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN - AHIGH_27_.PIN AHIGH_28_.PIN AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN - BERR.PIN RW.PIN CIIN_0 + inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q + inst_AS_030_D0.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q + inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q inst_VPA_D.Q CLK_000_D_3_.Q + inst_DTACK_D0.Q inst_RESET_OUT.Q CLK_000_D_1_.Q CLK_000_D_0_.Q + inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_D.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q + CLK_000_D_2_.Q CLK_000_D_4_.Q inst_LDS_000_INT.Q inst_DS_000_ENABLE.Q + inst_UDS_000_INT.Q SM_AMIGA_6_.Q SM_AMIGA_4_.Q SM_AMIGA_1_.Q SM_AMIGA_0_.Q + SIZE_0_.Q SIZE_1_.Q RW_000.Q RW.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q A_0_.Q + inst_CLK_030_H.Q inst_DSACK1_INT.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q SM_AMIGA_3_.Q + SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q + AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN + AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN + AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN CIIN_0 .ob AHIGH_31_ AHIGH_31_.OE AS_030% AS_030.OE AS_000% AS_000.OE DS_030% DS_030.OE UDS_000% UDS_000.OE LDS_000% LDS_000.OE BERR BERR.OE AHIGH_30_ AHIGH_30_.OE - AHIGH_29_ AHIGH_29_.OE AHIGH_28_ AHIGH_28_.OE CLK_DIV_OUT.D CLK_DIV_OUT.C - AHIGH_27_ AHIGH_27_.OE AHIGH_26_ AHIGH_26_.OE FPU_CS% AHIGH_25_ AHIGH_25_.OE - AHIGH_24_ AHIGH_24_.OE DSACK1% DSACK1.OE AVEC E RESET RESET.OE AMIGA_ADDR_ENABLE - AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW% AMIGA_BUS_ENABLE_HIGH CIIN CIIN.OE - SIZE_1_.D SIZE_1_.C SIZE_1_.OE IPL_030_2_.D% IPL_030_2_.C RW_000.D% RW_000.C - RW_000.OE BG_000.D% BG_000.C BGACK_030.D BGACK_030.C SIZE_0_.D% SIZE_0_.C - SIZE_0_.OE CLK_EXP.D CLK_EXP.C VMA.T VMA.C RW.D% RW.C RW.OE A_0_.D A_0_.C - A_0_.OE IPL_030_1_.D% IPL_030_1_.C IPL_030_0_.D% IPL_030_0_.C cpu_est_2_.D.X1 + AHIGH_29_ AHIGH_29_.OE AHIGH_28_ AHIGH_28_.OE AHIGH_27_ AHIGH_27_.OE AHIGH_26_ + AHIGH_26_.OE CLK_DIV_OUT.D CLK_DIV_OUT.C AHIGH_25_ AHIGH_25_.OE AHIGH_24_ + AHIGH_24_.OE FPU_CS% DSACK1% DSACK1.OE AVEC E RESET RESET.OE AMIGA_ADDR_ENABLE + AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW% AMIGA_BUS_ENABLE_HIGH% CIIN CIIN.OE + SIZE_1_.D SIZE_1_.C SIZE_1_.OE IPL_030_2_.T IPL_030_2_.C RW_000.D% RW_000.C + RW_000.OE BG_000.D% BG_000.C SIZE_0_.D% SIZE_0_.C SIZE_0_.OE BGACK_030.D + BGACK_030.C CLK_EXP.D CLK_EXP.C VMA.T VMA.C RW.D% RW.C RW.OE A_0_.D A_0_.C + A_0_.OE IPL_030_1_.T IPL_030_1_.C IPL_030_0_.T IPL_030_0_.C cpu_est_2_.D.X1 cpu_est_2_.D.X2 cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C cpu_est_0_.D cpu_est_0_.C - cpu_est_1_.D cpu_est_1_.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D% + cpu_est_1_.D cpu_est_1_.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D% + inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D% inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_AS_030_D0.D% inst_AS_030_D0.C inst_AS_030_000_SYNC.D% inst_AS_030_000_SYNC.C inst_BGACK_030_INT_D.D% inst_BGACK_030_INT_D.C inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D inst_DS_000_DMA.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C - inst_VPA_D.D% inst_VPA_D.C CLK_000_D_2_.D CLK_000_D_2_.C CLK_000_D_4_.D - CLK_000_D_4_.C inst_DTACK_D0.D% inst_DTACK_D0.C inst_RESET_OUT.D - inst_RESET_OUT.C CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_0_.D CLK_000_D_0_.C - inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_D.D - inst_CLK_OUT_PRE_D.C IPL_D0_0_.D% IPL_D0_0_.C IPL_D0_1_.D% IPL_D0_1_.C - IPL_D0_2_.D% IPL_D0_2_.C CLK_000_D_3_.D CLK_000_D_3_.C CLK_000_D_5_.D - CLK_000_D_5_.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D% - inst_AMIGA_BUS_ENABLE_DMA_HIGH.C SM_AMIGA_1_.D SM_AMIGA_1_.C inst_UDS_000_INT.D% - inst_UDS_000_INT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C inst_LDS_000_INT.D - inst_LDS_000_INT.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_4_.D SM_AMIGA_4_.C - SM_AMIGA_0_.D SM_AMIGA_0_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D.X1 - RST_DLY_1_.D.X2 RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C inst_CLK_030_H.D - inst_CLK_030_H.C inst_DSACK1_INT.D% inst_DSACK1_INT.C inst_AS_000_INT.D% - inst_AS_000_INT.C SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_3_.T SM_AMIGA_3_.C - SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_i_7_.T.X1 SM_AMIGA_i_7_.T.X2 + inst_VPA_D.D% inst_VPA_D.C CLK_000_D_3_.D CLK_000_D_3_.C inst_DTACK_D0.D% + inst_DTACK_D0.C inst_RESET_OUT.D inst_RESET_OUT.C CLK_000_D_1_.D CLK_000_D_1_.C + CLK_000_D_0_.D CLK_000_D_0_.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C + inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C IPL_D0_0_.D% IPL_D0_0_.C IPL_D0_1_.D% + IPL_D0_1_.C IPL_D0_2_.D% IPL_D0_2_.C CLK_000_D_2_.D CLK_000_D_2_.C + CLK_000_D_4_.D CLK_000_D_4_.C inst_LDS_000_INT.D inst_LDS_000_INT.C + inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C inst_UDS_000_INT.D% inst_UDS_000_INT.C + SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_1_.D + SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C RST_DLY_0_.D RST_DLY_0_.C + RST_DLY_1_.D.X1 RST_DLY_1_.D.X2 RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C + inst_CLK_030_H.D inst_CLK_030_H.C inst_DSACK1_INT.D% inst_DSACK1_INT.C + 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+------------1------------------------------10--------------------------1----------------------0-- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000 +------------0------------------------------------------------------------1----------------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000 +------------1------------------------------01-------------1--------------1----------------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000 +---1--------1--------------------0------0----------1---------------------0----------------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000 +---1--------1--------------------0------0--01------1------1--------------0----------------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 .end diff --git a/Logic/68030_tk.tte b/Logic/68030_tk.tte index 5d3c225..41b752d 100644 --- a/Logic/68030_tk.tte +++ b/Logic/68030_tk.tte @@ -1,262 +1,259 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Thu Oct 06 22:04:11 2016 +#$ DATE Sat Oct 15 23:48:24 2016 #$ MODULE BUS68030 #$ PINS 61 AHIGH_31_ A_DECODE_23_ IPL_2_ FC_1_ AS_030 AS_000 DS_030 UDS_000 - LDS_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 AHIGH_30_ CLK_000 AHIGH_29_ - CLK_OSZI AHIGH_28_ CLK_DIV_OUT AHIGH_27_ AHIGH_26_ FPU_CS AHIGH_25_ FPU_SENSE - AHIGH_24_ DSACK1 A_DECODE_22_ DTACK A_DECODE_21_ AVEC A_DECODE_20_ E - A_DECODE_19_ VPA A_DECODE_18_ A_DECODE_17_ RST A_DECODE_16_ RESET - AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH - CIIN IPL_1_ IPL_0_ FC_0_ A_1_ SIZE_1_ IPL_030_2_ RW_000 BG_000 BGACK_030 SIZE_0_ - CLK_EXP VMA RW A_0_ IPL_030_1_ IPL_030_0_ -#$ NODES 45 cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_ - inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_000_SYNC - inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ - inst_VPA_D CLK_000_D_2_ CLK_000_D_4_ inst_DTACK_D0 inst_RESET_OUT CLK_000_D_1_ - CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_D IPL_D0_0_ IPL_D0_1_ - IPL_D0_2_ CLK_000_D_3_ CLK_000_D_5_ inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_1_ - inst_UDS_000_INT inst_DS_000_ENABLE inst_LDS_000_INT SM_AMIGA_6_ SM_AMIGA_4_ + LDS_000 nEXP_SPACE BERR BG_030 AHIGH_30_ BGACK_000 AHIGH_29_ CLK_030 AHIGH_28_ + CLK_000 AHIGH_27_ CLK_OSZI AHIGH_26_ CLK_DIV_OUT AHIGH_25_ AHIGH_24_ FPU_CS + A_DECODE_22_ FPU_SENSE A_DECODE_21_ DSACK1 A_DECODE_20_ DTACK A_DECODE_19_ AVEC + A_DECODE_18_ E A_DECODE_17_ VPA A_DECODE_16_ RST RESET AMIGA_ADDR_ENABLE + AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_1_ IPL_0_ + FC_0_ A_1_ SIZE_1_ IPL_030_2_ RW_000 BG_000 SIZE_0_ BGACK_030 CLK_EXP VMA RW + A_0_ IPL_030_1_ IPL_030_0_ +#$ NODES 44 cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_ + inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 + inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA + CYCLE_DMA_0_ CYCLE_DMA_1_ inst_VPA_D CLK_000_D_3_ inst_DTACK_D0 inst_RESET_OUT + CLK_000_D_1_ CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_D IPL_D0_0_ + IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ CLK_000_D_4_ inst_LDS_000_INT + inst_DS_000_ENABLE inst_UDS_000_INT SM_AMIGA_6_ SM_AMIGA_4_ SM_AMIGA_1_ SM_AMIGA_0_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ inst_CLK_030_H inst_DSACK1_INT inst_AS_000_INT SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ CIIN_0 .type f -.i 98 -.o 164 +.i 97 +.o 162 .ilb A_DECODE_23_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_DECODE_22_ A_DECODE_21_ A_DECODE_20_ A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_1_ IPL_0_ FC_0_ A_1_ BGACK_030.Q VMA.Q cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q - inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_AS_030_000_SYNC.Q - inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q - CYCLE_DMA_1_.Q inst_VPA_D.Q CLK_000_D_2_.Q CLK_000_D_4_.Q inst_DTACK_D0.Q - inst_RESET_OUT.Q CLK_000_D_1_.Q CLK_000_D_0_.Q inst_CLK_OUT_PRE_50.Q - inst_CLK_OUT_PRE_D.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q CLK_000_D_3_.Q - CLK_000_D_5_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q SM_AMIGA_1_.Q inst_UDS_000_INT.Q - inst_DS_000_ENABLE.Q inst_LDS_000_INT.Q SM_AMIGA_6_.Q SM_AMIGA_4_.Q - SM_AMIGA_0_.Q SIZE_0_.Q SIZE_1_.Q RW_000.Q RW.Q RST_DLY_0_.Q RST_DLY_1_.Q - RST_DLY_2_.Q A_0_.Q inst_CLK_030_H.Q inst_DSACK1_INT.Q inst_AS_000_INT.Q - SM_AMIGA_5_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q - IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN - LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN - AHIGH_27_.PIN AHIGH_28_.PIN AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN - BERR.PIN RW.PIN CIIN_0 + inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q + inst_AS_030_D0.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q + inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q inst_VPA_D.Q CLK_000_D_3_.Q + inst_DTACK_D0.Q inst_RESET_OUT.Q CLK_000_D_1_.Q CLK_000_D_0_.Q + inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_D.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q + CLK_000_D_2_.Q CLK_000_D_4_.Q inst_LDS_000_INT.Q inst_DS_000_ENABLE.Q + inst_UDS_000_INT.Q SM_AMIGA_6_.Q SM_AMIGA_4_.Q SM_AMIGA_1_.Q SM_AMIGA_0_.Q + SIZE_0_.Q SIZE_1_.Q RW_000.Q RW.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q A_0_.Q + inst_CLK_030_H.Q inst_DSACK1_INT.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q SM_AMIGA_3_.Q + SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q + AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN + AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN + AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN CIIN_0 .ob AHIGH_31_ AHIGH_31_.OE AS_030- AS_030.OE AS_000- AS_000.OE DS_030- DS_030.OE UDS_000- UDS_000.OE LDS_000- LDS_000.OE BERR BERR.OE AHIGH_30_ AHIGH_30_.OE - AHIGH_29_ AHIGH_29_.OE AHIGH_28_ AHIGH_28_.OE CLK_DIV_OUT.D CLK_DIV_OUT.C - AHIGH_27_ AHIGH_27_.OE AHIGH_26_ AHIGH_26_.OE FPU_CS- AHIGH_25_ AHIGH_25_.OE - AHIGH_24_ AHIGH_24_.OE DSACK1- DSACK1.OE AVEC E RESET RESET.OE AMIGA_ADDR_ENABLE - AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW- AMIGA_BUS_ENABLE_HIGH CIIN CIIN.OE - SIZE_1_.D SIZE_1_.C SIZE_1_.OE IPL_030_2_.D- IPL_030_2_.C RW_000.D- RW_000.C - RW_000.OE BG_000.D- BG_000.C BGACK_030.D BGACK_030.C SIZE_0_.D- SIZE_0_.C - SIZE_0_.OE CLK_EXP.D CLK_EXP.C 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000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000 +---1--------1--------------------0------0----------1---------------------0----------------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000 +---1--------1--------------------0------0--01------1------1--------------0----------------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 .end diff --git a/Logic/68030_tk.vcl b/Logic/68030_tk.vcl index 925addc..a5c1440 100644 --- a/Logic/68030_tk.vcl +++ b/Logic/68030_tk.vcl @@ -17,8 +17,8 @@ Parent = m4a5.lci; SDS_file = m4a5.sds; Design = 68030_tk.tt4; Rev = 0.01; -DATE = 10/6/16; -TIME = 22:04:16; +DATE = 10/15/16; +TIME = 23:48:29; Type = TT2; Pre_Fit_Time = 1; Source_Format = Pure_VHDL; @@ -123,7 +123,7 @@ Type = GLB; [HARDWARE DEVICE OPTIONS] Zero_Hold_Time = Yes; Signature_Word = 0; -Pull_up = Yes; +Pull_up = No; Out_Slew_Rate = SLOW, FAST, 57, CLK_DIV_OUT, CLK_EXP, FPU_CS, AMIGA_BUS_DATA_DIR, AMIGA_BUS_ENABLE_LOW, AMIGA_ADDR_ENABLE, AMIGA_BUS_ENABLE_HIGH, AS_030, A_16_, A_17_, A_18_, A_19_, RW, SIZE_1_, SIZE_0_, AVEC, BGACK_030, BG_000, E, IPL_030_0_, IPL_030_1_, @@ -142,15 +142,15 @@ layer = OFF; Layer = OFF AS_030 = OUTPUT,82,7,-; -AS_000 = OUTPUT,42,4,-; RW_000 = BIDIR,80,7,-; +AS_000 = OUTPUT,42,4,-; UDS_000 = OUTPUT,32,3,-; LDS_000 = OUTPUT,31,3,-; -A_0_ = BIDIR,69,6,-; RW = BIDIR,71,6,-; +BERR = OUTPUT,41,4,-; SIZE_1_ = BIDIR,79,7,-; SIZE_0_ = BIDIR,70,6,-; -BERR = OUTPUT,41,4,-; +A_0_ = BIDIR,69,6,-; AHIGH_24_ = OUTPUT,19,2,-; AHIGH_25_ = OUTPUT,18,2,-; AHIGH_26_ = OUTPUT,17,2,-; @@ -180,58 +180,57 @@ CLK_EXP = OUTPUT,10,1,-; RESET = OUTPUT,3,1,-; RN_BGACK_030 = NODE,-1,7,-; inst_RESET_OUT = NODE,*,6,-; -CLK_000_D_0_ = NODE,*,3,-; +CLK_000_D_0_ = NODE,*,2,-; CLK_000_D_1_ = NODE,*,7,-; -SM_AMIGA_6_ = NODE,*,5,-; -SM_AMIGA_0_ = NODE,*,0,-; -cpu_est_1_ = NODE,*,3,-; -cpu_est_3_ = NODE,*,0,-; -inst_BGACK_030_INT_D = NODE,*,0,-; -inst_AS_030_D0 = NODE,*,7,-; -cpu_est_2_ = NODE,*,3,-; -inst_DS_000_DMA = NODE,*,2,-; -inst_AS_000_DMA = NODE,*,2,-; +SM_AMIGA_6_ = NODE,*,2,-; +inst_BGACK_030_INT_D = NODE,*,4,-; inst_AS_030_000_SYNC = NODE,*,5,-; -RST_DLY_0_ = NODE,*,6,-; -SM_AMIGA_1_ = NODE,*,0,-; -CYCLE_DMA_1_ = NODE,*,3,-; +cpu_est_1_ = NODE,*,0,-; +cpu_est_3_ = NODE,*,3,-; +SM_AMIGA_i_7_ = NODE,*,2,-; +cpu_est_0_ = NODE,*,6,-; +inst_AS_030_D0 = NODE,*,4,-; +cpu_est_2_ = NODE,*,0,-; +inst_AS_000_DMA = NODE,*,0,-; +SM_AMIGA_2_ = NODE,*,0,-; +SM_AMIGA_3_ = NODE,*,3,-; RN_VMA = NODE,-1,3,-; -SM_AMIGA_i_7_ = NODE,*,5,-; -SM_AMIGA_5_ = NODE,*,1,-; -SM_AMIGA_4_ = NODE,*,0,-; -inst_LDS_000_INT = NODE,*,2,-; +SM_AMIGA_5_ = NODE,*,2,-; +SM_AMIGA_0_ = NODE,*,7,-; +SM_AMIGA_1_ = NODE,*,5,-; +SM_AMIGA_4_ = NODE,*,3,-; inst_DS_000_ENABLE = NODE,*,1,-; -CYCLE_DMA_0_ = NODE,*,3,-; -cpu_est_0_ = NODE,*,3,-; +inst_LDS_000_INT = NODE,*,5,-; inst_AS_000_INT = NODE,*,2,-; -inst_DSACK1_INT = NODE,*,5,-; -RST_DLY_2_ = NODE,*,6,-; -RST_DLY_1_ = NODE,*,1,-; inst_UDS_000_INT = NODE,*,5,-; -inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,*,6,-; -inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,*,6,-; -CLK_000_D_3_ = NODE,*,0,-; -inst_CLK_OUT_PRE_D = NODE,*,4,-; -CLK_000_D_4_ = NODE,*,0,-; -CLK_000_D_2_ = NODE,*,7,-; -inst_VPA_D = NODE,*,2,-; +inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,*,5,-; +inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,*,2,-; +inst_CLK_OUT_PRE_D = NODE,*,3,-; +inst_CLK_OUT_PRE_50 = NODE,*,6,-; +inst_DTACK_D0 = NODE,*,1,-; +CLK_000_D_3_ = NODE,*,3,-; +inst_VPA_D = NODE,*,0,-; RN_IPL_030_0_ = NODE,-1,1,-; RN_IPL_030_1_ = NODE,-1,1,-; RN_IPL_030_2_ = NODE,-1,1,-; -inst_CLK_030_H = NODE,*,2,-; -SM_AMIGA_2_ = NODE,*,0,-; -SM_AMIGA_3_ = NODE,*,0,-; +inst_DS_000_DMA = NODE,*,0,-; +inst_CLK_030_H = NODE,*,0,-; RN_RW_000 = NODE,-1,7,-; +RST_DLY_0_ = NODE,*,6,-; +CYCLE_DMA_1_ = NODE,*,0,-; RN_A_0_ = NODE,-1,6,-; RN_SIZE_0_ = NODE,-1,6,-; RN_SIZE_1_ = NODE,-1,7,-; +CYCLE_DMA_0_ = NODE,*,0,-; RN_RW = NODE,-1,6,-; RN_BG_000 = NODE,-1,3,-; CIIN_0 = NODE,*,4,-; -CLK_000_D_5_ = NODE,*,6,-; -IPL_D0_2_ = NODE,*,6,-; -IPL_D0_1_ = NODE,*,1,-; -IPL_D0_0_ = NODE,*,0,-; -inst_CLK_OUT_PRE_50 = NODE,*,4,-; -inst_DTACK_D0 = NODE,*,7,-; +inst_DSACK1_INT = NODE,*,7,-; +RST_DLY_2_ = NODE,*,6,-; +RST_DLY_1_ = NODE,*,6,-; +CLK_000_D_4_ = NODE,*,1,-; +CLK_000_D_2_ = NODE,*,7,-; +IPL_D0_2_ = NODE,*,1,-; +IPL_D0_1_ = NODE,*,3,-; +IPL_D0_0_ = NODE,*,6,-; CLK_OSZI = INPUT,61,-,-; diff --git a/Logic/68030_tk.vco b/Logic/68030_tk.vco index 0bc0969..5ad9750 100644 --- a/Logic/68030_tk.vco +++ b/Logic/68030_tk.vco @@ -17,8 +17,8 @@ Parent = m4a5.lci; SDS_file = m4a5.sds; Design = 68030_tk.tt4; Rev = 0.01; -DATE = 10/6/16; -TIME = 22:04:16; +DATE = 10/15/16; +TIME = 23:48:29; Type = TT2; Pre_Fit_Time = 1; Source_Format = Pure_VHDL; @@ -123,7 +123,7 @@ Type = GLB; [HARDWARE DEVICE OPTIONS] Zero_Hold_Time = Yes; Signature_Word = 0; -Pull_up = Yes; +Pull_up = No; Out_Slew_Rate = SLOW, FAST, 57, CLK_DIV_OUT, CLK_EXP, FPU_CS, AMIGA_BUS_DATA_DIR, AMIGA_BUS_ENABLE_LOW, AMIGA_ADDR_ENABLE, AMIGA_BUS_ENABLE_HIGH, AS_030, A_16_, A_17_, A_18_, A_19_, RW, SIZE_1_, SIZE_0_, AVEC, BGACK_030, BG_000, E, IPL_030_0_, IPL_030_1_, @@ -153,33 +153,33 @@ LDS_000 = BIDIR,31, D,-; nEXP_SPACE = INPUT,14,-,-; BERR = BIDIR,41, E,-; BG_030 = INPUT,21, C,-; -BGACK_000 = INPUT,28, D,-; -CLK_030 = INPUT,64,-,-; AHIGH_30_ = BIDIR,5, B,-; -CLK_000 = INPUT,11,-,-; +BGACK_000 = INPUT,28, D,-; AHIGH_29_ = BIDIR,6, B,-; -CLK_OSZI = INPUT,61,-,-; +CLK_030 = INPUT,64,-,-; AHIGH_28_ = BIDIR,15, C,-; -CLK_DIV_OUT = OUTPUT,65, G,-; +CLK_000 = INPUT,11,-,-; AHIGH_27_ = BIDIR,16, C,-; +CLK_OSZI = INPUT,61,-,-; AHIGH_26_ = BIDIR,17, C,-; -FPU_CS = OUTPUT,78, H,-; +CLK_DIV_OUT = OUTPUT,65, G,-; AHIGH_25_ = BIDIR,18, C,-; -FPU_SENSE = INPUT,91, A,-; AHIGH_24_ = BIDIR,19, C,-; -DSACK1 = OUTPUT,81, H,-; +FPU_CS = OUTPUT,78, H,-; A_DECODE_22_ = INPUT,84, H,-; -DTACK = INPUT,30, D,-; +FPU_SENSE = INPUT,91, A,-; A_DECODE_21_ = INPUT,94, A,-; -AVEC = OUTPUT,92, A,-; +DSACK1 = OUTPUT,81, H,-; A_DECODE_20_ = INPUT,93, A,-; -E = OUTPUT,66, G,-; +DTACK = INPUT,30, D,-; A_DECODE_19_ = INPUT,97, A,-; -VPA = INPUT,36,-,-; +AVEC = OUTPUT,92, A,-; A_DECODE_18_ = INPUT,95, A,-; +E = OUTPUT,66, G,-; A_DECODE_17_ = INPUT,59, F,-; -RST = INPUT,86,-,-; +VPA = INPUT,36,-,-; A_DECODE_16_ = INPUT,96, A,-; +RST = INPUT,86,-,-; RESET = OUTPUT,3, B,-; AMIGA_ADDR_ENABLE = OUTPUT,33, D,-; AMIGA_BUS_DATA_DIR = OUTPUT,48, E,-; @@ -194,56 +194,55 @@ SIZE_1_ = BIDIR,79, H,-; IPL_030_2_ = OUTPUT,9, B,-; RW_000 = BIDIR,80, H,-; BG_000 = OUTPUT,29, D,-; -BGACK_030 = OUTPUT,83, H,-; SIZE_0_ = BIDIR,70, G,-; +BGACK_030 = OUTPUT,83, H,-; CLK_EXP = OUTPUT,10, B,-; VMA = OUTPUT,35, D,-; RW = BIDIR,71, G,-; A_0_ = BIDIR,69, G,-; IPL_030_1_ = OUTPUT,7, B,-; IPL_030_0_ = OUTPUT,8, B,-; -cpu_est_2_ = NODE,2, D,-; -cpu_est_3_ = NODE,12, A,-; -cpu_est_0_ = NODE,14, D,-; -cpu_est_1_ = NODE,13, D,-; -inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,6, G,-; -inst_AS_030_D0 = NODE,13, H,-; -inst_AS_030_000_SYNC = NODE,4, F,-; -inst_BGACK_030_INT_D = NODE,1, A,-; -inst_AS_000_DMA = NODE,13, C,-; -inst_DS_000_DMA = NODE,9, C,-; -CYCLE_DMA_0_ = NODE,10, D,-; -CYCLE_DMA_1_ = NODE,6, D,-; -inst_VPA_D = NODE,10, C,-; -CLK_000_D_2_ = NODE,2, H,-; -CLK_000_D_4_ = NODE,2, A,-; -inst_DTACK_D0 = NODE,6, H,-; +cpu_est_2_ = NODE,12, A,-; +cpu_est_3_ = NODE,9, D,-; +cpu_est_0_ = NODE,9, G,-; +cpu_est_1_ = NODE,8, A,-; +inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,14, C,-; +inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,1, F,-; +inst_AS_030_D0 = NODE,5, E,-; +inst_AS_030_000_SYNC = NODE,0, F,-; +inst_BGACK_030_INT_D = NODE,8, E,-; +inst_AS_000_DMA = NODE,1, A,-; +inst_DS_000_DMA = NODE,13, A,-; +CYCLE_DMA_0_ = NODE,10, A,-; +CYCLE_DMA_1_ = NODE,6, A,-; +inst_VPA_D = NODE,9, A,-; +CLK_000_D_3_ = NODE,10, D,-; +inst_DTACK_D0 = NODE,6, B,-; inst_RESET_OUT = NODE,5, G,-; CLK_000_D_1_ = NODE,5, H,-; -CLK_000_D_0_ = NODE,9, D,-; -inst_CLK_OUT_PRE_50 = NODE,9, E,-; -inst_CLK_OUT_PRE_D = NODE,8, E,-; -IPL_D0_0_ = NODE,14, A,-; -IPL_D0_1_ = NODE,14, B,-; -IPL_D0_2_ = NODE,14, G,-; -CLK_000_D_3_ = NODE,13, A,-; -CLK_000_D_5_ = NODE,10, G,-; -inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,2, G,-; -SM_AMIGA_1_ = NODE,5, A,-; -inst_UDS_000_INT = NODE,1, F,-; -inst_DS_000_ENABLE = NODE,6, B,-; -inst_LDS_000_INT = NODE,2, C,-; -SM_AMIGA_6_ = NODE,0, F,-; -SM_AMIGA_4_ = NODE,9, A,-; -SM_AMIGA_0_ = NODE,8, A,-; -RST_DLY_0_ = NODE,9, G,-; -RST_DLY_1_ = NODE,10, B,-; -RST_DLY_2_ = NODE,13, G,-; -inst_CLK_030_H = NODE,14, C,-; -inst_DSACK1_INT = NODE,12, F,-; -inst_AS_000_INT = NODE,6, C,-; -SM_AMIGA_5_ = NODE,13, B,-; -SM_AMIGA_3_ = NODE,10, A,-; -SM_AMIGA_2_ = NODE,6, A,-; -SM_AMIGA_i_7_ = NODE,8, F,-; -CIIN_0 = NODE,5, E,-; +CLK_000_D_0_ = NODE,9, C,-; +inst_CLK_OUT_PRE_50 = NODE,13, G,-; +inst_CLK_OUT_PRE_D = NODE,6, D,-; +IPL_D0_0_ = NODE,14, G,-; +IPL_D0_1_ = NODE,14, D,-; +IPL_D0_2_ = NODE,14, B,-; +CLK_000_D_2_ = NODE,6, H,-; +CLK_000_D_4_ = NODE,10, B,-; +inst_LDS_000_INT = NODE,8, F,-; +inst_DS_000_ENABLE = NODE,13, B,-; +inst_UDS_000_INT = NODE,12, F,-; +SM_AMIGA_6_ = NODE,13, C,-; +SM_AMIGA_4_ = NODE,2, D,-; +SM_AMIGA_1_ = NODE,4, F,-; +SM_AMIGA_0_ = NODE,13, H,-; +RST_DLY_0_ = NODE,2, G,-; +RST_DLY_1_ = NODE,10, G,-; +RST_DLY_2_ = NODE,6, G,-; +inst_CLK_030_H = NODE,2, A,-; +inst_DSACK1_INT = NODE,2, H,-; +inst_AS_000_INT = NODE,10, C,-; +SM_AMIGA_5_ = NODE,6, C,-; +SM_AMIGA_3_ = NODE,13, D,-; +SM_AMIGA_2_ = NODE,5, A,-; +SM_AMIGA_i_7_ = NODE,2, C,-; +CIIN_0 = NODE,9, E,-; diff --git a/Logic/68030_tk.vct b/Logic/68030_tk.vct index 8382c5f..6b2c2e2 100644 --- a/Logic/68030_tk.vct +++ b/Logic/68030_tk.vct @@ -15,8 +15,8 @@ Voltage = 5.0; RCS = "$Revision: 1.2 $"; Parent = m4a5.lci; SDS_File = m4a5.sds; -DATE = 08/23/2016; -TIME = 20:07:14; +DATE = 10/08/2016; +TIME = 22:26:00; Source_Format = Pure_VHDL; Type = TT2; Pre_Fit_Time = 1; @@ -103,7 +103,7 @@ Conf_Unused_IOs = Out_Low; [HARDWARE DEVICE OPTIONS] Zero_Hold_Time = Yes; Signature_Word = 0; -Pull_up = Yes; +Pull_up = No; Out_Slew_Rate = SLOW,FAST,57,CLK_DIV_OUT,CLK_EXP,FPU_CS,AMIGA_BUS_DATA_DIR,AMIGA_BUS_ENABLE_LOW,AMIGA_ADDR_ENABLE,AMIGA_BUS_ENABLE_HIGH,AS_030,A_16_,A_17_,A_18_,A_19_,RW,SIZE_1_,SIZE_0_,AVEC,BGACK_030,BG_000,E,IPL_030_0_,IPL_030_1_,IPL_030_2_,LDS_000,UDS_000,VMA,RESET,CIIN,A_20_,A_21_,A_22_,A_24_,A_25_,A_26_,A_27_,A_28_,A_29_,A_30_,A_31_,DS_030,BERR,A0,DSACK1,RW_000,AS_000,A_23_,A1,A_3_,A_2_,AHIGH_24_,AHIGH_25_,AHIGH_26_,AHIGH_27_,AHIGH_28_,AHIGH_29_,AHIGH_30_,AHIGH_31_,A_0_; Device_max_fanin = 33; Device_max_pterms = 20; diff --git a/Logic/68030_tk.xrf b/Logic/68030_tk.xrf index 017e754..b64ac76 100644 --- a/Logic/68030_tk.xrf +++ b/Logic/68030_tk.xrf @@ -2,7 +2,7 @@ Signal Name Cross Reference File ispLEVER Classic 2.0.00.17.20.15 -Design '68030_tk' created Thu Oct 06 22:04:11 2016 +Design '68030_tk' created Sat Oct 15 23:48:24 2016 LEGEND: '>' Functional Block Port Separator diff --git a/Logic/BUS68030.bl0 b/Logic/BUS68030.bl0 index e8177c6..f897da8 100644 --- a/Logic/BUS68030.bl0 +++ b/Logic/BUS68030.bl0 @@ -1,214 +1,213 @@ -#$ DATE Thu Oct 06 22:04:11 2016 +#$ DATE Sat Oct 15 23:48:24 2016 #$ TOOL EDIF2BLIF version IspLever 1.0 #$ MODULE bus68030 -#$ PINS 75 SIZE_1_ AHIGH_31_ A_DECODE_23_ IPL_030_2_ IPL_2_ FC_1_ AS_030 AS_000 RW_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 SIZE_0_ CLK_030 AHIGH_30_ CLK_000 AHIGH_29_ CLK_OSZI AHIGH_28_ CLK_DIV_OUT AHIGH_27_ CLK_EXP AHIGH_26_ FPU_CS AHIGH_25_ FPU_SENSE AHIGH_24_ DSACK1 A_DECODE_22_ DTACK A_DECODE_21_ AVEC A_DECODE_20_ E A_DECODE_19_ VPA A_DECODE_18_ VMA A_DECODE_17_ RST A_DECODE_16_ RESET A_DECODE_15_ RW A_DECODE_14_ AMIGA_ADDR_ENABLE A_DECODE_13_ AMIGA_BUS_DATA_DIR A_DECODE_12_ AMIGA_BUS_ENABLE_LOW A_DECODE_11_ AMIGA_BUS_ENABLE_HIGH A_DECODE_10_ CIIN A_DECODE_9_ A_DECODE_8_ A_DECODE_7_ A_DECODE_6_ A_DECODE_5_ A_DECODE_4_ A_DECODE_3_ A_DECODE_2_ A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ IPL_0_ FC_0_ A_1_ -#$ NODES 600 rst_dly_i_1__n N_41_0 sm_amiga_i_5__n a_c_i_0__n rst_dly_i_0__n size_c_i_1__n sm_amiga_i_i_7__n pos_clk_un10_sm_amiga_i_n AS_030_D0_i un1_as_000_i \ -# AS_000_INT_i un10_ciin_i a_i_1__n N_260_0 a_decode_i_16__n N_229_i inst_BGACK_030_INTreg a_decode_i_18__n N_230_i vcc_n_n \ -# a_decode_i_19__n N_298_0 inst_VMA_INTreg ahigh_i_30__n N_48_0 gnd_n_n ahigh_i_31__n N_299_i un1_amiga_bus_enable_low ahigh_i_28__n \ -# N_345_i un7_as_030 ahigh_i_29__n N_349_i un1_UDS_000_INT ahigh_i_26__n un1_DS_000_ENABLE_0_sqmuxa_i un1_LDS_000_INT ahigh_i_27__n N_180_i \ -# un1_SM_AMIGA_0_sqmuxa_1 ahigh_i_24__n N_181_i un10_ciin ahigh_i_25__n N_326_i un21_fpu_cs N_206_i un21_berr N_207_i \ -# N_186_i un6_ds_030 N_208_i N_163_i cpu_est_2_ N_197_0 cpu_est_3_ N_79_i N_213_i cpu_est_0_ \ -# N_78_i N_214_i cpu_est_1_ un6_ds_030_i N_215_i inst_AMIGA_BUS_ENABLE_DMA_LOW N_165_i inst_AS_030_D0 N_169_i N_199_i \ -# inst_AS_030_000_SYNC un7_as_030_i N_191_0 inst_BGACK_030_INT_D AMIGA_BUS_ENABLE_DMA_LOW_i N_275_i inst_AS_000_DMA AS_030_c N_187_0 inst_DS_000_DMA \ -# LDS_000_c_i CYCLE_DMA_0_ AS_000_c UDS_000_c_i CYCLE_DMA_1_ N_184_i inst_VPA_D RW_000_c clk_000_d_i_4__n CLK_000_D_2_ \ -# N_171_i CLK_000_D_4_ AS_030_000_SYNC_i inst_DTACK_D0 UDS_000_c N_161_i inst_RESET_OUT CLK_000_D_1_ LDS_000_c N_113_0 \ -# CLK_000_D_0_ N_338_i inst_CLK_OUT_PRE_50 size_c_0__n N_339_i inst_CLK_OUT_PRE_D IPL_D0_0_ size_c_1__n N_335_i IPL_D0_1_ \ -# N_336_i IPL_D0_2_ ahigh_c_24__n CLK_000_D_3_ N_334_i CLK_000_D_5_ ahigh_c_25__n pos_clk_size_dma_6_0_1__n pos_clk_un6_bg_030_n N_333_i \ -# inst_AMIGA_BUS_ENABLE_DMA_HIGH ahigh_c_26__n pos_clk_size_dma_6_0_0__n pos_clk_ipl_n N_295_i SM_AMIGA_1_ ahigh_c_27__n N_332_i inst_UDS_000_INT inst_DS_000_ENABLE \ -# ahigh_c_28__n N_292_i inst_LDS_000_INT N_302_0 pos_clk_un9_bg_030_n ahigh_c_29__n N_300_0 SM_AMIGA_6_ N_290_i SM_AMIGA_4_ \ -# ahigh_c_30__n SM_AMIGA_0_ N_273_i SIZE_DMA_0_ ahigh_c_31__n SIZE_DMA_1_ N_327_i inst_RW_000_INT inst_RW_000_DMA N_270_i \ -# RST_DLY_0_ RST_DLY_1_ N_269_i RST_DLY_2_ inst_A0_DMA N_267_i pos_clk_a0_dma_3_n N_324_i inst_CLK_030_H pos_clk_rw_000_int_5_n \ -# un1_SM_AMIGA_0_sqmuxa_1_0 inst_DSACK1_INT N_319_i inst_AS_000_INT N_320_i SM_AMIGA_5_ SM_AMIGA_3_ RW_c_i SM_AMIGA_2_ pos_clk_rw_000_int_5_0_n \ -# N_227_i N_297_0 N_15_i N_40_0 N_16_i N_15 N_39_0 N_16 N_19_i N_19 \ -# N_36_0 N_20 N_20_i N_22 N_35_0 N_23 N_22_i N_24 N_33_0 N_23_i \ -# N_32_0 a_decode_c_16__n N_24_i N_31_0 a_decode_c_17__n BG_030_c_i pos_clk_un6_bg_030_i_n a_decode_c_18__n pos_clk_un9_bg_030_0_n N_161_i_1 \ -# a_decode_c_19__n N_161_i_2 N_161_i_3 a_decode_c_20__n N_161_i_4 N_233_i_1 a_decode_c_21__n N_233_i_2 N_180_i_1 a_decode_c_22__n \ -# N_180_i_2 pos_clk_un10_sm_amiga_i_1_n a_decode_c_23__n N_196_0_1 N_188_i_1 a_c_0__n un10_ciin_1 un10_ciin_2 a_c_1__n un10_ciin_3 \ -# un10_ciin_4 nEXP_SPACE_c un10_ciin_5 SM_AMIGA_i_7_ un10_ciin_6 pos_clk_size_dma_6_0__n BERR_c un10_ciin_7 pos_clk_size_dma_6_1__n un10_ciin_8 \ -# G_107 BG_030_c un10_ciin_9 G_108 un10_ciin_10 G_109 BG_000DFFreg un10_ciin_11 N_171_i_1 N_78 \ -# N_171_i_2 N_79 BGACK_000_c N_227_1 N_260 N_227_2 N_139 CLK_030_c N_227_3 N_141 \ -# un21_fpu_cs_1 N_165 un21_berr_1_0 N_169 N_235_i_1 N_297 CLK_OSZI_c N_235_i_2 N_256_1 N_300 \ -# N_256_2 N_302 CLK_OUT_INTreg N_232_i_1 N_113 N_232_i_2 N_305 N_219_1 N_155 FPU_SENSE_c \ -# N_219_2 N_163 N_218_1 N_166 IPL_030DFF_0_reg N_218_2 N_171 N_347_1 N_180 IPL_030DFF_1_reg \ -# N_347_2 N_184 N_136_i_1 N_191 IPL_030DFF_2_reg N_146_i_1 N_199 N_142_i_1 N_205 ipl_c_0__n \ -# N_234_i_1 N_306 N_302_0_1 N_215 ipl_c_1__n N_63_i_1 N_221 N_154_i_1 N_227 ipl_c_2__n \ -# N_152_i_1 N_230 N_148_i_1 N_319 N_144_i_1 N_320 DTACK_c N_140_i_1 N_267 pos_clk_un6_bg_030_1_n \ -# N_324 N_230_1 N_269 N_221_1 N_270 VPA_c N_215_1 N_327 N_306_1 N_273 \ -# pos_clk_ipl_1_n N_275 RST_c ipl_030_0_2__un3_n N_290 ipl_030_0_2__un1_n N_292 ipl_030_0_2__un0_n N_295 RW_c \ -# ipl_030_0_1__un3_n N_332 ipl_030_0_1__un1_n N_333 fc_c_0__n ipl_030_0_1__un0_n N_334 ipl_030_0_0__un3_n N_335 fc_c_1__n \ -# ipl_030_0_0__un1_n N_336 ipl_030_0_0__un0_n N_338 cpu_est_0_3__un3_n N_339 AMIGA_BUS_DATA_DIR_c cpu_est_0_3__un1_n N_350 cpu_est_0_3__un0_n \ -# pos_clk_CYCLE_DMA_5_1_i_x2 vma_int_0_un3_n N_161 vma_int_0_un1_n N_213 vma_int_0_un0_n N_214 VPA_c_i cpu_est_0_1__un3_n N_197 \ -# N_52_0 cpu_est_0_1__un1_n N_159 DTACK_c_i cpu_est_0_1__un0_n N_326 N_53_0 cpu_est_0_2__un3_n un21_berr_1 ipl_c_i_0__n \ -# cpu_est_0_2__un1_n N_181 N_49_0 cpu_est_0_2__un0_n pos_clk_un21_bgack_030_int_i_i_a2_i_x2 ipl_c_i_1__n ds_000_dma_0_un3_n un1_DS_000_ENABLE_0_sqmuxa N_50_0 ds_000_dma_0_un1_n \ -# N_349 ipl_c_i_2__n ds_000_dma_0_un0_n N_345 N_51_0 as_000_dma_0_un3_n N_229 N_25_i as_000_dma_0_un1_n N_14 \ -# N_28_0 as_000_dma_0_un0_n N_21 N_26_i bgack_030_int_0_un3_n N_3 N_29_0 bgack_030_int_0_un1_n N_301 N_27_i \ -# bgack_030_int_0_un0_n N_4 N_30_0 ds_000_enable_0_un3_n N_303 N_222_i ds_000_enable_0_un1_n N_8 N_223_i ds_000_enable_0_un0_n \ -# pos_clk_un6_bgack_000_n N_192_i uds_000_int_0_un3_n N_9 N_231_i uds_000_int_0_un1_n N_65 N_237_i uds_000_int_0_un0_n N_217 \ -# lds_000_int_0_un3_n N_216 N_342_i lds_000_int_0_un1_n N_248 N_341_i lds_000_int_0_un0_n N_198 un1_amiga_bus_enable_dma_high_i_m2_0__un3_n N_291 \ -# N_160_0 un1_amiga_bus_enable_dma_high_i_m2_0__un1_n N_353 N_164_i un1_amiga_bus_enable_dma_high_i_m2_0__un0_n N_256 VMA_INT_i amiga_bus_enable_dma_high_0_un3_n N_18 N_347_i \ -# amiga_bus_enable_dma_high_0_un1_n pos_clk_un9_clk_000_pe_n N_348_i amiga_bus_enable_dma_high_0_un0_n cpu_est_2_1__n N_188_i bg_000_0_un3_n cpu_est_2_2__n N_245_0 bg_000_0_un1_n \ -# N_209 N_194_0 bg_000_0_un0_n N_211 N_196_0 size_dma_0_0__un3_n N_220 size_dma_0_0__un1_n N_222 N_211_i \ -# size_dma_0_0__un0_n N_162 N_209_i size_dma_0_1__un3_n N_224 N_306_i size_dma_0_1__un1_n N_193 N_193_0 size_dma_0_1__un0_n \ -# N_225 N_190_0 as_030_000_sync_0_un3_n N_190 N_183_i as_030_000_sync_0_un1_n N_346 N_162_i as_030_000_sync_0_un0_n N_352 \ -# N_346_i rw_000_int_0_un3_n N_219 N_159_0 rw_000_int_0_un1_n N_218 N_305_i rw_000_int_0_un0_n N_183 N_210_i \ -# rw_000_dma_0_un3_n N_196 N_225_i rw_000_dma_0_un1_n N_188 N_224_i rw_000_dma_0_un0_n N_194 N_296_i a0_dma_0_un3_n \ -# N_347 N_352_i a0_dma_0_un1_n N_348 cpu_est_2_0_2__n a0_dma_0_un0_n N_160 N_220_i amiga_bus_enable_dma_low_0_un3_n N_341 \ -# N_221_i amiga_bus_enable_dma_low_0_un1_n N_342 cpu_est_2_0_1__n amiga_bus_enable_dma_low_0_un0_n N_231 N_219_i a_decode_15__n N_237 N_218_i \ -# N_223 pos_clk_un9_clk_000_pe_0_n a_decode_14__n N_27 clk_000_d_i_2__n N_26 N_157_i a_decode_13__n N_25 N_18_i \ -# un1_amiga_bus_enable_low_i N_37_0 a_decode_12__n un21_fpu_cs_i cpu_est_i_2__n N_217_i a_decode_11__n sm_amiga_i_0__n N_216_i sm_amiga_i_2__n \ -# CLK_030_c_i a_decode_10__n sm_amiga_i_1__n N_198_0 cpu_est_i_0__n N_166_i a_decode_9__n VPA_D_i N_155_i DTACK_D0_i \ -# N_303_0 a_decode_8__n AS_030_i N_291_i DSACK1_INT_i N_301_0 a_decode_7__n cpu_est_i_3__n N_256_i sm_amiga_i_3__n \ -# N_248_i a_decode_6__n cpu_est_i_1__n AMIGA_BUS_DATA_DIR_c_0 clk_000_d_i_1__n N_353_i a_decode_5__n N_350_i_0 pos_clk_un6_bgack_000_0_n rst_dly_i_2__n \ -# N_65_0 a_decode_4__n nEXP_SPACE_i N_3_i AS_000_i N_45_0 a_decode_3__n BGACK_030_INT_i N_4_i sm_amiga_i_6__n \ -# N_44_0 a_decode_2__n clk_000_d_i_0__n N_8_i RW_000_i N_42_0 CLK_030_H_i UDS_000_INT_i AS_000_DMA_i un1_UDS_000_INT_0 \ -# cycle_dma_i_0__n LDS_000_INT_i DS_000_DMA_i un1_LDS_000_INT_0 RESET_OUT_i N_21_i sm_amiga_i_4__n N_34_0 FPU_SENSE_i N_14_i \ -# +#$ PINS 75 SIZE_1_ AHIGH_31_ A_DECODE_23_ IPL_030_2_ IPL_2_ FC_1_ AS_030 AS_000 RW_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BG_000 SIZE_0_ BGACK_030 AHIGH_30_ BGACK_000 AHIGH_29_ CLK_030 AHIGH_28_ CLK_000 AHIGH_27_ CLK_OSZI AHIGH_26_ CLK_DIV_OUT AHIGH_25_ CLK_EXP AHIGH_24_ FPU_CS A_DECODE_22_ FPU_SENSE A_DECODE_21_ DSACK1 A_DECODE_20_ DTACK A_DECODE_19_ AVEC A_DECODE_18_ E A_DECODE_17_ VPA A_DECODE_16_ VMA A_DECODE_15_ RST A_DECODE_14_ RESET A_DECODE_13_ RW A_DECODE_12_ AMIGA_ADDR_ENABLE A_DECODE_11_ AMIGA_BUS_DATA_DIR A_DECODE_10_ AMIGA_BUS_ENABLE_LOW A_DECODE_9_ AMIGA_BUS_ENABLE_HIGH A_DECODE_8_ CIIN A_DECODE_7_ A_DECODE_6_ A_DECODE_5_ A_DECODE_4_ A_DECODE_3_ A_DECODE_2_ A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ IPL_0_ FC_0_ A_1_ +#$ NODES 598 ipl_i_2__n N_233_0 ipl_i_1__n N_360_i ipl_i_0__n N_191_i_i a_i_1__n N_192_i_i AS_000_DMA_i AS_000_i \ +# N_199_i CLK_030_H_i N_204_i AS_030_000_SYNC_i inst_BGACK_030_INTreg AMIGA_BUS_ENABLE_DMA_HIGH_i N_282_i vcc_n_n cycle_dma_i_0__n N_278_i \ +# inst_VMA_INTreg ahigh_i_30__n N_186_i gnd_n_n ahigh_i_31__n N_185_i un1_amiga_bus_enable_low ahigh_i_28__n CLK_030_c_i un7_as_030 \ +# ahigh_i_29__n N_184_0 un1_LDS_000_INT ahigh_i_26__n N_179_0 un1_UDS_000_INT ahigh_i_27__n N_251_i un10_ciin ahigh_i_24__n \ +# LDS_000_c_i un21_fpu_cs ahigh_i_25__n UDS_000_c_i un21_berr N_172_i un6_ds_030 pos_clk_un21_bgack_030_int_i_0_0_n cpu_est_2_ N_163_i \ +# cpu_est_3_ clk_000_d_i_3__n cpu_est_0_ N_115_i N_350_i cpu_est_1_ N_114_i un1_rw_i inst_AMIGA_BUS_ENABLE_DMA_HIGH un6_ds_030_i \ +# N_126_0 inst_AMIGA_BUS_ENABLE_DMA_LOW DS_000_DMA_i N_313_i inst_AS_030_D0 N_132_i N_231_i inst_AS_030_000_SYNC N_133_i N_291_i \ +# inst_BGACK_030_INT_D un7_as_030_i inst_AS_000_DMA AMIGA_BUS_ENABLE_DMA_LOW_i N_288_i inst_DS_000_DMA AS_030_c CYCLE_DMA_0_ N_287_i CYCLE_DMA_1_ \ +# AS_000_c N_340_i inst_VPA_D CLK_000_D_3_ RW_000_c N_284_i inst_DTACK_D0 inst_RESET_OUT N_275_i CLK_000_D_1_ \ +# UDS_000_c pos_clk_size_dma_6_0_1__n CLK_000_D_0_ N_268_i inst_CLK_OUT_PRE_50 LDS_000_c pos_clk_size_dma_6_0_0__n inst_CLK_OUT_PRE_D N_265_i IPL_D0_0_ \ +# size_c_0__n N_267_i IPL_D0_1_ IPL_D0_2_ size_c_1__n N_337_i CLK_000_D_2_ N_338_i CLK_000_D_4_ ahigh_c_24__n \ +# N_55_0 inst_LDS_000_INT un1_as_000_i inst_DS_000_ENABLE ahigh_c_25__n N_245_0 inst_UDS_000_INT N_229_i pos_clk_un9_bg_030_n ahigh_c_26__n \ +# SM_AMIGA_6_ N_227_i SM_AMIGA_4_ ahigh_c_27__n SM_AMIGA_1_ N_226_i SM_AMIGA_0_ ahigh_c_28__n N_246_0 SIZE_DMA_0_ \ +# N_332_i SIZE_DMA_1_ ahigh_c_29__n pos_clk_ds_000_dma_4_0_n inst_RW_000_INT N_48_0 inst_RW_000_DMA ahigh_c_30__n pos_clk_rw_000_dma_3_0_n RST_DLY_0_ \ +# N_218_i RST_DLY_1_ ahigh_c_31__n RST_DLY_2_ inst_A0_DMA un10_ciin_i pos_clk_a0_dma_3_n N_62_0 pos_clk_rw_000_dma_3_n N_215_i \ +# inst_CLK_030_H N_216_i inst_DSACK1_INT un10_amiga_bus_enable_high_i inst_AS_000_INT N_214_i SM_AMIGA_5_ N_310_0 SM_AMIGA_3_ N_24_i \ +# SM_AMIGA_2_ N_33_0 pos_clk_ds_000_dma_4_n N_23_i N_3 N_32_0 N_4 N_22_i N_31_0 N_3_i \ +# N_45_0 N_4_i N_44_0 N_15 N_15_i N_19 N_40_0 N_20 N_19_i N_22 \ +# N_36_0 N_23 N_20_i N_24 N_35_0 N_25 N_25_i N_26 N_30_0 N_27 \ +# N_26_i N_29_0 N_27_i a_decode_c_16__n N_28_0 BG_030_c_i a_decode_c_17__n pos_clk_un9_bg_030_0_n N_235_i_1 a_decode_c_18__n \ +# N_235_i_2 N_156_i_1 a_decode_c_19__n N_156_i_2 N_156_i_3 a_decode_c_20__n N_156_i_4 pos_clk_un10_sm_amiga_i_1_n a_decode_c_21__n N_176_i_1 \ +# un10_ciin_1 a_decode_c_22__n un10_ciin_2 un10_ciin_3 a_decode_c_23__n un10_ciin_4 un10_ciin_5 a_c_0__n un10_ciin_6 un10_ciin_7 \ +# a_c_1__n un10_ciin_8 SM_AMIGA_i_7_ un10_ciin_9 pos_clk_size_dma_6_0__n nEXP_SPACE_c un10_ciin_10 pos_clk_size_dma_6_1__n un10_ciin_11 N_199 \ +# BERR_c N_163_i_1 pos_clk_un21_bgack_030_int_i_0_n N_163_i_2 N_231 BG_030_c pos_clk_un21_bgack_030_int_i_0_0_1_n N_233 pos_clk_un21_bgack_030_int_i_0_0_2_n N_111 \ +# BG_000DFFreg N_138_i_1 N_112 N_138_i_2 N_113 N_59_i_1 N_114 BGACK_000_c N_59_i_2 N_115 \ +# N_233_0_1 N_245 CLK_030_c N_233_0_2 N_246 N_214_1 N_62 N_214_2 N_214_3 N_132 \ +# CLK_OSZI_c un21_fpu_cs_1 N_133 un21_berr_1_0 N_310 N_182_0_1 N_126 CLK_OUT_INTreg N_234_i_1 N_149 \ +# N_234_i_2 N_150 N_206_1 N_158 FPU_SENSE_c N_206_2 N_160 N_205_1 N_163 IPL_030DFF_0_reg \ +# N_205_2 N_172 N_352_1 N_179 IPL_030DFF_1_reg N_352_2 N_184 N_231_i_1 N_185 IPL_030DFF_2_reg \ +# N_152_i_1 N_196 N_144_i_1 N_203 ipl_c_0__n N_142_i_1 N_204 N_312_i_1 N_209 ipl_c_1__n \ +# N_236_i_1 N_214 N_148_i_1 N_215 ipl_c_2__n N_136_i_1 N_216 N_246_0_1 N_218 N_249_i_1 \ +# N_224 DTACK_c N_57_i_1 N_332 N_338_1 N_226 N_224_1 N_227 N_216_1 N_229 \ +# VPA_c N_209_1 N_337 N_203_1 N_338 N_196_1 N_265 RST_c cpu_est_0_3__un3_n N_267 \ +# cpu_est_0_3__un1_n N_268 cpu_est_0_3__un0_n N_275 RW_c rw_000_int_0_un3_n N_278 rw_000_int_0_un1_n N_282 fc_c_0__n \ +# rw_000_int_0_un0_n N_284 vma_int_0_un3_n N_340 fc_c_1__n vma_int_0_un1_n N_287 vma_int_0_un0_n N_288 cpu_est_0_1__un3_n \ +# N_291 AMIGA_BUS_DATA_DIR_c cpu_est_0_1__un1_n N_293 cpu_est_0_1__un0_n N_350 cpu_est_0_2__un3_n N_355 cpu_est_0_2__un1_n pos_clk_un21_bgack_030_int_i_0_o3_0_x2 \ +# cpu_est_0_2__un0_n pos_clk_un1_ipl_i_0_x2 N_16_i uds_000_int_0_un3_n pos_clk_un1_ipl_i_0_x2_0 N_39_0 uds_000_int_0_un1_n pos_clk_un1_ipl_i_0_x2_1 VPA_c_i uds_000_int_0_un0_n \ +# pos_clk_CYCLE_DMA_5_1_i_0_x2 N_52_0 lds_000_int_0_un3_n N_156 DTACK_c_i lds_000_int_0_un1_n N_201 N_53_0 lds_000_int_0_un0_n N_202 \ +# N_210_i bgack_030_int_0_un3_n N_154 N_211_i bgack_030_int_0_un1_n un21_berr_1 N_189_i bgack_030_int_0_un0_n N_174 un1_SM_AMIGA_0_sqmuxa_1_0 \ +# ds_000_enable_0_un3_n N_223 RW_c_i ds_000_enable_0_un1_n N_221 N_311_0 ds_000_enable_0_un0_n N_222 N_336_i size_dma_0_0__un3_n \ +# N_219 N_244_i size_dma_0_0__un1_n N_220 size_dma_0_0__un0_n pos_clk_un6_bgack_000_n N_314_0 size_dma_0_1__un3_n N_359 N_159_i \ +# size_dma_0_1__un1_n N_8 VMA_INT_i size_dma_0_1__un0_n N_14 N_352_i ipl_030_0_0__un3_n N_21 N_353_i ipl_030_0_0__un1_n \ +# N_9 N_293_i ipl_030_0_0__un0_n un1_DS_000_ENABLE_0_sqmuxa N_175_i ipl_030_0_1__un3_n N_66 N_176_i ipl_030_0_1__un1_n N_171 \ +# ipl_030_0_1__un0_n N_354 N_198_i ipl_030_0_2__un3_n N_18 N_197_i ipl_030_0_2__un1_n pos_clk_un9_clk_000_pe_n N_196_i ipl_030_0_2__un0_n \ +# cpu_est_2_1__n N_183_0 a0_dma_0_un3_n cpu_est_2_2__n N_182_0 a0_dma_0_un1_n N_197 N_180_0 a0_dma_0_un0_n N_198 \ +# N_178_0 amiga_bus_enable_dma_low_0_un3_n N_208 N_82_i amiga_bus_enable_dma_low_0_un1_n N_210 N_315_i amiga_bus_enable_dma_low_0_un0_n N_315 N_351_i \ +# amiga_bus_enable_dma_high_0_un3_n N_212 N_154_0 amiga_bus_enable_dma_high_0_un1_n N_180 N_149_i amiga_bus_enable_dma_high_0_un0_n N_213 N_207_i bg_000_0_un3_n \ +# N_178 N_228_i bg_000_0_un1_n N_228 bg_000_0_un0_n N_182 N_213_i ds_000_dma_0_un3_n N_176 N_212_i \ +# ds_000_dma_0_un1_n N_183 N_309_i ds_000_dma_0_un0_n N_351 N_357_i as_000_dma_0_un3_n N_357 cpu_est_2_0_2__n as_000_dma_0_un1_n \ +# N_206 N_208_i as_000_dma_0_un0_n N_205 N_209_i as_030_000_sync_0_un3_n N_352 cpu_est_2_0_1__n as_030_000_sync_0_un1_n N_353 \ +# N_206_i as_030_000_sync_0_un0_n N_314 N_205_i rw_000_dma_0_un3_n N_244 pos_clk_un9_clk_000_pe_0_n rw_000_dma_0_un1_n N_336 N_18_i \ +# rw_000_dma_0_un0_n N_311 N_37_0 a_decode_15__n un1_SM_AMIGA_0_sqmuxa_1 N_171_i N_211 N_354_i a_decode_14__n N_16 \ +# un1_DS_000_ENABLE_0_sqmuxa_0 un1_amiga_bus_enable_low_i N_66_0 a_decode_13__n un21_fpu_cs_i UDS_000_INT_i cpu_est_i_2__n un1_UDS_000_INT_0 a_decode_12__n cpu_est_i_0__n \ +# LDS_000_INT_i VPA_D_i un1_LDS_000_INT_0 a_decode_11__n DTACK_D0_i N_21_i cpu_est_i_3__n N_34_0 a_decode_10__n sm_amiga_i_i_7__n \ +# N_14_i sm_amiga_i_5__n N_41_0 a_decode_9__n sm_amiga_i_3__n N_8_i cpu_est_i_1__n N_42_0 a_decode_8__n clk_000_d_i_1__n \ +# a_c_i_0__n N_355_i_0 size_c_i_1__n a_decode_7__n sm_amiga_i_4__n pos_clk_un10_sm_amiga_i_n sm_amiga_i_2__n N_359_i a_decode_6__n rst_dly_i_0__n \ +# pos_clk_un6_bgack_000_0_n rst_dly_i_2__n N_220_i a_decode_5__n a_decode_i_19__n N_219_i a_decode_i_18__n a_decode_4__n a_decode_i_16__n N_222_i \ +# RW_000_i N_221_i a_decode_3__n sm_amiga_i_0__n AS_030_i N_223_i a_decode_2__n AS_000_INT_i N_224_i DSACK1_INT_i \ +# AMIGA_BUS_DATA_DIR_c_0 clk_000_d_i_0__n N_150_i sm_amiga_i_6__n N_156_i sm_amiga_i_1__n N_160_i FPU_SENSE_i N_174_i rst_dly_i_1__n \ +# N_158_i AS_030_D0_i N_201_i BGACK_030_INT_i N_202_i nEXP_SPACE_i N_203_i RESET_OUT_i .model bus68030 .inputs A_DECODE_23_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF \ FPU_SENSE.BLIF DTACK.BLIF VPA.BLIF RST.BLIF A_DECODE_22_.BLIF A_DECODE_21_.BLIF A_DECODE_20_.BLIF A_DECODE_19_.BLIF A_DECODE_18_.BLIF \ A_DECODE_17_.BLIF A_DECODE_16_.BLIF A_DECODE_15_.BLIF A_DECODE_14_.BLIF A_DECODE_13_.BLIF A_DECODE_12_.BLIF A_DECODE_11_.BLIF A_DECODE_10_.BLIF A_DECODE_9_.BLIF \ A_DECODE_8_.BLIF A_DECODE_7_.BLIF A_DECODE_6_.BLIF A_DECODE_5_.BLIF A_DECODE_4_.BLIF A_DECODE_3_.BLIF A_DECODE_2_.BLIF IPL_1_.BLIF IPL_0_.BLIF \ - FC_0_.BLIF A_1_.BLIF SIZE_1_.BLIF AHIGH_31_.BLIF AS_030.BLIF AS_000.BLIF RW_000.BLIF UDS_000.BLIF LDS_000.BLIF BERR.BLIF RW.BLIF SIZE_0_.BLIF AHIGH_30_.BLIF AHIGH_29_.BLIF AHIGH_28_.BLIF AHIGH_27_.BLIF AHIGH_26_.BLIF AHIGH_25_.BLIF AHIGH_24_.BLIF A_0_.BLIF rst_dly_i_1__n.BLIF N_41_0.BLIF sm_amiga_i_5__n.BLIF a_c_i_0__n.BLIF rst_dly_i_0__n.BLIF size_c_i_1__n.BLIF sm_amiga_i_i_7__n.BLIF \ - pos_clk_un10_sm_amiga_i_n.BLIF AS_030_D0_i.BLIF un1_as_000_i.BLIF AS_000_INT_i.BLIF un10_ciin_i.BLIF a_i_1__n.BLIF N_260_0.BLIF a_decode_i_16__n.BLIF N_229_i.BLIF \ - inst_BGACK_030_INTreg.BLIF a_decode_i_18__n.BLIF N_230_i.BLIF vcc_n_n.BLIF a_decode_i_19__n.BLIF N_298_0.BLIF inst_VMA_INTreg.BLIF ahigh_i_30__n.BLIF N_48_0.BLIF \ - gnd_n_n.BLIF ahigh_i_31__n.BLIF N_299_i.BLIF un1_amiga_bus_enable_low.BLIF ahigh_i_28__n.BLIF N_345_i.BLIF un7_as_030.BLIF ahigh_i_29__n.BLIF N_349_i.BLIF \ - un1_UDS_000_INT.BLIF ahigh_i_26__n.BLIF un1_DS_000_ENABLE_0_sqmuxa_i.BLIF un1_LDS_000_INT.BLIF ahigh_i_27__n.BLIF N_180_i.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF ahigh_i_24__n.BLIF N_181_i.BLIF \ - un10_ciin.BLIF ahigh_i_25__n.BLIF N_326_i.BLIF un21_fpu_cs.BLIF N_206_i.BLIF un21_berr.BLIF N_207_i.BLIF N_186_i.BLIF un6_ds_030.BLIF \ - N_208_i.BLIF N_163_i.BLIF cpu_est_2_.BLIF N_197_0.BLIF cpu_est_3_.BLIF N_79_i.BLIF N_213_i.BLIF cpu_est_0_.BLIF N_78_i.BLIF \ - N_214_i.BLIF cpu_est_1_.BLIF un6_ds_030_i.BLIF N_215_i.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF N_165_i.BLIF inst_AS_030_D0.BLIF N_169_i.BLIF N_199_i.BLIF \ - inst_AS_030_000_SYNC.BLIF un7_as_030_i.BLIF N_191_0.BLIF inst_BGACK_030_INT_D.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF N_275_i.BLIF inst_AS_000_DMA.BLIF AS_030_c.BLIF N_187_0.BLIF \ - inst_DS_000_DMA.BLIF LDS_000_c_i.BLIF CYCLE_DMA_0_.BLIF AS_000_c.BLIF UDS_000_c_i.BLIF CYCLE_DMA_1_.BLIF N_184_i.BLIF inst_VPA_D.BLIF RW_000_c.BLIF \ - clk_000_d_i_4__n.BLIF CLK_000_D_2_.BLIF N_171_i.BLIF CLK_000_D_4_.BLIF AS_030_000_SYNC_i.BLIF inst_DTACK_D0.BLIF UDS_000_c.BLIF N_161_i.BLIF inst_RESET_OUT.BLIF \ - CLK_000_D_1_.BLIF LDS_000_c.BLIF N_113_0.BLIF CLK_000_D_0_.BLIF N_338_i.BLIF inst_CLK_OUT_PRE_50.BLIF size_c_0__n.BLIF N_339_i.BLIF inst_CLK_OUT_PRE_D.BLIF \ - IPL_D0_0_.BLIF size_c_1__n.BLIF N_335_i.BLIF IPL_D0_1_.BLIF N_336_i.BLIF IPL_D0_2_.BLIF ahigh_c_24__n.BLIF CLK_000_D_3_.BLIF N_334_i.BLIF \ - CLK_000_D_5_.BLIF ahigh_c_25__n.BLIF pos_clk_size_dma_6_0_1__n.BLIF pos_clk_un6_bg_030_n.BLIF N_333_i.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF ahigh_c_26__n.BLIF pos_clk_size_dma_6_0_0__n.BLIF pos_clk_ipl_n.BLIF \ - N_295_i.BLIF SM_AMIGA_1_.BLIF ahigh_c_27__n.BLIF N_332_i.BLIF inst_UDS_000_INT.BLIF inst_DS_000_ENABLE.BLIF ahigh_c_28__n.BLIF N_292_i.BLIF inst_LDS_000_INT.BLIF \ - N_302_0.BLIF pos_clk_un9_bg_030_n.BLIF ahigh_c_29__n.BLIF N_300_0.BLIF SM_AMIGA_6_.BLIF N_290_i.BLIF SM_AMIGA_4_.BLIF ahigh_c_30__n.BLIF SM_AMIGA_0_.BLIF \ - N_273_i.BLIF SIZE_DMA_0_.BLIF ahigh_c_31__n.BLIF SIZE_DMA_1_.BLIF N_327_i.BLIF inst_RW_000_INT.BLIF inst_RW_000_DMA.BLIF N_270_i.BLIF RST_DLY_0_.BLIF \ - RST_DLY_1_.BLIF N_269_i.BLIF RST_DLY_2_.BLIF inst_A0_DMA.BLIF N_267_i.BLIF pos_clk_a0_dma_3_n.BLIF N_324_i.BLIF inst_CLK_030_H.BLIF pos_clk_rw_000_int_5_n.BLIF \ - un1_SM_AMIGA_0_sqmuxa_1_0.BLIF inst_DSACK1_INT.BLIF N_319_i.BLIF inst_AS_000_INT.BLIF N_320_i.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_3_.BLIF RW_c_i.BLIF SM_AMIGA_2_.BLIF \ - pos_clk_rw_000_int_5_0_n.BLIF N_227_i.BLIF N_297_0.BLIF N_15_i.BLIF N_40_0.BLIF N_16_i.BLIF N_15.BLIF N_39_0.BLIF N_16.BLIF \ - N_19_i.BLIF N_19.BLIF N_36_0.BLIF N_20.BLIF N_20_i.BLIF N_22.BLIF N_35_0.BLIF N_23.BLIF N_22_i.BLIF \ - N_24.BLIF N_33_0.BLIF N_23_i.BLIF N_32_0.BLIF a_decode_c_16__n.BLIF N_24_i.BLIF N_31_0.BLIF a_decode_c_17__n.BLIF BG_030_c_i.BLIF \ - pos_clk_un6_bg_030_i_n.BLIF a_decode_c_18__n.BLIF pos_clk_un9_bg_030_0_n.BLIF N_161_i_1.BLIF a_decode_c_19__n.BLIF N_161_i_2.BLIF N_161_i_3.BLIF a_decode_c_20__n.BLIF N_161_i_4.BLIF \ - N_233_i_1.BLIF a_decode_c_21__n.BLIF N_233_i_2.BLIF N_180_i_1.BLIF a_decode_c_22__n.BLIF N_180_i_2.BLIF pos_clk_un10_sm_amiga_i_1_n.BLIF a_decode_c_23__n.BLIF N_196_0_1.BLIF \ - N_188_i_1.BLIF a_c_0__n.BLIF un10_ciin_1.BLIF un10_ciin_2.BLIF a_c_1__n.BLIF un10_ciin_3.BLIF un10_ciin_4.BLIF nEXP_SPACE_c.BLIF un10_ciin_5.BLIF \ - SM_AMIGA_i_7_.BLIF un10_ciin_6.BLIF pos_clk_size_dma_6_0__n.BLIF BERR_c.BLIF un10_ciin_7.BLIF pos_clk_size_dma_6_1__n.BLIF un10_ciin_8.BLIF G_107.BLIF BG_030_c.BLIF \ - un10_ciin_9.BLIF G_108.BLIF un10_ciin_10.BLIF G_109.BLIF BG_000DFFreg.BLIF un10_ciin_11.BLIF N_171_i_1.BLIF N_78.BLIF N_171_i_2.BLIF \ - N_79.BLIF BGACK_000_c.BLIF N_227_1.BLIF N_260.BLIF N_227_2.BLIF N_139.BLIF CLK_030_c.BLIF N_227_3.BLIF N_141.BLIF \ - un21_fpu_cs_1.BLIF N_165.BLIF un21_berr_1_0.BLIF N_169.BLIF N_235_i_1.BLIF N_297.BLIF CLK_OSZI_c.BLIF N_235_i_2.BLIF N_256_1.BLIF \ - N_300.BLIF N_256_2.BLIF N_302.BLIF CLK_OUT_INTreg.BLIF N_232_i_1.BLIF N_113.BLIF N_232_i_2.BLIF N_305.BLIF N_219_1.BLIF \ - N_155.BLIF FPU_SENSE_c.BLIF N_219_2.BLIF N_163.BLIF N_218_1.BLIF N_166.BLIF IPL_030DFF_0_reg.BLIF N_218_2.BLIF N_171.BLIF \ - N_347_1.BLIF N_180.BLIF IPL_030DFF_1_reg.BLIF N_347_2.BLIF N_184.BLIF N_136_i_1.BLIF N_191.BLIF IPL_030DFF_2_reg.BLIF N_146_i_1.BLIF \ - N_199.BLIF N_142_i_1.BLIF N_205.BLIF ipl_c_0__n.BLIF N_234_i_1.BLIF N_306.BLIF N_302_0_1.BLIF N_215.BLIF ipl_c_1__n.BLIF \ - N_63_i_1.BLIF N_221.BLIF N_154_i_1.BLIF N_227.BLIF ipl_c_2__n.BLIF N_152_i_1.BLIF N_230.BLIF N_148_i_1.BLIF N_319.BLIF \ - N_144_i_1.BLIF N_320.BLIF DTACK_c.BLIF N_140_i_1.BLIF N_267.BLIF pos_clk_un6_bg_030_1_n.BLIF N_324.BLIF N_230_1.BLIF N_269.BLIF \ - N_221_1.BLIF N_270.BLIF VPA_c.BLIF N_215_1.BLIF N_327.BLIF N_306_1.BLIF N_273.BLIF pos_clk_ipl_1_n.BLIF N_275.BLIF \ - RST_c.BLIF ipl_030_0_2__un3_n.BLIF N_290.BLIF ipl_030_0_2__un1_n.BLIF N_292.BLIF ipl_030_0_2__un0_n.BLIF N_295.BLIF RW_c.BLIF ipl_030_0_1__un3_n.BLIF \ - N_332.BLIF ipl_030_0_1__un1_n.BLIF N_333.BLIF fc_c_0__n.BLIF ipl_030_0_1__un0_n.BLIF N_334.BLIF ipl_030_0_0__un3_n.BLIF N_335.BLIF fc_c_1__n.BLIF \ - ipl_030_0_0__un1_n.BLIF N_336.BLIF ipl_030_0_0__un0_n.BLIF N_338.BLIF cpu_est_0_3__un3_n.BLIF N_339.BLIF AMIGA_BUS_DATA_DIR_c.BLIF cpu_est_0_3__un1_n.BLIF N_350.BLIF \ - cpu_est_0_3__un0_n.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.BLIF vma_int_0_un3_n.BLIF N_161.BLIF vma_int_0_un1_n.BLIF N_213.BLIF vma_int_0_un0_n.BLIF N_214.BLIF VPA_c_i.BLIF \ - cpu_est_0_1__un3_n.BLIF N_197.BLIF N_52_0.BLIF cpu_est_0_1__un1_n.BLIF N_159.BLIF DTACK_c_i.BLIF cpu_est_0_1__un0_n.BLIF N_326.BLIF N_53_0.BLIF \ - cpu_est_0_2__un3_n.BLIF un21_berr_1.BLIF ipl_c_i_0__n.BLIF cpu_est_0_2__un1_n.BLIF N_181.BLIF N_49_0.BLIF cpu_est_0_2__un0_n.BLIF pos_clk_un21_bgack_030_int_i_i_a2_i_x2.BLIF ipl_c_i_1__n.BLIF \ - ds_000_dma_0_un3_n.BLIF un1_DS_000_ENABLE_0_sqmuxa.BLIF N_50_0.BLIF ds_000_dma_0_un1_n.BLIF N_349.BLIF ipl_c_i_2__n.BLIF ds_000_dma_0_un0_n.BLIF N_345.BLIF N_51_0.BLIF \ - as_000_dma_0_un3_n.BLIF N_229.BLIF N_25_i.BLIF as_000_dma_0_un1_n.BLIF N_14.BLIF N_28_0.BLIF as_000_dma_0_un0_n.BLIF N_21.BLIF N_26_i.BLIF \ - bgack_030_int_0_un3_n.BLIF N_3.BLIF N_29_0.BLIF bgack_030_int_0_un1_n.BLIF N_301.BLIF N_27_i.BLIF bgack_030_int_0_un0_n.BLIF N_4.BLIF N_30_0.BLIF \ - ds_000_enable_0_un3_n.BLIF N_303.BLIF N_222_i.BLIF ds_000_enable_0_un1_n.BLIF N_8.BLIF N_223_i.BLIF ds_000_enable_0_un0_n.BLIF pos_clk_un6_bgack_000_n.BLIF N_192_i.BLIF \ - uds_000_int_0_un3_n.BLIF N_9.BLIF N_231_i.BLIF uds_000_int_0_un1_n.BLIF N_65.BLIF N_237_i.BLIF uds_000_int_0_un0_n.BLIF N_217.BLIF lds_000_int_0_un3_n.BLIF \ - N_216.BLIF N_342_i.BLIF lds_000_int_0_un1_n.BLIF N_248.BLIF N_341_i.BLIF lds_000_int_0_un0_n.BLIF N_198.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un3_n.BLIF N_291.BLIF \ - N_160_0.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un1_n.BLIF N_353.BLIF N_164_i.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un0_n.BLIF N_256.BLIF VMA_INT_i.BLIF amiga_bus_enable_dma_high_0_un3_n.BLIF N_18.BLIF \ - N_347_i.BLIF amiga_bus_enable_dma_high_0_un1_n.BLIF pos_clk_un9_clk_000_pe_n.BLIF N_348_i.BLIF amiga_bus_enable_dma_high_0_un0_n.BLIF cpu_est_2_1__n.BLIF N_188_i.BLIF bg_000_0_un3_n.BLIF cpu_est_2_2__n.BLIF \ - N_245_0.BLIF bg_000_0_un1_n.BLIF N_209.BLIF N_194_0.BLIF bg_000_0_un0_n.BLIF N_211.BLIF N_196_0.BLIF size_dma_0_0__un3_n.BLIF N_220.BLIF \ - size_dma_0_0__un1_n.BLIF N_222.BLIF N_211_i.BLIF size_dma_0_0__un0_n.BLIF N_162.BLIF N_209_i.BLIF size_dma_0_1__un3_n.BLIF N_224.BLIF N_306_i.BLIF \ - size_dma_0_1__un1_n.BLIF N_193.BLIF N_193_0.BLIF size_dma_0_1__un0_n.BLIF N_225.BLIF N_190_0.BLIF as_030_000_sync_0_un3_n.BLIF N_190.BLIF N_183_i.BLIF \ - as_030_000_sync_0_un1_n.BLIF N_346.BLIF N_162_i.BLIF as_030_000_sync_0_un0_n.BLIF N_352.BLIF N_346_i.BLIF rw_000_int_0_un3_n.BLIF N_219.BLIF N_159_0.BLIF \ - rw_000_int_0_un1_n.BLIF N_218.BLIF N_305_i.BLIF rw_000_int_0_un0_n.BLIF N_183.BLIF N_210_i.BLIF rw_000_dma_0_un3_n.BLIF N_196.BLIF N_225_i.BLIF \ - rw_000_dma_0_un1_n.BLIF N_188.BLIF N_224_i.BLIF rw_000_dma_0_un0_n.BLIF N_194.BLIF N_296_i.BLIF a0_dma_0_un3_n.BLIF N_347.BLIF N_352_i.BLIF \ - a0_dma_0_un1_n.BLIF N_348.BLIF cpu_est_2_0_2__n.BLIF a0_dma_0_un0_n.BLIF N_160.BLIF N_220_i.BLIF amiga_bus_enable_dma_low_0_un3_n.BLIF N_341.BLIF N_221_i.BLIF \ - amiga_bus_enable_dma_low_0_un1_n.BLIF N_342.BLIF cpu_est_2_0_1__n.BLIF amiga_bus_enable_dma_low_0_un0_n.BLIF N_231.BLIF N_219_i.BLIF a_decode_15__n.BLIF N_237.BLIF N_218_i.BLIF \ - N_223.BLIF pos_clk_un9_clk_000_pe_0_n.BLIF a_decode_14__n.BLIF N_27.BLIF clk_000_d_i_2__n.BLIF N_26.BLIF N_157_i.BLIF a_decode_13__n.BLIF N_25.BLIF \ - N_18_i.BLIF un1_amiga_bus_enable_low_i.BLIF N_37_0.BLIF a_decode_12__n.BLIF un21_fpu_cs_i.BLIF cpu_est_i_2__n.BLIF N_217_i.BLIF a_decode_11__n.BLIF sm_amiga_i_0__n.BLIF \ - N_216_i.BLIF sm_amiga_i_2__n.BLIF CLK_030_c_i.BLIF a_decode_10__n.BLIF sm_amiga_i_1__n.BLIF N_198_0.BLIF cpu_est_i_0__n.BLIF N_166_i.BLIF a_decode_9__n.BLIF \ - VPA_D_i.BLIF N_155_i.BLIF DTACK_D0_i.BLIF N_303_0.BLIF a_decode_8__n.BLIF AS_030_i.BLIF N_291_i.BLIF DSACK1_INT_i.BLIF N_301_0.BLIF \ - a_decode_7__n.BLIF cpu_est_i_3__n.BLIF N_256_i.BLIF sm_amiga_i_3__n.BLIF N_248_i.BLIF a_decode_6__n.BLIF cpu_est_i_1__n.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF clk_000_d_i_1__n.BLIF \ - N_353_i.BLIF a_decode_5__n.BLIF N_350_i_0.BLIF pos_clk_un6_bgack_000_0_n.BLIF rst_dly_i_2__n.BLIF N_65_0.BLIF a_decode_4__n.BLIF nEXP_SPACE_i.BLIF N_3_i.BLIF \ - AS_000_i.BLIF N_45_0.BLIF a_decode_3__n.BLIF BGACK_030_INT_i.BLIF N_4_i.BLIF sm_amiga_i_6__n.BLIF N_44_0.BLIF a_decode_2__n.BLIF clk_000_d_i_0__n.BLIF \ - N_8_i.BLIF RW_000_i.BLIF N_42_0.BLIF CLK_030_H_i.BLIF UDS_000_INT_i.BLIF AS_000_DMA_i.BLIF un1_UDS_000_INT_0.BLIF cycle_dma_i_0__n.BLIF LDS_000_INT_i.BLIF \ - DS_000_DMA_i.BLIF un1_LDS_000_INT_0.BLIF RESET_OUT_i.BLIF N_21_i.BLIF sm_amiga_i_4__n.BLIF N_34_0.BLIF FPU_SENSE_i.BLIF N_14_i.BLIF AS_030.PIN \ - AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN \ - AHIGH_27_.PIN AHIGH_28_.PIN AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN + FC_0_.BLIF A_1_.BLIF SIZE_1_.BLIF AHIGH_31_.BLIF AS_030.BLIF AS_000.BLIF RW_000.BLIF UDS_000.BLIF LDS_000.BLIF BERR.BLIF RW.BLIF SIZE_0_.BLIF AHIGH_30_.BLIF AHIGH_29_.BLIF AHIGH_28_.BLIF AHIGH_27_.BLIF AHIGH_26_.BLIF AHIGH_25_.BLIF AHIGH_24_.BLIF A_0_.BLIF ipl_i_2__n.BLIF N_233_0.BLIF ipl_i_1__n.BLIF N_360_i.BLIF ipl_i_0__n.BLIF N_191_i_i.BLIF a_i_1__n.BLIF \ + N_192_i_i.BLIF AS_000_DMA_i.BLIF AS_000_i.BLIF N_199_i.BLIF CLK_030_H_i.BLIF N_204_i.BLIF AS_030_000_SYNC_i.BLIF inst_BGACK_030_INTreg.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF \ + N_282_i.BLIF vcc_n_n.BLIF cycle_dma_i_0__n.BLIF N_278_i.BLIF inst_VMA_INTreg.BLIF ahigh_i_30__n.BLIF N_186_i.BLIF gnd_n_n.BLIF ahigh_i_31__n.BLIF \ + N_185_i.BLIF un1_amiga_bus_enable_low.BLIF ahigh_i_28__n.BLIF CLK_030_c_i.BLIF un7_as_030.BLIF ahigh_i_29__n.BLIF N_184_0.BLIF un1_LDS_000_INT.BLIF ahigh_i_26__n.BLIF \ + N_179_0.BLIF un1_UDS_000_INT.BLIF ahigh_i_27__n.BLIF N_251_i.BLIF un10_ciin.BLIF ahigh_i_24__n.BLIF LDS_000_c_i.BLIF un21_fpu_cs.BLIF ahigh_i_25__n.BLIF \ + UDS_000_c_i.BLIF un21_berr.BLIF N_172_i.BLIF un6_ds_030.BLIF pos_clk_un21_bgack_030_int_i_0_0_n.BLIF cpu_est_2_.BLIF N_163_i.BLIF cpu_est_3_.BLIF clk_000_d_i_3__n.BLIF \ + cpu_est_0_.BLIF N_115_i.BLIF N_350_i.BLIF cpu_est_1_.BLIF N_114_i.BLIF un1_rw_i.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF un6_ds_030_i.BLIF N_126_0.BLIF \ + inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF DS_000_DMA_i.BLIF N_313_i.BLIF inst_AS_030_D0.BLIF N_132_i.BLIF N_231_i.BLIF inst_AS_030_000_SYNC.BLIF N_133_i.BLIF N_291_i.BLIF \ + inst_BGACK_030_INT_D.BLIF un7_as_030_i.BLIF inst_AS_000_DMA.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF N_288_i.BLIF inst_DS_000_DMA.BLIF AS_030_c.BLIF CYCLE_DMA_0_.BLIF N_287_i.BLIF \ + CYCLE_DMA_1_.BLIF AS_000_c.BLIF N_340_i.BLIF inst_VPA_D.BLIF CLK_000_D_3_.BLIF RW_000_c.BLIF N_284_i.BLIF inst_DTACK_D0.BLIF inst_RESET_OUT.BLIF \ + N_275_i.BLIF CLK_000_D_1_.BLIF UDS_000_c.BLIF pos_clk_size_dma_6_0_1__n.BLIF CLK_000_D_0_.BLIF N_268_i.BLIF inst_CLK_OUT_PRE_50.BLIF LDS_000_c.BLIF pos_clk_size_dma_6_0_0__n.BLIF \ + inst_CLK_OUT_PRE_D.BLIF N_265_i.BLIF IPL_D0_0_.BLIF size_c_0__n.BLIF N_267_i.BLIF IPL_D0_1_.BLIF IPL_D0_2_.BLIF size_c_1__n.BLIF N_337_i.BLIF \ + CLK_000_D_2_.BLIF N_338_i.BLIF CLK_000_D_4_.BLIF ahigh_c_24__n.BLIF N_55_0.BLIF inst_LDS_000_INT.BLIF un1_as_000_i.BLIF inst_DS_000_ENABLE.BLIF ahigh_c_25__n.BLIF \ + N_245_0.BLIF inst_UDS_000_INT.BLIF N_229_i.BLIF pos_clk_un9_bg_030_n.BLIF ahigh_c_26__n.BLIF SM_AMIGA_6_.BLIF N_227_i.BLIF SM_AMIGA_4_.BLIF ahigh_c_27__n.BLIF \ + SM_AMIGA_1_.BLIF N_226_i.BLIF SM_AMIGA_0_.BLIF ahigh_c_28__n.BLIF N_246_0.BLIF SIZE_DMA_0_.BLIF N_332_i.BLIF SIZE_DMA_1_.BLIF ahigh_c_29__n.BLIF \ + pos_clk_ds_000_dma_4_0_n.BLIF inst_RW_000_INT.BLIF N_48_0.BLIF inst_RW_000_DMA.BLIF ahigh_c_30__n.BLIF pos_clk_rw_000_dma_3_0_n.BLIF RST_DLY_0_.BLIF N_218_i.BLIF RST_DLY_1_.BLIF \ + ahigh_c_31__n.BLIF RST_DLY_2_.BLIF inst_A0_DMA.BLIF un10_ciin_i.BLIF pos_clk_a0_dma_3_n.BLIF N_62_0.BLIF pos_clk_rw_000_dma_3_n.BLIF N_215_i.BLIF inst_CLK_030_H.BLIF \ + N_216_i.BLIF inst_DSACK1_INT.BLIF un10_amiga_bus_enable_high_i.BLIF inst_AS_000_INT.BLIF N_214_i.BLIF SM_AMIGA_5_.BLIF N_310_0.BLIF SM_AMIGA_3_.BLIF N_24_i.BLIF \ + SM_AMIGA_2_.BLIF N_33_0.BLIF pos_clk_ds_000_dma_4_n.BLIF N_23_i.BLIF N_3.BLIF N_32_0.BLIF N_4.BLIF N_22_i.BLIF N_31_0.BLIF \ + N_3_i.BLIF N_45_0.BLIF N_4_i.BLIF N_44_0.BLIF N_15.BLIF N_15_i.BLIF N_19.BLIF N_40_0.BLIF N_20.BLIF \ + N_19_i.BLIF N_22.BLIF N_36_0.BLIF N_23.BLIF N_20_i.BLIF N_24.BLIF N_35_0.BLIF N_25.BLIF N_25_i.BLIF \ + N_26.BLIF N_30_0.BLIF N_27.BLIF N_26_i.BLIF N_29_0.BLIF N_27_i.BLIF a_decode_c_16__n.BLIF N_28_0.BLIF BG_030_c_i.BLIF \ + a_decode_c_17__n.BLIF pos_clk_un9_bg_030_0_n.BLIF N_235_i_1.BLIF a_decode_c_18__n.BLIF N_235_i_2.BLIF N_156_i_1.BLIF a_decode_c_19__n.BLIF N_156_i_2.BLIF N_156_i_3.BLIF \ + a_decode_c_20__n.BLIF N_156_i_4.BLIF pos_clk_un10_sm_amiga_i_1_n.BLIF a_decode_c_21__n.BLIF N_176_i_1.BLIF un10_ciin_1.BLIF a_decode_c_22__n.BLIF un10_ciin_2.BLIF un10_ciin_3.BLIF \ + a_decode_c_23__n.BLIF un10_ciin_4.BLIF un10_ciin_5.BLIF a_c_0__n.BLIF un10_ciin_6.BLIF un10_ciin_7.BLIF a_c_1__n.BLIF un10_ciin_8.BLIF SM_AMIGA_i_7_.BLIF \ + un10_ciin_9.BLIF pos_clk_size_dma_6_0__n.BLIF nEXP_SPACE_c.BLIF un10_ciin_10.BLIF pos_clk_size_dma_6_1__n.BLIF un10_ciin_11.BLIF N_199.BLIF BERR_c.BLIF N_163_i_1.BLIF \ + pos_clk_un21_bgack_030_int_i_0_n.BLIF N_163_i_2.BLIF N_231.BLIF BG_030_c.BLIF pos_clk_un21_bgack_030_int_i_0_0_1_n.BLIF N_233.BLIF pos_clk_un21_bgack_030_int_i_0_0_2_n.BLIF N_111.BLIF BG_000DFFreg.BLIF \ + N_138_i_1.BLIF N_112.BLIF N_138_i_2.BLIF N_113.BLIF N_59_i_1.BLIF N_114.BLIF BGACK_000_c.BLIF N_59_i_2.BLIF N_115.BLIF \ + N_233_0_1.BLIF N_245.BLIF CLK_030_c.BLIF N_233_0_2.BLIF N_246.BLIF N_214_1.BLIF N_62.BLIF N_214_2.BLIF N_214_3.BLIF \ + N_132.BLIF CLK_OSZI_c.BLIF un21_fpu_cs_1.BLIF N_133.BLIF un21_berr_1_0.BLIF N_310.BLIF N_182_0_1.BLIF N_126.BLIF CLK_OUT_INTreg.BLIF \ + N_234_i_1.BLIF N_149.BLIF N_234_i_2.BLIF N_150.BLIF N_206_1.BLIF N_158.BLIF FPU_SENSE_c.BLIF N_206_2.BLIF N_160.BLIF \ + N_205_1.BLIF N_163.BLIF IPL_030DFF_0_reg.BLIF N_205_2.BLIF N_172.BLIF N_352_1.BLIF N_179.BLIF IPL_030DFF_1_reg.BLIF N_352_2.BLIF \ + N_184.BLIF N_231_i_1.BLIF N_185.BLIF IPL_030DFF_2_reg.BLIF N_152_i_1.BLIF N_196.BLIF N_144_i_1.BLIF N_203.BLIF ipl_c_0__n.BLIF \ + N_142_i_1.BLIF N_204.BLIF N_312_i_1.BLIF N_209.BLIF ipl_c_1__n.BLIF N_236_i_1.BLIF N_214.BLIF N_148_i_1.BLIF N_215.BLIF \ + ipl_c_2__n.BLIF N_136_i_1.BLIF N_216.BLIF N_246_0_1.BLIF N_218.BLIF N_249_i_1.BLIF N_224.BLIF DTACK_c.BLIF N_57_i_1.BLIF \ + N_332.BLIF N_338_1.BLIF N_226.BLIF N_224_1.BLIF N_227.BLIF N_216_1.BLIF N_229.BLIF VPA_c.BLIF N_209_1.BLIF \ + N_337.BLIF N_203_1.BLIF N_338.BLIF N_196_1.BLIF N_265.BLIF RST_c.BLIF cpu_est_0_3__un3_n.BLIF N_267.BLIF cpu_est_0_3__un1_n.BLIF \ + N_268.BLIF cpu_est_0_3__un0_n.BLIF N_275.BLIF RW_c.BLIF rw_000_int_0_un3_n.BLIF N_278.BLIF rw_000_int_0_un1_n.BLIF N_282.BLIF fc_c_0__n.BLIF \ + rw_000_int_0_un0_n.BLIF N_284.BLIF vma_int_0_un3_n.BLIF N_340.BLIF fc_c_1__n.BLIF vma_int_0_un1_n.BLIF N_287.BLIF vma_int_0_un0_n.BLIF N_288.BLIF \ + cpu_est_0_1__un3_n.BLIF N_291.BLIF AMIGA_BUS_DATA_DIR_c.BLIF cpu_est_0_1__un1_n.BLIF N_293.BLIF cpu_est_0_1__un0_n.BLIF N_350.BLIF cpu_est_0_2__un3_n.BLIF N_355.BLIF \ + cpu_est_0_2__un1_n.BLIF pos_clk_un21_bgack_030_int_i_0_o3_0_x2.BLIF cpu_est_0_2__un0_n.BLIF pos_clk_un1_ipl_i_0_x2.BLIF N_16_i.BLIF uds_000_int_0_un3_n.BLIF pos_clk_un1_ipl_i_0_x2_0.BLIF N_39_0.BLIF uds_000_int_0_un1_n.BLIF \ + pos_clk_un1_ipl_i_0_x2_1.BLIF VPA_c_i.BLIF uds_000_int_0_un0_n.BLIF pos_clk_CYCLE_DMA_5_1_i_0_x2.BLIF N_52_0.BLIF lds_000_int_0_un3_n.BLIF N_156.BLIF DTACK_c_i.BLIF lds_000_int_0_un1_n.BLIF \ + N_201.BLIF N_53_0.BLIF lds_000_int_0_un0_n.BLIF N_202.BLIF N_210_i.BLIF bgack_030_int_0_un3_n.BLIF N_154.BLIF N_211_i.BLIF bgack_030_int_0_un1_n.BLIF \ + un21_berr_1.BLIF N_189_i.BLIF bgack_030_int_0_un0_n.BLIF N_174.BLIF un1_SM_AMIGA_0_sqmuxa_1_0.BLIF ds_000_enable_0_un3_n.BLIF N_223.BLIF RW_c_i.BLIF ds_000_enable_0_un1_n.BLIF \ + N_221.BLIF N_311_0.BLIF ds_000_enable_0_un0_n.BLIF N_222.BLIF N_336_i.BLIF size_dma_0_0__un3_n.BLIF N_219.BLIF N_244_i.BLIF size_dma_0_0__un1_n.BLIF \ + N_220.BLIF size_dma_0_0__un0_n.BLIF pos_clk_un6_bgack_000_n.BLIF N_314_0.BLIF size_dma_0_1__un3_n.BLIF N_359.BLIF N_159_i.BLIF size_dma_0_1__un1_n.BLIF N_8.BLIF \ + VMA_INT_i.BLIF size_dma_0_1__un0_n.BLIF N_14.BLIF N_352_i.BLIF ipl_030_0_0__un3_n.BLIF N_21.BLIF N_353_i.BLIF ipl_030_0_0__un1_n.BLIF N_9.BLIF \ + N_293_i.BLIF ipl_030_0_0__un0_n.BLIF un1_DS_000_ENABLE_0_sqmuxa.BLIF N_175_i.BLIF ipl_030_0_1__un3_n.BLIF N_66.BLIF N_176_i.BLIF ipl_030_0_1__un1_n.BLIF N_171.BLIF \ + ipl_030_0_1__un0_n.BLIF N_354.BLIF N_198_i.BLIF ipl_030_0_2__un3_n.BLIF N_18.BLIF N_197_i.BLIF ipl_030_0_2__un1_n.BLIF pos_clk_un9_clk_000_pe_n.BLIF N_196_i.BLIF \ + ipl_030_0_2__un0_n.BLIF cpu_est_2_1__n.BLIF N_183_0.BLIF a0_dma_0_un3_n.BLIF cpu_est_2_2__n.BLIF N_182_0.BLIF a0_dma_0_un1_n.BLIF N_197.BLIF N_180_0.BLIF \ + a0_dma_0_un0_n.BLIF N_198.BLIF N_178_0.BLIF amiga_bus_enable_dma_low_0_un3_n.BLIF N_208.BLIF N_82_i.BLIF amiga_bus_enable_dma_low_0_un1_n.BLIF N_210.BLIF N_315_i.BLIF \ + amiga_bus_enable_dma_low_0_un0_n.BLIF N_315.BLIF N_351_i.BLIF amiga_bus_enable_dma_high_0_un3_n.BLIF N_212.BLIF N_154_0.BLIF amiga_bus_enable_dma_high_0_un1_n.BLIF N_180.BLIF N_149_i.BLIF \ + amiga_bus_enable_dma_high_0_un0_n.BLIF N_213.BLIF N_207_i.BLIF bg_000_0_un3_n.BLIF N_178.BLIF N_228_i.BLIF bg_000_0_un1_n.BLIF N_228.BLIF bg_000_0_un0_n.BLIF \ + N_182.BLIF N_213_i.BLIF ds_000_dma_0_un3_n.BLIF N_176.BLIF N_212_i.BLIF ds_000_dma_0_un1_n.BLIF N_183.BLIF N_309_i.BLIF ds_000_dma_0_un0_n.BLIF \ + N_351.BLIF N_357_i.BLIF as_000_dma_0_un3_n.BLIF N_357.BLIF cpu_est_2_0_2__n.BLIF as_000_dma_0_un1_n.BLIF N_206.BLIF N_208_i.BLIF as_000_dma_0_un0_n.BLIF \ + N_205.BLIF N_209_i.BLIF as_030_000_sync_0_un3_n.BLIF N_352.BLIF cpu_est_2_0_1__n.BLIF as_030_000_sync_0_un1_n.BLIF N_353.BLIF N_206_i.BLIF as_030_000_sync_0_un0_n.BLIF \ + N_314.BLIF N_205_i.BLIF rw_000_dma_0_un3_n.BLIF N_244.BLIF pos_clk_un9_clk_000_pe_0_n.BLIF rw_000_dma_0_un1_n.BLIF N_336.BLIF N_18_i.BLIF rw_000_dma_0_un0_n.BLIF \ + N_311.BLIF N_37_0.BLIF a_decode_15__n.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF N_171_i.BLIF N_211.BLIF N_354_i.BLIF a_decode_14__n.BLIF N_16.BLIF \ + un1_DS_000_ENABLE_0_sqmuxa_0.BLIF un1_amiga_bus_enable_low_i.BLIF N_66_0.BLIF a_decode_13__n.BLIF un21_fpu_cs_i.BLIF UDS_000_INT_i.BLIF cpu_est_i_2__n.BLIF un1_UDS_000_INT_0.BLIF a_decode_12__n.BLIF \ + cpu_est_i_0__n.BLIF LDS_000_INT_i.BLIF VPA_D_i.BLIF un1_LDS_000_INT_0.BLIF a_decode_11__n.BLIF DTACK_D0_i.BLIF N_21_i.BLIF cpu_est_i_3__n.BLIF N_34_0.BLIF \ + a_decode_10__n.BLIF sm_amiga_i_i_7__n.BLIF N_14_i.BLIF sm_amiga_i_5__n.BLIF N_41_0.BLIF a_decode_9__n.BLIF sm_amiga_i_3__n.BLIF N_8_i.BLIF cpu_est_i_1__n.BLIF \ + N_42_0.BLIF a_decode_8__n.BLIF clk_000_d_i_1__n.BLIF a_c_i_0__n.BLIF N_355_i_0.BLIF size_c_i_1__n.BLIF a_decode_7__n.BLIF sm_amiga_i_4__n.BLIF pos_clk_un10_sm_amiga_i_n.BLIF \ + sm_amiga_i_2__n.BLIF N_359_i.BLIF a_decode_6__n.BLIF rst_dly_i_0__n.BLIF pos_clk_un6_bgack_000_0_n.BLIF rst_dly_i_2__n.BLIF N_220_i.BLIF a_decode_5__n.BLIF a_decode_i_19__n.BLIF \ + N_219_i.BLIF a_decode_i_18__n.BLIF a_decode_4__n.BLIF a_decode_i_16__n.BLIF N_222_i.BLIF RW_000_i.BLIF N_221_i.BLIF a_decode_3__n.BLIF sm_amiga_i_0__n.BLIF \ + AS_030_i.BLIF N_223_i.BLIF a_decode_2__n.BLIF AS_000_INT_i.BLIF N_224_i.BLIF DSACK1_INT_i.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF clk_000_d_i_0__n.BLIF N_150_i.BLIF \ + sm_amiga_i_6__n.BLIF N_156_i.BLIF sm_amiga_i_1__n.BLIF N_160_i.BLIF FPU_SENSE_i.BLIF N_174_i.BLIF rst_dly_i_1__n.BLIF N_158_i.BLIF AS_030_D0_i.BLIF \ + N_201_i.BLIF BGACK_030_INT_i.BLIF N_202_i.BLIF nEXP_SPACE_i.BLIF N_203_i.BLIF RESET_OUT_i.BLIF AS_030.PIN AS_000.PIN RW_000.PIN \ + UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN \ + AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN .outputs IPL_030_2_ DS_030 BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 AVEC E VMA \ - RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C SM_AMIGA_6_.D \ - SM_AMIGA_6_.C SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C \ - SM_AMIGA_0_.D SM_AMIGA_0_.C cpu_est_3_.D cpu_est_3_.C IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D IPL_030DFF_2_reg.C IPL_D0_0_.D \ - IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C CLK_000_D_0_.D CLK_000_D_0_.C CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_2_.D CLK_000_D_2_.C \ - CLK_000_D_3_.D CLK_000_D_3_.C CLK_000_D_4_.D CLK_000_D_4_.C CLK_000_D_5_.D CLK_000_D_5_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D \ - SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C RST_DLY_0_.D RST_DLY_0_.C \ - RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C inst_DS_000_DMA.D inst_DS_000_DMA.C inst_DSACK1_INT.D inst_DSACK1_INT.C inst_AS_000_INT.D inst_AS_000_INT.C inst_AS_030_D0.D \ - inst_AS_030_D0.C inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D inst_DTACK_D0.C inst_CLK_030_H.D inst_CLK_030_H.C inst_RESET_OUT.D inst_RESET_OUT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C \ - BG_000DFFreg.D BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_UDS_000_INT.D inst_UDS_000_INT.C inst_A0_DMA.D inst_A0_DMA.C inst_RW_000_DMA.D \ - inst_RW_000_DMA.C inst_VMA_INTreg.D inst_VMA_INTreg.C inst_RW_000_INT.D inst_RW_000_INT.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_LDS_000_INT.D inst_LDS_000_INT.C inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C \ - inst_AS_000_DMA.D inst_AS_000_DMA.C inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C pos_clk_un21_bgack_030_int_i_i_a2_i_x2.X1 \ - pos_clk_un21_bgack_030_int_i_i_a2_i_x2.X2 G_109.X1 G_109.X2 G_108.X1 G_108.X2 G_107.X1 G_107.X2 pos_clk_CYCLE_DMA_5_1_i_x2.X1 pos_clk_CYCLE_DMA_5_1_i_x2.X2 SIZE_1_ AHIGH_31_ AS_030 AS_000 RW_000 UDS_000 LDS_000 BERR RW SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ A_0_ rst_dly_i_1__n N_41_0 \ - sm_amiga_i_5__n a_c_i_0__n rst_dly_i_0__n size_c_i_1__n sm_amiga_i_i_7__n pos_clk_un10_sm_amiga_i_n AS_030_D0_i un1_as_000_i AS_000_INT_i un10_ciin_i a_i_1__n \ - N_260_0 a_decode_i_16__n N_229_i a_decode_i_18__n N_230_i vcc_n_n a_decode_i_19__n N_298_0 ahigh_i_30__n N_48_0 gnd_n_n \ - ahigh_i_31__n N_299_i un1_amiga_bus_enable_low ahigh_i_28__n N_345_i un7_as_030 ahigh_i_29__n N_349_i un1_UDS_000_INT ahigh_i_26__n un1_DS_000_ENABLE_0_sqmuxa_i \ - un1_LDS_000_INT ahigh_i_27__n N_180_i un1_SM_AMIGA_0_sqmuxa_1 ahigh_i_24__n N_181_i un10_ciin ahigh_i_25__n N_326_i un21_fpu_cs N_206_i \ - un21_berr N_207_i N_186_i un6_ds_030 N_208_i N_163_i N_197_0 N_79_i N_213_i N_78_i N_214_i \ - un6_ds_030_i N_215_i N_165_i N_169_i N_199_i un7_as_030_i N_191_0 AMIGA_BUS_ENABLE_DMA_LOW_i N_275_i AS_030_c N_187_0 \ - LDS_000_c_i AS_000_c UDS_000_c_i N_184_i RW_000_c clk_000_d_i_4__n N_171_i AS_030_000_SYNC_i UDS_000_c N_161_i LDS_000_c \ - N_113_0 N_338_i size_c_0__n N_339_i size_c_1__n N_335_i N_336_i ahigh_c_24__n N_334_i ahigh_c_25__n pos_clk_size_dma_6_0_1__n \ - pos_clk_un6_bg_030_n N_333_i ahigh_c_26__n pos_clk_size_dma_6_0_0__n pos_clk_ipl_n N_295_i ahigh_c_27__n N_332_i ahigh_c_28__n N_292_i N_302_0 \ - pos_clk_un9_bg_030_n ahigh_c_29__n N_300_0 N_290_i ahigh_c_30__n N_273_i ahigh_c_31__n N_327_i N_270_i N_269_i N_267_i \ - pos_clk_a0_dma_3_n N_324_i pos_clk_rw_000_int_5_n un1_SM_AMIGA_0_sqmuxa_1_0 N_319_i N_320_i RW_c_i pos_clk_rw_000_int_5_0_n N_227_i N_297_0 N_15_i \ - N_40_0 N_16_i N_15 N_39_0 N_16 N_19_i N_19 N_36_0 N_20 N_20_i N_22 \ - N_35_0 N_23 N_22_i N_24 N_33_0 N_23_i N_32_0 a_decode_c_16__n N_24_i N_31_0 a_decode_c_17__n \ - BG_030_c_i pos_clk_un6_bg_030_i_n a_decode_c_18__n pos_clk_un9_bg_030_0_n N_161_i_1 a_decode_c_19__n N_161_i_2 N_161_i_3 a_decode_c_20__n N_161_i_4 N_233_i_1 \ - a_decode_c_21__n N_233_i_2 N_180_i_1 a_decode_c_22__n N_180_i_2 pos_clk_un10_sm_amiga_i_1_n a_decode_c_23__n N_196_0_1 N_188_i_1 a_c_0__n un10_ciin_1 \ - un10_ciin_2 a_c_1__n un10_ciin_3 un10_ciin_4 nEXP_SPACE_c un10_ciin_5 un10_ciin_6 pos_clk_size_dma_6_0__n BERR_c un10_ciin_7 pos_clk_size_dma_6_1__n \ - un10_ciin_8 BG_030_c un10_ciin_9 un10_ciin_10 un10_ciin_11 N_171_i_1 N_78 N_171_i_2 N_79 BGACK_000_c N_227_1 \ - N_260 N_227_2 N_139 CLK_030_c N_227_3 N_141 un21_fpu_cs_1 N_165 un21_berr_1_0 N_169 N_235_i_1 \ - N_297 CLK_OSZI_c N_235_i_2 N_256_1 N_300 N_256_2 N_302 N_232_i_1 N_113 N_232_i_2 N_305 \ - N_219_1 N_155 FPU_SENSE_c N_219_2 N_163 N_218_1 N_166 N_218_2 N_171 N_347_1 N_180 \ - N_347_2 N_184 N_136_i_1 N_191 N_146_i_1 N_199 N_142_i_1 N_205 ipl_c_0__n N_234_i_1 N_306 \ - N_302_0_1 N_215 ipl_c_1__n N_63_i_1 N_221 N_154_i_1 N_227 ipl_c_2__n N_152_i_1 N_230 N_148_i_1 \ - N_319 N_144_i_1 N_320 DTACK_c N_140_i_1 N_267 pos_clk_un6_bg_030_1_n N_324 N_230_1 N_269 N_221_1 \ - N_270 VPA_c N_215_1 N_327 N_306_1 N_273 pos_clk_ipl_1_n N_275 RST_c ipl_030_0_2__un3_n N_290 \ - ipl_030_0_2__un1_n N_292 ipl_030_0_2__un0_n N_295 RW_c ipl_030_0_1__un3_n N_332 ipl_030_0_1__un1_n N_333 fc_c_0__n ipl_030_0_1__un0_n \ - N_334 ipl_030_0_0__un3_n N_335 fc_c_1__n ipl_030_0_0__un1_n N_336 ipl_030_0_0__un0_n N_338 cpu_est_0_3__un3_n N_339 AMIGA_BUS_DATA_DIR_c \ - cpu_est_0_3__un1_n N_350 cpu_est_0_3__un0_n vma_int_0_un3_n N_161 vma_int_0_un1_n N_213 vma_int_0_un0_n N_214 VPA_c_i cpu_est_0_1__un3_n \ - N_197 N_52_0 cpu_est_0_1__un1_n N_159 DTACK_c_i cpu_est_0_1__un0_n N_326 N_53_0 cpu_est_0_2__un3_n un21_berr_1 ipl_c_i_0__n \ - cpu_est_0_2__un1_n N_181 N_49_0 cpu_est_0_2__un0_n ipl_c_i_1__n ds_000_dma_0_un3_n un1_DS_000_ENABLE_0_sqmuxa N_50_0 ds_000_dma_0_un1_n N_349 ipl_c_i_2__n \ - ds_000_dma_0_un0_n N_345 N_51_0 as_000_dma_0_un3_n N_229 N_25_i as_000_dma_0_un1_n N_14 N_28_0 as_000_dma_0_un0_n N_21 \ - N_26_i bgack_030_int_0_un3_n N_3 N_29_0 bgack_030_int_0_un1_n N_301 N_27_i bgack_030_int_0_un0_n N_4 N_30_0 ds_000_enable_0_un3_n \ - N_303 N_222_i ds_000_enable_0_un1_n N_8 N_223_i ds_000_enable_0_un0_n pos_clk_un6_bgack_000_n N_192_i uds_000_int_0_un3_n N_9 N_231_i \ - uds_000_int_0_un1_n N_65 N_237_i uds_000_int_0_un0_n N_217 lds_000_int_0_un3_n N_216 N_342_i lds_000_int_0_un1_n N_248 N_341_i \ - lds_000_int_0_un0_n N_198 un1_amiga_bus_enable_dma_high_i_m2_0__un3_n N_291 N_160_0 un1_amiga_bus_enable_dma_high_i_m2_0__un1_n N_353 N_164_i un1_amiga_bus_enable_dma_high_i_m2_0__un0_n N_256 VMA_INT_i \ - amiga_bus_enable_dma_high_0_un3_n N_18 N_347_i amiga_bus_enable_dma_high_0_un1_n pos_clk_un9_clk_000_pe_n N_348_i amiga_bus_enable_dma_high_0_un0_n cpu_est_2_1__n N_188_i bg_000_0_un3_n cpu_est_2_2__n \ - N_245_0 bg_000_0_un1_n N_209 N_194_0 bg_000_0_un0_n N_211 N_196_0 size_dma_0_0__un3_n N_220 size_dma_0_0__un1_n N_222 \ - N_211_i size_dma_0_0__un0_n N_162 N_209_i size_dma_0_1__un3_n N_224 N_306_i size_dma_0_1__un1_n N_193 N_193_0 size_dma_0_1__un0_n \ - N_225 N_190_0 as_030_000_sync_0_un3_n N_190 N_183_i as_030_000_sync_0_un1_n N_346 N_162_i as_030_000_sync_0_un0_n N_352 N_346_i \ - rw_000_int_0_un3_n N_219 N_159_0 rw_000_int_0_un1_n N_218 N_305_i rw_000_int_0_un0_n N_183 N_210_i rw_000_dma_0_un3_n N_196 \ - N_225_i rw_000_dma_0_un1_n N_188 N_224_i rw_000_dma_0_un0_n N_194 N_296_i a0_dma_0_un3_n N_347 N_352_i a0_dma_0_un1_n \ - N_348 cpu_est_2_0_2__n a0_dma_0_un0_n N_160 N_220_i amiga_bus_enable_dma_low_0_un3_n N_341 N_221_i amiga_bus_enable_dma_low_0_un1_n N_342 cpu_est_2_0_1__n \ - amiga_bus_enable_dma_low_0_un0_n N_231 N_219_i a_decode_15__n N_237 N_218_i N_223 pos_clk_un9_clk_000_pe_0_n a_decode_14__n N_27 clk_000_d_i_2__n \ - N_26 N_157_i a_decode_13__n N_25 N_18_i un1_amiga_bus_enable_low_i N_37_0 a_decode_12__n un21_fpu_cs_i cpu_est_i_2__n N_217_i \ - a_decode_11__n sm_amiga_i_0__n N_216_i sm_amiga_i_2__n CLK_030_c_i a_decode_10__n sm_amiga_i_1__n N_198_0 cpu_est_i_0__n N_166_i a_decode_9__n \ - VPA_D_i N_155_i DTACK_D0_i N_303_0 a_decode_8__n AS_030_i N_291_i DSACK1_INT_i N_301_0 a_decode_7__n cpu_est_i_3__n \ - N_256_i sm_amiga_i_3__n N_248_i a_decode_6__n cpu_est_i_1__n AMIGA_BUS_DATA_DIR_c_0 clk_000_d_i_1__n N_353_i a_decode_5__n N_350_i_0 pos_clk_un6_bgack_000_0_n \ - rst_dly_i_2__n N_65_0 a_decode_4__n nEXP_SPACE_i N_3_i AS_000_i N_45_0 a_decode_3__n BGACK_030_INT_i N_4_i sm_amiga_i_6__n \ - N_44_0 a_decode_2__n clk_000_d_i_0__n N_8_i RW_000_i N_42_0 CLK_030_H_i UDS_000_INT_i AS_000_DMA_i un1_UDS_000_INT_0 cycle_dma_i_0__n \ - LDS_000_INT_i DS_000_DMA_i un1_LDS_000_INT_0 RESET_OUT_i N_21_i sm_amiga_i_4__n N_34_0 FPU_SENSE_i N_14_i \ - AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE \ - AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE RW.OE \ - DS_030.OE DSACK1.OE RESET.OE CIIN.OE + RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D \ + IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_4_.D SM_AMIGA_4_.C \ + SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D \ + cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D IPL_030DFF_2_reg.C \ + RST_DLY_2_.D RST_DLY_2_.C CLK_000_D_0_.D CLK_000_D_0_.C CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_2_.D CLK_000_D_2_.C CLK_000_D_3_.D CLK_000_D_3_.C CLK_000_D_4_.D \ + CLK_000_D_4_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C RST_DLY_0_.D RST_DLY_0_.C \ + RST_DLY_1_.D RST_DLY_1_.C inst_RW_000_INT.D inst_RW_000_INT.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_LDS_000_INT.D inst_LDS_000_INT.C inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_AS_000_DMA.D \ + inst_AS_000_DMA.C inst_DS_000_DMA.D inst_DS_000_DMA.C inst_DSACK1_INT.D inst_DSACK1_INT.C inst_AS_000_INT.D inst_AS_000_INT.C inst_AS_030_D0.D inst_AS_030_D0.C inst_VPA_D.D inst_VPA_D.C \ + inst_DTACK_D0.D inst_DTACK_D0.C inst_CLK_030_H.D inst_CLK_030_H.C inst_RESET_OUT.D inst_RESET_OUT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C BG_000DFFreg.D BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D \ + inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_UDS_000_INT.D inst_UDS_000_INT.C inst_A0_DMA.D inst_A0_DMA.C inst_RW_000_DMA.D inst_RW_000_DMA.C inst_VMA_INTreg.D inst_VMA_INTreg.C \ + inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C pos_clk_un21_bgack_030_int_i_0_o3_0_x2.X1 pos_clk_un21_bgack_030_int_i_0_o3_0_x2.X2 pos_clk_un1_ipl_i_0_x2.X1 \ + pos_clk_un1_ipl_i_0_x2.X2 pos_clk_un1_ipl_i_0_x2_0.X1 pos_clk_un1_ipl_i_0_x2_0.X2 pos_clk_un1_ipl_i_0_x2_1.X1 pos_clk_un1_ipl_i_0_x2_1.X2 pos_clk_CYCLE_DMA_5_1_i_0_x2.X1 pos_clk_CYCLE_DMA_5_1_i_0_x2.X2 SIZE_1_ AHIGH_31_ AS_030 AS_000 RW_000 UDS_000 LDS_000 BERR RW SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ A_0_ ipl_i_2__n N_233_0 ipl_i_1__n N_360_i \ + ipl_i_0__n N_191_i_i a_i_1__n N_192_i_i AS_000_DMA_i AS_000_i N_199_i CLK_030_H_i N_204_i AS_030_000_SYNC_i AMIGA_BUS_ENABLE_DMA_HIGH_i \ + N_282_i vcc_n_n cycle_dma_i_0__n N_278_i ahigh_i_30__n N_186_i gnd_n_n ahigh_i_31__n N_185_i un1_amiga_bus_enable_low ahigh_i_28__n \ + CLK_030_c_i un7_as_030 ahigh_i_29__n N_184_0 un1_LDS_000_INT ahigh_i_26__n N_179_0 un1_UDS_000_INT ahigh_i_27__n N_251_i un10_ciin \ + ahigh_i_24__n LDS_000_c_i un21_fpu_cs ahigh_i_25__n UDS_000_c_i un21_berr N_172_i un6_ds_030 pos_clk_un21_bgack_030_int_i_0_0_n N_163_i clk_000_d_i_3__n \ + N_115_i N_350_i N_114_i un1_rw_i un6_ds_030_i N_126_0 DS_000_DMA_i N_313_i N_132_i N_231_i N_133_i \ + N_291_i un7_as_030_i AMIGA_BUS_ENABLE_DMA_LOW_i N_288_i AS_030_c N_287_i AS_000_c N_340_i RW_000_c N_284_i N_275_i \ + UDS_000_c pos_clk_size_dma_6_0_1__n N_268_i LDS_000_c pos_clk_size_dma_6_0_0__n N_265_i size_c_0__n N_267_i size_c_1__n N_337_i N_338_i \ + ahigh_c_24__n N_55_0 un1_as_000_i ahigh_c_25__n N_245_0 N_229_i pos_clk_un9_bg_030_n ahigh_c_26__n N_227_i ahigh_c_27__n N_226_i \ + ahigh_c_28__n N_246_0 N_332_i ahigh_c_29__n pos_clk_ds_000_dma_4_0_n N_48_0 ahigh_c_30__n pos_clk_rw_000_dma_3_0_n N_218_i ahigh_c_31__n un10_ciin_i \ + pos_clk_a0_dma_3_n N_62_0 pos_clk_rw_000_dma_3_n N_215_i N_216_i un10_amiga_bus_enable_high_i N_214_i N_310_0 N_24_i N_33_0 pos_clk_ds_000_dma_4_n \ + N_23_i N_3 N_32_0 N_4 N_22_i N_31_0 N_3_i N_45_0 N_4_i N_44_0 N_15 \ + N_15_i N_19 N_40_0 N_20 N_19_i N_22 N_36_0 N_23 N_20_i N_24 N_35_0 \ + N_25 N_25_i N_26 N_30_0 N_27 N_26_i N_29_0 N_27_i a_decode_c_16__n N_28_0 BG_030_c_i \ + a_decode_c_17__n pos_clk_un9_bg_030_0_n N_235_i_1 a_decode_c_18__n N_235_i_2 N_156_i_1 a_decode_c_19__n N_156_i_2 N_156_i_3 a_decode_c_20__n N_156_i_4 \ + pos_clk_un10_sm_amiga_i_1_n a_decode_c_21__n N_176_i_1 un10_ciin_1 a_decode_c_22__n un10_ciin_2 un10_ciin_3 a_decode_c_23__n un10_ciin_4 un10_ciin_5 a_c_0__n \ + un10_ciin_6 un10_ciin_7 a_c_1__n un10_ciin_8 un10_ciin_9 pos_clk_size_dma_6_0__n nEXP_SPACE_c un10_ciin_10 pos_clk_size_dma_6_1__n un10_ciin_11 N_199 \ + BERR_c N_163_i_1 pos_clk_un21_bgack_030_int_i_0_n N_163_i_2 N_231 BG_030_c pos_clk_un21_bgack_030_int_i_0_0_1_n N_233 pos_clk_un21_bgack_030_int_i_0_0_2_n N_111 N_138_i_1 \ + N_112 N_138_i_2 N_113 N_59_i_1 N_114 BGACK_000_c N_59_i_2 N_115 N_233_0_1 N_245 CLK_030_c \ + N_233_0_2 N_246 N_214_1 N_62 N_214_2 N_214_3 N_132 CLK_OSZI_c un21_fpu_cs_1 N_133 un21_berr_1_0 \ + N_310 N_182_0_1 N_126 N_234_i_1 N_149 N_234_i_2 N_150 N_206_1 N_158 FPU_SENSE_c N_206_2 \ + N_160 N_205_1 N_163 N_205_2 N_172 N_352_1 N_179 N_352_2 N_184 N_231_i_1 N_185 \ + N_152_i_1 N_196 N_144_i_1 N_203 ipl_c_0__n N_142_i_1 N_204 N_312_i_1 N_209 ipl_c_1__n N_236_i_1 \ + N_214 N_148_i_1 N_215 ipl_c_2__n N_136_i_1 N_216 N_246_0_1 N_218 N_249_i_1 N_224 DTACK_c \ + N_57_i_1 N_332 N_338_1 N_226 N_224_1 N_227 N_216_1 N_229 VPA_c N_209_1 N_337 \ + N_203_1 N_338 N_196_1 N_265 RST_c cpu_est_0_3__un3_n N_267 cpu_est_0_3__un1_n N_268 cpu_est_0_3__un0_n N_275 \ + RW_c rw_000_int_0_un3_n N_278 rw_000_int_0_un1_n N_282 fc_c_0__n rw_000_int_0_un0_n N_284 vma_int_0_un3_n N_340 fc_c_1__n \ + vma_int_0_un1_n N_287 vma_int_0_un0_n N_288 cpu_est_0_1__un3_n N_291 AMIGA_BUS_DATA_DIR_c cpu_est_0_1__un1_n N_293 cpu_est_0_1__un0_n N_350 \ + cpu_est_0_2__un3_n N_355 cpu_est_0_2__un1_n cpu_est_0_2__un0_n N_16_i uds_000_int_0_un3_n N_39_0 uds_000_int_0_un1_n VPA_c_i uds_000_int_0_un0_n N_52_0 \ + lds_000_int_0_un3_n N_156 DTACK_c_i lds_000_int_0_un1_n N_201 N_53_0 lds_000_int_0_un0_n N_202 N_210_i bgack_030_int_0_un3_n N_154 \ + N_211_i bgack_030_int_0_un1_n un21_berr_1 N_189_i bgack_030_int_0_un0_n N_174 un1_SM_AMIGA_0_sqmuxa_1_0 ds_000_enable_0_un3_n N_223 RW_c_i ds_000_enable_0_un1_n \ + N_221 N_311_0 ds_000_enable_0_un0_n N_222 N_336_i size_dma_0_0__un3_n N_219 N_244_i size_dma_0_0__un1_n N_220 size_dma_0_0__un0_n \ + pos_clk_un6_bgack_000_n N_314_0 size_dma_0_1__un3_n N_359 N_159_i size_dma_0_1__un1_n N_8 VMA_INT_i size_dma_0_1__un0_n N_14 N_352_i \ + ipl_030_0_0__un3_n N_21 N_353_i ipl_030_0_0__un1_n N_9 N_293_i ipl_030_0_0__un0_n un1_DS_000_ENABLE_0_sqmuxa N_175_i ipl_030_0_1__un3_n N_66 \ + N_176_i ipl_030_0_1__un1_n N_171 ipl_030_0_1__un0_n N_354 N_198_i ipl_030_0_2__un3_n N_18 N_197_i ipl_030_0_2__un1_n pos_clk_un9_clk_000_pe_n \ + N_196_i ipl_030_0_2__un0_n cpu_est_2_1__n N_183_0 a0_dma_0_un3_n cpu_est_2_2__n N_182_0 a0_dma_0_un1_n N_197 N_180_0 a0_dma_0_un0_n \ + N_198 N_178_0 amiga_bus_enable_dma_low_0_un3_n N_208 N_82_i amiga_bus_enable_dma_low_0_un1_n N_210 N_315_i amiga_bus_enable_dma_low_0_un0_n N_315 N_351_i \ + amiga_bus_enable_dma_high_0_un3_n N_212 N_154_0 amiga_bus_enable_dma_high_0_un1_n N_180 N_149_i amiga_bus_enable_dma_high_0_un0_n N_213 N_207_i bg_000_0_un3_n N_178 \ + N_228_i bg_000_0_un1_n N_228 bg_000_0_un0_n N_182 N_213_i ds_000_dma_0_un3_n N_176 N_212_i ds_000_dma_0_un1_n N_183 \ + N_309_i ds_000_dma_0_un0_n N_351 N_357_i as_000_dma_0_un3_n N_357 cpu_est_2_0_2__n as_000_dma_0_un1_n N_206 N_208_i as_000_dma_0_un0_n \ + N_205 N_209_i as_030_000_sync_0_un3_n N_352 cpu_est_2_0_1__n as_030_000_sync_0_un1_n N_353 N_206_i as_030_000_sync_0_un0_n N_314 N_205_i \ + rw_000_dma_0_un3_n N_244 pos_clk_un9_clk_000_pe_0_n rw_000_dma_0_un1_n N_336 N_18_i rw_000_dma_0_un0_n N_311 N_37_0 a_decode_15__n un1_SM_AMIGA_0_sqmuxa_1 \ + N_171_i N_211 N_354_i a_decode_14__n N_16 un1_DS_000_ENABLE_0_sqmuxa_0 un1_amiga_bus_enable_low_i N_66_0 a_decode_13__n un21_fpu_cs_i UDS_000_INT_i \ + cpu_est_i_2__n un1_UDS_000_INT_0 a_decode_12__n cpu_est_i_0__n LDS_000_INT_i VPA_D_i un1_LDS_000_INT_0 a_decode_11__n DTACK_D0_i N_21_i cpu_est_i_3__n \ + N_34_0 a_decode_10__n sm_amiga_i_i_7__n N_14_i sm_amiga_i_5__n N_41_0 a_decode_9__n sm_amiga_i_3__n N_8_i cpu_est_i_1__n N_42_0 \ + a_decode_8__n clk_000_d_i_1__n a_c_i_0__n N_355_i_0 size_c_i_1__n a_decode_7__n sm_amiga_i_4__n pos_clk_un10_sm_amiga_i_n sm_amiga_i_2__n N_359_i a_decode_6__n \ + rst_dly_i_0__n pos_clk_un6_bgack_000_0_n rst_dly_i_2__n N_220_i a_decode_5__n a_decode_i_19__n N_219_i a_decode_i_18__n a_decode_4__n a_decode_i_16__n N_222_i \ + RW_000_i N_221_i a_decode_3__n sm_amiga_i_0__n AS_030_i N_223_i a_decode_2__n AS_000_INT_i N_224_i DSACK1_INT_i AMIGA_BUS_DATA_DIR_c_0 \ + clk_000_d_i_0__n N_150_i sm_amiga_i_6__n N_156_i sm_amiga_i_1__n N_160_i FPU_SENSE_i N_174_i rst_dly_i_1__n N_158_i AS_030_D0_i \ + N_201_i BGACK_030_INT_i N_202_i nEXP_SPACE_i N_203_i RESET_OUT_i AS_030.OE AS_000.OE RW_000.OE \ + UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE \ + AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE \ + CIIN.OE .names un7_as_030_i.BLIF AS_030 1 1 .names AS_030.PIN AS_030_c 1 1 -.names N_139.BLIF AS_030.OE +.names N_313_i.BLIF AS_030.OE 1 1 -.names N_169_i.BLIF AS_000 +.names N_133_i.BLIF AS_000 1 1 .names AS_000.PIN AS_000_c 1 1 @@ -236,67 +235,67 @@ 1 1 .names SIZE_0_.PIN size_c_0__n 1 1 -.names N_299_i.BLIF SIZE_0_.OE +.names N_186_i.BLIF SIZE_0_.OE 1 1 .names SIZE_DMA_1_.BLIF SIZE_1_ 1 1 .names SIZE_1_.PIN size_c_1__n 1 1 -.names N_299_i.BLIF SIZE_1_.OE +.names N_186_i.BLIF SIZE_1_.OE 1 1 .names gnd_n_n.BLIF AHIGH_24_ 1 1 .names AHIGH_24_.PIN ahigh_c_24__n 1 1 -.names N_139.BLIF AHIGH_24_.OE +.names N_313_i.BLIF AHIGH_24_.OE 1 1 .names gnd_n_n.BLIF AHIGH_25_ 1 1 .names AHIGH_25_.PIN ahigh_c_25__n 1 1 -.names N_139.BLIF AHIGH_25_.OE +.names N_313_i.BLIF AHIGH_25_.OE 1 1 .names gnd_n_n.BLIF AHIGH_26_ 1 1 .names AHIGH_26_.PIN ahigh_c_26__n 1 1 -.names N_139.BLIF AHIGH_26_.OE +.names N_313_i.BLIF AHIGH_26_.OE 1 1 .names gnd_n_n.BLIF AHIGH_27_ 1 1 .names AHIGH_27_.PIN ahigh_c_27__n 1 1 -.names N_139.BLIF AHIGH_27_.OE +.names N_313_i.BLIF AHIGH_27_.OE 1 1 .names gnd_n_n.BLIF AHIGH_28_ 1 1 .names AHIGH_28_.PIN ahigh_c_28__n 1 1 -.names N_139.BLIF AHIGH_28_.OE +.names N_313_i.BLIF AHIGH_28_.OE 1 1 .names gnd_n_n.BLIF AHIGH_29_ 1 1 .names AHIGH_29_.PIN ahigh_c_29__n 1 1 -.names N_139.BLIF AHIGH_29_.OE +.names N_313_i.BLIF AHIGH_29_.OE 1 1 .names gnd_n_n.BLIF AHIGH_30_ 1 1 .names AHIGH_30_.PIN ahigh_c_30__n 1 1 -.names N_139.BLIF AHIGH_30_.OE +.names N_313_i.BLIF AHIGH_30_.OE 1 1 .names gnd_n_n.BLIF AHIGH_31_ 1 1 .names AHIGH_31_.PIN ahigh_c_31__n 1 1 -.names N_139.BLIF AHIGH_31_.OE +.names N_313_i.BLIF AHIGH_31_.OE 1 1 .names inst_A0_DMA.BLIF A_0_ 1 1 .names A_0_.PIN a_c_0__n 1 1 -.names N_139.BLIF A_0_.OE +.names N_313_i.BLIF A_0_.OE 1 1 .names gnd_n_n.BLIF BERR 1 1 @@ -308,13 +307,13 @@ 1 1 .names RW.PIN RW_c 1 1 -.names N_141.BLIF RW.OE +.names un1_rw_i.BLIF RW.OE 1 1 .names un6_ds_030_i.BLIF DS_030 1 1 -.names N_139.BLIF DS_030.OE +.names N_313_i.BLIF DS_030.OE 1 1 -.names N_165_i.BLIF DSACK1 +.names N_132_i.BLIF DSACK1 1 1 .names nEXP_SPACE_c.BLIF DSACK1.OE 1 1 @@ -324,1344 +323,1337 @@ 1 1 .names un10_ciin.BLIF CIIN 1 1 -.names N_260.BLIF CIIN.OE +.names N_62.BLIF CIIN.OE 1 1 -.names N_161_i_4.BLIF N_161_i_3.BLIF N_161_i +.names N_156_i_1.BLIF N_156_i_2.BLIF N_156_i_4 11 1 -.names pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un3_n +.names a_decode_c_19__n.BLIF a_decode_i_19__n 0 1 -.names N_213_i.BLIF N_214_i.BLIF N_233_i_1 +.names N_156_i_4.BLIF N_156_i_3.BLIF N_156_i 11 1 -.names cpu_est_i_1__n.BLIF pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un1_n -11 1 -.names N_215_i.BLIF RST_c.BLIF N_233_i_2 -11 1 -.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n -11 1 -.names N_233_i_1.BLIF N_233_i_2.BLIF RST_DLY_1_.D -11 1 -.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF N_18 -1- 1 --1 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C -1 1 -.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_180_i_1 -11 1 -.names N_18_i.BLIF RST_c.BLIF N_37_0 -11 1 -.names N_345_i.BLIF pos_clk_un21_bgack_030_int_i_i_a2_i_x2.BLIF N_180_i_2 -11 1 -.names N_305.BLIF cpu_est_0_1__un3_n +.names a_decode_c_18__n.BLIF a_decode_i_18__n 0 1 -.names N_180_i_1.BLIF N_180_i_2.BLIF N_180_i -11 1 -.names cpu_est_1_.BLIF N_305.BLIF cpu_est_0_1__un1_n -11 1 -.names size_c_0__n.BLIF a_c_i_0__n.BLIF pos_clk_un10_sm_amiga_i_1_n -11 1 -.names cpu_est_2_1__n.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C -1 1 -.names pos_clk_un10_sm_amiga_i_1_n.BLIF size_c_i_1__n.BLIF pos_clk_un10_sm_amiga_i_n -11 1 -.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D -1- 1 --1 1 -.names N_188.BLIF N_305_i.BLIF N_196_0_1 -11 1 -.names N_305.BLIF cpu_est_0_2__un3_n -0 1 -.names N_196_0_1.BLIF SM_AMIGA_3_.BLIF N_196_0 -11 1 -.names cpu_est_2_.BLIF N_305.BLIF cpu_est_0_2__un1_n -11 1 -.names BERR_c.BLIF N_347_i.BLIF N_188_i_1 -11 1 -.names cpu_est_2_2__n.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C -1 1 -.names N_188_i_1.BLIF N_348_i.BLIF N_188_i -11 1 -.names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D -1- 1 --1 1 -.names N_19.BLIF N_19_i -0 1 -.names CLK_000_D_3_.BLIF clk_000_d_i_2__n.BLIF N_157_i -11 1 -.names N_36_0.BLIF inst_RW_000_DMA.D -0 1 -.names N_159.BLIF N_350.BLIF N_209 -11 1 -.names N_20.BLIF N_20_i -0 1 -.names RST_DLY_2_.BLIF rst_dly_i_2__n -0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C -1 1 -.names N_35_0.BLIF inst_A0_DMA.D -0 1 -.names N_305.BLIF rst_dly_i_2__n.BLIF N_211 -11 1 -.names N_22.BLIF N_22_i -0 1 -.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_220 -11 1 -.names N_33_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D -0 1 -.names AS_000_DMA_i.BLIF AS_000_i.BLIF un7_as_030 -11 1 -.names N_23.BLIF N_23_i -0 1 -.names inst_CLK_030_H.BLIF CLK_030_H_i -0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C -1 1 -.names N_32_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D -0 1 -.names CLK_030_H_i.BLIF N_198.BLIF N_290 -11 1 -.names N_24.BLIF N_24_i -0 1 -.names RW_000_c.BLIF RW_000_i -0 1 -.names N_31_0.BLIF BG_000DFFreg.D -0 1 -.names inst_AS_000_DMA.BLIF RW_000_i.BLIF N_291 -11 1 -.names BG_030_c.BLIF BG_030_c_i -0 1 -.names inst_CLK_030_H.BLIF CLK_030_c.BLIF N_292 -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C -1 1 -.names pos_clk_un6_bg_030_n.BLIF pos_clk_un6_bg_030_i_n -0 1 -.names AS_000_c.BLIF N_155_i.BLIF N_353 -11 1 -.names pos_clk_un9_bg_030_0_n.BLIF pos_clk_un9_bg_030_n -0 1 -.names AS_030_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_i.BLIF N_65_0 -11 1 -.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_161_i_1 -11 1 -.names BGACK_000_c.BLIF N_353_i.BLIF pos_clk_un6_bgack_000_0_n -11 1 -.names a_decode_c_17__n.BLIF a_decode_i_16__n.BLIF N_161_i_2 -11 1 -.names N_248_i.BLIF N_256_i.BLIF AMIGA_BUS_DATA_DIR_c_0 -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C -1 1 -.names N_270.BLIF N_270_i -0 1 -.names N_180_i.BLIF N_291_i.BLIF N_301_0 -11 1 -.names N_269.BLIF N_269_i -0 1 -.names CLK_030_c_i.BLIF N_180_i.BLIF N_303_0 -11 1 -.names N_267.BLIF N_267_i -0 1 -.names CLK_000_D_0_.BLIF clk_000_d_i_0__n -0 1 -.names N_324.BLIF N_324_i -0 1 -.names CLK_000_D_0_.BLIF clk_000_d_i_1__n.BLIF N_155_i -11 1 -.names CLK_OSZI_c.BLIF cpu_est_3_.C -1 1 -.names un1_SM_AMIGA_0_sqmuxa_1_0.BLIF un1_SM_AMIGA_0_sqmuxa_1 -0 1 -.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n -0 1 -.names N_319.BLIF N_319_i -0 1 -.names N_302.BLIF ds_000_dma_0_un3_n -0 1 -.names N_320.BLIF N_320_i -0 1 -.names N_301.BLIF N_302.BLIF ds_000_dma_0_un1_n -11 1 -.names RW_c.BLIF RW_c_i -0 1 -.names inst_DS_000_DMA.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n -11 1 -.names CLK_OSZI_c.BLIF IPL_030DFF_0_reg.C -1 1 -.names pos_clk_rw_000_int_5_0_n.BLIF pos_clk_rw_000_int_5_n -0 1 -.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3 -1- 1 --1 1 -.names N_227.BLIF N_227_i -0 1 -.names N_303.BLIF as_000_dma_0_un3_n -0 1 -.names N_297_0.BLIF N_297 -0 1 -.names N_180.BLIF N_303.BLIF as_000_dma_0_un1_n -11 1 -.names N_15.BLIF N_15_i -0 1 -.names inst_AS_000_DMA.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n -11 1 -.names CLK_OSZI_c.BLIF IPL_030DFF_1_reg.C -1 1 -.names N_40_0.BLIF inst_AS_030_000_SYNC.D -0 1 -.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF N_4 -1- 1 --1 1 -.names N_16.BLIF N_16_i -0 1 -.names pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n -0 1 -.names N_39_0.BLIF inst_RW_000_INT.D -0 1 -.names BGACK_000_c.BLIF pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n -11 1 -.names N_339.BLIF N_339_i -0 1 -.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un0_n -11 1 -.names CLK_OSZI_c.BLIF IPL_030DFF_2_reg.C -1 1 -.names N_335.BLIF N_335_i -0 1 -.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF N_8 -1- 1 --1 1 -.names N_336.BLIF N_336_i -0 1 -.names N_65.BLIF ds_000_enable_0_un3_n -0 1 -.names N_334.BLIF N_334_i -0 1 -.names un1_DS_000_ENABLE_0_sqmuxa.BLIF N_65.BLIF ds_000_enable_0_un1_n -11 1 -.names pos_clk_size_dma_6_0_1__n.BLIF pos_clk_size_dma_6_1__n -0 1 -.names inst_DS_000_ENABLE.BLIF ds_000_enable_0_un3_n.BLIF ds_000_enable_0_un0_n -11 1 -.names CLK_OSZI_c.BLIF IPL_D0_0_.C -1 1 -.names N_333.BLIF N_333_i -0 1 -.names ds_000_enable_0_un1_n.BLIF ds_000_enable_0_un0_n.BLIF N_9 -1- 1 --1 1 -.names pos_clk_size_dma_6_0_0__n.BLIF pos_clk_size_dma_6_0__n -0 1 -.names N_9.BLIF RST_c.BLIF inst_DS_000_ENABLE.D -11 1 -.names N_295.BLIF N_295_i -0 1 -.names N_8_i.BLIF RST_c.BLIF N_42_0 -11 1 -.names N_332.BLIF N_332_i -0 1 -.names N_4_i.BLIF RST_c.BLIF N_44_0 -11 1 .names CLK_OSZI_c.BLIF IPL_D0_1_.C 1 1 -.names N_292.BLIF N_292_i -0 1 -.names N_3_i.BLIF RST_c.BLIF N_45_0 +.names size_c_0__n.BLIF a_c_i_0__n.BLIF pos_clk_un10_sm_amiga_i_1_n 11 1 -.names N_302_0.BLIF N_302 -0 1 -.names CYCLE_DMA_0_.BLIF N_155_i.BLIF N_217 +.names N_8_i.BLIF RST_c.BLIF N_42_0 11 1 -.names N_300_0.BLIF N_300 -0 1 -.names CYCLE_DMA_0_.BLIF cycle_dma_i_0__n -0 1 -.names N_290.BLIF N_290_i -0 1 -.names cycle_dma_i_0__n.BLIF N_155.BLIF N_216 +.names pos_clk_un10_sm_amiga_i_1_n.BLIF size_c_i_1__n.BLIF pos_clk_un10_sm_amiga_i_n +11 1 +.names N_14_i.BLIF RST_c.BLIF N_41_0 +11 1 +.names BERR_c.BLIF N_352_i.BLIF N_176_i_1 +11 1 +.names N_21_i.BLIF RST_c.BLIF N_34_0 +11 1 +.names N_176_i_1.BLIF N_353_i.BLIF N_176_i +11 1 +.names inst_DS_000_ENABLE.BLIF LDS_000_INT_i.BLIF un1_LDS_000_INT_0 11 1 .names CLK_OSZI_c.BLIF IPL_D0_2_.C 1 1 -.names N_273.BLIF N_273_i -0 1 -.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_248 +.names ahigh_i_24__n.BLIF ahigh_i_25__n.BLIF un10_ciin_1 11 1 -.names N_327.BLIF N_327_i -0 1 -.names N_155_i.BLIF sm_amiga_i_1__n.BLIF N_324 -11 1 -.names N_213.BLIF N_213_i -0 1 -.names N_155_i.BLIF SM_AMIGA_0_.BLIF N_275 -11 1 -.names N_214.BLIF N_214_i -0 1 -.names inst_AS_000_DMA.BLIF AS_000_DMA_i -0 1 -.names CLK_OSZI_c.BLIF CLK_000_D_0_.C -1 1 -.names N_215.BLIF N_215_i -0 1 -.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF un1_as_000_i -11 1 -.names N_199_i.BLIF N_199 -0 1 -.names BGACK_030_INT_i.BLIF inst_RESET_OUT.BLIF N_141 -11 1 -.names N_191_0.BLIF N_191 -0 1 -.names N_166_i.BLIF RW_c.BLIF N_349 -11 1 -.names CLK_000_D_0_.BLIF CLK_000_D_1_.D -1 1 -.names N_275.BLIF N_275_i -0 1 -.names LDS_000_c.BLIF UDS_000_c.BLIF N_345 -11 1 -.names LDS_000_c.BLIF LDS_000_c_i -0 1 -.names N_181.BLIF sm_amiga_i_3__n.BLIF N_339 -11 1 -.names CLK_OSZI_c.BLIF CLK_000_D_1_.C -1 1 -.names UDS_000_c.BLIF UDS_000_c_i -0 1 -.names N_141.BLIF nEXP_SPACE_i.BLIF N_139 -11 1 -.names N_184_i.BLIF N_184 -0 1 -.names inst_RESET_OUT.BLIF RST_c.BLIF N_229 -11 1 -.names CLK_000_D_4_.BLIF clk_000_d_i_4__n -0 1 -.names N_14_i.BLIF RST_c.BLIF N_41_0 -11 1 -.names CLK_000_D_1_.BLIF CLK_000_D_2_.D -1 1 -.names N_171_i.BLIF N_171 -0 1 -.names N_21_i.BLIF RST_c.BLIF N_34_0 -11 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i -0 1 -.names inst_DS_000_ENABLE.BLIF LDS_000_INT_i.BLIF un1_LDS_000_INT_0 -11 1 -.names CLK_OSZI_c.BLIF CLK_000_D_2_.C -1 1 -.names N_161_i.BLIF N_161 -0 1 .names inst_DS_000_ENABLE.BLIF UDS_000_INT_i.BLIF un1_UDS_000_INT_0 11 1 -.names N_113_0.BLIF N_113 -0 1 +.names ahigh_i_26__n.BLIF ahigh_i_27__n.BLIF un10_ciin_2 +11 1 .names SM_AMIGA_6_.BLIF uds_000_int_0_un3_n 0 1 -.names N_338.BLIF N_338_i -0 1 +.names ahigh_i_28__n.BLIF ahigh_i_29__n.BLIF un10_ciin_3 +11 1 .names a_c_0__n.BLIF SM_AMIGA_6_.BLIF uds_000_int_0_un1_n 11 1 -.names CLK_000_D_2_.BLIF CLK_000_D_3_.D -1 1 -.names size_c_1__n.BLIF size_c_i_1__n -0 1 +.names ahigh_i_30__n.BLIF ahigh_i_31__n.BLIF un10_ciin_4 +11 1 .names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n 11 1 -.names un10_ciin.BLIF un10_ciin_i -0 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_i_7_.C +1 1 +.names a_decode_c_23__n.BLIF AS_030_D0_i.BLIF un10_ciin_5 +11 1 .names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_21 1- 1 -1 1 -.names CLK_OSZI_c.BLIF CLK_000_D_3_.C -1 1 -.names N_260_0.BLIF N_260 -0 1 +.names a_decode_c_20__n.BLIF a_decode_c_21__n.BLIF un10_ciin_6 +11 1 .names SM_AMIGA_6_.BLIF lds_000_int_0_un3_n 0 1 -.names N_229.BLIF N_229_i -0 1 +.names un10_ciin_1.BLIF un10_ciin_2.BLIF un10_ciin_7 +11 1 .names pos_clk_un10_sm_amiga_i_n.BLIF SM_AMIGA_6_.BLIF lds_000_int_0_un1_n 11 1 -.names N_230.BLIF N_230_i +.names N_36_0.BLIF inst_RW_000_DMA.D 0 1 .names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n 11 1 -.names CLK_000_D_3_.BLIF CLK_000_D_4_.D +.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C 1 1 -.names N_298_0.BLIF inst_RESET_OUT.D +.names N_20.BLIF N_20_i 0 1 .names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF N_14 1- 1 -1 1 -.names N_48_0.BLIF inst_AS_030_D0.D +.names N_35_0.BLIF inst_A0_DMA.D 0 1 -.names inst_DS_000_DMA.BLIF DS_000_DMA_i +.names pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n 0 1 -.names CLK_OSZI_c.BLIF CLK_000_D_4_.C +.names N_25.BLIF N_25_i +0 1 +.names BGACK_000_c.BLIF pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n +11 1 +.names N_30_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D +0 1 +.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un0_n +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C 1 1 -.names N_345.BLIF N_345_i +.names N_26.BLIF N_26_i 0 1 -.names AS_000_i.BLIF DS_000_DMA_i.BLIF un6_ds_030 +.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF N_8 +1- 1 +-1 1 +.names N_29_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D +0 1 +.names N_66.BLIF ds_000_enable_0_un3_n +0 1 +.names N_27.BLIF N_27_i +0 1 +.names un1_DS_000_ENABLE_0_sqmuxa.BLIF N_66.BLIF ds_000_enable_0_un1_n 11 1 -.names N_349.BLIF N_349_i +.names N_28_0.BLIF BG_000DFFreg.D 0 1 -.names N_197.BLIF sm_amiga_i_4__n.BLIF N_270 +.names inst_DS_000_ENABLE.BLIF ds_000_enable_0_un3_n.BLIF ds_000_enable_0_un0_n 11 1 -.names un1_DS_000_ENABLE_0_sqmuxa_i.BLIF un1_DS_000_ENABLE_0_sqmuxa -0 1 -.names RST_DLY_1_.BLIF rst_dly_i_1__n -0 1 -.names CLK_000_D_4_.BLIF CLK_000_D_5_.D +.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C 1 1 -.names N_180_i.BLIF N_180 +.names BG_030_c.BLIF BG_030_c_i 0 1 -.names N_186_i.BLIF rst_dly_i_1__n.BLIF N_214 -11 1 -.names N_181_i.BLIF N_181 +.names ds_000_enable_0_un1_n.BLIF ds_000_enable_0_un0_n.BLIF N_9 +1- 1 +-1 1 +.names pos_clk_un9_bg_030_0_n.BLIF pos_clk_un9_bg_030_n 0 1 -.names N_159.BLIF N_163_i.BLIF N_213 +.names N_9.BLIF RST_c.BLIF inst_DS_000_ENABLE.D 11 1 -.names CLK_OSZI_c.BLIF CLK_000_D_5_.C +.names N_201_i.BLIF N_202_i.BLIF N_235_i_1 +11 1 +.names N_219_i.BLIF N_220_i.BLIF inst_DSACK1_INT.D +11 1 +.names N_203_i.BLIF RST_c.BLIF N_235_i_2 +11 1 +.names BGACK_000_c.BLIF N_359_i.BLIF pos_clk_un6_bgack_000_0_n +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C 1 1 -.names N_326.BLIF N_326_i -0 1 -.names FPU_SENSE_c.BLIF FPU_SENSE_i -0 1 -.names N_163_i.BLIF N_163 -0 1 -.names AS_030_i.BLIF BGACK_000_c.BLIF un21_berr_1 +.names N_235_i_1.BLIF N_235_i_2.BLIF RST_DLY_1_.D 11 1 -.names N_197_0.BLIF N_197 +.names AS_000_c.BLIF N_150_i.BLIF N_359 +11 1 +.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_156_i_1 +11 1 +.names inst_DSACK1_INT.BLIF DSACK1_INT_i 0 1 -.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n +.names N_214.BLIF N_214_i +0 1 +.names AS_030_i.BLIF DSACK1_INT_i.BLIF N_132 +11 1 +.names N_310_0.BLIF N_310 +0 1 +.names AS_030_c.BLIF AS_030_i +0 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C +1 1 +.names N_24.BLIF N_24_i +0 1 +.names inst_AS_000_INT.BLIF AS_000_INT_i +0 1 +.names N_33_0.BLIF IPL_030DFF_2_reg.D +0 1 +.names AS_000_INT_i.BLIF AS_030_i.BLIF N_133 +11 1 +.names N_23.BLIF N_23_i +0 1 +.names N_150_i.BLIF SM_AMIGA_0_.BLIF N_293 +11 1 +.names N_32_0.BLIF IPL_030DFF_1_reg.D +0 1 +.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n +0 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C +1 1 +.names N_22.BLIF N_22_i +0 1 +.names N_174.BLIF sm_amiga_i_0__n.BLIF N_227 +11 1 +.names N_31_0.BLIF IPL_030DFF_0_reg.D +0 1 +.names RW_000_c.BLIF RW_000_i 0 1 .names N_3.BLIF N_3_i 0 1 -.names N_155_i.BLIF SM_AMIGA_4_.BLIF N_181_i +.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_223 11 1 -.names CLK_OSZI_c.BLIF CYCLE_DMA_0_.C -1 1 .names N_45_0.BLIF inst_DS_000_DMA.D 0 1 -.names N_181.BLIF N_349_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_i +.names N_160_i.BLIF RST_c.BLIF N_222 11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C +1 1 .names N_4.BLIF N_4_i 0 1 +.names N_133.BLIF RST_c.BLIF N_221 +11 1 .names N_44_0.BLIF inst_AS_000_DMA.D 0 1 -.names BGACK_030_INT_i.BLIF nEXP_SPACE_i.BLIF N_299_i +.names RST_DLY_0_.BLIF RST_DLY_1_.BLIF N_158_i 11 1 -.names N_8.BLIF N_8_i +.names N_15.BLIF N_15_i 0 1 -.names AS_030_i.BLIF RST_c.BLIF N_48_0 +.names N_158_i.BLIF RST_DLY_2_.BLIF N_355 11 1 -.names CLK_OSZI_c.BLIF CYCLE_DMA_1_.C -1 1 -.names N_42_0.BLIF inst_BGACK_030_INTreg.D +.names N_40_0.BLIF inst_AS_030_000_SYNC.D 0 1 -.names N_229_i.BLIF N_230_i.BLIF N_298_0 -11 1 -.names inst_UDS_000_INT.BLIF UDS_000_INT_i -0 1 -.names nEXP_SPACE_i.BLIF un10_ciin_i.BLIF N_260_0 -11 1 -.names un1_UDS_000_INT_0.BLIF un1_UDS_000_INT -0 1 -.names inst_RESET_OUT.BLIF RESET_OUT_i -0 1 -.names inst_LDS_000_INT.BLIF LDS_000_INT_i -0 1 -.names N_275_i.BLIF SM_AMIGA_i_7_.BLIF N_187_0 -11 1 -.names CLK_OSZI_c.BLIF SIZE_DMA_0_.C -1 1 -.names un1_LDS_000_INT_0.BLIF un1_LDS_000_INT -0 1 -.names N_171_i.BLIF sm_amiga_i_i_7__n.BLIF N_191_0 -11 1 -.names N_21.BLIF N_21_i -0 1 -.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF N_199_i -11 1 -.names N_34_0.BLIF inst_UDS_000_INT.D -0 1 -.names inst_BGACK_030_INTreg.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un3_n -0 1 -.names N_14.BLIF N_14_i -0 1 -.names inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INTreg.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un1_n -11 1 -.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C -1 1 -.names N_41_0.BLIF inst_LDS_000_INT.D -0 1 -.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un3_n.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un0_n -11 1 -.names a_c_0__n.BLIF a_c_i_0__n -0 1 -.names un1_amiga_bus_enable_dma_high_i_m2_0__un1_n.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un0_n.BLIF N_205 -1- 1 --1 1 -.names N_217.BLIF N_217_i -0 1 -.names inst_AS_030_D0.BLIF AS_030_D0_i -0 1 -.names N_216.BLIF N_216_i -0 1 -.names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n +.names RST_DLY_1_.BLIF rst_dly_i_1__n 0 1 .names CLK_OSZI_c.BLIF cpu_est_0_.C 1 1 -.names CLK_030_c.BLIF CLK_030_c_i +.names N_19.BLIF N_19_i 0 1 -.names N_305_i.BLIF SM_AMIGA_5_.BLIF N_197_0 +.names N_82_i.BLIF rst_dly_i_1__n.BLIF N_202 11 1 -.names N_198_0.BLIF N_198 +.names N_55_0.BLIF inst_RESET_OUT.D 0 1 -.names RST_DLY_0_.BLIF RST_DLY_1_.BLIF N_163_i +.names N_154.BLIF N_158_i.BLIF N_201 11 1 -.names N_166_i.BLIF N_166 +.names N_245_0.BLIF N_245 0 1 -.names N_305.BLIF RST_c.BLIF N_186_i -11 1 -.names N_155_i.BLIF N_155 +.names FPU_SENSE_c.BLIF FPU_SENSE_i 0 1 -.names N_186_i.BLIF N_326_i.BLIF SM_AMIGA_5_.D +.names N_229.BLIF N_229_i +0 1 +.names AS_030_i.BLIF BGACK_000_c.BLIF un21_berr_1 11 1 .names CLK_OSZI_c.BLIF cpu_est_1_.C 1 1 -.names N_303_0.BLIF N_303 +.names N_227.BLIF N_227_i 0 1 -.names N_163_i.BLIF RST_DLY_2_.BLIF N_350 +.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n +0 1 +.names N_226.BLIF N_226_i +0 1 +.names N_149_i.BLIF SM_AMIGA_1_.BLIF N_174_i +11 1 +.names N_246_0.BLIF N_246 +0 1 +.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n +0 1 +.names N_332.BLIF N_332_i +0 1 +.names N_150_i.BLIF SM_AMIGA_6_.BLIF N_160_i +11 1 +.names CLK_OSZI_c.BLIF cpu_est_2_.C +1 1 +.names pos_clk_ds_000_dma_4_0_n.BLIF pos_clk_ds_000_dma_4_n +0 1 +.names CLK_000_D_0_.BLIF clk_000_d_i_0__n +0 1 +.names N_48_0.BLIF inst_AS_030_D0.D +0 1 +.names CLK_000_D_0_.BLIF clk_000_d_i_1__n.BLIF N_150_i +11 1 +.names pos_clk_rw_000_dma_3_0_n.BLIF pos_clk_rw_000_dma_3_n +0 1 +.names N_223_i.BLIF N_224_i.BLIF AMIGA_BUS_DATA_DIR_c_0 +11 1 +.names N_218.BLIF N_218_i +0 1 +.names N_221_i.BLIF N_222_i.BLIF inst_AS_000_INT.D +11 1 +.names CLK_OSZI_c.BLIF cpu_est_3_.C +1 1 +.names un10_ciin.BLIF un10_ciin_i +0 1 +.names BGACK_030_INT_i.BLIF inst_RESET_OUT.BLIF un1_rw_i +11 1 +.names N_62_0.BLIF N_62 +0 1 +.names N_215.BLIF N_215_i +0 1 +.names nEXP_SPACE_c.BLIF nEXP_SPACE_i +0 1 +.names N_216.BLIF N_216_i +0 1 +.names LDS_000_c_i.BLIF UDS_000_c_i.BLIF N_172_i +11 1 +.names CLK_OSZI_c.BLIF IPL_030DFF_0_reg.C +1 1 +.names N_126_0.BLIF N_126 +0 1 +.names BGACK_030_INT_i.BLIF RST_c.BLIF N_251_i +11 1 +.names N_231_i.BLIF N_231 +0 1 +.names N_163_i.BLIF sm_amiga_i_i_7__n.BLIF N_179_0 11 1 .names N_291.BLIF N_291_i 0 1 -.names RST_DLY_0_.BLIF rst_dly_i_0__n -0 1 -.names N_301_0.BLIF N_301 -0 1 -.names N_186_i.BLIF rst_dly_i_0__n.BLIF N_332 +.names AS_000_DMA_i.BLIF CLK_030_c_i.BLIF N_184_0 11 1 -.names N_256.BLIF N_256_i +.names N_288.BLIF N_288_i 0 1 -.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i 0 1 -.names CLK_OSZI_c.BLIF cpu_est_2_.C +.names CLK_OSZI_c.BLIF IPL_030DFF_1_reg.C 1 1 -.names N_248.BLIF N_248_i +.names N_287.BLIF N_287_i 0 1 -.names N_166.BLIF sm_amiga_i_5__n.BLIF N_326 +.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF N_185_i +11 1 +.names N_340.BLIF N_340_i +0 1 +.names BGACK_030_INT_i.BLIF nEXP_SPACE_i.BLIF N_186_i +11 1 +.names N_284.BLIF N_284_i +0 1 +.names N_275.BLIF N_275_i +0 1 +.names CLK_OSZI_c.BLIF IPL_030DFF_2_reg.C +1 1 +.names pos_clk_size_dma_6_0_1__n.BLIF pos_clk_size_dma_6_1__n +0 1 +.names N_268.BLIF N_268_i +0 1 +.names pos_clk_size_dma_6_0_0__n.BLIF pos_clk_size_dma_6_0__n +0 1 +.names inst_AS_030_D0.BLIF AS_030_D0_i +0 1 +.names N_265.BLIF N_265_i +0 1 +.names LDS_000_c.BLIF UDS_000_c.BLIF N_350 +11 1 +.names CLK_OSZI_c.BLIF RST_DLY_2_.C +1 1 +.names N_267.BLIF N_267_i +0 1 +.names AS_030_i.BLIF N_214_i.BLIF N_310_0 +11 1 +.names N_337.BLIF N_337_i +0 1 +.names N_215_i.BLIF N_216_i.BLIF un10_amiga_bus_enable_high_i +11 1 +.names N_338.BLIF N_338_i +0 1 +.names nEXP_SPACE_i.BLIF un10_ciin_i.BLIF N_62_0 +11 1 +.names N_204.BLIF N_204_i +0 1 +.names BGACK_030_INT_i.BLIF RW_000_i.BLIF pos_clk_rw_000_dma_3_0_n +11 1 +.names CLK_OSZI_c.BLIF CLK_000_D_0_.C +1 1 +.names N_282.BLIF N_282_i +0 1 +.names AS_030_i.BLIF RST_c.BLIF N_48_0 +11 1 +.names N_278.BLIF N_278_i +0 1 +.names N_332_i.BLIF pos_clk_un21_bgack_030_int_i_0_0_n.BLIF pos_clk_ds_000_dma_4_0_n +11 1 +.names N_185_i.BLIF N_185 +0 1 +.names CLK_030_c_i.BLIF pos_clk_un21_bgack_030_int_i_0_0_n.BLIF N_245_0 +11 1 +.names CLK_000_D_0_.BLIF CLK_000_D_1_.D +1 1 +.names CLK_030_c.BLIF CLK_030_c_i +0 1 +.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF un1_as_000_i +11 1 +.names N_184_0.BLIF N_184 +0 1 +.names N_337_i.BLIF N_338_i.BLIF N_55_0 +11 1 +.names CLK_OSZI_c.BLIF CLK_000_D_1_.C +1 1 +.names N_179_0.BLIF N_179 +0 1 +.names N_268_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n +11 1 +.names N_251_i.BLIF inst_BGACK_030_INT_D.D +0 1 +.names N_275_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n +11 1 +.names LDS_000_c.BLIF LDS_000_c_i +0 1 +.names N_186_i.BLIF inst_RESET_OUT.BLIF N_313_i +11 1 +.names CLK_000_D_1_.BLIF CLK_000_D_2_.D +1 1 +.names UDS_000_c.BLIF UDS_000_c_i +0 1 +.names N_185_i.BLIF RST_c.BLIF N_126_0 +11 1 +.names N_172_i.BLIF N_172 +0 1 +.names inst_RESET_OUT.BLIF RESET_OUT_i +0 1 +.names CLK_OSZI_c.BLIF CLK_000_D_2_.C +1 1 +.names pos_clk_un21_bgack_030_int_i_0_0_n.BLIF pos_clk_un21_bgack_030_int_i_0_n +0 1 +.names BGACK_030_INT_i.BLIF N_172.BLIF N_268 +11 1 +.names N_163_i.BLIF N_163 +0 1 +.names BGACK_030_INT_i.BLIF N_172_i.BLIF N_275 +11 1 +.names CLK_000_D_3_.BLIF clk_000_d_i_3__n +0 1 +.names N_150.BLIF SM_AMIGA_2_.BLIF N_278 +11 1 +.names N_350.BLIF N_350_i +0 1 +.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_282 +11 1 +.names CLK_OSZI_c.BLIF CLK_000_D_3_.C +1 1 +.names N_224.BLIF N_224_i +0 1 +.names N_163.BLIF sm_amiga_i_i_7__n.BLIF N_291 11 1 .names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c 0 1 .names BGACK_030_INT_i.BLIF UDS_000_c.BLIF pos_clk_a0_dma_3_n 11 1 -.names N_353.BLIF N_353_i +.names N_150_i.BLIF N_150 0 1 .names a_c_1__n.BLIF a_i_1__n 0 1 -.names pos_clk_un6_bgack_000_0_n.BLIF pos_clk_un6_bgack_000_n -0 1 -.names a_i_1__n.BLIF BGACK_030_INT_i.BLIF N_79 -11 1 -.names CLK_OSZI_c.BLIF RST_DLY_0_.C +.names CLK_000_D_3_.BLIF CLK_000_D_4_.D 1 1 -.names N_65_0.BLIF N_65 +.names N_156_i.BLIF N_156 0 1 -.names a_c_1__n.BLIF BGACK_030_INT_i.BLIF N_78 +.names a_i_1__n.BLIF BGACK_030_INT_i.BLIF N_115 11 1 -.names N_159_0.BLIF N_159 +.names N_160_i.BLIF N_160 0 1 -.names inst_AS_000_INT.BLIF AS_000_INT_i -0 1 -.names N_305_i.BLIF N_305 -0 1 -.names AS_000_INT_i.BLIF AS_030_i.BLIF N_169 +.names a_c_1__n.BLIF BGACK_030_INT_i.BLIF N_114 11 1 -.names N_225.BLIF N_225_i -0 1 -.names AS_030_i.BLIF N_227_i.BLIF N_297_0 -11 1 -.names CLK_OSZI_c.BLIF RST_DLY_1_.C +.names CLK_OSZI_c.BLIF CLK_000_D_4_.C 1 1 -.names N_224.BLIF N_224_i +.names N_174_i.BLIF N_174 0 1 -.names N_187_0.BLIF RW_c_i.BLIF pos_clk_rw_000_int_5_0_n -11 1 -.names N_352.BLIF N_352_i +.names ipl_c_0__n.BLIF ipl_i_0__n 0 1 -.names N_319_i.BLIF N_320_i.BLIF inst_AS_000_INT.D -11 1 -.names cpu_est_2_0_2__n.BLIF cpu_est_2_2__n +.names N_158_i.BLIF N_158 0 1 -.names N_166.BLIF N_187_0.BLIF un1_SM_AMIGA_0_sqmuxa_1_0 +.names ipl_i_0__n.BLIF RST_c.BLIF N_113 11 1 -.names N_220.BLIF N_220_i +.names N_201.BLIF N_201_i 0 1 -.names BGACK_030_INT_i.BLIF RW_000_i.BLIF N_300_0 +.names ipl_c_1__n.BLIF ipl_i_1__n +0 1 +.names N_202.BLIF N_202_i +0 1 +.names ipl_i_1__n.BLIF RST_c.BLIF N_112 11 1 -.names CLK_OSZI_c.BLIF RST_DLY_2_.C +.names CLK_OSZI_c.BLIF CYCLE_DMA_0_.C 1 1 -.names N_221.BLIF N_221_i +.names N_203.BLIF N_203_i 0 1 -.names N_333_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n +.names ipl_c_2__n.BLIF ipl_i_2__n +0 1 +.names N_233_0.BLIF N_233 +0 1 +.names ipl_i_2__n.BLIF RST_c.BLIF N_111 11 1 -.names cpu_est_2_0_1__n.BLIF cpu_est_2_1__n -0 1 -.names N_334_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n -11 1 -.names N_219.BLIF N_219_i -0 1 -.names N_199_i.BLIF RST_c.BLIF N_113_0 -11 1 -.names N_218.BLIF N_218_i -0 1 -.names LDS_000_c_i.BLIF UDS_000_c_i.BLIF N_184_i -11 1 -.names CLK_OSZI_c.BLIF inst_DS_000_DMA.C -1 1 -.names pos_clk_un9_clk_000_pe_0_n.BLIF pos_clk_un9_clk_000_pe_n -0 1 -.names ahigh_c_26__n.BLIF ahigh_i_26__n -0 1 -.names CLK_000_D_2_.BLIF clk_000_d_i_2__n -0 1 -.names ahigh_c_27__n.BLIF ahigh_i_27__n -0 1 -.names N_18.BLIF N_18_i -0 1 -.names ahigh_c_28__n.BLIF ahigh_i_28__n -0 1 -.names N_37_0.BLIF inst_VMA_INTreg.D -0 1 -.names ahigh_c_29__n.BLIF ahigh_i_29__n -0 1 -.names CLK_OSZI_c.BLIF inst_DSACK1_INT.C -1 1 -.names inst_VMA_INTreg.BLIF VMA_INT_i -0 1 -.names ahigh_c_30__n.BLIF ahigh_i_30__n -0 1 -.names A_DECODE_16_.BLIF a_decode_c_16__n -1 1 -.names N_347.BLIF N_347_i +.names pos_clk_un1_ipl_i_0_x2.BLIF N_360_i 0 1 .names ahigh_c_31__n.BLIF ahigh_i_31__n 0 1 -.names A_DECODE_17_.BLIF a_decode_c_17__n +.names pos_clk_un1_ipl_i_0_x2_0.BLIF N_191_i_i +0 1 +.names CYCLE_DMA_0_.BLIF cycle_dma_i_0__n +0 1 +.names CLK_OSZI_c.BLIF CYCLE_DMA_1_.C 1 1 -.names N_348.BLIF N_348_i +.names pos_clk_un1_ipl_i_0_x2_1.BLIF N_192_i_i 0 1 -.names a_decode_c_18__n.BLIF a_decode_i_18__n -0 1 -.names A_DECODE_18_.BLIF a_decode_c_18__n -1 1 -.names N_188_i.BLIF N_188 -0 1 -.names a_decode_c_19__n.BLIF a_decode_i_19__n -0 1 -.names CLK_OSZI_c.BLIF inst_AS_000_INT.C -1 1 -.names A_DECODE_19_.BLIF a_decode_c_19__n -1 1 -.names N_245_0.BLIF inst_BGACK_030_INT_D.D -0 1 -.names a_decode_c_16__n.BLIF a_decode_i_16__n -0 1 -.names A_DECODE_20_.BLIF a_decode_c_20__n -1 1 -.names N_194_0.BLIF N_194 -0 1 -.names N_169.BLIF RST_c.BLIF N_319 +.names cycle_dma_i_0__n.BLIF N_150.BLIF N_204 11 1 -.names A_DECODE_21_.BLIF a_decode_c_21__n -1 1 -.names N_196_0.BLIF N_196 +.names N_199.BLIF N_199_i 0 1 -.names N_166_i.BLIF RST_c.BLIF N_320 -11 1 -.names A_DECODE_22_.BLIF a_decode_c_22__n -1 1 -.names N_211.BLIF N_211_i +.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i 0 1 -.names N_191.BLIF sm_amiga_i_6__n.BLIF N_327 -11 1 -.names CLK_OSZI_c.BLIF inst_AS_030_D0.C -1 1 -.names A_DECODE_23_.BLIF a_decode_c_23__n -1 1 -.names N_209.BLIF N_209_i +.names N_21.BLIF N_21_i 0 1 -.names N_171.BLIF sm_amiga_i_i_7__n.BLIF N_273 +.names AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF BGACK_030_INT_i.BLIF N_215 11 1 -.names N_306.BLIF N_306_i +.names N_34_0.BLIF inst_UDS_000_INT.D 0 1 -.names BGACK_030_INT_i.BLIF N_184.BLIF N_333 -11 1 -.names A_1_.BLIF a_c_1__n -1 1 -.names N_193_0.BLIF N_193 +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i 0 1 -.names BGACK_030_INT_i.BLIF N_184_i.BLIF N_334 -11 1 -.names nEXP_SPACE.BLIF nEXP_SPACE_c +.names CLK_OSZI_c.BLIF SIZE_DMA_0_.C 1 1 -.names N_190_0.BLIF N_190 +.names N_14.BLIF N_14_i +0 1 +.names inst_CLK_030_H.BLIF CLK_030_H_i +0 1 +.names N_41_0.BLIF inst_LDS_000_INT.D +0 1 +.names CLK_030_H_i.BLIF N_184.BLIF N_218 +11 1 +.names N_8.BLIF N_8_i +0 1 +.names inst_AS_000_DMA.BLIF RW_000_i.BLIF N_332 +11 1 +.names N_42_0.BLIF inst_BGACK_030_INTreg.D +0 1 +.names inst_CLK_030_H.BLIF CLK_030_c.BLIF N_226 +11 1 +.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C +1 1 +.names a_c_0__n.BLIF a_c_i_0__n +0 1 +.names N_179.BLIF sm_amiga_i_6__n.BLIF N_229 +11 1 +.names size_c_1__n.BLIF size_c_i_1__n +0 1 +.names inst_AS_000_DMA.BLIF AS_000_DMA_i +0 1 +.names N_359.BLIF N_359_i +0 1 +.names AS_000_c.BLIF AS_000_i +0 1 +.names pos_clk_un6_bgack_000_0_n.BLIF pos_clk_un6_bgack_000_n +0 1 +.names AS_000_DMA_i.BLIF AS_000_i.BLIF un7_as_030 +11 1 +.names CLK_OSZI_c.BLIF RST_DLY_0_.C +1 1 +.names N_220.BLIF N_220_i +0 1 +.names inst_RESET_OUT.BLIF RST_c.BLIF N_337 +11 1 +.names N_219.BLIF N_219_i 0 1 .names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D 0 1 -.names CLK_OSZI_c.BLIF inst_VPA_D.C -1 1 -.names N_183_i.BLIF N_183 +.names N_222.BLIF N_222_i 0 1 -.names G_107.BLIF N_206_i -0 1 -.names BG_030.BLIF BG_030_c -1 1 -.names N_162_i.BLIF N_162 -0 1 -.names G_108.BLIF N_207_i -0 1 -.names BG_000DFFreg.BLIF BG_000 -1 1 -.names N_346.BLIF N_346_i -0 1 -.names G_109.BLIF N_208_i -0 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030 -1 1 -.names ipl_c_2__n.BLIF ipl_c_i_2__n +.names CYCLE_DMA_0_.BLIF N_150_i.BLIF N_199 +11 1 +.names N_221.BLIF N_221_i 0 1 .names ahigh_c_24__n.BLIF ahigh_i_24__n 0 1 -.names CLK_OSZI_c.BLIF inst_DTACK_D0.C -1 1 -.names BGACK_000.BLIF BGACK_000_c -1 1 -.names N_51_0.BLIF IPL_D0_2_.D -0 1 -.names ahigh_c_25__n.BLIF ahigh_i_25__n -0 1 -.names CLK_030.BLIF CLK_030_c -1 1 -.names N_25.BLIF N_25_i -0 1 -.names N_79.BLIF N_79_i -0 1 -.names CLK_000.BLIF CLK_000_D_0_.D -1 1 -.names N_28_0.BLIF IPL_030DFF_0_reg.D -0 1 -.names N_199.BLIF amiga_bus_enable_dma_high_0_un3_n -0 1 -.names CLK_OSZI.BLIF CLK_OSZI_c -1 1 -.names N_26.BLIF N_26_i -0 1 -.names N_79_i.BLIF N_199.BLIF amiga_bus_enable_dma_high_0_un1_n -11 1 -.names CLK_OSZI_c.BLIF inst_CLK_030_H.C -1 1 -.names CLK_OUT_INTreg.BLIF CLK_DIV_OUT -1 1 -.names N_29_0.BLIF IPL_030DFF_1_reg.D -0 1 -.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n -11 1 -.names CLK_OUT_INTreg.BLIF CLK_EXP -1 1 -.names N_27.BLIF N_27_i -0 1 -.names amiga_bus_enable_dma_high_0_un1_n.BLIF amiga_bus_enable_dma_high_0_un0_n.BLIF N_23 -1- 1 --1 1 -.names un21_fpu_cs_i.BLIF FPU_CS -1 1 -.names N_30_0.BLIF IPL_030DFF_2_reg.D -0 1 -.names pos_clk_un9_bg_030_n.BLIF bg_000_0_un3_n -0 1 -.names FPU_SENSE.BLIF FPU_SENSE_c -1 1 -.names N_222.BLIF N_222_i -0 1 -.names BG_030_c.BLIF pos_clk_un9_bg_030_n.BLIF bg_000_0_un1_n -11 1 -.names CLK_OSZI_c.BLIF inst_RESET_OUT.C -1 1 -.names IPL_030DFF_0_reg.BLIF IPL_030_0_ +.names CLK_OSZI_c.BLIF RST_DLY_1_.C 1 1 .names N_223.BLIF N_223_i 0 1 -.names BG_000DFFreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n -11 1 -.names IPL_030DFF_1_reg.BLIF IPL_030_1_ -1 1 -.names N_231.BLIF N_231_i +.names ahigh_c_25__n.BLIF ahigh_i_25__n 0 1 -.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF N_24 -1- 1 --1 1 -.names IPL_030DFF_2_reg.BLIF IPL_030_2_ -1 1 -.names N_237.BLIF N_237_i +.names N_209.BLIF N_209_i 0 1 -.names N_24_i.BLIF RST_c.BLIF N_31_0 -11 1 -.names IPL_0_.BLIF ipl_c_0__n +.names ahigh_c_26__n.BLIF ahigh_i_26__n +0 1 +.names cpu_est_2_0_1__n.BLIF cpu_est_2_1__n +0 1 +.names ahigh_c_27__n.BLIF ahigh_i_27__n +0 1 +.names N_206.BLIF N_206_i +0 1 +.names ahigh_c_28__n.BLIF ahigh_i_28__n +0 1 +.names CLK_OSZI_c.BLIF inst_RW_000_INT.C 1 1 -.names N_342.BLIF N_342_i +.names N_205.BLIF N_205_i +0 1 +.names ahigh_c_29__n.BLIF ahigh_i_29__n +0 1 +.names pos_clk_un9_clk_000_pe_0_n.BLIF pos_clk_un9_clk_000_pe_n +0 1 +.names ahigh_c_30__n.BLIF ahigh_i_30__n +0 1 +.names N_18.BLIF N_18_i 0 1 .names N_23_i.BLIF RST_c.BLIF N_32_0 11 1 -.names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C -1 1 -.names IPL_1_.BLIF ipl_c_1__n -1 1 -.names N_341.BLIF N_341_i +.names N_37_0.BLIF inst_VMA_INTreg.D 0 1 -.names N_22_i.BLIF RST_c.BLIF N_33_0 +.names N_24_i.BLIF RST_c.BLIF N_33_0 11 1 -.names IPL_2_.BLIF ipl_c_2__n +.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C 1 1 -.names N_160_0.BLIF N_160 +.names N_171_i.BLIF N_171 0 1 -.names N_20_i.BLIF RST_c.BLIF N_35_0 +.names N_126.BLIF size_dma_0_0__un3_n +0 1 +.names N_354.BLIF N_354_i +0 1 +.names pos_clk_size_dma_6_0__n.BLIF N_126.BLIF size_dma_0_0__un1_n 11 1 -.names VPA_c.BLIF VPA_c_i -0 1 -.names N_19_i.BLIF RST_c.BLIF N_36_0 -11 1 -.names DTACK.BLIF DTACK_c -1 1 -.names N_52_0.BLIF inst_VPA_D.D -0 1 -.names N_16_i.BLIF RST_c.BLIF N_39_0 -11 1 -.names CLK_OSZI_c.BLIF BG_000DFFreg.C -1 1 -.names vcc_n_n.BLIF AVEC -1 1 -.names DTACK_c.BLIF DTACK_c_i -0 1 -.names N_15_i.BLIF RST_c.BLIF N_40_0 -11 1 -.names N_296_i.BLIF E -1 1 -.names N_53_0.BLIF inst_DTACK_D0.D -0 1 -.names N_113.BLIF size_dma_0_0__un3_n -0 1 -.names VPA.BLIF VPA_c -1 1 -.names ipl_c_0__n.BLIF ipl_c_i_0__n -0 1 -.names pos_clk_size_dma_6_0__n.BLIF N_113.BLIF size_dma_0_0__un1_n -11 1 -.names inst_VMA_INTreg.BLIF VMA -1 1 -.names N_49_0.BLIF IPL_D0_0_.D +.names un1_DS_000_ENABLE_0_sqmuxa_0.BLIF un1_DS_000_ENABLE_0_sqmuxa 0 1 .names SIZE_DMA_0_.BLIF size_dma_0_0__un3_n.BLIF size_dma_0_0__un0_n 11 1 -.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.C -1 1 -.names RST.BLIF RST_c -1 1 -.names ipl_c_1__n.BLIF ipl_c_i_1__n +.names N_66_0.BLIF N_66 0 1 .names size_dma_0_0__un1_n.BLIF size_dma_0_0__un0_n.BLIF SIZE_DMA_0_.D 1- 1 -1 1 -.names N_50_0.BLIF IPL_D0_1_.D -0 1 -.names N_113.BLIF size_dma_0_1__un3_n -0 1 -.names ipl_c_i_2__n.BLIF RST_c.BLIF N_51_0 -11 1 -.names pos_clk_size_dma_6_1__n.BLIF N_113.BLIF size_dma_0_1__un1_n -11 1 -.names FC_0_.BLIF fc_c_0__n +.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C 1 1 -.names ipl_c_i_1__n.BLIF RST_c.BLIF N_50_0 +.names inst_UDS_000_INT.BLIF UDS_000_INT_i +0 1 +.names N_126.BLIF size_dma_0_1__un3_n +0 1 +.names un1_UDS_000_INT_0.BLIF un1_UDS_000_INT +0 1 +.names pos_clk_size_dma_6_1__n.BLIF N_126.BLIF size_dma_0_1__un1_n 11 1 +.names inst_LDS_000_INT.BLIF LDS_000_INT_i +0 1 .names SIZE_DMA_1_.BLIF size_dma_0_1__un3_n.BLIF size_dma_0_1__un0_n 11 1 -.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C -1 1 -.names FC_1_.BLIF fc_c_1__n -1 1 -.names ipl_c_i_0__n.BLIF RST_c.BLIF N_49_0 -11 1 +.names un1_LDS_000_INT_0.BLIF un1_LDS_000_INT +0 1 .names size_dma_0_1__un1_n.BLIF size_dma_0_1__un0_n.BLIF SIZE_DMA_1_.D 1- 1 -1 1 +.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C +1 1 +.names A_DECODE_16_.BLIF a_decode_c_16__n +1 1 +.names N_196.BLIF N_196_i +0 1 +.names N_233.BLIF ipl_030_0_0__un3_n +0 1 +.names A_DECODE_17_.BLIF a_decode_c_17__n +1 1 +.names N_183_0.BLIF N_183 +0 1 +.names IPL_030DFF_0_reg.BLIF N_233.BLIF ipl_030_0_0__un1_n +11 1 +.names A_DECODE_18_.BLIF a_decode_c_18__n +1 1 +.names N_182_0.BLIF N_182 +0 1 +.names ipl_c_0__n.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n +11 1 +.names A_DECODE_19_.BLIF a_decode_c_19__n +1 1 +.names N_180_0.BLIF N_180 +0 1 +.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF N_22 +1- 1 +-1 1 +.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C +1 1 +.names A_DECODE_20_.BLIF a_decode_c_20__n +1 1 +.names N_178_0.BLIF N_178 +0 1 +.names N_233.BLIF ipl_030_0_1__un3_n +0 1 +.names A_DECODE_21_.BLIF a_decode_c_21__n +1 1 +.names N_315_i.BLIF N_315 +0 1 +.names IPL_030DFF_1_reg.BLIF N_233.BLIF ipl_030_0_1__un1_n +11 1 +.names A_DECODE_22_.BLIF a_decode_c_22__n +1 1 +.names N_351.BLIF N_351_i +0 1 +.names ipl_c_1__n.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n +11 1 +.names A_DECODE_23_.BLIF a_decode_c_23__n +1 1 +.names N_154_0.BLIF N_154 +0 1 +.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF N_23 +1- 1 +-1 1 +.names CLK_OSZI_c.BLIF inst_DS_000_DMA.C +1 1 +.names N_149_i.BLIF N_149 +0 1 +.names N_233.BLIF ipl_030_0_2__un3_n +0 1 +.names A_1_.BLIF a_c_1__n +1 1 +.names N_228.BLIF N_228_i +0 1 +.names IPL_030DFF_2_reg.BLIF N_233.BLIF ipl_030_0_2__un1_n +11 1 +.names nEXP_SPACE.BLIF nEXP_SPACE_c +1 1 +.names N_213.BLIF N_213_i +0 1 +.names ipl_c_2__n.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n +11 1 +.names N_212.BLIF N_212_i +0 1 +.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_24 +1- 1 +-1 1 +.names CLK_OSZI_c.BLIF inst_DSACK1_INT.C +1 1 +.names BG_030.BLIF BG_030_c +1 1 +.names N_357.BLIF N_357_i +0 1 +.names N_113.BLIF IPL_D0_0_.D +0 1 +.names BG_000DFFreg.BLIF BG_000 +1 1 +.names cpu_est_2_0_2__n.BLIF cpu_est_2_2__n +0 1 +.names N_112.BLIF IPL_D0_1_.D +0 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030 +1 1 +.names N_208.BLIF N_208_i +0 1 +.names N_111.BLIF IPL_D0_2_.D +0 1 +.names BGACK_000.BLIF BGACK_000_c +1 1 +.names N_210.BLIF N_210_i +0 1 +.names N_185.BLIF a0_dma_0_un3_n +0 1 +.names CLK_OSZI_c.BLIF inst_AS_000_INT.C +1 1 +.names CLK_030.BLIF CLK_030_c +1 1 +.names N_211.BLIF N_211_i +0 1 +.names pos_clk_a0_dma_3_n.BLIF N_185.BLIF a0_dma_0_un1_n +11 1 +.names CLK_000.BLIF CLK_000_D_0_.D +1 1 +.names un1_SM_AMIGA_0_sqmuxa_1_0.BLIF un1_SM_AMIGA_0_sqmuxa_1 +0 1 +.names inst_A0_DMA.BLIF a0_dma_0_un3_n.BLIF a0_dma_0_un0_n +11 1 +.names CLK_OSZI.BLIF CLK_OSZI_c +1 1 +.names RW_c.BLIF RW_c_i +0 1 +.names a0_dma_0_un1_n.BLIF a0_dma_0_un0_n.BLIF N_20 +1- 1 +-1 1 +.names CLK_OUT_INTreg.BLIF CLK_DIV_OUT +1 1 +.names N_311_0.BLIF N_311 +0 1 +.names N_114.BLIF N_114_i +0 1 +.names CLK_OSZI_c.BLIF inst_AS_030_D0.C +1 1 +.names CLK_OUT_INTreg.BLIF CLK_EXP +1 1 +.names N_336.BLIF N_336_i +0 1 +.names N_185.BLIF amiga_bus_enable_dma_low_0_un3_n +0 1 +.names un21_fpu_cs_i.BLIF FPU_CS +1 1 +.names N_244.BLIF N_244_i +0 1 +.names N_114_i.BLIF N_185.BLIF amiga_bus_enable_dma_low_0_un1_n +11 1 +.names FPU_SENSE.BLIF FPU_SENSE_c +1 1 +.names N_314_0.BLIF N_314 +0 1 +.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF amiga_bus_enable_dma_low_0_un3_n.BLIF amiga_bus_enable_dma_low_0_un0_n +11 1 +.names IPL_030DFF_0_reg.BLIF IPL_030_0_ +1 1 +.names inst_VMA_INTreg.BLIF VMA_INT_i +0 1 +.names amiga_bus_enable_dma_low_0_un1_n.BLIF amiga_bus_enable_dma_low_0_un0_n.BLIF N_25 +1- 1 +-1 1 +.names CLK_OSZI_c.BLIF inst_VPA_D.C +1 1 +.names IPL_030DFF_1_reg.BLIF IPL_030_1_ +1 1 +.names N_352.BLIF N_352_i +0 1 +.names N_115.BLIF N_115_i +0 1 +.names IPL_030DFF_2_reg.BLIF IPL_030_2_ +1 1 +.names N_353.BLIF N_353_i +0 1 +.names N_185.BLIF amiga_bus_enable_dma_high_0_un3_n +0 1 +.names IPL_0_.BLIF ipl_c_0__n +1 1 +.names N_293.BLIF N_293_i +0 1 +.names N_115_i.BLIF N_185.BLIF amiga_bus_enable_dma_high_0_un1_n +11 1 +.names IPL_1_.BLIF ipl_c_1__n +1 1 +.names N_176_i.BLIF N_176 +0 1 +.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n +11 1 +.names CLK_OSZI_c.BLIF inst_DTACK_D0.C +1 1 +.names IPL_2_.BLIF ipl_c_2__n +1 1 +.names N_198.BLIF N_198_i +0 1 +.names amiga_bus_enable_dma_high_0_un1_n.BLIF amiga_bus_enable_dma_high_0_un0_n.BLIF N_26 +1- 1 +-1 1 +.names N_197.BLIF N_197_i +0 1 +.names pos_clk_un9_bg_030_n.BLIF bg_000_0_un3_n +0 1 +.names DTACK.BLIF DTACK_c +1 1 +.names N_16.BLIF N_16_i +0 1 +.names BG_030_c.BLIF pos_clk_un9_bg_030_n.BLIF bg_000_0_un1_n +11 1 +.names vcc_n_n.BLIF AVEC +1 1 +.names N_39_0.BLIF inst_RW_000_INT.D +0 1 +.names BG_000DFFreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n +11 1 +.names CLK_OSZI_c.BLIF inst_CLK_030_H.C +1 1 +.names N_309_i.BLIF E +1 1 +.names VPA_c.BLIF VPA_c_i +0 1 +.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF N_27 +1- 1 +-1 1 +.names VPA.BLIF VPA_c +1 1 +.names N_52_0.BLIF inst_VPA_D.D +0 1 +.names N_27_i.BLIF RST_c.BLIF N_28_0 +11 1 +.names inst_VMA_INTreg.BLIF VMA +1 1 +.names DTACK_c.BLIF DTACK_c_i +0 1 +.names N_26_i.BLIF RST_c.BLIF N_29_0 +11 1 +.names RST.BLIF RST_c +1 1 +.names N_53_0.BLIF inst_DTACK_D0.D +0 1 +.names N_25_i.BLIF RST_c.BLIF N_30_0 +11 1 +.names CLK_OSZI_c.BLIF inst_RESET_OUT.C +1 1 +.names cpu_est_2_.BLIF cpu_est_i_2__n +0 1 +.names N_20_i.BLIF RST_c.BLIF N_35_0 +11 1 +.names N_314.BLIF cpu_est_i_2__n.BLIF N_211 +11 1 +.names N_19_i.BLIF RST_c.BLIF N_36_0 +11 1 +.names FC_0_.BLIF fc_c_0__n +1 1 +.names N_149.BLIF cpu_est_0_3__un3_n +0 1 +.names N_15_i.BLIF RST_c.BLIF N_40_0 +11 1 +.names FC_1_.BLIF fc_c_1__n +1 1 +.names cpu_est_3_.BLIF N_149.BLIF cpu_est_0_3__un1_n +11 1 +.names N_4_i.BLIF RST_c.BLIF N_44_0 +11 1 +.names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C +1 1 .names gnd_n_n.BLIF AMIGA_ADDR_ENABLE 1 1 +.names N_189_i.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n +11 1 +.names N_3_i.BLIF RST_c.BLIF N_45_0 +11 1 +.names AMIGA_BUS_DATA_DIR_c.BLIF AMIGA_BUS_DATA_DIR +1 1 +.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_.D +1- 1 +-1 1 +.names N_22_i.BLIF RST_c.BLIF N_31_0 +11 1 +.names un1_amiga_bus_enable_low_i.BLIF AMIGA_BUS_ENABLE_LOW +1 1 .names DTACK_c_i.BLIF RST_c.BLIF N_53_0 11 1 .names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i 0 1 -.names AMIGA_BUS_DATA_DIR_c.BLIF AMIGA_BUS_DATA_DIR +.names un10_amiga_bus_enable_high_i.BLIF AMIGA_BUS_ENABLE_HIGH 1 1 .names RST_c.BLIF VPA_c_i.BLIF N_52_0 11 1 .names AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF BGACK_030_INT_i.BLIF un1_amiga_bus_enable_low 11 1 -.names un1_amiga_bus_enable_low_i.BLIF AMIGA_BUS_ENABLE_LOW +.names CLK_OSZI_c.BLIF BG_000DFFreg.C 1 1 -.names un1_amiga_bus_enable_low.BLIF un1_amiga_bus_enable_low_i -0 1 -.names BG_030_c_i.BLIF pos_clk_un6_bg_030_i_n.BLIF pos_clk_un9_bg_030_0_n +.names N_16_i.BLIF RST_c.BLIF N_39_0 11 1 -.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C -1 1 -.names N_205.BLIF AMIGA_BUS_ENABLE_HIGH -1 1 -.names un21_fpu_cs.BLIF un21_fpu_cs_i -0 1 -.names un7_as_030.BLIF un7_as_030_i -0 1 -.names N_183.BLIF sm_amiga_i_0__n.BLIF N_267 +.names BG_030_c_i.BLIF N_231.BLIF pos_clk_un9_bg_030_0_n 11 1 -.names N_169.BLIF N_169_i -0 1 -.names N_144_i_1.BLIF RST_c.BLIF SM_AMIGA_2_.D -11 1 -.names N_165.BLIF RST_c.BLIF N_237 -11 1 -.names N_165.BLIF N_165_i -0 1 -.names N_267_i.BLIF N_324_i.BLIF N_140_i_1 -11 1 -.names N_183_i.BLIF RST_c.BLIF N_231 -11 1 -.names un6_ds_030.BLIF un6_ds_030_i -0 1 -.names CLK_OSZI_c.BLIF inst_A0_DMA.C -1 1 -.names N_140_i_1.BLIF RST_c.BLIF SM_AMIGA_0_.D -11 1 -.names cpu_est_2_.BLIF cpu_est_i_2__n -0 1 -.names N_297.BLIF as_030_000_sync_0_un3_n -0 1 -.names nEXP_SPACE_c.BLIF inst_AS_030_D0.BLIF pos_clk_un6_bg_030_1_n -11 1 -.names N_160.BLIF cpu_est_i_2__n.BLIF N_223 -11 1 -.names AS_030_c.BLIF N_297.BLIF as_030_000_sync_0_un1_n -11 1 -.names pos_clk_un6_bg_030_1_n.BLIF CLK_000_D_0_.BLIF pos_clk_un6_bg_030_n -11 1 -.names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n -11 1 -.names N_305_i.BLIF N_350.BLIF N_230_1 -11 1 -.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF N_15 -1- 1 --1 1 -.names CLK_OSZI_c.BLIF inst_RW_000_DMA.C -1 1 -.names N_230_1.BLIF RST_c.BLIF N_230 +.names N_196_1.BLIF rst_dly_i_2__n.BLIF N_196 11 1 .names un1_SM_AMIGA_0_sqmuxa_1.BLIF rw_000_int_0_un3_n 0 1 -.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_221_1 -11 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_2__un3_n +.names un7_as_030.BLIF un7_as_030_i 0 1 -.names pos_clk_rw_000_int_5_n.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF rw_000_int_0_un1_n +.names N_218_i.BLIF RST_c.BLIF N_249_i_1 11 1 -.names N_221_1.BLIF cpu_est_i_3__n.BLIF N_221 +.names N_311.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF rw_000_int_0_un1_n 11 1 -.names ipl_c_2__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_2__un1_n +.names N_133.BLIF N_133_i +0 1 +.names N_249_i_1.BLIF pos_clk_un21_bgack_030_int_i_0_0_n.BLIF inst_CLK_030_H.D 11 1 .names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n 11 1 -.names N_210_i.BLIF rst_dly_i_0__n.BLIF N_215_1 -11 1 -.names IPL_030DFF_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n +.names N_132.BLIF N_132_i +0 1 +.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.C +1 1 +.names AS_000_i.BLIF pos_clk_CYCLE_DMA_5_1_i_0_x2.BLIF N_57_i_1 11 1 .names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF N_16 1- 1 -1 1 -.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C -1 1 -.names N_215_1.BLIF rst_dly_i_1__n.BLIF N_215 +.names inst_DS_000_DMA.BLIF DS_000_DMA_i +0 1 +.names N_57_i_1.BLIF N_251_i.BLIF CYCLE_DMA_1_.D 11 1 -.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_27 +.names un1_amiga_bus_enable_low.BLIF un1_amiga_bus_enable_low_i +0 1 +.names AS_000_i.BLIF DS_000_DMA_i.BLIF un6_ds_030 +11 1 +.names N_149_i.BLIF N_355.BLIF N_338_1 +11 1 +.names un21_fpu_cs.BLIF un21_fpu_cs_i +0 1 +.names un6_ds_030.BLIF un6_ds_030_i +0 1 +.names N_338_1.BLIF RST_c.BLIF N_338 +11 1 +.names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n +0 1 +.names N_246.BLIF ds_000_dma_0_un3_n +0 1 +.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C +1 1 +.names AS_000_i.BLIF N_186_i.BLIF N_224_1 +11 1 +.names N_293_i.BLIF SM_AMIGA_i_7_.BLIF N_175_i +11 1 +.names pos_clk_ds_000_dma_4_n.BLIF N_246.BLIF ds_000_dma_0_un1_n +11 1 +.names N_224_1.BLIF RW_000_c.BLIF N_224 +11 1 +.names cpu_est_i_1__n.BLIF cpu_est_i_2__n.BLIF N_159_i +11 1 +.names inst_DS_000_DMA.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n +11 1 +.names inst_BGACK_030_INTreg.BLIF AS_030_000_SYNC_i.BLIF N_216_1 +11 1 +.names cpu_est_3_.BLIF cpu_est_i_3__n +0 1 +.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3 1- 1 -1 1 -.names N_199.BLIF rw_000_dma_0_un3_n +.names N_216_1.BLIF AS_030_i.BLIF N_216 +11 1 +.names cpu_est_3_.BLIF cpu_est_i_0__n.BLIF N_314_0 +11 1 +.names N_245.BLIF as_000_dma_0_un3_n 0 1 -.names N_163.BLIF N_210_i.BLIF N_306_1 +.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C +1 1 +.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_209_1 11 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_1__un3_n +.names N_244_i.BLIF N_336_i.BLIF cpu_est_0_.D +11 1 +.names pos_clk_un21_bgack_030_int_i_0_n.BLIF N_245.BLIF as_000_dma_0_un1_n +11 1 +.names N_209_1.BLIF cpu_est_i_3__n.BLIF N_209 +11 1 +.names N_175_i.BLIF RW_c_i.BLIF N_311_0 +11 1 +.names inst_AS_000_DMA.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n +11 1 +.names N_207_i.BLIF rst_dly_i_0__n.BLIF N_203_1 +11 1 +.names N_160.BLIF N_175_i.BLIF un1_SM_AMIGA_0_sqmuxa_1_0 +11 1 +.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF N_4 +1- 1 +-1 1 +.names N_203_1.BLIF rst_dly_i_1__n.BLIF N_203 +11 1 +.names N_210_i.BLIF N_211_i.BLIF N_189_i +11 1 +.names N_310.BLIF as_030_000_sync_0_un3_n 0 1 -.names N_300.BLIF N_199.BLIF rw_000_dma_0_un1_n +.names CLK_OSZI_c.BLIF inst_A0_DMA.C +1 1 +.names N_158.BLIF N_207_i.BLIF N_196_1 11 1 -.names N_306_1.BLIF rst_dly_i_2__n.BLIF N_306 +.names inst_DTACK_D0.BLIF DTACK_D0_i +0 1 +.names AS_030_c.BLIF N_310.BLIF as_030_000_sync_0_un1_n 11 1 -.names ipl_c_1__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_1__un1_n +.names N_152_i_1.BLIF RST_c.BLIF SM_AMIGA_i_7_.D +11 1 +.names DTACK_D0_i.BLIF inst_VPA_D.BLIF N_353 +11 1 +.names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n +11 1 +.names N_150.BLIF N_288_i.BLIF N_144_i_1 +11 1 +.names inst_VPA_D.BLIF VPA_D_i +0 1 +.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF N_15 +1- 1 +-1 1 +.names N_144_i_1.BLIF RST_c.BLIF SM_AMIGA_4_.D +11 1 +.names N_149_i.BLIF cpu_est_0_.BLIF N_244 +11 1 +.names N_185.BLIF rw_000_dma_0_un3_n +0 1 +.names CLK_OSZI_c.BLIF inst_RW_000_DMA.C +1 1 +.names N_287_i.BLIF N_340_i.BLIF N_142_i_1 +11 1 +.names cpu_est_0_.BLIF cpu_est_i_0__n +0 1 +.names pos_clk_rw_000_dma_3_n.BLIF N_185.BLIF rw_000_dma_0_un1_n +11 1 +.names N_142_i_1.BLIF RST_c.BLIF SM_AMIGA_3_.D +11 1 +.names N_149.BLIF cpu_est_i_0__n.BLIF N_336 11 1 .names inst_RW_000_DMA.BLIF rw_000_dma_0_un3_n.BLIF rw_000_dma_0_un0_n 11 1 -.names N_208_i.BLIF N_206_i.BLIF pos_clk_ipl_1_n +.names N_150.BLIF N_284_i.BLIF N_312_i_1 11 1 -.names IPL_030DFF_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n +.names N_210_i.BLIF N_357_i.BLIF cpu_est_2_0_2__n 11 1 .names rw_000_dma_0_un1_n.BLIF rw_000_dma_0_un0_n.BLIF N_19 1- 1 -1 1 -.names CLK_OSZI_c.BLIF inst_RW_000_INT.C -1 1 -.names pos_clk_ipl_1_n.BLIF N_207_i.BLIF pos_clk_ipl_n +.names N_312_i_1.BLIF RST_c.BLIF SM_AMIGA_2_.D 11 1 -.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF N_26 -1- 1 --1 1 -.names N_199.BLIF a0_dma_0_un3_n -0 1 -.names N_335_i.BLIF N_336_i.BLIF N_142_i_1 -11 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_0__un3_n -0 1 -.names pos_clk_a0_dma_3_n.BLIF N_199.BLIF a0_dma_0_un1_n -11 1 -.names N_142_i_1.BLIF RST_c.BLIF SM_AMIGA_1_.D -11 1 -.names ipl_c_0__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_0__un1_n -11 1 -.names inst_A0_DMA.BLIF a0_dma_0_un3_n.BLIF a0_dma_0_un0_n -11 1 -.names N_295_i.BLIF N_332_i.BLIF N_234_i_1 -11 1 -.names IPL_030DFF_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n -11 1 -.names a0_dma_0_un1_n.BLIF a0_dma_0_un0_n.BLIF N_20 -1- 1 --1 1 -.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C -1 1 -.names N_234_i_1.BLIF RST_c.BLIF RST_DLY_0_.D -11 1 -.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF N_25 -1- 1 --1 1 -.names N_78.BLIF N_78_i -0 1 -.names N_180_i.BLIF N_292_i.BLIF N_302_0_1 -11 1 -.names N_305.BLIF cpu_est_0_3__un3_n -0 1 -.names N_199.BLIF amiga_bus_enable_dma_low_0_un3_n -0 1 -.names N_302_0_1.BLIF RW_000_i.BLIF N_302_0 -11 1 -.names cpu_est_3_.BLIF N_305.BLIF cpu_est_0_3__un1_n -11 1 -.names N_78_i.BLIF N_199.BLIF amiga_bus_enable_dma_low_0_un1_n -11 1 -.names N_180_i.BLIF N_290_i.BLIF N_63_i_1 -11 1 -.names N_192_i.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n -11 1 -.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF amiga_bus_enable_dma_low_0_un3_n.BLIF amiga_bus_enable_dma_low_0_un0_n -11 1 -.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C -1 1 -.names N_63_i_1.BLIF RST_c.BLIF inst_CLK_030_H.D -11 1 -.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_.D -1- 1 --1 1 -.names amiga_bus_enable_dma_low_0_un1_n.BLIF amiga_bus_enable_dma_low_0_un0_n.BLIF N_22 -1- 1 --1 1 -.names N_273_i.BLIF N_275_i.BLIF N_154_i_1 -11 1 -.names N_27_i.BLIF RST_c.BLIF N_30_0 +.names N_212_i.BLIF N_213_i.BLIF N_309_i 11 1 .names vcc_n_n 1 -.names N_154_i_1.BLIF RST_c.BLIF SM_AMIGA_i_7_.D +.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C +1 1 +.names N_265_i.BLIF N_267_i.BLIF N_236_i_1 11 1 -.names N_26_i.BLIF RST_c.BLIF N_29_0 +.names N_82_i.BLIF N_228_i.BLIF SM_AMIGA_5_.D 11 1 .names gnd_n_n -.names N_166.BLIF N_327_i.BLIF N_152_i_1 +.names N_236_i_1.BLIF RST_c.BLIF RST_DLY_0_.D 11 1 -.names N_25_i.BLIF RST_c.BLIF N_28_0 +.names N_355_i_0.BLIF RST_c.BLIF N_207_i 11 1 .names A_DECODE_15_.BLIF a_decode_15__n 1 1 -.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C -1 1 -.names N_152_i_1.BLIF RST_c.BLIF SM_AMIGA_6_.D -11 1 -.names AS_030_c.BLIF AS_030_i -0 1 -.names A_DECODE_14_.BLIF a_decode_14__n -1 1 -.names N_155.BLIF N_270_i.BLIF N_148_i_1 -11 1 -.names inst_DSACK1_INT.BLIF DSACK1_INT_i -0 1 -.names A_DECODE_13_.BLIF a_decode_13__n -1 1 -.names N_148_i_1.BLIF RST_c.BLIF SM_AMIGA_4_.D -11 1 -.names AS_030_i.BLIF DSACK1_INT_i.BLIF N_165 -11 1 -.names A_DECODE_12_.BLIF a_decode_12__n -1 1 -.names N_155.BLIF N_269_i.BLIF N_144_i_1 -11 1 -.names inst_DTACK_D0.BLIF DTACK_D0_i -0 1 -.names A_DECODE_11_.BLIF a_decode_11__n -1 1 -.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C -1 1 -.names N_306_i.BLIF RST_c.BLIF N_232_i_2 -11 1 -.names DTACK_D0_i.BLIF inst_VPA_D.BLIF N_348 -11 1 -.names A_DECODE_10_.BLIF a_decode_10__n -1 1 -.names N_232_i_1.BLIF N_232_i_2.BLIF RST_DLY_2_.D -11 1 -.names inst_VPA_D.BLIF VPA_D_i -0 1 -.names A_DECODE_9_.BLIF a_decode_9__n -1 1 -.names N_305_i.BLIF N_352.BLIF N_219_1 -11 1 -.names N_305_i.BLIF cpu_est_0_.BLIF N_342 -11 1 -.names A_DECODE_8_.BLIF a_decode_8__n -1 1 -.names VPA_D_i.BLIF cpu_est_i_3__n.BLIF N_219_2 -11 1 -.names cpu_est_0_.BLIF cpu_est_i_0__n -0 1 -.names A_DECODE_7_.BLIF a_decode_7__n -1 1 -.names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C -1 1 -.names N_219_1.BLIF N_219_2.BLIF N_219 -11 1 -.names N_305.BLIF cpu_est_i_0__n.BLIF N_341 -11 1 -.names A_DECODE_6_.BLIF a_decode_6__n -1 1 -.names N_155_i.BLIF N_164_i.BLIF N_218_1 -11 1 -.names N_188.BLIF N_305_i.BLIF N_338 -11 1 -.names A_DECODE_5_.BLIF a_decode_5__n -1 1 -.names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF N_218_2 -11 1 -.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n -0 1 -.names A_DECODE_4_.BLIF a_decode_4__n -1 1 -.names N_218_1.BLIF N_218_2.BLIF N_218 -11 1 -.names N_194.BLIF sm_amiga_i_1__n.BLIF N_335 -11 1 -.names A_DECODE_3_.BLIF a_decode_3__n -1 1 -.names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C -1 1 -.names N_160_0.BLIF N_164_i.BLIF N_347_1 -11 1 -.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n -0 1 -.names A_DECODE_2_.BLIF a_decode_2__n -1 1 -.names VMA_INT_i.BLIF VPA_D_i.BLIF N_347_2 -11 1 -.names N_196.BLIF sm_amiga_i_2__n.BLIF N_269 -11 1 -.names N_347_1.BLIF N_347_2.BLIF N_347 -11 1 -.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n -0 1 -.names AS_000_i.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.BLIF N_136_i_1 -11 1 -.names N_346_i.BLIF RST_c.BLIF N_159_0 -11 1 -.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C -1 1 -.names N_136_i_1.BLIF N_245_0.BLIF CYCLE_DMA_1_.D -11 1 -.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_162_i -11 1 -.names N_338_i.BLIF N_339_i.BLIF N_146_i_1 -11 1 -.names N_157_i.BLIF SM_AMIGA_1_.BLIF N_183_i -11 1 -.names N_146_i_1.BLIF RST_c.BLIF SM_AMIGA_3_.D -11 1 -.names cpu_est_1_.BLIF cpu_est_i_1__n -0 1 -.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_D.D -1 1 -.names AS_030_D0_i.BLIF N_161.BLIF N_227_1 -11 1 -.names cpu_est_1_.BLIF cpu_est_i_3__n.BLIF N_190_0 -11 1 -.names N_199_i.BLIF sm_amiga_i_i_7__n.BLIF N_227_2 -11 1 -.names cpu_est_3_.BLIF cpu_est_i_1__n.BLIF N_193_0 -11 1 -.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_D.C -1 1 -.names N_227_1.BLIF N_227_2.BLIF N_227_3 -11 1 -.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n -0 1 -.names N_227_3.BLIF nEXP_SPACE_c.BLIF N_227 -11 1 -.names N_155_i.BLIF SM_AMIGA_2_.BLIF N_194_0 -11 1 -.names un21_berr_1.BLIF FPU_SENSE_i.BLIF un21_fpu_cs_1 -11 1 -.names BGACK_030_INT_i.BLIF RST_c.BLIF N_245_0 -11 1 -.names CYCLE_DMA_0_.BLIF pos_clk_un21_bgack_030_int_i_i_a2_i_x2.X1 -1 1 -.names un21_fpu_cs_1.BLIF N_161_i.BLIF un21_fpu_cs -11 1 -.names cpu_est_i_1__n.BLIF cpu_est_i_2__n.BLIF N_164_i -11 1 -.names un21_berr_1.BLIF FPU_SENSE_c.BLIF un21_berr_1_0 -11 1 -.names cpu_est_3_.BLIF cpu_est_i_3__n -0 1 -.names CYCLE_DMA_1_.BLIF pos_clk_un21_bgack_030_int_i_i_a2_i_x2.X2 -1 1 -.names un21_berr_1_0.BLIF N_161_i.BLIF un21_berr -11 1 -.names cpu_est_3_.BLIF cpu_est_i_0__n.BLIF N_160_0 -11 1 -.names AS_000_i.BLIF N_216_i.BLIF N_235_i_1 -11 1 -.names N_341_i.BLIF N_342_i.BLIF cpu_est_0_.D -11 1 -.names N_217_i.BLIF N_245_0.BLIF N_235_i_2 -11 1 -.names N_231_i.BLIF N_237_i.BLIF inst_DSACK1_INT.D -11 1 -.names IPL_D0_2_.BLIF G_109.X1 -1 1 -.names N_235_i_1.BLIF N_235_i_2.BLIF CYCLE_DMA_0_.D -11 1 -.names N_222_i.BLIF N_223_i.BLIF N_192_i -11 1 -.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_256_1 -11 1 -.names N_162.BLIF cpu_est_2_.BLIF N_222 -11 1 -.names ipl_c_2__n.BLIF G_109.X2 -1 1 -.names RW_000_c.BLIF nEXP_SPACE_i.BLIF N_256_2 -11 1 -.names N_193.BLIF cpu_est_i_2__n.BLIF N_224 -11 1 -.names N_256_1.BLIF N_256_2.BLIF N_256 -11 1 -.names N_190.BLIF cpu_est_2_.BLIF N_225 -11 1 -.names N_209_i.BLIF N_211_i.BLIF N_232_i_1 -11 1 -.names N_159.BLIF RST_DLY_0_.BLIF N_295 -11 1 -.names IPL_D0_1_.BLIF G_108.X1 -1 1 -.names ahigh_i_24__n.BLIF ahigh_i_25__n.BLIF un10_ciin_1 -11 1 -.names N_157_i.BLIF sm_amiga_i_2__n.BLIF N_336 -11 1 -.names ahigh_i_26__n.BLIF ahigh_i_27__n.BLIF un10_ciin_2 -11 1 -.names N_350.BLIF N_350_i_0 -0 1 -.names ipl_c_1__n.BLIF G_108.X2 -1 1 -.names ahigh_i_28__n.BLIF ahigh_i_29__n.BLIF un10_ciin_3 -11 1 -.names N_305_i.BLIF N_350_i_0.BLIF N_346 -11 1 -.names ahigh_i_30__n.BLIF ahigh_i_31__n.BLIF un10_ciin_4 -11 1 -.names N_162_i.BLIF cpu_est_i_2__n.BLIF N_352 -11 1 -.names a_decode_c_23__n.BLIF AS_030_D0_i.BLIF un10_ciin_5 -11 1 -.names N_218_i.BLIF N_219_i.BLIF pos_clk_un9_clk_000_pe_0_n -11 1 -.names IPL_D0_0_.BLIF G_107.X1 -1 1 -.names a_decode_c_20__n.BLIF a_decode_c_21__n.BLIF un10_ciin_6 -11 1 -.names N_220_i.BLIF N_221_i.BLIF cpu_est_2_0_1__n -11 1 -.names un10_ciin_1.BLIF un10_ciin_2.BLIF un10_ciin_7 -11 1 -.names N_222_i.BLIF N_352_i.BLIF cpu_est_2_0_2__n -11 1 -.names ipl_c_0__n.BLIF G_107.X2 -1 1 -.names un10_ciin_3.BLIF un10_ciin_4.BLIF un10_ciin_8 -11 1 -.names N_224_i.BLIF N_225_i.BLIF N_296_i -11 1 -.names un10_ciin_5.BLIF un10_ciin_6.BLIF un10_ciin_9 -11 1 -.names N_350_i_0.BLIF RST_c.BLIF N_210_i -11 1 -.names un10_ciin_7.BLIF un10_ciin_8.BLIF un10_ciin_10 +.names N_160.BLIF N_229_i.BLIF N_148_i_1 11 1 .names CLK_000_D_1_.BLIF clk_000_d_i_1__n 0 1 -.names CYCLE_DMA_1_.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.X1 +.names A_DECODE_14_.BLIF a_decode_14__n 1 1 +.names N_148_i_1.BLIF RST_c.BLIF SM_AMIGA_6_.D +11 1 +.names CLK_000_D_1_.BLIF clk_000_d_i_0__n.BLIF N_149_i +11 1 +.names A_DECODE_13_.BLIF a_decode_13__n +1 1 +.names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C +1 1 +.names N_150.BLIF N_227_i.BLIF N_136_i_1 +11 1 +.names N_351_i.BLIF RST_c.BLIF N_154_0 +11 1 +.names A_DECODE_12_.BLIF a_decode_12__n +1 1 +.names N_136_i_1.BLIF RST_c.BLIF SM_AMIGA_0_.D +11 1 +.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_315_i +11 1 +.names A_DECODE_11_.BLIF a_decode_11__n +1 1 +.names N_226_i.BLIF RW_000_i.BLIF N_246_0_1 +11 1 +.names N_149.BLIF RST_c.BLIF N_82_i +11 1 +.names A_DECODE_10_.BLIF a_decode_10__n +1 1 +.names N_246_0_1.BLIF pos_clk_un21_bgack_030_int_i_0_0_n.BLIF N_246_0 +11 1 +.names cpu_est_1_.BLIF cpu_est_i_1__n +0 1 +.names A_DECODE_9_.BLIF a_decode_9__n +1 1 +.names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C +1 1 +.names N_196_i.BLIF N_197_i.BLIF N_234_i_1 +11 1 +.names cpu_est_1_.BLIF cpu_est_i_3__n.BLIF N_178_0 +11 1 +.names A_DECODE_8_.BLIF a_decode_8__n +1 1 +.names N_198_i.BLIF RST_c.BLIF N_234_i_2 +11 1 +.names cpu_est_3_.BLIF cpu_est_i_1__n.BLIF N_180_0 +11 1 +.names A_DECODE_7_.BLIF a_decode_7__n +1 1 +.names N_234_i_1.BLIF N_234_i_2.BLIF RST_DLY_2_.D +11 1 +.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n +0 1 +.names A_DECODE_6_.BLIF a_decode_6__n +1 1 +.names N_149_i.BLIF N_357.BLIF N_206_1 +11 1 +.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +0 1 +.names A_DECODE_5_.BLIF a_decode_5__n +1 1 +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C +1 1 +.names VPA_D_i.BLIF cpu_est_i_3__n.BLIF N_206_2 +11 1 +.names N_149_i.BLIF SM_AMIGA_5_.BLIF N_183_0 +11 1 +.names A_DECODE_4_.BLIF a_decode_4__n +1 1 +.names N_206_1.BLIF N_206_2.BLIF N_206 +11 1 +.names N_178.BLIF cpu_est_2_.BLIF N_213 +11 1 +.names A_DECODE_3_.BLIF a_decode_3__n +1 1 +.names N_150_i.BLIF N_159_i.BLIF N_205_1 +11 1 +.names N_160.BLIF sm_amiga_i_5__n.BLIF N_228 +11 1 +.names A_DECODE_2_.BLIF a_decode_2__n +1 1 +.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_D.D +1 1 +.names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF N_205_2 +11 1 +.names N_154.BLIF RST_DLY_0_.BLIF N_265 +11 1 +.names N_205_1.BLIF N_205_2.BLIF N_205 +11 1 +.names RST_DLY_0_.BLIF rst_dly_i_0__n +0 1 +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_D.C +1 1 +.names N_159_i.BLIF N_314_0.BLIF N_352_1 +11 1 +.names N_82_i.BLIF rst_dly_i_0__n.BLIF N_267 +11 1 +.names VMA_INT_i.BLIF VPA_D_i.BLIF N_352_2 +11 1 +.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n +0 1 +.names N_352_1.BLIF N_352_2.BLIF N_352 +11 1 +.names N_182.BLIF sm_amiga_i_2__n.BLIF N_284 +11 1 +.names CYCLE_DMA_0_.BLIF pos_clk_un21_bgack_030_int_i_0_o3_0_x2.X1 +1 1 +.names inst_AS_030_D0.BLIF CLK_000_D_0_.BLIF N_231_i_1 +11 1 +.names N_149_i.BLIF N_176.BLIF N_340 +11 1 +.names N_231_i_1.BLIF nEXP_SPACE_c.BLIF N_231_i +11 1 +.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n +0 1 +.names CYCLE_DMA_1_.BLIF pos_clk_un21_bgack_030_int_i_0_o3_0_x2.X2 +1 1 +.names N_291_i.BLIF N_293_i.BLIF N_152_i_1 +11 1 +.names N_183.BLIF sm_amiga_i_4__n.BLIF N_288 +11 1 +.names N_204_i.BLIF N_251_i.BLIF N_59_i_2 +11 1 +.names N_355.BLIF N_355_i_0 +0 1 +.names N_59_i_1.BLIF N_59_i_2.BLIF CYCLE_DMA_0_.D +11 1 +.names N_149_i.BLIF N_355_i_0.BLIF N_351 +11 1 +.names IPL_D0_0_.BLIF pos_clk_un1_ipl_i_0_x2.X1 +1 1 +.names N_150_i.BLIF N_191_i_i.BLIF N_233_0_1 +11 1 +.names N_315_i.BLIF cpu_est_i_2__n.BLIF N_357 +11 1 +.names N_192_i_i.BLIF N_360_i.BLIF N_233_0_2 +11 1 +.names N_205_i.BLIF N_206_i.BLIF pos_clk_un9_clk_000_pe_0_n +11 1 +.names ipl_c_0__n.BLIF pos_clk_un1_ipl_i_0_x2.X2 +1 1 +.names N_233_0_1.BLIF N_233_0_2.BLIF N_233_0 +11 1 +.names N_208_i.BLIF N_209_i.BLIF cpu_est_2_0_1__n +11 1 +.names AS_030_D0_i.BLIF N_156.BLIF N_214_1 +11 1 +.names N_171.BLIF sm_amiga_i_3__n.BLIF N_287 +11 1 +.names N_185_i.BLIF sm_amiga_i_i_7__n.BLIF N_214_2 +11 1 +.names N_160_i.BLIF RW_c.BLIF N_354 +11 1 +.names IPL_D0_1_.BLIF pos_clk_un1_ipl_i_0_x2_0.X1 +1 1 +.names N_214_1.BLIF N_214_2.BLIF N_214_3 +11 1 +.names AS_030_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_0.BLIF N_66_0 +11 1 +.names N_214_3.BLIF nEXP_SPACE_c.BLIF N_214 +11 1 +.names N_171.BLIF N_354_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_0 +11 1 +.names ipl_c_1__n.BLIF pos_clk_un1_ipl_i_0_x2_0.X2 +1 1 +.names un21_berr_1.BLIF FPU_SENSE_i.BLIF un21_fpu_cs_1 +11 1 +.names N_150_i.BLIF SM_AMIGA_4_.BLIF N_171_i +11 1 +.names un21_fpu_cs_1.BLIF N_156_i.BLIF un21_fpu_cs +11 1 +.names pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un3_n +0 1 +.names un21_berr_1.BLIF FPU_SENSE_c.BLIF un21_berr_1_0 +11 1 +.names cpu_est_i_1__n.BLIF pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un1_n +11 1 +.names IPL_D0_2_.BLIF pos_clk_un1_ipl_i_0_x2_1.X1 +1 1 +.names un21_berr_1_0.BLIF N_156_i.BLIF un21_berr +11 1 +.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n +11 1 +.names N_149_i.BLIF N_176.BLIF N_182_0_1 +11 1 +.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF N_18 +1- 1 +-1 1 +.names ipl_c_2__n.BLIF pos_clk_un1_ipl_i_0_x2_1.X2 +1 1 +.names N_182_0_1.BLIF SM_AMIGA_3_.BLIF N_182_0 +11 1 +.names N_18_i.BLIF RST_c.BLIF N_37_0 +11 1 +.names un10_ciin_3.BLIF un10_ciin_4.BLIF un10_ciin_8 +11 1 +.names N_149.BLIF cpu_est_0_1__un3_n +0 1 +.names un10_ciin_5.BLIF un10_ciin_6.BLIF un10_ciin_9 +11 1 +.names cpu_est_1_.BLIF N_149.BLIF cpu_est_0_1__un1_n +11 1 +.names CYCLE_DMA_1_.BLIF pos_clk_CYCLE_DMA_5_1_i_0_x2.X1 +1 1 +.names un10_ciin_7.BLIF un10_ciin_8.BLIF un10_ciin_10 +11 1 +.names cpu_est_2_1__n.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n +11 1 .names un10_ciin_9.BLIF a_decode_c_22__n.BLIF un10_ciin_11 11 1 -.names CLK_000_D_1_.BLIF clk_000_d_i_0__n.BLIF N_305_i -11 1 +.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D +1- 1 +-1 1 +.names N_199.BLIF pos_clk_CYCLE_DMA_5_1_i_0_x2.X2 +1 1 .names un10_ciin_10.BLIF un10_ciin_11.BLIF un10_ciin 11 1 -.names N_155_i.BLIF SM_AMIGA_6_.BLIF N_166_i -11 1 -.names N_217.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.X2 -1 1 -.names AS_030_000_SYNC_i.BLIF CLK_000_D_5_.BLIF N_171_i_1 -11 1 -.names AS_000_DMA_i.BLIF CLK_030_c_i.BLIF N_198_0 -11 1 -.names clk_000_d_i_4__n.BLIF nEXP_SPACE_c.BLIF N_171_i_2 -11 1 -.names N_171_i_1.BLIF N_171_i_2.BLIF N_171_i -11 1 -.names AS_000_c.BLIF AS_000_i +.names N_149.BLIF cpu_est_0_2__un3_n 0 1 +.names AS_030_000_SYNC_i.BLIF CLK_000_D_4_.BLIF N_163_i_1 +11 1 +.names cpu_est_2_.BLIF N_149.BLIF cpu_est_0_2__un1_n +11 1 +.names clk_000_d_i_3__n.BLIF nEXP_SPACE_c.BLIF N_163_i_2 +11 1 +.names cpu_est_2_2__n.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n +11 1 +.names CLK_000_D_2_.BLIF CLK_000_D_3_.D +1 1 +.names N_163_i_1.BLIF N_163_i_2.BLIF N_163_i +11 1 +.names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D +1- 1 +-1 1 .names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_INTreg.D 1 1 -.names a_decode_i_18__n.BLIF a_decode_i_19__n.BLIF N_161_i_3 +.names AS_000_i.BLIF BGACK_030_INT_i.BLIF pos_clk_un21_bgack_030_int_i_0_0_1_n 11 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i -0 1 -.names N_161_i_1.BLIF N_161_i_2.BLIF N_161_i_4 +.names N_154.BLIF N_355.BLIF N_197 11 1 -.names nEXP_SPACE_c.BLIF nEXP_SPACE_i +.names pos_clk_un21_bgack_030_int_i_0_o3_0_x2.BLIF N_350_i.BLIF pos_clk_un21_bgack_030_int_i_0_0_2_n +11 1 +.names RST_DLY_2_.BLIF rst_dly_i_2__n 0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_i_7_.C +.names pos_clk_un21_bgack_030_int_i_0_0_1_n.BLIF pos_clk_un21_bgack_030_int_i_0_0_2_n.BLIF pos_clk_un21_bgack_030_int_i_0_0_n +11 1 +.names N_149.BLIF rst_dly_i_2__n.BLIF N_198 +11 1 +.names N_149.BLIF N_278_i.BLIF N_138_i_1 +11 1 +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_208 +11 1 +.names N_282_i.BLIF RST_c.BLIF N_138_i_2 +11 1 +.names N_315.BLIF cpu_est_2_.BLIF N_210 +11 1 +.names N_138_i_1.BLIF N_138_i_2.BLIF SM_AMIGA_1_.D +11 1 +.names N_180.BLIF cpu_est_i_2__n.BLIF N_212 +11 1 +.names AS_000_i.BLIF N_199_i.BLIF N_59_i_1 +11 1 +.names N_174_i.BLIF RST_c.BLIF N_220 +11 1 +.names CLK_OSZI_c.BLIF IPL_D0_0_.C 1 1 +.names a_decode_c_17__n.BLIF a_decode_i_16__n.BLIF N_156_i_2 +11 1 +.names N_132.BLIF RST_c.BLIF N_219 +11 1 +.names a_decode_i_18__n.BLIF a_decode_i_19__n.BLIF N_156_i_3 +11 1 +.names a_decode_c_16__n.BLIF a_decode_i_16__n +0 1 .end diff --git a/Logic/BUS68030.bl1 b/Logic/BUS68030.bl1 index 8a83527..63fc923 100644 --- a/Logic/BUS68030.bl1 +++ b/Logic/BUS68030.bl1 @@ -1,109 +1,108 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Thu Oct 06 22:04:11 2016 +#$ DATE Sat Oct 15 23:48:24 2016 #$ MODULE bus68030 #$ PINS 75 SIZE_1_ AHIGH_31_ A_DECODE_23_ IPL_030_2_ IPL_2_ FC_1_ AS_030 AS_000 RW_000 \ -# DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 SIZE_0_ CLK_030 \ -# AHIGH_30_ CLK_000 AHIGH_29_ CLK_OSZI AHIGH_28_ CLK_DIV_OUT AHIGH_27_ CLK_EXP AHIGH_26_ \ -# FPU_CS AHIGH_25_ FPU_SENSE AHIGH_24_ DSACK1 A_DECODE_22_ DTACK A_DECODE_21_ AVEC \ -# A_DECODE_20_ E A_DECODE_19_ VPA A_DECODE_18_ VMA A_DECODE_17_ RST A_DECODE_16_ RESET \ -# A_DECODE_15_ RW A_DECODE_14_ AMIGA_ADDR_ENABLE A_DECODE_13_ AMIGA_BUS_DATA_DIR \ -# A_DECODE_12_ AMIGA_BUS_ENABLE_LOW A_DECODE_11_ AMIGA_BUS_ENABLE_HIGH A_DECODE_10_ \ -# CIIN A_DECODE_9_ A_DECODE_8_ A_DECODE_7_ A_DECODE_6_ A_DECODE_5_ A_DECODE_4_ \ -# A_DECODE_3_ A_DECODE_2_ A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ IPL_0_ FC_0_ A_1_ -#$ NODES 600 rst_dly_i_1__n N_41_0 sm_amiga_i_5__n a_c_i_0__n rst_dly_i_0__n \ -# size_c_i_1__n sm_amiga_i_i_7__n pos_clk_un10_sm_amiga_i_n AS_030_D0_i un1_as_000_i \ -# AS_000_INT_i un10_ciin_i a_i_1__n N_260_0 a_decode_i_16__n N_229_i \ -# inst_BGACK_030_INTreg a_decode_i_18__n N_230_i vcc_n_n a_decode_i_19__n N_298_0 \ -# inst_VMA_INTreg ahigh_i_30__n N_48_0 gnd_n_n ahigh_i_31__n N_299_i \ -# un1_amiga_bus_enable_low ahigh_i_28__n N_345_i un7_as_030 ahigh_i_29__n N_349_i \ -# un1_UDS_000_INT ahigh_i_26__n un1_DS_000_ENABLE_0_sqmuxa_i un1_LDS_000_INT \ -# ahigh_i_27__n N_180_i un1_SM_AMIGA_0_sqmuxa_1 ahigh_i_24__n N_181_i un10_ciin \ -# ahigh_i_25__n N_326_i un21_fpu_cs N_206_i un21_berr N_207_i N_186_i un6_ds_030 N_208_i \ -# N_163_i cpu_est_2_ N_197_0 cpu_est_3_ N_79_i N_213_i cpu_est_0_ N_78_i N_214_i \ -# cpu_est_1_ un6_ds_030_i N_215_i inst_AMIGA_BUS_ENABLE_DMA_LOW N_165_i \ -# inst_AS_030_D0 N_169_i N_199_i inst_AS_030_000_SYNC un7_as_030_i N_191_0 \ -# inst_BGACK_030_INT_D AMIGA_BUS_ENABLE_DMA_LOW_i N_275_i inst_AS_000_DMA AS_030_c \ -# N_187_0 inst_DS_000_DMA LDS_000_c_i CYCLE_DMA_0_ AS_000_c UDS_000_c_i CYCLE_DMA_1_ \ -# N_184_i inst_VPA_D RW_000_c clk_000_d_i_4__n CLK_000_D_2_ N_171_i CLK_000_D_4_ \ -# AS_030_000_SYNC_i inst_DTACK_D0 UDS_000_c N_161_i inst_RESET_OUT CLK_000_D_1_ \ -# LDS_000_c N_113_0 CLK_000_D_0_ N_338_i inst_CLK_OUT_PRE_50 size_c_0__n N_339_i \ -# inst_CLK_OUT_PRE_D IPL_D0_0_ size_c_1__n N_335_i IPL_D0_1_ N_336_i IPL_D0_2_ \ -# ahigh_c_24__n CLK_000_D_3_ N_334_i CLK_000_D_5_ ahigh_c_25__n \ -# pos_clk_size_dma_6_0_1__n pos_clk_un6_bg_030_n N_333_i \ -# inst_AMIGA_BUS_ENABLE_DMA_HIGH ahigh_c_26__n pos_clk_size_dma_6_0_0__n \ -# pos_clk_ipl_n N_295_i SM_AMIGA_1_ ahigh_c_27__n N_332_i inst_UDS_000_INT \ -# inst_DS_000_ENABLE ahigh_c_28__n N_292_i inst_LDS_000_INT N_302_0 \ -# pos_clk_un9_bg_030_n ahigh_c_29__n N_300_0 SM_AMIGA_6_ N_290_i SM_AMIGA_4_ \ -# ahigh_c_30__n SM_AMIGA_0_ N_273_i SIZE_DMA_0_ ahigh_c_31__n SIZE_DMA_1_ N_327_i \ -# inst_RW_000_INT inst_RW_000_DMA N_270_i RST_DLY_0_ RST_DLY_1_ N_269_i RST_DLY_2_ \ -# inst_A0_DMA N_267_i pos_clk_a0_dma_3_n N_324_i inst_CLK_030_H \ -# pos_clk_rw_000_int_5_n un1_SM_AMIGA_0_sqmuxa_1_0 inst_DSACK1_INT N_319_i \ -# inst_AS_000_INT N_320_i SM_AMIGA_5_ SM_AMIGA_3_ RW_c_i SM_AMIGA_2_ \ -# pos_clk_rw_000_int_5_0_n N_227_i N_297_0 N_15_i N_40_0 N_16_i N_15 N_39_0 N_16 N_19_i \ -# N_19 N_36_0 N_20 N_20_i N_22 N_35_0 N_23 N_22_i N_24 N_33_0 N_23_i N_32_0 a_decode_c_16__n \ -# N_24_i N_31_0 a_decode_c_17__n BG_030_c_i pos_clk_un6_bg_030_i_n a_decode_c_18__n \ -# pos_clk_un9_bg_030_0_n N_161_i_1 a_decode_c_19__n N_161_i_2 N_161_i_3 \ -# a_decode_c_20__n N_161_i_4 N_233_i_1 a_decode_c_21__n N_233_i_2 N_180_i_1 \ -# a_decode_c_22__n N_180_i_2 pos_clk_un10_sm_amiga_i_1_n a_decode_c_23__n N_196_0_1 \ -# N_188_i_1 a_c_0__n un10_ciin_1 un10_ciin_2 a_c_1__n un10_ciin_3 un10_ciin_4 \ -# nEXP_SPACE_c un10_ciin_5 SM_AMIGA_i_7_ un10_ciin_6 pos_clk_size_dma_6_0__n BERR_c \ -# un10_ciin_7 pos_clk_size_dma_6_1__n un10_ciin_8 G_107 BG_030_c un10_ciin_9 G_108 \ -# un10_ciin_10 G_109 BG_000DFFreg un10_ciin_11 N_171_i_1 N_78 N_171_i_2 N_79 BGACK_000_c \ -# N_227_1 N_260 N_227_2 N_139 CLK_030_c N_227_3 N_141 un21_fpu_cs_1 N_165 un21_berr_1_0 \ -# N_169 N_235_i_1 N_297 CLK_OSZI_c N_235_i_2 N_256_1 N_300 N_256_2 N_302 CLK_OUT_INTreg \ -# N_232_i_1 N_113 N_232_i_2 N_305 N_219_1 N_155 FPU_SENSE_c N_219_2 N_163 N_218_1 N_166 \ -# IPL_030DFF_0_reg N_218_2 N_171 N_347_1 N_180 IPL_030DFF_1_reg N_347_2 N_184 N_136_i_1 \ -# N_191 IPL_030DFF_2_reg N_146_i_1 N_199 N_142_i_1 N_205 ipl_c_0__n N_234_i_1 N_306 \ -# N_302_0_1 N_215 ipl_c_1__n N_63_i_1 N_221 N_154_i_1 N_227 ipl_c_2__n N_152_i_1 N_230 \ -# N_148_i_1 N_319 N_144_i_1 N_320 DTACK_c N_140_i_1 N_267 pos_clk_un6_bg_030_1_n N_324 \ -# N_230_1 N_269 N_221_1 N_270 VPA_c N_215_1 N_327 N_306_1 N_273 pos_clk_ipl_1_n N_275 RST_c \ -# ipl_030_0_2__un3_n N_290 ipl_030_0_2__un1_n N_292 ipl_030_0_2__un0_n N_295 RW_c \ -# ipl_030_0_1__un3_n N_332 ipl_030_0_1__un1_n N_333 fc_c_0__n ipl_030_0_1__un0_n N_334 \ -# ipl_030_0_0__un3_n N_335 fc_c_1__n ipl_030_0_0__un1_n N_336 ipl_030_0_0__un0_n N_338 \ -# cpu_est_0_3__un3_n N_339 AMIGA_BUS_DATA_DIR_c cpu_est_0_3__un1_n N_350 \ -# cpu_est_0_3__un0_n pos_clk_CYCLE_DMA_5_1_i_x2 vma_int_0_un3_n N_161 \ -# vma_int_0_un1_n N_213 vma_int_0_un0_n N_214 VPA_c_i cpu_est_0_1__un3_n N_197 N_52_0 \ -# cpu_est_0_1__un1_n N_159 DTACK_c_i cpu_est_0_1__un0_n N_326 N_53_0 \ -# cpu_est_0_2__un3_n un21_berr_1 ipl_c_i_0__n cpu_est_0_2__un1_n N_181 N_49_0 \ -# cpu_est_0_2__un0_n pos_clk_un21_bgack_030_int_i_i_a2_i_x2 ipl_c_i_1__n \ -# ds_000_dma_0_un3_n un1_DS_000_ENABLE_0_sqmuxa N_50_0 ds_000_dma_0_un1_n N_349 \ -# ipl_c_i_2__n ds_000_dma_0_un0_n N_345 N_51_0 as_000_dma_0_un3_n N_229 N_25_i \ -# as_000_dma_0_un1_n N_14 N_28_0 as_000_dma_0_un0_n N_21 N_26_i bgack_030_int_0_un3_n \ -# N_3 N_29_0 bgack_030_int_0_un1_n N_301 N_27_i bgack_030_int_0_un0_n N_4 N_30_0 \ -# ds_000_enable_0_un3_n N_303 N_222_i ds_000_enable_0_un1_n N_8 N_223_i \ -# ds_000_enable_0_un0_n pos_clk_un6_bgack_000_n N_192_i uds_000_int_0_un3_n N_9 \ -# N_231_i uds_000_int_0_un1_n N_65 N_237_i uds_000_int_0_un0_n N_217 \ -# lds_000_int_0_un3_n N_216 N_342_i lds_000_int_0_un1_n N_248 N_341_i \ -# lds_000_int_0_un0_n N_198 un1_amiga_bus_enable_dma_high_i_m2_0__un3_n N_291 \ -# N_160_0 un1_amiga_bus_enable_dma_high_i_m2_0__un1_n N_353 N_164_i \ -# un1_amiga_bus_enable_dma_high_i_m2_0__un0_n N_256 VMA_INT_i \ -# amiga_bus_enable_dma_high_0_un3_n N_18 N_347_i amiga_bus_enable_dma_high_0_un1_n \ -# pos_clk_un9_clk_000_pe_n N_348_i amiga_bus_enable_dma_high_0_un0_n cpu_est_2_1__n \ -# N_188_i bg_000_0_un3_n cpu_est_2_2__n N_245_0 bg_000_0_un1_n N_209 N_194_0 \ -# bg_000_0_un0_n N_211 N_196_0 size_dma_0_0__un3_n N_220 size_dma_0_0__un1_n N_222 \ -# N_211_i size_dma_0_0__un0_n N_162 N_209_i size_dma_0_1__un3_n N_224 N_306_i \ -# size_dma_0_1__un1_n N_193 N_193_0 size_dma_0_1__un0_n N_225 N_190_0 \ -# as_030_000_sync_0_un3_n N_190 N_183_i as_030_000_sync_0_un1_n N_346 N_162_i \ -# as_030_000_sync_0_un0_n N_352 N_346_i rw_000_int_0_un3_n N_219 N_159_0 \ -# rw_000_int_0_un1_n N_218 N_305_i rw_000_int_0_un0_n N_183 N_210_i rw_000_dma_0_un3_n \ -# N_196 N_225_i rw_000_dma_0_un1_n N_188 N_224_i rw_000_dma_0_un0_n N_194 N_296_i \ -# a0_dma_0_un3_n N_347 N_352_i a0_dma_0_un1_n N_348 cpu_est_2_0_2__n a0_dma_0_un0_n \ -# N_160 N_220_i amiga_bus_enable_dma_low_0_un3_n N_341 N_221_i \ -# amiga_bus_enable_dma_low_0_un1_n N_342 cpu_est_2_0_1__n \ -# amiga_bus_enable_dma_low_0_un0_n N_231 N_219_i a_decode_15__n N_237 N_218_i N_223 \ -# pos_clk_un9_clk_000_pe_0_n a_decode_14__n N_27 clk_000_d_i_2__n N_26 N_157_i \ -# a_decode_13__n N_25 N_18_i un1_amiga_bus_enable_low_i N_37_0 a_decode_12__n \ -# un21_fpu_cs_i cpu_est_i_2__n N_217_i a_decode_11__n sm_amiga_i_0__n N_216_i \ -# sm_amiga_i_2__n CLK_030_c_i a_decode_10__n sm_amiga_i_1__n N_198_0 cpu_est_i_0__n \ -# N_166_i a_decode_9__n VPA_D_i N_155_i DTACK_D0_i N_303_0 a_decode_8__n AS_030_i \ -# N_291_i DSACK1_INT_i N_301_0 a_decode_7__n cpu_est_i_3__n N_256_i sm_amiga_i_3__n \ -# N_248_i a_decode_6__n cpu_est_i_1__n AMIGA_BUS_DATA_DIR_c_0 clk_000_d_i_1__n \ -# N_353_i a_decode_5__n N_350_i_0 pos_clk_un6_bgack_000_0_n rst_dly_i_2__n N_65_0 \ -# a_decode_4__n nEXP_SPACE_i N_3_i AS_000_i N_45_0 a_decode_3__n BGACK_030_INT_i N_4_i \ -# sm_amiga_i_6__n N_44_0 a_decode_2__n clk_000_d_i_0__n N_8_i RW_000_i N_42_0 \ -# CLK_030_H_i UDS_000_INT_i AS_000_DMA_i un1_UDS_000_INT_0 cycle_dma_i_0__n \ -# LDS_000_INT_i DS_000_DMA_i un1_LDS_000_INT_0 RESET_OUT_i N_21_i sm_amiga_i_4__n \ -# N_34_0 FPU_SENSE_i N_14_i +# DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BG_000 SIZE_0_ BGACK_030 AHIGH_30_ \ +# BGACK_000 AHIGH_29_ CLK_030 AHIGH_28_ CLK_000 AHIGH_27_ CLK_OSZI AHIGH_26_ CLK_DIV_OUT \ +# AHIGH_25_ CLK_EXP AHIGH_24_ FPU_CS A_DECODE_22_ FPU_SENSE A_DECODE_21_ DSACK1 \ +# A_DECODE_20_ DTACK A_DECODE_19_ AVEC A_DECODE_18_ E A_DECODE_17_ VPA A_DECODE_16_ VMA \ +# A_DECODE_15_ RST A_DECODE_14_ RESET A_DECODE_13_ RW A_DECODE_12_ AMIGA_ADDR_ENABLE \ +# A_DECODE_11_ AMIGA_BUS_DATA_DIR A_DECODE_10_ AMIGA_BUS_ENABLE_LOW A_DECODE_9_ \ +# AMIGA_BUS_ENABLE_HIGH A_DECODE_8_ CIIN A_DECODE_7_ A_DECODE_6_ A_DECODE_5_ \ +# A_DECODE_4_ A_DECODE_3_ A_DECODE_2_ A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ IPL_0_ FC_0_ A_1_ +#$ NODES 598 ipl_i_2__n N_233_0 ipl_i_1__n N_360_i ipl_i_0__n N_191_i_i a_i_1__n \ +# N_192_i_i AS_000_DMA_i AS_000_i N_199_i CLK_030_H_i N_204_i AS_030_000_SYNC_i \ +# inst_BGACK_030_INTreg AMIGA_BUS_ENABLE_DMA_HIGH_i N_282_i vcc_n_n cycle_dma_i_0__n \ +# N_278_i inst_VMA_INTreg ahigh_i_30__n N_186_i gnd_n_n ahigh_i_31__n N_185_i \ +# un1_amiga_bus_enable_low ahigh_i_28__n CLK_030_c_i un7_as_030 ahigh_i_29__n N_184_0 \ +# un1_LDS_000_INT ahigh_i_26__n N_179_0 un1_UDS_000_INT ahigh_i_27__n N_251_i \ +# un10_ciin ahigh_i_24__n LDS_000_c_i un21_fpu_cs ahigh_i_25__n UDS_000_c_i un21_berr \ +# N_172_i un6_ds_030 pos_clk_un21_bgack_030_int_i_0_0_n cpu_est_2_ N_163_i cpu_est_3_ \ +# clk_000_d_i_3__n cpu_est_0_ N_115_i N_350_i cpu_est_1_ N_114_i un1_rw_i \ +# inst_AMIGA_BUS_ENABLE_DMA_HIGH un6_ds_030_i N_126_0 inst_AMIGA_BUS_ENABLE_DMA_LOW \ +# DS_000_DMA_i N_313_i inst_AS_030_D0 N_132_i N_231_i inst_AS_030_000_SYNC N_133_i \ +# N_291_i inst_BGACK_030_INT_D un7_as_030_i inst_AS_000_DMA \ +# AMIGA_BUS_ENABLE_DMA_LOW_i N_288_i inst_DS_000_DMA AS_030_c CYCLE_DMA_0_ N_287_i \ +# CYCLE_DMA_1_ AS_000_c N_340_i inst_VPA_D CLK_000_D_3_ RW_000_c N_284_i inst_DTACK_D0 \ +# inst_RESET_OUT N_275_i CLK_000_D_1_ UDS_000_c pos_clk_size_dma_6_0_1__n \ +# CLK_000_D_0_ N_268_i inst_CLK_OUT_PRE_50 LDS_000_c pos_clk_size_dma_6_0_0__n \ +# inst_CLK_OUT_PRE_D N_265_i IPL_D0_0_ size_c_0__n N_267_i IPL_D0_1_ IPL_D0_2_ \ +# size_c_1__n N_337_i CLK_000_D_2_ N_338_i CLK_000_D_4_ ahigh_c_24__n N_55_0 \ +# inst_LDS_000_INT un1_as_000_i inst_DS_000_ENABLE ahigh_c_25__n N_245_0 \ +# inst_UDS_000_INT N_229_i pos_clk_un9_bg_030_n ahigh_c_26__n SM_AMIGA_6_ N_227_i \ +# SM_AMIGA_4_ ahigh_c_27__n SM_AMIGA_1_ N_226_i SM_AMIGA_0_ ahigh_c_28__n N_246_0 \ +# SIZE_DMA_0_ N_332_i SIZE_DMA_1_ ahigh_c_29__n pos_clk_ds_000_dma_4_0_n \ +# inst_RW_000_INT N_48_0 inst_RW_000_DMA ahigh_c_30__n pos_clk_rw_000_dma_3_0_n \ +# RST_DLY_0_ N_218_i RST_DLY_1_ ahigh_c_31__n RST_DLY_2_ inst_A0_DMA un10_ciin_i \ +# pos_clk_a0_dma_3_n N_62_0 pos_clk_rw_000_dma_3_n N_215_i inst_CLK_030_H N_216_i \ +# inst_DSACK1_INT un10_amiga_bus_enable_high_i inst_AS_000_INT N_214_i SM_AMIGA_5_ \ +# N_310_0 SM_AMIGA_3_ N_24_i SM_AMIGA_2_ N_33_0 pos_clk_ds_000_dma_4_n N_23_i N_3 N_32_0 \ +# N_4 N_22_i N_31_0 N_3_i N_45_0 N_4_i N_44_0 N_15 N_15_i N_19 N_40_0 N_20 N_19_i N_22 N_36_0 \ +# N_23 N_20_i N_24 N_35_0 N_25 N_25_i N_26 N_30_0 N_27 N_26_i N_29_0 N_27_i a_decode_c_16__n \ +# N_28_0 BG_030_c_i a_decode_c_17__n pos_clk_un9_bg_030_0_n N_235_i_1 \ +# a_decode_c_18__n N_235_i_2 N_156_i_1 a_decode_c_19__n N_156_i_2 N_156_i_3 \ +# a_decode_c_20__n N_156_i_4 pos_clk_un10_sm_amiga_i_1_n a_decode_c_21__n N_176_i_1 \ +# un10_ciin_1 a_decode_c_22__n un10_ciin_2 un10_ciin_3 a_decode_c_23__n un10_ciin_4 \ +# un10_ciin_5 a_c_0__n un10_ciin_6 un10_ciin_7 a_c_1__n un10_ciin_8 SM_AMIGA_i_7_ \ +# un10_ciin_9 pos_clk_size_dma_6_0__n nEXP_SPACE_c un10_ciin_10 \ +# pos_clk_size_dma_6_1__n un10_ciin_11 N_199 BERR_c N_163_i_1 \ +# pos_clk_un21_bgack_030_int_i_0_n N_163_i_2 N_231 BG_030_c \ +# pos_clk_un21_bgack_030_int_i_0_0_1_n N_233 pos_clk_un21_bgack_030_int_i_0_0_2_n \ +# N_111 BG_000DFFreg N_138_i_1 N_112 N_138_i_2 N_113 N_59_i_1 N_114 BGACK_000_c N_59_i_2 \ +# N_115 N_233_0_1 N_245 CLK_030_c N_233_0_2 N_246 N_214_1 N_62 N_214_2 N_214_3 N_132 \ +# CLK_OSZI_c un21_fpu_cs_1 N_133 un21_berr_1_0 N_310 N_182_0_1 N_126 CLK_OUT_INTreg \ +# N_234_i_1 N_149 N_234_i_2 N_150 N_206_1 N_158 FPU_SENSE_c N_206_2 N_160 N_205_1 N_163 \ +# IPL_030DFF_0_reg N_205_2 N_172 N_352_1 N_179 IPL_030DFF_1_reg N_352_2 N_184 N_231_i_1 \ +# N_185 IPL_030DFF_2_reg N_152_i_1 N_196 N_144_i_1 N_203 ipl_c_0__n N_142_i_1 N_204 \ +# N_312_i_1 N_209 ipl_c_1__n N_236_i_1 N_214 N_148_i_1 N_215 ipl_c_2__n N_136_i_1 N_216 \ +# N_246_0_1 N_218 N_249_i_1 N_224 DTACK_c N_57_i_1 N_332 N_338_1 N_226 N_224_1 N_227 \ +# N_216_1 N_229 VPA_c N_209_1 N_337 N_203_1 N_338 N_196_1 N_265 RST_c cpu_est_0_3__un3_n \ +# N_267 cpu_est_0_3__un1_n N_268 cpu_est_0_3__un0_n N_275 RW_c rw_000_int_0_un3_n N_278 \ +# rw_000_int_0_un1_n N_282 fc_c_0__n rw_000_int_0_un0_n N_284 vma_int_0_un3_n N_340 \ +# fc_c_1__n vma_int_0_un1_n N_287 vma_int_0_un0_n N_288 cpu_est_0_1__un3_n N_291 \ +# AMIGA_BUS_DATA_DIR_c cpu_est_0_1__un1_n N_293 cpu_est_0_1__un0_n N_350 \ +# cpu_est_0_2__un3_n N_355 cpu_est_0_2__un1_n \ +# pos_clk_un21_bgack_030_int_i_0_o3_0_x2 cpu_est_0_2__un0_n pos_clk_un1_ipl_i_0_x2 \ +# N_16_i uds_000_int_0_un3_n pos_clk_un1_ipl_i_0_x2_0 N_39_0 uds_000_int_0_un1_n \ +# pos_clk_un1_ipl_i_0_x2_1 VPA_c_i uds_000_int_0_un0_n pos_clk_CYCLE_DMA_5_1_i_0_x2 \ +# N_52_0 lds_000_int_0_un3_n N_156 DTACK_c_i lds_000_int_0_un1_n N_201 N_53_0 \ +# lds_000_int_0_un0_n N_202 N_210_i bgack_030_int_0_un3_n N_154 N_211_i \ +# bgack_030_int_0_un1_n un21_berr_1 N_189_i bgack_030_int_0_un0_n N_174 \ +# un1_SM_AMIGA_0_sqmuxa_1_0 ds_000_enable_0_un3_n N_223 RW_c_i ds_000_enable_0_un1_n \ +# N_221 N_311_0 ds_000_enable_0_un0_n N_222 N_336_i size_dma_0_0__un3_n N_219 N_244_i \ +# size_dma_0_0__un1_n N_220 size_dma_0_0__un0_n pos_clk_un6_bgack_000_n N_314_0 \ +# size_dma_0_1__un3_n N_359 N_159_i size_dma_0_1__un1_n N_8 VMA_INT_i \ +# size_dma_0_1__un0_n N_14 N_352_i ipl_030_0_0__un3_n N_21 N_353_i ipl_030_0_0__un1_n \ +# N_9 N_293_i ipl_030_0_0__un0_n un1_DS_000_ENABLE_0_sqmuxa N_175_i \ +# ipl_030_0_1__un3_n N_66 N_176_i ipl_030_0_1__un1_n N_171 ipl_030_0_1__un0_n N_354 \ +# N_198_i ipl_030_0_2__un3_n N_18 N_197_i ipl_030_0_2__un1_n pos_clk_un9_clk_000_pe_n \ +# N_196_i ipl_030_0_2__un0_n cpu_est_2_1__n N_183_0 a0_dma_0_un3_n cpu_est_2_2__n \ +# N_182_0 a0_dma_0_un1_n N_197 N_180_0 a0_dma_0_un0_n N_198 N_178_0 \ +# amiga_bus_enable_dma_low_0_un3_n N_208 N_82_i amiga_bus_enable_dma_low_0_un1_n \ +# N_210 N_315_i amiga_bus_enable_dma_low_0_un0_n N_315 N_351_i \ +# amiga_bus_enable_dma_high_0_un3_n N_212 N_154_0 amiga_bus_enable_dma_high_0_un1_n \ +# N_180 N_149_i amiga_bus_enable_dma_high_0_un0_n N_213 N_207_i bg_000_0_un3_n N_178 \ +# N_228_i bg_000_0_un1_n N_228 bg_000_0_un0_n N_182 N_213_i ds_000_dma_0_un3_n N_176 \ +# N_212_i ds_000_dma_0_un1_n N_183 N_309_i ds_000_dma_0_un0_n N_351 N_357_i \ +# as_000_dma_0_un3_n N_357 cpu_est_2_0_2__n as_000_dma_0_un1_n N_206 N_208_i \ +# as_000_dma_0_un0_n N_205 N_209_i as_030_000_sync_0_un3_n N_352 cpu_est_2_0_1__n \ +# as_030_000_sync_0_un1_n N_353 N_206_i as_030_000_sync_0_un0_n N_314 N_205_i \ +# rw_000_dma_0_un3_n N_244 pos_clk_un9_clk_000_pe_0_n rw_000_dma_0_un1_n N_336 N_18_i \ +# rw_000_dma_0_un0_n N_311 N_37_0 a_decode_15__n un1_SM_AMIGA_0_sqmuxa_1 N_171_i N_211 \ +# N_354_i a_decode_14__n N_16 un1_DS_000_ENABLE_0_sqmuxa_0 \ +# un1_amiga_bus_enable_low_i N_66_0 a_decode_13__n un21_fpu_cs_i UDS_000_INT_i \ +# cpu_est_i_2__n un1_UDS_000_INT_0 a_decode_12__n cpu_est_i_0__n LDS_000_INT_i \ +# VPA_D_i un1_LDS_000_INT_0 a_decode_11__n DTACK_D0_i N_21_i cpu_est_i_3__n N_34_0 \ +# a_decode_10__n sm_amiga_i_i_7__n N_14_i sm_amiga_i_5__n N_41_0 a_decode_9__n \ +# sm_amiga_i_3__n N_8_i cpu_est_i_1__n N_42_0 a_decode_8__n clk_000_d_i_1__n \ +# a_c_i_0__n N_355_i_0 size_c_i_1__n a_decode_7__n sm_amiga_i_4__n \ +# pos_clk_un10_sm_amiga_i_n sm_amiga_i_2__n N_359_i a_decode_6__n rst_dly_i_0__n \ +# pos_clk_un6_bgack_000_0_n rst_dly_i_2__n N_220_i a_decode_5__n a_decode_i_19__n \ +# N_219_i a_decode_i_18__n a_decode_4__n a_decode_i_16__n N_222_i RW_000_i N_221_i \ +# a_decode_3__n sm_amiga_i_0__n AS_030_i N_223_i a_decode_2__n AS_000_INT_i N_224_i \ +# DSACK1_INT_i AMIGA_BUS_DATA_DIR_c_0 clk_000_d_i_0__n N_150_i sm_amiga_i_6__n \ +# N_156_i sm_amiga_i_1__n N_160_i FPU_SENSE_i N_174_i rst_dly_i_1__n N_158_i \ +# AS_030_D0_i N_201_i BGACK_030_INT_i N_202_i nEXP_SPACE_i N_203_i RESET_OUT_i .model bus68030 .inputs A_DECODE_23_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF \ BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF FPU_SENSE.BLIF \ @@ -116,323 +115,305 @@ A_DECODE_4_.BLIF A_DECODE_3_.BLIF A_DECODE_2_.BLIF IPL_1_.BLIF IPL_0_.BLIF \ FC_0_.BLIF A_1_.BLIF SIZE_1_.BLIF AHIGH_31_.BLIF AS_030.BLIF AS_000.BLIF \ RW_000.BLIF UDS_000.BLIF LDS_000.BLIF BERR.BLIF RW.BLIF SIZE_0_.BLIF \ AHIGH_30_.BLIF AHIGH_29_.BLIF AHIGH_28_.BLIF AHIGH_27_.BLIF AHIGH_26_.BLIF \ -AHIGH_25_.BLIF AHIGH_24_.BLIF A_0_.BLIF rst_dly_i_1__n.BLIF N_41_0.BLIF \ -sm_amiga_i_5__n.BLIF a_c_i_0__n.BLIF rst_dly_i_0__n.BLIF size_c_i_1__n.BLIF \ -sm_amiga_i_i_7__n.BLIF pos_clk_un10_sm_amiga_i_n.BLIF AS_030_D0_i.BLIF \ -un1_as_000_i.BLIF AS_000_INT_i.BLIF un10_ciin_i.BLIF a_i_1__n.BLIF \ -N_260_0.BLIF a_decode_i_16__n.BLIF N_229_i.BLIF inst_BGACK_030_INTreg.BLIF \ -a_decode_i_18__n.BLIF N_230_i.BLIF vcc_n_n.BLIF a_decode_i_19__n.BLIF \ -N_298_0.BLIF inst_VMA_INTreg.BLIF ahigh_i_30__n.BLIF N_48_0.BLIF gnd_n_n.BLIF \ -ahigh_i_31__n.BLIF N_299_i.BLIF un1_amiga_bus_enable_low.BLIF \ -ahigh_i_28__n.BLIF N_345_i.BLIF un7_as_030.BLIF ahigh_i_29__n.BLIF \ -N_349_i.BLIF un1_UDS_000_INT.BLIF ahigh_i_26__n.BLIF \ -un1_DS_000_ENABLE_0_sqmuxa_i.BLIF un1_LDS_000_INT.BLIF ahigh_i_27__n.BLIF \ -N_180_i.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF ahigh_i_24__n.BLIF N_181_i.BLIF \ -un10_ciin.BLIF ahigh_i_25__n.BLIF N_326_i.BLIF un21_fpu_cs.BLIF N_206_i.BLIF \ -un21_berr.BLIF N_207_i.BLIF N_186_i.BLIF un6_ds_030.BLIF N_208_i.BLIF \ -N_163_i.BLIF cpu_est_2_.BLIF N_197_0.BLIF cpu_est_3_.BLIF N_79_i.BLIF \ -N_213_i.BLIF cpu_est_0_.BLIF N_78_i.BLIF N_214_i.BLIF cpu_est_1_.BLIF \ -un6_ds_030_i.BLIF N_215_i.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF N_165_i.BLIF \ -inst_AS_030_D0.BLIF N_169_i.BLIF N_199_i.BLIF inst_AS_030_000_SYNC.BLIF \ -un7_as_030_i.BLIF N_191_0.BLIF inst_BGACK_030_INT_D.BLIF \ -AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF N_275_i.BLIF inst_AS_000_DMA.BLIF \ -AS_030_c.BLIF N_187_0.BLIF inst_DS_000_DMA.BLIF LDS_000_c_i.BLIF \ -CYCLE_DMA_0_.BLIF AS_000_c.BLIF UDS_000_c_i.BLIF CYCLE_DMA_1_.BLIF \ -N_184_i.BLIF inst_VPA_D.BLIF RW_000_c.BLIF clk_000_d_i_4__n.BLIF \ -CLK_000_D_2_.BLIF N_171_i.BLIF CLK_000_D_4_.BLIF AS_030_000_SYNC_i.BLIF \ -inst_DTACK_D0.BLIF UDS_000_c.BLIF N_161_i.BLIF inst_RESET_OUT.BLIF \ -CLK_000_D_1_.BLIF LDS_000_c.BLIF N_113_0.BLIF CLK_000_D_0_.BLIF N_338_i.BLIF \ -inst_CLK_OUT_PRE_50.BLIF size_c_0__n.BLIF N_339_i.BLIF inst_CLK_OUT_PRE_D.BLIF \ -IPL_D0_0_.BLIF size_c_1__n.BLIF N_335_i.BLIF IPL_D0_1_.BLIF N_336_i.BLIF \ -IPL_D0_2_.BLIF ahigh_c_24__n.BLIF CLK_000_D_3_.BLIF N_334_i.BLIF \ -CLK_000_D_5_.BLIF ahigh_c_25__n.BLIF pos_clk_size_dma_6_0_1__n.BLIF \ -pos_clk_un6_bg_030_n.BLIF N_333_i.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ -ahigh_c_26__n.BLIF pos_clk_size_dma_6_0_0__n.BLIF pos_clk_ipl_n.BLIF \ -N_295_i.BLIF SM_AMIGA_1_.BLIF ahigh_c_27__n.BLIF N_332_i.BLIF \ -inst_UDS_000_INT.BLIF inst_DS_000_ENABLE.BLIF ahigh_c_28__n.BLIF N_292_i.BLIF \ -inst_LDS_000_INT.BLIF N_302_0.BLIF pos_clk_un9_bg_030_n.BLIF \ -ahigh_c_29__n.BLIF N_300_0.BLIF SM_AMIGA_6_.BLIF N_290_i.BLIF SM_AMIGA_4_.BLIF \ -ahigh_c_30__n.BLIF SM_AMIGA_0_.BLIF N_273_i.BLIF SIZE_DMA_0_.BLIF \ -ahigh_c_31__n.BLIF SIZE_DMA_1_.BLIF N_327_i.BLIF inst_RW_000_INT.BLIF \ -inst_RW_000_DMA.BLIF N_270_i.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF N_269_i.BLIF \ -RST_DLY_2_.BLIF inst_A0_DMA.BLIF N_267_i.BLIF pos_clk_a0_dma_3_n.BLIF \ -N_324_i.BLIF inst_CLK_030_H.BLIF pos_clk_rw_000_int_5_n.BLIF \ -un1_SM_AMIGA_0_sqmuxa_1_0.BLIF inst_DSACK1_INT.BLIF N_319_i.BLIF \ -inst_AS_000_INT.BLIF N_320_i.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_3_.BLIF \ -RW_c_i.BLIF SM_AMIGA_2_.BLIF pos_clk_rw_000_int_5_0_n.BLIF N_227_i.BLIF \ -N_297_0.BLIF N_15_i.BLIF N_40_0.BLIF N_16_i.BLIF N_15.BLIF N_39_0.BLIF \ -N_16.BLIF N_19_i.BLIF N_19.BLIF N_36_0.BLIF N_20.BLIF N_20_i.BLIF N_22.BLIF \ -N_35_0.BLIF N_23.BLIF N_22_i.BLIF N_24.BLIF N_33_0.BLIF N_23_i.BLIF \ -N_32_0.BLIF a_decode_c_16__n.BLIF N_24_i.BLIF N_31_0.BLIF \ -a_decode_c_17__n.BLIF BG_030_c_i.BLIF pos_clk_un6_bg_030_i_n.BLIF \ -a_decode_c_18__n.BLIF pos_clk_un9_bg_030_0_n.BLIF N_161_i_1.BLIF \ -a_decode_c_19__n.BLIF N_161_i_2.BLIF N_161_i_3.BLIF a_decode_c_20__n.BLIF \ -N_161_i_4.BLIF N_233_i_1.BLIF a_decode_c_21__n.BLIF N_233_i_2.BLIF \ -N_180_i_1.BLIF a_decode_c_22__n.BLIF N_180_i_2.BLIF \ -pos_clk_un10_sm_amiga_i_1_n.BLIF a_decode_c_23__n.BLIF N_196_0_1.BLIF \ -N_188_i_1.BLIF a_c_0__n.BLIF un10_ciin_1.BLIF un10_ciin_2.BLIF a_c_1__n.BLIF \ -un10_ciin_3.BLIF un10_ciin_4.BLIF nEXP_SPACE_c.BLIF un10_ciin_5.BLIF \ -SM_AMIGA_i_7_.BLIF un10_ciin_6.BLIF pos_clk_size_dma_6_0__n.BLIF BERR_c.BLIF \ -un10_ciin_7.BLIF pos_clk_size_dma_6_1__n.BLIF un10_ciin_8.BLIF G_107.BLIF \ -BG_030_c.BLIF un10_ciin_9.BLIF G_108.BLIF un10_ciin_10.BLIF G_109.BLIF \ -BG_000DFFreg.BLIF un10_ciin_11.BLIF N_171_i_1.BLIF N_78.BLIF N_171_i_2.BLIF \ -N_79.BLIF BGACK_000_c.BLIF N_227_1.BLIF N_260.BLIF N_227_2.BLIF N_139.BLIF \ -CLK_030_c.BLIF N_227_3.BLIF N_141.BLIF un21_fpu_cs_1.BLIF N_165.BLIF \ -un21_berr_1_0.BLIF N_169.BLIF N_235_i_1.BLIF N_297.BLIF CLK_OSZI_c.BLIF \ -N_235_i_2.BLIF N_256_1.BLIF N_300.BLIF N_256_2.BLIF N_302.BLIF \ -CLK_OUT_INTreg.BLIF N_232_i_1.BLIF N_113.BLIF N_232_i_2.BLIF N_305.BLIF \ -N_219_1.BLIF N_155.BLIF FPU_SENSE_c.BLIF N_219_2.BLIF N_163.BLIF N_218_1.BLIF \ -N_166.BLIF IPL_030DFF_0_reg.BLIF N_218_2.BLIF N_171.BLIF N_347_1.BLIF \ -N_180.BLIF IPL_030DFF_1_reg.BLIF N_347_2.BLIF N_184.BLIF N_136_i_1.BLIF \ -N_191.BLIF IPL_030DFF_2_reg.BLIF N_146_i_1.BLIF N_199.BLIF N_142_i_1.BLIF \ -N_205.BLIF ipl_c_0__n.BLIF N_234_i_1.BLIF N_306.BLIF N_302_0_1.BLIF N_215.BLIF \ -ipl_c_1__n.BLIF N_63_i_1.BLIF N_221.BLIF N_154_i_1.BLIF N_227.BLIF \ -ipl_c_2__n.BLIF N_152_i_1.BLIF N_230.BLIF N_148_i_1.BLIF N_319.BLIF \ -N_144_i_1.BLIF N_320.BLIF DTACK_c.BLIF N_140_i_1.BLIF N_267.BLIF \ -pos_clk_un6_bg_030_1_n.BLIF N_324.BLIF N_230_1.BLIF N_269.BLIF N_221_1.BLIF \ -N_270.BLIF VPA_c.BLIF N_215_1.BLIF N_327.BLIF N_306_1.BLIF N_273.BLIF \ -pos_clk_ipl_1_n.BLIF N_275.BLIF RST_c.BLIF ipl_030_0_2__un3_n.BLIF N_290.BLIF \ -ipl_030_0_2__un1_n.BLIF N_292.BLIF ipl_030_0_2__un0_n.BLIF N_295.BLIF \ -RW_c.BLIF ipl_030_0_1__un3_n.BLIF N_332.BLIF ipl_030_0_1__un1_n.BLIF \ -N_333.BLIF fc_c_0__n.BLIF ipl_030_0_1__un0_n.BLIF N_334.BLIF \ -ipl_030_0_0__un3_n.BLIF N_335.BLIF fc_c_1__n.BLIF ipl_030_0_0__un1_n.BLIF \ -N_336.BLIF ipl_030_0_0__un0_n.BLIF N_338.BLIF cpu_est_0_3__un3_n.BLIF \ -N_339.BLIF AMIGA_BUS_DATA_DIR_c.BLIF cpu_est_0_3__un1_n.BLIF N_350.BLIF \ -cpu_est_0_3__un0_n.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.BLIF vma_int_0_un3_n.BLIF \ -N_161.BLIF vma_int_0_un1_n.BLIF N_213.BLIF vma_int_0_un0_n.BLIF N_214.BLIF \ -VPA_c_i.BLIF cpu_est_0_1__un3_n.BLIF N_197.BLIF N_52_0.BLIF \ -cpu_est_0_1__un1_n.BLIF N_159.BLIF DTACK_c_i.BLIF cpu_est_0_1__un0_n.BLIF \ -N_326.BLIF N_53_0.BLIF cpu_est_0_2__un3_n.BLIF un21_berr_1.BLIF \ -ipl_c_i_0__n.BLIF cpu_est_0_2__un1_n.BLIF N_181.BLIF N_49_0.BLIF \ -cpu_est_0_2__un0_n.BLIF pos_clk_un21_bgack_030_int_i_i_a2_i_x2.BLIF \ -ipl_c_i_1__n.BLIF ds_000_dma_0_un3_n.BLIF un1_DS_000_ENABLE_0_sqmuxa.BLIF \ -N_50_0.BLIF ds_000_dma_0_un1_n.BLIF N_349.BLIF ipl_c_i_2__n.BLIF \ -ds_000_dma_0_un0_n.BLIF N_345.BLIF N_51_0.BLIF as_000_dma_0_un3_n.BLIF \ -N_229.BLIF N_25_i.BLIF as_000_dma_0_un1_n.BLIF N_14.BLIF N_28_0.BLIF \ -as_000_dma_0_un0_n.BLIF N_21.BLIF N_26_i.BLIF bgack_030_int_0_un3_n.BLIF \ -N_3.BLIF N_29_0.BLIF bgack_030_int_0_un1_n.BLIF N_301.BLIF N_27_i.BLIF \ -bgack_030_int_0_un0_n.BLIF N_4.BLIF N_30_0.BLIF ds_000_enable_0_un3_n.BLIF \ -N_303.BLIF N_222_i.BLIF ds_000_enable_0_un1_n.BLIF N_8.BLIF N_223_i.BLIF \ -ds_000_enable_0_un0_n.BLIF pos_clk_un6_bgack_000_n.BLIF N_192_i.BLIF \ -uds_000_int_0_un3_n.BLIF N_9.BLIF N_231_i.BLIF uds_000_int_0_un1_n.BLIF \ -N_65.BLIF N_237_i.BLIF uds_000_int_0_un0_n.BLIF N_217.BLIF \ -lds_000_int_0_un3_n.BLIF N_216.BLIF N_342_i.BLIF lds_000_int_0_un1_n.BLIF \ -N_248.BLIF N_341_i.BLIF lds_000_int_0_un0_n.BLIF N_198.BLIF \ -un1_amiga_bus_enable_dma_high_i_m2_0__un3_n.BLIF N_291.BLIF N_160_0.BLIF \ -un1_amiga_bus_enable_dma_high_i_m2_0__un1_n.BLIF N_353.BLIF N_164_i.BLIF \ -un1_amiga_bus_enable_dma_high_i_m2_0__un0_n.BLIF N_256.BLIF VMA_INT_i.BLIF \ -amiga_bus_enable_dma_high_0_un3_n.BLIF N_18.BLIF N_347_i.BLIF \ -amiga_bus_enable_dma_high_0_un1_n.BLIF pos_clk_un9_clk_000_pe_n.BLIF \ -N_348_i.BLIF amiga_bus_enable_dma_high_0_un0_n.BLIF cpu_est_2_1__n.BLIF \ -N_188_i.BLIF bg_000_0_un3_n.BLIF cpu_est_2_2__n.BLIF N_245_0.BLIF \ -bg_000_0_un1_n.BLIF N_209.BLIF N_194_0.BLIF bg_000_0_un0_n.BLIF N_211.BLIF \ -N_196_0.BLIF size_dma_0_0__un3_n.BLIF N_220.BLIF size_dma_0_0__un1_n.BLIF \ -N_222.BLIF N_211_i.BLIF size_dma_0_0__un0_n.BLIF N_162.BLIF N_209_i.BLIF \ -size_dma_0_1__un3_n.BLIF N_224.BLIF N_306_i.BLIF size_dma_0_1__un1_n.BLIF \ -N_193.BLIF N_193_0.BLIF size_dma_0_1__un0_n.BLIF N_225.BLIF N_190_0.BLIF \ -as_030_000_sync_0_un3_n.BLIF N_190.BLIF N_183_i.BLIF \ -as_030_000_sync_0_un1_n.BLIF N_346.BLIF N_162_i.BLIF \ -as_030_000_sync_0_un0_n.BLIF N_352.BLIF N_346_i.BLIF rw_000_int_0_un3_n.BLIF \ -N_219.BLIF N_159_0.BLIF rw_000_int_0_un1_n.BLIF N_218.BLIF N_305_i.BLIF \ -rw_000_int_0_un0_n.BLIF N_183.BLIF N_210_i.BLIF rw_000_dma_0_un3_n.BLIF \ -N_196.BLIF N_225_i.BLIF rw_000_dma_0_un1_n.BLIF N_188.BLIF N_224_i.BLIF \ -rw_000_dma_0_un0_n.BLIF N_194.BLIF N_296_i.BLIF a0_dma_0_un3_n.BLIF N_347.BLIF \ -N_352_i.BLIF a0_dma_0_un1_n.BLIF N_348.BLIF cpu_est_2_0_2__n.BLIF \ -a0_dma_0_un0_n.BLIF N_160.BLIF N_220_i.BLIF \ -amiga_bus_enable_dma_low_0_un3_n.BLIF N_341.BLIF N_221_i.BLIF \ -amiga_bus_enable_dma_low_0_un1_n.BLIF N_342.BLIF cpu_est_2_0_1__n.BLIF \ -amiga_bus_enable_dma_low_0_un0_n.BLIF N_231.BLIF N_219_i.BLIF \ -a_decode_15__n.BLIF N_237.BLIF N_218_i.BLIF N_223.BLIF \ -pos_clk_un9_clk_000_pe_0_n.BLIF a_decode_14__n.BLIF N_27.BLIF \ -clk_000_d_i_2__n.BLIF N_26.BLIF N_157_i.BLIF a_decode_13__n.BLIF N_25.BLIF \ -N_18_i.BLIF un1_amiga_bus_enable_low_i.BLIF N_37_0.BLIF a_decode_12__n.BLIF \ -un21_fpu_cs_i.BLIF cpu_est_i_2__n.BLIF N_217_i.BLIF a_decode_11__n.BLIF \ -sm_amiga_i_0__n.BLIF N_216_i.BLIF sm_amiga_i_2__n.BLIF CLK_030_c_i.BLIF \ -a_decode_10__n.BLIF sm_amiga_i_1__n.BLIF N_198_0.BLIF cpu_est_i_0__n.BLIF \ -N_166_i.BLIF a_decode_9__n.BLIF VPA_D_i.BLIF N_155_i.BLIF DTACK_D0_i.BLIF \ -N_303_0.BLIF a_decode_8__n.BLIF AS_030_i.BLIF N_291_i.BLIF DSACK1_INT_i.BLIF \ -N_301_0.BLIF a_decode_7__n.BLIF cpu_est_i_3__n.BLIF N_256_i.BLIF \ -sm_amiga_i_3__n.BLIF N_248_i.BLIF a_decode_6__n.BLIF cpu_est_i_1__n.BLIF \ -AMIGA_BUS_DATA_DIR_c_0.BLIF clk_000_d_i_1__n.BLIF N_353_i.BLIF \ -a_decode_5__n.BLIF N_350_i_0.BLIF pos_clk_un6_bgack_000_0_n.BLIF \ -rst_dly_i_2__n.BLIF N_65_0.BLIF a_decode_4__n.BLIF nEXP_SPACE_i.BLIF \ -N_3_i.BLIF AS_000_i.BLIF N_45_0.BLIF a_decode_3__n.BLIF BGACK_030_INT_i.BLIF \ -N_4_i.BLIF sm_amiga_i_6__n.BLIF N_44_0.BLIF a_decode_2__n.BLIF \ -clk_000_d_i_0__n.BLIF N_8_i.BLIF RW_000_i.BLIF N_42_0.BLIF CLK_030_H_i.BLIF \ -UDS_000_INT_i.BLIF AS_000_DMA_i.BLIF un1_UDS_000_INT_0.BLIF \ -cycle_dma_i_0__n.BLIF LDS_000_INT_i.BLIF DS_000_DMA_i.BLIF \ -un1_LDS_000_INT_0.BLIF RESET_OUT_i.BLIF N_21_i.BLIF sm_amiga_i_4__n.BLIF \ -N_34_0.BLIF FPU_SENSE_i.BLIF N_14_i.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF \ -RW_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF \ -SIZE_1_.PIN.BLIF AHIGH_24_.PIN.BLIF AHIGH_25_.PIN.BLIF AHIGH_26_.PIN.BLIF \ -AHIGH_27_.PIN.BLIF AHIGH_28_.PIN.BLIF AHIGH_29_.PIN.BLIF AHIGH_30_.PIN.BLIF \ -AHIGH_31_.PIN.BLIF A_0_.PIN.BLIF BERR.PIN.BLIF RW.PIN.BLIF +AHIGH_25_.BLIF AHIGH_24_.BLIF A_0_.BLIF ipl_i_2__n.BLIF N_233_0.BLIF \ +ipl_i_1__n.BLIF N_360_i.BLIF ipl_i_0__n.BLIF N_191_i_i.BLIF a_i_1__n.BLIF \ +N_192_i_i.BLIF AS_000_DMA_i.BLIF AS_000_i.BLIF N_199_i.BLIF CLK_030_H_i.BLIF \ +N_204_i.BLIF AS_030_000_SYNC_i.BLIF inst_BGACK_030_INTreg.BLIF \ +AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF N_282_i.BLIF vcc_n_n.BLIF \ +cycle_dma_i_0__n.BLIF N_278_i.BLIF inst_VMA_INTreg.BLIF ahigh_i_30__n.BLIF \ +N_186_i.BLIF gnd_n_n.BLIF ahigh_i_31__n.BLIF N_185_i.BLIF \ +un1_amiga_bus_enable_low.BLIF ahigh_i_28__n.BLIF CLK_030_c_i.BLIF \ +un7_as_030.BLIF ahigh_i_29__n.BLIF N_184_0.BLIF un1_LDS_000_INT.BLIF \ +ahigh_i_26__n.BLIF N_179_0.BLIF un1_UDS_000_INT.BLIF ahigh_i_27__n.BLIF \ +N_251_i.BLIF un10_ciin.BLIF ahigh_i_24__n.BLIF LDS_000_c_i.BLIF \ +un21_fpu_cs.BLIF ahigh_i_25__n.BLIF UDS_000_c_i.BLIF un21_berr.BLIF \ +N_172_i.BLIF un6_ds_030.BLIF pos_clk_un21_bgack_030_int_i_0_0_n.BLIF \ +cpu_est_2_.BLIF N_163_i.BLIF cpu_est_3_.BLIF clk_000_d_i_3__n.BLIF \ +cpu_est_0_.BLIF N_115_i.BLIF N_350_i.BLIF cpu_est_1_.BLIF N_114_i.BLIF \ +un1_rw_i.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF un6_ds_030_i.BLIF \ +N_126_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF DS_000_DMA_i.BLIF N_313_i.BLIF \ +inst_AS_030_D0.BLIF N_132_i.BLIF N_231_i.BLIF inst_AS_030_000_SYNC.BLIF \ +N_133_i.BLIF N_291_i.BLIF inst_BGACK_030_INT_D.BLIF un7_as_030_i.BLIF \ +inst_AS_000_DMA.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF N_288_i.BLIF \ +inst_DS_000_DMA.BLIF AS_030_c.BLIF CYCLE_DMA_0_.BLIF N_287_i.BLIF \ +CYCLE_DMA_1_.BLIF AS_000_c.BLIF N_340_i.BLIF inst_VPA_D.BLIF CLK_000_D_3_.BLIF \ +RW_000_c.BLIF N_284_i.BLIF inst_DTACK_D0.BLIF inst_RESET_OUT.BLIF N_275_i.BLIF \ +CLK_000_D_1_.BLIF UDS_000_c.BLIF pos_clk_size_dma_6_0_1__n.BLIF \ +CLK_000_D_0_.BLIF N_268_i.BLIF inst_CLK_OUT_PRE_50.BLIF LDS_000_c.BLIF \ +pos_clk_size_dma_6_0_0__n.BLIF inst_CLK_OUT_PRE_D.BLIF N_265_i.BLIF \ +IPL_D0_0_.BLIF size_c_0__n.BLIF N_267_i.BLIF IPL_D0_1_.BLIF IPL_D0_2_.BLIF \ +size_c_1__n.BLIF N_337_i.BLIF CLK_000_D_2_.BLIF N_338_i.BLIF CLK_000_D_4_.BLIF \ +ahigh_c_24__n.BLIF N_55_0.BLIF inst_LDS_000_INT.BLIF un1_as_000_i.BLIF \ +inst_DS_000_ENABLE.BLIF ahigh_c_25__n.BLIF N_245_0.BLIF inst_UDS_000_INT.BLIF \ +N_229_i.BLIF pos_clk_un9_bg_030_n.BLIF ahigh_c_26__n.BLIF SM_AMIGA_6_.BLIF \ +N_227_i.BLIF SM_AMIGA_4_.BLIF ahigh_c_27__n.BLIF SM_AMIGA_1_.BLIF N_226_i.BLIF \ +SM_AMIGA_0_.BLIF ahigh_c_28__n.BLIF N_246_0.BLIF SIZE_DMA_0_.BLIF N_332_i.BLIF \ +SIZE_DMA_1_.BLIF ahigh_c_29__n.BLIF pos_clk_ds_000_dma_4_0_n.BLIF \ +inst_RW_000_INT.BLIF N_48_0.BLIF inst_RW_000_DMA.BLIF ahigh_c_30__n.BLIF \ +pos_clk_rw_000_dma_3_0_n.BLIF RST_DLY_0_.BLIF N_218_i.BLIF RST_DLY_1_.BLIF \ +ahigh_c_31__n.BLIF RST_DLY_2_.BLIF inst_A0_DMA.BLIF un10_ciin_i.BLIF \ +pos_clk_a0_dma_3_n.BLIF N_62_0.BLIF pos_clk_rw_000_dma_3_n.BLIF N_215_i.BLIF \ +inst_CLK_030_H.BLIF N_216_i.BLIF inst_DSACK1_INT.BLIF \ +un10_amiga_bus_enable_high_i.BLIF inst_AS_000_INT.BLIF N_214_i.BLIF \ +SM_AMIGA_5_.BLIF N_310_0.BLIF SM_AMIGA_3_.BLIF N_24_i.BLIF SM_AMIGA_2_.BLIF \ +N_33_0.BLIF pos_clk_ds_000_dma_4_n.BLIF N_23_i.BLIF N_3.BLIF N_32_0.BLIF \ +N_4.BLIF N_22_i.BLIF N_31_0.BLIF N_3_i.BLIF N_45_0.BLIF N_4_i.BLIF N_44_0.BLIF \ +N_15.BLIF N_15_i.BLIF N_19.BLIF N_40_0.BLIF N_20.BLIF N_19_i.BLIF N_22.BLIF \ +N_36_0.BLIF N_23.BLIF N_20_i.BLIF N_24.BLIF N_35_0.BLIF N_25.BLIF N_25_i.BLIF \ +N_26.BLIF N_30_0.BLIF N_27.BLIF N_26_i.BLIF N_29_0.BLIF N_27_i.BLIF \ +a_decode_c_16__n.BLIF N_28_0.BLIF BG_030_c_i.BLIF a_decode_c_17__n.BLIF \ +pos_clk_un9_bg_030_0_n.BLIF N_235_i_1.BLIF a_decode_c_18__n.BLIF \ +N_235_i_2.BLIF N_156_i_1.BLIF a_decode_c_19__n.BLIF N_156_i_2.BLIF \ +N_156_i_3.BLIF a_decode_c_20__n.BLIF N_156_i_4.BLIF \ +pos_clk_un10_sm_amiga_i_1_n.BLIF a_decode_c_21__n.BLIF N_176_i_1.BLIF \ +un10_ciin_1.BLIF a_decode_c_22__n.BLIF un10_ciin_2.BLIF un10_ciin_3.BLIF \ +a_decode_c_23__n.BLIF un10_ciin_4.BLIF un10_ciin_5.BLIF a_c_0__n.BLIF \ +un10_ciin_6.BLIF un10_ciin_7.BLIF a_c_1__n.BLIF un10_ciin_8.BLIF \ +SM_AMIGA_i_7_.BLIF un10_ciin_9.BLIF pos_clk_size_dma_6_0__n.BLIF \ +nEXP_SPACE_c.BLIF un10_ciin_10.BLIF pos_clk_size_dma_6_1__n.BLIF \ +un10_ciin_11.BLIF N_199.BLIF BERR_c.BLIF N_163_i_1.BLIF \ +pos_clk_un21_bgack_030_int_i_0_n.BLIF N_163_i_2.BLIF N_231.BLIF BG_030_c.BLIF \ +pos_clk_un21_bgack_030_int_i_0_0_1_n.BLIF N_233.BLIF \ +pos_clk_un21_bgack_030_int_i_0_0_2_n.BLIF N_111.BLIF BG_000DFFreg.BLIF \ +N_138_i_1.BLIF N_112.BLIF N_138_i_2.BLIF N_113.BLIF N_59_i_1.BLIF N_114.BLIF \ +BGACK_000_c.BLIF N_59_i_2.BLIF N_115.BLIF N_233_0_1.BLIF N_245.BLIF \ +CLK_030_c.BLIF N_233_0_2.BLIF N_246.BLIF N_214_1.BLIF N_62.BLIF N_214_2.BLIF \ +N_214_3.BLIF N_132.BLIF CLK_OSZI_c.BLIF un21_fpu_cs_1.BLIF N_133.BLIF \ +un21_berr_1_0.BLIF N_310.BLIF N_182_0_1.BLIF N_126.BLIF CLK_OUT_INTreg.BLIF \ +N_234_i_1.BLIF N_149.BLIF N_234_i_2.BLIF N_150.BLIF N_206_1.BLIF N_158.BLIF \ +FPU_SENSE_c.BLIF N_206_2.BLIF N_160.BLIF N_205_1.BLIF N_163.BLIF \ +IPL_030DFF_0_reg.BLIF N_205_2.BLIF N_172.BLIF N_352_1.BLIF N_179.BLIF \ +IPL_030DFF_1_reg.BLIF N_352_2.BLIF N_184.BLIF N_231_i_1.BLIF N_185.BLIF \ +IPL_030DFF_2_reg.BLIF N_152_i_1.BLIF N_196.BLIF N_144_i_1.BLIF N_203.BLIF \ +ipl_c_0__n.BLIF N_142_i_1.BLIF N_204.BLIF N_312_i_1.BLIF N_209.BLIF \ +ipl_c_1__n.BLIF N_236_i_1.BLIF N_214.BLIF N_148_i_1.BLIF N_215.BLIF \ +ipl_c_2__n.BLIF N_136_i_1.BLIF N_216.BLIF N_246_0_1.BLIF N_218.BLIF \ +N_249_i_1.BLIF N_224.BLIF DTACK_c.BLIF N_57_i_1.BLIF N_332.BLIF N_338_1.BLIF \ +N_226.BLIF N_224_1.BLIF N_227.BLIF N_216_1.BLIF N_229.BLIF VPA_c.BLIF \ +N_209_1.BLIF N_337.BLIF N_203_1.BLIF N_338.BLIF N_196_1.BLIF N_265.BLIF \ +RST_c.BLIF cpu_est_0_3__un3_n.BLIF N_267.BLIF cpu_est_0_3__un1_n.BLIF \ +N_268.BLIF cpu_est_0_3__un0_n.BLIF N_275.BLIF RW_c.BLIF \ +rw_000_int_0_un3_n.BLIF N_278.BLIF rw_000_int_0_un1_n.BLIF N_282.BLIF \ +fc_c_0__n.BLIF rw_000_int_0_un0_n.BLIF N_284.BLIF vma_int_0_un3_n.BLIF \ +N_340.BLIF fc_c_1__n.BLIF vma_int_0_un1_n.BLIF N_287.BLIF vma_int_0_un0_n.BLIF \ +N_288.BLIF cpu_est_0_1__un3_n.BLIF N_291.BLIF AMIGA_BUS_DATA_DIR_c.BLIF \ +cpu_est_0_1__un1_n.BLIF N_293.BLIF cpu_est_0_1__un0_n.BLIF N_350.BLIF \ +cpu_est_0_2__un3_n.BLIF N_355.BLIF cpu_est_0_2__un1_n.BLIF \ +pos_clk_un21_bgack_030_int_i_0_o3_0_x2.BLIF cpu_est_0_2__un0_n.BLIF \ +pos_clk_un1_ipl_i_0_x2.BLIF N_16_i.BLIF uds_000_int_0_un3_n.BLIF \ +pos_clk_un1_ipl_i_0_x2_0.BLIF N_39_0.BLIF uds_000_int_0_un1_n.BLIF \ +pos_clk_un1_ipl_i_0_x2_1.BLIF VPA_c_i.BLIF uds_000_int_0_un0_n.BLIF \ +pos_clk_CYCLE_DMA_5_1_i_0_x2.BLIF N_52_0.BLIF lds_000_int_0_un3_n.BLIF \ +N_156.BLIF DTACK_c_i.BLIF lds_000_int_0_un1_n.BLIF N_201.BLIF N_53_0.BLIF \ +lds_000_int_0_un0_n.BLIF N_202.BLIF N_210_i.BLIF bgack_030_int_0_un3_n.BLIF \ +N_154.BLIF N_211_i.BLIF bgack_030_int_0_un1_n.BLIF un21_berr_1.BLIF \ +N_189_i.BLIF bgack_030_int_0_un0_n.BLIF N_174.BLIF \ +un1_SM_AMIGA_0_sqmuxa_1_0.BLIF ds_000_enable_0_un3_n.BLIF N_223.BLIF \ +RW_c_i.BLIF ds_000_enable_0_un1_n.BLIF N_221.BLIF N_311_0.BLIF \ +ds_000_enable_0_un0_n.BLIF N_222.BLIF N_336_i.BLIF size_dma_0_0__un3_n.BLIF \ +N_219.BLIF N_244_i.BLIF size_dma_0_0__un1_n.BLIF N_220.BLIF \ +size_dma_0_0__un0_n.BLIF pos_clk_un6_bgack_000_n.BLIF N_314_0.BLIF \ +size_dma_0_1__un3_n.BLIF N_359.BLIF N_159_i.BLIF size_dma_0_1__un1_n.BLIF \ +N_8.BLIF VMA_INT_i.BLIF size_dma_0_1__un0_n.BLIF N_14.BLIF N_352_i.BLIF \ +ipl_030_0_0__un3_n.BLIF N_21.BLIF N_353_i.BLIF ipl_030_0_0__un1_n.BLIF \ +N_9.BLIF N_293_i.BLIF ipl_030_0_0__un0_n.BLIF un1_DS_000_ENABLE_0_sqmuxa.BLIF \ +N_175_i.BLIF ipl_030_0_1__un3_n.BLIF N_66.BLIF N_176_i.BLIF \ +ipl_030_0_1__un1_n.BLIF N_171.BLIF ipl_030_0_1__un0_n.BLIF N_354.BLIF \ +N_198_i.BLIF ipl_030_0_2__un3_n.BLIF N_18.BLIF N_197_i.BLIF \ +ipl_030_0_2__un1_n.BLIF pos_clk_un9_clk_000_pe_n.BLIF N_196_i.BLIF \ +ipl_030_0_2__un0_n.BLIF cpu_est_2_1__n.BLIF N_183_0.BLIF a0_dma_0_un3_n.BLIF \ +cpu_est_2_2__n.BLIF N_182_0.BLIF a0_dma_0_un1_n.BLIF N_197.BLIF N_180_0.BLIF \ +a0_dma_0_un0_n.BLIF N_198.BLIF N_178_0.BLIF \ +amiga_bus_enable_dma_low_0_un3_n.BLIF N_208.BLIF N_82_i.BLIF \ +amiga_bus_enable_dma_low_0_un1_n.BLIF N_210.BLIF N_315_i.BLIF \ +amiga_bus_enable_dma_low_0_un0_n.BLIF N_315.BLIF N_351_i.BLIF \ +amiga_bus_enable_dma_high_0_un3_n.BLIF N_212.BLIF N_154_0.BLIF \ +amiga_bus_enable_dma_high_0_un1_n.BLIF N_180.BLIF N_149_i.BLIF \ +amiga_bus_enable_dma_high_0_un0_n.BLIF N_213.BLIF N_207_i.BLIF \ +bg_000_0_un3_n.BLIF N_178.BLIF N_228_i.BLIF bg_000_0_un1_n.BLIF N_228.BLIF \ +bg_000_0_un0_n.BLIF N_182.BLIF N_213_i.BLIF ds_000_dma_0_un3_n.BLIF N_176.BLIF \ +N_212_i.BLIF ds_000_dma_0_un1_n.BLIF N_183.BLIF N_309_i.BLIF \ +ds_000_dma_0_un0_n.BLIF N_351.BLIF N_357_i.BLIF as_000_dma_0_un3_n.BLIF \ +N_357.BLIF cpu_est_2_0_2__n.BLIF as_000_dma_0_un1_n.BLIF N_206.BLIF \ +N_208_i.BLIF as_000_dma_0_un0_n.BLIF N_205.BLIF N_209_i.BLIF \ +as_030_000_sync_0_un3_n.BLIF N_352.BLIF cpu_est_2_0_1__n.BLIF \ +as_030_000_sync_0_un1_n.BLIF N_353.BLIF N_206_i.BLIF \ +as_030_000_sync_0_un0_n.BLIF N_314.BLIF N_205_i.BLIF rw_000_dma_0_un3_n.BLIF \ +N_244.BLIF pos_clk_un9_clk_000_pe_0_n.BLIF rw_000_dma_0_un1_n.BLIF N_336.BLIF \ +N_18_i.BLIF rw_000_dma_0_un0_n.BLIF N_311.BLIF N_37_0.BLIF a_decode_15__n.BLIF \ +un1_SM_AMIGA_0_sqmuxa_1.BLIF N_171_i.BLIF N_211.BLIF N_354_i.BLIF \ +a_decode_14__n.BLIF N_16.BLIF un1_DS_000_ENABLE_0_sqmuxa_0.BLIF \ +un1_amiga_bus_enable_low_i.BLIF N_66_0.BLIF a_decode_13__n.BLIF \ +un21_fpu_cs_i.BLIF UDS_000_INT_i.BLIF cpu_est_i_2__n.BLIF \ +un1_UDS_000_INT_0.BLIF a_decode_12__n.BLIF cpu_est_i_0__n.BLIF \ +LDS_000_INT_i.BLIF VPA_D_i.BLIF un1_LDS_000_INT_0.BLIF a_decode_11__n.BLIF \ +DTACK_D0_i.BLIF N_21_i.BLIF cpu_est_i_3__n.BLIF N_34_0.BLIF \ +a_decode_10__n.BLIF sm_amiga_i_i_7__n.BLIF N_14_i.BLIF sm_amiga_i_5__n.BLIF \ +N_41_0.BLIF a_decode_9__n.BLIF sm_amiga_i_3__n.BLIF N_8_i.BLIF \ +cpu_est_i_1__n.BLIF N_42_0.BLIF a_decode_8__n.BLIF clk_000_d_i_1__n.BLIF \ +a_c_i_0__n.BLIF N_355_i_0.BLIF size_c_i_1__n.BLIF a_decode_7__n.BLIF \ +sm_amiga_i_4__n.BLIF pos_clk_un10_sm_amiga_i_n.BLIF sm_amiga_i_2__n.BLIF \ +N_359_i.BLIF a_decode_6__n.BLIF rst_dly_i_0__n.BLIF \ +pos_clk_un6_bgack_000_0_n.BLIF rst_dly_i_2__n.BLIF N_220_i.BLIF \ +a_decode_5__n.BLIF a_decode_i_19__n.BLIF N_219_i.BLIF a_decode_i_18__n.BLIF \ +a_decode_4__n.BLIF a_decode_i_16__n.BLIF N_222_i.BLIF RW_000_i.BLIF \ +N_221_i.BLIF a_decode_3__n.BLIF sm_amiga_i_0__n.BLIF AS_030_i.BLIF \ +N_223_i.BLIF a_decode_2__n.BLIF AS_000_INT_i.BLIF N_224_i.BLIF \ +DSACK1_INT_i.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF clk_000_d_i_0__n.BLIF \ +N_150_i.BLIF sm_amiga_i_6__n.BLIF N_156_i.BLIF sm_amiga_i_1__n.BLIF \ +N_160_i.BLIF FPU_SENSE_i.BLIF N_174_i.BLIF rst_dly_i_1__n.BLIF N_158_i.BLIF \ +AS_030_D0_i.BLIF N_201_i.BLIF BGACK_030_INT_i.BLIF N_202_i.BLIF \ +nEXP_SPACE_i.BLIF N_203_i.BLIF RESET_OUT_i.BLIF AS_030.PIN.BLIF \ +AS_000.PIN.BLIF RW_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF \ +SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF AHIGH_24_.PIN.BLIF AHIGH_25_.PIN.BLIF \ +AHIGH_26_.PIN.BLIF AHIGH_27_.PIN.BLIF AHIGH_28_.PIN.BLIF AHIGH_29_.PIN.BLIF \ +AHIGH_30_.PIN.BLIF AHIGH_31_.PIN.BLIF A_0_.PIN.BLIF BERR.PIN.BLIF RW.PIN.BLIF .outputs IPL_030_2_ DS_030 BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 \ AVEC E VMA RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ -AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_i_7_.D \ +AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ IPL_D0_0_.D IPL_D0_0_.C \ +IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C SM_AMIGA_i_7_.D \ SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_5_.D SM_AMIGA_5_.C \ SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_2_.D \ SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C \ +cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C \ cpu_est_3_.D cpu_est_3_.C IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C \ IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D IPL_030DFF_2_reg.C \ -IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C \ -CLK_000_D_0_.D CLK_000_D_0_.C CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_2_.D \ -CLK_000_D_2_.C CLK_000_D_3_.D CLK_000_D_3_.C CLK_000_D_4_.D CLK_000_D_4_.C \ -CLK_000_D_5_.D CLK_000_D_5_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D \ +RST_DLY_2_.D RST_DLY_2_.C CLK_000_D_0_.D CLK_000_D_0_.C CLK_000_D_1_.D \ +CLK_000_D_1_.C CLK_000_D_2_.D CLK_000_D_2_.C CLK_000_D_3_.D CLK_000_D_3_.C \ +CLK_000_D_4_.D CLK_000_D_4_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D \ CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C \ -cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C \ -RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C \ -inst_DS_000_DMA.D inst_DS_000_DMA.C inst_DSACK1_INT.D inst_DSACK1_INT.C \ -inst_AS_000_INT.D inst_AS_000_INT.C inst_AS_030_D0.D inst_AS_030_D0.C \ -inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D inst_DTACK_D0.C inst_CLK_030_H.D \ -inst_CLK_030_H.C inst_RESET_OUT.D inst_RESET_OUT.C inst_DS_000_ENABLE.D \ -inst_DS_000_ENABLE.C BG_000DFFreg.D BG_000DFFreg.C \ -inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.C \ -inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AMIGA_BUS_ENABLE_DMA_LOW.C \ -inst_UDS_000_INT.D inst_UDS_000_INT.C inst_A0_DMA.D inst_A0_DMA.C \ -inst_RW_000_DMA.D inst_RW_000_DMA.C inst_VMA_INTreg.D inst_VMA_INTreg.C \ -inst_RW_000_INT.D inst_RW_000_INT.C inst_AS_030_000_SYNC.D \ -inst_AS_030_000_SYNC.C inst_LDS_000_INT.D inst_LDS_000_INT.C \ -inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_AS_000_DMA.D \ -inst_AS_000_DMA.C inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C \ -CLK_OUT_INTreg.D CLK_OUT_INTreg.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C \ -inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C SIZE_1_ AHIGH_31_ AS_030 AS_000 \ -RW_000 UDS_000 LDS_000 BERR RW SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ \ -AHIGH_26_ AHIGH_25_ AHIGH_24_ A_0_ rst_dly_i_1__n N_41_0 sm_amiga_i_5__n \ -a_c_i_0__n rst_dly_i_0__n size_c_i_1__n sm_amiga_i_i_7__n \ -pos_clk_un10_sm_amiga_i_n AS_030_D0_i un1_as_000_i AS_000_INT_i un10_ciin_i \ -a_i_1__n N_260_0 a_decode_i_16__n N_229_i a_decode_i_18__n N_230_i vcc_n_n \ -a_decode_i_19__n N_298_0 ahigh_i_30__n N_48_0 gnd_n_n ahigh_i_31__n N_299_i \ -un1_amiga_bus_enable_low ahigh_i_28__n N_345_i un7_as_030 ahigh_i_29__n \ -N_349_i un1_UDS_000_INT ahigh_i_26__n un1_DS_000_ENABLE_0_sqmuxa_i \ -un1_LDS_000_INT ahigh_i_27__n N_180_i un1_SM_AMIGA_0_sqmuxa_1 ahigh_i_24__n \ -N_181_i un10_ciin ahigh_i_25__n N_326_i un21_fpu_cs N_206_i un21_berr N_207_i \ -N_186_i un6_ds_030 N_208_i N_163_i N_197_0 N_79_i N_213_i N_78_i N_214_i \ -un6_ds_030_i N_215_i N_165_i N_169_i N_199_i un7_as_030_i N_191_0 \ -AMIGA_BUS_ENABLE_DMA_LOW_i N_275_i AS_030_c N_187_0 LDS_000_c_i AS_000_c \ -UDS_000_c_i N_184_i RW_000_c clk_000_d_i_4__n N_171_i AS_030_000_SYNC_i \ -UDS_000_c N_161_i LDS_000_c N_113_0 N_338_i size_c_0__n N_339_i size_c_1__n \ -N_335_i N_336_i ahigh_c_24__n N_334_i ahigh_c_25__n pos_clk_size_dma_6_0_1__n \ -pos_clk_un6_bg_030_n N_333_i ahigh_c_26__n pos_clk_size_dma_6_0_0__n \ -pos_clk_ipl_n N_295_i ahigh_c_27__n N_332_i ahigh_c_28__n N_292_i N_302_0 \ -pos_clk_un9_bg_030_n ahigh_c_29__n N_300_0 N_290_i ahigh_c_30__n N_273_i \ -ahigh_c_31__n N_327_i N_270_i N_269_i N_267_i pos_clk_a0_dma_3_n N_324_i \ -pos_clk_rw_000_int_5_n un1_SM_AMIGA_0_sqmuxa_1_0 N_319_i N_320_i RW_c_i \ -pos_clk_rw_000_int_5_0_n N_227_i N_297_0 N_15_i N_40_0 N_16_i N_15 N_39_0 N_16 \ -N_19_i N_19 N_36_0 N_20 N_20_i N_22 N_35_0 N_23 N_22_i N_24 N_33_0 N_23_i \ -N_32_0 a_decode_c_16__n N_24_i N_31_0 a_decode_c_17__n BG_030_c_i \ -pos_clk_un6_bg_030_i_n a_decode_c_18__n pos_clk_un9_bg_030_0_n N_161_i_1 \ -a_decode_c_19__n N_161_i_2 N_161_i_3 a_decode_c_20__n N_161_i_4 N_233_i_1 \ -a_decode_c_21__n N_233_i_2 N_180_i_1 a_decode_c_22__n N_180_i_2 \ -pos_clk_un10_sm_amiga_i_1_n a_decode_c_23__n N_196_0_1 N_188_i_1 a_c_0__n \ -un10_ciin_1 un10_ciin_2 a_c_1__n un10_ciin_3 un10_ciin_4 nEXP_SPACE_c \ -un10_ciin_5 un10_ciin_6 pos_clk_size_dma_6_0__n BERR_c un10_ciin_7 \ -pos_clk_size_dma_6_1__n un10_ciin_8 BG_030_c un10_ciin_9 un10_ciin_10 \ -un10_ciin_11 N_171_i_1 N_78 N_171_i_2 N_79 BGACK_000_c N_227_1 N_260 N_227_2 \ -N_139 CLK_030_c N_227_3 N_141 un21_fpu_cs_1 N_165 un21_berr_1_0 N_169 \ -N_235_i_1 N_297 CLK_OSZI_c N_235_i_2 N_256_1 N_300 N_256_2 N_302 N_232_i_1 \ -N_113 N_232_i_2 N_305 N_219_1 N_155 FPU_SENSE_c N_219_2 N_163 N_218_1 N_166 \ -N_218_2 N_171 N_347_1 N_180 N_347_2 N_184 N_136_i_1 N_191 N_146_i_1 N_199 \ -N_142_i_1 N_205 ipl_c_0__n N_234_i_1 N_306 N_302_0_1 N_215 ipl_c_1__n N_63_i_1 \ -N_221 N_154_i_1 N_227 ipl_c_2__n N_152_i_1 N_230 N_148_i_1 N_319 N_144_i_1 \ -N_320 DTACK_c N_140_i_1 N_267 pos_clk_un6_bg_030_1_n N_324 N_230_1 N_269 \ -N_221_1 N_270 VPA_c N_215_1 N_327 N_306_1 N_273 pos_clk_ipl_1_n N_275 RST_c \ -ipl_030_0_2__un3_n N_290 ipl_030_0_2__un1_n N_292 ipl_030_0_2__un0_n N_295 \ -RW_c ipl_030_0_1__un3_n N_332 ipl_030_0_1__un1_n N_333 fc_c_0__n \ -ipl_030_0_1__un0_n N_334 ipl_030_0_0__un3_n N_335 fc_c_1__n ipl_030_0_0__un1_n \ -N_336 ipl_030_0_0__un0_n N_338 cpu_est_0_3__un3_n N_339 AMIGA_BUS_DATA_DIR_c \ -cpu_est_0_3__un1_n N_350 cpu_est_0_3__un0_n vma_int_0_un3_n N_161 \ -vma_int_0_un1_n N_213 vma_int_0_un0_n N_214 VPA_c_i cpu_est_0_1__un3_n N_197 \ -N_52_0 cpu_est_0_1__un1_n N_159 DTACK_c_i cpu_est_0_1__un0_n N_326 N_53_0 \ -cpu_est_0_2__un3_n un21_berr_1 ipl_c_i_0__n cpu_est_0_2__un1_n N_181 N_49_0 \ -cpu_est_0_2__un0_n ipl_c_i_1__n ds_000_dma_0_un3_n un1_DS_000_ENABLE_0_sqmuxa \ -N_50_0 ds_000_dma_0_un1_n N_349 ipl_c_i_2__n ds_000_dma_0_un0_n N_345 N_51_0 \ -as_000_dma_0_un3_n N_229 N_25_i as_000_dma_0_un1_n N_14 N_28_0 \ -as_000_dma_0_un0_n N_21 N_26_i bgack_030_int_0_un3_n N_3 N_29_0 \ -bgack_030_int_0_un1_n N_301 N_27_i bgack_030_int_0_un0_n N_4 N_30_0 \ -ds_000_enable_0_un3_n N_303 N_222_i ds_000_enable_0_un1_n N_8 N_223_i \ -ds_000_enable_0_un0_n pos_clk_un6_bgack_000_n N_192_i uds_000_int_0_un3_n N_9 \ -N_231_i uds_000_int_0_un1_n N_65 N_237_i uds_000_int_0_un0_n N_217 \ -lds_000_int_0_un3_n N_216 N_342_i lds_000_int_0_un1_n N_248 N_341_i \ -lds_000_int_0_un0_n N_198 un1_amiga_bus_enable_dma_high_i_m2_0__un3_n N_291 \ -N_160_0 un1_amiga_bus_enable_dma_high_i_m2_0__un1_n N_353 N_164_i \ -un1_amiga_bus_enable_dma_high_i_m2_0__un0_n N_256 VMA_INT_i \ -amiga_bus_enable_dma_high_0_un3_n N_18 N_347_i \ -amiga_bus_enable_dma_high_0_un1_n pos_clk_un9_clk_000_pe_n N_348_i \ -amiga_bus_enable_dma_high_0_un0_n cpu_est_2_1__n N_188_i bg_000_0_un3_n \ -cpu_est_2_2__n N_245_0 bg_000_0_un1_n N_209 N_194_0 bg_000_0_un0_n N_211 \ -N_196_0 size_dma_0_0__un3_n N_220 size_dma_0_0__un1_n N_222 N_211_i \ -size_dma_0_0__un0_n N_162 N_209_i size_dma_0_1__un3_n N_224 N_306_i \ -size_dma_0_1__un1_n N_193 N_193_0 size_dma_0_1__un0_n N_225 N_190_0 \ -as_030_000_sync_0_un3_n N_190 N_183_i as_030_000_sync_0_un1_n N_346 N_162_i \ -as_030_000_sync_0_un0_n N_352 N_346_i rw_000_int_0_un3_n N_219 N_159_0 \ -rw_000_int_0_un1_n N_218 N_305_i rw_000_int_0_un0_n N_183 N_210_i \ -rw_000_dma_0_un3_n N_196 N_225_i rw_000_dma_0_un1_n N_188 N_224_i \ -rw_000_dma_0_un0_n N_194 N_296_i a0_dma_0_un3_n N_347 N_352_i a0_dma_0_un1_n \ -N_348 cpu_est_2_0_2__n a0_dma_0_un0_n N_160 N_220_i \ -amiga_bus_enable_dma_low_0_un3_n N_341 N_221_i \ -amiga_bus_enable_dma_low_0_un1_n N_342 cpu_est_2_0_1__n \ -amiga_bus_enable_dma_low_0_un0_n N_231 N_219_i a_decode_15__n N_237 N_218_i \ -N_223 pos_clk_un9_clk_000_pe_0_n a_decode_14__n N_27 clk_000_d_i_2__n N_26 \ -N_157_i a_decode_13__n N_25 N_18_i un1_amiga_bus_enable_low_i N_37_0 \ -a_decode_12__n un21_fpu_cs_i cpu_est_i_2__n N_217_i a_decode_11__n \ -sm_amiga_i_0__n N_216_i sm_amiga_i_2__n CLK_030_c_i a_decode_10__n \ -sm_amiga_i_1__n N_198_0 cpu_est_i_0__n N_166_i a_decode_9__n VPA_D_i N_155_i \ -DTACK_D0_i N_303_0 a_decode_8__n AS_030_i N_291_i DSACK1_INT_i N_301_0 \ -a_decode_7__n cpu_est_i_3__n N_256_i sm_amiga_i_3__n N_248_i a_decode_6__n \ -cpu_est_i_1__n AMIGA_BUS_DATA_DIR_c_0 clk_000_d_i_1__n N_353_i a_decode_5__n \ -N_350_i_0 pos_clk_un6_bgack_000_0_n rst_dly_i_2__n N_65_0 a_decode_4__n \ -nEXP_SPACE_i N_3_i AS_000_i N_45_0 a_decode_3__n BGACK_030_INT_i N_4_i \ -sm_amiga_i_6__n N_44_0 a_decode_2__n clk_000_d_i_0__n N_8_i RW_000_i N_42_0 \ -CLK_030_H_i UDS_000_INT_i AS_000_DMA_i un1_UDS_000_INT_0 cycle_dma_i_0__n \ -LDS_000_INT_i DS_000_DMA_i un1_LDS_000_INT_0 RESET_OUT_i N_21_i \ -sm_amiga_i_4__n N_34_0 FPU_SENSE_i N_14_i AS_030.OE AS_000.OE RW_000.OE \ -UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE \ -AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE \ -A_0_.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE G_107 G_108 G_109 \ -pos_clk_CYCLE_DMA_5_1_i_x2 pos_clk_un21_bgack_030_int_i_i_a2_i_x2 -.names N_154_i_1.BLIF RST_c.BLIF SM_AMIGA_i_7_.D -11 1 -.names N_152_i_1.BLIF RST_c.BLIF SM_AMIGA_6_.D -11 1 -.names N_186_i.BLIF N_326_i.BLIF SM_AMIGA_5_.D -11 1 -.names N_148_i_1.BLIF RST_c.BLIF SM_AMIGA_4_.D -11 1 -.names N_146_i_1.BLIF RST_c.BLIF SM_AMIGA_3_.D -11 1 -.names N_144_i_1.BLIF RST_c.BLIF SM_AMIGA_2_.D -11 1 -.names N_142_i_1.BLIF RST_c.BLIF SM_AMIGA_1_.D -11 1 -.names N_140_i_1.BLIF RST_c.BLIF SM_AMIGA_0_.D -11 1 -.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_.D -1- 1 --1 1 -.names N_28_0.BLIF IPL_030DFF_0_reg.D +RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C inst_RW_000_INT.D \ +inst_RW_000_INT.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \ +inst_LDS_000_INT.D inst_LDS_000_INT.C inst_BGACK_030_INTreg.D \ +inst_BGACK_030_INTreg.C inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D \ +inst_DS_000_DMA.C inst_DSACK1_INT.D inst_DSACK1_INT.C inst_AS_000_INT.D \ +inst_AS_000_INT.C inst_AS_030_D0.D inst_AS_030_D0.C inst_VPA_D.D inst_VPA_D.C \ +inst_DTACK_D0.D inst_DTACK_D0.C inst_CLK_030_H.D inst_CLK_030_H.C \ +inst_RESET_OUT.D inst_RESET_OUT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C \ +BG_000DFFreg.D BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D \ +inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D \ +inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_UDS_000_INT.D inst_UDS_000_INT.C \ +inst_A0_DMA.D inst_A0_DMA.C inst_RW_000_DMA.D inst_RW_000_DMA.C \ +inst_VMA_INTreg.D inst_VMA_INTreg.C inst_BGACK_030_INT_D.D \ +inst_BGACK_030_INT_D.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C inst_CLK_OUT_PRE_50.D \ +inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C SIZE_1_ \ +AHIGH_31_ AS_030 AS_000 RW_000 UDS_000 LDS_000 BERR RW SIZE_0_ AHIGH_30_ \ +AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ A_0_ ipl_i_2__n \ +N_233_0 ipl_i_1__n N_360_i ipl_i_0__n N_191_i_i a_i_1__n N_192_i_i \ +AS_000_DMA_i AS_000_i N_199_i CLK_030_H_i N_204_i AS_030_000_SYNC_i \ +AMIGA_BUS_ENABLE_DMA_HIGH_i N_282_i vcc_n_n cycle_dma_i_0__n N_278_i \ +ahigh_i_30__n N_186_i gnd_n_n ahigh_i_31__n N_185_i un1_amiga_bus_enable_low \ +ahigh_i_28__n CLK_030_c_i un7_as_030 ahigh_i_29__n N_184_0 un1_LDS_000_INT \ +ahigh_i_26__n N_179_0 un1_UDS_000_INT ahigh_i_27__n N_251_i un10_ciin \ +ahigh_i_24__n LDS_000_c_i un21_fpu_cs ahigh_i_25__n UDS_000_c_i un21_berr \ +N_172_i un6_ds_030 pos_clk_un21_bgack_030_int_i_0_0_n N_163_i clk_000_d_i_3__n \ +N_115_i N_350_i N_114_i un1_rw_i un6_ds_030_i N_126_0 DS_000_DMA_i N_313_i \ +N_132_i N_231_i N_133_i N_291_i un7_as_030_i AMIGA_BUS_ENABLE_DMA_LOW_i \ +N_288_i AS_030_c N_287_i AS_000_c N_340_i RW_000_c N_284_i N_275_i UDS_000_c \ +pos_clk_size_dma_6_0_1__n N_268_i LDS_000_c pos_clk_size_dma_6_0_0__n N_265_i \ +size_c_0__n N_267_i size_c_1__n N_337_i N_338_i ahigh_c_24__n N_55_0 \ +un1_as_000_i ahigh_c_25__n N_245_0 N_229_i pos_clk_un9_bg_030_n ahigh_c_26__n \ +N_227_i ahigh_c_27__n N_226_i ahigh_c_28__n N_246_0 N_332_i ahigh_c_29__n \ +pos_clk_ds_000_dma_4_0_n N_48_0 ahigh_c_30__n pos_clk_rw_000_dma_3_0_n N_218_i \ +ahigh_c_31__n un10_ciin_i pos_clk_a0_dma_3_n N_62_0 pos_clk_rw_000_dma_3_n \ +N_215_i N_216_i un10_amiga_bus_enable_high_i N_214_i N_310_0 N_24_i N_33_0 \ +pos_clk_ds_000_dma_4_n N_23_i N_3 N_32_0 N_4 N_22_i N_31_0 N_3_i N_45_0 N_4_i \ +N_44_0 N_15 N_15_i N_19 N_40_0 N_20 N_19_i N_22 N_36_0 N_23 N_20_i N_24 N_35_0 \ +N_25 N_25_i N_26 N_30_0 N_27 N_26_i N_29_0 N_27_i a_decode_c_16__n N_28_0 \ +BG_030_c_i a_decode_c_17__n pos_clk_un9_bg_030_0_n N_235_i_1 a_decode_c_18__n \ +N_235_i_2 N_156_i_1 a_decode_c_19__n N_156_i_2 N_156_i_3 a_decode_c_20__n \ +N_156_i_4 pos_clk_un10_sm_amiga_i_1_n a_decode_c_21__n N_176_i_1 un10_ciin_1 \ +a_decode_c_22__n un10_ciin_2 un10_ciin_3 a_decode_c_23__n un10_ciin_4 \ +un10_ciin_5 a_c_0__n un10_ciin_6 un10_ciin_7 a_c_1__n un10_ciin_8 un10_ciin_9 \ +pos_clk_size_dma_6_0__n nEXP_SPACE_c un10_ciin_10 pos_clk_size_dma_6_1__n \ +un10_ciin_11 N_199 BERR_c N_163_i_1 pos_clk_un21_bgack_030_int_i_0_n N_163_i_2 \ +N_231 BG_030_c pos_clk_un21_bgack_030_int_i_0_0_1_n N_233 \ +pos_clk_un21_bgack_030_int_i_0_0_2_n N_111 N_138_i_1 N_112 N_138_i_2 N_113 \ +N_59_i_1 N_114 BGACK_000_c N_59_i_2 N_115 N_233_0_1 N_245 CLK_030_c N_233_0_2 \ +N_246 N_214_1 N_62 N_214_2 N_214_3 N_132 CLK_OSZI_c un21_fpu_cs_1 N_133 \ +un21_berr_1_0 N_310 N_182_0_1 N_126 N_234_i_1 N_149 N_234_i_2 N_150 N_206_1 \ +N_158 FPU_SENSE_c N_206_2 N_160 N_205_1 N_163 N_205_2 N_172 N_352_1 N_179 \ +N_352_2 N_184 N_231_i_1 N_185 N_152_i_1 N_196 N_144_i_1 N_203 ipl_c_0__n \ +N_142_i_1 N_204 N_312_i_1 N_209 ipl_c_1__n N_236_i_1 N_214 N_148_i_1 N_215 \ +ipl_c_2__n N_136_i_1 N_216 N_246_0_1 N_218 N_249_i_1 N_224 DTACK_c N_57_i_1 \ +N_332 N_338_1 N_226 N_224_1 N_227 N_216_1 N_229 VPA_c N_209_1 N_337 N_203_1 \ +N_338 N_196_1 N_265 RST_c cpu_est_0_3__un3_n N_267 cpu_est_0_3__un1_n N_268 \ +cpu_est_0_3__un0_n N_275 RW_c rw_000_int_0_un3_n N_278 rw_000_int_0_un1_n \ +N_282 fc_c_0__n rw_000_int_0_un0_n N_284 vma_int_0_un3_n N_340 fc_c_1__n \ +vma_int_0_un1_n N_287 vma_int_0_un0_n N_288 cpu_est_0_1__un3_n N_291 \ +AMIGA_BUS_DATA_DIR_c cpu_est_0_1__un1_n N_293 cpu_est_0_1__un0_n N_350 \ +cpu_est_0_2__un3_n N_355 cpu_est_0_2__un1_n cpu_est_0_2__un0_n N_16_i \ +uds_000_int_0_un3_n N_39_0 uds_000_int_0_un1_n VPA_c_i uds_000_int_0_un0_n \ +N_52_0 lds_000_int_0_un3_n N_156 DTACK_c_i lds_000_int_0_un1_n N_201 N_53_0 \ +lds_000_int_0_un0_n N_202 N_210_i bgack_030_int_0_un3_n N_154 N_211_i \ +bgack_030_int_0_un1_n un21_berr_1 N_189_i bgack_030_int_0_un0_n N_174 \ +un1_SM_AMIGA_0_sqmuxa_1_0 ds_000_enable_0_un3_n N_223 RW_c_i \ +ds_000_enable_0_un1_n N_221 N_311_0 ds_000_enable_0_un0_n N_222 N_336_i \ +size_dma_0_0__un3_n N_219 N_244_i size_dma_0_0__un1_n N_220 \ +size_dma_0_0__un0_n pos_clk_un6_bgack_000_n N_314_0 size_dma_0_1__un3_n N_359 \ +N_159_i size_dma_0_1__un1_n N_8 VMA_INT_i size_dma_0_1__un0_n N_14 N_352_i \ +ipl_030_0_0__un3_n N_21 N_353_i ipl_030_0_0__un1_n N_9 N_293_i \ +ipl_030_0_0__un0_n un1_DS_000_ENABLE_0_sqmuxa N_175_i ipl_030_0_1__un3_n N_66 \ +N_176_i ipl_030_0_1__un1_n N_171 ipl_030_0_1__un0_n N_354 N_198_i \ +ipl_030_0_2__un3_n N_18 N_197_i ipl_030_0_2__un1_n pos_clk_un9_clk_000_pe_n \ +N_196_i ipl_030_0_2__un0_n cpu_est_2_1__n N_183_0 a0_dma_0_un3_n \ +cpu_est_2_2__n N_182_0 a0_dma_0_un1_n N_197 N_180_0 a0_dma_0_un0_n N_198 \ +N_178_0 amiga_bus_enable_dma_low_0_un3_n N_208 N_82_i \ +amiga_bus_enable_dma_low_0_un1_n N_210 N_315_i \ +amiga_bus_enable_dma_low_0_un0_n N_315 N_351_i \ +amiga_bus_enable_dma_high_0_un3_n N_212 N_154_0 \ +amiga_bus_enable_dma_high_0_un1_n N_180 N_149_i \ +amiga_bus_enable_dma_high_0_un0_n N_213 N_207_i bg_000_0_un3_n N_178 N_228_i \ +bg_000_0_un1_n N_228 bg_000_0_un0_n N_182 N_213_i ds_000_dma_0_un3_n N_176 \ +N_212_i ds_000_dma_0_un1_n N_183 N_309_i ds_000_dma_0_un0_n N_351 N_357_i \ +as_000_dma_0_un3_n N_357 cpu_est_2_0_2__n as_000_dma_0_un1_n N_206 N_208_i \ +as_000_dma_0_un0_n N_205 N_209_i as_030_000_sync_0_un3_n N_352 \ +cpu_est_2_0_1__n as_030_000_sync_0_un1_n N_353 N_206_i as_030_000_sync_0_un0_n \ +N_314 N_205_i rw_000_dma_0_un3_n N_244 pos_clk_un9_clk_000_pe_0_n \ +rw_000_dma_0_un1_n N_336 N_18_i rw_000_dma_0_un0_n N_311 N_37_0 a_decode_15__n \ +un1_SM_AMIGA_0_sqmuxa_1 N_171_i N_211 N_354_i a_decode_14__n N_16 \ +un1_DS_000_ENABLE_0_sqmuxa_0 un1_amiga_bus_enable_low_i N_66_0 a_decode_13__n \ +un21_fpu_cs_i UDS_000_INT_i cpu_est_i_2__n un1_UDS_000_INT_0 a_decode_12__n \ +cpu_est_i_0__n LDS_000_INT_i VPA_D_i un1_LDS_000_INT_0 a_decode_11__n \ +DTACK_D0_i N_21_i cpu_est_i_3__n N_34_0 a_decode_10__n sm_amiga_i_i_7__n \ +N_14_i sm_amiga_i_5__n N_41_0 a_decode_9__n sm_amiga_i_3__n N_8_i \ +cpu_est_i_1__n N_42_0 a_decode_8__n clk_000_d_i_1__n a_c_i_0__n N_355_i_0 \ +size_c_i_1__n a_decode_7__n sm_amiga_i_4__n pos_clk_un10_sm_amiga_i_n \ +sm_amiga_i_2__n N_359_i a_decode_6__n rst_dly_i_0__n pos_clk_un6_bgack_000_0_n \ +rst_dly_i_2__n N_220_i a_decode_5__n a_decode_i_19__n N_219_i a_decode_i_18__n \ +a_decode_4__n a_decode_i_16__n N_222_i RW_000_i N_221_i a_decode_3__n \ +sm_amiga_i_0__n AS_030_i N_223_i a_decode_2__n AS_000_INT_i N_224_i \ +DSACK1_INT_i AMIGA_BUS_DATA_DIR_c_0 clk_000_d_i_0__n N_150_i sm_amiga_i_6__n \ +N_156_i sm_amiga_i_1__n N_160_i FPU_SENSE_i N_174_i rst_dly_i_1__n N_158_i \ +AS_030_D0_i N_201_i BGACK_030_INT_i N_202_i nEXP_SPACE_i N_203_i RESET_OUT_i \ +AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE \ +AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE \ +AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE \ +CIIN.OE pos_clk_un21_bgack_030_int_i_0_o3_0_x2 pos_clk_un1_ipl_i_0_x2 \ +pos_clk_un1_ipl_i_0_x2_0 pos_clk_un1_ipl_i_0_x2_1 pos_clk_CYCLE_DMA_5_1_i_0_x2 +.names N_113.BLIF IPL_D0_0_.D 0 1 -.names N_29_0.BLIF IPL_030DFF_1_reg.D +.names N_112.BLIF IPL_D0_1_.D 0 1 -.names N_30_0.BLIF IPL_030DFF_2_reg.D +.names N_111.BLIF IPL_D0_2_.D 0 1 -.names N_49_0.BLIF IPL_D0_0_.D -0 1 -.names N_50_0.BLIF IPL_D0_1_.D -0 1 -.names N_51_0.BLIF IPL_D0_2_.D -0 1 -.names N_235_i_1.BLIF N_235_i_2.BLIF CYCLE_DMA_0_.D +.names N_152_i_1.BLIF RST_c.BLIF SM_AMIGA_i_7_.D 11 1 -.names N_136_i_1.BLIF N_245_0.BLIF CYCLE_DMA_1_.D +.names N_148_i_1.BLIF RST_c.BLIF SM_AMIGA_6_.D 11 1 -.names size_dma_0_0__un1_n.BLIF size_dma_0_0__un0_n.BLIF SIZE_DMA_0_.D -1- 1 --1 1 -.names size_dma_0_1__un1_n.BLIF size_dma_0_1__un0_n.BLIF SIZE_DMA_1_.D -1- 1 --1 1 -.names N_341_i.BLIF N_342_i.BLIF cpu_est_0_.D +.names N_82_i.BLIF N_228_i.BLIF SM_AMIGA_5_.D +11 1 +.names N_144_i_1.BLIF RST_c.BLIF SM_AMIGA_4_.D +11 1 +.names N_142_i_1.BLIF RST_c.BLIF SM_AMIGA_3_.D +11 1 +.names N_312_i_1.BLIF RST_c.BLIF SM_AMIGA_2_.D +11 1 +.names N_138_i_1.BLIF N_138_i_2.BLIF SM_AMIGA_1_.D +11 1 +.names N_136_i_1.BLIF RST_c.BLIF SM_AMIGA_0_.D +11 1 +.names N_244_i.BLIF N_336_i.BLIF cpu_est_0_.D 11 1 .names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D 1- 1 @@ -440,44 +421,31 @@ pos_clk_CYCLE_DMA_5_1_i_x2 pos_clk_un21_bgack_030_int_i_i_a2_i_x2 .names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D 1- 1 -1 1 -.names N_234_i_1.BLIF RST_c.BLIF RST_DLY_0_.D +.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_.D +1- 1 +-1 1 +.names N_31_0.BLIF IPL_030DFF_0_reg.D +0 1 +.names N_32_0.BLIF IPL_030DFF_1_reg.D +0 1 +.names N_33_0.BLIF IPL_030DFF_2_reg.D +0 1 +.names N_234_i_1.BLIF N_234_i_2.BLIF RST_DLY_2_.D 11 1 -.names N_233_i_1.BLIF N_233_i_2.BLIF RST_DLY_1_.D +.names N_59_i_1.BLIF N_59_i_2.BLIF CYCLE_DMA_0_.D 11 1 -.names N_232_i_1.BLIF N_232_i_2.BLIF RST_DLY_2_.D +.names N_57_i_1.BLIF N_251_i.BLIF CYCLE_DMA_1_.D 11 1 -.names N_45_0.BLIF inst_DS_000_DMA.D -0 1 -.names N_231_i.BLIF N_237_i.BLIF inst_DSACK1_INT.D +.names size_dma_0_0__un1_n.BLIF size_dma_0_0__un0_n.BLIF SIZE_DMA_0_.D +1- 1 +-1 1 +.names size_dma_0_1__un1_n.BLIF size_dma_0_1__un0_n.BLIF SIZE_DMA_1_.D +1- 1 +-1 1 +.names N_236_i_1.BLIF RST_c.BLIF RST_DLY_0_.D 11 1 -.names N_319_i.BLIF N_320_i.BLIF inst_AS_000_INT.D +.names N_235_i_1.BLIF N_235_i_2.BLIF RST_DLY_1_.D 11 1 -.names N_48_0.BLIF inst_AS_030_D0.D -0 1 -.names N_52_0.BLIF inst_VPA_D.D -0 1 -.names N_53_0.BLIF inst_DTACK_D0.D -0 1 -.names N_63_i_1.BLIF RST_c.BLIF inst_CLK_030_H.D -11 1 -.names N_298_0.BLIF inst_RESET_OUT.D -0 1 -.names N_9.BLIF RST_c.BLIF inst_DS_000_ENABLE.D -11 1 -.names N_31_0.BLIF BG_000DFFreg.D -0 1 -.names N_32_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D -0 1 -.names N_33_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D -0 1 -.names N_34_0.BLIF inst_UDS_000_INT.D -0 1 -.names N_35_0.BLIF inst_A0_DMA.D -0 1 -.names N_36_0.BLIF inst_RW_000_DMA.D -0 1 -.names N_37_0.BLIF inst_VMA_INTreg.D -0 1 .names N_39_0.BLIF inst_RW_000_INT.D 0 1 .names N_40_0.BLIF inst_AS_030_000_SYNC.D @@ -488,303 +456,336 @@ pos_clk_CYCLE_DMA_5_1_i_x2 pos_clk_un21_bgack_030_int_i_i_a2_i_x2 0 1 .names N_44_0.BLIF inst_AS_000_DMA.D 0 1 -.names N_245_0.BLIF inst_BGACK_030_INT_D.D +.names N_45_0.BLIF inst_DS_000_DMA.D +0 1 +.names N_219_i.BLIF N_220_i.BLIF inst_DSACK1_INT.D +11 1 +.names N_221_i.BLIF N_222_i.BLIF inst_AS_000_INT.D +11 1 +.names N_48_0.BLIF inst_AS_030_D0.D +0 1 +.names N_52_0.BLIF inst_VPA_D.D +0 1 +.names N_53_0.BLIF inst_DTACK_D0.D +0 1 +.names N_249_i_1.BLIF pos_clk_un21_bgack_030_int_i_0_0_n.BLIF inst_CLK_030_H.D +11 1 +.names N_55_0.BLIF inst_RESET_OUT.D +0 1 +.names N_9.BLIF RST_c.BLIF inst_DS_000_ENABLE.D +11 1 +.names N_28_0.BLIF BG_000DFFreg.D +0 1 +.names N_29_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D +0 1 +.names N_30_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D +0 1 +.names N_34_0.BLIF inst_UDS_000_INT.D +0 1 +.names N_35_0.BLIF inst_A0_DMA.D +0 1 +.names N_36_0.BLIF inst_RW_000_DMA.D +0 1 +.names N_37_0.BLIF inst_VMA_INTreg.D +0 1 +.names N_251_i.BLIF inst_BGACK_030_INT_D.D 0 1 .names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D 0 1 -.names RST_DLY_1_.BLIF rst_dly_i_1__n +.names ipl_c_2__n.BLIF ipl_i_2__n 0 1 -.names N_14_i.BLIF RST_c.BLIF N_41_0 +.names N_233_0_1.BLIF N_233_0_2.BLIF N_233_0 11 1 -.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +.names ipl_c_1__n.BLIF ipl_i_1__n 0 1 -.names a_c_0__n.BLIF a_c_i_0__n +.names pos_clk_un1_ipl_i_0_x2.BLIF N_360_i 0 1 -.names RST_DLY_0_.BLIF rst_dly_i_0__n +.names ipl_c_0__n.BLIF ipl_i_0__n 0 1 -.names size_c_1__n.BLIF size_c_i_1__n -0 1 -.names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n -0 1 -.names pos_clk_un10_sm_amiga_i_1_n.BLIF size_c_i_1__n.BLIF \ -pos_clk_un10_sm_amiga_i_n -11 1 -.names inst_AS_030_D0.BLIF AS_030_D0_i -0 1 -.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF un1_as_000_i -11 1 -.names inst_AS_000_INT.BLIF AS_000_INT_i -0 1 -.names un10_ciin.BLIF un10_ciin_i +.names pos_clk_un1_ipl_i_0_x2_0.BLIF N_191_i_i 0 1 .names a_c_1__n.BLIF a_i_1__n 0 1 -.names nEXP_SPACE_i.BLIF un10_ciin_i.BLIF N_260_0 -11 1 -.names a_decode_c_16__n.BLIF a_decode_i_16__n +.names pos_clk_un1_ipl_i_0_x2_1.BLIF N_192_i_i 0 1 -.names N_229.BLIF N_229_i +.names inst_AS_000_DMA.BLIF AS_000_DMA_i 0 1 -.names a_decode_c_18__n.BLIF a_decode_i_18__n +.names AS_000_c.BLIF AS_000_i 0 1 -.names N_230.BLIF N_230_i +.names N_199.BLIF N_199_i +0 1 +.names inst_CLK_030_H.BLIF CLK_030_H_i +0 1 +.names N_204.BLIF N_204_i +0 1 +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +0 1 +.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i +0 1 +.names N_282.BLIF N_282_i 0 1 .names vcc_n_n 1 -.names a_decode_c_19__n.BLIF a_decode_i_19__n +.names CYCLE_DMA_0_.BLIF cycle_dma_i_0__n +0 1 +.names N_278.BLIF N_278_i 0 1 -.names N_229_i.BLIF N_230_i.BLIF N_298_0 -11 1 .names ahigh_c_30__n.BLIF ahigh_i_30__n 0 1 -.names AS_030_i.BLIF RST_c.BLIF N_48_0 +.names BGACK_030_INT_i.BLIF nEXP_SPACE_i.BLIF N_186_i 11 1 .names gnd_n_n .names ahigh_c_31__n.BLIF ahigh_i_31__n 0 1 -.names BGACK_030_INT_i.BLIF nEXP_SPACE_i.BLIF N_299_i +.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF N_185_i 11 1 .names AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF BGACK_030_INT_i.BLIF \ un1_amiga_bus_enable_low 11 1 .names ahigh_c_28__n.BLIF ahigh_i_28__n 0 1 -.names N_345.BLIF N_345_i +.names CLK_030_c.BLIF CLK_030_c_i 0 1 .names AS_000_DMA_i.BLIF AS_000_i.BLIF un7_as_030 11 1 .names ahigh_c_29__n.BLIF ahigh_i_29__n 0 1 -.names N_349.BLIF N_349_i -0 1 -.names un1_UDS_000_INT_0.BLIF un1_UDS_000_INT -0 1 -.names ahigh_c_26__n.BLIF ahigh_i_26__n -0 1 -.names N_181.BLIF N_349_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_i +.names AS_000_DMA_i.BLIF CLK_030_c_i.BLIF N_184_0 11 1 .names un1_LDS_000_INT_0.BLIF un1_LDS_000_INT 0 1 +.names ahigh_c_26__n.BLIF ahigh_i_26__n +0 1 +.names N_163_i.BLIF sm_amiga_i_i_7__n.BLIF N_179_0 +11 1 +.names un1_UDS_000_INT_0.BLIF un1_UDS_000_INT +0 1 .names ahigh_c_27__n.BLIF ahigh_i_27__n 0 1 -.names N_180_i_1.BLIF N_180_i_2.BLIF N_180_i -11 1 -.names un1_SM_AMIGA_0_sqmuxa_1_0.BLIF un1_SM_AMIGA_0_sqmuxa_1 -0 1 -.names ahigh_c_24__n.BLIF ahigh_i_24__n -0 1 -.names N_155_i.BLIF SM_AMIGA_4_.BLIF N_181_i +.names BGACK_030_INT_i.BLIF RST_c.BLIF N_251_i 11 1 .names un10_ciin_10.BLIF un10_ciin_11.BLIF un10_ciin 11 1 -.names ahigh_c_25__n.BLIF ahigh_i_25__n +.names ahigh_c_24__n.BLIF ahigh_i_24__n 0 1 -.names N_326.BLIF N_326_i -0 1 -.names un21_fpu_cs_1.BLIF N_161_i.BLIF un21_fpu_cs -11 1 -.names G_107.BLIF N_206_i -0 1 -.names un21_berr_1_0.BLIF N_161_i.BLIF un21_berr -11 1 -.names G_108.BLIF N_207_i -0 1 -.names N_305.BLIF RST_c.BLIF N_186_i -11 1 -.names AS_000_i.BLIF DS_000_DMA_i.BLIF un6_ds_030 -11 1 -.names G_109.BLIF N_208_i -0 1 -.names RST_DLY_0_.BLIF RST_DLY_1_.BLIF N_163_i -11 1 -.names N_305_i.BLIF SM_AMIGA_5_.BLIF N_197_0 -11 1 -.names N_79.BLIF N_79_i -0 1 -.names N_213.BLIF N_213_i -0 1 -.names N_78.BLIF N_78_i -0 1 -.names N_214.BLIF N_214_i -0 1 -.names un6_ds_030.BLIF un6_ds_030_i -0 1 -.names N_215.BLIF N_215_i -0 1 -.names N_165.BLIF N_165_i -0 1 -.names N_169.BLIF N_169_i -0 1 -.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF N_199_i -11 1 -.names un7_as_030.BLIF un7_as_030_i -0 1 -.names N_171_i.BLIF sm_amiga_i_i_7__n.BLIF N_191_0 -11 1 -.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i -0 1 -.names N_275.BLIF N_275_i -0 1 -.names N_275_i.BLIF SM_AMIGA_i_7_.BLIF N_187_0 -11 1 .names LDS_000_c.BLIF LDS_000_c_i 0 1 +.names un21_fpu_cs_1.BLIF N_156_i.BLIF un21_fpu_cs +11 1 +.names ahigh_c_25__n.BLIF ahigh_i_25__n +0 1 .names UDS_000_c.BLIF UDS_000_c_i 0 1 -.names LDS_000_c_i.BLIF UDS_000_c_i.BLIF N_184_i +.names un21_berr_1_0.BLIF N_156_i.BLIF un21_berr 11 1 -.names CLK_000_D_4_.BLIF clk_000_d_i_4__n -0 1 -.names N_171_i_1.BLIF N_171_i_2.BLIF N_171_i +.names LDS_000_c_i.BLIF UDS_000_c_i.BLIF N_172_i 11 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i -0 1 -.names N_161_i_4.BLIF N_161_i_3.BLIF N_161_i +.names AS_000_i.BLIF DS_000_DMA_i.BLIF un6_ds_030 11 1 -.names N_199_i.BLIF RST_c.BLIF N_113_0 +.names pos_clk_un21_bgack_030_int_i_0_0_1_n.BLIF \ +pos_clk_un21_bgack_030_int_i_0_0_2_n.BLIF pos_clk_un21_bgack_030_int_i_0_0_n 11 1 -.names N_338.BLIF N_338_i -0 1 -.names N_339.BLIF N_339_i -0 1 -.names N_335.BLIF N_335_i -0 1 -.names N_336.BLIF N_336_i -0 1 -.names N_334.BLIF N_334_i -0 1 -.names N_334_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n +.names N_163_i_1.BLIF N_163_i_2.BLIF N_163_i 11 1 -.names pos_clk_un6_bg_030_1_n.BLIF CLK_000_D_0_.BLIF pos_clk_un6_bg_030_n +.names CLK_000_D_3_.BLIF clk_000_d_i_3__n +0 1 +.names N_115.BLIF N_115_i +0 1 +.names N_350.BLIF N_350_i +0 1 +.names N_114.BLIF N_114_i +0 1 +.names BGACK_030_INT_i.BLIF inst_RESET_OUT.BLIF un1_rw_i 11 1 -.names N_333.BLIF N_333_i +.names un6_ds_030.BLIF un6_ds_030_i 0 1 -.names N_333_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n +.names N_185_i.BLIF RST_c.BLIF N_126_0 11 1 -.names pos_clk_ipl_1_n.BLIF N_207_i.BLIF pos_clk_ipl_n +.names inst_DS_000_DMA.BLIF DS_000_DMA_i +0 1 +.names N_186_i.BLIF inst_RESET_OUT.BLIF N_313_i 11 1 -.names N_295.BLIF N_295_i +.names N_132.BLIF N_132_i 0 1 -.names N_332.BLIF N_332_i -0 1 -.names N_292.BLIF N_292_i -0 1 -.names N_302_0_1.BLIF RW_000_i.BLIF N_302_0 +.names N_231_i_1.BLIF nEXP_SPACE_c.BLIF N_231_i 11 1 -.names pos_clk_un9_bg_030_0_n.BLIF pos_clk_un9_bg_030_n +.names N_133.BLIF N_133_i 0 1 -.names BGACK_030_INT_i.BLIF RW_000_i.BLIF N_300_0 +.names N_291.BLIF N_291_i +0 1 +.names un7_as_030.BLIF un7_as_030_i +0 1 +.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i +0 1 +.names N_288.BLIF N_288_i +0 1 +.names N_287.BLIF N_287_i +0 1 +.names N_340.BLIF N_340_i +0 1 +.names N_284.BLIF N_284_i +0 1 +.names N_275.BLIF N_275_i +0 1 +.names N_275_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n 11 1 -.names N_290.BLIF N_290_i +.names N_268.BLIF N_268_i 0 1 -.names N_273.BLIF N_273_i -0 1 -.names N_327.BLIF N_327_i -0 1 -.names N_270.BLIF N_270_i -0 1 -.names N_269.BLIF N_269_i +.names N_268_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n +11 1 +.names N_265.BLIF N_265_i 0 1 .names N_267.BLIF N_267_i 0 1 -.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF pos_clk_a0_dma_3_n +.names N_337.BLIF N_337_i +0 1 +.names N_338.BLIF N_338_i +0 1 +.names N_337_i.BLIF N_338_i.BLIF N_55_0 11 1 -.names N_324.BLIF N_324_i -0 1 -.names pos_clk_rw_000_int_5_0_n.BLIF pos_clk_rw_000_int_5_n -0 1 -.names N_166.BLIF N_187_0.BLIF un1_SM_AMIGA_0_sqmuxa_1_0 +.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF un1_as_000_i 11 1 -.names N_319.BLIF N_319_i -0 1 -.names N_320.BLIF N_320_i -0 1 -.names RW_c.BLIF RW_c_i -0 1 -.names N_187_0.BLIF RW_c_i.BLIF pos_clk_rw_000_int_5_0_n +.names CLK_030_c_i.BLIF pos_clk_un21_bgack_030_int_i_0_0_n.BLIF N_245_0 11 1 +.names N_229.BLIF N_229_i +0 1 +.names pos_clk_un9_bg_030_0_n.BLIF pos_clk_un9_bg_030_n +0 1 .names N_227.BLIF N_227_i 0 1 -.names AS_030_i.BLIF N_227_i.BLIF N_297_0 -11 1 -.names N_15.BLIF N_15_i +.names N_226.BLIF N_226_i 0 1 -.names N_15_i.BLIF RST_c.BLIF N_40_0 +.names N_246_0_1.BLIF pos_clk_un21_bgack_030_int_i_0_0_n.BLIF N_246_0 11 1 -.names N_16.BLIF N_16_i +.names N_332.BLIF N_332_i 0 1 -.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF N_15 -1- 1 --1 1 -.names N_16_i.BLIF RST_c.BLIF N_39_0 +.names N_332_i.BLIF pos_clk_un21_bgack_030_int_i_0_0_n.BLIF \ +pos_clk_ds_000_dma_4_0_n 11 1 -.names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF N_16 -1- 1 --1 1 -.names N_19.BLIF N_19_i +.names AS_030_i.BLIF RST_c.BLIF N_48_0 +11 1 +.names BGACK_030_INT_i.BLIF RW_000_i.BLIF pos_clk_rw_000_dma_3_0_n +11 1 +.names N_218.BLIF N_218_i 0 1 -.names rw_000_dma_0_un1_n.BLIF rw_000_dma_0_un0_n.BLIF N_19 -1- 1 --1 1 -.names N_19_i.BLIF RST_c.BLIF N_36_0 -11 1 -.names a0_dma_0_un1_n.BLIF a0_dma_0_un0_n.BLIF N_20 -1- 1 --1 1 -.names N_20.BLIF N_20_i +.names un10_ciin.BLIF un10_ciin_i 0 1 -.names amiga_bus_enable_dma_low_0_un1_n.BLIF \ -amiga_bus_enable_dma_low_0_un0_n.BLIF N_22 +.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF pos_clk_a0_dma_3_n +11 1 +.names nEXP_SPACE_i.BLIF un10_ciin_i.BLIF N_62_0 +11 1 +.names pos_clk_rw_000_dma_3_0_n.BLIF pos_clk_rw_000_dma_3_n +0 1 +.names N_215.BLIF N_215_i +0 1 +.names N_216.BLIF N_216_i +0 1 +.names N_215_i.BLIF N_216_i.BLIF un10_amiga_bus_enable_high_i +11 1 +.names N_214.BLIF N_214_i +0 1 +.names AS_030_i.BLIF N_214_i.BLIF N_310_0 +11 1 +.names N_24.BLIF N_24_i +0 1 +.names N_24_i.BLIF RST_c.BLIF N_33_0 +11 1 +.names pos_clk_ds_000_dma_4_0_n.BLIF pos_clk_ds_000_dma_4_n +0 1 +.names N_23.BLIF N_23_i +0 1 +.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3 1- 1 -1 1 -.names N_20_i.BLIF RST_c.BLIF N_35_0 +.names N_23_i.BLIF RST_c.BLIF N_32_0 11 1 -.names amiga_bus_enable_dma_high_0_un1_n.BLIF \ -amiga_bus_enable_dma_high_0_un0_n.BLIF N_23 +.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF N_4 1- 1 -1 1 .names N_22.BLIF N_22_i 0 1 -.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF N_24 +.names N_22_i.BLIF RST_c.BLIF N_31_0 +11 1 +.names N_3.BLIF N_3_i +0 1 +.names N_3_i.BLIF RST_c.BLIF N_45_0 +11 1 +.names N_4.BLIF N_4_i +0 1 +.names N_4_i.BLIF RST_c.BLIF N_44_0 +11 1 +.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF N_15 1- 1 -1 1 -.names N_22_i.BLIF RST_c.BLIF N_33_0 -11 1 -.names N_23.BLIF N_23_i +.names N_15.BLIF N_15_i 0 1 -.names N_23_i.BLIF RST_c.BLIF N_32_0 +.names rw_000_dma_0_un1_n.BLIF rw_000_dma_0_un0_n.BLIF N_19 +1- 1 +-1 1 +.names N_15_i.BLIF RST_c.BLIF N_40_0 11 1 -.names N_24.BLIF N_24_i +.names a0_dma_0_un1_n.BLIF a0_dma_0_un0_n.BLIF N_20 +1- 1 +-1 1 +.names N_19.BLIF N_19_i 0 1 -.names N_24_i.BLIF RST_c.BLIF N_31_0 +.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF N_22 +1- 1 +-1 1 +.names N_19_i.BLIF RST_c.BLIF N_36_0 +11 1 +.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF N_23 +1- 1 +-1 1 +.names N_20.BLIF N_20_i +0 1 +.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_24 +1- 1 +-1 1 +.names N_20_i.BLIF RST_c.BLIF N_35_0 +11 1 +.names amiga_bus_enable_dma_low_0_un1_n.BLIF \ +amiga_bus_enable_dma_low_0_un0_n.BLIF N_25 +1- 1 +-1 1 +.names N_25.BLIF N_25_i +0 1 +.names amiga_bus_enable_dma_high_0_un1_n.BLIF \ +amiga_bus_enable_dma_high_0_un0_n.BLIF N_26 +1- 1 +-1 1 +.names N_25_i.BLIF RST_c.BLIF N_30_0 +11 1 +.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF N_27 +1- 1 +-1 1 +.names N_26.BLIF N_26_i +0 1 +.names N_26_i.BLIF RST_c.BLIF N_29_0 +11 1 +.names N_27.BLIF N_27_i +0 1 +.names N_27_i.BLIF RST_c.BLIF N_28_0 11 1 .names BG_030_c.BLIF BG_030_c_i 0 1 -.names pos_clk_un6_bg_030_n.BLIF pos_clk_un6_bg_030_i_n -0 1 -.names BG_030_c_i.BLIF pos_clk_un6_bg_030_i_n.BLIF pos_clk_un9_bg_030_0_n +.names BG_030_c_i.BLIF N_231.BLIF pos_clk_un9_bg_030_0_n 11 1 -.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_161_i_1 +.names N_201_i.BLIF N_202_i.BLIF N_235_i_1 11 1 -.names a_decode_c_17__n.BLIF a_decode_i_16__n.BLIF N_161_i_2 +.names N_203_i.BLIF RST_c.BLIF N_235_i_2 11 1 -.names a_decode_i_18__n.BLIF a_decode_i_19__n.BLIF N_161_i_3 +.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_156_i_1 11 1 -.names N_161_i_1.BLIF N_161_i_2.BLIF N_161_i_4 +.names a_decode_c_17__n.BLIF a_decode_i_16__n.BLIF N_156_i_2 11 1 -.names N_213_i.BLIF N_214_i.BLIF N_233_i_1 +.names a_decode_i_18__n.BLIF a_decode_i_19__n.BLIF N_156_i_3 11 1 -.names N_215_i.BLIF RST_c.BLIF N_233_i_2 -11 1 -.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_180_i_1 -11 1 -.names N_345_i.BLIF pos_clk_un21_bgack_030_int_i_i_a2_i_x2.BLIF N_180_i_2 +.names N_156_i_1.BLIF N_156_i_2.BLIF N_156_i_4 11 1 .names size_c_0__n.BLIF a_c_i_0__n.BLIF pos_clk_un10_sm_amiga_i_1_n 11 1 -.names N_188.BLIF N_305_i.BLIF N_196_0_1 -11 1 -.names BERR_c.BLIF N_347_i.BLIF N_188_i_1 +.names BERR_c.BLIF N_352_i.BLIF N_176_i_1 11 1 .names ahigh_i_24__n.BLIF ahigh_i_25__n.BLIF un10_ciin_1 11 1 @@ -798,699 +799,694 @@ amiga_bus_enable_dma_high_0_un0_n.BLIF N_23 11 1 .names a_decode_c_20__n.BLIF a_decode_c_21__n.BLIF un10_ciin_6 11 1 -.names pos_clk_size_dma_6_0_0__n.BLIF pos_clk_size_dma_6_0__n -0 1 .names un10_ciin_1.BLIF un10_ciin_2.BLIF un10_ciin_7 11 1 -.names pos_clk_size_dma_6_0_1__n.BLIF pos_clk_size_dma_6_1__n -0 1 .names un10_ciin_3.BLIF un10_ciin_4.BLIF un10_ciin_8 11 1 .names un10_ciin_5.BLIF un10_ciin_6.BLIF un10_ciin_9 11 1 +.names pos_clk_size_dma_6_0_0__n.BLIF pos_clk_size_dma_6_0__n +0 1 .names un10_ciin_7.BLIF un10_ciin_8.BLIF un10_ciin_10 11 1 +.names pos_clk_size_dma_6_0_1__n.BLIF pos_clk_size_dma_6_1__n +0 1 .names un10_ciin_9.BLIF a_decode_c_22__n.BLIF un10_ciin_11 11 1 -.names AS_030_000_SYNC_i.BLIF CLK_000_D_5_.BLIF N_171_i_1 +.names CYCLE_DMA_0_.BLIF N_150_i.BLIF N_199 11 1 -.names a_c_1__n.BLIF BGACK_030_INT_i.BLIF N_78 +.names AS_030_000_SYNC_i.BLIF CLK_000_D_4_.BLIF N_163_i_1 11 1 -.names clk_000_d_i_4__n.BLIF nEXP_SPACE_c.BLIF N_171_i_2 -11 1 -.names a_i_1__n.BLIF BGACK_030_INT_i.BLIF N_79 -11 1 -.names AS_030_D0_i.BLIF N_161.BLIF N_227_1 -11 1 -.names N_260_0.BLIF N_260 +.names pos_clk_un21_bgack_030_int_i_0_0_n.BLIF \ +pos_clk_un21_bgack_030_int_i_0_n 0 1 -.names N_199_i.BLIF sm_amiga_i_i_7__n.BLIF N_227_2 +.names clk_000_d_i_3__n.BLIF nEXP_SPACE_c.BLIF N_163_i_2 11 1 -.names N_141.BLIF nEXP_SPACE_i.BLIF N_139 +.names N_231_i.BLIF N_231 +0 1 +.names AS_000_i.BLIF BGACK_030_INT_i.BLIF pos_clk_un21_bgack_030_int_i_0_0_1_n 11 1 -.names N_227_1.BLIF N_227_2.BLIF N_227_3 +.names N_233_0.BLIF N_233 +0 1 +.names pos_clk_un21_bgack_030_int_i_0_o3_0_x2.BLIF N_350_i.BLIF \ +pos_clk_un21_bgack_030_int_i_0_0_2_n 11 1 -.names BGACK_030_INT_i.BLIF inst_RESET_OUT.BLIF N_141 +.names ipl_i_2__n.BLIF RST_c.BLIF N_111 +11 1 +.names N_149.BLIF N_278_i.BLIF N_138_i_1 +11 1 +.names ipl_i_1__n.BLIF RST_c.BLIF N_112 +11 1 +.names N_282_i.BLIF RST_c.BLIF N_138_i_2 +11 1 +.names ipl_i_0__n.BLIF RST_c.BLIF N_113 +11 1 +.names AS_000_i.BLIF N_199_i.BLIF N_59_i_1 +11 1 +.names a_c_1__n.BLIF BGACK_030_INT_i.BLIF N_114 +11 1 +.names N_204_i.BLIF N_251_i.BLIF N_59_i_2 +11 1 +.names a_i_1__n.BLIF BGACK_030_INT_i.BLIF N_115 +11 1 +.names N_150_i.BLIF N_191_i_i.BLIF N_233_0_1 +11 1 +.names N_245_0.BLIF N_245 +0 1 +.names N_192_i_i.BLIF N_360_i.BLIF N_233_0_2 +11 1 +.names N_246_0.BLIF N_246 +0 1 +.names AS_030_D0_i.BLIF N_156.BLIF N_214_1 +11 1 +.names N_62_0.BLIF N_62 +0 1 +.names N_185_i.BLIF sm_amiga_i_i_7__n.BLIF N_214_2 +11 1 +.names N_214_1.BLIF N_214_2.BLIF N_214_3 +11 1 +.names AS_030_i.BLIF DSACK1_INT_i.BLIF N_132 11 1 .names un21_berr_1.BLIF FPU_SENSE_i.BLIF un21_fpu_cs_1 11 1 -.names AS_030_i.BLIF DSACK1_INT_i.BLIF N_165 +.names AS_000_INT_i.BLIF AS_030_i.BLIF N_133 11 1 .names un21_berr_1.BLIF FPU_SENSE_c.BLIF un21_berr_1_0 11 1 -.names AS_000_INT_i.BLIF AS_030_i.BLIF N_169 -11 1 -.names AS_000_i.BLIF N_216_i.BLIF N_235_i_1 -11 1 -.names N_297_0.BLIF N_297 +.names N_310_0.BLIF N_310 0 1 -.names N_217_i.BLIF N_245_0.BLIF N_235_i_2 +.names N_149_i.BLIF N_176.BLIF N_182_0_1 11 1 -.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_256_1 -11 1 -.names N_300_0.BLIF N_300 +.names N_126_0.BLIF N_126 0 1 -.names RW_000_c.BLIF nEXP_SPACE_i.BLIF N_256_2 +.names N_196_i.BLIF N_197_i.BLIF N_234_i_1 11 1 -.names N_302_0.BLIF N_302 +.names N_149_i.BLIF N_149 0 1 -.names N_209_i.BLIF N_211_i.BLIF N_232_i_1 +.names N_198_i.BLIF RST_c.BLIF N_234_i_2 11 1 -.names N_113_0.BLIF N_113 +.names N_150_i.BLIF N_150 0 1 -.names N_306_i.BLIF RST_c.BLIF N_232_i_2 +.names N_149_i.BLIF N_357.BLIF N_206_1 11 1 -.names N_305_i.BLIF N_305 +.names N_158_i.BLIF N_158 0 1 -.names N_305_i.BLIF N_352.BLIF N_219_1 +.names VPA_D_i.BLIF cpu_est_i_3__n.BLIF N_206_2 11 1 -.names N_155_i.BLIF N_155 +.names N_160_i.BLIF N_160 0 1 -.names VPA_D_i.BLIF cpu_est_i_3__n.BLIF N_219_2 +.names N_150_i.BLIF N_159_i.BLIF N_205_1 11 1 .names N_163_i.BLIF N_163 0 1 -.names N_155_i.BLIF N_164_i.BLIF N_218_1 +.names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF N_205_2 11 1 -.names N_166_i.BLIF N_166 +.names N_172_i.BLIF N_172 0 1 -.names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF N_218_2 +.names N_159_i.BLIF N_314_0.BLIF N_352_1 11 1 -.names N_171_i.BLIF N_171 +.names N_179_0.BLIF N_179 0 1 -.names N_160_0.BLIF N_164_i.BLIF N_347_1 +.names VMA_INT_i.BLIF VPA_D_i.BLIF N_352_2 11 1 -.names N_180_i.BLIF N_180 +.names N_184_0.BLIF N_184 0 1 -.names VMA_INT_i.BLIF VPA_D_i.BLIF N_347_2 +.names inst_AS_030_D0.BLIF CLK_000_D_0_.BLIF N_231_i_1 11 1 -.names N_184_i.BLIF N_184 +.names N_185_i.BLIF N_185 0 1 -.names AS_000_i.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.BLIF N_136_i_1 +.names N_291_i.BLIF N_293_i.BLIF N_152_i_1 11 1 -.names N_191_0.BLIF N_191 +.names N_196_1.BLIF rst_dly_i_2__n.BLIF N_196 +11 1 +.names N_150.BLIF N_288_i.BLIF N_144_i_1 +11 1 +.names N_203_1.BLIF rst_dly_i_1__n.BLIF N_203 +11 1 +.names N_287_i.BLIF N_340_i.BLIF N_142_i_1 +11 1 +.names cycle_dma_i_0__n.BLIF N_150.BLIF N_204 +11 1 +.names N_150.BLIF N_284_i.BLIF N_312_i_1 +11 1 +.names N_209_1.BLIF cpu_est_i_3__n.BLIF N_209 +11 1 +.names N_265_i.BLIF N_267_i.BLIF N_236_i_1 +11 1 +.names N_214_3.BLIF nEXP_SPACE_c.BLIF N_214 +11 1 +.names N_160.BLIF N_229_i.BLIF N_148_i_1 +11 1 +.names AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF BGACK_030_INT_i.BLIF N_215 +11 1 +.names N_150.BLIF N_227_i.BLIF N_136_i_1 +11 1 +.names N_216_1.BLIF AS_030_i.BLIF N_216 +11 1 +.names N_226_i.BLIF RW_000_i.BLIF N_246_0_1 +11 1 +.names CLK_030_H_i.BLIF N_184.BLIF N_218 +11 1 +.names N_218_i.BLIF RST_c.BLIF N_249_i_1 +11 1 +.names N_224_1.BLIF RW_000_c.BLIF N_224 +11 1 +.names AS_000_i.BLIF pos_clk_CYCLE_DMA_5_1_i_0_x2.BLIF N_57_i_1 +11 1 +.names inst_AS_000_DMA.BLIF RW_000_i.BLIF N_332 +11 1 +.names N_149_i.BLIF N_355.BLIF N_338_1 +11 1 +.names inst_CLK_030_H.BLIF CLK_030_c.BLIF N_226 +11 1 +.names AS_000_i.BLIF N_186_i.BLIF N_224_1 +11 1 +.names N_174.BLIF sm_amiga_i_0__n.BLIF N_227 +11 1 +.names inst_BGACK_030_INTreg.BLIF AS_030_000_SYNC_i.BLIF N_216_1 +11 1 +.names N_179.BLIF sm_amiga_i_6__n.BLIF N_229 +11 1 +.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_209_1 +11 1 +.names inst_RESET_OUT.BLIF RST_c.BLIF N_337 +11 1 +.names N_207_i.BLIF rst_dly_i_0__n.BLIF N_203_1 +11 1 +.names N_338_1.BLIF RST_c.BLIF N_338 +11 1 +.names N_158.BLIF N_207_i.BLIF N_196_1 +11 1 +.names N_154.BLIF RST_DLY_0_.BLIF N_265 +11 1 +.names N_149.BLIF cpu_est_0_3__un3_n 0 1 -.names N_338_i.BLIF N_339_i.BLIF N_146_i_1 +.names N_82_i.BLIF rst_dly_i_0__n.BLIF N_267 11 1 -.names N_199_i.BLIF N_199 +.names cpu_est_3_.BLIF N_149.BLIF cpu_est_0_3__un1_n +11 1 +.names BGACK_030_INT_i.BLIF N_172.BLIF N_268 +11 1 +.names N_189_i.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n +11 1 +.names BGACK_030_INT_i.BLIF N_172_i.BLIF N_275 +11 1 +.names un1_SM_AMIGA_0_sqmuxa_1.BLIF rw_000_int_0_un3_n 0 1 -.names N_335_i.BLIF N_336_i.BLIF N_142_i_1 +.names N_150.BLIF SM_AMIGA_2_.BLIF N_278 11 1 -.names un1_amiga_bus_enable_dma_high_i_m2_0__un1_n.BLIF \ -un1_amiga_bus_enable_dma_high_i_m2_0__un0_n.BLIF N_205 -1- 1 --1 1 -.names N_295_i.BLIF N_332_i.BLIF N_234_i_1 +.names N_311.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF rw_000_int_0_un1_n 11 1 -.names N_306_1.BLIF rst_dly_i_2__n.BLIF N_306 +.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_282 11 1 -.names N_180_i.BLIF N_292_i.BLIF N_302_0_1 +.names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n 11 1 -.names N_215_1.BLIF rst_dly_i_1__n.BLIF N_215 -11 1 -.names N_180_i.BLIF N_290_i.BLIF N_63_i_1 -11 1 -.names N_221_1.BLIF cpu_est_i_3__n.BLIF N_221 -11 1 -.names N_273_i.BLIF N_275_i.BLIF N_154_i_1 -11 1 -.names N_227_3.BLIF nEXP_SPACE_c.BLIF N_227 -11 1 -.names N_166.BLIF N_327_i.BLIF N_152_i_1 -11 1 -.names N_230_1.BLIF RST_c.BLIF N_230 -11 1 -.names N_155.BLIF N_270_i.BLIF N_148_i_1 -11 1 -.names N_169.BLIF RST_c.BLIF N_319 -11 1 -.names N_155.BLIF N_269_i.BLIF N_144_i_1 -11 1 -.names N_166_i.BLIF RST_c.BLIF N_320 -11 1 -.names N_267_i.BLIF N_324_i.BLIF N_140_i_1 -11 1 -.names N_183.BLIF sm_amiga_i_0__n.BLIF N_267 -11 1 -.names nEXP_SPACE_c.BLIF inst_AS_030_D0.BLIF pos_clk_un6_bg_030_1_n -11 1 -.names N_155_i.BLIF sm_amiga_i_1__n.BLIF N_324 -11 1 -.names N_305_i.BLIF N_350.BLIF N_230_1 -11 1 -.names N_196.BLIF sm_amiga_i_2__n.BLIF N_269 -11 1 -.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_221_1 -11 1 -.names N_197.BLIF sm_amiga_i_4__n.BLIF N_270 -11 1 -.names N_210_i.BLIF rst_dly_i_0__n.BLIF N_215_1 -11 1 -.names N_191.BLIF sm_amiga_i_6__n.BLIF N_327 -11 1 -.names N_163.BLIF N_210_i.BLIF N_306_1 -11 1 -.names N_171.BLIF sm_amiga_i_i_7__n.BLIF N_273 -11 1 -.names N_208_i.BLIF N_206_i.BLIF pos_clk_ipl_1_n -11 1 -.names N_155_i.BLIF SM_AMIGA_0_.BLIF N_275 -11 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_2__un3_n -0 1 -.names CLK_030_H_i.BLIF N_198.BLIF N_290 -11 1 -.names ipl_c_2__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_2__un1_n -11 1 -.names inst_CLK_030_H.BLIF CLK_030_c.BLIF N_292 -11 1 -.names IPL_030DFF_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n -11 1 -.names N_159.BLIF RST_DLY_0_.BLIF N_295 -11 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_1__un3_n -0 1 -.names N_186_i.BLIF rst_dly_i_0__n.BLIF N_332 -11 1 -.names ipl_c_1__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_1__un1_n -11 1 -.names BGACK_030_INT_i.BLIF N_184.BLIF N_333 -11 1 -.names IPL_030DFF_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n -11 1 -.names BGACK_030_INT_i.BLIF N_184_i.BLIF N_334 -11 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_0__un3_n -0 1 -.names N_194.BLIF sm_amiga_i_1__n.BLIF N_335 -11 1 -.names ipl_c_0__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_0__un1_n -11 1 -.names N_157_i.BLIF sm_amiga_i_2__n.BLIF N_336 -11 1 -.names IPL_030DFF_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n -11 1 -.names N_188.BLIF N_305_i.BLIF N_338 -11 1 -.names N_305.BLIF cpu_est_0_3__un3_n -0 1 -.names N_181.BLIF sm_amiga_i_3__n.BLIF N_339 -11 1 -.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c -0 1 -.names cpu_est_3_.BLIF N_305.BLIF cpu_est_0_3__un1_n -11 1 -.names N_163_i.BLIF RST_DLY_2_.BLIF N_350 -11 1 -.names N_192_i.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n +.names N_182.BLIF sm_amiga_i_2__n.BLIF N_284 11 1 .names pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un3_n 0 1 -.names N_161_i.BLIF N_161 -0 1 +.names N_149_i.BLIF N_176.BLIF N_340 +11 1 .names cpu_est_i_1__n.BLIF pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un1_n 11 1 -.names N_159.BLIF N_163_i.BLIF N_213 +.names N_171.BLIF sm_amiga_i_3__n.BLIF N_287 11 1 .names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n 11 1 -.names N_186_i.BLIF rst_dly_i_1__n.BLIF N_214 +.names N_183.BLIF sm_amiga_i_4__n.BLIF N_288 11 1 -.names VPA_c.BLIF VPA_c_i +.names N_149.BLIF cpu_est_0_1__un3_n 0 1 -.names N_305.BLIF cpu_est_0_1__un3_n -0 1 -.names N_197_0.BLIF N_197 -0 1 -.names RST_c.BLIF VPA_c_i.BLIF N_52_0 +.names N_163.BLIF sm_amiga_i_i_7__n.BLIF N_291 11 1 -.names cpu_est_1_.BLIF N_305.BLIF cpu_est_0_1__un1_n +.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c +0 1 +.names cpu_est_1_.BLIF N_149.BLIF cpu_est_0_1__un1_n +11 1 +.names N_150_i.BLIF SM_AMIGA_0_.BLIF N_293 11 1 -.names N_159_0.BLIF N_159 -0 1 -.names DTACK_c.BLIF DTACK_c_i -0 1 .names cpu_est_2_1__n.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n 11 1 -.names N_166.BLIF sm_amiga_i_5__n.BLIF N_326 +.names LDS_000_c.BLIF UDS_000_c.BLIF N_350 11 1 -.names DTACK_c_i.BLIF RST_c.BLIF N_53_0 -11 1 -.names N_305.BLIF cpu_est_0_2__un3_n +.names N_149.BLIF cpu_est_0_2__un3_n 0 1 -.names AS_030_i.BLIF BGACK_000_c.BLIF un21_berr_1 +.names N_158_i.BLIF RST_DLY_2_.BLIF N_355 11 1 -.names ipl_c_0__n.BLIF ipl_c_i_0__n -0 1 -.names cpu_est_2_.BLIF N_305.BLIF cpu_est_0_2__un1_n -11 1 -.names N_181_i.BLIF N_181 -0 1 -.names ipl_c_i_0__n.BLIF RST_c.BLIF N_49_0 +.names cpu_est_2_.BLIF N_149.BLIF cpu_est_0_2__un1_n 11 1 .names cpu_est_2_2__n.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n 11 1 -.names ipl_c_1__n.BLIF ipl_c_i_1__n +.names N_16.BLIF N_16_i 0 1 -.names N_302.BLIF ds_000_dma_0_un3_n +.names SM_AMIGA_6_.BLIF uds_000_int_0_un3_n 0 1 -.names un1_DS_000_ENABLE_0_sqmuxa_i.BLIF un1_DS_000_ENABLE_0_sqmuxa +.names N_16_i.BLIF RST_c.BLIF N_39_0 +11 1 +.names a_c_0__n.BLIF SM_AMIGA_6_.BLIF uds_000_int_0_un1_n +11 1 +.names VPA_c.BLIF VPA_c_i 0 1 -.names ipl_c_i_1__n.BLIF RST_c.BLIF N_50_0 +.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n 11 1 -.names N_301.BLIF N_302.BLIF ds_000_dma_0_un1_n +.names RST_c.BLIF VPA_c_i.BLIF N_52_0 11 1 -.names N_166_i.BLIF RW_c.BLIF N_349 -11 1 -.names ipl_c_2__n.BLIF ipl_c_i_2__n +.names SM_AMIGA_6_.BLIF lds_000_int_0_un3_n 0 1 -.names inst_DS_000_DMA.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n -11 1 -.names LDS_000_c.BLIF UDS_000_c.BLIF N_345 -11 1 -.names ipl_c_i_2__n.BLIF RST_c.BLIF N_51_0 -11 1 -.names N_303.BLIF as_000_dma_0_un3_n +.names N_156_i.BLIF N_156 0 1 -.names inst_RESET_OUT.BLIF RST_c.BLIF N_229 -11 1 -.names N_25.BLIF N_25_i +.names DTACK_c.BLIF DTACK_c_i 0 1 -.names N_180.BLIF N_303.BLIF as_000_dma_0_un1_n +.names pos_clk_un10_sm_amiga_i_n.BLIF SM_AMIGA_6_.BLIF lds_000_int_0_un1_n 11 1 -.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF N_14 -1- 1 --1 1 -.names N_25_i.BLIF RST_c.BLIF N_28_0 +.names N_154.BLIF N_158_i.BLIF N_201 11 1 -.names inst_AS_000_DMA.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n +.names DTACK_c_i.BLIF RST_c.BLIF N_53_0 11 1 -.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_21 -1- 1 --1 1 -.names N_26.BLIF N_26_i +.names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n +11 1 +.names N_82_i.BLIF rst_dly_i_1__n.BLIF N_202 +11 1 +.names N_210.BLIF N_210_i 0 1 .names pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n 0 1 -.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3 -1- 1 --1 1 -.names N_26_i.BLIF RST_c.BLIF N_29_0 -11 1 +.names N_154_0.BLIF N_154 +0 1 +.names N_211.BLIF N_211_i +0 1 .names BGACK_000_c.BLIF pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n 11 1 -.names N_301_0.BLIF N_301 -0 1 -.names N_27.BLIF N_27_i -0 1 +.names AS_030_i.BLIF BGACK_000_c.BLIF un21_berr_1 +11 1 +.names N_210_i.BLIF N_211_i.BLIF N_189_i +11 1 .names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \ bgack_030_int_0_un0_n 11 1 -.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF N_4 -1- 1 --1 1 -.names N_27_i.BLIF RST_c.BLIF N_30_0 +.names N_174_i.BLIF N_174 +0 1 +.names N_160.BLIF N_175_i.BLIF un1_SM_AMIGA_0_sqmuxa_1_0 11 1 -.names N_65.BLIF ds_000_enable_0_un3_n +.names N_66.BLIF ds_000_enable_0_un3_n 0 1 -.names N_303_0.BLIF N_303 +.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_223 +11 1 +.names RW_c.BLIF RW_c_i 0 1 -.names N_222.BLIF N_222_i +.names un1_DS_000_ENABLE_0_sqmuxa.BLIF N_66.BLIF ds_000_enable_0_un1_n +11 1 +.names N_133.BLIF RST_c.BLIF N_221 +11 1 +.names N_175_i.BLIF RW_c_i.BLIF N_311_0 +11 1 +.names inst_DS_000_ENABLE.BLIF ds_000_enable_0_un3_n.BLIF \ +ds_000_enable_0_un0_n +11 1 +.names N_160_i.BLIF RST_c.BLIF N_222 +11 1 +.names N_336.BLIF N_336_i 0 1 -.names un1_DS_000_ENABLE_0_sqmuxa.BLIF N_65.BLIF ds_000_enable_0_un1_n +.names N_126.BLIF size_dma_0_0__un3_n +0 1 +.names N_132.BLIF RST_c.BLIF N_219 +11 1 +.names N_244.BLIF N_244_i +0 1 +.names pos_clk_size_dma_6_0__n.BLIF N_126.BLIF size_dma_0_0__un1_n +11 1 +.names N_174_i.BLIF RST_c.BLIF N_220 +11 1 +.names SIZE_DMA_0_.BLIF size_dma_0_0__un3_n.BLIF size_dma_0_0__un0_n +11 1 +.names pos_clk_un6_bgack_000_0_n.BLIF pos_clk_un6_bgack_000_n +0 1 +.names cpu_est_3_.BLIF cpu_est_i_0__n.BLIF N_314_0 +11 1 +.names N_126.BLIF size_dma_0_1__un3_n +0 1 +.names AS_000_c.BLIF N_150_i.BLIF N_359 +11 1 +.names cpu_est_i_1__n.BLIF cpu_est_i_2__n.BLIF N_159_i +11 1 +.names pos_clk_size_dma_6_1__n.BLIF N_126.BLIF size_dma_0_1__un1_n 11 1 .names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF N_8 1- 1 -1 1 -.names N_223.BLIF N_223_i +.names inst_VMA_INTreg.BLIF VMA_INT_i 0 1 -.names inst_DS_000_ENABLE.BLIF ds_000_enable_0_un3_n.BLIF \ -ds_000_enable_0_un0_n +.names SIZE_DMA_1_.BLIF size_dma_0_1__un3_n.BLIF size_dma_0_1__un0_n 11 1 -.names pos_clk_un6_bgack_000_0_n.BLIF pos_clk_un6_bgack_000_n +.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF N_14 +1- 1 +-1 1 +.names N_352.BLIF N_352_i 0 1 -.names N_222_i.BLIF N_223_i.BLIF N_192_i +.names N_233.BLIF ipl_030_0_0__un3_n +0 1 +.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_21 +1- 1 +-1 1 +.names N_353.BLIF N_353_i +0 1 +.names IPL_030DFF_0_reg.BLIF N_233.BLIF ipl_030_0_0__un1_n 11 1 -.names SM_AMIGA_6_.BLIF uds_000_int_0_un3_n -0 1 .names ds_000_enable_0_un1_n.BLIF ds_000_enable_0_un0_n.BLIF N_9 1- 1 -1 1 -.names N_231.BLIF N_231_i +.names N_293.BLIF N_293_i 0 1 -.names a_c_0__n.BLIF SM_AMIGA_6_.BLIF uds_000_int_0_un1_n +.names ipl_c_0__n.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n 11 1 -.names N_65_0.BLIF N_65 +.names un1_DS_000_ENABLE_0_sqmuxa_0.BLIF un1_DS_000_ENABLE_0_sqmuxa 0 1 -.names N_237.BLIF N_237_i +.names N_293_i.BLIF SM_AMIGA_i_7_.BLIF N_175_i +11 1 +.names N_233.BLIF ipl_030_0_1__un3_n 0 1 -.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n -11 1 -.names CYCLE_DMA_0_.BLIF N_155_i.BLIF N_217 -11 1 -.names SM_AMIGA_6_.BLIF lds_000_int_0_un3_n +.names N_66_0.BLIF N_66 0 1 -.names cycle_dma_i_0__n.BLIF N_155.BLIF N_216 +.names N_176_i_1.BLIF N_353_i.BLIF N_176_i 11 1 -.names N_342.BLIF N_342_i +.names IPL_030DFF_1_reg.BLIF N_233.BLIF ipl_030_0_1__un1_n +11 1 +.names N_171_i.BLIF N_171 0 1 -.names pos_clk_un10_sm_amiga_i_n.BLIF SM_AMIGA_6_.BLIF lds_000_int_0_un1_n +.names ipl_c_1__n.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n 11 1 -.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_248 +.names N_160_i.BLIF RW_c.BLIF N_354 11 1 -.names N_341.BLIF N_341_i +.names N_198.BLIF N_198_i 0 1 -.names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n -11 1 -.names N_198_0.BLIF N_198 -0 1 -.names inst_BGACK_030_INTreg.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un3_n -0 1 -.names inst_AS_000_DMA.BLIF RW_000_i.BLIF N_291 -11 1 -.names cpu_est_3_.BLIF cpu_est_i_0__n.BLIF N_160_0 -11 1 -.names inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INTreg.BLIF \ -un1_amiga_bus_enable_dma_high_i_m2_0__un1_n -11 1 -.names AS_000_c.BLIF N_155_i.BLIF N_353 -11 1 -.names cpu_est_i_1__n.BLIF cpu_est_i_2__n.BLIF N_164_i -11 1 -.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ -un1_amiga_bus_enable_dma_high_i_m2_0__un3_n.BLIF \ -un1_amiga_bus_enable_dma_high_i_m2_0__un0_n -11 1 -.names N_256_1.BLIF N_256_2.BLIF N_256 -11 1 -.names inst_VMA_INTreg.BLIF VMA_INT_i -0 1 -.names N_199.BLIF amiga_bus_enable_dma_high_0_un3_n +.names N_233.BLIF ipl_030_0_2__un3_n 0 1 .names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF N_18 1- 1 -1 1 -.names N_347.BLIF N_347_i +.names N_197.BLIF N_197_i 0 1 -.names N_79_i.BLIF N_199.BLIF amiga_bus_enable_dma_high_0_un1_n +.names IPL_030DFF_2_reg.BLIF N_233.BLIF ipl_030_0_2__un1_n 11 1 .names pos_clk_un9_clk_000_pe_0_n.BLIF pos_clk_un9_clk_000_pe_n 0 1 -.names N_348.BLIF N_348_i +.names N_196.BLIF N_196_i 0 1 -.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ -amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n +.names ipl_c_2__n.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n 11 1 .names cpu_est_2_0_1__n.BLIF cpu_est_2_1__n 0 1 -.names N_188_i_1.BLIF N_348_i.BLIF N_188_i +.names N_149_i.BLIF SM_AMIGA_5_.BLIF N_183_0 11 1 -.names pos_clk_un9_bg_030_n.BLIF bg_000_0_un3_n +.names N_185.BLIF a0_dma_0_un3_n 0 1 .names cpu_est_2_0_2__n.BLIF cpu_est_2_2__n 0 1 -.names BGACK_030_INT_i.BLIF RST_c.BLIF N_245_0 +.names N_182_0_1.BLIF SM_AMIGA_3_.BLIF N_182_0 11 1 -.names BG_030_c.BLIF pos_clk_un9_bg_030_n.BLIF bg_000_0_un1_n +.names pos_clk_a0_dma_3_n.BLIF N_185.BLIF a0_dma_0_un1_n 11 1 -.names N_159.BLIF N_350.BLIF N_209 +.names N_154.BLIF N_355.BLIF N_197 11 1 -.names N_155_i.BLIF SM_AMIGA_2_.BLIF N_194_0 -11 1 -.names BG_000DFFreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n -11 1 -.names N_305.BLIF rst_dly_i_2__n.BLIF N_211 -11 1 -.names N_196_0_1.BLIF SM_AMIGA_3_.BLIF N_196_0 -11 1 -.names N_113.BLIF size_dma_0_0__un3_n -0 1 -.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_220 -11 1 -.names pos_clk_size_dma_6_0__n.BLIF N_113.BLIF size_dma_0_0__un1_n -11 1 -.names N_162.BLIF cpu_est_2_.BLIF N_222 -11 1 -.names N_211.BLIF N_211_i -0 1 -.names SIZE_DMA_0_.BLIF size_dma_0_0__un3_n.BLIF size_dma_0_0__un0_n -11 1 -.names N_162_i.BLIF N_162 -0 1 -.names N_209.BLIF N_209_i -0 1 -.names N_113.BLIF size_dma_0_1__un3_n -0 1 -.names N_193.BLIF cpu_est_i_2__n.BLIF N_224 -11 1 -.names N_306.BLIF N_306_i -0 1 -.names pos_clk_size_dma_6_1__n.BLIF N_113.BLIF size_dma_0_1__un1_n -11 1 -.names N_193_0.BLIF N_193 -0 1 -.names cpu_est_3_.BLIF cpu_est_i_1__n.BLIF N_193_0 -11 1 -.names SIZE_DMA_1_.BLIF size_dma_0_1__un3_n.BLIF size_dma_0_1__un0_n -11 1 -.names N_190.BLIF cpu_est_2_.BLIF N_225 -11 1 -.names cpu_est_1_.BLIF cpu_est_i_3__n.BLIF N_190_0 -11 1 -.names N_297.BLIF as_030_000_sync_0_un3_n -0 1 -.names N_190_0.BLIF N_190 -0 1 -.names N_157_i.BLIF SM_AMIGA_1_.BLIF N_183_i -11 1 -.names AS_030_c.BLIF N_297.BLIF as_030_000_sync_0_un1_n -11 1 -.names N_305_i.BLIF N_350_i_0.BLIF N_346 -11 1 -.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_162_i -11 1 -.names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF \ -as_030_000_sync_0_un0_n -11 1 -.names N_162_i.BLIF cpu_est_i_2__n.BLIF N_352 -11 1 -.names N_346.BLIF N_346_i -0 1 -.names un1_SM_AMIGA_0_sqmuxa_1.BLIF rw_000_int_0_un3_n -0 1 -.names N_219_1.BLIF N_219_2.BLIF N_219 -11 1 -.names N_346_i.BLIF RST_c.BLIF N_159_0 -11 1 -.names pos_clk_rw_000_int_5_n.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF \ -rw_000_int_0_un1_n -11 1 -.names N_218_1.BLIF N_218_2.BLIF N_218 -11 1 -.names CLK_000_D_1_.BLIF clk_000_d_i_0__n.BLIF N_305_i -11 1 -.names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n -11 1 -.names N_183_i.BLIF N_183 -0 1 -.names N_350_i_0.BLIF RST_c.BLIF N_210_i -11 1 -.names N_199.BLIF rw_000_dma_0_un3_n -0 1 -.names N_196_0.BLIF N_196 -0 1 -.names N_225.BLIF N_225_i -0 1 -.names N_300.BLIF N_199.BLIF rw_000_dma_0_un1_n -11 1 -.names N_188_i.BLIF N_188 -0 1 -.names N_224.BLIF N_224_i -0 1 -.names inst_RW_000_DMA.BLIF rw_000_dma_0_un3_n.BLIF rw_000_dma_0_un0_n -11 1 -.names N_194_0.BLIF N_194 -0 1 -.names N_224_i.BLIF N_225_i.BLIF N_296_i -11 1 -.names N_199.BLIF a0_dma_0_un3_n -0 1 -.names N_347_1.BLIF N_347_2.BLIF N_347 -11 1 -.names N_352.BLIF N_352_i -0 1 -.names pos_clk_a0_dma_3_n.BLIF N_199.BLIF a0_dma_0_un1_n -11 1 -.names DTACK_D0_i.BLIF inst_VPA_D.BLIF N_348 -11 1 -.names N_222_i.BLIF N_352_i.BLIF cpu_est_2_0_2__n +.names cpu_est_3_.BLIF cpu_est_i_1__n.BLIF N_180_0 11 1 .names inst_A0_DMA.BLIF a0_dma_0_un3_n.BLIF a0_dma_0_un0_n 11 1 -.names N_160_0.BLIF N_160 -0 1 -.names N_220.BLIF N_220_i -0 1 -.names N_199.BLIF amiga_bus_enable_dma_low_0_un3_n -0 1 -.names N_305.BLIF cpu_est_i_0__n.BLIF N_341 +.names N_149.BLIF rst_dly_i_2__n.BLIF N_198 11 1 -.names N_221.BLIF N_221_i +.names cpu_est_1_.BLIF cpu_est_i_3__n.BLIF N_178_0 +11 1 +.names N_185.BLIF amiga_bus_enable_dma_low_0_un3_n 0 1 -.names N_78_i.BLIF N_199.BLIF amiga_bus_enable_dma_low_0_un1_n +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_208 11 1 -.names N_305_i.BLIF cpu_est_0_.BLIF N_342 +.names N_149.BLIF RST_c.BLIF N_82_i 11 1 -.names N_220_i.BLIF N_221_i.BLIF cpu_est_2_0_1__n +.names N_114_i.BLIF N_185.BLIF amiga_bus_enable_dma_low_0_un1_n +11 1 +.names N_315.BLIF cpu_est_2_.BLIF N_210 +11 1 +.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_315_i 11 1 .names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF \ amiga_bus_enable_dma_low_0_un3_n.BLIF amiga_bus_enable_dma_low_0_un0_n 11 1 -.names N_183_i.BLIF RST_c.BLIF N_231 -11 1 -.names N_219.BLIF N_219_i +.names N_315_i.BLIF N_315 0 1 -.names N_165.BLIF RST_c.BLIF N_237 -11 1 -.names N_218.BLIF N_218_i +.names N_351.BLIF N_351_i 0 1 -.names N_160.BLIF cpu_est_i_2__n.BLIF N_223 -11 1 -.names N_218_i.BLIF N_219_i.BLIF pos_clk_un9_clk_000_pe_0_n -11 1 -.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_27 -1- 1 --1 1 -.names CLK_000_D_2_.BLIF clk_000_d_i_2__n +.names N_185.BLIF amiga_bus_enable_dma_high_0_un3_n 0 1 -.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF N_26 -1- 1 --1 1 -.names CLK_000_D_3_.BLIF clk_000_d_i_2__n.BLIF N_157_i +.names N_180.BLIF cpu_est_i_2__n.BLIF N_212 +11 1 +.names N_351_i.BLIF RST_c.BLIF N_154_0 +11 1 +.names N_115_i.BLIF N_185.BLIF amiga_bus_enable_dma_high_0_un1_n +11 1 +.names N_180_0.BLIF N_180 +0 1 +.names CLK_000_D_1_.BLIF clk_000_d_i_0__n.BLIF N_149_i +11 1 +.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ +amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n +11 1 +.names N_178.BLIF cpu_est_2_.BLIF N_213 +11 1 +.names N_355_i_0.BLIF RST_c.BLIF N_207_i +11 1 +.names pos_clk_un9_bg_030_n.BLIF bg_000_0_un3_n +0 1 +.names N_178_0.BLIF N_178 +0 1 +.names N_228.BLIF N_228_i +0 1 +.names BG_030_c.BLIF pos_clk_un9_bg_030_n.BLIF bg_000_0_un1_n +11 1 +.names N_160.BLIF sm_amiga_i_5__n.BLIF N_228 +11 1 +.names BG_000DFFreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n +11 1 +.names N_182_0.BLIF N_182 +0 1 +.names N_213.BLIF N_213_i +0 1 +.names N_246.BLIF ds_000_dma_0_un3_n +0 1 +.names N_176_i.BLIF N_176 +0 1 +.names N_212.BLIF N_212_i +0 1 +.names pos_clk_ds_000_dma_4_n.BLIF N_246.BLIF ds_000_dma_0_un1_n +11 1 +.names N_183_0.BLIF N_183 +0 1 +.names N_212_i.BLIF N_213_i.BLIF N_309_i +11 1 +.names inst_DS_000_DMA.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n +11 1 +.names N_149_i.BLIF N_355_i_0.BLIF N_351 +11 1 +.names N_357.BLIF N_357_i +0 1 +.names N_245.BLIF as_000_dma_0_un3_n +0 1 +.names N_315_i.BLIF cpu_est_i_2__n.BLIF N_357 +11 1 +.names N_210_i.BLIF N_357_i.BLIF cpu_est_2_0_2__n +11 1 +.names pos_clk_un21_bgack_030_int_i_0_n.BLIF N_245.BLIF as_000_dma_0_un1_n +11 1 +.names N_206_1.BLIF N_206_2.BLIF N_206 +11 1 +.names N_208.BLIF N_208_i +0 1 +.names inst_AS_000_DMA.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n +11 1 +.names N_205_1.BLIF N_205_2.BLIF N_205 +11 1 +.names N_209.BLIF N_209_i +0 1 +.names N_310.BLIF as_030_000_sync_0_un3_n +0 1 +.names N_352_1.BLIF N_352_2.BLIF N_352 +11 1 +.names N_208_i.BLIF N_209_i.BLIF cpu_est_2_0_1__n +11 1 +.names AS_030_c.BLIF N_310.BLIF as_030_000_sync_0_un1_n +11 1 +.names DTACK_D0_i.BLIF inst_VPA_D.BLIF N_353 +11 1 +.names N_206.BLIF N_206_i +0 1 +.names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF \ +as_030_000_sync_0_un0_n +11 1 +.names N_314_0.BLIF N_314 +0 1 +.names N_205.BLIF N_205_i +0 1 +.names N_185.BLIF rw_000_dma_0_un3_n +0 1 +.names N_149_i.BLIF cpu_est_0_.BLIF N_244 +11 1 +.names N_205_i.BLIF N_206_i.BLIF pos_clk_un9_clk_000_pe_0_n +11 1 +.names pos_clk_rw_000_dma_3_n.BLIF N_185.BLIF rw_000_dma_0_un1_n +11 1 +.names N_149.BLIF cpu_est_i_0__n.BLIF N_336 11 1 -.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF N_25 -1- 1 --1 1 .names N_18.BLIF N_18_i 0 1 -.names un1_amiga_bus_enable_low.BLIF un1_amiga_bus_enable_low_i +.names inst_RW_000_DMA.BLIF rw_000_dma_0_un3_n.BLIF rw_000_dma_0_un0_n +11 1 +.names N_311_0.BLIF N_311 0 1 .names N_18_i.BLIF RST_c.BLIF N_37_0 11 1 +.names un1_SM_AMIGA_0_sqmuxa_1_0.BLIF un1_SM_AMIGA_0_sqmuxa_1 +0 1 +.names N_150_i.BLIF SM_AMIGA_4_.BLIF N_171_i +11 1 +.names N_314.BLIF cpu_est_i_2__n.BLIF N_211 +11 1 +.names N_354.BLIF N_354_i +0 1 +.names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF N_16 +1- 1 +-1 1 +.names N_171.BLIF N_354_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_0 +11 1 +.names un1_amiga_bus_enable_low.BLIF un1_amiga_bus_enable_low_i +0 1 +.names AS_030_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_0.BLIF N_66_0 +11 1 .names un21_fpu_cs.BLIF un21_fpu_cs_i 0 1 -.names cpu_est_2_.BLIF cpu_est_i_2__n -0 1 -.names N_217.BLIF N_217_i -0 1 -.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n -0 1 -.names N_216.BLIF N_216_i -0 1 -.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n -0 1 -.names CLK_030_c.BLIF CLK_030_c_i -0 1 -.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n -0 1 -.names AS_000_DMA_i.BLIF CLK_030_c_i.BLIF N_198_0 -11 1 -.names cpu_est_0_.BLIF cpu_est_i_0__n -0 1 -.names N_155_i.BLIF SM_AMIGA_6_.BLIF N_166_i -11 1 -.names inst_VPA_D.BLIF VPA_D_i -0 1 -.names CLK_000_D_0_.BLIF clk_000_d_i_1__n.BLIF N_155_i -11 1 -.names inst_DTACK_D0.BLIF DTACK_D0_i -0 1 -.names CLK_030_c_i.BLIF N_180_i.BLIF N_303_0 -11 1 -.names AS_030_c.BLIF AS_030_i -0 1 -.names N_291.BLIF N_291_i -0 1 -.names inst_DSACK1_INT.BLIF DSACK1_INT_i -0 1 -.names N_180_i.BLIF N_291_i.BLIF N_301_0 -11 1 -.names cpu_est_3_.BLIF cpu_est_i_3__n -0 1 -.names N_256.BLIF N_256_i -0 1 -.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n -0 1 -.names N_248.BLIF N_248_i -0 1 -.names cpu_est_1_.BLIF cpu_est_i_1__n -0 1 -.names N_248_i.BLIF N_256_i.BLIF AMIGA_BUS_DATA_DIR_c_0 -11 1 -.names CLK_000_D_1_.BLIF clk_000_d_i_1__n -0 1 -.names N_353.BLIF N_353_i -0 1 -.names N_350.BLIF N_350_i_0 -0 1 -.names BGACK_000_c.BLIF N_353_i.BLIF pos_clk_un6_bgack_000_0_n -11 1 -.names RST_DLY_2_.BLIF rst_dly_i_2__n -0 1 -.names AS_030_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_i.BLIF N_65_0 -11 1 -.names nEXP_SPACE_c.BLIF nEXP_SPACE_i -0 1 -.names N_3.BLIF N_3_i -0 1 -.names AS_000_c.BLIF AS_000_i -0 1 -.names N_3_i.BLIF RST_c.BLIF N_45_0 -11 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i -0 1 -.names N_4.BLIF N_4_i -0 1 -.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n -0 1 -.names N_4_i.BLIF RST_c.BLIF N_44_0 -11 1 -.names CLK_000_D_0_.BLIF clk_000_d_i_0__n -0 1 -.names N_8.BLIF N_8_i -0 1 -.names RW_000_c.BLIF RW_000_i -0 1 -.names N_8_i.BLIF RST_c.BLIF N_42_0 -11 1 -.names inst_CLK_030_H.BLIF CLK_030_H_i -0 1 .names inst_UDS_000_INT.BLIF UDS_000_INT_i 0 1 -.names inst_AS_000_DMA.BLIF AS_000_DMA_i +.names cpu_est_2_.BLIF cpu_est_i_2__n 0 1 .names inst_DS_000_ENABLE.BLIF UDS_000_INT_i.BLIF un1_UDS_000_INT_0 11 1 -.names CYCLE_DMA_0_.BLIF cycle_dma_i_0__n +.names cpu_est_0_.BLIF cpu_est_i_0__n 0 1 .names inst_LDS_000_INT.BLIF LDS_000_INT_i 0 1 -.names inst_DS_000_DMA.BLIF DS_000_DMA_i +.names inst_VPA_D.BLIF VPA_D_i 0 1 .names inst_DS_000_ENABLE.BLIF LDS_000_INT_i.BLIF un1_LDS_000_INT_0 11 1 -.names inst_RESET_OUT.BLIF RESET_OUT_i +.names inst_DTACK_D0.BLIF DTACK_D0_i 0 1 .names N_21.BLIF N_21_i 0 1 -.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n +.names cpu_est_3_.BLIF cpu_est_i_3__n 0 1 .names N_21_i.BLIF RST_c.BLIF N_34_0 11 1 -.names FPU_SENSE_c.BLIF FPU_SENSE_i +.names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n 0 1 .names N_14.BLIF N_14_i 0 1 +.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +0 1 +.names N_14_i.BLIF RST_c.BLIF N_41_0 +11 1 +.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n +0 1 +.names N_8.BLIF N_8_i +0 1 +.names cpu_est_1_.BLIF cpu_est_i_1__n +0 1 +.names N_8_i.BLIF RST_c.BLIF N_42_0 +11 1 +.names CLK_000_D_1_.BLIF clk_000_d_i_1__n +0 1 +.names a_c_0__n.BLIF a_c_i_0__n +0 1 +.names N_355.BLIF N_355_i_0 +0 1 +.names size_c_1__n.BLIF size_c_i_1__n +0 1 +.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n +0 1 +.names pos_clk_un10_sm_amiga_i_1_n.BLIF size_c_i_1__n.BLIF \ +pos_clk_un10_sm_amiga_i_n +11 1 +.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n +0 1 +.names N_359.BLIF N_359_i +0 1 +.names RST_DLY_0_.BLIF rst_dly_i_0__n +0 1 +.names BGACK_000_c.BLIF N_359_i.BLIF pos_clk_un6_bgack_000_0_n +11 1 +.names RST_DLY_2_.BLIF rst_dly_i_2__n +0 1 +.names N_220.BLIF N_220_i +0 1 +.names a_decode_c_19__n.BLIF a_decode_i_19__n +0 1 +.names N_219.BLIF N_219_i +0 1 +.names a_decode_c_18__n.BLIF a_decode_i_18__n +0 1 +.names a_decode_c_16__n.BLIF a_decode_i_16__n +0 1 +.names N_222.BLIF N_222_i +0 1 +.names RW_000_c.BLIF RW_000_i +0 1 +.names N_221.BLIF N_221_i +0 1 +.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n +0 1 +.names AS_030_c.BLIF AS_030_i +0 1 +.names N_223.BLIF N_223_i +0 1 +.names inst_AS_000_INT.BLIF AS_000_INT_i +0 1 +.names N_224.BLIF N_224_i +0 1 +.names inst_DSACK1_INT.BLIF DSACK1_INT_i +0 1 +.names N_223_i.BLIF N_224_i.BLIF AMIGA_BUS_DATA_DIR_c_0 +11 1 +.names CLK_000_D_0_.BLIF clk_000_d_i_0__n +0 1 +.names CLK_000_D_0_.BLIF clk_000_d_i_1__n.BLIF N_150_i +11 1 +.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n +0 1 +.names N_156_i_4.BLIF N_156_i_3.BLIF N_156_i +11 1 +.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n +0 1 +.names N_150_i.BLIF SM_AMIGA_6_.BLIF N_160_i +11 1 +.names FPU_SENSE_c.BLIF FPU_SENSE_i +0 1 +.names N_149_i.BLIF SM_AMIGA_1_.BLIF N_174_i +11 1 +.names RST_DLY_1_.BLIF rst_dly_i_1__n +0 1 +.names RST_DLY_0_.BLIF RST_DLY_1_.BLIF N_158_i +11 1 +.names inst_AS_030_D0.BLIF AS_030_D0_i +0 1 +.names N_201.BLIF N_201_i +0 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i +0 1 +.names N_202.BLIF N_202_i +0 1 +.names nEXP_SPACE_c.BLIF nEXP_SPACE_i +0 1 +.names N_203.BLIF N_203_i +0 1 +.names inst_RESET_OUT.BLIF RESET_OUT_i +0 1 .names IPL_030DFF_2_reg.BLIF IPL_030_2_ 1 1 0 0 @@ -1512,13 +1508,13 @@ amiga_bus_enable_dma_low_0_un3_n.BLIF amiga_bus_enable_dma_low_0_un0_n .names un21_fpu_cs_i.BLIF FPU_CS 1 1 0 0 -.names N_165_i.BLIF DSACK1 +.names N_132_i.BLIF DSACK1 1 1 0 0 .names vcc_n_n.BLIF AVEC 1 1 0 0 -.names N_296_i.BLIF E +.names N_309_i.BLIF E 1 1 0 0 .names inst_VMA_INTreg.BLIF VMA @@ -1536,7 +1532,7 @@ amiga_bus_enable_dma_low_0_un3_n.BLIF amiga_bus_enable_dma_low_0_un0_n .names un1_amiga_bus_enable_low_i.BLIF AMIGA_BUS_ENABLE_LOW 1 1 0 0 -.names N_205.BLIF AMIGA_BUS_ENABLE_HIGH +.names un10_amiga_bus_enable_high_i.BLIF AMIGA_BUS_ENABLE_HIGH 1 1 0 0 .names un10_ciin.BLIF CIIN @@ -1548,6 +1544,15 @@ amiga_bus_enable_dma_low_0_un3_n.BLIF amiga_bus_enable_dma_low_0_un0_n .names IPL_030DFF_0_reg.BLIF IPL_030_0_ 1 1 0 0 +.names CLK_OSZI_c.BLIF IPL_D0_0_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF IPL_D0_1_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF IPL_D0_2_.C +1 1 +0 0 .names CLK_OSZI_c.BLIF SM_AMIGA_i_7_.C 1 1 0 0 @@ -1572,6 +1577,15 @@ amiga_bus_enable_dma_low_0_un3_n.BLIF amiga_bus_enable_dma_low_0_un0_n .names CLK_OSZI_c.BLIF SM_AMIGA_0_.C 1 1 0 0 +.names CLK_OSZI_c.BLIF cpu_est_0_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF cpu_est_1_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF cpu_est_2_.C +1 1 +0 0 .names CLK_OSZI_c.BLIF cpu_est_3_.C 1 1 0 0 @@ -1584,13 +1598,7 @@ amiga_bus_enable_dma_low_0_un3_n.BLIF amiga_bus_enable_dma_low_0_un0_n .names CLK_OSZI_c.BLIF IPL_030DFF_2_reg.C 1 1 0 0 -.names CLK_OSZI_c.BLIF IPL_D0_0_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF IPL_D0_1_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF IPL_D0_2_.C +.names CLK_OSZI_c.BLIF RST_DLY_2_.C 1 1 0 0 .names CLK_000.BLIF CLK_000_D_0_.D @@ -1623,12 +1631,6 @@ amiga_bus_enable_dma_low_0_un3_n.BLIF amiga_bus_enable_dma_low_0_un0_n .names CLK_OSZI_c.BLIF CLK_000_D_4_.C 1 1 0 0 -.names CLK_000_D_4_.BLIF CLK_000_D_5_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_D_5_.C -1 1 -0 0 .names CLK_OSZI_c.BLIF CYCLE_DMA_0_.C 1 1 0 0 @@ -1641,22 +1643,25 @@ amiga_bus_enable_dma_low_0_un3_n.BLIF amiga_bus_enable_dma_low_0_un0_n .names CLK_OSZI_c.BLIF SIZE_DMA_1_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF cpu_est_0_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF cpu_est_1_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF cpu_est_2_.C -1 1 -0 0 .names CLK_OSZI_c.BLIF RST_DLY_0_.C 1 1 0 0 .names CLK_OSZI_c.BLIF RST_DLY_1_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF RST_DLY_2_.C +.names CLK_OSZI_c.BLIF inst_RW_000_INT.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C 1 1 0 0 .names CLK_OSZI_c.BLIF inst_DS_000_DMA.C @@ -1707,21 +1712,6 @@ amiga_bus_enable_dma_low_0_un3_n.BLIF amiga_bus_enable_dma_low_0_un0_n .names CLK_OSZI_c.BLIF inst_VMA_INTreg.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_RW_000_INT.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C -1 1 -0 0 .names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C 1 1 0 0 @@ -1749,7 +1739,7 @@ amiga_bus_enable_dma_low_0_un3_n.BLIF amiga_bus_enable_dma_low_0_un0_n .names un7_as_030_i.BLIF AS_030 1 1 0 0 -.names N_169_i.BLIF AS_000 +.names N_133_i.BLIF AS_000 1 1 0 0 .names inst_RW_000_INT.BLIF RW_000 @@ -1959,7 +1949,7 @@ amiga_bus_enable_dma_low_0_un3_n.BLIF amiga_bus_enable_dma_low_0_un0_n .names A_DECODE_2_.BLIF a_decode_2__n 1 1 0 0 -.names N_139.BLIF AS_030.OE +.names N_313_i.BLIF AS_030.OE 1 1 0 0 .names un1_as_000_i.BLIF AS_000.OE @@ -1974,46 +1964,46 @@ amiga_bus_enable_dma_low_0_un3_n.BLIF amiga_bus_enable_dma_low_0_un0_n .names un1_as_000_i.BLIF LDS_000.OE 1 1 0 0 -.names N_299_i.BLIF SIZE_0_.OE +.names N_186_i.BLIF SIZE_0_.OE 1 1 0 0 -.names N_299_i.BLIF SIZE_1_.OE +.names N_186_i.BLIF SIZE_1_.OE 1 1 0 0 -.names N_139.BLIF AHIGH_24_.OE +.names N_313_i.BLIF AHIGH_24_.OE 1 1 0 0 -.names N_139.BLIF AHIGH_25_.OE +.names N_313_i.BLIF AHIGH_25_.OE 1 1 0 0 -.names N_139.BLIF AHIGH_26_.OE +.names N_313_i.BLIF AHIGH_26_.OE 1 1 0 0 -.names N_139.BLIF AHIGH_27_.OE +.names N_313_i.BLIF AHIGH_27_.OE 1 1 0 0 -.names N_139.BLIF AHIGH_28_.OE +.names N_313_i.BLIF AHIGH_28_.OE 1 1 0 0 -.names N_139.BLIF AHIGH_29_.OE +.names N_313_i.BLIF AHIGH_29_.OE 1 1 0 0 -.names N_139.BLIF AHIGH_30_.OE +.names N_313_i.BLIF AHIGH_30_.OE 1 1 0 0 -.names N_139.BLIF AHIGH_31_.OE +.names N_313_i.BLIF AHIGH_31_.OE 1 1 0 0 -.names N_139.BLIF A_0_.OE +.names N_313_i.BLIF A_0_.OE 1 1 0 0 .names un21_berr.BLIF BERR.OE 1 1 0 0 -.names N_141.BLIF RW.OE +.names un1_rw_i.BLIF RW.OE 1 1 0 0 -.names N_139.BLIF DS_030.OE +.names N_313_i.BLIF DS_030.OE 1 1 0 0 .names nEXP_SPACE_c.BLIF DSACK1.OE @@ -2022,31 +2012,31 @@ amiga_bus_enable_dma_low_0_un3_n.BLIF amiga_bus_enable_dma_low_0_un0_n .names RESET_OUT_i.BLIF RESET.OE 1 1 0 0 -.names N_260.BLIF CIIN.OE +.names N_62.BLIF CIIN.OE 1 1 0 0 -.names IPL_D0_0_.BLIF ipl_c_0__n.BLIF G_107 -01 1 -10 1 -11 0 -00 0 -.names IPL_D0_1_.BLIF ipl_c_1__n.BLIF G_108 -01 1 -10 1 -11 0 -00 0 -.names IPL_D0_2_.BLIF ipl_c_2__n.BLIF G_109 -01 1 -10 1 -11 0 -00 0 -.names CYCLE_DMA_1_.BLIF N_217.BLIF pos_clk_CYCLE_DMA_5_1_i_x2 -01 1 -10 1 -11 0 -00 0 .names CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF \ -pos_clk_un21_bgack_030_int_i_i_a2_i_x2 +pos_clk_un21_bgack_030_int_i_0_o3_0_x2 +01 1 +10 1 +11 0 +00 0 +.names IPL_D0_0_.BLIF ipl_c_0__n.BLIF pos_clk_un1_ipl_i_0_x2 +01 1 +10 1 +11 0 +00 0 +.names IPL_D0_1_.BLIF ipl_c_1__n.BLIF pos_clk_un1_ipl_i_0_x2_0 +01 1 +10 1 +11 0 +00 0 +.names IPL_D0_2_.BLIF ipl_c_2__n.BLIF pos_clk_un1_ipl_i_0_x2_1 +01 1 +10 1 +11 0 +00 0 +.names CYCLE_DMA_1_.BLIF N_199.BLIF pos_clk_CYCLE_DMA_5_1_i_0_x2 01 1 10 1 11 0 diff --git a/Logic/BUS68030.edi b/Logic/BUS68030.edi index b7bcb4b..778db70 100644 --- a/Logic/BUS68030.edi +++ b/Logic/BUS68030.edi @@ -4,7 +4,7 @@ (keywordMap (keywordLevel 0)) (status (written - (timeStamp 2016 10 6 22 4 6) + (timeStamp 2016 10 15 23 48 19) (author "Synopsys, Inc.") (program "Synplify Pro" (version "I-2014.03LC , mapper maplat, Build 923R")) ) @@ -140,6 +140,12 @@ (port CIIN (direction OUTPUT)) ) (contents + (instance (rename IPL_D0_0 "IPL_D0[0]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename IPL_D0_1 "IPL_D0[1]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename IPL_D0_2 "IPL_D0[2]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) (instance (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance (rename SM_AMIGA_6 "SM_AMIGA[6]") (viewRef prim (cellRef DFF (libraryRef mach))) @@ -156,6 +162,12 @@ ) (instance (rename SM_AMIGA_0 "SM_AMIGA[0]") (viewRef prim (cellRef DFF (libraryRef mach))) ) + (instance (rename cpu_est_0 "cpu_est[0]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename cpu_est_1 "cpu_est[1]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename cpu_est_2 "cpu_est[2]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) (instance (rename cpu_est_3 "cpu_est[3]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance (rename IPL_030DFF_0 "IPL_030DFF[0]") (viewRef prim (cellRef DFF (libraryRef mach))) @@ -164,11 +176,7 @@ ) (instance (rename IPL_030DFF_2 "IPL_030DFF[2]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance (rename IPL_D0_0 "IPL_D0[0]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename IPL_D0_1 "IPL_D0[1]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename IPL_D0_2 "IPL_D0[2]") (viewRef prim (cellRef DFF (libraryRef mach))) + (instance (rename RST_DLY_2 "RST_DLY[2]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance (rename CLK_000_D_0 "CLK_000_D[0]") (viewRef prim (cellRef DFF (libraryRef mach))) ) @@ -180,8 +188,6 @@ ) (instance (rename CLK_000_D_4 "CLK_000_D[4]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance (rename CLK_000_D_5 "CLK_000_D[5]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) (instance (rename CYCLE_DMA_0 "CYCLE_DMA[0]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance (rename CYCLE_DMA_1 "CYCLE_DMA[1]") (viewRef prim (cellRef DFF (libraryRef mach))) @@ -190,17 +196,19 @@ ) (instance (rename SIZE_DMA_1 "SIZE_DMA[1]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance (rename cpu_est_0 "cpu_est[0]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename cpu_est_1 "cpu_est[1]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename cpu_est_2 "cpu_est[2]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) (instance (rename RST_DLY_0 "RST_DLY[0]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance (rename RST_DLY_1 "RST_DLY[1]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance (rename RST_DLY_2 "RST_DLY[2]") (viewRef prim (cellRef DFF (libraryRef mach))) + (instance RW_000_INT (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance AS_030_000_SYNC (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance LDS_000_INT (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance BGACK_030_INT (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance AS_000_DMA (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance DS_000_DMA (viewRef prim (cellRef DFF (libraryRef mach))) ) @@ -234,16 +242,6 @@ ) (instance VMA_INT (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance RW_000_INT (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance AS_030_000_SYNC (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance LDS_000_INT (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance BGACK_030_INT (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance AS_000_DMA (viewRef prim (cellRef DFF (libraryRef mach))) - ) (instance BGACK_030_INT_D (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance CLK_OUT_INT (viewRef prim (cellRef DFF (libraryRef mach))) @@ -327,339 +325,318 @@ (instance AMIGA_BUS_ENABLE_LOW (viewRef prim (cellRef OBUF (libraryRef mach))) ) (instance AMIGA_BUS_ENABLE_HIGH (viewRef prim (cellRef OBUF (libraryRef mach))) ) (instance CIIN (viewRef prim (cellRef BUFTH (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_2 "SM_AMIGA_srsts_i_0_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_1_0 "SM_AMIGA_srsts_i_0_0_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_0 "SM_AMIGA_srsts_i_0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un6_bg_030_0_a2_0_a2_1 "pos_clk.un6_bg_030_0_a2_0_a2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un6_bg_030_0_a2_0_a2 "pos_clk.un6_bg_030_0_a2_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RESET_OUT_2_i_i_a2_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RESET_OUT_2_i_i_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_a2_0_1_1 "cpu_est_2_0_0_a2_0_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_a2_0_1 "cpu_est_2_0_0_a2_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e1_i_0_a2_1_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e1_i_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e2_i_0_a2_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e2_i_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance G_110_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance G_110 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_1_1 "SM_AMIGA_srsts_i_0_0_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_1 "SM_AMIGA_srsts_i_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e0_i_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e0_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DS_000_DMA_2_sqmuxa_0_a2_i_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DS_000_DMA_2_sqmuxa_0_a2_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_030_H_2_0_a2_i_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_030_H_2_0_a2_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0_1_0 "SM_AMIGA_nss_i_i_0_0_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e2_i_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_030_H_2_i_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_030_H_2_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_1_i_0_1 "pos_clk.CYCLE_DMA_5_1_i_0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_1_i_0 "pos_clk.CYCLE_DMA_5_1_i_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_OUT_2_0_0_a3_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_OUT_2_0_0_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_iv_0_0_a3_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_iv_0_0_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un10_amiga_bus_enable_high_0_0_a3_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un10_amiga_bus_enable_high_0_0_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_a3_1_1_1 "cpu_est_2_0_0_a3_1_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_a3_1_1 "cpu_est_2_0_0_a3_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e1_i_0_a3_1_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e1_i_0_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e2_i_0_a3_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_nss_i_i_0_0_0 "SM_AMIGA_nss_i_i_0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_1_6 "SM_AMIGA_srsts_i_0_0_1[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_6 "SM_AMIGA_srsts_i_0_0[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_srsts_i_0_0_1_4 "SM_AMIGA_srsts_i_0_0_1[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_srsts_i_0_0_4 "SM_AMIGA_srsts_i_0_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_1_2 "SM_AMIGA_srsts_i_0_0_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e2_i_0_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e2_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un9_clk_000_pe_0_0_a2_0_1 "pos_clk.un9_clk_000_pe_0_0_a2_0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un9_clk_000_pe_0_0_a2_0_2 "pos_clk.un9_clk_000_pe_0_0_a2_0_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un9_clk_000_pe_0_0_a2_0 "pos_clk.un9_clk_000_pe_0_0_a2_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un9_clk_000_pe_0_0_a2_1 "pos_clk.un9_clk_000_pe_0_0_a2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un9_clk_000_pe_0_0_a2_2 "pos_clk.un9_clk_000_pe_0_0_a2_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un9_clk_000_pe_0_0_a2 "pos_clk.un9_clk_000_pe_0_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a2_1_1_3 "SM_AMIGA_srsts_i_0_0_a2_1_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a2_1_2_3 "SM_AMIGA_srsts_i_0_0_a2_1_2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a2_1_3 "SM_AMIGA_srsts_i_0_0_a2_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_CYCLE_DMA_5_1_i_1 "pos_clk.CYCLE_DMA_5_1_i_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_CYCLE_DMA_5_1_i "pos_clk.CYCLE_DMA_5_1_i") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_srsts_i_0_0_1_3 "SM_AMIGA_srsts_i_0_0_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_srsts_i_0_0_3 "SM_AMIGA_srsts_i_0_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un34_as_030_d0_i_i_a2_1 "pos_clk.un34_as_030_d0_i_i_a2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un34_as_030_d0_i_i_a2_2 "pos_clk.un34_as_030_d0_i_i_a2_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un34_as_030_d0_i_i_a2_3 "pos_clk.un34_as_030_d0_i_i_a2_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un34_as_030_d0_i_i_a2 "pos_clk.un34_as_030_d0_i_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un21_fpu_cs_0_a2_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un21_fpu_cs_0_a2_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un21_berr_0_a2_0_a2_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un21_berr_0_a2_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_CYCLE_DMA_5_0_i_0_1 "pos_clk.CYCLE_DMA_5_0_i_0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_i_i_1_2 "SM_AMIGA_srsts_i_i_i_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_i_i_2 "SM_AMIGA_srsts_i_i_i[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e0_i_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e0_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_1_6 "SM_AMIGA_srsts_i_0_0_1[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_6 "SM_AMIGA_srsts_i_0_0[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_1_0 "SM_AMIGA_srsts_i_0_0_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_0 "SM_AMIGA_srsts_i_0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DS_000_DMA_2_sqmuxa_i_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DS_000_DMA_2_sqmuxa_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e2_i_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e2_i_0_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e2_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_pe_0_0_a3_0_1 "pos_clk.un9_clk_000_pe_0_0_a3_0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_pe_0_0_a3_0_2 "pos_clk.un9_clk_000_pe_0_0_a3_0_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_pe_0_0_a3_0 "pos_clk.un9_clk_000_pe_0_0_a3_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_pe_0_0_a3_1 "pos_clk.un9_clk_000_pe_0_0_a3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_pe_0_0_a3_2 "pos_clk.un9_clk_000_pe_0_0_a3_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_pe_0_0_a3 "pos_clk.un9_clk_000_pe_0_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_a2_1_3 "SM_AMIGA_srsts_i_0_0_a2_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_a2_2_3 "SM_AMIGA_srsts_i_0_0_a2_2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_a2_3 "SM_AMIGA_srsts_i_0_0_a2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un6_bg_030_i_0_1 "pos_clk.un6_bg_030_i_0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un6_bg_030_i_0 "pos_clk.un6_bg_030_i_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_0_1_0 "SM_AMIGA_nss_i_i_0_0_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename pos_clk_CYCLE_DMA_5_0_i_0_2 "pos_clk.CYCLE_DMA_5_0_i_0_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename pos_clk_CYCLE_DMA_5_0_i_0 "pos_clk.CYCLE_DMA_5_0_i_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_iv_0_0_a2_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_iv_0_0_a2_0_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_iv_0_0_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e2_i_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un13_ciin_i_0_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un13_ciin_i_0_0_a2_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un13_ciin_i_0_0_a2_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un13_ciin_i_0_0_a2_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un13_ciin_i_0_0_a2_5 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un13_ciin_i_0_0_a2_6 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un13_ciin_i_0_0_a2_7 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un13_ciin_i_0_0_a2_8 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un13_ciin_i_0_0_a2_9 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un13_ciin_i_0_0_a2_10 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un13_ciin_i_0_0_a2_11 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un13_ciin_i_0_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un1_ipl_i_0_1 "pos_clk.un1_ipl_i_0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un1_ipl_i_0_2 "pos_clk.un1_ipl_i_0_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un1_ipl_i_0 "pos_clk.un1_ipl_i_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d0_i_i_a3_1 "pos_clk.un34_as_030_d0_i_i_a3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d0_i_i_a3_2 "pos_clk.un34_as_030_d0_i_i_a3_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d0_i_i_a3_3 "pos_clk.un34_as_030_d0_i_i_a3_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d0_i_i_a3 "pos_clk.un34_as_030_d0_i_i_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un21_fpu_cs_0_a3_0_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un21_fpu_cs_0_a3_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un21_berr_0_a3_0_a3_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un21_berr_0_a3_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_i_i_o2_1_2 "SM_AMIGA_srsts_i_i_i_o2_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_i_i_o2_2 "SM_AMIGA_srsts_i_i_i_o2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un13_ciin_i_0_0_a3_8 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un13_ciin_i_0_0_a3_9 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un13_ciin_i_0_0_a3_10 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un13_ciin_i_0_0_a3_11 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un13_ciin_i_0_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_nss_i_i_0_0_o2_1_0 "SM_AMIGA_nss_i_i_0_0_o2_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_nss_i_i_0_0_o2_2_0 "SM_AMIGA_nss_i_i_0_0_o2_2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_nss_i_i_0_0_o2_0 "SM_AMIGA_nss_i_i_0_0_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un21_bgack_030_int_i_0_o3_0_o3_1 "pos_clk.un21_bgack_030_int_i_0_o3_0_o3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un21_bgack_030_int_i_0_o3_0_o3_2 "pos_clk.un21_bgack_030_int_i_0_o3_0_o3_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un21_bgack_030_int_i_0_o3_0_o3 "pos_clk.un21_bgack_030_int_i_0_o3_0_o3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_1_1 "SM_AMIGA_srsts_i_0_0_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_2_1 "SM_AMIGA_srsts_i_0_0_2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_1 "SM_AMIGA_srsts_i_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_0_i_0_1 "pos_clk.CYCLE_DMA_5_0_i_0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d0_i_i_o2_2 "pos_clk.un34_as_030_d0_i_i_o2_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename pos_clk_un34_as_030_d0_i_i_o2_3 "pos_clk.un34_as_030_d0_i_i_o2_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename pos_clk_un34_as_030_d0_i_i_o2_4 "pos_clk.un34_as_030_d0_i_i_o2_4") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename pos_clk_un34_as_030_d0_i_i_o2 "pos_clk.un34_as_030_d0_i_i_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e1_i_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e1_i_0_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e1_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un21_bgack_030_int_i_i_a2_i_o2_1 "pos_clk.un21_bgack_030_int_i_i_a2_i_o2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un21_bgack_030_int_i_i_a2_i_o2_2 "pos_clk.un21_bgack_030_int_i_i_a2_i_o2_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un21_bgack_030_int_i_i_a2_i_o2 "pos_clk.un21_bgack_030_int_i_i_a2_i_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename pos_clk_un10_sm_amiga_1 "pos_clk.un10_sm_amiga_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename pos_clk_un10_sm_amiga "pos_clk.un10_sm_amiga") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_1_2 "SM_AMIGA_srsts_i_0_0_o2_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_2 "SM_AMIGA_srsts_i_0_0_o2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_srsts_i_0_0_o2_0_1_3 "SM_AMIGA_srsts_i_0_0_o2_0_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_srsts_i_0_0_o2_0_3 "SM_AMIGA_srsts_i_0_0_o2_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance N_19_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un13_ciin_i_0_0_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un13_ciin_i_0_0_a3_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un13_ciin_i_0_0_a3_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un13_ciin_i_0_0_a3_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un13_ciin_i_0_0_a3_5 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un13_ciin_i_0_0_a3_6 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un13_ciin_i_0_0_a3_7 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance RW_000_DMA_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_20_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance A0_DMA_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_22_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_25_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance AMIGA_BUS_ENABLE_DMA_LOW_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_23_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_26_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance AMIGA_BUS_ENABLE_DMA_HIGH_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_24_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_27_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance BG_000_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance BG_030_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un6_bg_030_i "pos_clk.un6_bg_030_i") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename pos_clk_un9_bg_030_i "pos_clk.un9_bg_030_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RST_DLY_e1_i_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e1_i_0_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e1_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename pos_clk_un34_as_030_d0_i_i_o2_1 "pos_clk.un34_as_030_d0_i_i_o2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un34_as_030_d0_i_i_o2_2 "pos_clk.un34_as_030_d0_i_i_o2_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance N_270_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_269_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_267_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_324_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_SM_AMIGA_0_sqmuxa_1_0_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_319_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_320_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RW_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_RW_000_INT_5_0_0_i "pos_clk.RW_000_INT_5_0_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_227_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un34_as_030_d0_i_i_i "pos_clk.un34_as_030_d0_i_i_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_15_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_030_000_SYNC_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_16_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RW_000_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_339_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_335_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_336_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_334_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_0_i_1 "pos_clk.SIZE_DMA_6_0_0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_333_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_0_i_0 "pos_clk.SIZE_DMA_6_0_0_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_295_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_332_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_292_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DS_000_DMA_2_sqmuxa_0_a2_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_RW_000_DMA_3_i_a2_i_i "pos_clk.RW_000_DMA_3_i_a2_i_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_290_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_273_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_327_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_213_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_214_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_215_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un5_bgack_030_int_d_i_0_a2_i_o2_i "pos_clk.un5_bgack_030_int_d_i_0_a2_i_o2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_i_6 "SM_AMIGA_srsts_i_0_0_o2_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_275_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance LDS_000_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance UDS_000_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_0_o2_i_0 "pos_clk.SIZE_DMA_6_0_0_0_o2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename CLK_000_D_i_4 "CLK_000_D_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0_o2_i_0 "SM_AMIGA_nss_i_i_0_0_o2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_030_000_SYNC_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un34_as_030_d0_i_i_o2_i "pos_clk.un34_as_030_d0_i_i_o2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance SIZE_DMA_3_sqmuxa_0_a2_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_338_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SIZE_c_i_1 "SIZE_c_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un10_ciin_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un13_ciin_i_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_229_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_230_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RESET_OUT_2_i_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_030_D0_0_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_345_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_349_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_DS_000_ENABLE_0_sqmuxa_0_o2_0_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un21_bgack_030_int_i_i_a2_i_o2_i "pos_clk.un21_bgack_030_int_i_i_a2_i_o2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_i_3 "SM_AMIGA_srsts_i_0_0_o2_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_326_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RST_DLY_e2_i_0_o2_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_i_4 "SM_AMIGA_srsts_i_0_0_o2_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d0_i_i_i "pos_clk.un34_as_030_d0_i_i_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_24_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_1_i_2 "IPL_030_1_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_23_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_1_i_1 "IPL_030_1_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_22_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_1_i_0 "IPL_030_1_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_3_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance DS_000_DMA_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_4_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance AS_000_DMA_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_8_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance BGACK_030_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance UDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_UDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance LDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_LDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_15_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_030_000_SYNC_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_19_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RESET_OUT_2_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_000_DMA_1_sqmuxa_i_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_229_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_227_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_226_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DS_000_DMA_2_sqmuxa_i_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_332_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_DS_000_DMA_4_f0_0_0_i "pos_clk.DS_000_DMA_4_f0_0_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_030_D0_0_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_RW_000_DMA_3_0_0_i "pos_clk.RW_000_DMA_3_0_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_218_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un10_ciin_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un13_ciin_i_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_215_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_216_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance SIZE_DMA_3_sqmuxa_0_a3_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un6_bg_030_i_0_i "pos_clk.un6_bg_030_i_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_291_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_288_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_287_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_340_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_284_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_275_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_0_i_1 "pos_clk.SIZE_DMA_6_0_0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_268_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_0_i_0 "pos_clk.SIZE_DMA_6_0_0_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_265_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_267_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_337_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_338_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_204_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_282_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_278_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un5_bgack_030_int_d_i_0_a2_i_o3_i "pos_clk.un5_bgack_030_int_d_i_0_a2_i_o3_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_030_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_030_H_2_i_0_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_o2_i_6 "SM_AMIGA_srsts_i_0_0_o2_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_0_i_0_o3_i "pos_clk.CYCLE_DMA_5_0_i_0_o3_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance LDS_000_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance UDS_000_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_0_o2_i_0 "pos_clk.SIZE_DMA_6_0_0_0_o2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un21_bgack_030_int_i_0_o3_0_o3_i "pos_clk.un21_bgack_030_int_i_0_o3_0_o3_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_0_o2_i_0 "SM_AMIGA_nss_i_i_0_0_o2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename CLK_000_D_i_3 "CLK_000_D_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_350_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_224_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_iv_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un1_ipl_i_0_o3_i "pos_clk.un1_ipl_i_0_o3_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d0_i_i_o2_i "pos_clk.un34_as_030_d0_i_i_o2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_SM_AMIGA_0_sqmuxa_1_0_1_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_o2_i_0 "SM_AMIGA_srsts_i_0_0_o2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RST_DLY_e2_i_0_o2_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_201_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_202_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_203_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un1_ipl_i_0_i "pos_clk.un1_ipl_i_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_360_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_191_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_192_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_199_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_21_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance UDS_000_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_14_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance LDS_000_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_8_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance BGACK_030_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename A_c_i_0 "A_c_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_217_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_216_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance CLK_030_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance CLK_030_H_2_0_a2_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_SM_AMIGA_0_sqmuxa_1_0_1_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_261_i_0_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_000_DMA_1_sqmuxa_0_a2_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_291_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_DS_000_DMA_4_f0_i_a2_i_i "pos_clk.DS_000_DMA_4_f0_i_a2_i_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_256_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_248_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_iv_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_353_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SIZE_c_i_1 "SIZE_c_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_359_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename pos_clk_un6_bgack_000_0_0_i "pos_clk.un6_bgack_000_0_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DS_000_ENABLE_1_sqmuxa_i_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RST_DLY_e2_i_0_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance CLK_000_NE_0_o3_i_a2_0_o2_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_225_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_224_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_352_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_0_i_2 "cpu_est_2_0_0_0_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_220_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_221_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_0_i_1 "cpu_est_2_0_0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_219_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_218_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_222_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_221_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_223_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_209_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_0_i_1 "cpu_est_2_0_0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_206_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_205_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename pos_clk_un9_clk_000_pe_0_0_i "pos_clk.un9_clk_000_pe_0_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename CLK_000_D_i_2 "CLK_000_D_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_18_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance VMA_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance VMA_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_347_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_348_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_0_i_3 "SM_AMIGA_srsts_i_0_0_o2_0_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_CYCLE_DMA_5_0_i_0_o2_i "pos_clk.CYCLE_DMA_5_0_i_0_o2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_i_1 "SM_AMIGA_srsts_i_0_0_o2_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_i_2 "SM_AMIGA_srsts_i_0_0_o2_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_211_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_209_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_306_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_o2_i_3 "SM_AMIGA_srsts_i_0_0_o2_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_354_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_DS_000_ENABLE_0_sqmuxa_0_o3_0_o3_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DS_000_ENABLE_1_sqmuxa_i_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance UDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_UDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance LDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_LDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_196_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_o2_i_4 "SM_AMIGA_srsts_i_0_0_o2_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_i_i_o2_i_2 "SM_AMIGA_srsts_i_i_i_o2_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance un5_e_0_i_o2_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance un5_e_0_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_i_0 "SM_AMIGA_srsts_i_0_0_o2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename cpu_est_2_0_0_0_o2_i_2 "cpu_est_2_0_0_0_o2_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_346_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_c_i_2 "IPL_c_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_D0_0_i_2 "IPL_D0_0_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_25_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_030_1_i_0 "IPL_030_1_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_26_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_030_1_i_1 "IPL_030_1_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_27_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_030_1_i_2 "IPL_030_1_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_222_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_223_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_231_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_237_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_342_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_341_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_351_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RST_DLY_e2_i_0_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_155_i_0_o2_i_o2_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_228_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_213_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_212_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_357_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_0_i_2 "cpu_est_2_0_0_0_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_208_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_210_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_211_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_SM_AMIGA_0_sqmuxa_1_0_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RW_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_RW_000_INT_5_i_a3_i_i "pos_clk.RW_000_INT_5_i_a3_i_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_336_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_244_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename cpu_est_2_i_0_0_o2_i_3 "cpu_est_2_i_0_0_o2_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance VMA_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_352_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_353_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_293_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_o2_0_i_3 "SM_AMIGA_srsts_i_0_0_o2_0_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_198_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_197_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_16_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RW_000_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance VPA_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance VPA_D_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance DTACK_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance DTACK_D0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_c_i_0 "IPL_c_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_D0_0_i_0 "IPL_D0_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_c_i_1 "IPL_c_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_D0_0_i_1 "IPL_D0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_D0_0_2 "IPL_D0_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_D0_0_1 "IPL_D0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_D0_0_0 "IPL_D0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DTACK_D0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_D_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_amiga_bus_enable_low_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un21_fpu_cs_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a2_0 "SM_AMIGA_srsts_i_0_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DSACK1_INT_0_i_0_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DSACK1_INT_0_i_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename cpu_est_i_2 "cpu_est_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_2_i_0_0_a2_3 "cpu_est_2_i_0_0_a2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance G_109 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance G_108 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance G_107 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance (rename IPL_030_0_2__r "IPL_030_0_2_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_030_0_2__m "IPL_030_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_2__n "IPL_030_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_2__p "IPL_030_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename IPL_030_0_1__r "IPL_030_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_030_0_1__m "IPL_030_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_1__n "IPL_030_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_1__p "IPL_030_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename IPL_030_0_0__r "IPL_030_0_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_030_0_0__m "IPL_030_0_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_0__n "IPL_030_0_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_0__p "IPL_030_0_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename cpu_est_2_i_0_0_a3_3 "cpu_est_2_i_0_0_a3[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename cpu_est_0_3__r "cpu_est_0_3_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename cpu_est_0_3__m "cpu_est_0_3_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename cpu_est_0_3__n "cpu_est_0_3_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename cpu_est_0_3__p "cpu_est_0_3_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename IPL_030_1_2 "IPL_030_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_1_1 "IPL_030_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_1_0 "IPL_030_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance I_218 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DSACK1_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_DSACK1_INT_1_i_a2_0_a2 "pos_clk.DSACK1_INT_1_i_a2_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DTACK_D0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VPA_D_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RW_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename RW_000_INT_0_r "RW_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename RW_000_INT_0_m "RW_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename RW_000_INT_0_n "RW_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename RW_000_INT_0_p "RW_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance un1_amiga_bus_enable_low_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un21_fpu_cs_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_i_7 "SM_AMIGA_i_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_SM_AMIGA_0_sqmuxa_1_0_1_o3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_pe_0_0_o2 "pos_clk.un9_clk_000_pe_0_0_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_i_3 "cpu_est_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_2_i_0_0_o2_3 "cpu_est_2_i_0_0_o2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_0_x2_0_0 "cpu_est_0_0_x2_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_RW_000_INT_5_i_a3_i "pos_clk.RW_000_INT_5_i_a3_i") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_SM_AMIGA_0_sqmuxa_1_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_i_0_0_3 "cpu_est_2_i_0_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance DTACK_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a2_2_3 "SM_AMIGA_srsts_i_0_0_a2_2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_a2_0_3 "SM_AMIGA_srsts_i_0_0_a2_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance VPA_D_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_0_0_a2_0_0 "cpu_est_0_0_a2_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_0_x2_0_a3_0_0 "cpu_est_0_0_x2_0_a3_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename cpu_est_i_0 "cpu_est_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_0_0_a2_0 "cpu_est_0_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a2_3 "SM_AMIGA_srsts_i_0_0_a2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a2_1 "SM_AMIGA_srsts_i_0_0_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a2_2 "SM_AMIGA_srsts_i_0_0_a2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_0_0_x2_0_a3_0 "cpu_est_0_0_x2_0_a3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_0_2 "cpu_est_2_0_0_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_e_0_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_5 "SM_AMIGA_srsts_i_0_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_OUT_1_sqmuxa_i_0_111_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename CLK_000_D_i_1 "CLK_000_D_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_155_i_0_o2_i_o2_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance RST_DLY_e2_i_0_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename cpu_est_2_0_0_0_o2_2 "cpu_est_2_0_0_0_o2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_0 "SM_AMIGA_srsts_i_0_0_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLYlde_0_0_o3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename cpu_est_i_1 "cpu_est_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance un5_e_0_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un5_e_0_i_o2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_1 "SM_AMIGA_srsts_i_0_0_o2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_CYCLE_DMA_5_0_i_0_o2 "pos_clk.CYCLE_DMA_5_0_i_0_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un9_clk_000_pe_0_0_o2 "pos_clk.un9_clk_000_pe_0_0_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_i_3 "cpu_est_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_2_i_0_0_o2_3 "cpu_est_2_i_0_0_o2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_0_0 "cpu_est_0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DSACK1_INT_0_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_i_0_0_3 "cpu_est_2_i_0_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_o2_4 "SM_AMIGA_srsts_i_0_0_o2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_e_0_i_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_a3_5 "SM_AMIGA_srsts_i_0_0_a3[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e0_i_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename RST_DLY_i_0 "RST_DLY_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RST_DLY_e0_i_0_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_i_i_a3_2 "SM_AMIGA_srsts_i_i_i_a3[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_a3_3 "SM_AMIGA_srsts_i_0_0_a3[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_a3_4 "SM_AMIGA_srsts_i_0_0_a3[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance N_355_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RST_DLY_e2_i_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename cpu_est_2_0_0_0_a2_2 "cpu_est_2_0_0_0_a2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un5_e_0_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un5_e_0_i_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e0_i_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a2_0_1 "SM_AMIGA_srsts_i_0_0_a2_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance N_350_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RST_DLY_e2_i_0_a2_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_a2_0_2 "cpu_est_2_0_0_a2_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename pos_clk_un9_clk_000_pe_0_0 "pos_clk.un9_clk_000_pe_0_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename cpu_est_2_0_0_0_1 "cpu_est_2_0_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_0_2 "cpu_est_2_0_0_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un5_e_0_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RESET_OUT_1_sqmuxa_i_0_117_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename CLK_000_D_i_1 "CLK_000_D_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance CLK_000_NE_0_o3_i_a2_0_o2_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_SM_AMIGA_0_sqmuxa_1_0_1_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_030_H_2_0_a2_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_CYCLE_DMA_5_1_i_x2 "pos_clk.CYCLE_DMA_5_1_i_x2") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance I_220 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance BGACK_030_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance nEXP_SPACE_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_a3_0_3 "SM_AMIGA_srsts_i_0_0_a3_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_DS_000_ENABLE_0_sqmuxa_0_o3_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DS_000_ENABLE_1_sqmuxa_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_DS_000_ENABLE_0_sqmuxa_0_o3_0_o3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_o2_3 "SM_AMIGA_srsts_i_0_0_o2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename VMA_INT_0_r "VMA_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename VMA_INT_0_m "VMA_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename VMA_INT_0_n "VMA_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) @@ -673,60 +650,18 @@ (instance (rename cpu_est_0_2__m "cpu_est_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename cpu_est_0_2__n "cpu_est_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename cpu_est_0_2__p "cpu_est_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_o3_0_1 "SM_AMIGA_srsts_i_o3_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e2_i_0_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e2_i_0_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename RST_DLY_i_2 "RST_DLY_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RST_DLY_e2_i_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_0_a2_1 "cpu_est_2_0_0_0_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un7_as_030_0_a2_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_030_H_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance CLK_030_H_2_0_a2_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance I_221 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_DS_000_DMA_4_f0_i_a2_i_a2 "pos_clk.DS_000_DMA_4_f0_i_a2_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DS_000_DMA_2_sqmuxa_0_a2_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un6_bgack_000_0_0_a2 "pos_clk.un6_bgack_000_0_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DS_000_ENABLE_1_sqmuxa_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un6_bgack_000_0_0 "pos_clk.un6_bgack_000_0_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_iv_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_DS_000_DMA_4_f0_i_a2_i "pos_clk.DS_000_DMA_4_f0_i_a2_i") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_000_DMA_1_sqmuxa_0_a2_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename CLK_000_D_i_0 "CLK_000_D_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_261_i_0_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename DS_000_DMA_0_r "DS_000_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename DS_000_DMA_0_m "DS_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename DS_000_DMA_0_n "DS_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename DS_000_DMA_0_p "DS_000_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename AS_000_DMA_0_r "AS_000_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AS_000_DMA_0_m "AS_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AS_000_DMA_0_n "AS_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AS_000_DMA_0_p "AS_000_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename BGACK_030_INT_0_r "BGACK_030_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename BGACK_030_INT_0_m "BGACK_030_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename BGACK_030_INT_0_n "BGACK_030_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename BGACK_030_INT_0_p "BGACK_030_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename DS_000_ENABLE_0_r "DS_000_ENABLE_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename DS_000_ENABLE_0_m "DS_000_ENABLE_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename DS_000_ENABLE_0_n "DS_000_ENABLE_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename DS_000_ENABLE_0_p "DS_000_ENABLE_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance DS_000_ENABLE_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e2_i_0_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_0_a3_1 "cpu_est_2_0_0_0_a3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_0_a3_2 "cpu_est_2_0_0_0_a3[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_e_0_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DSACK1_INT_0_i_0_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DSACK1_INT_0_i_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename A_DECODE_i_16 "A_DECODE_i[16]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_DECODE_i_19 "A_DECODE_i[19]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_DECODE_i_18 "A_DECODE_i[18]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance BGACK_030_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_000_DMA_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DS_000_DMA_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance G_102 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename CYCLE_DMA_i_0 "CYCLE_DMA_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_CYCLE_DMA_5_0_i_0_a2 "pos_clk.CYCLE_DMA_5_0_i_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_iv_0_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a2_0_0 "SM_AMIGA_srsts_i_0_0_a2_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0_a2_0_0 "SM_AMIGA_nss_i_i_0_0_a2_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_000_DMA_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_as_000_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_rw_i_a2_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_DS_000_ENABLE_0_sqmuxa_0_o2_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un21_bgack_030_int_i_i_a2_i_a2 "pos_clk.un21_bgack_030_int_i_i_a2_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a2_0_3 "SM_AMIGA_srsts_i_0_0_a2_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un4_as_030_i_a2_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RESET_OUT_2_i_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance LDS_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance UDS_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un1_LDS_000_INT (viewRef prim (cellRef AND2 (libraryRef mach))) ) @@ -739,78 +674,149 @@ (instance (rename LDS_000_INT_0_m "LDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename LDS_000_INT_0_n "LDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename LDS_000_INT_0_p "LDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance DS_000_DMA_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un6_ds_030 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a2_4 "SM_AMIGA_srsts_i_0_0_a2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename RST_DLY_i_1 "RST_DLY_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RST_DLY_e1_i_0_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e1_i_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance FPU_SENSE_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un21_berr_0_a2_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_3 "SM_AMIGA_srsts_i_0_0_o2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_DS_000_ENABLE_0_sqmuxa_0_o2_0_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un21_bgack_030_int_i_i_a2_i_x2 "pos_clk.un21_bgack_030_int_i_i_a2_i_x2") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance un2_as_030_i_a2_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_D0_0_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RESET_OUT_2_i_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un13_ciin_i_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RESET_OUT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_RW_000_INT_5_0_0_o2 "pos_clk.RW_000_INT_5_0_0_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_6 "SM_AMIGA_srsts_i_0_0_o2[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un5_bgack_030_int_d_i_0_a2_i_o2 "pos_clk.un5_bgack_030_int_d_i_0_a2_i_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__r "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__m "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__n "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__p "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance AS_030_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_i_7 "SM_AMIGA_i_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_4 "SM_AMIGA_srsts_i_0_0_o2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e2_i_0_o2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLYlde_i_a2_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_5 "SM_AMIGA_srsts_i_0_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RESET_OUT_1_sqmuxa_i_0_117_1_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename RST_DLY_i_0 "RST_DLY_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RST_DLY_e0_i_0_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a2_5 "SM_AMIGA_srsts_i_0_0_a2[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_A0_DMA_3_0_a2_0_a2 "pos_clk.A0_DMA_3_0_a2_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename A_i_1 "A_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2_0_a2 "pos_clk.AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2_0_a2 "pos_clk.AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BGACK_030_INT_0_r "BGACK_030_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename BGACK_030_INT_0_m "BGACK_030_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BGACK_030_INT_0_n "BGACK_030_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BGACK_030_INT_0_p "BGACK_030_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename DS_000_ENABLE_0_r "DS_000_ENABLE_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename DS_000_ENABLE_0_m "DS_000_ENABLE_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DS_000_ENABLE_0_n "DS_000_ENABLE_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DS_000_ENABLE_0_p "DS_000_ENABLE_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance DS_000_ENABLE_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DSACK1_INT_0_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un6_bgack_000_0_0 "pos_clk.un6_bgack_000_0_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un6_bgack_000_0_0_a2 "pos_clk.un6_bgack_000_0_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DSACK1_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_DSACK1_INT_1_i_a2_0_a2 "pos_clk.DSACK1_INT_1_i_a2_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance I_216 (viewRef prim (cellRef INV (libraryRef mach))) ) (instance AS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename pos_clk_AS_000_INT_1_i_a2_0_a2 "pos_clk.AS_000_INT_1_i_a2_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un34_as_030_d0_i_i "pos_clk.un34_as_030_d0_i_i") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_RW_000_INT_5_0_0 "pos_clk.RW_000_INT_5_0_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_0_a3_0_0 "SM_AMIGA_nss_i_i_0_0_a3_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_a3_0 "SM_AMIGA_srsts_i_0_0_a3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance I_215 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_iv_0_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_INT_0_i_0_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_INT_0_i_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e2_i_0_o2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_OUT_1_sqmuxa_i_0_111_1_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename RST_DLY_i_1 "RST_DLY_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RST_DLY_e1_i_0_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e1_i_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance FPU_SENSE_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un21_berr_0_a3_0_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_o2_0 "SM_AMIGA_srsts_i_0_0_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_SM_AMIGA_0_sqmuxa_1_0_1_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename CLK_000_D_i_0 "CLK_000_D_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un1_ipl_i_0_o3 "pos_clk.un1_ipl_i_0_o3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_iv_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance AS_000_INT_0_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_SM_AMIGA_0_sqmuxa_1_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_RW_000_DMA_3_i_a2_i "pos_clk.RW_000_DMA_3_i_a2_i") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_rw_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un21_bgack_030_int_i_0_o3_0_x2 "pos_clk.un21_bgack_030_int_i_0_o3_0_x2") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance nEXP_SPACE_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_0_o2_0 "pos_clk.SIZE_DMA_6_0_0_0_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_0_i_0_o3 "pos_clk.CYCLE_DMA_5_0_i_0_o3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_o2_6 "SM_AMIGA_srsts_i_0_0_o2[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_030_H_2_i_0_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance BGACK_030_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un5_bgack_030_int_d_i_0_a2_i_o3 "pos_clk.un5_bgack_030_int_d_i_0_a2_i_o3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un2_as_030_i_a2_i_o3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un1_ipl_i_0_x2 "pos_clk.un1_ipl_i_0_x2") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance (rename pos_clk_un1_ipl_i_0_x2_0 "pos_clk.un1_ipl_i_0_x2_0") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance (rename pos_clk_un1_ipl_i_0_x2_1 "pos_clk.un1_ipl_i_0_x2_1") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_1_i_0_x2 "pos_clk.CYCLE_DMA_5_1_i_0_x2") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance AS_030_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un21_bgack_030_int_i_0_o3_0_a2 "pos_clk.un21_bgack_030_int_i_0_o3_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d0_i_i "pos_clk.un34_as_030_d0_i_i") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un10_amiga_bus_enable_high_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un13_ciin_i_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_RW_000_DMA_3_0_0 "pos_clk.RW_000_DMA_3_0_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_D0_0_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_DS_000_DMA_4_f0_0_0 "pos_clk.DS_000_DMA_4_f0_0_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_DMA_1_sqmuxa_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_as_000_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_OUT_2_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename pos_clk_SIZE_DMA_6_0_0_0_0 "pos_clk.SIZE_DMA_6_0_0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename pos_clk_SIZE_DMA_6_0_0_0_1 "pos_clk.SIZE_DMA_6_0_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance SIZE_DMA_3_sqmuxa_0_a2_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_0_o2_0 "pos_clk.SIZE_DMA_6_0_0_0_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance I_227 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_228 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_225 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_226 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_223 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_224 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_DECODE_i_18 "A_DECODE_i[18]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_DECODE_i_19 "A_DECODE_i[19]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_DECODE_i_16 "A_DECODE_i[16]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_000_INT_0_i_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_000_INT_0_i_0_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a2_6 "SM_AMIGA_srsts_i_0_0_a2[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0_a2_0 "SM_AMIGA_nss_i_i_0_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_0_a2_0 "pos_clk.SIZE_DMA_6_0_0_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_0_a2_1 "pos_clk.SIZE_DMA_6_0_0_0_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un4_as_030_i_a3_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance SIZE_DMA_3_sqmuxa_0_a3_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_OUT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_0_a3_0 "pos_clk.SIZE_DMA_6_0_0_0_a3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_0_a3_1 "pos_clk.SIZE_DMA_6_0_0_0_a3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_a3_1 "SM_AMIGA_srsts_i_0_0_a3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_a3_0_1 "SM_AMIGA_srsts_i_0_0_a3_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_0_a3_0 "SM_AMIGA_nss_i_i_0_0_a3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_A0_DMA_3_0_a3_0_a3 "pos_clk.A0_DMA_3_0_a3_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename A_i_1 "A_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a3_0_a3 "pos_clk.AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a3_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a3_0_a3 "pos_clk.AMIGA_BUS_ENABLE_DMA_LOW_3_i_a3_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_i_0 "IPL_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_D0_0_i_a3_0_a3_0 "IPL_D0_0_i_a3_0_a3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_i_1 "IPL_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_D0_0_i_a3_0_a3_1 "IPL_D0_0_i_a3_0_a3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_i_2 "IPL_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_D0_0_i_a3_0_a3_2 "IPL_D0_0_i_a3_0_a3[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance I_219 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename CYCLE_DMA_i_0 "CYCLE_DMA_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_0_i_0_a3 "pos_clk.CYCLE_DMA_5_0_i_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_HIGH_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un10_amiga_bus_enable_high_0_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_000_SYNC_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_030_H_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_030_H_2_i_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_DS_000_DMA_4_f0_0_0_a3 "pos_clk.DS_000_DMA_4_f0_0_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DS_000_DMA_2_sqmuxa_i_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_a3_6 "SM_AMIGA_srsts_i_0_0_a3[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_DMA_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_217 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un7_as_030_0_a3_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_OUT_2_0_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance CLK_OUT_PRE_50_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_206_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_207_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_208_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_229 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_230 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_79_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance G_96 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance I_224 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_225 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_222 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_223 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_220 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_221 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_218 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_1_1 "IPL_030_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_1_2 "IPL_030_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_0__r "SIZE_DMA_0_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_0__m "SIZE_DMA_0_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_0__n "SIZE_DMA_0_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_0__p "SIZE_DMA_0_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_1__r "SIZE_DMA_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_1__m "SIZE_DMA_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_1__n "SIZE_DMA_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_1__p "SIZE_DMA_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename IPL_030_0_0__r "IPL_030_0_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_0_0__m "IPL_030_0_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_0__n "IPL_030_0_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_0__p "IPL_030_0_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename IPL_030_0_1__r "IPL_030_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_0_1__m "IPL_030_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_1__n "IPL_030_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_1__p "IPL_030_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename IPL_030_0_2__r "IPL_030_0_2_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_0_2__m "IPL_030_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_2__n "IPL_030_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_2__p "IPL_030_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance N_113_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_112_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_111_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A0_DMA_0_r "A0_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A0_DMA_0_m "A0_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename A0_DMA_0_n "A0_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename A0_DMA_0_p "A0_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance N_114_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_r "AMIGA_BUS_ENABLE_DMA_LOW_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_m "AMIGA_BUS_ENABLE_DMA_LOW_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_n "AMIGA_BUS_ENABLE_DMA_LOW_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_p "AMIGA_BUS_ENABLE_DMA_LOW_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance N_115_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_r "AMIGA_BUS_ENABLE_DMA_HIGH_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_m "AMIGA_BUS_ENABLE_DMA_HIGH_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_n "AMIGA_BUS_ENABLE_DMA_HIGH_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) @@ -824,53 +830,43 @@ (instance AMIGA_BUS_ENABLE_DMA_LOW_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance A0_DMA_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance RW_000_DMA_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RW_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance AS_030_000_SYNC_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SIZE_DMA_0_0__r "SIZE_DMA_0_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SIZE_DMA_0_0__m "SIZE_DMA_0_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SIZE_DMA_0_0__n "SIZE_DMA_0_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SIZE_DMA_0_0__p "SIZE_DMA_0_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename SIZE_DMA_0_1__r "SIZE_DMA_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SIZE_DMA_0_1__m "SIZE_DMA_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SIZE_DMA_0_1__n "SIZE_DMA_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SIZE_DMA_0_1__p "SIZE_DMA_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance AS_000_DMA_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DS_000_DMA_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_1_0 "IPL_030_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance AMIGA_BUS_ENABLE_DMA_LOW_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance un1_amiga_bus_enable_low (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename pos_clk_un9_bg_030 "pos_clk.un9_bg_030") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un7_as_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_169_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_165_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_133_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_132_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DS_000_DMA_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un6_ds_030 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un6_ds_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename DS_000_DMA_0_r "DS_000_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename DS_000_DMA_0_m "DS_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DS_000_DMA_0_n "DS_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DS_000_DMA_0_p "DS_000_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename AS_000_DMA_0_r "AS_000_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AS_000_DMA_0_m "AS_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_000_DMA_0_n "AS_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_000_DMA_0_p "AS_000_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (instance (rename AS_030_000_SYNC_0_r "AS_030_000_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename AS_030_000_SYNC_0_m "AS_030_000_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename AS_030_000_SYNC_0_n "AS_030_000_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename AS_030_000_SYNC_0_p "AS_030_000_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename RW_000_INT_0_r "RW_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename RW_000_INT_0_m "RW_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename RW_000_INT_0_n "RW_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename RW_000_INT_0_p "RW_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (instance (rename RW_000_DMA_0_r "RW_000_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename RW_000_DMA_0_m "RW_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename RW_000_DMA_0_n "RW_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename RW_000_DMA_0_p "RW_000_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename A0_DMA_0_r "A0_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A0_DMA_0_m "A0_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename A0_DMA_0_n "A0_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename A0_DMA_0_p "A0_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance N_78_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_r "AMIGA_BUS_ENABLE_DMA_LOW_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_m "AMIGA_BUS_ENABLE_DMA_LOW_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_n "AMIGA_BUS_ENABLE_DMA_LOW_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_p "AMIGA_BUS_ENABLE_DMA_LOW_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (net BGACK_030_INT (joined (portRef Q (instanceRef BGACK_030_INT)) - (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__m)) - (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__r)) - (portRef I0 (instanceRef pos_clk_un5_bgack_030_int_d_i_0_a2_i_o2)) (portRef I0 (instanceRef un1_as_000_0_0)) - (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_a2)) - (portRef I0 (instanceRef BGACK_030_INT_0_n)) + (portRef I0 (instanceRef pos_clk_un5_bgack_030_int_d_i_0_a2_i_o3)) (portRef I0 (instanceRef BGACK_030_INT_i)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_a3)) + (portRef I0 (instanceRef BGACK_030_INT_0_n)) + (portRef I0 (instanceRef un10_amiga_bus_enable_high_0_0_a3_0_1)) (portRef I0 (instanceRef BGACK_030)) )) (net VCC (joined @@ -900,33 +896,28 @@ (portRef I0 (instanceRef un1_amiga_bus_enable_low_i)) )) (net un7_as_030 (joined - (portRef O (instanceRef un7_as_030_0_a2_0_a2)) + (portRef O (instanceRef un7_as_030_0_a3_0_a3)) (portRef I0 (instanceRef un7_as_030_i)) )) - (net un1_UDS_000_INT (joined - (portRef O (instanceRef un1_UDS_000_INT_i)) - (portRef I0 (instanceRef UDS_000)) - )) (net un1_LDS_000_INT (joined (portRef O (instanceRef un1_LDS_000_INT_i)) (portRef I0 (instanceRef LDS_000)) )) - (net un1_SM_AMIGA_0_sqmuxa_1 (joined - (portRef O (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_1_i)) - (portRef I1 (instanceRef RW_000_INT_0_m)) - (portRef I0 (instanceRef RW_000_INT_0_r)) + (net un1_UDS_000_INT (joined + (portRef O (instanceRef un1_UDS_000_INT_i)) + (portRef I0 (instanceRef UDS_000)) )) (net un10_ciin (joined - (portRef O (instanceRef un13_ciin_i_0_0_a2)) + (portRef O (instanceRef un13_ciin_i_0_0_a3)) (portRef I0 (instanceRef un10_ciin_i)) (portRef I0 (instanceRef CIIN)) )) (net un21_fpu_cs (joined - (portRef O (instanceRef un21_fpu_cs_0_a2_0_a2)) + (portRef O (instanceRef un21_fpu_cs_0_a3_0_a3)) (portRef I0 (instanceRef un21_fpu_cs_i)) )) (net un21_berr (joined - (portRef O (instanceRef un21_berr_0_a2_0_a2)) + (portRef O (instanceRef un21_berr_0_a3_0_a3)) (portRef OE (instanceRef BERR)) )) (net un6_ds_030 (joined @@ -935,89 +926,88 @@ )) (net (rename cpu_est_2 "cpu_est[2]") (joined (portRef Q (instanceRef cpu_est_2)) + (portRef I1 (instanceRef cpu_est_2_0_0_0_a3_2)) (portRef I0 (instanceRef cpu_est_0_2__m)) - (portRef I1 (instanceRef un5_e_0_i_a2_0)) - (portRef I1 (instanceRef cpu_est_2_0_0_0_a2_2)) + (portRef I1 (instanceRef un5_e_0_i_a3_0)) (portRef I0 (instanceRef cpu_est_i_2)) )) (net (rename cpu_est_3 "cpu_est[3]") (joined (portRef Q (instanceRef cpu_est_3)) + (portRef I0 (instanceRef un5_e_0_i_o2_0)) (portRef I0 (instanceRef cpu_est_2_i_0_0_o2_3)) (portRef I0 (instanceRef cpu_est_i_3)) - (portRef I0 (instanceRef un5_e_0_i_o2_0)) (portRef I0 (instanceRef cpu_est_0_3__m)) )) (net (rename cpu_est_0 "cpu_est[0]") (joined (portRef Q (instanceRef cpu_est_0)) (portRef I0 (instanceRef cpu_est_2_0_0_0_o2_2)) (portRef I0 (instanceRef cpu_est_i_0)) - (portRef I1 (instanceRef cpu_est_0_0_a2_0_0)) - (portRef I0 (instanceRef cpu_est_2_0_0_a2_0_1_1)) + (portRef I1 (instanceRef cpu_est_0_0_x2_0_a3_0_0)) + (portRef I0 (instanceRef cpu_est_2_0_0_a3_1_1_1)) )) (net (rename cpu_est_1 "cpu_est[1]") (joined (portRef Q (instanceRef cpu_est_1)) - (portRef I0 (instanceRef cpu_est_2_0_0_0_a2_1)) + (portRef I0 (instanceRef cpu_est_2_0_0_0_a3_1)) (portRef I0 (instanceRef cpu_est_0_1__m)) (portRef I0 (instanceRef un5_e_0_i_o2)) (portRef I0 (instanceRef cpu_est_i_1)) (portRef I1 (instanceRef cpu_est_2_0_0_0_o2_2)) )) + (net AMIGA_BUS_ENABLE_DMA_HIGH (joined + (portRef Q (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_n)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_i)) + )) (net AMIGA_BUS_ENABLE_DMA_LOW (joined (portRef Q (instanceRef AMIGA_BUS_ENABLE_DMA_LOW)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_n)) (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_i)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_n)) )) (net AS_030_D0 (joined (portRef Q (instanceRef AS_030_D0)) (portRef I0 (instanceRef AS_030_D0_i)) - (portRef I1 (instanceRef pos_clk_un6_bg_030_0_a2_0_a2_1)) + (portRef I0 (instanceRef pos_clk_un6_bg_030_i_0_1)) )) (net AS_030_000_SYNC (joined (portRef Q (instanceRef AS_030_000_SYNC)) (portRef I0 (instanceRef AS_030_000_SYNC_0_n)) - (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__m)) (portRef I0 (instanceRef AS_030_000_SYNC_i)) )) (net BGACK_030_INT_D (joined (portRef Q (instanceRef BGACK_030_INT_D)) - (portRef I1 (instanceRef pos_clk_un5_bgack_030_int_d_i_0_a2_i_o2)) + (portRef I1 (instanceRef pos_clk_un5_bgack_030_int_d_i_0_a2_i_o3)) )) (net AS_000_DMA (joined (portRef Q (instanceRef AS_000_DMA)) - (portRef I0 (instanceRef AS_000_DMA_i)) (portRef I0 (instanceRef AS_000_DMA_0_n)) - (portRef I0 (instanceRef pos_clk_DS_000_DMA_4_f0_i_a2_i_a2)) + (portRef I0 (instanceRef AS_000_DMA_i)) + (portRef I0 (instanceRef pos_clk_DS_000_DMA_4_f0_0_0_a3)) )) (net DS_000_DMA (joined (portRef Q (instanceRef DS_000_DMA)) - (portRef I0 (instanceRef DS_000_DMA_i)) (portRef I0 (instanceRef DS_000_DMA_0_n)) + (portRef I0 (instanceRef DS_000_DMA_i)) )) (net (rename CYCLE_DMA_0 "CYCLE_DMA[0]") (joined (portRef Q (instanceRef CYCLE_DMA_0)) - (portRef I0 (instanceRef pos_clk_un21_bgack_030_int_i_i_a2_i_x2)) + (portRef I0 (instanceRef G_96)) (portRef I0 (instanceRef CYCLE_DMA_i_0)) - (portRef I0 (instanceRef G_102)) + (portRef I0 (instanceRef pos_clk_un21_bgack_030_int_i_0_o3_0_x2)) )) (net (rename CYCLE_DMA_1 "CYCLE_DMA[1]") (joined (portRef Q (instanceRef CYCLE_DMA_1)) - (portRef I1 (instanceRef pos_clk_un21_bgack_030_int_i_i_a2_i_x2)) - (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_1_i_x2)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_1_i_0_x2)) + (portRef I1 (instanceRef pos_clk_un21_bgack_030_int_i_0_o3_0_x2)) )) (net VPA_D (joined (portRef Q (instanceRef VPA_D)) (portRef I0 (instanceRef VPA_D_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_2_3)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_3)) )) - (net (rename CLK_000_D_2 "CLK_000_D[2]") (joined - (portRef Q (instanceRef CLK_000_D_2)) - (portRef I0 (instanceRef CLK_000_D_i_2)) - (portRef D (instanceRef CLK_000_D_3)) - )) - (net (rename CLK_000_D_4 "CLK_000_D[4]") (joined - (portRef Q (instanceRef CLK_000_D_4)) - (portRef I0 (instanceRef CLK_000_D_i_4)) - (portRef D (instanceRef CLK_000_D_5)) + (net (rename CLK_000_D_3 "CLK_000_D[3]") (joined + (portRef Q (instanceRef CLK_000_D_3)) + (portRef I0 (instanceRef CLK_000_D_i_3)) + (portRef D (instanceRef CLK_000_D_4)) )) (net DTACK_D0 (joined (portRef Q (instanceRef DTACK_D0)) @@ -1025,22 +1015,23 @@ )) (net RESET_OUT (joined (portRef Q (instanceRef RESET_OUT)) + (portRef I0 (instanceRef RESET_OUT_2_0_0_a3)) (portRef I0 (instanceRef RESET_OUT_i)) - (portRef I0 (instanceRef RESET_OUT_2_i_i_a2)) - (portRef I1 (instanceRef un1_rw_i_a2_0_a2)) + (portRef I1 (instanceRef un4_as_030_i_a3_i)) (portRef I1 (instanceRef un1_as_000_0_0)) + (portRef I1 (instanceRef un1_rw_0)) )) (net (rename CLK_000_D_1 "CLK_000_D[1]") (joined (portRef Q (instanceRef CLK_000_D_1)) - (portRef I0 (instanceRef CLK_000_NE_0_o3_i_a2_0_o2_i_o2)) + (portRef I0 (instanceRef N_155_i_0_o2_i_o2_i_o2)) (portRef I0 (instanceRef CLK_000_D_i_1)) (portRef D (instanceRef CLK_000_D_2)) )) (net (rename CLK_000_D_0 "CLK_000_D[0]") (joined (portRef Q (instanceRef CLK_000_D_0)) - (portRef I0 (instanceRef N_261_i_0_o2)) + (portRef I0 (instanceRef pos_clk_un1_ipl_i_0_o3)) (portRef I0 (instanceRef CLK_000_D_i_0)) - (portRef I1 (instanceRef pos_clk_un6_bg_030_0_a2_0_a2)) + (portRef I1 (instanceRef pos_clk_un6_bg_030_i_0_1)) (portRef D (instanceRef CLK_000_D_1)) )) (net CLK_OUT_PRE_50 (joined @@ -1054,64 +1045,40 @@ )) (net (rename IPL_D0_0 "IPL_D0[0]") (joined (portRef Q (instanceRef IPL_D0_0)) - (portRef I0 (instanceRef G_107)) + (portRef I0 (instanceRef pos_clk_un1_ipl_i_0_x2)) )) (net (rename IPL_D0_1 "IPL_D0[1]") (joined (portRef Q (instanceRef IPL_D0_1)) - (portRef I0 (instanceRef G_108)) + (portRef I0 (instanceRef pos_clk_un1_ipl_i_0_x2_0)) )) (net (rename IPL_D0_2 "IPL_D0[2]") (joined (portRef Q (instanceRef IPL_D0_2)) - (portRef I0 (instanceRef G_109)) + (portRef I0 (instanceRef pos_clk_un1_ipl_i_0_x2_1)) )) - (net (rename CLK_000_D_3 "CLK_000_D[3]") (joined - (portRef Q (instanceRef CLK_000_D_3)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_o3_0_1)) - (portRef D (instanceRef CLK_000_D_4)) + (net (rename CLK_000_D_2 "CLK_000_D[2]") (joined + (portRef Q (instanceRef CLK_000_D_2)) + (portRef D (instanceRef CLK_000_D_3)) )) - (net (rename CLK_000_D_5 "CLK_000_D[5]") (joined - (portRef Q (instanceRef CLK_000_D_5)) + (net (rename CLK_000_D_4 "CLK_000_D[4]") (joined + (portRef Q (instanceRef CLK_000_D_4)) (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_1_0)) )) - (net (rename pos_clk_un6_bg_030 "pos_clk.un6_bg_030") (joined - (portRef O (instanceRef pos_clk_un6_bg_030_0_a2_0_a2)) - (portRef I0 (instanceRef pos_clk_un6_bg_030_i)) - )) - (net AMIGA_BUS_ENABLE_DMA_HIGH (joined - (portRef Q (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_n)) - (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__n)) - )) - (net (rename pos_clk_ipl "pos_clk.ipl") (joined - (portRef O (instanceRef G_110)) - (portRef I1 (instanceRef IPL_030_0_0__m)) - (portRef I0 (instanceRef IPL_030_0_0__r)) - (portRef I1 (instanceRef IPL_030_0_1__m)) - (portRef I0 (instanceRef IPL_030_0_1__r)) - (portRef I1 (instanceRef IPL_030_0_2__m)) - (portRef I0 (instanceRef IPL_030_0_2__r)) - )) - (net (rename SM_AMIGA_1 "SM_AMIGA[1]") (joined - (portRef Q (instanceRef SM_AMIGA_1)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_0)) - (portRef I0 (instanceRef SM_AMIGA_i_1)) - )) - (net UDS_000_INT (joined - (portRef Q (instanceRef UDS_000_INT)) - (portRef I0 (instanceRef UDS_000_INT_0_n)) - (portRef I0 (instanceRef UDS_000_INT_i)) - )) - (net DS_000_ENABLE (joined - (portRef Q (instanceRef DS_000_ENABLE)) - (portRef I0 (instanceRef un1_UDS_000_INT)) - (portRef I0 (instanceRef un1_LDS_000_INT)) - (portRef I0 (instanceRef DS_000_ENABLE_0_n)) - )) (net LDS_000_INT (joined (portRef Q (instanceRef LDS_000_INT)) (portRef I0 (instanceRef LDS_000_INT_0_n)) (portRef I0 (instanceRef LDS_000_INT_i)) )) + (net DS_000_ENABLE (joined + (portRef Q (instanceRef DS_000_ENABLE)) + (portRef I0 (instanceRef DS_000_ENABLE_0_n)) + (portRef I0 (instanceRef un1_UDS_000_INT)) + (portRef I0 (instanceRef un1_LDS_000_INT)) + )) + (net UDS_000_INT (joined + (portRef Q (instanceRef UDS_000_INT)) + (portRef I0 (instanceRef UDS_000_INT_0_n)) + (portRef I0 (instanceRef UDS_000_INT_i)) + )) (net (rename pos_clk_un9_bg_030 "pos_clk.un9_bg_030") (joined (portRef O (instanceRef pos_clk_un9_bg_030_i)) (portRef I1 (instanceRef BG_000_0_m)) @@ -1119,22 +1086,27 @@ )) (net (rename SM_AMIGA_6 "SM_AMIGA[6]") (joined (portRef Q (instanceRef SM_AMIGA_6)) + (portRef I1 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_1_o2)) + (portRef I0 (instanceRef SM_AMIGA_i_6)) (portRef I1 (instanceRef LDS_000_INT_0_m)) (portRef I0 (instanceRef LDS_000_INT_0_r)) (portRef I1 (instanceRef UDS_000_INT_0_m)) (portRef I0 (instanceRef UDS_000_INT_0_r)) - (portRef I0 (instanceRef SM_AMIGA_i_6)) - (portRef I1 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_1_o2)) )) (net (rename SM_AMIGA_4 "SM_AMIGA[4]") (joined (portRef Q (instanceRef SM_AMIGA_4)) (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_3)) (portRef I0 (instanceRef SM_AMIGA_i_4)) )) + (net (rename SM_AMIGA_1 "SM_AMIGA[1]") (joined + (portRef Q (instanceRef SM_AMIGA_1)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_0)) + (portRef I0 (instanceRef SM_AMIGA_i_1)) + )) (net (rename SM_AMIGA_0 "SM_AMIGA[0]") (joined (portRef Q (instanceRef SM_AMIGA_0)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_0_0)) (portRef I0 (instanceRef SM_AMIGA_i_0)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_a3_0_0)) )) (net (rename SIZE_DMA_0 "SIZE_DMA[0]") (joined (portRef Q (instanceRef SIZE_DMA_0)) @@ -1158,18 +1130,18 @@ )) (net (rename RST_DLY_0 "RST_DLY[0]") (joined (portRef Q (instanceRef RST_DLY_0)) - (portRef I0 (instanceRef RST_DLY_i_0)) (portRef I0 (instanceRef RST_DLY_e2_i_0_o2_0)) - (portRef I1 (instanceRef RST_DLY_e0_i_0_a2)) + (portRef I0 (instanceRef RST_DLY_i_0)) + (portRef I1 (instanceRef RST_DLY_e0_i_0_a3)) )) (net (rename RST_DLY_1 "RST_DLY[1]") (joined (portRef Q (instanceRef RST_DLY_1)) - (portRef I1 (instanceRef RST_DLY_e2_i_0_o2_0)) (portRef I0 (instanceRef RST_DLY_i_1)) + (portRef I1 (instanceRef RST_DLY_e2_i_0_o2_0)) )) (net (rename RST_DLY_2 "RST_DLY[2]") (joined (portRef Q (instanceRef RST_DLY_2)) - (portRef I1 (instanceRef RESET_OUT_1_sqmuxa_i_0_117_1_a2)) + (portRef I1 (instanceRef RESET_OUT_1_sqmuxa_i_0_111_1_a2)) (portRef I0 (instanceRef RST_DLY_i_2)) )) (net A0_DMA (joined @@ -1178,18 +1150,18 @@ (portRef I0 (instanceRef A_0)) )) (net (rename pos_clk_A0_DMA_3 "pos_clk.A0_DMA_3") (joined - (portRef O (instanceRef pos_clk_A0_DMA_3_0_a2_0_a2)) + (portRef O (instanceRef pos_clk_A0_DMA_3_0_a3_0_a3)) (portRef I0 (instanceRef A0_DMA_0_m)) )) + (net (rename pos_clk_RW_000_DMA_3 "pos_clk.RW_000_DMA_3") (joined + (portRef O (instanceRef pos_clk_RW_000_DMA_3_0_0_i)) + (portRef I0 (instanceRef RW_000_DMA_0_m)) + )) (net CLK_030_H (joined (portRef Q (instanceRef CLK_030_H)) - (portRef I0 (instanceRef DS_000_DMA_2_sqmuxa_0_a2_i_a2)) + (portRef I0 (instanceRef DS_000_DMA_2_sqmuxa_i_0_a3)) (portRef I0 (instanceRef CLK_030_H_i)) )) - (net (rename pos_clk_RW_000_INT_5 "pos_clk.RW_000_INT_5") (joined - (portRef O (instanceRef pos_clk_RW_000_INT_5_0_0_i)) - (portRef I0 (instanceRef RW_000_INT_0_m)) - )) (net DSACK1_INT (joined (portRef Q (instanceRef DSACK1_INT)) (portRef I0 (instanceRef DSACK1_INT_i)) @@ -1200,19 +1172,31 @@ )) (net (rename SM_AMIGA_5 "SM_AMIGA[5]") (joined (portRef Q (instanceRef SM_AMIGA_5)) - (portRef I0 (instanceRef SM_AMIGA_i_5)) (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_4)) + (portRef I0 (instanceRef SM_AMIGA_i_5)) )) (net (rename SM_AMIGA_3 "SM_AMIGA[3]") (joined (portRef Q (instanceRef SM_AMIGA_3)) (portRef I0 (instanceRef SM_AMIGA_i_3)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_2)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_i_o2_2)) )) (net (rename SM_AMIGA_2 "SM_AMIGA[2]") (joined (portRef Q (instanceRef SM_AMIGA_2)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_1)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a3_1)) (portRef I0 (instanceRef SM_AMIGA_i_2)) )) + (net (rename pos_clk_DS_000_DMA_4 "pos_clk.DS_000_DMA_4") (joined + (portRef O (instanceRef pos_clk_DS_000_DMA_4_f0_0_0_i)) + (portRef I0 (instanceRef DS_000_DMA_0_m)) + )) + (net N_3 (joined + (portRef O (instanceRef DS_000_DMA_0_p)) + (portRef I0 (instanceRef N_3_i)) + )) + (net N_4 (joined + (portRef O (instanceRef AS_000_DMA_0_p)) + (portRef I0 (instanceRef N_4_i)) + )) (net N_6 (joined (portRef O (instanceRef SIZE_DMA_0_0__p)) (portRef D (instanceRef SIZE_DMA_0)) @@ -1237,10 +1221,6 @@ (portRef O (instanceRef AS_030_000_SYNC_0_p)) (portRef I0 (instanceRef N_15_i)) )) - (net N_16 (joined - (portRef O (instanceRef RW_000_INT_0_p)) - (portRef I0 (instanceRef N_16_i)) - )) (net N_19 (joined (portRef O (instanceRef RW_000_DMA_0_p)) (portRef I0 (instanceRef N_19_i)) @@ -1250,41 +1230,53 @@ (portRef I0 (instanceRef N_20_i)) )) (net N_22 (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_p)) + (portRef O (instanceRef IPL_030_0_0__p)) (portRef I0 (instanceRef N_22_i)) )) (net N_23 (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_p)) + (portRef O (instanceRef IPL_030_0_1__p)) (portRef I0 (instanceRef N_23_i)) )) (net N_24 (joined - (portRef O (instanceRef BG_000_0_p)) + (portRef O (instanceRef IPL_030_0_2__p)) (portRef I0 (instanceRef N_24_i)) )) + (net N_25 (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_p)) + (portRef I0 (instanceRef N_25_i)) + )) + (net N_26 (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_p)) + (portRef I0 (instanceRef N_26_i)) + )) + (net N_27 (joined + (portRef O (instanceRef BG_000_0_p)) + (portRef I0 (instanceRef N_27_i)) + )) (net N_28 (joined - (portRef O (instanceRef IPL_030_1_i_0)) - (portRef D (instanceRef IPL_030DFF_0)) - )) - (net N_29 (joined - (portRef O (instanceRef IPL_030_1_i_1)) - (portRef D (instanceRef IPL_030DFF_1)) - )) - (net N_30 (joined - (portRef O (instanceRef IPL_030_1_i_2)) - (portRef D (instanceRef IPL_030DFF_2)) - )) - (net N_31 (joined (portRef O (instanceRef BG_000_1_i)) (portRef D (instanceRef BG_000DFF)) )) - (net N_32 (joined + (net N_29 (joined (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1_i)) (portRef D (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH)) )) - (net N_33 (joined + (net N_30 (joined (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1_i)) (portRef D (instanceRef AMIGA_BUS_ENABLE_DMA_LOW)) )) + (net N_31 (joined + (portRef O (instanceRef IPL_030_1_i_0)) + (portRef D (instanceRef IPL_030DFF_0)) + )) + (net N_32 (joined + (portRef O (instanceRef IPL_030_1_i_1)) + (portRef D (instanceRef IPL_030DFF_1)) + )) + (net N_33 (joined + (portRef O (instanceRef IPL_030_1_i_2)) + (portRef D (instanceRef IPL_030DFF_2)) + )) (net N_34 (joined (portRef O (instanceRef UDS_000_INT_1_i)) (portRef D (instanceRef UDS_000_INT)) @@ -1329,18 +1321,6 @@ (portRef O (instanceRef AS_030_D0_0_0_0_i)) (portRef D (instanceRef AS_030_D0)) )) - (net N_49 (joined - (portRef O (instanceRef IPL_D0_0_i_0)) - (portRef D (instanceRef IPL_D0_0)) - )) - (net N_50 (joined - (portRef O (instanceRef IPL_D0_0_i_1)) - (portRef D (instanceRef IPL_D0_1)) - )) - (net N_51 (joined - (portRef O (instanceRef IPL_D0_0_i_2)) - (portRef D (instanceRef IPL_D0_2)) - )) (net N_52 (joined (portRef O (instanceRef VPA_D_0_i)) (portRef D (instanceRef VPA_D)) @@ -1349,14 +1329,18 @@ (portRef O (instanceRef DTACK_D0_0_i)) (portRef D (instanceRef DTACK_D0)) )) + (net N_55 (joined + (portRef O (instanceRef RESET_OUT_2_0_0_i)) + (portRef D (instanceRef RESET_OUT)) + )) (net N_56 (joined (portRef O (instanceRef DS_000_ENABLE_1)) (portRef D (instanceRef DS_000_ENABLE)) )) (net (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (joined (portRef Q (instanceRef SM_AMIGA_i_7)) + (portRef I1 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_1_o3)) (portRef I0 (instanceRef SM_AMIGA_i_i_7)) - (portRef I1 (instanceRef pos_clk_RW_000_INT_5_0_0_o2)) )) (net (rename pos_clk_SIZE_DMA_6_0 "pos_clk.SIZE_DMA_6[0]") (joined (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0_i_0)) @@ -1366,309 +1350,344 @@ (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0_i_1)) (portRef I0 (instanceRef SIZE_DMA_0_1__m)) )) - (net N_206 (joined - (portRef O (instanceRef G_107)) - (portRef I0 (instanceRef N_206_i)) + (net N_199 (joined + (portRef O (instanceRef G_96)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_1_i_0_x2)) + (portRef I0 (instanceRef N_199_i)) )) - (net N_207 (joined - (portRef O (instanceRef G_108)) - (portRef I0 (instanceRef N_207_i)) + (net (rename pos_clk_un21_bgack_030_int_i_0 "pos_clk.un21_bgack_030_int_i_0") (joined + (portRef O (instanceRef pos_clk_un21_bgack_030_int_i_0_o3_0_o3_i)) + (portRef I0 (instanceRef AS_000_DMA_0_m)) )) - (net N_208 (joined - (portRef O (instanceRef G_109)) - (portRef I0 (instanceRef N_208_i)) + (net N_231 (joined + (portRef O (instanceRef pos_clk_un6_bg_030_i_0_i)) + (portRef I1 (instanceRef pos_clk_un9_bg_030)) + )) + (net N_233 (joined + (portRef O (instanceRef pos_clk_un1_ipl_i_0_i)) + (portRef I1 (instanceRef IPL_030_0_2__m)) + (portRef I0 (instanceRef IPL_030_0_2__r)) + (portRef I1 (instanceRef IPL_030_0_1__m)) + (portRef I0 (instanceRef IPL_030_0_1__r)) + (portRef I1 (instanceRef IPL_030_0_0__m)) + (portRef I0 (instanceRef IPL_030_0_0__r)) + )) + (net N_111 (joined + (portRef O (instanceRef IPL_D0_0_i_a3_0_a3_2)) + (portRef I0 (instanceRef N_111_i)) + )) + (net N_112 (joined + (portRef O (instanceRef IPL_D0_0_i_a3_0_a3_1)) + (portRef I0 (instanceRef N_112_i)) + )) + (net N_113 (joined + (portRef O (instanceRef IPL_D0_0_i_a3_0_a3_0)) + (portRef I0 (instanceRef N_113_i)) + )) + (net N_114 (joined + (portRef O (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a3_0_a3)) + (portRef I0 (instanceRef N_114_i)) + )) + (net N_115 (joined + (portRef O (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a3_0_a3)) + (portRef I0 (instanceRef N_115_i)) )) (net N_245 (joined - (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_o2_i)) - (portRef D (instanceRef BGACK_030_INT_D)) + (portRef O (instanceRef AS_000_DMA_1_sqmuxa_i_0_i)) + (portRef I1 (instanceRef AS_000_DMA_0_m)) + (portRef I0 (instanceRef AS_000_DMA_0_r)) )) - (net N_78 (joined - (portRef O (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2_0_a2)) - (portRef I0 (instanceRef N_78_i)) + (net N_246 (joined + (portRef O (instanceRef DS_000_DMA_2_sqmuxa_i_0_i)) + (portRef I1 (instanceRef DS_000_DMA_0_m)) + (portRef I0 (instanceRef DS_000_DMA_0_r)) )) - (net N_79 (joined - (portRef O (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2_0_a2)) - (portRef I0 (instanceRef N_79_i)) - )) - (net N_260 (joined + (net N_62 (joined (portRef O (instanceRef un13_ciin_i_0_0_i)) (portRef OE (instanceRef CIIN)) )) - (net N_139 (joined - (portRef O (instanceRef un4_as_030_i_a2_0_a2)) - (portRef OE (instanceRef AHIGH_24)) - (portRef OE (instanceRef AHIGH_25)) - (portRef OE (instanceRef AHIGH_26)) - (portRef OE (instanceRef AHIGH_27)) - (portRef OE (instanceRef AHIGH_28)) - (portRef OE (instanceRef AHIGH_29)) - (portRef OE (instanceRef AHIGH_30)) - (portRef OE (instanceRef AHIGH_31)) - (portRef OE (instanceRef AS_030)) - (portRef OE (instanceRef A_0)) - (portRef OE (instanceRef DS_030)) + (net N_251 (joined + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_o3_i)) + (portRef D (instanceRef BGACK_030_INT_D)) )) - (net N_141 (joined - (portRef O (instanceRef un1_rw_i_a2_0_a2)) - (portRef I0 (instanceRef un4_as_030_i_a2_0_a2)) - (portRef OE (instanceRef RW)) - )) - (net N_165 (joined + (net N_132 (joined (portRef O (instanceRef pos_clk_DSACK1_INT_1_i_a2_0_a2)) - (portRef I0 (instanceRef N_165_i)) - (portRef I0 (instanceRef DSACK1_INT_0_i_0_a2_0)) + (portRef I0 (instanceRef N_132_i)) + (portRef I0 (instanceRef DSACK1_INT_0_i_0_a3)) )) - (net N_169 (joined + (net N_133 (joined (portRef O (instanceRef pos_clk_AS_000_INT_1_i_a2_0_a2)) - (portRef I0 (instanceRef N_169_i)) - (portRef I0 (instanceRef AS_000_INT_0_i_0_a2)) + (portRef I0 (instanceRef N_133_i)) + (portRef I0 (instanceRef AS_000_INT_0_i_0_a3)) )) - (net N_297 (joined + (net N_310 (joined (portRef O (instanceRef pos_clk_un34_as_030_d0_i_i_i)) (portRef I1 (instanceRef AS_030_000_SYNC_0_m)) (portRef I0 (instanceRef AS_030_000_SYNC_0_r)) )) - (net N_298 (joined - (portRef O (instanceRef RESET_OUT_2_i_i_i)) - (portRef D (instanceRef RESET_OUT)) - )) - (net N_300 (joined - (portRef O (instanceRef pos_clk_RW_000_DMA_3_i_a2_i_i)) - (portRef I0 (instanceRef RW_000_DMA_0_m)) - )) - (net N_302 (joined - (portRef O (instanceRef DS_000_DMA_2_sqmuxa_0_a2_i_i)) - (portRef I1 (instanceRef DS_000_DMA_0_m)) - (portRef I0 (instanceRef DS_000_DMA_0_r)) - )) - (net N_113 (joined - (portRef O (instanceRef SIZE_DMA_3_sqmuxa_0_a2_i_i)) + (net N_126 (joined + (portRef O (instanceRef SIZE_DMA_3_sqmuxa_0_a3_i_i)) (portRef I1 (instanceRef SIZE_DMA_0_1__m)) (portRef I0 (instanceRef SIZE_DMA_0_1__r)) (portRef I1 (instanceRef SIZE_DMA_0_0__m)) (portRef I0 (instanceRef SIZE_DMA_0_0__r)) )) - (net N_305 (joined - (portRef O (instanceRef CLK_000_NE_0_o3_i_a2_0_o2_i_o2_i)) - (portRef I0 (instanceRef RST_DLYlde_i_a2_i)) - (portRef I0 (instanceRef RST_DLY_e2_i_0_a2_1)) + (net N_149 (joined + (portRef O (instanceRef N_155_i_0_o2_i_o2_i_o2_i)) + (portRef I0 (instanceRef RST_DLY_e2_i_0_a3_1)) (portRef I1 (instanceRef cpu_est_0_2__m)) (portRef I0 (instanceRef cpu_est_0_2__r)) (portRef I1 (instanceRef cpu_est_0_1__m)) (portRef I0 (instanceRef cpu_est_0_1__r)) - (portRef I0 (instanceRef cpu_est_0_0_a2_0)) + (portRef I0 (instanceRef RST_DLYlde_0_0_o3)) + (portRef I0 (instanceRef cpu_est_0_0_x2_0_a3_0)) (portRef I1 (instanceRef cpu_est_0_3__m)) (portRef I0 (instanceRef cpu_est_0_3__r)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_1_1)) )) - (net N_155 (joined - (portRef O (instanceRef N_261_i_0_o2_i)) - (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_a2)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_1_2)) + (net N_150 (joined + (portRef O (instanceRef pos_clk_un1_ipl_i_0_o3_i)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_a3)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a3_1)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_1_0)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_i_1_2)) (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_1_4)) )) - (net N_163 (joined + (net N_158 (joined (portRef O (instanceRef RST_DLY_e2_i_0_o2_0_i)) - (portRef I0 (instanceRef RST_DLY_e2_i_0_a2_1_0)) + (portRef I0 (instanceRef RST_DLY_e2_i_0_a3_1_0)) )) - (net N_166 (joined + (net N_160 (joined (portRef O (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_1_o2_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a3_5)) (portRef I0 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_1)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_5)) (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_1_6)) )) - (net N_171 (joined + (net N_163 (joined (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_o2_i_0)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_a3_0)) )) - (net N_180 (joined - (portRef O (instanceRef pos_clk_un21_bgack_030_int_i_i_a2_i_o2_i)) - (portRef I0 (instanceRef AS_000_DMA_0_m)) + (net N_172 (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0_o2_i_0)) + (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_a3_0)) + )) + (net N_179 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_6)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a3_6)) )) (net N_184 (joined - (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0_o2_i_0)) - (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_a2_0)) + (portRef O (instanceRef CLK_030_H_2_i_0_o2_i)) + (portRef I1 (instanceRef CLK_030_H_2_i_0_a3)) )) - (net N_191 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_6)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_6)) - )) - (net N_199 (joined - (portRef O (instanceRef pos_clk_un5_bgack_030_int_d_i_0_a2_i_o2_i)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_m)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_r)) - (portRef I1 (instanceRef A0_DMA_0_m)) - (portRef I0 (instanceRef A0_DMA_0_r)) + (net N_185 (joined + (portRef O (instanceRef pos_clk_un5_bgack_030_int_d_i_0_a2_i_o3_i)) (portRef I1 (instanceRef RW_000_DMA_0_m)) (portRef I0 (instanceRef RW_000_DMA_0_r)) (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_m)) (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_r)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_m)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_r)) + (portRef I1 (instanceRef A0_DMA_0_m)) + (portRef I0 (instanceRef A0_DMA_0_r)) )) - (net N_205 (joined - (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__p)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_HIGH)) + (net N_196 (joined + (portRef O (instanceRef RST_DLY_e2_i_0_a3)) + (portRef I0 (instanceRef N_196_i)) )) - (net N_306 (joined - (portRef O (instanceRef RST_DLY_e2_i_0_a2)) - (portRef I0 (instanceRef N_306_i)) + (net N_203 (joined + (portRef O (instanceRef RST_DLY_e1_i_0_a3_1)) + (portRef I0 (instanceRef N_203_i)) )) - (net N_215 (joined - (portRef O (instanceRef RST_DLY_e1_i_0_a2_1)) - (portRef I0 (instanceRef N_215_i)) + (net N_204 (joined + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_a3)) + (portRef I0 (instanceRef N_204_i)) )) - (net N_221 (joined - (portRef O (instanceRef cpu_est_2_0_0_a2_0_1)) - (portRef I0 (instanceRef N_221_i)) - )) - (net N_227 (joined - (portRef O (instanceRef pos_clk_un34_as_030_d0_i_i_a2)) - (portRef I0 (instanceRef N_227_i)) - )) - (net N_230 (joined - (portRef O (instanceRef RESET_OUT_2_i_i_a2_0)) - (portRef I0 (instanceRef N_230_i)) - )) - (net N_319 (joined - (portRef O (instanceRef AS_000_INT_0_i_0_a2)) - (portRef I0 (instanceRef N_319_i)) - )) - (net N_320 (joined - (portRef O (instanceRef AS_000_INT_0_i_0_a2_0)) - (portRef I0 (instanceRef N_320_i)) - )) - (net N_267 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_0)) - (portRef I0 (instanceRef N_267_i)) - )) - (net N_324 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_0)) - (portRef I0 (instanceRef N_324_i)) - )) - (net N_269 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_2)) - (portRef I0 (instanceRef N_269_i)) - )) - (net N_270 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_4)) - (portRef I0 (instanceRef N_270_i)) - )) - (net N_327 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_6)) - (portRef I0 (instanceRef N_327_i)) - )) - (net N_273 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_a2_0)) - (portRef I0 (instanceRef N_273_i)) - )) - (net N_275 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_a2_0_0)) - (portRef I0 (instanceRef N_275_i)) - )) - (net N_290 (joined - (portRef O (instanceRef CLK_030_H_2_0_a2_i_a2)) - (portRef I0 (instanceRef N_290_i)) - )) - (net N_292 (joined - (portRef O (instanceRef DS_000_DMA_2_sqmuxa_0_a2_i_a2)) - (portRef I0 (instanceRef N_292_i)) - )) - (net N_295 (joined - (portRef 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(net N_355 (joined + (portRef O (instanceRef RESET_OUT_1_sqmuxa_i_0_111_1_a2)) + (portRef I1 (instanceRef RST_DLY_e2_i_0_a3_0)) + (portRef I0 (instanceRef N_355_i)) + (portRef I1 (instanceRef RESET_OUT_2_0_0_a3_0_1)) + )) + (net N_151_i (joined + (portRef O (instanceRef pos_clk_un21_bgack_030_int_i_0_o3_0_x2)) + (portRef I0 (instanceRef pos_clk_un21_bgack_030_int_i_0_o3_0_o3_2)) + )) + (net N_360 (joined + (portRef O (instanceRef pos_clk_un1_ipl_i_0_x2)) + (portRef I0 (instanceRef N_360_i)) + )) + (net N_191_i (joined + (portRef O (instanceRef pos_clk_un1_ipl_i_0_x2_0)) + (portRef I0 (instanceRef N_191_i_i)) + )) + (net N_192_i (joined + (portRef O (instanceRef pos_clk_un1_ipl_i_0_x2_1)) + (portRef I0 (instanceRef N_192_i_i)) + )) + (net N_193_i (joined + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_1_i_0_x2)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_1_i_0_1)) + )) + (net N_156 (joined + (portRef O (instanceRef pos_clk_un34_as_030_d0_i_i_o2_i)) + (portRef I1 (instanceRef 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I0 (instanceRef N_221_i)) + )) + (net N_222 (joined + (portRef O (instanceRef AS_000_INT_0_i_0_a3_0)) + (portRef I0 (instanceRef N_222_i)) + )) + (net N_219 (joined + (portRef O (instanceRef DSACK1_INT_0_i_0_a3)) + (portRef I0 (instanceRef N_219_i)) + )) + (net N_220 (joined + (portRef O (instanceRef DSACK1_INT_0_i_0_a3_0)) + (portRef I0 (instanceRef N_220_i)) + )) + (net (rename pos_clk_un6_bgack_000 "pos_clk.un6_bgack_000") (joined + (portRef O (instanceRef pos_clk_un6_bgack_000_0_0_i)) + (portRef I1 (instanceRef BGACK_030_INT_0_m)) + (portRef I0 (instanceRef BGACK_030_INT_0_r)) + )) + (net N_359 (joined + (portRef O (instanceRef pos_clk_un6_bgack_000_0_0_a2)) + (portRef I0 (instanceRef N_359_i)) + )) + (net N_8 (joined + (portRef O (instanceRef BGACK_030_INT_0_p)) + (portRef I0 (instanceRef N_8_i)) + )) (net N_14 (joined (portRef O (instanceRef LDS_000_INT_0_p)) (portRef I0 (instanceRef N_14_i)) @@ -1677,69 +1696,27 @@ (portRef O (instanceRef UDS_000_INT_0_p)) (portRef I0 (instanceRef N_21_i)) )) - (net N_3 (joined - (portRef O (instanceRef DS_000_DMA_0_p)) - (portRef I0 (instanceRef N_3_i)) - )) - (net N_301 (joined - (portRef O (instanceRef pos_clk_DS_000_DMA_4_f0_i_a2_i_i)) - (portRef I0 (instanceRef DS_000_DMA_0_m)) - )) - (net N_4 (joined - (portRef O (instanceRef AS_000_DMA_0_p)) - (portRef I0 (instanceRef N_4_i)) - )) - (net N_303 (joined - (portRef O (instanceRef AS_000_DMA_1_sqmuxa_0_a2_i_i)) - (portRef I1 (instanceRef AS_000_DMA_0_m)) - (portRef I0 (instanceRef AS_000_DMA_0_r)) - )) - (net N_8 (joined - (portRef O (instanceRef BGACK_030_INT_0_p)) - (portRef I0 (instanceRef N_8_i)) - )) - (net (rename pos_clk_un6_bgack_000 "pos_clk.un6_bgack_000") (joined - (portRef O (instanceRef pos_clk_un6_bgack_000_0_0_i)) - (portRef I1 (instanceRef BGACK_030_INT_0_m)) - (portRef I0 (instanceRef BGACK_030_INT_0_r)) - )) (net N_9 (joined (portRef O (instanceRef DS_000_ENABLE_0_p)) (portRef I0 (instanceRef DS_000_ENABLE_1)) )) - (net N_65 (joined + (net un1_DS_000_ENABLE_0_sqmuxa (joined + (portRef O (instanceRef un1_DS_000_ENABLE_0_sqmuxa_0_o3_0_o3_i)) + (portRef I0 (instanceRef DS_000_ENABLE_0_m)) + )) + (net N_66 (joined (portRef O (instanceRef DS_000_ENABLE_1_sqmuxa_i_0_i)) (portRef I1 (instanceRef DS_000_ENABLE_0_m)) (portRef I0 (instanceRef DS_000_ENABLE_0_r)) )) - (net N_217 (joined - (portRef O (instanceRef G_102)) - (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_1_i_x2)) - (portRef I0 (instanceRef N_217_i)) + (net N_171 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_3)) + (portRef I0 (instanceRef un1_DS_000_ENABLE_0_sqmuxa_0_o3_0_o3)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a3_0_3)) )) - (net N_216 (joined - (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_a2)) - (portRef I0 (instanceRef N_216_i)) - )) - (net N_248 (joined - (portRef O (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_a2)) - (portRef I0 (instanceRef N_248_i)) - )) - (net N_198 (joined - (portRef O (instanceRef CLK_030_H_2_0_a2_i_o2_i)) - (portRef I1 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(instanceRef SM_AMIGA_srsts_i_0_0_o2_0_i_3)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_3)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_1_2)) + (net N_357 (joined + (portRef O (instanceRef cpu_est_2_0_0_0_a2_2)) + (portRef I0 (instanceRef N_357_i)) + (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_0_a3_0_1)) )) - (net N_194 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_1)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_1)) + (net N_206 (joined + (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_0_a3_0)) + (portRef I0 (instanceRef N_206_i)) )) - (net N_347 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_1_3)) - (portRef I0 (instanceRef N_347_i)) + (net N_205 (joined + (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_0_a3)) + (portRef I0 (instanceRef N_205_i)) )) - (net N_348 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_2_3)) - (portRef I0 (instanceRef N_348_i)) + (net N_352 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_3)) + (portRef I0 (instanceRef N_352_i)) )) - (net N_160 (joined + (net N_353 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_3)) + (portRef I0 (instanceRef N_353_i)) + )) + (net N_314 (joined (portRef O (instanceRef cpu_est_2_i_0_0_o2_i_3)) - (portRef I0 (instanceRef cpu_est_2_i_0_0_a2_3)) + (portRef I0 (instanceRef cpu_est_2_i_0_0_a3_3)) )) - (net N_341 (joined - (portRef O (instanceRef cpu_est_0_0_a2_0)) - (portRef I0 (instanceRef N_341_i)) + (net N_244 (joined + (portRef O (instanceRef cpu_est_0_0_x2_0_a3_0_0)) + (portRef I0 (instanceRef N_244_i)) )) - (net N_342 (joined - (portRef O (instanceRef cpu_est_0_0_a2_0_0)) - (portRef I0 (instanceRef N_342_i)) + (net N_336 (joined + (portRef O (instanceRef cpu_est_0_0_x2_0_a3_0)) + (portRef I0 (instanceRef N_336_i)) )) - (net N_231 (joined - (portRef O (instanceRef DSACK1_INT_0_i_0_a2)) - (portRef I0 (instanceRef N_231_i)) + (net N_311 (joined + (portRef O (instanceRef pos_clk_RW_000_INT_5_i_a3_i_i)) + (portRef I0 (instanceRef RW_000_INT_0_m)) )) - (net N_237 (joined - (portRef O (instanceRef DSACK1_INT_0_i_0_a2_0)) - (portRef I0 (instanceRef N_237_i)) + (net un1_SM_AMIGA_0_sqmuxa_1 (joined + (portRef O (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_1_i)) + (portRef I1 (instanceRef RW_000_INT_0_m)) + (portRef I0 (instanceRef RW_000_INT_0_r)) )) - (net N_223 (joined - (portRef O (instanceRef cpu_est_2_i_0_0_a2_3)) - (portRef I0 (instanceRef N_223_i)) + (net N_211 (joined + (portRef O (instanceRef cpu_est_2_i_0_0_a3_3)) + (portRef I0 (instanceRef N_211_i)) )) - (net N_27 (joined - (portRef O (instanceRef IPL_030_0_2__p)) - (portRef I0 (instanceRef N_27_i)) - )) - (net N_26 (joined - (portRef O (instanceRef IPL_030_0_1__p)) - (portRef I0 (instanceRef N_26_i)) - )) - (net N_25 (joined - (portRef O (instanceRef IPL_030_0_0__p)) - (portRef I0 (instanceRef N_25_i)) + (net N_16 (joined + (portRef O (instanceRef RW_000_INT_0_p)) + (portRef I0 (instanceRef N_16_i)) )) (net un1_amiga_bus_enable_low_i (joined (portRef O (instanceRef un1_amiga_bus_enable_low_i)) @@ -1882,272 +1852,291 @@ )) (net (rename cpu_est_i_2 "cpu_est_i[2]") (joined (portRef O (instanceRef cpu_est_i_2)) - (portRef I1 (instanceRef cpu_est_2_0_0_a2_0_2)) - (portRef I1 (instanceRef un5_e_0_i_a2)) + (portRef I1 (instanceRef un5_e_0_i_a3)) + (portRef I1 (instanceRef cpu_est_2_0_0_0_a2_2)) (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_0_o2)) - (portRef I1 (instanceRef cpu_est_2_i_0_0_a2_3)) - )) - (net (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (joined - (portRef O (instanceRef SM_AMIGA_i_0)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_0)) - )) - (net (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (joined - (portRef O (instanceRef SM_AMIGA_i_2)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_1)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_2)) - )) - (net (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (joined - (portRef O (instanceRef SM_AMIGA_i_1)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_0)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_1)) + (portRef I1 (instanceRef cpu_est_2_i_0_0_a3_3)) )) (net (rename cpu_est_i_0 "cpu_est_i[0]") (joined (portRef O (instanceRef cpu_est_i_0)) - (portRef I1 (instanceRef cpu_est_2_0_0_0_a2_1)) + (portRef I1 (instanceRef cpu_est_2_0_0_0_a3_1)) + (portRef I1 (instanceRef cpu_est_0_0_x2_0_a3_0)) (portRef I1 (instanceRef cpu_est_2_i_0_0_o2_3)) - (portRef I1 (instanceRef cpu_est_0_0_a2_0)) - (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_0_a2_2)) + (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_0_a3_2)) )) (net VPA_D_i (joined (portRef O (instanceRef VPA_D_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_1_2_3)) - (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_0_a2_0_2)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_2_3)) + (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_0_a3_0_2)) )) (net DTACK_D0_i (joined (portRef O (instanceRef DTACK_D0_i)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_2_3)) - )) - (net AS_030_i (joined - (portRef O (instanceRef I_218)) - (portRef I0 (instanceRef pos_clk_un34_as_030_d0_i_i)) - (portRef I1 (instanceRef pos_clk_AS_000_INT_1_i_a2_0_a2)) - (portRef I0 (instanceRef AS_030_D0_0_0_0)) - (portRef I0 (instanceRef un21_berr_0_a2_0_a2_1)) - (portRef I0 (instanceRef DS_000_ENABLE_1_sqmuxa_i_0)) - (portRef I0 (instanceRef pos_clk_DSACK1_INT_1_i_a2_0_a2)) - )) - (net DSACK1_INT_i (joined - (portRef O (instanceRef DSACK1_INT_i)) - (portRef I1 (instanceRef pos_clk_DSACK1_INT_1_i_a2_0_a2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_3)) )) (net (rename cpu_est_i_3 "cpu_est_i[3]") (joined (portRef O (instanceRef cpu_est_i_3)) (portRef I1 (instanceRef un5_e_0_i_o2)) - (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_0_a2_2)) - (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_0_a2_0_2)) - (portRef I1 (instanceRef cpu_est_2_0_0_a2_0_1)) + (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_0_a3_2)) + (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_0_a3_0_2)) + (portRef I1 (instanceRef cpu_est_2_0_0_a3_1_1)) + )) + (net (rename SM_AMIGA_i_i_7 "SM_AMIGA_i_i[7]") (joined + (portRef O (instanceRef SM_AMIGA_i_i_7)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_a3_0)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_6)) + (portRef I1 (instanceRef pos_clk_un34_as_030_d0_i_i_a3_2)) + )) + (net (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (joined + (portRef O (instanceRef SM_AMIGA_i_5)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a3_5)) )) (net (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (joined (portRef O (instanceRef SM_AMIGA_i_3)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_3)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a3_0_3)) )) (net (rename cpu_est_i_1 "cpu_est_i[1]") (joined (portRef O (instanceRef cpu_est_i_1)) (portRef I0 (instanceRef VMA_INT_0_m)) - (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_0_o2)) (portRef I1 (instanceRef un5_e_0_i_o2_0)) - (portRef I1 (instanceRef cpu_est_2_0_0_a2_0_1_1)) + (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_0_o2)) + (portRef I1 (instanceRef cpu_est_2_0_0_a3_1_1_1)) )) (net (rename CLK_000_D_i_1 "CLK_000_D_i[1]") (joined (portRef O (instanceRef CLK_000_D_i_1)) - (portRef I1 (instanceRef N_261_i_0_o2)) + (portRef I1 (instanceRef pos_clk_un1_ipl_i_0_o3)) )) - (net N_350_i_0 (joined - (portRef O (instanceRef N_350_i)) - (portRef I0 (instanceRef RESET_OUT_1_sqmuxa_i_0_117_1)) - (portRef I1 (instanceRef RST_DLY_e2_i_0_a2_3)) - )) - (net (rename RST_DLY_i_2 "RST_DLY_i[2]") (joined - (portRef O (instanceRef RST_DLY_i_2)) - (portRef I1 (instanceRef RST_DLY_e2_i_0_a2_1)) + (net N_355_i_0 (joined + (portRef O (instanceRef N_355_i)) (portRef I1 (instanceRef RST_DLY_e2_i_0_a2)) - )) - (net nEXP_SPACE_i (joined - (portRef O (instanceRef nEXP_SPACE_i)) - (portRef I0 (instanceRef un13_ciin_i_0_0)) - (portRef I1 (instanceRef un2_as_030_i_a2_i)) - (portRef I1 (instanceRef un4_as_030_i_a2_0_a2)) - (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_a2_0_2)) - )) - (net AS_000_i (joined - (portRef O (instanceRef I_220)) - (portRef I0 (instanceRef un6_ds_030)) - (portRef I1 (instanceRef un7_as_030_0_a2_0_a2)) - (portRef I0 (instanceRef pos_clk_un21_bgack_030_int_i_i_a2_i_o2_1)) - (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_a2_0_1)) - (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_1)) - (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_1_i_1)) - )) - (net BGACK_030_INT_i (joined - (portRef O (instanceRef BGACK_030_INT_i)) - (portRef I1 (instanceRef un1_amiga_bus_enable_low)) - (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_a2_1)) - (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_a2_0)) - (portRef I0 (instanceRef pos_clk_RW_000_DMA_3_i_a2_i)) - (portRef I1 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2_0_a2)) - (portRef I1 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2_0_a2)) - (portRef I0 (instanceRef pos_clk_A0_DMA_3_0_a2_0_a2)) - (portRef I0 (instanceRef un2_as_030_i_a2_i)) - (portRef I0 (instanceRef un1_rw_i_a2_0_a2)) - (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_o2)) - (portRef I1 (instanceRef pos_clk_un21_bgack_030_int_i_i_a2_i_o2_1)) - (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_a2_0_1)) - )) - (net (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (joined - (portRef O (instanceRef SM_AMIGA_i_6)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_6)) - )) - (net (rename CLK_000_D_i_0 "CLK_000_D_i[0]") (joined - (portRef O (instanceRef CLK_000_D_i_0)) - (portRef I1 (instanceRef CLK_000_NE_0_o3_i_a2_0_o2_i_o2)) - )) - (net RW_000_i (joined - (portRef O (instanceRef I_221)) - (portRef I1 (instanceRef pos_clk_RW_000_DMA_3_i_a2_i)) - (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_a2)) - (portRef I1 (instanceRef pos_clk_DS_000_DMA_4_f0_i_a2_i_a2)) - (portRef I1 (instanceRef DS_000_DMA_2_sqmuxa_0_a2_i)) - )) - (net CLK_030_H_i (joined - (portRef O (instanceRef CLK_030_H_i)) - (portRef I0 (instanceRef CLK_030_H_2_0_a2_i_a2)) - )) - (net AS_000_DMA_i (joined - (portRef O (instanceRef AS_000_DMA_i)) - (portRef I0 (instanceRef un7_as_030_0_a2_0_a2)) - (portRef I0 (instanceRef CLK_030_H_2_0_a2_i_o2)) - )) - (net (rename CYCLE_DMA_i_0 "CYCLE_DMA_i[0]") (joined - (portRef O (instanceRef CYCLE_DMA_i_0)) - (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_a2)) - )) - (net DS_000_DMA_i (joined - (portRef O (instanceRef DS_000_DMA_i)) - (portRef I1 (instanceRef un6_ds_030)) - )) - (net RESET_OUT_i (joined - (portRef O (instanceRef RESET_OUT_i)) - (portRef OE (instanceRef RESET)) + (portRef I0 (instanceRef RESET_OUT_1_sqmuxa_i_0_111_1)) )) (net (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (joined (portRef O (instanceRef SM_AMIGA_i_4)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_4)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a3_4)) )) - (net FPU_SENSE_i (joined - (portRef O (instanceRef FPU_SENSE_i)) - (portRef I1 (instanceRef un21_fpu_cs_0_a2_0_a2_1)) - )) - (net (rename RST_DLY_i_1 "RST_DLY_i[1]") (joined - (portRef O (instanceRef RST_DLY_i_1)) - (portRef I1 (instanceRef RST_DLY_e1_i_0_a2_0)) - (portRef I1 (instanceRef RST_DLY_e1_i_0_a2_1)) - )) - (net (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (joined - (portRef O (instanceRef SM_AMIGA_i_5)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_5)) + (net (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (joined + (portRef O (instanceRef SM_AMIGA_i_2)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a3_0_1)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_i_a3_2)) )) (net (rename RST_DLY_i_0 "RST_DLY_i[0]") (joined (portRef O (instanceRef RST_DLY_i_0)) - (portRef I1 (instanceRef RST_DLY_e0_i_0_a2_0)) - (portRef I1 (instanceRef RST_DLY_e1_i_0_a2_1_1)) + (portRef I1 (instanceRef RST_DLY_e0_i_0_a3_0)) + (portRef I1 (instanceRef RST_DLY_e1_i_0_a3_1_1)) )) - (net (rename SM_AMIGA_i_i_7 "SM_AMIGA_i_i[7]") (joined - (portRef O (instanceRef SM_AMIGA_i_i_7)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_0)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_6)) - (portRef I1 (instanceRef pos_clk_un34_as_030_d0_i_i_a2_2)) - )) - (net AS_030_D0_i (joined - (portRef O (instanceRef AS_030_D0_i)) - (portRef I1 (instanceRef un13_ciin_i_0_0_a2_5)) - (portRef I0 (instanceRef pos_clk_un34_as_030_d0_i_i_a2_1)) - )) - (net AS_000_INT_i (joined - (portRef O (instanceRef AS_000_INT_i)) - (portRef I0 (instanceRef pos_clk_AS_000_INT_1_i_a2_0_a2)) - )) - (net (rename A_i_1 "A_i[1]") (joined - (portRef O (instanceRef A_i_1)) - (portRef I0 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2_0_a2)) - )) - (net (rename A_DECODE_i_16 "A_DECODE_i[16]") (joined - (portRef O (instanceRef A_DECODE_i_16)) - (portRef I1 (instanceRef pos_clk_un34_as_030_d0_i_i_o2_2)) - )) - (net (rename A_DECODE_i_18 "A_DECODE_i[18]") (joined - (portRef O (instanceRef A_DECODE_i_18)) - (portRef I0 (instanceRef pos_clk_un34_as_030_d0_i_i_o2_3)) + (net (rename RST_DLY_i_2 "RST_DLY_i[2]") (joined + (portRef O (instanceRef RST_DLY_i_2)) + (portRef I1 (instanceRef RST_DLY_e2_i_0_a3_1)) + (portRef I1 (instanceRef RST_DLY_e2_i_0_a3)) )) (net (rename A_DECODE_i_19 "A_DECODE_i[19]") (joined (portRef O (instanceRef A_DECODE_i_19)) (portRef I1 (instanceRef pos_clk_un34_as_030_d0_i_i_o2_3)) )) + (net (rename A_DECODE_i_18 "A_DECODE_i[18]") (joined + (portRef O (instanceRef A_DECODE_i_18)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d0_i_i_o2_3)) + )) + (net (rename A_DECODE_i_16 "A_DECODE_i[16]") (joined + (portRef O (instanceRef A_DECODE_i_16)) + (portRef I1 (instanceRef pos_clk_un34_as_030_d0_i_i_o2_2)) + )) + (net RW_000_i (joined + (portRef O (instanceRef I_215)) + (portRef I1 (instanceRef pos_clk_DS_000_DMA_4_f0_0_0_a3)) + (portRef I1 (instanceRef pos_clk_RW_000_DMA_3_0_0)) + (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_a3)) + (portRef I1 (instanceRef DS_000_DMA_2_sqmuxa_i_0_1)) + )) + (net (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (joined + (portRef O (instanceRef SM_AMIGA_i_0)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a3_0)) + )) + (net AS_030_i (joined + (portRef O (instanceRef I_216)) + (portRef I0 (instanceRef AS_030_D0_0_0_0)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d0_i_i)) + (portRef I0 (instanceRef un21_berr_0_a3_0_a3_1)) + (portRef I1 (instanceRef pos_clk_AS_000_INT_1_i_a2_0_a2)) + (portRef I0 (instanceRef pos_clk_DSACK1_INT_1_i_a2_0_a2)) + (portRef I0 (instanceRef DS_000_ENABLE_1_sqmuxa_i_0)) + (portRef I1 (instanceRef un10_amiga_bus_enable_high_0_0_a3_0)) + )) + (net AS_000_INT_i (joined + (portRef O (instanceRef AS_000_INT_i)) + (portRef I0 (instanceRef pos_clk_AS_000_INT_1_i_a2_0_a2)) + )) + (net DSACK1_INT_i (joined + (portRef O (instanceRef DSACK1_INT_i)) + (portRef I1 (instanceRef pos_clk_DSACK1_INT_1_i_a2_0_a2)) + )) + (net (rename CLK_000_D_i_0 "CLK_000_D_i[0]") (joined + (portRef O (instanceRef CLK_000_D_i_0)) + (portRef I1 (instanceRef N_155_i_0_o2_i_o2_i_o2)) + )) + (net (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (joined + (portRef O (instanceRef SM_AMIGA_i_6)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a3_6)) + )) + (net (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (joined + (portRef O (instanceRef SM_AMIGA_i_1)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a3_0_1)) + )) + (net FPU_SENSE_i (joined + (portRef O (instanceRef FPU_SENSE_i)) + (portRef I1 (instanceRef un21_fpu_cs_0_a3_0_a3_1)) + )) + (net (rename RST_DLY_i_1 "RST_DLY_i[1]") (joined + (portRef O (instanceRef RST_DLY_i_1)) + (portRef I1 (instanceRef RST_DLY_e1_i_0_a3_0)) + (portRef I1 (instanceRef RST_DLY_e1_i_0_a3_1)) + )) + (net AS_030_D0_i (joined + (portRef O (instanceRef AS_030_D0_i)) + (portRef I1 (instanceRef un13_ciin_i_0_0_a3_5)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d0_i_i_a3_1)) + )) + (net BGACK_030_INT_i (joined + (portRef O (instanceRef BGACK_030_INT_i)) + (portRef I1 (instanceRef un1_amiga_bus_enable_low)) + (portRef I1 (instanceRef un10_amiga_bus_enable_high_0_0_a3)) + (portRef I1 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a3_0_a3)) + (portRef I1 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a3_0_a3)) + (portRef I0 (instanceRef pos_clk_A0_DMA_3_0_a3_0_a3)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_a3_1)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_a3_0)) + (portRef I0 (instanceRef pos_clk_RW_000_DMA_3_0_0)) + (portRef I0 (instanceRef un2_as_030_i_a2_i_o3)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_o3)) + (portRef I0 (instanceRef un1_rw_0)) + (portRef I1 (instanceRef pos_clk_un21_bgack_030_int_i_0_o3_0_o3_1)) + )) + (net nEXP_SPACE_i (joined + (portRef O (instanceRef nEXP_SPACE_i)) + (portRef I0 (instanceRef un13_ciin_i_0_0)) + (portRef I1 (instanceRef un2_as_030_i_a2_i_o3)) + )) + (net RESET_OUT_i (joined + (portRef O (instanceRef RESET_OUT_i)) + (portRef OE (instanceRef RESET)) + )) + (net (rename IPL_i_2 "IPL_i[2]") (joined + (portRef O (instanceRef IPL_i_2)) + (portRef I0 (instanceRef IPL_D0_0_i_a3_0_a3_2)) + )) + (net (rename IPL_i_1 "IPL_i[1]") (joined + (portRef O (instanceRef IPL_i_1)) + (portRef I0 (instanceRef IPL_D0_0_i_a3_0_a3_1)) + )) + (net (rename IPL_i_0 "IPL_i[0]") (joined + (portRef O (instanceRef IPL_i_0)) + (portRef I0 (instanceRef IPL_D0_0_i_a3_0_a3_0)) + )) + (net (rename A_i_1 "A_i[1]") (joined + (portRef O (instanceRef A_i_1)) + (portRef I0 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a3_0_a3)) + )) + (net AS_000_DMA_i (joined + (portRef O (instanceRef AS_000_DMA_i)) + (portRef I0 (instanceRef un7_as_030_0_a3_0_a3)) + (portRef I0 (instanceRef CLK_030_H_2_i_0_o2)) + )) + (net AS_000_i (joined + (portRef O (instanceRef I_217)) + (portRef I0 (instanceRef un6_ds_030)) + (portRef I1 (instanceRef un7_as_030_0_a3_0_a3)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_1)) + (portRef I0 (instanceRef pos_clk_un21_bgack_030_int_i_0_o3_0_o3_1)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_a3_0_1)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_1_i_0_1)) + )) + (net CLK_030_H_i (joined + (portRef O (instanceRef CLK_030_H_i)) + (portRef I0 (instanceRef CLK_030_H_2_i_0_a3)) + )) + (net AS_030_000_SYNC_i (joined + (portRef O (instanceRef AS_030_000_SYNC_i)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_1_0)) + (portRef I1 (instanceRef un10_amiga_bus_enable_high_0_0_a3_0_1)) + )) + (net AMIGA_BUS_ENABLE_DMA_HIGH_i (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_i)) + (portRef I0 (instanceRef un10_amiga_bus_enable_high_0_0_a3)) + )) + (net (rename CYCLE_DMA_i_0 "CYCLE_DMA_i[0]") (joined + (portRef O (instanceRef CYCLE_DMA_i_0)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_a3)) + )) (net (rename AHIGH_i_30 "AHIGH_i[30]") (joined - (portRef O (instanceRef I_223)) - (portRef I0 (instanceRef un13_ciin_i_0_0_a2_4)) + (portRef O (instanceRef I_218)) + (portRef I0 (instanceRef un13_ciin_i_0_0_a3_4)) )) (net (rename AHIGH_i_31 "AHIGH_i[31]") (joined - (portRef O (instanceRef I_224)) - (portRef I1 (instanceRef un13_ciin_i_0_0_a2_4)) + (portRef O (instanceRef I_219)) + (portRef I1 (instanceRef un13_ciin_i_0_0_a3_4)) )) (net (rename AHIGH_i_28 "AHIGH_i[28]") (joined - (portRef O (instanceRef I_225)) - (portRef I0 (instanceRef un13_ciin_i_0_0_a2_3)) + (portRef O (instanceRef I_220)) + (portRef I0 (instanceRef un13_ciin_i_0_0_a3_3)) )) (net (rename AHIGH_i_29 "AHIGH_i[29]") (joined - (portRef O (instanceRef I_226)) - (portRef I1 (instanceRef un13_ciin_i_0_0_a2_3)) + (portRef O (instanceRef I_221)) + (portRef I1 (instanceRef un13_ciin_i_0_0_a3_3)) )) (net (rename AHIGH_i_26 "AHIGH_i[26]") (joined - (portRef O (instanceRef I_227)) - (portRef I0 (instanceRef un13_ciin_i_0_0_a2_2)) + (portRef O (instanceRef I_222)) + (portRef I0 (instanceRef un13_ciin_i_0_0_a3_2)) )) (net (rename AHIGH_i_27 "AHIGH_i[27]") (joined - (portRef O (instanceRef I_228)) - (portRef I1 (instanceRef un13_ciin_i_0_0_a2_2)) + (portRef O (instanceRef I_223)) + (portRef I1 (instanceRef un13_ciin_i_0_0_a3_2)) )) (net (rename AHIGH_i_24 "AHIGH_i[24]") (joined - (portRef O (instanceRef I_229)) - (portRef I0 (instanceRef un13_ciin_i_0_0_a2_1)) + (portRef O (instanceRef I_224)) + (portRef I0 (instanceRef un13_ciin_i_0_0_a3_1)) )) (net (rename AHIGH_i_25 "AHIGH_i[25]") (joined - (portRef O (instanceRef I_230)) - (portRef I1 (instanceRef un13_ciin_i_0_0_a2_1)) - )) - (net N_206_i (joined - (portRef O (instanceRef N_206_i)) - (portRef I1 (instanceRef G_110_1)) - )) - (net N_207_i (joined - (portRef O (instanceRef N_207_i)) - (portRef I1 (instanceRef G_110)) - )) - (net N_208_i (joined - (portRef O (instanceRef N_208_i)) - (portRef I0 (instanceRef G_110_1)) + (portRef O (instanceRef I_225)) + (portRef I1 (instanceRef un13_ciin_i_0_0_a3_1)) )) (net CLK_OUT_PRE_50_i (joined (portRef O (instanceRef CLK_OUT_PRE_50_i)) (portRef D (instanceRef CLK_OUT_PRE_50)) )) - (net N_79_i (joined - (portRef O (instanceRef N_79_i)) + (net N_111_i (joined + (portRef O (instanceRef N_111_i)) + (portRef D (instanceRef IPL_D0_2)) + )) + (net N_112_i (joined + (portRef O (instanceRef N_112_i)) + (portRef D (instanceRef IPL_D0_1)) + )) + (net N_113_i (joined + (portRef O (instanceRef N_113_i)) + (portRef D (instanceRef IPL_D0_0)) + )) + (net N_115_i (joined + (portRef O (instanceRef N_115_i)) (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_m)) )) - (net N_78_i (joined - (portRef O (instanceRef N_78_i)) + (net N_114_i (joined + (portRef O (instanceRef N_114_i)) (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_m)) )) (net un6_ds_030_i (joined (portRef O (instanceRef un6_ds_030_i)) (portRef I0 (instanceRef DS_030)) )) - (net N_165_i (joined - (portRef O (instanceRef N_165_i)) + (net DS_000_DMA_i (joined + (portRef O (instanceRef DS_000_DMA_i)) + (portRef I1 (instanceRef un6_ds_030)) + )) + (net N_132_i (joined + (portRef O (instanceRef N_132_i)) (portRef I0 (instanceRef DSACK1)) )) - (net N_169_i (joined - (portRef O (instanceRef N_169_i)) + (net N_133_i (joined + (portRef O (instanceRef N_133_i)) (portRef I0 (instanceRef AS_000)) )) (net un7_as_030_i (joined @@ -2161,7 +2150,7 @@ (net AS_030_c (joined (portRef O (instanceRef AS_030)) (portRef I0 (instanceRef AS_030_000_SYNC_0_m)) - (portRef I0 (instanceRef I_218)) + (portRef I0 (instanceRef I_216)) )) (net AS_030 (joined (portRef AS_030) @@ -2169,8 +2158,8 @@ )) (net AS_000_c (joined (portRef O (instanceRef AS_000)) + (portRef I0 (instanceRef I_217)) (portRef I0 (instanceRef pos_clk_un6_bgack_000_0_0_a2)) - (portRef I0 (instanceRef I_220)) )) (net AS_000 (joined (portRef AS_000) @@ -2178,8 +2167,8 @@ )) (net RW_000_c (joined (portRef O (instanceRef RW_000)) - (portRef I0 (instanceRef I_221)) - (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_a2_0_2)) + (portRef I0 (instanceRef I_215)) + (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_a3_0)) )) (net RW_000 (joined (portRef IO (instanceRef RW_000)) @@ -2191,8 +2180,8 @@ )) (net UDS_000_c (joined (portRef O (instanceRef UDS_000)) - (portRef I1 (instanceRef pos_clk_A0_DMA_3_0_a2_0_a2)) - (portRef I1 (instanceRef pos_clk_un21_bgack_030_int_i_i_a2_i_a2)) + (portRef I1 (instanceRef pos_clk_A0_DMA_3_0_a3_0_a3)) + (portRef I1 (instanceRef pos_clk_un21_bgack_030_int_i_0_o3_0_a2)) (portRef I0 (instanceRef UDS_000_c_i)) )) (net UDS_000 (joined @@ -2201,7 +2190,7 @@ )) (net LDS_000_c (joined (portRef O (instanceRef LDS_000)) - (portRef I0 (instanceRef pos_clk_un21_bgack_030_int_i_i_a2_i_a2)) + (portRef I0 (instanceRef pos_clk_un21_bgack_030_int_i_0_o3_0_a2)) (portRef I0 (instanceRef LDS_000_c_i)) )) (net LDS_000 (joined @@ -2226,7 +2215,7 @@ )) (net (rename AHIGH_c_24 "AHIGH_c[24]") (joined (portRef O (instanceRef AHIGH_24)) - (portRef I0 (instanceRef I_229)) + (portRef I0 (instanceRef I_224)) )) (net (rename AHIGH_24 "AHIGH[24]") (joined (portRef IO (instanceRef AHIGH_24)) @@ -2234,7 +2223,7 @@ )) (net (rename AHIGH_c_25 "AHIGH_c[25]") (joined (portRef O (instanceRef AHIGH_25)) - (portRef I0 (instanceRef I_230)) + (portRef I0 (instanceRef I_225)) )) (net (rename AHIGH_25 "AHIGH[25]") (joined (portRef IO (instanceRef AHIGH_25)) @@ -2242,7 +2231,7 @@ )) (net (rename AHIGH_c_26 "AHIGH_c[26]") (joined (portRef O (instanceRef AHIGH_26)) - (portRef I0 (instanceRef I_227)) + (portRef I0 (instanceRef I_222)) )) (net (rename AHIGH_26 "AHIGH[26]") (joined (portRef IO (instanceRef AHIGH_26)) @@ -2250,7 +2239,7 @@ )) (net (rename AHIGH_c_27 "AHIGH_c[27]") (joined (portRef O (instanceRef AHIGH_27)) - (portRef I0 (instanceRef I_228)) + (portRef I0 (instanceRef I_223)) )) (net (rename AHIGH_27 "AHIGH[27]") (joined (portRef IO (instanceRef AHIGH_27)) @@ -2258,7 +2247,7 @@ )) (net (rename AHIGH_c_28 "AHIGH_c[28]") (joined (portRef O (instanceRef AHIGH_28)) - (portRef I0 (instanceRef I_225)) + (portRef I0 (instanceRef I_220)) )) (net (rename AHIGH_28 "AHIGH[28]") (joined (portRef IO (instanceRef AHIGH_28)) @@ -2266,7 +2255,7 @@ )) (net (rename AHIGH_c_29 "AHIGH_c[29]") (joined (portRef O (instanceRef AHIGH_29)) - (portRef I0 (instanceRef I_226)) + (portRef I0 (instanceRef I_221)) )) (net (rename AHIGH_29 "AHIGH[29]") (joined (portRef IO (instanceRef AHIGH_29)) @@ -2274,7 +2263,7 @@ )) (net (rename AHIGH_c_30 "AHIGH_c[30]") (joined (portRef O (instanceRef AHIGH_30)) - (portRef I0 (instanceRef I_223)) + (portRef I0 (instanceRef I_218)) )) (net (rename AHIGH_30 "AHIGH[30]") (joined (portRef IO (instanceRef AHIGH_30)) @@ -2282,7 +2271,7 @@ )) (net (rename AHIGH_c_31 "AHIGH_c[31]") (joined (portRef O (instanceRef AHIGH_31)) - (portRef I0 (instanceRef I_224)) + (portRef I0 (instanceRef I_219)) )) (net (rename AHIGH_31 "AHIGH[31]") (joined (portRef (member ahigh 0)) @@ -2420,7 +2409,7 @@ )) (net (rename A_DECODE_c_20 "A_DECODE_c[20]") (joined (portRef O (instanceRef A_DECODE_20)) - (portRef I0 (instanceRef un13_ciin_i_0_0_a2_6)) + (portRef I0 (instanceRef un13_ciin_i_0_0_a3_6)) )) (net (rename A_DECODE_20 "A_DECODE[20]") (joined (portRef (member a_decode 3)) @@ -2428,7 +2417,7 @@ )) (net (rename A_DECODE_c_21 "A_DECODE_c[21]") (joined (portRef O (instanceRef A_DECODE_21)) - (portRef I1 (instanceRef un13_ciin_i_0_0_a2_6)) + (portRef I1 (instanceRef un13_ciin_i_0_0_a3_6)) )) (net (rename A_DECODE_21 "A_DECODE[21]") (joined (portRef (member a_decode 2)) @@ -2436,7 +2425,7 @@ )) (net (rename A_DECODE_c_22 "A_DECODE_c[22]") (joined (portRef O (instanceRef A_DECODE_22)) - (portRef I1 (instanceRef un13_ciin_i_0_0_a2_11)) + (portRef I1 (instanceRef un13_ciin_i_0_0_a3_11)) )) (net (rename A_DECODE_22 "A_DECODE[22]") (joined (portRef (member a_decode 1)) @@ -2444,7 +2433,7 @@ )) (net (rename A_DECODE_c_23 "A_DECODE_c[23]") (joined (portRef O (instanceRef A_DECODE_23)) - (portRef I0 (instanceRef un13_ciin_i_0_0_a2_5)) + (portRef I0 (instanceRef un13_ciin_i_0_0_a3_5)) )) (net (rename A_DECODE_23 "A_DECODE[23]") (joined (portRef (member a_decode 0)) @@ -2461,7 +2450,7 @@ )) (net (rename A_c_1 "A_c[1]") (joined (portRef O (instanceRef A_1)) - (portRef I0 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2_0_a2)) + (portRef I0 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a3_0_a3)) (portRef I0 (instanceRef A_i_1)) )) (net (rename A_1 "A[1]") (joined @@ -2472,8 +2461,8 @@ (portRef O (instanceRef nEXP_SPACE)) (portRef I0 (instanceRef nEXP_SPACE_i)) (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_2_0)) - (portRef I1 (instanceRef pos_clk_un34_as_030_d0_i_i_a2)) - (portRef I0 (instanceRef pos_clk_un6_bg_030_0_a2_0_a2_1)) + (portRef I1 (instanceRef pos_clk_un34_as_030_d0_i_i_a3)) + (portRef I1 (instanceRef pos_clk_un6_bg_030_i_0)) (portRef OE (instanceRef DSACK1)) )) (net nEXP_SPACE (joined @@ -2512,9 +2501,9 @@ )) (net BGACK_000_c (joined (portRef O (instanceRef BGACK_000)) - (portRef I1 (instanceRef un21_berr_0_a2_0_a2_1)) - (portRef I0 (instanceRef BGACK_030_INT_0_m)) + (portRef I1 (instanceRef un21_berr_0_a3_0_a3_1)) (portRef I0 (instanceRef pos_clk_un6_bgack_000_0_0)) + (portRef I0 (instanceRef BGACK_030_INT_0_m)) )) (net BGACK_000 (joined (portRef BGACK_000) @@ -2522,7 +2511,7 @@ )) (net CLK_030_c (joined (portRef O (instanceRef CLK_030)) - (portRef I1 (instanceRef DS_000_DMA_2_sqmuxa_0_a2_i_a2)) + (portRef I1 (instanceRef DS_000_DMA_2_sqmuxa_i_0_a3)) (portRef I0 (instanceRef CLK_030_c_i)) )) (net CLK_030 (joined @@ -2554,7 +2543,6 @@ (portRef CLK (instanceRef CLK_000_D_2)) (portRef CLK (instanceRef CLK_000_D_3)) (portRef CLK (instanceRef CLK_000_D_4)) - (portRef CLK (instanceRef CLK_000_D_5)) (portRef CLK (instanceRef CLK_030_H)) (portRef CLK (instanceRef CLK_OUT_INT)) (portRef CLK (instanceRef CLK_OUT_PRE_50)) @@ -2620,7 +2608,7 @@ (net FPU_SENSE_c (joined (portRef O (instanceRef FPU_SENSE)) (portRef I0 (instanceRef FPU_SENSE_i)) - (portRef I1 (instanceRef un21_berr_0_a2_0_a2_1_0)) + (portRef I1 (instanceRef un21_berr_0_a3_0_a3_1_0)) )) (net FPU_SENSE (joined (portRef FPU_SENSE) @@ -2628,7 +2616,7 @@ )) (net (rename IPL_030_c_0 "IPL_030_c[0]") (joined (portRef Q (instanceRef IPL_030DFF_0)) - (portRef I0 (instanceRef IPL_030_0_0__n)) + (portRef I0 (instanceRef IPL_030_0_0__m)) (portRef I0 (instanceRef IPL_030_0)) )) (net (rename IPL_030_0 "IPL_030[0]") (joined @@ -2637,7 +2625,7 @@ )) (net (rename IPL_030_c_1 "IPL_030_c[1]") (joined (portRef Q (instanceRef IPL_030DFF_1)) - (portRef I0 (instanceRef IPL_030_0_1__n)) + (portRef I0 (instanceRef IPL_030_0_1__m)) (portRef I0 (instanceRef IPL_030_1)) )) (net (rename IPL_030_1 "IPL_030[1]") (joined @@ -2646,7 +2634,7 @@ )) (net (rename IPL_030_c_2 "IPL_030_c[2]") (joined (portRef Q (instanceRef IPL_030DFF_2)) - (portRef I0 (instanceRef IPL_030_0_2__n)) + (portRef I0 (instanceRef IPL_030_0_2__m)) (portRef I0 (instanceRef IPL_030_2)) )) (net (rename IPL_030_2 "IPL_030[2]") (joined @@ -2655,9 +2643,9 @@ )) (net (rename IPL_c_0 "IPL_c[0]") (joined (portRef O (instanceRef IPL_0)) - (portRef I0 (instanceRef IPL_030_0_0__m)) - (portRef I1 (instanceRef G_107)) - (portRef I0 (instanceRef IPL_c_i_0)) + (portRef I0 (instanceRef IPL_030_0_0__n)) + (portRef I0 (instanceRef IPL_i_0)) + (portRef I1 (instanceRef pos_clk_un1_ipl_i_0_x2)) )) (net (rename IPL_0 "IPL[0]") (joined (portRef (member ipl 2)) @@ -2665,9 +2653,9 @@ )) (net (rename IPL_c_1 "IPL_c[1]") (joined (portRef O (instanceRef IPL_1)) - (portRef I0 (instanceRef IPL_030_0_1__m)) - (portRef I1 (instanceRef G_108)) - (portRef I0 (instanceRef IPL_c_i_1)) + (portRef I0 (instanceRef IPL_030_0_1__n)) + (portRef I0 (instanceRef IPL_i_1)) + (portRef I1 (instanceRef pos_clk_un1_ipl_i_0_x2_0)) )) (net (rename IPL_1 "IPL[1]") (joined (portRef (member ipl 1)) @@ -2675,9 +2663,9 @@ )) (net (rename IPL_c_2 "IPL_c[2]") (joined (portRef O (instanceRef IPL_2)) - (portRef I0 (instanceRef IPL_030_0_2__m)) - (portRef I1 (instanceRef G_109)) - (portRef I0 (instanceRef IPL_c_i_2)) + (portRef I0 (instanceRef IPL_030_0_2__n)) + (portRef I0 (instanceRef IPL_i_2)) + (portRef I1 (instanceRef pos_clk_un1_ipl_i_0_x2_1)) )) (net (rename IPL_2 "IPL[2]") (joined (portRef (member ipl 0)) @@ -2717,53 +2705,53 @@ )) (net RST_c (joined (portRef O (instanceRef RST)) + (portRef I1 (instanceRef IPL_030_1_0)) + (portRef I1 (instanceRef DS_000_DMA_1)) + (portRef I1 (instanceRef AS_000_DMA_1)) (portRef I1 (instanceRef AS_030_000_SYNC_1)) - (portRef I1 (instanceRef RW_000_INT_1)) (portRef I1 (instanceRef RW_000_DMA_1)) (portRef I1 (instanceRef A0_DMA_1)) (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1)) (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1)) (portRef I1 (instanceRef BG_000_1)) - (portRef I1 (instanceRef AS_000_INT_0_i_0_a2_0)) - (portRef I1 (instanceRef AS_000_INT_0_i_0_a2)) - (portRef I1 (instanceRef SIZE_DMA_3_sqmuxa_0_a2_i)) + (portRef I1 (instanceRef IPL_030_1_2)) + (portRef I1 (instanceRef IPL_030_1_1)) + (portRef I1 (instanceRef RESET_OUT_2_0_0_a3)) + (portRef I1 (instanceRef IPL_D0_0_i_a3_0_a3_2)) + (portRef I1 (instanceRef IPL_D0_0_i_a3_0_a3_1)) + (portRef I1 (instanceRef IPL_D0_0_i_a3_0_a3_0)) + (portRef I1 (instanceRef SIZE_DMA_3_sqmuxa_0_a3_i)) (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_1)) (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_0)) - (portRef I1 (instanceRef RST_DLYlde_i_a2_i)) (portRef I1 (instanceRef AS_030_D0_0_0_0)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_o3)) + (portRef I1 (instanceRef AS_000_INT_0_i_0_a3)) + (portRef I1 (instanceRef AS_000_INT_0_i_0_a3_0)) + (portRef I1 (instanceRef DS_000_ENABLE_1)) (portRef I1 (instanceRef UDS_000_INT_1)) (portRef I1 (instanceRef LDS_000_INT_1)) - (portRef I1 (instanceRef RESET_OUT_2_i_i_a2)) - (portRef I1 (instanceRef DS_000_DMA_1)) - (portRef I1 (instanceRef AS_000_DMA_1)) (portRef I1 (instanceRef BGACK_030_INT_1)) - (portRef I1 (instanceRef DS_000_ENABLE_1)) + (portRef I1 (instanceRef DSACK1_INT_0_i_0_a3)) + (portRef I1 (instanceRef DSACK1_INT_0_i_0_a3_0)) (portRef I1 (instanceRef VMA_INT_1)) - (portRef I1 (instanceRef RESET_OUT_1_sqmuxa_i_0_117_1)) - (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_o2)) + (portRef I1 (instanceRef RST_DLYlde_0_0_o3)) (portRef I1 (instanceRef RST_DLY_e2_i_0_o2)) - (portRef I1 (instanceRef IPL_030_1_0)) - (portRef I1 (instanceRef IPL_030_1_1)) - (portRef I1 (instanceRef IPL_030_1_2)) - (portRef I1 (instanceRef DSACK1_INT_0_i_0_a2)) - (portRef I1 (instanceRef DSACK1_INT_0_i_0_a2_0)) + (portRef I1 (instanceRef RESET_OUT_1_sqmuxa_i_0_111_1)) + (portRef I1 (instanceRef RW_000_INT_1)) (portRef I0 (instanceRef VPA_D_0)) (portRef I1 (instanceRef DTACK_D0_0)) - (portRef I1 (instanceRef IPL_D0_0_0)) - (portRef I1 (instanceRef IPL_D0_0_1)) - (portRef I1 (instanceRef IPL_D0_0_2)) (portRef I1 (instanceRef RST_DLY_e1_i_0_2)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_3)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_2_1)) (portRef I1 (instanceRef RST_DLY_e2_i_0_2)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_4)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_6)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_0)) - (portRef I1 (instanceRef CLK_030_H_2_0_a2_i)) - (portRef I1 (instanceRef RST_DLY_e0_i_0)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_1)) - (portRef I1 (instanceRef RESET_OUT_2_i_i_a2_0)) (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_0)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_2)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_6)) + (portRef I1 (instanceRef RST_DLY_e0_i_0)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_i_2)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_3)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_4)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_0)) + (portRef I1 (instanceRef RESET_OUT_2_0_0_a3_0)) + (portRef I1 (instanceRef CLK_030_H_2_i_0_1)) )) (net RST (joined (portRef RST) @@ -2775,7 +2763,7 @@ )) (net RW_c (joined (portRef O (instanceRef RW)) - (portRef I1 (instanceRef un1_DS_000_ENABLE_0_sqmuxa_0_o2_0_a2)) + (portRef I1 (instanceRef un1_DS_000_ENABLE_0_sqmuxa_0_o3_0_a2)) (portRef I0 (instanceRef RW_c_i)) )) (net RW (joined @@ -2822,6 +2810,14 @@ (portRef O (instanceRef CIIN)) (portRef CIIN) )) + (net N_16_i (joined + (portRef O (instanceRef N_16_i)) + (portRef I0 (instanceRef RW_000_INT_1)) + )) + (net N_39_0 (joined + (portRef O (instanceRef RW_000_INT_1)) + (portRef I0 (instanceRef RW_000_INT_1_i)) + )) (net VPA_c_i (joined (portRef O (instanceRef VPA_c_i)) (portRef I1 (instanceRef VPA_D_0)) @@ -2838,242 +2834,199 @@ (portRef O (instanceRef DTACK_D0_0)) (portRef I0 (instanceRef DTACK_D0_0_i)) )) - (net (rename IPL_c_i_0 "IPL_c_i[0]") (joined - (portRef O (instanceRef IPL_c_i_0)) - (portRef I0 (instanceRef IPL_D0_0_0)) - )) - (net N_49_0 (joined - (portRef O (instanceRef IPL_D0_0_0)) - (portRef I0 (instanceRef IPL_D0_0_i_0)) - )) - (net (rename IPL_c_i_1 "IPL_c_i[1]") (joined - (portRef O (instanceRef IPL_c_i_1)) - (portRef I0 (instanceRef IPL_D0_0_1)) - )) - (net N_50_0 (joined - (portRef O (instanceRef IPL_D0_0_1)) - (portRef I0 (instanceRef IPL_D0_0_i_1)) - )) - (net (rename IPL_c_i_2 "IPL_c_i[2]") (joined - (portRef O (instanceRef IPL_c_i_2)) - (portRef I0 (instanceRef IPL_D0_0_2)) - )) - (net N_51_0 (joined - (portRef O (instanceRef IPL_D0_0_2)) - (portRef I0 (instanceRef IPL_D0_0_i_2)) - )) - (net N_25_i (joined - (portRef O (instanceRef N_25_i)) - (portRef I0 (instanceRef IPL_030_1_0)) - )) - (net N_28_0 (joined - (portRef O (instanceRef IPL_030_1_0)) - (portRef I0 (instanceRef IPL_030_1_i_0)) - )) - (net N_26_i (joined - (portRef O (instanceRef N_26_i)) - (portRef I0 (instanceRef IPL_030_1_1)) - )) - (net N_29_0 (joined - (portRef O (instanceRef IPL_030_1_1)) - (portRef I0 (instanceRef IPL_030_1_i_1)) - )) - (net N_27_i (joined - (portRef O (instanceRef N_27_i)) - (portRef I0 (instanceRef IPL_030_1_2)) - )) - (net N_30_0 (joined - (portRef O (instanceRef IPL_030_1_2)) - (portRef I0 (instanceRef IPL_030_1_i_2)) - )) - (net N_222_i (joined - (portRef O (instanceRef N_222_i)) + (net N_210_i (joined + (portRef O (instanceRef N_210_i)) (portRef I0 (instanceRef cpu_est_2_0_0_0_2)) (portRef I0 (instanceRef cpu_est_2_i_0_0_3)) )) - (net N_223_i (joined - (portRef O (instanceRef N_223_i)) + (net N_211_i (joined + (portRef O (instanceRef N_211_i)) (portRef I1 (instanceRef cpu_est_2_i_0_0_3)) )) - (net N_192_i (joined + (net N_189_i (joined (portRef O (instanceRef cpu_est_2_i_0_0_3)) (portRef I0 (instanceRef cpu_est_0_3__n)) )) - (net N_231_i (joined - (portRef O (instanceRef N_231_i)) - (portRef I0 (instanceRef DSACK1_INT_0_i_0)) + (net un1_SM_AMIGA_0_sqmuxa_1_0 (joined + (portRef O (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_1)) + (portRef I0 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_1_i)) )) - (net N_237_i (joined - (portRef O (instanceRef N_237_i)) - (portRef I1 (instanceRef DSACK1_INT_0_i_0)) + (net RW_c_i (joined + (portRef O (instanceRef RW_c_i)) + (portRef I1 (instanceRef pos_clk_RW_000_INT_5_i_a3_i)) )) - (net N_258_i (joined - (portRef O (instanceRef DSACK1_INT_0_i_0)) - (portRef D (instanceRef DSACK1_INT)) + (net N_311_0 (joined + (portRef O (instanceRef pos_clk_RW_000_INT_5_i_a3_i)) + (portRef I0 (instanceRef pos_clk_RW_000_INT_5_i_a3_i_i)) )) - (net N_342_i (joined - (portRef O (instanceRef N_342_i)) - (portRef I1 (instanceRef cpu_est_0_0_0)) + (net N_336_i (joined + (portRef O (instanceRef N_336_i)) + (portRef I1 (instanceRef cpu_est_0_0_x2_0_0)) )) - (net N_341_i (joined - (portRef O (instanceRef N_341_i)) - (portRef I0 (instanceRef cpu_est_0_0_0)) + (net N_244_i (joined + (portRef O (instanceRef N_244_i)) + (portRef I0 (instanceRef cpu_est_0_0_x2_0_0)) )) - (net N_226_i (joined - (portRef O (instanceRef cpu_est_0_0_0)) + (net N_91_i_i (joined + (portRef O (instanceRef cpu_est_0_0_x2_0_0)) (portRef D (instanceRef cpu_est_0)) )) - (net N_160_0 (joined + (net N_314_0 (joined (portRef O (instanceRef cpu_est_2_i_0_0_o2_3)) (portRef I0 (instanceRef cpu_est_2_i_0_0_o2_i_3)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_1_1_3)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_1_3)) )) - (net N_164_i (joined + (net N_159_i (joined (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_0_o2)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_1_1_3)) - (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_0_a2_1)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_1_3)) + (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_0_a3_1)) )) (net VMA_INT_i (joined (portRef O (instanceRef VMA_INT_i)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_1_2_3)) - )) - (net N_347_i (joined - (portRef O (instanceRef N_347_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_0_1_3)) - )) - (net N_348_i (joined - (portRef O (instanceRef N_348_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_0_3)) - )) - (net N_188_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_0_3)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_0_i_3)) - )) - (net N_245_0 (joined - (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_o2)) - (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_o2_i)) - (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_2)) - (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_1_i)) - )) - (net N_194_0 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_1)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_1)) - )) - (net N_196_0 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_2)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_2)) - )) - (net N_232_i (joined - (portRef O (instanceRef RST_DLY_e2_i_0)) - (portRef D (instanceRef RST_DLY_2)) - )) - (net N_211_i (joined - (portRef O (instanceRef N_211_i)) - (portRef I1 (instanceRef RST_DLY_e2_i_0_1)) - )) - (net N_209_i (joined - (portRef O (instanceRef N_209_i)) - (portRef I0 (instanceRef RST_DLY_e2_i_0_1)) - )) - (net N_306_i (joined - (portRef O (instanceRef N_306_i)) - (portRef I0 (instanceRef RST_DLY_e2_i_0_2)) - )) - (net N_193_0 (joined - (portRef O (instanceRef un5_e_0_i_o2_0)) - (portRef I0 (instanceRef un5_e_0_i_o2_0_i)) - )) - (net N_190_0 (joined - (portRef O (instanceRef un5_e_0_i_o2)) - (portRef I0 (instanceRef un5_e_0_i_o2_i)) - )) - (net N_183_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_0)) - (portRef I0 (instanceRef DSACK1_INT_0_i_0_a2)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_0)) - )) - (net N_162_i (joined - (portRef O (instanceRef cpu_est_2_0_0_0_o2_2)) - (portRef I0 (instanceRef cpu_est_2_0_0_a2_0_2)) - (portRef I0 (instanceRef cpu_est_2_0_0_0_o2_i_2)) - )) - (net N_346_i (joined - (portRef O (instanceRef N_346_i)) - (portRef I0 (instanceRef RST_DLY_e2_i_0_o2)) - )) - (net N_159_0 (joined - (portRef O (instanceRef RST_DLY_e2_i_0_o2)) - (portRef I0 (instanceRef RST_DLY_e2_i_0_o2_i)) - )) - (net N_305_i (joined - (portRef O (instanceRef CLK_000_NE_0_o3_i_a2_0_o2_i_o2)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_4)) - (portRef I0 (instanceRef RST_DLY_e2_i_0_a2_3)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_3)) - (portRef I0 (instanceRef cpu_est_0_0_a2_0_0)) - (portRef I0 (instanceRef CLK_000_NE_0_o3_i_a2_0_o2_i_o2_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_1_2)) - (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_0_a2_0_1)) - (portRef I0 (instanceRef RESET_OUT_2_i_i_a2_0_1)) - )) - (net N_210_i (joined - (portRef O (instanceRef RESET_OUT_1_sqmuxa_i_0_117_1)) - (portRef I1 (instanceRef RST_DLY_e2_i_0_a2_1_0)) - (portRef I0 (instanceRef RST_DLY_e1_i_0_a2_1_1)) - )) - (net N_225_i (joined - (portRef O (instanceRef N_225_i)) - (portRef I1 (instanceRef un5_e_0_i)) - )) - (net N_224_i (joined - (portRef O (instanceRef N_224_i)) - (portRef I0 (instanceRef un5_e_0_i)) - )) - (net N_296_i (joined - (portRef O (instanceRef un5_e_0_i)) - (portRef I0 (instanceRef E)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_2_3)) )) (net N_352_i (joined (portRef O (instanceRef N_352_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_0_1_3)) + )) + (net N_353_i (joined + (portRef O (instanceRef N_353_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_0_3)) + )) + (net N_293_i (joined + (portRef O (instanceRef N_293_i)) + (portRef I0 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_1_o3)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_1_0)) + )) + (net N_175_i (joined + (portRef O (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_1_o3)) + (portRef I1 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_1)) + (portRef I0 (instanceRef pos_clk_RW_000_INT_5_i_a3_i)) + )) + (net N_176_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_0_3)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_0_i_3)) + )) + (net N_234_i (joined + (portRef O (instanceRef RST_DLY_e2_i_0)) + (portRef D (instanceRef RST_DLY_2)) + )) + (net N_198_i (joined + (portRef O (instanceRef N_198_i)) + (portRef I0 (instanceRef RST_DLY_e2_i_0_2)) + )) + (net N_197_i (joined + (portRef O (instanceRef N_197_i)) + (portRef I1 (instanceRef RST_DLY_e2_i_0_1)) + )) + (net N_196_i (joined + (portRef O (instanceRef N_196_i)) + (portRef I0 (instanceRef RST_DLY_e2_i_0_1)) + )) + (net N_183_0 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_4)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_4)) + )) + (net N_182_0 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_i_i_o2_2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_i_o2_i_2)) + )) + (net N_180_0 (joined + (portRef O (instanceRef un5_e_0_i_o2_0)) + (portRef I0 (instanceRef un5_e_0_i_o2_0_i)) + )) + (net N_178_0 (joined + (portRef O (instanceRef un5_e_0_i_o2)) + (portRef I0 (instanceRef un5_e_0_i_o2_i)) + )) + (net N_82_i (joined + (portRef O (instanceRef RST_DLYlde_0_0_o3)) + (portRef I0 (instanceRef RST_DLY_e1_i_0_a3_0)) + (portRef I0 (instanceRef RST_DLY_e0_i_0_a3_0)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_5)) + )) + (net N_315_i (joined + (portRef O (instanceRef cpu_est_2_0_0_0_o2_2)) + (portRef I0 (instanceRef cpu_est_2_0_0_0_a2_2)) + (portRef I0 (instanceRef cpu_est_2_0_0_0_o2_i_2)) + )) + (net N_351_i (joined + (portRef O (instanceRef N_351_i)) + (portRef I0 (instanceRef RST_DLY_e2_i_0_o2)) + )) + (net N_154_0 (joined + (portRef O (instanceRef RST_DLY_e2_i_0_o2)) + (portRef I0 (instanceRef RST_DLY_e2_i_0_o2_i)) + )) + (net N_149_i (joined + (portRef O (instanceRef N_155_i_0_o2_i_o2_i_o2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_0)) + (portRef I0 (instanceRef RST_DLY_e2_i_0_a2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a3_3)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_4)) + (portRef I0 (instanceRef cpu_est_0_0_x2_0_a3_0_0)) + (portRef I0 (instanceRef N_155_i_0_o2_i_o2_i_o2_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_i_o2_1_2)) + (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_0_a3_0_1)) + (portRef I0 (instanceRef RESET_OUT_2_0_0_a3_0_1)) + )) + (net N_207_i (joined + (portRef O (instanceRef RESET_OUT_1_sqmuxa_i_0_111_1)) + (portRef I1 (instanceRef RST_DLY_e2_i_0_a3_1_0)) + (portRef I0 (instanceRef RST_DLY_e1_i_0_a3_1_1)) + )) + (net N_228_i (joined + (portRef O (instanceRef N_228_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_5)) + )) + (net N_146_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_5)) + (portRef D (instanceRef SM_AMIGA_5)) + )) + (net N_213_i (joined + (portRef O (instanceRef N_213_i)) + (portRef I1 (instanceRef un5_e_0_i)) + )) + (net N_212_i (joined + (portRef O (instanceRef N_212_i)) + (portRef I0 (instanceRef un5_e_0_i)) + )) + (net N_309_i (joined + (portRef O (instanceRef un5_e_0_i)) + (portRef I0 (instanceRef E)) + )) + (net N_357_i (joined + (portRef O (instanceRef N_357_i)) (portRef I1 (instanceRef cpu_est_2_0_0_0_2)) )) (net (rename cpu_est_2_0_2 "cpu_est_2_0[2]") (joined (portRef O (instanceRef cpu_est_2_0_0_0_2)) (portRef I0 (instanceRef cpu_est_2_0_0_0_i_2)) )) - (net N_220_i (joined - (portRef O (instanceRef N_220_i)) + (net N_208_i (joined + (portRef O (instanceRef N_208_i)) (portRef I0 (instanceRef cpu_est_2_0_0_0_1)) )) - (net N_221_i (joined - (portRef O (instanceRef N_221_i)) + (net N_209_i (joined + (portRef O (instanceRef N_209_i)) (portRef I1 (instanceRef cpu_est_2_0_0_0_1)) )) (net (rename cpu_est_2_0_1 "cpu_est_2_0[1]") (joined (portRef O (instanceRef cpu_est_2_0_0_0_1)) (portRef I0 (instanceRef cpu_est_2_0_0_0_i_1)) )) - (net N_219_i (joined - (portRef O (instanceRef N_219_i)) + (net N_206_i (joined + (portRef O (instanceRef N_206_i)) (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_0)) )) - (net N_218_i (joined - (portRef O (instanceRef N_218_i)) + (net N_205_i (joined + (portRef O (instanceRef N_205_i)) (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_0)) )) (net (rename pos_clk_un9_clk_000_pe_0 "pos_clk.un9_clk_000_pe_0") (joined (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_0)) (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_0_i)) )) - (net (rename CLK_000_D_i_2 "CLK_000_D_i[2]") (joined - (portRef O (instanceRef CLK_000_D_i_2)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_o3_0_1)) - )) - (net N_157_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_o3_0_1)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_1)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_0)) - )) (net N_18_i (joined (portRef O (instanceRef N_18_i)) (portRef I0 (instanceRef VMA_INT_1)) @@ -3082,105 +3035,23 @@ (portRef O (instanceRef VMA_INT_1)) (portRef I0 (instanceRef VMA_INT_1_i)) )) - (net N_235_i (joined - (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i_0)) - (portRef D (instanceRef CYCLE_DMA_0)) + (net N_171_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_3)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_3)) )) - (net N_217_i (joined - (portRef O (instanceRef N_217_i)) - (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_2)) + (net N_354_i (joined + (portRef O (instanceRef N_354_i)) + (portRef I1 (instanceRef un1_DS_000_ENABLE_0_sqmuxa_0_o3_0_o3)) )) - (net N_216_i (joined - (portRef O (instanceRef N_216_i)) - (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_1)) + (net un1_DS_000_ENABLE_0_sqmuxa_0 (joined + (portRef O (instanceRef un1_DS_000_ENABLE_0_sqmuxa_0_o3_0_o3)) + (portRef I1 (instanceRef DS_000_ENABLE_1_sqmuxa_i_0)) + (portRef I0 (instanceRef un1_DS_000_ENABLE_0_sqmuxa_0_o3_0_o3_i)) )) - (net CLK_030_c_i (joined - (portRef O (instanceRef CLK_030_c_i)) - (portRef I0 (instanceRef AS_000_DMA_1_sqmuxa_0_a2_i)) - (portRef I1 (instanceRef CLK_030_H_2_0_a2_i_o2)) - )) - (net N_198_0 (joined - (portRef O (instanceRef CLK_030_H_2_0_a2_i_o2)) - (portRef I0 (instanceRef CLK_030_H_2_0_a2_i_o2_i)) - )) - (net N_166_i (joined - (portRef O (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_1_o2)) - (portRef I0 (instanceRef AS_000_INT_0_i_0_a2_0)) - (portRef I0 (instanceRef un1_DS_000_ENABLE_0_sqmuxa_0_o2_0_a2)) - (portRef I0 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_1_o2_i)) - )) - (net N_155_i (joined - (portRef O (instanceRef N_261_i_0_o2)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_3)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_0_0)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_0)) - (portRef I1 (instanceRef G_102)) - (portRef I1 (instanceRef pos_clk_un6_bgack_000_0_0_a2)) - (portRef I0 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_1_o2)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_1)) - (portRef I0 (instanceRef N_261_i_0_o2_i)) - (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_0_a2_1)) - )) - (net N_303_0 (joined - (portRef O (instanceRef AS_000_DMA_1_sqmuxa_0_a2_i)) - (portRef I0 (instanceRef AS_000_DMA_1_sqmuxa_0_a2_i_i)) - )) - (net N_291_i (joined - (portRef O (instanceRef N_291_i)) - (portRef I1 (instanceRef pos_clk_DS_000_DMA_4_f0_i_a2_i)) - )) - (net N_301_0 (joined - (portRef O (instanceRef pos_clk_DS_000_DMA_4_f0_i_a2_i)) - (portRef I0 (instanceRef pos_clk_DS_000_DMA_4_f0_i_a2_i_i)) - )) - (net N_256_i (joined - (portRef O (instanceRef N_256_i)) - (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0)) - )) - (net N_248_i (joined - (portRef O (instanceRef N_248_i)) - (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0)) - )) - (net AMIGA_BUS_DATA_DIR_c_0 (joined - (portRef O (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0)) - (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_i)) - )) - (net N_353_i (joined - (portRef O (instanceRef N_353_i)) - (portRef I1 (instanceRef pos_clk_un6_bgack_000_0_0)) - )) - (net (rename pos_clk_un6_bgack_000_0 "pos_clk.un6_bgack_000_0") (joined - (portRef O (instanceRef pos_clk_un6_bgack_000_0_0)) - (portRef I0 (instanceRef pos_clk_un6_bgack_000_0_0_i)) - )) - (net N_65_0 (joined + (net N_66_0 (joined (portRef O (instanceRef DS_000_ENABLE_1_sqmuxa_i_0)) (portRef I0 (instanceRef DS_000_ENABLE_1_sqmuxa_i_0_i)) )) - (net N_3_i (joined - (portRef O (instanceRef N_3_i)) - (portRef I0 (instanceRef DS_000_DMA_1)) - )) - (net N_45_0 (joined - (portRef O (instanceRef DS_000_DMA_1)) - (portRef I0 (instanceRef DS_000_DMA_1_i)) - )) - (net N_4_i (joined - (portRef O (instanceRef N_4_i)) - (portRef I0 (instanceRef AS_000_DMA_1)) - )) - (net N_44_0 (joined - (portRef O (instanceRef AS_000_DMA_1)) - (portRef I0 (instanceRef AS_000_DMA_1_i)) - )) - (net N_8_i (joined - (portRef O (instanceRef N_8_i)) - (portRef I0 (instanceRef BGACK_030_INT_1)) - )) - (net N_42_0 (joined - (portRef O (instanceRef BGACK_030_INT_1)) - (portRef I0 (instanceRef BGACK_030_INT_1_i)) - )) (net UDS_000_INT_i (joined (portRef O (instanceRef UDS_000_INT_i)) (portRef I1 (instanceRef un1_UDS_000_INT)) @@ -3213,6 +3084,14 @@ (portRef O (instanceRef LDS_000_INT_1)) (portRef I0 (instanceRef LDS_000_INT_1_i)) )) + (net N_8_i (joined + (portRef O (instanceRef N_8_i)) + (portRef I0 (instanceRef BGACK_030_INT_1)) + )) + (net N_42_0 (joined + (portRef O (instanceRef BGACK_030_INT_1)) + (portRef I0 (instanceRef BGACK_030_INT_1_i)) + )) (net (rename A_c_i_0 "A_c_i[0]") (joined (portRef O (instanceRef A_c_i_0)) (portRef I1 (instanceRef pos_clk_un10_sm_amiga_1)) @@ -3225,126 +3104,171 @@ (portRef O (instanceRef pos_clk_un10_sm_amiga)) (portRef I0 (instanceRef LDS_000_INT_0_m)) )) - (net un1_as_000_i (joined - (portRef O (instanceRef un1_as_000_0_0)) - (portRef OE (instanceRef AS_000)) - (portRef OE (instanceRef LDS_000)) - (portRef OE (instanceRef RW_000)) - (portRef OE (instanceRef UDS_000)) + (net N_359_i (joined + (portRef O (instanceRef N_359_i)) + (portRef I1 (instanceRef pos_clk_un6_bgack_000_0_0)) )) - (net un10_ciin_i (joined - (portRef O (instanceRef un10_ciin_i)) - (portRef I1 (instanceRef un13_ciin_i_0_0)) + (net (rename pos_clk_un6_bgack_000_0 "pos_clk.un6_bgack_000_0") (joined + (portRef O (instanceRef pos_clk_un6_bgack_000_0_0)) + (portRef I0 (instanceRef pos_clk_un6_bgack_000_0_0_i)) )) - (net N_260_0 (joined - (portRef O (instanceRef un13_ciin_i_0_0)) - (portRef I0 (instanceRef un13_ciin_i_0_0_i)) + (net N_220_i (joined + (portRef O (instanceRef N_220_i)) + (portRef I1 (instanceRef DSACK1_INT_0_i_0)) )) - (net N_229_i (joined - (portRef O (instanceRef N_229_i)) - (portRef I0 (instanceRef RESET_OUT_2_i_i)) + (net N_219_i (joined + (portRef O (instanceRef N_219_i)) + (portRef I0 (instanceRef DSACK1_INT_0_i_0)) )) - (net N_230_i (joined - (portRef O (instanceRef N_230_i)) - (portRef I1 (instanceRef RESET_OUT_2_i_i)) + (net N_248_i (joined + (portRef O (instanceRef DSACK1_INT_0_i_0)) + (portRef D (instanceRef DSACK1_INT)) )) - (net N_298_0 (joined - (portRef O (instanceRef RESET_OUT_2_i_i)) - (portRef I0 (instanceRef RESET_OUT_2_i_i_i)) + (net N_222_i (joined + (portRef O (instanceRef N_222_i)) + (portRef I1 (instanceRef AS_000_INT_0_i_0)) )) - (net N_48_0 (joined - (portRef O (instanceRef AS_030_D0_0_0_0)) - (portRef I0 (instanceRef AS_030_D0_0_0_0_i)) + (net N_221_i (joined + (portRef O (instanceRef N_221_i)) + (portRef I0 (instanceRef AS_000_INT_0_i_0)) )) - (net N_299_i (joined - (portRef O (instanceRef un2_as_030_i_a2_i)) - (portRef OE (instanceRef SIZE_0)) - (portRef OE (instanceRef SIZE_1)) + (net N_247_i (joined + (portRef O (instanceRef AS_000_INT_0_i_0)) + (portRef D (instanceRef AS_000_INT)) )) - (net N_345_i (joined - (portRef O (instanceRef N_345_i)) - (portRef I0 (instanceRef pos_clk_un21_bgack_030_int_i_i_a2_i_o2_2)) + (net N_223_i (joined + (portRef O (instanceRef N_223_i)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0)) )) - (net N_349_i (joined - (portRef O (instanceRef N_349_i)) - (portRef I1 (instanceRef un1_DS_000_ENABLE_0_sqmuxa_0_o2_0_o2)) + (net N_224_i (joined + (portRef O (instanceRef N_224_i)) + (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0)) )) - (net un1_DS_000_ENABLE_0_sqmuxa_i (joined - (portRef O (instanceRef un1_DS_000_ENABLE_0_sqmuxa_0_o2_0_o2)) - (portRef I1 (instanceRef DS_000_ENABLE_1_sqmuxa_i_0)) - (portRef I0 (instanceRef un1_DS_000_ENABLE_0_sqmuxa_0_o2_0_o2_i)) - )) - (net N_180_i (joined - (portRef O (instanceRef pos_clk_un21_bgack_030_int_i_i_a2_i_o2)) - (portRef I1 (instanceRef AS_000_DMA_1_sqmuxa_0_a2_i)) - (portRef I0 (instanceRef pos_clk_DS_000_DMA_4_f0_i_a2_i)) - (portRef I0 (instanceRef pos_clk_un21_bgack_030_int_i_i_a2_i_o2_i)) - (portRef I0 (instanceRef CLK_030_H_2_0_a2_i_1)) - (portRef I0 (instanceRef DS_000_DMA_2_sqmuxa_0_a2_i_1)) - )) - (net N_181_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_3)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_3)) - )) - (net N_326_i (joined - (portRef O (instanceRef N_326_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_5)) + (net AMIGA_BUS_DATA_DIR_c_0 (joined + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_i)) )) (net N_150_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_5)) - (portRef D (instanceRef SM_AMIGA_5)) + (portRef O (instanceRef pos_clk_un1_ipl_i_0_o3)) + (portRef I1 (instanceRef G_96)) + (portRef I0 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_1_o2)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_a3_0_0)) + (portRef I1 (instanceRef pos_clk_un6_bgack_000_0_0_a2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_3)) + (portRef I0 (instanceRef pos_clk_un1_ipl_i_0_o3_i)) + (portRef I0 (instanceRef pos_clk_un1_ipl_i_0_1)) + (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_0_a3_1)) )) - (net N_186_i (joined - (portRef O (instanceRef RST_DLYlde_i_a2_i)) - (portRef I0 (instanceRef RST_DLY_e0_i_0_a2_0)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_5)) - (portRef I0 (instanceRef RST_DLY_e1_i_0_a2_0)) + (net N_156_i (joined + (portRef O (instanceRef pos_clk_un34_as_030_d0_i_i_o2)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d0_i_i_o2_i)) + (portRef I1 (instanceRef un21_berr_0_a3_0_a3)) + (portRef I1 (instanceRef un21_fpu_cs_0_a3_0_a3)) )) - (net N_163_i (joined + (net N_160_i (joined + (portRef O (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_1_o2)) + (portRef I0 (instanceRef AS_000_INT_0_i_0_a3_0)) + (portRef I0 (instanceRef un1_DS_000_ENABLE_0_sqmuxa_0_o3_0_a2)) + (portRef I0 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_1_o2_i)) + )) + (net N_174_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_0)) + (portRef I0 (instanceRef DSACK1_INT_0_i_0_a3_0)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_0)) + )) + (net N_158_i (joined (portRef O (instanceRef RST_DLY_e2_i_0_o2_0)) - (portRef I0 (instanceRef RESET_OUT_1_sqmuxa_i_0_117_1_a2)) - (portRef I1 (instanceRef RST_DLY_e1_i_0_a2)) + (portRef I1 (instanceRef RST_DLY_e1_i_0_a3)) + (portRef I0 (instanceRef RESET_OUT_1_sqmuxa_i_0_111_1_a2)) (portRef I0 (instanceRef RST_DLY_e2_i_0_o2_0_i)) )) - (net N_197_0 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_4)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_4)) - )) - (net N_213_i (joined - (portRef O (instanceRef N_213_i)) + (net N_201_i (joined + (portRef O (instanceRef N_201_i)) (portRef I0 (instanceRef RST_DLY_e1_i_0_1)) )) - (net N_214_i (joined - (portRef O (instanceRef N_214_i)) + (net N_202_i (joined + (portRef O (instanceRef N_202_i)) (portRef I1 (instanceRef RST_DLY_e1_i_0_1)) )) - (net N_215_i (joined - (portRef O (instanceRef N_215_i)) + (net N_203_i (joined + (portRef O (instanceRef N_203_i)) (portRef I0 (instanceRef RST_DLY_e1_i_0_2)) )) - (net N_233_i (joined + (net N_235_i (joined (portRef O (instanceRef RST_DLY_e1_i_0)) (portRef D (instanceRef RST_DLY_1)) )) - (net N_199_i (joined - (portRef O (instanceRef pos_clk_un5_bgack_030_int_d_i_0_a2_i_o2)) - (portRef I0 (instanceRef SIZE_DMA_3_sqmuxa_0_a2_i)) - (portRef I0 (instanceRef pos_clk_un5_bgack_030_int_d_i_0_a2_i_o2_i)) - (portRef I0 (instanceRef pos_clk_un34_as_030_d0_i_i_a2_2)) + (net N_233_0 (joined + (portRef O (instanceRef pos_clk_un1_ipl_i_0)) + (portRef I0 (instanceRef pos_clk_un1_ipl_i_0_i)) )) - (net N_191_0 (joined + (net N_360_i (joined + (portRef O (instanceRef N_360_i)) + (portRef I1 (instanceRef pos_clk_un1_ipl_i_0_2)) + )) + (net N_191_i_i (joined + (portRef O (instanceRef N_191_i_i)) + (portRef I1 (instanceRef pos_clk_un1_ipl_i_0_1)) + )) + (net N_192_i_i (joined + (portRef O (instanceRef N_192_i_i)) + (portRef I0 (instanceRef pos_clk_un1_ipl_i_0_2)) + )) + (net N_59_i (joined + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i_0)) + (portRef D (instanceRef CYCLE_DMA_0)) + )) + (net N_199_i (joined + (portRef O (instanceRef N_199_i)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_1)) + )) + (net N_204_i (joined + (portRef O (instanceRef N_204_i)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_2)) + )) + (net N_138_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1)) + (portRef D (instanceRef SM_AMIGA_1)) + )) + (net N_282_i (joined + (portRef O (instanceRef N_282_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_2_1)) + )) + (net N_278_i (joined + (portRef O (instanceRef N_278_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_1_1)) + )) + (net N_186_i (joined + (portRef O (instanceRef un2_as_030_i_a2_i_o3)) + (portRef I0 (instanceRef un4_as_030_i_a3_i)) + (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_a3_0_1)) + (portRef OE (instanceRef SIZE_0)) + (portRef OE (instanceRef SIZE_1)) + )) + (net N_185_i (joined + (portRef O (instanceRef pos_clk_un5_bgack_030_int_d_i_0_a2_i_o3)) + (portRef I0 (instanceRef SIZE_DMA_3_sqmuxa_0_a3_i)) + (portRef I0 (instanceRef pos_clk_un5_bgack_030_int_d_i_0_a2_i_o3_i)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d0_i_i_a3_2)) + )) + (net CLK_030_c_i (joined + (portRef O (instanceRef CLK_030_c_i)) + (portRef I0 (instanceRef AS_000_DMA_1_sqmuxa_i_0)) + (portRef I1 (instanceRef CLK_030_H_2_i_0_o2)) + )) + (net N_184_0 (joined + (portRef O (instanceRef CLK_030_H_2_i_0_o2)) + (portRef I0 (instanceRef CLK_030_H_2_i_0_o2_i)) + )) + (net N_179_0 (joined (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_6)) (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_6)) )) - (net N_275_i (joined - (portRef O (instanceRef N_275_i)) - (portRef I0 (instanceRef pos_clk_RW_000_INT_5_0_0_o2)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_1_0)) - )) - (net N_187_0 (joined - (portRef O (instanceRef pos_clk_RW_000_INT_5_0_0_o2)) - (portRef I1 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_1)) - (portRef I0 (instanceRef pos_clk_RW_000_INT_5_0_0)) + (net N_251_i (joined + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_o3)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_o3_i)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_2)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_1_i_0)) )) (net LDS_000_c_i (joined (portRef O (instanceRef LDS_000_c_i)) @@ -3354,186 +3278,265 @@ (portRef O (instanceRef UDS_000_c_i)) (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_o2_0)) )) - (net N_184_i (joined + (net N_172_i (joined (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0_o2_0)) - (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_a2_1)) + (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_a3_1)) (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_o2_i_0)) )) - (net (rename CLK_000_D_i_4 "CLK_000_D_i[4]") (joined - (portRef O (instanceRef CLK_000_D_i_4)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_2_0)) + (net (rename pos_clk_un21_bgack_030_int_i_0_0 "pos_clk.un21_bgack_030_int_i_0_0") (joined + (portRef O (instanceRef pos_clk_un21_bgack_030_int_i_0_o3_0_o3)) + (portRef I1 (instanceRef AS_000_DMA_1_sqmuxa_i_0)) + (portRef I1 (instanceRef pos_clk_DS_000_DMA_4_f0_0_0)) + (portRef I0 (instanceRef pos_clk_un21_bgack_030_int_i_0_o3_0_o3_i)) + (portRef I1 (instanceRef DS_000_DMA_2_sqmuxa_i_0)) + (portRef I1 (instanceRef CLK_030_H_2_i_0)) )) - (net N_171_i (joined + (net N_163_i (joined (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_o2_0)) (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_6)) (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_i_0)) )) - (net AS_030_000_SYNC_i (joined - (portRef O (instanceRef AS_030_000_SYNC_i)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_1_0)) + (net (rename CLK_000_D_i_3 "CLK_000_D_i[3]") (joined + (portRef O (instanceRef CLK_000_D_i_3)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_2_0)) )) - (net N_161_i (joined - (portRef O (instanceRef pos_clk_un34_as_030_d0_i_i_o2)) - (portRef I0 (instanceRef pos_clk_un34_as_030_d0_i_i_o2_i)) - (portRef I1 (instanceRef un21_berr_0_a2_0_a2)) - (portRef I1 (instanceRef un21_fpu_cs_0_a2_0_a2)) + (net N_350_i (joined + (portRef O (instanceRef N_350_i)) + (portRef I1 (instanceRef pos_clk_un21_bgack_030_int_i_0_o3_0_o3_2)) )) - (net N_136_i (joined - (portRef O (instanceRef pos_clk_CYCLE_DMA_5_1_i)) - (portRef D (instanceRef CYCLE_DMA_1)) + (net un1_rw_i (joined + (portRef O (instanceRef un1_rw_0)) + (portRef OE (instanceRef RW)) )) - (net N_113_0 (joined - (portRef O (instanceRef SIZE_DMA_3_sqmuxa_0_a2_i)) - (portRef I0 (instanceRef SIZE_DMA_3_sqmuxa_0_a2_i_i)) + (net N_126_0 (joined + (portRef O (instanceRef SIZE_DMA_3_sqmuxa_0_a3_i)) + (portRef I0 (instanceRef SIZE_DMA_3_sqmuxa_0_a3_i_i)) )) - (net N_338_i (joined - (portRef O (instanceRef N_338_i)) + (net N_313_i (joined + (portRef O (instanceRef un4_as_030_i_a3_i)) + (portRef OE (instanceRef AHIGH_24)) + (portRef OE (instanceRef AHIGH_25)) + (portRef OE (instanceRef AHIGH_26)) + (portRef OE (instanceRef AHIGH_27)) + (portRef OE (instanceRef AHIGH_28)) + (portRef OE (instanceRef AHIGH_29)) + (portRef OE (instanceRef AHIGH_30)) + (portRef OE (instanceRef AHIGH_31)) + (portRef OE (instanceRef AS_030)) + (portRef OE (instanceRef A_0)) + (portRef OE (instanceRef DS_030)) + )) + (net N_231_i (joined + (portRef O (instanceRef pos_clk_un6_bg_030_i_0)) + (portRef I0 (instanceRef pos_clk_un6_bg_030_i_0_i)) + )) + (net N_291_i (joined + (portRef O (instanceRef N_291_i)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_1_0)) + )) + (net N_152_i (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_0)) + (portRef D (instanceRef SM_AMIGA_i_7)) + )) + (net N_288_i (joined + (portRef O (instanceRef N_288_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_1_4)) + )) + (net N_144_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_4)) + (portRef D (instanceRef SM_AMIGA_4)) + )) + (net N_287_i (joined + (portRef O (instanceRef N_287_i)) (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_1_3)) )) - (net N_339_i (joined - (portRef O (instanceRef N_339_i)) + (net N_340_i (joined + (portRef O (instanceRef N_340_i)) (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_1_3)) )) - (net N_146_i (joined + (net N_142_i (joined (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_3)) (portRef D (instanceRef SM_AMIGA_3)) )) - (net N_335_i (joined - (portRef O (instanceRef N_335_i)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_1_1)) + (net N_284_i (joined + (portRef O (instanceRef N_284_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_i_1_2)) )) - (net N_336_i (joined - (portRef O (instanceRef N_336_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_1_1)) + (net N_312_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_i_i_2)) + (portRef D (instanceRef SM_AMIGA_2)) )) - (net N_142_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1)) - (portRef D (instanceRef SM_AMIGA_1)) - )) - (net N_334_i (joined - (portRef O (instanceRef N_334_i)) + (net N_275_i (joined + (portRef O (instanceRef N_275_i)) (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_1)) )) (net (rename pos_clk_SIZE_DMA_6_0_1 "pos_clk.SIZE_DMA_6_0[1]") (joined (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0_1)) (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_i_1)) )) - (net N_333_i (joined - (portRef O (instanceRef N_333_i)) + (net N_268_i (joined + (portRef O (instanceRef N_268_i)) (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_0)) )) (net (rename pos_clk_SIZE_DMA_6_0_0 "pos_clk.SIZE_DMA_6_0[0]") (joined (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0_0)) (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_i_0)) )) - (net N_295_i (joined - (portRef O (instanceRef N_295_i)) + (net N_265_i (joined + (portRef O (instanceRef N_265_i)) (portRef I0 (instanceRef RST_DLY_e0_i_0_1)) )) - (net N_332_i (joined - (portRef O (instanceRef N_332_i)) - (portRef I1 (instanceRef RST_DLY_e0_i_0_1)) - )) - (net N_234_i (joined - (portRef O (instanceRef RST_DLY_e0_i_0)) - (portRef D (instanceRef RST_DLY_0)) - )) - (net N_292_i (joined - (portRef O (instanceRef N_292_i)) - (portRef I1 (instanceRef DS_000_DMA_2_sqmuxa_0_a2_i_1)) - )) - (net N_302_0 (joined - (portRef O (instanceRef DS_000_DMA_2_sqmuxa_0_a2_i)) - (portRef I0 (instanceRef DS_000_DMA_2_sqmuxa_0_a2_i_i)) - )) - (net N_300_0 (joined - (portRef O (instanceRef pos_clk_RW_000_DMA_3_i_a2_i)) - (portRef I0 (instanceRef pos_clk_RW_000_DMA_3_i_a2_i_i)) - )) - (net N_290_i (joined - (portRef O (instanceRef N_290_i)) - (portRef I1 (instanceRef CLK_030_H_2_0_a2_i_1)) - )) - (net N_63_i (joined - (portRef O (instanceRef CLK_030_H_2_0_a2_i)) - (portRef D (instanceRef CLK_030_H)) - )) - (net N_273_i (joined - (portRef O (instanceRef N_273_i)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_1_0)) - )) - (net N_154_i (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_0)) - (portRef D (instanceRef SM_AMIGA_i_7)) - )) - (net N_327_i (joined - (portRef O (instanceRef N_327_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_1_6)) - )) - (net N_152_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_6)) - (portRef D (instanceRef SM_AMIGA_6)) - )) - (net N_270_i (joined - (portRef O (instanceRef N_270_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_1_4)) - )) - (net N_148_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_4)) - (portRef D (instanceRef SM_AMIGA_4)) - )) - (net N_269_i (joined - (portRef O (instanceRef N_269_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_1_2)) - )) - (net N_144_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_2)) - (portRef D (instanceRef SM_AMIGA_2)) - )) (net N_267_i (joined (portRef O (instanceRef N_267_i)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_1_0)) + (portRef I1 (instanceRef RST_DLY_e0_i_0_1)) )) - (net N_324_i (joined - (portRef O (instanceRef N_324_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_1_0)) + (net N_236_i (joined + (portRef O (instanceRef RST_DLY_e0_i_0)) + (portRef D (instanceRef RST_DLY_0)) )) - (net N_140_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_0)) - (portRef D (instanceRef SM_AMIGA_0)) + (net N_337_i (joined + (portRef O (instanceRef N_337_i)) + (portRef I0 (instanceRef RESET_OUT_2_0_0)) )) - (net un1_SM_AMIGA_0_sqmuxa_1_0 (joined - (portRef O (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_1)) - (portRef I0 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_1_i)) + (net N_338_i (joined + (portRef O (instanceRef N_338_i)) + (portRef I1 (instanceRef RESET_OUT_2_0_0)) )) - (net N_319_i (joined - (portRef O (instanceRef N_319_i)) - (portRef I0 (instanceRef AS_000_INT_0_i_0)) + (net N_55_0 (joined + (portRef O (instanceRef RESET_OUT_2_0_0)) + (portRef I0 (instanceRef RESET_OUT_2_0_0_i)) )) - (net N_320_i (joined - (portRef O (instanceRef N_320_i)) - (portRef I1 (instanceRef AS_000_INT_0_i_0)) + (net un1_as_000_i (joined + (portRef O (instanceRef un1_as_000_0_0)) + (portRef OE (instanceRef AS_000)) + (portRef OE (instanceRef LDS_000)) + (portRef OE (instanceRef RW_000)) + (portRef OE (instanceRef UDS_000)) )) - (net N_257_i (joined - (portRef O (instanceRef AS_000_INT_0_i_0)) - (portRef D (instanceRef AS_000_INT)) + (net N_245_0 (joined + (portRef O (instanceRef AS_000_DMA_1_sqmuxa_i_0)) + (portRef I0 (instanceRef AS_000_DMA_1_sqmuxa_i_0_i)) )) - (net RW_c_i (joined - (portRef O (instanceRef RW_c_i)) - (portRef I1 (instanceRef pos_clk_RW_000_INT_5_0_0)) + (net N_229_i (joined + (portRef O (instanceRef N_229_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_1_6)) )) - (net (rename pos_clk_RW_000_INT_5_0 "pos_clk.RW_000_INT_5_0") (joined - (portRef O (instanceRef pos_clk_RW_000_INT_5_0_0)) - (portRef I0 (instanceRef pos_clk_RW_000_INT_5_0_0_i)) + (net N_148_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_6)) + (portRef D (instanceRef SM_AMIGA_6)) )) (net N_227_i (joined (portRef O (instanceRef N_227_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_1_0)) + )) + (net N_136_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_0)) + (portRef D (instanceRef SM_AMIGA_0)) + )) + (net N_226_i (joined + (portRef O (instanceRef N_226_i)) + (portRef I0 (instanceRef DS_000_DMA_2_sqmuxa_i_0_1)) + )) + (net N_246_0 (joined + (portRef O (instanceRef DS_000_DMA_2_sqmuxa_i_0)) + (portRef I0 (instanceRef DS_000_DMA_2_sqmuxa_i_0_i)) + )) + (net N_332_i (joined + (portRef O (instanceRef N_332_i)) + (portRef I0 (instanceRef pos_clk_DS_000_DMA_4_f0_0_0)) + )) + (net (rename pos_clk_DS_000_DMA_4_0 "pos_clk.DS_000_DMA_4_0") (joined + (portRef O (instanceRef pos_clk_DS_000_DMA_4_f0_0_0)) + (portRef I0 (instanceRef pos_clk_DS_000_DMA_4_f0_0_0_i)) + )) + (net N_48_0 (joined + (portRef O (instanceRef AS_030_D0_0_0_0)) + (portRef I0 (instanceRef AS_030_D0_0_0_0_i)) + )) + (net (rename pos_clk_RW_000_DMA_3_0 "pos_clk.RW_000_DMA_3_0") (joined + (portRef O (instanceRef pos_clk_RW_000_DMA_3_0_0)) + (portRef I0 (instanceRef pos_clk_RW_000_DMA_3_0_0_i)) + )) + (net N_218_i (joined + (portRef O (instanceRef N_218_i)) + (portRef I0 (instanceRef CLK_030_H_2_i_0_1)) + )) + (net N_249_i (joined + (portRef O (instanceRef CLK_030_H_2_i_0)) + (portRef D (instanceRef CLK_030_H)) + )) + (net N_57_i (joined + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_1_i_0)) + (portRef D (instanceRef CYCLE_DMA_1)) + )) + (net un10_ciin_i (joined + (portRef O (instanceRef un10_ciin_i)) + (portRef I1 (instanceRef un13_ciin_i_0_0)) + )) + (net N_62_0 (joined + (portRef O (instanceRef un13_ciin_i_0_0)) + (portRef I0 (instanceRef un13_ciin_i_0_0_i)) + )) + (net N_215_i (joined + (portRef O (instanceRef N_215_i)) + (portRef I0 (instanceRef un10_amiga_bus_enable_high_0_0)) + )) + (net N_216_i (joined + (portRef O (instanceRef N_216_i)) + (portRef I1 (instanceRef un10_amiga_bus_enable_high_0_0)) + )) + (net un10_amiga_bus_enable_high_i (joined + (portRef O (instanceRef un10_amiga_bus_enable_high_0_0)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_HIGH)) + )) + (net N_214_i (joined + (portRef O (instanceRef N_214_i)) (portRef I1 (instanceRef pos_clk_un34_as_030_d0_i_i)) )) - (net N_297_0 (joined + (net N_310_0 (joined (portRef O (instanceRef pos_clk_un34_as_030_d0_i_i)) (portRef I0 (instanceRef pos_clk_un34_as_030_d0_i_i_i)) )) + (net N_24_i (joined + (portRef O (instanceRef N_24_i)) + (portRef I0 (instanceRef IPL_030_1_2)) + )) + (net N_33_0 (joined + (portRef O (instanceRef IPL_030_1_2)) + (portRef I0 (instanceRef IPL_030_1_i_2)) + )) + (net N_23_i (joined + (portRef O (instanceRef N_23_i)) + (portRef I0 (instanceRef IPL_030_1_1)) + )) + (net N_32_0 (joined + (portRef O (instanceRef IPL_030_1_1)) + (portRef I0 (instanceRef IPL_030_1_i_1)) + )) + (net N_22_i (joined + (portRef O (instanceRef N_22_i)) + (portRef I0 (instanceRef IPL_030_1_0)) + )) + (net N_31_0 (joined + (portRef O (instanceRef IPL_030_1_0)) + (portRef I0 (instanceRef IPL_030_1_i_0)) + )) + (net N_3_i (joined + (portRef O (instanceRef N_3_i)) + (portRef I0 (instanceRef DS_000_DMA_1)) + )) + (net N_45_0 (joined + (portRef O (instanceRef DS_000_DMA_1)) + (portRef I0 (instanceRef DS_000_DMA_1_i)) + )) + (net N_4_i (joined + (portRef O (instanceRef N_4_i)) + (portRef I0 (instanceRef AS_000_DMA_1)) + )) + (net N_44_0 (joined + (portRef O (instanceRef AS_000_DMA_1)) + (portRef I0 (instanceRef AS_000_DMA_1_i)) + )) (net N_15_i (joined (portRef O (instanceRef N_15_i)) (portRef I0 (instanceRef AS_030_000_SYNC_1)) @@ -3542,14 +3545,6 @@ (portRef O (instanceRef AS_030_000_SYNC_1)) (portRef I0 (instanceRef AS_030_000_SYNC_1_i)) )) - (net N_16_i (joined - (portRef O (instanceRef N_16_i)) - (portRef I0 (instanceRef RW_000_INT_1)) - )) - (net N_39_0 (joined - (portRef O (instanceRef RW_000_INT_1)) - (portRef I0 (instanceRef RW_000_INT_1_i)) - )) (net N_19_i (joined (portRef O (instanceRef N_19_i)) (portRef I0 (instanceRef RW_000_DMA_1)) @@ -3566,27 +3561,27 @@ (portRef O (instanceRef A0_DMA_1)) (portRef I0 (instanceRef A0_DMA_1_i)) )) - (net N_22_i (joined - (portRef O (instanceRef N_22_i)) + (net N_25_i (joined + (portRef O (instanceRef N_25_i)) (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1)) )) - (net N_33_0 (joined + (net N_30_0 (joined (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1)) (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1_i)) )) - (net N_23_i (joined - (portRef O (instanceRef N_23_i)) + (net N_26_i (joined + (portRef O (instanceRef N_26_i)) (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1)) )) - (net N_32_0 (joined + (net N_29_0 (joined (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1)) (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1_i)) )) - (net N_24_i (joined - (portRef O (instanceRef N_24_i)) + (net N_27_i (joined + (portRef O (instanceRef N_27_i)) (portRef I0 (instanceRef BG_000_1)) )) - (net N_31_0 (joined + (net N_28_0 (joined (portRef O (instanceRef BG_000_1)) (portRef I0 (instanceRef BG_000_1_i)) )) @@ -3594,281 +3589,249 @@ (portRef O (instanceRef BG_030_c_i)) (portRef I0 (instanceRef pos_clk_un9_bg_030)) )) - (net (rename pos_clk_un6_bg_030_i "pos_clk.un6_bg_030_i") (joined - (portRef O (instanceRef pos_clk_un6_bg_030_i)) - (portRef I1 (instanceRef pos_clk_un9_bg_030)) - )) (net (rename pos_clk_un9_bg_030_0 "pos_clk.un9_bg_030_0") (joined (portRef O (instanceRef pos_clk_un9_bg_030)) (portRef I0 (instanceRef pos_clk_un9_bg_030_i)) )) - (net N_161_i_1 (joined - (portRef O (instanceRef pos_clk_un34_as_030_d0_i_i_o2_1)) - (portRef I0 (instanceRef pos_clk_un34_as_030_d0_i_i_o2_4)) - )) - (net N_161_i_2 (joined - (portRef O (instanceRef pos_clk_un34_as_030_d0_i_i_o2_2)) - (portRef I1 (instanceRef pos_clk_un34_as_030_d0_i_i_o2_4)) - )) - (net N_161_i_3 (joined - (portRef O (instanceRef pos_clk_un34_as_030_d0_i_i_o2_3)) - (portRef I1 (instanceRef pos_clk_un34_as_030_d0_i_i_o2)) - )) - (net N_161_i_4 (joined - (portRef O (instanceRef pos_clk_un34_as_030_d0_i_i_o2_4)) - (portRef I0 (instanceRef pos_clk_un34_as_030_d0_i_i_o2)) - )) - (net N_233_i_1 (joined + (net N_235_i_1 (joined (portRef O (instanceRef RST_DLY_e1_i_0_1)) (portRef I0 (instanceRef RST_DLY_e1_i_0)) )) - (net N_233_i_2 (joined + (net N_235_i_2 (joined (portRef O (instanceRef RST_DLY_e1_i_0_2)) (portRef I1 (instanceRef RST_DLY_e1_i_0)) )) - (net N_180_i_1 (joined - (portRef O (instanceRef pos_clk_un21_bgack_030_int_i_i_a2_i_o2_1)) - (portRef I0 (instanceRef pos_clk_un21_bgack_030_int_i_i_a2_i_o2)) + (net N_156_i_1 (joined + (portRef O (instanceRef pos_clk_un34_as_030_d0_i_i_o2_1)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d0_i_i_o2_4)) )) - (net N_180_i_2 (joined - (portRef O (instanceRef pos_clk_un21_bgack_030_int_i_i_a2_i_o2_2)) - (portRef I1 (instanceRef pos_clk_un21_bgack_030_int_i_i_a2_i_o2)) + (net N_156_i_2 (joined + (portRef O (instanceRef pos_clk_un34_as_030_d0_i_i_o2_2)) + (portRef I1 (instanceRef pos_clk_un34_as_030_d0_i_i_o2_4)) + )) + (net N_156_i_3 (joined + (portRef O (instanceRef pos_clk_un34_as_030_d0_i_i_o2_3)) + (portRef I1 (instanceRef pos_clk_un34_as_030_d0_i_i_o2)) + )) + (net N_156_i_4 (joined + (portRef O (instanceRef pos_clk_un34_as_030_d0_i_i_o2_4)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d0_i_i_o2)) )) (net (rename pos_clk_un10_sm_amiga_i_1 "pos_clk.un10_sm_amiga_i_1") (joined (portRef O (instanceRef pos_clk_un10_sm_amiga_1)) (portRef I0 (instanceRef pos_clk_un10_sm_amiga)) )) - (net N_196_0_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_1_2)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_2)) - )) - (net N_188_i_1 (joined + (net N_176_i_1 (joined (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_0_1_3)) (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_0_3)) )) (net un10_ciin_1 (joined - (portRef O (instanceRef un13_ciin_i_0_0_a2_1)) - (portRef I0 (instanceRef un13_ciin_i_0_0_a2_7)) + (portRef O (instanceRef un13_ciin_i_0_0_a3_1)) + (portRef I0 (instanceRef un13_ciin_i_0_0_a3_7)) )) (net un10_ciin_2 (joined - (portRef O (instanceRef un13_ciin_i_0_0_a2_2)) - (portRef I1 (instanceRef un13_ciin_i_0_0_a2_7)) + (portRef O (instanceRef un13_ciin_i_0_0_a3_2)) + (portRef I1 (instanceRef un13_ciin_i_0_0_a3_7)) )) (net un10_ciin_3 (joined - (portRef O (instanceRef un13_ciin_i_0_0_a2_3)) - (portRef I0 (instanceRef un13_ciin_i_0_0_a2_8)) + (portRef O (instanceRef un13_ciin_i_0_0_a3_3)) + (portRef I0 (instanceRef un13_ciin_i_0_0_a3_8)) )) (net un10_ciin_4 (joined - (portRef O (instanceRef un13_ciin_i_0_0_a2_4)) - (portRef I1 (instanceRef un13_ciin_i_0_0_a2_8)) + (portRef O (instanceRef un13_ciin_i_0_0_a3_4)) + (portRef I1 (instanceRef un13_ciin_i_0_0_a3_8)) )) (net un10_ciin_5 (joined - (portRef O (instanceRef un13_ciin_i_0_0_a2_5)) - (portRef I0 (instanceRef un13_ciin_i_0_0_a2_9)) + (portRef O (instanceRef un13_ciin_i_0_0_a3_5)) + (portRef I0 (instanceRef un13_ciin_i_0_0_a3_9)) )) (net un10_ciin_6 (joined - (portRef O (instanceRef un13_ciin_i_0_0_a2_6)) - (portRef I1 (instanceRef un13_ciin_i_0_0_a2_9)) + (portRef O (instanceRef un13_ciin_i_0_0_a3_6)) + (portRef I1 (instanceRef un13_ciin_i_0_0_a3_9)) )) (net un10_ciin_7 (joined - (portRef O (instanceRef un13_ciin_i_0_0_a2_7)) - (portRef I0 (instanceRef un13_ciin_i_0_0_a2_10)) + (portRef O (instanceRef un13_ciin_i_0_0_a3_7)) + (portRef I0 (instanceRef un13_ciin_i_0_0_a3_10)) )) (net un10_ciin_8 (joined - (portRef O (instanceRef un13_ciin_i_0_0_a2_8)) - (portRef I1 (instanceRef un13_ciin_i_0_0_a2_10)) + (portRef O (instanceRef un13_ciin_i_0_0_a3_8)) + (portRef I1 (instanceRef un13_ciin_i_0_0_a3_10)) )) (net un10_ciin_9 (joined - (portRef O (instanceRef un13_ciin_i_0_0_a2_9)) - (portRef I0 (instanceRef un13_ciin_i_0_0_a2_11)) + (portRef O (instanceRef un13_ciin_i_0_0_a3_9)) + (portRef I0 (instanceRef un13_ciin_i_0_0_a3_11)) )) (net un10_ciin_10 (joined - (portRef O (instanceRef un13_ciin_i_0_0_a2_10)) - (portRef I0 (instanceRef un13_ciin_i_0_0_a2)) + (portRef O (instanceRef un13_ciin_i_0_0_a3_10)) + (portRef I0 (instanceRef un13_ciin_i_0_0_a3)) )) (net un10_ciin_11 (joined - (portRef O (instanceRef un13_ciin_i_0_0_a2_11)) - (portRef I1 (instanceRef un13_ciin_i_0_0_a2)) + (portRef O (instanceRef un13_ciin_i_0_0_a3_11)) + (portRef I1 (instanceRef un13_ciin_i_0_0_a3)) )) - (net N_171_i_1 (joined + (net N_163_i_1 (joined (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_o2_1_0)) (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_0)) )) - (net N_171_i_2 (joined + (net N_163_i_2 (joined (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_o2_2_0)) (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_0)) )) - (net N_227_1 (joined - (portRef O (instanceRef pos_clk_un34_as_030_d0_i_i_a2_1)) - (portRef I0 (instanceRef pos_clk_un34_as_030_d0_i_i_a2_3)) + (net (rename pos_clk_un21_bgack_030_int_i_0_0_1 "pos_clk.un21_bgack_030_int_i_0_0_1") (joined + (portRef O (instanceRef pos_clk_un21_bgack_030_int_i_0_o3_0_o3_1)) + (portRef I0 (instanceRef pos_clk_un21_bgack_030_int_i_0_o3_0_o3)) )) - (net N_227_2 (joined - (portRef O (instanceRef pos_clk_un34_as_030_d0_i_i_a2_2)) - (portRef I1 (instanceRef pos_clk_un34_as_030_d0_i_i_a2_3)) + (net (rename pos_clk_un21_bgack_030_int_i_0_0_2 "pos_clk.un21_bgack_030_int_i_0_0_2") (joined + (portRef O (instanceRef pos_clk_un21_bgack_030_int_i_0_o3_0_o3_2)) + (portRef I1 (instanceRef pos_clk_un21_bgack_030_int_i_0_o3_0_o3)) )) - (net N_227_3 (joined - (portRef O (instanceRef pos_clk_un34_as_030_d0_i_i_a2_3)) - (portRef I0 (instanceRef pos_clk_un34_as_030_d0_i_i_a2)) - )) - (net un21_fpu_cs_1 (joined - (portRef O (instanceRef un21_fpu_cs_0_a2_0_a2_1)) - (portRef I0 (instanceRef un21_fpu_cs_0_a2_0_a2)) - )) - (net un21_berr_1_0 (joined - (portRef O (instanceRef un21_berr_0_a2_0_a2_1_0)) - (portRef I0 (instanceRef un21_berr_0_a2_0_a2)) - )) - (net N_235_i_1 (joined - (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_1)) - (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i_0)) - )) - (net N_235_i_2 (joined - (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_2)) - (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i_0)) - )) - (net N_256_1 (joined - (portRef O (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_a2_0_1)) - (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_a2_0)) - )) - (net N_256_2 (joined - (portRef O (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_a2_0_2)) - (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_a2_0)) - )) - (net N_232_i_1 (joined - (portRef O (instanceRef RST_DLY_e2_i_0_1)) - (portRef I0 (instanceRef RST_DLY_e2_i_0)) - )) - (net N_232_i_2 (joined - (portRef O (instanceRef RST_DLY_e2_i_0_2)) - (portRef I1 (instanceRef RST_DLY_e2_i_0)) - )) - (net N_219_1 (joined - (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_0_a2_0_1)) - (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_0_a2_0)) - )) - (net N_219_2 (joined - (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_0_a2_0_2)) - (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_0_a2_0)) - )) - (net N_218_1 (joined - (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_0_a2_1)) - (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_0_a2)) - )) - (net N_218_2 (joined - (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_0_a2_2)) - (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_0_a2)) - )) - (net N_347_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_1_1_3)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_1_3)) - )) - (net N_347_2 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_1_2_3)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_1_3)) - )) - (net N_136_i_1 (joined - (portRef O (instanceRef pos_clk_CYCLE_DMA_5_1_i_1)) - (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_1_i)) - )) - (net N_146_i_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1_3)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_3)) - )) - (net N_142_i_1 (joined + (net N_138_i_1 (joined (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1_1)) (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_1)) )) + (net N_138_i_2 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_2_1)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_1)) + )) + (net N_59_i_1 (joined + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_1)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i_0)) + )) + (net N_59_i_2 (joined + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_2)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i_0)) + )) + (net N_233_0_1 (joined + (portRef O (instanceRef pos_clk_un1_ipl_i_0_1)) + (portRef I0 (instanceRef pos_clk_un1_ipl_i_0)) + )) + (net N_233_0_2 (joined + (portRef O (instanceRef pos_clk_un1_ipl_i_0_2)) + (portRef I1 (instanceRef pos_clk_un1_ipl_i_0)) + )) + (net N_214_1 (joined + (portRef O (instanceRef pos_clk_un34_as_030_d0_i_i_a3_1)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d0_i_i_a3_3)) + )) + (net N_214_2 (joined + (portRef O (instanceRef pos_clk_un34_as_030_d0_i_i_a3_2)) + (portRef I1 (instanceRef pos_clk_un34_as_030_d0_i_i_a3_3)) + )) + (net N_214_3 (joined + (portRef O (instanceRef pos_clk_un34_as_030_d0_i_i_a3_3)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d0_i_i_a3)) + )) + (net un21_fpu_cs_1 (joined + (portRef O (instanceRef un21_fpu_cs_0_a3_0_a3_1)) + (portRef I0 (instanceRef un21_fpu_cs_0_a3_0_a3)) + )) + (net un21_berr_1_0 (joined + (portRef O (instanceRef un21_berr_0_a3_0_a3_1_0)) + (portRef I0 (instanceRef un21_berr_0_a3_0_a3)) + )) + (net N_182_0_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_i_i_o2_1_2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_i_o2_2)) + )) (net N_234_i_1 (joined - (portRef O (instanceRef RST_DLY_e0_i_0_1)) - (portRef I0 (instanceRef RST_DLY_e0_i_0)) + (portRef O (instanceRef RST_DLY_e2_i_0_1)) + (portRef I0 (instanceRef RST_DLY_e2_i_0)) )) - (net N_302_0_1 (joined - (portRef O (instanceRef DS_000_DMA_2_sqmuxa_0_a2_i_1)) - (portRef I0 (instanceRef DS_000_DMA_2_sqmuxa_0_a2_i)) + (net N_234_i_2 (joined + (portRef O (instanceRef RST_DLY_e2_i_0_2)) + (portRef I1 (instanceRef RST_DLY_e2_i_0)) )) - (net N_63_i_1 (joined - (portRef O (instanceRef CLK_030_H_2_0_a2_i_1)) - (portRef I0 (instanceRef CLK_030_H_2_0_a2_i)) + (net N_206_1 (joined + (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_0_a3_0_1)) + (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_0_a3_0)) )) - (net N_154_i_1 (joined + (net N_206_2 (joined + (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_0_a3_0_2)) + (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_0_a3_0)) + )) + (net N_205_1 (joined + (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_0_a3_1)) + (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_0_a3)) + )) + (net N_205_2 (joined + (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_0_a3_2)) + (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_0_a3)) + )) + (net N_352_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_1_3)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_3)) + )) + (net N_352_2 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_2_3)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_3)) + )) + (net N_231_i_1 (joined + (portRef O (instanceRef pos_clk_un6_bg_030_i_0_1)) + (portRef I0 (instanceRef pos_clk_un6_bg_030_i_0)) + )) + (net N_152_i_1 (joined (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_1_0)) (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_0)) )) - (net N_152_i_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1_6)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_6)) - )) - (net N_148_i_1 (joined + (net N_144_i_1 (joined (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1_4)) (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_4)) )) - (net N_144_i_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1_2)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_2)) + (net N_142_i_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1_3)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_3)) )) - (net N_140_i_1 (joined + (net N_312_i_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_i_i_1_2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_i_2)) + )) + (net N_236_i_1 (joined + (portRef O (instanceRef RST_DLY_e0_i_0_1)) + (portRef I0 (instanceRef RST_DLY_e0_i_0)) + )) + (net N_148_i_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1_6)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_6)) + )) + (net N_136_i_1 (joined (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1_0)) (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_0)) )) - (net (rename pos_clk_un6_bg_030_1 "pos_clk.un6_bg_030_1") (joined - (portRef O (instanceRef pos_clk_un6_bg_030_0_a2_0_a2_1)) - (portRef I0 (instanceRef pos_clk_un6_bg_030_0_a2_0_a2)) + (net N_246_0_1 (joined + (portRef O (instanceRef DS_000_DMA_2_sqmuxa_i_0_1)) + (portRef I0 (instanceRef DS_000_DMA_2_sqmuxa_i_0)) )) - (net N_230_1 (joined - (portRef O (instanceRef RESET_OUT_2_i_i_a2_0_1)) - (portRef I0 (instanceRef RESET_OUT_2_i_i_a2_0)) + (net N_249_i_1 (joined + (portRef O (instanceRef CLK_030_H_2_i_0_1)) + (portRef I0 (instanceRef CLK_030_H_2_i_0)) )) - (net N_221_1 (joined - (portRef O (instanceRef cpu_est_2_0_0_a2_0_1_1)) - (portRef I0 (instanceRef cpu_est_2_0_0_a2_0_1)) + (net N_57_i_1 (joined + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_1_i_0_1)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_1_i_0)) )) - (net N_215_1 (joined - (portRef O (instanceRef RST_DLY_e1_i_0_a2_1_1)) - (portRef I0 (instanceRef RST_DLY_e1_i_0_a2_1)) + (net N_338_1 (joined + (portRef O (instanceRef RESET_OUT_2_0_0_a3_0_1)) + (portRef I0 (instanceRef RESET_OUT_2_0_0_a3_0)) )) - (net N_306_1 (joined - (portRef O (instanceRef RST_DLY_e2_i_0_a2_1_0)) - (portRef I0 (instanceRef RST_DLY_e2_i_0_a2)) + (net N_224_1 (joined + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_a3_0_1)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_a3_0)) )) - (net (rename pos_clk_ipl_1 "pos_clk.ipl_1") (joined - (portRef O (instanceRef G_110_1)) - (portRef I0 (instanceRef G_110)) + (net N_216_1 (joined + (portRef O (instanceRef un10_amiga_bus_enable_high_0_0_a3_0_1)) + (portRef I0 (instanceRef un10_amiga_bus_enable_high_0_0_a3_0)) )) - (net (rename IPL_030_0_2__un3 "IPL_030_0_2_.un3") (joined - (portRef O (instanceRef IPL_030_0_2__r)) - (portRef I1 (instanceRef IPL_030_0_2__n)) + (net N_209_1 (joined + (portRef O (instanceRef cpu_est_2_0_0_a3_1_1_1)) + (portRef I0 (instanceRef cpu_est_2_0_0_a3_1_1)) )) - (net (rename IPL_030_0_2__un1 "IPL_030_0_2_.un1") (joined - (portRef O (instanceRef IPL_030_0_2__m)) - (portRef I0 (instanceRef IPL_030_0_2__p)) + (net N_203_1 (joined + (portRef O (instanceRef RST_DLY_e1_i_0_a3_1_1)) + (portRef I0 (instanceRef RST_DLY_e1_i_0_a3_1)) )) - (net (rename IPL_030_0_2__un0 "IPL_030_0_2_.un0") (joined - (portRef O (instanceRef IPL_030_0_2__n)) - (portRef I1 (instanceRef IPL_030_0_2__p)) - )) - (net (rename IPL_030_0_1__un3 "IPL_030_0_1_.un3") (joined - (portRef O (instanceRef IPL_030_0_1__r)) - (portRef I1 (instanceRef IPL_030_0_1__n)) - )) - (net (rename IPL_030_0_1__un1 "IPL_030_0_1_.un1") (joined - (portRef O (instanceRef IPL_030_0_1__m)) - (portRef I0 (instanceRef IPL_030_0_1__p)) - )) - (net (rename IPL_030_0_1__un0 "IPL_030_0_1_.un0") (joined - (portRef O (instanceRef IPL_030_0_1__n)) - (portRef I1 (instanceRef IPL_030_0_1__p)) - )) - (net (rename IPL_030_0_0__un3 "IPL_030_0_0_.un3") (joined - (portRef O (instanceRef IPL_030_0_0__r)) - (portRef I1 (instanceRef IPL_030_0_0__n)) - )) - (net (rename IPL_030_0_0__un1 "IPL_030_0_0_.un1") (joined - (portRef O (instanceRef IPL_030_0_0__m)) - (portRef I0 (instanceRef IPL_030_0_0__p)) - )) - (net (rename IPL_030_0_0__un0 "IPL_030_0_0_.un0") (joined - (portRef O (instanceRef IPL_030_0_0__n)) - (portRef I1 (instanceRef IPL_030_0_0__p)) + (net N_196_1 (joined + (portRef O (instanceRef RST_DLY_e2_i_0_a3_1_0)) + (portRef I0 (instanceRef RST_DLY_e2_i_0_a3)) )) (net (rename cpu_est_0_3__un3 "cpu_est_0_3_.un3") (joined (portRef O (instanceRef cpu_est_0_3__r)) @@ -3882,6 +3845,18 @@ (portRef O (instanceRef cpu_est_0_3__n)) (portRef I1 (instanceRef cpu_est_0_3__p)) )) + (net (rename RW_000_INT_0_un3 "RW_000_INT_0.un3") (joined + (portRef O (instanceRef RW_000_INT_0_r)) + (portRef I1 (instanceRef RW_000_INT_0_n)) + )) + (net (rename RW_000_INT_0_un1 "RW_000_INT_0.un1") (joined + (portRef O (instanceRef RW_000_INT_0_m)) + (portRef I0 (instanceRef RW_000_INT_0_p)) + )) + (net (rename RW_000_INT_0_un0 "RW_000_INT_0.un0") (joined + (portRef O (instanceRef RW_000_INT_0_n)) + (portRef I1 (instanceRef RW_000_INT_0_p)) + )) (net (rename VMA_INT_0_un3 "VMA_INT_0.un3") (joined (portRef O (instanceRef VMA_INT_0_r)) (portRef I1 (instanceRef VMA_INT_0_n)) @@ -3918,29 +3893,29 @@ (portRef O (instanceRef cpu_est_0_2__n)) (portRef I1 (instanceRef cpu_est_0_2__p)) )) - (net (rename DS_000_DMA_0_un3 "DS_000_DMA_0.un3") (joined - (portRef O (instanceRef DS_000_DMA_0_r)) - (portRef I1 (instanceRef DS_000_DMA_0_n)) + (net (rename UDS_000_INT_0_un3 "UDS_000_INT_0.un3") (joined + (portRef O (instanceRef UDS_000_INT_0_r)) + (portRef I1 (instanceRef UDS_000_INT_0_n)) )) - (net (rename DS_000_DMA_0_un1 "DS_000_DMA_0.un1") (joined - (portRef O (instanceRef DS_000_DMA_0_m)) - (portRef I0 (instanceRef DS_000_DMA_0_p)) + (net (rename UDS_000_INT_0_un1 "UDS_000_INT_0.un1") (joined + (portRef O (instanceRef UDS_000_INT_0_m)) + (portRef I0 (instanceRef UDS_000_INT_0_p)) )) - (net (rename DS_000_DMA_0_un0 "DS_000_DMA_0.un0") (joined - (portRef O (instanceRef DS_000_DMA_0_n)) - (portRef I1 (instanceRef DS_000_DMA_0_p)) + (net (rename UDS_000_INT_0_un0 "UDS_000_INT_0.un0") (joined + (portRef O (instanceRef UDS_000_INT_0_n)) + (portRef I1 (instanceRef UDS_000_INT_0_p)) )) - (net (rename AS_000_DMA_0_un3 "AS_000_DMA_0.un3") (joined - (portRef O (instanceRef AS_000_DMA_0_r)) - (portRef I1 (instanceRef AS_000_DMA_0_n)) + (net (rename LDS_000_INT_0_un3 "LDS_000_INT_0.un3") (joined + (portRef O (instanceRef LDS_000_INT_0_r)) + (portRef I1 (instanceRef LDS_000_INT_0_n)) )) - (net (rename AS_000_DMA_0_un1 "AS_000_DMA_0.un1") (joined - (portRef O (instanceRef AS_000_DMA_0_m)) - (portRef I0 (instanceRef AS_000_DMA_0_p)) + (net (rename LDS_000_INT_0_un1 "LDS_000_INT_0.un1") (joined + (portRef O (instanceRef LDS_000_INT_0_m)) + (portRef I0 (instanceRef LDS_000_INT_0_p)) )) - (net (rename AS_000_DMA_0_un0 "AS_000_DMA_0.un0") (joined - (portRef O (instanceRef AS_000_DMA_0_n)) - (portRef I1 (instanceRef AS_000_DMA_0_p)) + (net (rename LDS_000_INT_0_un0 "LDS_000_INT_0.un0") (joined + (portRef O (instanceRef LDS_000_INT_0_n)) + (portRef I1 (instanceRef LDS_000_INT_0_p)) )) (net (rename BGACK_030_INT_0_un3 "BGACK_030_INT_0.un3") (joined (portRef O (instanceRef BGACK_030_INT_0_r)) @@ -3966,66 +3941,6 @@ (portRef O (instanceRef DS_000_ENABLE_0_n)) (portRef I1 (instanceRef DS_000_ENABLE_0_p)) )) - (net (rename UDS_000_INT_0_un3 "UDS_000_INT_0.un3") (joined - (portRef O (instanceRef UDS_000_INT_0_r)) - (portRef I1 (instanceRef UDS_000_INT_0_n)) - )) - (net (rename UDS_000_INT_0_un1 "UDS_000_INT_0.un1") (joined - (portRef O (instanceRef UDS_000_INT_0_m)) - (portRef I0 (instanceRef UDS_000_INT_0_p)) - )) - (net (rename UDS_000_INT_0_un0 "UDS_000_INT_0.un0") (joined - (portRef O (instanceRef UDS_000_INT_0_n)) - (portRef I1 (instanceRef UDS_000_INT_0_p)) - )) - (net (rename LDS_000_INT_0_un3 "LDS_000_INT_0.un3") (joined - (portRef O (instanceRef LDS_000_INT_0_r)) - (portRef I1 (instanceRef LDS_000_INT_0_n)) - )) - (net (rename LDS_000_INT_0_un1 "LDS_000_INT_0.un1") (joined - (portRef O (instanceRef LDS_000_INT_0_m)) - (portRef I0 (instanceRef LDS_000_INT_0_p)) - )) - (net (rename LDS_000_INT_0_un0 "LDS_000_INT_0.un0") (joined - (portRef O (instanceRef LDS_000_INT_0_n)) - (portRef I1 (instanceRef LDS_000_INT_0_p)) - )) - (net (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__un3 "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.un3") (joined - (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__r)) - (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__n)) - )) - (net (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__un1 "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.un1") (joined - (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__m)) - (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__p)) - )) - (net (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__un0 "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.un0") (joined - (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__n)) - (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__p)) - )) - (net (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_un3 "AMIGA_BUS_ENABLE_DMA_HIGH_0.un3") (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_r)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_n)) - )) - (net (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_un1 "AMIGA_BUS_ENABLE_DMA_HIGH_0.un1") (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_m)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_p)) - )) - (net (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_un0 "AMIGA_BUS_ENABLE_DMA_HIGH_0.un0") (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_n)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_p)) - )) - (net (rename BG_000_0_un3 "BG_000_0.un3") (joined - (portRef O (instanceRef BG_000_0_r)) - (portRef I1 (instanceRef BG_000_0_n)) - )) - (net (rename BG_000_0_un1 "BG_000_0.un1") (joined - (portRef O (instanceRef BG_000_0_m)) - (portRef I0 (instanceRef BG_000_0_p)) - )) - (net (rename BG_000_0_un0 "BG_000_0.un0") (joined - (portRef O (instanceRef BG_000_0_n)) - (portRef I1 (instanceRef BG_000_0_p)) - )) (net (rename SIZE_DMA_0_0__un3 "SIZE_DMA_0_0_.un3") (joined (portRef O (instanceRef SIZE_DMA_0_0__r)) (portRef I1 (instanceRef SIZE_DMA_0_0__n)) @@ -4050,41 +3965,41 @@ (portRef O (instanceRef SIZE_DMA_0_1__n)) (portRef I1 (instanceRef SIZE_DMA_0_1__p)) )) - (net (rename AS_030_000_SYNC_0_un3 "AS_030_000_SYNC_0.un3") (joined - (portRef O (instanceRef AS_030_000_SYNC_0_r)) - (portRef I1 (instanceRef AS_030_000_SYNC_0_n)) + (net (rename IPL_030_0_0__un3 "IPL_030_0_0_.un3") (joined + (portRef O (instanceRef IPL_030_0_0__r)) + (portRef I1 (instanceRef IPL_030_0_0__n)) )) - (net (rename AS_030_000_SYNC_0_un1 "AS_030_000_SYNC_0.un1") (joined - (portRef O (instanceRef AS_030_000_SYNC_0_m)) - (portRef I0 (instanceRef AS_030_000_SYNC_0_p)) + (net (rename IPL_030_0_0__un1 "IPL_030_0_0_.un1") (joined + (portRef O (instanceRef IPL_030_0_0__m)) + (portRef I0 (instanceRef IPL_030_0_0__p)) )) - (net (rename AS_030_000_SYNC_0_un0 "AS_030_000_SYNC_0.un0") (joined - (portRef O (instanceRef AS_030_000_SYNC_0_n)) - (portRef I1 (instanceRef AS_030_000_SYNC_0_p)) + (net (rename IPL_030_0_0__un0 "IPL_030_0_0_.un0") (joined + (portRef O (instanceRef IPL_030_0_0__n)) + (portRef I1 (instanceRef IPL_030_0_0__p)) )) - (net (rename RW_000_INT_0_un3 "RW_000_INT_0.un3") (joined - (portRef O (instanceRef RW_000_INT_0_r)) - (portRef I1 (instanceRef RW_000_INT_0_n)) + (net (rename IPL_030_0_1__un3 "IPL_030_0_1_.un3") (joined + (portRef O (instanceRef IPL_030_0_1__r)) + (portRef I1 (instanceRef IPL_030_0_1__n)) )) - (net (rename RW_000_INT_0_un1 "RW_000_INT_0.un1") (joined - (portRef O (instanceRef RW_000_INT_0_m)) - (portRef I0 (instanceRef RW_000_INT_0_p)) + (net (rename IPL_030_0_1__un1 "IPL_030_0_1_.un1") (joined + (portRef O (instanceRef IPL_030_0_1__m)) + (portRef I0 (instanceRef IPL_030_0_1__p)) )) - (net (rename RW_000_INT_0_un0 "RW_000_INT_0.un0") (joined - (portRef O (instanceRef RW_000_INT_0_n)) - (portRef I1 (instanceRef RW_000_INT_0_p)) + (net (rename IPL_030_0_1__un0 "IPL_030_0_1_.un0") (joined + (portRef O (instanceRef IPL_030_0_1__n)) + (portRef I1 (instanceRef IPL_030_0_1__p)) )) - (net (rename RW_000_DMA_0_un3 "RW_000_DMA_0.un3") (joined - (portRef O (instanceRef RW_000_DMA_0_r)) - (portRef I1 (instanceRef RW_000_DMA_0_n)) + (net (rename IPL_030_0_2__un3 "IPL_030_0_2_.un3") (joined + (portRef O (instanceRef IPL_030_0_2__r)) + (portRef I1 (instanceRef IPL_030_0_2__n)) )) - (net (rename RW_000_DMA_0_un1 "RW_000_DMA_0.un1") (joined - (portRef O (instanceRef RW_000_DMA_0_m)) - (portRef I0 (instanceRef RW_000_DMA_0_p)) + (net (rename IPL_030_0_2__un1 "IPL_030_0_2_.un1") (joined + (portRef O (instanceRef IPL_030_0_2__m)) + (portRef I0 (instanceRef IPL_030_0_2__p)) )) - (net (rename RW_000_DMA_0_un0 "RW_000_DMA_0.un0") (joined - (portRef O (instanceRef RW_000_DMA_0_n)) - (portRef I1 (instanceRef RW_000_DMA_0_p)) + (net (rename IPL_030_0_2__un0 "IPL_030_0_2_.un0") (joined + (portRef O (instanceRef IPL_030_0_2__n)) + (portRef I1 (instanceRef IPL_030_0_2__p)) )) (net (rename A0_DMA_0_un3 "A0_DMA_0.un3") (joined (portRef O (instanceRef A0_DMA_0_r)) @@ -4110,6 +4025,78 @@ (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_n)) (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_p)) )) + (net (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_un3 "AMIGA_BUS_ENABLE_DMA_HIGH_0.un3") (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_r)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_n)) + )) + (net (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_un1 "AMIGA_BUS_ENABLE_DMA_HIGH_0.un1") (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_m)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_p)) + )) + (net (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_un0 "AMIGA_BUS_ENABLE_DMA_HIGH_0.un0") (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_n)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_p)) + )) + (net (rename BG_000_0_un3 "BG_000_0.un3") (joined + (portRef O (instanceRef BG_000_0_r)) + (portRef I1 (instanceRef BG_000_0_n)) + )) + (net (rename BG_000_0_un1 "BG_000_0.un1") (joined + (portRef O (instanceRef BG_000_0_m)) + (portRef I0 (instanceRef BG_000_0_p)) + )) + (net (rename BG_000_0_un0 "BG_000_0.un0") (joined + (portRef O (instanceRef BG_000_0_n)) + (portRef I1 (instanceRef BG_000_0_p)) + )) + (net (rename DS_000_DMA_0_un3 "DS_000_DMA_0.un3") (joined + (portRef O (instanceRef DS_000_DMA_0_r)) + (portRef I1 (instanceRef DS_000_DMA_0_n)) + )) + (net (rename DS_000_DMA_0_un1 "DS_000_DMA_0.un1") (joined + (portRef O (instanceRef DS_000_DMA_0_m)) + (portRef I0 (instanceRef DS_000_DMA_0_p)) + )) + (net (rename DS_000_DMA_0_un0 "DS_000_DMA_0.un0") (joined + (portRef O (instanceRef DS_000_DMA_0_n)) + (portRef I1 (instanceRef DS_000_DMA_0_p)) + )) + (net (rename AS_000_DMA_0_un3 "AS_000_DMA_0.un3") (joined + (portRef O (instanceRef AS_000_DMA_0_r)) + (portRef I1 (instanceRef AS_000_DMA_0_n)) + )) + (net (rename AS_000_DMA_0_un1 "AS_000_DMA_0.un1") (joined + (portRef O (instanceRef AS_000_DMA_0_m)) + (portRef I0 (instanceRef AS_000_DMA_0_p)) + )) + (net (rename AS_000_DMA_0_un0 "AS_000_DMA_0.un0") (joined + (portRef O (instanceRef AS_000_DMA_0_n)) + (portRef I1 (instanceRef AS_000_DMA_0_p)) + )) + (net (rename AS_030_000_SYNC_0_un3 "AS_030_000_SYNC_0.un3") (joined + (portRef O (instanceRef AS_030_000_SYNC_0_r)) + (portRef I1 (instanceRef AS_030_000_SYNC_0_n)) + )) + (net (rename AS_030_000_SYNC_0_un1 "AS_030_000_SYNC_0.un1") (joined + (portRef O (instanceRef AS_030_000_SYNC_0_m)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_p)) + )) + (net (rename AS_030_000_SYNC_0_un0 "AS_030_000_SYNC_0.un0") (joined + (portRef O (instanceRef AS_030_000_SYNC_0_n)) + (portRef I1 (instanceRef AS_030_000_SYNC_0_p)) + )) + (net (rename RW_000_DMA_0_un3 "RW_000_DMA_0.un3") (joined + (portRef O (instanceRef RW_000_DMA_0_r)) + (portRef I1 (instanceRef RW_000_DMA_0_n)) + )) + (net (rename RW_000_DMA_0_un1 "RW_000_DMA_0.un1") (joined + (portRef O (instanceRef RW_000_DMA_0_m)) + (portRef I0 (instanceRef RW_000_DMA_0_p)) + )) + (net (rename RW_000_DMA_0_un0 "RW_000_DMA_0.un0") (joined + (portRef O (instanceRef RW_000_DMA_0_n)) + (portRef I1 (instanceRef RW_000_DMA_0_p)) + )) ) (property orig_inst_of (string "BUS68030")) ) diff --git a/Logic/BUS68030.prj b/Logic/BUS68030.prj index 46feb15..2fb2d96 100644 --- a/Logic/BUS68030.prj +++ b/Logic/BUS68030.prj @@ -1,6 +1,6 @@ #-- Lattice Semiconductor Corporation Ltd. #-- Synplify OEM project file c:/users/matze/amiga/hardwarehacks/68030-tk/github/logic\BUS68030.prj -#-- Written on Thu Oct 06 22:03:43 2016 +#-- Written on Sat Oct 15 23:47:55 2016 #device options diff --git a/Logic/BUS68030.srm b/Logic/BUS68030.srm index 210960b..4a75d46 100644 --- a/Logic/BUS68030.srm +++ b/Logic/BUS68030.srm @@ -39,8 +39,8 @@ VNAME 'mach.IBUF.prim'; # view id 4 VNAME 'mach.OBUF.prim'; # view id 5 VNAME 'mach.AND2.prim'; # view id 6 VNAME 'mach.INV.prim'; # view id 7 -VNAME 'mach.XOR2.prim'; # view id 8 -VNAME 'mach.OR2.prim'; # view id 9 +VNAME 'mach.OR2.prim'; # view id 8 +VNAME 'mach.XOR2.prim'; # view id 9 VNAME 'work.BUS68030.behavioral'; # view id 10 @ERMRlENORBvq]w_7wsRbH l;N3ORCV8HMCF8V;R4 @@ -157,24 +157,24 @@ R;Qj fbRjR:jHRMPmRRmQ j;bjRf:0jRsRkC0CskRBeB;R bfjj:RDVN#VCRNCD#R7th;R -MROlNEmRX)b.Rs;Hl -RNP3bH#sRHl4N; -P#R3$DM_HCM sRH8"OlNEm3X)b.3s"Hl;R -FmH; -R;Qj -QHR4b; -R:fjjsR0k0CRsRkCe;BB -fbRjR:jV#NDCNRVDR#Ct;h7 -fbRjR:jGPFsRmmRRRQjQ -4;MlRRNROEmR).blsH;P -NR#3HblsHR -4;N3PR#_$MD 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+@HR@6(:d::46.d::rwB49:jRrwB49:jRrwB49:j;H +NR03sDs_FHNoMl"CRw;B" +RNH3HC8VsNsNN$Ml'CRV;O' +@FR@6(:c::464c:(v:qQ_tqq)77_q hARp qtvQq7_q7 )_hpqA N; +HsR30FD_sMHoNRlC"Qqvtqq_7_7) Ahqp; " +@FR@6(:6::4646:Uv:qQ_tqA_z17qqa_)7QRQqvtAq_z71_q_aq7;Q) +RNH3Ds0_HFsolMNCqR"vqQt_1Az_a7qqQ_7) +";F@R@(n:6:64:nj:.:QqvtAq_z 1_hpqA m_pWvRqQ_tqA_z1 Ahqpp _m +W;N3HRs_0DFosHMCNlRv"qQ_tqA_z1 Ahqpp _m;W" +@FR@6(:(::46.(:4v:qQ_tqA_z1 Ahqp] _QRt]qtvQqz_A1h_ q Ap_t]Q]N; +HsR30FD_sMHoNRlC"QqvtAq_z 1_hpqA Q_]t;]" +@FR@6(:U::46cU::QBQhQRBQ +h;N3HRs_0DFosHMCNlRQ"BQ;h" +RoLq9r4;L +NRH3L0sbF0s8HR +4;okMRMN4_lNHo_#Lk_NCML_DCD;FI +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR(kM__N#j;dj +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR4kM_1p7_jjj_aQh;M NRN3#PMC_CV0_D#No46R.no; MMRk47_z1j_jjh_QaN; M#R3N_PCM_C0VoDN#.4R6 -n;okMRMp4_7j1_jQj_h -a;N3MR#CNP_0MC_NVDoR#4.;6n -RoMk_M41qv_vqQt_#j_JGlkN;_4 -RNM3P#NCC_M0D_VN4o#Rn.6;M -oR4kMjH_OH -M;N3MR#CNP_0MC_NVDoR#4.;6n -RoMk4M._kVb_;O# -RNM3P#NCC_M0D_VN4o#Rn.6;M -oR.kM4C_Ls -s;N3MR#CNP_0MC_NVDoR#4.;6n -RoMk_Mn8j#_d -j;N3MR#CNP_0MC_NVDoR#4.;6n +n;okMRM_4jOMHH;M +NRN3#PMC_CV0_D#No46R.no; +MMRk.V4_bOk_#N; +M#R3N_PCM_C0VoDN#.4R6 +n;okMRM_.4LsCs;M +NRN3#PMC_CV0_D#No46R.no; +MMRkn#_8_jjd;M +NRN3#PMC_CV0_D#No46R.no; +M_RhdN; +M#R3N_PCM_C0VoDN#.4R6 +n;ohMR_ +c;N3MR#CNP_0MC_NVDoR#4.;6n RoMh;_n RNM3P#NCC_M0D_VN4o#Rn.6;M oR(h_;M @@ -384,16 +386,20 @@ d;N3MR#CNP_0MC_NVDoR#4.;6n RoMh6_4;M NRN3#PMC_CV0_D#No46R.no; M_Rh4 +g;N3MR#CNP_0MC_NVDoR#4.;6n +RoMhj_.;M +NRN3#PMC_CV0_D#No46R.no; +M_Rh. +.;N3MR#CNP_0MC_NVDoR#4.;6n +RoMhd_.;M +NRN3#PMC_CV0_D#No46R.no; +M_Rh. +c;N3MR#CNP_0MC_NVDoR#4.;6n +RoMh6_.;M +NRN3#PMC_CV0_D#No46R.no; +M_Rh. n;N3MR#CNP_0MC_NVDoR#4.;6n -RoMhg_4;M -NRN3#PMC_CV0_D#No46R.no; -M_Rh. -j;N3MR#CNP_0MC_NVDoR#4.;6n -RoMh._.;M -NRN3#PMC_CV0_D#No46R.no; -M_Rh. -d;N3MR#CNP_0MC_NVDoR#4.;6n -RoMhc_.;M +RoMh(_.;M NRN3#PMC_CV0_D#No46R.no; M_Rh. U;N3MR#CNP_0MC_NVDoR#4.;6n @@ -429,15 +435,11 @@ RoMh6_c;M NRN3#PMC_CV0_D#No46R.no; M_Rhc U;N3MR#CNP_0MC_NVDoR#4.;6n -RoMhg_c;M +RoMh._6;M NRN3#PMC_CV0_D#No46R.no; M_Rh6 -j;N3MR#CNP_0MC_NVDoR#4.;6n -RoMh4_6;M -NRN3#PMC_CV0_D#No46R.no; -M_Rh6 -.;N3MR#CNP_0MC_NVDoR#4.;6n -RoMhd_6;M +d;N3MR#CNP_0MC_NVDoR#4.;6n +RoMh6_6;M NRN3#PMC_CV0_D#No46R.no; M_Rh6 n;N3MR#CNP_0MC_NVDoR#4.;6n @@ -457,63 +459,99 @@ RoMhc_(;M NRN3#PMC_CV0_D#No46R.no; M_Rh( 6;N3MR#CNP_0MC_NVDoR#4.;6n -RoMhj_.nN; +RoMhg_4gN; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_(.j;M +n;ohMR_4.d;M NRN3#PMC_CV0_D#No46R.no; -M_Rh.;jU +M_Rh.;dd RNM3P#NCC_M0D_VN4o#Rn.6;M oR.h_c 6;N3MR#CNP_0MC_NVDoR#4.;6n -RoMhn_.jN; +RoMhc_.nN; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_(.g;M +n;ohMR_4.6;M NRN3#PMC_CV0_D#No46R.no; -M_Rh.;gU -RNM3P#NCC_M0D_VN4o#Rn.6;M -oRdh_j -j;N3MR#CNP_0MC_NVDoR#4.;6n -RoMhj_d.N; -M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_6dj;M -NRN3#PMC_CV0_D#No46R.no; -M_Rhd;jn -RNM3P#NCC_M0D_VN4o#Rn.6;M -oRdh_4 -g;N3MR#CNP_0MC_NVDoR#4.;6n -RoMh._djN; -M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_cd.;M -NRN3#PMC_CV0_D#No46R.no; -M_Rhd;.( +M_Rhd;4j RNM3P#NCC_M0D_VN4o#Rn.6;M oRdh_d .;N3MR#CNP_0MC_NVDoR#4.;6n -RoMhd_ddN; +RoMhd_d(N; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_cdd;M +n;ohMR_Udd;M NRN3#PMC_CV0_D#No46R.no; -M_Rhd;d6 +M_Rhd;cj RNM3P#NCC_M0D_VN4o#Rn.6;M -oRdh_d -n;N3MR#CNP_0MC_NVDoR#4.;6n -RoMhd_dUN; +oRdh_6 +j;N3MR#CNP_0MC_NVDoR#4.;6n +RoMh6_d6N; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_gdd;M +n;ohMR_jdn;M NRN3#PMC_CV0_D#No46R.no; -M_Rhd;6j +MbROk#_C0__jdk_3M +d;N3MR#CNP_0MC_NVDoR#4.;6n +RoMO_bkC_#0j__d34kM;M +NRN3#PMC_CV0_D#No46R.no; +MbROk#_C0__jdk_3M +j;N3MR#CNP_0MC_NVDoR#4.;6n +RoM)jW_jQj_hja_3dkM;M +NRN3#PMC_CV0_D#No46R.no; +MWR)_jjj_aQh_kj3M +4;N3MR#CNP_0MC_NVDoR#4.;6n +RoM)jW_jQj_hja_3jkM;M +NRN3#PMC_CV0_D#No46R.no; +MvReqh_Qa3_jk;Md RNM3P#NCC_M0D_VN4o#Rn.6;M -oRpQu_jjd_.j__M3kdN; +oRqev_aQh_kj3M +4;N3MR#CNP_0MC_NVDoR#4.;6n +RoMe_vqQ_hajM3kjN; M#R3N_PCM_C0VoDN#.4R6 -n;oQMRujp_djj__3._k;M4 +n;oOMRbCk_#j0__34_k;Md RNM3P#NCC_M0D_VN4o#Rn.6;M -oRpQu_jjd_.j__M3kjN; +oRkOb_0C#_4j__M3k4N; M#R3N_PCM_C0VoDN#.4R6 -n;oQMRujp_djj__34_k;Md +n;oOMRbCk_#j0__34_k;Mj RNM3P#NCC_M0D_VN4o#Rn.6;M -oRpQu_jjd_4j__M3k4N; +oRkOb_0C#_.j__M3kdN; M#R3N_PCM_C0VoDN#.4R6 -n;oQMRujp_djj__34_k;Mj +n;oOMRbCk_#j0__3._k;M4 +RNM3P#NCC_M0D_VN4o#Rn.6;M +oRkOb_0C#_.j__M3kjN; +M#R3N_PCM_C0VoDN#.4R6 +n;ozMR7j1_jQj_hja_3dkM;M +NRN3#PMC_CV0_D#No46R.no; +M7Rz1j_jjh_Qa3_jk;M4 +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR1z7_jjj_aQh_kj3M +j;N3MR#CNP_0MC_NVDoR#4.;6n +RoMp_71j_jjQ_hajM3kdN; +M#R3N_PCM_C0VoDN#.4R6 +n;opMR7j1_jQj_hja_34kM;M +NRN3#PMC_CV0_D#No46R.no; +M7Rp1j_jjh_Qa3_jk;Mj +RNM3P#NCC_M0D_VN4o#Rn.6;M +oRqAtBji_dQj_hja_3dkM;M +NRN3#PMC_CV0_D#No46R.no; +MtRAq_Bij_djQ_hajM3k4N; +M#R3N_PCM_C0VoDN#.4R6 +n;oAMRtiqB_jjd_aQh_kj3M +j;N3MR#CNP_0MC_NVDoR#4.;6n +RoM7j1_j j_hpqA 3_jk;Md +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR_71j_jj Ahqpj _34kM;M +NRN3#PMC_CV0_D#No46R.no; +M1R7_jjj_q hA_p jM3kjN; +M#R3N_PCM_C0VoDN#.4R6 +n;o1MRQ_Z 7_vqj__j3dkM;M +NRN3#PMC_CV0_D#No46R.no; +MQR1Z7 _vjq__3j_k;M4 +RNM3P#NCC_M0D_VN4o#Rn.6;M +oRZ1Q v_7q__jjk_3M +j;N3MR#CNP_0MC_NVDoR#4.;6n +RoM1 QZ_q7v_4j__M3kdN; +M#R3N_PCM_C0VoDN#.4R6 +n;o1MRQ_Z 7_vqj__434kM;M +NRN3#PMC_CV0_D#No46R.no; +MQR1Z7 _vjq__34_k;Mj RNM3P#NCC_M0D_VN4o#Rn.6;M oRpQu_jjd_jj__M3kdN; M#R3N_PCM_C0VoDN#.4R6 @@ -521,29 +559,41 @@ n;oQMRujp_djj__3j_k;M4 RNM3P#NCC_M0D_VN4o#Rn.6;M oRpQu_jjd_jj__M3kjN; M#R3N_PCM_C0VoDN#.4R6 -n;oOMRbCk_#j0__3d_k;Md +n;oQMRujp_djj__34_k;Md RNM3P#NCC_M0D_VN4o#Rn.6;M -oRkOb_0C#_dj__M3k4N; +oRpQu_jjd_4j__M3k4N; M#R3N_PCM_C0VoDN#.4R6 -n;oOMRbCk_#j0__3d_k;Mj +n;oQMRujp_djj__34_k;Mj RNM3P#NCC_M0D_VN4o#Rn.6;M -oRqev_aQh_kj3M -d;N3MR#CNP_0MC_NVDoR#4.;6n -RoMe_vqQ_hajM3k4N; +oRpQu_jjd_.j__M3kdN; M#R3N_PCM_C0VoDN#.4R6 -n;oeMRvQq_hja_3jkM;M +n;oQMRujp_djj__3._k;M4 +RNM3P#NCC_M0D_VN4o#Rn.6;M +oRpQu_jjd_.j__M3kjN; +M#R3N_PCM_C0VoDN#.4R6 +n;oqMRjv_7q3_jk;Md +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR_qj7_vqjM3k4N; +M#R3N_PCM_C0VoDN#.4R6 +n;oqMRjv_7q3_jk;Mj +RNM3P#NCC_M0D_VN4o#Rn.6;M +oRQqvtAq_z 1_hpqA v_7qm_pW3_jk;Md +RNM3P#NCC_M0D_VN4o#Rn.6;M +oRQqvtAq_z 1_hpqA v_7qm_pW3_jk;M4 +RNM3P#NCC_M0D_VN4o#Rn.6;M +oRQqvtAq_z 1_hpqA v_7qm_pW3_jk;Mj +RNM3P#NCC_M0D_VN4o#Rn.6;M +oRQqvtAq_z 1_hpqA v_7qQ_]tj]_3dkM;M NRN3#PMC_CV0_D#No46R.no; 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+R:fjjNRlOmER)b.RsRHlqj1_djj_j1j_Y_hBj 3bShm=_ -..S=QjqtvQqz_A1h_ q Ap_q7v_Wpm_kj3MS4 -Qq4=vqQt_1Az_q hA_p 7_vqp_mWjM3kj +46S=Qjqj1_djj_j1j_Y_hBjM3k4Q +S41=q_jjd_jjj_h1YB3_jk;Mj +fsRjR:jlENOReQhRHbslWR)_jjj_q7v_sj3 +=Sm)jW_j7j_vjq_3dkM +jSQ=4h_U +6;sjRf:ljRNROEq.h7RHbslWR)_jjj_q7v_lj3 +=Sm)jW_j7j_vjq_34kM +jSQ=#bF_ OD\W3)_jjj_q7v_Sd +Qh4=_64U;R +sfjj:ROlNEhRq7b.RsRHl)jW_j7j_vjq_3SM +mW=)_jjj_q7v_kj3MSj +Q)j=Wj_jjv_7qQ +S4W=)_jjj_q7v_kj3M +d;sjRf:ljRNROEmR).blsHR_)Wj_jj7_vqj +3bShm=_ +4gS=Qj)jW_j7j_vjq_34kM +4SQ=_)Wj_jj7_vqjM3kj ; diff --git a/Logic/BUS68030.srr b/Logic/BUS68030.srr index 4e5d5fe..1949b2a 100644 --- a/Logic/BUS68030.srr +++ b/Logic/BUS68030.srr @@ -6,7 +6,7 @@ #Implementation: logic $ Start of Compile -#Thu Oct 06 22:04:05 2016 +#Sat Oct 15 23:48:18 2016 Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014 @N|Running in 64-bit mode @@ -28,7 +28,7 @@ Post processing for work.bus68030.behavioral @W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_OUT_EXP_INT_1 @W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":126:36:126:38|Pruning register CLK_OUT_PRE_25_3 @W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":154:2:154:3|Pruning register CLK_030_D0_2 -@W: CL271 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Pruning bits 12 to 6 of CLK_000_D_3(12 downto 0) -- not in use ... +@W: CL271 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Pruning bits 12 to 5 of CLK_000_D_3(12 downto 0) -- not in use ... @N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Trying to extract state machine for register SM_AMIGA Extracted state machine for register SM_AMIGA State machine has 8 reachable states with original encodings of: @@ -47,7 +47,7 @@ State machine has 8 reachable states with original encodings of: At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Thu Oct 06 22:04:05 2016 +# Sat Oct 15 23:48:18 2016 ###########################################################] Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014 @@ -57,7 +57,7 @@ File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\synwork\BUS68030_c At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Thu Oct 06 22:04:06 2016 +# Sat Oct 15 23:48:19 2016 ###########################################################] Map & Optimize Report @@ -81,15 +81,15 @@ original code -> new code Resource Usage Report Simple gate primitives: -DFF 56 uses +DFF 55 uses BI_DIR 18 uses BUFTH 4 uses IBUF 38 uses OBUF 15 uses AND2 269 uses INV 238 uses +OR2 22 uses XOR2 5 uses -OR2 23 uses @N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis. @@ -99,6 +99,6 @@ Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Thu Oct 06 22:04:07 2016 +# Sat Oct 15 23:48:19 2016 ###########################################################] diff --git a/Logic/BUS68030.srs b/Logic/BUS68030.srs index 6a70794..69e630c 100644 Binary files a/Logic/BUS68030.srs and b/Logic/BUS68030.srs differ diff --git a/Logic/Programming.xcf b/Logic/Programming.xcf index acb1ab4..308e284 100644 --- a/Logic/Programming.xcf +++ b/Logic/Programming.xcf @@ -19,8 +19,8 @@ 0 C:\Users\Matze\Amiga\Hardwarehacks\68030-TK\GitHub\Logic\68030_tk.jed - 09/14/16 23:54:30 - 0xD04F + 10/15/16 23:48:29 + 0x1315 Erase,Program,Verify