diff --git a/Logic/68030-68000-bus.vhd b/Logic/68030-68000-bus.vhd index 26b6c77..103a32b 100644 --- a/Logic/68030-68000-bus.vhd +++ b/Logic/68030-68000-bus.vhd @@ -14,7 +14,7 @@ port( SIZE: inout std_logic_vector ( 1 downto 0 ); A: inout std_logic_vector ( 31 downto 0 ); CPU_SPACE: in std_logic ; - BERR: inout std_logic ; --error: this is connected to a global input pin :( + BERR: inout std_logic ; BG_030: in std_logic ; BG_000: out std_logic ; BGACK_030: out std_logic ; @@ -84,11 +84,9 @@ constant DATA_FETCH_P : AMIGA_STATE := "110"; constant END_CYCLE_N : AMIGA_STATE := "111"; signal SM_AMIGA : AMIGA_STATE := IDLE_P; -signal SM_AMIGA_D : AMIGA_STATE := IDLE_P; --signal Dout:STD_LOGIC_VECTOR(3 downto 0) := "0000"; signal AS_000_INT:STD_LOGIC:= '1'; -signal AS_000_START:STD_LOGIC:= '1'; signal AS_030_000_SYNC:STD_LOGIC:= '1'; signal BGACK_030_INT:STD_LOGIC:= '1'; signal DTACK_SYNC:STD_LOGIC:= '1'; @@ -97,7 +95,6 @@ signal FPU_CS_INT:STD_LOGIC:= '1'; signal VPA_D: STD_LOGIC:='1'; signal VPA_SYNC: STD_LOGIC:='1'; signal VMA_INT: STD_LOGIC:='1'; -signal VMA_INT_D: STD_LOGIC:='1'; signal UDS_000_INT: STD_LOGIC:='1'; signal LDS_000_INT: STD_LOGIC:='1'; signal DSACK_INT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "11"; @@ -109,10 +106,6 @@ signal CLK_OUT_INT: STD_LOGIC:='1'; signal CLK_030_D: STD_LOGIC:='1'; signal CLK_000_D: STD_LOGIC := '1'; signal CLK_000_DD: STD_LOGIC := '1'; -signal RISING_CLK_AMIGA: STD_LOGIC :='0'; -signal FALLING_CLK_AMIGA: STD_LOGIC :='0'; ---signal RISING_CLK_030: STD_LOGIC :='0'; ---signal FALLING_CLK_030: STD_LOGIC :='0'; begin @@ -139,16 +132,8 @@ begin CLK_000_DD <= CLK_000_D; - - --RISING_CLK_030 <= CLK_OUT_PRE and not CLK_030; - --FALLING_CLK_030 <= not CLK_OUT_PRE and CLK_030; - --edge detection stuff - RISING_CLK_AMIGA <= not CLK_000_D and CLK_000; - FALLING_CLK_AMIGA <= CLK_000_D and not CLK_000; - --cycle counter for Amiga-Bus-Timing - if( CLK_000_D /= CLK_000)then --not equal CLK_000_CNT <= "0001"; else @@ -184,35 +169,6 @@ begin end if; end process clk; - --eclk: process(CLK_000) - --begin - -- if(rising_edge(CLK_000)) then - -- -- e clock - -- case (cpu_est) is - -- when E1 => cpu_est <= E2 ; - -- when E2 => cpu_est <= E3 ; - -- when E3 => cpu_est <= E4; - -- when E4 => cpu_est <= E5 ; - -- when E5 => cpu_est <= E6 ; - -- when E6 => cpu_est <= E7 ; - -- when E7 => cpu_est <= E8 ; - -- when E8 => cpu_est <= E9 ; - -- when E9 => cpu_est <= E10; - -- when E10 => cpu_est <= E1 ; - -- -- Illegal states - -- when E4a => cpu_est <= E5 ; - -- when E20 => cpu_est <= E10; - -- when E21 => cpu_est <= E10; - -- when E22 => cpu_est <= E9 ; - -- when E23 => cpu_est <= E9 ; - -- when E24 => cpu_est <= E10; - -- when others => - -- null; - -- end case; - -- end if; - --end process eclk; - - --the state process state_machine: process(RST, CLK_OSZI) @@ -220,13 +176,11 @@ begin if(RST = '0' ) then SM_AMIGA <= IDLE_P; AS_000_INT <='1'; - AS_000_START<= '0'; AS_030_000_SYNC <='1'; UDS_000_INT <='1'; LDS_000_INT <='1'; CLK_REF <= "10"; VMA_INT <= '1'; - VMA_INT_D <= '1'; FPU_CS_INT <= '1'; BG_000 <= '1'; BGACK_030_INT <= '1'; @@ -242,7 +196,7 @@ begin --bgack is simple: assert as soon as Amiga asserts but hold bg_ack for one amiga-clock if(BGACK_000='0') then BGACK_030_INT <= '0'; - elsif (BGACK_000='1' AND RISING_CLK_AMIGA='1') then -- BGACK_000 is high here! + elsif (BGACK_000='1' AND CLK_000_DD='0' and CLK_000_D='1') then -- BGACK_000 is high here! BGACK_030_INT <= '1'; --hold this signal high until 7m clock goes high end if; @@ -258,20 +212,24 @@ begin end if; end if; - --CO-Processor Chip select - - - + --interrupt buffering to avoid ghost interrupts - if(RISING_CLK_AMIGA='1')then + if(CLK_000_DD='0' and CLK_000_D='1')then IPL_030<=IPL; end if; -- as030-sampling and FPU-Select - if(AS_030 ='1') then + + if(AS_030 ='1') then -- "async" reset of various signals AS_030_000_SYNC <= '1'; FPU_CS_INT <= '1'; + DSACK_INT<="11"; + AS_000_INT <= '1'; + UDS_000_INT <= '1'; + LDS_000_INT <= '1'; + DTACK_SYNC <= '1'; + VPA_SYNC <= '1'; elsif( CLK_030 = '1' AND --68030 has a valid AS on high clocks AS_030 = '0') then @@ -284,24 +242,10 @@ begin end if; end if; - -- "async" reset - if(AS_030 ='1') then - DSACK_INT<="11"; - AS_000_INT <= '1'; - UDS_000_INT <= '1'; - LDS_000_INT <= '1'; - DTACK_SYNC <= '1'; - VPA_SYNC <= '1'; - end if; - -- VMA generation - --assert - if(CLK_000_D='0' AND VPA_D='0' AND cpu_est = E4)then + if(CLK_000_D='0' AND VPA_D='0' AND cpu_est = E4)then --assert VMA_INT <= '0'; - end if; - - --deassert - if(CLK_000_D='1' AND AS_000_INT='1' AND cpu_est_d=E1)then + elsif(CLK_000_D='1' AND AS_000_INT='1' AND cpu_est=E1)then --deassert VMA_INT <= '1'; end if; @@ -313,7 +257,6 @@ begin SM_AMIGA<=IDLE_N; end if; when IDLE_N => --68000:S1 wait for rising edge, on a rising CLK_000 look for a amiga adressrobe - --AS_000_START <='0'; if(CLK_000_D='1' and CLK_000_DD = '0')then --sample AS only at the rising edge! if( AS_030_000_SYNC = '0' )then AS_000_INT <= '0'; @@ -356,15 +299,12 @@ begin if(CLK_000_D='0' )then if(DTACK_SYNC = '0' OR VPA_SYNC ='0')then SM_AMIGA<=DATA_FETCH_N; - --else - -- SM_AMIGA<=AS_SET_N; -- no dtack sampled wait one clock: go back to AS_SET_N end if; else -- high clock: sample DTACK if(VPA_D = '1' AND DTACK='0') then DTACK_SYNC <= '0'; elsif(VPA_D='0' AND cpu_est=E9 AND VMA_INT='0') then --vpa/vma cycle: sync VPA on E9: one 7M-clock to latch! - VPA_SYNC <= '0'; - + VPA_SYNC <= '0'; end if; end if; when DATA_FETCH_N=> --68000:S5 nothing happens here just wait for positive clock @@ -372,31 +312,16 @@ begin SM_AMIGA<=DATA_FETCH_P; end if; when DATA_FETCH_P => --68000:S6: READ: here comes the data on the bus! - if( CLK_000_D ='0' AND CLK_OUT_PRE='1' - ) then + if( CLK_000_D ='0' AND CLK_OUT_PRE='1' ) then --next 030-clock is high: dsack is sampled at the falling edge DSACK_INT<="01"; SM_AMIGA<=END_CYCLE_N; end if; when END_CYCLE_N =>--68000:S7: Latch/Store data and go to IDLE on high clock if(CLK_000_D='1' and AS_000_INT='1' )then SM_AMIGA<=IDLE_P; - --elsif( CLK_OUT_PRE='1' --assert here (next 68030-Clock will be high)! - -- and AS_030_000_SYNC ='0' -- if the cycle somehow aboarded do not send a dsack! - -- ) then --timing is everything! - --if( (VPA_SYNC ='0' AND CLK_000_CNT > x"0" and RW='0') OR - -- (VPA_SYNC ='0' AND CLK_000_CNT > x"0" and RW='1') OR - -- (DTACK_SYNC='0' AND CLK_000_CNT > x"0" and RW='0') OR - -- (DTACK_SYNC='0' AND CLK_000_CNT > x"0" and RW='1') - --)then - -- DSACK_INT<="01"; - --end if; - end if; end case; - - --delay for hold time of CIAs - VMA_INT_D <= VMA_INT; - + --dma stuff --DTACK for DMA cycles @@ -406,8 +331,6 @@ begin DTACK_DMA <= '1'; end if; - SM_AMIGA_D <= SM_AMIGA; - end if; end process state_machine; diff --git a/Logic/68030_TK.tcl b/Logic/68030_TK.tcl index 19ffb69..253ae88 100644 --- a/Logic/68030_TK.tcl +++ b/Logic/68030_TK.tcl @@ -119320,3 +119320,1149 @@ if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 6 ########## Tcl recorder end at 05/15/14 22:21:47 ########### + +########## Tcl recorder starts at 05/15/14 22:52:38 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 22:52:38 ########### + + +########## Tcl recorder starts at 05/15/14 22:55:00 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 22:55:00 ########### + + +########## Tcl recorder starts at 05/15/14 22:55:06 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 22:55:06 ########### + + +########## Tcl recorder starts at 05/15/14 22:55:58 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 22:55:58 ########### + + +########## Tcl recorder starts at 05/15/14 22:55:59 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 22:55:59 ########### + + +########## Tcl recorder starts at 05/15/14 22:57:53 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 22:57:53 ########### + + +########## Tcl recorder starts at 05/15/14 22:59:50 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 22:59:50 ########### + + +########## Tcl recorder starts at 05/15/14 23:00:42 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 23:00:42 ########### + + +########## Tcl recorder starts at 05/15/14 23:01:06 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 23:01:06 ########### + + +########## Tcl recorder starts at 05/15/14 23:01:19 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 23:01:19 ########### + + +########## Tcl recorder starts at 05/15/14 23:01:23 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 23:01:23 ########### + + +########## Tcl recorder starts at 05/15/14 23:01:37 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 23:01:37 ########### + + +########## Tcl recorder starts at 05/15/14 23:01:39 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 23:01:39 ########### + + +########## Tcl recorder starts at 05/15/14 23:02:37 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 23:02:37 ########### + + +########## Tcl recorder starts at 05/15/14 23:02:39 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 23:02:39 ########### + diff --git a/Logic/68030_tk.bl2 b/Logic/68030_tk.bl2 index 219428e..307216f 100644 --- a/Logic/68030_tk.bl2 +++ b/Logic/68030_tk.bl2 @@ -1,85 +1,86 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Thu May 15 22:21:53 2014 +#$ DATE Thu May 15 23:02:46 2014 #$ MODULE 68030_tk -#$ PINS 74 A_28_ A_27_ SIZE_1_ A_26_ A_25_ A_31_ A_24_ A_23_ IPL_030_2_ A_22_ A_21_ \ -# IPL_2_ A_20_ A_19_ DSACK_1_ A_18_ A_17_ FC_1_ A_16_ AS_030 A_15_ AS_000 A_14_ DS_030 A_13_ \ -# UDS_000 A_12_ LDS_000 A_11_ CPU_SPACE A_10_ BERR A_9_ BG_030 A_8_ BG_000 A_7_ BGACK_030 \ -# A_6_ BGACK_000 A_5_ CLK_030 A_4_ CLK_000 A_3_ CLK_OSZI A_2_ CLK_DIV_OUT A_1_ CLK_EXP A_0_ \ -# FPU_CS IPL_030_1_ DTACK IPL_030_0_ AVEC IPL_1_ AVEC_EXP IPL_0_ E DSACK_0_ VPA FC_0_ VMA RST \ -# RESET RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ \ -# A_29_ -#$ NODES 351 CLK_OSZI_c CLK_OUT_INTreg IPL_030DFFSH_0_reg inst_BGACK_030_INTreg \ -# inst_FPU_CS_INTreg IPL_030DFFSH_1_reg cpu_est_3_reg inst_VMA_INTreg \ -# IPL_030DFFSH_2_reg gnd_n_n cpu_est_0_ ipl_c_0__n cpu_est_1_ cpu_est_d_0_ ipl_c_1__n \ -# cpu_est_d_3_ inst_AS_000_INTreg ipl_c_2__n inst_AS_030_000_SYNC inst_DTACK_SYNC \ -# inst_VPA_D dsack_c_1__n inst_VPA_SYNC inst_CLK_000_D DTACK_c inst_CLK_000_DD \ -# inst_CLK_OUT_PRE vcc_n_n cpu_est_d_1_ cpu_est_d_2_ cpu_est_2_ CLK_CNT_0_ SM_AMIGA_6_ \ -# RST_c SM_AMIGA_7_ inst_UDS_000_INTreg RESETDFFreg inst_LDS_000_INTreg RW_c \ -# inst_RISING_CLK_AMIGA state_machine_un57_clk_000_d_n fc_c_0__n SM_AMIGA_1_ \ -# DSACK_INT_1_ fc_c_1__n inst_DTACK_DMA SM_AMIGA_4_ SM_AMIGA_3_ \ -# state_machine_un13_as_000_int_n SM_AMIGA_5_ SM_AMIGA_2_ N_145_i SM_AMIGA_0_ \ -# a_c_i_0__n state_machine_uds_000_int_8_0_n state_machine_lds_000_int_8_0_n N_99_i \ -# N_112_i N_100_i N_101_i sm_amiga_ns_0_2__n N_103_i N_110_i sm_amiga_ns_0_7__n \ -# cpu_est_0_0_ N_91_0 N_92_0 N_131_i N_132_i N_122_i CLK_OUT_PRE_0 N_124_i N_125_i \ -# N_126_i N_129_i N_98 N_127_i N_97 N_128_i N_104 N_130_i N_93 clk_cpu_est_11_0_1__n N_105 \ -# N_134_i N_106 N_133_i N_108 N_135_i N_94 clk_cpu_est_11_0_3__n N_109 size_c_i_1__n \ -# N_107 state_machine_un31_clk_000_d_i_n N_135_1 \ -# state_machine_as_030_000_sync_3_0_n VPA_SYNC_1_sqmuxa_1_0 un1_as_030_2_0 N_167 \ -# state_machine_un17_clk_030_0_n N_170 state_machine_un57_clk_000_d_0_n \ -# state_machine_un42_clk_030_n RISING_CLK_AMIGA_i DTACK_SYNC_1_sqmuxa \ -# state_machine_un4_bgack_000_0_n VPA_SYNC_1_sqmuxa BG_030_c_i un1_bg_030 \ -# state_machine_un1_clk_030_0_n DTACK_SYNC_1_sqmuxa_1 N_97_i DSACK_INT_1_sqmuxa \ -# un1_bg_030_0 state_machine_un1_clk_030_n CLK_OUT_PRE_i \ -# state_machine_un4_bgack_000_n N_94_0 un1_as_030_2 N_93_0 \ -# state_machine_un17_clk_030_n N_108_i N_102 N_109_i AS_000_INT_1_sqmuxa \ -# VPA_SYNC_1_sqmuxa_1 N_106_i state_machine_as_030_000_sync_3_n N_107_i \ -# clk_un3_clk_000_dd_n sm_amiga_ns_0_5__n state_machine_un31_clk_000_d_n N_104_i \ -# UDS_000_INT_0_sqmuxa N_105_i state_machine_un13_clk_000_d_n \ -# state_machine_un13_clk_000_d_4_n un1_bg_030_0_1 state_machine_un13_clk_000_d_1_n \ -# un1_bg_030_0_2 state_machine_un8_clk_000_d_n state_machine_un31_clk_000_d_i_1_n \ -# UDS_000_INT_0_sqmuxa_1 clk_cpu_est_11_0_1_3__n N_132 clk_cpu_est_11_0_1_1__n N_131 \ -# clk_cpu_est_11_0_2_1__n N_124 N_167_1 clk_cpu_est_11_3__n N_167_2 N_135 N_167_3 N_133 \ -# N_167_4 N_134 N_167_5 clk_cpu_est_11_1__n N_167_6 N_130 N_170_1 N_128 N_170_2 N_145 \ -# N_107_1 N_127 state_machine_un42_clk_030_1_n N_129 state_machine_un42_clk_030_2_n \ -# N_126 state_machine_un42_clk_030_3_n N_125 state_machine_un42_clk_030_4_n N_92 \ -# state_machine_un42_clk_030_5_n N_91 DTACK_SYNC_1_sqmuxa_1_0 N_110 \ -# VPA_SYNC_1_sqmuxa_1_1 N_103 VPA_SYNC_1_sqmuxa_2 N_101 VPA_SYNC_1_sqmuxa_3 N_100 \ -# VPA_SYNC_1_sqmuxa_4 N_112 N_98_1 N_99 state_machine_as_030_000_sync_3_0_1_n \ -# state_machine_lds_000_int_8_n UDS_000_INT_0_sqmuxa_1_0 \ -# state_machine_uds_000_int_8_n UDS_000_INT_0_sqmuxa_2 un2_clk_030_1 \ -# state_machine_un13_clk_000_d_1_0_n VMA_INT_1_sqmuxa \ -# state_machine_un13_clk_000_d_4_1_n RW_i state_machine_un8_clk_000_d_1_n \ -# cpu_est_d_i_3__n state_machine_un8_clk_000_d_2_n cpu_est_d_i_0__n \ -# state_machine_un8_clk_000_d_3_n CLK_000_D_i state_machine_un8_clk_000_d_4_n \ -# AS_000_INT_i UDS_000_INT_0_sqmuxa_1_1 dsack_i_1__n UDS_000_INT_0_sqmuxa_1_2 \ -# state_machine_un13_clk_000_d_i_n UDS_000_INT_0_sqmuxa_1_3 \ -# state_machine_un8_clk_000_d_i_n N_132_1 AS_030_i N_131_1 sm_amiga_i_6__n \ -# vma_int_0_un3_n sm_amiga_i_7__n vma_int_0_un1_n sm_amiga_i_5__n vma_int_0_un0_n \ -# sm_amiga_i_4__n lds_000_int_0_un3_n state_machine_un13_clk_000_d_1_i_n \ -# lds_000_int_0_un1_n CLK_000_DD_i lds_000_int_0_un0_n AS_030_000_SYNC_i \ -# uds_000_int_0_un3_n cpu_est_i_0__n uds_000_int_0_un1_n cpu_est_i_2__n \ -# uds_000_int_0_un0_n cpu_est_i_3__n cpu_est_0_3__un3_n cpu_est_i_1__n \ -# cpu_est_0_3__un1_n UDS_000_INT_0_sqmuxa_1_i cpu_est_0_3__un0_n \ -# UDS_000_INT_0_sqmuxa_i cpu_est_0_2__un3_n DS_030_i cpu_est_0_2__un1_n VPA_D_i \ -# cpu_est_0_2__un0_n state_machine_un42_clk_030_i_n cpu_est_0_1__un3_n \ -# VPA_SYNC_1_sqmuxa_i cpu_est_0_1__un1_n N_102_i cpu_est_0_1__un0_n \ -# DTACK_SYNC_1_sqmuxa_i fpu_cs_int_0_un3_n N_98_i fpu_cs_int_0_un1_n a_i_18__n \ -# fpu_cs_int_0_un0_n a_i_16__n as_000_int_0_un3_n a_i_19__n as_000_int_0_un1_n \ -# CLK_030_i as_000_int_0_un0_n VMA_INT_i vpa_sync_0_un3_n DTACK_i vpa_sync_0_un1_n \ -# sm_amiga_i_3__n vpa_sync_0_un0_n sm_amiga_i_1__n as_030_000_sync_0_un3_n \ -# sm_amiga_i_2__n as_030_000_sync_0_un1_n a_i_30__n as_030_000_sync_0_un0_n \ -# a_i_31__n ipl_030_0_2__un3_n a_i_28__n ipl_030_0_2__un1_n a_i_29__n \ -# ipl_030_0_2__un0_n a_i_26__n ipl_030_0_1__un3_n a_i_27__n ipl_030_0_1__un1_n \ -# a_i_24__n ipl_030_0_1__un0_n a_i_25__n ipl_030_0_0__un3_n ipl_030_0_0__un1_n \ -# ipl_030_0_0__un0_n RST_i bgack_030_int_0_un3_n FPU_CS_INT_i bgack_030_int_0_un1_n \ -# CPU_SPACE_i bgack_030_int_0_un0_n BGACK_030_INT_i dsack_int_0_1__un3_n AS_030_c \ -# dsack_int_0_1__un1_n dsack_int_0_1__un0_n bg_000_0_un3_n DS_030_c bg_000_0_un1_n \ -# bg_000_0_un0_n dtack_sync_0_un3_n dtack_sync_0_un1_n size_c_0__n \ -# dtack_sync_0_un0_n a_15__n size_c_1__n a_14__n a_c_0__n a_13__n a_12__n a_11__n \ -# a_10__n a_9__n a_8__n a_7__n a_6__n a_c_16__n a_5__n a_c_17__n a_4__n a_c_18__n a_3__n \ -# a_c_19__n a_2__n a_c_20__n a_1__n a_c_21__n a_c_22__n a_c_23__n a_c_24__n a_c_25__n \ -# a_c_26__n a_c_27__n a_c_28__n a_c_29__n a_c_30__n a_c_31__n CPU_SPACE_c BG_030_c \ -# BG_000DFFSHreg BGACK_000_c CLK_030_c CLK_000_c +#$ PINS 74 A_21_ A_20_ SIZE_1_ A_19_ A_18_ A_31_ A_17_ A_16_ IPL_030_2_ A_15_ A_14_ \ +# IPL_2_ A_13_ A_12_ DSACK_1_ A_11_ A_10_ FC_1_ A_9_ AS_030 A_8_ AS_000 A_7_ DS_030 A_6_ \ +# UDS_000 A_5_ LDS_000 A_4_ CPU_SPACE A_3_ BERR A_2_ BG_030 A_1_ BG_000 A_0_ BGACK_030 \ +# IPL_030_1_ BGACK_000 IPL_030_0_ CLK_030 IPL_1_ CLK_000 IPL_0_ CLK_OSZI DSACK_0_ \ +# CLK_DIV_OUT FC_0_ CLK_EXP FPU_CS DTACK AVEC AVEC_EXP E VPA VMA RST RESET RW \ +# AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ \ +# A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ +#$ NODES 344 IPL_030DFFSH_1_reg IPL_030DFFSH_2_reg ipl_c_0__n ipl_c_1__n \ +# inst_BGACK_030_INTreg inst_FPU_CS_INTreg ipl_c_2__n cpu_est_3_reg inst_VMA_INTreg \ +# gnd_n_n dsack_c_1__n cpu_est_0_ cpu_est_1_ DTACK_c inst_AS_000_INTreg \ +# inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D \ +# inst_CLK_000_DD inst_CLK_OUT_PRE RST_c vcc_n_n cpu_est_2_ RESETDFFreg CLK_CNT_0_ \ +# SM_AMIGA_6_ RW_c SM_AMIGA_7_ inst_UDS_000_INTreg fc_c_0__n inst_LDS_000_INTreg \ +# state_machine_un1_clk_030_n fc_c_1__n SM_AMIGA_1_ DSACK_INT_1_ inst_DTACK_DMA \ +# SM_AMIGA_4_ state_machine_un6_bgack_000_n SM_AMIGA_3_ N_99_i \ +# state_machine_un13_as_000_int_n un1_bg_030 N_101_i SM_AMIGA_5_ sm_amiga_ns_0_2__n \ +# SM_AMIGA_2_ N_107_i SM_AMIGA_0_ N_106_i sm_amiga_ns_0_5__n N_108_i N_109_i N_110_i \ +# sm_amiga_ns_0_7__n N_91_0 CLK_OUT_PRE_i N_94_0 state_machine_un8_clk_000_d_i_n \ +# state_machine_un13_clk_000_d_i_n cpu_est_0_0_ state_machine_un15_clk_000_d_0_n \ +# N_93_0 N_104_i N_105_i N_103_i CLK_OUT_PRE_0 state_machine_un60_clk_000_d_i_n \ +# state_machine_un17_clk_030_0_n un1_as_030_3_0 N_145_i clk_un4_clk_000_dd_n \ +# a_c_i_0__n clk_cpu_est_11_1__n state_machine_uds_000_int_8_0_n \ +# state_machine_un42_clk_030_n state_machine_lds_000_int_8_0_n N_102 \ +# state_machine_as_030_000_sync_3_2_n N_98 size_c_i_1__n N_97 \ +# state_machine_un34_clk_000_d_i_n N_100 N_131_i N_92 N_132_i N_112 N_122_i N_127 \ +# N_125_i N_125 N_126_i N_128 N_134_i N_129 N_133_i N_130 N_135_i N_168 \ +# clk_cpu_est_11_0_3__n N_171 N_130_i N_135_1 clk_cpu_est_11_0_1__n \ +# state_machine_un13_clk_000_d_2_n N_128_i clk_cpu_est_11_3__n un1_bg_030_0 N_135 \ +# N_97_i N_133 BG_030_c_i N_134 N_127_i N_132 N_129_i N_131 N_92_0 N_126 N_100_i \ +# state_machine_un34_clk_000_d_n N_112_i UDS_000_INT_0_sqmuxa \ +# UDS_000_INT_0_sqmuxa_1 clk_un4_clk_000_dd_i_n state_machine_as_030_000_sync_3_n \ +# state_machine_un6_bgack_000_0_n N_145 state_machine_un1_clk_030_0_n \ +# state_machine_lds_000_int_8_n clk_cpu_est_11_0_1_3__n \ +# state_machine_uds_000_int_8_n state_machine_un34_clk_000_d_i_1_n un1_as_030_4 \ +# state_machine_as_030_000_sync_3_2_1_n un1_as_030_3 N_168_1 DSACK_INT_1_sqmuxa \ +# N_168_2 state_machine_un17_clk_030_n N_168_3 state_machine_un60_clk_000_d_n \ +# N_168_4 DTACK_SYNC_1_sqmuxa N_168_5 DTACK_SYNC_1_sqmuxa_1 N_168_6 VPA_SYNC_1_sqmuxa \ +# N_171_1 VPA_SYNC_1_sqmuxa_1 N_171_2 N_103 un1_bg_030_0_1 N_104 un1_bg_030_0_2 N_93 \ +# clk_cpu_est_11_0_1_1__n N_105 clk_cpu_est_11_0_2_1__n VPA_SYNC_1_sqmuxa_1_0 \ +# state_machine_un42_clk_030_1_n state_machine_un15_clk_000_d_n \ +# state_machine_un42_clk_030_2_n state_machine_un13_clk_000_d_n \ +# state_machine_un42_clk_030_3_n state_machine_un8_clk_000_d_n \ +# state_machine_un42_clk_030_4_n state_machine_un8_clk_000_d_1_n \ +# state_machine_un42_clk_030_5_n state_machine_un13_clk_000_d_1_n N_132_1 N_107 \ +# N_131_1 N_94 UDS_000_INT_0_sqmuxa_1_0 N_91 UDS_000_INT_0_sqmuxa_2 N_110 \ +# UDS_000_INT_0_sqmuxa_1_1 N_108 UDS_000_INT_0_sqmuxa_1_2 N_109 \ +# UDS_000_INT_0_sqmuxa_1_3 N_106 DTACK_SYNC_1_sqmuxa_1_0 N_101 \ +# state_machine_un8_clk_000_d_1_0_n N_99 state_machine_un8_clk_000_d_2_n \ +# AS_000_INT_1_sqmuxa state_machine_un8_clk_000_d_3_n RW_i \ +# state_machine_un13_clk_000_d_1_0_n N_102_i state_machine_un13_clk_000_d_2_0_n \ +# AS_000_INT_i VPA_SYNC_1_sqmuxa_1_1 dsack_i_1__n VPA_SYNC_1_sqmuxa_2 AS_030_i \ +# VPA_SYNC_1_sqmuxa_3 sm_amiga_i_7__n VPA_SYNC_1_sqmuxa_4 CLK_000_D_i N_107_1 \ +# sm_amiga_i_2__n N_98_1 sm_amiga_i_1__n as_000_int_0_un3_n \ +# state_machine_un13_clk_000_d_1_i_n as_000_int_0_un1_n VPA_D_i as_000_int_0_un0_n \ +# VMA_INT_i vma_int_0_un3_n cpu_est_i_0__n vma_int_0_un1_n cpu_est_i_1__n \ +# vma_int_0_un0_n cpu_est_i_3__n uds_000_int_0_un3_n \ +# state_machine_un8_clk_000_d_1_i_0_n uds_000_int_0_un1_n DTACK_i \ +# uds_000_int_0_un0_n sm_amiga_i_3__n dtack_sync_0_un3_n sm_amiga_i_4__n \ +# dtack_sync_0_un1_n sm_amiga_i_5__n dtack_sync_0_un0_n DTACK_SYNC_1_sqmuxa_i \ +# vpa_sync_0_un3_n VPA_SYNC_1_sqmuxa_i vpa_sync_0_un1_n N_98_i vpa_sync_0_un0_n \ +# state_machine_un42_clk_030_i_n dsack_int_0_1__un3_n UDS_000_INT_0_sqmuxa_1_i \ +# dsack_int_0_1__un1_n UDS_000_INT_0_sqmuxa_i dsack_int_0_1__un0_n \ +# AS_030_000_SYNC_i as_030_000_sync_0_un3_n DS_030_i as_030_000_sync_0_un1_n \ +# cpu_est_i_2__n as_030_000_sync_0_un0_n state_machine_un13_clk_000_d_2_i_n \ +# fpu_cs_int_0_un3_n CLK_000_DD_i fpu_cs_int_0_un1_n sm_amiga_i_6__n \ +# fpu_cs_int_0_un0_n CLK_030_i lds_000_int_0_un3_n a_i_30__n lds_000_int_0_un1_n \ +# a_i_31__n lds_000_int_0_un0_n a_i_28__n cpu_est_0_3__un3_n a_i_29__n \ +# cpu_est_0_3__un1_n a_i_26__n cpu_est_0_3__un0_n a_i_27__n cpu_est_0_2__un3_n \ +# a_i_24__n cpu_est_0_2__un1_n a_i_25__n cpu_est_0_2__un0_n a_i_19__n bg_000_0_un3_n \ +# a_i_16__n bg_000_0_un1_n a_i_18__n bg_000_0_un0_n bgack_030_int_0_un3_n RST_i \ +# bgack_030_int_0_un1_n bgack_030_int_0_un0_n FPU_CS_INT_i cpu_est_0_1__un3_n \ +# CPU_SPACE_i cpu_est_0_1__un1_n BGACK_030_INT_i cpu_est_0_1__un0_n AS_030_c \ +# ipl_030_0_0__un3_n ipl_030_0_0__un1_n ipl_030_0_0__un0_n DS_030_c \ +# ipl_030_0_1__un3_n ipl_030_0_1__un1_n ipl_030_0_1__un0_n ipl_030_0_2__un3_n \ +# size_c_0__n ipl_030_0_2__un1_n ipl_030_0_2__un0_n size_c_1__n a_15__n a_c_0__n \ +# a_14__n a_13__n a_12__n a_11__n a_10__n a_9__n a_8__n a_7__n a_6__n a_c_16__n a_5__n \ +# a_c_17__n a_4__n a_c_18__n a_3__n a_c_19__n a_2__n a_c_20__n a_1__n a_c_21__n a_c_22__n \ +# a_c_23__n a_c_24__n a_c_25__n a_c_26__n a_c_27__n a_c_28__n a_c_29__n a_c_30__n \ +# a_c_31__n CPU_SPACE_c BG_030_c BG_000DFFSHreg BGACK_000_c CLK_030_c CLK_OSZI_c \ +# CLK_OUT_INTreg IPL_030DFFSH_0_reg .model bus68030 .inputs SIZE_1_.BLIF A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF AS_030.BLIF DS_030.BLIF \ CPU_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF \ @@ -89,219 +90,208 @@ A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF A_15_.BLIF \ A_14_.BLIF A_13_.BLIF A_12_.BLIF A_11_.BLIF A_10_.BLIF A_9_.BLIF A_8_.BLIF \ A_7_.BLIF A_6_.BLIF A_5_.BLIF A_4_.BLIF A_3_.BLIF A_2_.BLIF A_1_.BLIF \ A_0_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF DSACK_1_.BLIF DTACK.BLIF \ -DSACK_0_.BLIF CLK_OSZI_c.BLIF CLK_OUT_INTreg.BLIF IPL_030DFFSH_0_reg.BLIF \ -inst_BGACK_030_INTreg.BLIF inst_FPU_CS_INTreg.BLIF IPL_030DFFSH_1_reg.BLIF \ -cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF IPL_030DFFSH_2_reg.BLIF gnd_n_n.BLIF \ -cpu_est_0_.BLIF ipl_c_0__n.BLIF cpu_est_1_.BLIF cpu_est_d_0_.BLIF \ -ipl_c_1__n.BLIF cpu_est_d_3_.BLIF inst_AS_000_INTreg.BLIF ipl_c_2__n.BLIF \ -inst_AS_030_000_SYNC.BLIF inst_DTACK_SYNC.BLIF inst_VPA_D.BLIF \ -dsack_c_1__n.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D.BLIF DTACK_c.BLIF \ -inst_CLK_000_DD.BLIF inst_CLK_OUT_PRE.BLIF vcc_n_n.BLIF cpu_est_d_1_.BLIF \ -cpu_est_d_2_.BLIF cpu_est_2_.BLIF CLK_CNT_0_.BLIF SM_AMIGA_6_.BLIF RST_c.BLIF \ -SM_AMIGA_7_.BLIF inst_UDS_000_INTreg.BLIF RESETDFFreg.BLIF \ -inst_LDS_000_INTreg.BLIF RW_c.BLIF inst_RISING_CLK_AMIGA.BLIF \ -state_machine_un57_clk_000_d_n.BLIF fc_c_0__n.BLIF SM_AMIGA_1_.BLIF \ -DSACK_INT_1_.BLIF fc_c_1__n.BLIF inst_DTACK_DMA.BLIF SM_AMIGA_4_.BLIF \ -SM_AMIGA_3_.BLIF state_machine_un13_as_000_int_n.BLIF SM_AMIGA_5_.BLIF \ -SM_AMIGA_2_.BLIF N_145_i.BLIF SM_AMIGA_0_.BLIF a_c_i_0__n.BLIF \ -state_machine_uds_000_int_8_0_n.BLIF state_machine_lds_000_int_8_0_n.BLIF \ -N_99_i.BLIF N_112_i.BLIF N_100_i.BLIF N_101_i.BLIF sm_amiga_ns_0_2__n.BLIF \ -N_103_i.BLIF N_110_i.BLIF sm_amiga_ns_0_7__n.BLIF cpu_est_0_0_.BLIF \ -N_91_0.BLIF N_92_0.BLIF N_131_i.BLIF N_132_i.BLIF N_122_i.BLIF \ -CLK_OUT_PRE_0.BLIF N_124_i.BLIF N_125_i.BLIF N_126_i.BLIF N_129_i.BLIF \ -N_98.BLIF N_127_i.BLIF N_97.BLIF N_128_i.BLIF N_104.BLIF N_130_i.BLIF \ -N_93.BLIF clk_cpu_est_11_0_1__n.BLIF N_105.BLIF N_134_i.BLIF N_106.BLIF \ -N_133_i.BLIF N_108.BLIF N_135_i.BLIF N_94.BLIF clk_cpu_est_11_0_3__n.BLIF \ -N_109.BLIF size_c_i_1__n.BLIF N_107.BLIF state_machine_un31_clk_000_d_i_n.BLIF \ -N_135_1.BLIF state_machine_as_030_000_sync_3_0_n.BLIF \ -VPA_SYNC_1_sqmuxa_1_0.BLIF un1_as_030_2_0.BLIF N_167.BLIF \ -state_machine_un17_clk_030_0_n.BLIF N_170.BLIF \ -state_machine_un57_clk_000_d_0_n.BLIF state_machine_un42_clk_030_n.BLIF \ -RISING_CLK_AMIGA_i.BLIF DTACK_SYNC_1_sqmuxa.BLIF \ -state_machine_un4_bgack_000_0_n.BLIF VPA_SYNC_1_sqmuxa.BLIF BG_030_c_i.BLIF \ -un1_bg_030.BLIF state_machine_un1_clk_030_0_n.BLIF DTACK_SYNC_1_sqmuxa_1.BLIF \ -N_97_i.BLIF DSACK_INT_1_sqmuxa.BLIF un1_bg_030_0.BLIF \ -state_machine_un1_clk_030_n.BLIF CLK_OUT_PRE_i.BLIF \ -state_machine_un4_bgack_000_n.BLIF N_94_0.BLIF un1_as_030_2.BLIF N_93_0.BLIF \ -state_machine_un17_clk_030_n.BLIF N_108_i.BLIF N_102.BLIF N_109_i.BLIF \ -AS_000_INT_1_sqmuxa.BLIF VPA_SYNC_1_sqmuxa_1.BLIF N_106_i.BLIF \ -state_machine_as_030_000_sync_3_n.BLIF N_107_i.BLIF clk_un3_clk_000_dd_n.BLIF \ -sm_amiga_ns_0_5__n.BLIF state_machine_un31_clk_000_d_n.BLIF N_104_i.BLIF \ -UDS_000_INT_0_sqmuxa.BLIF N_105_i.BLIF state_machine_un13_clk_000_d_n.BLIF \ -state_machine_un13_clk_000_d_4_n.BLIF un1_bg_030_0_1.BLIF \ -state_machine_un13_clk_000_d_1_n.BLIF un1_bg_030_0_2.BLIF \ -state_machine_un8_clk_000_d_n.BLIF state_machine_un31_clk_000_d_i_1_n.BLIF \ -UDS_000_INT_0_sqmuxa_1.BLIF clk_cpu_est_11_0_1_3__n.BLIF N_132.BLIF \ -clk_cpu_est_11_0_1_1__n.BLIF N_131.BLIF clk_cpu_est_11_0_2_1__n.BLIF \ -N_124.BLIF N_167_1.BLIF clk_cpu_est_11_3__n.BLIF N_167_2.BLIF N_135.BLIF \ -N_167_3.BLIF N_133.BLIF N_167_4.BLIF N_134.BLIF N_167_5.BLIF \ -clk_cpu_est_11_1__n.BLIF N_167_6.BLIF N_130.BLIF N_170_1.BLIF N_128.BLIF \ -N_170_2.BLIF N_145.BLIF N_107_1.BLIF N_127.BLIF \ -state_machine_un42_clk_030_1_n.BLIF N_129.BLIF \ -state_machine_un42_clk_030_2_n.BLIF N_126.BLIF \ -state_machine_un42_clk_030_3_n.BLIF N_125.BLIF \ -state_machine_un42_clk_030_4_n.BLIF N_92.BLIF \ -state_machine_un42_clk_030_5_n.BLIF N_91.BLIF DTACK_SYNC_1_sqmuxa_1_0.BLIF \ -N_110.BLIF VPA_SYNC_1_sqmuxa_1_1.BLIF N_103.BLIF VPA_SYNC_1_sqmuxa_2.BLIF \ -N_101.BLIF VPA_SYNC_1_sqmuxa_3.BLIF N_100.BLIF VPA_SYNC_1_sqmuxa_4.BLIF \ -N_112.BLIF N_98_1.BLIF N_99.BLIF state_machine_as_030_000_sync_3_0_1_n.BLIF \ -state_machine_lds_000_int_8_n.BLIF UDS_000_INT_0_sqmuxa_1_0.BLIF \ -state_machine_uds_000_int_8_n.BLIF UDS_000_INT_0_sqmuxa_2.BLIF \ -un2_clk_030_1.BLIF state_machine_un13_clk_000_d_1_0_n.BLIF \ -VMA_INT_1_sqmuxa.BLIF state_machine_un13_clk_000_d_4_1_n.BLIF RW_i.BLIF \ -state_machine_un8_clk_000_d_1_n.BLIF cpu_est_d_i_3__n.BLIF \ -state_machine_un8_clk_000_d_2_n.BLIF cpu_est_d_i_0__n.BLIF \ -state_machine_un8_clk_000_d_3_n.BLIF CLK_000_D_i.BLIF \ -state_machine_un8_clk_000_d_4_n.BLIF AS_000_INT_i.BLIF \ -UDS_000_INT_0_sqmuxa_1_1.BLIF dsack_i_1__n.BLIF UDS_000_INT_0_sqmuxa_1_2.BLIF \ -state_machine_un13_clk_000_d_i_n.BLIF UDS_000_INT_0_sqmuxa_1_3.BLIF \ -state_machine_un8_clk_000_d_i_n.BLIF N_132_1.BLIF AS_030_i.BLIF N_131_1.BLIF \ -sm_amiga_i_6__n.BLIF vma_int_0_un3_n.BLIF sm_amiga_i_7__n.BLIF \ -vma_int_0_un1_n.BLIF sm_amiga_i_5__n.BLIF vma_int_0_un0_n.BLIF \ -sm_amiga_i_4__n.BLIF lds_000_int_0_un3_n.BLIF \ -state_machine_un13_clk_000_d_1_i_n.BLIF lds_000_int_0_un1_n.BLIF \ -CLK_000_DD_i.BLIF lds_000_int_0_un0_n.BLIF AS_030_000_SYNC_i.BLIF \ -uds_000_int_0_un3_n.BLIF cpu_est_i_0__n.BLIF uds_000_int_0_un1_n.BLIF \ -cpu_est_i_2__n.BLIF uds_000_int_0_un0_n.BLIF cpu_est_i_3__n.BLIF \ -cpu_est_0_3__un3_n.BLIF cpu_est_i_1__n.BLIF cpu_est_0_3__un1_n.BLIF \ -UDS_000_INT_0_sqmuxa_1_i.BLIF cpu_est_0_3__un0_n.BLIF \ -UDS_000_INT_0_sqmuxa_i.BLIF cpu_est_0_2__un3_n.BLIF DS_030_i.BLIF \ -cpu_est_0_2__un1_n.BLIF VPA_D_i.BLIF cpu_est_0_2__un0_n.BLIF \ -state_machine_un42_clk_030_i_n.BLIF cpu_est_0_1__un3_n.BLIF \ -VPA_SYNC_1_sqmuxa_i.BLIF cpu_est_0_1__un1_n.BLIF N_102_i.BLIF \ -cpu_est_0_1__un0_n.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF fpu_cs_int_0_un3_n.BLIF \ -N_98_i.BLIF fpu_cs_int_0_un1_n.BLIF a_i_18__n.BLIF fpu_cs_int_0_un0_n.BLIF \ -a_i_16__n.BLIF as_000_int_0_un3_n.BLIF a_i_19__n.BLIF as_000_int_0_un1_n.BLIF \ -CLK_030_i.BLIF as_000_int_0_un0_n.BLIF VMA_INT_i.BLIF vpa_sync_0_un3_n.BLIF \ -DTACK_i.BLIF vpa_sync_0_un1_n.BLIF sm_amiga_i_3__n.BLIF vpa_sync_0_un0_n.BLIF \ -sm_amiga_i_1__n.BLIF as_030_000_sync_0_un3_n.BLIF sm_amiga_i_2__n.BLIF \ -as_030_000_sync_0_un1_n.BLIF a_i_30__n.BLIF as_030_000_sync_0_un0_n.BLIF \ -a_i_31__n.BLIF ipl_030_0_2__un3_n.BLIF a_i_28__n.BLIF ipl_030_0_2__un1_n.BLIF \ -a_i_29__n.BLIF ipl_030_0_2__un0_n.BLIF a_i_26__n.BLIF ipl_030_0_1__un3_n.BLIF \ -a_i_27__n.BLIF ipl_030_0_1__un1_n.BLIF a_i_24__n.BLIF ipl_030_0_1__un0_n.BLIF \ -a_i_25__n.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un1_n.BLIF \ -ipl_030_0_0__un0_n.BLIF RST_i.BLIF bgack_030_int_0_un3_n.BLIF \ -FPU_CS_INT_i.BLIF bgack_030_int_0_un1_n.BLIF CPU_SPACE_i.BLIF \ -bgack_030_int_0_un0_n.BLIF BGACK_030_INT_i.BLIF dsack_int_0_1__un3_n.BLIF \ -AS_030_c.BLIF dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF \ -bg_000_0_un3_n.BLIF DS_030_c.BLIF bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF \ -dtack_sync_0_un3_n.BLIF dtack_sync_0_un1_n.BLIF size_c_0__n.BLIF \ -dtack_sync_0_un0_n.BLIF a_15__n.BLIF size_c_1__n.BLIF a_14__n.BLIF \ -a_c_0__n.BLIF a_13__n.BLIF a_12__n.BLIF a_11__n.BLIF a_10__n.BLIF a_9__n.BLIF \ +DSACK_0_.BLIF IPL_030DFFSH_1_reg.BLIF IPL_030DFFSH_2_reg.BLIF ipl_c_0__n.BLIF \ +ipl_c_1__n.BLIF inst_BGACK_030_INTreg.BLIF inst_FPU_CS_INTreg.BLIF \ +ipl_c_2__n.BLIF cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF gnd_n_n.BLIF \ +dsack_c_1__n.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF DTACK_c.BLIF \ +inst_AS_000_INTreg.BLIF inst_AS_030_000_SYNC.BLIF inst_DTACK_SYNC.BLIF \ +inst_VPA_D.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF \ +inst_CLK_OUT_PRE.BLIF RST_c.BLIF vcc_n_n.BLIF cpu_est_2_.BLIF RESETDFFreg.BLIF \ +CLK_CNT_0_.BLIF SM_AMIGA_6_.BLIF RW_c.BLIF SM_AMIGA_7_.BLIF \ +inst_UDS_000_INTreg.BLIF fc_c_0__n.BLIF inst_LDS_000_INTreg.BLIF \ +state_machine_un1_clk_030_n.BLIF fc_c_1__n.BLIF SM_AMIGA_1_.BLIF \ +DSACK_INT_1_.BLIF inst_DTACK_DMA.BLIF SM_AMIGA_4_.BLIF \ +state_machine_un6_bgack_000_n.BLIF SM_AMIGA_3_.BLIF N_99_i.BLIF \ +state_machine_un13_as_000_int_n.BLIF un1_bg_030.BLIF N_101_i.BLIF \ +SM_AMIGA_5_.BLIF sm_amiga_ns_0_2__n.BLIF SM_AMIGA_2_.BLIF N_107_i.BLIF \ +SM_AMIGA_0_.BLIF N_106_i.BLIF sm_amiga_ns_0_5__n.BLIF N_108_i.BLIF \ +N_109_i.BLIF N_110_i.BLIF sm_amiga_ns_0_7__n.BLIF N_91_0.BLIF \ +CLK_OUT_PRE_i.BLIF N_94_0.BLIF state_machine_un8_clk_000_d_i_n.BLIF \ +state_machine_un13_clk_000_d_i_n.BLIF cpu_est_0_0_.BLIF \ +state_machine_un15_clk_000_d_0_n.BLIF N_93_0.BLIF N_104_i.BLIF N_105_i.BLIF \ +N_103_i.BLIF CLK_OUT_PRE_0.BLIF state_machine_un60_clk_000_d_i_n.BLIF \ +state_machine_un17_clk_030_0_n.BLIF un1_as_030_3_0.BLIF N_145_i.BLIF \ +clk_un4_clk_000_dd_n.BLIF a_c_i_0__n.BLIF clk_cpu_est_11_1__n.BLIF \ +state_machine_uds_000_int_8_0_n.BLIF state_machine_un42_clk_030_n.BLIF \ +state_machine_lds_000_int_8_0_n.BLIF N_102.BLIF \ +state_machine_as_030_000_sync_3_2_n.BLIF N_98.BLIF size_c_i_1__n.BLIF \ +N_97.BLIF state_machine_un34_clk_000_d_i_n.BLIF N_100.BLIF N_131_i.BLIF \ +N_92.BLIF N_132_i.BLIF N_112.BLIF N_122_i.BLIF N_127.BLIF N_125_i.BLIF \ +N_125.BLIF N_126_i.BLIF N_128.BLIF N_134_i.BLIF N_129.BLIF N_133_i.BLIF \ +N_130.BLIF N_135_i.BLIF N_168.BLIF clk_cpu_est_11_0_3__n.BLIF N_171.BLIF \ +N_130_i.BLIF N_135_1.BLIF clk_cpu_est_11_0_1__n.BLIF \ +state_machine_un13_clk_000_d_2_n.BLIF N_128_i.BLIF clk_cpu_est_11_3__n.BLIF \ +un1_bg_030_0.BLIF N_135.BLIF N_97_i.BLIF N_133.BLIF BG_030_c_i.BLIF N_134.BLIF \ +N_127_i.BLIF N_132.BLIF N_129_i.BLIF N_131.BLIF N_92_0.BLIF N_126.BLIF \ +N_100_i.BLIF state_machine_un34_clk_000_d_n.BLIF N_112_i.BLIF \ +UDS_000_INT_0_sqmuxa.BLIF UDS_000_INT_0_sqmuxa_1.BLIF \ +clk_un4_clk_000_dd_i_n.BLIF state_machine_as_030_000_sync_3_n.BLIF \ +state_machine_un6_bgack_000_0_n.BLIF N_145.BLIF \ +state_machine_un1_clk_030_0_n.BLIF state_machine_lds_000_int_8_n.BLIF \ +clk_cpu_est_11_0_1_3__n.BLIF state_machine_uds_000_int_8_n.BLIF \ +state_machine_un34_clk_000_d_i_1_n.BLIF un1_as_030_4.BLIF \ +state_machine_as_030_000_sync_3_2_1_n.BLIF un1_as_030_3.BLIF N_168_1.BLIF \ +DSACK_INT_1_sqmuxa.BLIF N_168_2.BLIF state_machine_un17_clk_030_n.BLIF \ +N_168_3.BLIF state_machine_un60_clk_000_d_n.BLIF N_168_4.BLIF \ +DTACK_SYNC_1_sqmuxa.BLIF N_168_5.BLIF DTACK_SYNC_1_sqmuxa_1.BLIF N_168_6.BLIF \ +VPA_SYNC_1_sqmuxa.BLIF N_171_1.BLIF VPA_SYNC_1_sqmuxa_1.BLIF N_171_2.BLIF \ +N_103.BLIF un1_bg_030_0_1.BLIF N_104.BLIF un1_bg_030_0_2.BLIF N_93.BLIF \ +clk_cpu_est_11_0_1_1__n.BLIF N_105.BLIF clk_cpu_est_11_0_2_1__n.BLIF \ +VPA_SYNC_1_sqmuxa_1_0.BLIF state_machine_un42_clk_030_1_n.BLIF \ +state_machine_un15_clk_000_d_n.BLIF state_machine_un42_clk_030_2_n.BLIF \ +state_machine_un13_clk_000_d_n.BLIF state_machine_un42_clk_030_3_n.BLIF \ +state_machine_un8_clk_000_d_n.BLIF state_machine_un42_clk_030_4_n.BLIF \ +state_machine_un8_clk_000_d_1_n.BLIF state_machine_un42_clk_030_5_n.BLIF \ +state_machine_un13_clk_000_d_1_n.BLIF N_132_1.BLIF N_107.BLIF N_131_1.BLIF \ +N_94.BLIF UDS_000_INT_0_sqmuxa_1_0.BLIF N_91.BLIF UDS_000_INT_0_sqmuxa_2.BLIF \ +N_110.BLIF UDS_000_INT_0_sqmuxa_1_1.BLIF N_108.BLIF \ +UDS_000_INT_0_sqmuxa_1_2.BLIF N_109.BLIF UDS_000_INT_0_sqmuxa_1_3.BLIF \ +N_106.BLIF DTACK_SYNC_1_sqmuxa_1_0.BLIF N_101.BLIF \ +state_machine_un8_clk_000_d_1_0_n.BLIF N_99.BLIF \ +state_machine_un8_clk_000_d_2_n.BLIF AS_000_INT_1_sqmuxa.BLIF \ +state_machine_un8_clk_000_d_3_n.BLIF RW_i.BLIF \ +state_machine_un13_clk_000_d_1_0_n.BLIF N_102_i.BLIF \ +state_machine_un13_clk_000_d_2_0_n.BLIF AS_000_INT_i.BLIF \ +VPA_SYNC_1_sqmuxa_1_1.BLIF dsack_i_1__n.BLIF VPA_SYNC_1_sqmuxa_2.BLIF \ +AS_030_i.BLIF VPA_SYNC_1_sqmuxa_3.BLIF sm_amiga_i_7__n.BLIF \ +VPA_SYNC_1_sqmuxa_4.BLIF CLK_000_D_i.BLIF N_107_1.BLIF sm_amiga_i_2__n.BLIF \ +N_98_1.BLIF sm_amiga_i_1__n.BLIF as_000_int_0_un3_n.BLIF \ +state_machine_un13_clk_000_d_1_i_n.BLIF as_000_int_0_un1_n.BLIF VPA_D_i.BLIF \ +as_000_int_0_un0_n.BLIF VMA_INT_i.BLIF vma_int_0_un3_n.BLIF \ +cpu_est_i_0__n.BLIF vma_int_0_un1_n.BLIF cpu_est_i_1__n.BLIF \ +vma_int_0_un0_n.BLIF cpu_est_i_3__n.BLIF uds_000_int_0_un3_n.BLIF \ +state_machine_un8_clk_000_d_1_i_0_n.BLIF uds_000_int_0_un1_n.BLIF DTACK_i.BLIF \ +uds_000_int_0_un0_n.BLIF sm_amiga_i_3__n.BLIF dtack_sync_0_un3_n.BLIF \ +sm_amiga_i_4__n.BLIF dtack_sync_0_un1_n.BLIF sm_amiga_i_5__n.BLIF \ +dtack_sync_0_un0_n.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF vpa_sync_0_un3_n.BLIF \ +VPA_SYNC_1_sqmuxa_i.BLIF vpa_sync_0_un1_n.BLIF N_98_i.BLIF \ +vpa_sync_0_un0_n.BLIF state_machine_un42_clk_030_i_n.BLIF \ +dsack_int_0_1__un3_n.BLIF UDS_000_INT_0_sqmuxa_1_i.BLIF \ +dsack_int_0_1__un1_n.BLIF UDS_000_INT_0_sqmuxa_i.BLIF \ +dsack_int_0_1__un0_n.BLIF AS_030_000_SYNC_i.BLIF as_030_000_sync_0_un3_n.BLIF \ +DS_030_i.BLIF as_030_000_sync_0_un1_n.BLIF cpu_est_i_2__n.BLIF \ +as_030_000_sync_0_un0_n.BLIF state_machine_un13_clk_000_d_2_i_n.BLIF \ +fpu_cs_int_0_un3_n.BLIF CLK_000_DD_i.BLIF fpu_cs_int_0_un1_n.BLIF \ +sm_amiga_i_6__n.BLIF fpu_cs_int_0_un0_n.BLIF CLK_030_i.BLIF \ +lds_000_int_0_un3_n.BLIF a_i_30__n.BLIF lds_000_int_0_un1_n.BLIF \ +a_i_31__n.BLIF lds_000_int_0_un0_n.BLIF a_i_28__n.BLIF cpu_est_0_3__un3_n.BLIF \ +a_i_29__n.BLIF cpu_est_0_3__un1_n.BLIF a_i_26__n.BLIF cpu_est_0_3__un0_n.BLIF \ +a_i_27__n.BLIF cpu_est_0_2__un3_n.BLIF a_i_24__n.BLIF cpu_est_0_2__un1_n.BLIF \ +a_i_25__n.BLIF cpu_est_0_2__un0_n.BLIF a_i_19__n.BLIF bg_000_0_un3_n.BLIF \ +a_i_16__n.BLIF bg_000_0_un1_n.BLIF a_i_18__n.BLIF bg_000_0_un0_n.BLIF \ +bgack_030_int_0_un3_n.BLIF RST_i.BLIF bgack_030_int_0_un1_n.BLIF \ +bgack_030_int_0_un0_n.BLIF FPU_CS_INT_i.BLIF cpu_est_0_1__un3_n.BLIF \ +CPU_SPACE_i.BLIF cpu_est_0_1__un1_n.BLIF BGACK_030_INT_i.BLIF \ +cpu_est_0_1__un0_n.BLIF AS_030_c.BLIF ipl_030_0_0__un3_n.BLIF \ +ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF DS_030_c.BLIF \ +ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF \ +ipl_030_0_2__un3_n.BLIF size_c_0__n.BLIF ipl_030_0_2__un1_n.BLIF \ +ipl_030_0_2__un0_n.BLIF size_c_1__n.BLIF a_15__n.BLIF a_c_0__n.BLIF \ +a_14__n.BLIF a_13__n.BLIF a_12__n.BLIF a_11__n.BLIF a_10__n.BLIF a_9__n.BLIF \ a_8__n.BLIF a_7__n.BLIF a_6__n.BLIF a_c_16__n.BLIF a_5__n.BLIF a_c_17__n.BLIF \ a_4__n.BLIF a_c_18__n.BLIF a_3__n.BLIF a_c_19__n.BLIF a_2__n.BLIF \ a_c_20__n.BLIF a_1__n.BLIF a_c_21__n.BLIF a_c_22__n.BLIF a_c_23__n.BLIF \ a_c_24__n.BLIF a_c_25__n.BLIF a_c_26__n.BLIF a_c_27__n.BLIF a_c_28__n.BLIF \ a_c_29__n.BLIF a_c_30__n.BLIF a_c_31__n.BLIF CPU_SPACE_c.BLIF BG_030_c.BLIF \ -BG_000DFFSHreg.BLIF BGACK_000_c.BLIF CLK_030_c.BLIF CLK_000_c.BLIF \ -DSACK_1_.PIN.BLIF DTACK.PIN.BLIF +BG_000DFFSHreg.BLIF BGACK_000_c.BLIF CLK_030_c.BLIF CLK_OSZI_c.BLIF \ +CLK_OUT_INTreg.BLIF IPL_030DFFSH_0_reg.BLIF DSACK_1_.PIN.BLIF DTACK.PIN.BLIF .outputs IPL_030_2_ AS_000 UDS_000 LDS_000 BERR BG_000 BGACK_030 CLK_DIV_OUT \ CLK_EXP FPU_CS AVEC AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR \ -AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ cpu_est_3_reg.D \ -cpu_est_3_reg.C SM_AMIGA_7_.D SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.D \ -SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR \ -SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C \ +AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_3_.D SM_AMIGA_3_.C \ SM_AMIGA_3_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D \ SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR \ -cpu_est_d_0_.D cpu_est_d_0_.C cpu_est_d_1_.D cpu_est_d_1_.C cpu_est_d_2_.D \ -cpu_est_d_2_.C cpu_est_d_3_.D cpu_est_d_3_.C IPL_030DFFSH_0_reg.D \ -IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP IPL_030DFFSH_1_reg.D \ -IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D \ -IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP cpu_est_0_.D cpu_est_0_.C \ -cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C inst_VPA_SYNC.D \ -inst_VPA_SYNC.C inst_VPA_SYNC.AP inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \ -inst_AS_030_000_SYNC.AP inst_VMA_INTreg.D inst_VMA_INTreg.C inst_VMA_INTreg.AP \ -BG_000DFFSHreg.D BG_000DFFSHreg.C BG_000DFFSHreg.AP DSACK_INT_1_.D \ -DSACK_INT_1_.C DSACK_INT_1_.AP inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C \ -inst_BGACK_030_INTreg.AP inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C \ -inst_UDS_000_INTreg.D inst_UDS_000_INTreg.C inst_UDS_000_INTreg.AP \ +IPL_030DFFSH_0_reg.D IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP \ +IPL_030DFFSH_1_reg.D IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP \ +IPL_030DFFSH_2_reg.D IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D \ +SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR \ +SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C \ +SM_AMIGA_4_.AR DSACK_INT_1_.D DSACK_INT_1_.C DSACK_INT_1_.AP inst_VMA_INTreg.D \ +inst_VMA_INTreg.C inst_VMA_INTreg.AP inst_BGACK_030_INTreg.D \ +inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP inst_CLK_OUT_PRE.D \ +inst_CLK_OUT_PRE.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C \ +cpu_est_2_.D cpu_est_2_.C cpu_est_3_reg.D cpu_est_3_reg.C \ inst_LDS_000_INTreg.D inst_LDS_000_INTreg.C inst_LDS_000_INTreg.AP \ inst_DTACK_SYNC.D inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_FPU_CS_INTreg.D \ -inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP inst_AS_000_INTreg.D \ -inst_AS_000_INTreg.C inst_AS_000_INTreg.AP inst_DTACK_DMA.D inst_DTACK_DMA.C \ -inst_DTACK_DMA.AP inst_RISING_CLK_AMIGA.D inst_RISING_CLK_AMIGA.C CLK_CNT_0_.D \ -CLK_CNT_0_.C inst_VPA_D.D inst_VPA_D.C inst_CLK_000_D.D inst_CLK_000_D.C \ -RESETDFFreg.D RESETDFFreg.C inst_CLK_000_DD.D inst_CLK_000_DD.C \ -CLK_OUT_INTreg.D CLK_OUT_INTreg.C DSACK_1_ DTACK DSACK_0_ CLK_OSZI_c gnd_n_n \ -ipl_c_0__n ipl_c_1__n ipl_c_2__n dsack_c_1__n DTACK_c vcc_n_n RST_c RW_c \ -state_machine_un57_clk_000_d_n fc_c_0__n fc_c_1__n \ -state_machine_un13_as_000_int_n N_145_i a_c_i_0__n \ -state_machine_uds_000_int_8_0_n state_machine_lds_000_int_8_0_n N_99_i N_112_i \ -N_100_i N_101_i sm_amiga_ns_0_2__n N_103_i N_110_i sm_amiga_ns_0_7__n N_91_0 \ -N_92_0 N_131_i N_132_i N_122_i N_124_i N_125_i N_126_i N_129_i N_98 N_127_i \ -N_97 N_128_i N_104 N_130_i N_93 clk_cpu_est_11_0_1__n N_105 N_134_i N_106 \ -N_133_i N_108 N_135_i N_94 clk_cpu_est_11_0_3__n N_109 size_c_i_1__n N_107 \ -state_machine_un31_clk_000_d_i_n N_135_1 state_machine_as_030_000_sync_3_0_n \ -VPA_SYNC_1_sqmuxa_1_0 un1_as_030_2_0 N_167 state_machine_un17_clk_030_0_n \ -N_170 state_machine_un57_clk_000_d_0_n state_machine_un42_clk_030_n \ -RISING_CLK_AMIGA_i DTACK_SYNC_1_sqmuxa state_machine_un4_bgack_000_0_n \ -VPA_SYNC_1_sqmuxa BG_030_c_i un1_bg_030 state_machine_un1_clk_030_0_n \ -DTACK_SYNC_1_sqmuxa_1 N_97_i DSACK_INT_1_sqmuxa un1_bg_030_0 \ -state_machine_un1_clk_030_n CLK_OUT_PRE_i state_machine_un4_bgack_000_n N_94_0 \ -un1_as_030_2 N_93_0 state_machine_un17_clk_030_n N_108_i N_102 N_109_i \ -AS_000_INT_1_sqmuxa VPA_SYNC_1_sqmuxa_1 N_106_i \ -state_machine_as_030_000_sync_3_n N_107_i clk_un3_clk_000_dd_n \ -sm_amiga_ns_0_5__n state_machine_un31_clk_000_d_n N_104_i UDS_000_INT_0_sqmuxa \ -N_105_i state_machine_un13_clk_000_d_n state_machine_un13_clk_000_d_4_n \ -un1_bg_030_0_1 state_machine_un13_clk_000_d_1_n un1_bg_030_0_2 \ -state_machine_un8_clk_000_d_n state_machine_un31_clk_000_d_i_1_n \ -UDS_000_INT_0_sqmuxa_1 clk_cpu_est_11_0_1_3__n N_132 clk_cpu_est_11_0_1_1__n \ -N_131 clk_cpu_est_11_0_2_1__n N_124 N_167_1 clk_cpu_est_11_3__n N_167_2 N_135 \ -N_167_3 N_133 N_167_4 N_134 N_167_5 clk_cpu_est_11_1__n N_167_6 N_130 N_170_1 \ -N_128 N_170_2 N_145 N_107_1 N_127 state_machine_un42_clk_030_1_n N_129 \ -state_machine_un42_clk_030_2_n N_126 state_machine_un42_clk_030_3_n N_125 \ -state_machine_un42_clk_030_4_n N_92 state_machine_un42_clk_030_5_n N_91 \ -DTACK_SYNC_1_sqmuxa_1_0 N_110 VPA_SYNC_1_sqmuxa_1_1 N_103 VPA_SYNC_1_sqmuxa_2 \ -N_101 VPA_SYNC_1_sqmuxa_3 N_100 VPA_SYNC_1_sqmuxa_4 N_112 N_98_1 N_99 \ -state_machine_as_030_000_sync_3_0_1_n state_machine_lds_000_int_8_n \ -UDS_000_INT_0_sqmuxa_1_0 state_machine_uds_000_int_8_n UDS_000_INT_0_sqmuxa_2 \ -un2_clk_030_1 state_machine_un13_clk_000_d_1_0_n VMA_INT_1_sqmuxa \ -state_machine_un13_clk_000_d_4_1_n RW_i state_machine_un8_clk_000_d_1_n \ -cpu_est_d_i_3__n state_machine_un8_clk_000_d_2_n cpu_est_d_i_0__n \ -state_machine_un8_clk_000_d_3_n CLK_000_D_i state_machine_un8_clk_000_d_4_n \ -AS_000_INT_i UDS_000_INT_0_sqmuxa_1_1 dsack_i_1__n UDS_000_INT_0_sqmuxa_1_2 \ -state_machine_un13_clk_000_d_i_n UDS_000_INT_0_sqmuxa_1_3 \ -state_machine_un8_clk_000_d_i_n N_132_1 AS_030_i N_131_1 sm_amiga_i_6__n \ -vma_int_0_un3_n sm_amiga_i_7__n vma_int_0_un1_n sm_amiga_i_5__n \ -vma_int_0_un0_n sm_amiga_i_4__n lds_000_int_0_un3_n \ -state_machine_un13_clk_000_d_1_i_n lds_000_int_0_un1_n CLK_000_DD_i \ -lds_000_int_0_un0_n AS_030_000_SYNC_i uds_000_int_0_un3_n cpu_est_i_0__n \ -uds_000_int_0_un1_n cpu_est_i_2__n uds_000_int_0_un0_n cpu_est_i_3__n \ -cpu_est_0_3__un3_n cpu_est_i_1__n cpu_est_0_3__un1_n UDS_000_INT_0_sqmuxa_1_i \ -cpu_est_0_3__un0_n UDS_000_INT_0_sqmuxa_i cpu_est_0_2__un3_n DS_030_i \ -cpu_est_0_2__un1_n VPA_D_i cpu_est_0_2__un0_n state_machine_un42_clk_030_i_n \ -cpu_est_0_1__un3_n VPA_SYNC_1_sqmuxa_i cpu_est_0_1__un1_n N_102_i \ -cpu_est_0_1__un0_n DTACK_SYNC_1_sqmuxa_i fpu_cs_int_0_un3_n N_98_i \ -fpu_cs_int_0_un1_n a_i_18__n fpu_cs_int_0_un0_n a_i_16__n as_000_int_0_un3_n \ -a_i_19__n as_000_int_0_un1_n CLK_030_i as_000_int_0_un0_n VMA_INT_i \ -vpa_sync_0_un3_n DTACK_i vpa_sync_0_un1_n sm_amiga_i_3__n vpa_sync_0_un0_n \ -sm_amiga_i_1__n as_030_000_sync_0_un3_n sm_amiga_i_2__n \ -as_030_000_sync_0_un1_n a_i_30__n as_030_000_sync_0_un0_n a_i_31__n \ -ipl_030_0_2__un3_n a_i_28__n ipl_030_0_2__un1_n a_i_29__n ipl_030_0_2__un0_n \ -a_i_26__n ipl_030_0_1__un3_n a_i_27__n ipl_030_0_1__un1_n a_i_24__n \ -ipl_030_0_1__un0_n a_i_25__n ipl_030_0_0__un3_n ipl_030_0_0__un1_n \ -ipl_030_0_0__un0_n RST_i bgack_030_int_0_un3_n FPU_CS_INT_i \ -bgack_030_int_0_un1_n CPU_SPACE_i bgack_030_int_0_un0_n BGACK_030_INT_i \ -dsack_int_0_1__un3_n AS_030_c dsack_int_0_1__un1_n dsack_int_0_1__un0_n \ -bg_000_0_un3_n DS_030_c bg_000_0_un1_n bg_000_0_un0_n dtack_sync_0_un3_n \ -dtack_sync_0_un1_n size_c_0__n dtack_sync_0_un0_n a_15__n size_c_1__n a_14__n \ -a_c_0__n a_13__n a_12__n a_11__n a_10__n a_9__n a_8__n a_7__n a_6__n a_c_16__n \ -a_5__n a_c_17__n a_4__n a_c_18__n a_3__n a_c_19__n a_2__n a_c_20__n a_1__n \ -a_c_21__n a_c_22__n a_c_23__n a_c_24__n a_c_25__n a_c_26__n a_c_27__n \ -a_c_28__n a_c_29__n a_c_30__n a_c_31__n CPU_SPACE_c BG_030_c BGACK_000_c \ -CLK_030_c CLK_000_c DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE \ -BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE cpu_est_0_0_ CLK_OUT_PRE_0 -.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_reg.D -1- 1 --1 1 -.names inst_CLK_000_D.BLIF N_99_i.BLIF SM_AMIGA_7_.D -11 1 -.names N_100_i.BLIF N_112_i.BLIF SM_AMIGA_6_.D -11 1 -.names sm_amiga_ns_0_2__n.BLIF SM_AMIGA_5_.D -0 1 -.names CLK_000_D_i.BLIF N_103_i.BLIF SM_AMIGA_4_.D -11 1 +inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP inst_AS_030_000_SYNC.D \ +inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_AS_000_INTreg.D \ +inst_AS_000_INTreg.C inst_AS_000_INTreg.AP inst_VPA_SYNC.D inst_VPA_SYNC.C \ +inst_VPA_SYNC.AP BG_000DFFSHreg.D BG_000DFFSHreg.C BG_000DFFSHreg.AP \ +inst_DTACK_DMA.D inst_DTACK_DMA.C inst_DTACK_DMA.AP inst_UDS_000_INTreg.D \ +inst_UDS_000_INTreg.C inst_UDS_000_INTreg.AP CLK_CNT_0_.D CLK_CNT_0_.C \ +inst_VPA_D.D inst_VPA_D.C inst_CLK_000_D.D inst_CLK_000_D.C RESETDFFreg.D \ +RESETDFFreg.C inst_CLK_000_DD.D inst_CLK_000_DD.C CLK_OUT_INTreg.D \ +CLK_OUT_INTreg.C DSACK_1_ DTACK DSACK_0_ ipl_c_0__n ipl_c_1__n ipl_c_2__n \ +gnd_n_n dsack_c_1__n DTACK_c RST_c vcc_n_n RW_c fc_c_0__n \ +state_machine_un1_clk_030_n fc_c_1__n state_machine_un6_bgack_000_n N_99_i \ +state_machine_un13_as_000_int_n un1_bg_030 N_101_i sm_amiga_ns_0_2__n N_107_i \ +N_106_i sm_amiga_ns_0_5__n N_108_i N_109_i N_110_i sm_amiga_ns_0_7__n N_91_0 \ +CLK_OUT_PRE_i N_94_0 state_machine_un8_clk_000_d_i_n \ +state_machine_un13_clk_000_d_i_n state_machine_un15_clk_000_d_0_n N_93_0 \ +N_104_i N_105_i N_103_i state_machine_un60_clk_000_d_i_n \ +state_machine_un17_clk_030_0_n un1_as_030_3_0 N_145_i clk_un4_clk_000_dd_n \ +a_c_i_0__n clk_cpu_est_11_1__n state_machine_uds_000_int_8_0_n \ +state_machine_un42_clk_030_n state_machine_lds_000_int_8_0_n N_102 \ +state_machine_as_030_000_sync_3_2_n N_98 size_c_i_1__n N_97 \ +state_machine_un34_clk_000_d_i_n N_100 N_131_i N_92 N_132_i N_112 N_122_i \ +N_127 N_125_i N_125 N_126_i N_128 N_134_i N_129 N_133_i N_130 N_135_i N_168 \ +clk_cpu_est_11_0_3__n N_171 N_130_i N_135_1 clk_cpu_est_11_0_1__n \ +state_machine_un13_clk_000_d_2_n N_128_i clk_cpu_est_11_3__n un1_bg_030_0 \ +N_135 N_97_i N_133 BG_030_c_i N_134 N_127_i N_132 N_129_i N_131 N_92_0 N_126 \ +N_100_i state_machine_un34_clk_000_d_n N_112_i UDS_000_INT_0_sqmuxa \ +UDS_000_INT_0_sqmuxa_1 clk_un4_clk_000_dd_i_n \ +state_machine_as_030_000_sync_3_n state_machine_un6_bgack_000_0_n N_145 \ +state_machine_un1_clk_030_0_n state_machine_lds_000_int_8_n \ +clk_cpu_est_11_0_1_3__n state_machine_uds_000_int_8_n \ +state_machine_un34_clk_000_d_i_1_n un1_as_030_4 \ +state_machine_as_030_000_sync_3_2_1_n un1_as_030_3 N_168_1 DSACK_INT_1_sqmuxa \ +N_168_2 state_machine_un17_clk_030_n N_168_3 state_machine_un60_clk_000_d_n \ +N_168_4 DTACK_SYNC_1_sqmuxa N_168_5 DTACK_SYNC_1_sqmuxa_1 N_168_6 \ +VPA_SYNC_1_sqmuxa N_171_1 VPA_SYNC_1_sqmuxa_1 N_171_2 N_103 un1_bg_030_0_1 \ +N_104 un1_bg_030_0_2 N_93 clk_cpu_est_11_0_1_1__n N_105 \ +clk_cpu_est_11_0_2_1__n VPA_SYNC_1_sqmuxa_1_0 state_machine_un42_clk_030_1_n \ +state_machine_un15_clk_000_d_n state_machine_un42_clk_030_2_n \ +state_machine_un13_clk_000_d_n state_machine_un42_clk_030_3_n \ +state_machine_un8_clk_000_d_n state_machine_un42_clk_030_4_n \ +state_machine_un8_clk_000_d_1_n state_machine_un42_clk_030_5_n \ +state_machine_un13_clk_000_d_1_n N_132_1 N_107 N_131_1 N_94 \ +UDS_000_INT_0_sqmuxa_1_0 N_91 UDS_000_INT_0_sqmuxa_2 N_110 \ +UDS_000_INT_0_sqmuxa_1_1 N_108 UDS_000_INT_0_sqmuxa_1_2 N_109 \ +UDS_000_INT_0_sqmuxa_1_3 N_106 DTACK_SYNC_1_sqmuxa_1_0 N_101 \ +state_machine_un8_clk_000_d_1_0_n N_99 state_machine_un8_clk_000_d_2_n \ +AS_000_INT_1_sqmuxa state_machine_un8_clk_000_d_3_n RW_i \ +state_machine_un13_clk_000_d_1_0_n N_102_i state_machine_un13_clk_000_d_2_0_n \ +AS_000_INT_i VPA_SYNC_1_sqmuxa_1_1 dsack_i_1__n VPA_SYNC_1_sqmuxa_2 AS_030_i \ +VPA_SYNC_1_sqmuxa_3 sm_amiga_i_7__n VPA_SYNC_1_sqmuxa_4 CLK_000_D_i N_107_1 \ +sm_amiga_i_2__n N_98_1 sm_amiga_i_1__n as_000_int_0_un3_n \ +state_machine_un13_clk_000_d_1_i_n as_000_int_0_un1_n VPA_D_i \ +as_000_int_0_un0_n VMA_INT_i vma_int_0_un3_n cpu_est_i_0__n vma_int_0_un1_n \ +cpu_est_i_1__n vma_int_0_un0_n cpu_est_i_3__n uds_000_int_0_un3_n \ +state_machine_un8_clk_000_d_1_i_0_n uds_000_int_0_un1_n DTACK_i \ +uds_000_int_0_un0_n sm_amiga_i_3__n dtack_sync_0_un3_n sm_amiga_i_4__n \ +dtack_sync_0_un1_n sm_amiga_i_5__n dtack_sync_0_un0_n DTACK_SYNC_1_sqmuxa_i \ +vpa_sync_0_un3_n VPA_SYNC_1_sqmuxa_i vpa_sync_0_un1_n N_98_i vpa_sync_0_un0_n \ +state_machine_un42_clk_030_i_n dsack_int_0_1__un3_n UDS_000_INT_0_sqmuxa_1_i \ +dsack_int_0_1__un1_n UDS_000_INT_0_sqmuxa_i dsack_int_0_1__un0_n \ +AS_030_000_SYNC_i as_030_000_sync_0_un3_n DS_030_i as_030_000_sync_0_un1_n \ +cpu_est_i_2__n as_030_000_sync_0_un0_n state_machine_un13_clk_000_d_2_i_n \ +fpu_cs_int_0_un3_n CLK_000_DD_i fpu_cs_int_0_un1_n sm_amiga_i_6__n \ +fpu_cs_int_0_un0_n CLK_030_i lds_000_int_0_un3_n a_i_30__n lds_000_int_0_un1_n \ +a_i_31__n lds_000_int_0_un0_n a_i_28__n cpu_est_0_3__un3_n a_i_29__n \ +cpu_est_0_3__un1_n a_i_26__n cpu_est_0_3__un0_n a_i_27__n cpu_est_0_2__un3_n \ +a_i_24__n cpu_est_0_2__un1_n a_i_25__n cpu_est_0_2__un0_n a_i_19__n \ +bg_000_0_un3_n a_i_16__n bg_000_0_un1_n a_i_18__n bg_000_0_un0_n \ +bgack_030_int_0_un3_n RST_i bgack_030_int_0_un1_n bgack_030_int_0_un0_n \ +FPU_CS_INT_i cpu_est_0_1__un3_n CPU_SPACE_i cpu_est_0_1__un1_n BGACK_030_INT_i \ +cpu_est_0_1__un0_n AS_030_c ipl_030_0_0__un3_n ipl_030_0_0__un1_n \ +ipl_030_0_0__un0_n DS_030_c ipl_030_0_1__un3_n ipl_030_0_1__un1_n \ +ipl_030_0_1__un0_n ipl_030_0_2__un3_n size_c_0__n ipl_030_0_2__un1_n \ +ipl_030_0_2__un0_n size_c_1__n a_15__n a_c_0__n a_14__n a_13__n a_12__n \ +a_11__n a_10__n a_9__n a_8__n a_7__n a_6__n a_c_16__n a_5__n a_c_17__n a_4__n \ +a_c_18__n a_3__n a_c_19__n a_2__n a_c_20__n a_1__n a_c_21__n a_c_22__n \ +a_c_23__n a_c_24__n a_c_25__n a_c_26__n a_c_27__n a_c_28__n a_c_29__n \ +a_c_30__n a_c_31__n CPU_SPACE_c BG_030_c BGACK_000_c CLK_030_c CLK_OSZI_c \ +DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE \ +AVEC_EXP.OE CIIN.OE cpu_est_0_0_ CLK_OUT_PRE_0 .names N_104_i.BLIF N_105_i.BLIF SM_AMIGA_3_.D 11 1 .names sm_amiga_ns_0_5__n.BLIF SM_AMIGA_2_.D @@ -319,33 +309,31 @@ BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE cpu_est_0_0_ CLK_OUT_PRE_0 .names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF IPL_030DFFSH_2_reg.D 1- 1 -1 1 -.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D -1- 1 --1 1 -.names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D -1- 1 --1 1 -.names vpa_sync_0_un1_n.BLIF vpa_sync_0_un0_n.BLIF inst_VPA_SYNC.D -1- 1 --1 1 -.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF \ -inst_AS_030_000_SYNC.D +.names inst_CLK_000_D.BLIF N_99_i.BLIF SM_AMIGA_7_.D +11 1 +.names N_100_i.BLIF N_112_i.BLIF SM_AMIGA_6_.D +11 1 +.names sm_amiga_ns_0_2__n.BLIF SM_AMIGA_5_.D +0 1 +.names CLK_000_D_i.BLIF N_103_i.BLIF SM_AMIGA_4_.D +11 1 +.names dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF DSACK_INT_1_.D 1- 1 -1 1 .names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D 1- 1 -1 1 -.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF BG_000DFFSHreg.D -1- 1 --1 1 -.names dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF DSACK_INT_1_.D -1- 1 --1 1 .names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF \ inst_BGACK_030_INTreg.D 1- 1 -1 1 -.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INTreg.D +.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D +1- 1 +-1 1 +.names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D +1- 1 +-1 1 +.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_reg.D 1- 1 -1 1 .names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF inst_LDS_000_INTreg.D @@ -357,42 +345,52 @@ inst_BGACK_030_INTreg.D .names fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF inst_FPU_CS_INTreg.D 1- 1 -1 1 +.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF \ +inst_AS_030_000_SYNC.D +1- 1 +-1 1 .names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF inst_AS_000_INTreg.D 1- 1 -1 1 +.names vpa_sync_0_un1_n.BLIF vpa_sync_0_un0_n.BLIF inst_VPA_SYNC.D +1- 1 +-1 1 +.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF BG_000DFFSHreg.D +1- 1 +-1 1 .names state_machine_un13_as_000_int_n.BLIF inst_DTACK_DMA.D 0 1 -.names CLK_000_D_i.BLIF CLK_000_c.BLIF inst_RISING_CLK_AMIGA.D -11 1 +.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INTreg.D +1- 1 +-1 1 .names CLK_CNT_0_.BLIF CLK_CNT_0_.D 0 1 .names gnd_n_n .names vcc_n_n 1 -.names state_machine_un57_clk_000_d_0_n.BLIF state_machine_un57_clk_000_d_n +.names state_machine_un1_clk_030_0_n.BLIF state_machine_un1_clk_030_n +0 1 +.names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n +0 1 +.names N_99.BLIF N_99_i 0 1 .names AS_000_INT_i.BLIF dsack_i_1__n.BLIF state_machine_un13_as_000_int_n 11 1 -.names N_145.BLIF N_145_i -0 1 -.names a_c_0__n.BLIF a_c_i_0__n -0 1 -.names a_c_i_0__n.BLIF N_145_i.BLIF state_machine_uds_000_int_8_0_n -11 1 -.names N_145_i.BLIF state_machine_un31_clk_000_d_n.BLIF \ -state_machine_lds_000_int_8_0_n -11 1 -.names N_99.BLIF N_99_i -0 1 -.names N_112.BLIF N_112_i -0 1 -.names N_100.BLIF N_100_i +.names un1_bg_030_0.BLIF un1_bg_030 0 1 .names N_101.BLIF N_101_i 0 1 .names N_101_i.BLIF N_102_i.BLIF sm_amiga_ns_0_2__n 11 1 -.names N_103.BLIF N_103_i +.names N_107.BLIF N_107_i +0 1 +.names N_106.BLIF N_106_i +0 1 +.names N_106_i.BLIF N_107_i.BLIF sm_amiga_ns_0_5__n +11 1 +.names N_108.BLIF N_108_i +0 1 +.names N_109.BLIF N_109_i 0 1 .names N_110.BLIF N_110_i 0 1 @@ -400,520 +398,521 @@ state_machine_lds_000_int_8_0_n 11 1 .names inst_AS_000_INTreg.BLIF SM_AMIGA_0_.BLIF N_91_0 11 1 -.names CLK_000_D_i.BLIF SM_AMIGA_7_.BLIF N_92_0 -11 1 -.names N_131.BLIF N_131_i +.names inst_CLK_OUT_PRE.BLIF CLK_OUT_PRE_i 0 1 -.names N_132.BLIF N_132_i +.names CLK_OUT_PRE_i.BLIF sm_amiga_i_2__n.BLIF N_94_0 +11 1 +.names state_machine_un8_clk_000_d_n.BLIF state_machine_un8_clk_000_d_i_n 0 1 -.names N_131_i.BLIF N_132_i.BLIF N_122_i -11 1 -.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_124_i -11 1 -.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF N_125_i -11 1 -.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_126_i -11 1 -.names N_129.BLIF N_129_i +.names state_machine_un13_clk_000_d_n.BLIF state_machine_un13_clk_000_d_i_n 0 1 -.names N_98_1.BLIF SM_AMIGA_1_.BLIF N_98 +.names state_machine_un8_clk_000_d_i_n.BLIF \ +state_machine_un13_clk_000_d_i_n.BLIF state_machine_un15_clk_000_d_0_n 11 1 -.names N_127.BLIF N_127_i +.names SM_AMIGA_3_.BLIF state_machine_un60_clk_000_d_i_n.BLIF N_93_0 +11 1 +.names N_104.BLIF N_104_i 0 1 -.names sm_amiga_i_6__n.BLIF sm_amiga_i_7__n.BLIF N_97 -11 1 -.names N_128.BLIF N_128_i +.names N_105.BLIF N_105_i 0 1 -.names CLK_000_D_i.BLIF N_93.BLIF N_104 -11 1 -.names N_130.BLIF N_130_i +.names N_103.BLIF N_103_i 0 1 -.names N_93_0.BLIF N_93 -0 1 -.names clk_cpu_est_11_0_1_1__n.BLIF clk_cpu_est_11_0_2_1__n.BLIF \ -clk_cpu_est_11_0_1__n -11 1 -.names sm_amiga_i_3__n.BLIF sm_amiga_i_4__n.BLIF N_105 -11 1 -.names N_134.BLIF N_134_i -0 1 -.names CLK_000_D_i.BLIF SM_AMIGA_2_.BLIF N_106 -11 1 -.names N_133.BLIF N_133_i -0 1 -.names CLK_000_D_i.BLIF N_94.BLIF N_108 -11 1 -.names N_135.BLIF N_135_i -0 1 -.names N_94_0.BLIF N_94 -0 1 -.names clk_cpu_est_11_0_1_3__n.BLIF N_134_i.BLIF clk_cpu_est_11_0_3__n -11 1 -.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_109 -11 1 -.names size_c_1__n.BLIF size_c_i_1__n -0 1 -.names N_107_1.BLIF state_machine_un57_clk_000_d_n.BLIF N_107 -11 1 -.names state_machine_un31_clk_000_d_i_1_n.BLIF size_c_i_1__n.BLIF \ -state_machine_un31_clk_000_d_i_n -11 1 -.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_135_1 -11 1 -.names state_machine_as_030_000_sync_3_0_1_n.BLIF \ -state_machine_un42_clk_030_i_n.BLIF state_machine_as_030_000_sync_3_0_n -11 1 -.names inst_CLK_000_D.BLIF SM_AMIGA_3_.BLIF VPA_SYNC_1_sqmuxa_1_0 -11 1 -.names AS_030_i.BLIF state_machine_un42_clk_030_n.BLIF un1_as_030_2_0 -11 1 -.names N_167_5.BLIF N_167_6.BLIF N_167 +.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF \ +state_machine_un60_clk_000_d_i_n 11 1 .names AS_030_i.BLIF CLK_030_i.BLIF state_machine_un17_clk_030_0_n 11 1 -.names N_170_1.BLIF N_170_2.BLIF N_170 +.names AS_030_i.BLIF state_machine_un42_clk_030_n.BLIF un1_as_030_3_0 11 1 -.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF \ -state_machine_un57_clk_000_d_0_n +.names N_145.BLIF N_145_i +0 1 +.names inst_CLK_000_D.BLIF CLK_000_DD_i.BLIF clk_un4_clk_000_dd_n +11 1 +.names a_c_0__n.BLIF a_c_i_0__n +0 1 +.names clk_cpu_est_11_0_1__n.BLIF clk_cpu_est_11_1__n +0 1 +.names a_c_i_0__n.BLIF N_145_i.BLIF state_machine_uds_000_int_8_0_n 11 1 .names state_machine_un42_clk_030_4_n.BLIF state_machine_un42_clk_030_5_n.BLIF \ state_machine_un42_clk_030_n 11 1 -.names inst_RISING_CLK_AMIGA.BLIF RISING_CLK_AMIGA_i +.names N_145_i.BLIF state_machine_un34_clk_000_d_n.BLIF \ +state_machine_lds_000_int_8_0_n +11 1 +.names N_112.BLIF SM_AMIGA_6_.BLIF N_102 +11 1 +.names state_machine_as_030_000_sync_3_2_1_n.BLIF \ +state_machine_un42_clk_030_i_n.BLIF state_machine_as_030_000_sync_3_2_n +11 1 +.names N_98_1.BLIF SM_AMIGA_1_.BLIF N_98 +11 1 +.names size_c_1__n.BLIF size_c_i_1__n 0 1 -.names DTACK_SYNC_1_sqmuxa_1_0.BLIF VPA_SYNC_1_sqmuxa_1_0.BLIF \ -DTACK_SYNC_1_sqmuxa +.names sm_amiga_i_6__n.BLIF sm_amiga_i_7__n.BLIF N_97 11 1 -.names BGACK_000_c.BLIF RISING_CLK_AMIGA_i.BLIF \ -state_machine_un4_bgack_000_0_n +.names state_machine_un34_clk_000_d_i_1_n.BLIF size_c_i_1__n.BLIF \ +state_machine_un34_clk_000_d_i_n 11 1 -.names VPA_SYNC_1_sqmuxa_4.BLIF VPA_SYNC_1_sqmuxa_3.BLIF VPA_SYNC_1_sqmuxa +.names N_92.BLIF sm_amiga_i_6__n.BLIF N_100 11 1 -.names BG_030_c.BLIF BG_030_c_i +.names N_131.BLIF N_131_i 0 1 -.names un1_bg_030_0.BLIF un1_bg_030 +.names N_92_0.BLIF N_92 0 1 -.names BG_030_c_i.BLIF CLK_030_c.BLIF state_machine_un1_clk_030_0_n +.names N_132.BLIF N_132_i +0 1 +.names AS_030_000_SYNC_i.BLIF clk_un4_clk_000_dd_n.BLIF N_112 11 1 -.names AS_030_i.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF DTACK_SYNC_1_sqmuxa_1 +.names N_131_i.BLIF N_132_i.BLIF N_122_i +11 1 +.names N_125.BLIF cpu_est_i_0__n.BLIF N_127 +11 1 +.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF N_125_i +11 1 +.names N_125_i.BLIF N_125 +0 1 +.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_126_i +11 1 +.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_128 +11 1 +.names N_134.BLIF N_134_i +0 1 +.names N_125_i.BLIF cpu_est_0_.BLIF N_129 +11 1 +.names N_133.BLIF N_133_i +0 1 +.names cpu_est_3_reg.BLIF state_machine_un13_clk_000_d_2_n.BLIF N_130 +11 1 +.names N_135.BLIF N_135_i +0 1 +.names N_168_5.BLIF N_168_6.BLIF N_168 +11 1 +.names clk_cpu_est_11_0_1_3__n.BLIF N_134_i.BLIF clk_cpu_est_11_0_3__n +11 1 +.names N_171_1.BLIF N_171_2.BLIF N_171 +11 1 +.names N_130.BLIF N_130_i +0 1 +.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_135_1 +11 1 +.names clk_cpu_est_11_0_1_1__n.BLIF clk_cpu_est_11_0_2_1__n.BLIF \ +clk_cpu_est_11_0_1__n +11 1 +.names cpu_est_1_.BLIF cpu_est_2_.BLIF state_machine_un13_clk_000_d_2_n +11 1 +.names N_128.BLIF N_128_i +0 1 +.names clk_cpu_est_11_0_3__n.BLIF clk_cpu_est_11_3__n +0 1 +.names un1_bg_030_0_1.BLIF un1_bg_030_0_2.BLIF un1_bg_030_0 +11 1 +.names N_135_1.BLIF cpu_est_i_2__n.BLIF N_135 11 1 .names N_97.BLIF N_97_i 0 1 -.names AS_030_i.BLIF N_98_i.BLIF DSACK_INT_1_sqmuxa +.names N_126.BLIF cpu_est_3_reg.BLIF N_133 11 1 -.names un1_bg_030_0_1.BLIF un1_bg_030_0_2.BLIF un1_bg_030_0 +.names BG_030_c.BLIF BG_030_c_i +0 1 +.names N_126_i.BLIF cpu_est_i_2__n.BLIF N_134 11 1 -.names state_machine_un1_clk_030_0_n.BLIF state_machine_un1_clk_030_n +.names N_127.BLIF N_127_i 0 1 -.names inst_CLK_OUT_PRE.BLIF CLK_OUT_PRE_i -0 1 -.names state_machine_un4_bgack_000_0_n.BLIF state_machine_un4_bgack_000_n -0 1 -.names CLK_OUT_PRE_i.BLIF sm_amiga_i_2__n.BLIF N_94_0 +.names N_132_1.BLIF cpu_est_i_2__n.BLIF N_132 11 1 -.names un1_as_030_2_0.BLIF un1_as_030_2 +.names N_129.BLIF N_129_i 0 1 -.names SM_AMIGA_3_.BLIF state_machine_un57_clk_000_d_0_n.BLIF N_93_0 +.names N_131_1.BLIF state_machine_un13_clk_000_d_2_i_n.BLIF N_131 11 1 -.names state_machine_un17_clk_030_0_n.BLIF state_machine_un17_clk_030_n -0 1 -.names N_108.BLIF N_108_i -0 1 -.names N_112.BLIF SM_AMIGA_6_.BLIF N_102 +.names CLK_000_D_i.BLIF SM_AMIGA_7_.BLIF N_92_0 11 1 -.names N_109.BLIF N_109_i +.names N_126_i.BLIF N_126 0 1 -.names AS_030_i.BLIF N_102_i.BLIF AS_000_INT_1_sqmuxa -11 1 -.names AS_030_i.BLIF VPA_SYNC_1_sqmuxa_i.BLIF VPA_SYNC_1_sqmuxa_1 -11 1 -.names N_106.BLIF N_106_i +.names N_100.BLIF N_100_i 0 1 -.names state_machine_as_030_000_sync_3_0_n.BLIF \ -state_machine_as_030_000_sync_3_n +.names state_machine_un34_clk_000_d_i_n.BLIF state_machine_un34_clk_000_d_n 0 1 -.names N_107.BLIF N_107_i -0 1 -.names inst_CLK_000_D.BLIF CLK_000_DD_i.BLIF clk_un3_clk_000_dd_n -11 1 -.names N_106_i.BLIF N_107_i.BLIF sm_amiga_ns_0_5__n -11 1 -.names state_machine_un31_clk_000_d_i_n.BLIF state_machine_un31_clk_000_d_n -0 1 -.names N_104.BLIF N_104_i +.names N_112.BLIF N_112_i 0 1 .names UDS_000_INT_0_sqmuxa_1_0.BLIF UDS_000_INT_0_sqmuxa_2.BLIF \ UDS_000_INT_0_sqmuxa 11 1 -.names N_105.BLIF N_105_i +.names UDS_000_INT_0_sqmuxa_1_3.BLIF clk_un4_clk_000_dd_n.BLIF \ +UDS_000_INT_0_sqmuxa_1 +11 1 +.names clk_un4_clk_000_dd_n.BLIF clk_un4_clk_000_dd_i_n 0 1 +.names state_machine_as_030_000_sync_3_2_n.BLIF \ +state_machine_as_030_000_sync_3_n +0 1 +.names BGACK_000_c.BLIF clk_un4_clk_000_dd_i_n.BLIF \ +state_machine_un6_bgack_000_0_n +11 1 +.names UDS_000_INT_0_sqmuxa_1_i.BLIF UDS_000_INT_0_sqmuxa_i.BLIF N_145 +11 1 +.names BG_030_c_i.BLIF CLK_030_c.BLIF state_machine_un1_clk_030_0_n +11 1 +.names state_machine_lds_000_int_8_0_n.BLIF state_machine_lds_000_int_8_n +0 1 +.names N_135_i.BLIF N_133_i.BLIF clk_cpu_est_11_0_1_3__n +11 1 +.names state_machine_uds_000_int_8_0_n.BLIF state_machine_uds_000_int_8_n +0 1 +.names size_c_0__n.BLIF a_c_i_0__n.BLIF state_machine_un34_clk_000_d_i_1_n +11 1 +.names AS_030_i.BLIF N_145.BLIF un1_as_030_4 +11 1 +.names AS_030_i.BLIF CPU_SPACE_i.BLIF state_machine_as_030_000_sync_3_2_1_n +11 1 +.names un1_as_030_3_0.BLIF un1_as_030_3 +0 1 +.names a_i_24__n.BLIF a_i_25__n.BLIF N_168_1 +11 1 +.names AS_030_i.BLIF N_98_i.BLIF DSACK_INT_1_sqmuxa +11 1 +.names a_i_26__n.BLIF a_i_27__n.BLIF N_168_2 +11 1 +.names state_machine_un17_clk_030_0_n.BLIF state_machine_un17_clk_030_n +0 1 +.names a_i_28__n.BLIF a_i_29__n.BLIF N_168_3 +11 1 +.names state_machine_un60_clk_000_d_i_n.BLIF state_machine_un60_clk_000_d_n +0 1 +.names a_i_30__n.BLIF a_i_31__n.BLIF N_168_4 +11 1 +.names DTACK_SYNC_1_sqmuxa_1_0.BLIF VPA_SYNC_1_sqmuxa_1_0.BLIF \ +DTACK_SYNC_1_sqmuxa +11 1 +.names N_168_1.BLIF N_168_2.BLIF N_168_5 +11 1 +.names AS_030_i.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF DTACK_SYNC_1_sqmuxa_1 +11 1 +.names N_168_3.BLIF N_168_4.BLIF N_168_6 +11 1 +.names VPA_SYNC_1_sqmuxa_4.BLIF VPA_SYNC_1_sqmuxa_3.BLIF VPA_SYNC_1_sqmuxa +11 1 +.names a_c_20__n.BLIF a_c_21__n.BLIF N_171_1 +11 1 +.names AS_030_i.BLIF VPA_SYNC_1_sqmuxa_i.BLIF VPA_SYNC_1_sqmuxa_1 +11 1 +.names a_c_22__n.BLIF a_c_23__n.BLIF N_171_2 +11 1 +.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_103 +11 1 +.names AS_030_c.BLIF BG_030_c_i.BLIF un1_bg_030_0_1 +11 1 +.names CLK_000_D_i.BLIF N_93.BLIF N_104 +11 1 +.names CPU_SPACE_i.BLIF N_97_i.BLIF un1_bg_030_0_2 +11 1 +.names N_93_0.BLIF N_93 +0 1 +.names N_127_i.BLIF N_128_i.BLIF clk_cpu_est_11_0_1_1__n +11 1 +.names sm_amiga_i_3__n.BLIF sm_amiga_i_4__n.BLIF N_105 +11 1 +.names N_129_i.BLIF N_130_i.BLIF clk_cpu_est_11_0_2_1__n +11 1 +.names inst_CLK_000_D.BLIF SM_AMIGA_3_.BLIF VPA_SYNC_1_sqmuxa_1_0 +11 1 +.names a_c_17__n.BLIF a_i_16__n.BLIF state_machine_un42_clk_030_1_n +11 1 +.names state_machine_un15_clk_000_d_0_n.BLIF state_machine_un15_clk_000_d_n +0 1 +.names a_i_18__n.BLIF a_i_19__n.BLIF state_machine_un42_clk_030_2_n +11 1 .names state_machine_un13_clk_000_d_1_0_n.BLIF \ -state_machine_un13_clk_000_d_4_n.BLIF state_machine_un13_clk_000_d_n +state_machine_un13_clk_000_d_2_0_n.BLIF state_machine_un13_clk_000_d_n 11 1 -.names state_machine_un13_clk_000_d_4_1_n.BLIF cpu_est_d_2_.BLIF \ -state_machine_un13_clk_000_d_4_n +.names fc_c_1__n.BLIF BGACK_000_c.BLIF state_machine_un42_clk_030_3_n 11 1 -.names BG_030_c_i.BLIF CPU_SPACE_i.BLIF un1_bg_030_0_1 +.names state_machine_un8_clk_000_d_3_n.BLIF cpu_est_i_3__n.BLIF \ +state_machine_un8_clk_000_d_n +11 1 +.names state_machine_un42_clk_030_1_n.BLIF state_machine_un42_clk_030_2_n.BLIF \ +state_machine_un42_clk_030_4_n +11 1 +.names CLK_000_D_i.BLIF cpu_est_0_.BLIF state_machine_un8_clk_000_d_1_n +11 1 +.names state_machine_un42_clk_030_3_n.BLIF fc_c_0__n.BLIF \ +state_machine_un42_clk_030_5_n 11 1 .names inst_AS_000_INTreg.BLIF inst_CLK_000_D.BLIF \ state_machine_un13_clk_000_d_1_n 11 1 -.names AS_030_c.BLIF N_97_i.BLIF un1_bg_030_0_2 +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_132_1 11 1 -.names state_machine_un8_clk_000_d_4_n.BLIF \ -state_machine_un8_clk_000_d_3_n.BLIF state_machine_un8_clk_000_d_n +.names N_107_1.BLIF state_machine_un60_clk_000_d_n.BLIF N_107 11 1 -.names size_c_0__n.BLIF a_c_i_0__n.BLIF state_machine_un31_clk_000_d_i_1_n +.names cpu_est_0_.BLIF cpu_est_i_3__n.BLIF N_131_1 11 1 -.names UDS_000_INT_0_sqmuxa_1_3.BLIF clk_un3_clk_000_dd_n.BLIF \ -UDS_000_INT_0_sqmuxa_1 -11 1 -.names N_135_i.BLIF N_133_i.BLIF clk_cpu_est_11_0_1_3__n -11 1 -.names N_132_1.BLIF cpu_est_i_2__n.BLIF N_132 -11 1 -.names N_130_i.BLIF N_128_i.BLIF clk_cpu_est_11_0_1_1__n -11 1 -.names N_131_1.BLIF cpu_est_i_3__n.BLIF N_131 -11 1 -.names N_127_i.BLIF N_129_i.BLIF clk_cpu_est_11_0_2_1__n -11 1 -.names N_124_i.BLIF N_124 -0 1 -.names a_i_24__n.BLIF a_i_25__n.BLIF N_167_1 -11 1 -.names clk_cpu_est_11_0_3__n.BLIF clk_cpu_est_11_3__n -0 1 -.names a_i_26__n.BLIF a_i_27__n.BLIF N_167_2 -11 1 -.names N_135_1.BLIF cpu_est_i_2__n.BLIF N_135 -11 1 -.names a_i_28__n.BLIF a_i_29__n.BLIF N_167_3 -11 1 -.names N_126.BLIF cpu_est_3_reg.BLIF N_133 -11 1 -.names a_i_30__n.BLIF a_i_31__n.BLIF N_167_4 -11 1 -.names N_126_i.BLIF cpu_est_i_2__n.BLIF N_134 -11 1 -.names N_167_1.BLIF N_167_2.BLIF N_167_5 -11 1 -.names clk_cpu_est_11_0_1__n.BLIF clk_cpu_est_11_1__n -0 1 -.names N_167_3.BLIF N_167_4.BLIF N_167_6 -11 1 -.names N_124_i.BLIF cpu_est_3_reg.BLIF N_130 -11 1 -.names a_c_20__n.BLIF a_c_21__n.BLIF N_170_1 -11 1 -.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_128 -11 1 -.names a_c_22__n.BLIF a_c_23__n.BLIF N_170_2 -11 1 -.names UDS_000_INT_0_sqmuxa_1_i.BLIF UDS_000_INT_0_sqmuxa_i.BLIF N_145 -11 1 -.names CLK_000_D_i.BLIF SM_AMIGA_3_.BLIF N_107_1 -11 1 -.names N_125.BLIF cpu_est_i_0__n.BLIF N_127 -11 1 -.names a_c_17__n.BLIF a_i_16__n.BLIF state_machine_un42_clk_030_1_n -11 1 -.names N_125_i.BLIF cpu_est_0_.BLIF N_129 -11 1 -.names a_i_18__n.BLIF a_i_19__n.BLIF state_machine_un42_clk_030_2_n -11 1 -.names N_126_i.BLIF N_126 -0 1 -.names fc_c_1__n.BLIF BGACK_000_c.BLIF state_machine_un42_clk_030_3_n -11 1 -.names N_125_i.BLIF N_125 -0 1 -.names state_machine_un42_clk_030_1_n.BLIF state_machine_un42_clk_030_2_n.BLIF \ -state_machine_un42_clk_030_4_n -11 1 -.names N_92_0.BLIF N_92 -0 1 -.names state_machine_un42_clk_030_3_n.BLIF fc_c_0__n.BLIF \ -state_machine_un42_clk_030_5_n -11 1 -.names N_91_0.BLIF N_91 -0 1 -.names DTACK_i.BLIF inst_VPA_D.BLIF DTACK_SYNC_1_sqmuxa_1_0 -11 1 -.names SM_AMIGA_0_.BLIF state_machine_un13_clk_000_d_1_i_n.BLIF N_110 -11 1 -.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF VPA_SYNC_1_sqmuxa_1_1 -11 1 -.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_103 -11 1 -.names N_135_1.BLIF VMA_INT_i.BLIF VPA_SYNC_1_sqmuxa_2 -11 1 -.names inst_CLK_000_D.BLIF SM_AMIGA_5_.BLIF N_101 -11 1 -.names VPA_D_i.BLIF VPA_SYNC_1_sqmuxa_1_0.BLIF VPA_SYNC_1_sqmuxa_3 -11 1 -.names N_92.BLIF sm_amiga_i_6__n.BLIF N_100 -11 1 -.names VPA_SYNC_1_sqmuxa_1_1.BLIF VPA_SYNC_1_sqmuxa_2.BLIF VPA_SYNC_1_sqmuxa_4 -11 1 -.names AS_030_000_SYNC_i.BLIF clk_un3_clk_000_dd_n.BLIF N_112 -11 1 -.names CLK_000_D_i.BLIF inst_CLK_OUT_PRE.BLIF N_98_1 -11 1 -.names N_91.BLIF sm_amiga_i_7__n.BLIF N_99 -11 1 -.names AS_030_i.BLIF CPU_SPACE_i.BLIF state_machine_as_030_000_sync_3_0_1_n -11 1 -.names state_machine_lds_000_int_8_0_n.BLIF state_machine_lds_000_int_8_n +.names N_94_0.BLIF N_94 0 1 .names inst_CLK_000_D.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_0 11 1 -.names state_machine_uds_000_int_8_0_n.BLIF state_machine_uds_000_int_8_n +.names N_91_0.BLIF N_91 0 1 .names RW_i.BLIF SM_AMIGA_4_.BLIF UDS_000_INT_0_sqmuxa_2 11 1 -.names AS_030_i.BLIF N_145.BLIF un2_clk_030_1 +.names SM_AMIGA_0_.BLIF state_machine_un13_clk_000_d_1_i_n.BLIF N_110 11 1 -.names cpu_est_d_i_0__n.BLIF cpu_est_d_i_3__n.BLIF \ -state_machine_un13_clk_000_d_1_0_n -11 1 -.names state_machine_un8_clk_000_d_i_n.BLIF \ -state_machine_un13_clk_000_d_i_n.BLIF VMA_INT_1_sqmuxa -11 1 -.names state_machine_un13_clk_000_d_1_n.BLIF cpu_est_d_1_.BLIF \ -state_machine_un13_clk_000_d_4_1_n -11 1 -.names RW_c.BLIF RW_i -0 1 -.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF state_machine_un8_clk_000_d_1_n -11 1 -.names cpu_est_d_3_.BLIF cpu_est_d_i_3__n -0 1 -.names CLK_000_D_i.BLIF VPA_D_i.BLIF state_machine_un8_clk_000_d_2_n -11 1 -.names cpu_est_d_0_.BLIF cpu_est_d_i_0__n -0 1 -.names cpu_est_0_.BLIF cpu_est_2_.BLIF state_machine_un8_clk_000_d_3_n -11 1 -.names inst_CLK_000_D.BLIF CLK_000_D_i -0 1 -.names state_machine_un8_clk_000_d_1_n.BLIF \ -state_machine_un8_clk_000_d_2_n.BLIF state_machine_un8_clk_000_d_4_n -11 1 -.names inst_AS_000_INTreg.BLIF AS_000_INT_i -0 1 .names AS_030_000_SYNC_i.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_1 11 1 -.names dsack_c_1__n.BLIF dsack_i_1__n -0 1 +.names CLK_000_D_i.BLIF N_94.BLIF N_108 +11 1 .names RW_c.BLIF SM_AMIGA_6_.BLIF UDS_000_INT_0_sqmuxa_1_2 11 1 -.names state_machine_un13_clk_000_d_n.BLIF state_machine_un13_clk_000_d_i_n -0 1 +.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_109 +11 1 .names UDS_000_INT_0_sqmuxa_1_1.BLIF UDS_000_INT_0_sqmuxa_1_2.BLIF \ UDS_000_INT_0_sqmuxa_1_3 11 1 -.names state_machine_un8_clk_000_d_n.BLIF state_machine_un8_clk_000_d_i_n +.names CLK_000_D_i.BLIF SM_AMIGA_2_.BLIF N_106 +11 1 +.names DTACK_i.BLIF inst_VPA_D.BLIF DTACK_SYNC_1_sqmuxa_1_0 +11 1 +.names inst_CLK_000_D.BLIF SM_AMIGA_5_.BLIF N_101 +11 1 +.names state_machine_un8_clk_000_d_1_n.BLIF VPA_D_i.BLIF \ +state_machine_un8_clk_000_d_1_0_n +11 1 +.names N_91.BLIF sm_amiga_i_7__n.BLIF N_99 +11 1 +.names cpu_est_2_.BLIF cpu_est_i_1__n.BLIF state_machine_un8_clk_000_d_2_n +11 1 +.names AS_030_i.BLIF N_102_i.BLIF AS_000_INT_1_sqmuxa +11 1 +.names state_machine_un8_clk_000_d_1_0_n.BLIF \ +state_machine_un8_clk_000_d_2_n.BLIF state_machine_un8_clk_000_d_3_n +11 1 +.names RW_c.BLIF RW_i 0 1 -.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_132_1 +.names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF \ +state_machine_un13_clk_000_d_1_0_n +11 1 +.names N_102.BLIF N_102_i +0 1 +.names state_machine_un13_clk_000_d_1_n.BLIF \ +state_machine_un13_clk_000_d_2_n.BLIF state_machine_un13_clk_000_d_2_0_n +11 1 +.names inst_AS_000_INTreg.BLIF AS_000_INT_i +0 1 +.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF VPA_SYNC_1_sqmuxa_1_1 +11 1 +.names dsack_c_1__n.BLIF dsack_i_1__n +0 1 +.names N_135_1.BLIF VMA_INT_i.BLIF VPA_SYNC_1_sqmuxa_2 11 1 .names AS_030_c.BLIF AS_030_i 0 1 -.names N_124.BLIF cpu_est_0_.BLIF N_131_1 +.names VPA_D_i.BLIF VPA_SYNC_1_sqmuxa_1_0.BLIF VPA_SYNC_1_sqmuxa_3 11 1 -.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n -0 1 -.names VMA_INT_1_sqmuxa.BLIF vma_int_0_un3_n -0 1 .names SM_AMIGA_7_.BLIF sm_amiga_i_7__n 0 1 -.names inst_VMA_INTreg.BLIF VMA_INT_1_sqmuxa.BLIF vma_int_0_un1_n +.names VPA_SYNC_1_sqmuxa_1_1.BLIF VPA_SYNC_1_sqmuxa_2.BLIF VPA_SYNC_1_sqmuxa_4 11 1 -.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +.names inst_CLK_000_D.BLIF CLK_000_D_i 0 1 -.names state_machine_un13_clk_000_d_4_n.BLIF vma_int_0_un3_n.BLIF \ -vma_int_0_un0_n +.names CLK_000_D_i.BLIF SM_AMIGA_3_.BLIF N_107_1 11 1 -.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n +.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n 0 1 -.names un2_clk_030_1.BLIF lds_000_int_0_un3_n +.names CLK_000_D_i.BLIF inst_CLK_OUT_PRE.BLIF N_98_1 +11 1 +.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n +0 1 +.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n 0 1 .names state_machine_un13_clk_000_d_1_n.BLIF \ state_machine_un13_clk_000_d_1_i_n 0 1 -.names inst_LDS_000_INTreg.BLIF un2_clk_030_1.BLIF lds_000_int_0_un1_n -11 1 -.names inst_CLK_000_DD.BLIF CLK_000_DD_i -0 1 -.names state_machine_lds_000_int_8_n.BLIF lds_000_int_0_un3_n.BLIF \ -lds_000_int_0_un0_n -11 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i -0 1 -.names un2_clk_030_1.BLIF uds_000_int_0_un3_n -0 1 -.names cpu_est_0_.BLIF cpu_est_i_0__n -0 1 -.names inst_UDS_000_INTreg.BLIF un2_clk_030_1.BLIF uds_000_int_0_un1_n -11 1 -.names cpu_est_2_.BLIF cpu_est_i_2__n -0 1 -.names state_machine_uds_000_int_8_n.BLIF uds_000_int_0_un3_n.BLIF \ -uds_000_int_0_un0_n -11 1 -.names cpu_est_3_reg.BLIF cpu_est_i_3__n -0 1 -.names clk_un3_clk_000_dd_n.BLIF cpu_est_0_3__un3_n -0 1 -.names cpu_est_1_.BLIF cpu_est_i_1__n -0 1 -.names clk_cpu_est_11_3__n.BLIF clk_un3_clk_000_dd_n.BLIF cpu_est_0_3__un1_n -11 1 -.names UDS_000_INT_0_sqmuxa_1.BLIF UDS_000_INT_0_sqmuxa_1_i -0 1 -.names cpu_est_3_reg.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n -11 1 -.names UDS_000_INT_0_sqmuxa.BLIF UDS_000_INT_0_sqmuxa_i -0 1 -.names clk_un3_clk_000_dd_n.BLIF cpu_est_0_2__un3_n -0 1 -.names DS_030_c.BLIF DS_030_i -0 1 -.names N_122_i.BLIF clk_un3_clk_000_dd_n.BLIF cpu_est_0_2__un1_n -11 1 -.names inst_VPA_D.BLIF VPA_D_i -0 1 -.names cpu_est_2_.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n -11 1 -.names state_machine_un42_clk_030_n.BLIF state_machine_un42_clk_030_i_n -0 1 -.names clk_un3_clk_000_dd_n.BLIF cpu_est_0_1__un3_n -0 1 -.names VPA_SYNC_1_sqmuxa.BLIF VPA_SYNC_1_sqmuxa_i -0 1 -.names clk_cpu_est_11_1__n.BLIF clk_un3_clk_000_dd_n.BLIF cpu_est_0_1__un1_n -11 1 -.names N_102.BLIF N_102_i -0 1 -.names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n -11 1 -.names DTACK_SYNC_1_sqmuxa.BLIF DTACK_SYNC_1_sqmuxa_i -0 1 -.names state_machine_un17_clk_030_n.BLIF fpu_cs_int_0_un3_n -0 1 -.names N_98.BLIF N_98_i -0 1 -.names un1_as_030_2.BLIF state_machine_un17_clk_030_n.BLIF fpu_cs_int_0_un1_n -11 1 -.names a_c_18__n.BLIF a_i_18__n -0 1 -.names inst_FPU_CS_INTreg.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un0_n -11 1 -.names a_c_16__n.BLIF a_i_16__n -0 1 -.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n -0 1 -.names a_c_19__n.BLIF a_i_19__n -0 1 .names inst_AS_000_INTreg.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n 11 1 -.names CLK_030_c.BLIF CLK_030_i +.names inst_VPA_D.BLIF VPA_D_i 0 1 .names N_102_i.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n 11 1 .names inst_VMA_INTreg.BLIF VMA_INT_i 0 1 -.names VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un3_n +.names state_machine_un15_clk_000_d_n.BLIF vma_int_0_un3_n 0 1 +.names cpu_est_0_.BLIF cpu_est_i_0__n +0 1 +.names state_machine_un8_clk_000_d_1_i_0_n.BLIF \ +state_machine_un15_clk_000_d_n.BLIF vma_int_0_un1_n +11 1 +.names cpu_est_1_.BLIF cpu_est_i_1__n +0 1 +.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n +11 1 +.names cpu_est_3_reg.BLIF cpu_est_i_3__n +0 1 +.names un1_as_030_4.BLIF uds_000_int_0_un3_n +0 1 +.names state_machine_un8_clk_000_d_1_n.BLIF \ +state_machine_un8_clk_000_d_1_i_0_n +0 1 +.names inst_UDS_000_INTreg.BLIF un1_as_030_4.BLIF uds_000_int_0_un1_n +11 1 .names DTACK_c.BLIF DTACK_i 0 1 -.names inst_VPA_SYNC.BLIF VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un1_n +.names state_machine_uds_000_int_8_n.BLIF uds_000_int_0_un3_n.BLIF \ +uds_000_int_0_un0_n 11 1 .names SM_AMIGA_3_.BLIF sm_amiga_i_3__n 0 1 +.names DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un3_n +0 1 +.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n +0 1 +.names inst_DTACK_SYNC.BLIF DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un1_n +11 1 +.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +0 1 +.names DTACK_SYNC_1_sqmuxa_i.BLIF dtack_sync_0_un3_n.BLIF dtack_sync_0_un0_n +11 1 +.names DTACK_SYNC_1_sqmuxa.BLIF DTACK_SYNC_1_sqmuxa_i +0 1 +.names VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un3_n +0 1 +.names VPA_SYNC_1_sqmuxa.BLIF VPA_SYNC_1_sqmuxa_i +0 1 +.names inst_VPA_SYNC.BLIF VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un1_n +11 1 +.names N_98.BLIF N_98_i +0 1 .names VPA_SYNC_1_sqmuxa_i.BLIF vpa_sync_0_un3_n.BLIF vpa_sync_0_un0_n 11 1 -.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n +.names state_machine_un42_clk_030_n.BLIF state_machine_un42_clk_030_i_n +0 1 +.names DSACK_INT_1_sqmuxa.BLIF dsack_int_0_1__un3_n +0 1 +.names UDS_000_INT_0_sqmuxa_1.BLIF UDS_000_INT_0_sqmuxa_1_i +0 1 +.names DSACK_INT_1_.BLIF DSACK_INT_1_sqmuxa.BLIF dsack_int_0_1__un1_n +11 1 +.names UDS_000_INT_0_sqmuxa.BLIF UDS_000_INT_0_sqmuxa_i +0 1 +.names N_98_i.BLIF dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un0_n +11 1 +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i 0 1 .names state_machine_un17_clk_030_n.BLIF as_030_000_sync_0_un3_n 0 1 -.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n +.names DS_030_c.BLIF DS_030_i 0 1 .names state_machine_as_030_000_sync_3_n.BLIF \ state_machine_un17_clk_030_n.BLIF as_030_000_sync_0_un1_n 11 1 -.names a_c_30__n.BLIF a_i_30__n +.names cpu_est_2_.BLIF cpu_est_i_2__n 0 1 .names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF \ as_030_000_sync_0_un0_n 11 1 +.names state_machine_un13_clk_000_d_2_n.BLIF \ +state_machine_un13_clk_000_d_2_i_n +0 1 +.names state_machine_un17_clk_030_n.BLIF fpu_cs_int_0_un3_n +0 1 +.names inst_CLK_000_DD.BLIF CLK_000_DD_i +0 1 +.names un1_as_030_3.BLIF state_machine_un17_clk_030_n.BLIF fpu_cs_int_0_un1_n +11 1 +.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n +0 1 +.names inst_FPU_CS_INTreg.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un0_n +11 1 +.names CLK_030_c.BLIF CLK_030_i +0 1 +.names un1_as_030_4.BLIF lds_000_int_0_un3_n +0 1 +.names a_c_30__n.BLIF a_i_30__n +0 1 +.names inst_LDS_000_INTreg.BLIF un1_as_030_4.BLIF lds_000_int_0_un1_n +11 1 .names a_c_31__n.BLIF a_i_31__n 0 1 -.names inst_RISING_CLK_AMIGA.BLIF ipl_030_0_2__un3_n -0 1 +.names state_machine_lds_000_int_8_n.BLIF lds_000_int_0_un3_n.BLIF \ +lds_000_int_0_un0_n +11 1 .names a_c_28__n.BLIF a_i_28__n 0 1 -.names ipl_c_2__n.BLIF inst_RISING_CLK_AMIGA.BLIF ipl_030_0_2__un1_n -11 1 +.names clk_un4_clk_000_dd_n.BLIF cpu_est_0_3__un3_n +0 1 .names a_c_29__n.BLIF a_i_29__n 0 1 -.names IPL_030DFFSH_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n +.names clk_cpu_est_11_3__n.BLIF clk_un4_clk_000_dd_n.BLIF cpu_est_0_3__un1_n 11 1 .names a_c_26__n.BLIF a_i_26__n 0 1 -.names inst_RISING_CLK_AMIGA.BLIF ipl_030_0_1__un3_n -0 1 +.names cpu_est_3_reg.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n +11 1 .names a_c_27__n.BLIF a_i_27__n 0 1 -.names ipl_c_1__n.BLIF inst_RISING_CLK_AMIGA.BLIF ipl_030_0_1__un1_n -11 1 +.names clk_un4_clk_000_dd_n.BLIF cpu_est_0_2__un3_n +0 1 .names a_c_24__n.BLIF a_i_24__n 0 1 -.names IPL_030DFFSH_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n +.names N_122_i.BLIF clk_un4_clk_000_dd_n.BLIF cpu_est_0_2__un1_n 11 1 .names a_c_25__n.BLIF a_i_25__n 0 1 -.names inst_RISING_CLK_AMIGA.BLIF ipl_030_0_0__un3_n -0 1 -.names ipl_c_0__n.BLIF inst_RISING_CLK_AMIGA.BLIF ipl_030_0_0__un1_n +.names cpu_est_2_.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n 11 1 -.names IPL_030DFFSH_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n -11 1 -.names RST_c.BLIF RST_i +.names a_c_19__n.BLIF a_i_19__n 0 1 -.names state_machine_un4_bgack_000_n.BLIF bgack_030_int_0_un3_n -0 1 -.names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i -0 1 -.names BGACK_000_c.BLIF state_machine_un4_bgack_000_n.BLIF \ -bgack_030_int_0_un1_n -11 1 -.names CPU_SPACE_c.BLIF CPU_SPACE_i -0 1 -.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \ -bgack_030_int_0_un0_n -11 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i -0 1 -.names DSACK_INT_1_sqmuxa.BLIF dsack_int_0_1__un3_n -0 1 -.names DSACK_INT_1_.BLIF DSACK_INT_1_sqmuxa.BLIF dsack_int_0_1__un1_n -11 1 -.names N_98_i.BLIF dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un0_n -11 1 .names state_machine_un1_clk_030_n.BLIF bg_000_0_un3_n 0 1 +.names a_c_16__n.BLIF a_i_16__n +0 1 .names un1_bg_030.BLIF state_machine_un1_clk_030_n.BLIF bg_000_0_un1_n 11 1 +.names a_c_18__n.BLIF a_i_18__n +0 1 .names BG_000DFFSHreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n 11 1 -.names DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un3_n +.names state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n 0 1 -.names inst_DTACK_SYNC.BLIF DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un1_n +.names RST_c.BLIF RST_i +0 1 +.names BGACK_000_c.BLIF state_machine_un6_bgack_000_n.BLIF \ +bgack_030_int_0_un1_n 11 1 -.names DTACK_SYNC_1_sqmuxa_i.BLIF dtack_sync_0_un3_n.BLIF dtack_sync_0_un0_n +.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \ +bgack_030_int_0_un0_n 11 1 -.names cpu_est_0_.BLIF clk_un3_clk_000_dd_n.BLIF cpu_est_0_0_ +.names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i +0 1 +.names clk_un4_clk_000_dd_n.BLIF cpu_est_0_1__un3_n +0 1 +.names CPU_SPACE_c.BLIF CPU_SPACE_i +0 1 +.names clk_cpu_est_11_1__n.BLIF clk_un4_clk_000_dd_n.BLIF cpu_est_0_1__un1_n +11 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i +0 1 +.names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n +11 1 +.names clk_un4_clk_000_dd_n.BLIF ipl_030_0_0__un3_n +0 1 +.names ipl_c_0__n.BLIF clk_un4_clk_000_dd_n.BLIF ipl_030_0_0__un1_n +11 1 +.names IPL_030DFFSH_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n +11 1 +.names clk_un4_clk_000_dd_n.BLIF ipl_030_0_1__un3_n +0 1 +.names ipl_c_1__n.BLIF clk_un4_clk_000_dd_n.BLIF ipl_030_0_1__un1_n +11 1 +.names IPL_030DFFSH_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n +11 1 +.names clk_un4_clk_000_dd_n.BLIF ipl_030_0_2__un3_n +0 1 +.names ipl_c_2__n.BLIF clk_un4_clk_000_dd_n.BLIF ipl_030_0_2__un1_n +11 1 +.names IPL_030DFFSH_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n +11 1 +.names cpu_est_0_.BLIF clk_un4_clk_000_dd_n.BLIF cpu_est_0_0_ 01 1 10 1 11 0 @@ -977,7 +976,7 @@ bgack_030_int_0_un0_n .names vcc_n_n.BLIF AMIGA_BUS_ENABLE_LOW 1 1 0 0 -.names N_170.BLIF CIIN +.names N_171.BLIF CIIN 1 1 0 0 .names IPL_030DFFSH_1_reg.BLIF IPL_030_1_ @@ -986,33 +985,6 @@ bgack_030_int_0_un0_n .names IPL_030DFFSH_0_reg.BLIF IPL_030_0_ 1 1 0 0 -.names CLK_OSZI_c.BLIF cpu_est_3_reg.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_7_.C -1 1 -0 0 -.names RST_i.BLIF SM_AMIGA_7_.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C -1 1 -0 0 -.names RST_i.BLIF SM_AMIGA_6_.AR -1 1 -0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C -1 1 -0 0 -.names RST_i.BLIF SM_AMIGA_5_.AR -1 1 -0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C -1 1 -0 0 -.names RST_i.BLIF SM_AMIGA_4_.AR -1 1 -0 0 .names CLK_OSZI_c.BLIF SM_AMIGA_3_.C 1 1 0 0 @@ -1037,30 +1009,6 @@ bgack_030_int_0_un0_n .names RST_i.BLIF SM_AMIGA_0_.AR 1 1 0 0 -.names cpu_est_0_.BLIF cpu_est_d_0_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF cpu_est_d_0_.C -1 1 -0 0 -.names cpu_est_1_.BLIF cpu_est_d_1_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF cpu_est_d_1_.C -1 1 -0 0 -.names cpu_est_2_.BLIF cpu_est_d_2_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF cpu_est_d_2_.C -1 1 -0 0 -.names cpu_est_3_reg.BLIF cpu_est_d_3_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF cpu_est_d_3_.C -1 1 -0 0 .names CLK_OSZI_c.BLIF IPL_030DFFSH_0_reg.C 1 1 0 0 @@ -1079,40 +1027,28 @@ bgack_030_int_0_un0_n .names RST_i.BLIF IPL_030DFFSH_2_reg.AP 1 1 0 0 -.names cpu_est_0_0_.BLIF cpu_est_0_.D +.names CLK_OSZI_c.BLIF SM_AMIGA_7_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF cpu_est_0_.C +.names RST_i.BLIF SM_AMIGA_7_.AP 1 1 0 0 -.names CLK_OSZI_c.BLIF cpu_est_1_.C +.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF cpu_est_2_.C +.names RST_i.BLIF SM_AMIGA_6_.AR 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_VPA_SYNC.C +.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C 1 1 0 0 -.names RST_i.BLIF inst_VPA_SYNC.AP +.names RST_i.BLIF SM_AMIGA_5_.AR 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C +.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C 1 1 0 0 -.names RST_i.BLIF inst_AS_030_000_SYNC.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C -1 1 -0 0 -.names RST_i.BLIF inst_VMA_INTreg.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C -1 1 -0 0 -.names RST_i.BLIF BG_000DFFSHreg.AP +.names RST_i.BLIF SM_AMIGA_4_.AR 1 1 0 0 .names CLK_OSZI_c.BLIF DSACK_INT_1_.C @@ -1121,6 +1057,12 @@ bgack_030_int_0_un0_n .names RST_i.BLIF DSACK_INT_1_.AP 1 1 0 0 +.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C +1 1 +0 0 +.names RST_i.BLIF inst_VMA_INTreg.AP +1 1 +0 0 .names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C 1 1 0 0 @@ -1133,10 +1075,19 @@ bgack_030_int_0_un0_n .names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_UDS_000_INTreg.C +.names cpu_est_0_0_.BLIF cpu_est_0_.D 1 1 0 0 -.names RST_i.BLIF inst_UDS_000_INTreg.AP +.names CLK_OSZI_c.BLIF cpu_est_0_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF cpu_est_1_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF cpu_est_2_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF cpu_est_3_reg.C 1 1 0 0 .names CLK_OSZI_c.BLIF inst_LDS_000_INTreg.C @@ -1157,19 +1108,40 @@ bgack_030_int_0_un0_n .names RST_i.BLIF inst_FPU_CS_INTreg.AP 1 1 0 0 +.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C +1 1 +0 0 +.names RST_i.BLIF inst_AS_030_000_SYNC.AP +1 1 +0 0 .names CLK_OSZI_c.BLIF inst_AS_000_INTreg.C 1 1 0 0 .names RST_i.BLIF inst_AS_000_INTreg.AP 1 1 0 0 +.names CLK_OSZI_c.BLIF inst_VPA_SYNC.C +1 1 +0 0 +.names RST_i.BLIF inst_VPA_SYNC.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C +1 1 +0 0 +.names RST_i.BLIF BG_000DFFSHreg.AP +1 1 +0 0 .names CLK_OSZI_c.BLIF inst_DTACK_DMA.C 1 1 0 0 .names RST_i.BLIF inst_DTACK_DMA.AP 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_RISING_CLK_AMIGA.C +.names CLK_OSZI_c.BLIF inst_UDS_000_INTreg.C +1 1 +0 0 +.names RST_i.BLIF inst_UDS_000_INTreg.AP 1 1 0 0 .names CLK_OSZI_c.BLIF CLK_CNT_0_.C @@ -1181,7 +1153,7 @@ bgack_030_int_0_un0_n .names CLK_OSZI_c.BLIF inst_VPA_D.C 1 1 0 0 -.names CLK_000_c.BLIF inst_CLK_000_D.D +.names CLK_000.BLIF inst_CLK_000_D.D 1 1 0 0 .names CLK_OSZI_c.BLIF inst_CLK_000_D.C @@ -1214,9 +1186,6 @@ bgack_030_int_0_un0_n .names vcc_n_n.BLIF DSACK_0_ 1 1 0 0 -.names CLK_OSZI.BLIF CLK_OSZI_c -1 1 -0 0 .names IPL_0_.BLIF ipl_c_0__n 1 1 0 0 @@ -1253,18 +1222,18 @@ bgack_030_int_0_un0_n .names SIZE_0_.BLIF size_c_0__n 1 1 0 0 -.names A_15_.BLIF a_15__n -1 1 -0 0 .names SIZE_1_.BLIF size_c_1__n 1 1 0 0 -.names A_14_.BLIF a_14__n +.names A_15_.BLIF a_15__n 1 1 0 0 .names A_0_.BLIF a_c_0__n 1 1 0 0 +.names A_14_.BLIF a_14__n +1 1 +0 0 .names A_13_.BLIF a_13__n 1 1 0 0 @@ -1364,7 +1333,7 @@ bgack_030_int_0_un0_n .names CLK_030.BLIF CLK_030_c 1 1 0 0 -.names CLK_000.BLIF CLK_000_c +.names CLK_OSZI.BLIF CLK_OSZI_c 1 1 0 0 .names CPU_SPACE_i.BLIF DSACK_1_.OE @@ -1391,7 +1360,7 @@ bgack_030_int_0_un0_n .names FPU_CS_INT_i.BLIF AVEC_EXP.OE 1 1 0 0 -.names N_167.BLIF CIIN.OE +.names N_168.BLIF CIIN.OE 1 1 0 0 .end diff --git a/Logic/68030_tk.bl3 b/Logic/68030_tk.bl3 index e914de1..509350c 100644 --- a/Logic/68030_tk.bl3 +++ b/Logic/68030_tk.bl3 @@ -1,97 +1,64 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Thu May 15 22:21:53 2014 +#$ DATE Thu May 15 23:02:46 2014 #$ MODULE 68030_tk -#$ PINS 59 A_28_ A_27_ SIZE_1_ A_26_ A_25_ A_31_ A_24_ A_23_ IPL_030_2_ A_22_ A_21_ \ -# IPL_2_ A_20_ A_19_ DSACK_1_ A_18_ A_17_ FC_1_ A_16_ AS_030 AS_000 DS_030 UDS_000 LDS_000 \ -# CPU_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT \ -# CLK_EXP A_0_ FPU_CS IPL_030_1_ DTACK IPL_030_0_ AVEC IPL_1_ AVEC_EXP IPL_0_ E DSACK_0_ VPA \ -# FC_0_ VMA RST RESET RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN \ -# SIZE_0_ A_30_ A_29_ -#$ NODES 39 CLK_OUT_INTreg IPL_030DFFSH_0_reg inst_BGACK_030_INTreg \ -# inst_FPU_CS_INTreg IPL_030DFFSH_1_reg cpu_est_3_reg inst_VMA_INTreg \ -# IPL_030DFFSH_2_reg cpu_est_0_ cpu_est_1_ cpu_est_d_0_ cpu_est_d_3_ \ +#$ PINS 59 A_21_ A_20_ SIZE_1_ A_19_ A_18_ A_31_ A_17_ A_16_ IPL_030_2_ IPL_2_ DSACK_1_ \ +# FC_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 CPU_SPACE BERR BG_030 BG_000 A_0_ BGACK_030 \ +# IPL_030_1_ BGACK_000 IPL_030_0_ CLK_030 IPL_1_ CLK_000 IPL_0_ CLK_OSZI DSACK_0_ \ +# CLK_DIV_OUT FC_0_ CLK_EXP FPU_CS DTACK AVEC AVEC_EXP E VPA VMA RST RESET RW \ +# AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ \ +# A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ +#$ NODES 34 IPL_030DFFSH_1_reg IPL_030DFFSH_2_reg inst_BGACK_030_INTreg \ +# inst_FPU_CS_INTreg cpu_est_3_reg inst_VMA_INTreg cpu_est_0_ cpu_est_1_ \ # inst_AS_000_INTreg inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC \ -# inst_CLK_000_D inst_CLK_000_DD inst_CLK_OUT_PRE cpu_est_d_1_ cpu_est_d_2_ \ -# cpu_est_2_ CLK_CNT_0_ SM_AMIGA_6_ SM_AMIGA_7_ inst_UDS_000_INTreg RESETDFFreg \ -# inst_LDS_000_INTreg inst_RISING_CLK_AMIGA SM_AMIGA_1_ DSACK_INT_1_ inst_DTACK_DMA \ -# SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_5_ SM_AMIGA_2_ SM_AMIGA_0_ BG_000DFFSHreg +# inst_CLK_000_D inst_CLK_000_DD inst_CLK_OUT_PRE cpu_est_2_ RESETDFFreg CLK_CNT_0_ \ +# SM_AMIGA_6_ SM_AMIGA_7_ inst_UDS_000_INTreg inst_LDS_000_INTreg SM_AMIGA_1_ \ +# DSACK_INT_1_ inst_DTACK_DMA SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_5_ SM_AMIGA_2_ \ +# SM_AMIGA_0_ BG_000DFFSHreg CLK_OUT_INTreg IPL_030DFFSH_0_reg .model bus68030 .inputs SIZE_1_.BLIF A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF AS_030.BLIF DS_030.BLIF \ CPU_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF \ CLK_OSZI.BLIF VPA.BLIF RST.BLIF RW.BLIF SIZE_0_.BLIF A_30_.BLIF A_29_.BLIF \ A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF \ A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF A_0_.BLIF \ -IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF CLK_OUT_INTreg.BLIF IPL_030DFFSH_0_reg.BLIF \ -inst_BGACK_030_INTreg.BLIF inst_FPU_CS_INTreg.BLIF IPL_030DFFSH_1_reg.BLIF \ -cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF IPL_030DFFSH_2_reg.BLIF \ -cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_d_0_.BLIF cpu_est_d_3_.BLIF \ +IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF IPL_030DFFSH_1_reg.BLIF \ +IPL_030DFFSH_2_reg.BLIF inst_BGACK_030_INTreg.BLIF inst_FPU_CS_INTreg.BLIF \ +cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \ inst_AS_000_INTreg.BLIF inst_AS_030_000_SYNC.BLIF inst_DTACK_SYNC.BLIF \ inst_VPA_D.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF \ -inst_CLK_OUT_PRE.BLIF cpu_est_d_1_.BLIF cpu_est_d_2_.BLIF cpu_est_2_.BLIF \ -CLK_CNT_0_.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_7_.BLIF inst_UDS_000_INTreg.BLIF \ -RESETDFFreg.BLIF inst_LDS_000_INTreg.BLIF inst_RISING_CLK_AMIGA.BLIF \ -SM_AMIGA_1_.BLIF DSACK_INT_1_.BLIF inst_DTACK_DMA.BLIF SM_AMIGA_4_.BLIF \ -SM_AMIGA_3_.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_0_.BLIF \ -BG_000DFFSHreg.BLIF DSACK_1_.PIN.BLIF DTACK.PIN.BLIF +inst_CLK_OUT_PRE.BLIF cpu_est_2_.BLIF RESETDFFreg.BLIF CLK_CNT_0_.BLIF \ +SM_AMIGA_6_.BLIF SM_AMIGA_7_.BLIF inst_UDS_000_INTreg.BLIF \ +inst_LDS_000_INTreg.BLIF SM_AMIGA_1_.BLIF DSACK_INT_1_.BLIF \ +inst_DTACK_DMA.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_5_.BLIF \ +SM_AMIGA_2_.BLIF SM_AMIGA_0_.BLIF BG_000DFFSHreg.BLIF CLK_OUT_INTreg.BLIF \ +IPL_030DFFSH_0_reg.BLIF DSACK_1_.PIN.BLIF DTACK.PIN.BLIF .outputs IPL_030_2_ AS_000 UDS_000 LDS_000 BERR BG_000 BGACK_030 CLK_DIV_OUT \ CLK_EXP FPU_CS AVEC AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR \ -AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ cpu_est_3_reg.C SM_AMIGA_7_.D \ +AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_3_.D SM_AMIGA_3_.C \ +SM_AMIGA_3_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D \ +SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR \ +IPL_030DFFSH_0_reg.D IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP \ +IPL_030DFFSH_1_reg.D IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP \ +IPL_030DFFSH_2_reg.D IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D \ SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR \ SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C \ -SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D \ -SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR \ -SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR cpu_est_d_0_.D cpu_est_d_0_.C \ -cpu_est_d_1_.D cpu_est_d_1_.C cpu_est_d_2_.D cpu_est_d_2_.C cpu_est_d_3_.D \ -cpu_est_d_3_.C IPL_030DFFSH_0_reg.D IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP \ -IPL_030DFFSH_1_reg.D IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP \ -IPL_030DFFSH_2_reg.D IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP cpu_est_0_.D \ +SM_AMIGA_4_.AR DSACK_INT_1_.D DSACK_INT_1_.C DSACK_INT_1_.AP inst_VMA_INTreg.C \ +inst_VMA_INTreg.AP inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C \ +inst_BGACK_030_INTreg.AP inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C cpu_est_0_.D \ cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C \ -inst_VPA_SYNC.D inst_VPA_SYNC.C inst_VPA_SYNC.AP inst_AS_030_000_SYNC.D \ -inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_VMA_INTreg.C \ -inst_VMA_INTreg.AP BG_000DFFSHreg.D BG_000DFFSHreg.C BG_000DFFSHreg.AP \ -DSACK_INT_1_.D DSACK_INT_1_.C DSACK_INT_1_.AP inst_BGACK_030_INTreg.D \ -inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP inst_CLK_OUT_PRE.D \ -inst_CLK_OUT_PRE.C inst_UDS_000_INTreg.D inst_UDS_000_INTreg.C \ -inst_UDS_000_INTreg.AP inst_LDS_000_INTreg.D inst_LDS_000_INTreg.C \ +cpu_est_3_reg.C inst_LDS_000_INTreg.D inst_LDS_000_INTreg.C \ inst_LDS_000_INTreg.AP inst_DTACK_SYNC.D inst_DTACK_SYNC.C inst_DTACK_SYNC.AP \ inst_FPU_CS_INTreg.D inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP \ +inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP \ inst_AS_000_INTreg.D inst_AS_000_INTreg.C inst_AS_000_INTreg.AP \ -inst_DTACK_DMA.D inst_DTACK_DMA.C inst_DTACK_DMA.AP inst_RISING_CLK_AMIGA.D \ -inst_RISING_CLK_AMIGA.C CLK_CNT_0_.D CLK_CNT_0_.C inst_VPA_D.D inst_VPA_D.C \ +inst_VPA_SYNC.D inst_VPA_SYNC.C inst_VPA_SYNC.AP BG_000DFFSHreg.D \ +BG_000DFFSHreg.C BG_000DFFSHreg.AP inst_DTACK_DMA.D inst_DTACK_DMA.C \ +inst_DTACK_DMA.AP inst_UDS_000_INTreg.D inst_UDS_000_INTreg.C \ +inst_UDS_000_INTreg.AP CLK_CNT_0_.D CLK_CNT_0_.C inst_VPA_D.D inst_VPA_D.C \ inst_CLK_000_D.D inst_CLK_000_D.C RESETDFFreg.D RESETDFFreg.C \ inst_CLK_000_DD.D inst_CLK_000_DD.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C DSACK_1_ \ DTACK DSACK_0_ DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE BERR.OE \ DSACK_0_.OE AVEC_EXP.OE CIIN.OE cpu_est_3_reg.D.X1 cpu_est_3_reg.D.X2 \ inst_VMA_INTreg.D.X1 inst_VMA_INTreg.D.X2 -.names inst_AS_000_INTreg.BLIF inst_CLK_000_D.BLIF SM_AMIGA_7_.BLIF \ -SM_AMIGA_0_.BLIF SM_AMIGA_7_.D --11- 1 -11-1 1 -0-0- 0 ---00 0 --0-- 0 -.names inst_AS_030_000_SYNC.BLIF inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF \ -SM_AMIGA_6_.BLIF SM_AMIGA_7_.BLIF SM_AMIGA_6_.D ---11- 1 --0-1- 1 -1--1- 1 --0--1 1 -010-- 0 --1-0- 0 ----00 0 -.names inst_AS_030_000_SYNC.BLIF inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF \ -SM_AMIGA_6_.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_5_.D -0101- 1 --1--1 1 --0--- 0 ----00 0 ---1-0 0 -1---0 0 -.names inst_CLK_000_D.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_4_.D -01- 1 -0-1 1 --00 0 -1-- 0 .names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D.BLIF \ SM_AMIGA_4_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_3_.D --11- 1 @@ -126,24 +93,76 @@ SM_AMIGA_1_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_0_.D ---00 0 --0-0 0 -1--0 0 -.names IPL_0_.BLIF IPL_030DFFSH_0_reg.BLIF inst_RISING_CLK_AMIGA.BLIF \ -IPL_030DFFSH_0_reg.D --10 1 -1-1 1 +.names IPL_0_.BLIF inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF \ +IPL_030DFFSH_0_reg.BLIF IPL_030DFFSH_0_reg.D +110- 1 +--11 1 +-0-1 1 +010- 0 +--10 0 +-0-0 0 +.names IPL_1_.BLIF IPL_030DFFSH_1_reg.BLIF inst_CLK_000_D.BLIF \ +inst_CLK_000_DD.BLIF IPL_030DFFSH_1_reg.D +1-10 1 +-10- 1 +-1-1 1 +0-10 0 +-00- 0 +-0-1 0 +.names IPL_2_.BLIF IPL_030DFFSH_2_reg.BLIF inst_CLK_000_D.BLIF \ +inst_CLK_000_DD.BLIF IPL_030DFFSH_2_reg.D +1-10 1 +-10- 1 +-1-1 1 +0-10 0 +-00- 0 +-0-1 0 +.names inst_AS_000_INTreg.BLIF inst_CLK_000_D.BLIF SM_AMIGA_7_.BLIF \ +SM_AMIGA_0_.BLIF SM_AMIGA_7_.D +-11- 1 +11-1 1 +0-0- 0 +--00 0 +-0-- 0 +.names inst_AS_030_000_SYNC.BLIF inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF \ +SM_AMIGA_6_.BLIF SM_AMIGA_7_.BLIF SM_AMIGA_6_.D +--11- 1 +-0-1- 1 +1--1- 1 +-0--1 1 +010-- 0 +-1-0- 0 +---00 0 +.names inst_AS_030_000_SYNC.BLIF inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF \ +SM_AMIGA_6_.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_5_.D +0101- 1 +-1--1 1 +-0--- 0 +---00 0 +--1-0 0 +1---0 0 +.names inst_CLK_000_D.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_4_.D +01- 1 +0-1 1 -00 0 -0-1 0 -.names IPL_1_.BLIF IPL_030DFFSH_1_reg.BLIF inst_RISING_CLK_AMIGA.BLIF \ -IPL_030DFFSH_1_reg.D --10 1 -1-1 1 --00 0 -0-1 0 -.names IPL_2_.BLIF IPL_030DFFSH_2_reg.BLIF inst_RISING_CLK_AMIGA.BLIF \ -IPL_030DFFSH_2_reg.D --10 1 -1-1 1 --00 0 -0-1 0 +1-- 0 +.names AS_030.BLIF inst_CLK_000_D.BLIF inst_CLK_OUT_PRE.BLIF SM_AMIGA_1_.BLIF \ +DSACK_INT_1_.BLIF DSACK_INT_1_.D +1--0- 1 +1-0-- 1 +11--- 1 +---01 1 +--0-1 1 +-1--1 1 +-011- 0 +0---0 0 +.names BGACK_000.BLIF inst_BGACK_030_INTreg.BLIF inst_CLK_000_D.BLIF \ +inst_CLK_000_DD.BLIF inst_BGACK_030_INTreg.D +1-10 1 +11-- 1 +-00- 0 +0--- 0 +-0-1 0 .names cpu_est_3_reg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_CLK_000_D.BLIF \ inst_CLK_000_DD.BLIF cpu_est_2_.BLIF cpu_est_1_.D 0--100 1 @@ -171,93 +190,6 @@ inst_CLK_000_DD.BLIF cpu_est_2_.BLIF cpu_est_2_.D -01--0 0 ----10 0 ---0-0 0 -.names AS_030.BLIF cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF \ -cpu_est_1_.BLIF inst_VPA_D.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D.BLIF \ -cpu_est_2_.BLIF SM_AMIGA_3_.BLIF inst_VPA_SYNC.D -------1-0- 1 -------10-- 1 ------11--- 1 -----1-1--- 1 ----1--1--- 1 ---1---1--- 1 --0----1--- 1 -------1--0 1 -1-------0- 1 -1------0-- 1 -1----1---- 1 -1---1----- 1 -1--1------ 1 -1-1------- 1 -10-------- 1 -1--------0 1 --10000-111 0 -0-----0--- 0 -.names FC_1_.BLIF AS_030.BLIF CPU_SPACE.BLIF BGACK_000.BLIF CLK_030.BLIF \ -A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF FC_0_.BLIF \ -inst_AS_030_000_SYNC.BLIF inst_AS_030_000_SYNC.D -1--1100101- 1 -----0-----1 1 ---1-1------ 1 --1--------- 1 --00-1----0- 0 --00-1---1-- 0 --00-1--0--- 0 --00-1-1---- 0 --00-11----- 0 --0001------ 0 -000-1------ 0 --0--0-----0 0 -.names AS_030.BLIF CPU_SPACE.BLIF BG_030.BLIF CLK_030.BLIF SM_AMIGA_6_.BLIF \ -SM_AMIGA_7_.BLIF BG_000DFFSHreg.BLIF BG_000DFFSHreg.D ----000- 1 ----1--1 1 --1-0--- 1 -0--0--- 1 ---1---- 1 -1000-1- 0 -10001-- 0 ---01--0 0 -.names AS_030.BLIF inst_CLK_000_D.BLIF inst_CLK_OUT_PRE.BLIF SM_AMIGA_1_.BLIF \ -DSACK_INT_1_.BLIF DSACK_INT_1_.D -1--0- 1 -1-0-- 1 -11--- 1 ----01 1 ---0-1 1 --1--1 1 --011- 0 -0---0 0 -.names BGACK_000.BLIF inst_BGACK_030_INTreg.BLIF inst_RISING_CLK_AMIGA.BLIF \ -inst_BGACK_030_INTreg.D -11- 1 -1-1 1 --00 0 -0-- 0 -.names AS_030.BLIF DS_030.BLIF RW.BLIF A_0_.BLIF inst_AS_030_000_SYNC.BLIF \ -inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF SM_AMIGA_6_.BLIF \ -inst_UDS_000_INTreg.BLIF SM_AMIGA_4_.BLIF inst_UDS_000_INTreg.D --0110101-- 1 --001-1---1 1 ---1----01- 1 ---1---1-1- 1 ---1-1---1- 1 -1-1----0-- 1 -1-1---1--- 1 -1-1-1----- 1 ---0-----10 1 ------0--1- 1 --1------1- 1 -1-0------0 1 -1----0---- 1 -11-------- 1 --0100101-- 0 --000-1---1 0 -0-1----00- 0 -0-1---1-0- 0 -0-1-1---0- 0 -0----0--0- 0 -0-0-----00 0 -01------0- 0 .names SIZE_1_.BLIF AS_030.BLIF DS_030.BLIF RW.BLIF SIZE_0_.BLIF A_0_.BLIF \ inst_AS_030_000_SYNC.BLIF inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF \ SM_AMIGA_6_.BLIF inst_LDS_000_INTreg.BLIF SM_AMIGA_4_.BLIF \ @@ -314,6 +246,21 @@ inst_FPU_CS_INTreg.D -1-------- 1 101100101- 0 -0-0-----0 0 +.names FC_1_.BLIF AS_030.BLIF CPU_SPACE.BLIF BGACK_000.BLIF CLK_030.BLIF \ +A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF FC_0_.BLIF \ +inst_AS_030_000_SYNC.BLIF inst_AS_030_000_SYNC.D +1--1100101- 1 +----0-----1 1 +--1-1------ 1 +-1--------- 1 +-00-1----0- 0 +-00-1---1-- 0 +-00-1--0--- 0 +-00-1-1---- 0 +-00-11----- 0 +-0001------ 0 +000-1------ 0 +-0--0-----0 0 .names AS_030.BLIF inst_AS_000_INTreg.BLIF inst_AS_030_000_SYNC.BLIF \ inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF SM_AMIGA_6_.BLIF inst_AS_000_INTreg.D -1--1- 1 @@ -326,14 +273,66 @@ inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF SM_AMIGA_6_.BLIF inst_AS_000_INTreg.D 1----0 1 --0101 0 00---- 0 +.names AS_030.BLIF cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF \ +cpu_est_1_.BLIF inst_VPA_D.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D.BLIF \ +cpu_est_2_.BLIF SM_AMIGA_3_.BLIF inst_VPA_SYNC.D +------1-0- 1 +------10-- 1 +-----11--- 1 +----1-1--- 1 +---1--1--- 1 +--1---1--- 1 +-0----1--- 1 +------1--0 1 +1-------0- 1 +1------0-- 1 +1----1---- 1 +1---1----- 1 +1--1------ 1 +1-1------- 1 +10-------- 1 +1--------0 1 +-10000-111 0 +0-----0--- 0 +.names AS_030.BLIF CPU_SPACE.BLIF BG_030.BLIF CLK_030.BLIF SM_AMIGA_6_.BLIF \ +SM_AMIGA_7_.BLIF BG_000DFFSHreg.BLIF BG_000DFFSHreg.D +---000- 1 +---1--1 1 +-1-0--- 1 +0--0--- 1 +--1---- 1 +1000-1- 0 +10001-- 0 +--01--0 0 .names inst_AS_000_INTreg.BLIF DSACK_1_.PIN.BLIF inst_DTACK_DMA.D 1- 1 -1 1 00 0 -.names CLK_000.BLIF inst_CLK_000_D.BLIF inst_RISING_CLK_AMIGA.D -10 1 -0- 0 --1 0 +.names AS_030.BLIF DS_030.BLIF RW.BLIF A_0_.BLIF inst_AS_030_000_SYNC.BLIF \ +inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF SM_AMIGA_6_.BLIF \ +inst_UDS_000_INTreg.BLIF SM_AMIGA_4_.BLIF inst_UDS_000_INTreg.D +-0110101-- 1 +-001-1---1 1 +--1----01- 1 +--1---1-1- 1 +--1-1---1- 1 +1-1----0-- 1 +1-1---1--- 1 +1-1-1----- 1 +--0-----10 1 +-----0--1- 1 +-1------1- 1 +1-0------0 1 +1----0---- 1 +11-------- 1 +-0100101-- 0 +-000-1---1 0 +0-1----00- 0 +0-1---1-0- 0 +0-1-1---0- 0 +0----0--0- 0 +0-0-----00 0 +01------0- 0 .names CLK_CNT_0_.BLIF CLK_CNT_0_.D 0 1 1 0 @@ -398,33 +397,6 @@ inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF SM_AMIGA_6_.BLIF inst_AS_000_INTreg.D .names IPL_030DFFSH_0_reg.BLIF IPL_030_0_ 1 1 0 0 -.names CLK_OSZI.BLIF cpu_est_3_reg.C -1 1 -0 0 -.names CLK_OSZI.BLIF SM_AMIGA_7_.C -1 1 -0 0 -.names RST.BLIF SM_AMIGA_7_.AP -0 1 -1 0 -.names CLK_OSZI.BLIF SM_AMIGA_6_.C -1 1 -0 0 -.names RST.BLIF SM_AMIGA_6_.AR -0 1 -1 0 -.names CLK_OSZI.BLIF SM_AMIGA_5_.C -1 1 -0 0 -.names RST.BLIF SM_AMIGA_5_.AR -0 1 -1 0 -.names CLK_OSZI.BLIF SM_AMIGA_4_.C -1 1 -0 0 -.names RST.BLIF SM_AMIGA_4_.AR -0 1 -1 0 .names CLK_OSZI.BLIF SM_AMIGA_3_.C 1 1 0 0 @@ -449,30 +421,6 @@ inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF SM_AMIGA_6_.BLIF inst_AS_000_INTreg.D .names RST.BLIF SM_AMIGA_0_.AR 0 1 1 0 -.names cpu_est_0_.BLIF cpu_est_d_0_.D -1 1 -0 0 -.names CLK_OSZI.BLIF cpu_est_d_0_.C -1 1 -0 0 -.names cpu_est_1_.BLIF cpu_est_d_1_.D -1 1 -0 0 -.names CLK_OSZI.BLIF cpu_est_d_1_.C -1 1 -0 0 -.names cpu_est_2_.BLIF cpu_est_d_2_.D -1 1 -0 0 -.names CLK_OSZI.BLIF cpu_est_d_2_.C -1 1 -0 0 -.names cpu_est_3_reg.BLIF cpu_est_d_3_.D -1 1 -0 0 -.names CLK_OSZI.BLIF cpu_est_d_3_.C -1 1 -0 0 .names CLK_OSZI.BLIF IPL_030DFFSH_0_reg.C 1 1 0 0 @@ -491,44 +439,28 @@ inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF SM_AMIGA_6_.BLIF inst_AS_000_INTreg.D .names RST.BLIF IPL_030DFFSH_2_reg.AP 0 1 1 0 -.names cpu_est_0_.BLIF inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF cpu_est_0_.D -010 1 -10- 1 -1-1 1 -110 0 -00- 0 -0-1 0 -.names CLK_OSZI.BLIF cpu_est_0_.C +.names CLK_OSZI.BLIF SM_AMIGA_7_.C 1 1 0 0 -.names CLK_OSZI.BLIF cpu_est_1_.C -1 1 -0 0 -.names CLK_OSZI.BLIF cpu_est_2_.C -1 1 -0 0 -.names CLK_OSZI.BLIF inst_VPA_SYNC.C -1 1 -0 0 -.names RST.BLIF inst_VPA_SYNC.AP +.names RST.BLIF SM_AMIGA_7_.AP 0 1 1 0 -.names CLK_OSZI.BLIF inst_AS_030_000_SYNC.C +.names CLK_OSZI.BLIF SM_AMIGA_6_.C 1 1 0 0 -.names RST.BLIF inst_AS_030_000_SYNC.AP +.names RST.BLIF SM_AMIGA_6_.AR 0 1 1 0 -.names CLK_OSZI.BLIF inst_VMA_INTreg.C +.names CLK_OSZI.BLIF SM_AMIGA_5_.C 1 1 0 0 -.names RST.BLIF inst_VMA_INTreg.AP +.names RST.BLIF SM_AMIGA_5_.AR 0 1 1 0 -.names CLK_OSZI.BLIF BG_000DFFSHreg.C +.names CLK_OSZI.BLIF SM_AMIGA_4_.C 1 1 0 0 -.names RST.BLIF BG_000DFFSHreg.AP +.names RST.BLIF SM_AMIGA_4_.AR 0 1 1 0 .names CLK_OSZI.BLIF DSACK_INT_1_.C @@ -537,6 +469,12 @@ inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF SM_AMIGA_6_.BLIF inst_AS_000_INTreg.D .names RST.BLIF DSACK_INT_1_.AP 0 1 1 0 +.names CLK_OSZI.BLIF inst_VMA_INTreg.C +1 1 +0 0 +.names RST.BLIF inst_VMA_INTreg.AP +0 1 +1 0 .names CLK_OSZI.BLIF inst_BGACK_030_INTreg.C 1 1 0 0 @@ -551,12 +489,25 @@ inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF SM_AMIGA_6_.BLIF inst_AS_000_INTreg.D .names CLK_OSZI.BLIF inst_CLK_OUT_PRE.C 1 1 0 0 -.names CLK_OSZI.BLIF inst_UDS_000_INTreg.C +.names cpu_est_0_.BLIF inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF cpu_est_0_.D +010 1 +10- 1 +1-1 1 +110 0 +00- 0 +0-1 0 +.names CLK_OSZI.BLIF cpu_est_0_.C +1 1 +0 0 +.names CLK_OSZI.BLIF cpu_est_1_.C +1 1 +0 0 +.names CLK_OSZI.BLIF cpu_est_2_.C +1 1 +0 0 +.names CLK_OSZI.BLIF cpu_est_3_reg.C 1 1 0 0 -.names RST.BLIF inst_UDS_000_INTreg.AP -0 1 -1 0 .names CLK_OSZI.BLIF inst_LDS_000_INTreg.C 1 1 0 0 @@ -575,21 +526,42 @@ inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF SM_AMIGA_6_.BLIF inst_AS_000_INTreg.D .names RST.BLIF inst_FPU_CS_INTreg.AP 0 1 1 0 +.names CLK_OSZI.BLIF inst_AS_030_000_SYNC.C +1 1 +0 0 +.names RST.BLIF inst_AS_030_000_SYNC.AP +0 1 +1 0 .names CLK_OSZI.BLIF inst_AS_000_INTreg.C 1 1 0 0 .names RST.BLIF inst_AS_000_INTreg.AP 0 1 1 0 +.names CLK_OSZI.BLIF inst_VPA_SYNC.C +1 1 +0 0 +.names RST.BLIF inst_VPA_SYNC.AP +0 1 +1 0 +.names CLK_OSZI.BLIF BG_000DFFSHreg.C +1 1 +0 0 +.names RST.BLIF BG_000DFFSHreg.AP +0 1 +1 0 .names CLK_OSZI.BLIF inst_DTACK_DMA.C 1 1 0 0 .names RST.BLIF inst_DTACK_DMA.AP 0 1 1 0 -.names CLK_OSZI.BLIF inst_RISING_CLK_AMIGA.C +.names CLK_OSZI.BLIF inst_UDS_000_INTreg.C 1 1 0 0 +.names RST.BLIF inst_UDS_000_INTreg.AP +0 1 +1 0 .names CLK_OSZI.BLIF CLK_CNT_0_.C 1 1 0 0 @@ -684,26 +656,25 @@ inst_CLK_000_DD.BLIF cpu_est_2_.BLIF cpu_est_3_reg.D.X2 0----1 0 001--- 0 11---0 0 -.names inst_VMA_INTreg.BLIF inst_CLK_000_D.BLIF inst_VMA_INTreg.D.X1 -10 1 -0- 0 --1 0 +.names cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF inst_VMA_INTreg.D.X1 +01 1 +1- 0 +-0 0 .names cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \ -cpu_est_d_0_.BLIF cpu_est_d_3_.BLIF inst_AS_000_INTreg.BLIF inst_VPA_D.BLIF \ -inst_CLK_000_D.BLIF cpu_est_d_1_.BLIF cpu_est_d_2_.BLIF cpu_est_2_.BLIF \ +inst_AS_000_INTreg.BLIF inst_VPA_D.BLIF inst_CLK_000_D.BLIF cpu_est_2_.BLIF \ inst_VMA_INTreg.D.X2 -0110---0---1 1 --1------1--- 1 -----001-111- 1 --0--1------- 0 --0---1------ 0 --0----0----- 0 -1-------0--- 0 --0------0--- 0 ---0-----0--- 0 ----1----0--- 0 --------10--- 0 --0-------0-- 0 --0--------0- 0 ---------0--0 0 +00011-11 1 +-110-001 1 +11------ 1 +10------ 0 +-01----- 0 +-0-0---- 0 +-0--0--- 0 +-0----0- 0 +0------0 0 +-0-----0 0 +010----- 0 +01-1---- 0 +01---1-- 0 +01----1- 0 .end diff --git a/Logic/68030_tk.crf b/Logic/68030_tk.crf index 0596034..a40f593 100644 --- a/Logic/68030_tk.crf +++ b/Logic/68030_tk.crf @@ -1,7 +1,7 @@ // Signal Name Cross Reference File // ispLEVER Classic 1.7.00.05.28.13 -// Design '68030_tk' created Thu May 15 22:21:53 2014 +// Design '68030_tk' created Thu May 15 23:02:46 2014 // LEGEND: '>' Functional Block Port Separator diff --git a/Logic/68030_tk.eq3 b/Logic/68030_tk.eq3 index fb805dd..21108f8 100644 --- a/Logic/68030_tk.eq3 +++ b/Logic/68030_tk.eq3 @@ -2,26 +2,26 @@ Copyright(C), 1992-2013, Lattice Semiconductor Corp. All Rights Reserved. -Design bus68030 created Thu May 15 22:21:53 2014 +Design bus68030 created Thu May 15 23:02:46 2014 P-Terms Fan-in Fan-out Type Name (attributes) --------- ------ ------- ---- ----------------- 0 0 1 Pin BERR 1 1 1 Pin BERR.OE + 1 0 1 Pin DSACK_0_ + 1 1 1 Pin DSACK_0_.OE 1 1 1 Pin CLK_DIV_OUT.D 1 1 1 Pin CLK_DIV_OUT.C 1 0 1 Pin AVEC 0 0 1 Pin AVEC_EXP 1 1 1 Pin AVEC_EXP.OE - 1 0 1 Pin DSACK_0_ - 1 1 1 Pin DSACK_0_.OE 0 0 1 Pin AMIGA_BUS_ENABLE 1 1 1 Pin AMIGA_BUS_DATA_DIR 1 0 1 Pin AMIGA_BUS_ENABLE_LOW 1 4 1 Pin CIIN 1 8 1 Pin CIIN.OE - 2 3 1 Pin IPL_030_2_.D + 3 4 1 Pin IPL_030_2_.D 1 1 1 Pin IPL_030_2_.AP 1 1 1 Pin IPL_030_2_.C 1 1 1 Pin DSACK_1_.OE @@ -43,28 +43,28 @@ Design bus68030 created Thu May 15 22:21:53 2014 3 7 1 Pin BG_000.D- 1 1 1 Pin BG_000.AP 1 1 1 Pin BG_000.C - 2 3 1 Pin BGACK_030.D + 2 4 1 Pin BGACK_030.D 1 1 1 Pin BGACK_030.AP 1 1 1 Pin BGACK_030.C + 3 4 1 Pin IPL_030_1_.D + 1 1 1 Pin IPL_030_1_.AP + 1 1 1 Pin IPL_030_1_.C + 3 4 1 Pin IPL_030_0_.D + 1 1 1 Pin IPL_030_0_.AP + 1 1 1 Pin IPL_030_0_.C 1 1 1 Pin CLK_EXP.D 1 1 1 Pin CLK_EXP.C 2 10 1 Pin FPU_CS.D- 1 1 1 Pin FPU_CS.AP 1 1 1 Pin FPU_CS.C - 2 3 1 Pin IPL_030_1_.D - 1 1 1 Pin IPL_030_1_.AP - 1 1 1 Pin IPL_030_1_.C 1 1 1 Pin DTACK.OE 1 2 1 Pin DTACK.D- 1 1 1 Pin DTACK.AP 1 1 1 Pin DTACK.C - 2 3 1 Pin IPL_030_0_.D - 1 1 1 Pin IPL_030_0_.AP - 1 1 1 Pin IPL_030_0_.C 3 6 1 Pin E.T 1 1 1 Pin E.C 1 1 1 Pin VMA.AP - 2 12 1 Pin VMA.T + 2 8 1 Pin VMA.T 1 1 1 Pin VMA.C 1 1 1 Pin RESET.D 1 1 1 Pin RESET.C @@ -72,10 +72,6 @@ Design bus68030 created Thu May 15 22:21:53 2014 1 1 1 Node cpu_est_0_.C 4 6 1 Node cpu_est_1_.T 1 1 1 Node cpu_est_1_.C - 1 1 1 Node cpu_est_d_0_.D - 1 1 1 Node cpu_est_d_0_.C - 1 1 1 Node cpu_est_d_3_.D - 1 1 1 Node cpu_est_d_3_.C 4 11 1 Node inst_AS_030_000_SYNC.D 1 1 1 Node inst_AS_030_000_SYNC.AP 1 1 1 Node inst_AS_030_000_SYNC.C @@ -93,10 +89,6 @@ Design bus68030 created Thu May 15 22:21:53 2014 1 1 1 Node inst_CLK_000_DD.C 2 2 1 Node inst_CLK_OUT_PRE.D 1 1 1 Node inst_CLK_OUT_PRE.C - 1 1 1 Node cpu_est_d_1_.D - 1 1 1 Node cpu_est_d_1_.C - 1 1 1 Node cpu_est_d_2_.D - 1 1 1 Node cpu_est_d_2_.C 3 6 1 NodeX1 cpu_est_2_.D.X1 1 1 1 NodeX2 cpu_est_2_.D.X2 1 1 1 Node cpu_est_2_.C @@ -108,8 +100,6 @@ Design bus68030 created Thu May 15 22:21:53 2014 2 4 1 Node SM_AMIGA_7_.D 1 1 1 Node SM_AMIGA_7_.AP 1 1 1 Node SM_AMIGA_7_.C - 1 2 1 Node inst_RISING_CLK_AMIGA.D - 1 1 1 Node inst_RISING_CLK_AMIGA.C 1 1 1 Node SM_AMIGA_1_.AR 3 4 1 Node SM_AMIGA_1_.D 1 1 1 Node SM_AMIGA_1_.C @@ -129,9 +119,9 @@ Design bus68030 created Thu May 15 22:21:53 2014 3 5 1 Node SM_AMIGA_0_.D 1 1 1 Node SM_AMIGA_0_.C ========= - 174 P-Term Total: 174 + 167 P-Term Total: 167 Total Pins: 59 - Total Nodes: 24 + Total Nodes: 19 Average P-Term/Output: 2 @@ -141,6 +131,10 @@ BERR = (0); BERR.OE = (!FPU_CS.Q); +DSACK_0_ = (1); + +DSACK_0_.OE = (!CPU_SPACE); + CLK_DIV_OUT.D = (inst_CLK_OUT_PRE.Q); CLK_DIV_OUT.C = (CLK_OSZI); @@ -151,10 +145,6 @@ AVEC_EXP = (0); AVEC_EXP.OE = (!FPU_CS.Q); -DSACK_0_ = (1); - -DSACK_0_.OE = (!CPU_SPACE); - AMIGA_BUS_ENABLE = (0); AMIGA_BUS_DATA_DIR = (!RW); @@ -165,8 +155,9 @@ CIIN = (A_23_ & A_22_ & A_21_ & A_20_); CIIN.OE = (!A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_); -IPL_030_2_.D = (IPL_2_ & inst_RISING_CLK_AMIGA.Q - # IPL_030_2_.Q & !inst_RISING_CLK_AMIGA.Q); +IPL_030_2_.D = (IPL_030_2_.Q & !inst_CLK_000_D.Q + # IPL_030_2_.Q & inst_CLK_000_DD.Q + # IPL_2_ & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q); IPL_030_2_.AP = (!RST); @@ -233,12 +224,28 @@ BG_000.AP = (!RST); BG_000.C = (CLK_OSZI); BGACK_030.D = (BGACK_000 & BGACK_030.Q - # BGACK_000 & inst_RISING_CLK_AMIGA.Q); + # BGACK_000 & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q); BGACK_030.AP = (!RST); BGACK_030.C = (CLK_OSZI); +IPL_030_1_.D = (IPL_030_1_.Q & !inst_CLK_000_D.Q + # IPL_030_1_.Q & inst_CLK_000_DD.Q + # IPL_1_ & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q); + +IPL_030_1_.AP = (!RST); + +IPL_030_1_.C = (CLK_OSZI); + +IPL_030_0_.D = (!inst_CLK_000_D.Q & IPL_030_0_.Q + # inst_CLK_000_DD.Q & IPL_030_0_.Q + # IPL_0_ & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q); + +IPL_030_0_.AP = (!RST); + +IPL_030_0_.C = (CLK_OSZI); + CLK_EXP.D = (inst_CLK_OUT_PRE.Q); CLK_EXP.C = (CLK_OSZI); @@ -250,13 +257,6 @@ FPU_CS.AP = (!RST); FPU_CS.C = (CLK_OSZI); -IPL_030_1_.D = (IPL_1_ & inst_RISING_CLK_AMIGA.Q - # IPL_030_1_.Q & !inst_RISING_CLK_AMIGA.Q); - -IPL_030_1_.AP = (!RST); - -IPL_030_1_.C = (CLK_OSZI); - DTACK.OE = (!BGACK_030.Q); !DTACK.D = (!AS_000.Q & !DSACK_1_.PIN); @@ -265,13 +265,6 @@ DTACK.AP = (!RST); DTACK.C = (CLK_OSZI); -IPL_030_0_.D = (IPL_0_ & inst_RISING_CLK_AMIGA.Q - # IPL_030_0_.Q & !inst_RISING_CLK_AMIGA.Q); - -IPL_030_0_.AP = (!RST); - -IPL_030_0_.C = (CLK_OSZI); - E.T = (E.Q & cpu_est_0_.Q & cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & cpu_est_2_.Q # !E.Q & cpu_est_0_.Q & cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & !cpu_est_2_.Q # !E.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & !cpu_est_2_.Q); @@ -280,7 +273,7 @@ E.C = (CLK_OSZI); VMA.AP = (!RST); -VMA.T = (!VMA.Q & !cpu_est_d_0_.Q & !cpu_est_d_3_.Q & AS_000.Q & inst_CLK_000_D.Q & cpu_est_d_1_.Q & cpu_est_d_2_.Q +VMA.T = (!E.Q & !VMA.Q & !cpu_est_0_.Q & cpu_est_1_.Q & AS_000.Q & inst_CLK_000_D.Q & cpu_est_2_.Q # !E.Q & VMA.Q & cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & !inst_CLK_000_D.Q & cpu_est_2_.Q); VMA.C = (CLK_OSZI); @@ -302,14 +295,6 @@ cpu_est_1_.T = (E.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_C cpu_est_1_.C = (CLK_OSZI); -cpu_est_d_0_.D = (cpu_est_0_.Q); - -cpu_est_d_0_.C = (CLK_OSZI); - -cpu_est_d_3_.D = (E.Q); - -cpu_est_d_3_.C = (CLK_OSZI); - inst_AS_030_000_SYNC.D = (AS_030 # CPU_SPACE & CLK_030 # !CLK_030 & inst_AS_030_000_SYNC.Q @@ -350,14 +335,6 @@ inst_CLK_OUT_PRE.D = (!inst_CLK_OUT_PRE.Q & CLK_CNT_0_.Q inst_CLK_OUT_PRE.C = (CLK_OSZI); -cpu_est_d_1_.D = (cpu_est_1_.Q); - -cpu_est_d_1_.C = (CLK_OSZI); - -cpu_est_d_2_.D = (cpu_est_2_.Q); - -cpu_est_d_2_.C = (CLK_OSZI); - cpu_est_2_.D.X1 = (E.Q & cpu_est_0_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & !cpu_est_2_.Q # !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & !cpu_est_2_.Q # !E.Q & cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & cpu_est_2_.Q); @@ -385,10 +362,6 @@ SM_AMIGA_7_.AP = (!RST); SM_AMIGA_7_.C = (CLK_OSZI); -inst_RISING_CLK_AMIGA.D = (CLK_000 & !inst_CLK_000_D.Q); - -inst_RISING_CLK_AMIGA.C = (CLK_OSZI); - SM_AMIGA_1_.AR = (!RST); SM_AMIGA_1_.D = (inst_CLK_000_D.Q & SM_AMIGA_1_.Q diff --git a/Logic/68030_tk.fti b/Logic/68030_tk.fti index bcb58ba..d0a5974 100644 --- a/Logic/68030_tk.fti +++ b/Logic/68030_tk.fti @@ -4,9 +4,9 @@ #DEVICE mach447a DATA LOCATION AMIGA_BUS_DATA_DIR:E_0_48 // OUT -DATA LOCATION AMIGA_BUS_ENABLE:D_2_34 // OUT +DATA LOCATION AMIGA_BUS_ENABLE:D_9_34 // OUT DATA LOCATION AMIGA_BUS_ENABLE_LOW:C_12_20 // OUT -DATA LOCATION AS_000:D_9_33 // IO {RN_AS_000} +DATA LOCATION AS_000:D_5_33 // IO {RN_AS_000} DATA LOCATION AS_030:H_*_82 // INP DATA LOCATION AVEC:A_4_92 // OUT DATA LOCATION AVEC_EXP:C_0_22 // OUT @@ -35,16 +35,16 @@ DATA LOCATION BG_030:C_*_21 // INP DATA LOCATION CIIN:E_12_47 // OUT DATA LOCATION CLK_000:*_*_11 // INP DATA LOCATION CLK_030:*_*_64 // INP -DATA LOCATION CLK_CNT_0_:G_14 // NOD +DATA LOCATION CLK_CNT_0_:H_6 // NOD DATA LOCATION CLK_DIV_OUT:G_0_65 // OUT DATA LOCATION CLK_EXP:B_0_10 // OUT DATA LOCATION CLK_OSZI:*_*_61 // Cin DATA LOCATION CPU_SPACE:*_*_14 // INP -DATA LOCATION DSACK_0_:H_1_80 // OUT -DATA LOCATION DSACK_1_:H_12_81 // IO {RN_DSACK_1_} +DATA LOCATION DSACK_0_:H_12_80 // OUT +DATA LOCATION DSACK_1_:H_8_81 // IO {RN_DSACK_1_} DATA LOCATION DS_030:A_*_98 // INP DATA LOCATION DTACK:D_0_30 // IO -DATA LOCATION E:G_2_66 // IO {RN_E} +DATA LOCATION E:G_4_66 // IO {RN_E} DATA LOCATION FC_0_:F_*_57 // INP DATA LOCATION FC_1_:F_*_58 // INP DATA LOCATION FPU_CS:H_0_78 // IO {RN_FPU_CS} @@ -56,48 +56,43 @@ DATA LOCATION IPL_1_:F_*_56 // INP DATA LOCATION IPL_2_:G_*_68 // INP DATA LOCATION LDS_000:D_8_31 // IO {RN_LDS_000} DATA LOCATION RESET:B_1_3 // OUT -DATA LOCATION RN_AS_000:D_9 // NOD {AS_000} +DATA LOCATION RN_AS_000:D_5 // NOD {AS_000} DATA LOCATION RN_BGACK_030:H_4 // NOD {BGACK_030} DATA LOCATION RN_BG_000:D_1 // NOD {BG_000} -DATA LOCATION RN_DSACK_1_:H_12 // NOD {DSACK_1_} -DATA LOCATION RN_E:G_2 // NOD {E} +DATA LOCATION RN_DSACK_1_:H_8 // NOD {DSACK_1_} +DATA LOCATION RN_E:G_4 // NOD {E} DATA LOCATION RN_FPU_CS:H_0 // NOD {FPU_CS} DATA LOCATION RN_IPL_030_0_:B_8 // NOD {IPL_030_0_} DATA LOCATION RN_IPL_030_1_:B_12 // NOD {IPL_030_1_} DATA LOCATION RN_IPL_030_2_:B_4 // NOD {IPL_030_2_} DATA LOCATION RN_LDS_000:D_8 // NOD {LDS_000} DATA LOCATION RN_UDS_000:D_12 // NOD {UDS_000} -DATA LOCATION RN_VMA:D_5 // NOD {VMA} +DATA LOCATION RN_VMA:D_4 // NOD {VMA} DATA LOCATION RST:*_*_86 // INP DATA LOCATION RW:G_*_71 // INP DATA LOCATION SIZE_0_:G_*_70 // INP DATA LOCATION SIZE_1_:H_*_79 // INP -DATA LOCATION SM_AMIGA_0_:G_13 // NOD -DATA LOCATION SM_AMIGA_1_:G_5 // NOD -DATA LOCATION SM_AMIGA_2_:G_10 // NOD -DATA LOCATION SM_AMIGA_3_:B_5 // NOD -DATA LOCATION SM_AMIGA_4_:D_13 // NOD -DATA LOCATION SM_AMIGA_5_:D_10 // NOD +DATA LOCATION SM_AMIGA_0_:H_13 // NOD +DATA LOCATION SM_AMIGA_1_:H_2 // NOD +DATA LOCATION SM_AMIGA_2_:G_8 // NOD +DATA LOCATION SM_AMIGA_3_:G_5 // NOD +DATA LOCATION SM_AMIGA_4_:G_12 // NOD +DATA LOCATION SM_AMIGA_5_:A_0 // NOD DATA LOCATION SM_AMIGA_6_:D_6 // NOD -DATA LOCATION SM_AMIGA_7_:G_9 // NOD +DATA LOCATION SM_AMIGA_7_:H_9 // NOD DATA LOCATION UDS_000:D_12_32 // IO {RN_UDS_000} -DATA LOCATION VMA:D_5_35 // IO {RN_VMA} +DATA LOCATION VMA:D_4_35 // IO {RN_VMA} DATA LOCATION VPA:*_*_36 // INP -DATA LOCATION cpu_est_0_:G_8 // NOD -DATA LOCATION cpu_est_1_:G_6 // NOD -DATA LOCATION cpu_est_2_:G_4 // NOD -DATA LOCATION cpu_est_d_0_:G_15 // NOD -DATA LOCATION cpu_est_d_1_:G_7 // NOD -DATA LOCATION cpu_est_d_2_:G_3 // NOD -DATA LOCATION cpu_est_d_3_:G_11 // NOD -DATA LOCATION inst_AS_030_000_SYNC:H_8 // NOD -DATA LOCATION inst_CLK_000_D:H_2 // NOD -DATA LOCATION inst_CLK_000_DD:H_13 // NOD -DATA LOCATION inst_CLK_OUT_PRE:G_12 // NOD -DATA LOCATION inst_DTACK_SYNC:B_9 // NOD -DATA LOCATION inst_RISING_CLK_AMIGA:H_9 // NOD +DATA LOCATION cpu_est_0_:D_14 // NOD +DATA LOCATION cpu_est_1_:D_2 // NOD +DATA LOCATION cpu_est_2_:D_10 // NOD +DATA LOCATION inst_AS_030_000_SYNC:F_0 // NOD +DATA LOCATION inst_CLK_000_D:H_1 // NOD +DATA LOCATION inst_CLK_000_DD:D_13 // NOD +DATA LOCATION inst_CLK_OUT_PRE:H_5 // NOD +DATA LOCATION inst_DTACK_SYNC:G_13 // NOD DATA LOCATION inst_VPA_D:G_1 // NOD -DATA LOCATION inst_VPA_SYNC:A_0 // NOD +DATA LOCATION inst_VPA_SYNC:G_9 // NOD DATA IO_DIR AMIGA_BUS_DATA_DIR:OUT DATA IO_DIR AMIGA_BUS_ENABLE:OUT DATA IO_DIR AMIGA_BUS_ENABLE_LOW:OUT @@ -158,40 +153,26 @@ DATA IO_DIR UDS_000:OUT DATA IO_DIR VMA:OUT DATA IO_DIR VPA:IN DATA GLB_CLOCK CLK_OSZI -DATA PW_LEVEL A_28_:0 -DATA SLEW A_28_:0 -DATA PW_LEVEL A_27_:0 -DATA SLEW A_27_:0 -DATA PW_LEVEL SIZE_1_:0 -DATA SLEW SIZE_1_:0 -DATA PW_LEVEL A_26_:0 -DATA SLEW A_26_:0 -DATA PW_LEVEL A_25_:0 -DATA SLEW A_25_:0 -DATA PW_LEVEL A_31_:0 -DATA SLEW A_31_:0 -DATA PW_LEVEL A_24_:0 -DATA SLEW A_24_:0 -DATA PW_LEVEL A_23_:0 -DATA SLEW A_23_:0 -DATA PW_LEVEL A_22_:0 -DATA SLEW A_22_:0 DATA PW_LEVEL A_21_:0 DATA SLEW A_21_:0 -DATA PW_LEVEL IPL_2_:0 -DATA SLEW IPL_2_:0 DATA PW_LEVEL A_20_:0 DATA SLEW A_20_:0 +DATA PW_LEVEL SIZE_1_:0 +DATA SLEW SIZE_1_:0 DATA PW_LEVEL A_19_:0 DATA SLEW A_19_:0 DATA PW_LEVEL A_18_:0 DATA SLEW A_18_:0 +DATA PW_LEVEL A_31_:0 +DATA SLEW A_31_:0 DATA PW_LEVEL A_17_:0 DATA SLEW A_17_:0 -DATA PW_LEVEL FC_1_:0 -DATA SLEW FC_1_:0 DATA PW_LEVEL A_16_:0 DATA SLEW A_16_:0 +DATA PW_LEVEL IPL_2_:0 +DATA SLEW IPL_2_:0 +DATA PW_LEVEL FC_1_:0 +DATA SLEW FC_1_:0 DATA PW_LEVEL AS_030:0 DATA SLEW AS_030:0 DATA PW_LEVEL DS_030:0 @@ -201,28 +182,28 @@ DATA PW_LEVEL BERR:0 DATA SLEW BERR:0 DATA PW_LEVEL BG_030:0 DATA SLEW BG_030:0 +DATA PW_LEVEL A_0_:0 +DATA SLEW A_0_:0 DATA PW_LEVEL BGACK_000:0 DATA SLEW BGACK_000:0 DATA SLEW CLK_030:0 -DATA SLEW CLK_000:0 -DATA SLEW CLK_OSZI:0 -DATA PW_LEVEL CLK_DIV_OUT:0 -DATA SLEW CLK_DIV_OUT:0 -DATA PW_LEVEL A_0_:0 -DATA SLEW A_0_:0 -DATA PW_LEVEL AVEC:0 -DATA SLEW AVEC:0 DATA PW_LEVEL IPL_1_:0 DATA SLEW IPL_1_:0 -DATA PW_LEVEL AVEC_EXP:0 -DATA SLEW AVEC_EXP:0 +DATA SLEW CLK_000:0 DATA PW_LEVEL IPL_0_:0 DATA SLEW IPL_0_:0 +DATA SLEW CLK_OSZI:0 DATA PW_LEVEL DSACK_0_:0 DATA SLEW DSACK_0_:0 -DATA SLEW VPA:0 +DATA PW_LEVEL CLK_DIV_OUT:0 +DATA SLEW CLK_DIV_OUT:0 DATA PW_LEVEL FC_0_:0 DATA SLEW FC_0_:0 +DATA PW_LEVEL AVEC:0 +DATA SLEW AVEC:0 +DATA PW_LEVEL AVEC_EXP:0 +DATA SLEW AVEC_EXP:0 +DATA SLEW VPA:0 DATA SLEW RST:0 DATA PW_LEVEL RW:0 DATA SLEW RW:0 @@ -240,6 +221,20 @@ DATA PW_LEVEL A_30_:0 DATA SLEW A_30_:0 DATA PW_LEVEL A_29_:0 DATA SLEW A_29_:0 +DATA PW_LEVEL A_28_:0 +DATA SLEW A_28_:0 +DATA PW_LEVEL A_27_:0 +DATA SLEW A_27_:0 +DATA PW_LEVEL A_26_:0 +DATA SLEW A_26_:0 +DATA PW_LEVEL A_25_:0 +DATA SLEW A_25_:0 +DATA PW_LEVEL A_24_:0 +DATA SLEW A_24_:0 +DATA PW_LEVEL A_23_:0 +DATA SLEW A_23_:0 +DATA PW_LEVEL A_22_:0 +DATA SLEW A_22_:0 DATA PW_LEVEL IPL_030_2_:0 DATA SLEW IPL_030_2_:0 DATA PW_LEVEL DSACK_1_:0 @@ -254,16 +249,16 @@ DATA PW_LEVEL BG_000:0 DATA SLEW BG_000:0 DATA PW_LEVEL BGACK_030:0 DATA SLEW BGACK_030:0 +DATA PW_LEVEL IPL_030_1_:0 +DATA SLEW IPL_030_1_:0 +DATA PW_LEVEL IPL_030_0_:0 +DATA SLEW IPL_030_0_:0 DATA PW_LEVEL CLK_EXP:0 DATA SLEW CLK_EXP:0 DATA PW_LEVEL FPU_CS:0 DATA SLEW FPU_CS:0 -DATA PW_LEVEL IPL_030_1_:0 -DATA SLEW IPL_030_1_:0 DATA PW_LEVEL DTACK:0 DATA SLEW DTACK:0 -DATA PW_LEVEL IPL_030_0_:0 -DATA SLEW IPL_030_0_:0 DATA PW_LEVEL E:0 DATA SLEW E:0 DATA PW_LEVEL VMA:0 @@ -274,10 +269,6 @@ DATA PW_LEVEL cpu_est_0_:0 DATA SLEW cpu_est_0_:0 DATA PW_LEVEL cpu_est_1_:0 DATA SLEW cpu_est_1_:0 -DATA PW_LEVEL cpu_est_d_0_:0 -DATA SLEW cpu_est_d_0_:0 -DATA PW_LEVEL cpu_est_d_3_:0 -DATA SLEW cpu_est_d_3_:0 DATA PW_LEVEL inst_AS_030_000_SYNC:0 DATA SLEW inst_AS_030_000_SYNC:0 DATA PW_LEVEL inst_DTACK_SYNC:0 @@ -292,10 +283,6 @@ DATA PW_LEVEL inst_CLK_000_DD:0 DATA SLEW inst_CLK_000_DD:0 DATA PW_LEVEL inst_CLK_OUT_PRE:0 DATA SLEW inst_CLK_OUT_PRE:0 -DATA PW_LEVEL cpu_est_d_1_:0 -DATA SLEW cpu_est_d_1_:0 -DATA PW_LEVEL cpu_est_d_2_:0 -DATA SLEW cpu_est_d_2_:0 DATA PW_LEVEL cpu_est_2_:0 DATA SLEW cpu_est_2_:0 DATA PW_LEVEL CLK_CNT_0_:0 @@ -304,8 +291,6 @@ DATA PW_LEVEL SM_AMIGA_6_:0 DATA SLEW SM_AMIGA_6_:0 DATA PW_LEVEL SM_AMIGA_7_:0 DATA SLEW SM_AMIGA_7_:0 -DATA PW_LEVEL inst_RISING_CLK_AMIGA:0 -DATA SLEW inst_RISING_CLK_AMIGA:0 DATA PW_LEVEL SM_AMIGA_1_:0 DATA SLEW SM_AMIGA_1_:0 DATA PW_LEVEL SM_AMIGA_4_:0 @@ -325,9 +310,9 @@ DATA PW_LEVEL RN_UDS_000:0 DATA PW_LEVEL RN_LDS_000:0 DATA PW_LEVEL RN_BG_000:0 DATA PW_LEVEL RN_BGACK_030:0 -DATA PW_LEVEL RN_FPU_CS:0 DATA PW_LEVEL RN_IPL_030_1_:0 DATA PW_LEVEL RN_IPL_030_0_:0 +DATA PW_LEVEL RN_FPU_CS:0 DATA PW_LEVEL RN_E:0 DATA PW_LEVEL RN_VMA:0 END diff --git a/Logic/68030_tk.grp b/Logic/68030_tk.grp index 5912e58..b276e9a 100644 --- a/Logic/68030_tk.grp +++ b/Logic/68030_tk.grp @@ -1,15 +1,15 @@ -GROUP MACH_SEG_A inst_VPA_SYNC AVEC -GROUP MACH_SEG_B inst_DTACK_SYNC SM_AMIGA_3_ IPL_030_1_ RN_IPL_030_1_ IPL_030_0_ - RN_IPL_030_0_ IPL_030_2_ RN_IPL_030_2_ CLK_EXP RESET +GROUP MACH_SEG_A SM_AMIGA_5_ AVEC +GROUP MACH_SEG_B IPL_030_1_ RN_IPL_030_1_ IPL_030_0_ RN_IPL_030_0_ IPL_030_2_ + RN_IPL_030_2_ CLK_EXP RESET GROUP MACH_SEG_C AVEC_EXP AMIGA_BUS_ENABLE_LOW -GROUP MACH_SEG_D LDS_000 RN_LDS_000 VMA RN_VMA UDS_000 RN_UDS_000 BG_000 - RN_BG_000 AS_000 RN_AS_000 SM_AMIGA_5_ SM_AMIGA_6_ SM_AMIGA_4_ DTACK - AMIGA_BUS_ENABLE +GROUP MACH_SEG_D LDS_000 RN_LDS_000 UDS_000 RN_UDS_000 VMA RN_VMA BG_000 + RN_BG_000 AS_000 RN_AS_000 cpu_est_1_ cpu_est_2_ SM_AMIGA_6_ DTACK + cpu_est_0_ inst_CLK_000_DD AMIGA_BUS_ENABLE GROUP MACH_SEG_E CIIN BERR AMIGA_BUS_DATA_DIR -GROUP MACH_SEG_G E RN_E cpu_est_1_ cpu_est_2_ SM_AMIGA_2_ SM_AMIGA_0_ SM_AMIGA_7_ - SM_AMIGA_1_ cpu_est_0_ inst_CLK_OUT_PRE inst_VPA_D CLK_CNT_0_ CLK_DIV_OUT - cpu_est_d_3_ cpu_est_d_1_ cpu_est_d_2_ cpu_est_d_0_ -GROUP MACH_SEG_H inst_AS_030_000_SYNC FPU_CS RN_FPU_CS DSACK_1_ RN_DSACK_1_ - BGACK_030 RN_BGACK_030 inst_RISING_CLK_AMIGA inst_CLK_000_D inst_CLK_000_DD - DSACK_0_ \ No newline at end of file +GROUP MACH_SEG_F inst_AS_030_000_SYNC +GROUP MACH_SEG_G inst_VPA_SYNC inst_DTACK_SYNC E RN_E SM_AMIGA_2_ SM_AMIGA_3_ + SM_AMIGA_4_ inst_VPA_D CLK_DIV_OUT +GROUP MACH_SEG_H FPU_CS RN_FPU_CS DSACK_1_ RN_DSACK_1_ SM_AMIGA_0_ SM_AMIGA_7_ + SM_AMIGA_1_ BGACK_030 RN_BGACK_030 inst_CLK_OUT_PRE inst_CLK_000_D + CLK_CNT_0_ DSACK_0_ \ No newline at end of file diff --git a/Logic/68030_tk.ipr b/Logic/68030_tk.ipr index 91e36a6..3d93bb9 100644 --- a/Logic/68030_tk.ipr +++ b/Logic/68030_tk.ipr @@ -1 +1 @@ -4016<466m'D+v_ \ No newline at end of file +6754<46>b[ðb4 \ No newline at end of file diff --git a/Logic/68030_tk.jed b/Logic/68030_tk.jed index d1d7b73..af54237 100644 --- a/Logic/68030_tk.jed +++ b/Logic/68030_tk.jed @@ -10,7 +10,7 @@ AUTHOR: PATTERN: COMPANY: REVISION: -DATE: Thu May 15 22:21:57 2014 +DATE: Thu May 15 23:02:50 2014 ABEL mach447a * @@ -31,46 +31,44 @@ NOTE Spread Placement? Y * NOTE Run Time Upper Bound in 15 minutes 0 * NOTE Zero Hold Time For Input Registers? Y * NOTE Table of pin names and numbers* -NOTE PINS A_28_:15 A_27_:16 SIZE_1_:79 A_26_:17 A_25_:18* -NOTE PINS A_31_:4 A_24_:19 A_23_:84 A_22_:85 A_21_:94 IPL_2_:68* -NOTE PINS A_20_:93 A_19_:97 A_18_:95 A_17_:59 FC_1_:58 A_16_:96* -NOTE PINS AS_030:82 DS_030:98 CPU_SPACE:14 BERR:41 BG_030:21* -NOTE PINS BGACK_000:28 CLK_030:64 CLK_000:11 CLK_OSZI:61* -NOTE PINS CLK_DIV_OUT:65 A_0_:69 AVEC:92 IPL_1_:56 AVEC_EXP:22* -NOTE PINS IPL_0_:67 DSACK_0_:80 VPA:36 FC_0_:57 RST:86 RW:71* -NOTE PINS AMIGA_BUS_ENABLE:34 AMIGA_BUS_DATA_DIR:48 AMIGA_BUS_ENABLE_LOW:20* -NOTE PINS CIIN:47 SIZE_0_:70 A_30_:5 A_29_:6 IPL_030_2_:9* +NOTE PINS A_21_:94 A_20_:93 SIZE_1_:79 A_19_:97 A_18_:95* +NOTE PINS A_31_:4 A_17_:59 A_16_:96 IPL_2_:68 FC_1_:58 AS_030:82* +NOTE PINS DS_030:98 CPU_SPACE:14 BERR:41 BG_030:21 A_0_:69* +NOTE PINS BGACK_000:28 CLK_030:64 IPL_1_:56 CLK_000:11 IPL_0_:67* +NOTE PINS CLK_OSZI:61 DSACK_0_:80 CLK_DIV_OUT:65 FC_0_:57* +NOTE PINS AVEC:92 AVEC_EXP:22 VPA:36 RST:86 RW:71 AMIGA_BUS_ENABLE:34* +NOTE PINS AMIGA_BUS_DATA_DIR:48 AMIGA_BUS_ENABLE_LOW:20 CIIN:47* +NOTE PINS SIZE_0_:70 A_30_:5 A_29_:6 A_28_:15 A_27_:16 A_26_:17* +NOTE PINS A_25_:18 A_24_:19 A_23_:84 A_22_:85 IPL_030_2_:9* NOTE PINS DSACK_1_:81 AS_000:33 UDS_000:32 LDS_000:31 BG_000:29* -NOTE PINS BGACK_030:83 CLK_EXP:10 FPU_CS:78 IPL_030_1_:7* -NOTE PINS DTACK:30 IPL_030_0_:8 E:66 VMA:35 RESET:3 * +NOTE PINS BGACK_030:83 IPL_030_1_:7 IPL_030_0_:8 CLK_EXP:10* +NOTE PINS FPU_CS:78 DTACK:30 E:66 VMA:35 RESET:3 * NOTE Table of node names and numbers* -NOTE NODES RN_IPL_030_2_:131 RN_DSACK_1_:287 RN_AS_000:187 * +NOTE NODES RN_IPL_030_2_:131 RN_DSACK_1_:281 RN_AS_000:181 * NOTE NODES RN_UDS_000:191 RN_LDS_000:185 RN_BG_000:175 RN_BGACK_030:275 * -NOTE NODES RN_FPU_CS:269 RN_IPL_030_1_:143 RN_DTACK:173 * -NOTE NODES RN_IPL_030_0_:137 RN_E:248 RN_VMA:181 cpu_est_0_:257 * -NOTE NODES cpu_est_1_:254 cpu_est_d_0_:268 cpu_est_d_3_:262 * -NOTE NODES inst_AS_030_000_SYNC:281 inst_DTACK_SYNC:139 * -NOTE NODES inst_VPA_D:247 inst_VPA_SYNC:101 inst_CLK_000_D:272 * -NOTE NODES inst_CLK_000_DD:289 inst_CLK_OUT_PRE:263 cpu_est_d_1_:256 * -NOTE NODES cpu_est_d_2_:250 cpu_est_2_:251 CLK_CNT_0_:266 * -NOTE NODES SM_AMIGA_6_:182 SM_AMIGA_7_:259 inst_RISING_CLK_AMIGA:283 * -NOTE NODES SM_AMIGA_1_:253 SM_AMIGA_4_:193 SM_AMIGA_3_:133 * -NOTE NODES SM_AMIGA_5_:188 SM_AMIGA_2_:260 SM_AMIGA_0_:265 * +NOTE NODES RN_IPL_030_1_:143 RN_IPL_030_0_:137 RN_FPU_CS:269 * +NOTE NODES RN_DTACK:173 RN_E:251 RN_VMA:179 cpu_est_0_:194 * +NOTE NODES cpu_est_1_:176 inst_AS_030_000_SYNC:221 inst_DTACK_SYNC:265 * +NOTE NODES inst_VPA_D:247 inst_VPA_SYNC:259 inst_CLK_000_D:271 * +NOTE NODES inst_CLK_000_DD:193 inst_CLK_OUT_PRE:277 cpu_est_2_:188 * +NOTE NODES CLK_CNT_0_:278 SM_AMIGA_6_:182 SM_AMIGA_7_:283 * +NOTE NODES SM_AMIGA_1_:272 SM_AMIGA_4_:263 SM_AMIGA_3_:253 * +NOTE NODES SM_AMIGA_5_:101 SM_AMIGA_2_:257 SM_AMIGA_0_:289 * NOTE BLOCK 0 * L000000 111111111111111111111111111111111111111111111111111111111111111111 111111111011111111111111111111111111111111111111111111111111111111 - 111111111110111111111011111111111111111111111111111111110111111111 - 111110111111111111111111111111111111111111111110111111111111111111 - 111111111111111111111111111111111111111111111111101111111111111111 111111111111111111111111111111111111111111111111111111111111111111 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111110111101111111111111111111111111111111111111111111111 - 101111111111111111111111111110011111111111111111111111111111111111* + 111111111110111111111111111111111111111111111111111111111111111111 + 110111111111111111111111111111111111111111111111111111111111111111 + 111111111111111111111111111111111111111111111111111111111111111111 + 111111111111111111111111111111110111111111111111111111111111111111 + 101111111111111111111011111111011111111111111111111111111111111111* L000594 000000000000000000000000000000000000000000000000000000000000000000* -L000660 111111111111111111101111111111101111111111111111111111111111111111* -L000726 111101111110111011111011111101111111111111111101101111110111111111* +L000660 111011111110111111110111111111110111111111111111111111111111111111* +L000726 111111111111111111110111111111011111111111111111111111111111111111* L000792 000000000000000000000000000000000000000000000000000000000000000000* L000858 000000000000000000000000000000000000000000000000000000000000000000* L000924 000000000000000000000000000000000000000000000000000000000000000000* @@ -164,10 +162,10 @@ L006204 111111111111111111111111111111111111111111111111111111111111111111* L006270 111111111111111111111111111111111111111111111111111111111111111111* L006336 111111111111111111111111111111111111111111111111111111111111111111* L006402 - 000000000000000000000000000000000000000000000000000000000000000000 - 101111111111111111111111111111111111111111111111111111111111111111* + 101111111111111111111111111111111111111111111111111111111111111111 + 000000000000000000000000000000000000000000000000000000000000000000* L006534 0010* -L006538 11100110010000* +L006538 10100110010000* L006552 11011011111110* L006566 11110011110101* L006580 11110111111111* @@ -185,18 +183,18 @@ L006734 11110111110001* L006748 11111111110011* NOTE BLOCK 1 * L006762 - 111111111111111011111111011111111111111111111111111111111111111111 - 111111111111011111111111111111111111111111111111111111111110111111 - 111111101011111101111111111111111111111111111111111111110111111111 + 111111111111111111111111011111111111111111111111111111111111111111 + 111111111111111111111111111111111111111111111111111111111110111111 + 111111101011111101111111111111111111111111111111111111111111111111 101111111111111111111111111111111111111111111111111111011111111111 - 111111111111111111111111111111111111111111111111101111111111111111 + 111111111111111111111111111111111111111111111111111111111111111111 110111111111111111111111111111111111111111111111111111111111111111 - 111111111110111111111111111111111111111111111101111111111111111111 - 111111111111111111101111111111111111111111111111111111111111111111 - 111111111111111111111111111110011111111111101111111111111111111111* + 111111111111111111111111111111111111111111111111111111111111111111 + 111111111111111111111111111011111111111111111111111111111111111111 + 111111111111111111111011111111111111111111101111111111111111111111* L007356 111111111111111111111111111111111111111111111111111111111111111111* -L007422 111111111111110111111111111111111111111111111111111111111111111111* +L007422 111111111111111111111111110111111111111111111111111111111111111111* L007488 111111111111111111111111111111111111111111111111111111111101111111* L007554 000000000000000000000000000000000000000000000000000000000000000000* L007620 000000000000000000000000000000000000000000000000000000000000000000* @@ -220,16 +218,16 @@ L008676 111111111111111111111111111111111111111111111111111111111111111111* L008742 111111111111111111111111111111111111111111111111111111111111111111* L008808 111111111111111111111111111111111111111111111111111111111111111111* -L008874 111111110101111111111111111111111111111111111111111111111111111111* -L008940 111111111110111111111111111111111111111111111111111111011111111111* -L009006 000000000000000000000000000000000000000000000000000000000000000000* +L008874 111111111111111111111011111111111111111111111111111111011111111111* +L008940 110111111111111111111111111111111111111111111111111111011111111111* +L009006 111011110111111111110111111111111111111111111111111111111111111111* L009072 000000000000000000000000000000000000000000000000000000000000000000* L009138 000000000000000000000000000000000000000000000000000000000000000000* -L009204 110111111111111111111111111101111111111111111111111111111111111111* -L009270 111111111111011111111111111111011111111111111111111111110111111111* -L009336 111111111111111111111111111101111111111111111111111111110111111111* -L009402 000000000000000000000000000000000000000000000000000000000000000000* -L009468 000000000000000000000000000000000000000000000000000000000000000000* +L009204 111111111111111111111111111111111111111111111111111111111111111111* +L009270 111111111111111111111111111111111111111111111111111111111111111111* +L009336 111111111111111111111111111111111111111111111111111111111111111111* +L009402 111111111111111111111111111111111111111111111111111111111111111111* +L009468 111111111111111111111111111111111111111111111111111111111111111111* L009534 111111111111111111111111111111111111111111111111111111111111111111* L009600 111111111111111111111111111111111111111111111111111111111111111111* @@ -244,16 +242,16 @@ L010128 111111111111111111111111111111111111111111111111111111111111111111* L010194 111111111111111111111111111111111111111111111111111111111111111111* L010260 000000000000000000000000000000000000000000000000000000000000000000* -L010326 011111111101111111111111111111111111111111111111111111111111111111* -L010392 111111111110111101111111111111111111111111111111111111111111111111* -L010458 000000000000000000000000000000000000000000000000000000000000000000* +L010326 011011111111111111110111111111111111111111111111111111111111111111* +L010392 111111111111111101111011111111111111111111111111111111111111111111* +L010458 110111111111111101111111111111111111111111111111111111111111111111* L010524 000000000000000000000000000000000000000000000000000000000000000000* L010590 000000000000000000000000000000000000000000000000000000000000000000* -L010656 111111111111101111101111111111111111111111111111111111111111111111* -L010722 111111111111111111111111111101111111111111111110011111110111111111* -L010788 000000000000000000000000000000000000000000000000000000000000000000* -L010854 000000000000000000000000000000000000000000000000000000000000000000* -L010920 000000000000000000000000000000000000000000000000000000000000000000* +L010656 111111111111111111111111111111111111111111111111111111111111111111* +L010722 111111111111111111111111111111111111111111111111111111111111111111* +L010788 111111111111111111111111111111111111111111111111111111111111111111* +L010854 111111111111111111111111111111111111111111111111111111111111111111* +L010920 111111111111111111111111111111111111111111111111111111111111111111* L010986 000000000000000000000000000000000000000000000000000000000000000000* L011052 111111111111111111111111111111111111111111111111111111111111111111* @@ -268,9 +266,9 @@ L011580 111111111111111111111111111111111111111111111111111111111111111111* L011646 111111111111111111111111111111111111111111111111111111111111111111* L011712 000000000000000000000000000000000000000000000000000000000000000000* -L011778 111111011101111111111111111111111111111111111111111111111111111111* -L011844 111111111110111111111111011111111111111111111111111111111111111111* -L011910 000000000000000000000000000000000000000000000000000000000000000000* +L011778 111111111111111111111011011111111111111111111111111111111111111111* +L011844 110111111111111111111111011111111111111111111111111111111111111111* +L011910 111011011111111111110111111111111111111111111111111111111111111111* L011976 000000000000000000000000000000000000000000000000000000000000000000* L012042 000000000000000000000000000000000000000000000000000000000000000000* L012108 111111111111111111111111111111111111111111111111111111111111111111* @@ -299,15 +297,15 @@ L013314 00011110001110* L013328 11011111110100* L013342 11111011111111* L013356 10100110010010* -L013370 10100100011110* -L013384 11011111110111* -L013398 11111011111111* +L013370 11001011111110* +L013384 11110011110111* +L013398 11110111111111* L013412 10100110011000* -L013426 11100110010010* -L013440 11010011110000* -L013454 11111011110011* +L013426 11000011110010* +L013440 11111011110001* +L013454 11110111110011* L013468 10100110011000* -L013482 11001111110010* +L013482 11001111110011* L013496 11110011111101* L013510 11111011111111* NOTE BLOCK 2 * @@ -439,106 +437,106 @@ L020258 11110111110101* L020272 11111111111111* NOTE BLOCK 3 * L020286 - 111111111111111111111111111111111111101111111111111111111011111111 - 111111111111111110101111111110011111111111110111111111101111111111 - 101111111111111111111111111011111111111111111111111110111110111111 - 111110111111111111111111111111111111111111111111111111111111101011 - 111111111111111111111111011111111111111111111111101111111111111111 - 110111111101101011111111111111111111111101111111111111111111111111 - 111111101111111111111011111111111111111111111111110111111111111101 - 111111111111111111111101111111110111111011111110111111111111111111 - 111111111011111111111111111111111101111111101111111111111111111111* + 111111111111111111111111111110111111111111111111111111111011111111 + 101111111111111110111111111111011111111111110111111111111110111111 + 111111111111111111111111111111111111101111111111111111111111111111 + 111110111111111111111111111111111111111111111111111111111111111111 + 111111111001111111110111111111111111111111111111111011111111111111 + 110111111111101111111101111111111111111101111111111111111111111111 + 111111111111111111111111111111110111111111111111111111101111111110 + 111111111111110111101111111111111111111111011110111111111111011111 + 111111011111111111111111101111111101111111111111101111111111111111* L020880 111111111111111111111111111111111111111111111111111111111111111111* -L020946 111111111111111111111011111111111111111111111111111011111111111111* +L020946 111111111111111011111111111111111111111111111111111111111111111110* L021012 000000000000000000000000000000000000000000000000000000000000000000* L021078 000000000000000000000000000000000000000000000000000000000000000000* L021144 000000000000000000000000000000000000000000000000000000000000000000* L021210 000000000000000000000000000000000000000000000000000000000000000000* -L021276 111111111111111111111111111111100111110111111011111111111011111111* -L021342 111111111111111111111111111111101111110111111011111111011011111111* -L021408 111111111111111111111111111111111110111111111011111111110111111111* -L021474 000000000000000000000000000000000000000000000000000000000000000000* +L021276 111001101111111111111011011111111111111111111111111111111111111111* +L021342 111010111111111111110111011111111111111101111111111111111111111111* +L021408 111001011111111111110111011111111111111110111111111111111111111111* +L021474 111010101111111111111111011111111111111110111111111111111111111111* L021540 000000000000000000000000000000000000000000000000000000000000000000* L021606 111111111111111111111111111111111111111111111111111111111111111111* -L021672 000000000000000000000000000000000000000000000000000000000000000000* -L021738 111111111111111111111111111111111111111111111111111111111111111111* -L021804 111111111111111111111111111111111111111111111111111111111111111111* -L021870 111111111111111111111111111111111111111111111111111111111111111111* -L021936 111111111111111111111111111111111111111111111111111111111111111111* -L022002 111111111111111111111111111111111111111111111111111111111111111111* -L022068 111111111111111111111111111111111111111111111111111111111111111111* -L022134 111111111111111111111111111111111111111111111111111111111111111111* -L022200 111111111111111111111111111111111111111111111111111111111111111111* -L022266 111111111111111111111111111111111111111111111111111111111111111111* +L021672 111111111111111111011111111111101111111111111011111111111011011111* +L021738 111111111111111111111111111111111111111111111111111111111101111111* +L021804 000000000000000000000000000000000000000000000000000000000000000000* +L021870 111111111111111111011111111111101111111111111011111111011011111111* +L021936 111111111111111111111111111111111110111111111011111111110111111111* +L022002 111110011111110111111011011111111111111101101111111111111111111111* +L022068 111110101011111111110111101111111111111101011111111111111111111111* +L022134 000000000000000000000000000000000000000000000000000000000000000000* +L022200 000000000000000000000000000000000000000000000000000000000000000000* +L022266 000000000000000000000000000000000000000000000000000000000000000000* L022332 111111111111111111111111111111111111111111111101111111111111111111* -L022398 111111111111111111111111111111111111111111111111111111111111111111* -L022464 111111111111111111111111111111111111111111111111111111111111111111* -L022530 111111111111111111111111111111111111111111111111111111111111111111* -L022596 111111111111111111111111111111111111111111111111111111111111111111* -L022662 111111111111111111111111111111111111111111111111111111111111111111* -L022728 111111110111111111101110111111111111101111111111110101111111011111* -L022794 111101111011111111111101110111111111111111111111101111111110111011* -L022860 000000000000000000000000000000000000000000000000000000000000000000* +L022398 111111111111111011101111111111111111111111111111111111111111111111* +L022464 111011111111111111111111011111111111111111111111111011111111011111* +L022530 000000000000000000000000000000000000000000000000000000000000000000* +L022596 000000000000000000000000000000000000000000000000000000000000000000* +L022662 000000000000000000000000000000000000000000000000000000000000000000* +L022728 111011111111111111111111011111111111111111111111111011111111111111* +L022794 111111111111111111111111011111111111111111111111111111111111101111* +L022860 111111111111111111111111111111111111111111111111111111101111101111* L022926 000000000000000000000000000000000000000000000000000000000000000000* L022992 000000000000000000000000000000000000000000000000000000000000000000* L023058 111111111111111111111111111111111111111111111101111111111111111111* -L023124 111111100111111011111111111111111111111111111111111111111111111111* -L023190 111111110111111111111111111111111011111111111111111111111111111111* -L023256 111111111111111111111111111111111011111111111111111111101111111111* -L023322 000000000000000000000000000000000000000000000000000000000000000000* -L023388 000000000000000000000000000000000000000000000000000000000000000000* -L023454 111111100111011001111111101111110111111111111111111111111111111111* -L023520 111111100111111001111111101110110111111111111111111111111111111111* -L023586 011111100111111001111111101111110111111111111111111111111111111111* -L023652 111111111111111111111111011111111111111011111111111111111111111110* -L023718 111111011111111101111111111111111111111011111111111111111111111110* +L023124 111111111111111111111111111111111111111111111111111111111111111111* +L023190 111111111111111111111111111111111111111111111111111111111111111111* +L023256 111111111111111111111111111111111111111111111111111111111111111111* +L023322 111111111111111111111111111111111111111111111111111111111111111111* +L023388 111111111111111111111111111111111111111111111111111111111111111111* +L023454 111011111110011101111111011111111111111111111111111011111111011111* +L023520 101011111110111101111111011111111111111111111111111011111111011111* +L023586 111011111110111101111111011111111111011111111111111011111111011111* +L023652 111111111101111111101111111111111011111111111111111111111111111111* +L023718 111111111111111101101111111111111011111111111111110111111111111111* L023784 111111111111111111111111111111111111111111111101111111111111111111* -L023850 111111111011111111111111111111111111111011111111111111111111111110* -L023916 111111111111110101111111111111111111111011111111111111111111111110* -L023982 111111111111111101111111111111111011111011111111111111111111111110* -L024048 110111110111011110111111101111111111111111111111111111111111111111* -L024114 110111110111111110111111101110111111111111111111111111111111111111* -L024180 010111110111111110111111101111111111111111111111111111111111111111* -L024246 111011111111111110111111111111111111111011111111111111111111111110* -L024312 000000000000000000000000000000000000000000000000000000000000000000* -L024378 000000000000000000000000000000000000000000000000000000000000000000* +L023850 111111111111111111101111101111111011111111111111111111111111111111* +L023916 110111111111111101101111111111111011111111111111111111111111111111* +L023982 111111111111111101101111111111111011111111111111111111111111101111* +L024048 111111111110011110111111011101111111111111111111111111111111111111* +L024114 101111111110111110111111011101111111111111111111111111111111111111* +L024180 000000000000000000000000000000000000000000000000000000000000000000* +L024246 111001111111111111110111011111111111111110111111111111111111111111* +L024312 111011101111111111111011011111111111111110111111111111111111111111* +L024378 111010101111111111110111011111111111111101111111111111111111111111* L024444 000000000000000000000000000000000000000000000000000000000000000000* L024510 111111111111111111111111111111111111111111111110111111111111111111* -L024576 111111100111111011111111111111110111111111111111111111111111111111* -L024642 111111110111111111111111111111111111111101111111111111111111111111* +L024576 111111111111111111111111111111111111111101111111111111111111111111* +L024642 111111111111111111111111111111111111111111111111111111111101111111* L024708 000000000000000000000000000000000000000000000000000000000000000000* -L024774 000000000000000000000000000000000000000000000000000000000000000000* -L024840 000000000000000000000000000000000000000000000000000000000000000000* -L024906 111111111111111111111111111111111111111011111111111011111111111111* -L024972 111111100111111011111111111111110111111111111111111111111111111111* -L025038 000000000000000000000000000000000000000000000000000000000000000000* -L025104 000000000000000000000000000000000000000000000000000000000000000000* -L025170 000000000000000000000000000000000000000000000000000000000000000000* +L024774 111111111110111110111111011101111111011111111111111111111111111111* +L024840 111111111111111110101111111110111011111111111111111111111111111111* +L024906 111011111110111101111111011111111111101111111111111011111111011111* +L024972 111111111101111111101110111111111111111111111111111111111111111111* +L025038 111111111111111101101110111111111111111111111111110111111111111111* +L025104 111111111111111111101110101111111111111111111111111111111111111111* +L025170 110111111111111101101110111111111111111111111111111111111111111111* L025236 111111111111111111111111111111111111111111111111111111111111111111* -L025302 101111100111111001111111101111110111111111111111111111111111111111* -L025368 111111111110111111111111011111111111111011111111111111111111111111* -L025434 111111011110111101111111111111111111111011111111111111111111111111* -L025500 111111111010111111111111111111111111111011111111111111111111111111* -L025566 111111111110110101111111111111111111111011111111111111111111111111* -L025632 110111111011111111111111111111111111111111111111111111111111111111* -L025698 111111111011111111111111111111111111111101111111111111111111111111* +L025302 111111111111111101101110111111111111111111111111111111111111101111* +L025368 111111111110111110111111011101111111101111111111111111111111111111* +L025434 111111111111111110101110111110111111111111111111111111111111111111* +L025500 000000000000000000000000000000000000000000000000000000000000000000* +L025566 000000000000000000000000000000000000000000000000000000000000000000* +L025632 111111111111111111111111011111111111111111111111111111111111111111* +L025698 111111111111111111111111111111111111111111111111111111111101111111* L025764 000000000000000000000000000000000000000000000000000000000000000000* L025830 000000000000000000000000000000000000000000000000000000000000000000* L025896 000000000000000000000000000000000000000000000000000000000000000000* L025962 000000000000000000000000000000000000000000000000000000000000000000* -L026028 111111111110111101111111111111111011111011111111111111111111111111* -L026094 100111110111111110111111101111111111111111111111111111111111111111* -L026160 111011111110111110111111111111111111111011111111111111111111111111* -L026226 000000000000000000000000000000000000000000000000000000000000000000* -L026292 000000000000000000000000000000000000000000000000000000000000000000* +L026028 111111111111111111110111101111111111111111111111111111111111111111* +L026094 111111111111111111111111111111111111111111111111111111111101111111* +L026160 000000000000000000000000000000000000000000000000000000000000000000* +L026226 110111111111111111110111111111111111111111111111111111111111111111* +L026292 111011111111111111111011011111111111111111111111111111111111111111* L026358 111111111111111111111111111111111111111111111111111111111111111111* L026424 111111111111111111111111111111111111111111111111111111111111111111* L026490 111111111111111111111111111111111111111111111111111111111111111111* @@ -546,24 +544,24 @@ L026556 111111111111111111111111111111111111111111111111111111111111111111* L026622 111111111111111111111111111111111111111111111111111111111111111111* L026688 000000000000000000000000000000000000000000000000000000000000000000 - 111111111111111111111111111111111111111111101111111111111111111111* + 111111111111111111111111111111111111111111111111101111111111111111* L026820 0010* -L026824 01100110011010* -L026838 11100110011110* -L026852 00011111110000* -L026866 11011011111111* -L026880 11110011111010* -L026894 10100111011110* -L026908 11100100010111* -L026922 11011011111111* -L026936 11100110010000* -L026950 11110110011111* -L026964 10100100010111* -L026978 11000011110011* +L026824 01100110010010* +L026838 11010110011110* +L026852 10111111001110* +L026866 11010011111111* +L026880 10010111011001* +L026894 11010110011111* +L026908 11010100010110* +L026922 11011111111111* +L026936 11100110010001* +L026950 00011011111111* +L026964 00001110000110* +L026978 11011111110010* L026992 11100110011010* -L027006 10100100011110* -L027020 11001011110001* -L027034 11111111110011* +L027006 00111110001111* +L027020 10101110000000* +L027034 11100011110010* NOTE BLOCK 4 * L027048 111111111111111111111111111111111111111111111111111111111111111111 @@ -693,22 +691,22 @@ L033782 11110111110101* L033796 11111111111111* NOTE BLOCK 5 * L033810 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111* + 111111111111111111111111111111111111111110111111111111111111111111 + 111111111101111111111111111111111111111111111111111111111111111111 + 111111111111101111111111111111111111111111111111111111111111111111 + 111011111111111110111111111111111111111111111111111111111111111111 + 111111111111111111111111111111111111111111111111111011111111111111 + 111111110111111111111111011111111111111111111111111111111111111111 + 111111111111111111111101111111111101111111111111111111111111111111 + 111111111111111111101111111111111111111111111111111111111111111111 + 101111111111111111111111111111111111111111111111111111111111111111* L034404 000000000000000000000000000000000000000000000000000000000000000000* -L034470 111111111111111111111111111111111111111111111111111111111111111111* -L034536 111111111111111111111111111111111111111111111111111111111111111111* -L034602 111111111111111111111111111111111111111111111111111111111111111111* -L034668 111111111111111111111111111111111111111111111111111111111111111111* -L034734 111111111111111111111111111111111111111111111111111111111111111111* +L034470 111111111111111111011111111111111111111111111111111111111111111111* +L034536 111111111101111111111111111111111111111101111111111111111111111111* +L034602 110111110111011101111110101111111110111101111111111111111111111111* +L034668 111111111111111111111111111111111111111110111111110111111111111111* +L034734 000000000000000000000000000000000000000000000000000000000000000000* L034800 111111111111111111111111111111111111111111111111111111111111111111* L034866 111111111111111111111111111111111111111111111111111111111111111111* L034932 111111111111111111111111111111111111111111111111111111111111111111* @@ -800,10 +798,10 @@ L040080 111111111111111111111111111111111111111111111111111111111111111111* L040146 111111111111111111111111111111111111111111111111111111111111111111* L040212 000000000000000000000000000000000000000000000000000000000000000000 - 000000000000000000000000000000000000000000000000000000000000000000* -L040344 0000* -L040348 11010011111110* -L040362 11110111111111* + 101111111111111111111111111111111111111111111111111111111111111111* +L040344 0010* +L040348 10100110011110* +L040362 11011011111110* L040376 11110011111111* L040390 11110111110011* L040404 11110011111110* @@ -820,161 +818,161 @@ L040544 11110111111111* L040558 11111111111111* NOTE BLOCK 6 * L040572 - 111111111111111111101110111110111111111111111111111111111111111111 - 111111111110011111111111101111111111111111101111111111111111111111 - 111111111111111111111111111011111111111111111111111111110110111111 - 111110101111111111111111111111111111111111111110111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111011111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111110111111111111111 - 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111111111111111111111111111111111111111111111111111111111111111111* -L041958 111101110111111011111111110111111111111111111101111111111101111111* -L042024 111110110111111011111111110111111111111111111110111111111101111111* -L042090 111110110111111011111111111011111111111111111110111111111110111111* -L042156 000000000000000000000000000000000000000000000000000000000000000000* -L042222 000000000000000000000000000000000000000000000000000000000000000000* -L042288 111101111111111111111111111111111111111111111111111111111111111111* -L042354 000000000000000000000000000000000000000000000000000000000000000000* -L042420 000000000000000000000000000000000000000000000000000000000000000000* -L042486 000000000000000000000000000000000000000000000000000000000000000000* -L042552 000000000000000000000000000000000000000000000000000000000000000000* +L041958 111111111111111111111111111111111111111111111111111111111111111111* +L042024 111111111111111111111111111111111111111111111111111111111111111111* +L042090 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11110111111111* -L054040 11100110011000* -L054054 00001110000011* -L054068 11011111110100* -L054082 11110011111110* +L053872 11100110011000* +L053886 00101110000010* +L053900 10100100010000* +L053914 11100011110011* +L053928 10100110010001* +L053942 10101110001111* +L053956 00011110000000* +L053970 11101111110011* +L053984 11100110010001* +L053998 10100110010011* +L054012 11011011110100* +L054026 11111111111110* +L054040 00110011111000* +L054054 10100100010011* +L054068 11011011110100* +L054082 11111111111110* E1 0 00000000 @@ -1091,6 +1089,6 @@ E1 00000000 1 * -CBB2F* +CDE1F* U00000000000000000000000000000000* -BCCB +A145 diff --git a/Logic/68030_tk.lco b/Logic/68030_tk.lco index f580561..967a9aa 100644 --- a/Logic/68030_tk.lco +++ b/Logic/68030_tk.lco @@ -17,7 +17,7 @@ Parent = m4a5.lci; SDS_File = m4a5.sds; Design = 68030_tk.tt4; DATE = 5/15/14; -TIME = 22:21:57; +TIME = 23:02:50; Source_Format = Pure_VHDL; Type = TT2; Pre_Fit_Time = 1; @@ -76,41 +76,34 @@ Usercode_Format = Hex; [LOCATION ASSIGNMENTS] Layer = OFF; -A_28_ = pin,15,-,C,-; -A_27_ = pin,16,-,C,-; -SIZE_1_ = pin,79,-,H,-; -A_26_ = pin,17,-,C,-; -A_25_ = pin,18,-,C,-; -A_31_ = pin,4,-,B,-; -A_24_ = pin,19,-,C,-; -A_23_ = pin,84,-,H,-; -A_22_ = pin,85,-,H,-; A_21_ = pin,94,-,A,-; -IPL_2_ = pin,68,-,G,-; A_20_ = pin,93,-,A,-; +SIZE_1_ = pin,79,-,H,-; A_19_ = pin,97,-,A,-; A_18_ = pin,95,-,A,-; +A_31_ = pin,4,-,B,-; A_17_ = pin,59,-,F,-; -FC_1_ = pin,58,-,F,-; A_16_ = pin,96,-,A,-; +IPL_2_ = pin,68,-,G,-; +FC_1_ = pin,58,-,F,-; AS_030 = pin,82,-,H,-; DS_030 = pin,98,-,A,-; CPU_SPACE = pin,14,-,-,-; BERR = pin,41,-,E,-; BG_030 = pin,21,-,C,-; +A_0_ = pin,69,-,G,-; BGACK_000 = pin,28,-,D,-; CLK_030 = pin,64,-,-,-; -CLK_000 = pin,11,-,-,-; -CLK_OSZI = pin,61,-,-,-; -CLK_DIV_OUT = pin,65,-,G,-; -A_0_ = pin,69,-,G,-; -AVEC = pin,92,-,A,-; IPL_1_ = pin,56,-,F,-; -AVEC_EXP = pin,22,-,C,-; +CLK_000 = pin,11,-,-,-; IPL_0_ = pin,67,-,G,-; +CLK_OSZI = pin,61,-,-,-; DSACK_0_ = pin,80,-,H,-; -VPA = pin,36,-,-,-; +CLK_DIV_OUT = pin,65,-,G,-; FC_0_ = pin,57,-,F,-; +AVEC = pin,92,-,A,-; +AVEC_EXP = pin,22,-,C,-; +VPA = pin,36,-,-,-; RST = pin,86,-,-,-; RW = pin,71,-,G,-; AMIGA_BUS_ENABLE = pin,34,-,D,-; @@ -120,6 +113,13 @@ CIIN = pin,47,-,E,-; SIZE_0_ = pin,70,-,G,-; A_30_ = pin,5,-,B,-; A_29_ = pin,6,-,B,-; +A_28_ = pin,15,-,C,-; +A_27_ = pin,16,-,C,-; +A_26_ = pin,17,-,C,-; +A_25_ = pin,18,-,C,-; +A_24_ = pin,19,-,C,-; +A_23_ = pin,84,-,H,-; +A_22_ = pin,85,-,H,-; IPL_030_2_ = pin,9,-,B,-; DSACK_1_ = pin,81,-,H,-; AS_000 = pin,33,-,D,-; @@ -127,38 +127,33 @@ UDS_000 = pin,32,-,D,-; LDS_000 = pin,31,-,D,-; BG_000 = pin,29,-,D,-; BGACK_030 = pin,83,-,H,-; +IPL_030_1_ = pin,7,-,B,-; +IPL_030_0_ = pin,8,-,B,-; CLK_EXP = pin,10,-,B,-; FPU_CS = pin,78,-,H,-; -IPL_030_1_ = pin,7,-,B,-; DTACK = pin,30,-,D,-; -IPL_030_0_ = pin,8,-,B,-; E = pin,66,-,G,-; VMA = pin,35,-,D,-; RESET = pin,3,-,B,-; -cpu_est_0_ = node,-,-,G,8; -cpu_est_1_ = node,-,-,G,6; -cpu_est_d_0_ = node,-,-,G,15; -cpu_est_d_3_ = node,-,-,G,11; -inst_AS_030_000_SYNC = node,-,-,H,8; -inst_DTACK_SYNC = node,-,-,B,9; +cpu_est_0_ = node,-,-,D,14; +cpu_est_1_ = node,-,-,D,2; +inst_AS_030_000_SYNC = node,-,-,F,0; +inst_DTACK_SYNC = node,-,-,G,13; inst_VPA_D = node,-,-,G,1; -inst_VPA_SYNC = node,-,-,A,0; -inst_CLK_000_D = node,-,-,H,2; -inst_CLK_000_DD = node,-,-,H,13; -inst_CLK_OUT_PRE = node,-,-,G,12; -cpu_est_d_1_ = node,-,-,G,7; -cpu_est_d_2_ = node,-,-,G,3; -cpu_est_2_ = node,-,-,G,4; -CLK_CNT_0_ = node,-,-,G,14; +inst_VPA_SYNC = node,-,-,G,9; +inst_CLK_000_D = node,-,-,H,1; +inst_CLK_000_DD = node,-,-,D,13; +inst_CLK_OUT_PRE = node,-,-,H,5; +cpu_est_2_ = node,-,-,D,10; +CLK_CNT_0_ = node,-,-,H,6; SM_AMIGA_6_ = node,-,-,D,6; -SM_AMIGA_7_ = node,-,-,G,9; -inst_RISING_CLK_AMIGA = node,-,-,H,9; -SM_AMIGA_1_ = node,-,-,G,5; -SM_AMIGA_4_ = node,-,-,D,13; -SM_AMIGA_3_ = node,-,-,B,5; -SM_AMIGA_5_ = node,-,-,D,10; -SM_AMIGA_2_ = node,-,-,G,10; -SM_AMIGA_0_ = node,-,-,G,13; +SM_AMIGA_7_ = node,-,-,H,9; +SM_AMIGA_1_ = node,-,-,H,2; +SM_AMIGA_4_ = node,-,-,G,12; +SM_AMIGA_3_ = node,-,-,G,5; +SM_AMIGA_5_ = node,-,-,A,0; +SM_AMIGA_2_ = node,-,-,G,8; +SM_AMIGA_0_ = node,-,-,H,13; [GROUP ASSIGNMENTS] Layer = OFF; diff --git a/Logic/68030_tk.out b/Logic/68030_tk.out index 61ce612..6347986 100644 --- a/Logic/68030_tk.out +++ b/Logic/68030_tk.out @@ -49136,6 +49136,295 @@ 16 A_26_ 1 -1 -1 1 4 16 -1 15 A_27_ 1 -1 -1 1 4 15 -1 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 7 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +90 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 313 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 + 30 LDS_000 5 316 3 0 30 -1 12 0 21 + 31 UDS_000 5 315 3 0 31 -1 8 0 21 + 65 E 5 322 6 0 65 -1 3 0 21 + 28 BG_000 5 318 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 312 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 319 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 317 1 0 6 -1 3 0 21 + 82 BGACK_030 5 320 7 0 82 -1 2 0 21 + 77 FPU_CS 5 321 7 0 77 -1 2 0 21 + 34 VMA 5 323 3 0 34 -1 2 0 21 + 32 AS_000 5 314 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_DD 3 -1 3 5 0 1 3 6 7 -1 -1 1 0 20 + 299 inst_CLK_000_D 3 -1 7 5 0 1 3 6 7 -1 -1 1 0 20 + 295 inst_AS_030_000_SYNC 3 -1 5 3 0 3 5 -1 -1 4 0 21 + 321 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 301 inst_CLK_OUT_PRE 3 -1 7 3 1 6 7 -1 -1 2 0 20 + 294 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 20 + 322 RN_E 3 65 6 2 3 6 65 -1 3 0 21 + 310 SM_AMIGA_2_ 3 -1 6 2 6 7 -1 -1 3 0 20 + 304 SM_AMIGA_6_ 3 -1 3 2 0 3 -1 -1 3 0 21 + 302 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 1 20 + 293 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 20 + 323 RN_VMA 3 34 3 2 3 6 34 -1 2 0 21 + 320 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 314 RN_AS_000 3 32 3 2 3 7 32 -1 2 0 21 + 309 SM_AMIGA_5_ 3 -1 0 2 0 6 -1 -1 2 0 21 + 307 SM_AMIGA_4_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 305 SM_AMIGA_7_ 3 -1 7 2 3 7 -1 -1 2 0 21 + 297 inst_VPA_D 3 -1 6 2 3 6 -1 -1 1 0 21 + 316 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 315 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 319 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 318 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 317 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 312 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 311 SM_AMIGA_0_ 3 -1 7 1 7 -1 -1 3 0 21 + 308 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 3 0 20 + 306 SM_AMIGA_1_ 3 -1 7 1 7 -1 -1 3 0 21 + 313 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 298 inst_VPA_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 296 inst_DTACK_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 303 CLK_CNT_0_ 3 -1 7 1 7 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 5 0 1 3 6 7 60 -1 + 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1 + 81 AS_030 1 -1 -1 4 3 5 6 7 81 -1 + 63 CLK_030 1 -1 -1 3 3 5 7 63 -1 + 13 CPU_SPACE 1 -1 -1 3 3 5 7 13 -1 + 96 A_19_ 1 -1 -1 2 5 7 96 -1 + 95 A_16_ 1 -1 -1 2 5 7 95 -1 + 94 A_18_ 1 -1 -1 2 5 7 94 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 58 A_17_ 1 -1 -1 2 5 7 58 -1 + 57 FC_1_ 1 -1 -1 2 5 7 57 -1 + 56 FC_0_ 1 -1 -1 2 5 7 56 -1 + 27 BGACK_000 1 -1 -1 2 5 7 27 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 7 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +91 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 314 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 5 29 -1 1 0 21 + 30 LDS_000 5 317 3 0 30 -1 12 0 21 + 31 UDS_000 5 316 3 0 31 -1 8 0 21 + 65 E 5 323 6 0 65 -1 3 0 21 + 28 BG_000 5 318 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 313 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 321 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 320 1 0 6 -1 3 0 21 + 82 BGACK_030 5 319 7 0 82 -1 2 0 21 + 77 FPU_CS 5 322 7 0 77 -1 2 0 21 + 34 VMA 5 324 3 0 34 -1 2 0 21 + 32 AS_000 5 315 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 301 inst_CLK_000_D 3 -1 6 6 0 1 3 5 6 7 -1 -1 1 0 21 + 302 inst_CLK_000_DD 3 -1 3 4 1 3 6 7 -1 -1 1 0 20 + 295 inst_AS_030_000_SYNC 3 -1 7 3 3 6 7 -1 -1 4 0 21 + 294 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 20 + 323 RN_E 3 65 6 3 0 3 6 65 -1 3 0 21 + 309 SM_AMIGA_3_ 3 -1 6 3 0 5 6 -1 -1 3 0 20 + 304 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 3 1 20 + 303 inst_CLK_OUT_PRE 3 -1 7 3 1 6 7 -1 -1 3 0 20 + 293 cpu_est_0_ 3 -1 3 3 0 3 6 -1 -1 3 0 20 + 322 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 297 inst_VPA_D 3 -1 7 3 0 3 5 -1 -1 1 0 20 + 311 SM_AMIGA_2_ 3 -1 6 2 6 7 -1 -1 3 0 20 + 307 SM_AMIGA_1_ 3 -1 7 2 6 7 -1 -1 3 0 21 + 305 SM_AMIGA_6_ 3 -1 3 2 3 6 -1 -1 3 0 21 + 324 RN_VMA 3 34 3 2 0 3 34 -1 2 0 21 + 319 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 315 RN_AS_000 3 32 3 2 3 6 32 -1 2 0 21 + 308 SM_AMIGA_4_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 306 SM_AMIGA_7_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 298 inst_VPA_SYNC 3 -1 0 2 0 6 -1 -1 2 0 21 + 296 inst_DTACK_SYNC 3 -1 5 2 5 6 -1 -1 2 0 21 + 317 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 316 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 321 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 320 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 318 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 313 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 312 SM_AMIGA_0_ 3 -1 6 1 6 -1 -1 3 0 20 + 314 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 310 SM_AMIGA_5_ 3 -1 6 1 6 -1 -1 2 0 20 + 300 CLK_CNT_1_ 3 -1 7 1 7 -1 -1 2 0 20 + 299 CLK_CNT_0_ 3 -1 7 1 7 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 6 0 1 3 5 6 7 60 -1 + 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 3 5 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 13 CPU_SPACE 1 -1 -1 2 3 7 13 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 7 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 6 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +90 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 313 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 + 30 LDS_000 5 316 3 0 30 -1 12 0 21 + 31 UDS_000 5 315 3 0 31 -1 8 0 21 + 65 E 5 322 6 0 65 -1 3 0 21 + 28 BG_000 5 317 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 312 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 320 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 319 1 0 6 -1 3 0 21 + 82 BGACK_030 5 318 7 0 82 -1 2 0 21 + 77 FPU_CS 5 321 7 0 77 -1 2 0 21 + 34 VMA 5 323 3 0 34 -1 2 0 21 + 32 AS_000 5 314 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_DD 3 -1 3 5 0 1 3 6 7 -1 -1 1 0 20 + 299 inst_CLK_000_D 3 -1 7 5 0 1 3 6 7 -1 -1 1 0 20 + 295 inst_AS_030_000_SYNC 3 -1 5 3 0 3 5 -1 -1 4 0 21 + 321 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 301 inst_CLK_OUT_PRE 3 -1 7 3 1 6 7 -1 -1 2 0 20 + 294 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 20 + 322 RN_E 3 65 6 2 3 6 65 -1 3 0 21 + 310 SM_AMIGA_2_ 3 -1 6 2 6 7 -1 -1 3 0 20 + 304 SM_AMIGA_6_ 3 -1 3 2 0 3 -1 -1 3 0 21 + 302 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 1 20 + 293 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 20 + 323 RN_VMA 3 34 3 2 3 6 34 -1 2 0 21 + 318 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 314 RN_AS_000 3 32 3 2 3 7 32 -1 2 0 21 + 309 SM_AMIGA_5_ 3 -1 0 2 0 6 -1 -1 2 0 21 + 307 SM_AMIGA_4_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 305 SM_AMIGA_7_ 3 -1 7 2 3 7 -1 -1 2 0 21 + 297 inst_VPA_D 3 -1 6 2 3 6 -1 -1 1 0 21 + 316 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 315 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 320 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 319 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 317 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 312 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 311 SM_AMIGA_0_ 3 -1 7 1 7 -1 -1 3 0 21 + 308 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 3 0 20 + 306 SM_AMIGA_1_ 3 -1 7 1 7 -1 -1 3 0 21 + 313 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 298 inst_VPA_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 296 inst_DTACK_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 303 CLK_CNT_0_ 3 -1 7 1 7 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 5 0 1 3 6 7 60 -1 + 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1 + 81 AS_030 1 -1 -1 4 3 5 6 7 81 -1 + 63 CLK_030 1 -1 -1 3 3 5 7 63 -1 + 13 CPU_SPACE 1 -1 -1 3 3 5 7 13 -1 + 96 A_19_ 1 -1 -1 2 5 7 96 -1 + 95 A_16_ 1 -1 -1 2 5 7 95 -1 + 94 A_18_ 1 -1 -1 2 5 7 94 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 58 A_17_ 1 -1 -1 2 5 7 58 -1 + 57 FC_1_ 1 -1 -1 2 5 7 57 -1 + 56 FC_0_ 1 -1 -1 2 5 7 56 -1 + 27 BGACK_000 1 -1 -1 2 5 7 27 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 10 CLK_000 1 -1 -1 1 7 10 -1 5 A_29_ 1 -1 -1 1 4 5 -1 4 A_30_ 1 -1 -1 1 4 4 -1 diff --git a/Logic/68030_tk.plc b/Logic/68030_tk.plc index 78e4159..504648c 100644 --- a/Logic/68030_tk.plc +++ b/Logic/68030_tk.plc @@ -8,104 +8,99 @@ ; Source file 68030_tk.tt4 ; FITTER-generated Placements. ; DEVICE mach447a -; DATE Thu May 15 22:21:57 2014 +; DATE Thu May 15 23:02:50 2014 -Pin 15 A_28_ -Pin 16 A_27_ -Pin 79 SIZE_1_ -Pin 17 A_26_ -Pin 18 A_25_ -Pin 4 A_31_ -Pin 19 A_24_ -Pin 84 A_23_ -Pin 85 A_22_ Pin 94 A_21_ -Pin 68 IPL_2_ Pin 93 A_20_ +Pin 79 SIZE_1_ Pin 97 A_19_ Pin 95 A_18_ +Pin 4 A_31_ Pin 59 A_17_ -Pin 58 FC_1_ Pin 96 A_16_ +Pin 68 IPL_2_ +Pin 58 FC_1_ Pin 82 AS_030 Pin 98 DS_030 Pin 14 CPU_SPACE Pin 41 BERR Comb ; S6=1 S9=1 Pair 203 Pin 21 BG_030 +Pin 69 A_0_ Pin 28 BGACK_000 Pin 64 CLK_030 -Pin 11 CLK_000 -Pin 61 CLK_OSZI -Pin 65 CLK_DIV_OUT Reg ; S6=1 S9=1 Pair 245 -Pin 69 A_0_ -Pin 92 AVEC Comb ; S6=1 S9=1 Pair 107 Pin 56 IPL_1_ -Pin 22 AVEC_EXP Comb ; S6=1 S9=1 Pair 149 +Pin 11 CLK_000 Pin 67 IPL_0_ -Pin 80 DSACK_0_ Comb ; S6=1 S9=1 Pair 271 -Pin 36 VPA +Pin 61 CLK_OSZI +Pin 80 DSACK_0_ Comb ; S6=1 S9=1 Pair 287 +Pin 65 CLK_DIV_OUT Reg ; S6=1 S9=1 Pair 245 Pin 57 FC_0_ +Pin 92 AVEC Comb ; S6=1 S9=1 Pair 107 +Pin 22 AVEC_EXP Comb ; S6=1 S9=1 Pair 149 +Pin 36 VPA Pin 86 RST Pin 71 RW -Pin 34 AMIGA_BUS_ENABLE Comb ; S6=1 S9=1 Pair 176 +Pin 34 AMIGA_BUS_ENABLE Comb ; S6=1 S9=1 Pair 187 Pin 48 AMIGA_BUS_DATA_DIR Comb ; S6=1 S9=1 Pair 197 Pin 20 AMIGA_BUS_ENABLE_LOW Comb ; S6=1 S9=1 Pair 167 Pin 47 CIIN Comb ; S6=1 S9=1 Pair 215 Pin 70 SIZE_0_ Pin 5 A_30_ Pin 6 A_29_ +Pin 15 A_28_ +Pin 16 A_27_ +Pin 17 A_26_ +Pin 18 A_25_ +Pin 19 A_24_ +Pin 84 A_23_ +Pin 85 A_22_ Pin 9 IPL_030_2_ Reg ; S6=1 S9=1 Pair 131 -Pin 81 DSACK_1_ Reg ; S6=1 S9=1 Pair 287 -Pin 33 AS_000 Reg ; S6=1 S9=1 Pair 187 +Pin 81 DSACK_1_ Reg ; S6=1 S9=1 Pair 281 +Pin 33 AS_000 Reg ; S6=1 S9=1 Pair 181 Pin 32 UDS_000 Reg ; S6=1 S9=1 Pair 191 Pin 31 LDS_000 Reg ; S6=1 S9=1 Pair 185 Pin 29 BG_000 Reg ; S6=1 S9=1 Pair 175 Pin 83 BGACK_030 Reg ; S6=1 S9=1 Pair 275 +Pin 7 IPL_030_1_ Reg ; S6=1 S9=1 Pair 143 +Pin 8 IPL_030_0_ Reg ; S6=1 S9=1 Pair 137 Pin 10 CLK_EXP Reg ; S6=1 S9=0 Pair 125 Pin 78 FPU_CS Reg ; S6=1 S9=1 Pair 269 -Pin 7 IPL_030_1_ Reg ; S6=1 S9=1 Pair 143 Pin 30 DTACK Reg ; S6=1 S9=1 Pair 173 -Pin 8 IPL_030_0_ Reg ; S6=1 S9=1 Pair 137 -Pin 66 E Reg ; S6=1 S9=1 Pair 248 -Pin 35 VMA Reg ; S6=1 S9=1 Pair 181 +Pin 66 E Reg ; S6=1 S9=1 Pair 251 +Pin 35 VMA Reg ; S6=1 S9=1 Pair 179 Pin 3 RESET Reg ; S6=1 S9=0 Pair 127 Node 131 RN_IPL_030_2_ Reg ; S6=1 S9=1 -Node 287 RN_DSACK_1_ Reg ; S6=1 S9=1 -Node 187 RN_AS_000 Reg ; S6=1 S9=1 +Node 281 RN_DSACK_1_ Reg ; S6=1 S9=1 +Node 181 RN_AS_000 Reg ; S6=1 S9=1 Node 191 RN_UDS_000 Reg ; S6=1 S9=1 Node 185 RN_LDS_000 Reg ; S6=1 S9=1 Node 175 RN_BG_000 Reg ; S6=1 S9=1 Node 275 RN_BGACK_030 Reg ; S6=1 S9=1 -Node 269 RN_FPU_CS Reg ; S6=1 S9=1 Node 143 RN_IPL_030_1_ Reg ; S6=1 S9=1 -Node 173 RN_DTACK Reg ; S6=1 S9=1 Node 137 RN_IPL_030_0_ Reg ; S6=1 S9=1 -Node 248 RN_E Reg ; S6=1 S9=1 -Node 181 RN_VMA Reg ; S6=1 S9=1 -Node 257 cpu_est_0_ Reg ; S6=1 S9=1 -Node 254 cpu_est_1_ Reg ; S6=1 S9=1 -Node 268 cpu_est_d_0_ Reg ; S6=1 S9=1 -Node 262 cpu_est_d_3_ Reg ; S6=1 S9=1 -Node 281 inst_AS_030_000_SYNC Reg ; S6=1 S9=1 -Node 139 inst_DTACK_SYNC Reg ; S6=1 S9=1 +Node 269 RN_FPU_CS Reg ; S6=1 S9=1 +Node 173 RN_DTACK Reg ; S6=1 S9=1 +Node 251 RN_E Reg ; S6=1 S9=1 +Node 179 RN_VMA Reg ; S6=1 S9=1 +Node 194 cpu_est_0_ Reg ; S6=1 S9=0 +Node 176 cpu_est_1_ Reg ; S6=1 S9=0 +Node 221 inst_AS_030_000_SYNC Reg ; S6=1 S9=1 +Node 265 inst_DTACK_SYNC Reg ; S6=0 S9=0 Node 247 inst_VPA_D Reg ; S6=1 S9=1 -Node 101 inst_VPA_SYNC Reg ; S6=1 S9=1 -Node 272 inst_CLK_000_D Reg ; S6=1 S9=0 -Node 289 inst_CLK_000_DD Reg ; S6=1 S9=0 -Node 263 inst_CLK_OUT_PRE Reg ; S6=1 S9=1 -Node 256 cpu_est_d_1_ Reg ; S6=1 S9=1 -Node 250 cpu_est_d_2_ Reg ; S6=1 S9=1 -Node 251 cpu_est_2_ Reg ; S6=1 S9=1 -Node 266 CLK_CNT_0_ Reg ; S6=1 S9=1 +Node 259 inst_VPA_SYNC Reg ; S6=0 S9=0 +Node 271 inst_CLK_000_D Reg ; S6=1 S9=0 +Node 193 inst_CLK_000_DD Reg ; S6=1 S9=0 +Node 277 inst_CLK_OUT_PRE Reg ; S6=1 S9=0 +Node 188 cpu_est_2_ Reg ; S6=1 S9=0 +Node 278 CLK_CNT_0_ Reg ; S6=1 S9=0 Node 182 SM_AMIGA_6_ Reg ; S6=0 S9=1 -Node 259 SM_AMIGA_7_ Reg ; S6=0 S9=0 -Node 283 inst_RISING_CLK_AMIGA Reg ; S6=1 S9=0 -Node 253 SM_AMIGA_1_ Reg ; S6=1 S9=0 -Node 193 SM_AMIGA_4_ Reg ; S6=0 S9=1 -Node 133 SM_AMIGA_3_ Reg ; S6=0 S9=1 -Node 188 SM_AMIGA_5_ Reg ; S6=0 S9=1 -Node 260 SM_AMIGA_2_ Reg ; S6=1 S9=0 -Node 265 SM_AMIGA_0_ Reg ; S6=1 S9=0 +Node 283 SM_AMIGA_7_ Reg ; S6=1 S9=1 +Node 272 SM_AMIGA_1_ Reg ; S6=0 S9=1 +Node 263 SM_AMIGA_4_ Reg ; S6=1 S9=0 +Node 253 SM_AMIGA_3_ Reg ; S6=1 S9=0 +Node 101 SM_AMIGA_5_ Reg ; S6=1 S9=1 +Node 257 SM_AMIGA_2_ Reg ; S6=1 S9=0 +Node 289 SM_AMIGA_0_ Reg ; S6=0 S9=1 ; Unused Pins & Nodes ; -> None Found. diff --git a/Logic/68030_tk.prd b/Logic/68030_tk.prd index c12bcf9..d4884f6 100644 --- a/Logic/68030_tk.prd +++ b/Logic/68030_tk.prd @@ -5,8 +5,8 @@ |--------------------------------------------| -Start: Thu May 15 22:21:57 2014 -End : Thu May 15 22:21:57 2014 $$$ Elapsed time: 00:00:00 +Start: Thu May 15 23:02:49 2014 +End : Thu May 15 23:02:50 2014 $$$ Elapsed time: 00:00:01 =========================================================================== Part [C:/Program Files (x86)/ispLever/ispcpld/dat/mach4a/mach447a] Design [68030_tk.tt4] @@ -21,16 +21,16 @@ Part [C:/Program Files (x86)/ispLever/ispcpld/dat/mach4a/mach447a] Design [68030 | | +- Signals to Place | | +----- Logic Array Inputs | | | +- Placed | | | +- Array Inputs Used _|____|____|____|_______________|____|_____________|___|________________ - 0 | 16 | 2 | 2 => 100% | 8 | 7 => 87% | 33 | 12 => 36% - 1 | 16 | 7 | 7 => 100% | 8 | 8 => 100% | 33 | 18 => 54% + 0 | 16 | 2 | 2 => 100% | 8 | 7 => 87% | 33 | 7 => 21% + 1 | 16 | 5 | 5 => 100% | 8 | 8 => 100% | 33 | 11 => 33% 2 | 16 | 2 | 2 => 100% | 8 | 8 => 100% | 33 | 1 => 3% - 3 | 16 | 10 | 10 => 100% | 8 | 8 => 100% | 33 | 33 => 100% + 3 | 16 | 12 | 12 => 100% | 8 | 8 => 100% | 33 | 29 => 87% 4 | 16 | 3 | 3 => 100% | 8 | 3 => 37% | 33 | 14 => 42% - 5 | 16 | 0 | 0 => n/a | 8 | 4 => 50% | 33 | 0 => 0% - 6 | 16 | 16 | 16 => 100% | 8 | 7 => 87% | 33 | 19 => 57% - 7 | 16 | 8 | 8 => 100% | 8 | 8 => 100% | 33 | 21 => 63% + 5 | 16 | 1 | 1 => 100% | 8 | 4 => 50% | 33 | 12 => 36% + 6 | 16 | 8 | 8 => 100% | 8 | 7 => 87% | 33 | 20 => 60% + 7 | 16 | 10 | 10 => 100% | 8 | 8 => 100% | 33 | 25 => 75% ---|----|----|------------|-------|------------|-----|------------------ - | Avg number of array inputs in used blocks : 16.86 => 51% + | Avg number of array inputs in used blocks : 14.88 => 45% * Input/Clock Signal count: 35 -> placed: 35 = 100% @@ -40,14 +40,14 @@ _|____|____|____|_______________|____|_____________|___|________________ I/O Pins : 64 53 => 82% Clock Only Pins : 0 0 => 0% Clock/Input Pins : 4 4 => 100% - Logic Blocks : 8 7 => 87% - Macrocells : 128 48 => 37% - PT Clusters : 128 30 => 23% - - Single PT Clusters : 128 21 => 16% + Logic Blocks : 8 8 => 100% + Macrocells : 128 43 => 33% + PT Clusters : 128 31 => 24% + - Single PT Clusters : 128 16 => 12% Input Registers : 0 * Routing Completion: 100% -* Attempts: Place [ 1176] Route [ 0] +* Attempts: Place [ 90] Route [ 0] =========================================================================== Signal Fanout Table =========================================================================== @@ -62,14 +62,14 @@ ___|__|__|____|____________________________________________________________ 3| 2|OUT| 20|=> ....|....| AMIGA_BUS_ENABLE_LOW 4| 3| IO| 33|=> ....|....| AS_000 |=> Paired w/: RN_AS_000 - 5| 7|INP| 82|=> 01.3|...7| AS_030 + 5| 7|INP| 82|=> ...3|.567| AS_030 6| 0|OUT| 92|=> ....|....| AVEC 7| 2|OUT| 22|=> ....|....| AVEC_EXP 8| 6|INP| 69|=> ...3|....| A_0_ - 9| 0|INP| 96|=> ....|...7| A_16_ - 10| 5|INP| 59|=> ....|...7| A_17_ - 11| 0|INP| 95|=> ....|...7| A_18_ - 12| 0|INP| 97|=> ....|...7| A_19_ + 9| 0|INP| 96|=> ....|.5.7| A_16_ + 10| 5|INP| 59|=> ....|.5.7| A_17_ + 11| 0|INP| 95|=> ....|.5.7| A_18_ + 12| 0|INP| 97|=> ....|.5.7| A_19_ 13| 0|INP| 93|=> ....|4...| A_20_ 14| 0|INP| 94|=> ....|4...| A_21_ 15| 7|INP| 85|=> ....|4...| A_22_ @@ -83,7 +83,7 @@ ___|__|__|____|____________________________________________________________ 23| 1|INP| 5|=> ....|4...| A_30_ 24| 1|INP| 4|=> ....|4...| A_31_ 25| 4|OUT| 41|=> ....|....| BERR - 26| 3|INP| 28|=> ....|...7| BGACK_000 + 26| 3|INP| 28|=> ....|.5.7| BGACK_000 27| 7| IO| 83|=> ....|....| BGACK_030 |=> Paired w/: RN_BGACK_030 28| 3| IO| 29|=> ....|....| BG_000 @@ -91,21 +91,21 @@ ___|__|__|____|____________________________________________________________ 29| 2|INP| 21|=> ...3|....| BG_030 30| 4|OUT| 47|=> ....|....| CIIN 31| +|INP| 11|=> ....|...7| CLK_000 - 32| +|INP| 64|=> ...3|...7| CLK_030 - 33| 6|NOD| . |=> ....|..6.| CLK_CNT_0_ + 32| +|INP| 64|=> ...3|.5.7| CLK_030 + 33| 7|NOD| . |=> ....|...7| CLK_CNT_0_ 34| 6|OUT| 65|=> ....|....| CLK_DIV_OUT 35| 1|OUT| 10|=> ....|....| CLK_EXP - 36| +|Cin| 61|=> 01..|..67| CLK_OSZI - 37| +|INP| 14|=> ...3|...7| CPU_SPACE + 36| +|Cin| 61|=> 01.3|..67| CLK_OSZI + 37| +|INP| 14|=> ...3|.5.7| CPU_SPACE 38| 7|OUT| 80|=> ....|....| DSACK_0_ 39| 7| IO| 81|=> ...3|....| DSACK_1_ |=> Paired w/: RN_DSACK_1_ 40| 0|INP| 98|=> ...3|....| DS_030 - 41| 3| IO| 30|=> .1..|....| DTACK + 41| 3| IO| 30|=> ....|..6.| DTACK 42| 6| IO| 66|=> ....|....| E |=> Paired w/: RN_E - 43| 5|INP| 57|=> ....|...7| FC_0_ - 44| 5|INP| 58|=> ....|...7| FC_1_ + 43| 5|INP| 57|=> ....|.5.7| FC_0_ + 44| 5|INP| 58|=> ....|.5.7| FC_1_ 45| 7| IO| 78|=> ....|....| FPU_CS |=> Paired w/: RN_FPU_CS 46| 1| IO| 8|=> ....|....| IPL_030_0_ @@ -120,7 +120,7 @@ ___|__|__|____|____________________________________________________________ 52| 3| IO| 31|=> ....|....| LDS_000 |=> Paired w/: RN_LDS_000 53| 1|OUT| 3|=> ....|....| RESET - 54| 3|NOD| . |=> ...3|..6.| RN_AS_000 + 54| 3|NOD| . |=> ...3|...7| RN_AS_000 |=> Paired w/: AS_000 55| 7|NOD| . |=> ...3|...7| RN_BGACK_030 |=> Paired w/: BGACK_030 @@ -128,7 +128,7 @@ ___|__|__|____|____________________________________________________________ |=> Paired w/: BG_000 57| 7|NOD| . |=> ....|...7| RN_DSACK_1_ |=> Paired w/: DSACK_1_ - 58| 6|NOD| . |=> 0..3|..6.| RN_E + 58| 6|NOD| . |=> ...3|..6.| RN_E |=> Paired w/: E 59| 7|NOD| . |=> ..2.|4..7| RN_FPU_CS |=> Paired w/: FPU_CS @@ -142,40 +142,35 @@ ___|__|__|____|____________________________________________________________ |=> Paired w/: LDS_000 64| 3|NOD| . |=> ...3|....| RN_UDS_000 |=> Paired w/: UDS_000 - 65| 3|NOD| . |=> 0..3|....| RN_VMA + 65| 3|NOD| . |=> ...3|..6.| RN_VMA |=> Paired w/: VMA - 66| +|INP| 86|=> 01.3|..67| RST + 66| +|INP| 86|=> 01.3|.567| RST 67| 6|INP| 71|=> ...3|4...| RW 68| 6|INP| 70|=> ...3|....| SIZE_0_ 69| 7|INP| 79|=> ...3|....| SIZE_1_ - 70| 6|NOD| . |=> ....|..6.| SM_AMIGA_0_ - 71| 6|NOD| . |=> ....|..67| SM_AMIGA_1_ - 72| 6|NOD| . |=> ....|..6.| SM_AMIGA_2_ - 73| 1|NOD| . |=> 01..|..6.| SM_AMIGA_3_ - 74| 3|NOD| . |=> .1.3|....| SM_AMIGA_4_ - 75| 3|NOD| . |=> ...3|....| SM_AMIGA_5_ - 76| 3|NOD| . |=> ...3|....| SM_AMIGA_6_ - 77| 6|NOD| . |=> ...3|..6.| SM_AMIGA_7_ + 70| 7|NOD| . |=> ....|...7| SM_AMIGA_0_ + 71| 7|NOD| . |=> ....|...7| SM_AMIGA_1_ + 72| 6|NOD| . |=> ....|..67| SM_AMIGA_2_ + 73| 6|NOD| . |=> ....|..6.| SM_AMIGA_3_ + 74| 6|NOD| . |=> ...3|..6.| SM_AMIGA_4_ + 75| 0|NOD| . |=> 0...|..6.| SM_AMIGA_5_ + 76| 3|NOD| . |=> 0..3|....| SM_AMIGA_6_ + 77| 7|NOD| . |=> ...3|...7| SM_AMIGA_7_ 78| 3| IO| 32|=> ....|....| UDS_000 |=> Paired w/: RN_UDS_000 79| 3| IO| 35|=> ....|....| VMA |=> Paired w/: RN_VMA 80| +|INP| 36|=> ....|..6.| VPA - 81| 6|NOD| . |=> 0..3|..6.| cpu_est_0_ - 82| 6|NOD| . |=> 0..3|..6.| cpu_est_1_ - 83| 6|NOD| . |=> 0..3|..6.| cpu_est_2_ - 84| 6|NOD| . |=> ...3|....| cpu_est_d_0_ - 85| 6|NOD| . |=> ...3|....| cpu_est_d_1_ - 86| 6|NOD| . |=> ...3|....| cpu_est_d_2_ - 87| 6|NOD| . |=> ...3|....| cpu_est_d_3_ - 88| 7|NOD| . |=> ...3|...7| inst_AS_030_000_SYNC - 89| 7|NOD| . |=> 01.3|..67| inst_CLK_000_D - 90| 7|NOD| . |=> ...3|..6.| inst_CLK_000_DD - 91| 6|NOD| . |=> .1..|..67| inst_CLK_OUT_PRE - 92| 1|NOD| . |=> .1..|..6.| inst_DTACK_SYNC - 93| 7|NOD| . |=> .1..|...7| inst_RISING_CLK_AMIGA - 94| 6|NOD| . |=> 01.3|....| inst_VPA_D - 95| 0|NOD| . |=> 01..|..6.| inst_VPA_SYNC + 81| 3|NOD| . |=> ...3|..6.| cpu_est_0_ + 82| 3|NOD| . |=> ...3|..6.| cpu_est_1_ + 83| 3|NOD| . |=> ...3|..6.| cpu_est_2_ + 84| 5|NOD| . |=> 0..3|.5..| inst_AS_030_000_SYNC + 85| 7|NOD| . |=> 01.3|..67| inst_CLK_000_D + 86| 3|NOD| . |=> 01.3|..67| inst_CLK_000_DD + 87| 7|NOD| . |=> .1..|..67| inst_CLK_OUT_PRE + 88| 6|NOD| . |=> ....|..6.| inst_DTACK_SYNC + 89| 6|NOD| . |=> ...3|..6.| inst_VPA_D + 90| 6|NOD| . |=> ....|..6.| inst_VPA_SYNC --------------------------------------------------------------------------- =========================================================================== < C:/Program Files (x86)/ispLever/ispcpld/dat/mach4a/mach447a Device Pin Assignments > @@ -295,7 +290,7 @@ ____|_____|_________|______________________________________________________ | Sig Type-+ | | | | | | | XOR to Mcell Assignment | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ - 0| inst_VPA_SYNC|NOD| | S | 2 | 4 to [ 0]| 1 XOR free + 0| SM_AMIGA_5_|NOD| | S | 2 | 4 to [ 0]| 1 XOR free 1| | ? | | S | | 4 free | 1 XOR free 2| | ? | | S | | 4 free | 1 XOR free 3| | ? | | S | | 4 free | 1 XOR free @@ -322,7 +317,7 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| inst_VPA_SYNC|NOD| | S | 2 |=> can support up to [ 15] logic PT(s) + 0| SM_AMIGA_5_|NOD| | S | 2 |=> can support up to [ 15] logic PT(s) 1| | ? | | S | |=> can support up to [ 15] logic PT(s) 2| | ? | | S | |=> can support up to [ 19] logic PT(s) 3| | ? | | S | |=> can support up to [ 19] logic PT(s) @@ -347,7 +342,7 @@ _|_________________|__|__|___|_____|_______________________________________ | Sig Type---+ | to | Block [ 0] IO Pin | Device Pin | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ - 0| inst_VPA_SYNC|NOD| | => | 5 6 7 0 | 96 97 98 91 + 0| SM_AMIGA_5_|NOD| | => | 5 6 7 0 | 96 97 98 91 1| | | | => | 5 6 7 0 | 96 97 98 91 2| | | | => | 6 7 0 1 | 97 98 91 92 3| | | | => | 6 7 0 1 | 97 98 91 92 @@ -411,7 +406,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number ---|-------|----|---|---|----------|------|-|------------------------------ 0 [IOpin 0 | 91| -| | ] [RegIn 0 |102| -| | ] - [MCell 0 |101|NOD inst_VPA_SYNC| |*] + [MCell 0 |101|NOD SM_AMIGA_5_| |*] [MCell 1 |103| -| | ] 1 [IOpin 1 | 92|OUT AVEC|*| ] @@ -456,34 +451,34 @@ IMX No. | +---- Block IO Pin or Macrocell Number | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- Mux00| Input Pin ( 86)| RST -Mux01| ... | ... -Mux02| Mcel 6 4 ( 251)| cpu_est_2_ +Mux01| Mcel 3 13 ( 193)| inst_CLK_000_DD +Mux02| ... | ... Mux03| ... | ... Mux04| Input Pin ( 61)| CLK_OSZI -Mux05| Mcel 6 6 ( 254)| cpu_est_1_ +Mux05| Mcel 5 0 ( 221)| inst_AS_030_000_SYNC Mux06| ... | ... -Mux07| Mcel 3 5 ( 181)| RN_VMA +Mux07| ... | ... Mux08| ... | ... -Mux09| IOPin 7 3 ( 82)| AS_030 -Mux10| Mcel 6 8 ( 257)| cpu_est_0_ +Mux09| ... | ... +Mux10| Mcel 7 1 ( 271)| inst_CLK_000_D Mux11| ... | ... Mux12| ... | ... Mux13| ... | ... -Mux14| Mcel 7 2 ( 272)| inst_CLK_000_D -Mux15| Mcel 0 0 ( 101)| inst_VPA_SYNC -Mux16| ... | ... +Mux14| ... | ... +Mux15| Mcel 0 0 ( 101)| SM_AMIGA_5_ +Mux16| Mcel 3 6 ( 182)| SM_AMIGA_6_ Mux17| ... | ... Mux18| ... | ... Mux19| ... | ... Mux20| ... | ... Mux21| ... | ... Mux22| ... | ... -Mux23| Mcel 6 2 ( 248)| RN_E -Mux24| Mcel 6 1 ( 247)| inst_VPA_D +Mux23| ... | ... +Mux24| ... | ... Mux25| ... | ... Mux26| ... | ... Mux27| ... | ... -Mux28| Mcel 1 5 ( 133)| SM_AMIGA_3_ +Mux28| ... | ... Mux29| ... | ... Mux30| ... | ... Mux31| ... | ... @@ -503,15 +498,15 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ 1| RESET|OUT| | A | 1 | 2 free | 1 XOR to [ 1] for 1 PT sig 2| | ? | | S | | 4 free | 1 XOR free 3| | ? | | S | | 4 free | 1 XOR free - 4| IPL_030_2_| IO| | S | 2 | 4 to [ 4]| 1 XOR free - 5| SM_AMIGA_3_|NOD| | S | 3 | 4 to [ 5]| 1 XOR free + 4| IPL_030_2_| IO| | S | 3 | 4 to [ 4]| 1 XOR free + 5| | ? | | S | | 4 free | 1 XOR free 6| | ? | | S | | 4 free | 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free - 8| IPL_030_0_| IO| | S | 2 | 4 to [ 8]| 1 XOR free - 9|inst_DTACK_SYNC|NOD| | S | 2 | 4 to [ 9]| 1 XOR free + 8| IPL_030_0_| IO| | S | 3 | 4 to [ 8]| 1 XOR free + 9| | ? | | S | | 4 free | 1 XOR free 10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free -12| IPL_030_1_| IO| | S | 2 | 4 to [12]| 1 XOR free +12| IPL_030_1_| IO| | S | 3 | 4 to [12]| 1 XOR free 13| | ? | | S | | 4 free | 1 XOR free 14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free @@ -529,16 +524,16 @@ _|_________________|__|__|___|_____|_______________________________________ 0| CLK_EXP|OUT| | A | 1 |=> can support up to [ 10] logic PT(s) 1| RESET|OUT| | A | 1 |=> can support up to [ 15] logic PT(s) 2| | ? | | S | |=> can support up to [ 12] logic PT(s) - 3| | ? | | S | |=> can support up to [ 10] logic PT(s) - 4| IPL_030_2_| IO| | S | 2 |=> can support up to [ 15] logic PT(s) - 5| SM_AMIGA_3_|NOD| | S | 3 |=> can support up to [ 15] logic PT(s) - 6| | ? | | S | |=> can support up to [ 10] logic PT(s) - 7| | ? | | S | |=> can support up to [ 10] logic PT(s) - 8| IPL_030_0_| IO| | S | 2 |=> can support up to [ 15] logic PT(s) - 9|inst_DTACK_SYNC|NOD| | S | 2 |=> can support up to [ 15] logic PT(s) -10| | ? | | S | |=> can support up to [ 10] logic PT(s) + 3| | ? | | S | |=> can support up to [ 15] logic PT(s) + 4| IPL_030_2_| IO| | S | 3 |=> can support up to [ 20] logic PT(s) + 5| | ? | | S | |=> can support up to [ 15] logic PT(s) + 6| | ? | | S | |=> can support up to [ 15] logic PT(s) + 7| | ? | | S | |=> can support up to [ 15] logic PT(s) + 8| IPL_030_0_| IO| | S | 3 |=> can support up to [ 20] logic PT(s) + 9| | ? | | S | |=> can support up to [ 15] logic PT(s) +10| | ? | | S | |=> can support up to [ 15] logic PT(s) 11| | ? | | S | |=> can support up to [ 15] logic PT(s) -12| IPL_030_1_| IO| | S | 2 |=> can support up to [ 20] logic PT(s) +12| IPL_030_1_| IO| | S | 3 |=> can support up to [ 20] logic PT(s) 13| | ? | | S | |=> can support up to [ 15] logic PT(s) 14| | ? | | S | |=> can support up to [ 15] logic PT(s) 15| | ? | | S | |=> can support up to [ 10] logic PT(s) @@ -556,11 +551,11 @@ _|_________________|__|_____|____________________|________________________ 2| | | | => | 6 7 0 1 | 4 3 10 9 3| | | | => | 6 7 0 1 | 4 3 10 9 4| IPL_030_2_| IO| | => | 7 0 ( 1) 2 | 3 10 ( 9) 8 - 5| SM_AMIGA_3_|NOD| | => | 7 0 1 2 | 3 10 9 8 + 5| | | | => | 7 0 1 2 | 3 10 9 8 6| | | | => | 0 1 2 3 | 10 9 8 7 7| | | | => | 0 1 2 3 | 10 9 8 7 8| IPL_030_0_| IO| | => | 1 ( 2) 3 4 | 9 ( 8) 7 6 - 9|inst_DTACK_SYNC|NOD| | => | 1 2 3 4 | 9 8 7 6 + 9| | | | => | 1 2 3 4 | 9 8 7 6 10| | | | => | 2 3 4 5 | 8 7 6 5 11| | | | => | 2 3 4 5 | 8 7 6 5 12| IPL_030_1_| IO| | => |( 3) 4 5 6 |( 7) 6 5 4 @@ -629,7 +624,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 2 [IOpin 2 | 8| IO IPL_030_0_|*| ] paired w/[ RN_IPL_030_0_] [RegIn 2 |132| -| | ] [MCell 4 |131|NOD RN_IPL_030_2_| |*] paired w/[ IPL_030_2_] - [MCell 5 |133|NOD SM_AMIGA_3_| |*] + [MCell 5 |133| -| | ] 3 [IOpin 3 | 7| IO IPL_030_1_|*| ] paired w/[ RN_IPL_030_1_] [RegIn 3 |135| -| | ] @@ -639,7 +634,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 4 [IOpin 4 | 6|INP A_29_|*|*] [RegIn 4 |138| -| | ] [MCell 8 |137|NOD RN_IPL_030_0_| |*] paired w/[ IPL_030_0_] - [MCell 9 |139|NOD inst_DTACK_SYNC| |*] + [MCell 9 |139| -| | ] 5 [IOpin 5 | 5|INP A_30_|*|*] [RegIn 5 |141| -| | ] @@ -663,21 +658,21 @@ IMX No. | +---- Block IO Pin or Macrocell Number | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- Mux00| IOPin 6 2 ( 67)| IPL_0_ -Mux01| Mcel 3 13 ( 193)| SM_AMIGA_4_ +Mux01| Mcel 3 13 ( 193)| inst_CLK_000_DD Mux02| ... | ... Mux03| IOPin 5 4 ( 56)| IPL_1_ Mux04| IOPin 6 3 ( 68)| IPL_2_ -Mux05| Mcel 7 9 ( 283)| inst_RISING_CLK_AMIGA -Mux06| Mcel 1 9 ( 139)| inst_DTACK_SYNC -Mux07| Mcel 6 12 ( 263)| inst_CLK_OUT_PRE +Mux05| ... | ... +Mux06| ... | ... +Mux07| ... | ... Mux08| Mcel 1 8 ( 137)| RN_IPL_030_0_ -Mux09| IOPin 7 3 ( 82)| AS_030 -Mux10| ... | ... +Mux09| ... | ... +Mux10| Mcel 7 1 ( 271)| inst_CLK_000_D Mux11| ... | ... Mux12| Mcel 1 12 ( 143)| RN_IPL_030_1_ -Mux13| ... | ... -Mux14| Mcel 7 2 ( 272)| inst_CLK_000_D -Mux15| Mcel 0 0 ( 101)| inst_VPA_SYNC +Mux13| Mcel 7 5 ( 277)| inst_CLK_OUT_PRE +Mux14| ... | ... +Mux15| ... | ... Mux16| ... | ... Mux17| ... | ... Mux18| ... | ... @@ -685,12 +680,12 @@ Mux19| ... | ... Mux20| ... | ... Mux21| Input Pin ( 86)| RST Mux22| ... | ... -Mux23| IOPin 3 5 ( 30)| DTACK -Mux24| Mcel 6 1 ( 247)| inst_VPA_D +Mux23| ... | ... +Mux24| ... | ... Mux25| ... | ... Mux26| ... | ... Mux27| Mcel 1 4 ( 131)| RN_IPL_030_2_ -Mux28| Mcel 1 5 ( 133)| SM_AMIGA_3_ +Mux28| ... | ... Mux29| Input Pin ( 61)| CLK_OSZI Mux30| ... | ... Mux31| ... | ... @@ -911,20 +906,20 @@ Mux32| ... | ... | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| DTACK| IO| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig - 1| BG_000| IO| | S | 3 | 4 to [ 1]| 1 XOR free - 2|AMIGA_BUS_ENABLE|OUT| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig - 3| | ? | | S | | 4 free | 1 XOR free - 4| | ? | | S | | 4 free | 1 XOR free - 5| VMA| IO| | S | 2 | 4 to [ 5]| 1 XOR free - 6| SM_AMIGA_6_|NOD| | S | 3 | 4 to [ 6]| 1 XOR free - 7| | ? | | S | | 4 to [ 8]| 1 XOR free + 1| BG_000| IO| | S | 3 | 4 to [ 2]| 1 XOR free + 2| cpu_est_1_|NOD| | A | 4 | 2 to [ 1]| 1 XOR to [ 1] as logic PT + 3| | ? | | S | | 4 to [ 4]| 1 XOR free + 4| VMA| IO| | S | 2 | 4 to [ 5]| 1 XOR free + 5| AS_000| IO| | S | 2 | 4 to [ 6]| 1 XOR free + 6| SM_AMIGA_6_|NOD| | S | 3 | 4 free | 1 XOR free + 7| | ? | | S | | 4 to [ 8]| 1 XOR to [ 8] as logic PT 8| LDS_000| IO| | S |12 | 4 to [ 8]| 1 XOR to [ 8] as logic PT - 9| AS_000| IO| | S | 2 | 4 to [ 8]| 1 XOR free -10| SM_AMIGA_5_|NOD| | S | 2 | 4 to [10]| 1 XOR free -11| | ? | | S | | 4 to [ 9]| 1 XOR free + 9|AMIGA_BUS_ENABLE|OUT| | S | 1 | 4 to [10]| 1 XOR to [ 9] for 1 PT sig +10| cpu_est_2_|NOD| | A | 3 :+: 1| 2 to [ 8]| 1 XOR to [10] +11| | ? | | S | | 4 to [12]| 1 XOR free 12| UDS_000| IO| | S | 8 | 4 to [12]| 1 XOR to [12] as logic PT -13| SM_AMIGA_4_|NOD| | S | 2 | 4 to [13]| 1 XOR free -14| | ? | | S | | 4 to [12]| 1 XOR free +13|inst_CLK_000_DD|NOD| | A | 1 | 2 to [12]| 1 XOR to [13] for 1 PT sig +14| cpu_est_0_|NOD| | A | 3 | 2 to [14]| 1 XOR to [14] as logic PT 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== @@ -937,21 +932,21 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| DTACK| IO| | S | 1 |=> can support up to [ 9] logic PT(s) - 1| BG_000| IO| | S | 3 |=> can support up to [ 18] logic PT(s) - 2|AMIGA_BUS_ENABLE|OUT| | S | 1 |=> can support up to [ 15] logic PT(s) - 3| | ? | | S | |=> can support up to [ 14] logic PT(s) - 4| | ? | | S | |=> can support up to [ 10] logic PT(s) - 5| VMA| IO| | S | 2 |=> can support up to [ 10] logic PT(s) - 6| SM_AMIGA_6_|NOD| | S | 3 |=> can support up to [ 5] logic PT(s) - 7| | ? | | S | |=> can support up to [ 1] logic PT(s) - 8| LDS_000| IO| | S |12 |=> can support up to [ 15] logic PT(s) - 9| AS_000| IO| | S | 2 |=> can support up to [ 5] logic PT(s) -10| SM_AMIGA_5_|NOD| | S | 2 |=> can support up to [ 5] logic PT(s) + 0| DTACK| IO| | S | 1 |=> can support up to [ 5] logic PT(s) + 1| BG_000| IO| | S | 3 |=> can support up to [ 7] logic PT(s) + 2| cpu_est_1_|NOD| | A | 4 |=> can support up to [ 5] logic PT(s) + 3| | ? | | S | |=> can support up to [ 1] logic PT(s) + 4| VMA| IO| | S | 2 |=> can support up to [ 10] logic PT(s) + 5| AS_000| IO| | S | 2 |=> can support up to [ 10] logic PT(s) + 6| SM_AMIGA_6_|NOD| | S | 3 |=> can support up to [ 10] logic PT(s) + 7| | ? | | S | |=> can support up to [ 5] logic PT(s) + 8| LDS_000| IO| | S |12 |=> can support up to [ 12] logic PT(s) + 9|AMIGA_BUS_ENABLE|OUT| | S | 1 |=> can support up to [ 1] logic PT(s) +10| cpu_est_2_|NOD| | A | 3 :+: 1|=> can support up to [ 4] logic PT(s) 11| | ? | | S | |=> can support up to [ 1] logic PT(s) -12| UDS_000| IO| | S | 8 |=> can support up to [ 10] logic PT(s) -13| SM_AMIGA_4_|NOD| | S | 2 |=> can support up to [ 10] logic PT(s) -14| | ? | | S | |=> can support up to [ 6] logic PT(s) +12| UDS_000| IO| | S | 8 |=> can support up to [ 12] logic PT(s) +13|inst_CLK_000_DD|NOD| | A | 1 |=> can support up to [ 6] logic PT(s) +14| cpu_est_0_|NOD| | A | 3 |=> can support up to [ 8] logic PT(s) 15| | ? | | S | |=> can support up to [ 5] logic PT(s) --------------------------------------------------------------------------- =========================================================================== @@ -964,19 +959,19 @@ _|_________________|__|__|___|_____|_______________________________________ _|_________________|__|_____|____________________|________________________ 0| DTACK| IO| | => |( 5) 6 7 0 |( 30) 29 28 35 1| BG_000| IO| | => | 5 ( 6) 7 0 | 30 ( 29) 28 35 - 2|AMIGA_BUS_ENABLE|OUT| | => | 6 7 0 ( 1)| 29 28 35 ( 34) + 2| cpu_est_1_|NOD| | => | 6 7 0 1 | 29 28 35 34 3| | | | => | 6 7 0 1 | 29 28 35 34 - 4| | | | => | 7 0 1 2 | 28 35 34 33 - 5| VMA| IO| | => | 7 ( 0) 1 2 | 28 ( 35) 34 33 + 4| VMA| IO| | => | 7 ( 0) 1 2 | 28 ( 35) 34 33 + 5| AS_000| IO| | => | 7 0 1 ( 2)| 28 35 34 ( 33) 6| SM_AMIGA_6_|NOD| | => | 0 1 2 3 | 35 34 33 32 7| | | | => | 0 1 2 3 | 35 34 33 32 8| LDS_000| IO| | => | 1 2 3 ( 4)| 34 33 32 ( 31) - 9| AS_000| IO| | => | 1 ( 2) 3 4 | 34 ( 33) 32 31 -10| SM_AMIGA_5_|NOD| | => | 2 3 4 5 | 33 32 31 30 + 9|AMIGA_BUS_ENABLE|OUT| | => |( 1) 2 3 4 |( 34) 33 32 31 +10| cpu_est_2_|NOD| | => | 2 3 4 5 | 33 32 31 30 11| | | | => | 2 3 4 5 | 33 32 31 30 12| UDS_000| IO| | => |( 3) 4 5 6 |( 32) 31 30 29 -13| SM_AMIGA_4_|NOD| | => | 3 4 5 6 | 32 31 30 29 -14| | | | => | 4 5 6 7 | 31 30 29 28 +13|inst_CLK_000_DD|NOD| | => | 3 4 5 6 | 32 31 30 29 +14| cpu_est_0_|NOD| | => | 4 5 6 7 | 31 30 29 28 15| | | | => | 4 5 6 7 | 31 30 29 28 --------------------------------------------------------------------------- =========================================================================== @@ -988,9 +983,9 @@ _|_________________|__|_____|____________________|________________________ | Sig Type--+ | | | | Signal Name | | | | Node Destinations Via Output Matrix _|_________________|__|___|_____|___________________________________________ - 0| VMA| IO|*| 35| => | 0 1 2 3 4 ( 5) 6 7 - 1|AMIGA_BUS_ENABLE|OUT|*| 34| => | ( 2) 3 4 5 6 7 8 9 - 2| AS_000| IO|*| 33| => | 4 5 6 7 8 ( 9) 10 11 + 0| VMA| IO|*| 35| => | 0 1 2 3 ( 4) 5 6 7 + 1|AMIGA_BUS_ENABLE|OUT|*| 34| => | 2 3 4 5 6 7 8 ( 9) + 2| AS_000| IO|*| 33| => | 4 ( 5) 6 7 8 9 10 11 3| UDS_000| IO|*| 32| => | 6 7 8 9 10 11 (12) 13 4| LDS_000| IO|*| 31| => | ( 8) 9 10 11 12 13 14 15 5| DTACK| IO|*| 30| => | 10 11 12 13 14 15 ( 0) 1 @@ -1036,13 +1031,13 @@ IMX No. | +---- Block IO Pin or Macrocell Number 1 [IOpin 1 | 34|OUT AMIGA_BUS_ENABLE|*| ] [RegIn 1 |177| -| | ] - [MCell 2 |176|OUT AMIGA_BUS_ENABLE| | ] + [MCell 2 |176|NOD cpu_est_1_| |*] [MCell 3 |178| -| | ] 2 [IOpin 2 | 33| IO AS_000|*| ] paired w/[ RN_AS_000] [RegIn 2 |180| -| | ] - [MCell 4 |179| -| | ] - [MCell 5 |181|NOD RN_VMA| |*] paired w/[ VMA] + [MCell 4 |179|NOD RN_VMA| |*] paired w/[ VMA] + [MCell 5 |181|NOD RN_AS_000| |*] paired w/[ AS_000] 3 [IOpin 3 | 32| IO UDS_000|*| ] paired w/[ RN_UDS_000] [RegIn 3 |183| -| | ] @@ -1052,21 +1047,21 @@ IMX No. | +---- Block IO Pin or Macrocell Number 4 [IOpin 4 | 31| IO LDS_000|*| ] paired w/[ RN_LDS_000] [RegIn 4 |186| -| | ] [MCell 8 |185|NOD RN_LDS_000| |*] paired w/[ LDS_000] - [MCell 9 |187|NOD RN_AS_000| |*] paired w/[ AS_000] + [MCell 9 |187|OUT AMIGA_BUS_ENABLE| | ] 5 [IOpin 5 | 30| IO DTACK|*|*] [RegIn 5 |189| -| | ] - [MCell 10 |188|NOD SM_AMIGA_5_| |*] + [MCell 10 |188|NOD cpu_est_2_| |*] [MCell 11 |190| -| | ] 6 [IOpin 6 | 29| IO BG_000|*| ] paired w/[ RN_BG_000] [RegIn 6 |192| -| | ] [MCell 12 |191|NOD RN_UDS_000| |*] paired w/[ UDS_000] - [MCell 13 |193|NOD SM_AMIGA_4_| |*] + [MCell 13 |193|NOD inst_CLK_000_DD| |*] 7 [IOpin 7 | 28|INP BGACK_000|*|*] [RegIn 7 |195| -| | ] - [MCell 14 |194| -| | ] + [MCell 14 |194|NOD cpu_est_0_| |*] [MCell 15 |196| -| | ] --------------------------------------------------------------------------- =========================================================================== @@ -1075,39 +1070,39 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| IOPin 6 4 ( 69)| A_0_ -Mux01| Mcel 3 13 ( 193)| SM_AMIGA_4_ -Mux02| Mcel 6 4 ( 251)| cpu_est_2_ -Mux03| Mcel 7 8 ( 281)| inst_AS_030_000_SYNC -Mux04| Mcel 7 2 ( 272)| inst_CLK_000_D -Mux05| Mcel 3 12 ( 191)| RN_UDS_000 +Mux00| IOPin 6 5 ( 70)| SIZE_0_ +Mux01| Mcel 3 13 ( 193)| inst_CLK_000_DD +Mux02| Mcel 6 4 ( 251)| RN_E +Mux03| Mcel 3 2 ( 176)| cpu_est_1_ +Mux04| Mcel 6 1 ( 247)| inst_VPA_D +Mux05| IOPin 0 7 ( 98)| DS_030 Mux06| IOPin 7 6 ( 79)| SIZE_1_ -Mux07| Mcel 7 13 ( 289)| inst_CLK_000_DD +Mux07| Mcel 3 5 ( 181)| RN_AS_000 Mux08| IOPin 6 6 ( 71)| RW -Mux09| Mcel 6 11 ( 262)| cpu_est_d_3_ -Mux10| IOPin 7 4 ( 81)| DSACK_1_ -Mux11| Mcel 3 5 ( 181)| RN_VMA -Mux12| IOPin 0 7 ( 98)| DS_030 -Mux13| Mcel 6 8 ( 257)| cpu_est_0_ -Mux14| IOPin 6 5 ( 70)| SIZE_0_ +Mux09| IOPin 7 3 ( 82)| AS_030 +Mux10| Mcel 3 14 ( 194)| cpu_est_0_ +Mux11| Mcel 3 12 ( 191)| RN_UDS_000 +Mux12| Mcel 7 1 ( 271)| inst_CLK_000_D +Mux13| ... | ... +Mux14| Mcel 6 12 ( 263)| SM_AMIGA_4_ Mux15| Input Pin ( 14)| CPU_SPACE -Mux16| Mcel 3 6 ( 182)| SM_AMIGA_6_ +Mux16| Mcel 3 8 ( 185)| RN_LDS_000 Mux17| Mcel 3 1 ( 175)| RN_BG_000 -Mux18| Mcel 6 15 ( 268)| cpu_est_d_0_ -Mux19| IOPin 7 3 ( 82)| AS_030 -Mux20| Mcel 3 10 ( 188)| SM_AMIGA_5_ -Mux21| Input Pin ( 86)| RST +Mux18| IOPin 6 4 ( 69)| A_0_ +Mux19| ... | ... +Mux20| Mcel 3 10 ( 188)| cpu_est_2_ +Mux21| Mcel 3 4 ( 179)| RN_VMA Mux22| IOPin 2 6 ( 21)| BG_030 Mux23| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux24| Mcel 6 1 ( 247)| inst_VPA_D -Mux25| Mcel 3 9 ( 187)| RN_AS_000 -Mux26| Mcel 6 7 ( 256)| cpu_est_d_1_ -Mux27| Mcel 6 9 ( 259)| SM_AMIGA_7_ +Mux24| Input Pin ( 86)| RST +Mux25| Mcel 5 0 ( 221)| inst_AS_030_000_SYNC +Mux26| ... | ... +Mux27| Mcel 7 9 ( 283)| SM_AMIGA_7_ Mux28| Input Pin ( 64)| CLK_030 -Mux29| Mcel 6 6 ( 254)| cpu_est_1_ -Mux30| Mcel 6 3 ( 250)| cpu_est_d_2_ -Mux31| Mcel 6 2 ( 248)| RN_E -Mux32| Mcel 3 8 ( 185)| RN_LDS_000 +Mux29| Input Pin ( 61)| CLK_OSZI +Mux30| Mcel 3 6 ( 182)| SM_AMIGA_6_ +Mux31| ... | ... +Mux32| IOPin 7 4 ( 81)| DSACK_1_ --------------------------------------------------------------------------- =========================================================================== < Block [ 4] > Macrocell (MCell) Cluster Assignments @@ -1313,6 +1308,85 @@ Mux30| ... | ... Mux31| ... | ... Mux32| ... | ... --------------------------------------------------------------------------- +=========================================================================== + < Block [ 5] > Macrocell (MCell) Cluster Assignments +=========================================================================== + + Macrocell Number + | PT Requirements------ Logic XOR+ +--- Macrocell PT Cluster Size + | Sync/Async-------+ | | | Cluster to Mcell Assignment + | Node Fixed(*)----+ | | | | | +- XOR PT Size + | Sig Type-+ | | | | | | | XOR to Mcell Assignment + | Signal Name | | | | | | | | | +_|_________________|__|__|___|_____|__|______|___|__________|______________ + 0|inst_AS_030_000_SYNC|NOD| | S | 4 | 4 to [ 0]| 1 XOR free + 1| | ? | | S | | 4 free | 1 XOR free + 2| | ? | | S | | 4 free | 1 XOR free + 3| | ? | | S | | 4 free | 1 XOR free + 4| | ? | | S | | 4 free | 1 XOR free + 5| | ? | | S | | 4 free | 1 XOR free + 6| | ? | | S | | 4 free | 1 XOR free + 7| | ? | | S | | 4 free | 1 XOR free + 8| | ? | | S | | 4 free | 1 XOR free + 9| | ? | | S | | 4 free | 1 XOR free +10| | ? | | S | | 4 free | 1 XOR free +11| | ? | | S | | 4 free | 1 XOR free +12| | ? | | S | | 4 free | 1 XOR free +13| | ? | | S | | 4 free | 1 XOR free +14| | ? | | S | | 4 free | 1 XOR free +15| | ? | | S | | 4 free | 1 XOR free +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 5] > Maximum PT Capacity +=========================================================================== + + Macrocell Number + | PT Requirements------ Logic XOR+ + | Sync/Async-------+ | | + | Node Fixed(*)----+ | | | + | Sig Type-+ | | | | + | Signal Name | | | | | Maximum PT Capacity +_|_________________|__|__|___|_____|_______________________________________ + 0|inst_AS_030_000_SYNC|NOD| | S | 4 |=> can support up to [ 15] logic PT(s) + 1| | ? | | S | |=> can support up to [ 15] logic PT(s) + 2| | ? | | S | |=> can support up to [ 20] logic PT(s) + 3| | ? | | S | |=> can support up to [ 20] logic PT(s) + 4| | ? | | S | |=> can support up to [ 20] logic PT(s) + 5| | ? | | S | |=> can support up to [ 20] logic PT(s) + 6| | ? | | S | |=> can support up to [ 20] logic PT(s) + 7| | ? | | S | |=> can support up to [ 20] logic PT(s) + 8| | ? | | S | |=> can support up to [ 20] logic PT(s) + 9| | ? | | S | |=> can support up to [ 20] logic PT(s) +10| | ? | | S | |=> can support up to [ 20] logic PT(s) +11| | ? | | S | |=> can support up to [ 20] logic PT(s) +12| | ? | | S | |=> can support up to [ 20] logic PT(s) +13| | ? | | S | |=> can support up to [ 20] logic PT(s) +14| | ? | | S | |=> can support up to [ 15] logic PT(s) +15| | ? | | S | |=> can support up to [ 10] logic PT(s) +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 5] > Node-Pin Assignments +=========================================================================== + + Macrocell Number + | Node Fixed(*)------+ + | Sig Type---+ | to | Block [ 5] IO Pin | Device Pin + | Signal Name | | pin | Numbers | Numbers +_|_________________|__|_____|____________________|________________________ + 0|inst_AS_030_000_SYNC|NOD| | => | 5 6 7 0 | 55 54 53 60 + 1| | | | => | 5 6 7 0 | 55 54 53 60 + 2| | | | => | 6 7 0 1 | 54 53 60 59 + 3| | | | => | 6 7 0 1 | 54 53 60 59 + 4| | | | => | 7 0 1 2 | 53 60 59 58 + 5| | | | => | 7 0 1 2 | 53 60 59 58 + 6| | | | => | 0 1 2 3 | 60 59 58 57 + 7| | | | => | 0 1 2 3 | 60 59 58 57 + 8| | | | => | 1 2 3 4 | 59 58 57 56 + 9| | | | => | 1 2 3 4 | 59 58 57 56 +10| | | | => | 2 3 4 5 | 58 57 56 55 +11| | | | => | 2 3 4 5 | 58 57 56 55 +12| | | | => | 3 4 5 6 | 57 56 55 54 +13| | | | => | 3 4 5 6 | 57 56 55 54 +14| | | | => | 4 5 6 7 | 56 55 54 53 +15| | | | => | 4 5 6 7 | 56 55 54 53 +--------------------------------------------------------------------------- =========================================================================== < Block [ 5] > IO-to-Node Pin Mapping =========================================================================== @@ -1360,7 +1434,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number ---|-------|----|---|---|----------|------|-|------------------------------ 0 [IOpin 0 | 60| -| | ] [RegIn 0 |222| -| | ] - [MCell 0 |221| -| | ] + [MCell 0 |221|NOD inst_AS_030_000_SYNC| |*] [MCell 1 |223| -| | ] 1 [IOpin 1 | 59|INP A_17_|*|*] @@ -1398,6 +1472,46 @@ IMX No. | +---- Block IO Pin or Macrocell Number [MCell 14 |242| -| | ] [MCell 15 |244| -| | ] --------------------------------------------------------------------------- +=========================================================================== + < Block [ 5] > Logic Array Fan-in +=========================================================================== + +- Central Switch Matrix No. + | Src (ABEL Node/Pin#) Signal +--|--|--------------------|--------------------------------------------------- +Mux00| Input Pin ( 86)| RST +Mux01| IOPin 5 2 ( 58)| FC_1_ +Mux02| ... | ... +Mux03| ... | ... +Mux04| IOPin 3 7 ( 28)| BGACK_000 +Mux05| Input Pin ( 14)| CPU_SPACE +Mux06| IOPin 5 3 ( 57)| FC_0_ +Mux07| ... | ... +Mux08| IOPin 5 1 ( 59)| A_17_ +Mux09| IOPin 7 3 ( 82)| AS_030 +Mux10| ... | ... +Mux11| IOPin 0 5 ( 96)| A_16_ +Mux12| IOPin 0 6 ( 97)| A_19_ +Mux13| ... | ... +Mux14| ... | ... +Mux15| ... | ... +Mux16| ... | ... +Mux17| IOPin 0 4 ( 95)| A_18_ +Mux18| ... | ... +Mux19| ... | ... +Mux20| Input Pin ( 64)| CLK_030 +Mux21| ... | ... +Mux22| ... | ... +Mux23| ... | ... +Mux24| ... | ... +Mux25| Mcel 5 0 ( 221)| inst_AS_030_000_SYNC +Mux26| ... | ... +Mux27| ... | ... +Mux28| ... | ... +Mux29| ... | ... +Mux30| ... | ... +Mux31| ... | ... +Mux32| ... | ... +--------------------------------------------------------------------------- =========================================================================== < Block [ 6] > Macrocell (MCell) Cluster Assignments =========================================================================== @@ -1410,20 +1524,20 @@ IMX No. | +---- Block IO Pin or Macrocell Number _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| CLK_DIV_OUT|OUT| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig 1| inst_VPA_D|NOD| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig - 2| E| IO| | S | 3 | 4 to [ 2]| 1 XOR free - 3| cpu_est_d_2_|NOD| | S | 1 | 4 free | 1 XOR to [ 3] for 1 PT sig - 4| cpu_est_2_|NOD| | S | 3 :+: 1| 4 to [ 4]| 1 XOR to [ 4] - 5| SM_AMIGA_1_|NOD| | A | 3 | 2 to [ 5]| 1 XOR to [ 5] as logic PT - 6| cpu_est_1_|NOD| | S | 4 | 4 to [ 6]| 1 XOR free - 7| cpu_est_d_1_|NOD| | S | 1 | 4 free | 1 XOR to [ 7] for 1 PT sig - 8| cpu_est_0_|NOD| | S | 3 | 4 to [ 8]| 1 XOR free - 9| SM_AMIGA_7_|NOD| | A | 2 | 2 to [ 9]| 1 XOR free -10| SM_AMIGA_2_|NOD| | A | 3 | 2 to [10]| 1 XOR to [10] as logic PT -11| cpu_est_d_3_|NOD| | S | 1 | 4 free | 1 XOR to [11] for 1 PT sig -12|inst_CLK_OUT_PRE|NOD| | S | 2 | 4 to [12]| 1 XOR free -13| SM_AMIGA_0_|NOD| | A | 3 | 2 to [13]| 1 XOR to [13] as logic PT -14| CLK_CNT_0_|NOD| | S | 1 | 4 free | 1 XOR to [14] for 1 PT sig -15| cpu_est_d_0_|NOD| | S | 1 | 4 free | 1 XOR to [15] for 1 PT sig + 2| | ? | | S | | 4 free | 1 XOR free + 3| | ? | | S | | 4 free | 1 XOR free + 4| E| IO| | S | 3 | 4 to [ 4]| 1 XOR free + 5| SM_AMIGA_3_|NOD| | A | 3 | 2 to [ 5]| 1 XOR to [ 5] as logic PT + 6| | ? | | S | | 4 free | 1 XOR free + 7| | ? | | S | | 4 free | 1 XOR free + 8| SM_AMIGA_2_|NOD| | A | 3 | 2 to [ 8]| 1 XOR to [ 8] as logic PT + 9| inst_VPA_SYNC|NOD| | A | 2 | 2 to [ 9]| 1 XOR free +10| | ? | | S | | 4 free | 1 XOR free +11| | ? | | S | | 4 free | 1 XOR free +12| SM_AMIGA_4_|NOD| | A | 2 | 2 to [12]| 1 XOR free +13|inst_DTACK_SYNC|NOD| | A | 2 | 2 to [13]| 1 XOR free +14| | ? | | S | | 4 free | 1 XOR free +15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== < Block [ 6] > Maximum PT Capacity @@ -1435,22 +1549,22 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| CLK_DIV_OUT|OUT| | S | 1 |=> can support up to [ 9] logic PT(s) - 1| inst_VPA_D|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) - 2| E| IO| | S | 3 |=> can support up to [ 13] logic PT(s) - 3| cpu_est_d_2_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) - 4| cpu_est_2_|NOD| | S | 3 :+: 1|=> can support up to [ 8] logic PT(s) - 5| SM_AMIGA_1_|NOD| | A | 3 |=> can support up to [ 7] logic PT(s) - 6| cpu_est_1_|NOD| | S | 4 |=> can support up to [ 9] logic PT(s) - 7| cpu_est_d_1_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) - 8| cpu_est_0_|NOD| | S | 3 |=> can support up to [ 9] logic PT(s) - 9| SM_AMIGA_7_|NOD| | A | 2 |=> can support up to [ 7] logic PT(s) -10| SM_AMIGA_2_|NOD| | A | 3 |=> can support up to [ 7] logic PT(s) -11| cpu_est_d_3_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) -12|inst_CLK_OUT_PRE|NOD| | S | 2 |=> can support up to [ 13] logic PT(s) -13| SM_AMIGA_0_|NOD| | A | 3 |=> can support up to [ 11] logic PT(s) -14| CLK_CNT_0_|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) -15| cpu_est_d_0_|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) + 0| CLK_DIV_OUT|OUT| | S | 1 |=> can support up to [ 14] logic PT(s) + 1| inst_VPA_D|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) + 2| | ? | | S | |=> can support up to [ 14] logic PT(s) + 3| | ? | | S | |=> can support up to [ 10] logic PT(s) + 4| E| IO| | S | 3 |=> can support up to [ 15] logic PT(s) + 5| SM_AMIGA_3_|NOD| | A | 3 |=> can support up to [ 13] logic PT(s) + 6| | ? | | S | |=> can support up to [ 10] logic PT(s) + 7| | ? | | S | |=> can support up to [ 10] logic PT(s) + 8| SM_AMIGA_2_|NOD| | A | 3 |=> can support up to [ 13] logic PT(s) + 9| inst_VPA_SYNC|NOD| | A | 2 |=> can support up to [ 13] logic PT(s) +10| | ? | | S | |=> can support up to [ 10] logic PT(s) +11| | ? | | S | |=> can support up to [ 10] logic PT(s) +12| SM_AMIGA_4_|NOD| | A | 2 |=> can support up to [ 13] logic PT(s) +13|inst_DTACK_SYNC|NOD| | A | 2 |=> can support up to [ 13] logic PT(s) +14| | ? | | S | |=> can support up to [ 10] logic PT(s) +15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 6] > Node-Pin Assignments @@ -1462,20 +1576,20 @@ _|_________________|__|__|___|_____|_______________________________________ _|_________________|__|_____|____________________|________________________ 0| CLK_DIV_OUT|OUT| | => | 5 6 7 ( 0)| 70 71 72 ( 65) 1| inst_VPA_D|NOD| | => | 5 6 7 0 | 70 71 72 65 - 2| E| IO| | => | 6 7 0 ( 1)| 71 72 65 ( 66) - 3| cpu_est_d_2_|NOD| | => | 6 7 0 1 | 71 72 65 66 - 4| cpu_est_2_|NOD| | => | 7 0 1 2 | 72 65 66 67 - 5| SM_AMIGA_1_|NOD| | => | 7 0 1 2 | 72 65 66 67 - 6| cpu_est_1_|NOD| | => | 0 1 2 3 | 65 66 67 68 - 7| cpu_est_d_1_|NOD| | => | 0 1 2 3 | 65 66 67 68 - 8| cpu_est_0_|NOD| | => | 1 2 3 4 | 66 67 68 69 - 9| SM_AMIGA_7_|NOD| | => | 1 2 3 4 | 66 67 68 69 -10| SM_AMIGA_2_|NOD| | => | 2 3 4 5 | 67 68 69 70 -11| cpu_est_d_3_|NOD| | => | 2 3 4 5 | 67 68 69 70 -12|inst_CLK_OUT_PRE|NOD| | => | 3 4 5 6 | 68 69 70 71 -13| SM_AMIGA_0_|NOD| | => | 3 4 5 6 | 68 69 70 71 -14| CLK_CNT_0_|NOD| | => | 4 5 6 7 | 69 70 71 72 -15| cpu_est_d_0_|NOD| | => | 4 5 6 7 | 69 70 71 72 + 2| | | | => | 6 7 0 1 | 71 72 65 66 + 3| | | | => | 6 7 0 1 | 71 72 65 66 + 4| E| IO| | => | 7 0 ( 1) 2 | 72 65 ( 66) 67 + 5| SM_AMIGA_3_|NOD| | => | 7 0 1 2 | 72 65 66 67 + 6| | | | => | 0 1 2 3 | 65 66 67 68 + 7| | | | => | 0 1 2 3 | 65 66 67 68 + 8| SM_AMIGA_2_|NOD| | => | 1 2 3 4 | 66 67 68 69 + 9| inst_VPA_SYNC|NOD| | => | 1 2 3 4 | 66 67 68 69 +10| | | | => | 2 3 4 5 | 67 68 69 70 +11| | | | => | 2 3 4 5 | 67 68 69 70 +12| SM_AMIGA_4_|NOD| | => | 3 4 5 6 | 68 69 70 71 +13|inst_DTACK_SYNC|NOD| | => | 3 4 5 6 | 68 69 70 71 +14| | | | => | 4 5 6 7 | 69 70 71 72 +15| | | | => | 4 5 6 7 | 69 70 71 72 --------------------------------------------------------------------------- =========================================================================== < Block [ 6] > IO-to-Node Pin Mapping @@ -1487,7 +1601,7 @@ _|_________________|__|_____|____________________|________________________ | Signal Name | | | | Node Destinations Via Output Matrix _|_________________|__|___|_____|___________________________________________ 0| CLK_DIV_OUT|OUT|*| 65| => | ( 0) 1 2 3 4 5 6 7 - 1| E| IO|*| 66| => | ( 2) 3 4 5 6 7 8 9 + 1| E| IO|*| 66| => | 2 3 ( 4) 5 6 7 8 9 2| IPL_0_|INP|*| 67| => | 4 5 6 7 8 9 10 11 3| IPL_2_|INP|*| 68| => | 6 7 8 9 10 11 12 13 4| A_0_|INP|*| 69| => | 8 9 10 11 12 13 14 15 @@ -1530,38 +1644,38 @@ IMX No. | +---- Block IO Pin or Macrocell Number 1 [IOpin 1 | 66| IO E|*| ] paired w/[ RN_E] [RegIn 1 |249| -| | ] - [MCell 2 |248|NOD RN_E| |*] paired w/[ E] - [MCell 3 |250|NOD cpu_est_d_2_| |*] + [MCell 2 |248| -| | ] + [MCell 3 |250| -| | ] 2 [IOpin 2 | 67|INP IPL_0_|*|*] [RegIn 2 |252| -| | ] - [MCell 4 |251|NOD cpu_est_2_| |*] - [MCell 5 |253|NOD SM_AMIGA_1_| |*] + [MCell 4 |251|NOD RN_E| |*] paired w/[ E] + [MCell 5 |253|NOD SM_AMIGA_3_| |*] 3 [IOpin 3 | 68|INP IPL_2_|*|*] [RegIn 3 |255| -| | ] - [MCell 6 |254|NOD cpu_est_1_| |*] - [MCell 7 |256|NOD cpu_est_d_1_| |*] + [MCell 6 |254| -| | ] + [MCell 7 |256| -| | ] 4 [IOpin 4 | 69|INP A_0_|*|*] [RegIn 4 |258| -| | ] - [MCell 8 |257|NOD cpu_est_0_| |*] - [MCell 9 |259|NOD SM_AMIGA_7_| |*] + [MCell 8 |257|NOD SM_AMIGA_2_| |*] + [MCell 9 |259|NOD inst_VPA_SYNC| |*] 5 [IOpin 5 | 70|INP SIZE_0_|*|*] [RegIn 5 |261| -| | ] - [MCell 10 |260|NOD SM_AMIGA_2_| |*] - [MCell 11 |262|NOD cpu_est_d_3_| |*] + [MCell 10 |260| -| | ] + [MCell 11 |262| -| | ] 6 [IOpin 6 | 71|INP RW|*|*] [RegIn 6 |264| -| | ] - [MCell 12 |263|NOD inst_CLK_OUT_PRE| |*] - [MCell 13 |265|NOD SM_AMIGA_0_| |*] + [MCell 12 |263|NOD SM_AMIGA_4_| |*] + [MCell 13 |265|NOD inst_DTACK_SYNC| |*] 7 [IOpin 7 | 72| -| | ] [RegIn 7 |267| -| | ] - [MCell 14 |266|NOD CLK_CNT_0_| |*] - [MCell 15 |268|NOD cpu_est_d_0_| |*] + [MCell 14 |266| -| | ] + [MCell 15 |268| -| | ] --------------------------------------------------------------------------- =========================================================================== < Block [ 6] > Logic Array Fan-in @@ -1570,35 +1684,35 @@ IMX No. | +---- Block IO Pin or Macrocell Number | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- Mux00| Input Pin ( 86)| RST -Mux01| ... | ... -Mux02| Mcel 6 4 ( 251)| cpu_est_2_ -Mux03| Mcel 6 5 ( 253)| SM_AMIGA_1_ -Mux04| Mcel 7 2 ( 272)| inst_CLK_000_D -Mux05| Mcel 6 10 ( 260)| SM_AMIGA_2_ -Mux06| Mcel 1 9 ( 139)| inst_DTACK_SYNC -Mux07| Mcel 7 13 ( 289)| inst_CLK_000_DD +Mux01| Mcel 3 13 ( 193)| inst_CLK_000_DD +Mux02| Mcel 3 10 ( 188)| cpu_est_2_ +Mux03| Mcel 6 5 ( 253)| SM_AMIGA_3_ +Mux04| Mcel 7 5 ( 277)| inst_CLK_OUT_PRE +Mux05| ... | ... +Mux06| ... | ... +Mux07| Mcel 6 12 ( 263)| SM_AMIGA_4_ Mux08| ... | ... -Mux09| Mcel 6 13 ( 265)| SM_AMIGA_0_ +Mux09| IOPin 7 3 ( 82)| AS_030 Mux10| Input Pin ( 36)| VPA -Mux11| Mcel 6 14 ( 266)| CLK_CNT_0_ -Mux12| Mcel 6 9 ( 259)| SM_AMIGA_7_ -Mux13| Mcel 6 8 ( 257)| cpu_est_0_ -Mux14| Mcel 6 12 ( 263)| inst_CLK_OUT_PRE -Mux15| Mcel 0 0 ( 101)| inst_VPA_SYNC -Mux16| ... | ... -Mux17| ... | ... +Mux11| Mcel 6 4 ( 251)| RN_E +Mux12| Mcel 6 13 ( 265)| inst_DTACK_SYNC +Mux13| Mcel 6 8 ( 257)| SM_AMIGA_2_ +Mux14| Mcel 3 4 ( 179)| RN_VMA +Mux15| Mcel 0 0 ( 101)| SM_AMIGA_5_ +Mux16| Mcel 3 2 ( 176)| cpu_est_1_ +Mux17| Mcel 3 14 ( 194)| cpu_est_0_ Mux18| ... | ... -Mux19| ... | ... +Mux19| Mcel 7 1 ( 271)| inst_CLK_000_D Mux20| ... | ... Mux21| Input Pin ( 61)| CLK_OSZI Mux22| ... | ... -Mux23| Mcel 6 2 ( 248)| RN_E -Mux24| ... | ... -Mux25| Mcel 3 9 ( 187)| RN_AS_000 +Mux23| IOPin 3 5 ( 30)| DTACK +Mux24| Mcel 6 1 ( 247)| inst_VPA_D +Mux25| ... | ... Mux26| ... | ... -Mux27| ... | ... -Mux28| Mcel 1 5 ( 133)| SM_AMIGA_3_ -Mux29| Mcel 6 6 ( 254)| cpu_est_1_ +Mux27| Mcel 6 9 ( 259)| inst_VPA_SYNC +Mux28| ... | ... +Mux29| ... | ... Mux30| ... | ... Mux31| ... | ... Mux32| ... | ... @@ -1614,19 +1728,19 @@ Mux32| ... | ... | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| FPU_CS| IO| | S | 2 | 4 to [ 0]| 1 XOR free - 1| DSACK_0_|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig - 2|inst_CLK_000_D|NOD| | A | 1 | 2 free | 1 XOR to [ 2] for 1 PT sig + 1|inst_CLK_000_D|NOD| | A | 1 | 2 free | 1 XOR to [ 1] for 1 PT sig + 2| SM_AMIGA_1_|NOD| | S | 3 | 4 to [ 2]| 1 XOR free 3| | ? | | S | | 4 free | 1 XOR free 4| BGACK_030| IO| | S | 2 | 4 to [ 4]| 1 XOR free - 5| | ? | | S | | 4 free | 1 XOR free - 6| | ? | | S | | 4 free | 1 XOR free + 5|inst_CLK_OUT_PRE|NOD| | A | 2 | 2 to [ 5]| 1 XOR free + 6| CLK_CNT_0_|NOD| | A | 1 | 2 free | 1 XOR to [ 6] for 1 PT sig 7| | ? | | S | | 4 free | 1 XOR free - 8|inst_AS_030_000_SYNC|NOD| | S | 4 | 4 to [ 8]| 1 XOR free - 9|inst_RISING_CLK_AMIGA|NOD| | A | 1 | 2 free | 1 XOR to [ 9] for 1 PT sig + 8| DSACK_1_| IO| | S | 2 | 4 to [ 8]| 1 XOR free + 9| SM_AMIGA_7_|NOD| | S | 2 | 4 to [ 9]| 1 XOR free 10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free -12| DSACK_1_| IO| | S | 2 | 4 to [12]| 1 XOR free -13|inst_CLK_000_DD|NOD| | A | 1 | 2 free | 1 XOR to [13] for 1 PT sig +12| DSACK_0_|OUT| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig +13| SM_AMIGA_0_|NOD| | S | 3 | 4 to [13]| 1 XOR free 14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- @@ -1640,21 +1754,21 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| FPU_CS| IO| | S | 2 |=> can support up to [ 11] logic PT(s) - 1| DSACK_0_|OUT| | S | 1 |=> can support up to [ 12] logic PT(s) - 2|inst_CLK_000_D|NOD| | A | 1 |=> can support up to [ 12] logic PT(s) - 3| | ? | | S | |=> can support up to [ 12] logic PT(s) - 4| BGACK_030| IO| | S | 2 |=> can support up to [ 20] logic PT(s) - 5| | ? | | S | |=> can support up to [ 15] logic PT(s) - 6| | ? | | S | |=> can support up to [ 15] logic PT(s) - 7| | ? | | S | |=> can support up to [ 12] logic PT(s) - 8|inst_AS_030_000_SYNC|NOD| | S | 4 |=> can support up to [ 17] logic PT(s) - 9|inst_RISING_CLK_AMIGA|NOD| | A | 1 |=> can support up to [ 13] logic PT(s) -10| | ? | | S | |=> can support up to [ 12] logic PT(s) -11| | ? | | S | |=> can support up to [ 12] logic PT(s) -12| DSACK_1_| IO| | S | 2 |=> can support up to [ 17] logic PT(s) -13|inst_CLK_000_DD|NOD| | A | 1 |=> can support up to [ 13] logic PT(s) -14| | ? | | S | |=> can support up to [ 12] logic PT(s) + 0| FPU_CS| IO| | S | 2 |=> can support up to [ 7] logic PT(s) + 1|inst_CLK_000_D|NOD| | A | 1 |=> can support up to [ 8] logic PT(s) + 2| SM_AMIGA_1_|NOD| | S | 3 |=> can support up to [ 12] logic PT(s) + 3| | ? | | S | |=> can support up to [ 5] logic PT(s) + 4| BGACK_030| IO| | S | 2 |=> can support up to [ 12] logic PT(s) + 5|inst_CLK_OUT_PRE|NOD| | A | 2 |=> can support up to [ 10] logic PT(s) + 6| CLK_CNT_0_|NOD| | A | 1 |=> can support up to [ 8] logic PT(s) + 7| | ? | | S | |=> can support up to [ 7] logic PT(s) + 8| DSACK_1_| IO| | S | 2 |=> can support up to [ 15] logic PT(s) + 9| SM_AMIGA_7_|NOD| | S | 2 |=> can support up to [ 15] logic PT(s) +10| | ? | | S | |=> can support up to [ 14] logic PT(s) +11| | ? | | S | |=> can support up to [ 14] logic PT(s) +12| DSACK_0_|OUT| | S | 1 |=> can support up to [ 15] logic PT(s) +13| SM_AMIGA_0_|NOD| | S | 3 |=> can support up to [ 19] logic PT(s) +14| | ? | | S | |=> can support up to [ 10] logic PT(s) 15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- =========================================================================== @@ -1666,19 +1780,19 @@ _|_________________|__|__|___|_____|_______________________________________ | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ 0| FPU_CS| IO| | => | 5 6 ( 7) 0 | 80 79 ( 78) 85 - 1| DSACK_0_|OUT| | => |( 5) 6 7 0 |( 80) 79 78 85 - 2|inst_CLK_000_D|NOD| | => | 6 7 0 1 | 79 78 85 84 + 1|inst_CLK_000_D|NOD| | => | 5 6 7 0 | 80 79 78 85 + 2| SM_AMIGA_1_|NOD| | => | 6 7 0 1 | 79 78 85 84 3| | | | => | 6 7 0 1 | 79 78 85 84 4| BGACK_030| IO| | => | 7 0 1 ( 2)| 78 85 84 ( 83) - 5| | | | => | 7 0 1 2 | 78 85 84 83 - 6| | | | => | 0 1 2 3 | 85 84 83 82 + 5|inst_CLK_OUT_PRE|NOD| | => | 7 0 1 2 | 78 85 84 83 + 6| CLK_CNT_0_|NOD| | => | 0 1 2 3 | 85 84 83 82 7| | | | => | 0 1 2 3 | 85 84 83 82 - 8|inst_AS_030_000_SYNC|NOD| | => | 1 2 3 4 | 84 83 82 81 - 9|inst_RISING_CLK_AMIGA|NOD| | => | 1 2 3 4 | 84 83 82 81 + 8| DSACK_1_| IO| | => | 1 2 3 ( 4)| 84 83 82 ( 81) + 9| SM_AMIGA_7_|NOD| | => | 1 2 3 4 | 84 83 82 81 10| | | | => | 2 3 4 5 | 83 82 81 80 11| | | | => | 2 3 4 5 | 83 82 81 80 -12| DSACK_1_| IO| | => | 3 ( 4) 5 6 | 82 ( 81) 80 79 -13|inst_CLK_000_DD|NOD| | => | 3 4 5 6 | 82 81 80 79 +12| DSACK_0_|OUT| | => | 3 4 ( 5) 6 | 82 81 ( 80) 79 +13| SM_AMIGA_0_|NOD| | => | 3 4 5 6 | 82 81 80 79 14| | | | => | 4 5 6 7 | 81 80 79 78 15| | | | => | 4 5 6 7 | 81 80 79 78 --------------------------------------------------------------------------- @@ -1695,8 +1809,8 @@ _|_________________|__|___|_____|___________________________________________ 1| A_23_|INP|*| 84| => | 2 3 4 5 6 7 8 9 2| BGACK_030| IO|*| 83| => | ( 4) 5 6 7 8 9 10 11 3| AS_030|INP|*| 82| => | 6 7 8 9 10 11 12 13 - 4| DSACK_1_| IO|*| 81| => | 8 9 10 11 (12) 13 14 15 - 5| DSACK_0_|OUT|*| 80| => | 10 11 12 13 14 15 0 ( 1) + 4| DSACK_1_| IO|*| 81| => | ( 8) 9 10 11 12 13 14 15 + 5| DSACK_0_|OUT|*| 80| => | 10 11 (12) 13 14 15 0 1 6| SIZE_1_|INP|*| 79| => | 12 13 14 15 0 1 2 3 7| FPU_CS| IO|*| 78| => | 14 15 ( 0) 1 2 3 4 5 --------------------------------------------------------------------------- @@ -1733,27 +1847,27 @@ IMX No. | +---- Block IO Pin or Macrocell Number 0 [IOpin 0 | 85|INP A_22_|*|*] [RegIn 0 |270| -| | ] [MCell 0 |269|NOD RN_FPU_CS| |*] paired w/[ FPU_CS] - [MCell 1 |271|OUT DSACK_0_| | ] + [MCell 1 |271|NOD inst_CLK_000_D| |*] 1 [IOpin 1 | 84|INP A_23_|*|*] [RegIn 1 |273| -| | ] - [MCell 2 |272|NOD inst_CLK_000_D| |*] + [MCell 2 |272|NOD SM_AMIGA_1_| |*] [MCell 3 |274| -| | ] 2 [IOpin 2 | 83| IO BGACK_030|*| ] paired w/[ RN_BGACK_030] [RegIn 2 |276| -| | ] [MCell 4 |275|NOD RN_BGACK_030| |*] paired w/[ BGACK_030] - [MCell 5 |277| -| | ] + [MCell 5 |277|NOD inst_CLK_OUT_PRE| |*] 3 [IOpin 3 | 82|INP AS_030|*|*] [RegIn 3 |279| -| | ] - [MCell 6 |278| -| | ] + [MCell 6 |278|NOD CLK_CNT_0_| |*] [MCell 7 |280| -| | ] 4 [IOpin 4 | 81| IO DSACK_1_|*|*] paired w/[ RN_DSACK_1_] [RegIn 4 |282| -| | ] - [MCell 8 |281|NOD inst_AS_030_000_SYNC| |*] - [MCell 9 |283|NOD inst_RISING_CLK_AMIGA| |*] + [MCell 8 |281|NOD RN_DSACK_1_| |*] paired w/[ DSACK_1_] + [MCell 9 |283|NOD SM_AMIGA_7_| |*] 5 [IOpin 5 | 80|OUT DSACK_0_|*| ] [RegIn 5 |285| -| | ] @@ -1762,8 +1876,8 @@ IMX No. | +---- Block IO Pin or Macrocell Number 6 [IOpin 6 | 79|INP SIZE_1_|*|*] [RegIn 6 |288| -| | ] - [MCell 12 |287|NOD RN_DSACK_1_| |*] paired w/[ DSACK_1_] - [MCell 13 |289|NOD inst_CLK_000_DD| |*] + [MCell 12 |287|OUT DSACK_0_| | ] + [MCell 13 |289|NOD SM_AMIGA_0_| |*] 7 [IOpin 7 | 78| IO FPU_CS|*| ] paired w/[ RN_FPU_CS] [RegIn 7 |291| -| | ] @@ -1779,33 +1893,33 @@ IMX No. | +---- Block IO Pin or Macrocell Number Mux00| Input Pin ( 86)| RST Mux01| IOPin 5 2 ( 58)| FC_1_ Mux02| ... | ... -Mux03| Input Pin ( 11)| CLK_000 -Mux04| IOPin 3 7 ( 28)| BGACK_000 -Mux05| Input Pin ( 14)| CPU_SPACE +Mux03| Mcel 7 8 ( 281)| RN_DSACK_1_ +Mux04| Mcel 7 2 ( 272)| SM_AMIGA_1_ +Mux05| Mcel 7 9 ( 283)| SM_AMIGA_7_ Mux06| IOPin 5 3 ( 57)| FC_0_ -Mux07| Mcel 6 12 ( 263)| inst_CLK_OUT_PRE +Mux07| Mcel 7 6 ( 278)| CLK_CNT_0_ Mux08| IOPin 5 1 ( 59)| A_17_ Mux09| IOPin 7 3 ( 82)| AS_030 -Mux10| ... | ... +Mux10| Mcel 7 1 ( 271)| inst_CLK_000_D Mux11| IOPin 0 5 ( 96)| A_16_ Mux12| IOPin 0 6 ( 97)| A_19_ -Mux13| Mcel 7 8 ( 281)| inst_AS_030_000_SYNC -Mux14| Mcel 7 2 ( 272)| inst_CLK_000_D -Mux15| Mcel 7 12 ( 287)| RN_DSACK_1_ +Mux13| Mcel 6 8 ( 257)| SM_AMIGA_2_ +Mux14| Input Pin ( 11)| CLK_000 +Mux15| Input Pin ( 14)| CPU_SPACE Mux16| ... | ... Mux17| IOPin 0 4 ( 95)| A_18_ -Mux18| ... | ... -Mux19| ... | ... +Mux18| IOPin 3 7 ( 28)| BGACK_000 +Mux19| Mcel 7 13 ( 289)| SM_AMIGA_0_ Mux20| Input Pin ( 64)| CLK_030 Mux21| Input Pin ( 61)| CLK_OSZI -Mux22| Mcel 6 5 ( 253)| SM_AMIGA_1_ +Mux22| ... | ... Mux23| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux24| ... | ... +Mux24| Mcel 3 5 ( 181)| RN_AS_000 Mux25| ... | ... Mux26| ... | ... -Mux27| Mcel 7 9 ( 283)| inst_RISING_CLK_AMIGA +Mux27| Mcel 7 5 ( 277)| inst_CLK_OUT_PRE Mux28| ... | ... -Mux29| ... | ... +Mux29| Mcel 3 13 ( 193)| inst_CLK_000_DD Mux30| Mcel 7 0 ( 269)| RN_FPU_CS Mux31| ... | ... Mux32| ... | ... diff --git a/Logic/68030_tk.rpt b/Logic/68030_tk.rpt index 5cec7a8..cddfa87 100644 --- a/Logic/68030_tk.rpt +++ b/Logic/68030_tk.rpt @@ -12,7 +12,7 @@ Project_Summary Project Name : 68030_tk Project Path : C:\Users\Matze\Documents\GitHub\68030tk\Logic -Project Fitted on : Thu May 15 22:21:57 2014 +Project Fitted on : Thu May 15 23:02:50 2014 Device : M4A5-128/64 Package : 100TQFP @@ -40,8 +40,8 @@ Design_Summary Total Input Pins : 35 Total Output Pins : 22 Total Bidir I/O Pins : 2 - Total Flip-Flops : 40 - Total Product Terms : 104 + Total Flip-Flops : 35 + Total Product Terms : 102 Total Reserved Pins : 0 Total Reserved Blocks : 0 @@ -54,13 +54,13 @@ Dedicated Pins Input-Only Pins 2 2 0 --> 100% Clock/Input Pins 4 4 0 --> 100% I/O Pins 64 53 11 --> 82% -Logic Macrocells 128 48 80 --> 37% +Logic Macrocells 128 43 85 --> 33% Input Registers 64 0 64 --> 0% Unusable Macrocells .. 0 .. -CSM Outputs/Total Block Inputs 264 118 146 --> 44% -Logical Product Terms 640 105 535 --> 16% -Product Term Clusters 128 33 95 --> 25% +CSM Outputs/Total Block Inputs 264 119 145 --> 45% +Logical Product Terms 640 103 537 --> 16% +Product Term Clusters 128 37 91 --> 28%  Blocks_Resource_Summary @@ -71,14 +71,14 @@ Blocks_Resource_Summary --------------------------------------------------------------------------------- Maximum 33 8 8 -- -- 16 80 16 - --------------------------------------------------------------------------------- -Block A 12 7 0 2 0 14 3 15 Hi -Block B 18 8 0 7 0 9 13 11 Hi +Block A 7 7 0 2 0 14 3 15 Hi +Block B 11 8 0 5 0 11 11 13 Hi Block C 1 8 0 2 0 14 2 16 Hi -Block D 33 8 0 10 0 6 36 5 Hi +Block D 29 8 0 12 0 4 44 3 Hi Block E 14 3 0 3 0 13 3 16 Hi -Block F 0 4 0 0 0 16 0 16 Hi -Block G 19 7 0 16 0 0 34 7 Hi -Block H 21 8 0 8 0 8 14 12 Hi +Block F 12 4 0 1 0 15 4 15 Hi +Block G 20 7 0 8 0 8 17 10 Hi +Block H 25 8 0 10 0 6 19 9 Hi --------------------------------------------------------------------------------- Four rightmost columns above reflect last status of the placement process. @@ -287,12 +287,12 @@ Input_Signal_List Pin r e O Input Pin Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- - 82 H . I/O AB-D---H Hi Fast AS_030 + 82 H . I/O ---D-FGH Hi Fast AS_030 69 G . I/O ---D---- Hi Fast A_0_ - 96 A . I/O -------H Hi Fast A_16_ - 59 F . I/O -------H Hi Fast A_17_ - 95 A . I/O -------H Hi Fast A_18_ - 97 A . I/O -------H Hi Fast A_19_ + 96 A . I/O -----F-H Hi Fast A_16_ + 59 F . I/O -----F-H Hi Fast A_17_ + 95 A . I/O -----F-H Hi Fast A_18_ + 97 A . I/O -----F-H Hi Fast A_19_ 93 A . I/O ----E--- Hi Fast A_20_ 94 A . I/O ----E--- Hi Fast A_21_ 85 H . I/O ----E--- Hi Fast A_22_ @@ -305,11 +305,11 @@ Pin Blk PTs Type e s E Fanout Pwr Slew Signal 6 B . I/O ----E--- Hi Fast A_29_ 5 B . I/O ----E--- Hi Fast A_30_ 4 B . I/O ----E--- Hi Fast A_31_ - 28 D . I/O -------H Hi Fast BGACK_000 + 28 D . I/O -----F-H Hi Fast BGACK_000 21 C . I/O ---D---- Hi Fast BG_030 98 A . I/O ---D---- Hi Fast DS_030 - 57 F . I/O -------H Hi Fast FC_0_ - 58 F . I/O -------H Hi Fast FC_1_ + 57 F . I/O -----F-H Hi Fast FC_0_ + 58 F . I/O -----F-H Hi Fast FC_1_ 67 G . I/O -B------ Hi Fast IPL_0_ 56 F . I/O -B------ Hi Fast IPL_1_ 68 G . I/O -B------ Hi Fast IPL_2_ @@ -317,11 +317,11 @@ Pin Blk PTs Type e s E Fanout Pwr Slew Signal 70 G . I/O ---D---- Hi Fast SIZE_0_ 79 H . I/O ---D---- Hi Fast SIZE_1_ 11 . . Ck/I -------H - Fast CLK_000 - 14 . . Ck/I ---D---H - Fast CPU_SPACE + 14 . . Ck/I ---D-F-H - Fast CPU_SPACE 36 . . Ded ------G- - Fast VPA - 61 . . Ck/I AB-D--GH - Fast CLK_OSZI - 64 . . Ck/I ---D---H - Fast CLK_030 - 86 . . Ded AB-D--GH - Fast RST + 61 . . Ck/I AB-D-FGH - Fast CLK_OSZI + 64 . . Ck/I ---D-F-H - Fast CLK_030 + 86 . . Ded AB-D-FGH - Fast RST ---------------------------------------------------------------------- Power : Hi = High @@ -352,9 +352,9 @@ Pin Blk PTs Type e s E Fanout Pwr Slew Signal 80 H 1 COM -------- Hi Fast DSACK_0_ 66 G 3 TFF * * -------- Hi Fast E 78 H 2 DFF * * -------- Hi Fast FPU_CS - 8 B 2 DFF * * -------- Hi Fast IPL_030_0_ - 7 B 2 DFF * * -------- Hi Fast IPL_030_1_ - 9 B 2 DFF * * -------- Hi Fast IPL_030_2_ + 8 B 3 DFF * * -------- Hi Fast IPL_030_0_ + 7 B 3 DFF * * -------- Hi Fast IPL_030_1_ + 9 B 3 DFF * * -------- Hi Fast IPL_030_2_ 31 D 12 DFF * * -------- Hi Fast LDS_000 3 B 1 DFF * * -------- Hi Fast RESET 32 D 8 DFF * * -------- Hi Fast UDS_000 @@ -375,7 +375,7 @@ Bidir_Signal_List Pin Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- 81 H 2 DFF * * ---D---- Hi Fast DSACK_1_ - 30 D 1 DFF * * -B------ Hi Fast DTACK + 30 D 1 DFF * * ------G- Hi Fast DTACK ---------------------------------------------------------------------- Power : Hi = High @@ -391,42 +391,37 @@ Buried_Signal_List Pin r e O Node #Mc Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- - G14 G 1 DFF * * ------G- Hi Fast CLK_CNT_0_ - D9 D 2 DFF * * ---D--G- Hi - RN_AS_000 --> AS_000 + H6 H 1 DFF * * -------H Hi Fast CLK_CNT_0_ + D5 D 2 DFF * * ---D---H Hi - RN_AS_000 --> AS_000 H4 H 2 DFF * * ---D---H Hi - RN_BGACK_030 --> BGACK_030 D1 D 3 DFF * * ---D---- Hi - RN_BG_000 --> BG_000 - H12 H 2 DFF * * -------H Hi - RN_DSACK_1_ --> DSACK_1_ - G2 G 3 TFF * * A--D--G- Hi - RN_E --> E + H8 H 2 DFF * * -------H Hi - RN_DSACK_1_ --> DSACK_1_ + G4 G 3 TFF * * ---D--G- Hi - RN_E --> E H0 H 2 DFF * * --C-E--H Hi - RN_FPU_CS --> FPU_CS - B8 B 2 DFF * * -B------ Hi - RN_IPL_030_0_ --> IPL_030_0_ - B12 B 2 DFF * * -B------ Hi - RN_IPL_030_1_ --> IPL_030_1_ - B4 B 2 DFF * * -B------ Hi - RN_IPL_030_2_ --> IPL_030_2_ + B8 B 3 DFF * * -B------ Hi - RN_IPL_030_0_ --> IPL_030_0_ + B12 B 3 DFF * * -B------ Hi - RN_IPL_030_1_ --> IPL_030_1_ + B4 B 3 DFF * * -B------ Hi - RN_IPL_030_2_ --> IPL_030_2_ D8 D 12 DFF * * ---D---- Hi - RN_LDS_000 --> LDS_000 D12 D 8 DFF * * ---D---- Hi - RN_UDS_000 --> UDS_000 - D5 D 2 TFF * * A--D---- Hi - RN_VMA --> VMA - G13 G 3 DFF * * ------G- Hi Fast SM_AMIGA_0_ - G5 G 3 DFF * * ------GH Hi Fast SM_AMIGA_1_ - G10 G 3 DFF * * ------G- Hi Fast SM_AMIGA_2_ - B5 B 3 DFF * * AB----G- Hi Fast SM_AMIGA_3_ - D13 D 2 DFF * * -B-D---- Hi Fast SM_AMIGA_4_ - D10 D 2 DFF * * ---D---- Hi Fast SM_AMIGA_5_ - D6 D 3 DFF * * ---D---- Hi Fast SM_AMIGA_6_ - G9 G 2 DFF * * ---D--G- Hi Fast SM_AMIGA_7_ - G8 G 3 DFF * * A--D--G- Hi Fast cpu_est_0_ - G6 G 4 TFF * * A--D--G- Hi Fast cpu_est_1_ - G4 G 3 DFF * * A--D--G- Hi Fast cpu_est_2_ - G15 G 1 DFF * * ---D---- Hi Fast cpu_est_d_0_ - G7 G 1 DFF * * ---D---- Hi Fast cpu_est_d_1_ - G3 G 1 DFF * * ---D---- Hi Fast cpu_est_d_2_ - G11 G 1 DFF * * ---D---- Hi Fast cpu_est_d_3_ - H8 H 4 DFF * * ---D---H Hi Fast inst_AS_030_000_SYNC - H2 H 1 DFF * * AB-D--GH Hi Fast inst_CLK_000_D - H13 H 1 DFF * * ---D--G- Hi Fast inst_CLK_000_DD - G12 G 2 DFF * * -B----GH Hi Fast inst_CLK_OUT_PRE - B9 B 2 DFF * * -B----G- Hi Fast inst_DTACK_SYNC - H9 H 1 DFF * * -B-----H Hi Fast inst_RISING_CLK_AMIGA - G1 G 1 DFF * * AB-D---- Hi Fast inst_VPA_D - A0 A 2 DFF * * AB----G- Hi Fast inst_VPA_SYNC + D4 D 2 TFF * * ---D--G- Hi - RN_VMA --> VMA + H13 H 3 DFF * * -------H Hi Fast SM_AMIGA_0_ + H2 H 3 DFF * * -------H Hi Fast SM_AMIGA_1_ + G8 G 3 DFF * * ------GH Hi Fast SM_AMIGA_2_ + G5 G 3 DFF * * ------G- Hi Fast SM_AMIGA_3_ + G12 G 2 DFF * * ---D--G- Hi Fast SM_AMIGA_4_ + A0 A 2 DFF * * A-----G- Hi Fast SM_AMIGA_5_ + D6 D 3 DFF * * A--D---- Hi Fast SM_AMIGA_6_ + H9 H 2 DFF * * ---D---H Hi Fast SM_AMIGA_7_ + D14 D 3 DFF * * ---D--G- Hi Fast cpu_est_0_ + D2 D 4 TFF * * ---D--G- Hi Fast cpu_est_1_ + D10 D 3 DFF * * ---D--G- Hi Fast cpu_est_2_ + F0 F 4 DFF * * A--D-F-- Hi Fast inst_AS_030_000_SYNC + H1 H 1 DFF * * AB-D--GH Hi Fast inst_CLK_000_D + D13 D 1 DFF * * AB-D--GH Hi Fast inst_CLK_000_DD + H5 H 2 DFF * * -B----GH Hi Fast inst_CLK_OUT_PRE + G13 G 2 DFF * * ------G- Hi Fast inst_DTACK_SYNC + G1 G 1 DFF * * ---D--G- Hi Fast inst_VPA_D + G9 G 2 DFF * * ------G- Hi Fast inst_VPA_SYNC ---------------------------------------------------------------------- Power : Hi = High @@ -441,109 +436,105 @@ Signals_Fanout_List ~~~~~~~~~~~~~~~~~~~ Signal Source : Fanout List ----------------------------------------------------------------------------- - A_28_{ D}: CIIN{ E} - A_27_{ D}: CIIN{ E} - SIZE_1_{ I}: LDS_000{ D} - A_26_{ D}: CIIN{ E} - A_25_{ D}: CIIN{ E} - A_31_{ C}: CIIN{ E} - A_24_{ D}: CIIN{ E} - A_23_{ I}: CIIN{ E} - A_22_{ I}: CIIN{ E} A_21_{ B}: CIIN{ E} - IPL_2_{ H}: IPL_030_2_{ B} A_20_{ B}: CIIN{ E} - A_19_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} - A_18_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} - A_17_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} - FC_1_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} - A_16_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} + SIZE_1_{ I}: LDS_000{ D} + A_19_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ F} + A_18_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ F} + A_31_{ C}: CIIN{ E} + A_17_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ F} + A_16_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ F} + IPL_2_{ H}: IPL_030_2_{ B} + FC_1_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ F} AS_030{ I}: DSACK_1_{ H} AS_000{ D} UDS_000{ D} : LDS_000{ D} BG_000{ D} FPU_CS{ H} - :inst_AS_030_000_SYNC{ H}inst_DTACK_SYNC{ B} inst_VPA_SYNC{ A} + :inst_AS_030_000_SYNC{ F}inst_DTACK_SYNC{ G} inst_VPA_SYNC{ G} DS_030{ B}: UDS_000{ D} LDS_000{ D} CPU_SPACE{. }: DSACK_0_{ H} DSACK_1_{ H} BG_000{ D} - :inst_AS_030_000_SYNC{ H} + :inst_AS_030_000_SYNC{ F} BG_030{ D}: BG_000{ D} - BGACK_000{ E}: BGACK_030{ H} FPU_CS{ H}inst_AS_030_000_SYNC{ H} - CLK_030{. }: BG_000{ D} FPU_CS{ H}inst_AS_030_000_SYNC{ H} - CLK_000{. }: inst_CLK_000_D{ H}inst_RISING_CLK_AMIGA{ H} A_0_{ H}: UDS_000{ D} LDS_000{ D} + BGACK_000{ E}: BGACK_030{ H} FPU_CS{ H}inst_AS_030_000_SYNC{ F} + CLK_030{. }: BG_000{ D} FPU_CS{ H}inst_AS_030_000_SYNC{ F} IPL_1_{ G}: IPL_030_1_{ B} + CLK_000{. }: inst_CLK_000_D{ H} IPL_0_{ H}: IPL_030_0_{ B} + FC_0_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ F} VPA{. }: inst_VPA_D{ G} - FC_0_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} RST{. }: IPL_030_2_{ B} DSACK_1_{ H} AS_000{ D} : UDS_000{ D} LDS_000{ D} BG_000{ D} - : BGACK_030{ H} FPU_CS{ H} IPL_030_1_{ B} - : DTACK{ D} IPL_030_0_{ B} VMA{ D} - : RESET{ B}inst_AS_030_000_SYNC{ H}inst_DTACK_SYNC{ B} - : inst_VPA_SYNC{ A} SM_AMIGA_6_{ D} SM_AMIGA_7_{ G} - : SM_AMIGA_1_{ G} SM_AMIGA_4_{ D} SM_AMIGA_3_{ B} - : SM_AMIGA_5_{ D} SM_AMIGA_2_{ G} SM_AMIGA_0_{ G} + : BGACK_030{ H} IPL_030_1_{ B} IPL_030_0_{ B} + : FPU_CS{ H} DTACK{ D} VMA{ D} + : RESET{ B}inst_AS_030_000_SYNC{ F}inst_DTACK_SYNC{ G} + : inst_VPA_SYNC{ G} SM_AMIGA_6_{ D} SM_AMIGA_7_{ H} + : SM_AMIGA_1_{ H} SM_AMIGA_4_{ G} SM_AMIGA_3_{ G} + : SM_AMIGA_5_{ A} SM_AMIGA_2_{ G} SM_AMIGA_0_{ H} RW{ H}:AMIGA_BUS_DATA_DIR{ E} UDS_000{ D} LDS_000{ D} SIZE_0_{ H}: LDS_000{ D} A_30_{ C}: CIIN{ E} A_29_{ C}: CIIN{ E} + A_28_{ D}: CIIN{ E} + A_27_{ D}: CIIN{ E} + A_26_{ D}: CIIN{ E} + A_25_{ D}: CIIN{ E} + A_24_{ D}: CIIN{ E} + A_23_{ I}: CIIN{ E} + A_22_{ I}: CIIN{ E} RN_IPL_030_2_{ C}: IPL_030_2_{ B} DSACK_1_{ I}: DTACK{ D} RN_DSACK_1_{ I}: DSACK_1_{ H} RN_AS_000{ E}: AS_000{ D} DTACK{ D} VMA{ D} - : SM_AMIGA_7_{ G} SM_AMIGA_0_{ G} + : SM_AMIGA_7_{ H} SM_AMIGA_0_{ H} RN_UDS_000{ E}: UDS_000{ D} RN_LDS_000{ E}: LDS_000{ D} RN_BG_000{ E}: BG_000{ D} RN_BGACK_030{ I}: AS_000{ D} UDS_000{ D} LDS_000{ D} : BGACK_030{ H} DTACK{ D} - RN_FPU_CS{ I}: BERR{ E} AVEC_EXP{ C} FPU_CS{ H} RN_IPL_030_1_{ C}: IPL_030_1_{ B} - DTACK{ E}:inst_DTACK_SYNC{ B} RN_IPL_030_0_{ C}: IPL_030_0_{ B} - RN_E{ H}: E{ G} VMA{ D} cpu_est_1_{ G} - : cpu_est_d_3_{ G} inst_VPA_SYNC{ A} cpu_est_2_{ G} - RN_VMA{ E}: VMA{ D} inst_VPA_SYNC{ A} - cpu_est_0_{ H}: E{ G} VMA{ D} cpu_est_0_{ G} - : cpu_est_1_{ G} cpu_est_d_0_{ G} inst_VPA_SYNC{ A} - : cpu_est_2_{ G} - cpu_est_1_{ H}: E{ G} VMA{ D} cpu_est_1_{ G} - : inst_VPA_SYNC{ A} cpu_est_d_1_{ G} cpu_est_2_{ G} -cpu_est_d_0_{ H}: VMA{ D} -cpu_est_d_3_{ H}: VMA{ D} -inst_AS_030_000_SYNC{ I}: AS_000{ D} UDS_000{ D} LDS_000{ D} - :inst_AS_030_000_SYNC{ H} SM_AMIGA_6_{ D} SM_AMIGA_5_{ D} -inst_DTACK_SYNC{ C}:inst_DTACK_SYNC{ B} SM_AMIGA_3_{ B} SM_AMIGA_2_{ G} - inst_VPA_D{ H}: VMA{ D}inst_DTACK_SYNC{ B} inst_VPA_SYNC{ A} -inst_VPA_SYNC{ B}: inst_VPA_SYNC{ A} SM_AMIGA_3_{ B} SM_AMIGA_2_{ G} -inst_CLK_000_D{ I}: DSACK_1_{ H} AS_000{ D} UDS_000{ D} - : LDS_000{ D} E{ G} VMA{ D} - : cpu_est_0_{ G} cpu_est_1_{ G}inst_DTACK_SYNC{ B} - : inst_VPA_SYNC{ A}inst_CLK_000_DD{ H} cpu_est_2_{ G} - : SM_AMIGA_6_{ D} SM_AMIGA_7_{ G}inst_RISING_CLK_AMIGA{ H} - : SM_AMIGA_1_{ G} SM_AMIGA_4_{ D} SM_AMIGA_3_{ B} - : SM_AMIGA_5_{ D} SM_AMIGA_2_{ G} SM_AMIGA_0_{ G} -inst_CLK_000_DD{ I}: AS_000{ D} UDS_000{ D} LDS_000{ D} - : E{ G} cpu_est_0_{ G} cpu_est_1_{ G} - : cpu_est_2_{ G} SM_AMIGA_6_{ D} SM_AMIGA_5_{ D} -inst_CLK_OUT_PRE{ H}: CLK_DIV_OUT{ G} DSACK_1_{ H} CLK_EXP{ B} - :inst_CLK_OUT_PRE{ G} SM_AMIGA_1_{ G} SM_AMIGA_0_{ G} -cpu_est_d_1_{ H}: VMA{ D} -cpu_est_d_2_{ H}: VMA{ D} - cpu_est_2_{ H}: E{ G} VMA{ D} cpu_est_1_{ G} - : inst_VPA_SYNC{ A} cpu_est_d_2_{ G} cpu_est_2_{ G} - CLK_CNT_0_{ H}:inst_CLK_OUT_PRE{ G} CLK_CNT_0_{ G} + RN_FPU_CS{ I}: BERR{ E} AVEC_EXP{ C} FPU_CS{ H} + DTACK{ E}:inst_DTACK_SYNC{ G} + RN_E{ H}: E{ G} VMA{ D} cpu_est_1_{ D} + : inst_VPA_SYNC{ G} cpu_est_2_{ D} + RN_VMA{ E}: VMA{ D} inst_VPA_SYNC{ G} + cpu_est_0_{ E}: E{ G} VMA{ D} cpu_est_0_{ D} + : cpu_est_1_{ D} inst_VPA_SYNC{ G} cpu_est_2_{ D} + cpu_est_1_{ E}: E{ G} VMA{ D} cpu_est_1_{ D} + : inst_VPA_SYNC{ G} cpu_est_2_{ D} +inst_AS_030_000_SYNC{ G}: AS_000{ D} UDS_000{ D} LDS_000{ D} + :inst_AS_030_000_SYNC{ F} SM_AMIGA_6_{ D} SM_AMIGA_5_{ A} +inst_DTACK_SYNC{ H}:inst_DTACK_SYNC{ G} SM_AMIGA_3_{ G} SM_AMIGA_2_{ G} + inst_VPA_D{ H}: VMA{ D}inst_DTACK_SYNC{ G} inst_VPA_SYNC{ G} +inst_VPA_SYNC{ H}: inst_VPA_SYNC{ G} SM_AMIGA_3_{ G} SM_AMIGA_2_{ G} +inst_CLK_000_D{ I}: IPL_030_2_{ B} DSACK_1_{ H} AS_000{ D} + : UDS_000{ D} LDS_000{ D} BGACK_030{ H} + : IPL_030_1_{ B} IPL_030_0_{ B} E{ G} + : VMA{ D} cpu_est_0_{ D} cpu_est_1_{ D} + :inst_DTACK_SYNC{ G} inst_VPA_SYNC{ G}inst_CLK_000_DD{ D} + : cpu_est_2_{ D} SM_AMIGA_6_{ D} SM_AMIGA_7_{ H} + : SM_AMIGA_1_{ H} SM_AMIGA_4_{ G} SM_AMIGA_3_{ G} + : SM_AMIGA_5_{ A} SM_AMIGA_2_{ G} SM_AMIGA_0_{ H} +inst_CLK_000_DD{ E}: IPL_030_2_{ B} AS_000{ D} UDS_000{ D} + : LDS_000{ D} BGACK_030{ H} IPL_030_1_{ B} + : IPL_030_0_{ B} E{ G} cpu_est_0_{ D} + : cpu_est_1_{ D} cpu_est_2_{ D} SM_AMIGA_6_{ D} + : SM_AMIGA_5_{ A} +inst_CLK_OUT_PRE{ I}: CLK_DIV_OUT{ G} DSACK_1_{ H} CLK_EXP{ B} + :inst_CLK_OUT_PRE{ H} SM_AMIGA_1_{ H} SM_AMIGA_0_{ H} + cpu_est_2_{ E}: E{ G} VMA{ D} cpu_est_1_{ D} + : inst_VPA_SYNC{ G} cpu_est_2_{ D} + CLK_CNT_0_{ I}:inst_CLK_OUT_PRE{ H} CLK_CNT_0_{ H} SM_AMIGA_6_{ E}: AS_000{ D} UDS_000{ D} LDS_000{ D} - : BG_000{ D} SM_AMIGA_6_{ D} SM_AMIGA_5_{ D} -SM_AMIGA_7_{ H}: BG_000{ D} SM_AMIGA_6_{ D} SM_AMIGA_7_{ G} -inst_RISING_CLK_AMIGA{ I}: IPL_030_2_{ B} BGACK_030{ H} IPL_030_1_{ B} - : IPL_030_0_{ B} -SM_AMIGA_1_{ H}: DSACK_1_{ H} SM_AMIGA_1_{ G} SM_AMIGA_0_{ G} -SM_AMIGA_4_{ E}: UDS_000{ D} LDS_000{ D} SM_AMIGA_4_{ D} - : SM_AMIGA_3_{ B} -SM_AMIGA_3_{ C}:inst_DTACK_SYNC{ B} inst_VPA_SYNC{ A} SM_AMIGA_3_{ B} + : BG_000{ D} SM_AMIGA_6_{ D} SM_AMIGA_5_{ A} +SM_AMIGA_7_{ I}: BG_000{ D} SM_AMIGA_6_{ D} SM_AMIGA_7_{ H} +SM_AMIGA_1_{ I}: DSACK_1_{ H} SM_AMIGA_1_{ H} SM_AMIGA_0_{ H} +SM_AMIGA_4_{ H}: UDS_000{ D} LDS_000{ D} SM_AMIGA_4_{ G} + : SM_AMIGA_3_{ G} +SM_AMIGA_3_{ H}:inst_DTACK_SYNC{ G} inst_VPA_SYNC{ G} SM_AMIGA_3_{ G} : SM_AMIGA_2_{ G} -SM_AMIGA_5_{ E}: SM_AMIGA_4_{ D} SM_AMIGA_5_{ D} -SM_AMIGA_2_{ H}: SM_AMIGA_1_{ G} SM_AMIGA_2_{ G} -SM_AMIGA_0_{ H}: SM_AMIGA_7_{ G} SM_AMIGA_0_{ G} +SM_AMIGA_5_{ B}: SM_AMIGA_4_{ G} SM_AMIGA_5_{ A} +SM_AMIGA_2_{ H}: SM_AMIGA_1_{ H} SM_AMIGA_2_{ G} +SM_AMIGA_0_{ I}: SM_AMIGA_7_{ H} SM_AMIGA_0_{ H} ----------------------------------------------------------------------------- {.} : Indicates block location of signal @@ -553,18 +544,18 @@ Set_Reset_Summary ~~~~~~~~~~~~~~~~~ Block A -block level set pt : !RST -block level reset pt : GND +block level set pt : GND +block level reset pt : !RST Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ | | | | | AVEC -| * | S | BS | BR | inst_VPA_SYNC -| | | | | DS_030 +| * | S | BS | BR | SM_AMIGA_5_ | | | | | A_19_ | | | | | A_16_ | | | | | A_18_ +| | | | | DS_030 | | | | | A_21_ | | | | | A_20_ @@ -581,8 +572,6 @@ Equations : | * | S | BS | BR | IPL_030_1_ | * | A | | | CLK_EXP | * | A | | | RESET -| * | S | BR | BS | SM_AMIGA_3_ -| * | S | BS | BR | inst_DTACK_SYNC | * | S | BS | BR | RN_IPL_030_0_ | * | S | BS | BR | RN_IPL_030_1_ | * | S | BS | BR | RN_IPL_030_2_ @@ -622,14 +611,16 @@ Equations : | * | S | BS | BR | VMA | * | S | BS | BR | AS_000 | | | | | AMIGA_BUS_ENABLE +| * | A | | | inst_CLK_000_DD +| * | A | | | cpu_est_1_ +| * | S | BR | BS | SM_AMIGA_6_ +| * | A | | | cpu_est_2_ +| * | A | | | cpu_est_0_ | * | S | BS | BR | RN_VMA | * | S | BS | BR | RN_AS_000 -| * | S | BR | BS | SM_AMIGA_4_ | * | S | BS | BR | RN_LDS_000 | * | S | BS | BR | RN_UDS_000 | * | S | BS | BR | RN_BG_000 -| * | S | BR | BS | SM_AMIGA_6_ -| * | S | BR | BS | SM_AMIGA_5_ | | | | | BGACK_000 @@ -646,12 +637,13 @@ Equations : Block F -block level set pt : -block level reset pt : +block level set pt : !RST +block level reset pt : GND Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ +| * | S | BS | BR | inst_AS_030_000_SYNC | | | | | A_17_ | | | | | FC_1_ | | | | | FC_0_ @@ -667,21 +659,13 @@ Equations : +-----+-----+-----+-----+------------------------ | * | S | BS | BR | E | * | S | BS | BR | CLK_DIV_OUT -| * | S | BS | BR | cpu_est_1_ | * | S | BS | BR | RN_E -| * | S | BS | BR | cpu_est_2_ -| * | S | BS | BR | cpu_est_0_ -| * | S | BS | BR | inst_CLK_OUT_PRE -| * | S | BS | BR | inst_VPA_D -| * | A | | | SM_AMIGA_1_ -| * | A | | | SM_AMIGA_7_ -| * | A | | | SM_AMIGA_0_ | * | A | | | SM_AMIGA_2_ -| * | S | BS | BR | CLK_CNT_0_ -| * | S | BS | BR | cpu_est_d_2_ -| * | S | BS | BR | cpu_est_d_1_ -| * | S | BS | BR | cpu_est_d_3_ -| * | S | BS | BR | cpu_est_d_0_ +| * | A | | | SM_AMIGA_4_ +| * | S | BS | BR | inst_VPA_D +| * | A | | | SM_AMIGA_3_ +| * | A | | | inst_VPA_SYNC +| * | A | | | inst_DTACK_SYNC | | | | | RW | | | | | SIZE_0_ | | | | | A_0_ @@ -702,11 +686,13 @@ Equations : | | | | | DSACK_0_ | * | A | | | inst_CLK_000_D | * | S | BS | BR | RN_FPU_CS -| * | S | BS | BR | inst_AS_030_000_SYNC +| * | A | | | inst_CLK_OUT_PRE | * | S | BS | BR | RN_BGACK_030 -| * | A | | | inst_RISING_CLK_AMIGA -| * | A | | | inst_CLK_000_DD +| * | S | BS | BR | SM_AMIGA_7_ +| * | S | BR | BS | SM_AMIGA_0_ +| * | S | BR | BS | SM_AMIGA_1_ | * | S | BS | BR | RN_DSACK_1_ +| * | A | | | CLK_CNT_0_ | | | | | AS_030 | | | | | A_22_ | | | | | A_23_ @@ -728,22 +714,22 @@ BLOCK_A_LOGIC_ARRAY_FANIN CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ mx A0 RST pin 86 mx A17 ... ... -mx A1 ... ... mx A18 ... ... -mx A2 cpu_est_2_ mcell G4 mx A19 ... ... +mx A1 inst_CLK_000_DD mcell D13 mx A18 ... ... +mx A2 ... ... mx A19 ... ... mx A3 ... ... mx A20 ... ... mx A4 CLK_OSZI pin 61 mx A21 ... ... -mx A5 cpu_est_1_ mcell G6 mx A22 ... ... -mx A6 ... ... mx A23 RN_E mcell G2 -mx A7 RN_VMA mcell D5 mx A24 inst_VPA_D mcell G1 +mx A5inst_AS_030_000_SYNC mcell F0 mx A22 ... ... +mx A6 ... ... mx A23 ... ... +mx A7 ... ... mx A24 ... ... mx A8 ... ... mx A25 ... ... -mx A9 AS_030 pin 82 mx A26 ... ... -mx A10 cpu_est_0_ mcell G8 mx A27 ... ... -mx A11 ... ... mx A28 SM_AMIGA_3_ mcell B5 +mx A9 ... ... mx A26 ... ... +mx A10 inst_CLK_000_D mcell H1 mx A27 ... ... +mx A11 ... ... mx A28 ... ... mx A12 ... ... mx A29 ... ... mx A13 ... ... mx A30 ... ... -mx A14 inst_CLK_000_D mcell H2 mx A31 ... ... -mx A15 inst_VPA_SYNC mcell A0 mx A32 ... ... -mx A16 ... ... +mx A14 ... ... mx A31 ... ... +mx A15 SM_AMIGA_5_ mcell A0 mx A32 ... ... +mx A16 SM_AMIGA_6_ mcell D6 ---------------------------------------------------------------------------- @@ -752,21 +738,21 @@ BLOCK_B_LOGIC_ARRAY_FANIN CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ mx B0 IPL_0_ pin 67 mx B17 ... ... -mx B1 SM_AMIGA_4_ mcell D13 mx B18 ... ... +mx B1 inst_CLK_000_DD mcell D13 mx B18 ... ... mx B2 ... ... mx B19 ... ... mx B3 IPL_1_ pin 56 mx B20 ... ... mx B4 IPL_2_ pin 68 mx B21 RST pin 86 -mx B5inst_RISING_CLK_AMIGA mcell H9 mx B22 ... ... -mx B6 inst_DTACK_SYNC mcell B9 mx B23 DTACK pin 30 -mx B7inst_CLK_OUT_PRE mcell G12 mx B24 inst_VPA_D mcell G1 +mx B5 ... ... mx B22 ... ... +mx B6 ... ... mx B23 ... ... +mx B7 ... ... mx B24 ... ... mx B8 RN_IPL_030_0_ mcell B8 mx B25 ... ... -mx B9 AS_030 pin 82 mx B26 ... ... -mx B10 ... ... mx B27 RN_IPL_030_2_ mcell B4 -mx B11 ... ... mx B28 SM_AMIGA_3_ mcell B5 +mx B9 ... ... mx B26 ... ... +mx B10 inst_CLK_000_D mcell H1 mx B27 RN_IPL_030_2_ mcell B4 +mx B11 ... ... mx B28 ... ... mx B12 RN_IPL_030_1_ mcell B12 mx B29 CLK_OSZI pin 61 -mx B13 ... ... mx B30 ... ... -mx B14 inst_CLK_000_D mcell H2 mx B31 ... ... -mx B15 inst_VPA_SYNC mcell A0 mx B32 ... ... +mx B13inst_CLK_OUT_PRE mcell H5 mx B30 ... ... +mx B14 ... ... mx B31 ... ... +mx B15 ... ... mx B32 ... ... mx B16 ... ... ---------------------------------------------------------------------------- @@ -799,23 +785,23 @@ BLOCK_D_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx D0 A_0_ pin 69 mx D17 RN_BG_000 mcell D1 -mx D1 SM_AMIGA_4_ mcell D13 mx D18 cpu_est_d_0_ mcell G15 -mx D2 cpu_est_2_ mcell G4 mx D19 AS_030 pin 82 -mx D3inst_AS_030_000_SYNC mcell H8 mx D20 SM_AMIGA_5_ mcell D10 -mx D4 inst_CLK_000_D mcell H2 mx D21 RST pin 86 -mx D5 RN_UDS_000 mcell D12 mx D22 BG_030 pin 21 +mx D0 SIZE_0_ pin 70 mx D17 RN_BG_000 mcell D1 +mx D1 inst_CLK_000_DD mcell D13 mx D18 A_0_ pin 69 +mx D2 RN_E mcell G4 mx D19 ... ... +mx D3 cpu_est_1_ mcell D2 mx D20 cpu_est_2_ mcell D10 +mx D4 inst_VPA_D mcell G1 mx D21 RN_VMA mcell D4 +mx D5 DS_030 pin 98 mx D22 BG_030 pin 21 mx D6 SIZE_1_ pin 79 mx D23 RN_BGACK_030 mcell H4 -mx D7 inst_CLK_000_DD mcell H13 mx D24 inst_VPA_D mcell G1 -mx D8 RW pin 71 mx D25 RN_AS_000 mcell D9 -mx D9 cpu_est_d_3_ mcell G11 mx D26 cpu_est_d_1_ mcell G7 -mx D10 DSACK_1_ pin 81 mx D27 SM_AMIGA_7_ mcell G9 -mx D11 RN_VMA mcell D5 mx D28 CLK_030 pin 64 -mx D12 DS_030 pin 98 mx D29 cpu_est_1_ mcell G6 -mx D13 cpu_est_0_ mcell G8 mx D30 cpu_est_d_2_ mcell G3 -mx D14 SIZE_0_ pin 70 mx D31 RN_E mcell G2 -mx D15 CPU_SPACE pin 14 mx D32 RN_LDS_000 mcell D8 -mx D16 SM_AMIGA_6_ mcell D6 +mx D7 RN_AS_000 mcell D5 mx D24 RST pin 86 +mx D8 RW pin 71 mx D25inst_AS_030_000_SYNC mcell F0 +mx D9 AS_030 pin 82 mx D26 ... ... +mx D10 cpu_est_0_ mcell D14 mx D27 SM_AMIGA_7_ mcell H9 +mx D11 RN_UDS_000 mcell D12 mx D28 CLK_030 pin 64 +mx D12 inst_CLK_000_D mcell H1 mx D29 CLK_OSZI pin 61 +mx D13 ... ... mx D30 SM_AMIGA_6_ mcell D6 +mx D14 SM_AMIGA_4_ mcell G12 mx D31 ... ... +mx D15 CPU_SPACE pin 14 mx D32 DSACK_1_ pin 81 +mx D16 RN_LDS_000 mcell D8 ---------------------------------------------------------------------------- @@ -843,27 +829,51 @@ mx E16 ... ... ---------------------------------------------------------------------------- +BLOCK_F_LOGIC_ARRAY_FANIN +~~~~~~~~~~~~~~~~~~~~~~~~~ +CSM Signal Source CSM Signal Source +------------------------------------ ------------------------------------ +mx F0 RST pin 86 mx F17 A_18_ pin 95 +mx F1 FC_1_ pin 58 mx F18 ... ... +mx F2 ... ... mx F19 ... ... +mx F3 ... ... mx F20 CLK_030 pin 64 +mx F4 BGACK_000 pin 28 mx F21 ... ... +mx F5 CPU_SPACE pin 14 mx F22 ... ... +mx F6 FC_0_ pin 57 mx F23 ... ... +mx F7 ... ... mx F24 ... ... +mx F8 A_17_ pin 59 mx F25inst_AS_030_000_SYNC mcell F0 +mx F9 AS_030 pin 82 mx F26 ... ... +mx F10 ... ... mx F27 ... ... +mx F11 A_16_ pin 96 mx F28 ... ... +mx F12 A_19_ pin 97 mx F29 ... ... +mx F13 ... ... mx F30 ... ... +mx F14 ... ... mx F31 ... ... +mx F15 ... ... mx F32 ... ... +mx F16 ... ... +---------------------------------------------------------------------------- + + BLOCK_G_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx G0 RST pin 86 mx G17 ... ... -mx G1 ... ... mx G18 ... ... -mx G2 cpu_est_2_ mcell G4 mx G19 ... ... -mx G3 SM_AMIGA_1_ mcell G5 mx G20 ... ... -mx G4 inst_CLK_000_D mcell H2 mx G21 CLK_OSZI pin 61 -mx G5 SM_AMIGA_2_ mcell G10 mx G22 ... ... -mx G6 inst_DTACK_SYNC mcell B9 mx G23 RN_E mcell G2 -mx G7 inst_CLK_000_DD mcell H13 mx G24 ... ... -mx G8 ... ... mx G25 RN_AS_000 mcell D9 -mx G9 SM_AMIGA_0_ mcell G13 mx G26 ... ... -mx G10 VPA pin 36 mx G27 ... ... -mx G11 CLK_CNT_0_ mcell G14 mx G28 SM_AMIGA_3_ mcell B5 -mx G12 SM_AMIGA_7_ mcell G9 mx G29 cpu_est_1_ mcell G6 -mx G13 cpu_est_0_ mcell G8 mx G30 ... ... -mx G14inst_CLK_OUT_PRE mcell G12 mx G31 ... ... -mx G15 inst_VPA_SYNC mcell A0 mx G32 ... ... -mx G16 ... ... +mx G0 RST pin 86 mx G17 cpu_est_0_ mcell D14 +mx G1 inst_CLK_000_DD mcell D13 mx G18 ... ... +mx G2 cpu_est_2_ mcell D10 mx G19 inst_CLK_000_D mcell H1 +mx G3 SM_AMIGA_3_ mcell G5 mx G20 ... ... +mx G4inst_CLK_OUT_PRE mcell H5 mx G21 CLK_OSZI pin 61 +mx G5 ... ... mx G22 ... ... +mx G6 ... ... mx G23 DTACK pin 30 +mx G7 SM_AMIGA_4_ mcell G12 mx G24 inst_VPA_D mcell G1 +mx G8 ... ... mx G25 ... ... +mx G9 AS_030 pin 82 mx G26 ... ... +mx G10 VPA pin 36 mx G27 inst_VPA_SYNC mcell G9 +mx G11 RN_E mcell G4 mx G28 ... ... +mx G12 inst_DTACK_SYNC mcell G13 mx G29 ... ... +mx G13 SM_AMIGA_2_ mcell G8 mx G30 ... ... +mx G14 RN_VMA mcell D4 mx G31 ... ... +mx G15 SM_AMIGA_5_ mcell A0 mx G32 ... ... +mx G16 cpu_est_1_ mcell D2 ---------------------------------------------------------------------------- @@ -872,21 +882,21 @@ BLOCK_H_LOGIC_ARRAY_FANIN CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ mx H0 RST pin 86 mx H17 A_18_ pin 95 -mx H1 FC_1_ pin 58 mx H18 ... ... -mx H2 ... ... mx H19 ... ... -mx H3 CLK_000 pin 11 mx H20 CLK_030 pin 64 -mx H4 BGACK_000 pin 28 mx H21 CLK_OSZI pin 61 -mx H5 CPU_SPACE pin 14 mx H22 SM_AMIGA_1_ mcell G5 +mx H1 FC_1_ pin 58 mx H18 BGACK_000 pin 28 +mx H2 ... ... mx H19 SM_AMIGA_0_ mcell H13 +mx H3 RN_DSACK_1_ mcell H8 mx H20 CLK_030 pin 64 +mx H4 SM_AMIGA_1_ mcell H2 mx H21 CLK_OSZI pin 61 +mx H5 SM_AMIGA_7_ mcell H9 mx H22 ... ... mx H6 FC_0_ pin 57 mx H23 RN_BGACK_030 mcell H4 -mx H7inst_CLK_OUT_PRE mcell G12 mx H24 ... ... +mx H7 CLK_CNT_0_ mcell H6 mx H24 RN_AS_000 mcell D5 mx H8 A_17_ pin 59 mx H25 ... ... mx H9 AS_030 pin 82 mx H26 ... ... -mx H10 ... ... mx H27inst_RISING_CLK_AMIGA mcell H9 +mx H10 inst_CLK_000_D mcell H1 mx H27inst_CLK_OUT_PRE mcell H5 mx H11 A_16_ pin 96 mx H28 ... ... -mx H12 A_19_ pin 97 mx H29 ... ... -mx H13inst_AS_030_000_SYNC mcell H8 mx H30 RN_FPU_CS mcell H0 -mx H14 inst_CLK_000_D mcell H2 mx H31 ... ... -mx H15 RN_DSACK_1_ mcell H12 mx H32 ... ... +mx H12 A_19_ pin 97 mx H29 inst_CLK_000_DD mcell D13 +mx H13 SM_AMIGA_2_ mcell G8 mx H30 RN_FPU_CS mcell H0 +mx H14 CLK_000 pin 11 mx H31 ... ... +mx H15 CPU_SPACE pin 14 mx H32 ... ... mx H16 ... ... ---------------------------------------------------------------------------- @@ -904,19 +914,19 @@ PostFit_Equations --------- ------ ------- ---- ----------------- 0 0 1 Pin BERR 1 1 1 Pin BERR.OE + 1 0 1 Pin DSACK_0_ + 1 1 1 Pin DSACK_0_.OE 1 1 1 Pin CLK_DIV_OUT.D 1 1 1 Pin CLK_DIV_OUT.C 1 0 1 Pin AVEC 0 0 1 Pin AVEC_EXP 1 1 1 Pin AVEC_EXP.OE - 1 0 1 Pin DSACK_0_ - 1 1 1 Pin DSACK_0_.OE 0 0 1 Pin AMIGA_BUS_ENABLE 1 1 1 Pin AMIGA_BUS_DATA_DIR 1 0 1 Pin AMIGA_BUS_ENABLE_LOW 1 4 1 Pin CIIN 1 8 1 Pin CIIN.OE - 2 3 1 Pin IPL_030_2_.D + 3 4 1 Pin IPL_030_2_.D 1 1 1 Pin IPL_030_2_.AP 1 1 1 Pin IPL_030_2_.C 1 1 1 Pin DSACK_1_.OE @@ -938,28 +948,28 @@ PostFit_Equations 3 7 1 Pin BG_000.D- 1 1 1 Pin BG_000.AP 1 1 1 Pin BG_000.C - 2 3 1 Pin BGACK_030.D + 2 4 1 Pin BGACK_030.D 1 1 1 Pin BGACK_030.AP 1 1 1 Pin BGACK_030.C + 3 4 1 Pin IPL_030_1_.D + 1 1 1 Pin IPL_030_1_.AP + 1 1 1 Pin IPL_030_1_.C + 3 4 1 Pin IPL_030_0_.D + 1 1 1 Pin IPL_030_0_.AP + 1 1 1 Pin IPL_030_0_.C 1 1 1 Pin CLK_EXP.D 1 1 1 Pin CLK_EXP.C 2 10 1 Pin FPU_CS.D- 1 1 1 Pin FPU_CS.AP 1 1 1 Pin FPU_CS.C - 2 3 1 Pin IPL_030_1_.D - 1 1 1 Pin IPL_030_1_.AP - 1 1 1 Pin IPL_030_1_.C 1 1 1 Pin DTACK.OE 1 2 1 Pin DTACK.D- 1 1 1 Pin DTACK.AP 1 1 1 Pin DTACK.C - 2 3 1 Pin IPL_030_0_.D - 1 1 1 Pin IPL_030_0_.AP - 1 1 1 Pin IPL_030_0_.C 3 6 1 Pin E.T 1 1 1 Pin E.C 1 1 1 Pin VMA.AP - 2 12 1 Pin VMA.T + 2 8 1 Pin VMA.T 1 1 1 Pin VMA.C 1 1 1 Pin RESET.D 1 1 1 Pin RESET.C @@ -967,10 +977,6 @@ PostFit_Equations 1 1 1 Node cpu_est_0_.C 4 6 1 Node cpu_est_1_.T 1 1 1 Node cpu_est_1_.C - 1 1 1 Node cpu_est_d_0_.D - 1 1 1 Node cpu_est_d_0_.C - 1 1 1 Node cpu_est_d_3_.D - 1 1 1 Node cpu_est_d_3_.C 4 11 1 Node inst_AS_030_000_SYNC.D 1 1 1 Node inst_AS_030_000_SYNC.AP 1 1 1 Node inst_AS_030_000_SYNC.C @@ -988,10 +994,6 @@ PostFit_Equations 1 1 1 Node inst_CLK_000_DD.C 2 2 1 Node inst_CLK_OUT_PRE.D 1 1 1 Node inst_CLK_OUT_PRE.C - 1 1 1 Node cpu_est_d_1_.D - 1 1 1 Node cpu_est_d_1_.C - 1 1 1 Node cpu_est_d_2_.D - 1 1 1 Node cpu_est_d_2_.C 3 6 1 NodeX1 cpu_est_2_.D.X1 1 1 1 NodeX2 cpu_est_2_.D.X2 1 1 1 Node cpu_est_2_.C @@ -1003,8 +1005,6 @@ PostFit_Equations 2 4 1 Node SM_AMIGA_7_.D 1 1 1 Node SM_AMIGA_7_.AP 1 1 1 Node SM_AMIGA_7_.C - 1 2 1 Node inst_RISING_CLK_AMIGA.D - 1 1 1 Node inst_RISING_CLK_AMIGA.C 1 1 1 Node SM_AMIGA_1_.AR 3 4 1 Node SM_AMIGA_1_.D 1 1 1 Node SM_AMIGA_1_.C @@ -1024,9 +1024,9 @@ PostFit_Equations 3 5 1 Node SM_AMIGA_0_.D 1 1 1 Node SM_AMIGA_0_.C ========= - 174 P-Term Total: 174 + 167 P-Term Total: 167 Total Pins: 59 - Total Nodes: 24 + Total Nodes: 19 Average P-Term/Output: 2 @@ -1036,6 +1036,10 @@ BERR = (0); BERR.OE = (!FPU_CS.Q); +DSACK_0_ = (1); + +DSACK_0_.OE = (!CPU_SPACE); + CLK_DIV_OUT.D = (inst_CLK_OUT_PRE.Q); CLK_DIV_OUT.C = (CLK_OSZI); @@ -1046,10 +1050,6 @@ AVEC_EXP = (0); AVEC_EXP.OE = (!FPU_CS.Q); -DSACK_0_ = (1); - -DSACK_0_.OE = (!CPU_SPACE); - AMIGA_BUS_ENABLE = (0); AMIGA_BUS_DATA_DIR = (!RW); @@ -1060,8 +1060,9 @@ CIIN = (A_23_ & A_22_ & A_21_ & A_20_); CIIN.OE = (!A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_); -IPL_030_2_.D = (IPL_2_ & inst_RISING_CLK_AMIGA.Q - # IPL_030_2_.Q & !inst_RISING_CLK_AMIGA.Q); +IPL_030_2_.D = (IPL_030_2_.Q & !inst_CLK_000_D.Q + # IPL_030_2_.Q & inst_CLK_000_DD.Q + # IPL_2_ & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q); IPL_030_2_.AP = (!RST); @@ -1128,12 +1129,28 @@ BG_000.AP = (!RST); BG_000.C = (CLK_OSZI); BGACK_030.D = (BGACK_000 & BGACK_030.Q - # BGACK_000 & inst_RISING_CLK_AMIGA.Q); + # BGACK_000 & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q); BGACK_030.AP = (!RST); BGACK_030.C = (CLK_OSZI); +IPL_030_1_.D = (IPL_030_1_.Q & !inst_CLK_000_D.Q + # IPL_030_1_.Q & inst_CLK_000_DD.Q + # IPL_1_ & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q); + +IPL_030_1_.AP = (!RST); + +IPL_030_1_.C = (CLK_OSZI); + +IPL_030_0_.D = (!inst_CLK_000_D.Q & IPL_030_0_.Q + # inst_CLK_000_DD.Q & IPL_030_0_.Q + # IPL_0_ & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q); + +IPL_030_0_.AP = (!RST); + +IPL_030_0_.C = (CLK_OSZI); + CLK_EXP.D = (inst_CLK_OUT_PRE.Q); CLK_EXP.C = (CLK_OSZI); @@ -1145,13 +1162,6 @@ FPU_CS.AP = (!RST); FPU_CS.C = (CLK_OSZI); -IPL_030_1_.D = (IPL_1_ & inst_RISING_CLK_AMIGA.Q - # IPL_030_1_.Q & !inst_RISING_CLK_AMIGA.Q); - -IPL_030_1_.AP = (!RST); - -IPL_030_1_.C = (CLK_OSZI); - DTACK.OE = (!BGACK_030.Q); !DTACK.D = (!AS_000.Q & !DSACK_1_.PIN); @@ -1160,13 +1170,6 @@ DTACK.AP = (!RST); DTACK.C = (CLK_OSZI); -IPL_030_0_.D = (IPL_0_ & inst_RISING_CLK_AMIGA.Q - # IPL_030_0_.Q & !inst_RISING_CLK_AMIGA.Q); - -IPL_030_0_.AP = (!RST); - -IPL_030_0_.C = (CLK_OSZI); - E.T = (E.Q & cpu_est_0_.Q & cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & cpu_est_2_.Q # !E.Q & cpu_est_0_.Q & cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & !cpu_est_2_.Q # !E.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & !cpu_est_2_.Q); @@ -1175,7 +1178,7 @@ E.C = (CLK_OSZI); VMA.AP = (!RST); -VMA.T = (!VMA.Q & !cpu_est_d_0_.Q & !cpu_est_d_3_.Q & AS_000.Q & inst_CLK_000_D.Q & cpu_est_d_1_.Q & cpu_est_d_2_.Q +VMA.T = (!E.Q & !VMA.Q & !cpu_est_0_.Q & cpu_est_1_.Q & AS_000.Q & inst_CLK_000_D.Q & cpu_est_2_.Q # !E.Q & VMA.Q & cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & !inst_CLK_000_D.Q & cpu_est_2_.Q); VMA.C = (CLK_OSZI); @@ -1197,14 +1200,6 @@ cpu_est_1_.T = (E.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_C cpu_est_1_.C = (CLK_OSZI); -cpu_est_d_0_.D = (cpu_est_0_.Q); - -cpu_est_d_0_.C = (CLK_OSZI); - -cpu_est_d_3_.D = (E.Q); - -cpu_est_d_3_.C = (CLK_OSZI); - inst_AS_030_000_SYNC.D = (AS_030 # CPU_SPACE & CLK_030 # !CLK_030 & inst_AS_030_000_SYNC.Q @@ -1245,14 +1240,6 @@ inst_CLK_OUT_PRE.D = (!inst_CLK_OUT_PRE.Q & CLK_CNT_0_.Q inst_CLK_OUT_PRE.C = (CLK_OSZI); -cpu_est_d_1_.D = (cpu_est_1_.Q); - -cpu_est_d_1_.C = (CLK_OSZI); - -cpu_est_d_2_.D = (cpu_est_2_.Q); - -cpu_est_d_2_.C = (CLK_OSZI); - cpu_est_2_.D.X1 = (E.Q & cpu_est_0_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & !cpu_est_2_.Q # !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & !cpu_est_2_.Q # !E.Q & cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & cpu_est_2_.Q); @@ -1280,10 +1267,6 @@ SM_AMIGA_7_.AP = (!RST); SM_AMIGA_7_.C = (CLK_OSZI); -inst_RISING_CLK_AMIGA.D = (CLK_000 & !inst_CLK_000_D.Q); - -inst_RISING_CLK_AMIGA.C = (CLK_OSZI); - SM_AMIGA_1_.AR = (!RST); SM_AMIGA_1_.D = (inst_CLK_000_D.Q & SM_AMIGA_1_.Q diff --git a/Logic/68030_tk.tal b/Logic/68030_tk.tal index eea3929..773fc3e 100644 --- a/Logic/68030_tk.tal +++ b/Logic/68030_tk.tal @@ -48,13 +48,13 @@ AMIGA_BUS_DATA_DIR .. .. .. .. 1 1 .. .. RN_BG_000 1 1 0 0 .. .. 1 1 BGACK_030 1 1 0 0 .. .. 1 1 RN_BGACK_030 1 1 0 0 .. .. 1 1 - FPU_CS 1 1 0 0 .. .. 1 1 - RN_FPU_CS 1 1 0 0 .. .. 1 1 IPL_030_1_ 1 1 0 0 .. .. 1 1 RN_IPL_030_1_ 1 1 0 0 .. .. 1 1 - DTACK 1 1 0 0 .. .. .. .. IPL_030_0_ 1 1 0 0 .. .. 1 1 RN_IPL_030_0_ 1 1 0 0 .. .. 1 1 + FPU_CS 1 1 0 0 .. .. 1 1 + RN_FPU_CS 1 1 0 0 .. .. 1 1 + DTACK 1 1 0 0 .. .. .. .. E .. .. 0 0 .. .. 1 1 RN_E .. .. 0 0 .. .. 1 1 VMA .. .. 0 0 .. .. 1 1 @@ -62,8 +62,6 @@ AMIGA_BUS_DATA_DIR .. .. .. .. 1 1 .. .. RESET 1 1 0 0 .. .. .. .. cpu_est_0_ .. .. .. .. .. .. 1 1 cpu_est_1_ .. .. .. .. .. .. 1 1 - cpu_est_d_0_ .. .. .. .. .. .. 1 1 - cpu_est_d_3_ .. .. .. .. .. .. 1 1 inst_AS_030_000_SYNC 1 1 .. .. .. .. 1 1 inst_DTACK_SYNC 1 1 .. .. .. .. 1 1 inst_VPA_D 1 1 .. .. .. .. 1 1 @@ -71,13 +69,10 @@ inst_AS_030_000_SYNC 1 1 .. .. .. .. 1 1 inst_CLK_000_D 1 1 .. .. .. .. 1 1 inst_CLK_000_DD .. .. .. .. .. .. 1 1 inst_CLK_OUT_PRE .. .. .. .. .. .. 1 1 - cpu_est_d_1_ .. .. .. .. .. .. 1 1 - cpu_est_d_2_ .. .. .. .. .. .. 1 1 cpu_est_2_ .. .. .. .. .. .. 1 1 CLK_CNT_0_ .. .. .. .. .. .. 1 1 SM_AMIGA_6_ .. .. .. .. .. .. 1 1 SM_AMIGA_7_ .. .. .. .. .. .. 1 1 -inst_RISING_CLK_AMIGA 1 1 .. .. .. .. 1 1 SM_AMIGA_1_ .. .. .. .. .. .. 1 1 SM_AMIGA_4_ .. .. .. .. .. .. 1 1 SM_AMIGA_3_ .. .. .. .. .. .. 1 1 diff --git a/Logic/68030_tk.tt2 b/Logic/68030_tk.tt2 index 9982b1b..d1cc156 100644 --- a/Logic/68030_tk.tt2 +++ b/Logic/68030_tk.tt2 @@ -1,289 +1,285 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Thu May 15 22:21:53 2014 +#$ DATE Thu May 15 23:02:46 2014 #$ MODULE 68030_tk -#$ PINS 59 A_28_ A_27_ SIZE_1_ A_26_ A_25_ A_31_ A_24_ A_23_ A_22_ A_21_ IPL_2_ A_20_ A_19_ A_18_ A_17_ FC_1_ A_16_ AS_030 DS_030 CPU_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT A_0_ AVEC IPL_1_ AVEC_EXP IPL_0_ DSACK_0_ VPA FC_0_ RST RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 BG_000 BGACK_030 CLK_EXP FPU_CS IPL_030_1_ DTACK IPL_030_0_ E VMA RESET -#$ NODES 24 cpu_est_0_ cpu_est_1_ cpu_est_d_0_ cpu_est_d_3_ inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D inst_CLK_000_DD inst_CLK_OUT_PRE cpu_est_d_1_ cpu_est_d_2_ cpu_est_2_ CLK_CNT_0_ SM_AMIGA_6_ SM_AMIGA_7_ inst_RISING_CLK_AMIGA SM_AMIGA_1_ SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_5_ SM_AMIGA_2_ SM_AMIGA_0_ +#$ PINS 59 A_21_ A_20_ SIZE_1_ A_19_ A_18_ A_31_ A_17_ A_16_ IPL_2_ FC_1_ AS_030 DS_030 CPU_SPACE BERR BG_030 A_0_ BGACK_000 CLK_030 IPL_1_ CLK_000 IPL_0_ CLK_OSZI DSACK_0_ CLK_DIV_OUT FC_0_ AVEC AVEC_EXP VPA RST RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 BG_000 BGACK_030 IPL_030_1_ IPL_030_0_ CLK_EXP FPU_CS DTACK E VMA RESET +#$ NODES 19 cpu_est_0_ cpu_est_1_ inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D inst_CLK_000_DD inst_CLK_OUT_PRE cpu_est_2_ CLK_CNT_0_ SM_AMIGA_6_ SM_AMIGA_7_ SM_AMIGA_1_ SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_5_ SM_AMIGA_2_ SM_AMIGA_0_ .type fr -.i 73 -.o 120 -.ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 CPU_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_ IPL_030_0_.Q BGACK_030.Q FPU_CS.Q IPL_030_1_.Q E.Q VMA.Q IPL_030_2_.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_d_0_.Q cpu_est_d_3_.Q AS_000.Q inst_AS_030_000_SYNC.Q inst_DTACK_SYNC.Q inst_VPA_D.Q inst_VPA_SYNC.Q inst_CLK_000_D.Q inst_CLK_000_DD.Q inst_CLK_OUT_PRE.Q cpu_est_d_1_.Q cpu_est_d_2_.Q cpu_est_2_.Q CLK_CNT_0_.Q SM_AMIGA_6_.Q SM_AMIGA_7_.Q UDS_000.Q LDS_000.Q inst_RISING_CLK_AMIGA.Q SM_AMIGA_1_.Q DSACK_1_.Q SM_AMIGA_4_.Q SM_AMIGA_3_.Q SM_AMIGA_5_.Q SM_AMIGA_2_.Q SM_AMIGA_0_.Q BG_000.Q DSACK_1_.PIN DTACK.PIN -.ob BERR AVEC AVEC_EXP AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN E.C SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.C SM_AMIGA_0_.AR cpu_est_d_0_.C cpu_est_d_1_.C cpu_est_d_2_.C cpu_est_d_3_.C IPL_030_0_.C IPL_030_0_.AP IPL_030_1_.C IPL_030_1_.AP IPL_030_2_.C IPL_030_2_.AP cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C inst_VPA_SYNC.C inst_VPA_SYNC.AP inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP VMA.C VMA.AP BG_000.C BG_000.AP DSACK_1_.C DSACK_1_.AP BGACK_030.C BGACK_030.AP inst_CLK_OUT_PRE.C UDS_000.C UDS_000.AP LDS_000.C LDS_000.AP inst_DTACK_SYNC.C inst_DTACK_SYNC.AP FPU_CS.C FPU_CS.AP AS_000.C AS_000.AP DTACK.C DTACK.AP inst_RISING_CLK_AMIGA.C CLK_CNT_0_.C inst_VPA_D.C inst_CLK_000_D.C RESET.C inst_CLK_000_DD.C CLK_EXP.C DSACK_0_ DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_DIV_OUT.C CLK_DIV_OUT.D CLK_EXP.D IPL_030_0_.D BGACK_030.D FPU_CS.D IPL_030_1_.D E.T VMA.T IPL_030_2_.D cpu_est_0_.D cpu_est_1_.T cpu_est_d_0_.D cpu_est_d_3_.D AS_000.D inst_AS_030_000_SYNC.D inst_DTACK_SYNC.D inst_VPA_D.D inst_VPA_SYNC.D inst_CLK_000_D.D inst_CLK_000_DD.D inst_CLK_OUT_PRE.D cpu_est_d_1_.D cpu_est_d_2_.D cpu_est_2_.D CLK_CNT_0_.D SM_AMIGA_6_.D SM_AMIGA_7_.D UDS_000.D RESET.D LDS_000.D inst_RISING_CLK_AMIGA.D SM_AMIGA_1_.D DSACK_1_.D DTACK.D SM_AMIGA_4_.D SM_AMIGA_3_.D SM_AMIGA_5_.D SM_AMIGA_2_.D SM_AMIGA_0_.D BG_000.D -.p 277 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-----------------------------------------------1-----1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------1--1--------10-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~ -------------------------------------------0--------10-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------00-------10-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~ ----------------------------------------1--00-------10-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----1------------------------------------------------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~ -----------------------------------------0---001----1--11----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~ --------------------------------------------1------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~ ----------------------------------------------------0----1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~ ----------------------------------------01-10-----0-0----1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------------1---1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~ ----------------------------------------0--1--------10---1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------1--11-------10---1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----1---------------------------------------------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------1-----0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------1--11-------10---0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------0--11-------10---0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------0---0-------10---0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------0--00-------10---0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------------------0---1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~ ------------------------------------------------------1---0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ ------------------------------------------------1----------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ ----------------------------------------------------0------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ -----------------------------------------------------1-----1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ ------------------------------------------------0---10-----1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ ------0--------1----------------1---------------0---10-----1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ -0----0--------11---------------0---------------0---10-----1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~ -----1-----------------------------------------------------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~ -----1---------1-------------------------------------------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~ -----------------------------------------------1-----------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------1-------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ ----------------------------------------------------0-------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ ----------0------------------------------------------------00------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 ------1------------------------------------------------------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ ---------------1--------------------------------1------------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ ----------------------------------------------------0--------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ ---------------1-------------------------------------1-------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ ---------------1-------------------------------------------0-1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ ------1-------------------------------------------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~ ---------------1--------------------------------1-------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~ ----------------------------------------------------0---------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~ ---------------1-------------------------------------1--------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~ ---------------1-------------------------------------------0--1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~ ---1-----------------------------------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------1-----------------------------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------1-----------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------1----------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------1--------------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------1-----------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------1--------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------1-----------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~ ----------------------------------------------------0-1---------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ -----1----------------------------------------------------------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~ ----------------------------------------------------1------------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~ ------------------------------------------------------0----------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~ ----------------------------------------------------------------01-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~ ----------------------------------------------------1-------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ ------0--------0----------------1-------------------1-------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ -0----0--------01---------------0-------------------1-------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~ ----------------------------------------------------0-------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~ -----1---------0--------------------------------------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~ ---------------0---------------------------------------------1----0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ ---------------0----------------------------------------------1---0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~ -------------------------------------------------1-1---------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ ----------------------------------------------------1--------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ -------------------------------------------------0--0--------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ ---------------------------------------------------00--------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ -----1-------------------------------------------------------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------1-----------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------1---------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------1---------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ ----------------------------------------------------0---------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~ ----------------------------------------------------1----------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~ ----------------------------------------------------0----------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ ------------------------------------------------------0---------1----0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~ -----------------------------------------------0----------------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ -----------------------------------------------1----1-----------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ ----------------------------------------------------0-----------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ ----------1------------------------------------------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 ------------------------------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ -----1-------------------------------------------------------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------1-----------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------------------------------- 0~00~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --1----------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------1------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------0---------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----00-0--1--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-0-01--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ -----------0-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~0~~~~~~~~~ ------------0------------------------------------------------------------- ~~~~~~~00~0~0~0~0~0~0~0~00000~0~0~0000~0~0~0~0~0~00~0~0~0~0~0~0000000~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------0------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~ --------------1----------------------------------------------------------- ~~~~~~~~~0~0~0~0~0~0~0~0~~~~~0~0~0~~~~0~0~0~0~0~0~~0~0~0~0~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------0----------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~ ---------------1---------------------------------------------------------- ~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------1-------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------1------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------1------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------1----------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------1---------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------1--------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------1-------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------0------------------------------------------------- ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------0------------------------------------------------ ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------0----------------------------------------------- ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------0---------------------------------------------- ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-0--1-----------------1--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-0--1------------------1-------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-0--1-------------------0------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-0--1--------------------1------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ ----10---11-----------------0010---1-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-0--1------------------------0-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------1------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------0------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~000~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------1----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0----0---------------------------0----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------0--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------0------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------01----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------0----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ -------------------------------------------10----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------1--10----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-----------------------------------------0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0----0-------------------------------------0------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-------------------------------------------0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~ -----0---------------------------------------------0---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------1--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~0~~0~~ -----------------------------------------1----------1--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------1------1--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------1-----1--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------1----1--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ -----------------------------------------------0----1--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------0--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~0~~~~~~~~0~~~~~~0~~~~~~~~~0~~~ ----------------------------------------1-----------0--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------0----------0--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------0--------0--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------1-------0--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------0--0--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ --------------------------------------------------1-0--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------00--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ -----------------------------------------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------0---------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------1--------10-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------0--10-------10-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ ------------------------------------------------0---10-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ ----------------------------------------------------0-1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~ ------------------------------------------------------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~00~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------1--0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------1---0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------0----------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------0-------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------0--0-------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------1---1------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ ----------------------------------------1----------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------0---1------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ -------------------------------------------01------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ ----------------------------------------------------0----0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ -----------------------------------------------------1---0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ ----------------------------------------------------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ ------------------------------------------------------1---1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ ------------------------------------------------------0---0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ -----1-00-0------------------------------------------------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 ------------------------------------------------0---10-----1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~ -1----0--------1--------------------------------0---10-----1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ ------0--------10-------------------------------0---10-----1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ ------0--------1----------------1---------------0---10-----1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ ------0--------1----------------0---------------0---10-----1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ ----------------------------------------------------1------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ -----1-00-0-------------------------------------------------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 -----------------------------------------------0------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ -----------------------------------------------------------00------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ -----01------------------------------------------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ -----0---------1--------------------------------1------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ -----0----------------------------------------------0--------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ -----0---------1-------------------------------------1-------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ -----0---------1-------------------------------------------0-0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ -----01-------------------------------------------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ -----0---------1--------------------------------1-------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ -----0----------------------------------------------0---------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ -----0---------1-------------------------------------1--------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ -----0---------1-------------------------------------------0--0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ ---0-----------------------------------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------0-----------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------0----------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------0--------------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------0-------------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------0-----------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------0--------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------0-1---------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ -----0-----------------------------------------------------------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ -1----0--------0------------------------------------1-------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ ------0--------00-----------------------------------1-------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ ------0--------0----------------1-------------------1-------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ ------0--------0----------------0-------------------1-------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ -----0---------0---------------------------------------------0----0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ -----0---------0----------------------------------------------0---0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ ----------------------------------------10-00-----0-1----1---------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------0--------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ ------------------------------------------------------------------00------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ ------------------------------------------------1-------------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ -----------------------------------------------------1--------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ -----------------------------------------------------------0--------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ ------------------------------------------------------------------0-0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ----------------------------------------------------0----------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~ -------------------------------------------------1-1-----------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ ----------------------------------------------------------------0----0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~ -------------------------------------------------------------------0-0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ ----------------------------------------------------1-----------------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ ------------------------------------------------------0---------------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ ------------------------------------------------------------0---------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ ----------------------------------------------------------------0-----0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ --------0-1------------------------------------------------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 -----------------------------------------------0------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ --------------------------------------------------1-1--------------1-----0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~ +.i 68 +.o 110 +.ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 CPU_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_ IPL_030_1_.Q IPL_030_2_.Q BGACK_030.Q FPU_CS.Q E.Q VMA.Q cpu_est_0_.Q cpu_est_1_.Q AS_000.Q inst_AS_030_000_SYNC.Q inst_DTACK_SYNC.Q inst_VPA_D.Q inst_VPA_SYNC.Q inst_CLK_000_D.Q inst_CLK_000_DD.Q inst_CLK_OUT_PRE.Q cpu_est_2_.Q CLK_CNT_0_.Q SM_AMIGA_6_.Q SM_AMIGA_7_.Q UDS_000.Q LDS_000.Q SM_AMIGA_1_.Q DSACK_1_.Q SM_AMIGA_4_.Q SM_AMIGA_3_.Q SM_AMIGA_5_.Q SM_AMIGA_2_.Q SM_AMIGA_0_.Q BG_000.Q IPL_030_0_.Q DSACK_1_.PIN DTACK.PIN +.ob BERR AVEC AVEC_EXP AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.C SM_AMIGA_0_.AR IPL_030_0_.C IPL_030_0_.AP IPL_030_1_.C IPL_030_1_.AP IPL_030_2_.C IPL_030_2_.AP SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.C SM_AMIGA_4_.AR DSACK_1_.C DSACK_1_.AP VMA.C VMA.AP BGACK_030.C BGACK_030.AP inst_CLK_OUT_PRE.C cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C E.C LDS_000.C LDS_000.AP inst_DTACK_SYNC.C inst_DTACK_SYNC.AP FPU_CS.C FPU_CS.AP inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP AS_000.C AS_000.AP inst_VPA_SYNC.C inst_VPA_SYNC.AP BG_000.C BG_000.AP DTACK.C DTACK.AP UDS_000.C UDS_000.AP CLK_CNT_0_.C inst_VPA_D.C inst_CLK_000_D.C RESET.C inst_CLK_000_DD.C CLK_EXP.C DSACK_0_ DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_DIV_OUT.C CLK_DIV_OUT.D IPL_030_1_.D IPL_030_2_.D BGACK_030.D FPU_CS.D E.T VMA.T cpu_est_0_.D cpu_est_1_.T AS_000.D inst_AS_030_000_SYNC.D inst_DTACK_SYNC.D inst_VPA_D.D inst_VPA_SYNC.D inst_CLK_000_D.D inst_CLK_000_DD.D inst_CLK_OUT_PRE.D cpu_est_2_.D RESET.D CLK_CNT_0_.D SM_AMIGA_6_.D SM_AMIGA_7_.D UDS_000.D LDS_000.D SM_AMIGA_1_.D DSACK_1_.D DTACK.D SM_AMIGA_4_.D SM_AMIGA_3_.D SM_AMIGA_5_.D SM_AMIGA_2_.D SM_AMIGA_0_.D BG_000.D CLK_EXP.D IPL_030_0_.D +.p 273 +-------------------------------------------------------------------- ~1~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~ +----11-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~ +------0------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------1------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +---0-----1---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------1--1---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~ +--------01---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0----0---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +------1--0---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +----------1--------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~ +-----------1-------------------------------------------------------- ~~~~~~~1~1~1~1~1~1~1~1~1~1~1~1~1~1~111111~1~1~1~1~1~1~1~1~111111~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------1------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +-------------1------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~ +-------------0------------------------------------------------------ ~~~~~~~~1~1~1~1~1~1~1~1~1~1~1~1~1~1~~~~~~1~1~1~1~1~1~1~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------0----------------------------------------------------- ~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-0--------------0000000--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------1111----------------------------------------- ~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1-----------------1---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1------------------1--------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1-------------------0-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1--------------------1------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1----11-----------------0010---1--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~ +---------1------------------------0--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~111~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------1----------------------------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------0------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------0----------------------------1----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1----------------------------------0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +----1-----------------------------------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +----1------------------------------------1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +----1-------------------------------------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~ +----1---------------------------------------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +---------0----------------------------------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~ +----1---------1-----------------------------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~ +-------------------------------------------11----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +----1-----------------------------------------1--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +----1-----------------------------------------0--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------10--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------0-------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------1------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------1-----1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------1----1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------11-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ +----1-------------------------------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~ +----1-------------------------------------------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~1~~~~~~~~11~~~~~~~~~~~ +-----------------------------------1------------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------1-----------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------1------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------1----0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------1--0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------10------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +----1--------------------------------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +----1---------1----------------------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~ +-----------------------------------1-------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------1------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------1-------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------1-----1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +--1---------------------------------------------10------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------1---------------------------------------10------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------1---------------10------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------1--------------10------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +---------------------------------------1-1------10------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~ +-----------------------------------------0------10------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------00-----10------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~ +---------------------------------------1-00-----10------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +----1---------------------------------------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~ +------------------------------------------1--------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~ +---------------------------------------00011----1--1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------0--1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~ +---------------------------------------0110---0-0--1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------1-1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~ +---------------------------------------0-1------10-1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------1-11-----10-1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1----------------------------------------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------1---0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------1-11-----10-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------0-11-----10-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------0--0-----10-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------0-00-----10-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------0-1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ +----------------------------------------------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~ +--------------------------------------------------1-0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ +--------------------------------------------1--------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +------------------------------------------------0----1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +-------------------------------------------------1---1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +--------------------------------------------0---10---1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~ +-----0--------1----------------1------------0---10---1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +0----0--------11---------------0------------0---10---1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +----1------------------------------------------------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +----1---------1--------------------------------------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~ +-------------------------------------------1---------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------1-----1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +------------------------------------------------0-----1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +---------0-------------------------------------------00------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +-----1-------------------------------------------------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +--------------1-----------------------------1----------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +------------------------------------------------0------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +--------------1----------------------------------1-----1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +--------------1--------------------------------------0-1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +-----1--------------------------------------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +--------------1-----------------------------1-----------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +------------------------------------------------0-------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +--------------1----------------------------------1------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +--------------1--------------------------------------0--1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +------------------------------------------------1--------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~ +------------------------------------------------0-1------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ +----1----------------------------------------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~ +------------------------------------------------1---------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~ +--------------------------------------------------0-------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~ +---------------------------------------------------------01--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~ +------------------------------------------------1----------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ +-----0--------0----------------1----------------1----------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +0----0--------01---------------0----------------1----------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +------------------------------------------------0----------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~ +----1---------0--------------------------------------------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~ +--------------0----------------------------------------1---0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +--------------0-----------------------------------------1--0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +---------------------------------------------1-1------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ +------------------------------------------------1-----------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ +---------------------------------------------0--0-----------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ +-----------------------------------------------00-----------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ +----1-------------------------------------------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------1--------------0------- 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~ +---------------------------------------1000---0-1--1--------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------0-----------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +-----------------------------------------------------------00------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +--------------------------------------------1----------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +-------------------------------------------------1-----------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +-----------------------------------------------------0-------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +-----------------------------------------------------------0-0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ +------------------------------------------------0-------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ +---------------------------------------------1-1--------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +---------------------------------------------------------0----0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ +------------------------------------------------------------0-0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +------------------------------------------------1--------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ +--------------------------------------------------0------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ +------------------------------------------------------0--------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +---------------------------------------------------------0-----0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ +-------0-1------------------------------------------------------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ +------------------------------------------------0----------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 +-------------------------------------------------1---------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 +-------------------------------------------0----------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~ +----------------------------------------------1-1-----------1------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~ .end diff --git a/Logic/68030_tk.tt3 b/Logic/68030_tk.tt3 index e87bcd4..0467835 100644 --- a/Logic/68030_tk.tt3 +++ b/Logic/68030_tk.tt3 @@ -1,289 +1,285 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Thu May 15 22:21:53 2014 +#$ DATE Thu May 15 23:02:46 2014 #$ MODULE 68030_tk -#$ PINS 59 A_28_ A_27_ SIZE_1_ A_26_ A_25_ A_31_ A_24_ A_23_ A_22_ A_21_ IPL_2_ A_20_ A_19_ A_18_ A_17_ FC_1_ A_16_ AS_030 DS_030 CPU_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT A_0_ AVEC IPL_1_ AVEC_EXP IPL_0_ DSACK_0_ VPA FC_0_ RST RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 BG_000 BGACK_030 CLK_EXP FPU_CS IPL_030_1_ DTACK IPL_030_0_ E VMA RESET -#$ NODES 24 cpu_est_0_ cpu_est_1_ cpu_est_d_0_ cpu_est_d_3_ inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D inst_CLK_000_DD inst_CLK_OUT_PRE cpu_est_d_1_ cpu_est_d_2_ cpu_est_2_ CLK_CNT_0_ SM_AMIGA_6_ SM_AMIGA_7_ inst_RISING_CLK_AMIGA SM_AMIGA_1_ SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_5_ SM_AMIGA_2_ SM_AMIGA_0_ +#$ PINS 59 A_21_ A_20_ SIZE_1_ A_19_ A_18_ A_31_ A_17_ A_16_ IPL_2_ FC_1_ AS_030 DS_030 CPU_SPACE BERR BG_030 A_0_ BGACK_000 CLK_030 IPL_1_ CLK_000 IPL_0_ CLK_OSZI DSACK_0_ CLK_DIV_OUT FC_0_ AVEC AVEC_EXP VPA RST RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 BG_000 BGACK_030 IPL_030_1_ IPL_030_0_ CLK_EXP FPU_CS DTACK E VMA RESET +#$ NODES 19 cpu_est_0_ cpu_est_1_ inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D inst_CLK_000_DD inst_CLK_OUT_PRE cpu_est_2_ CLK_CNT_0_ SM_AMIGA_6_ SM_AMIGA_7_ SM_AMIGA_1_ SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_5_ SM_AMIGA_2_ SM_AMIGA_0_ .type fr -.i 73 -.o 120 -.ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 CPU_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_ IPL_030_0_.Q BGACK_030.Q FPU_CS.Q IPL_030_1_.Q E.Q VMA.Q IPL_030_2_.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_d_0_.Q cpu_est_d_3_.Q AS_000.Q inst_AS_030_000_SYNC.Q inst_DTACK_SYNC.Q inst_VPA_D.Q inst_VPA_SYNC.Q inst_CLK_000_D.Q inst_CLK_000_DD.Q inst_CLK_OUT_PRE.Q cpu_est_d_1_.Q cpu_est_d_2_.Q cpu_est_2_.Q CLK_CNT_0_.Q SM_AMIGA_6_.Q SM_AMIGA_7_.Q UDS_000.Q LDS_000.Q inst_RISING_CLK_AMIGA.Q SM_AMIGA_1_.Q DSACK_1_.Q SM_AMIGA_4_.Q SM_AMIGA_3_.Q SM_AMIGA_5_.Q SM_AMIGA_2_.Q SM_AMIGA_0_.Q BG_000.Q DSACK_1_.PIN DTACK.PIN -.ob BERR AVEC AVEC_EXP AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN E.C SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.C SM_AMIGA_0_.AR cpu_est_d_0_.C cpu_est_d_1_.C cpu_est_d_2_.C cpu_est_d_3_.C IPL_030_0_.C IPL_030_0_.AP IPL_030_1_.C IPL_030_1_.AP IPL_030_2_.C IPL_030_2_.AP cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C inst_VPA_SYNC.C inst_VPA_SYNC.AP inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP VMA.C VMA.AP BG_000.C BG_000.AP DSACK_1_.C DSACK_1_.AP BGACK_030.C BGACK_030.AP inst_CLK_OUT_PRE.C UDS_000.C UDS_000.AP LDS_000.C LDS_000.AP inst_DTACK_SYNC.C inst_DTACK_SYNC.AP FPU_CS.C FPU_CS.AP AS_000.C AS_000.AP DTACK.C DTACK.AP inst_RISING_CLK_AMIGA.C CLK_CNT_0_.C inst_VPA_D.C inst_CLK_000_D.C RESET.C inst_CLK_000_DD.C CLK_EXP.C DSACK_0_ DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_DIV_OUT.C CLK_DIV_OUT.D CLK_EXP.D IPL_030_0_.D BGACK_030.D FPU_CS.D IPL_030_1_.D E.T VMA.T IPL_030_2_.D cpu_est_0_.D cpu_est_1_.T cpu_est_d_0_.D cpu_est_d_3_.D AS_000.D inst_AS_030_000_SYNC.D inst_DTACK_SYNC.D inst_VPA_D.D inst_VPA_SYNC.D inst_CLK_000_D.D inst_CLK_000_DD.D inst_CLK_OUT_PRE.D cpu_est_d_1_.D cpu_est_d_2_.D cpu_est_2_.D CLK_CNT_0_.D SM_AMIGA_6_.D SM_AMIGA_7_.D UDS_000.D RESET.D LDS_000.D inst_RISING_CLK_AMIGA.D SM_AMIGA_1_.D DSACK_1_.D DTACK.D SM_AMIGA_4_.D SM_AMIGA_3_.D SM_AMIGA_5_.D SM_AMIGA_2_.D SM_AMIGA_0_.D BG_000.D -.p 277 -------------------------------------------------------------------------- ~1~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----1-------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ -----11------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~ -------0------------------------------------------------------------------ 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----00-0--1--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-0-01--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ -----------0-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~0~~~~~~~~~ ------------0------------------------------------------------------------- ~~~~~~~00~0~0~0~0~0~0~0~00000~0~0~0000~0~0~0~0~0~00~0~0~0~0~0~0000000~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------0------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~ --------------1----------------------------------------------------------- ~~~~~~~~~0~0~0~0~0~0~0~0~~~~~0~0~0~~~~0~0~0~0~0~0~~0~0~0~0~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------0----------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~ ---------------1---------------------------------------------------------- ~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------1-------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------1------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------1------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------1----------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------1---------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------1--------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------1-------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------0------------------------------------------------- ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------0------------------------------------------------ ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------0----------------------------------------------- ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------0---------------------------------------------- ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-0--1-----------------1--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-0--1------------------1-------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-0--1-------------------0------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-0--1--------------------1------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ ----10---11-----------------0010---1-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-0--1------------------------0-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------1------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------0------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~000~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------1----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0----0---------------------------0----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------0--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------0------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------01----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------0----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ -------------------------------------------10----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------1--10----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-----------------------------------------0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0----0-------------------------------------0------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-------------------------------------------0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~ -----0---------------------------------------------0---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------1--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~0~~0~~ -----------------------------------------1----------1--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------1------1--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------1-----1--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------1----1--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ -----------------------------------------------0----1--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------0--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~0~~~~~~~~0~~~~~~0~~~~~~~~~0~~~ ----------------------------------------1-----------0--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------0----------0--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------0--------0--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------1-------0--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------0--0--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ --------------------------------------------------1-0--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------00--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ -----------------------------------------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------0---------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------1--------10-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------0--10-------10-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ ------------------------------------------------0---10-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ ----------------------------------------------------0-1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~ ------------------------------------------------------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~00~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------1--0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------1---0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------0----------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------0-------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------0--0-------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------1---1------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ ----------------------------------------1----------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------0---1------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ -------------------------------------------01------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ ----------------------------------------------------0----0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ -----------------------------------------------------1---0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ ----------------------------------------------------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ ------------------------------------------------------1---1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ ------------------------------------------------------0---0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ -----1-00-0------------------------------------------------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 ------------------------------------------------0---10-----1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~ -1----0--------1--------------------------------0---10-----1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ ------0--------10-------------------------------0---10-----1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ ------0--------1----------------1---------------0---10-----1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ ------0--------1----------------0---------------0---10-----1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ ----------------------------------------------------1------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ -----1-00-0-------------------------------------------------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 -----------------------------------------------0------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ -----------------------------------------------------------00------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ -----01------------------------------------------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ -----0---------1--------------------------------1------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ -----0----------------------------------------------0--------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ -----0---------1-------------------------------------1-------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ -----0---------1-------------------------------------------0-0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ -----01-------------------------------------------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ -----0---------1--------------------------------1-------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ -----0----------------------------------------------0---------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ -----0---------1-------------------------------------1--------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ -----0---------1-------------------------------------------0--0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ ---0-----------------------------------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------0-----------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------0----------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------0--------------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------0-------------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------0-----------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------0--------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------0-1---------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ -----0-----------------------------------------------------------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ -1----0--------0------------------------------------1-------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ ------0--------00-----------------------------------1-------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ ------0--------0----------------1-------------------1-------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ ------0--------0----------------0-------------------1-------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ -----0---------0---------------------------------------------0----0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ -----0---------0----------------------------------------------0---0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ ----------------------------------------10-00-----0-1----1---------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------0--------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ ------------------------------------------------------------------00------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ ------------------------------------------------1-------------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ -----------------------------------------------------1--------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ -----------------------------------------------------------0--------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ ------------------------------------------------------------------0-0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ----------------------------------------------------0----------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~ -------------------------------------------------1-1-----------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ ----------------------------------------------------------------0----0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~ -------------------------------------------------------------------0-0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ ----------------------------------------------------1-----------------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ ------------------------------------------------------0---------------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ ------------------------------------------------------------0---------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ ----------------------------------------------------------------0-----0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ --------0-1------------------------------------------------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 -----------------------------------------------0------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ --------------------------------------------------1-1--------------1-----0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~ +.i 68 +.o 110 +.ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 CPU_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_ IPL_030_1_.Q IPL_030_2_.Q BGACK_030.Q FPU_CS.Q E.Q VMA.Q cpu_est_0_.Q cpu_est_1_.Q AS_000.Q inst_AS_030_000_SYNC.Q inst_DTACK_SYNC.Q inst_VPA_D.Q inst_VPA_SYNC.Q inst_CLK_000_D.Q inst_CLK_000_DD.Q inst_CLK_OUT_PRE.Q cpu_est_2_.Q CLK_CNT_0_.Q SM_AMIGA_6_.Q SM_AMIGA_7_.Q UDS_000.Q LDS_000.Q SM_AMIGA_1_.Q DSACK_1_.Q SM_AMIGA_4_.Q SM_AMIGA_3_.Q SM_AMIGA_5_.Q SM_AMIGA_2_.Q SM_AMIGA_0_.Q BG_000.Q IPL_030_0_.Q DSACK_1_.PIN DTACK.PIN +.ob BERR AVEC AVEC_EXP AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.C SM_AMIGA_0_.AR IPL_030_0_.C IPL_030_0_.AP IPL_030_1_.C IPL_030_1_.AP IPL_030_2_.C IPL_030_2_.AP SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.C SM_AMIGA_4_.AR DSACK_1_.C DSACK_1_.AP VMA.C VMA.AP BGACK_030.C BGACK_030.AP inst_CLK_OUT_PRE.C cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C E.C LDS_000.C LDS_000.AP inst_DTACK_SYNC.C inst_DTACK_SYNC.AP FPU_CS.C FPU_CS.AP inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP AS_000.C AS_000.AP inst_VPA_SYNC.C inst_VPA_SYNC.AP BG_000.C BG_000.AP DTACK.C DTACK.AP UDS_000.C UDS_000.AP CLK_CNT_0_.C inst_VPA_D.C inst_CLK_000_D.C RESET.C inst_CLK_000_DD.C CLK_EXP.C DSACK_0_ DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_DIV_OUT.C CLK_DIV_OUT.D IPL_030_1_.D IPL_030_2_.D BGACK_030.D FPU_CS.D E.T VMA.T cpu_est_0_.D cpu_est_1_.T AS_000.D inst_AS_030_000_SYNC.D inst_DTACK_SYNC.D inst_VPA_D.D inst_VPA_SYNC.D inst_CLK_000_D.D inst_CLK_000_DD.D inst_CLK_OUT_PRE.D cpu_est_2_.D RESET.D CLK_CNT_0_.D SM_AMIGA_6_.D SM_AMIGA_7_.D UDS_000.D LDS_000.D SM_AMIGA_1_.D DSACK_1_.D DTACK.D SM_AMIGA_4_.D SM_AMIGA_3_.D SM_AMIGA_5_.D SM_AMIGA_2_.D SM_AMIGA_0_.D BG_000.D CLK_EXP.D IPL_030_0_.D +.p 273 +-------------------------------------------------------------------- ~1~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~ +----11-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~ +------0------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------1------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +---0-----1---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------1--1---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~ +--------01---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0----0---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +------1--0---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +----------1--------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~ +-----------1-------------------------------------------------------- ~~~~~~~1~1~1~1~1~1~1~1~1~1~1~1~1~1~111111~1~1~1~1~1~1~1~1~111111~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------1------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +-------------1------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~ +-------------0------------------------------------------------------ ~~~~~~~~1~1~1~1~1~1~1~1~1~1~1~1~1~1~~~~~~1~1~1~1~1~1~1~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------0----------------------------------------------------- ~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-0--------------0000000--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------1111----------------------------------------- ~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1-----------------1---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1------------------1--------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1-------------------0-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1--------------------1------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1----11-----------------0010---1--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~ +---------1------------------------0--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~111~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------1----------------------------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------0------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------0----------------------------1----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1----------------------------------0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +----1-----------------------------------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +----1------------------------------------1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +----1-------------------------------------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~ +----1---------------------------------------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +---------0----------------------------------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~ +----1---------1-----------------------------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~ +-------------------------------------------11----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +----1-----------------------------------------1--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +----1-----------------------------------------0--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------10--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------0-------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------1------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------1-----1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------1----1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------11-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ +----1-------------------------------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~ +----1-------------------------------------------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~1~~~~~~~~11~~~~~~~~~~~ +-----------------------------------1------------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------1-----------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------1------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------1----0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------1--0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------10------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +----1--------------------------------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +----1---------1----------------------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~ +-----------------------------------1-------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------1------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------1-------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------1-----1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +--1---------------------------------------------10------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------1---------------------------------------10------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------1---------------10------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------1--------------10------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +---------------------------------------1-1------10------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~ +-----------------------------------------0------10------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------00-----10------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~ +---------------------------------------1-00-----10------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +----1---------------------------------------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~ +------------------------------------------1--------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~ +---------------------------------------00011----1--1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------0--1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~ +---------------------------------------0110---0-0--1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------1-1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~ +---------------------------------------0-1------10-1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------1-11-----10-1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1----------------------------------------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------1---0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------1-11-----10-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------0-11-----10-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------0--0-----10-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------0-00-----10-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------0-1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ +----------------------------------------------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~ +--------------------------------------------------1-0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ +--------------------------------------------1--------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +------------------------------------------------0----1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +-------------------------------------------------1---1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +--------------------------------------------0---10---1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~ +-----0--------1----------------1------------0---10---1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +0----0--------11---------------0------------0---10---1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +----1------------------------------------------------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +----1---------1--------------------------------------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~ +-------------------------------------------1---------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------1-----1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +------------------------------------------------0-----1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +---------0-------------------------------------------00------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +-----1-------------------------------------------------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +--------------1-----------------------------1----------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +------------------------------------------------0------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +--------------1----------------------------------1-----1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +--------------1--------------------------------------0-1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +-----1--------------------------------------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +--------------1-----------------------------1-----------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +------------------------------------------------0-------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +--------------1----------------------------------1------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +--------------1--------------------------------------0--1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +------------------------------------------------1--------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~ +------------------------------------------------0-1------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ +----1----------------------------------------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~ +------------------------------------------------1---------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~ +--------------------------------------------------0-------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~ +---------------------------------------------------------01--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~ +------------------------------------------------1----------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ +-----0--------0----------------1----------------1----------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +0----0--------01---------------0----------------1----------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +------------------------------------------------0----------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~ +----1---------0--------------------------------------------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~ +--------------0----------------------------------------1---0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +--------------0-----------------------------------------1--0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +---------------------------------------------1-1------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ +------------------------------------------------1-----------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ +---------------------------------------------0--0-----------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ +-----------------------------------------------00-----------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ +----1-------------------------------------------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------1--------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------1------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------1------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~ +------------------------------------------------0------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~ +------------------------------------------------1-------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~ +------------------------------------------------0-------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ +--------------------------------------------------0------1----0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~ +-------------------------------------------0-------------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ +-------------------------------------------1----1--------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +------------------------------------------------0--------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ +---------1------------------------------------------------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +------------------------------------------------0----------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +-------------------------------------------------1---------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +------------------------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~ +----1--------------------------------------------------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------1---------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------------------------- 0~00~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-1------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------1------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------0----------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---00-0--1---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~ +----0-0-01---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~ +----------0--------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ +-----------0-------------------------------------------------------- ~~~~~~~0~0~0~0~0~0~0~0~0~0~0~0~0~0~000000~0~0~0~0~0~0~0~0~000000~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------0------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ +-------------1------------------------------------------------------ ~~~~~~~~0~0~0~0~0~0~0~0~0~0~0~0~0~0~~~~~~0~0~0~0~0~0~0~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------0------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ +--------------1----------------------------------------------------- ~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------1--------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------1-------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------1------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------1----------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------1---------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------1--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------0-------------------------------------------- ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------0------------------------------------------- ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------0------------------------------------------ ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------0----------------------------------------- ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-0--1-----------------1---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~ +----0-0--1------------------1--------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~ +----0-0--1-------------------0-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~ +----0-0--1--------------------1------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~ +---10---11-----------------0010---1--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-0--1------------------------0--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------0------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~000~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0----0----------------------------0----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------1---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------01-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------01------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~0~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------10------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------1-10------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------00------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0--------------------------------------0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ +----0----0----------------------------------0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~ +----0----------------------------------------0---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~ +----0------------------------------------------0-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~0~~~~ +----------------------------------------1-------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------1----1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ +-------------------------------------------0----1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~0~~~~~~0~~~~~0~~~~~~~0~~~~~ +-----------------------------------0------------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------0-----------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------0----------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------0------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------1-----0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------0--0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +----------------------------------------------1-0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------00------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +-------------------------------------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~0~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------0-------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------0------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------0-----------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------0-------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--0---------------------------------------------10------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------0---------------10------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------0--------------10------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 +-----------------------------------------1------10------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------0-10-----10------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ +--------------------------------------------0---10------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ +------------------------------------------------0-1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ +--------------------------------------------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ +---------------------------------------0-----------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------0---------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------0-0---------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------1--1--------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------1-----------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------0--1--------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~0~~~~~~~~~~~~~~~~~ +-----------------------------------------01--------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ +------------------------------------------------0--0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ +-------------------------------------------------1-0---------------- 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +---------------------------------------------------------0----0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ +------------------------------------------------------------0-0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +------------------------------------------------1--------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ +--------------------------------------------------0------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ +------------------------------------------------------0--------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +---------------------------------------------------------0-----0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ +-------0-1------------------------------------------------------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ +------------------------------------------------0----------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 +-------------------------------------------------1---------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 +-------------------------------------------0----------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~ +----------------------------------------------1-1-----------1------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~ .end diff --git a/Logic/68030_tk.tt4 b/Logic/68030_tk.tt4 index 89d9184..06d9777 100644 --- a/Logic/68030_tk.tt4 +++ b/Logic/68030_tk.tt4 @@ -1,156 +1,150 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Thu May 15 22:21:53 2014 +#$ DATE Thu May 15 23:02:46 2014 #$ MODULE BUS68030 -#$ PINS 59 A_28_ A_27_ SIZE_1_ A_26_ A_25_ A_31_ A_24_ A_23_ A_22_ A_21_ IPL_2_ - A_20_ A_19_ A_18_ A_17_ FC_1_ A_16_ AS_030 DS_030 CPU_SPACE BERR BG_030 - BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT A_0_ AVEC IPL_1_ AVEC_EXP IPL_0_ - DSACK_0_ VPA FC_0_ RST RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR - AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 - LDS_000 BG_000 BGACK_030 CLK_EXP FPU_CS IPL_030_1_ DTACK IPL_030_0_ E VMA RESET -#$ NODES 24 cpu_est_0_ cpu_est_1_ cpu_est_d_0_ cpu_est_d_3_ - inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D - inst_CLK_000_DD inst_CLK_OUT_PRE cpu_est_d_1_ cpu_est_d_2_ cpu_est_2_ CLK_CNT_0_ - SM_AMIGA_6_ SM_AMIGA_7_ inst_RISING_CLK_AMIGA SM_AMIGA_1_ SM_AMIGA_4_ +#$ PINS 59 A_21_ A_20_ SIZE_1_ A_19_ A_18_ A_31_ A_17_ A_16_ IPL_2_ FC_1_ + AS_030 DS_030 CPU_SPACE BERR BG_030 A_0_ BGACK_000 CLK_030 IPL_1_ CLK_000 IPL_0_ + CLK_OSZI DSACK_0_ CLK_DIV_OUT FC_0_ AVEC AVEC_EXP VPA RST RW AMIGA_BUS_ENABLE + AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ A_28_ A_27_ + A_26_ A_25_ A_24_ A_23_ A_22_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 BG_000 + BGACK_030 IPL_030_1_ IPL_030_0_ CLK_EXP FPU_CS DTACK E VMA RESET +#$ NODES 19 cpu_est_0_ cpu_est_1_ inst_AS_030_000_SYNC inst_DTACK_SYNC + inst_VPA_D inst_VPA_SYNC inst_CLK_000_D inst_CLK_000_DD inst_CLK_OUT_PRE + cpu_est_2_ CLK_CNT_0_ SM_AMIGA_6_ SM_AMIGA_7_ SM_AMIGA_1_ SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_5_ SM_AMIGA_2_ SM_AMIGA_0_ .type f -.i 73 -.o 121 +.i 68 +.o 111 .ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 CPU_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_ - IPL_030_0_.Q BGACK_030.Q FPU_CS.Q IPL_030_1_.Q E.Q VMA.Q IPL_030_2_.Q - cpu_est_0_.Q cpu_est_1_.Q cpu_est_d_0_.Q cpu_est_d_3_.Q AS_000.Q - inst_AS_030_000_SYNC.Q inst_DTACK_SYNC.Q inst_VPA_D.Q inst_VPA_SYNC.Q - inst_CLK_000_D.Q inst_CLK_000_DD.Q inst_CLK_OUT_PRE.Q cpu_est_d_1_.Q - cpu_est_d_2_.Q cpu_est_2_.Q CLK_CNT_0_.Q SM_AMIGA_6_.Q SM_AMIGA_7_.Q UDS_000.Q - LDS_000.Q inst_RISING_CLK_AMIGA.Q SM_AMIGA_1_.Q DSACK_1_.Q SM_AMIGA_4_.Q - SM_AMIGA_3_.Q SM_AMIGA_5_.Q SM_AMIGA_2_.Q SM_AMIGA_0_.Q BG_000.Q DSACK_1_.PIN - DTACK.PIN -.ob BERR BERR.OE CLK_DIV_OUT.D CLK_DIV_OUT.C AVEC AVEC_EXP AVEC_EXP.OE DSACK_0_ - DSACK_0_.OE AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN + IPL_030_1_.Q IPL_030_2_.Q BGACK_030.Q FPU_CS.Q E.Q VMA.Q cpu_est_0_.Q + cpu_est_1_.Q AS_000.Q inst_AS_030_000_SYNC.Q inst_DTACK_SYNC.Q inst_VPA_D.Q + inst_VPA_SYNC.Q inst_CLK_000_D.Q inst_CLK_000_DD.Q inst_CLK_OUT_PRE.Q + cpu_est_2_.Q CLK_CNT_0_.Q SM_AMIGA_6_.Q SM_AMIGA_7_.Q UDS_000.Q LDS_000.Q + SM_AMIGA_1_.Q DSACK_1_.Q SM_AMIGA_4_.Q SM_AMIGA_3_.Q SM_AMIGA_5_.Q SM_AMIGA_2_.Q + SM_AMIGA_0_.Q BG_000.Q IPL_030_0_.Q DSACK_1_.PIN DTACK.PIN +.ob BERR BERR.OE DSACK_0_ DSACK_0_.OE CLK_DIV_OUT.D CLK_DIV_OUT.C AVEC AVEC_EXP + AVEC_EXP.OE AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN CIIN.OE IPL_030_2_.D IPL_030_2_.C IPL_030_2_.AP DSACK_1_.D% DSACK_1_.C DSACK_1_.AP DSACK_1_.OE AS_000.D% AS_000.C AS_000.AP AS_000.OE UDS_000.D% UDS_000.C UDS_000.AP UDS_000.OE LDS_000.D% LDS_000.C LDS_000.AP LDS_000.OE - BG_000.D% BG_000.C BG_000.AP BGACK_030.D BGACK_030.C BGACK_030.AP CLK_EXP.D - CLK_EXP.C FPU_CS.D% FPU_CS.C FPU_CS.AP IPL_030_1_.D IPL_030_1_.C IPL_030_1_.AP - DTACK.D% DTACK.C DTACK.AP DTACK.OE IPL_030_0_.D IPL_030_0_.C IPL_030_0_.AP E.T + BG_000.D% BG_000.C BG_000.AP BGACK_030.D BGACK_030.C BGACK_030.AP IPL_030_1_.D + IPL_030_1_.C IPL_030_1_.AP IPL_030_0_.D IPL_030_0_.C IPL_030_0_.AP CLK_EXP.D + CLK_EXP.C FPU_CS.D% FPU_CS.C FPU_CS.AP DTACK.D% DTACK.C DTACK.AP DTACK.OE E.T E.C VMA.T VMA.C VMA.AP RESET.D RESET.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.T - cpu_est_1_.C cpu_est_d_0_.D cpu_est_d_0_.C cpu_est_d_3_.D cpu_est_d_3_.C - inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP - inst_DTACK_SYNC.D% inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_VPA_D.D - inst_VPA_D.C inst_VPA_SYNC.D% inst_VPA_SYNC.C inst_VPA_SYNC.AP inst_CLK_000_D.D - inst_CLK_000_D.C inst_CLK_000_DD.D inst_CLK_000_DD.C inst_CLK_OUT_PRE.D - inst_CLK_OUT_PRE.C cpu_est_d_1_.D cpu_est_d_1_.C cpu_est_d_2_.D cpu_est_d_2_.C - cpu_est_2_.D.X1 cpu_est_2_.D.X2 cpu_est_2_.C CLK_CNT_0_.D CLK_CNT_0_.C - SM_AMIGA_6_.D% SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_7_.D SM_AMIGA_7_.C - SM_AMIGA_7_.AP inst_RISING_CLK_AMIGA.D inst_RISING_CLK_AMIGA.C SM_AMIGA_1_.D + cpu_est_1_.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C + inst_AS_030_000_SYNC.AP inst_DTACK_SYNC.D% inst_DTACK_SYNC.C inst_DTACK_SYNC.AP + inst_VPA_D.D inst_VPA_D.C inst_VPA_SYNC.D% inst_VPA_SYNC.C inst_VPA_SYNC.AP + inst_CLK_000_D.D inst_CLK_000_D.C inst_CLK_000_DD.D inst_CLK_000_DD.C + inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C cpu_est_2_.D.X1 cpu_est_2_.D.X2 + cpu_est_2_.C CLK_CNT_0_.D CLK_CNT_0_.C SM_AMIGA_6_.D% SM_AMIGA_6_.C + SM_AMIGA_6_.AR SM_AMIGA_7_.D SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR -.phase 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 -.p 103 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000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 .end diff --git a/Logic/68030_tk.tte b/Logic/68030_tk.tte index a188f96..4ec737f 100644 --- a/Logic/68030_tk.tte +++ b/Logic/68030_tk.tte @@ -1,156 +1,150 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Thu May 15 22:21:53 2014 +#$ DATE Thu May 15 23:02:46 2014 #$ MODULE BUS68030 -#$ PINS 59 A_28_ A_27_ SIZE_1_ A_26_ A_25_ A_31_ A_24_ A_23_ A_22_ A_21_ IPL_2_ - A_20_ A_19_ A_18_ A_17_ FC_1_ A_16_ AS_030 DS_030 CPU_SPACE BERR BG_030 - BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT A_0_ AVEC IPL_1_ AVEC_EXP IPL_0_ - DSACK_0_ VPA FC_0_ RST RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR - AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 - LDS_000 BG_000 BGACK_030 CLK_EXP FPU_CS IPL_030_1_ DTACK IPL_030_0_ E VMA RESET -#$ NODES 24 cpu_est_0_ cpu_est_1_ cpu_est_d_0_ cpu_est_d_3_ - inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D - inst_CLK_000_DD inst_CLK_OUT_PRE cpu_est_d_1_ cpu_est_d_2_ cpu_est_2_ CLK_CNT_0_ - SM_AMIGA_6_ SM_AMIGA_7_ inst_RISING_CLK_AMIGA SM_AMIGA_1_ SM_AMIGA_4_ +#$ PINS 59 A_21_ A_20_ SIZE_1_ A_19_ A_18_ A_31_ A_17_ A_16_ IPL_2_ FC_1_ + AS_030 DS_030 CPU_SPACE BERR BG_030 A_0_ BGACK_000 CLK_030 IPL_1_ CLK_000 IPL_0_ + CLK_OSZI DSACK_0_ CLK_DIV_OUT FC_0_ AVEC AVEC_EXP VPA RST RW AMIGA_BUS_ENABLE + AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ A_28_ A_27_ + A_26_ A_25_ A_24_ A_23_ A_22_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 BG_000 + BGACK_030 IPL_030_1_ IPL_030_0_ CLK_EXP FPU_CS DTACK E VMA RESET +#$ NODES 19 cpu_est_0_ cpu_est_1_ inst_AS_030_000_SYNC inst_DTACK_SYNC + inst_VPA_D inst_VPA_SYNC inst_CLK_000_D inst_CLK_000_DD inst_CLK_OUT_PRE + cpu_est_2_ CLK_CNT_0_ SM_AMIGA_6_ SM_AMIGA_7_ SM_AMIGA_1_ SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_5_ SM_AMIGA_2_ SM_AMIGA_0_ .type f -.i 73 -.o 121 +.i 68 +.o 111 .ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 CPU_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_ - IPL_030_0_.Q BGACK_030.Q FPU_CS.Q IPL_030_1_.Q E.Q VMA.Q IPL_030_2_.Q - cpu_est_0_.Q cpu_est_1_.Q cpu_est_d_0_.Q cpu_est_d_3_.Q AS_000.Q - inst_AS_030_000_SYNC.Q inst_DTACK_SYNC.Q inst_VPA_D.Q inst_VPA_SYNC.Q - inst_CLK_000_D.Q inst_CLK_000_DD.Q inst_CLK_OUT_PRE.Q cpu_est_d_1_.Q - cpu_est_d_2_.Q cpu_est_2_.Q CLK_CNT_0_.Q SM_AMIGA_6_.Q SM_AMIGA_7_.Q UDS_000.Q - LDS_000.Q inst_RISING_CLK_AMIGA.Q SM_AMIGA_1_.Q DSACK_1_.Q SM_AMIGA_4_.Q - SM_AMIGA_3_.Q SM_AMIGA_5_.Q SM_AMIGA_2_.Q SM_AMIGA_0_.Q BG_000.Q DSACK_1_.PIN - DTACK.PIN -.ob BERR BERR.OE CLK_DIV_OUT.D CLK_DIV_OUT.C AVEC AVEC_EXP AVEC_EXP.OE DSACK_0_ - DSACK_0_.OE AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN + IPL_030_1_.Q IPL_030_2_.Q BGACK_030.Q FPU_CS.Q E.Q VMA.Q cpu_est_0_.Q + cpu_est_1_.Q AS_000.Q inst_AS_030_000_SYNC.Q inst_DTACK_SYNC.Q inst_VPA_D.Q + inst_VPA_SYNC.Q inst_CLK_000_D.Q inst_CLK_000_DD.Q inst_CLK_OUT_PRE.Q + cpu_est_2_.Q CLK_CNT_0_.Q SM_AMIGA_6_.Q SM_AMIGA_7_.Q UDS_000.Q LDS_000.Q + SM_AMIGA_1_.Q DSACK_1_.Q SM_AMIGA_4_.Q SM_AMIGA_3_.Q SM_AMIGA_5_.Q SM_AMIGA_2_.Q + SM_AMIGA_0_.Q BG_000.Q IPL_030_0_.Q DSACK_1_.PIN DTACK.PIN +.ob BERR BERR.OE DSACK_0_ DSACK_0_.OE CLK_DIV_OUT.D CLK_DIV_OUT.C AVEC AVEC_EXP + AVEC_EXP.OE AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN CIIN.OE IPL_030_2_.D IPL_030_2_.C IPL_030_2_.AP DSACK_1_.D- DSACK_1_.C DSACK_1_.AP DSACK_1_.OE AS_000.D- AS_000.C AS_000.AP AS_000.OE UDS_000.D- UDS_000.C UDS_000.AP UDS_000.OE LDS_000.D- LDS_000.C LDS_000.AP LDS_000.OE - BG_000.D- BG_000.C BG_000.AP BGACK_030.D BGACK_030.C BGACK_030.AP CLK_EXP.D - CLK_EXP.C FPU_CS.D- FPU_CS.C FPU_CS.AP IPL_030_1_.D IPL_030_1_.C IPL_030_1_.AP - DTACK.D- DTACK.C DTACK.AP DTACK.OE IPL_030_0_.D IPL_030_0_.C IPL_030_0_.AP E.T + BG_000.D- BG_000.C BG_000.AP BGACK_030.D BGACK_030.C BGACK_030.AP IPL_030_1_.D + IPL_030_1_.C IPL_030_1_.AP IPL_030_0_.D IPL_030_0_.C IPL_030_0_.AP CLK_EXP.D + CLK_EXP.C FPU_CS.D- FPU_CS.C FPU_CS.AP DTACK.D- DTACK.C DTACK.AP DTACK.OE E.T E.C VMA.T VMA.C VMA.AP RESET.D RESET.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.T - cpu_est_1_.C cpu_est_d_0_.D cpu_est_d_0_.C cpu_est_d_3_.D cpu_est_d_3_.C - inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP - inst_DTACK_SYNC.D- inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_VPA_D.D - inst_VPA_D.C inst_VPA_SYNC.D- inst_VPA_SYNC.C inst_VPA_SYNC.AP inst_CLK_000_D.D - inst_CLK_000_D.C inst_CLK_000_DD.D inst_CLK_000_DD.C inst_CLK_OUT_PRE.D - inst_CLK_OUT_PRE.C cpu_est_d_1_.D cpu_est_d_1_.C cpu_est_d_2_.D cpu_est_d_2_.C - cpu_est_2_.D.X1 cpu_est_2_.D.X2 cpu_est_2_.C CLK_CNT_0_.D CLK_CNT_0_.C - SM_AMIGA_6_.D- SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_7_.D SM_AMIGA_7_.C - SM_AMIGA_7_.AP inst_RISING_CLK_AMIGA.D inst_RISING_CLK_AMIGA.C SM_AMIGA_1_.D + cpu_est_1_.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C + inst_AS_030_000_SYNC.AP inst_DTACK_SYNC.D- inst_DTACK_SYNC.C inst_DTACK_SYNC.AP + inst_VPA_D.D inst_VPA_D.C inst_VPA_SYNC.D- inst_VPA_SYNC.C inst_VPA_SYNC.AP + inst_CLK_000_D.D inst_CLK_000_D.C inst_CLK_000_DD.D inst_CLK_000_DD.C + inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C cpu_est_2_.D.X1 cpu_est_2_.D.X2 + cpu_est_2_.C CLK_CNT_0_.D CLK_CNT_0_.C SM_AMIGA_6_.D- SM_AMIGA_6_.C + SM_AMIGA_6_.AR SM_AMIGA_7_.D SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR -.phase 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 -.p 103 -------------------------------------------------------------------------- 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000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 .end diff --git a/Logic/68030_tk.vcl b/Logic/68030_tk.vcl index 9784d60..78564b3 100644 --- a/Logic/68030_tk.vcl +++ b/Logic/68030_tk.vcl @@ -18,7 +18,7 @@ SDS_file = m4a5.sds; Design = 68030_tk.tt4; Rev = 0.01; DATE = 5/15/14; -TIME = 22:21:57; +TIME = 23:02:49; Type = TT2; Pre_Fit_Time = 1; Source_Format = Pure_VHDL; @@ -137,13 +137,13 @@ LDS_000 = OUTPUT,31,3,-; UDS_000 = OUTPUT,32,3,-; E = OUTPUT,66,6,-; BG_000 = OUTPUT,29,3,-; +IPL_030_2_ = OUTPUT,9,1,-; +IPL_030_0_ = OUTPUT,8,1,-; +IPL_030_1_ = OUTPUT,7,1,-; BGACK_030 = OUTPUT,83,7,-; FPU_CS = OUTPUT,78,7,-; VMA = OUTPUT,35,3,-; AS_000 = OUTPUT,33,3,-; -IPL_030_2_ = OUTPUT,9,1,-; -IPL_030_0_ = OUTPUT,8,1,-; -IPL_030_1_ = OUTPUT,7,1,-; AVEC = OUTPUT,92,0,-; DSACK_0_ = OUTPUT,80,7,-; CLK_DIV_OUT = OUTPUT,65,6,-; @@ -155,40 +155,35 @@ AVEC_EXP = OUTPUT,22,2,-; AMIGA_BUS_ENABLE_LOW = OUTPUT,20,2,-; CLK_EXP = OUTPUT,10,1,-; RESET = OUTPUT,3,1,-; +inst_CLK_000_DD = NODE,*,3,-; inst_CLK_000_D = NODE,*,7,-; -cpu_est_1_ = NODE,*,6,-; -RN_E = NODE,-1,6,-; -SM_AMIGA_3_ = NODE,*,1,-; -cpu_est_2_ = NODE,*,6,-; -cpu_est_0_ = NODE,*,6,-; +inst_AS_030_000_SYNC = NODE,*,5,-; RN_FPU_CS = NODE,-1,7,-; -inst_CLK_OUT_PRE = NODE,*,6,-; -inst_VPA_SYNC = NODE,*,0,-; -inst_VPA_D = NODE,*,6,-; -inst_AS_030_000_SYNC = NODE,*,7,-; -SM_AMIGA_1_ = NODE,*,6,-; +inst_CLK_OUT_PRE = NODE,*,7,-; +cpu_est_1_ = NODE,*,3,-; +RN_E = NODE,-1,6,-; +SM_AMIGA_2_ = NODE,*,6,-; +SM_AMIGA_6_ = NODE,*,3,-; +cpu_est_2_ = NODE,*,3,-; +cpu_est_0_ = NODE,*,3,-; RN_VMA = NODE,-1,3,-; RN_BGACK_030 = NODE,-1,7,-; RN_AS_000 = NODE,-1,3,-; -SM_AMIGA_4_ = NODE,*,3,-; -SM_AMIGA_7_ = NODE,*,6,-; -inst_DTACK_SYNC = NODE,*,1,-; -inst_RISING_CLK_AMIGA = NODE,*,7,-; -inst_CLK_000_DD = NODE,*,7,-; +SM_AMIGA_5_ = NODE,*,0,-; +SM_AMIGA_4_ = NODE,*,6,-; +SM_AMIGA_7_ = NODE,*,7,-; +inst_VPA_D = NODE,*,6,-; RN_LDS_000 = NODE,-1,3,-; RN_UDS_000 = NODE,-1,3,-; -RN_BG_000 = NODE,-1,3,-; -SM_AMIGA_0_ = NODE,*,6,-; -SM_AMIGA_2_ = NODE,*,6,-; -SM_AMIGA_6_ = NODE,*,3,-; RN_IPL_030_0_ = NODE,-1,1,-; RN_IPL_030_1_ = NODE,-1,1,-; -RN_DSACK_1_ = NODE,-1,7,-; +RN_BG_000 = NODE,-1,3,-; RN_IPL_030_2_ = NODE,-1,1,-; -SM_AMIGA_5_ = NODE,*,3,-; -CLK_CNT_0_ = NODE,*,6,-; -cpu_est_d_2_ = NODE,*,6,-; -cpu_est_d_1_ = NODE,*,6,-; -cpu_est_d_3_ = NODE,*,6,-; -cpu_est_d_0_ = NODE,*,6,-; +SM_AMIGA_0_ = NODE,*,7,-; +SM_AMIGA_3_ = NODE,*,6,-; +SM_AMIGA_1_ = NODE,*,7,-; +RN_DSACK_1_ = NODE,-1,7,-; +inst_VPA_SYNC = NODE,*,6,-; +inst_DTACK_SYNC = NODE,*,6,-; +CLK_CNT_0_ = NODE,*,7,-; CLK_OSZI = INPUT,61,-,-; diff --git a/Logic/68030_tk.vco b/Logic/68030_tk.vco index 944c26d..7cab251 100644 --- a/Logic/68030_tk.vco +++ b/Logic/68030_tk.vco @@ -18,7 +18,7 @@ SDS_file = m4a5.sds; Design = 68030_tk.tt4; Rev = 0.01; DATE = 5/15/14; -TIME = 22:21:57; +TIME = 23:02:50; Type = TT2; Pre_Fit_Time = 1; Source_Format = Pure_VHDL; @@ -131,41 +131,34 @@ Usercode_Format = Hex; [LOCATION ASSIGNMENT] Layer = OFF; -A_28_ = INPUT,15, C,-; -A_27_ = INPUT,16, C,-; -SIZE_1_ = INPUT,79, H,-; -A_26_ = INPUT,17, C,-; -A_25_ = INPUT,18, C,-; -A_31_ = INPUT,4, B,-; -A_24_ = INPUT,19, C,-; -A_23_ = INPUT,84, H,-; -A_22_ = INPUT,85, H,-; A_21_ = INPUT,94, A,-; -IPL_2_ = INPUT,68, G,-; A_20_ = INPUT,93, A,-; +SIZE_1_ = INPUT,79, H,-; A_19_ = INPUT,97, A,-; A_18_ = INPUT,95, A,-; +A_31_ = INPUT,4, B,-; A_17_ = INPUT,59, F,-; -FC_1_ = INPUT,58, F,-; A_16_ = INPUT,96, A,-; +IPL_2_ = INPUT,68, G,-; +FC_1_ = INPUT,58, F,-; AS_030 = INPUT,82, H,-; DS_030 = INPUT,98, A,-; CPU_SPACE = INPUT,14,-,-; BERR = OUTPUT,41, E,-; BG_030 = INPUT,21, C,-; +A_0_ = INPUT,69, G,-; BGACK_000 = INPUT,28, D,-; CLK_030 = INPUT,64,-,-; -CLK_000 = INPUT,11,-,-; -CLK_OSZI = INPUT,61,-,-; -CLK_DIV_OUT = OUTPUT,65, G,-; -A_0_ = INPUT,69, G,-; -AVEC = OUTPUT,92, A,-; IPL_1_ = INPUT,56, F,-; -AVEC_EXP = OUTPUT,22, C,-; +CLK_000 = INPUT,11,-,-; IPL_0_ = INPUT,67, G,-; +CLK_OSZI = INPUT,61,-,-; DSACK_0_ = OUTPUT,80, H,-; -VPA = INPUT,36,-,-; +CLK_DIV_OUT = OUTPUT,65, G,-; FC_0_ = INPUT,57, F,-; +AVEC = OUTPUT,92, A,-; +AVEC_EXP = OUTPUT,22, C,-; +VPA = INPUT,36,-,-; RST = INPUT,86,-,-; RW = INPUT,71, G,-; AMIGA_BUS_ENABLE = OUTPUT,34, D,-; @@ -175,6 +168,13 @@ CIIN = OUTPUT,47, E,-; SIZE_0_ = INPUT,70, G,-; A_30_ = INPUT,5, B,-; A_29_ = INPUT,6, B,-; +A_28_ = INPUT,15, C,-; +A_27_ = INPUT,16, C,-; +A_26_ = INPUT,17, C,-; +A_25_ = INPUT,18, C,-; +A_24_ = INPUT,19, C,-; +A_23_ = INPUT,84, H,-; +A_22_ = INPUT,85, H,-; IPL_030_2_ = OUTPUT,9, B,-; DSACK_1_ = BIDIR,81, H,-; AS_000 = OUTPUT,33, D,-; @@ -182,35 +182,30 @@ UDS_000 = OUTPUT,32, D,-; LDS_000 = OUTPUT,31, D,-; BG_000 = OUTPUT,29, D,-; BGACK_030 = OUTPUT,83, H,-; +IPL_030_1_ = OUTPUT,7, B,-; +IPL_030_0_ = OUTPUT,8, B,-; CLK_EXP = OUTPUT,10, B,-; FPU_CS = OUTPUT,78, H,-; -IPL_030_1_ = OUTPUT,7, B,-; DTACK = BIDIR,30, D,-; -IPL_030_0_ = OUTPUT,8, B,-; E = OUTPUT,66, G,-; VMA = OUTPUT,35, D,-; RESET = OUTPUT,3, B,-; -cpu_est_0_ = NODE,8, G,-; -cpu_est_1_ = NODE,6, G,-; -cpu_est_d_0_ = NODE,15, G,-; -cpu_est_d_3_ = NODE,11, G,-; -inst_AS_030_000_SYNC = NODE,8, H,-; -inst_DTACK_SYNC = NODE,9, B,-; +cpu_est_0_ = NODE,14, D,-; +cpu_est_1_ = NODE,2, D,-; +inst_AS_030_000_SYNC = NODE,0, F,-; +inst_DTACK_SYNC = NODE,13, G,-; inst_VPA_D = NODE,1, G,-; -inst_VPA_SYNC = NODE,0, A,-; -inst_CLK_000_D = NODE,2, H,-; -inst_CLK_000_DD = NODE,13, H,-; -inst_CLK_OUT_PRE = NODE,12, G,-; -cpu_est_d_1_ = NODE,7, G,-; -cpu_est_d_2_ = NODE,3, G,-; -cpu_est_2_ = NODE,4, G,-; -CLK_CNT_0_ = NODE,14, G,-; +inst_VPA_SYNC = NODE,9, G,-; +inst_CLK_000_D = NODE,1, H,-; +inst_CLK_000_DD = NODE,13, D,-; +inst_CLK_OUT_PRE = NODE,5, H,-; +cpu_est_2_ = NODE,10, D,-; +CLK_CNT_0_ = NODE,6, H,-; SM_AMIGA_6_ = NODE,6, D,-; -SM_AMIGA_7_ = NODE,9, G,-; -inst_RISING_CLK_AMIGA = NODE,9, H,-; -SM_AMIGA_1_ = NODE,5, G,-; -SM_AMIGA_4_ = NODE,13, D,-; -SM_AMIGA_3_ = NODE,5, B,-; -SM_AMIGA_5_ = NODE,10, D,-; -SM_AMIGA_2_ = NODE,10, G,-; -SM_AMIGA_0_ = NODE,13, G,-; +SM_AMIGA_7_ = NODE,9, H,-; +SM_AMIGA_1_ = NODE,2, H,-; +SM_AMIGA_4_ = NODE,12, G,-; +SM_AMIGA_3_ = NODE,5, G,-; +SM_AMIGA_5_ = NODE,0, A,-; +SM_AMIGA_2_ = NODE,8, G,-; +SM_AMIGA_0_ = NODE,13, H,-; diff --git a/Logic/68030_tk.xrf b/Logic/68030_tk.xrf index 7979ab7..f1cfaf0 100644 --- a/Logic/68030_tk.xrf +++ b/Logic/68030_tk.xrf @@ -2,7 +2,7 @@ Signal Name Cross Reference File ispLEVER Classic 1.7.00.05.28.13 -Design '68030_tk' created Thu May 15 22:21:53 2014 +Design '68030_tk' created Thu May 15 23:02:46 2014 LEGEND: '>' Functional Block Port Separator diff --git a/Logic/BUS68030.bl0 b/Logic/BUS68030.bl0 index 477021d..d5d0895 100644 --- a/Logic/BUS68030.bl0 +++ b/Logic/BUS68030.bl0 @@ -1,130 +1,127 @@ -#$ DATE Thu May 15 22:21:53 2014 +#$ DATE Thu May 15 23:02:46 2014 #$ TOOL EDIF2BLIF version IspLever 1.0 #$ MODULE bus68030 -#$ PINS 74 A_28_ A_27_ SIZE_1_ A_26_ A_25_ A_31_ A_24_ A_23_ IPL_030_2_ A_22_ A_21_ IPL_2_ A_20_ A_19_ DSACK_1_ A_18_ A_17_ FC_1_ A_16_ AS_030 A_15_ AS_000 A_14_ DS_030 A_13_ UDS_000 A_12_ LDS_000 A_11_ CPU_SPACE A_10_ BERR A_9_ BG_030 A_8_ BG_000 A_7_ BGACK_030 A_6_ BGACK_000 A_5_ CLK_030 A_4_ CLK_000 A_3_ CLK_OSZI A_2_ CLK_DIV_OUT A_1_ CLK_EXP A_0_ FPU_CS IPL_030_1_ DTACK IPL_030_0_ AVEC IPL_1_ AVEC_EXP IPL_0_ E DSACK_0_ VPA FC_0_ VMA RST RESET RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ -#$ NODES 351 CLK_OSZI_c CLK_OUT_INTreg IPL_030DFFSH_0_reg inst_BGACK_030_INTreg inst_FPU_CS_INTreg IPL_030DFFSH_1_reg cpu_est_3_reg inst_VMA_INTreg IPL_030DFFSH_2_reg gnd_n_n \ -# cpu_est_0_ ipl_c_0__n cpu_est_1_ cpu_est_d_0_ ipl_c_1__n cpu_est_d_3_ inst_AS_000_INTreg ipl_c_2__n inst_AS_030_000_SYNC inst_DTACK_SYNC \ -# inst_VPA_D dsack_c_1__n inst_VPA_SYNC inst_CLK_000_D DTACK_c inst_CLK_000_DD inst_CLK_OUT_PRE vcc_n_n cpu_est_d_1_ cpu_est_d_2_ \ -# cpu_est_2_ CLK_CNT_0_ SM_AMIGA_6_ RST_c SM_AMIGA_7_ inst_UDS_000_INTreg RESETDFFreg inst_LDS_000_INTreg RW_c inst_RISING_CLK_AMIGA \ -# state_machine_un57_clk_000_d_n fc_c_0__n SM_AMIGA_1_ DSACK_INT_1_ fc_c_1__n inst_DTACK_DMA SM_AMIGA_4_ SM_AMIGA_3_ state_machine_un13_as_000_int_n SM_AMIGA_5_ \ -# SM_AMIGA_2_ N_145_i SM_AMIGA_0_ a_c_i_0__n state_machine_uds_000_int_8_0_n state_machine_lds_000_int_8_0_n N_99_i N_112_i N_100_i N_101_i \ -# sm_amiga_ns_0_2__n N_103_i N_110_i sm_amiga_ns_0_7__n cpu_est_0_0_ N_91_0 N_92_0 N_131_i N_132_i N_122_i \ -# CLK_OUT_PRE_0 N_124_i N_125_i N_126_i N_129_i N_98 N_127_i N_97 N_128_i N_104 \ -# N_130_i N_93 clk_cpu_est_11_0_1__n N_105 N_134_i N_106 N_133_i N_108 N_135_i N_94 \ -# clk_cpu_est_11_0_3__n N_109 size_c_i_1__n N_107 state_machine_un31_clk_000_d_i_n N_135_1 state_machine_as_030_000_sync_3_0_n VPA_SYNC_1_sqmuxa_1_0 un1_as_030_2_0 N_167 \ -# state_machine_un17_clk_030_0_n N_170 state_machine_un57_clk_000_d_0_n state_machine_un42_clk_030_n RISING_CLK_AMIGA_i DTACK_SYNC_1_sqmuxa state_machine_un4_bgack_000_0_n VPA_SYNC_1_sqmuxa BG_030_c_i un1_bg_030 \ -# state_machine_un1_clk_030_0_n DTACK_SYNC_1_sqmuxa_1 N_97_i DSACK_INT_1_sqmuxa un1_bg_030_0 state_machine_un1_clk_030_n CLK_OUT_PRE_i state_machine_un4_bgack_000_n N_94_0 un1_as_030_2 \ -# N_93_0 state_machine_un17_clk_030_n N_108_i N_102 N_109_i AS_000_INT_1_sqmuxa VPA_SYNC_1_sqmuxa_1 N_106_i state_machine_as_030_000_sync_3_n N_107_i \ -# clk_un3_clk_000_dd_n sm_amiga_ns_0_5__n state_machine_un31_clk_000_d_n N_104_i UDS_000_INT_0_sqmuxa N_105_i state_machine_un13_clk_000_d_n state_machine_un13_clk_000_d_4_n un1_bg_030_0_1 state_machine_un13_clk_000_d_1_n \ -# un1_bg_030_0_2 state_machine_un8_clk_000_d_n state_machine_un31_clk_000_d_i_1_n UDS_000_INT_0_sqmuxa_1 clk_cpu_est_11_0_1_3__n N_132 clk_cpu_est_11_0_1_1__n N_131 clk_cpu_est_11_0_2_1__n N_124 \ -# N_167_1 clk_cpu_est_11_3__n N_167_2 N_135 N_167_3 N_133 N_167_4 N_134 N_167_5 clk_cpu_est_11_1__n \ -# N_167_6 N_130 N_170_1 N_128 N_170_2 N_145 N_107_1 N_127 state_machine_un42_clk_030_1_n N_129 \ -# state_machine_un42_clk_030_2_n N_126 state_machine_un42_clk_030_3_n N_125 state_machine_un42_clk_030_4_n N_92 state_machine_un42_clk_030_5_n N_91 DTACK_SYNC_1_sqmuxa_1_0 N_110 \ -# VPA_SYNC_1_sqmuxa_1_1 N_103 VPA_SYNC_1_sqmuxa_2 N_101 VPA_SYNC_1_sqmuxa_3 N_100 VPA_SYNC_1_sqmuxa_4 N_112 N_98_1 N_99 \ -# state_machine_as_030_000_sync_3_0_1_n state_machine_lds_000_int_8_n UDS_000_INT_0_sqmuxa_1_0 state_machine_uds_000_int_8_n UDS_000_INT_0_sqmuxa_2 un2_clk_030_1 state_machine_un13_clk_000_d_1_0_n VMA_INT_1_sqmuxa state_machine_un13_clk_000_d_4_1_n RW_i \ -# state_machine_un8_clk_000_d_1_n cpu_est_d_i_3__n state_machine_un8_clk_000_d_2_n cpu_est_d_i_0__n state_machine_un8_clk_000_d_3_n CLK_000_D_i state_machine_un8_clk_000_d_4_n AS_000_INT_i UDS_000_INT_0_sqmuxa_1_1 dsack_i_1__n \ -# UDS_000_INT_0_sqmuxa_1_2 state_machine_un13_clk_000_d_i_n UDS_000_INT_0_sqmuxa_1_3 state_machine_un8_clk_000_d_i_n N_132_1 AS_030_i N_131_1 sm_amiga_i_6__n vma_int_0_un3_n sm_amiga_i_7__n \ -# vma_int_0_un1_n sm_amiga_i_5__n vma_int_0_un0_n sm_amiga_i_4__n lds_000_int_0_un3_n state_machine_un13_clk_000_d_1_i_n lds_000_int_0_un1_n CLK_000_DD_i lds_000_int_0_un0_n AS_030_000_SYNC_i \ -# uds_000_int_0_un3_n cpu_est_i_0__n uds_000_int_0_un1_n cpu_est_i_2__n uds_000_int_0_un0_n cpu_est_i_3__n cpu_est_0_3__un3_n cpu_est_i_1__n cpu_est_0_3__un1_n UDS_000_INT_0_sqmuxa_1_i \ -# cpu_est_0_3__un0_n UDS_000_INT_0_sqmuxa_i cpu_est_0_2__un3_n DS_030_i cpu_est_0_2__un1_n VPA_D_i cpu_est_0_2__un0_n state_machine_un42_clk_030_i_n cpu_est_0_1__un3_n VPA_SYNC_1_sqmuxa_i \ -# cpu_est_0_1__un1_n N_102_i cpu_est_0_1__un0_n DTACK_SYNC_1_sqmuxa_i fpu_cs_int_0_un3_n N_98_i fpu_cs_int_0_un1_n a_i_18__n fpu_cs_int_0_un0_n a_i_16__n \ -# as_000_int_0_un3_n a_i_19__n as_000_int_0_un1_n CLK_030_i as_000_int_0_un0_n VMA_INT_i vpa_sync_0_un3_n DTACK_i vpa_sync_0_un1_n sm_amiga_i_3__n \ -# vpa_sync_0_un0_n sm_amiga_i_1__n as_030_000_sync_0_un3_n sm_amiga_i_2__n as_030_000_sync_0_un1_n a_i_30__n as_030_000_sync_0_un0_n a_i_31__n ipl_030_0_2__un3_n a_i_28__n \ -# ipl_030_0_2__un1_n a_i_29__n ipl_030_0_2__un0_n a_i_26__n ipl_030_0_1__un3_n a_i_27__n ipl_030_0_1__un1_n a_i_24__n ipl_030_0_1__un0_n a_i_25__n \ -# ipl_030_0_0__un3_n ipl_030_0_0__un1_n ipl_030_0_0__un0_n RST_i bgack_030_int_0_un3_n FPU_CS_INT_i bgack_030_int_0_un1_n CPU_SPACE_i bgack_030_int_0_un0_n BGACK_030_INT_i \ -# dsack_int_0_1__un3_n AS_030_c dsack_int_0_1__un1_n dsack_int_0_1__un0_n bg_000_0_un3_n DS_030_c bg_000_0_un1_n bg_000_0_un0_n dtack_sync_0_un3_n dtack_sync_0_un1_n \ -# size_c_0__n dtack_sync_0_un0_n a_15__n size_c_1__n a_14__n a_c_0__n a_13__n a_12__n a_11__n a_10__n \ -# a_9__n a_8__n a_7__n a_6__n a_c_16__n a_5__n a_c_17__n a_4__n a_c_18__n a_3__n \ -# a_c_19__n a_2__n a_c_20__n a_1__n a_c_21__n a_c_22__n a_c_23__n a_c_24__n a_c_25__n a_c_26__n \ -# a_c_27__n a_c_28__n a_c_29__n a_c_30__n a_c_31__n CPU_SPACE_c BG_030_c BG_000DFFSHreg BGACK_000_c CLK_030_c \ -# CLK_000_c +#$ PINS 74 A_21_ A_20_ SIZE_1_ A_19_ A_18_ A_31_ A_17_ A_16_ IPL_030_2_ A_15_ A_14_ IPL_2_ A_13_ A_12_ DSACK_1_ A_11_ A_10_ FC_1_ A_9_ AS_030 A_8_ AS_000 A_7_ DS_030 A_6_ UDS_000 A_5_ LDS_000 A_4_ CPU_SPACE A_3_ BERR A_2_ BG_030 A_1_ BG_000 A_0_ BGACK_030 IPL_030_1_ BGACK_000 IPL_030_0_ CLK_030 IPL_1_ CLK_000 IPL_0_ CLK_OSZI DSACK_0_ CLK_DIV_OUT FC_0_ CLK_EXP FPU_CS DTACK AVEC AVEC_EXP E VPA VMA RST RESET RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ +#$ NODES 344 IPL_030DFFSH_1_reg IPL_030DFFSH_2_reg ipl_c_0__n ipl_c_1__n inst_BGACK_030_INTreg inst_FPU_CS_INTreg ipl_c_2__n cpu_est_3_reg inst_VMA_INTreg gnd_n_n \ +# dsack_c_1__n cpu_est_0_ cpu_est_1_ DTACK_c inst_AS_000_INTreg inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D \ +# inst_CLK_000_DD inst_CLK_OUT_PRE RST_c vcc_n_n cpu_est_2_ RESETDFFreg CLK_CNT_0_ SM_AMIGA_6_ RW_c SM_AMIGA_7_ \ +# inst_UDS_000_INTreg fc_c_0__n inst_LDS_000_INTreg state_machine_un1_clk_030_n fc_c_1__n SM_AMIGA_1_ DSACK_INT_1_ inst_DTACK_DMA SM_AMIGA_4_ state_machine_un6_bgack_000_n \ +# SM_AMIGA_3_ N_99_i state_machine_un13_as_000_int_n un1_bg_030 N_101_i SM_AMIGA_5_ sm_amiga_ns_0_2__n SM_AMIGA_2_ N_107_i SM_AMIGA_0_ \ +# N_106_i sm_amiga_ns_0_5__n N_108_i N_109_i N_110_i sm_amiga_ns_0_7__n N_91_0 CLK_OUT_PRE_i N_94_0 state_machine_un8_clk_000_d_i_n \ +# state_machine_un13_clk_000_d_i_n cpu_est_0_0_ state_machine_un15_clk_000_d_0_n N_93_0 N_104_i N_105_i N_103_i CLK_OUT_PRE_0 state_machine_un60_clk_000_d_i_n state_machine_un17_clk_030_0_n \ +# un1_as_030_3_0 N_145_i clk_un4_clk_000_dd_n a_c_i_0__n clk_cpu_est_11_1__n state_machine_uds_000_int_8_0_n state_machine_un42_clk_030_n state_machine_lds_000_int_8_0_n N_102 state_machine_as_030_000_sync_3_2_n \ +# N_98 size_c_i_1__n N_97 state_machine_un34_clk_000_d_i_n N_100 N_131_i N_92 N_132_i N_112 N_122_i \ +# N_127 N_125_i N_125 N_126_i N_128 N_134_i N_129 N_133_i N_130 N_135_i \ +# N_168 clk_cpu_est_11_0_3__n N_171 N_130_i N_135_1 clk_cpu_est_11_0_1__n state_machine_un13_clk_000_d_2_n N_128_i clk_cpu_est_11_3__n un1_bg_030_0 \ +# N_135 N_97_i N_133 BG_030_c_i N_134 N_127_i N_132 N_129_i N_131 N_92_0 \ +# N_126 N_100_i state_machine_un34_clk_000_d_n N_112_i UDS_000_INT_0_sqmuxa UDS_000_INT_0_sqmuxa_1 clk_un4_clk_000_dd_i_n state_machine_as_030_000_sync_3_n state_machine_un6_bgack_000_0_n N_145 \ +# state_machine_un1_clk_030_0_n state_machine_lds_000_int_8_n clk_cpu_est_11_0_1_3__n state_machine_uds_000_int_8_n state_machine_un34_clk_000_d_i_1_n un1_as_030_4 state_machine_as_030_000_sync_3_2_1_n un1_as_030_3 N_168_1 DSACK_INT_1_sqmuxa \ +# N_168_2 state_machine_un17_clk_030_n N_168_3 state_machine_un60_clk_000_d_n N_168_4 DTACK_SYNC_1_sqmuxa N_168_5 DTACK_SYNC_1_sqmuxa_1 N_168_6 VPA_SYNC_1_sqmuxa \ +# N_171_1 VPA_SYNC_1_sqmuxa_1 N_171_2 N_103 un1_bg_030_0_1 N_104 un1_bg_030_0_2 N_93 clk_cpu_est_11_0_1_1__n N_105 \ +# clk_cpu_est_11_0_2_1__n VPA_SYNC_1_sqmuxa_1_0 state_machine_un42_clk_030_1_n state_machine_un15_clk_000_d_n state_machine_un42_clk_030_2_n state_machine_un13_clk_000_d_n state_machine_un42_clk_030_3_n state_machine_un8_clk_000_d_n state_machine_un42_clk_030_4_n state_machine_un8_clk_000_d_1_n \ +# state_machine_un42_clk_030_5_n state_machine_un13_clk_000_d_1_n N_132_1 N_107 N_131_1 N_94 UDS_000_INT_0_sqmuxa_1_0 N_91 UDS_000_INT_0_sqmuxa_2 N_110 \ +# UDS_000_INT_0_sqmuxa_1_1 N_108 UDS_000_INT_0_sqmuxa_1_2 N_109 UDS_000_INT_0_sqmuxa_1_3 N_106 DTACK_SYNC_1_sqmuxa_1_0 N_101 state_machine_un8_clk_000_d_1_0_n N_99 \ +# state_machine_un8_clk_000_d_2_n AS_000_INT_1_sqmuxa state_machine_un8_clk_000_d_3_n RW_i state_machine_un13_clk_000_d_1_0_n N_102_i state_machine_un13_clk_000_d_2_0_n AS_000_INT_i VPA_SYNC_1_sqmuxa_1_1 dsack_i_1__n \ +# VPA_SYNC_1_sqmuxa_2 AS_030_i VPA_SYNC_1_sqmuxa_3 sm_amiga_i_7__n VPA_SYNC_1_sqmuxa_4 CLK_000_D_i N_107_1 sm_amiga_i_2__n N_98_1 sm_amiga_i_1__n \ +# as_000_int_0_un3_n state_machine_un13_clk_000_d_1_i_n as_000_int_0_un1_n VPA_D_i as_000_int_0_un0_n VMA_INT_i vma_int_0_un3_n cpu_est_i_0__n vma_int_0_un1_n cpu_est_i_1__n \ +# vma_int_0_un0_n cpu_est_i_3__n uds_000_int_0_un3_n state_machine_un8_clk_000_d_1_i_0_n uds_000_int_0_un1_n DTACK_i uds_000_int_0_un0_n sm_amiga_i_3__n dtack_sync_0_un3_n sm_amiga_i_4__n \ +# dtack_sync_0_un1_n sm_amiga_i_5__n dtack_sync_0_un0_n DTACK_SYNC_1_sqmuxa_i vpa_sync_0_un3_n VPA_SYNC_1_sqmuxa_i vpa_sync_0_un1_n N_98_i vpa_sync_0_un0_n state_machine_un42_clk_030_i_n \ +# dsack_int_0_1__un3_n UDS_000_INT_0_sqmuxa_1_i dsack_int_0_1__un1_n UDS_000_INT_0_sqmuxa_i dsack_int_0_1__un0_n AS_030_000_SYNC_i as_030_000_sync_0_un3_n DS_030_i as_030_000_sync_0_un1_n cpu_est_i_2__n \ +# as_030_000_sync_0_un0_n state_machine_un13_clk_000_d_2_i_n fpu_cs_int_0_un3_n CLK_000_DD_i fpu_cs_int_0_un1_n sm_amiga_i_6__n fpu_cs_int_0_un0_n CLK_030_i lds_000_int_0_un3_n a_i_30__n \ +# lds_000_int_0_un1_n a_i_31__n lds_000_int_0_un0_n a_i_28__n cpu_est_0_3__un3_n a_i_29__n cpu_est_0_3__un1_n a_i_26__n cpu_est_0_3__un0_n a_i_27__n \ +# cpu_est_0_2__un3_n a_i_24__n cpu_est_0_2__un1_n a_i_25__n cpu_est_0_2__un0_n a_i_19__n bg_000_0_un3_n a_i_16__n bg_000_0_un1_n a_i_18__n \ +# bg_000_0_un0_n bgack_030_int_0_un3_n RST_i bgack_030_int_0_un1_n bgack_030_int_0_un0_n FPU_CS_INT_i cpu_est_0_1__un3_n CPU_SPACE_i cpu_est_0_1__un1_n BGACK_030_INT_i \ +# cpu_est_0_1__un0_n AS_030_c ipl_030_0_0__un3_n ipl_030_0_0__un1_n ipl_030_0_0__un0_n DS_030_c ipl_030_0_1__un3_n ipl_030_0_1__un1_n ipl_030_0_1__un0_n ipl_030_0_2__un3_n \ +# size_c_0__n ipl_030_0_2__un1_n ipl_030_0_2__un0_n size_c_1__n a_15__n a_c_0__n a_14__n a_13__n a_12__n a_11__n \ +# a_10__n a_9__n a_8__n a_7__n a_6__n a_c_16__n a_5__n a_c_17__n a_4__n a_c_18__n \ +# a_3__n a_c_19__n a_2__n a_c_20__n a_1__n a_c_21__n a_c_22__n a_c_23__n a_c_24__n a_c_25__n \ +# a_c_26__n a_c_27__n a_c_28__n a_c_29__n a_c_30__n a_c_31__n CPU_SPACE_c BG_030_c BG_000DFFSHreg BGACK_000_c \ +# CLK_030_c CLK_OSZI_c CLK_OUT_INTreg IPL_030DFFSH_0_reg .model bus68030 .inputs SIZE_1_.BLIF A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF AS_030.BLIF DS_030.BLIF CPU_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF \ CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF VPA.BLIF RST.BLIF RW.BLIF SIZE_0_.BLIF A_30_.BLIF A_29_.BLIF \ A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF \ A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF A_15_.BLIF A_14_.BLIF A_13_.BLIF A_12_.BLIF A_11_.BLIF \ A_10_.BLIF A_9_.BLIF A_8_.BLIF A_7_.BLIF A_6_.BLIF A_5_.BLIF A_4_.BLIF A_3_.BLIF A_2_.BLIF \ - A_1_.BLIF A_0_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF DSACK_1_.BLIF DTACK.BLIF DSACK_0_.BLIF CLK_OSZI_c.BLIF CLK_OUT_INTreg.BLIF IPL_030DFFSH_0_reg.BLIF inst_BGACK_030_INTreg.BLIF \ - inst_FPU_CS_INTreg.BLIF IPL_030DFFSH_1_reg.BLIF cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF IPL_030DFFSH_2_reg.BLIF gnd_n_n.BLIF cpu_est_0_.BLIF ipl_c_0__n.BLIF cpu_est_1_.BLIF \ - cpu_est_d_0_.BLIF ipl_c_1__n.BLIF cpu_est_d_3_.BLIF inst_AS_000_INTreg.BLIF ipl_c_2__n.BLIF inst_AS_030_000_SYNC.BLIF inst_DTACK_SYNC.BLIF inst_VPA_D.BLIF dsack_c_1__n.BLIF \ - inst_VPA_SYNC.BLIF inst_CLK_000_D.BLIF DTACK_c.BLIF inst_CLK_000_DD.BLIF inst_CLK_OUT_PRE.BLIF vcc_n_n.BLIF cpu_est_d_1_.BLIF cpu_est_d_2_.BLIF cpu_est_2_.BLIF \ - CLK_CNT_0_.BLIF SM_AMIGA_6_.BLIF RST_c.BLIF SM_AMIGA_7_.BLIF inst_UDS_000_INTreg.BLIF RESETDFFreg.BLIF inst_LDS_000_INTreg.BLIF RW_c.BLIF inst_RISING_CLK_AMIGA.BLIF \ - state_machine_un57_clk_000_d_n.BLIF fc_c_0__n.BLIF SM_AMIGA_1_.BLIF DSACK_INT_1_.BLIF fc_c_1__n.BLIF inst_DTACK_DMA.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_3_.BLIF state_machine_un13_as_000_int_n.BLIF \ - SM_AMIGA_5_.BLIF SM_AMIGA_2_.BLIF N_145_i.BLIF SM_AMIGA_0_.BLIF a_c_i_0__n.BLIF state_machine_uds_000_int_8_0_n.BLIF state_machine_lds_000_int_8_0_n.BLIF N_99_i.BLIF N_112_i.BLIF \ - N_100_i.BLIF N_101_i.BLIF sm_amiga_ns_0_2__n.BLIF N_103_i.BLIF N_110_i.BLIF sm_amiga_ns_0_7__n.BLIF cpu_est_0_0_.BLIF N_91_0.BLIF N_92_0.BLIF \ - N_131_i.BLIF N_132_i.BLIF N_122_i.BLIF CLK_OUT_PRE_0.BLIF N_124_i.BLIF N_125_i.BLIF N_126_i.BLIF N_129_i.BLIF N_98.BLIF \ - N_127_i.BLIF N_97.BLIF N_128_i.BLIF N_104.BLIF N_130_i.BLIF N_93.BLIF clk_cpu_est_11_0_1__n.BLIF N_105.BLIF N_134_i.BLIF \ - N_106.BLIF N_133_i.BLIF N_108.BLIF N_135_i.BLIF N_94.BLIF clk_cpu_est_11_0_3__n.BLIF N_109.BLIF size_c_i_1__n.BLIF N_107.BLIF \ - state_machine_un31_clk_000_d_i_n.BLIF N_135_1.BLIF state_machine_as_030_000_sync_3_0_n.BLIF VPA_SYNC_1_sqmuxa_1_0.BLIF un1_as_030_2_0.BLIF N_167.BLIF state_machine_un17_clk_030_0_n.BLIF N_170.BLIF state_machine_un57_clk_000_d_0_n.BLIF \ - state_machine_un42_clk_030_n.BLIF RISING_CLK_AMIGA_i.BLIF DTACK_SYNC_1_sqmuxa.BLIF state_machine_un4_bgack_000_0_n.BLIF VPA_SYNC_1_sqmuxa.BLIF BG_030_c_i.BLIF un1_bg_030.BLIF state_machine_un1_clk_030_0_n.BLIF DTACK_SYNC_1_sqmuxa_1.BLIF \ - N_97_i.BLIF DSACK_INT_1_sqmuxa.BLIF un1_bg_030_0.BLIF state_machine_un1_clk_030_n.BLIF CLK_OUT_PRE_i.BLIF state_machine_un4_bgack_000_n.BLIF N_94_0.BLIF un1_as_030_2.BLIF N_93_0.BLIF \ - state_machine_un17_clk_030_n.BLIF N_108_i.BLIF N_102.BLIF N_109_i.BLIF AS_000_INT_1_sqmuxa.BLIF VPA_SYNC_1_sqmuxa_1.BLIF N_106_i.BLIF state_machine_as_030_000_sync_3_n.BLIF N_107_i.BLIF \ - clk_un3_clk_000_dd_n.BLIF sm_amiga_ns_0_5__n.BLIF state_machine_un31_clk_000_d_n.BLIF N_104_i.BLIF UDS_000_INT_0_sqmuxa.BLIF N_105_i.BLIF state_machine_un13_clk_000_d_n.BLIF state_machine_un13_clk_000_d_4_n.BLIF un1_bg_030_0_1.BLIF \ - state_machine_un13_clk_000_d_1_n.BLIF un1_bg_030_0_2.BLIF state_machine_un8_clk_000_d_n.BLIF state_machine_un31_clk_000_d_i_1_n.BLIF UDS_000_INT_0_sqmuxa_1.BLIF clk_cpu_est_11_0_1_3__n.BLIF N_132.BLIF clk_cpu_est_11_0_1_1__n.BLIF N_131.BLIF \ - clk_cpu_est_11_0_2_1__n.BLIF N_124.BLIF N_167_1.BLIF clk_cpu_est_11_3__n.BLIF N_167_2.BLIF N_135.BLIF N_167_3.BLIF N_133.BLIF N_167_4.BLIF \ - N_134.BLIF N_167_5.BLIF clk_cpu_est_11_1__n.BLIF N_167_6.BLIF N_130.BLIF N_170_1.BLIF N_128.BLIF N_170_2.BLIF N_145.BLIF \ - N_107_1.BLIF N_127.BLIF state_machine_un42_clk_030_1_n.BLIF N_129.BLIF state_machine_un42_clk_030_2_n.BLIF N_126.BLIF state_machine_un42_clk_030_3_n.BLIF N_125.BLIF state_machine_un42_clk_030_4_n.BLIF \ - N_92.BLIF state_machine_un42_clk_030_5_n.BLIF N_91.BLIF DTACK_SYNC_1_sqmuxa_1_0.BLIF N_110.BLIF VPA_SYNC_1_sqmuxa_1_1.BLIF N_103.BLIF VPA_SYNC_1_sqmuxa_2.BLIF N_101.BLIF \ - VPA_SYNC_1_sqmuxa_3.BLIF N_100.BLIF VPA_SYNC_1_sqmuxa_4.BLIF N_112.BLIF N_98_1.BLIF N_99.BLIF state_machine_as_030_000_sync_3_0_1_n.BLIF state_machine_lds_000_int_8_n.BLIF UDS_000_INT_0_sqmuxa_1_0.BLIF \ - state_machine_uds_000_int_8_n.BLIF UDS_000_INT_0_sqmuxa_2.BLIF un2_clk_030_1.BLIF state_machine_un13_clk_000_d_1_0_n.BLIF VMA_INT_1_sqmuxa.BLIF state_machine_un13_clk_000_d_4_1_n.BLIF RW_i.BLIF state_machine_un8_clk_000_d_1_n.BLIF cpu_est_d_i_3__n.BLIF \ - state_machine_un8_clk_000_d_2_n.BLIF cpu_est_d_i_0__n.BLIF state_machine_un8_clk_000_d_3_n.BLIF CLK_000_D_i.BLIF state_machine_un8_clk_000_d_4_n.BLIF AS_000_INT_i.BLIF UDS_000_INT_0_sqmuxa_1_1.BLIF dsack_i_1__n.BLIF UDS_000_INT_0_sqmuxa_1_2.BLIF \ - state_machine_un13_clk_000_d_i_n.BLIF UDS_000_INT_0_sqmuxa_1_3.BLIF state_machine_un8_clk_000_d_i_n.BLIF N_132_1.BLIF AS_030_i.BLIF N_131_1.BLIF sm_amiga_i_6__n.BLIF vma_int_0_un3_n.BLIF sm_amiga_i_7__n.BLIF \ - vma_int_0_un1_n.BLIF sm_amiga_i_5__n.BLIF vma_int_0_un0_n.BLIF sm_amiga_i_4__n.BLIF lds_000_int_0_un3_n.BLIF state_machine_un13_clk_000_d_1_i_n.BLIF lds_000_int_0_un1_n.BLIF CLK_000_DD_i.BLIF lds_000_int_0_un0_n.BLIF \ - AS_030_000_SYNC_i.BLIF uds_000_int_0_un3_n.BLIF cpu_est_i_0__n.BLIF uds_000_int_0_un1_n.BLIF cpu_est_i_2__n.BLIF uds_000_int_0_un0_n.BLIF cpu_est_i_3__n.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_i_1__n.BLIF \ - cpu_est_0_3__un1_n.BLIF UDS_000_INT_0_sqmuxa_1_i.BLIF cpu_est_0_3__un0_n.BLIF UDS_000_INT_0_sqmuxa_i.BLIF cpu_est_0_2__un3_n.BLIF DS_030_i.BLIF cpu_est_0_2__un1_n.BLIF VPA_D_i.BLIF cpu_est_0_2__un0_n.BLIF \ - state_machine_un42_clk_030_i_n.BLIF cpu_est_0_1__un3_n.BLIF VPA_SYNC_1_sqmuxa_i.BLIF cpu_est_0_1__un1_n.BLIF N_102_i.BLIF cpu_est_0_1__un0_n.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF fpu_cs_int_0_un3_n.BLIF N_98_i.BLIF \ - fpu_cs_int_0_un1_n.BLIF a_i_18__n.BLIF fpu_cs_int_0_un0_n.BLIF a_i_16__n.BLIF as_000_int_0_un3_n.BLIF a_i_19__n.BLIF as_000_int_0_un1_n.BLIF CLK_030_i.BLIF as_000_int_0_un0_n.BLIF \ - VMA_INT_i.BLIF vpa_sync_0_un3_n.BLIF DTACK_i.BLIF vpa_sync_0_un1_n.BLIF sm_amiga_i_3__n.BLIF vpa_sync_0_un0_n.BLIF sm_amiga_i_1__n.BLIF as_030_000_sync_0_un3_n.BLIF sm_amiga_i_2__n.BLIF \ - as_030_000_sync_0_un1_n.BLIF a_i_30__n.BLIF as_030_000_sync_0_un0_n.BLIF a_i_31__n.BLIF ipl_030_0_2__un3_n.BLIF a_i_28__n.BLIF ipl_030_0_2__un1_n.BLIF a_i_29__n.BLIF ipl_030_0_2__un0_n.BLIF \ - a_i_26__n.BLIF ipl_030_0_1__un3_n.BLIF a_i_27__n.BLIF ipl_030_0_1__un1_n.BLIF a_i_24__n.BLIF ipl_030_0_1__un0_n.BLIF a_i_25__n.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un1_n.BLIF \ - ipl_030_0_0__un0_n.BLIF RST_i.BLIF bgack_030_int_0_un3_n.BLIF FPU_CS_INT_i.BLIF bgack_030_int_0_un1_n.BLIF CPU_SPACE_i.BLIF bgack_030_int_0_un0_n.BLIF BGACK_030_INT_i.BLIF dsack_int_0_1__un3_n.BLIF \ - AS_030_c.BLIF dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF bg_000_0_un3_n.BLIF DS_030_c.BLIF bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF dtack_sync_0_un3_n.BLIF dtack_sync_0_un1_n.BLIF \ - size_c_0__n.BLIF dtack_sync_0_un0_n.BLIF a_15__n.BLIF size_c_1__n.BLIF a_14__n.BLIF a_c_0__n.BLIF a_13__n.BLIF a_12__n.BLIF a_11__n.BLIF \ + A_1_.BLIF A_0_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF DSACK_1_.BLIF DTACK.BLIF DSACK_0_.BLIF IPL_030DFFSH_1_reg.BLIF IPL_030DFFSH_2_reg.BLIF ipl_c_0__n.BLIF ipl_c_1__n.BLIF \ + inst_BGACK_030_INTreg.BLIF inst_FPU_CS_INTreg.BLIF ipl_c_2__n.BLIF cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF gnd_n_n.BLIF dsack_c_1__n.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \ + DTACK_c.BLIF inst_AS_000_INTreg.BLIF inst_AS_030_000_SYNC.BLIF inst_DTACK_SYNC.BLIF inst_VPA_D.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF inst_CLK_OUT_PRE.BLIF \ + RST_c.BLIF vcc_n_n.BLIF cpu_est_2_.BLIF RESETDFFreg.BLIF CLK_CNT_0_.BLIF SM_AMIGA_6_.BLIF RW_c.BLIF SM_AMIGA_7_.BLIF inst_UDS_000_INTreg.BLIF \ + fc_c_0__n.BLIF inst_LDS_000_INTreg.BLIF state_machine_un1_clk_030_n.BLIF fc_c_1__n.BLIF SM_AMIGA_1_.BLIF DSACK_INT_1_.BLIF inst_DTACK_DMA.BLIF SM_AMIGA_4_.BLIF state_machine_un6_bgack_000_n.BLIF \ + SM_AMIGA_3_.BLIF N_99_i.BLIF state_machine_un13_as_000_int_n.BLIF un1_bg_030.BLIF N_101_i.BLIF SM_AMIGA_5_.BLIF sm_amiga_ns_0_2__n.BLIF SM_AMIGA_2_.BLIF N_107_i.BLIF \ + SM_AMIGA_0_.BLIF N_106_i.BLIF sm_amiga_ns_0_5__n.BLIF N_108_i.BLIF N_109_i.BLIF N_110_i.BLIF sm_amiga_ns_0_7__n.BLIF N_91_0.BLIF CLK_OUT_PRE_i.BLIF \ + N_94_0.BLIF state_machine_un8_clk_000_d_i_n.BLIF state_machine_un13_clk_000_d_i_n.BLIF cpu_est_0_0_.BLIF state_machine_un15_clk_000_d_0_n.BLIF N_93_0.BLIF N_104_i.BLIF N_105_i.BLIF N_103_i.BLIF \ + CLK_OUT_PRE_0.BLIF state_machine_un60_clk_000_d_i_n.BLIF state_machine_un17_clk_030_0_n.BLIF un1_as_030_3_0.BLIF N_145_i.BLIF clk_un4_clk_000_dd_n.BLIF a_c_i_0__n.BLIF clk_cpu_est_11_1__n.BLIF state_machine_uds_000_int_8_0_n.BLIF \ + state_machine_un42_clk_030_n.BLIF state_machine_lds_000_int_8_0_n.BLIF N_102.BLIF state_machine_as_030_000_sync_3_2_n.BLIF N_98.BLIF size_c_i_1__n.BLIF N_97.BLIF state_machine_un34_clk_000_d_i_n.BLIF N_100.BLIF \ + N_131_i.BLIF N_92.BLIF N_132_i.BLIF N_112.BLIF N_122_i.BLIF N_127.BLIF N_125_i.BLIF N_125.BLIF N_126_i.BLIF \ + N_128.BLIF N_134_i.BLIF N_129.BLIF N_133_i.BLIF N_130.BLIF N_135_i.BLIF N_168.BLIF clk_cpu_est_11_0_3__n.BLIF N_171.BLIF \ + N_130_i.BLIF N_135_1.BLIF clk_cpu_est_11_0_1__n.BLIF state_machine_un13_clk_000_d_2_n.BLIF N_128_i.BLIF clk_cpu_est_11_3__n.BLIF un1_bg_030_0.BLIF N_135.BLIF N_97_i.BLIF \ + N_133.BLIF BG_030_c_i.BLIF N_134.BLIF N_127_i.BLIF N_132.BLIF N_129_i.BLIF N_131.BLIF N_92_0.BLIF N_126.BLIF \ + N_100_i.BLIF state_machine_un34_clk_000_d_n.BLIF N_112_i.BLIF UDS_000_INT_0_sqmuxa.BLIF UDS_000_INT_0_sqmuxa_1.BLIF clk_un4_clk_000_dd_i_n.BLIF state_machine_as_030_000_sync_3_n.BLIF state_machine_un6_bgack_000_0_n.BLIF N_145.BLIF \ + state_machine_un1_clk_030_0_n.BLIF state_machine_lds_000_int_8_n.BLIF clk_cpu_est_11_0_1_3__n.BLIF state_machine_uds_000_int_8_n.BLIF state_machine_un34_clk_000_d_i_1_n.BLIF un1_as_030_4.BLIF state_machine_as_030_000_sync_3_2_1_n.BLIF un1_as_030_3.BLIF N_168_1.BLIF \ + DSACK_INT_1_sqmuxa.BLIF N_168_2.BLIF state_machine_un17_clk_030_n.BLIF N_168_3.BLIF state_machine_un60_clk_000_d_n.BLIF N_168_4.BLIF DTACK_SYNC_1_sqmuxa.BLIF N_168_5.BLIF DTACK_SYNC_1_sqmuxa_1.BLIF \ + N_168_6.BLIF VPA_SYNC_1_sqmuxa.BLIF N_171_1.BLIF VPA_SYNC_1_sqmuxa_1.BLIF N_171_2.BLIF N_103.BLIF un1_bg_030_0_1.BLIF N_104.BLIF un1_bg_030_0_2.BLIF \ + N_93.BLIF clk_cpu_est_11_0_1_1__n.BLIF N_105.BLIF clk_cpu_est_11_0_2_1__n.BLIF VPA_SYNC_1_sqmuxa_1_0.BLIF state_machine_un42_clk_030_1_n.BLIF state_machine_un15_clk_000_d_n.BLIF state_machine_un42_clk_030_2_n.BLIF state_machine_un13_clk_000_d_n.BLIF \ + state_machine_un42_clk_030_3_n.BLIF state_machine_un8_clk_000_d_n.BLIF state_machine_un42_clk_030_4_n.BLIF state_machine_un8_clk_000_d_1_n.BLIF state_machine_un42_clk_030_5_n.BLIF state_machine_un13_clk_000_d_1_n.BLIF N_132_1.BLIF N_107.BLIF N_131_1.BLIF \ + N_94.BLIF UDS_000_INT_0_sqmuxa_1_0.BLIF N_91.BLIF UDS_000_INT_0_sqmuxa_2.BLIF N_110.BLIF UDS_000_INT_0_sqmuxa_1_1.BLIF N_108.BLIF UDS_000_INT_0_sqmuxa_1_2.BLIF N_109.BLIF \ + UDS_000_INT_0_sqmuxa_1_3.BLIF N_106.BLIF DTACK_SYNC_1_sqmuxa_1_0.BLIF N_101.BLIF state_machine_un8_clk_000_d_1_0_n.BLIF N_99.BLIF state_machine_un8_clk_000_d_2_n.BLIF AS_000_INT_1_sqmuxa.BLIF state_machine_un8_clk_000_d_3_n.BLIF \ + RW_i.BLIF state_machine_un13_clk_000_d_1_0_n.BLIF N_102_i.BLIF state_machine_un13_clk_000_d_2_0_n.BLIF AS_000_INT_i.BLIF VPA_SYNC_1_sqmuxa_1_1.BLIF dsack_i_1__n.BLIF VPA_SYNC_1_sqmuxa_2.BLIF AS_030_i.BLIF \ + VPA_SYNC_1_sqmuxa_3.BLIF sm_amiga_i_7__n.BLIF VPA_SYNC_1_sqmuxa_4.BLIF CLK_000_D_i.BLIF N_107_1.BLIF sm_amiga_i_2__n.BLIF N_98_1.BLIF sm_amiga_i_1__n.BLIF as_000_int_0_un3_n.BLIF \ + state_machine_un13_clk_000_d_1_i_n.BLIF as_000_int_0_un1_n.BLIF VPA_D_i.BLIF as_000_int_0_un0_n.BLIF VMA_INT_i.BLIF vma_int_0_un3_n.BLIF cpu_est_i_0__n.BLIF vma_int_0_un1_n.BLIF cpu_est_i_1__n.BLIF \ + vma_int_0_un0_n.BLIF cpu_est_i_3__n.BLIF uds_000_int_0_un3_n.BLIF state_machine_un8_clk_000_d_1_i_0_n.BLIF uds_000_int_0_un1_n.BLIF DTACK_i.BLIF uds_000_int_0_un0_n.BLIF sm_amiga_i_3__n.BLIF dtack_sync_0_un3_n.BLIF \ + sm_amiga_i_4__n.BLIF dtack_sync_0_un1_n.BLIF sm_amiga_i_5__n.BLIF dtack_sync_0_un0_n.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF vpa_sync_0_un3_n.BLIF VPA_SYNC_1_sqmuxa_i.BLIF vpa_sync_0_un1_n.BLIF N_98_i.BLIF \ + vpa_sync_0_un0_n.BLIF state_machine_un42_clk_030_i_n.BLIF dsack_int_0_1__un3_n.BLIF UDS_000_INT_0_sqmuxa_1_i.BLIF dsack_int_0_1__un1_n.BLIF UDS_000_INT_0_sqmuxa_i.BLIF dsack_int_0_1__un0_n.BLIF AS_030_000_SYNC_i.BLIF as_030_000_sync_0_un3_n.BLIF \ + DS_030_i.BLIF as_030_000_sync_0_un1_n.BLIF cpu_est_i_2__n.BLIF as_030_000_sync_0_un0_n.BLIF state_machine_un13_clk_000_d_2_i_n.BLIF fpu_cs_int_0_un3_n.BLIF CLK_000_DD_i.BLIF fpu_cs_int_0_un1_n.BLIF sm_amiga_i_6__n.BLIF \ + fpu_cs_int_0_un0_n.BLIF CLK_030_i.BLIF lds_000_int_0_un3_n.BLIF a_i_30__n.BLIF lds_000_int_0_un1_n.BLIF a_i_31__n.BLIF lds_000_int_0_un0_n.BLIF a_i_28__n.BLIF cpu_est_0_3__un3_n.BLIF \ + a_i_29__n.BLIF cpu_est_0_3__un1_n.BLIF a_i_26__n.BLIF cpu_est_0_3__un0_n.BLIF a_i_27__n.BLIF cpu_est_0_2__un3_n.BLIF a_i_24__n.BLIF cpu_est_0_2__un1_n.BLIF a_i_25__n.BLIF \ + cpu_est_0_2__un0_n.BLIF a_i_19__n.BLIF bg_000_0_un3_n.BLIF a_i_16__n.BLIF bg_000_0_un1_n.BLIF a_i_18__n.BLIF bg_000_0_un0_n.BLIF bgack_030_int_0_un3_n.BLIF RST_i.BLIF \ + bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF FPU_CS_INT_i.BLIF cpu_est_0_1__un3_n.BLIF CPU_SPACE_i.BLIF cpu_est_0_1__un1_n.BLIF BGACK_030_INT_i.BLIF cpu_est_0_1__un0_n.BLIF AS_030_c.BLIF \ + ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF DS_030_c.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF ipl_030_0_2__un3_n.BLIF size_c_0__n.BLIF \ + ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF size_c_1__n.BLIF a_15__n.BLIF a_c_0__n.BLIF a_14__n.BLIF a_13__n.BLIF a_12__n.BLIF a_11__n.BLIF \ a_10__n.BLIF a_9__n.BLIF a_8__n.BLIF a_7__n.BLIF a_6__n.BLIF a_c_16__n.BLIF a_5__n.BLIF a_c_17__n.BLIF a_4__n.BLIF \ a_c_18__n.BLIF a_3__n.BLIF a_c_19__n.BLIF a_2__n.BLIF a_c_20__n.BLIF a_1__n.BLIF a_c_21__n.BLIF a_c_22__n.BLIF a_c_23__n.BLIF \ a_c_24__n.BLIF a_c_25__n.BLIF a_c_26__n.BLIF a_c_27__n.BLIF a_c_28__n.BLIF a_c_29__n.BLIF a_c_30__n.BLIF a_c_31__n.BLIF CPU_SPACE_c.BLIF \ - BG_030_c.BLIF BG_000DFFSHreg.BLIF BGACK_000_c.BLIF CLK_030_c.BLIF CLK_000_c.BLIF DSACK_1_.PIN DTACK.PIN + BG_030_c.BLIF BG_000DFFSHreg.BLIF BGACK_000_c.BLIF CLK_030_c.BLIF CLK_OSZI_c.BLIF CLK_OUT_INTreg.BLIF IPL_030DFFSH_0_reg.BLIF DSACK_1_.PIN DTACK.PIN .outputs IPL_030_2_ AS_000 UDS_000 LDS_000 BERR BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS AVEC \ - AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ cpu_est_3_reg.D \ - cpu_est_3_reg.C SM_AMIGA_7_.D SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D \ - SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR \ - SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR cpu_est_d_0_.D cpu_est_d_0_.C cpu_est_d_1_.D cpu_est_d_1_.C cpu_est_d_2_.D cpu_est_d_2_.C cpu_est_d_3_.D cpu_est_d_3_.C \ - IPL_030DFFSH_0_reg.D IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP IPL_030DFFSH_1_reg.D IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP cpu_est_0_.D cpu_est_0_.C \ - cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C inst_VPA_SYNC.D inst_VPA_SYNC.C inst_VPA_SYNC.AP inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_VMA_INTreg.D \ - inst_VMA_INTreg.C inst_VMA_INTreg.AP BG_000DFFSHreg.D BG_000DFFSHreg.C BG_000DFFSHreg.AP DSACK_INT_1_.D DSACK_INT_1_.C DSACK_INT_1_.AP inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP \ - inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C inst_UDS_000_INTreg.D inst_UDS_000_INTreg.C inst_UDS_000_INTreg.AP inst_LDS_000_INTreg.D inst_LDS_000_INTreg.C inst_LDS_000_INTreg.AP inst_DTACK_SYNC.D inst_DTACK_SYNC.C inst_DTACK_SYNC.AP \ - inst_FPU_CS_INTreg.D inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP inst_AS_000_INTreg.D inst_AS_000_INTreg.C inst_AS_000_INTreg.AP inst_DTACK_DMA.D inst_DTACK_DMA.C inst_DTACK_DMA.AP inst_RISING_CLK_AMIGA.D inst_RISING_CLK_AMIGA.C \ - CLK_CNT_0_.D CLK_CNT_0_.C inst_VPA_D.D inst_VPA_D.C inst_CLK_000_D.D inst_CLK_000_D.C RESETDFFreg.D RESETDFFreg.C inst_CLK_000_DD.D inst_CLK_000_DD.C CLK_OUT_INTreg.D \ - CLK_OUT_INTreg.C cpu_est_0_0_.X1 cpu_est_0_0_.X2 CLK_OUT_PRE_0.X1 CLK_OUT_PRE_0.X2 DSACK_1_ DTACK DSACK_0_ CLK_OSZI_c gnd_n_n ipl_c_0__n ipl_c_1__n ipl_c_2__n dsack_c_1__n \ - DTACK_c vcc_n_n RST_c RW_c state_machine_un57_clk_000_d_n fc_c_0__n fc_c_1__n state_machine_un13_as_000_int_n N_145_i a_c_i_0__n state_machine_uds_000_int_8_0_n \ - state_machine_lds_000_int_8_0_n N_99_i N_112_i N_100_i N_101_i sm_amiga_ns_0_2__n N_103_i N_110_i sm_amiga_ns_0_7__n N_91_0 N_92_0 \ - N_131_i N_132_i N_122_i N_124_i N_125_i N_126_i N_129_i N_98 N_127_i N_97 N_128_i \ - N_104 N_130_i N_93 clk_cpu_est_11_0_1__n N_105 N_134_i N_106 N_133_i N_108 N_135_i N_94 \ - clk_cpu_est_11_0_3__n N_109 size_c_i_1__n N_107 state_machine_un31_clk_000_d_i_n N_135_1 state_machine_as_030_000_sync_3_0_n VPA_SYNC_1_sqmuxa_1_0 un1_as_030_2_0 N_167 state_machine_un17_clk_030_0_n \ - N_170 state_machine_un57_clk_000_d_0_n state_machine_un42_clk_030_n RISING_CLK_AMIGA_i DTACK_SYNC_1_sqmuxa state_machine_un4_bgack_000_0_n VPA_SYNC_1_sqmuxa BG_030_c_i un1_bg_030 state_machine_un1_clk_030_0_n DTACK_SYNC_1_sqmuxa_1 \ - N_97_i DSACK_INT_1_sqmuxa un1_bg_030_0 state_machine_un1_clk_030_n CLK_OUT_PRE_i state_machine_un4_bgack_000_n N_94_0 un1_as_030_2 N_93_0 state_machine_un17_clk_030_n N_108_i \ - N_102 N_109_i AS_000_INT_1_sqmuxa VPA_SYNC_1_sqmuxa_1 N_106_i state_machine_as_030_000_sync_3_n N_107_i clk_un3_clk_000_dd_n sm_amiga_ns_0_5__n state_machine_un31_clk_000_d_n N_104_i \ - UDS_000_INT_0_sqmuxa N_105_i state_machine_un13_clk_000_d_n state_machine_un13_clk_000_d_4_n un1_bg_030_0_1 state_machine_un13_clk_000_d_1_n un1_bg_030_0_2 state_machine_un8_clk_000_d_n state_machine_un31_clk_000_d_i_1_n UDS_000_INT_0_sqmuxa_1 clk_cpu_est_11_0_1_3__n \ - N_132 clk_cpu_est_11_0_1_1__n N_131 clk_cpu_est_11_0_2_1__n N_124 N_167_1 clk_cpu_est_11_3__n N_167_2 N_135 N_167_3 N_133 \ - N_167_4 N_134 N_167_5 clk_cpu_est_11_1__n N_167_6 N_130 N_170_1 N_128 N_170_2 N_145 N_107_1 \ - N_127 state_machine_un42_clk_030_1_n N_129 state_machine_un42_clk_030_2_n N_126 state_machine_un42_clk_030_3_n N_125 state_machine_un42_clk_030_4_n N_92 state_machine_un42_clk_030_5_n N_91 \ - DTACK_SYNC_1_sqmuxa_1_0 N_110 VPA_SYNC_1_sqmuxa_1_1 N_103 VPA_SYNC_1_sqmuxa_2 N_101 VPA_SYNC_1_sqmuxa_3 N_100 VPA_SYNC_1_sqmuxa_4 N_112 N_98_1 \ - N_99 state_machine_as_030_000_sync_3_0_1_n state_machine_lds_000_int_8_n UDS_000_INT_0_sqmuxa_1_0 state_machine_uds_000_int_8_n UDS_000_INT_0_sqmuxa_2 un2_clk_030_1 state_machine_un13_clk_000_d_1_0_n VMA_INT_1_sqmuxa state_machine_un13_clk_000_d_4_1_n RW_i \ - state_machine_un8_clk_000_d_1_n cpu_est_d_i_3__n state_machine_un8_clk_000_d_2_n cpu_est_d_i_0__n state_machine_un8_clk_000_d_3_n CLK_000_D_i state_machine_un8_clk_000_d_4_n AS_000_INT_i UDS_000_INT_0_sqmuxa_1_1 dsack_i_1__n UDS_000_INT_0_sqmuxa_1_2 \ - state_machine_un13_clk_000_d_i_n UDS_000_INT_0_sqmuxa_1_3 state_machine_un8_clk_000_d_i_n N_132_1 AS_030_i N_131_1 sm_amiga_i_6__n vma_int_0_un3_n sm_amiga_i_7__n vma_int_0_un1_n sm_amiga_i_5__n \ - vma_int_0_un0_n sm_amiga_i_4__n lds_000_int_0_un3_n state_machine_un13_clk_000_d_1_i_n lds_000_int_0_un1_n CLK_000_DD_i lds_000_int_0_un0_n AS_030_000_SYNC_i uds_000_int_0_un3_n cpu_est_i_0__n uds_000_int_0_un1_n \ - cpu_est_i_2__n uds_000_int_0_un0_n cpu_est_i_3__n cpu_est_0_3__un3_n cpu_est_i_1__n cpu_est_0_3__un1_n UDS_000_INT_0_sqmuxa_1_i cpu_est_0_3__un0_n UDS_000_INT_0_sqmuxa_i cpu_est_0_2__un3_n DS_030_i \ - cpu_est_0_2__un1_n VPA_D_i cpu_est_0_2__un0_n state_machine_un42_clk_030_i_n cpu_est_0_1__un3_n VPA_SYNC_1_sqmuxa_i cpu_est_0_1__un1_n N_102_i cpu_est_0_1__un0_n DTACK_SYNC_1_sqmuxa_i fpu_cs_int_0_un3_n \ - N_98_i fpu_cs_int_0_un1_n a_i_18__n fpu_cs_int_0_un0_n a_i_16__n as_000_int_0_un3_n a_i_19__n as_000_int_0_un1_n CLK_030_i as_000_int_0_un0_n VMA_INT_i \ - vpa_sync_0_un3_n DTACK_i vpa_sync_0_un1_n sm_amiga_i_3__n vpa_sync_0_un0_n sm_amiga_i_1__n as_030_000_sync_0_un3_n sm_amiga_i_2__n as_030_000_sync_0_un1_n a_i_30__n as_030_000_sync_0_un0_n \ - a_i_31__n ipl_030_0_2__un3_n a_i_28__n ipl_030_0_2__un1_n a_i_29__n ipl_030_0_2__un0_n a_i_26__n ipl_030_0_1__un3_n a_i_27__n ipl_030_0_1__un1_n a_i_24__n \ - ipl_030_0_1__un0_n a_i_25__n ipl_030_0_0__un3_n ipl_030_0_0__un1_n ipl_030_0_0__un0_n RST_i bgack_030_int_0_un3_n FPU_CS_INT_i bgack_030_int_0_un1_n CPU_SPACE_i bgack_030_int_0_un0_n \ - BGACK_030_INT_i dsack_int_0_1__un3_n AS_030_c dsack_int_0_1__un1_n dsack_int_0_1__un0_n bg_000_0_un3_n DS_030_c bg_000_0_un1_n bg_000_0_un0_n dtack_sync_0_un3_n dtack_sync_0_un1_n \ - size_c_0__n dtack_sync_0_un0_n a_15__n size_c_1__n a_14__n a_c_0__n a_13__n a_12__n a_11__n a_10__n a_9__n \ - a_8__n a_7__n a_6__n a_c_16__n a_5__n a_c_17__n a_4__n a_c_18__n a_3__n a_c_19__n a_2__n \ - a_c_20__n a_1__n a_c_21__n a_c_22__n a_c_23__n a_c_24__n a_c_25__n a_c_26__n a_c_27__n a_c_28__n a_c_29__n \ - a_c_30__n a_c_31__n CPU_SPACE_c BG_030_c BGACK_000_c CLK_030_c CLK_000_c DSACK_1_.OE DTACK.OE \ - AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE + AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_3_.D \ + SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR \ + IPL_030DFFSH_0_reg.D IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP IPL_030DFFSH_1_reg.D IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D SM_AMIGA_7_.C \ + SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_4_.AR DSACK_INT_1_.D \ + DSACK_INT_1_.C DSACK_INT_1_.AP inst_VMA_INTreg.D inst_VMA_INTreg.C inst_VMA_INTreg.AP inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C cpu_est_0_.D \ + cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_reg.D cpu_est_3_reg.C inst_LDS_000_INTreg.D inst_LDS_000_INTreg.C inst_LDS_000_INTreg.AP inst_DTACK_SYNC.D \ + inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_FPU_CS_INTreg.D inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_AS_000_INTreg.D inst_AS_000_INTreg.C inst_AS_000_INTreg.AP \ + inst_VPA_SYNC.D inst_VPA_SYNC.C inst_VPA_SYNC.AP BG_000DFFSHreg.D BG_000DFFSHreg.C BG_000DFFSHreg.AP inst_DTACK_DMA.D inst_DTACK_DMA.C inst_DTACK_DMA.AP inst_UDS_000_INTreg.D inst_UDS_000_INTreg.C \ + inst_UDS_000_INTreg.AP CLK_CNT_0_.D CLK_CNT_0_.C inst_VPA_D.D inst_VPA_D.C inst_CLK_000_D.D inst_CLK_000_D.C RESETDFFreg.D RESETDFFreg.C inst_CLK_000_DD.D inst_CLK_000_DD.C \ + CLK_OUT_INTreg.D CLK_OUT_INTreg.C CLK_OUT_PRE_0.X1 CLK_OUT_PRE_0.X2 cpu_est_0_0_.X1 cpu_est_0_0_.X2 DSACK_1_ DTACK DSACK_0_ ipl_c_0__n ipl_c_1__n ipl_c_2__n gnd_n_n dsack_c_1__n \ + DTACK_c RST_c vcc_n_n RW_c fc_c_0__n state_machine_un1_clk_030_n fc_c_1__n state_machine_un6_bgack_000_n N_99_i state_machine_un13_as_000_int_n un1_bg_030 \ + N_101_i sm_amiga_ns_0_2__n N_107_i N_106_i sm_amiga_ns_0_5__n N_108_i N_109_i N_110_i sm_amiga_ns_0_7__n N_91_0 CLK_OUT_PRE_i \ + N_94_0 state_machine_un8_clk_000_d_i_n state_machine_un13_clk_000_d_i_n state_machine_un15_clk_000_d_0_n N_93_0 N_104_i N_105_i N_103_i state_machine_un60_clk_000_d_i_n state_machine_un17_clk_030_0_n un1_as_030_3_0 \ + N_145_i clk_un4_clk_000_dd_n a_c_i_0__n clk_cpu_est_11_1__n state_machine_uds_000_int_8_0_n state_machine_un42_clk_030_n state_machine_lds_000_int_8_0_n N_102 state_machine_as_030_000_sync_3_2_n N_98 size_c_i_1__n \ + N_97 state_machine_un34_clk_000_d_i_n N_100 N_131_i N_92 N_132_i N_112 N_122_i N_127 N_125_i N_125 \ + N_126_i N_128 N_134_i N_129 N_133_i N_130 N_135_i N_168 clk_cpu_est_11_0_3__n N_171 N_130_i \ + N_135_1 clk_cpu_est_11_0_1__n state_machine_un13_clk_000_d_2_n N_128_i clk_cpu_est_11_3__n un1_bg_030_0 N_135 N_97_i N_133 BG_030_c_i N_134 \ + N_127_i N_132 N_129_i N_131 N_92_0 N_126 N_100_i state_machine_un34_clk_000_d_n N_112_i UDS_000_INT_0_sqmuxa UDS_000_INT_0_sqmuxa_1 \ + clk_un4_clk_000_dd_i_n state_machine_as_030_000_sync_3_n state_machine_un6_bgack_000_0_n N_145 state_machine_un1_clk_030_0_n state_machine_lds_000_int_8_n clk_cpu_est_11_0_1_3__n state_machine_uds_000_int_8_n state_machine_un34_clk_000_d_i_1_n un1_as_030_4 state_machine_as_030_000_sync_3_2_1_n \ + un1_as_030_3 N_168_1 DSACK_INT_1_sqmuxa N_168_2 state_machine_un17_clk_030_n N_168_3 state_machine_un60_clk_000_d_n N_168_4 DTACK_SYNC_1_sqmuxa N_168_5 DTACK_SYNC_1_sqmuxa_1 \ + N_168_6 VPA_SYNC_1_sqmuxa N_171_1 VPA_SYNC_1_sqmuxa_1 N_171_2 N_103 un1_bg_030_0_1 N_104 un1_bg_030_0_2 N_93 clk_cpu_est_11_0_1_1__n \ + N_105 clk_cpu_est_11_0_2_1__n VPA_SYNC_1_sqmuxa_1_0 state_machine_un42_clk_030_1_n state_machine_un15_clk_000_d_n state_machine_un42_clk_030_2_n state_machine_un13_clk_000_d_n state_machine_un42_clk_030_3_n state_machine_un8_clk_000_d_n state_machine_un42_clk_030_4_n state_machine_un8_clk_000_d_1_n \ + state_machine_un42_clk_030_5_n state_machine_un13_clk_000_d_1_n N_132_1 N_107 N_131_1 N_94 UDS_000_INT_0_sqmuxa_1_0 N_91 UDS_000_INT_0_sqmuxa_2 N_110 UDS_000_INT_0_sqmuxa_1_1 \ + N_108 UDS_000_INT_0_sqmuxa_1_2 N_109 UDS_000_INT_0_sqmuxa_1_3 N_106 DTACK_SYNC_1_sqmuxa_1_0 N_101 state_machine_un8_clk_000_d_1_0_n N_99 state_machine_un8_clk_000_d_2_n AS_000_INT_1_sqmuxa \ + state_machine_un8_clk_000_d_3_n RW_i state_machine_un13_clk_000_d_1_0_n N_102_i state_machine_un13_clk_000_d_2_0_n AS_000_INT_i VPA_SYNC_1_sqmuxa_1_1 dsack_i_1__n VPA_SYNC_1_sqmuxa_2 AS_030_i VPA_SYNC_1_sqmuxa_3 \ + sm_amiga_i_7__n VPA_SYNC_1_sqmuxa_4 CLK_000_D_i N_107_1 sm_amiga_i_2__n N_98_1 sm_amiga_i_1__n as_000_int_0_un3_n state_machine_un13_clk_000_d_1_i_n as_000_int_0_un1_n VPA_D_i \ + as_000_int_0_un0_n VMA_INT_i vma_int_0_un3_n cpu_est_i_0__n vma_int_0_un1_n cpu_est_i_1__n vma_int_0_un0_n cpu_est_i_3__n uds_000_int_0_un3_n state_machine_un8_clk_000_d_1_i_0_n uds_000_int_0_un1_n \ + DTACK_i uds_000_int_0_un0_n sm_amiga_i_3__n dtack_sync_0_un3_n sm_amiga_i_4__n dtack_sync_0_un1_n sm_amiga_i_5__n dtack_sync_0_un0_n DTACK_SYNC_1_sqmuxa_i vpa_sync_0_un3_n VPA_SYNC_1_sqmuxa_i \ + vpa_sync_0_un1_n N_98_i vpa_sync_0_un0_n state_machine_un42_clk_030_i_n dsack_int_0_1__un3_n UDS_000_INT_0_sqmuxa_1_i dsack_int_0_1__un1_n UDS_000_INT_0_sqmuxa_i dsack_int_0_1__un0_n AS_030_000_SYNC_i as_030_000_sync_0_un3_n \ + DS_030_i as_030_000_sync_0_un1_n cpu_est_i_2__n as_030_000_sync_0_un0_n state_machine_un13_clk_000_d_2_i_n fpu_cs_int_0_un3_n CLK_000_DD_i fpu_cs_int_0_un1_n sm_amiga_i_6__n fpu_cs_int_0_un0_n CLK_030_i \ + lds_000_int_0_un3_n a_i_30__n lds_000_int_0_un1_n a_i_31__n lds_000_int_0_un0_n a_i_28__n cpu_est_0_3__un3_n a_i_29__n cpu_est_0_3__un1_n a_i_26__n cpu_est_0_3__un0_n \ + a_i_27__n cpu_est_0_2__un3_n a_i_24__n cpu_est_0_2__un1_n a_i_25__n cpu_est_0_2__un0_n a_i_19__n bg_000_0_un3_n a_i_16__n bg_000_0_un1_n a_i_18__n \ + bg_000_0_un0_n bgack_030_int_0_un3_n RST_i bgack_030_int_0_un1_n bgack_030_int_0_un0_n FPU_CS_INT_i cpu_est_0_1__un3_n CPU_SPACE_i cpu_est_0_1__un1_n BGACK_030_INT_i cpu_est_0_1__un0_n \ + AS_030_c ipl_030_0_0__un3_n ipl_030_0_0__un1_n ipl_030_0_0__un0_n DS_030_c ipl_030_0_1__un3_n ipl_030_0_1__un1_n ipl_030_0_1__un0_n ipl_030_0_2__un3_n size_c_0__n ipl_030_0_2__un1_n \ + ipl_030_0_2__un0_n size_c_1__n a_15__n a_c_0__n a_14__n a_13__n a_12__n a_11__n a_10__n a_9__n a_8__n \ + a_7__n a_6__n a_c_16__n a_5__n a_c_17__n a_4__n a_c_18__n a_3__n a_c_19__n a_2__n a_c_20__n \ + a_1__n a_c_21__n a_c_22__n a_c_23__n a_c_24__n a_c_25__n a_c_26__n a_c_27__n a_c_28__n a_c_29__n a_c_30__n \ + a_c_31__n CPU_SPACE_c BG_030_c BGACK_000_c CLK_030_c CLK_OSZI_c DSACK_1_.OE DTACK.OE AS_000.OE \ + UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE .names DSACK_INT_1_.BLIF DSACK_1_ 1 1 .names DSACK_1_.PIN dsack_c_1__n @@ -161,880 +158,856 @@ 1 1 .names FPU_CS_INT_i.BLIF AVEC_EXP.OE 1 1 -.names N_170.BLIF CIIN +.names N_171.BLIF CIIN 1 1 -.names N_167.BLIF CIIN.OE +.names N_168.BLIF CIIN.OE 1 1 -.names state_machine_lds_000_int_8_n.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n +.names inst_AS_000_INTreg.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n 11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C -1 1 -.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF inst_LDS_000_INTreg.D -1- 1 --1 1 -.names un2_clk_030_1.BLIF uds_000_int_0_un3_n -0 1 -.names RST_i.BLIF SM_AMIGA_3_.AR -1 1 -.names inst_UDS_000_INTreg.BLIF un2_clk_030_1.BLIF uds_000_int_0_un1_n +.names N_102_i.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n 11 1 -.names state_machine_uds_000_int_8_n.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n -11 1 -.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INTreg.D +.names CLK_OSZI_c.BLIF IPL_030DFFSH_2_reg.C +1 1 +.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF inst_AS_000_INTreg.D 1- 1 -1 1 .names RW_c.BLIF RW_i 0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C +.names RST_i.BLIF IPL_030DFFSH_2_reg.AP 1 1 -.names AS_030_c.BLIF AS_030_i -0 1 -.names AS_030_i.BLIF N_145.BLIF un2_clk_030_1 +.names inst_AS_000_INTreg.BLIF inst_CLK_000_D.BLIF state_machine_un13_clk_000_d_1_n 11 1 -.names RST_i.BLIF SM_AMIGA_2_.AR +.names CLK_OUT_PRE_i.BLIF sm_amiga_i_2__n.BLIF N_94_0 +11 1 +.names inst_AS_000_INTreg.BLIF SM_AMIGA_0_.BLIF N_91_0 +11 1 +.names N_98_i.BLIF N_110_i.BLIF sm_amiga_ns_0_7__n +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_7_.C 1 1 -.names state_machine_un13_clk_000_d_n.BLIF state_machine_un13_clk_000_d_i_n -0 1 -.names state_machine_un8_clk_000_d_n.BLIF state_machine_un8_clk_000_d_i_n -0 1 -.names state_machine_un8_clk_000_d_i_n.BLIF state_machine_un13_clk_000_d_i_n.BLIF VMA_INT_1_sqmuxa +.names N_108_i.BLIF N_109_i.BLIF SM_AMIGA_1_.D 11 1 -.names inst_AS_000_INTreg.BLIF AS_000_INT_i -0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C +.names N_106_i.BLIF N_107_i.BLIF sm_amiga_ns_0_5__n +11 1 +.names RST_i.BLIF SM_AMIGA_7_.AP 1 1 -.names dsack_c_1__n.BLIF dsack_i_1__n -0 1 -.names AS_000_INT_i.BLIF dsack_i_1__n.BLIF state_machine_un13_as_000_int_n +.names N_101_i.BLIF N_102_i.BLIF sm_amiga_ns_0_2__n 11 1 -.names RST_i.BLIF SM_AMIGA_1_.AR -1 1 -.names inst_CLK_000_D.BLIF CLK_000_D_i -0 1 -.names CLK_000_D_i.BLIF CLK_000_c.BLIF inst_RISING_CLK_AMIGA.D -11 1 -.names cpu_est_d_3_.BLIF cpu_est_d_i_3__n -0 1 -.names cpu_est_d_0_.BLIF cpu_est_d_i_0__n -0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C -1 1 -.names clk_un3_clk_000_dd_n.BLIF cpu_est_0_3__un3_n -0 1 -.names clk_cpu_est_11_3__n.BLIF clk_un3_clk_000_dd_n.BLIF cpu_est_0_3__un1_n -11 1 -.names RST_i.BLIF SM_AMIGA_0_.AR -1 1 -.names cpu_est_3_reg.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n -11 1 -.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_reg.D -1- 1 --1 1 -.names clk_un3_clk_000_dd_n.BLIF cpu_est_0_2__un3_n -0 1 -.names cpu_est_0_.BLIF cpu_est_d_0_.D -1 1 -.names N_122_i.BLIF clk_un3_clk_000_dd_n.BLIF cpu_est_0_2__un1_n -11 1 -.names cpu_est_2_.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n -11 1 -.names CLK_OSZI_c.BLIF cpu_est_d_0_.C -1 1 -.names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D -1- 1 --1 1 -.names clk_un3_clk_000_dd_n.BLIF cpu_est_0_1__un3_n -0 1 -.names clk_cpu_est_11_1__n.BLIF clk_un3_clk_000_dd_n.BLIF cpu_est_0_1__un1_n -11 1 -.names cpu_est_1_.BLIF cpu_est_d_1_.D -1 1 -.names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n -11 1 -.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D -1- 1 --1 1 -.names CLK_OSZI_c.BLIF cpu_est_d_1_.C -1 1 -.names inst_CLK_000_D.BLIF CLK_000_DD_i.BLIF clk_un3_clk_000_dd_n +.names inst_CLK_000_D.BLIF N_99_i.BLIF SM_AMIGA_7_.D 11 1 .names state_machine_un13_clk_000_d_1_n.BLIF state_machine_un13_clk_000_d_1_i_n 0 1 .names SM_AMIGA_0_.BLIF state_machine_un13_clk_000_d_1_i_n.BLIF N_110 11 1 -.names cpu_est_2_.BLIF cpu_est_d_2_.D +.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C 1 1 -.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n 0 1 -.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n +.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n 0 1 -.names CLK_OSZI_c.BLIF cpu_est_d_2_.C +.names RST_i.BLIF SM_AMIGA_6_.AR 1 1 -.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_103 +.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_109 11 1 -.names N_112.BLIF SM_AMIGA_6_.BLIF N_102 +.names CLK_000_D_i.BLIF N_94.BLIF N_108 11 1 -.names inst_CLK_000_D.BLIF SM_AMIGA_5_.BLIF N_101 -11 1 -.names cpu_est_3_reg.BLIF cpu_est_d_3_.D -1 1 -.names N_92.BLIF sm_amiga_i_6__n.BLIF N_100 -11 1 -.names N_91.BLIF sm_amiga_i_7__n.BLIF N_99 -11 1 -.names CLK_OSZI_c.BLIF cpu_est_d_3_.C -1 1 -.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n +.names inst_CLK_000_D.BLIF CLK_000_D_i 0 1 -.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n +.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n 0 1 -.names sm_amiga_i_6__n.BLIF sm_amiga_i_7__n.BLIF N_97 -11 1 -.names N_145_i.BLIF state_machine_un31_clk_000_d_n.BLIF state_machine_lds_000_int_8_0_n -11 1 -.names CLK_OSZI_c.BLIF IPL_030DFFSH_0_reg.C +.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C 1 1 -.names a_c_i_0__n.BLIF N_145_i.BLIF state_machine_uds_000_int_8_0_n +.names SM_AMIGA_3_.BLIF state_machine_un60_clk_000_d_i_n.BLIF N_93_0 11 1 -.names cpu_est_2_.BLIF cpu_est_i_2__n +.names DTACK_c.BLIF DTACK_i 0 1 -.names RST_i.BLIF IPL_030DFFSH_0_reg.AP +.names RST_i.BLIF SM_AMIGA_5_.AR 1 1 +.names inst_CLK_000_D.BLIF SM_AMIGA_3_.BLIF VPA_SYNC_1_sqmuxa_1_0 +11 1 +.names state_machine_un8_clk_000_d_1_n.BLIF state_machine_un8_clk_000_d_1_i_0_n +0 1 +.names state_machine_un15_clk_000_d_n.BLIF vma_int_0_un3_n +0 1 +.names state_machine_un8_clk_000_d_1_i_0_n.BLIF state_machine_un15_clk_000_d_n.BLIF vma_int_0_un1_n +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C +1 1 +.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n +11 1 +.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D +1- 1 +-1 1 +.names RST_i.BLIF SM_AMIGA_4_.AR +1 1 +.names state_machine_un8_clk_000_d_i_n.BLIF state_machine_un13_clk_000_d_i_n.BLIF state_machine_un15_clk_000_d_0_n +11 1 +.names CLK_000_D_i.BLIF cpu_est_0_.BLIF state_machine_un8_clk_000_d_1_n +11 1 .names cpu_est_3_reg.BLIF cpu_est_i_3__n 0 1 -.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_128 -11 1 .names cpu_est_0_.BLIF cpu_est_i_0__n 0 1 -.names N_125.BLIF cpu_est_i_0__n.BLIF N_127 -11 1 -.names CLK_OSZI_c.BLIF IPL_030DFFSH_1_reg.C +.names CLK_OSZI_c.BLIF DSACK_INT_1_.C 1 1 -.names CLK_000_D_i.BLIF SM_AMIGA_7_.BLIF N_92_0 -11 1 -.names inst_AS_000_INTreg.BLIF SM_AMIGA_0_.BLIF N_91_0 -11 1 -.names RST_i.BLIF IPL_030DFFSH_1_reg.AP -1 1 -.names N_98_i.BLIF N_110_i.BLIF sm_amiga_ns_0_7__n -11 1 -.names CLK_000_D_i.BLIF N_103_i.BLIF SM_AMIGA_4_.D -11 1 -.names N_101_i.BLIF N_102_i.BLIF sm_amiga_ns_0_2__n -11 1 -.names N_100_i.BLIF N_112_i.BLIF SM_AMIGA_6_.D -11 1 -.names CLK_OSZI_c.BLIF IPL_030DFFSH_2_reg.C -1 1 -.names inst_CLK_000_D.BLIF N_99_i.BLIF SM_AMIGA_7_.D -11 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i -0 1 -.names RST_i.BLIF IPL_030DFFSH_2_reg.AP -1 1 -.names AS_030_000_SYNC_i.BLIF clk_un3_clk_000_dd_n.BLIF N_112 -11 1 -.names inst_CLK_000_DD.BLIF CLK_000_DD_i -0 1 -.names DS_030_c.BLIF DS_030_i +.names cpu_est_1_.BLIF cpu_est_i_1__n 0 1 .names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_135_1 11 1 -.names CLK_OSZI_c.BLIF cpu_est_0_.C +.names RST_i.BLIF DSACK_INT_1_.AP 1 1 -.names N_135_1.BLIF cpu_est_i_2__n.BLIF N_135 -11 1 -.names UDS_000_INT_0_sqmuxa_1.BLIF UDS_000_INT_0_sqmuxa_1_i +.names inst_VPA_D.BLIF VPA_D_i 0 1 -.names UDS_000_INT_0_sqmuxa.BLIF UDS_000_INT_0_sqmuxa_i +.names inst_VMA_INTreg.BLIF VMA_INT_i 0 1 -.names UDS_000_INT_0_sqmuxa_1_i.BLIF UDS_000_INT_0_sqmuxa_i.BLIF N_145 -11 1 -.names CLK_OSZI_c.BLIF cpu_est_1_.C -1 1 -.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_126_i -11 1 -.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF N_125_i -11 1 -.names cpu_est_1_.BLIF cpu_est_i_1__n +.names un1_as_030_4.BLIF uds_000_int_0_un3_n 0 1 -.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_124_i -11 1 -.names CLK_OSZI_c.BLIF cpu_est_2_.C +.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C 1 1 -.names N_131_i.BLIF N_132_i.BLIF N_122_i +.names inst_UDS_000_INTreg.BLIF un1_as_030_4.BLIF uds_000_int_0_un1_n 11 1 -.names N_126_i.BLIF cpu_est_i_2__n.BLIF N_134 +.names state_machine_uds_000_int_8_n.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n 11 1 -.names N_126.BLIF cpu_est_3_reg.BLIF N_133 -11 1 -.names N_124_i.BLIF cpu_est_3_reg.BLIF N_130 -11 1 -.names CLK_OSZI_c.BLIF inst_VPA_SYNC.C +.names RST_i.BLIF inst_VMA_INTreg.AP 1 1 -.names N_125_i.BLIF cpu_est_0_.BLIF N_129 -11 1 -.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF state_machine_un57_clk_000_d_0_n -11 1 -.names RST_i.BLIF inst_VPA_SYNC.AP -1 1 -.names state_machine_un17_clk_030_n.BLIF fpu_cs_int_0_un3_n -0 1 -.names un1_as_030_2.BLIF state_machine_un17_clk_030_n.BLIF fpu_cs_int_0_un1_n -11 1 -.names inst_FPU_CS_INTreg.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un0_n -11 1 -.names fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF inst_FPU_CS_INTreg.D +.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INTreg.D 1- 1 -1 1 -.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C -1 1 -.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n +.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF state_machine_un60_clk_000_d_i_n +11 1 +.names DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un3_n 0 1 -.names AS_030.BLIF AS_030_c -1 1 -.names inst_AS_000_INTreg.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n +.names inst_DTACK_SYNC.BLIF DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un1_n 11 1 -.names RST_i.BLIF inst_AS_030_000_SYNC.AP +.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C 1 1 -.names N_102_i.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n +.names DTACK_SYNC_1_sqmuxa_i.BLIF dtack_sync_0_un3_n.BLIF dtack_sync_0_un0_n 11 1 -.names DS_030.BLIF DS_030_c -1 1 -.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF inst_AS_000_INTreg.D +.names dtack_sync_0_un1_n.BLIF dtack_sync_0_un0_n.BLIF inst_DTACK_SYNC.D 1- 1 -1 1 +.names RST_i.BLIF inst_BGACK_030_INTreg.AP +1 1 .names VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un3_n 0 1 .names inst_VPA_SYNC.BLIF VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un1_n 11 1 -.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C -1 1 -.names SIZE_0_.BLIF size_c_0__n -1 1 .names VPA_SYNC_1_sqmuxa_i.BLIF vpa_sync_0_un3_n.BLIF vpa_sync_0_un0_n 11 1 -.names SIZE_1_.BLIF size_c_1__n -1 1 .names vpa_sync_0_un1_n.BLIF vpa_sync_0_un0_n.BLIF inst_VPA_SYNC.D 1- 1 -1 1 -.names RST_i.BLIF inst_VMA_INTreg.AP -1 1 -.names A_0_.BLIF a_c_0__n -1 1 -.names state_machine_un17_clk_030_n.BLIF as_030_000_sync_0_un3_n -0 1 -.names A_16_.BLIF a_c_16__n -1 1 -.names state_machine_as_030_000_sync_3_n.BLIF state_machine_un17_clk_030_n.BLIF as_030_000_sync_0_un1_n -11 1 -.names A_17_.BLIF a_c_17__n -1 1 -.names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n -11 1 -.names A_18_.BLIF a_c_18__n -1 1 -.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF inst_AS_030_000_SYNC.D -1- 1 --1 1 -.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C -1 1 -.names A_19_.BLIF a_c_19__n -1 1 -.names AS_030_i.BLIF CLK_030_i.BLIF state_machine_un17_clk_030_0_n -11 1 -.names A_20_.BLIF a_c_20__n -1 1 -.names N_102.BLIF N_102_i -0 1 -.names RST_i.BLIF BG_000DFFSHreg.AP -1 1 -.names A_21_.BLIF a_c_21__n -1 1 -.names AS_030_i.BLIF N_102_i.BLIF AS_000_INT_1_sqmuxa -11 1 -.names A_22_.BLIF a_c_22__n +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE.C 1 1 .names VPA_SYNC_1_sqmuxa.BLIF VPA_SYNC_1_sqmuxa_i 0 1 -.names A_23_.BLIF a_c_23__n -1 1 .names AS_030_i.BLIF VPA_SYNC_1_sqmuxa_i.BLIF VPA_SYNC_1_sqmuxa_1 11 1 -.names A_24_.BLIF a_c_24__n +.names DTACK_SYNC_1_sqmuxa.BLIF DTACK_SYNC_1_sqmuxa_i +0 1 +.names AS_030_i.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF DTACK_SYNC_1_sqmuxa_1 +11 1 +.names CLK_OSZI_c.BLIF cpu_est_0_.C 1 1 +.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +0 1 +.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_103 +11 1 +.names CLK_000_D_i.BLIF N_93.BLIF N_104 +11 1 +.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n +0 1 +.names CLK_OSZI_c.BLIF cpu_est_1_.C +1 1 +.names sm_amiga_i_3__n.BLIF sm_amiga_i_4__n.BLIF N_105 +11 1 +.names CLK_000_D_i.BLIF N_103_i.BLIF SM_AMIGA_4_.D +11 1 +.names N_104_i.BLIF N_105_i.BLIF SM_AMIGA_3_.D +11 1 +.names UDS_000_INT_0_sqmuxa_1.BLIF UDS_000_INT_0_sqmuxa_1_i +0 1 +.names CLK_OSZI_c.BLIF cpu_est_2_.C +1 1 +.names UDS_000_INT_0_sqmuxa.BLIF UDS_000_INT_0_sqmuxa_i +0 1 +.names UDS_000_INT_0_sqmuxa_1_i.BLIF UDS_000_INT_0_sqmuxa_i.BLIF N_145 +11 1 +.names N_145_i.BLIF state_machine_un34_clk_000_d_n.BLIF state_machine_lds_000_int_8_0_n +11 1 +.names a_c_i_0__n.BLIF N_145_i.BLIF state_machine_uds_000_int_8_0_n +11 1 +.names CLK_OSZI_c.BLIF cpu_est_3_reg.C +1 1 +.names AS_030_i.BLIF N_145.BLIF un1_as_030_4 +11 1 .names state_machine_un42_clk_030_n.BLIF state_machine_un42_clk_030_i_n 0 1 -.names CLK_OSZI_c.BLIF DSACK_INT_1_.C -1 1 -.names A_25_.BLIF a_c_25__n -1 1 -.names AS_030_i.BLIF state_machine_un42_clk_030_n.BLIF un1_as_030_2_0 +.names AS_030_i.BLIF state_machine_un42_clk_030_n.BLIF un1_as_030_3_0 11 1 -.names A_26_.BLIF a_c_26__n -1 1 -.names RST_i.BLIF DSACK_INT_1_.AP -1 1 -.names A_27_.BLIF a_c_27__n -1 1 -.names inst_AS_000_INTreg.BLIF inst_CLK_000_D.BLIF state_machine_un13_clk_000_d_1_n +.names AS_030_i.BLIF N_98_i.BLIF DSACK_INT_1_sqmuxa 11 1 -.names A_28_.BLIF a_c_28__n -1 1 -.names inst_VPA_D.BLIF VPA_D_i -0 1 -.names A_29_.BLIF a_c_29__n -1 1 -.names CLK_030_c.BLIF CLK_030_i -0 1 -.names A_30_.BLIF a_c_30__n -1 1 -.names BG_030_c_i.BLIF CLK_030_c.BLIF state_machine_un1_clk_030_0_n -11 1 -.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C -1 1 -.names A_31_.BLIF a_c_31__n -1 1 -.names BGACK_000_c.BLIF RISING_CLK_AMIGA_i.BLIF state_machine_un4_bgack_000_0_n -11 1 -.names CPU_SPACE.BLIF CPU_SPACE_c -1 1 -.names a_c_19__n.BLIF a_i_19__n -0 1 -.names RST_i.BLIF inst_BGACK_030_INTreg.AP -1 1 -.names a_c_18__n.BLIF a_i_18__n -0 1 -.names BG_030.BLIF BG_030_c -1 1 -.names a_c_16__n.BLIF a_i_16__n -0 1 -.names BG_000DFFSHreg.BLIF BG_000 -1 1 -.names inst_RISING_CLK_AMIGA.BLIF ipl_030_0_2__un3_n -0 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030 -1 1 -.names ipl_c_2__n.BLIF inst_RISING_CLK_AMIGA.BLIF ipl_030_0_2__un1_n -11 1 -.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE.C -1 1 -.names BGACK_000.BLIF BGACK_000_c -1 1 -.names IPL_030DFFSH_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n -11 1 -.names CLK_030.BLIF CLK_030_c -1 1 -.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF IPL_030DFFSH_2_reg.D -1- 1 --1 1 -.names CLK_000.BLIF CLK_000_c -1 1 -.names inst_RISING_CLK_AMIGA.BLIF ipl_030_0_1__un3_n -0 1 -.names CLK_OSZI.BLIF CLK_OSZI_c -1 1 -.names ipl_c_1__n.BLIF inst_RISING_CLK_AMIGA.BLIF ipl_030_0_1__un1_n -11 1 -.names CLK_OSZI_c.BLIF inst_UDS_000_INTreg.C -1 1 -.names CLK_OUT_INTreg.BLIF CLK_DIV_OUT -1 1 -.names IPL_030DFFSH_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n -11 1 -.names CLK_OUT_INTreg.BLIF CLK_EXP -1 1 -.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF IPL_030DFFSH_1_reg.D -1- 1 --1 1 -.names RST_i.BLIF inst_UDS_000_INTreg.AP -1 1 -.names inst_FPU_CS_INTreg.BLIF FPU_CS -1 1 -.names inst_RISING_CLK_AMIGA.BLIF ipl_030_0_0__un3_n -0 1 -.names IPL_030DFFSH_0_reg.BLIF IPL_030_0_ -1 1 -.names ipl_c_0__n.BLIF inst_RISING_CLK_AMIGA.BLIF ipl_030_0_0__un1_n -11 1 -.names IPL_030DFFSH_1_reg.BLIF IPL_030_1_ -1 1 -.names IPL_030DFFSH_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n -11 1 -.names IPL_030DFFSH_2_reg.BLIF IPL_030_2_ -1 1 -.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF IPL_030DFFSH_0_reg.D -1- 1 --1 1 .names CLK_OSZI_c.BLIF inst_LDS_000_INTreg.C 1 1 -.names IPL_0_.BLIF ipl_c_0__n -1 1 -.names state_machine_un4_bgack_000_n.BLIF bgack_030_int_0_un3_n -0 1 -.names IPL_1_.BLIF ipl_c_1__n -1 1 -.names BGACK_000_c.BLIF state_machine_un4_bgack_000_n.BLIF bgack_030_int_0_un1_n +.names AS_030_i.BLIF CLK_030_i.BLIF state_machine_un17_clk_030_0_n 11 1 -.names RST_i.BLIF inst_LDS_000_INTreg.AP -1 1 -.names IPL_2_.BLIF ipl_c_2__n -1 1 -.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un0_n -11 1 -.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF inst_BGACK_030_INTreg.D -1- 1 --1 1 .names N_98.BLIF N_98_i 0 1 +.names RST_i.BLIF inst_LDS_000_INTreg.AP +1 1 .names DSACK_INT_1_sqmuxa.BLIF dsack_int_0_1__un3_n 0 1 -.names CLK_OSZI_c.BLIF inst_DTACK_SYNC.C -1 1 -.names vcc_n_n.BLIF AVEC -1 1 .names DSACK_INT_1_.BLIF DSACK_INT_1_sqmuxa.BLIF dsack_int_0_1__un1_n 11 1 .names N_98_i.BLIF dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un0_n 11 1 -.names RST_i.BLIF inst_DTACK_SYNC.AP -1 1 -.names cpu_est_3_reg.BLIF E -1 1 .names dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF DSACK_INT_1_.D 1- 1 -1 1 -.names VPA.BLIF inst_VPA_D.D +.names CLK_OSZI_c.BLIF inst_DTACK_SYNC.C 1 1 -.names state_machine_un1_clk_030_n.BLIF bg_000_0_un3_n +.names state_machine_un17_clk_030_n.BLIF as_030_000_sync_0_un3_n 0 1 -.names inst_VMA_INTreg.BLIF VMA +.names AS_030.BLIF AS_030_c 1 1 -.names un1_bg_030.BLIF state_machine_un1_clk_030_n.BLIF bg_000_0_un1_n +.names state_machine_as_030_000_sync_3_n.BLIF state_machine_un17_clk_030_n.BLIF as_030_000_sync_0_un1_n 11 1 -.names RST.BLIF RST_c +.names RST_i.BLIF inst_DTACK_SYNC.AP 1 1 -.names BG_000DFFSHreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n +.names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n +11 1 +.names DS_030.BLIF DS_030_c +1 1 +.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF inst_AS_030_000_SYNC.D +1- 1 +-1 1 +.names state_machine_un17_clk_030_n.BLIF fpu_cs_int_0_un3_n +0 1 +.names un1_as_030_3.BLIF state_machine_un17_clk_030_n.BLIF fpu_cs_int_0_un1_n 11 1 .names CLK_OSZI_c.BLIF inst_FPU_CS_INTreg.C 1 1 -.names RESETDFFreg.BLIF RESET +.names SIZE_0_.BLIF size_c_0__n 1 1 -.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF BG_000DFFSHreg.D +.names inst_FPU_CS_INTreg.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un0_n +11 1 +.names SIZE_1_.BLIF size_c_1__n +1 1 +.names fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF inst_FPU_CS_INTreg.D 1- 1 -1 1 -.names RW.BLIF RW_c -1 1 -.names DTACK_SYNC_1_sqmuxa.BLIF DTACK_SYNC_1_sqmuxa_i -0 1 .names RST_i.BLIF inst_FPU_CS_INTreg.AP 1 1 -.names FC_0_.BLIF fc_c_0__n +.names A_0_.BLIF a_c_0__n 1 1 -.names DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un3_n +.names un1_as_030_4.BLIF lds_000_int_0_un3_n 0 1 -.names FC_1_.BLIF fc_c_1__n +.names A_16_.BLIF a_c_16__n 1 1 -.names inst_DTACK_SYNC.BLIF DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un1_n +.names inst_LDS_000_INTreg.BLIF un1_as_030_4.BLIF lds_000_int_0_un1_n 11 1 -.names gnd_n_n.BLIF AMIGA_BUS_ENABLE +.names A_17_.BLIF a_c_17__n 1 1 -.names DTACK_SYNC_1_sqmuxa_i.BLIF dtack_sync_0_un3_n.BLIF dtack_sync_0_un0_n +.names state_machine_lds_000_int_8_n.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n 11 1 -.names RW_i.BLIF AMIGA_BUS_DATA_DIR +.names A_18_.BLIF a_c_18__n 1 1 -.names dtack_sync_0_un1_n.BLIF dtack_sync_0_un0_n.BLIF inst_DTACK_SYNC.D +.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF inst_LDS_000_INTreg.D 1- 1 -1 1 +.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C +1 1 +.names A_19_.BLIF a_c_19__n +1 1 +.names cpu_est_1_.BLIF cpu_est_2_.BLIF state_machine_un13_clk_000_d_2_n +11 1 +.names A_20_.BLIF a_c_20__n +1 1 +.names N_135_1.BLIF cpu_est_i_2__n.BLIF N_135 +11 1 +.names RST_i.BLIF inst_AS_030_000_SYNC.AP +1 1 +.names A_21_.BLIF a_c_21__n +1 1 +.names state_machine_un13_clk_000_d_2_n.BLIF state_machine_un13_clk_000_d_2_i_n +0 1 +.names A_22_.BLIF a_c_22__n +1 1 +.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_126_i +11 1 +.names A_23_.BLIF a_c_23__n +1 1 +.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF N_125_i +11 1 +.names A_24_.BLIF a_c_24__n +1 1 +.names N_131_i.BLIF N_132_i.BLIF N_122_i +11 1 .names CLK_OSZI_c.BLIF inst_AS_000_INTreg.C 1 1 -.names vcc_n_n.BLIF AMIGA_BUS_ENABLE_LOW +.names A_25_.BLIF a_c_25__n 1 1 -.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n -0 1 -.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n -0 1 +.names N_126_i.BLIF cpu_est_i_2__n.BLIF N_134 +11 1 +.names A_26_.BLIF a_c_26__n +1 1 +.names N_126.BLIF cpu_est_3_reg.BLIF N_133 +11 1 .names RST_i.BLIF inst_AS_000_INTreg.AP 1 1 -.names RW_c.BLIF SM_AMIGA_6_.BLIF UDS_000_INT_0_sqmuxa_1_2 +.names A_27_.BLIF a_c_27__n +1 1 +.names cpu_est_3_reg.BLIF state_machine_un13_clk_000_d_2_n.BLIF N_130 11 1 -.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_109 +.names A_28_.BLIF a_c_28__n +1 1 +.names cpu_est_2_.BLIF cpu_est_i_2__n +0 1 +.names A_29_.BLIF a_c_29__n +1 1 +.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_128 11 1 -.names UDS_000_INT_0_sqmuxa_1_1.BLIF UDS_000_INT_0_sqmuxa_1_2.BLIF UDS_000_INT_0_sqmuxa_1_3 +.names A_30_.BLIF a_c_30__n +1 1 +.names clk_un4_clk_000_dd_n.BLIF cpu_est_0_3__un3_n +0 1 +.names CLK_OSZI_c.BLIF inst_VPA_SYNC.C +1 1 +.names A_31_.BLIF a_c_31__n +1 1 +.names clk_cpu_est_11_3__n.BLIF clk_un4_clk_000_dd_n.BLIF cpu_est_0_3__un1_n 11 1 -.names N_104_i.BLIF N_105_i.BLIF SM_AMIGA_3_.D +.names CPU_SPACE.BLIF CPU_SPACE_c +1 1 +.names cpu_est_3_reg.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n 11 1 -.names UDS_000_INT_0_sqmuxa_1_3.BLIF clk_un3_clk_000_dd_n.BLIF UDS_000_INT_0_sqmuxa_1 +.names RST_i.BLIF inst_VPA_SYNC.AP +1 1 +.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_reg.D +1- 1 +-1 1 +.names BG_030.BLIF BG_030_c +1 1 +.names clk_un4_clk_000_dd_n.BLIF cpu_est_0_2__un3_n +0 1 +.names BG_000DFFSHreg.BLIF BG_000 +1 1 +.names N_122_i.BLIF clk_un4_clk_000_dd_n.BLIF cpu_est_0_2__un1_n 11 1 -.names N_106_i.BLIF N_107_i.BLIF sm_amiga_ns_0_5__n +.names inst_BGACK_030_INTreg.BLIF BGACK_030 +1 1 +.names cpu_est_2_.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n 11 1 -.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_132_1 +.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C +1 1 +.names BGACK_000.BLIF BGACK_000_c +1 1 +.names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D +1- 1 +-1 1 +.names CLK_030.BLIF CLK_030_c +1 1 +.names DS_030_c.BLIF DS_030_i +0 1 +.names RST_i.BLIF BG_000DFFSHreg.AP +1 1 +.names CLK_000.BLIF inst_CLK_000_D.D +1 1 +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +0 1 +.names CLK_OSZI.BLIF CLK_OSZI_c +1 1 +.names CLK_030_c.BLIF CLK_030_i +0 1 +.names CLK_OUT_INTreg.BLIF CLK_DIV_OUT +1 1 +.names BG_030_c_i.BLIF CLK_030_c.BLIF state_machine_un1_clk_030_0_n 11 1 -.names N_108_i.BLIF N_109_i.BLIF SM_AMIGA_1_.D +.names CLK_OUT_INTreg.BLIF CLK_EXP +1 1 +.names BGACK_000_c.BLIF clk_un4_clk_000_dd_i_n.BLIF state_machine_un6_bgack_000_0_n 11 1 .names CLK_OSZI_c.BLIF inst_DTACK_DMA.C 1 1 -.names N_132_1.BLIF cpu_est_i_2__n.BLIF N_132 +.names inst_FPU_CS_INTreg.BLIF FPU_CS +1 1 +.names sm_amiga_i_6__n.BLIF sm_amiga_i_7__n.BLIF N_97 11 1 -.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n +.names IPL_030DFFSH_0_reg.BLIF IPL_030_0_ +1 1 +.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n 0 1 -.names N_124.BLIF cpu_est_0_.BLIF N_131_1 -11 1 -.names SM_AMIGA_3_.BLIF state_machine_un57_clk_000_d_0_n.BLIF N_93_0 -11 1 .names RST_i.BLIF inst_DTACK_DMA.AP 1 1 -.names N_131_1.BLIF cpu_est_i_3__n.BLIF N_131 -11 1 -.names CLK_OUT_PRE_i.BLIF sm_amiga_i_2__n.BLIF N_94_0 -11 1 -.names AS_030_i.BLIF CPU_SPACE_i.BLIF state_machine_as_030_000_sync_3_0_1_n -11 1 -.names inst_CLK_000_D.BLIF SM_AMIGA_3_.BLIF VPA_SYNC_1_sqmuxa_1_0 -11 1 -.names state_machine_as_030_000_sync_3_0_1_n.BLIF state_machine_un42_clk_030_i_n.BLIF state_machine_as_030_000_sync_3_0_n -11 1 -.names inst_CLK_000_D.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_0 -11 1 -.names DTACK_c.BLIF DTACK_i -0 1 -.names CLK_OSZI_c.BLIF inst_RISING_CLK_AMIGA.C +.names IPL_030DFFSH_1_reg.BLIF IPL_030_1_ 1 1 -.names RW_i.BLIF SM_AMIGA_4_.BLIF UDS_000_INT_0_sqmuxa_2 +.names N_92.BLIF sm_amiga_i_6__n.BLIF N_100 11 1 -.names inst_VMA_INTreg.BLIF VMA_INT_i +.names IPL_030DFFSH_2_reg.BLIF IPL_030_2_ +1 1 +.names N_112.BLIF SM_AMIGA_6_.BLIF N_102 +11 1 +.names IPL_0_.BLIF ipl_c_0__n +1 1 +.names inst_CLK_000_DD.BLIF CLK_000_DD_i 0 1 -.names UDS_000_INT_0_sqmuxa_1_0.BLIF UDS_000_INT_0_sqmuxa_2.BLIF UDS_000_INT_0_sqmuxa +.names IPL_1_.BLIF ipl_c_1__n +1 1 +.names inst_CLK_000_D.BLIF CLK_000_DD_i.BLIF clk_un4_clk_000_dd_n 11 1 -.names AS_030_i.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF DTACK_SYNC_1_sqmuxa_1 +.names CLK_OSZI_c.BLIF inst_UDS_000_INTreg.C +1 1 +.names IPL_2_.BLIF ipl_c_2__n +1 1 +.names AS_030_000_SYNC_i.BLIF clk_un4_clk_000_dd_n.BLIF N_112 11 1 -.names cpu_est_d_i_0__n.BLIF cpu_est_d_i_3__n.BLIF state_machine_un13_clk_000_d_1_0_n +.names N_100_i.BLIF N_112_i.BLIF SM_AMIGA_6_.D 11 1 -.names AS_030_i.BLIF N_98_i.BLIF DSACK_INT_1_sqmuxa +.names RST_i.BLIF inst_UDS_000_INTreg.AP +1 1 +.names CLK_000_D_i.BLIF SM_AMIGA_7_.BLIF N_92_0 11 1 -.names state_machine_un13_clk_000_d_1_0_n.BLIF state_machine_un13_clk_000_d_4_n.BLIF state_machine_un13_clk_000_d_n +.names N_125.BLIF cpu_est_i_0__n.BLIF N_127 +11 1 +.names vcc_n_n.BLIF AVEC +1 1 +.names N_125_i.BLIF cpu_est_0_.BLIF N_129 11 1 -.names a_c_24__n.BLIF a_i_24__n -0 1 .names CLK_OSZI_c.BLIF CLK_CNT_0_.C 1 1 -.names state_machine_un13_clk_000_d_1_n.BLIF cpu_est_d_1_.BLIF state_machine_un13_clk_000_d_4_1_n -11 1 -.names a_c_25__n.BLIF a_i_25__n +.names cpu_est_3_reg.BLIF E +1 1 +.names a_c_16__n.BLIF a_i_16__n 0 1 -.names state_machine_un13_clk_000_d_4_1_n.BLIF cpu_est_d_2_.BLIF state_machine_un13_clk_000_d_4_n -11 1 -.names a_c_26__n.BLIF a_i_26__n +.names VPA.BLIF inst_VPA_D.D +1 1 +.names a_c_18__n.BLIF a_i_18__n 0 1 -.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF state_machine_un8_clk_000_d_1_n -11 1 -.names a_c_27__n.BLIF a_i_27__n +.names inst_VMA_INTreg.BLIF VMA +1 1 +.names a_c_19__n.BLIF a_i_19__n 0 1 -.names CLK_000_D_i.BLIF VPA_D_i.BLIF state_machine_un8_clk_000_d_2_n -11 1 -.names a_c_28__n.BLIF a_i_28__n +.names RST.BLIF RST_c +1 1 +.names a_c_24__n.BLIF a_i_24__n 0 1 .names CLK_OSZI_c.BLIF inst_VPA_D.C 1 1 -.names cpu_est_0_.BLIF cpu_est_2_.BLIF state_machine_un8_clk_000_d_3_n -11 1 -.names a_c_29__n.BLIF a_i_29__n -0 1 -.names state_machine_un8_clk_000_d_1_n.BLIF state_machine_un8_clk_000_d_2_n.BLIF state_machine_un8_clk_000_d_4_n -11 1 -.names a_c_30__n.BLIF a_i_30__n -0 1 -.names state_machine_un8_clk_000_d_4_n.BLIF state_machine_un8_clk_000_d_3_n.BLIF state_machine_un8_clk_000_d_n -11 1 -.names a_c_31__n.BLIF a_i_31__n -0 1 -.names CLK_000_c.BLIF inst_CLK_000_D.D +.names RESETDFFreg.BLIF RESET 1 1 -.names AS_030_000_SYNC_i.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_1 -11 1 -.names CLK_000_D_i.BLIF N_93.BLIF N_104 -11 1 -.names a_c_17__n.BLIF a_i_16__n.BLIF state_machine_un42_clk_030_1_n -11 1 -.names sm_amiga_i_3__n.BLIF sm_amiga_i_4__n.BLIF N_105 -11 1 +.names a_c_25__n.BLIF a_i_25__n +0 1 +.names RW.BLIF RW_c +1 1 +.names a_c_26__n.BLIF a_i_26__n +0 1 +.names FC_0_.BLIF fc_c_0__n +1 1 +.names a_c_27__n.BLIF a_i_27__n +0 1 +.names FC_1_.BLIF fc_c_1__n +1 1 +.names a_c_28__n.BLIF a_i_28__n +0 1 .names CLK_OSZI_c.BLIF inst_CLK_000_D.C 1 1 -.names a_i_18__n.BLIF a_i_19__n.BLIF state_machine_un42_clk_030_2_n -11 1 -.names CLK_000_D_i.BLIF SM_AMIGA_2_.BLIF N_106 -11 1 -.names fc_c_1__n.BLIF BGACK_000_c.BLIF state_machine_un42_clk_030_3_n -11 1 -.names CLK_000_D_i.BLIF N_94.BLIF N_108 -11 1 -.names state_machine_un42_clk_030_1_n.BLIF state_machine_un42_clk_030_2_n.BLIF state_machine_un42_clk_030_4_n -11 1 -.names state_machine_un13_as_000_int_n.BLIF inst_DTACK_DMA.D +.names gnd_n_n.BLIF AMIGA_BUS_ENABLE +1 1 +.names a_c_29__n.BLIF a_i_29__n +0 1 +.names RW_i.BLIF AMIGA_BUS_DATA_DIR +1 1 +.names a_c_30__n.BLIF a_i_30__n +0 1 +.names vcc_n_n.BLIF AMIGA_BUS_ENABLE_LOW +1 1 +.names a_c_31__n.BLIF a_i_31__n 0 1 .names RST_c.BLIF RESETDFFreg.D 1 1 -.names state_machine_un42_clk_030_3_n.BLIF fc_c_0__n.BLIF state_machine_un42_clk_030_5_n +.names state_machine_un13_as_000_int_n.BLIF inst_DTACK_DMA.D +0 1 +.names cpu_est_2_.BLIF cpu_est_i_1__n.BLIF state_machine_un8_clk_000_d_2_n 11 1 .names RST_c.BLIF RST_i 0 1 -.names state_machine_un42_clk_030_4_n.BLIF state_machine_un42_clk_030_5_n.BLIF state_machine_un42_clk_030_n +.names CLK_OSZI_c.BLIF RESETDFFreg.C +1 1 +.names state_machine_un8_clk_000_d_1_0_n.BLIF state_machine_un8_clk_000_d_2_n.BLIF state_machine_un8_clk_000_d_3_n 11 1 .names CLK_CNT_0_.BLIF CLK_CNT_0_.D 0 1 -.names CLK_OSZI_c.BLIF RESETDFFreg.C -1 1 -.names DTACK_i.BLIF inst_VPA_D.BLIF DTACK_SYNC_1_sqmuxa_1_0 +.names state_machine_un8_clk_000_d_3_n.BLIF cpu_est_i_3__n.BLIF state_machine_un8_clk_000_d_n 11 1 .names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i 0 1 -.names DTACK_SYNC_1_sqmuxa_1_0.BLIF VPA_SYNC_1_sqmuxa_1_0.BLIF DTACK_SYNC_1_sqmuxa +.names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF state_machine_un13_clk_000_d_1_0_n 11 1 .names CPU_SPACE_c.BLIF CPU_SPACE_i 0 1 -.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF VPA_SYNC_1_sqmuxa_1_1 +.names inst_CLK_000_D.BLIF inst_CLK_000_DD.D +1 1 +.names state_machine_un13_clk_000_d_1_n.BLIF state_machine_un13_clk_000_d_2_n.BLIF state_machine_un13_clk_000_d_2_0_n 11 1 .names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i 0 1 -.names inst_CLK_000_D.BLIF inst_CLK_000_DD.D +.names state_machine_un13_clk_000_d_1_0_n.BLIF state_machine_un13_clk_000_d_2_0_n.BLIF state_machine_un13_clk_000_d_n +11 1 +.names state_machine_un1_clk_030_n.BLIF bg_000_0_un3_n +0 1 +.names CLK_OSZI_c.BLIF inst_CLK_000_DD.C 1 1 +.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF VPA_SYNC_1_sqmuxa_1_1 +11 1 +.names un1_bg_030.BLIF state_machine_un1_clk_030_n.BLIF bg_000_0_un1_n +11 1 .names N_135_1.BLIF VMA_INT_i.BLIF VPA_SYNC_1_sqmuxa_2 11 1 -.names gnd_n_n +.names BG_000DFFSHreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n +11 1 .names VPA_D_i.BLIF VPA_SYNC_1_sqmuxa_1_0.BLIF VPA_SYNC_1_sqmuxa_3 11 1 -.names vcc_n_n -1 -.names CLK_OSZI_c.BLIF inst_CLK_000_DD.C +.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF BG_000DFFSHreg.D +1- 1 +-1 1 +.names inst_CLK_OUT_PRE.BLIF CLK_OUT_INTreg.D 1 1 .names VPA_SYNC_1_sqmuxa_1_1.BLIF VPA_SYNC_1_sqmuxa_2.BLIF VPA_SYNC_1_sqmuxa_4 11 1 -.names A_15_.BLIF a_15__n -1 1 +.names state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n +0 1 .names VPA_SYNC_1_sqmuxa_4.BLIF VPA_SYNC_1_sqmuxa_3.BLIF VPA_SYNC_1_sqmuxa 11 1 -.names A_14_.BLIF a_14__n +.names BGACK_000_c.BLIF state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n +11 1 +.names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C 1 1 +.names CLK_000_D_i.BLIF SM_AMIGA_3_.BLIF N_107_1 +11 1 +.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un0_n +11 1 +.names N_107_1.BLIF state_machine_un60_clk_000_d_n.BLIF N_107 +11 1 +.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF inst_BGACK_030_INTreg.D +1- 1 +-1 1 .names CLK_000_D_i.BLIF inst_CLK_OUT_PRE.BLIF N_98_1 11 1 -.names A_13_.BLIF a_13__n -1 1 -.names inst_CLK_OUT_PRE.BLIF CLK_OUT_INTreg.D +.names clk_un4_clk_000_dd_n.BLIF cpu_est_0_1__un3_n +0 1 +.names CLK_CNT_0_.BLIF CLK_OUT_PRE_0.X1 1 1 .names N_98_1.BLIF SM_AMIGA_1_.BLIF N_98 11 1 -.names A_12_.BLIF a_12__n -1 1 -.names N_130_i.BLIF N_128_i.BLIF clk_cpu_est_11_0_1_1__n +.names clk_cpu_est_11_1__n.BLIF clk_un4_clk_000_dd_n.BLIF cpu_est_0_1__un1_n 11 1 -.names A_11_.BLIF a_11__n -1 1 -.names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C -1 1 -.names N_127_i.BLIF N_129_i.BLIF clk_cpu_est_11_0_2_1__n +.names state_machine_un42_clk_030_4_n.BLIF state_machine_un42_clk_030_5_n.BLIF state_machine_un42_clk_030_n 11 1 -.names A_10_.BLIF a_10__n -1 1 -.names clk_cpu_est_11_0_1_1__n.BLIF clk_cpu_est_11_0_2_1__n.BLIF clk_cpu_est_11_0_1__n +.names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n 11 1 -.names A_9_.BLIF a_9__n -1 1 -.names a_i_24__n.BLIF a_i_25__n.BLIF N_167_1 -11 1 -.names A_8_.BLIF a_8__n -1 1 -.names clk_un3_clk_000_dd_n.BLIF cpu_est_0_0_.X1 -1 1 -.names a_i_26__n.BLIF a_i_27__n.BLIF N_167_2 -11 1 -.names A_7_.BLIF a_7__n -1 1 -.names a_i_28__n.BLIF a_i_29__n.BLIF N_167_3 -11 1 -.names A_6_.BLIF a_6__n -1 1 -.names cpu_est_0_.BLIF cpu_est_0_0_.X2 -1 1 -.names a_i_30__n.BLIF a_i_31__n.BLIF N_167_4 -11 1 -.names A_5_.BLIF a_5__n -1 1 -.names N_167_1.BLIF N_167_2.BLIF N_167_5 -11 1 -.names A_4_.BLIF a_4__n -1 1 -.names N_167_3.BLIF N_167_4.BLIF N_167_6 -11 1 -.names A_3_.BLIF a_3__n -1 1 -.names CLK_CNT_0_.BLIF CLK_OUT_PRE_0.X1 -1 1 -.names N_167_5.BLIF N_167_6.BLIF N_167 -11 1 -.names A_2_.BLIF a_2__n -1 1 -.names a_c_20__n.BLIF a_c_21__n.BLIF N_170_1 -11 1 -.names A_1_.BLIF a_1__n -1 1 .names inst_CLK_OUT_PRE.BLIF CLK_OUT_PRE_0.X2 1 1 -.names a_c_22__n.BLIF a_c_23__n.BLIF N_170_2 +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_132_1 11 1 -.names N_170_1.BLIF N_170_2.BLIF N_170 +.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D +1- 1 +-1 1 +.names N_132_1.BLIF cpu_est_i_2__n.BLIF N_132 11 1 -.names CLK_000_D_i.BLIF SM_AMIGA_3_.BLIF N_107_1 +.names clk_un4_clk_000_dd_n.BLIF ipl_030_0_0__un3_n +0 1 +.names cpu_est_0_.BLIF cpu_est_i_3__n.BLIF N_131_1 11 1 -.names cpu_est_0_0_.BLIF cpu_est_0_.D +.names ipl_c_0__n.BLIF clk_un4_clk_000_dd_n.BLIF ipl_030_0_0__un1_n +11 1 +.names clk_un4_clk_000_dd_n.BLIF cpu_est_0_0_.X1 1 1 -.names N_107_1.BLIF state_machine_un57_clk_000_d_n.BLIF N_107 +.names N_131_1.BLIF state_machine_un13_clk_000_d_2_i_n.BLIF N_131 +11 1 +.names IPL_030DFFSH_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n +11 1 +.names inst_CLK_000_D.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_0 +11 1 +.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF IPL_030DFFSH_0_reg.D +1- 1 +-1 1 +.names cpu_est_0_.BLIF cpu_est_0_0_.X2 +1 1 +.names RW_i.BLIF SM_AMIGA_4_.BLIF UDS_000_INT_0_sqmuxa_2 +11 1 +.names clk_un4_clk_000_dd_n.BLIF ipl_030_0_1__un3_n +0 1 +.names UDS_000_INT_0_sqmuxa_1_0.BLIF UDS_000_INT_0_sqmuxa_2.BLIF UDS_000_INT_0_sqmuxa +11 1 +.names ipl_c_1__n.BLIF clk_un4_clk_000_dd_n.BLIF ipl_030_0_1__un1_n +11 1 +.names AS_030_000_SYNC_i.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_1 +11 1 +.names IPL_030DFFSH_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n 11 1 .names CLK_OUT_PRE_0.BLIF inst_CLK_OUT_PRE.D 1 1 -.names N_93_0.BLIF N_93 -0 1 -.names N_108.BLIF N_108_i -0 1 -.names N_109.BLIF N_109_i -0 1 -.names N_106.BLIF N_106_i -0 1 -.names N_107.BLIF N_107_i -0 1 -.names sm_amiga_ns_0_5__n.BLIF SM_AMIGA_2_.D -0 1 -.names N_104.BLIF N_104_i -0 1 -.names N_105.BLIF N_105_i -0 1 -.names BG_030_c_i.BLIF CPU_SPACE_i.BLIF un1_bg_030_0_1 +.names RW_c.BLIF SM_AMIGA_6_.BLIF UDS_000_INT_0_sqmuxa_1_2 11 1 -.names AS_030_c.BLIF N_97_i.BLIF un1_bg_030_0_2 +.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF IPL_030DFFSH_1_reg.D +1- 1 +-1 1 +.names cpu_est_0_0_.BLIF cpu_est_0_.D +1 1 +.names UDS_000_INT_0_sqmuxa_1_1.BLIF UDS_000_INT_0_sqmuxa_1_2.BLIF UDS_000_INT_0_sqmuxa_1_3 11 1 +.names clk_un4_clk_000_dd_n.BLIF ipl_030_0_2__un3_n +0 1 +.names UDS_000_INT_0_sqmuxa_1_3.BLIF clk_un4_clk_000_dd_n.BLIF UDS_000_INT_0_sqmuxa_1 +11 1 +.names ipl_c_2__n.BLIF clk_un4_clk_000_dd_n.BLIF ipl_030_0_2__un1_n +11 1 +.names DTACK_i.BLIF inst_VPA_D.BLIF DTACK_SYNC_1_sqmuxa_1_0 +11 1 +.names IPL_030DFFSH_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n +11 1 +.names DTACK_SYNC_1_sqmuxa_1_0.BLIF VPA_SYNC_1_sqmuxa_1_0.BLIF DTACK_SYNC_1_sqmuxa +11 1 +.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF IPL_030DFFSH_2_reg.D +1- 1 +-1 1 +.names state_machine_un8_clk_000_d_1_n.BLIF VPA_D_i.BLIF state_machine_un8_clk_000_d_1_0_n +11 1 +.names gnd_n_n +.names N_168_5.BLIF N_168_6.BLIF N_168 +11 1 +.names vcc_n_n +1 +.names a_c_20__n.BLIF a_c_21__n.BLIF N_171_1 +11 1 +.names A_15_.BLIF a_15__n +1 1 +.names a_c_22__n.BLIF a_c_23__n.BLIF N_171_2 +11 1 +.names A_14_.BLIF a_14__n +1 1 +.names N_171_1.BLIF N_171_2.BLIF N_171 +11 1 +.names A_13_.BLIF a_13__n +1 1 +.names AS_030_c.BLIF BG_030_c_i.BLIF un1_bg_030_0_1 +11 1 +.names A_12_.BLIF a_12__n +1 1 +.names CPU_SPACE_i.BLIF N_97_i.BLIF un1_bg_030_0_2 +11 1 +.names A_11_.BLIF a_11__n +1 1 .names un1_bg_030_0_1.BLIF un1_bg_030_0_2.BLIF un1_bg_030_0 11 1 -.names size_c_0__n.BLIF a_c_i_0__n.BLIF state_machine_un31_clk_000_d_i_1_n +.names A_10_.BLIF a_10__n +1 1 +.names N_127_i.BLIF N_128_i.BLIF clk_cpu_est_11_0_1_1__n 11 1 -.names state_machine_un31_clk_000_d_i_1_n.BLIF size_c_i_1__n.BLIF state_machine_un31_clk_000_d_i_n +.names A_9_.BLIF a_9__n +1 1 +.names N_129_i.BLIF N_130_i.BLIF clk_cpu_est_11_0_2_1__n 11 1 +.names A_8_.BLIF a_8__n +1 1 +.names clk_cpu_est_11_0_1_1__n.BLIF clk_cpu_est_11_0_2_1__n.BLIF clk_cpu_est_11_0_1__n +11 1 +.names A_7_.BLIF a_7__n +1 1 +.names a_c_17__n.BLIF a_i_16__n.BLIF state_machine_un42_clk_030_1_n +11 1 +.names A_6_.BLIF a_6__n +1 1 +.names a_i_18__n.BLIF a_i_19__n.BLIF state_machine_un42_clk_030_2_n +11 1 +.names A_5_.BLIF a_5__n +1 1 +.names fc_c_1__n.BLIF BGACK_000_c.BLIF state_machine_un42_clk_030_3_n +11 1 +.names A_4_.BLIF a_4__n +1 1 +.names state_machine_un42_clk_030_1_n.BLIF state_machine_un42_clk_030_2_n.BLIF state_machine_un42_clk_030_4_n +11 1 +.names A_3_.BLIF a_3__n +1 1 +.names state_machine_un42_clk_030_3_n.BLIF fc_c_0__n.BLIF state_machine_un42_clk_030_5_n +11 1 +.names A_2_.BLIF a_2__n +1 1 +.names clk_un4_clk_000_dd_n.BLIF clk_un4_clk_000_dd_i_n +0 1 +.names A_1_.BLIF a_1__n +1 1 +.names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n +0 1 +.names state_machine_un1_clk_030_0_n.BLIF state_machine_un1_clk_030_n +0 1 .names N_135_i.BLIF N_133_i.BLIF clk_cpu_est_11_0_1_3__n 11 1 .names clk_cpu_est_11_0_1_3__n.BLIF N_134_i.BLIF clk_cpu_est_11_0_3__n 11 1 -.names clk_cpu_est_11_0_3__n.BLIF clk_cpu_est_11_3__n -0 1 -.names size_c_1__n.BLIF size_c_i_1__n -0 1 -.names state_machine_un31_clk_000_d_i_n.BLIF state_machine_un31_clk_000_d_n -0 1 -.names state_machine_as_030_000_sync_3_0_n.BLIF state_machine_as_030_000_sync_3_n -0 1 -.names un1_as_030_2_0.BLIF un1_as_030_2 -0 1 -.names state_machine_un17_clk_030_0_n.BLIF state_machine_un17_clk_030_n -0 1 -.names state_machine_un57_clk_000_d_0_n.BLIF state_machine_un57_clk_000_d_n -0 1 -.names inst_RISING_CLK_AMIGA.BLIF RISING_CLK_AMIGA_i -0 1 -.names state_machine_un4_bgack_000_0_n.BLIF state_machine_un4_bgack_000_n -0 1 -.names BG_030_c.BLIF BG_030_c_i -0 1 -.names state_machine_un1_clk_030_0_n.BLIF state_machine_un1_clk_030_n -0 1 -.names N_97.BLIF N_97_i -0 1 -.names un1_bg_030_0.BLIF un1_bg_030 -0 1 -.names inst_CLK_OUT_PRE.BLIF CLK_OUT_PRE_i -0 1 -.names N_94_0.BLIF N_94 -0 1 -.names N_91_0.BLIF N_91 -0 1 -.names N_92_0.BLIF N_92 -0 1 -.names N_131.BLIF N_131_i -0 1 -.names N_132.BLIF N_132_i -0 1 -.names N_124_i.BLIF N_124 -0 1 -.names N_125_i.BLIF N_125 -0 1 -.names CLK_OSZI_c.BLIF cpu_est_3_reg.C -1 1 -.names N_126_i.BLIF N_126 -0 1 -.names N_129.BLIF N_129_i -0 1 -.names N_127.BLIF N_127_i -0 1 -.names N_128.BLIF N_128_i -0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_7_.C -1 1 -.names N_130.BLIF N_130_i -0 1 -.names clk_cpu_est_11_0_1__n.BLIF clk_cpu_est_11_1__n -0 1 -.names RST_i.BLIF SM_AMIGA_7_.AP -1 1 +.names size_c_0__n.BLIF a_c_i_0__n.BLIF state_machine_un34_clk_000_d_i_1_n +11 1 +.names state_machine_un34_clk_000_d_i_1_n.BLIF size_c_i_1__n.BLIF state_machine_un34_clk_000_d_i_n +11 1 +.names AS_030_i.BLIF CPU_SPACE_i.BLIF state_machine_as_030_000_sync_3_2_1_n +11 1 +.names state_machine_as_030_000_sync_3_2_1_n.BLIF state_machine_un42_clk_030_i_n.BLIF state_machine_as_030_000_sync_3_2_n +11 1 +.names a_i_24__n.BLIF a_i_25__n.BLIF N_168_1 +11 1 +.names a_i_26__n.BLIF a_i_27__n.BLIF N_168_2 +11 1 +.names a_i_28__n.BLIF a_i_29__n.BLIF N_168_3 +11 1 +.names a_i_30__n.BLIF a_i_31__n.BLIF N_168_4 +11 1 +.names N_168_1.BLIF N_168_2.BLIF N_168_5 +11 1 +.names N_168_3.BLIF N_168_4.BLIF N_168_6 +11 1 .names N_134.BLIF N_134_i 0 1 .names N_133.BLIF N_133_i 0 1 .names N_135.BLIF N_135_i 0 1 +.names clk_cpu_est_11_0_3__n.BLIF clk_cpu_est_11_3__n +0 1 +.names N_130.BLIF N_130_i +0 1 +.names clk_cpu_est_11_0_1__n.BLIF clk_cpu_est_11_1__n +0 1 +.names N_128.BLIF N_128_i +0 1 +.names un1_bg_030_0.BLIF un1_bg_030 +0 1 +.names N_97.BLIF N_97_i +0 1 +.names BG_030_c.BLIF BG_030_c_i +0 1 +.names N_127.BLIF N_127_i +0 1 +.names N_129.BLIF N_129_i +0 1 +.names N_92_0.BLIF N_92 +0 1 +.names N_100.BLIF N_100_i +0 1 +.names N_112.BLIF N_112_i +0 1 +.names N_103.BLIF N_103_i +0 1 +.names state_machine_un60_clk_000_d_i_n.BLIF state_machine_un60_clk_000_d_n +0 1 +.names state_machine_un17_clk_030_0_n.BLIF state_machine_un17_clk_030_n +0 1 +.names un1_as_030_3_0.BLIF un1_as_030_3 +0 1 .names N_145.BLIF N_145_i 0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C -1 1 .names a_c_0__n.BLIF a_c_i_0__n 0 1 .names state_machine_uds_000_int_8_0_n.BLIF state_machine_uds_000_int_8_n 0 1 -.names RST_i.BLIF SM_AMIGA_6_.AR -1 1 .names state_machine_lds_000_int_8_0_n.BLIF state_machine_lds_000_int_8_n 0 1 +.names state_machine_as_030_000_sync_3_2_n.BLIF state_machine_as_030_000_sync_3_n +0 1 +.names size_c_1__n.BLIF size_c_i_1__n +0 1 +.names state_machine_un34_clk_000_d_i_n.BLIF state_machine_un34_clk_000_d_n +0 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C +1 1 +.names N_131.BLIF N_131_i +0 1 +.names N_132.BLIF N_132_i +0 1 +.names RST_i.BLIF SM_AMIGA_3_.AR +1 1 +.names N_125_i.BLIF N_125 +0 1 +.names N_126_i.BLIF N_126 +0 1 +.names N_106.BLIF N_106_i +0 1 +.names sm_amiga_ns_0_5__n.BLIF SM_AMIGA_2_.D +0 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C +1 1 +.names N_108.BLIF N_108_i +0 1 +.names N_109.BLIF N_109_i +0 1 +.names RST_i.BLIF SM_AMIGA_2_.AR +1 1 +.names N_110.BLIF N_110_i +0 1 +.names sm_amiga_ns_0_7__n.BLIF SM_AMIGA_0_.D +0 1 +.names N_91_0.BLIF N_91 +0 1 +.names inst_CLK_OUT_PRE.BLIF CLK_OUT_PRE_i +0 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C +1 1 +.names N_94_0.BLIF N_94 +0 1 +.names state_machine_un8_clk_000_d_n.BLIF state_machine_un8_clk_000_d_i_n +0 1 +.names RST_i.BLIF SM_AMIGA_1_.AR +1 1 +.names state_machine_un13_clk_000_d_n.BLIF state_machine_un13_clk_000_d_i_n +0 1 +.names state_machine_un15_clk_000_d_0_n.BLIF state_machine_un15_clk_000_d_n +0 1 +.names N_93_0.BLIF N_93 +0 1 +.names N_104.BLIF N_104_i +0 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C +1 1 +.names N_105.BLIF N_105_i +0 1 .names N_99.BLIF N_99_i 0 1 -.names N_112.BLIF N_112_i -0 1 -.names N_100.BLIF N_100_i -0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C +.names RST_i.BLIF SM_AMIGA_0_.AR 1 1 .names N_101.BLIF N_101_i 0 1 .names sm_amiga_ns_0_2__n.BLIF SM_AMIGA_5_.D 0 1 -.names RST_i.BLIF SM_AMIGA_5_.AR -1 1 -.names N_103.BLIF N_103_i +.names N_107.BLIF N_107_i 0 1 -.names N_110.BLIF N_110_i -0 1 -.names sm_amiga_ns_0_7__n.BLIF SM_AMIGA_0_.D -0 1 -.names VMA_INT_1_sqmuxa.BLIF vma_int_0_un3_n -0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C -1 1 -.names inst_VMA_INTreg.BLIF VMA_INT_1_sqmuxa.BLIF vma_int_0_un1_n +.names CLK_000_D_i.BLIF SM_AMIGA_2_.BLIF N_106 11 1 -.names state_machine_un13_clk_000_d_4_n.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n -11 1 -.names RST_i.BLIF SM_AMIGA_4_.AR +.names CLK_OSZI_c.BLIF IPL_030DFFSH_0_reg.C 1 1 -.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D -1- 1 --1 1 -.names un2_clk_030_1.BLIF lds_000_int_0_un3_n -0 1 -.names inst_LDS_000_INTreg.BLIF un2_clk_030_1.BLIF lds_000_int_0_un1_n +.names inst_CLK_000_D.BLIF SM_AMIGA_5_.BLIF N_101 11 1 +.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n +0 1 +.names RST_i.BLIF IPL_030DFFSH_0_reg.AP +1 1 +.names N_91.BLIF sm_amiga_i_7__n.BLIF N_99 +11 1 +.names AS_030_c.BLIF AS_030_i +0 1 +.names AS_030_i.BLIF N_102_i.BLIF AS_000_INT_1_sqmuxa +11 1 +.names inst_AS_000_INTreg.BLIF AS_000_INT_i +0 1 +.names CLK_OSZI_c.BLIF IPL_030DFFSH_1_reg.C +1 1 +.names dsack_c_1__n.BLIF dsack_i_1__n +0 1 +.names AS_000_INT_i.BLIF dsack_i_1__n.BLIF state_machine_un13_as_000_int_n +11 1 +.names RST_i.BLIF IPL_030DFFSH_1_reg.AP +1 1 +.names N_102.BLIF N_102_i +0 1 +.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n +0 1 .end diff --git a/Logic/BUS68030.bl1 b/Logic/BUS68030.bl1 index e70e888..9c85ea1 100644 --- a/Logic/BUS68030.bl1 +++ b/Logic/BUS68030.bl1 @@ -1,85 +1,86 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Thu May 15 22:21:53 2014 +#$ DATE Thu May 15 23:02:46 2014 #$ MODULE bus68030 -#$ PINS 74 A_28_ A_27_ SIZE_1_ A_26_ A_25_ A_31_ A_24_ A_23_ IPL_030_2_ A_22_ A_21_ \ -# IPL_2_ A_20_ A_19_ DSACK_1_ A_18_ A_17_ FC_1_ A_16_ AS_030 A_15_ AS_000 A_14_ DS_030 A_13_ \ -# UDS_000 A_12_ LDS_000 A_11_ CPU_SPACE A_10_ BERR A_9_ BG_030 A_8_ BG_000 A_7_ BGACK_030 \ -# A_6_ BGACK_000 A_5_ CLK_030 A_4_ CLK_000 A_3_ CLK_OSZI A_2_ CLK_DIV_OUT A_1_ CLK_EXP A_0_ \ -# FPU_CS IPL_030_1_ DTACK IPL_030_0_ AVEC IPL_1_ AVEC_EXP IPL_0_ E DSACK_0_ VPA FC_0_ VMA RST \ -# RESET RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ \ -# A_29_ -#$ NODES 351 CLK_OSZI_c CLK_OUT_INTreg IPL_030DFFSH_0_reg inst_BGACK_030_INTreg \ -# inst_FPU_CS_INTreg IPL_030DFFSH_1_reg cpu_est_3_reg inst_VMA_INTreg \ -# IPL_030DFFSH_2_reg gnd_n_n cpu_est_0_ ipl_c_0__n cpu_est_1_ cpu_est_d_0_ ipl_c_1__n \ -# cpu_est_d_3_ inst_AS_000_INTreg ipl_c_2__n inst_AS_030_000_SYNC inst_DTACK_SYNC \ -# inst_VPA_D dsack_c_1__n inst_VPA_SYNC inst_CLK_000_D DTACK_c inst_CLK_000_DD \ -# inst_CLK_OUT_PRE vcc_n_n cpu_est_d_1_ cpu_est_d_2_ cpu_est_2_ CLK_CNT_0_ SM_AMIGA_6_ \ -# RST_c SM_AMIGA_7_ inst_UDS_000_INTreg RESETDFFreg inst_LDS_000_INTreg RW_c \ -# inst_RISING_CLK_AMIGA state_machine_un57_clk_000_d_n fc_c_0__n SM_AMIGA_1_ \ -# DSACK_INT_1_ fc_c_1__n inst_DTACK_DMA SM_AMIGA_4_ SM_AMIGA_3_ \ -# state_machine_un13_as_000_int_n SM_AMIGA_5_ SM_AMIGA_2_ N_145_i SM_AMIGA_0_ \ -# a_c_i_0__n state_machine_uds_000_int_8_0_n state_machine_lds_000_int_8_0_n N_99_i \ -# N_112_i N_100_i N_101_i sm_amiga_ns_0_2__n N_103_i N_110_i sm_amiga_ns_0_7__n \ -# cpu_est_0_0_ N_91_0 N_92_0 N_131_i N_132_i N_122_i CLK_OUT_PRE_0 N_124_i N_125_i \ -# N_126_i N_129_i N_98 N_127_i N_97 N_128_i N_104 N_130_i N_93 clk_cpu_est_11_0_1__n N_105 \ -# N_134_i N_106 N_133_i N_108 N_135_i N_94 clk_cpu_est_11_0_3__n N_109 size_c_i_1__n \ -# N_107 state_machine_un31_clk_000_d_i_n N_135_1 \ -# state_machine_as_030_000_sync_3_0_n VPA_SYNC_1_sqmuxa_1_0 un1_as_030_2_0 N_167 \ -# state_machine_un17_clk_030_0_n N_170 state_machine_un57_clk_000_d_0_n \ -# state_machine_un42_clk_030_n RISING_CLK_AMIGA_i DTACK_SYNC_1_sqmuxa \ -# state_machine_un4_bgack_000_0_n VPA_SYNC_1_sqmuxa BG_030_c_i un1_bg_030 \ -# state_machine_un1_clk_030_0_n DTACK_SYNC_1_sqmuxa_1 N_97_i DSACK_INT_1_sqmuxa \ -# un1_bg_030_0 state_machine_un1_clk_030_n CLK_OUT_PRE_i \ -# state_machine_un4_bgack_000_n N_94_0 un1_as_030_2 N_93_0 \ -# state_machine_un17_clk_030_n N_108_i N_102 N_109_i AS_000_INT_1_sqmuxa \ -# VPA_SYNC_1_sqmuxa_1 N_106_i state_machine_as_030_000_sync_3_n N_107_i \ -# clk_un3_clk_000_dd_n sm_amiga_ns_0_5__n state_machine_un31_clk_000_d_n N_104_i \ -# UDS_000_INT_0_sqmuxa N_105_i state_machine_un13_clk_000_d_n \ -# state_machine_un13_clk_000_d_4_n un1_bg_030_0_1 state_machine_un13_clk_000_d_1_n \ -# un1_bg_030_0_2 state_machine_un8_clk_000_d_n state_machine_un31_clk_000_d_i_1_n \ -# UDS_000_INT_0_sqmuxa_1 clk_cpu_est_11_0_1_3__n N_132 clk_cpu_est_11_0_1_1__n N_131 \ -# clk_cpu_est_11_0_2_1__n N_124 N_167_1 clk_cpu_est_11_3__n N_167_2 N_135 N_167_3 N_133 \ -# N_167_4 N_134 N_167_5 clk_cpu_est_11_1__n N_167_6 N_130 N_170_1 N_128 N_170_2 N_145 \ -# N_107_1 N_127 state_machine_un42_clk_030_1_n N_129 state_machine_un42_clk_030_2_n \ -# N_126 state_machine_un42_clk_030_3_n N_125 state_machine_un42_clk_030_4_n N_92 \ -# state_machine_un42_clk_030_5_n N_91 DTACK_SYNC_1_sqmuxa_1_0 N_110 \ -# VPA_SYNC_1_sqmuxa_1_1 N_103 VPA_SYNC_1_sqmuxa_2 N_101 VPA_SYNC_1_sqmuxa_3 N_100 \ -# VPA_SYNC_1_sqmuxa_4 N_112 N_98_1 N_99 state_machine_as_030_000_sync_3_0_1_n \ -# state_machine_lds_000_int_8_n UDS_000_INT_0_sqmuxa_1_0 \ -# state_machine_uds_000_int_8_n UDS_000_INT_0_sqmuxa_2 un2_clk_030_1 \ -# state_machine_un13_clk_000_d_1_0_n VMA_INT_1_sqmuxa \ -# state_machine_un13_clk_000_d_4_1_n RW_i state_machine_un8_clk_000_d_1_n \ -# cpu_est_d_i_3__n state_machine_un8_clk_000_d_2_n cpu_est_d_i_0__n \ -# state_machine_un8_clk_000_d_3_n CLK_000_D_i state_machine_un8_clk_000_d_4_n \ -# AS_000_INT_i UDS_000_INT_0_sqmuxa_1_1 dsack_i_1__n UDS_000_INT_0_sqmuxa_1_2 \ -# state_machine_un13_clk_000_d_i_n UDS_000_INT_0_sqmuxa_1_3 \ -# state_machine_un8_clk_000_d_i_n N_132_1 AS_030_i N_131_1 sm_amiga_i_6__n \ -# vma_int_0_un3_n sm_amiga_i_7__n vma_int_0_un1_n sm_amiga_i_5__n vma_int_0_un0_n \ -# sm_amiga_i_4__n lds_000_int_0_un3_n state_machine_un13_clk_000_d_1_i_n \ -# lds_000_int_0_un1_n CLK_000_DD_i lds_000_int_0_un0_n AS_030_000_SYNC_i \ -# uds_000_int_0_un3_n cpu_est_i_0__n uds_000_int_0_un1_n cpu_est_i_2__n \ -# uds_000_int_0_un0_n cpu_est_i_3__n cpu_est_0_3__un3_n cpu_est_i_1__n \ -# cpu_est_0_3__un1_n UDS_000_INT_0_sqmuxa_1_i cpu_est_0_3__un0_n \ -# UDS_000_INT_0_sqmuxa_i cpu_est_0_2__un3_n DS_030_i cpu_est_0_2__un1_n VPA_D_i \ -# cpu_est_0_2__un0_n state_machine_un42_clk_030_i_n cpu_est_0_1__un3_n \ -# VPA_SYNC_1_sqmuxa_i cpu_est_0_1__un1_n N_102_i cpu_est_0_1__un0_n \ -# DTACK_SYNC_1_sqmuxa_i fpu_cs_int_0_un3_n N_98_i fpu_cs_int_0_un1_n a_i_18__n \ -# fpu_cs_int_0_un0_n a_i_16__n as_000_int_0_un3_n a_i_19__n as_000_int_0_un1_n \ -# CLK_030_i as_000_int_0_un0_n VMA_INT_i vpa_sync_0_un3_n DTACK_i vpa_sync_0_un1_n \ -# sm_amiga_i_3__n vpa_sync_0_un0_n sm_amiga_i_1__n as_030_000_sync_0_un3_n \ -# sm_amiga_i_2__n as_030_000_sync_0_un1_n a_i_30__n as_030_000_sync_0_un0_n \ -# a_i_31__n ipl_030_0_2__un3_n a_i_28__n ipl_030_0_2__un1_n a_i_29__n \ -# ipl_030_0_2__un0_n a_i_26__n ipl_030_0_1__un3_n a_i_27__n ipl_030_0_1__un1_n \ -# a_i_24__n ipl_030_0_1__un0_n a_i_25__n ipl_030_0_0__un3_n ipl_030_0_0__un1_n \ -# ipl_030_0_0__un0_n RST_i bgack_030_int_0_un3_n FPU_CS_INT_i bgack_030_int_0_un1_n \ -# CPU_SPACE_i bgack_030_int_0_un0_n BGACK_030_INT_i dsack_int_0_1__un3_n AS_030_c \ -# dsack_int_0_1__un1_n dsack_int_0_1__un0_n bg_000_0_un3_n DS_030_c bg_000_0_un1_n \ -# bg_000_0_un0_n dtack_sync_0_un3_n dtack_sync_0_un1_n size_c_0__n \ -# dtack_sync_0_un0_n a_15__n size_c_1__n a_14__n a_c_0__n a_13__n a_12__n a_11__n \ -# a_10__n a_9__n a_8__n a_7__n a_6__n a_c_16__n a_5__n a_c_17__n a_4__n a_c_18__n a_3__n \ -# a_c_19__n a_2__n a_c_20__n a_1__n a_c_21__n a_c_22__n a_c_23__n a_c_24__n a_c_25__n \ -# a_c_26__n a_c_27__n a_c_28__n a_c_29__n a_c_30__n a_c_31__n CPU_SPACE_c BG_030_c \ -# BG_000DFFSHreg BGACK_000_c CLK_030_c CLK_000_c +#$ PINS 74 A_21_ A_20_ SIZE_1_ A_19_ A_18_ A_31_ A_17_ A_16_ IPL_030_2_ A_15_ A_14_ \ +# IPL_2_ A_13_ A_12_ DSACK_1_ A_11_ A_10_ FC_1_ A_9_ AS_030 A_8_ AS_000 A_7_ DS_030 A_6_ \ +# UDS_000 A_5_ LDS_000 A_4_ CPU_SPACE A_3_ BERR A_2_ BG_030 A_1_ BG_000 A_0_ BGACK_030 \ +# IPL_030_1_ BGACK_000 IPL_030_0_ CLK_030 IPL_1_ CLK_000 IPL_0_ CLK_OSZI DSACK_0_ \ +# CLK_DIV_OUT FC_0_ CLK_EXP FPU_CS DTACK AVEC AVEC_EXP E VPA VMA RST RESET RW \ +# AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ \ +# A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ +#$ NODES 344 IPL_030DFFSH_1_reg IPL_030DFFSH_2_reg ipl_c_0__n ipl_c_1__n \ +# inst_BGACK_030_INTreg inst_FPU_CS_INTreg ipl_c_2__n cpu_est_3_reg inst_VMA_INTreg \ +# gnd_n_n dsack_c_1__n cpu_est_0_ cpu_est_1_ DTACK_c inst_AS_000_INTreg \ +# inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D \ +# inst_CLK_000_DD inst_CLK_OUT_PRE RST_c vcc_n_n cpu_est_2_ RESETDFFreg CLK_CNT_0_ \ +# SM_AMIGA_6_ RW_c SM_AMIGA_7_ inst_UDS_000_INTreg fc_c_0__n inst_LDS_000_INTreg \ +# state_machine_un1_clk_030_n fc_c_1__n SM_AMIGA_1_ DSACK_INT_1_ inst_DTACK_DMA \ +# SM_AMIGA_4_ state_machine_un6_bgack_000_n SM_AMIGA_3_ N_99_i \ +# state_machine_un13_as_000_int_n un1_bg_030 N_101_i SM_AMIGA_5_ sm_amiga_ns_0_2__n \ +# SM_AMIGA_2_ N_107_i SM_AMIGA_0_ N_106_i sm_amiga_ns_0_5__n N_108_i N_109_i N_110_i \ +# sm_amiga_ns_0_7__n N_91_0 CLK_OUT_PRE_i N_94_0 state_machine_un8_clk_000_d_i_n \ +# state_machine_un13_clk_000_d_i_n cpu_est_0_0_ state_machine_un15_clk_000_d_0_n \ +# N_93_0 N_104_i N_105_i N_103_i CLK_OUT_PRE_0 state_machine_un60_clk_000_d_i_n \ +# state_machine_un17_clk_030_0_n un1_as_030_3_0 N_145_i clk_un4_clk_000_dd_n \ +# a_c_i_0__n clk_cpu_est_11_1__n state_machine_uds_000_int_8_0_n \ +# state_machine_un42_clk_030_n state_machine_lds_000_int_8_0_n N_102 \ +# state_machine_as_030_000_sync_3_2_n N_98 size_c_i_1__n N_97 \ +# state_machine_un34_clk_000_d_i_n N_100 N_131_i N_92 N_132_i N_112 N_122_i N_127 \ +# N_125_i N_125 N_126_i N_128 N_134_i N_129 N_133_i N_130 N_135_i N_168 \ +# clk_cpu_est_11_0_3__n N_171 N_130_i N_135_1 clk_cpu_est_11_0_1__n \ +# state_machine_un13_clk_000_d_2_n N_128_i clk_cpu_est_11_3__n un1_bg_030_0 N_135 \ +# N_97_i N_133 BG_030_c_i N_134 N_127_i N_132 N_129_i N_131 N_92_0 N_126 N_100_i \ +# state_machine_un34_clk_000_d_n N_112_i UDS_000_INT_0_sqmuxa \ +# UDS_000_INT_0_sqmuxa_1 clk_un4_clk_000_dd_i_n state_machine_as_030_000_sync_3_n \ +# state_machine_un6_bgack_000_0_n N_145 state_machine_un1_clk_030_0_n \ +# state_machine_lds_000_int_8_n clk_cpu_est_11_0_1_3__n \ +# state_machine_uds_000_int_8_n state_machine_un34_clk_000_d_i_1_n un1_as_030_4 \ +# state_machine_as_030_000_sync_3_2_1_n un1_as_030_3 N_168_1 DSACK_INT_1_sqmuxa \ +# N_168_2 state_machine_un17_clk_030_n N_168_3 state_machine_un60_clk_000_d_n \ +# N_168_4 DTACK_SYNC_1_sqmuxa N_168_5 DTACK_SYNC_1_sqmuxa_1 N_168_6 VPA_SYNC_1_sqmuxa \ +# N_171_1 VPA_SYNC_1_sqmuxa_1 N_171_2 N_103 un1_bg_030_0_1 N_104 un1_bg_030_0_2 N_93 \ +# clk_cpu_est_11_0_1_1__n N_105 clk_cpu_est_11_0_2_1__n VPA_SYNC_1_sqmuxa_1_0 \ +# state_machine_un42_clk_030_1_n state_machine_un15_clk_000_d_n \ +# state_machine_un42_clk_030_2_n state_machine_un13_clk_000_d_n \ +# state_machine_un42_clk_030_3_n state_machine_un8_clk_000_d_n \ +# state_machine_un42_clk_030_4_n state_machine_un8_clk_000_d_1_n \ +# state_machine_un42_clk_030_5_n state_machine_un13_clk_000_d_1_n N_132_1 N_107 \ +# N_131_1 N_94 UDS_000_INT_0_sqmuxa_1_0 N_91 UDS_000_INT_0_sqmuxa_2 N_110 \ +# UDS_000_INT_0_sqmuxa_1_1 N_108 UDS_000_INT_0_sqmuxa_1_2 N_109 \ +# UDS_000_INT_0_sqmuxa_1_3 N_106 DTACK_SYNC_1_sqmuxa_1_0 N_101 \ +# state_machine_un8_clk_000_d_1_0_n N_99 state_machine_un8_clk_000_d_2_n \ +# AS_000_INT_1_sqmuxa state_machine_un8_clk_000_d_3_n RW_i \ +# state_machine_un13_clk_000_d_1_0_n N_102_i state_machine_un13_clk_000_d_2_0_n \ +# AS_000_INT_i VPA_SYNC_1_sqmuxa_1_1 dsack_i_1__n VPA_SYNC_1_sqmuxa_2 AS_030_i \ +# VPA_SYNC_1_sqmuxa_3 sm_amiga_i_7__n VPA_SYNC_1_sqmuxa_4 CLK_000_D_i N_107_1 \ +# sm_amiga_i_2__n N_98_1 sm_amiga_i_1__n as_000_int_0_un3_n \ +# state_machine_un13_clk_000_d_1_i_n as_000_int_0_un1_n VPA_D_i as_000_int_0_un0_n \ +# VMA_INT_i vma_int_0_un3_n cpu_est_i_0__n vma_int_0_un1_n cpu_est_i_1__n \ +# vma_int_0_un0_n cpu_est_i_3__n uds_000_int_0_un3_n \ +# state_machine_un8_clk_000_d_1_i_0_n uds_000_int_0_un1_n DTACK_i \ +# uds_000_int_0_un0_n sm_amiga_i_3__n dtack_sync_0_un3_n sm_amiga_i_4__n \ +# dtack_sync_0_un1_n sm_amiga_i_5__n dtack_sync_0_un0_n DTACK_SYNC_1_sqmuxa_i \ +# vpa_sync_0_un3_n VPA_SYNC_1_sqmuxa_i vpa_sync_0_un1_n N_98_i vpa_sync_0_un0_n \ +# state_machine_un42_clk_030_i_n dsack_int_0_1__un3_n UDS_000_INT_0_sqmuxa_1_i \ +# dsack_int_0_1__un1_n UDS_000_INT_0_sqmuxa_i dsack_int_0_1__un0_n \ +# AS_030_000_SYNC_i as_030_000_sync_0_un3_n DS_030_i as_030_000_sync_0_un1_n \ +# cpu_est_i_2__n as_030_000_sync_0_un0_n state_machine_un13_clk_000_d_2_i_n \ +# fpu_cs_int_0_un3_n CLK_000_DD_i fpu_cs_int_0_un1_n sm_amiga_i_6__n \ +# fpu_cs_int_0_un0_n CLK_030_i lds_000_int_0_un3_n a_i_30__n lds_000_int_0_un1_n \ +# a_i_31__n lds_000_int_0_un0_n a_i_28__n cpu_est_0_3__un3_n a_i_29__n \ +# cpu_est_0_3__un1_n a_i_26__n cpu_est_0_3__un0_n a_i_27__n cpu_est_0_2__un3_n \ +# a_i_24__n cpu_est_0_2__un1_n a_i_25__n cpu_est_0_2__un0_n a_i_19__n bg_000_0_un3_n \ +# a_i_16__n bg_000_0_un1_n a_i_18__n bg_000_0_un0_n bgack_030_int_0_un3_n RST_i \ +# bgack_030_int_0_un1_n bgack_030_int_0_un0_n FPU_CS_INT_i cpu_est_0_1__un3_n \ +# CPU_SPACE_i cpu_est_0_1__un1_n BGACK_030_INT_i cpu_est_0_1__un0_n AS_030_c \ +# ipl_030_0_0__un3_n ipl_030_0_0__un1_n ipl_030_0_0__un0_n DS_030_c \ +# ipl_030_0_1__un3_n ipl_030_0_1__un1_n ipl_030_0_1__un0_n ipl_030_0_2__un3_n \ +# size_c_0__n ipl_030_0_2__un1_n ipl_030_0_2__un0_n size_c_1__n a_15__n a_c_0__n \ +# a_14__n a_13__n a_12__n a_11__n a_10__n a_9__n a_8__n a_7__n a_6__n a_c_16__n a_5__n \ +# a_c_17__n a_4__n a_c_18__n a_3__n a_c_19__n a_2__n a_c_20__n a_1__n a_c_21__n a_c_22__n \ +# a_c_23__n a_c_24__n a_c_25__n a_c_26__n a_c_27__n a_c_28__n a_c_29__n a_c_30__n \ +# a_c_31__n CPU_SPACE_c BG_030_c BG_000DFFSHreg BGACK_000_c CLK_030_c CLK_OSZI_c \ +# CLK_OUT_INTreg IPL_030DFFSH_0_reg .model bus68030 .inputs SIZE_1_.BLIF A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF AS_030.BLIF DS_030.BLIF \ CPU_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF \ @@ -89,219 +90,208 @@ A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF A_15_.BLIF \ A_14_.BLIF A_13_.BLIF A_12_.BLIF A_11_.BLIF A_10_.BLIF A_9_.BLIF A_8_.BLIF \ A_7_.BLIF A_6_.BLIF A_5_.BLIF A_4_.BLIF A_3_.BLIF A_2_.BLIF A_1_.BLIF \ A_0_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF DSACK_1_.BLIF DTACK.BLIF \ -DSACK_0_.BLIF CLK_OSZI_c.BLIF CLK_OUT_INTreg.BLIF IPL_030DFFSH_0_reg.BLIF \ -inst_BGACK_030_INTreg.BLIF inst_FPU_CS_INTreg.BLIF IPL_030DFFSH_1_reg.BLIF \ -cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF IPL_030DFFSH_2_reg.BLIF gnd_n_n.BLIF \ -cpu_est_0_.BLIF ipl_c_0__n.BLIF cpu_est_1_.BLIF cpu_est_d_0_.BLIF \ -ipl_c_1__n.BLIF cpu_est_d_3_.BLIF inst_AS_000_INTreg.BLIF ipl_c_2__n.BLIF \ -inst_AS_030_000_SYNC.BLIF inst_DTACK_SYNC.BLIF inst_VPA_D.BLIF \ -dsack_c_1__n.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D.BLIF DTACK_c.BLIF \ -inst_CLK_000_DD.BLIF inst_CLK_OUT_PRE.BLIF vcc_n_n.BLIF cpu_est_d_1_.BLIF \ -cpu_est_d_2_.BLIF cpu_est_2_.BLIF CLK_CNT_0_.BLIF SM_AMIGA_6_.BLIF RST_c.BLIF \ -SM_AMIGA_7_.BLIF inst_UDS_000_INTreg.BLIF RESETDFFreg.BLIF \ -inst_LDS_000_INTreg.BLIF RW_c.BLIF inst_RISING_CLK_AMIGA.BLIF \ -state_machine_un57_clk_000_d_n.BLIF fc_c_0__n.BLIF SM_AMIGA_1_.BLIF \ -DSACK_INT_1_.BLIF fc_c_1__n.BLIF inst_DTACK_DMA.BLIF SM_AMIGA_4_.BLIF \ -SM_AMIGA_3_.BLIF state_machine_un13_as_000_int_n.BLIF SM_AMIGA_5_.BLIF \ -SM_AMIGA_2_.BLIF N_145_i.BLIF SM_AMIGA_0_.BLIF a_c_i_0__n.BLIF \ -state_machine_uds_000_int_8_0_n.BLIF state_machine_lds_000_int_8_0_n.BLIF \ -N_99_i.BLIF N_112_i.BLIF N_100_i.BLIF N_101_i.BLIF sm_amiga_ns_0_2__n.BLIF \ -N_103_i.BLIF N_110_i.BLIF sm_amiga_ns_0_7__n.BLIF cpu_est_0_0_.BLIF \ -N_91_0.BLIF N_92_0.BLIF N_131_i.BLIF N_132_i.BLIF N_122_i.BLIF \ -CLK_OUT_PRE_0.BLIF N_124_i.BLIF N_125_i.BLIF N_126_i.BLIF N_129_i.BLIF \ -N_98.BLIF N_127_i.BLIF N_97.BLIF N_128_i.BLIF N_104.BLIF N_130_i.BLIF \ -N_93.BLIF clk_cpu_est_11_0_1__n.BLIF N_105.BLIF N_134_i.BLIF N_106.BLIF \ -N_133_i.BLIF N_108.BLIF N_135_i.BLIF N_94.BLIF clk_cpu_est_11_0_3__n.BLIF \ -N_109.BLIF size_c_i_1__n.BLIF N_107.BLIF state_machine_un31_clk_000_d_i_n.BLIF \ -N_135_1.BLIF state_machine_as_030_000_sync_3_0_n.BLIF \ -VPA_SYNC_1_sqmuxa_1_0.BLIF un1_as_030_2_0.BLIF N_167.BLIF \ -state_machine_un17_clk_030_0_n.BLIF N_170.BLIF \ -state_machine_un57_clk_000_d_0_n.BLIF state_machine_un42_clk_030_n.BLIF \ -RISING_CLK_AMIGA_i.BLIF DTACK_SYNC_1_sqmuxa.BLIF \ -state_machine_un4_bgack_000_0_n.BLIF VPA_SYNC_1_sqmuxa.BLIF BG_030_c_i.BLIF \ -un1_bg_030.BLIF state_machine_un1_clk_030_0_n.BLIF DTACK_SYNC_1_sqmuxa_1.BLIF \ -N_97_i.BLIF DSACK_INT_1_sqmuxa.BLIF un1_bg_030_0.BLIF \ -state_machine_un1_clk_030_n.BLIF CLK_OUT_PRE_i.BLIF \ -state_machine_un4_bgack_000_n.BLIF N_94_0.BLIF un1_as_030_2.BLIF N_93_0.BLIF \ -state_machine_un17_clk_030_n.BLIF N_108_i.BLIF N_102.BLIF N_109_i.BLIF \ -AS_000_INT_1_sqmuxa.BLIF VPA_SYNC_1_sqmuxa_1.BLIF N_106_i.BLIF \ -state_machine_as_030_000_sync_3_n.BLIF N_107_i.BLIF clk_un3_clk_000_dd_n.BLIF \ -sm_amiga_ns_0_5__n.BLIF state_machine_un31_clk_000_d_n.BLIF N_104_i.BLIF \ -UDS_000_INT_0_sqmuxa.BLIF N_105_i.BLIF state_machine_un13_clk_000_d_n.BLIF \ -state_machine_un13_clk_000_d_4_n.BLIF un1_bg_030_0_1.BLIF \ -state_machine_un13_clk_000_d_1_n.BLIF un1_bg_030_0_2.BLIF \ -state_machine_un8_clk_000_d_n.BLIF state_machine_un31_clk_000_d_i_1_n.BLIF \ -UDS_000_INT_0_sqmuxa_1.BLIF clk_cpu_est_11_0_1_3__n.BLIF N_132.BLIF \ -clk_cpu_est_11_0_1_1__n.BLIF N_131.BLIF clk_cpu_est_11_0_2_1__n.BLIF \ -N_124.BLIF N_167_1.BLIF clk_cpu_est_11_3__n.BLIF N_167_2.BLIF N_135.BLIF \ -N_167_3.BLIF N_133.BLIF N_167_4.BLIF N_134.BLIF N_167_5.BLIF \ -clk_cpu_est_11_1__n.BLIF N_167_6.BLIF N_130.BLIF N_170_1.BLIF N_128.BLIF \ -N_170_2.BLIF N_145.BLIF N_107_1.BLIF N_127.BLIF \ -state_machine_un42_clk_030_1_n.BLIF N_129.BLIF \ -state_machine_un42_clk_030_2_n.BLIF N_126.BLIF \ -state_machine_un42_clk_030_3_n.BLIF N_125.BLIF \ -state_machine_un42_clk_030_4_n.BLIF N_92.BLIF \ -state_machine_un42_clk_030_5_n.BLIF N_91.BLIF DTACK_SYNC_1_sqmuxa_1_0.BLIF \ -N_110.BLIF VPA_SYNC_1_sqmuxa_1_1.BLIF N_103.BLIF VPA_SYNC_1_sqmuxa_2.BLIF \ -N_101.BLIF VPA_SYNC_1_sqmuxa_3.BLIF N_100.BLIF VPA_SYNC_1_sqmuxa_4.BLIF \ -N_112.BLIF N_98_1.BLIF N_99.BLIF state_machine_as_030_000_sync_3_0_1_n.BLIF \ -state_machine_lds_000_int_8_n.BLIF UDS_000_INT_0_sqmuxa_1_0.BLIF \ -state_machine_uds_000_int_8_n.BLIF UDS_000_INT_0_sqmuxa_2.BLIF \ -un2_clk_030_1.BLIF state_machine_un13_clk_000_d_1_0_n.BLIF \ -VMA_INT_1_sqmuxa.BLIF state_machine_un13_clk_000_d_4_1_n.BLIF RW_i.BLIF \ -state_machine_un8_clk_000_d_1_n.BLIF cpu_est_d_i_3__n.BLIF \ -state_machine_un8_clk_000_d_2_n.BLIF cpu_est_d_i_0__n.BLIF \ -state_machine_un8_clk_000_d_3_n.BLIF CLK_000_D_i.BLIF \ -state_machine_un8_clk_000_d_4_n.BLIF AS_000_INT_i.BLIF \ -UDS_000_INT_0_sqmuxa_1_1.BLIF dsack_i_1__n.BLIF UDS_000_INT_0_sqmuxa_1_2.BLIF \ -state_machine_un13_clk_000_d_i_n.BLIF UDS_000_INT_0_sqmuxa_1_3.BLIF \ -state_machine_un8_clk_000_d_i_n.BLIF N_132_1.BLIF AS_030_i.BLIF N_131_1.BLIF \ -sm_amiga_i_6__n.BLIF vma_int_0_un3_n.BLIF sm_amiga_i_7__n.BLIF \ -vma_int_0_un1_n.BLIF sm_amiga_i_5__n.BLIF vma_int_0_un0_n.BLIF \ -sm_amiga_i_4__n.BLIF lds_000_int_0_un3_n.BLIF \ -state_machine_un13_clk_000_d_1_i_n.BLIF lds_000_int_0_un1_n.BLIF \ -CLK_000_DD_i.BLIF lds_000_int_0_un0_n.BLIF AS_030_000_SYNC_i.BLIF \ -uds_000_int_0_un3_n.BLIF cpu_est_i_0__n.BLIF uds_000_int_0_un1_n.BLIF \ -cpu_est_i_2__n.BLIF uds_000_int_0_un0_n.BLIF cpu_est_i_3__n.BLIF \ -cpu_est_0_3__un3_n.BLIF cpu_est_i_1__n.BLIF cpu_est_0_3__un1_n.BLIF \ -UDS_000_INT_0_sqmuxa_1_i.BLIF cpu_est_0_3__un0_n.BLIF \ -UDS_000_INT_0_sqmuxa_i.BLIF cpu_est_0_2__un3_n.BLIF DS_030_i.BLIF \ -cpu_est_0_2__un1_n.BLIF VPA_D_i.BLIF cpu_est_0_2__un0_n.BLIF \ -state_machine_un42_clk_030_i_n.BLIF cpu_est_0_1__un3_n.BLIF \ -VPA_SYNC_1_sqmuxa_i.BLIF cpu_est_0_1__un1_n.BLIF N_102_i.BLIF \ -cpu_est_0_1__un0_n.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF fpu_cs_int_0_un3_n.BLIF \ -N_98_i.BLIF fpu_cs_int_0_un1_n.BLIF a_i_18__n.BLIF fpu_cs_int_0_un0_n.BLIF \ -a_i_16__n.BLIF as_000_int_0_un3_n.BLIF a_i_19__n.BLIF as_000_int_0_un1_n.BLIF \ -CLK_030_i.BLIF as_000_int_0_un0_n.BLIF VMA_INT_i.BLIF vpa_sync_0_un3_n.BLIF \ -DTACK_i.BLIF vpa_sync_0_un1_n.BLIF sm_amiga_i_3__n.BLIF vpa_sync_0_un0_n.BLIF \ -sm_amiga_i_1__n.BLIF as_030_000_sync_0_un3_n.BLIF sm_amiga_i_2__n.BLIF \ -as_030_000_sync_0_un1_n.BLIF a_i_30__n.BLIF as_030_000_sync_0_un0_n.BLIF \ -a_i_31__n.BLIF ipl_030_0_2__un3_n.BLIF a_i_28__n.BLIF ipl_030_0_2__un1_n.BLIF \ -a_i_29__n.BLIF ipl_030_0_2__un0_n.BLIF a_i_26__n.BLIF ipl_030_0_1__un3_n.BLIF \ -a_i_27__n.BLIF ipl_030_0_1__un1_n.BLIF a_i_24__n.BLIF ipl_030_0_1__un0_n.BLIF \ -a_i_25__n.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un1_n.BLIF \ -ipl_030_0_0__un0_n.BLIF RST_i.BLIF bgack_030_int_0_un3_n.BLIF \ -FPU_CS_INT_i.BLIF bgack_030_int_0_un1_n.BLIF CPU_SPACE_i.BLIF \ -bgack_030_int_0_un0_n.BLIF BGACK_030_INT_i.BLIF dsack_int_0_1__un3_n.BLIF \ -AS_030_c.BLIF dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF \ -bg_000_0_un3_n.BLIF DS_030_c.BLIF bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF \ -dtack_sync_0_un3_n.BLIF dtack_sync_0_un1_n.BLIF size_c_0__n.BLIF \ -dtack_sync_0_un0_n.BLIF a_15__n.BLIF size_c_1__n.BLIF a_14__n.BLIF \ -a_c_0__n.BLIF a_13__n.BLIF a_12__n.BLIF a_11__n.BLIF a_10__n.BLIF a_9__n.BLIF \ +DSACK_0_.BLIF IPL_030DFFSH_1_reg.BLIF IPL_030DFFSH_2_reg.BLIF ipl_c_0__n.BLIF \ +ipl_c_1__n.BLIF inst_BGACK_030_INTreg.BLIF inst_FPU_CS_INTreg.BLIF \ +ipl_c_2__n.BLIF cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF gnd_n_n.BLIF \ +dsack_c_1__n.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF DTACK_c.BLIF \ +inst_AS_000_INTreg.BLIF inst_AS_030_000_SYNC.BLIF inst_DTACK_SYNC.BLIF \ +inst_VPA_D.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF \ +inst_CLK_OUT_PRE.BLIF RST_c.BLIF vcc_n_n.BLIF cpu_est_2_.BLIF RESETDFFreg.BLIF \ +CLK_CNT_0_.BLIF SM_AMIGA_6_.BLIF RW_c.BLIF SM_AMIGA_7_.BLIF \ +inst_UDS_000_INTreg.BLIF fc_c_0__n.BLIF inst_LDS_000_INTreg.BLIF \ +state_machine_un1_clk_030_n.BLIF fc_c_1__n.BLIF SM_AMIGA_1_.BLIF \ +DSACK_INT_1_.BLIF inst_DTACK_DMA.BLIF SM_AMIGA_4_.BLIF \ +state_machine_un6_bgack_000_n.BLIF SM_AMIGA_3_.BLIF N_99_i.BLIF \ +state_machine_un13_as_000_int_n.BLIF un1_bg_030.BLIF N_101_i.BLIF \ +SM_AMIGA_5_.BLIF sm_amiga_ns_0_2__n.BLIF SM_AMIGA_2_.BLIF N_107_i.BLIF \ +SM_AMIGA_0_.BLIF N_106_i.BLIF sm_amiga_ns_0_5__n.BLIF N_108_i.BLIF \ +N_109_i.BLIF N_110_i.BLIF sm_amiga_ns_0_7__n.BLIF N_91_0.BLIF \ +CLK_OUT_PRE_i.BLIF N_94_0.BLIF state_machine_un8_clk_000_d_i_n.BLIF \ +state_machine_un13_clk_000_d_i_n.BLIF cpu_est_0_0_.BLIF \ +state_machine_un15_clk_000_d_0_n.BLIF N_93_0.BLIF N_104_i.BLIF N_105_i.BLIF \ +N_103_i.BLIF CLK_OUT_PRE_0.BLIF state_machine_un60_clk_000_d_i_n.BLIF \ +state_machine_un17_clk_030_0_n.BLIF un1_as_030_3_0.BLIF N_145_i.BLIF \ +clk_un4_clk_000_dd_n.BLIF a_c_i_0__n.BLIF clk_cpu_est_11_1__n.BLIF \ +state_machine_uds_000_int_8_0_n.BLIF state_machine_un42_clk_030_n.BLIF \ +state_machine_lds_000_int_8_0_n.BLIF N_102.BLIF \ +state_machine_as_030_000_sync_3_2_n.BLIF N_98.BLIF size_c_i_1__n.BLIF \ +N_97.BLIF state_machine_un34_clk_000_d_i_n.BLIF N_100.BLIF N_131_i.BLIF \ +N_92.BLIF N_132_i.BLIF N_112.BLIF N_122_i.BLIF N_127.BLIF N_125_i.BLIF \ +N_125.BLIF N_126_i.BLIF N_128.BLIF N_134_i.BLIF N_129.BLIF N_133_i.BLIF \ +N_130.BLIF N_135_i.BLIF N_168.BLIF clk_cpu_est_11_0_3__n.BLIF N_171.BLIF \ +N_130_i.BLIF N_135_1.BLIF clk_cpu_est_11_0_1__n.BLIF \ +state_machine_un13_clk_000_d_2_n.BLIF N_128_i.BLIF clk_cpu_est_11_3__n.BLIF \ +un1_bg_030_0.BLIF N_135.BLIF N_97_i.BLIF N_133.BLIF BG_030_c_i.BLIF N_134.BLIF \ +N_127_i.BLIF N_132.BLIF N_129_i.BLIF N_131.BLIF N_92_0.BLIF N_126.BLIF \ +N_100_i.BLIF state_machine_un34_clk_000_d_n.BLIF N_112_i.BLIF \ +UDS_000_INT_0_sqmuxa.BLIF UDS_000_INT_0_sqmuxa_1.BLIF \ +clk_un4_clk_000_dd_i_n.BLIF state_machine_as_030_000_sync_3_n.BLIF \ +state_machine_un6_bgack_000_0_n.BLIF N_145.BLIF \ +state_machine_un1_clk_030_0_n.BLIF state_machine_lds_000_int_8_n.BLIF \ +clk_cpu_est_11_0_1_3__n.BLIF state_machine_uds_000_int_8_n.BLIF \ +state_machine_un34_clk_000_d_i_1_n.BLIF un1_as_030_4.BLIF \ +state_machine_as_030_000_sync_3_2_1_n.BLIF un1_as_030_3.BLIF N_168_1.BLIF \ +DSACK_INT_1_sqmuxa.BLIF N_168_2.BLIF state_machine_un17_clk_030_n.BLIF \ +N_168_3.BLIF state_machine_un60_clk_000_d_n.BLIF N_168_4.BLIF \ +DTACK_SYNC_1_sqmuxa.BLIF N_168_5.BLIF DTACK_SYNC_1_sqmuxa_1.BLIF N_168_6.BLIF \ +VPA_SYNC_1_sqmuxa.BLIF N_171_1.BLIF VPA_SYNC_1_sqmuxa_1.BLIF N_171_2.BLIF \ +N_103.BLIF un1_bg_030_0_1.BLIF N_104.BLIF un1_bg_030_0_2.BLIF N_93.BLIF \ +clk_cpu_est_11_0_1_1__n.BLIF N_105.BLIF clk_cpu_est_11_0_2_1__n.BLIF \ +VPA_SYNC_1_sqmuxa_1_0.BLIF state_machine_un42_clk_030_1_n.BLIF \ +state_machine_un15_clk_000_d_n.BLIF state_machine_un42_clk_030_2_n.BLIF \ +state_machine_un13_clk_000_d_n.BLIF state_machine_un42_clk_030_3_n.BLIF \ +state_machine_un8_clk_000_d_n.BLIF state_machine_un42_clk_030_4_n.BLIF \ +state_machine_un8_clk_000_d_1_n.BLIF state_machine_un42_clk_030_5_n.BLIF \ +state_machine_un13_clk_000_d_1_n.BLIF N_132_1.BLIF N_107.BLIF N_131_1.BLIF \ +N_94.BLIF UDS_000_INT_0_sqmuxa_1_0.BLIF N_91.BLIF UDS_000_INT_0_sqmuxa_2.BLIF \ +N_110.BLIF UDS_000_INT_0_sqmuxa_1_1.BLIF N_108.BLIF \ +UDS_000_INT_0_sqmuxa_1_2.BLIF N_109.BLIF UDS_000_INT_0_sqmuxa_1_3.BLIF \ +N_106.BLIF DTACK_SYNC_1_sqmuxa_1_0.BLIF N_101.BLIF \ +state_machine_un8_clk_000_d_1_0_n.BLIF N_99.BLIF \ +state_machine_un8_clk_000_d_2_n.BLIF AS_000_INT_1_sqmuxa.BLIF \ +state_machine_un8_clk_000_d_3_n.BLIF RW_i.BLIF \ +state_machine_un13_clk_000_d_1_0_n.BLIF N_102_i.BLIF \ +state_machine_un13_clk_000_d_2_0_n.BLIF AS_000_INT_i.BLIF \ +VPA_SYNC_1_sqmuxa_1_1.BLIF dsack_i_1__n.BLIF VPA_SYNC_1_sqmuxa_2.BLIF \ +AS_030_i.BLIF VPA_SYNC_1_sqmuxa_3.BLIF sm_amiga_i_7__n.BLIF \ +VPA_SYNC_1_sqmuxa_4.BLIF CLK_000_D_i.BLIF N_107_1.BLIF sm_amiga_i_2__n.BLIF \ +N_98_1.BLIF sm_amiga_i_1__n.BLIF as_000_int_0_un3_n.BLIF \ +state_machine_un13_clk_000_d_1_i_n.BLIF as_000_int_0_un1_n.BLIF VPA_D_i.BLIF \ +as_000_int_0_un0_n.BLIF VMA_INT_i.BLIF vma_int_0_un3_n.BLIF \ +cpu_est_i_0__n.BLIF vma_int_0_un1_n.BLIF cpu_est_i_1__n.BLIF \ +vma_int_0_un0_n.BLIF cpu_est_i_3__n.BLIF uds_000_int_0_un3_n.BLIF \ +state_machine_un8_clk_000_d_1_i_0_n.BLIF uds_000_int_0_un1_n.BLIF DTACK_i.BLIF \ +uds_000_int_0_un0_n.BLIF sm_amiga_i_3__n.BLIF dtack_sync_0_un3_n.BLIF \ +sm_amiga_i_4__n.BLIF dtack_sync_0_un1_n.BLIF sm_amiga_i_5__n.BLIF \ +dtack_sync_0_un0_n.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF vpa_sync_0_un3_n.BLIF \ +VPA_SYNC_1_sqmuxa_i.BLIF vpa_sync_0_un1_n.BLIF N_98_i.BLIF \ +vpa_sync_0_un0_n.BLIF state_machine_un42_clk_030_i_n.BLIF \ +dsack_int_0_1__un3_n.BLIF UDS_000_INT_0_sqmuxa_1_i.BLIF \ +dsack_int_0_1__un1_n.BLIF UDS_000_INT_0_sqmuxa_i.BLIF \ +dsack_int_0_1__un0_n.BLIF AS_030_000_SYNC_i.BLIF as_030_000_sync_0_un3_n.BLIF \ +DS_030_i.BLIF as_030_000_sync_0_un1_n.BLIF cpu_est_i_2__n.BLIF \ +as_030_000_sync_0_un0_n.BLIF state_machine_un13_clk_000_d_2_i_n.BLIF \ +fpu_cs_int_0_un3_n.BLIF CLK_000_DD_i.BLIF fpu_cs_int_0_un1_n.BLIF \ +sm_amiga_i_6__n.BLIF fpu_cs_int_0_un0_n.BLIF CLK_030_i.BLIF \ +lds_000_int_0_un3_n.BLIF a_i_30__n.BLIF lds_000_int_0_un1_n.BLIF \ +a_i_31__n.BLIF lds_000_int_0_un0_n.BLIF a_i_28__n.BLIF cpu_est_0_3__un3_n.BLIF \ +a_i_29__n.BLIF cpu_est_0_3__un1_n.BLIF a_i_26__n.BLIF cpu_est_0_3__un0_n.BLIF \ +a_i_27__n.BLIF cpu_est_0_2__un3_n.BLIF a_i_24__n.BLIF cpu_est_0_2__un1_n.BLIF \ +a_i_25__n.BLIF cpu_est_0_2__un0_n.BLIF a_i_19__n.BLIF bg_000_0_un3_n.BLIF \ +a_i_16__n.BLIF bg_000_0_un1_n.BLIF a_i_18__n.BLIF bg_000_0_un0_n.BLIF \ +bgack_030_int_0_un3_n.BLIF RST_i.BLIF bgack_030_int_0_un1_n.BLIF \ +bgack_030_int_0_un0_n.BLIF FPU_CS_INT_i.BLIF cpu_est_0_1__un3_n.BLIF \ +CPU_SPACE_i.BLIF cpu_est_0_1__un1_n.BLIF BGACK_030_INT_i.BLIF \ +cpu_est_0_1__un0_n.BLIF AS_030_c.BLIF ipl_030_0_0__un3_n.BLIF \ +ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF DS_030_c.BLIF \ +ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF \ +ipl_030_0_2__un3_n.BLIF size_c_0__n.BLIF ipl_030_0_2__un1_n.BLIF \ +ipl_030_0_2__un0_n.BLIF size_c_1__n.BLIF a_15__n.BLIF a_c_0__n.BLIF \ +a_14__n.BLIF a_13__n.BLIF a_12__n.BLIF a_11__n.BLIF a_10__n.BLIF a_9__n.BLIF \ a_8__n.BLIF a_7__n.BLIF a_6__n.BLIF a_c_16__n.BLIF a_5__n.BLIF a_c_17__n.BLIF \ a_4__n.BLIF a_c_18__n.BLIF a_3__n.BLIF a_c_19__n.BLIF a_2__n.BLIF \ a_c_20__n.BLIF a_1__n.BLIF a_c_21__n.BLIF a_c_22__n.BLIF a_c_23__n.BLIF \ a_c_24__n.BLIF a_c_25__n.BLIF a_c_26__n.BLIF a_c_27__n.BLIF a_c_28__n.BLIF \ a_c_29__n.BLIF a_c_30__n.BLIF a_c_31__n.BLIF CPU_SPACE_c.BLIF BG_030_c.BLIF \ -BG_000DFFSHreg.BLIF BGACK_000_c.BLIF CLK_030_c.BLIF CLK_000_c.BLIF \ -DSACK_1_.PIN.BLIF DTACK.PIN.BLIF +BG_000DFFSHreg.BLIF BGACK_000_c.BLIF CLK_030_c.BLIF CLK_OSZI_c.BLIF \ +CLK_OUT_INTreg.BLIF IPL_030DFFSH_0_reg.BLIF DSACK_1_.PIN.BLIF DTACK.PIN.BLIF .outputs IPL_030_2_ AS_000 UDS_000 LDS_000 BERR BG_000 BGACK_030 CLK_DIV_OUT \ CLK_EXP FPU_CS AVEC AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR \ -AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ cpu_est_3_reg.D \ -cpu_est_3_reg.C SM_AMIGA_7_.D SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.D \ -SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR \ -SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C \ +AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_3_.D SM_AMIGA_3_.C \ SM_AMIGA_3_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D \ SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR \ -cpu_est_d_0_.D cpu_est_d_0_.C cpu_est_d_1_.D cpu_est_d_1_.C cpu_est_d_2_.D \ -cpu_est_d_2_.C cpu_est_d_3_.D cpu_est_d_3_.C IPL_030DFFSH_0_reg.D \ -IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP IPL_030DFFSH_1_reg.D \ -IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D \ -IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP cpu_est_0_.D cpu_est_0_.C \ -cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C inst_VPA_SYNC.D \ -inst_VPA_SYNC.C inst_VPA_SYNC.AP inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \ -inst_AS_030_000_SYNC.AP inst_VMA_INTreg.D inst_VMA_INTreg.C inst_VMA_INTreg.AP \ -BG_000DFFSHreg.D BG_000DFFSHreg.C BG_000DFFSHreg.AP DSACK_INT_1_.D \ -DSACK_INT_1_.C DSACK_INT_1_.AP inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C \ -inst_BGACK_030_INTreg.AP inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C \ -inst_UDS_000_INTreg.D inst_UDS_000_INTreg.C inst_UDS_000_INTreg.AP \ +IPL_030DFFSH_0_reg.D IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP \ +IPL_030DFFSH_1_reg.D IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP \ +IPL_030DFFSH_2_reg.D IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D \ +SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR \ +SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C \ +SM_AMIGA_4_.AR DSACK_INT_1_.D DSACK_INT_1_.C DSACK_INT_1_.AP inst_VMA_INTreg.D \ +inst_VMA_INTreg.C inst_VMA_INTreg.AP inst_BGACK_030_INTreg.D \ +inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP inst_CLK_OUT_PRE.D \ +inst_CLK_OUT_PRE.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C \ +cpu_est_2_.D cpu_est_2_.C cpu_est_3_reg.D cpu_est_3_reg.C \ inst_LDS_000_INTreg.D inst_LDS_000_INTreg.C inst_LDS_000_INTreg.AP \ inst_DTACK_SYNC.D inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_FPU_CS_INTreg.D \ -inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP inst_AS_000_INTreg.D \ -inst_AS_000_INTreg.C inst_AS_000_INTreg.AP inst_DTACK_DMA.D inst_DTACK_DMA.C \ -inst_DTACK_DMA.AP inst_RISING_CLK_AMIGA.D inst_RISING_CLK_AMIGA.C CLK_CNT_0_.D \ -CLK_CNT_0_.C inst_VPA_D.D inst_VPA_D.C inst_CLK_000_D.D inst_CLK_000_D.C \ -RESETDFFreg.D RESETDFFreg.C inst_CLK_000_DD.D inst_CLK_000_DD.C \ -CLK_OUT_INTreg.D CLK_OUT_INTreg.C DSACK_1_ DTACK DSACK_0_ CLK_OSZI_c gnd_n_n \ -ipl_c_0__n ipl_c_1__n ipl_c_2__n dsack_c_1__n DTACK_c vcc_n_n RST_c RW_c \ -state_machine_un57_clk_000_d_n fc_c_0__n fc_c_1__n \ -state_machine_un13_as_000_int_n N_145_i a_c_i_0__n \ -state_machine_uds_000_int_8_0_n state_machine_lds_000_int_8_0_n N_99_i N_112_i \ -N_100_i N_101_i sm_amiga_ns_0_2__n N_103_i N_110_i sm_amiga_ns_0_7__n N_91_0 \ -N_92_0 N_131_i N_132_i N_122_i N_124_i N_125_i N_126_i N_129_i N_98 N_127_i \ -N_97 N_128_i N_104 N_130_i N_93 clk_cpu_est_11_0_1__n N_105 N_134_i N_106 \ -N_133_i N_108 N_135_i N_94 clk_cpu_est_11_0_3__n N_109 size_c_i_1__n N_107 \ -state_machine_un31_clk_000_d_i_n N_135_1 state_machine_as_030_000_sync_3_0_n \ -VPA_SYNC_1_sqmuxa_1_0 un1_as_030_2_0 N_167 state_machine_un17_clk_030_0_n \ -N_170 state_machine_un57_clk_000_d_0_n state_machine_un42_clk_030_n \ -RISING_CLK_AMIGA_i DTACK_SYNC_1_sqmuxa state_machine_un4_bgack_000_0_n \ -VPA_SYNC_1_sqmuxa BG_030_c_i un1_bg_030 state_machine_un1_clk_030_0_n \ -DTACK_SYNC_1_sqmuxa_1 N_97_i DSACK_INT_1_sqmuxa un1_bg_030_0 \ -state_machine_un1_clk_030_n CLK_OUT_PRE_i state_machine_un4_bgack_000_n N_94_0 \ -un1_as_030_2 N_93_0 state_machine_un17_clk_030_n N_108_i N_102 N_109_i \ -AS_000_INT_1_sqmuxa VPA_SYNC_1_sqmuxa_1 N_106_i \ -state_machine_as_030_000_sync_3_n N_107_i clk_un3_clk_000_dd_n \ -sm_amiga_ns_0_5__n state_machine_un31_clk_000_d_n N_104_i UDS_000_INT_0_sqmuxa \ -N_105_i state_machine_un13_clk_000_d_n state_machine_un13_clk_000_d_4_n \ -un1_bg_030_0_1 state_machine_un13_clk_000_d_1_n un1_bg_030_0_2 \ -state_machine_un8_clk_000_d_n state_machine_un31_clk_000_d_i_1_n \ -UDS_000_INT_0_sqmuxa_1 clk_cpu_est_11_0_1_3__n N_132 clk_cpu_est_11_0_1_1__n \ -N_131 clk_cpu_est_11_0_2_1__n N_124 N_167_1 clk_cpu_est_11_3__n N_167_2 N_135 \ -N_167_3 N_133 N_167_4 N_134 N_167_5 clk_cpu_est_11_1__n N_167_6 N_130 N_170_1 \ -N_128 N_170_2 N_145 N_107_1 N_127 state_machine_un42_clk_030_1_n N_129 \ -state_machine_un42_clk_030_2_n N_126 state_machine_un42_clk_030_3_n N_125 \ -state_machine_un42_clk_030_4_n N_92 state_machine_un42_clk_030_5_n N_91 \ -DTACK_SYNC_1_sqmuxa_1_0 N_110 VPA_SYNC_1_sqmuxa_1_1 N_103 VPA_SYNC_1_sqmuxa_2 \ -N_101 VPA_SYNC_1_sqmuxa_3 N_100 VPA_SYNC_1_sqmuxa_4 N_112 N_98_1 N_99 \ -state_machine_as_030_000_sync_3_0_1_n state_machine_lds_000_int_8_n \ -UDS_000_INT_0_sqmuxa_1_0 state_machine_uds_000_int_8_n UDS_000_INT_0_sqmuxa_2 \ -un2_clk_030_1 state_machine_un13_clk_000_d_1_0_n VMA_INT_1_sqmuxa \ -state_machine_un13_clk_000_d_4_1_n RW_i state_machine_un8_clk_000_d_1_n \ -cpu_est_d_i_3__n state_machine_un8_clk_000_d_2_n cpu_est_d_i_0__n \ -state_machine_un8_clk_000_d_3_n CLK_000_D_i state_machine_un8_clk_000_d_4_n \ -AS_000_INT_i UDS_000_INT_0_sqmuxa_1_1 dsack_i_1__n UDS_000_INT_0_sqmuxa_1_2 \ -state_machine_un13_clk_000_d_i_n UDS_000_INT_0_sqmuxa_1_3 \ -state_machine_un8_clk_000_d_i_n N_132_1 AS_030_i N_131_1 sm_amiga_i_6__n \ -vma_int_0_un3_n sm_amiga_i_7__n vma_int_0_un1_n sm_amiga_i_5__n \ -vma_int_0_un0_n sm_amiga_i_4__n lds_000_int_0_un3_n \ -state_machine_un13_clk_000_d_1_i_n lds_000_int_0_un1_n CLK_000_DD_i \ -lds_000_int_0_un0_n AS_030_000_SYNC_i uds_000_int_0_un3_n cpu_est_i_0__n \ -uds_000_int_0_un1_n cpu_est_i_2__n uds_000_int_0_un0_n cpu_est_i_3__n \ -cpu_est_0_3__un3_n cpu_est_i_1__n cpu_est_0_3__un1_n UDS_000_INT_0_sqmuxa_1_i \ -cpu_est_0_3__un0_n UDS_000_INT_0_sqmuxa_i cpu_est_0_2__un3_n DS_030_i \ -cpu_est_0_2__un1_n VPA_D_i cpu_est_0_2__un0_n state_machine_un42_clk_030_i_n \ -cpu_est_0_1__un3_n VPA_SYNC_1_sqmuxa_i cpu_est_0_1__un1_n N_102_i \ -cpu_est_0_1__un0_n DTACK_SYNC_1_sqmuxa_i fpu_cs_int_0_un3_n N_98_i \ -fpu_cs_int_0_un1_n a_i_18__n fpu_cs_int_0_un0_n a_i_16__n as_000_int_0_un3_n \ -a_i_19__n as_000_int_0_un1_n CLK_030_i as_000_int_0_un0_n VMA_INT_i \ -vpa_sync_0_un3_n DTACK_i vpa_sync_0_un1_n sm_amiga_i_3__n vpa_sync_0_un0_n \ -sm_amiga_i_1__n as_030_000_sync_0_un3_n sm_amiga_i_2__n \ -as_030_000_sync_0_un1_n a_i_30__n as_030_000_sync_0_un0_n a_i_31__n \ -ipl_030_0_2__un3_n a_i_28__n ipl_030_0_2__un1_n a_i_29__n ipl_030_0_2__un0_n \ -a_i_26__n ipl_030_0_1__un3_n a_i_27__n ipl_030_0_1__un1_n a_i_24__n \ -ipl_030_0_1__un0_n a_i_25__n ipl_030_0_0__un3_n ipl_030_0_0__un1_n \ -ipl_030_0_0__un0_n RST_i bgack_030_int_0_un3_n FPU_CS_INT_i \ -bgack_030_int_0_un1_n CPU_SPACE_i bgack_030_int_0_un0_n BGACK_030_INT_i \ -dsack_int_0_1__un3_n AS_030_c dsack_int_0_1__un1_n dsack_int_0_1__un0_n \ -bg_000_0_un3_n DS_030_c bg_000_0_un1_n bg_000_0_un0_n dtack_sync_0_un3_n \ -dtack_sync_0_un1_n size_c_0__n dtack_sync_0_un0_n a_15__n size_c_1__n a_14__n \ -a_c_0__n a_13__n a_12__n a_11__n a_10__n a_9__n a_8__n a_7__n a_6__n a_c_16__n \ -a_5__n a_c_17__n a_4__n a_c_18__n a_3__n a_c_19__n a_2__n a_c_20__n a_1__n \ -a_c_21__n a_c_22__n a_c_23__n a_c_24__n a_c_25__n a_c_26__n a_c_27__n \ -a_c_28__n a_c_29__n a_c_30__n a_c_31__n CPU_SPACE_c BG_030_c BGACK_000_c \ -CLK_030_c CLK_000_c DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE \ -BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE cpu_est_0_0_ CLK_OUT_PRE_0 -.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_reg.D -1- 1 --1 1 -.names inst_CLK_000_D.BLIF N_99_i.BLIF SM_AMIGA_7_.D -11 1 -.names N_100_i.BLIF N_112_i.BLIF SM_AMIGA_6_.D -11 1 -.names sm_amiga_ns_0_2__n.BLIF SM_AMIGA_5_.D -0 1 -.names CLK_000_D_i.BLIF N_103_i.BLIF SM_AMIGA_4_.D -11 1 +inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP inst_AS_030_000_SYNC.D \ +inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_AS_000_INTreg.D \ +inst_AS_000_INTreg.C inst_AS_000_INTreg.AP inst_VPA_SYNC.D inst_VPA_SYNC.C \ +inst_VPA_SYNC.AP BG_000DFFSHreg.D BG_000DFFSHreg.C BG_000DFFSHreg.AP \ +inst_DTACK_DMA.D inst_DTACK_DMA.C inst_DTACK_DMA.AP inst_UDS_000_INTreg.D \ +inst_UDS_000_INTreg.C inst_UDS_000_INTreg.AP CLK_CNT_0_.D CLK_CNT_0_.C \ +inst_VPA_D.D inst_VPA_D.C inst_CLK_000_D.D inst_CLK_000_D.C RESETDFFreg.D \ +RESETDFFreg.C inst_CLK_000_DD.D inst_CLK_000_DD.C CLK_OUT_INTreg.D \ +CLK_OUT_INTreg.C DSACK_1_ DTACK DSACK_0_ ipl_c_0__n ipl_c_1__n ipl_c_2__n \ +gnd_n_n dsack_c_1__n DTACK_c RST_c vcc_n_n RW_c fc_c_0__n \ +state_machine_un1_clk_030_n fc_c_1__n state_machine_un6_bgack_000_n N_99_i \ +state_machine_un13_as_000_int_n un1_bg_030 N_101_i sm_amiga_ns_0_2__n N_107_i \ +N_106_i sm_amiga_ns_0_5__n N_108_i N_109_i N_110_i sm_amiga_ns_0_7__n N_91_0 \ +CLK_OUT_PRE_i N_94_0 state_machine_un8_clk_000_d_i_n \ +state_machine_un13_clk_000_d_i_n state_machine_un15_clk_000_d_0_n N_93_0 \ +N_104_i N_105_i N_103_i state_machine_un60_clk_000_d_i_n \ +state_machine_un17_clk_030_0_n un1_as_030_3_0 N_145_i clk_un4_clk_000_dd_n \ +a_c_i_0__n clk_cpu_est_11_1__n state_machine_uds_000_int_8_0_n \ +state_machine_un42_clk_030_n state_machine_lds_000_int_8_0_n N_102 \ +state_machine_as_030_000_sync_3_2_n N_98 size_c_i_1__n N_97 \ +state_machine_un34_clk_000_d_i_n N_100 N_131_i N_92 N_132_i N_112 N_122_i \ +N_127 N_125_i N_125 N_126_i N_128 N_134_i N_129 N_133_i N_130 N_135_i N_168 \ +clk_cpu_est_11_0_3__n N_171 N_130_i N_135_1 clk_cpu_est_11_0_1__n \ +state_machine_un13_clk_000_d_2_n N_128_i clk_cpu_est_11_3__n un1_bg_030_0 \ +N_135 N_97_i N_133 BG_030_c_i N_134 N_127_i N_132 N_129_i N_131 N_92_0 N_126 \ +N_100_i state_machine_un34_clk_000_d_n N_112_i UDS_000_INT_0_sqmuxa \ +UDS_000_INT_0_sqmuxa_1 clk_un4_clk_000_dd_i_n \ +state_machine_as_030_000_sync_3_n state_machine_un6_bgack_000_0_n N_145 \ +state_machine_un1_clk_030_0_n state_machine_lds_000_int_8_n \ +clk_cpu_est_11_0_1_3__n state_machine_uds_000_int_8_n \ +state_machine_un34_clk_000_d_i_1_n un1_as_030_4 \ +state_machine_as_030_000_sync_3_2_1_n un1_as_030_3 N_168_1 DSACK_INT_1_sqmuxa \ +N_168_2 state_machine_un17_clk_030_n N_168_3 state_machine_un60_clk_000_d_n \ +N_168_4 DTACK_SYNC_1_sqmuxa N_168_5 DTACK_SYNC_1_sqmuxa_1 N_168_6 \ +VPA_SYNC_1_sqmuxa N_171_1 VPA_SYNC_1_sqmuxa_1 N_171_2 N_103 un1_bg_030_0_1 \ +N_104 un1_bg_030_0_2 N_93 clk_cpu_est_11_0_1_1__n N_105 \ +clk_cpu_est_11_0_2_1__n VPA_SYNC_1_sqmuxa_1_0 state_machine_un42_clk_030_1_n \ +state_machine_un15_clk_000_d_n state_machine_un42_clk_030_2_n \ +state_machine_un13_clk_000_d_n state_machine_un42_clk_030_3_n \ +state_machine_un8_clk_000_d_n state_machine_un42_clk_030_4_n \ +state_machine_un8_clk_000_d_1_n state_machine_un42_clk_030_5_n \ +state_machine_un13_clk_000_d_1_n N_132_1 N_107 N_131_1 N_94 \ +UDS_000_INT_0_sqmuxa_1_0 N_91 UDS_000_INT_0_sqmuxa_2 N_110 \ +UDS_000_INT_0_sqmuxa_1_1 N_108 UDS_000_INT_0_sqmuxa_1_2 N_109 \ +UDS_000_INT_0_sqmuxa_1_3 N_106 DTACK_SYNC_1_sqmuxa_1_0 N_101 \ +state_machine_un8_clk_000_d_1_0_n N_99 state_machine_un8_clk_000_d_2_n \ +AS_000_INT_1_sqmuxa state_machine_un8_clk_000_d_3_n RW_i \ +state_machine_un13_clk_000_d_1_0_n N_102_i state_machine_un13_clk_000_d_2_0_n \ +AS_000_INT_i VPA_SYNC_1_sqmuxa_1_1 dsack_i_1__n VPA_SYNC_1_sqmuxa_2 AS_030_i \ +VPA_SYNC_1_sqmuxa_3 sm_amiga_i_7__n VPA_SYNC_1_sqmuxa_4 CLK_000_D_i N_107_1 \ +sm_amiga_i_2__n N_98_1 sm_amiga_i_1__n as_000_int_0_un3_n \ +state_machine_un13_clk_000_d_1_i_n as_000_int_0_un1_n VPA_D_i \ +as_000_int_0_un0_n VMA_INT_i vma_int_0_un3_n cpu_est_i_0__n vma_int_0_un1_n \ +cpu_est_i_1__n vma_int_0_un0_n cpu_est_i_3__n uds_000_int_0_un3_n \ +state_machine_un8_clk_000_d_1_i_0_n uds_000_int_0_un1_n DTACK_i \ +uds_000_int_0_un0_n sm_amiga_i_3__n dtack_sync_0_un3_n sm_amiga_i_4__n \ +dtack_sync_0_un1_n sm_amiga_i_5__n dtack_sync_0_un0_n DTACK_SYNC_1_sqmuxa_i \ +vpa_sync_0_un3_n VPA_SYNC_1_sqmuxa_i vpa_sync_0_un1_n N_98_i vpa_sync_0_un0_n \ +state_machine_un42_clk_030_i_n dsack_int_0_1__un3_n UDS_000_INT_0_sqmuxa_1_i \ +dsack_int_0_1__un1_n UDS_000_INT_0_sqmuxa_i dsack_int_0_1__un0_n \ +AS_030_000_SYNC_i as_030_000_sync_0_un3_n DS_030_i as_030_000_sync_0_un1_n \ +cpu_est_i_2__n as_030_000_sync_0_un0_n state_machine_un13_clk_000_d_2_i_n \ +fpu_cs_int_0_un3_n CLK_000_DD_i fpu_cs_int_0_un1_n sm_amiga_i_6__n \ +fpu_cs_int_0_un0_n CLK_030_i lds_000_int_0_un3_n a_i_30__n lds_000_int_0_un1_n \ +a_i_31__n lds_000_int_0_un0_n a_i_28__n cpu_est_0_3__un3_n a_i_29__n \ +cpu_est_0_3__un1_n a_i_26__n cpu_est_0_3__un0_n a_i_27__n cpu_est_0_2__un3_n \ +a_i_24__n cpu_est_0_2__un1_n a_i_25__n cpu_est_0_2__un0_n a_i_19__n \ +bg_000_0_un3_n a_i_16__n bg_000_0_un1_n a_i_18__n bg_000_0_un0_n \ +bgack_030_int_0_un3_n RST_i bgack_030_int_0_un1_n bgack_030_int_0_un0_n \ +FPU_CS_INT_i cpu_est_0_1__un3_n CPU_SPACE_i cpu_est_0_1__un1_n BGACK_030_INT_i \ +cpu_est_0_1__un0_n AS_030_c ipl_030_0_0__un3_n ipl_030_0_0__un1_n \ +ipl_030_0_0__un0_n DS_030_c ipl_030_0_1__un3_n ipl_030_0_1__un1_n \ +ipl_030_0_1__un0_n ipl_030_0_2__un3_n size_c_0__n ipl_030_0_2__un1_n \ +ipl_030_0_2__un0_n size_c_1__n a_15__n a_c_0__n a_14__n a_13__n a_12__n \ +a_11__n a_10__n a_9__n a_8__n a_7__n a_6__n a_c_16__n a_5__n a_c_17__n a_4__n \ +a_c_18__n a_3__n a_c_19__n a_2__n a_c_20__n a_1__n a_c_21__n a_c_22__n \ +a_c_23__n a_c_24__n a_c_25__n a_c_26__n a_c_27__n a_c_28__n a_c_29__n \ +a_c_30__n a_c_31__n CPU_SPACE_c BG_030_c BGACK_000_c CLK_030_c CLK_OSZI_c \ +DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE \ +AVEC_EXP.OE CIIN.OE cpu_est_0_0_ CLK_OUT_PRE_0 .names N_104_i.BLIF N_105_i.BLIF SM_AMIGA_3_.D 11 1 .names sm_amiga_ns_0_5__n.BLIF SM_AMIGA_2_.D @@ -319,33 +309,31 @@ BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE cpu_est_0_0_ CLK_OUT_PRE_0 .names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF IPL_030DFFSH_2_reg.D 1- 1 -1 1 -.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D -1- 1 --1 1 -.names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D -1- 1 --1 1 -.names vpa_sync_0_un1_n.BLIF vpa_sync_0_un0_n.BLIF inst_VPA_SYNC.D -1- 1 --1 1 -.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF \ -inst_AS_030_000_SYNC.D +.names inst_CLK_000_D.BLIF N_99_i.BLIF SM_AMIGA_7_.D +11 1 +.names N_100_i.BLIF N_112_i.BLIF SM_AMIGA_6_.D +11 1 +.names sm_amiga_ns_0_2__n.BLIF SM_AMIGA_5_.D +0 1 +.names CLK_000_D_i.BLIF N_103_i.BLIF SM_AMIGA_4_.D +11 1 +.names dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF DSACK_INT_1_.D 1- 1 -1 1 .names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D 1- 1 -1 1 -.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF BG_000DFFSHreg.D -1- 1 --1 1 -.names dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF DSACK_INT_1_.D -1- 1 --1 1 .names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF \ inst_BGACK_030_INTreg.D 1- 1 -1 1 -.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INTreg.D +.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D +1- 1 +-1 1 +.names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D +1- 1 +-1 1 +.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_reg.D 1- 1 -1 1 .names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF inst_LDS_000_INTreg.D @@ -357,42 +345,52 @@ inst_BGACK_030_INTreg.D .names fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF inst_FPU_CS_INTreg.D 1- 1 -1 1 +.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF \ +inst_AS_030_000_SYNC.D +1- 1 +-1 1 .names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF inst_AS_000_INTreg.D 1- 1 -1 1 +.names vpa_sync_0_un1_n.BLIF vpa_sync_0_un0_n.BLIF inst_VPA_SYNC.D +1- 1 +-1 1 +.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF BG_000DFFSHreg.D +1- 1 +-1 1 .names state_machine_un13_as_000_int_n.BLIF inst_DTACK_DMA.D 0 1 -.names CLK_000_D_i.BLIF CLK_000_c.BLIF inst_RISING_CLK_AMIGA.D -11 1 +.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INTreg.D +1- 1 +-1 1 .names CLK_CNT_0_.BLIF CLK_CNT_0_.D 0 1 .names gnd_n_n .names vcc_n_n 1 -.names state_machine_un57_clk_000_d_0_n.BLIF state_machine_un57_clk_000_d_n +.names state_machine_un1_clk_030_0_n.BLIF state_machine_un1_clk_030_n +0 1 +.names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n +0 1 +.names N_99.BLIF N_99_i 0 1 .names AS_000_INT_i.BLIF dsack_i_1__n.BLIF state_machine_un13_as_000_int_n 11 1 -.names N_145.BLIF N_145_i -0 1 -.names a_c_0__n.BLIF a_c_i_0__n -0 1 -.names a_c_i_0__n.BLIF N_145_i.BLIF state_machine_uds_000_int_8_0_n -11 1 -.names N_145_i.BLIF state_machine_un31_clk_000_d_n.BLIF \ -state_machine_lds_000_int_8_0_n -11 1 -.names N_99.BLIF N_99_i -0 1 -.names N_112.BLIF N_112_i -0 1 -.names N_100.BLIF N_100_i +.names un1_bg_030_0.BLIF un1_bg_030 0 1 .names N_101.BLIF N_101_i 0 1 .names N_101_i.BLIF N_102_i.BLIF sm_amiga_ns_0_2__n 11 1 -.names N_103.BLIF N_103_i +.names N_107.BLIF N_107_i +0 1 +.names N_106.BLIF N_106_i +0 1 +.names N_106_i.BLIF N_107_i.BLIF sm_amiga_ns_0_5__n +11 1 +.names N_108.BLIF N_108_i +0 1 +.names N_109.BLIF N_109_i 0 1 .names N_110.BLIF N_110_i 0 1 @@ -400,518 +398,519 @@ state_machine_lds_000_int_8_0_n 11 1 .names inst_AS_000_INTreg.BLIF SM_AMIGA_0_.BLIF N_91_0 11 1 -.names CLK_000_D_i.BLIF SM_AMIGA_7_.BLIF N_92_0 -11 1 -.names N_131.BLIF N_131_i +.names inst_CLK_OUT_PRE.BLIF CLK_OUT_PRE_i 0 1 -.names N_132.BLIF N_132_i +.names CLK_OUT_PRE_i.BLIF sm_amiga_i_2__n.BLIF N_94_0 +11 1 +.names state_machine_un8_clk_000_d_n.BLIF state_machine_un8_clk_000_d_i_n 0 1 -.names N_131_i.BLIF N_132_i.BLIF N_122_i -11 1 -.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_124_i -11 1 -.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF N_125_i -11 1 -.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_126_i -11 1 -.names N_129.BLIF N_129_i +.names state_machine_un13_clk_000_d_n.BLIF state_machine_un13_clk_000_d_i_n 0 1 -.names N_98_1.BLIF SM_AMIGA_1_.BLIF N_98 +.names state_machine_un8_clk_000_d_i_n.BLIF \ +state_machine_un13_clk_000_d_i_n.BLIF state_machine_un15_clk_000_d_0_n 11 1 -.names N_127.BLIF N_127_i +.names SM_AMIGA_3_.BLIF state_machine_un60_clk_000_d_i_n.BLIF N_93_0 +11 1 +.names N_104.BLIF N_104_i 0 1 -.names sm_amiga_i_6__n.BLIF sm_amiga_i_7__n.BLIF N_97 -11 1 -.names N_128.BLIF N_128_i +.names N_105.BLIF N_105_i 0 1 -.names CLK_000_D_i.BLIF N_93.BLIF N_104 -11 1 -.names N_130.BLIF N_130_i +.names N_103.BLIF N_103_i 0 1 -.names N_93_0.BLIF N_93 -0 1 -.names clk_cpu_est_11_0_1_1__n.BLIF clk_cpu_est_11_0_2_1__n.BLIF \ -clk_cpu_est_11_0_1__n -11 1 -.names sm_amiga_i_3__n.BLIF sm_amiga_i_4__n.BLIF N_105 -11 1 -.names N_134.BLIF N_134_i -0 1 -.names CLK_000_D_i.BLIF SM_AMIGA_2_.BLIF N_106 -11 1 -.names N_133.BLIF N_133_i -0 1 -.names CLK_000_D_i.BLIF N_94.BLIF N_108 -11 1 -.names N_135.BLIF N_135_i -0 1 -.names N_94_0.BLIF N_94 -0 1 -.names clk_cpu_est_11_0_1_3__n.BLIF N_134_i.BLIF clk_cpu_est_11_0_3__n -11 1 -.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_109 -11 1 -.names size_c_1__n.BLIF size_c_i_1__n -0 1 -.names N_107_1.BLIF state_machine_un57_clk_000_d_n.BLIF N_107 -11 1 -.names state_machine_un31_clk_000_d_i_1_n.BLIF size_c_i_1__n.BLIF \ -state_machine_un31_clk_000_d_i_n -11 1 -.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_135_1 -11 1 -.names state_machine_as_030_000_sync_3_0_1_n.BLIF \ -state_machine_un42_clk_030_i_n.BLIF state_machine_as_030_000_sync_3_0_n -11 1 -.names inst_CLK_000_D.BLIF SM_AMIGA_3_.BLIF VPA_SYNC_1_sqmuxa_1_0 -11 1 -.names AS_030_i.BLIF state_machine_un42_clk_030_n.BLIF un1_as_030_2_0 -11 1 -.names N_167_5.BLIF N_167_6.BLIF N_167 +.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF \ +state_machine_un60_clk_000_d_i_n 11 1 .names AS_030_i.BLIF CLK_030_i.BLIF state_machine_un17_clk_030_0_n 11 1 -.names N_170_1.BLIF N_170_2.BLIF N_170 +.names AS_030_i.BLIF state_machine_un42_clk_030_n.BLIF un1_as_030_3_0 11 1 -.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF \ -state_machine_un57_clk_000_d_0_n +.names N_145.BLIF N_145_i +0 1 +.names inst_CLK_000_D.BLIF CLK_000_DD_i.BLIF clk_un4_clk_000_dd_n +11 1 +.names a_c_0__n.BLIF a_c_i_0__n +0 1 +.names clk_cpu_est_11_0_1__n.BLIF clk_cpu_est_11_1__n +0 1 +.names a_c_i_0__n.BLIF N_145_i.BLIF state_machine_uds_000_int_8_0_n 11 1 .names state_machine_un42_clk_030_4_n.BLIF state_machine_un42_clk_030_5_n.BLIF \ state_machine_un42_clk_030_n 11 1 -.names inst_RISING_CLK_AMIGA.BLIF RISING_CLK_AMIGA_i +.names N_145_i.BLIF state_machine_un34_clk_000_d_n.BLIF \ +state_machine_lds_000_int_8_0_n +11 1 +.names N_112.BLIF SM_AMIGA_6_.BLIF N_102 +11 1 +.names state_machine_as_030_000_sync_3_2_1_n.BLIF \ +state_machine_un42_clk_030_i_n.BLIF state_machine_as_030_000_sync_3_2_n +11 1 +.names N_98_1.BLIF SM_AMIGA_1_.BLIF N_98 +11 1 +.names size_c_1__n.BLIF size_c_i_1__n 0 1 -.names DTACK_SYNC_1_sqmuxa_1_0.BLIF VPA_SYNC_1_sqmuxa_1_0.BLIF \ -DTACK_SYNC_1_sqmuxa +.names sm_amiga_i_6__n.BLIF sm_amiga_i_7__n.BLIF N_97 11 1 -.names BGACK_000_c.BLIF RISING_CLK_AMIGA_i.BLIF \ -state_machine_un4_bgack_000_0_n +.names state_machine_un34_clk_000_d_i_1_n.BLIF size_c_i_1__n.BLIF \ +state_machine_un34_clk_000_d_i_n 11 1 -.names VPA_SYNC_1_sqmuxa_4.BLIF VPA_SYNC_1_sqmuxa_3.BLIF VPA_SYNC_1_sqmuxa +.names N_92.BLIF sm_amiga_i_6__n.BLIF N_100 11 1 -.names BG_030_c.BLIF BG_030_c_i +.names N_131.BLIF N_131_i 0 1 -.names un1_bg_030_0.BLIF un1_bg_030 +.names N_92_0.BLIF N_92 0 1 -.names BG_030_c_i.BLIF CLK_030_c.BLIF state_machine_un1_clk_030_0_n +.names N_132.BLIF N_132_i +0 1 +.names AS_030_000_SYNC_i.BLIF clk_un4_clk_000_dd_n.BLIF N_112 11 1 -.names AS_030_i.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF DTACK_SYNC_1_sqmuxa_1 +.names N_131_i.BLIF N_132_i.BLIF N_122_i +11 1 +.names N_125.BLIF cpu_est_i_0__n.BLIF N_127 +11 1 +.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF N_125_i +11 1 +.names N_125_i.BLIF N_125 +0 1 +.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_126_i +11 1 +.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_128 +11 1 +.names N_134.BLIF N_134_i +0 1 +.names N_125_i.BLIF cpu_est_0_.BLIF N_129 +11 1 +.names N_133.BLIF N_133_i +0 1 +.names cpu_est_3_reg.BLIF state_machine_un13_clk_000_d_2_n.BLIF N_130 +11 1 +.names N_135.BLIF N_135_i +0 1 +.names N_168_5.BLIF N_168_6.BLIF N_168 +11 1 +.names clk_cpu_est_11_0_1_3__n.BLIF N_134_i.BLIF clk_cpu_est_11_0_3__n +11 1 +.names N_171_1.BLIF N_171_2.BLIF N_171 +11 1 +.names N_130.BLIF N_130_i +0 1 +.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_135_1 +11 1 +.names clk_cpu_est_11_0_1_1__n.BLIF clk_cpu_est_11_0_2_1__n.BLIF \ +clk_cpu_est_11_0_1__n +11 1 +.names cpu_est_1_.BLIF cpu_est_2_.BLIF state_machine_un13_clk_000_d_2_n +11 1 +.names N_128.BLIF N_128_i +0 1 +.names clk_cpu_est_11_0_3__n.BLIF clk_cpu_est_11_3__n +0 1 +.names un1_bg_030_0_1.BLIF un1_bg_030_0_2.BLIF un1_bg_030_0 +11 1 +.names N_135_1.BLIF cpu_est_i_2__n.BLIF N_135 11 1 .names N_97.BLIF N_97_i 0 1 -.names AS_030_i.BLIF N_98_i.BLIF DSACK_INT_1_sqmuxa +.names N_126.BLIF cpu_est_3_reg.BLIF N_133 11 1 -.names un1_bg_030_0_1.BLIF un1_bg_030_0_2.BLIF un1_bg_030_0 +.names BG_030_c.BLIF BG_030_c_i +0 1 +.names N_126_i.BLIF cpu_est_i_2__n.BLIF N_134 11 1 -.names state_machine_un1_clk_030_0_n.BLIF state_machine_un1_clk_030_n +.names N_127.BLIF N_127_i 0 1 -.names inst_CLK_OUT_PRE.BLIF CLK_OUT_PRE_i -0 1 -.names state_machine_un4_bgack_000_0_n.BLIF state_machine_un4_bgack_000_n -0 1 -.names CLK_OUT_PRE_i.BLIF sm_amiga_i_2__n.BLIF N_94_0 +.names N_132_1.BLIF cpu_est_i_2__n.BLIF N_132 11 1 -.names un1_as_030_2_0.BLIF un1_as_030_2 +.names N_129.BLIF N_129_i 0 1 -.names SM_AMIGA_3_.BLIF state_machine_un57_clk_000_d_0_n.BLIF N_93_0 +.names N_131_1.BLIF state_machine_un13_clk_000_d_2_i_n.BLIF N_131 11 1 -.names state_machine_un17_clk_030_0_n.BLIF state_machine_un17_clk_030_n -0 1 -.names N_108.BLIF N_108_i -0 1 -.names N_112.BLIF SM_AMIGA_6_.BLIF N_102 +.names CLK_000_D_i.BLIF SM_AMIGA_7_.BLIF N_92_0 11 1 -.names N_109.BLIF N_109_i +.names N_126_i.BLIF N_126 0 1 -.names AS_030_i.BLIF N_102_i.BLIF AS_000_INT_1_sqmuxa -11 1 -.names AS_030_i.BLIF VPA_SYNC_1_sqmuxa_i.BLIF VPA_SYNC_1_sqmuxa_1 -11 1 -.names N_106.BLIF N_106_i +.names N_100.BLIF N_100_i 0 1 -.names state_machine_as_030_000_sync_3_0_n.BLIF \ -state_machine_as_030_000_sync_3_n +.names state_machine_un34_clk_000_d_i_n.BLIF state_machine_un34_clk_000_d_n 0 1 -.names N_107.BLIF N_107_i -0 1 -.names inst_CLK_000_D.BLIF CLK_000_DD_i.BLIF clk_un3_clk_000_dd_n -11 1 -.names N_106_i.BLIF N_107_i.BLIF sm_amiga_ns_0_5__n -11 1 -.names state_machine_un31_clk_000_d_i_n.BLIF state_machine_un31_clk_000_d_n -0 1 -.names N_104.BLIF N_104_i +.names N_112.BLIF N_112_i 0 1 .names UDS_000_INT_0_sqmuxa_1_0.BLIF UDS_000_INT_0_sqmuxa_2.BLIF \ UDS_000_INT_0_sqmuxa 11 1 -.names N_105.BLIF N_105_i +.names UDS_000_INT_0_sqmuxa_1_3.BLIF clk_un4_clk_000_dd_n.BLIF \ +UDS_000_INT_0_sqmuxa_1 +11 1 +.names clk_un4_clk_000_dd_n.BLIF clk_un4_clk_000_dd_i_n 0 1 +.names state_machine_as_030_000_sync_3_2_n.BLIF \ +state_machine_as_030_000_sync_3_n +0 1 +.names BGACK_000_c.BLIF clk_un4_clk_000_dd_i_n.BLIF \ +state_machine_un6_bgack_000_0_n +11 1 +.names UDS_000_INT_0_sqmuxa_1_i.BLIF UDS_000_INT_0_sqmuxa_i.BLIF N_145 +11 1 +.names BG_030_c_i.BLIF CLK_030_c.BLIF state_machine_un1_clk_030_0_n +11 1 +.names state_machine_lds_000_int_8_0_n.BLIF state_machine_lds_000_int_8_n +0 1 +.names N_135_i.BLIF N_133_i.BLIF clk_cpu_est_11_0_1_3__n +11 1 +.names state_machine_uds_000_int_8_0_n.BLIF state_machine_uds_000_int_8_n +0 1 +.names size_c_0__n.BLIF a_c_i_0__n.BLIF state_machine_un34_clk_000_d_i_1_n +11 1 +.names AS_030_i.BLIF N_145.BLIF un1_as_030_4 +11 1 +.names AS_030_i.BLIF CPU_SPACE_i.BLIF state_machine_as_030_000_sync_3_2_1_n +11 1 +.names un1_as_030_3_0.BLIF un1_as_030_3 +0 1 +.names a_i_24__n.BLIF a_i_25__n.BLIF N_168_1 +11 1 +.names AS_030_i.BLIF N_98_i.BLIF DSACK_INT_1_sqmuxa +11 1 +.names a_i_26__n.BLIF a_i_27__n.BLIF N_168_2 +11 1 +.names state_machine_un17_clk_030_0_n.BLIF state_machine_un17_clk_030_n +0 1 +.names a_i_28__n.BLIF a_i_29__n.BLIF N_168_3 +11 1 +.names state_machine_un60_clk_000_d_i_n.BLIF state_machine_un60_clk_000_d_n +0 1 +.names a_i_30__n.BLIF a_i_31__n.BLIF N_168_4 +11 1 +.names DTACK_SYNC_1_sqmuxa_1_0.BLIF VPA_SYNC_1_sqmuxa_1_0.BLIF \ +DTACK_SYNC_1_sqmuxa +11 1 +.names N_168_1.BLIF N_168_2.BLIF N_168_5 +11 1 +.names AS_030_i.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF DTACK_SYNC_1_sqmuxa_1 +11 1 +.names N_168_3.BLIF N_168_4.BLIF N_168_6 +11 1 +.names VPA_SYNC_1_sqmuxa_4.BLIF VPA_SYNC_1_sqmuxa_3.BLIF VPA_SYNC_1_sqmuxa +11 1 +.names a_c_20__n.BLIF a_c_21__n.BLIF N_171_1 +11 1 +.names AS_030_i.BLIF VPA_SYNC_1_sqmuxa_i.BLIF VPA_SYNC_1_sqmuxa_1 +11 1 +.names a_c_22__n.BLIF a_c_23__n.BLIF N_171_2 +11 1 +.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_103 +11 1 +.names AS_030_c.BLIF BG_030_c_i.BLIF un1_bg_030_0_1 +11 1 +.names CLK_000_D_i.BLIF N_93.BLIF N_104 +11 1 +.names CPU_SPACE_i.BLIF N_97_i.BLIF un1_bg_030_0_2 +11 1 +.names N_93_0.BLIF N_93 +0 1 +.names N_127_i.BLIF N_128_i.BLIF clk_cpu_est_11_0_1_1__n +11 1 +.names sm_amiga_i_3__n.BLIF sm_amiga_i_4__n.BLIF N_105 +11 1 +.names N_129_i.BLIF N_130_i.BLIF clk_cpu_est_11_0_2_1__n +11 1 +.names inst_CLK_000_D.BLIF SM_AMIGA_3_.BLIF VPA_SYNC_1_sqmuxa_1_0 +11 1 +.names a_c_17__n.BLIF a_i_16__n.BLIF state_machine_un42_clk_030_1_n +11 1 +.names state_machine_un15_clk_000_d_0_n.BLIF state_machine_un15_clk_000_d_n +0 1 +.names a_i_18__n.BLIF a_i_19__n.BLIF state_machine_un42_clk_030_2_n +11 1 .names state_machine_un13_clk_000_d_1_0_n.BLIF \ -state_machine_un13_clk_000_d_4_n.BLIF state_machine_un13_clk_000_d_n +state_machine_un13_clk_000_d_2_0_n.BLIF state_machine_un13_clk_000_d_n 11 1 -.names state_machine_un13_clk_000_d_4_1_n.BLIF cpu_est_d_2_.BLIF \ -state_machine_un13_clk_000_d_4_n +.names fc_c_1__n.BLIF BGACK_000_c.BLIF state_machine_un42_clk_030_3_n 11 1 -.names BG_030_c_i.BLIF CPU_SPACE_i.BLIF un1_bg_030_0_1 +.names state_machine_un8_clk_000_d_3_n.BLIF cpu_est_i_3__n.BLIF \ +state_machine_un8_clk_000_d_n +11 1 +.names state_machine_un42_clk_030_1_n.BLIF state_machine_un42_clk_030_2_n.BLIF \ +state_machine_un42_clk_030_4_n +11 1 +.names CLK_000_D_i.BLIF cpu_est_0_.BLIF state_machine_un8_clk_000_d_1_n +11 1 +.names state_machine_un42_clk_030_3_n.BLIF fc_c_0__n.BLIF \ +state_machine_un42_clk_030_5_n 11 1 .names inst_AS_000_INTreg.BLIF inst_CLK_000_D.BLIF \ state_machine_un13_clk_000_d_1_n 11 1 -.names AS_030_c.BLIF N_97_i.BLIF un1_bg_030_0_2 +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_132_1 11 1 -.names state_machine_un8_clk_000_d_4_n.BLIF \ -state_machine_un8_clk_000_d_3_n.BLIF state_machine_un8_clk_000_d_n +.names N_107_1.BLIF state_machine_un60_clk_000_d_n.BLIF N_107 11 1 -.names size_c_0__n.BLIF a_c_i_0__n.BLIF state_machine_un31_clk_000_d_i_1_n +.names cpu_est_0_.BLIF cpu_est_i_3__n.BLIF N_131_1 11 1 -.names UDS_000_INT_0_sqmuxa_1_3.BLIF clk_un3_clk_000_dd_n.BLIF \ -UDS_000_INT_0_sqmuxa_1 -11 1 -.names N_135_i.BLIF N_133_i.BLIF clk_cpu_est_11_0_1_3__n -11 1 -.names N_132_1.BLIF cpu_est_i_2__n.BLIF N_132 -11 1 -.names N_130_i.BLIF N_128_i.BLIF clk_cpu_est_11_0_1_1__n -11 1 -.names N_131_1.BLIF cpu_est_i_3__n.BLIF N_131 -11 1 -.names N_127_i.BLIF N_129_i.BLIF clk_cpu_est_11_0_2_1__n -11 1 -.names N_124_i.BLIF N_124 -0 1 -.names a_i_24__n.BLIF a_i_25__n.BLIF N_167_1 -11 1 -.names clk_cpu_est_11_0_3__n.BLIF clk_cpu_est_11_3__n -0 1 -.names a_i_26__n.BLIF a_i_27__n.BLIF N_167_2 -11 1 -.names N_135_1.BLIF cpu_est_i_2__n.BLIF N_135 -11 1 -.names a_i_28__n.BLIF a_i_29__n.BLIF N_167_3 -11 1 -.names N_126.BLIF cpu_est_3_reg.BLIF N_133 -11 1 -.names a_i_30__n.BLIF a_i_31__n.BLIF N_167_4 -11 1 -.names N_126_i.BLIF cpu_est_i_2__n.BLIF N_134 -11 1 -.names N_167_1.BLIF N_167_2.BLIF N_167_5 -11 1 -.names clk_cpu_est_11_0_1__n.BLIF clk_cpu_est_11_1__n -0 1 -.names N_167_3.BLIF N_167_4.BLIF N_167_6 -11 1 -.names N_124_i.BLIF cpu_est_3_reg.BLIF N_130 -11 1 -.names a_c_20__n.BLIF a_c_21__n.BLIF N_170_1 -11 1 -.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_128 -11 1 -.names a_c_22__n.BLIF a_c_23__n.BLIF N_170_2 -11 1 -.names UDS_000_INT_0_sqmuxa_1_i.BLIF UDS_000_INT_0_sqmuxa_i.BLIF N_145 -11 1 -.names CLK_000_D_i.BLIF SM_AMIGA_3_.BLIF N_107_1 -11 1 -.names N_125.BLIF cpu_est_i_0__n.BLIF N_127 -11 1 -.names a_c_17__n.BLIF a_i_16__n.BLIF state_machine_un42_clk_030_1_n -11 1 -.names N_125_i.BLIF cpu_est_0_.BLIF N_129 -11 1 -.names a_i_18__n.BLIF a_i_19__n.BLIF state_machine_un42_clk_030_2_n -11 1 -.names N_126_i.BLIF N_126 -0 1 -.names fc_c_1__n.BLIF BGACK_000_c.BLIF state_machine_un42_clk_030_3_n -11 1 -.names N_125_i.BLIF N_125 -0 1 -.names state_machine_un42_clk_030_1_n.BLIF state_machine_un42_clk_030_2_n.BLIF \ -state_machine_un42_clk_030_4_n -11 1 -.names N_92_0.BLIF N_92 -0 1 -.names state_machine_un42_clk_030_3_n.BLIF fc_c_0__n.BLIF \ -state_machine_un42_clk_030_5_n -11 1 -.names N_91_0.BLIF N_91 -0 1 -.names DTACK_i.BLIF inst_VPA_D.BLIF DTACK_SYNC_1_sqmuxa_1_0 -11 1 -.names SM_AMIGA_0_.BLIF state_machine_un13_clk_000_d_1_i_n.BLIF N_110 -11 1 -.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF VPA_SYNC_1_sqmuxa_1_1 -11 1 -.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_103 -11 1 -.names N_135_1.BLIF VMA_INT_i.BLIF VPA_SYNC_1_sqmuxa_2 -11 1 -.names inst_CLK_000_D.BLIF SM_AMIGA_5_.BLIF N_101 -11 1 -.names VPA_D_i.BLIF VPA_SYNC_1_sqmuxa_1_0.BLIF VPA_SYNC_1_sqmuxa_3 -11 1 -.names N_92.BLIF sm_amiga_i_6__n.BLIF N_100 -11 1 -.names VPA_SYNC_1_sqmuxa_1_1.BLIF VPA_SYNC_1_sqmuxa_2.BLIF VPA_SYNC_1_sqmuxa_4 -11 1 -.names AS_030_000_SYNC_i.BLIF clk_un3_clk_000_dd_n.BLIF N_112 -11 1 -.names CLK_000_D_i.BLIF inst_CLK_OUT_PRE.BLIF N_98_1 -11 1 -.names N_91.BLIF sm_amiga_i_7__n.BLIF N_99 -11 1 -.names AS_030_i.BLIF CPU_SPACE_i.BLIF state_machine_as_030_000_sync_3_0_1_n -11 1 -.names state_machine_lds_000_int_8_0_n.BLIF state_machine_lds_000_int_8_n +.names N_94_0.BLIF N_94 0 1 .names inst_CLK_000_D.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_0 11 1 -.names state_machine_uds_000_int_8_0_n.BLIF state_machine_uds_000_int_8_n +.names N_91_0.BLIF N_91 0 1 .names RW_i.BLIF SM_AMIGA_4_.BLIF UDS_000_INT_0_sqmuxa_2 11 1 -.names AS_030_i.BLIF N_145.BLIF un2_clk_030_1 +.names SM_AMIGA_0_.BLIF state_machine_un13_clk_000_d_1_i_n.BLIF N_110 11 1 -.names cpu_est_d_i_0__n.BLIF cpu_est_d_i_3__n.BLIF \ -state_machine_un13_clk_000_d_1_0_n -11 1 -.names state_machine_un8_clk_000_d_i_n.BLIF \ -state_machine_un13_clk_000_d_i_n.BLIF VMA_INT_1_sqmuxa -11 1 -.names state_machine_un13_clk_000_d_1_n.BLIF cpu_est_d_1_.BLIF \ -state_machine_un13_clk_000_d_4_1_n -11 1 -.names RW_c.BLIF RW_i -0 1 -.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF state_machine_un8_clk_000_d_1_n -11 1 -.names cpu_est_d_3_.BLIF cpu_est_d_i_3__n -0 1 -.names CLK_000_D_i.BLIF VPA_D_i.BLIF state_machine_un8_clk_000_d_2_n -11 1 -.names cpu_est_d_0_.BLIF cpu_est_d_i_0__n -0 1 -.names cpu_est_0_.BLIF cpu_est_2_.BLIF state_machine_un8_clk_000_d_3_n -11 1 -.names inst_CLK_000_D.BLIF CLK_000_D_i -0 1 -.names state_machine_un8_clk_000_d_1_n.BLIF \ -state_machine_un8_clk_000_d_2_n.BLIF state_machine_un8_clk_000_d_4_n -11 1 -.names inst_AS_000_INTreg.BLIF AS_000_INT_i -0 1 .names AS_030_000_SYNC_i.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_1 11 1 -.names dsack_c_1__n.BLIF dsack_i_1__n -0 1 +.names CLK_000_D_i.BLIF N_94.BLIF N_108 +11 1 .names RW_c.BLIF SM_AMIGA_6_.BLIF UDS_000_INT_0_sqmuxa_1_2 11 1 -.names state_machine_un13_clk_000_d_n.BLIF state_machine_un13_clk_000_d_i_n -0 1 +.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_109 +11 1 .names UDS_000_INT_0_sqmuxa_1_1.BLIF UDS_000_INT_0_sqmuxa_1_2.BLIF \ UDS_000_INT_0_sqmuxa_1_3 11 1 -.names state_machine_un8_clk_000_d_n.BLIF state_machine_un8_clk_000_d_i_n +.names CLK_000_D_i.BLIF SM_AMIGA_2_.BLIF N_106 +11 1 +.names DTACK_i.BLIF inst_VPA_D.BLIF DTACK_SYNC_1_sqmuxa_1_0 +11 1 +.names inst_CLK_000_D.BLIF SM_AMIGA_5_.BLIF N_101 +11 1 +.names state_machine_un8_clk_000_d_1_n.BLIF VPA_D_i.BLIF \ +state_machine_un8_clk_000_d_1_0_n +11 1 +.names N_91.BLIF sm_amiga_i_7__n.BLIF N_99 +11 1 +.names cpu_est_2_.BLIF cpu_est_i_1__n.BLIF state_machine_un8_clk_000_d_2_n +11 1 +.names AS_030_i.BLIF N_102_i.BLIF AS_000_INT_1_sqmuxa +11 1 +.names state_machine_un8_clk_000_d_1_0_n.BLIF \ +state_machine_un8_clk_000_d_2_n.BLIF state_machine_un8_clk_000_d_3_n +11 1 +.names RW_c.BLIF RW_i 0 1 -.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_132_1 +.names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF \ +state_machine_un13_clk_000_d_1_0_n +11 1 +.names N_102.BLIF N_102_i +0 1 +.names state_machine_un13_clk_000_d_1_n.BLIF \ +state_machine_un13_clk_000_d_2_n.BLIF state_machine_un13_clk_000_d_2_0_n +11 1 +.names inst_AS_000_INTreg.BLIF AS_000_INT_i +0 1 +.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF VPA_SYNC_1_sqmuxa_1_1 +11 1 +.names dsack_c_1__n.BLIF dsack_i_1__n +0 1 +.names N_135_1.BLIF VMA_INT_i.BLIF VPA_SYNC_1_sqmuxa_2 11 1 .names AS_030_c.BLIF AS_030_i 0 1 -.names N_124.BLIF cpu_est_0_.BLIF N_131_1 +.names VPA_D_i.BLIF VPA_SYNC_1_sqmuxa_1_0.BLIF VPA_SYNC_1_sqmuxa_3 11 1 -.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n -0 1 -.names VMA_INT_1_sqmuxa.BLIF vma_int_0_un3_n -0 1 .names SM_AMIGA_7_.BLIF sm_amiga_i_7__n 0 1 -.names inst_VMA_INTreg.BLIF VMA_INT_1_sqmuxa.BLIF vma_int_0_un1_n +.names VPA_SYNC_1_sqmuxa_1_1.BLIF VPA_SYNC_1_sqmuxa_2.BLIF VPA_SYNC_1_sqmuxa_4 11 1 -.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +.names inst_CLK_000_D.BLIF CLK_000_D_i 0 1 -.names state_machine_un13_clk_000_d_4_n.BLIF vma_int_0_un3_n.BLIF \ -vma_int_0_un0_n +.names CLK_000_D_i.BLIF SM_AMIGA_3_.BLIF N_107_1 11 1 -.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n +.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n 0 1 -.names un2_clk_030_1.BLIF lds_000_int_0_un3_n +.names CLK_000_D_i.BLIF inst_CLK_OUT_PRE.BLIF N_98_1 +11 1 +.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n +0 1 +.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n 0 1 .names state_machine_un13_clk_000_d_1_n.BLIF \ state_machine_un13_clk_000_d_1_i_n 0 1 -.names inst_LDS_000_INTreg.BLIF un2_clk_030_1.BLIF lds_000_int_0_un1_n -11 1 -.names inst_CLK_000_DD.BLIF CLK_000_DD_i -0 1 -.names state_machine_lds_000_int_8_n.BLIF lds_000_int_0_un3_n.BLIF \ -lds_000_int_0_un0_n -11 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i -0 1 -.names un2_clk_030_1.BLIF uds_000_int_0_un3_n -0 1 -.names cpu_est_0_.BLIF cpu_est_i_0__n -0 1 -.names inst_UDS_000_INTreg.BLIF un2_clk_030_1.BLIF uds_000_int_0_un1_n -11 1 -.names cpu_est_2_.BLIF cpu_est_i_2__n -0 1 -.names state_machine_uds_000_int_8_n.BLIF uds_000_int_0_un3_n.BLIF \ -uds_000_int_0_un0_n -11 1 -.names cpu_est_3_reg.BLIF cpu_est_i_3__n -0 1 -.names clk_un3_clk_000_dd_n.BLIF cpu_est_0_3__un3_n -0 1 -.names cpu_est_1_.BLIF cpu_est_i_1__n -0 1 -.names clk_cpu_est_11_3__n.BLIF clk_un3_clk_000_dd_n.BLIF cpu_est_0_3__un1_n -11 1 -.names UDS_000_INT_0_sqmuxa_1.BLIF UDS_000_INT_0_sqmuxa_1_i -0 1 -.names cpu_est_3_reg.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n -11 1 -.names UDS_000_INT_0_sqmuxa.BLIF UDS_000_INT_0_sqmuxa_i -0 1 -.names clk_un3_clk_000_dd_n.BLIF cpu_est_0_2__un3_n -0 1 -.names DS_030_c.BLIF DS_030_i -0 1 -.names N_122_i.BLIF clk_un3_clk_000_dd_n.BLIF cpu_est_0_2__un1_n -11 1 -.names inst_VPA_D.BLIF VPA_D_i -0 1 -.names cpu_est_2_.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n -11 1 -.names state_machine_un42_clk_030_n.BLIF state_machine_un42_clk_030_i_n -0 1 -.names clk_un3_clk_000_dd_n.BLIF cpu_est_0_1__un3_n -0 1 -.names VPA_SYNC_1_sqmuxa.BLIF VPA_SYNC_1_sqmuxa_i -0 1 -.names clk_cpu_est_11_1__n.BLIF clk_un3_clk_000_dd_n.BLIF cpu_est_0_1__un1_n -11 1 -.names N_102.BLIF N_102_i -0 1 -.names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n -11 1 -.names DTACK_SYNC_1_sqmuxa.BLIF DTACK_SYNC_1_sqmuxa_i -0 1 -.names state_machine_un17_clk_030_n.BLIF fpu_cs_int_0_un3_n -0 1 -.names N_98.BLIF N_98_i -0 1 -.names un1_as_030_2.BLIF state_machine_un17_clk_030_n.BLIF fpu_cs_int_0_un1_n -11 1 -.names a_c_18__n.BLIF a_i_18__n -0 1 -.names inst_FPU_CS_INTreg.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un0_n -11 1 -.names a_c_16__n.BLIF a_i_16__n -0 1 -.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n -0 1 -.names a_c_19__n.BLIF a_i_19__n -0 1 .names inst_AS_000_INTreg.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n 11 1 -.names CLK_030_c.BLIF CLK_030_i +.names inst_VPA_D.BLIF VPA_D_i 0 1 .names N_102_i.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n 11 1 .names inst_VMA_INTreg.BLIF VMA_INT_i 0 1 -.names VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un3_n +.names state_machine_un15_clk_000_d_n.BLIF vma_int_0_un3_n 0 1 +.names cpu_est_0_.BLIF cpu_est_i_0__n +0 1 +.names state_machine_un8_clk_000_d_1_i_0_n.BLIF \ +state_machine_un15_clk_000_d_n.BLIF vma_int_0_un1_n +11 1 +.names cpu_est_1_.BLIF cpu_est_i_1__n +0 1 +.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n +11 1 +.names cpu_est_3_reg.BLIF cpu_est_i_3__n +0 1 +.names un1_as_030_4.BLIF uds_000_int_0_un3_n +0 1 +.names state_machine_un8_clk_000_d_1_n.BLIF \ +state_machine_un8_clk_000_d_1_i_0_n +0 1 +.names inst_UDS_000_INTreg.BLIF un1_as_030_4.BLIF uds_000_int_0_un1_n +11 1 .names DTACK_c.BLIF DTACK_i 0 1 -.names inst_VPA_SYNC.BLIF VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un1_n +.names state_machine_uds_000_int_8_n.BLIF uds_000_int_0_un3_n.BLIF \ +uds_000_int_0_un0_n 11 1 .names SM_AMIGA_3_.BLIF sm_amiga_i_3__n 0 1 +.names DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un3_n +0 1 +.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n +0 1 +.names inst_DTACK_SYNC.BLIF DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un1_n +11 1 +.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +0 1 +.names DTACK_SYNC_1_sqmuxa_i.BLIF dtack_sync_0_un3_n.BLIF dtack_sync_0_un0_n +11 1 +.names DTACK_SYNC_1_sqmuxa.BLIF DTACK_SYNC_1_sqmuxa_i +0 1 +.names VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un3_n +0 1 +.names VPA_SYNC_1_sqmuxa.BLIF VPA_SYNC_1_sqmuxa_i +0 1 +.names inst_VPA_SYNC.BLIF VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un1_n +11 1 +.names N_98.BLIF N_98_i +0 1 .names VPA_SYNC_1_sqmuxa_i.BLIF vpa_sync_0_un3_n.BLIF vpa_sync_0_un0_n 11 1 -.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n +.names state_machine_un42_clk_030_n.BLIF state_machine_un42_clk_030_i_n +0 1 +.names DSACK_INT_1_sqmuxa.BLIF dsack_int_0_1__un3_n +0 1 +.names UDS_000_INT_0_sqmuxa_1.BLIF UDS_000_INT_0_sqmuxa_1_i +0 1 +.names DSACK_INT_1_.BLIF DSACK_INT_1_sqmuxa.BLIF dsack_int_0_1__un1_n +11 1 +.names UDS_000_INT_0_sqmuxa.BLIF UDS_000_INT_0_sqmuxa_i +0 1 +.names N_98_i.BLIF dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un0_n +11 1 +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i 0 1 .names state_machine_un17_clk_030_n.BLIF as_030_000_sync_0_un3_n 0 1 -.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n +.names DS_030_c.BLIF DS_030_i 0 1 .names state_machine_as_030_000_sync_3_n.BLIF \ state_machine_un17_clk_030_n.BLIF as_030_000_sync_0_un1_n 11 1 -.names a_c_30__n.BLIF a_i_30__n +.names cpu_est_2_.BLIF cpu_est_i_2__n 0 1 .names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF \ as_030_000_sync_0_un0_n 11 1 +.names state_machine_un13_clk_000_d_2_n.BLIF \ +state_machine_un13_clk_000_d_2_i_n +0 1 +.names state_machine_un17_clk_030_n.BLIF fpu_cs_int_0_un3_n +0 1 +.names inst_CLK_000_DD.BLIF CLK_000_DD_i +0 1 +.names un1_as_030_3.BLIF state_machine_un17_clk_030_n.BLIF fpu_cs_int_0_un1_n +11 1 +.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n +0 1 +.names inst_FPU_CS_INTreg.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un0_n +11 1 +.names CLK_030_c.BLIF CLK_030_i +0 1 +.names un1_as_030_4.BLIF lds_000_int_0_un3_n +0 1 +.names a_c_30__n.BLIF a_i_30__n +0 1 +.names inst_LDS_000_INTreg.BLIF un1_as_030_4.BLIF lds_000_int_0_un1_n +11 1 .names a_c_31__n.BLIF a_i_31__n 0 1 -.names inst_RISING_CLK_AMIGA.BLIF ipl_030_0_2__un3_n -0 1 +.names state_machine_lds_000_int_8_n.BLIF lds_000_int_0_un3_n.BLIF \ +lds_000_int_0_un0_n +11 1 .names a_c_28__n.BLIF a_i_28__n 0 1 -.names ipl_c_2__n.BLIF inst_RISING_CLK_AMIGA.BLIF ipl_030_0_2__un1_n -11 1 +.names clk_un4_clk_000_dd_n.BLIF cpu_est_0_3__un3_n +0 1 .names a_c_29__n.BLIF a_i_29__n 0 1 -.names IPL_030DFFSH_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n +.names clk_cpu_est_11_3__n.BLIF clk_un4_clk_000_dd_n.BLIF cpu_est_0_3__un1_n 11 1 .names a_c_26__n.BLIF a_i_26__n 0 1 -.names inst_RISING_CLK_AMIGA.BLIF ipl_030_0_1__un3_n -0 1 +.names cpu_est_3_reg.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n +11 1 .names a_c_27__n.BLIF a_i_27__n 0 1 -.names ipl_c_1__n.BLIF inst_RISING_CLK_AMIGA.BLIF ipl_030_0_1__un1_n -11 1 +.names clk_un4_clk_000_dd_n.BLIF cpu_est_0_2__un3_n +0 1 .names a_c_24__n.BLIF a_i_24__n 0 1 -.names IPL_030DFFSH_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n +.names N_122_i.BLIF clk_un4_clk_000_dd_n.BLIF cpu_est_0_2__un1_n 11 1 .names a_c_25__n.BLIF a_i_25__n 0 1 -.names inst_RISING_CLK_AMIGA.BLIF ipl_030_0_0__un3_n -0 1 -.names ipl_c_0__n.BLIF inst_RISING_CLK_AMIGA.BLIF ipl_030_0_0__un1_n +.names cpu_est_2_.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n 11 1 -.names IPL_030DFFSH_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n -11 1 -.names RST_c.BLIF RST_i +.names a_c_19__n.BLIF a_i_19__n 0 1 -.names state_machine_un4_bgack_000_n.BLIF bgack_030_int_0_un3_n -0 1 -.names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i -0 1 -.names BGACK_000_c.BLIF state_machine_un4_bgack_000_n.BLIF \ -bgack_030_int_0_un1_n -11 1 -.names CPU_SPACE_c.BLIF CPU_SPACE_i -0 1 -.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \ -bgack_030_int_0_un0_n -11 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i -0 1 -.names DSACK_INT_1_sqmuxa.BLIF dsack_int_0_1__un3_n -0 1 -.names DSACK_INT_1_.BLIF DSACK_INT_1_sqmuxa.BLIF dsack_int_0_1__un1_n -11 1 -.names N_98_i.BLIF dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un0_n -11 1 .names state_machine_un1_clk_030_n.BLIF bg_000_0_un3_n 0 1 +.names a_c_16__n.BLIF a_i_16__n +0 1 .names un1_bg_030.BLIF state_machine_un1_clk_030_n.BLIF bg_000_0_un1_n 11 1 +.names a_c_18__n.BLIF a_i_18__n +0 1 .names BG_000DFFSHreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n 11 1 -.names DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un3_n +.names state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n 0 1 -.names inst_DTACK_SYNC.BLIF DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un1_n +.names RST_c.BLIF RST_i +0 1 +.names BGACK_000_c.BLIF state_machine_un6_bgack_000_n.BLIF \ +bgack_030_int_0_un1_n 11 1 -.names DTACK_SYNC_1_sqmuxa_i.BLIF dtack_sync_0_un3_n.BLIF dtack_sync_0_un0_n +.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \ +bgack_030_int_0_un0_n +11 1 +.names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i +0 1 +.names clk_un4_clk_000_dd_n.BLIF cpu_est_0_1__un3_n +0 1 +.names CPU_SPACE_c.BLIF CPU_SPACE_i +0 1 +.names clk_cpu_est_11_1__n.BLIF clk_un4_clk_000_dd_n.BLIF cpu_est_0_1__un1_n +11 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i +0 1 +.names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n +11 1 +.names clk_un4_clk_000_dd_n.BLIF ipl_030_0_0__un3_n +0 1 +.names ipl_c_0__n.BLIF clk_un4_clk_000_dd_n.BLIF ipl_030_0_0__un1_n +11 1 +.names IPL_030DFFSH_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n +11 1 +.names clk_un4_clk_000_dd_n.BLIF ipl_030_0_1__un3_n +0 1 +.names ipl_c_1__n.BLIF clk_un4_clk_000_dd_n.BLIF ipl_030_0_1__un1_n +11 1 +.names IPL_030DFFSH_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n +11 1 +.names clk_un4_clk_000_dd_n.BLIF ipl_030_0_2__un3_n +0 1 +.names ipl_c_2__n.BLIF clk_un4_clk_000_dd_n.BLIF ipl_030_0_2__un1_n +11 1 +.names IPL_030DFFSH_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n 11 1 .names IPL_030DFFSH_2_reg.BLIF IPL_030_2_ 1 1 @@ -967,7 +966,7 @@ bgack_030_int_0_un0_n .names vcc_n_n.BLIF AMIGA_BUS_ENABLE_LOW 1 1 0 0 -.names N_170.BLIF CIIN +.names N_171.BLIF CIIN 1 1 0 0 .names IPL_030DFFSH_1_reg.BLIF IPL_030_1_ @@ -976,33 +975,6 @@ bgack_030_int_0_un0_n .names IPL_030DFFSH_0_reg.BLIF IPL_030_0_ 1 1 0 0 -.names CLK_OSZI_c.BLIF cpu_est_3_reg.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_7_.C -1 1 -0 0 -.names RST_i.BLIF SM_AMIGA_7_.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C -1 1 -0 0 -.names RST_i.BLIF SM_AMIGA_6_.AR -1 1 -0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C -1 1 -0 0 -.names RST_i.BLIF SM_AMIGA_5_.AR -1 1 -0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C -1 1 -0 0 -.names RST_i.BLIF SM_AMIGA_4_.AR -1 1 -0 0 .names CLK_OSZI_c.BLIF SM_AMIGA_3_.C 1 1 0 0 @@ -1027,30 +999,6 @@ bgack_030_int_0_un0_n .names RST_i.BLIF SM_AMIGA_0_.AR 1 1 0 0 -.names cpu_est_0_.BLIF cpu_est_d_0_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF cpu_est_d_0_.C -1 1 -0 0 -.names cpu_est_1_.BLIF cpu_est_d_1_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF cpu_est_d_1_.C -1 1 -0 0 -.names cpu_est_2_.BLIF cpu_est_d_2_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF cpu_est_d_2_.C -1 1 -0 0 -.names cpu_est_3_reg.BLIF cpu_est_d_3_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF cpu_est_d_3_.C -1 1 -0 0 .names CLK_OSZI_c.BLIF IPL_030DFFSH_0_reg.C 1 1 0 0 @@ -1069,40 +1017,28 @@ bgack_030_int_0_un0_n .names RST_i.BLIF IPL_030DFFSH_2_reg.AP 1 1 0 0 -.names cpu_est_0_0_.BLIF cpu_est_0_.D +.names CLK_OSZI_c.BLIF SM_AMIGA_7_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF cpu_est_0_.C +.names RST_i.BLIF SM_AMIGA_7_.AP 1 1 0 0 -.names CLK_OSZI_c.BLIF cpu_est_1_.C +.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF cpu_est_2_.C +.names RST_i.BLIF SM_AMIGA_6_.AR 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_VPA_SYNC.C +.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C 1 1 0 0 -.names RST_i.BLIF inst_VPA_SYNC.AP +.names RST_i.BLIF SM_AMIGA_5_.AR 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C +.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C 1 1 0 0 -.names RST_i.BLIF inst_AS_030_000_SYNC.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C -1 1 -0 0 -.names RST_i.BLIF inst_VMA_INTreg.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C -1 1 -0 0 -.names RST_i.BLIF BG_000DFFSHreg.AP +.names RST_i.BLIF SM_AMIGA_4_.AR 1 1 0 0 .names CLK_OSZI_c.BLIF DSACK_INT_1_.C @@ -1111,6 +1047,12 @@ bgack_030_int_0_un0_n .names RST_i.BLIF DSACK_INT_1_.AP 1 1 0 0 +.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C +1 1 +0 0 +.names RST_i.BLIF inst_VMA_INTreg.AP +1 1 +0 0 .names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C 1 1 0 0 @@ -1123,10 +1065,19 @@ bgack_030_int_0_un0_n .names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_UDS_000_INTreg.C +.names cpu_est_0_0_.BLIF cpu_est_0_.D 1 1 0 0 -.names RST_i.BLIF inst_UDS_000_INTreg.AP +.names CLK_OSZI_c.BLIF cpu_est_0_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF cpu_est_1_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF cpu_est_2_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF cpu_est_3_reg.C 1 1 0 0 .names CLK_OSZI_c.BLIF inst_LDS_000_INTreg.C @@ -1147,19 +1098,40 @@ bgack_030_int_0_un0_n .names RST_i.BLIF inst_FPU_CS_INTreg.AP 1 1 0 0 +.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C +1 1 +0 0 +.names RST_i.BLIF inst_AS_030_000_SYNC.AP +1 1 +0 0 .names CLK_OSZI_c.BLIF inst_AS_000_INTreg.C 1 1 0 0 .names RST_i.BLIF inst_AS_000_INTreg.AP 1 1 0 0 +.names CLK_OSZI_c.BLIF inst_VPA_SYNC.C +1 1 +0 0 +.names RST_i.BLIF inst_VPA_SYNC.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C +1 1 +0 0 +.names RST_i.BLIF BG_000DFFSHreg.AP +1 1 +0 0 .names CLK_OSZI_c.BLIF inst_DTACK_DMA.C 1 1 0 0 .names RST_i.BLIF inst_DTACK_DMA.AP 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_RISING_CLK_AMIGA.C +.names CLK_OSZI_c.BLIF inst_UDS_000_INTreg.C +1 1 +0 0 +.names RST_i.BLIF inst_UDS_000_INTreg.AP 1 1 0 0 .names CLK_OSZI_c.BLIF CLK_CNT_0_.C @@ -1171,7 +1143,7 @@ bgack_030_int_0_un0_n .names CLK_OSZI_c.BLIF inst_VPA_D.C 1 1 0 0 -.names CLK_000_c.BLIF inst_CLK_000_D.D +.names CLK_000.BLIF inst_CLK_000_D.D 1 1 0 0 .names CLK_OSZI_c.BLIF inst_CLK_000_D.C @@ -1204,9 +1176,6 @@ bgack_030_int_0_un0_n .names vcc_n_n.BLIF DSACK_0_ 1 1 0 0 -.names CLK_OSZI.BLIF CLK_OSZI_c -1 1 -0 0 .names IPL_0_.BLIF ipl_c_0__n 1 1 0 0 @@ -1243,18 +1212,18 @@ bgack_030_int_0_un0_n .names SIZE_0_.BLIF size_c_0__n 1 1 0 0 -.names A_15_.BLIF a_15__n -1 1 -0 0 .names SIZE_1_.BLIF size_c_1__n 1 1 0 0 -.names A_14_.BLIF a_14__n +.names A_15_.BLIF a_15__n 1 1 0 0 .names A_0_.BLIF a_c_0__n 1 1 0 0 +.names A_14_.BLIF a_14__n +1 1 +0 0 .names A_13_.BLIF a_13__n 1 1 0 0 @@ -1354,7 +1323,7 @@ bgack_030_int_0_un0_n .names CLK_030.BLIF CLK_030_c 1 1 0 0 -.names CLK_000.BLIF CLK_000_c +.names CLK_OSZI.BLIF CLK_OSZI_c 1 1 0 0 .names CPU_SPACE_i.BLIF DSACK_1_.OE @@ -1381,10 +1350,10 @@ bgack_030_int_0_un0_n .names FPU_CS_INT_i.BLIF AVEC_EXP.OE 1 1 0 0 -.names N_167.BLIF CIIN.OE +.names N_168.BLIF CIIN.OE 1 1 0 0 -.names cpu_est_0_.BLIF clk_un3_clk_000_dd_n.BLIF cpu_est_0_0_ +.names cpu_est_0_.BLIF clk_un4_clk_000_dd_n.BLIF cpu_est_0_0_ 01 1 10 1 11 0 diff --git a/Logic/BUS68030.edi b/Logic/BUS68030.edi index 046cfca..a436852 100644 --- a/Logic/BUS68030.edi +++ b/Logic/BUS68030.edi @@ -4,7 +4,7 @@ (keywordMap (keywordLevel 0)) (status (written - (timeStamp 2014 5 15 22 21 49) + (timeStamp 2014 5 15 23 2 41) (author "Synopsys, Inc.") (program "Synplify Pro" (version "G-2012.09LC-SP1 , mapper maplat, Build 621R")) ) @@ -156,7 +156,19 @@ (port CIIN (direction OUTPUT)) ) (contents - (instance (rename cpu_est_3 "cpu_est[3]") (viewRef prim (cellRef DFF (libraryRef mach))) + (instance (rename SM_AMIGA_3 "SM_AMIGA[3]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename SM_AMIGA_2 "SM_AMIGA[2]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename SM_AMIGA_1 "SM_AMIGA[1]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename SM_AMIGA_0 "SM_AMIGA[0]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename IPL_030DFFSH_0 "IPL_030DFFSH[0]") (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance (rename IPL_030DFFSH_1 "IPL_030DFFSH[1]") (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance (rename IPL_030DFFSH_2 "IPL_030DFFSH[2]") (viewRef prim (cellRef DFFSH (libraryRef mach))) ) (instance (rename SM_AMIGA_7 "SM_AMIGA[7]") (viewRef prim (cellRef DFFSH (libraryRef mach))) ) @@ -166,27 +178,13 @@ ) (instance (rename SM_AMIGA_4 "SM_AMIGA[4]") (viewRef prim (cellRef DFFRH (libraryRef mach))) ) - (instance (rename SM_AMIGA_3 "SM_AMIGA[3]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + (instance (rename DSACK_INT_1 "DSACK_INT[1]") (viewRef prim (cellRef DFFSH (libraryRef mach))) ) - (instance (rename SM_AMIGA_2 "SM_AMIGA[2]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + (instance VMA_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) ) - (instance (rename SM_AMIGA_1 "SM_AMIGA[1]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + (instance BGACK_030_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) ) - (instance (rename SM_AMIGA_0 "SM_AMIGA[0]") (viewRef prim (cellRef DFFRH (libraryRef mach))) - ) - (instance (rename cpu_est_d_0 "cpu_est_d[0]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename cpu_est_d_1 "cpu_est_d[1]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename cpu_est_d_2 "cpu_est_d[2]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename cpu_est_d_3 "cpu_est_d[3]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename IPL_030DFFSH_0 "IPL_030DFFSH[0]") (viewRef prim (cellRef DFFSH (libraryRef mach))) - ) - (instance (rename IPL_030DFFSH_1 "IPL_030DFFSH[1]") (viewRef prim (cellRef DFFSH (libraryRef mach))) - ) - (instance (rename IPL_030DFFSH_2 "IPL_030DFFSH[2]") (viewRef prim (cellRef DFFSH (libraryRef mach))) + (instance CLK_OUT_PRE (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance (rename cpu_est_0 "cpu_est[0]") (viewRef prim (cellRef DFF (libraryRef mach))) ) @@ -194,21 +192,7 @@ ) (instance (rename cpu_est_2 "cpu_est[2]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance VPA_SYNC (viewRef prim (cellRef DFFSH (libraryRef mach))) - ) - (instance AS_030_000_SYNC (viewRef prim (cellRef DFFSH (libraryRef mach))) - ) - (instance VMA_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) - ) - (instance BG_000DFFSH (viewRef prim (cellRef DFFSH (libraryRef mach))) - ) - (instance (rename DSACK_INT_1 "DSACK_INT[1]") (viewRef prim (cellRef DFFSH (libraryRef mach))) - ) - (instance BGACK_030_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) - ) - (instance CLK_OUT_PRE (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance UDS_000_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) + (instance (rename cpu_est_3 "cpu_est[3]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance LDS_000_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) ) @@ -216,11 +200,17 @@ ) (instance FPU_CS_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) ) + (instance AS_030_000_SYNC (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) (instance AS_000_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) ) + (instance VPA_SYNC (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance BG_000DFFSH (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) (instance DTACK_DMA (viewRef prim (cellRef DFFSH (libraryRef mach))) ) - (instance RISING_CLK_AMIGA (viewRef prim (cellRef DFF (libraryRef mach))) + (instance UDS_000_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) ) (instance (rename CLK_CNT_0 "CLK_CNT[0]") (viewRef prim (cellRef DFF (libraryRef mach))) ) @@ -293,140 +283,225 @@ (instance AMIGA_BUS_DATA_DIR (viewRef prim (cellRef OBUF (libraryRef mach))) ) (instance AMIGA_BUS_ENABLE_LOW (viewRef prim (cellRef OBUF (libraryRef mach))) ) (instance CIIN (viewRef prim (cellRef BUFTH (libraryRef mach))) ) - (instance UDS_000_INT_0_sqmuxa_1_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance UDS_000_INT_0_sqmuxa_1_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance UDS_000_INT_0_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un8_clk_000_d_2 "state_machine.un8_clk_000_d_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un8_clk_000_d_3 "state_machine.un8_clk_000_d_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un8_clk_000_d "state_machine.un8_clk_000_d") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un13_clk_000_d_1_0 "state_machine.un13_clk_000_d_1_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un13_clk_000_d_2_0 "state_machine.un13_clk_000_d_2_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un13_clk_000_d "state_machine.un13_clk_000_d") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VPA_SYNC_1_sqmuxa_1_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VPA_SYNC_1_sqmuxa_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VPA_SYNC_1_sqmuxa_3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VPA_SYNC_1_sqmuxa_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VPA_SYNC_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_a2_0_1_5 "SM_AMIGA_ns_a2_0_1[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_a2_0_5 "SM_AMIGA_ns_a2_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_DSACK_INT_0_sqmuxa_i_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_DSACK_INT_0_sqmuxa_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un42_clk_030 "state_machine.un42_clk_030") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename clk_cpu_est_11_i_a4_0_1_2 "clk.cpu_est_11_i_a4_0_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename clk_cpu_est_11_i_a4_0_2 "clk.cpu_est_11_i_a4_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename clk_cpu_est_11_i_a4_1_2 "clk.cpu_est_11_i_a4_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename clk_cpu_est_11_i_a4_2 "clk.cpu_est_11_i_a4[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_AS_030_000_SYNC_3_1 "state_machine.AS_030_000_SYNC_3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_AS_030_000_SYNC_3 "state_machine.AS_030_000_SYNC_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance UDS_000_INT_0_sqmuxa_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance UDS_000_INT_0_sqmuxa_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance UDS_000_INT_0_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un13_clk_000_d_1_0 "state_machine.un13_clk_000_d_1_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un13_clk_000_d "state_machine.un13_clk_000_d") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un13_clk_000_d_4_1 "state_machine.un13_clk_000_d_4_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un13_clk_000_d_4 "state_machine.un13_clk_000_d_4") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un8_clk_000_d_1 "state_machine.un8_clk_000_d_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un8_clk_000_d_2 "state_machine.un8_clk_000_d_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un8_clk_000_d_3 "state_machine.un8_clk_000_d_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un8_clk_000_d_4 "state_machine.un8_clk_000_d_4") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un8_clk_000_d "state_machine.un8_clk_000_d") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance UDS_000_INT_0_sqmuxa_1_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance UDS_000_INT_0_sqmuxa_1_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance UDS_000_INT_0_sqmuxa_1_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance UDS_000_INT_0_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DTACK_SYNC_1_sqmuxa_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DTACK_SYNC_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un8_clk_000_d_1_0 "state_machine.un8_clk_000_d_1_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un8_ciin (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un4_ciin_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un4_ciin_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un4_ciin (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_bg_030_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_bg_030_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_bg_030 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_1_1 "clk.cpu_est_11_0_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_2_1 "clk.cpu_est_11_0_2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_1 "clk.cpu_est_11_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename state_machine_un42_clk_030_1 "state_machine.un42_clk_030_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename state_machine_un42_clk_030_2 "state_machine.un42_clk_030_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename state_machine_un42_clk_030_3 "state_machine.un42_clk_030_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename state_machine_un42_clk_030_4 "state_machine.un42_clk_030_4") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename state_machine_un42_clk_030_5 "state_machine.un42_clk_030_5") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un42_clk_030 "state_machine.un42_clk_030") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DTACK_SYNC_1_sqmuxa_1_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DTACK_SYNC_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_SYNC_1_sqmuxa_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_SYNC_1_sqmuxa_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_SYNC_1_sqmuxa_3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_SYNC_1_sqmuxa_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_SYNC_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_DSACK_INT_0_sqmuxa_i_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_DSACK_INT_0_sqmuxa_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_1_1 "clk.cpu_est_11_0_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_2_1 "clk.cpu_est_11_0_2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_1 "clk.cpu_est_11_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_un4_clk_000_dd_i "clk.un4_clk_000_dd_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un6_bgack_000_i "state_machine.un6_bgack_000_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un1_clk_030_i "state_machine.un1_clk_030_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_1_3 "clk.cpu_est_11_0_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_3 "clk.cpu_est_11_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un34_clk_000_d_1 "state_machine.un34_clk_000_d_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un34_clk_000_d "state_machine.un34_clk_000_d") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_AS_030_000_SYNC_3_1 "state_machine.AS_030_000_SYNC_3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_AS_030_000_SYNC_3 "state_machine.AS_030_000_SYNC_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un8_ciin_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un8_ciin_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un8_ciin_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un8_ciin_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un8_ciin_5 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un8_ciin_6 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un8_ciin (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un4_ciin_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un4_ciin_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un4_ciin (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_a2_0_1_5 "SM_AMIGA_ns_a2_0_1[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_a2_0_5 "SM_AMIGA_ns_a2_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_o2_i_4 "SM_AMIGA_ns_i_o2_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_108_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_109_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_106_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_107_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_5 "SM_AMIGA_ns_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_104_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_105_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_bg_030_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_bg_030_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_bg_030 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un31_clk_000_d_1 "state_machine.un31_clk_000_d_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un31_clk_000_d "state_machine.un31_clk_000_d") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_1_3 "clk.cpu_est_11_0_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_3 "clk.cpu_est_11_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_i_3 "clk.cpu_est_11_0_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SIZE_c_i_1 "SIZE_c_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un31_clk_000_d_i_0 "state_machine.un31_clk_000_d_i_0") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_AS_030_000_SYNC_3_i "state_machine.AS_030_000_SYNC_3_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_as_030_2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un17_clk_030_i "state_machine.un17_clk_030_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un57_clk_000_d_i "state_machine.un57_clk_000_d_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RISING_CLK_AMIGA_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un4_bgack_000_i "state_machine.un4_bgack_000_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance BG_030_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un1_clk_030_i "state_machine.un1_clk_030_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_97_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_bg_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance CLK_OUT_PRE_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_o2_i_6 "SM_AMIGA_ns_i_o2_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_o2_i_0 "SM_AMIGA_ns_i_o2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_o2_i_1 "SM_AMIGA_ns_i_o2_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_131_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_132_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_i_o4_i_2 "clk.cpu_est_11_i_o4_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_o4_i_1 "clk.cpu_est_11_0_o4_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_o4_i_3 "clk.cpu_est_11_0_o4_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_129_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_127_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_128_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_130_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_i_1 "clk.cpu_est_11_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_134_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_133_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_135_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_i_3 "clk.cpu_est_11_0_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_130_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_i_1 "clk.cpu_est_11_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_128_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_bg_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_97_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance BG_030_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_127_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_129_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_o2_i_1 "SM_AMIGA_ns_i_o2_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_100_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_112_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_103_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un60_clk_000_d_i_0 "state_machine.un60_clk_000_d_i_0") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un17_clk_030_i "state_machine.un17_clk_030_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_as_030_3_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_145_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename A_c_i_0 "A_c_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename state_machine_UDS_000_INT_8_i "state_machine.UDS_000_INT_8_i") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename state_machine_LDS_000_INT_8_i "state_machine.LDS_000_INT_8_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_99_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_112_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_100_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_101_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_2 "SM_AMIGA_ns_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_103_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_AS_030_000_SYNC_3_i "state_machine.AS_030_000_SYNC_3_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SIZE_c_i_1 "SIZE_c_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un34_clk_000_d_i_0 "state_machine.un34_clk_000_d_i_0") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_131_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_132_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_o4_i_1 "clk.cpu_est_11_0_o4_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_o4_i_3 "clk.cpu_est_11_0_o4_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_106_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_5 "SM_AMIGA_ns_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_108_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_109_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_110_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename SM_AMIGA_ns_i_7 "SM_AMIGA_ns_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_o2_i_0 "SM_AMIGA_ns_i_o2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_OUT_PRE_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_o2_i_6 "SM_AMIGA_ns_i_o2_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un8_clk_000_d_i "state_machine.un8_clk_000_d_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un13_clk_000_d_i "state_machine.un13_clk_000_d_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un15_clk_000_d_i "state_machine.un15_clk_000_d_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_o2_i_4 "SM_AMIGA_ns_i_o2_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_104_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_105_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_99_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_101_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_2 "SM_AMIGA_ns_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_107_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_a2_5 "SM_AMIGA_ns_a2[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_a2_2 "SM_AMIGA_ns_a2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_a2_0 "SM_AMIGA_ns_i_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_000_INT_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_106 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un13_as_000_int "state_machine.un13_as_000_int") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance N_102_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AS_000_INT_0_r "AS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AS_000_INT_0_m "AS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_000_INT_0_n "AS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_000_INT_0_p "AS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance RW_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un13_clk_000_d_1 "state_machine.un13_clk_000_d_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_o2_6 "SM_AMIGA_ns_i_o2[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_o2_0 "SM_AMIGA_ns_i_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_7 "SM_AMIGA_ns[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_6 "SM_AMIGA_ns_i[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_5 "SM_AMIGA_ns[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_2 "SM_AMIGA_ns[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_0 "SM_AMIGA_ns_i[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un13_clk_000_d_1_i "state_machine.un13_clk_000_d_1_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_a2_7 "SM_AMIGA_ns_a2[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_a2_0_6 "SM_AMIGA_ns_i_a2_0[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_a2_6 "SM_AMIGA_ns_i_a2[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_000_D_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_o2_4 "SM_AMIGA_ns_i_o2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance I_107 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance VPA_SYNC_1_sqmuxa_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un8_clk_000_d_1_i "state_machine.un8_clk_000_d_1_i") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename VMA_INT_0_r "VMA_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename VMA_INT_0_m "VMA_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename VMA_INT_0_n "VMA_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename VMA_INT_0_p "VMA_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename LDS_000_INT_0_r "LDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename LDS_000_INT_0_m "LDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename LDS_000_INT_0_n "LDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename LDS_000_INT_0_p "LDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename state_machine_un15_clk_000_d "state_machine.un15_clk_000_d") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un8_clk_000_d_1 "state_machine.un8_clk_000_d_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_i_3 "cpu_est_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_i_0 "cpu_est_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_i_1 "cpu_est_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance VPA_SYNC_1_sqmuxa_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VPA_D_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance VMA_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_OUT_PRE_0 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) (instance (rename UDS_000_INT_0_r "UDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename UDS_000_INT_0_m "UDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename UDS_000_INT_0_n "UDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename UDS_000_INT_0_p "UDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance RW_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un2_clk_030_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un13_clk_000_d_i "state_machine.un13_clk_000_d_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un8_clk_000_d_i "state_machine.un8_clk_000_d_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance VMA_INT_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_106 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un13_as_000_int "state_machine.un13_as_000_int") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_000_D_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename clk_RISING_CLK_AMIGA_1 "clk.RISING_CLK_AMIGA_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_d_i_3 "cpu_est_d_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_d_i_0 "cpu_est_d_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un60_clk_000_d "state_machine.un60_clk_000_d") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DTACK_SYNC_0_r "DTACK_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename DTACK_SYNC_0_m "DTACK_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DTACK_SYNC_0_n "DTACK_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DTACK_SYNC_0_p "DTACK_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename VPA_SYNC_0_r "VPA_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename VPA_SYNC_0_m "VPA_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename VPA_SYNC_0_n "VPA_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename VPA_SYNC_0_p "VPA_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance VPA_SYNC_1_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance VPA_SYNC_1_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DTACK_SYNC_1_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DTACK_SYNC_1_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_a2_3 "SM_AMIGA_ns_i_a2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_a2_4 "SM_AMIGA_ns_i_a2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_a2_0_4 "SM_AMIGA_ns_i_a2_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_3 "SM_AMIGA_ns_i[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_4 "SM_AMIGA_ns_i[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance UDS_000_INT_0_sqmuxa_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance UDS_000_INT_0_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_as_030_4_93 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_LDS_000_INT_8 "state_machine.LDS_000_INT_8") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_UDS_000_INT_8 "state_machine.UDS_000_INT_8") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_as_030_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un42_clk_030_i "state_machine.un42_clk_030_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_as_030_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DSACK_INT_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un17_clk_030 "state_machine.un17_clk_030") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance N_98_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename DSACK_INT_0_1__r "DSACK_INT_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename DSACK_INT_0_1__m "DSACK_INT_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DSACK_INT_0_1__n "DSACK_INT_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DSACK_INT_0_1__p "DSACK_INT_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename AS_030_000_SYNC_0_r "AS_030_000_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AS_030_000_SYNC_0_m "AS_030_000_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_030_000_SYNC_0_n "AS_030_000_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_030_000_SYNC_0_p "AS_030_000_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename FPU_CS_INT_0_r "FPU_CS_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename FPU_CS_INT_0_m "FPU_CS_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename FPU_CS_INT_0_n "FPU_CS_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename FPU_CS_INT_0_p "FPU_CS_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename LDS_000_INT_0_r "LDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename LDS_000_INT_0_m "LDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename LDS_000_INT_0_n "LDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename LDS_000_INT_0_p "LDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename state_machine_un13_clk_000_d_2 "state_machine.un13_clk_000_d_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_a4_1_3 "clk.cpu_est_11_0_a4_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un13_clk_000_d_2_i "state_machine.un13_clk_000_d_2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_o4_3 "clk.cpu_est_11_0_o4[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_o4_1 "clk.cpu_est_11_0_o4[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_i_2 "clk.cpu_est_11_i[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_a4_0_3 "clk.cpu_est_11_0_a4_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_a4_3 "clk.cpu_est_11_0_a4[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_a4_2_1 "clk.cpu_est_11_0_a4_2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_i_2 "cpu_est_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_a4_0_1 "clk.cpu_est_11_0_a4_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename cpu_est_0_3__r "cpu_est_0_3_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename cpu_est_0_3__m "cpu_est_0_3_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename cpu_est_0_3__n "cpu_est_0_3_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) @@ -435,133 +510,26 @@ (instance (rename cpu_est_0_2__m "cpu_est_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename cpu_est_0_2__n "cpu_est_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename cpu_est_0_2__p "cpu_est_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename cpu_est_0_1__r "cpu_est_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_0_1__m "cpu_est_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_1__n "cpu_est_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_1__p "cpu_est_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename clk_un3_clk_000_dd_0_a2 "clk.un3_clk_000_dd_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un13_clk_000_d_1_i "state_machine.un13_clk_000_d_1_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_a2_7 "SM_AMIGA_ns_a2[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_a2_3 "SM_AMIGA_ns_i_a2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_a2_0_2 "SM_AMIGA_ns_a2_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_a2_2 "SM_AMIGA_ns_a2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_a2_1 "SM_AMIGA_ns_i_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_a2_0 "SM_AMIGA_ns_i_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un5_clk_030_i_a2 "state_machine.un5_clk_030_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_LDS_000_INT_8 "state_machine.LDS_000_INT_8") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_UDS_000_INT_8 "state_machine.UDS_000_INT_8") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_i_2 "cpu_est_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_i_3 "cpu_est_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_a4_0_1 "clk.cpu_est_11_0_a4_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_i_0 "cpu_est_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_a4_1 "clk.cpu_est_11_0_a4[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_o2_1 "SM_AMIGA_ns_i_o2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_o2_0 "SM_AMIGA_ns_i_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_7 "SM_AMIGA_ns[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_3 "SM_AMIGA_ns_i[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_2 "SM_AMIGA_ns[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_1 "SM_AMIGA_ns_i[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_0 "SM_AMIGA_ns_i[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_000_SYNC_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_a2_0_1 "SM_AMIGA_ns_i_a2_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_000_DD_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance DS_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance VPA_SYNC_1_sqmuxa_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_a4_1_3 "clk.cpu_est_11_0_a4_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance UDS_000_INT_0_sqmuxa_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance UDS_000_INT_0_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un2_clk_030_1_93 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_o4_3 "clk.cpu_est_11_0_o4[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_o4_1 "clk.cpu_est_11_0_o4[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_i_1 "cpu_est_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_i_o4_2 "clk.cpu_est_11_i_o4[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_i_2 "clk.cpu_est_11_i[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_a4_0_3 "clk.cpu_est_11_0_a4_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_a4_3 "clk.cpu_est_11_0_a4[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_a4_2_1 "clk.cpu_est_11_0_a4_2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_a4_1_1 "clk.cpu_est_11_0_a4_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un57_clk_000_d "state_machine.un57_clk_000_d") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename FPU_CS_INT_0_r "FPU_CS_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename FPU_CS_INT_0_m "FPU_CS_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename FPU_CS_INT_0_n "FPU_CS_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename FPU_CS_INT_0_p "FPU_CS_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename AS_000_INT_0_r "AS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AS_000_INT_0_m "AS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AS_000_INT_0_n "AS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AS_000_INT_0_p "AS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename VPA_SYNC_0_r "VPA_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename VPA_SYNC_0_m "VPA_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename VPA_SYNC_0_n "VPA_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename VPA_SYNC_0_p "VPA_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename AS_030_000_SYNC_0_r "AS_030_000_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AS_030_000_SYNC_0_m "AS_030_000_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AS_030_000_SYNC_0_n "AS_030_000_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AS_030_000_SYNC_0_p "AS_030_000_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename state_machine_un17_clk_030 "state_machine.un17_clk_030") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance N_102_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_000_INT_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_SYNC_1_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance VPA_SYNC_1_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un42_clk_030_i "state_machine.un42_clk_030_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_as_030_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_0 "cpu_est_0[0]") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance (rename state_machine_un13_clk_000_d_1 "state_machine.un13_clk_000_d_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_D_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_030_000_SYNC_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance CLK_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename state_machine_un1_clk_030 "state_machine.un1_clk_030") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un4_bgack_000 "state_machine.un4_bgack_000") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename A_i_19 "A_i[19]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_i_18 "A_i[18]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un6_bgack_000 "state_machine.un6_bgack_000") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un5_clk_030_i_a2 "state_machine.un5_clk_030_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_a2_1 "SM_AMIGA_ns_i_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_a2_0_2 "SM_AMIGA_ns_a2_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_000_DD_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename clk_un4_clk_000_dd_0_a2 "clk.un4_clk_000_dd_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_a2_0_1 "SM_AMIGA_ns_i_a2_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_1 "SM_AMIGA_ns_i[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_o2_1 "SM_AMIGA_ns_i_o2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_a4_1 "clk.cpu_est_11_0_a4[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_a4_1_1 "clk.cpu_est_11_0_a4_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_0 "cpu_est_0[0]") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) (instance (rename A_i_16 "A_i[16]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_030_0_2__r "IPL_030_0_2_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_030_0_2__m "IPL_030_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_2__n "IPL_030_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_2__p "IPL_030_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename IPL_030_0_1__r "IPL_030_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_030_0_1__m "IPL_030_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_1__n "IPL_030_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_1__p "IPL_030_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename IPL_030_0_0__r "IPL_030_0_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_030_0_0__m "IPL_030_0_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_0__n "IPL_030_0_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_0__p "IPL_030_0_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename BGACK_030_INT_0_r "BGACK_030_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename BGACK_030_INT_0_m "BGACK_030_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename BGACK_030_INT_0_n "BGACK_030_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename BGACK_030_INT_0_p "BGACK_030_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance N_98_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename DSACK_INT_0_1__r "DSACK_INT_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename DSACK_INT_0_1__m "DSACK_INT_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename DSACK_INT_0_1__n "DSACK_INT_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename DSACK_INT_0_1__p "DSACK_INT_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename BG_000_0_r "BG_000_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename BG_000_0_m "BG_000_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename BG_000_0_n "BG_000_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename BG_000_0_p "BG_000_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance DTACK_SYNC_1_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename DTACK_SYNC_0_r "DTACK_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename DTACK_SYNC_0_m "DTACK_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename DTACK_SYNC_0_n "DTACK_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename DTACK_SYNC_0_p "DTACK_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_a2_0_6 "SM_AMIGA_ns_i_a2_0[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_4 "SM_AMIGA_ns_i[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_5 "SM_AMIGA_ns[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_6 "SM_AMIGA_ns_i[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_o2_4 "SM_AMIGA_ns_i_o2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_o2_6 "SM_AMIGA_ns_i_o2[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DTACK_SYNC_1_sqmuxa_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_OUT_PRE_0 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance I_107 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance VMA_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DTACK_SYNC_1_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DSACK_INT_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename A_i_18 "A_i[18]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_19 "A_i[19]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename A_i_24 "A_i[24]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename A_i_25 "A_i[25]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename A_i_26 "A_i[26]") (viewRef prim (cellRef INV (libraryRef mach))) ) @@ -570,20 +538,40 @@ (instance (rename A_i_29 "A_i[29]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename A_i_30 "A_i[30]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename A_i_31 "A_i[31]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_a2_4 "SM_AMIGA_ns_i_a2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_a2_0_4 "SM_AMIGA_ns_i_a2_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_a2_5 "SM_AMIGA_ns_a2[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_a2_6 "SM_AMIGA_ns_i_a2[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename state_machine_un13_as_000_int_i "state_machine.un13_as_000_int_i") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance RST_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename CLK_CNT_i_0 "CLK_CNT_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance BGACK_030_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance CPU_SPACE_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance FPU_CS_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename BG_000_0_r "BG_000_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename BG_000_0_m "BG_000_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BG_000_0_n "BG_000_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BG_000_0_p "BG_000_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename BGACK_030_INT_0_r "BGACK_030_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename BGACK_030_INT_0_m "BGACK_030_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BGACK_030_INT_0_n "BGACK_030_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BGACK_030_INT_0_p "BGACK_030_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename cpu_est_0_1__r "cpu_est_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_0_1__m "cpu_est_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_1__n "cpu_est_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_1__p "cpu_est_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename IPL_030_0_0__r "IPL_030_0_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_0_0__m "IPL_030_0_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_0__n "IPL_030_0_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_0__p "IPL_030_0_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename IPL_030_0_1__r "IPL_030_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_0_1__m "IPL_030_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_1__n "IPL_030_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_1__p "IPL_030_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename IPL_030_0_2__r "IPL_030_0_2_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_0_2__m "IPL_030_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_2__n "IPL_030_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_2__p "IPL_030_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (net BGACK_030_INT (joined (portRef Q (instanceRef BGACK_030_INT)) - (portRef I0 (instanceRef BGACK_030_INT_i)) (portRef I0 (instanceRef BGACK_030_INT_0_n)) + (portRef I0 (instanceRef BGACK_030_INT_i)) (portRef OE (instanceRef AS_000)) (portRef I0 (instanceRef BGACK_030)) (portRef OE (instanceRef LDS_000)) @@ -597,18 +585,17 @@ )) (net (rename cpu_est_3 "cpu_est[3]") (joined (portRef Q (instanceRef cpu_est_3)) - (portRef I1 (instanceRef clk_cpu_est_11_0_a4_2_1)) + (portRef I0 (instanceRef cpu_est_0_3__n)) + (portRef I0 (instanceRef clk_cpu_est_11_0_a4_2_1)) (portRef I1 (instanceRef clk_cpu_est_11_0_a4_3)) (portRef I0 (instanceRef cpu_est_i_3)) - (portRef I0 (instanceRef cpu_est_0_3__n)) - (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_1_0)) + (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_1_1)) (portRef I0 (instanceRef E)) - (portRef D (instanceRef cpu_est_d_3)) )) (net VMA_INT (joined (portRef Q (instanceRef VMA_INT)) (portRef I0 (instanceRef VMA_INT_i)) - (portRef I0 (instanceRef VMA_INT_0_m)) + (portRef I0 (instanceRef VMA_INT_0_n)) (portRef I0 (instanceRef VMA)) )) (net GND (joined @@ -622,63 +609,53 @@ (portRef I1 (instanceRef clk_cpu_est_11_0_a4_1_1)) (portRef I0 (instanceRef clk_cpu_est_11_0_o4_3)) (portRef I0 (instanceRef cpu_est_i_0)) - (portRef I0 (instanceRef state_machine_un8_clk_000_d_3)) - (portRef I1 (instanceRef clk_cpu_est_11_i_a4_1_2)) - (portRef D (instanceRef cpu_est_d_0)) + (portRef I1 (instanceRef state_machine_un8_clk_000_d_1)) + (portRef I0 (instanceRef clk_cpu_est_11_i_a4_1_2)) )) (net (rename cpu_est_1 "cpu_est[1]") (joined (portRef Q (instanceRef cpu_est_1)) - (portRef I0 (instanceRef clk_cpu_est_11_i_o4_2)) - (portRef I0 (instanceRef cpu_est_i_1)) - (portRef I1 (instanceRef clk_cpu_est_11_0_o4_3)) (portRef I0 (instanceRef cpu_est_0_1__n)) + (portRef I1 (instanceRef clk_cpu_est_11_0_o4_3)) + (portRef I0 (instanceRef state_machine_un13_clk_000_d_2)) + (portRef I0 (instanceRef cpu_est_i_1)) (portRef I0 (instanceRef clk_cpu_est_11_i_a4_0_1_2)) - (portRef D (instanceRef cpu_est_d_1)) - )) - (net (rename cpu_est_d_0 "cpu_est_d[0]") (joined - (portRef Q (instanceRef cpu_est_d_0)) - (portRef I0 (instanceRef cpu_est_d_i_0)) - )) - (net (rename cpu_est_d_3 "cpu_est_d[3]") (joined - (portRef Q (instanceRef cpu_est_d_3)) - (portRef I0 (instanceRef cpu_est_d_i_3)) )) (net AS_000_INT (joined (portRef Q (instanceRef AS_000_INT)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_0)) (portRef I0 (instanceRef state_machine_un13_clk_000_d_1)) (portRef I0 (instanceRef AS_000_INT_0_m)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_0)) (portRef I0 (instanceRef AS_000_INT_i)) (portRef I0 (instanceRef AS_000)) )) (net AS_030_000_SYNC (joined (portRef Q (instanceRef AS_030_000_SYNC)) - (portRef I0 (instanceRef AS_030_000_SYNC_0_n)) (portRef I0 (instanceRef AS_030_000_SYNC_i)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_n)) )) (net DTACK_SYNC (joined (portRef Q (instanceRef DTACK_SYNC)) (portRef I0 (instanceRef DTACK_SYNC_0_m)) - (portRef I0 (instanceRef state_machine_un57_clk_000_d)) + (portRef I0 (instanceRef state_machine_un60_clk_000_d)) )) (net VPA_D (joined (portRef Q (instanceRef VPA_D)) (portRef I0 (instanceRef VPA_D_i)) - (portRef I1 (instanceRef DTACK_SYNC_1_sqmuxa_1_1)) + (portRef I1 (instanceRef DTACK_SYNC_1_sqmuxa_1_0)) )) (net VPA_SYNC (joined (portRef Q (instanceRef VPA_SYNC)) (portRef I0 (instanceRef VPA_SYNC_0_m)) - (portRef I1 (instanceRef state_machine_un57_clk_000_d)) + (portRef I1 (instanceRef state_machine_un60_clk_000_d)) )) (net CLK_000_D (joined (portRef Q (instanceRef CLK_000_D)) - (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa_1_0)) - (portRef I1 (instanceRef state_machine_un13_clk_000_d_1)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_0)) - (portRef I0 (instanceRef SM_AMIGA_ns_a2_2)) - (portRef I0 (instanceRef clk_un3_clk_000_dd_0_a2)) + (portRef I0 (instanceRef clk_un4_clk_000_dd_0_a2)) + (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1_0)) (portRef I0 (instanceRef CLK_000_D_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_0)) + (portRef I1 (instanceRef state_machine_un13_clk_000_d_1)) + (portRef I0 (instanceRef SM_AMIGA_ns_a2_2)) (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_1_0)) (portRef D (instanceRef CLK_000_DD)) )) @@ -698,22 +675,13 @@ (portRef I0 (instanceRef AVEC)) (portRef I0 (instanceRef DSACK_0)) )) - (net (rename cpu_est_d_1 "cpu_est_d[1]") (joined - (portRef Q (instanceRef cpu_est_d_1)) - (portRef I1 (instanceRef state_machine_un13_clk_000_d_4_1)) - )) - (net (rename cpu_est_d_2 "cpu_est_d[2]") (joined - (portRef Q (instanceRef cpu_est_d_2)) - (portRef I1 (instanceRef state_machine_un13_clk_000_d_4)) - )) (net (rename cpu_est_2 "cpu_est[2]") (joined (portRef Q (instanceRef cpu_est_2)) - (portRef I1 (instanceRef clk_cpu_est_11_i_o4_2)) - (portRef I0 (instanceRef cpu_est_i_2)) (portRef I0 (instanceRef cpu_est_0_2__n)) - (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1_0)) - (portRef I1 (instanceRef state_machine_un8_clk_000_d_3)) - (portRef D (instanceRef cpu_est_d_2)) + (portRef I0 (instanceRef cpu_est_i_2)) + (portRef I1 (instanceRef state_machine_un13_clk_000_d_2)) + (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1_1)) + (portRef I0 (instanceRef state_machine_un8_clk_000_d_2)) )) (net (rename CLK_CNT_0 "CLK_CNT[0]") (joined (portRef Q (instanceRef CLK_CNT_0)) @@ -722,8 +690,8 @@ )) (net (rename SM_AMIGA_6 "SM_AMIGA[6]") (joined (portRef Q (instanceRef SM_AMIGA_6)) - (portRef I0 (instanceRef SM_AMIGA_i_6)) (portRef I1 (instanceRef SM_AMIGA_ns_a2_0_2)) + (portRef I0 (instanceRef SM_AMIGA_i_6)) (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa_1_2)) )) (net (rename SM_AMIGA_7 "SM_AMIGA[7]") (joined @@ -741,23 +709,10 @@ (portRef I0 (instanceRef LDS_000_INT_0_m)) (portRef I0 (instanceRef LDS_000)) )) - (net (rename clk_RISING_CLK_AMIGA_1 "clk.RISING_CLK_AMIGA_1") (joined - (portRef O (instanceRef clk_RISING_CLK_AMIGA_1)) - (portRef D (instanceRef RISING_CLK_AMIGA)) - )) - (net RISING_CLK_AMIGA (joined - (portRef Q (instanceRef RISING_CLK_AMIGA)) - (portRef I1 (instanceRef IPL_030_0_0__m)) - (portRef I0 (instanceRef IPL_030_0_0__r)) - (portRef I1 (instanceRef IPL_030_0_1__m)) - (portRef I0 (instanceRef IPL_030_0_1__r)) - (portRef I1 (instanceRef IPL_030_0_2__m)) - (portRef I0 (instanceRef IPL_030_0_2__r)) - (portRef I0 (instanceRef RISING_CLK_AMIGA_i)) - )) - (net (rename state_machine_un57_clk_000_d "state_machine.un57_clk_000_d") (joined - (portRef O (instanceRef state_machine_un57_clk_000_d_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_a2_0_5)) + (net (rename state_machine_un1_clk_030 "state_machine.un1_clk_030") (joined + (portRef O (instanceRef state_machine_un1_clk_030_i)) + (portRef I1 (instanceRef BG_000_0_m)) + (portRef I0 (instanceRef BG_000_0_r)) )) (net (rename SM_AMIGA_1 "SM_AMIGA[1]") (joined (portRef Q (instanceRef SM_AMIGA_1)) @@ -778,9 +733,14 @@ (portRef I0 (instanceRef SM_AMIGA_i_4)) (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa_2)) )) + (net (rename state_machine_un6_bgack_000 "state_machine.un6_bgack_000") (joined + (portRef O (instanceRef state_machine_un6_bgack_000_i)) + (portRef I1 (instanceRef BGACK_030_INT_0_m)) + (portRef I0 (instanceRef BGACK_030_INT_0_r)) + )) (net (rename SM_AMIGA_3 "SM_AMIGA[3]") (joined (portRef Q (instanceRef SM_AMIGA_3)) - (portRef I1 (instanceRef DTACK_SYNC_1_sqmuxa_1_0)) + (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_1_0)) (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_4)) (portRef I0 (instanceRef SM_AMIGA_i_3)) (portRef I1 (instanceRef SM_AMIGA_ns_a2_0_1_5)) @@ -789,20 +749,24 @@ (portRef O (instanceRef state_machine_un13_as_000_int)) (portRef I0 (instanceRef state_machine_un13_as_000_int_i)) )) + (net un1_bg_030 (joined + (portRef O (instanceRef un1_bg_030_i)) + (portRef I0 (instanceRef BG_000_0_m)) + )) (net (rename SM_AMIGA_5 "SM_AMIGA[5]") (joined (portRef Q (instanceRef SM_AMIGA_5)) - (portRef I1 (instanceRef SM_AMIGA_ns_a2_2)) (portRef I0 (instanceRef SM_AMIGA_i_5)) + (portRef I1 (instanceRef SM_AMIGA_ns_a2_2)) )) (net (rename SM_AMIGA_2 "SM_AMIGA[2]") (joined (portRef Q (instanceRef SM_AMIGA_2)) - (portRef I1 (instanceRef SM_AMIGA_ns_a2_5)) (portRef I0 (instanceRef SM_AMIGA_i_2)) + (portRef I1 (instanceRef SM_AMIGA_ns_a2_5)) )) (net (rename SM_AMIGA_0 "SM_AMIGA[0]") (joined (portRef Q (instanceRef SM_AMIGA_0)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_o2_0)) (portRef I0 (instanceRef SM_AMIGA_ns_a2_7)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_o2_0)) )) (net N_1 (joined (portRef O (instanceRef UDS_000_INT_0_p)) @@ -821,60 +785,60 @@ (portRef D (instanceRef FPU_CS_INT)) )) (net N_5 (joined - (portRef O (instanceRef AS_000_INT_0_p)) - (portRef D (instanceRef AS_000_INT)) - )) - (net N_6 (joined - (portRef O (instanceRef VPA_SYNC_0_p)) - (portRef D (instanceRef VPA_SYNC)) - )) - (net N_7 (joined (portRef O (instanceRef AS_030_000_SYNC_0_p)) (portRef D (instanceRef AS_030_000_SYNC)) )) - (net N_8 (joined - (portRef O (instanceRef VMA_INT_0_p)) - (portRef D (instanceRef VMA_INT)) + (net N_6 (joined + (portRef O (instanceRef AS_000_INT_0_p)) + (portRef D (instanceRef AS_000_INT)) )) - (net N_9 (joined + (net N_7 (joined + (portRef O (instanceRef VPA_SYNC_0_p)) + (portRef D (instanceRef VPA_SYNC)) + )) + (net N_8 (joined (portRef O (instanceRef BG_000_0_p)) (portRef D (instanceRef BG_000DFFSH)) )) - (net N_10 (joined + (net N_9 (joined (portRef O (instanceRef DSACK_INT_0_1__p)) (portRef D (instanceRef DSACK_INT_1)) )) + (net N_10 (joined + (portRef O (instanceRef VMA_INT_0_p)) + (portRef D (instanceRef VMA_INT)) + )) (net N_11 (joined - (portRef O (instanceRef IPL_030_0_0__p)) - (portRef D (instanceRef IPL_030DFFSH_0)) + (portRef O (instanceRef BGACK_030_INT_0_p)) + (portRef D (instanceRef BGACK_030_INT)) )) (net N_12 (joined - (portRef O (instanceRef IPL_030_0_1__p)) - (portRef D (instanceRef IPL_030DFFSH_1)) - )) - (net N_13 (joined - (portRef O (instanceRef IPL_030_0_2__p)) - (portRef D (instanceRef IPL_030DFFSH_2)) - )) - (net N_14 (joined (portRef O (instanceRef cpu_est_0_0)) (portRef D (instanceRef cpu_est_0)) )) - (net N_15 (joined + (net N_13 (joined (portRef O (instanceRef cpu_est_0_1__p)) (portRef D (instanceRef cpu_est_1)) )) - (net N_16 (joined + (net N_14 (joined (portRef O (instanceRef cpu_est_0_2__p)) (portRef D (instanceRef cpu_est_2)) )) - (net N_17 (joined + (net N_15 (joined (portRef O (instanceRef cpu_est_0_3__p)) (portRef D (instanceRef cpu_est_3)) )) + (net N_16 (joined + (portRef O (instanceRef IPL_030_0_0__p)) + (portRef D (instanceRef IPL_030DFFSH_0)) + )) + (net N_17 (joined + (portRef O (instanceRef IPL_030_0_1__p)) + (portRef D (instanceRef IPL_030DFFSH_1)) + )) (net N_18 (joined - (portRef O (instanceRef BGACK_030_INT_0_p)) - (portRef D (instanceRef BGACK_030_INT)) + (portRef O (instanceRef IPL_030_0_2__p)) + (portRef D (instanceRef IPL_030DFFSH_2)) )) (net N_19 (joined (portRef O (instanceRef CLK_OUT_PRE_0)) @@ -892,6 +856,38 @@ (portRef O (instanceRef SM_AMIGA_ns_i_7)) (portRef D (instanceRef SM_AMIGA_0)) )) + (net (rename clk_un4_clk_000_dd "clk.un4_clk_000_dd") (joined + (portRef O (instanceRef clk_un4_clk_000_dd_0_a2)) + (portRef I1 (instanceRef IPL_030_0_2__m)) + (portRef I0 (instanceRef IPL_030_0_2__r)) + (portRef I1 (instanceRef IPL_030_0_1__m)) + (portRef I0 (instanceRef IPL_030_0_1__r)) + (portRef I1 (instanceRef IPL_030_0_0__m)) + (portRef I0 (instanceRef IPL_030_0_0__r)) + (portRef I1 (instanceRef cpu_est_0_1__m)) + (portRef I0 (instanceRef cpu_est_0_1__r)) + (portRef I0 (instanceRef cpu_est_0_0)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_0_1)) + (portRef I1 (instanceRef cpu_est_0_2__m)) + (portRef I0 (instanceRef cpu_est_0_2__r)) + (portRef I1 (instanceRef cpu_est_0_3__m)) + (portRef I0 (instanceRef cpu_est_0_3__r)) + (portRef I0 (instanceRef clk_un4_clk_000_dd_i)) + (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa_1)) + )) + (net (rename clk_cpu_est_11_1 "clk.cpu_est_11[1]") (joined + (portRef O (instanceRef clk_cpu_est_11_0_i_1)) + (portRef I0 (instanceRef cpu_est_0_1__m)) + )) + (net (rename state_machine_un42_clk_030 "state_machine.un42_clk_030") (joined + (portRef O (instanceRef state_machine_un42_clk_030)) + (portRef I1 (instanceRef un1_as_030_3)) + (portRef I0 (instanceRef state_machine_un42_clk_030_i)) + )) + (net N_102 (joined + (portRef O (instanceRef SM_AMIGA_ns_a2_0_2)) + (portRef I0 (instanceRef N_102_i)) + )) (net N_98 (joined (portRef O (instanceRef un1_DSACK_INT_0_sqmuxa_i_a2)) (portRef I0 (instanceRef N_98_i)) @@ -900,175 +896,57 @@ (portRef O (instanceRef state_machine_un5_clk_030_i_a2)) (portRef I0 (instanceRef N_97_i)) )) - (net N_104 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_a2_4)) - (portRef I0 (instanceRef N_104_i)) + (net N_100 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_a2_1)) + (portRef I0 (instanceRef N_100_i)) )) - (net N_93 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_o2_i_4)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_4)) + (net N_92 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_o2_i_1)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_1)) )) - (net N_105 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_a2_0_4)) - (portRef I0 (instanceRef N_105_i)) + (net N_112 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_a2_0_1)) + (portRef I0 (instanceRef SM_AMIGA_ns_a2_0_2)) + (portRef I0 (instanceRef N_112_i)) )) - (net N_106 (joined - (portRef O (instanceRef SM_AMIGA_ns_a2_5)) - (portRef I0 (instanceRef N_106_i)) + (net N_127 (joined + (portRef O (instanceRef clk_cpu_est_11_0_a4_1)) + (portRef I0 (instanceRef N_127_i)) )) - (net N_108 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_a2_6)) - (portRef I0 (instanceRef N_108_i)) + (net N_125 (joined + (portRef O (instanceRef clk_cpu_est_11_0_o4_i_1)) + (portRef I0 (instanceRef clk_cpu_est_11_0_a4_1)) )) - (net N_94 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_o2_i_6)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_6)) + (net N_128 (joined + (portRef O (instanceRef clk_cpu_est_11_0_a4_0_1)) + (portRef I0 (instanceRef N_128_i)) )) - (net N_109 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_a2_0_6)) - (portRef I0 (instanceRef N_109_i)) + (net N_129 (joined + (portRef O (instanceRef clk_cpu_est_11_0_a4_1_1)) + (portRef I0 (instanceRef N_129_i)) )) - (net N_107 (joined - (portRef O (instanceRef SM_AMIGA_ns_a2_0_5)) - (portRef I0 (instanceRef N_107_i)) + (net N_130 (joined + (portRef O (instanceRef clk_cpu_est_11_0_a4_2_1)) + (portRef I0 (instanceRef N_130_i)) + )) + (net N_168 (joined + (portRef O (instanceRef un8_ciin)) + (portRef OE (instanceRef CIIN)) + )) + (net N_171 (joined + (portRef O (instanceRef un4_ciin)) + (portRef I0 (instanceRef CIIN)) )) (net N_135_1 (joined (portRef O (instanceRef VPA_SYNC_1_sqmuxa_3)) (portRef I0 (instanceRef clk_cpu_est_11_0_a4_1_3)) (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_2)) )) - (net VPA_SYNC_1_sqmuxa_1_0 (joined - (portRef O (instanceRef DTACK_SYNC_1_sqmuxa_1_0)) - (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_3_0)) - (portRef I1 (instanceRef DTACK_SYNC_1_sqmuxa)) - )) - (net N_167 (joined - (portRef O (instanceRef un8_ciin)) - (portRef OE (instanceRef CIIN)) - )) - (net N_170 (joined - (portRef O (instanceRef un4_ciin)) - (portRef I0 (instanceRef CIIN)) - )) - (net (rename state_machine_un42_clk_030 "state_machine.un42_clk_030") (joined - (portRef O (instanceRef state_machine_un42_clk_030)) - (portRef I1 (instanceRef un1_as_030_2)) - (portRef I0 (instanceRef state_machine_un42_clk_030_i)) - )) - (net DTACK_SYNC_1_sqmuxa (joined - (portRef O (instanceRef DTACK_SYNC_1_sqmuxa)) - (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa_i)) - )) - (net VPA_SYNC_1_sqmuxa (joined - (portRef O (instanceRef VPA_SYNC_1_sqmuxa)) - (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_i)) - )) - (net un1_bg_030 (joined - (portRef O (instanceRef un1_bg_030_i)) - (portRef I0 (instanceRef BG_000_0_m)) - )) - (net DTACK_SYNC_1_sqmuxa_1 (joined - (portRef O (instanceRef DTACK_SYNC_1_sqmuxa_1)) - (portRef I1 (instanceRef DTACK_SYNC_0_m)) - (portRef I0 (instanceRef DTACK_SYNC_0_r)) - )) - (net DSACK_INT_1_sqmuxa (joined - (portRef O (instanceRef DSACK_INT_1_sqmuxa)) - (portRef I1 (instanceRef DSACK_INT_0_1__m)) - (portRef I0 (instanceRef DSACK_INT_0_1__r)) - )) - (net (rename state_machine_un1_clk_030 "state_machine.un1_clk_030") (joined - (portRef O (instanceRef state_machine_un1_clk_030_i)) - (portRef I1 (instanceRef BG_000_0_m)) - (portRef I0 (instanceRef BG_000_0_r)) - )) - (net (rename state_machine_un4_bgack_000 "state_machine.un4_bgack_000") (joined - (portRef O (instanceRef state_machine_un4_bgack_000_i)) - (portRef I1 (instanceRef BGACK_030_INT_0_m)) - (portRef I0 (instanceRef BGACK_030_INT_0_r)) - )) - (net un1_as_030_2 (joined - (portRef O (instanceRef un1_as_030_2_i)) - (portRef I0 (instanceRef FPU_CS_INT_0_m)) - )) - (net (rename state_machine_un17_clk_030 "state_machine.un17_clk_030") (joined - (portRef O (instanceRef state_machine_un17_clk_030_i)) - (portRef I1 (instanceRef AS_030_000_SYNC_0_m)) - (portRef I0 (instanceRef AS_030_000_SYNC_0_r)) - (portRef I1 (instanceRef FPU_CS_INT_0_m)) - (portRef I0 (instanceRef FPU_CS_INT_0_r)) - )) - (net N_102 (joined - (portRef O (instanceRef SM_AMIGA_ns_a2_0_2)) - (portRef I0 (instanceRef N_102_i)) - )) - (net AS_000_INT_1_sqmuxa (joined - (portRef O (instanceRef AS_000_INT_1_sqmuxa)) - (portRef I1 (instanceRef AS_000_INT_0_m)) - (portRef I0 (instanceRef AS_000_INT_0_r)) - )) - (net VPA_SYNC_1_sqmuxa_1 (joined - (portRef O (instanceRef VPA_SYNC_1_sqmuxa_1)) - (portRef I1 (instanceRef VPA_SYNC_0_m)) - (portRef I0 (instanceRef VPA_SYNC_0_r)) - )) - (net (rename state_machine_AS_030_000_SYNC_3 "state_machine.AS_030_000_SYNC_3") (joined - (portRef O (instanceRef state_machine_AS_030_000_SYNC_3_i)) - (portRef I0 (instanceRef AS_030_000_SYNC_0_m)) - )) - (net (rename clk_un3_clk_000_dd "clk.un3_clk_000_dd") (joined - (portRef O (instanceRef clk_un3_clk_000_dd_0_a2)) - (portRef I0 (instanceRef cpu_est_0_0)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_0_1)) - (portRef I1 (instanceRef cpu_est_0_1__m)) - (portRef I0 (instanceRef cpu_est_0_1__r)) - (portRef I1 (instanceRef cpu_est_0_2__m)) - (portRef I0 (instanceRef cpu_est_0_2__r)) - (portRef I1 (instanceRef cpu_est_0_3__m)) - (portRef I0 (instanceRef cpu_est_0_3__r)) - (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa_1)) - )) - (net (rename state_machine_un31_clk_000_d "state_machine.un31_clk_000_d") (joined - (portRef O (instanceRef state_machine_un31_clk_000_d_i_0)) - (portRef I1 (instanceRef state_machine_LDS_000_INT_8)) - )) - (net UDS_000_INT_0_sqmuxa (joined - (portRef O (instanceRef UDS_000_INT_0_sqmuxa)) - (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_i)) - )) - (net (rename state_machine_un13_clk_000_d "state_machine.un13_clk_000_d") (joined - (portRef O (instanceRef state_machine_un13_clk_000_d)) - (portRef I0 (instanceRef state_machine_un13_clk_000_d_i)) - )) - (net (rename state_machine_un13_clk_000_d_4 "state_machine.un13_clk_000_d_4") (joined - (portRef O (instanceRef state_machine_un13_clk_000_d_4)) - (portRef I0 (instanceRef VMA_INT_0_n)) - (portRef I1 (instanceRef state_machine_un13_clk_000_d)) - )) - (net (rename state_machine_un13_clk_000_d_1 "state_machine.un13_clk_000_d_1") (joined - (portRef O (instanceRef state_machine_un13_clk_000_d_1)) - (portRef I0 (instanceRef state_machine_un13_clk_000_d_1_i)) - (portRef I0 (instanceRef state_machine_un13_clk_000_d_4_1)) - )) - (net (rename state_machine_un8_clk_000_d "state_machine.un8_clk_000_d") (joined - (portRef O (instanceRef state_machine_un8_clk_000_d)) - (portRef I0 (instanceRef state_machine_un8_clk_000_d_i)) - )) - (net UDS_000_INT_0_sqmuxa_1 (joined - (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1)) - (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_1_i)) - )) - (net N_132 (joined - (portRef O (instanceRef clk_cpu_est_11_i_a4_0_2)) - (portRef I0 (instanceRef N_132_i)) - )) - (net N_131 (joined - (portRef O (instanceRef clk_cpu_est_11_i_a4_2)) - (portRef I0 (instanceRef N_131_i)) - )) - (net N_124 (joined - (portRef O (instanceRef clk_cpu_est_11_i_o4_i_2)) - (portRef I0 (instanceRef clk_cpu_est_11_i_a4_1_2)) + (net (rename state_machine_un13_clk_000_d_2 "state_machine.un13_clk_000_d_2") (joined + (portRef O (instanceRef state_machine_un13_clk_000_d_2)) + (portRef I1 (instanceRef clk_cpu_est_11_0_a4_2_1)) + (portRef I0 (instanceRef state_machine_un13_clk_000_d_2_i)) + (portRef I1 (instanceRef state_machine_un13_clk_000_d_2_0)) )) (net (rename clk_cpu_est_11_3 "clk.cpu_est_11[3]") (joined (portRef O (instanceRef clk_cpu_est_11_0_i_3)) @@ -1086,71 +964,38 @@ (portRef O (instanceRef clk_cpu_est_11_0_a4_0_3)) (portRef I0 (instanceRef N_134_i)) )) - (net (rename clk_cpu_est_11_1 "clk.cpu_est_11[1]") (joined - (portRef O (instanceRef clk_cpu_est_11_0_i_1)) - (portRef I0 (instanceRef cpu_est_0_1__m)) + (net N_132 (joined + (portRef O (instanceRef clk_cpu_est_11_i_a4_0_2)) + (portRef I0 (instanceRef N_132_i)) )) - (net N_130 (joined - (portRef O (instanceRef clk_cpu_est_11_0_a4_2_1)) - (portRef I0 (instanceRef N_130_i)) - )) - (net N_128 (joined - (portRef O (instanceRef clk_cpu_est_11_0_a4_0_1)) - (portRef I0 (instanceRef N_128_i)) - )) - (net N_145 (joined - (portRef O (instanceRef un2_clk_030_1_93)) - (portRef I1 (instanceRef un2_clk_030_1)) - (portRef I0 (instanceRef N_145_i)) - )) - (net N_127 (joined - (portRef O (instanceRef clk_cpu_est_11_0_a4_1)) - (portRef I0 (instanceRef N_127_i)) - )) - (net N_129 (joined - (portRef O (instanceRef clk_cpu_est_11_0_a4_1_1)) - (portRef I0 (instanceRef N_129_i)) + (net N_131 (joined + (portRef O (instanceRef clk_cpu_est_11_i_a4_2)) + (portRef I0 (instanceRef N_131_i)) )) (net N_126 (joined (portRef O (instanceRef clk_cpu_est_11_0_o4_i_3)) (portRef I0 (instanceRef clk_cpu_est_11_0_a4_3)) )) - (net N_125 (joined - (portRef O (instanceRef clk_cpu_est_11_0_o4_i_1)) - (portRef I0 (instanceRef clk_cpu_est_11_0_a4_1)) + (net (rename state_machine_un34_clk_000_d "state_machine.un34_clk_000_d") (joined + (portRef O (instanceRef state_machine_un34_clk_000_d_i_0)) + (portRef I1 (instanceRef state_machine_LDS_000_INT_8)) )) - (net N_92 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_o2_i_1)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_1)) + (net UDS_000_INT_0_sqmuxa (joined + (portRef O (instanceRef UDS_000_INT_0_sqmuxa)) + (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_i)) )) - (net N_91 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_o2_i_0)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_0)) + (net UDS_000_INT_0_sqmuxa_1 (joined + (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1)) + (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_1_i)) )) - (net N_110 (joined - (portRef O (instanceRef SM_AMIGA_ns_a2_7)) - (portRef I0 (instanceRef N_110_i)) + (net (rename state_machine_AS_030_000_SYNC_3 "state_machine.AS_030_000_SYNC_3") (joined + (portRef O (instanceRef state_machine_AS_030_000_SYNC_3_i)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_m)) )) - (net N_103 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_a2_3)) - (portRef I0 (instanceRef N_103_i)) - )) - (net N_101 (joined - (portRef O (instanceRef SM_AMIGA_ns_a2_2)) - (portRef I0 (instanceRef N_101_i)) - )) - (net N_100 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_a2_1)) - (portRef I0 (instanceRef N_100_i)) - )) - (net N_112 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_a2_0_1)) - (portRef I0 (instanceRef SM_AMIGA_ns_a2_0_2)) - (portRef I0 (instanceRef N_112_i)) - )) - (net N_99 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_a2_0)) - (portRef I0 (instanceRef N_99_i)) + (net N_145 (joined + (portRef O (instanceRef un1_as_030_4_93)) + (portRef I1 (instanceRef un1_as_030_4)) + (portRef I0 (instanceRef N_145_i)) )) (net (rename state_machine_LDS_000_INT_8 "state_machine.LDS_000_INT_8") (joined (portRef O (instanceRef state_machine_LDS_000_INT_8_i)) @@ -1160,42 +1005,146 @@ (portRef O (instanceRef state_machine_UDS_000_INT_8_i)) (portRef I0 (instanceRef UDS_000_INT_0_n)) )) - (net un2_clk_030_1 (joined - (portRef O (instanceRef un2_clk_030_1)) - (portRef I1 (instanceRef UDS_000_INT_0_m)) - (portRef I0 (instanceRef UDS_000_INT_0_r)) + (net un1_as_030_4 (joined + (portRef O (instanceRef un1_as_030_4)) (portRef I1 (instanceRef LDS_000_INT_0_m)) (portRef I0 (instanceRef LDS_000_INT_0_r)) + (portRef I1 (instanceRef UDS_000_INT_0_m)) + (portRef I0 (instanceRef UDS_000_INT_0_r)) )) - (net VMA_INT_1_sqmuxa (joined - (portRef O (instanceRef VMA_INT_1_sqmuxa)) + (net un1_as_030_3 (joined + (portRef O (instanceRef un1_as_030_3_i)) + (portRef I0 (instanceRef FPU_CS_INT_0_m)) + )) + (net DSACK_INT_1_sqmuxa (joined + (portRef O (instanceRef DSACK_INT_1_sqmuxa)) + (portRef I1 (instanceRef DSACK_INT_0_1__m)) + (portRef I0 (instanceRef DSACK_INT_0_1__r)) + )) + (net (rename state_machine_un17_clk_030 "state_machine.un17_clk_030") (joined + (portRef O (instanceRef state_machine_un17_clk_030_i)) + (portRef I1 (instanceRef FPU_CS_INT_0_m)) + (portRef I0 (instanceRef FPU_CS_INT_0_r)) + (portRef I1 (instanceRef AS_030_000_SYNC_0_m)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_r)) + )) + (net (rename state_machine_un60_clk_000_d "state_machine.un60_clk_000_d") (joined + (portRef O (instanceRef state_machine_un60_clk_000_d_i_0)) + (portRef I1 (instanceRef SM_AMIGA_ns_a2_0_5)) + )) + (net DTACK_SYNC_1_sqmuxa (joined + (portRef O (instanceRef DTACK_SYNC_1_sqmuxa)) + (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa_i)) + )) + (net DTACK_SYNC_1_sqmuxa_1 (joined + (portRef O (instanceRef DTACK_SYNC_1_sqmuxa_1)) + (portRef I1 (instanceRef DTACK_SYNC_0_m)) + (portRef I0 (instanceRef DTACK_SYNC_0_r)) + )) + (net VPA_SYNC_1_sqmuxa (joined + (portRef O (instanceRef VPA_SYNC_1_sqmuxa)) + (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_i)) + )) + (net VPA_SYNC_1_sqmuxa_1 (joined + (portRef O (instanceRef VPA_SYNC_1_sqmuxa_1)) + (portRef I1 (instanceRef VPA_SYNC_0_m)) + (portRef I0 (instanceRef VPA_SYNC_0_r)) + )) + (net N_103 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_a2_3)) + (portRef I0 (instanceRef N_103_i)) + )) + (net N_104 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_a2_4)) + (portRef I0 (instanceRef N_104_i)) + )) + (net N_93 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_o2_i_4)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_4)) + )) + (net N_105 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_a2_0_4)) + (portRef I0 (instanceRef N_105_i)) + )) + (net VPA_SYNC_1_sqmuxa_1_0 (joined + (portRef O (instanceRef VPA_SYNC_1_sqmuxa_1_0)) + (portRef I1 (instanceRef DTACK_SYNC_1_sqmuxa)) + (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_3_0)) + )) + (net (rename state_machine_un15_clk_000_d "state_machine.un15_clk_000_d") (joined + (portRef O (instanceRef state_machine_un15_clk_000_d_i)) (portRef I1 (instanceRef VMA_INT_0_m)) (portRef I0 (instanceRef VMA_INT_0_r)) )) + (net (rename state_machine_un13_clk_000_d "state_machine.un13_clk_000_d") (joined + (portRef O (instanceRef state_machine_un13_clk_000_d)) + (portRef I0 (instanceRef state_machine_un13_clk_000_d_i)) + )) + (net (rename state_machine_un8_clk_000_d "state_machine.un8_clk_000_d") (joined + (portRef O (instanceRef state_machine_un8_clk_000_d)) + (portRef I0 (instanceRef state_machine_un8_clk_000_d_i)) + )) + (net (rename state_machine_un8_clk_000_d_1 "state_machine.un8_clk_000_d_1") (joined + (portRef O (instanceRef state_machine_un8_clk_000_d_1)) + (portRef I0 (instanceRef state_machine_un8_clk_000_d_1_i)) + (portRef I0 (instanceRef state_machine_un8_clk_000_d_1_0)) + )) + (net (rename state_machine_un13_clk_000_d_1 "state_machine.un13_clk_000_d_1") (joined + (portRef O (instanceRef state_machine_un13_clk_000_d_1)) + (portRef I0 (instanceRef state_machine_un13_clk_000_d_1_i)) + (portRef I0 (instanceRef state_machine_un13_clk_000_d_2_0)) + )) + (net N_107 (joined + (portRef O (instanceRef SM_AMIGA_ns_a2_0_5)) + (portRef I0 (instanceRef N_107_i)) + )) + (net N_94 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_o2_i_6)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_6)) + )) + (net N_91 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_o2_i_0)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_0)) + )) + (net N_110 (joined + (portRef O (instanceRef SM_AMIGA_ns_a2_7)) + (portRef I0 (instanceRef N_110_i)) + )) + (net N_108 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_a2_6)) + (portRef I0 (instanceRef N_108_i)) + )) + (net N_109 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_a2_0_6)) + (portRef I0 (instanceRef N_109_i)) + )) + (net N_106 (joined + (portRef O (instanceRef SM_AMIGA_ns_a2_5)) + (portRef I0 (instanceRef N_106_i)) + )) + (net N_101 (joined + (portRef O (instanceRef SM_AMIGA_ns_a2_2)) + (portRef I0 (instanceRef N_101_i)) + )) + (net N_99 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_a2_0)) + (portRef I0 (instanceRef N_99_i)) + )) + (net AS_000_INT_1_sqmuxa (joined + (portRef O (instanceRef AS_000_INT_1_sqmuxa)) + (portRef I1 (instanceRef AS_000_INT_0_m)) + (portRef I0 (instanceRef AS_000_INT_0_r)) + )) (net RW_i (joined (portRef O (instanceRef RW_i)) (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_2)) (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR)) )) - (net (rename cpu_est_d_i_3 "cpu_est_d_i[3]") (joined - (portRef O (instanceRef cpu_est_d_i_3)) - (portRef I1 (instanceRef state_machine_un13_clk_000_d_1_0)) - )) - (net (rename cpu_est_d_i_0 "cpu_est_d_i[0]") (joined - (portRef O (instanceRef cpu_est_d_i_0)) - (portRef I0 (instanceRef state_machine_un13_clk_000_d_1_0)) - )) - (net CLK_000_D_i (joined - (portRef O (instanceRef CLK_000_D_i)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_6)) - (portRef I0 (instanceRef SM_AMIGA_ns_a2_5)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_4)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_3)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_1)) - (portRef I0 (instanceRef clk_RISING_CLK_AMIGA_1)) - (portRef I0 (instanceRef SM_AMIGA_ns_a2_0_1_5)) - (portRef I0 (instanceRef un1_DSACK_INT_0_sqmuxa_i_a2_1)) - (portRef I0 (instanceRef state_machine_un8_clk_000_d_2)) + (net N_102_i (joined + (portRef O (instanceRef N_102_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_2)) + (portRef I0 (instanceRef AS_000_INT_0_n)) + (portRef I1 (instanceRef AS_000_INT_1_sqmuxa)) )) (net AS_000_INT_i (joined (portRef O (instanceRef AS_000_INT_i)) @@ -1205,164 +1154,159 @@ (portRef O (instanceRef I_106)) (portRef I1 (instanceRef state_machine_un13_as_000_int)) )) - (net (rename state_machine_un13_clk_000_d_i "state_machine.un13_clk_000_d_i") (joined - (portRef O (instanceRef state_machine_un13_clk_000_d_i)) - (portRef I1 (instanceRef VMA_INT_1_sqmuxa)) - )) - (net (rename state_machine_un8_clk_000_d_i "state_machine.un8_clk_000_d_i") (joined - (portRef O (instanceRef state_machine_un8_clk_000_d_i)) - (portRef I0 (instanceRef VMA_INT_1_sqmuxa)) - )) (net AS_030_i (joined (portRef O (instanceRef AS_030_i)) + (portRef I0 (instanceRef state_machine_un17_clk_030)) (portRef I0 (instanceRef DSACK_INT_1_sqmuxa)) + (portRef I0 (instanceRef un1_as_030_3)) + (portRef I0 (instanceRef un1_as_030_4)) (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa_1)) - (portRef I0 (instanceRef un1_as_030_2)) (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1)) (portRef I0 (instanceRef AS_000_INT_1_sqmuxa)) - (portRef I0 (instanceRef state_machine_un17_clk_030)) - (portRef I0 (instanceRef un2_clk_030_1)) (portRef I0 (instanceRef state_machine_AS_030_000_SYNC_3_1)) )) - (net (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (joined - (portRef O (instanceRef SM_AMIGA_i_6)) - (portRef I0 (instanceRef state_machine_un5_clk_030_i_a2)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_1)) - )) (net (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (joined (portRef O (instanceRef SM_AMIGA_i_7)) (portRef I1 (instanceRef state_machine_un5_clk_030_i_a2)) (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_0)) )) - (net (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (joined - (portRef O (instanceRef SM_AMIGA_i_5)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_3)) + (net CLK_000_D_i (joined + (portRef O (instanceRef CLK_000_D_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_1)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_3)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_4)) + (portRef I0 (instanceRef state_machine_un8_clk_000_d_1)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_6)) + (portRef I0 (instanceRef SM_AMIGA_ns_a2_5)) + (portRef I0 (instanceRef un1_DSACK_INT_0_sqmuxa_i_a2_1)) + (portRef I0 (instanceRef SM_AMIGA_ns_a2_0_1_5)) + )) + (net (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (joined + (portRef O (instanceRef SM_AMIGA_i_2)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_0_6)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_o2_6)) + )) + (net (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (joined + (portRef O (instanceRef SM_AMIGA_i_1)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_0_6)) + )) + (net (rename state_machine_un13_clk_000_d_1_i "state_machine.un13_clk_000_d_1_i") (joined + (portRef O (instanceRef state_machine_un13_clk_000_d_1_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_a2_7)) + )) + (net VPA_D_i (joined + (portRef O (instanceRef VPA_D_i)) + (portRef I1 (instanceRef state_machine_un8_clk_000_d_1_0)) + (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_3_0)) + )) + (net VMA_INT_i (joined + (portRef O (instanceRef VMA_INT_i)) + (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_2)) + )) + (net (rename cpu_est_i_0 "cpu_est_i[0]") (joined + (portRef O (instanceRef cpu_est_i_0)) + (portRef I1 (instanceRef clk_cpu_est_11_0_a4_1)) + (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_3)) + (portRef I1 (instanceRef clk_cpu_est_11_i_a4_0_1_2)) + (portRef I0 (instanceRef state_machine_un13_clk_000_d_1_0)) + )) + (net (rename cpu_est_i_1 "cpu_est_i[1]") (joined + (portRef O (instanceRef cpu_est_i_1)) + (portRef I0 (instanceRef clk_cpu_est_11_0_o4_1)) + (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_3)) + (portRef I1 (instanceRef state_machine_un8_clk_000_d_2)) + )) + (net (rename cpu_est_i_3 "cpu_est_i[3]") (joined + (portRef O (instanceRef cpu_est_i_3)) + (portRef I1 (instanceRef clk_cpu_est_11_0_a4_0_1)) + (portRef I1 (instanceRef clk_cpu_est_11_0_o4_1)) + (portRef I1 (instanceRef clk_cpu_est_11_i_a4_1_2)) + (portRef I1 (instanceRef state_machine_un13_clk_000_d_1_0)) + (portRef I1 (instanceRef state_machine_un8_clk_000_d)) + )) + (net (rename state_machine_un8_clk_000_d_1_i_0 "state_machine.un8_clk_000_d_1_i_0") (joined + (portRef O (instanceRef state_machine_un8_clk_000_d_1_i)) + (portRef I0 (instanceRef VMA_INT_0_m)) + )) + (net DTACK_i (joined + (portRef O (instanceRef I_107)) + (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa_1_0)) + )) + (net (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (joined + (portRef O (instanceRef SM_AMIGA_i_3)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_0_4)) )) (net (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (joined (portRef O (instanceRef SM_AMIGA_i_4)) (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_0_4)) (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_3)) )) - (net (rename state_machine_un13_clk_000_d_1_i "state_machine.un13_clk_000_d_1_i") (joined - (portRef O (instanceRef state_machine_un13_clk_000_d_1_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_a2_7)) - )) - (net CLK_000_DD_i (joined - (portRef O (instanceRef CLK_000_DD_i)) - (portRef I1 (instanceRef clk_un3_clk_000_dd_0_a2)) - )) - (net AS_030_000_SYNC_i (joined - (portRef O (instanceRef AS_030_000_SYNC_i)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_0_1)) - (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_1_1)) - )) - (net (rename cpu_est_i_0 "cpu_est_i[0]") (joined - (portRef O (instanceRef cpu_est_i_0)) - (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_3)) - (portRef I1 (instanceRef clk_cpu_est_11_0_a4_1)) - (portRef I1 (instanceRef clk_cpu_est_11_i_a4_0_1_2)) - )) - (net (rename cpu_est_i_2 "cpu_est_i[2]") (joined - (portRef O (instanceRef cpu_est_i_2)) - (portRef I1 (instanceRef clk_cpu_est_11_0_a4_0_3)) - (portRef I1 (instanceRef clk_cpu_est_11_0_a4_1_3)) - (portRef I0 (instanceRef clk_cpu_est_11_0_a4_0_1)) - (portRef I1 (instanceRef clk_cpu_est_11_i_a4_0_2)) - )) - (net (rename cpu_est_i_3 "cpu_est_i[3]") (joined - (portRef O (instanceRef cpu_est_i_3)) - (portRef I1 (instanceRef clk_cpu_est_11_0_o4_1)) - (portRef I1 (instanceRef clk_cpu_est_11_0_a4_0_1)) - (portRef I1 (instanceRef state_machine_un8_clk_000_d_1)) - (portRef I1 (instanceRef clk_cpu_est_11_i_a4_2)) - )) - (net (rename cpu_est_i_1 "cpu_est_i[1]") (joined - (portRef O (instanceRef cpu_est_i_1)) - (portRef I0 (instanceRef clk_cpu_est_11_0_o4_1)) - (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_3)) - (portRef I0 (instanceRef state_machine_un8_clk_000_d_1)) - )) - (net UDS_000_INT_0_sqmuxa_1_i (joined - (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1_i)) - (portRef I0 (instanceRef un2_clk_030_1_93)) - )) - (net UDS_000_INT_0_sqmuxa_i (joined - (portRef O (instanceRef UDS_000_INT_0_sqmuxa_i)) - (portRef I1 (instanceRef un2_clk_030_1_93)) - )) - (net DS_030_i (joined - (portRef O (instanceRef DS_030_i)) - (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa_1_1)) - (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa_1_0)) - )) - (net VPA_D_i (joined - (portRef O (instanceRef VPA_D_i)) - (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_3_0)) - (portRef I1 (instanceRef state_machine_un8_clk_000_d_2)) - )) - (net (rename state_machine_un42_clk_030_i "state_machine.un42_clk_030_i") (joined - (portRef O (instanceRef state_machine_un42_clk_030_i)) - (portRef I1 (instanceRef state_machine_AS_030_000_SYNC_3)) - )) - (net VPA_SYNC_1_sqmuxa_i (joined - (portRef O (instanceRef VPA_SYNC_1_sqmuxa_i)) - (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_1)) - (portRef I0 (instanceRef VPA_SYNC_0_n)) - )) - (net N_102_i (joined - (portRef O (instanceRef N_102_i)) - (portRef I1 (instanceRef AS_000_INT_1_sqmuxa)) - (portRef I0 (instanceRef AS_000_INT_0_n)) - (portRef I1 (instanceRef SM_AMIGA_ns_2)) + (net (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (joined + (portRef O (instanceRef SM_AMIGA_i_5)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_3)) )) (net DTACK_SYNC_1_sqmuxa_i (joined (portRef O (instanceRef DTACK_SYNC_1_sqmuxa_i)) (portRef I1 (instanceRef DTACK_SYNC_1_sqmuxa_1)) (portRef I0 (instanceRef DTACK_SYNC_0_n)) )) + (net VPA_SYNC_1_sqmuxa_i (joined + (portRef O (instanceRef VPA_SYNC_1_sqmuxa_i)) + (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_1)) + (portRef I0 (instanceRef VPA_SYNC_0_n)) + )) (net N_98_i (joined (portRef O (instanceRef N_98_i)) - (portRef I1 (instanceRef DSACK_INT_1_sqmuxa)) (portRef I0 (instanceRef DSACK_INT_0_1__n)) + (portRef I1 (instanceRef DSACK_INT_1_sqmuxa)) (portRef I0 (instanceRef SM_AMIGA_ns_7)) )) - (net (rename A_i_18 "A_i[18]") (joined - (portRef O (instanceRef A_i_18)) - (portRef I0 (instanceRef state_machine_un42_clk_030_2)) + (net (rename state_machine_un42_clk_030_i "state_machine.un42_clk_030_i") (joined + (portRef O (instanceRef state_machine_un42_clk_030_i)) + (portRef I1 (instanceRef state_machine_AS_030_000_SYNC_3)) )) - (net (rename A_i_16 "A_i[16]") (joined - (portRef O (instanceRef A_i_16)) - (portRef I1 (instanceRef state_machine_un42_clk_030_1)) + (net UDS_000_INT_0_sqmuxa_1_i (joined + (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1_i)) + (portRef I0 (instanceRef un1_as_030_4_93)) )) - (net (rename A_i_19 "A_i[19]") (joined - (portRef O (instanceRef A_i_19)) - (portRef I1 (instanceRef state_machine_un42_clk_030_2)) + (net UDS_000_INT_0_sqmuxa_i (joined + (portRef O (instanceRef UDS_000_INT_0_sqmuxa_i)) + (portRef I1 (instanceRef un1_as_030_4_93)) + )) + (net AS_030_000_SYNC_i (joined + (portRef O (instanceRef AS_030_000_SYNC_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_0_1)) + (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_1_1)) + )) + (net DS_030_i (joined + (portRef O (instanceRef DS_030_i)) + (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa_1_1)) + (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa_1_0)) + )) + (net (rename cpu_est_i_2 "cpu_est_i[2]") (joined + (portRef O (instanceRef cpu_est_i_2)) + (portRef I0 (instanceRef clk_cpu_est_11_0_a4_0_1)) + (portRef I1 (instanceRef clk_cpu_est_11_0_a4_0_3)) + (portRef I1 (instanceRef clk_cpu_est_11_0_a4_1_3)) + (portRef I1 (instanceRef clk_cpu_est_11_i_a4_0_2)) + )) + (net (rename state_machine_un13_clk_000_d_2_i "state_machine.un13_clk_000_d_2_i") (joined + (portRef O (instanceRef state_machine_un13_clk_000_d_2_i)) + (portRef I1 (instanceRef clk_cpu_est_11_i_a4_2)) + )) + (net CLK_000_DD_i (joined + (portRef O (instanceRef CLK_000_DD_i)) + (portRef I1 (instanceRef clk_un4_clk_000_dd_0_a2)) + )) + (net (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (joined + (portRef O (instanceRef SM_AMIGA_i_6)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_1)) + (portRef I0 (instanceRef state_machine_un5_clk_030_i_a2)) )) (net CLK_030_i (joined (portRef O (instanceRef CLK_030_i)) (portRef I1 (instanceRef state_machine_un17_clk_030)) )) - (net VMA_INT_i (joined - (portRef O (instanceRef VMA_INT_i)) - (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_2)) - )) - (net DTACK_i (joined - (portRef O (instanceRef I_107)) - (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa_1_1)) - )) - (net (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (joined - (portRef O (instanceRef SM_AMIGA_i_3)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_0_4)) - )) - (net (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (joined - (portRef O (instanceRef SM_AMIGA_i_1)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_0_6)) - )) - (net (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (joined - (portRef O (instanceRef SM_AMIGA_i_2)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_o2_6)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_0_6)) - )) (net (rename A_i_30 "A_i[30]") (joined (portRef O (instanceRef A_i_30)) (portRef I0 (instanceRef un8_ciin_4)) @@ -1395,14 +1339,22 @@ (portRef O (instanceRef A_i_25)) (portRef I1 (instanceRef un8_ciin_1)) )) + (net (rename A_i_19 "A_i[19]") (joined + (portRef O (instanceRef A_i_19)) + (portRef I1 (instanceRef state_machine_un42_clk_030_2)) + )) + (net (rename A_i_16 "A_i[16]") (joined + (portRef O (instanceRef A_i_16)) + (portRef I1 (instanceRef state_machine_un42_clk_030_1)) + )) + (net (rename A_i_18 "A_i[18]") (joined + (portRef O (instanceRef A_i_18)) + (portRef I0 (instanceRef state_machine_un42_clk_030_2)) + )) (net (rename CLK_CNT_i_0 "CLK_CNT_i[0]") (joined (portRef O (instanceRef CLK_CNT_i_0)) (portRef D (instanceRef CLK_CNT_0)) )) - (net (rename state_machine_un13_as_000_int_i "state_machine.un13_as_000_int_i") (joined - (portRef O (instanceRef state_machine_un13_as_000_int_i)) - (portRef D (instanceRef DTACK_DMA)) - )) (net RST_i (joined (portRef O (instanceRef RST_i)) (portRef S (instanceRef AS_000_INT)) @@ -1429,6 +1381,10 @@ (portRef S (instanceRef VMA_INT)) (portRef S (instanceRef VPA_SYNC)) )) + (net (rename state_machine_un13_as_000_int_i "state_machine.un13_as_000_int_i") (joined + (portRef O (instanceRef state_machine_un13_as_000_int_i)) + (portRef D (instanceRef DTACK_DMA)) + )) (net FPU_CS_INT_i (joined (portRef O (instanceRef FPU_CS_INT_i)) (portRef OE (instanceRef AVEC_EXP)) @@ -1436,8 +1392,8 @@ )) (net CPU_SPACE_i (joined (portRef O (instanceRef CPU_SPACE_i)) - (portRef I1 (instanceRef un1_bg_030_1)) (portRef I1 (instanceRef state_machine_AS_030_000_SYNC_3_1)) + (portRef I0 (instanceRef un1_bg_030_2)) (portRef OE (instanceRef DSACK_0)) (portRef OE (instanceRef DSACK_1)) )) @@ -1448,7 +1404,7 @@ (net AS_030_c (joined (portRef O (instanceRef AS_030)) (portRef I0 (instanceRef AS_030_i)) - (portRef I0 (instanceRef un1_bg_030_2)) + (portRef I0 (instanceRef un1_bg_030_1)) )) (net AS_030 (joined (portRef AS_030) @@ -1476,7 +1432,7 @@ )) (net (rename SIZE_c_0 "SIZE_c[0]") (joined (portRef O (instanceRef SIZE_0)) - (portRef I0 (instanceRef state_machine_un31_clk_000_d_1)) + (portRef I0 (instanceRef state_machine_un34_clk_000_d_1)) )) (net (rename SIZE_0 "SIZE[0]") (joined (portRef (member size 1)) @@ -1707,7 +1663,7 @@ (net BGACK_000_c (joined (portRef O (instanceRef BGACK_000)) (portRef I0 (instanceRef BGACK_030_INT_0_m)) - (portRef I0 (instanceRef state_machine_un4_bgack_000)) + (portRef I0 (instanceRef state_machine_un6_bgack_000)) (portRef I1 (instanceRef state_machine_un42_clk_030_3)) )) (net BGACK_000 (joined @@ -1725,7 +1681,6 @@ )) (net CLK_000_c (joined (portRef O (instanceRef CLK_000)) - (portRef I1 (instanceRef clk_RISING_CLK_AMIGA_1)) (portRef D (instanceRef CLK_000_D)) )) (net CLK_000 (joined @@ -1752,7 +1707,6 @@ (portRef CLK (instanceRef IPL_030DFFSH_2)) (portRef CLK (instanceRef LDS_000_INT)) (portRef CLK (instanceRef RESETDFF)) - (portRef CLK (instanceRef RISING_CLK_AMIGA)) (portRef CLK (instanceRef SM_AMIGA_0)) (portRef CLK (instanceRef SM_AMIGA_1)) (portRef CLK (instanceRef SM_AMIGA_2)) @@ -1769,10 +1723,6 @@ (portRef CLK (instanceRef cpu_est_1)) (portRef CLK (instanceRef cpu_est_2)) (portRef CLK (instanceRef cpu_est_3)) - (portRef CLK (instanceRef cpu_est_d_0)) - (portRef CLK (instanceRef cpu_est_d_1)) - (portRef CLK (instanceRef cpu_est_d_2)) - (portRef CLK (instanceRef cpu_est_d_3)) )) (net CLK_OSZI (joined (portRef CLK_OSZI) @@ -1948,24 +1898,6 @@ (portRef O (instanceRef CIIN)) (portRef CIIN) )) - (net N_145_i (joined - (portRef O (instanceRef N_145_i)) - (portRef I1 (instanceRef state_machine_UDS_000_INT_8)) - (portRef I0 (instanceRef state_machine_LDS_000_INT_8)) - )) - (net (rename A_c_i_0 "A_c_i[0]") (joined - (portRef O (instanceRef A_c_i_0)) - (portRef I0 (instanceRef state_machine_UDS_000_INT_8)) - (portRef I1 (instanceRef state_machine_un31_clk_000_d_1)) - )) - (net (rename state_machine_UDS_000_INT_8_0 "state_machine.UDS_000_INT_8_0") (joined - (portRef O (instanceRef state_machine_UDS_000_INT_8)) - (portRef I0 (instanceRef state_machine_UDS_000_INT_8_i)) - )) - (net (rename state_machine_LDS_000_INT_8_0 "state_machine.LDS_000_INT_8_0") (joined - (portRef O (instanceRef state_machine_LDS_000_INT_8)) - (portRef I0 (instanceRef state_machine_LDS_000_INT_8_i)) - )) (net N_99_i (joined (portRef O (instanceRef N_99_i)) (portRef I1 (instanceRef SM_AMIGA_ns_i_0)) @@ -1974,18 +1906,6 @@ (portRef O (instanceRef SM_AMIGA_ns_i_0)) (portRef D (instanceRef SM_AMIGA_7)) )) - (net N_112_i (joined - (portRef O (instanceRef N_112_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_1)) - )) - (net N_100_i (joined - (portRef O (instanceRef N_100_i)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_1)) - )) - (net N_77_i (joined - (portRef O (instanceRef SM_AMIGA_ns_i_1)) - (portRef D (instanceRef SM_AMIGA_6)) - )) (net N_101_i (joined (portRef O (instanceRef N_101_i)) (portRef I0 (instanceRef SM_AMIGA_ns_2)) @@ -1994,13 +1914,29 @@ (portRef O (instanceRef SM_AMIGA_ns_2)) (portRef I0 (instanceRef SM_AMIGA_ns_i_2)) )) - (net N_103_i (joined - (portRef O (instanceRef N_103_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_3)) + (net N_107_i (joined + (portRef O (instanceRef N_107_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_5)) )) - (net N_80_i (joined - (portRef O (instanceRef SM_AMIGA_ns_i_3)) - (portRef D (instanceRef SM_AMIGA_4)) + (net N_106_i (joined + (portRef O (instanceRef N_106_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_5)) + )) + (net (rename SM_AMIGA_ns_0_5 "SM_AMIGA_ns_0[5]") (joined + (portRef O (instanceRef SM_AMIGA_ns_5)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_5)) + )) + (net N_108_i (joined + (portRef O (instanceRef N_108_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_6)) + )) + (net N_109_i (joined + (portRef O (instanceRef N_109_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_6)) + )) + (net N_85_i (joined + (portRef O (instanceRef SM_AMIGA_ns_i_6)) + (portRef D (instanceRef SM_AMIGA_1)) )) (net N_110_i (joined (portRef O (instanceRef N_110_i)) @@ -2014,9 +1950,92 @@ (portRef O (instanceRef SM_AMIGA_ns_i_o2_0)) (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_i_0)) )) - (net N_92_0 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_o2_1)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_i_1)) + (net CLK_OUT_PRE_i (joined + (portRef O (instanceRef CLK_OUT_PRE_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_6)) + )) + (net N_94_0 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_o2_6)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_i_6)) + )) + (net (rename state_machine_un8_clk_000_d_i "state_machine.un8_clk_000_d_i") (joined + (portRef O (instanceRef state_machine_un8_clk_000_d_i)) + (portRef I0 (instanceRef state_machine_un15_clk_000_d)) + )) + (net (rename state_machine_un13_clk_000_d_i "state_machine.un13_clk_000_d_i") (joined + (portRef O (instanceRef state_machine_un13_clk_000_d_i)) + (portRef I1 (instanceRef state_machine_un15_clk_000_d)) + )) + (net (rename state_machine_un15_clk_000_d_0 "state_machine.un15_clk_000_d_0") (joined + (portRef O (instanceRef state_machine_un15_clk_000_d)) + (portRef I0 (instanceRef state_machine_un15_clk_000_d_i)) + )) + (net N_93_0 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_o2_4)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_i_4)) + )) + (net N_104_i (joined + (portRef O (instanceRef N_104_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_4)) + )) + (net N_105_i (joined + (portRef O (instanceRef N_105_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_4)) + )) + (net N_82_i (joined + (portRef O (instanceRef SM_AMIGA_ns_i_4)) + (portRef D (instanceRef SM_AMIGA_3)) + )) + (net N_103_i (joined + (portRef O (instanceRef N_103_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_3)) + )) + (net N_80_i (joined + (portRef O (instanceRef SM_AMIGA_ns_i_3)) + (portRef D (instanceRef SM_AMIGA_4)) + )) + (net (rename state_machine_un60_clk_000_d_i "state_machine.un60_clk_000_d_i") (joined + (portRef O (instanceRef state_machine_un60_clk_000_d)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_o2_4)) + (portRef I0 (instanceRef state_machine_un60_clk_000_d_i_0)) + )) + (net (rename state_machine_un17_clk_030_0 "state_machine.un17_clk_030_0") (joined + (portRef O (instanceRef state_machine_un17_clk_030)) + (portRef I0 (instanceRef state_machine_un17_clk_030_i)) + )) + (net un1_as_030_3_0 (joined + (portRef O (instanceRef un1_as_030_3)) + (portRef I0 (instanceRef un1_as_030_3_i)) + )) + (net N_145_i (joined + (portRef O (instanceRef N_145_i)) + (portRef I1 (instanceRef state_machine_UDS_000_INT_8)) + (portRef I0 (instanceRef state_machine_LDS_000_INT_8)) + )) + (net (rename A_c_i_0 "A_c_i[0]") (joined + (portRef O (instanceRef A_c_i_0)) + (portRef I0 (instanceRef state_machine_UDS_000_INT_8)) + (portRef I1 (instanceRef state_machine_un34_clk_000_d_1)) + )) + (net (rename state_machine_UDS_000_INT_8_0 "state_machine.UDS_000_INT_8_0") (joined + (portRef O (instanceRef state_machine_UDS_000_INT_8)) + (portRef I0 (instanceRef state_machine_UDS_000_INT_8_i)) + )) + (net (rename state_machine_LDS_000_INT_8_0 "state_machine.LDS_000_INT_8_0") (joined + (portRef O (instanceRef state_machine_LDS_000_INT_8)) + (portRef I0 (instanceRef state_machine_LDS_000_INT_8_i)) + )) + (net (rename state_machine_AS_030_000_SYNC_3_2 "state_machine.AS_030_000_SYNC_3_2") (joined + (portRef O (instanceRef state_machine_AS_030_000_SYNC_3)) + (portRef I0 (instanceRef state_machine_AS_030_000_SYNC_3_i)) + )) + (net (rename SIZE_c_i_1 "SIZE_c_i[1]") (joined + (portRef O (instanceRef SIZE_c_i_1)) + (portRef I1 (instanceRef state_machine_un34_clk_000_d)) + )) + (net (rename state_machine_un34_clk_000_d_i "state_machine.un34_clk_000_d_i") (joined + (portRef O (instanceRef state_machine_un34_clk_000_d)) + (portRef I0 (instanceRef state_machine_un34_clk_000_d_i_0)) )) (net N_131_i (joined (portRef O (instanceRef N_131_i)) @@ -2030,11 +2049,6 @@ (portRef O (instanceRef clk_cpu_est_11_i_2)) (portRef I0 (instanceRef cpu_est_0_2__m)) )) - (net N_124_i (joined - (portRef O (instanceRef clk_cpu_est_11_i_o4_2)) - (portRef I0 (instanceRef clk_cpu_est_11_0_a4_2_1)) - (portRef I0 (instanceRef clk_cpu_est_11_i_o4_i_2)) - )) (net N_125_i (joined (portRef O (instanceRef clk_cpu_est_11_0_o4_1)) (portRef I0 (instanceRef clk_cpu_est_11_0_a4_1_1)) @@ -2045,26 +2059,6 @@ (portRef I0 (instanceRef clk_cpu_est_11_0_a4_0_3)) (portRef I0 (instanceRef clk_cpu_est_11_0_o4_i_3)) )) - (net N_129_i (joined - (portRef O (instanceRef N_129_i)) - (portRef I1 (instanceRef clk_cpu_est_11_0_2_1)) - )) - (net N_127_i (joined - (portRef O (instanceRef N_127_i)) - (portRef I0 (instanceRef clk_cpu_est_11_0_2_1)) - )) - (net N_128_i (joined - (portRef O (instanceRef N_128_i)) - (portRef I1 (instanceRef clk_cpu_est_11_0_1_1)) - )) - (net N_130_i (joined - (portRef O (instanceRef N_130_i)) - (portRef I0 (instanceRef clk_cpu_est_11_0_1_1)) - )) - (net (rename clk_cpu_est_11_0_1 "clk.cpu_est_11_0[1]") (joined - (portRef O (instanceRef clk_cpu_est_11_0_1)) - (portRef I0 (instanceRef clk_cpu_est_11_0_i_1)) - )) (net N_134_i (joined (portRef O (instanceRef N_134_i)) (portRef I1 (instanceRef clk_cpu_est_11_0_3)) @@ -2081,103 +2075,110 @@ (portRef O (instanceRef clk_cpu_est_11_0_3)) (portRef I0 (instanceRef clk_cpu_est_11_0_i_3)) )) - (net (rename SIZE_c_i_1 "SIZE_c_i[1]") (joined - (portRef O (instanceRef SIZE_c_i_1)) - (portRef I1 (instanceRef state_machine_un31_clk_000_d)) + (net N_130_i (joined + (portRef O (instanceRef N_130_i)) + (portRef I1 (instanceRef clk_cpu_est_11_0_2_1)) )) - (net (rename state_machine_un31_clk_000_d_i "state_machine.un31_clk_000_d_i") (joined - (portRef O (instanceRef state_machine_un31_clk_000_d)) - (portRef I0 (instanceRef state_machine_un31_clk_000_d_i_0)) + (net (rename clk_cpu_est_11_0_1 "clk.cpu_est_11_0[1]") (joined + (portRef O (instanceRef clk_cpu_est_11_0_1)) + (portRef I0 (instanceRef clk_cpu_est_11_0_i_1)) )) - (net (rename state_machine_AS_030_000_SYNC_3_0 "state_machine.AS_030_000_SYNC_3_0") (joined - (portRef O (instanceRef state_machine_AS_030_000_SYNC_3)) - (portRef I0 (instanceRef state_machine_AS_030_000_SYNC_3_i)) - )) - (net un1_as_030_2_0 (joined - (portRef O (instanceRef un1_as_030_2)) - (portRef I0 (instanceRef un1_as_030_2_i)) - )) - (net (rename state_machine_un17_clk_030_0 "state_machine.un17_clk_030_0") (joined - (portRef O (instanceRef state_machine_un17_clk_030)) - (portRef I0 (instanceRef state_machine_un17_clk_030_i)) - )) - (net (rename state_machine_un57_clk_000_d_0 "state_machine.un57_clk_000_d_0") (joined - (portRef O (instanceRef state_machine_un57_clk_000_d)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_o2_4)) - (portRef I0 (instanceRef state_machine_un57_clk_000_d_i)) - )) - (net RISING_CLK_AMIGA_i (joined - (portRef O (instanceRef RISING_CLK_AMIGA_i)) - (portRef I1 (instanceRef state_machine_un4_bgack_000)) - )) - (net (rename state_machine_un4_bgack_000_0 "state_machine.un4_bgack_000_0") (joined - (portRef O (instanceRef state_machine_un4_bgack_000)) - (portRef I0 (instanceRef state_machine_un4_bgack_000_i)) - )) - (net BG_030_c_i (joined - (portRef O (instanceRef BG_030_c_i)) - (portRef I0 (instanceRef state_machine_un1_clk_030)) - (portRef I0 (instanceRef un1_bg_030_1)) - )) - (net (rename state_machine_un1_clk_030_0 "state_machine.un1_clk_030_0") (joined - (portRef O (instanceRef state_machine_un1_clk_030)) - (portRef I0 (instanceRef state_machine_un1_clk_030_i)) - )) - (net N_97_i (joined - (portRef O (instanceRef N_97_i)) - (portRef I1 (instanceRef un1_bg_030_2)) + (net N_128_i (joined + (portRef O (instanceRef N_128_i)) + (portRef I1 (instanceRef clk_cpu_est_11_0_1_1)) )) (net un1_bg_030_0 (joined (portRef O (instanceRef un1_bg_030)) (portRef I0 (instanceRef un1_bg_030_i)) )) - (net CLK_OUT_PRE_i (joined - (portRef O (instanceRef CLK_OUT_PRE_i)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_6)) + (net N_97_i (joined + (portRef O (instanceRef N_97_i)) + (portRef I1 (instanceRef un1_bg_030_2)) )) - (net N_94_0 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_o2_6)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_i_6)) + (net BG_030_c_i (joined + (portRef O (instanceRef BG_030_c_i)) + (portRef I0 (instanceRef state_machine_un1_clk_030)) + (portRef I1 (instanceRef un1_bg_030_1)) )) - (net N_93_0 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_o2_4)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_i_4)) + (net N_127_i (joined + (portRef O (instanceRef N_127_i)) + (portRef I0 (instanceRef clk_cpu_est_11_0_1_1)) )) - (net N_108_i (joined - (portRef O (instanceRef N_108_i)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_6)) + (net N_129_i (joined + (portRef O (instanceRef N_129_i)) + (portRef I0 (instanceRef clk_cpu_est_11_0_2_1)) )) - (net N_109_i (joined - (portRef O (instanceRef N_109_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_6)) + (net N_92_0 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_o2_1)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_i_1)) )) - (net N_85_i (joined - (portRef O (instanceRef SM_AMIGA_ns_i_6)) - (portRef D (instanceRef SM_AMIGA_1)) + (net N_100_i (joined + (portRef O (instanceRef N_100_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_1)) )) - (net N_106_i (joined - (portRef O (instanceRef N_106_i)) - (portRef I0 (instanceRef SM_AMIGA_ns_5)) + (net N_112_i (joined + (portRef O (instanceRef N_112_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_1)) )) - (net N_107_i (joined - (portRef O (instanceRef N_107_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_5)) + (net N_77_i (joined + (portRef O (instanceRef SM_AMIGA_ns_i_1)) + (portRef D (instanceRef SM_AMIGA_6)) )) - (net (rename SM_AMIGA_ns_0_5 "SM_AMIGA_ns_0[5]") (joined - (portRef O (instanceRef SM_AMIGA_ns_5)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_5)) + (net (rename clk_un4_clk_000_dd_i "clk.un4_clk_000_dd_i") (joined + (portRef O (instanceRef clk_un4_clk_000_dd_i)) + (portRef I1 (instanceRef state_machine_un6_bgack_000)) )) - (net N_104_i (joined - (portRef O (instanceRef N_104_i)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_4)) + (net (rename state_machine_un6_bgack_000_0 "state_machine.un6_bgack_000_0") (joined + (portRef O (instanceRef state_machine_un6_bgack_000)) + (portRef I0 (instanceRef state_machine_un6_bgack_000_i)) )) - (net N_105_i (joined - (portRef O (instanceRef N_105_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_4)) + (net (rename state_machine_un1_clk_030_0 "state_machine.un1_clk_030_0") (joined + (portRef O (instanceRef state_machine_un1_clk_030)) + (portRef I0 (instanceRef state_machine_un1_clk_030_i)) )) - (net N_82_i (joined - (portRef O (instanceRef SM_AMIGA_ns_i_4)) - (portRef D (instanceRef SM_AMIGA_3)) + (net (rename clk_cpu_est_11_0_1_3 "clk.cpu_est_11_0_1[3]") (joined + (portRef O (instanceRef clk_cpu_est_11_0_1_3)) + (portRef I0 (instanceRef clk_cpu_est_11_0_3)) + )) + (net (rename state_machine_un34_clk_000_d_i_1 "state_machine.un34_clk_000_d_i_1") (joined + (portRef O (instanceRef state_machine_un34_clk_000_d_1)) + (portRef I0 (instanceRef state_machine_un34_clk_000_d)) + )) + (net (rename state_machine_AS_030_000_SYNC_3_2_1 "state_machine.AS_030_000_SYNC_3_2_1") (joined + (portRef O (instanceRef state_machine_AS_030_000_SYNC_3_1)) + (portRef I0 (instanceRef state_machine_AS_030_000_SYNC_3)) + )) + (net N_168_1 (joined + (portRef O (instanceRef un8_ciin_1)) + (portRef I0 (instanceRef un8_ciin_5)) + )) + (net N_168_2 (joined + (portRef O (instanceRef un8_ciin_2)) + (portRef I1 (instanceRef un8_ciin_5)) + )) + (net N_168_3 (joined + (portRef O (instanceRef un8_ciin_3)) + (portRef I0 (instanceRef un8_ciin_6)) + )) + (net N_168_4 (joined + (portRef O (instanceRef un8_ciin_4)) + (portRef I1 (instanceRef un8_ciin_6)) + )) + (net N_168_5 (joined + (portRef O (instanceRef un8_ciin_5)) + (portRef I0 (instanceRef un8_ciin)) + )) + (net N_168_6 (joined + (portRef O (instanceRef un8_ciin_6)) + (portRef I1 (instanceRef un8_ciin)) + )) + (net N_171_1 (joined + (portRef O (instanceRef un4_ciin_1)) + (portRef I0 (instanceRef un4_ciin)) + )) + (net N_171_2 (joined + (portRef O (instanceRef un4_ciin_2)) + (portRef I1 (instanceRef un4_ciin)) )) (net un1_bg_030_0_1 (joined (portRef O (instanceRef un1_bg_030_1)) @@ -2187,14 +2188,6 @@ (portRef O (instanceRef un1_bg_030_2)) (portRef I1 (instanceRef un1_bg_030)) )) - (net (rename state_machine_un31_clk_000_d_i_1 "state_machine.un31_clk_000_d_i_1") (joined - (portRef O (instanceRef state_machine_un31_clk_000_d_1)) - (portRef I0 (instanceRef state_machine_un31_clk_000_d)) - )) - (net (rename clk_cpu_est_11_0_1_3 "clk.cpu_est_11_0_1[3]") (joined - (portRef O (instanceRef clk_cpu_est_11_0_1_3)) - (portRef I0 (instanceRef clk_cpu_est_11_0_3)) - )) (net (rename clk_cpu_est_11_0_1_1 "clk.cpu_est_11_0_1[1]") (joined (portRef O (instanceRef clk_cpu_est_11_0_1_1)) (portRef I0 (instanceRef clk_cpu_est_11_0_1)) @@ -2203,42 +2196,6 @@ (portRef O (instanceRef clk_cpu_est_11_0_2_1)) (portRef I1 (instanceRef clk_cpu_est_11_0_1)) )) - (net N_167_1 (joined - (portRef O (instanceRef un8_ciin_1)) - (portRef I0 (instanceRef un8_ciin_5)) - )) - (net N_167_2 (joined - (portRef O (instanceRef un8_ciin_2)) - (portRef I1 (instanceRef un8_ciin_5)) - )) - (net N_167_3 (joined - (portRef O (instanceRef un8_ciin_3)) - (portRef I0 (instanceRef un8_ciin_6)) - )) - (net N_167_4 (joined - (portRef O (instanceRef un8_ciin_4)) - (portRef I1 (instanceRef un8_ciin_6)) - )) - (net N_167_5 (joined - (portRef O (instanceRef un8_ciin_5)) - (portRef I0 (instanceRef un8_ciin)) - )) - (net N_167_6 (joined - (portRef O (instanceRef un8_ciin_6)) - (portRef I1 (instanceRef un8_ciin)) - )) - (net N_170_1 (joined - (portRef O (instanceRef un4_ciin_1)) - (portRef I0 (instanceRef un4_ciin)) - )) - (net N_170_2 (joined - (portRef O (instanceRef un4_ciin_2)) - (portRef I1 (instanceRef un4_ciin)) - )) - (net N_107_1 (joined - (portRef O (instanceRef SM_AMIGA_ns_a2_0_1_5)) - (portRef I0 (instanceRef SM_AMIGA_ns_a2_0_5)) - )) (net (rename state_machine_un42_clk_030_1 "state_machine.un42_clk_030_1") (joined (portRef O (instanceRef state_machine_un42_clk_030_1)) (portRef I0 (instanceRef state_machine_un42_clk_030_4)) @@ -2259,12 +2216,60 @@ (portRef O (instanceRef state_machine_un42_clk_030_5)) (portRef I1 (instanceRef state_machine_un42_clk_030)) )) + (net N_132_1 (joined + (portRef O (instanceRef clk_cpu_est_11_i_a4_0_1_2)) + (portRef I0 (instanceRef clk_cpu_est_11_i_a4_0_2)) + )) + (net N_131_1 (joined + (portRef O (instanceRef clk_cpu_est_11_i_a4_1_2)) + (portRef I0 (instanceRef clk_cpu_est_11_i_a4_2)) + )) + (net UDS_000_INT_0_sqmuxa_1_0 (joined + (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1_0)) + (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa)) + )) + (net UDS_000_INT_0_sqmuxa_2 (joined + (portRef O (instanceRef UDS_000_INT_0_sqmuxa_2)) + (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa)) + )) + (net UDS_000_INT_0_sqmuxa_1_1 (joined + (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1_1)) + (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_1_3)) + )) + (net UDS_000_INT_0_sqmuxa_1_2 (joined + (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1_2)) + (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa_1_3)) + )) + (net UDS_000_INT_0_sqmuxa_1_3 (joined + (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1_3)) + (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_1)) + )) (net DTACK_SYNC_1_sqmuxa_1_0 (joined - (portRef O (instanceRef DTACK_SYNC_1_sqmuxa_1_1)) + (portRef O (instanceRef DTACK_SYNC_1_sqmuxa_1_0)) (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa)) )) + (net (rename state_machine_un8_clk_000_d_1_0 "state_machine.un8_clk_000_d_1_0") (joined + (portRef O (instanceRef state_machine_un8_clk_000_d_1_0)) + (portRef I0 (instanceRef state_machine_un8_clk_000_d_3)) + )) + (net (rename state_machine_un8_clk_000_d_2 "state_machine.un8_clk_000_d_2") (joined + (portRef O (instanceRef state_machine_un8_clk_000_d_2)) + (portRef I1 (instanceRef state_machine_un8_clk_000_d_3)) + )) + (net (rename state_machine_un8_clk_000_d_3 "state_machine.un8_clk_000_d_3") (joined + (portRef O (instanceRef state_machine_un8_clk_000_d_3)) + (portRef I0 (instanceRef state_machine_un8_clk_000_d)) + )) + (net (rename state_machine_un13_clk_000_d_1_0 "state_machine.un13_clk_000_d_1_0") (joined + (portRef O (instanceRef state_machine_un13_clk_000_d_1_0)) + (portRef I0 (instanceRef state_machine_un13_clk_000_d)) + )) + (net (rename state_machine_un13_clk_000_d_2_0 "state_machine.un13_clk_000_d_2_0") (joined + (portRef O (instanceRef state_machine_un13_clk_000_d_2_0)) + (portRef I1 (instanceRef state_machine_un13_clk_000_d)) + )) (net VPA_SYNC_1_sqmuxa_1_1 (joined - (portRef O (instanceRef VPA_SYNC_1_sqmuxa_1_0)) + (portRef O (instanceRef VPA_SYNC_1_sqmuxa_1_1)) (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_4)) )) (net VPA_SYNC_1_sqmuxa_2 (joined @@ -2279,65 +2284,25 @@ (portRef O (instanceRef VPA_SYNC_1_sqmuxa_4)) (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa)) )) + (net N_107_1 (joined + (portRef O (instanceRef SM_AMIGA_ns_a2_0_1_5)) + (portRef I0 (instanceRef SM_AMIGA_ns_a2_0_5)) + )) (net N_98_1 (joined (portRef O (instanceRef un1_DSACK_INT_0_sqmuxa_i_a2_1)) (portRef I0 (instanceRef un1_DSACK_INT_0_sqmuxa_i_a2)) )) - (net (rename state_machine_AS_030_000_SYNC_3_0_1 "state_machine.AS_030_000_SYNC_3_0_1") (joined - (portRef O (instanceRef state_machine_AS_030_000_SYNC_3_1)) - (portRef I0 (instanceRef state_machine_AS_030_000_SYNC_3)) + (net (rename AS_000_INT_0_un3 "AS_000_INT_0.un3") (joined + (portRef O (instanceRef AS_000_INT_0_r)) + (portRef I1 (instanceRef AS_000_INT_0_n)) )) - (net UDS_000_INT_0_sqmuxa_1_0 (joined - (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1_0)) - (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa)) + (net (rename AS_000_INT_0_un1 "AS_000_INT_0.un1") (joined + (portRef O (instanceRef AS_000_INT_0_m)) + (portRef I0 (instanceRef AS_000_INT_0_p)) )) - (net UDS_000_INT_0_sqmuxa_2 (joined - (portRef O (instanceRef UDS_000_INT_0_sqmuxa_2)) - (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa)) - )) - (net (rename state_machine_un13_clk_000_d_1_0 "state_machine.un13_clk_000_d_1_0") (joined - (portRef O (instanceRef state_machine_un13_clk_000_d_1_0)) - (portRef I0 (instanceRef state_machine_un13_clk_000_d)) - )) - (net (rename state_machine_un13_clk_000_d_4_1 "state_machine.un13_clk_000_d_4_1") (joined - (portRef O (instanceRef state_machine_un13_clk_000_d_4_1)) - (portRef I0 (instanceRef state_machine_un13_clk_000_d_4)) - )) - (net (rename state_machine_un8_clk_000_d_1 "state_machine.un8_clk_000_d_1") (joined - (portRef O (instanceRef state_machine_un8_clk_000_d_1)) - (portRef I0 (instanceRef state_machine_un8_clk_000_d_4)) - )) - (net (rename state_machine_un8_clk_000_d_2 "state_machine.un8_clk_000_d_2") (joined - (portRef O (instanceRef state_machine_un8_clk_000_d_2)) - (portRef I1 (instanceRef state_machine_un8_clk_000_d_4)) - )) - (net (rename state_machine_un8_clk_000_d_3 "state_machine.un8_clk_000_d_3") (joined - (portRef O (instanceRef state_machine_un8_clk_000_d_3)) - (portRef I1 (instanceRef state_machine_un8_clk_000_d)) - )) - (net (rename state_machine_un8_clk_000_d_4 "state_machine.un8_clk_000_d_4") (joined - (portRef O (instanceRef state_machine_un8_clk_000_d_4)) - (portRef I0 (instanceRef state_machine_un8_clk_000_d)) - )) - (net UDS_000_INT_0_sqmuxa_1_1 (joined - (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1_1)) - (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_1_3)) - )) - (net UDS_000_INT_0_sqmuxa_1_2 (joined - (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1_2)) - (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa_1_3)) - )) - (net UDS_000_INT_0_sqmuxa_1_3 (joined - (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1_3)) - (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_1)) - )) - (net N_132_1 (joined - (portRef O (instanceRef clk_cpu_est_11_i_a4_0_1_2)) - (portRef I0 (instanceRef clk_cpu_est_11_i_a4_0_2)) - )) - (net N_131_1 (joined - (portRef O (instanceRef clk_cpu_est_11_i_a4_1_2)) - (portRef I0 (instanceRef clk_cpu_est_11_i_a4_2)) + (net (rename AS_000_INT_0_un0 "AS_000_INT_0.un0") (joined + (portRef O (instanceRef AS_000_INT_0_n)) + (portRef I1 (instanceRef AS_000_INT_0_p)) )) (net (rename VMA_INT_0_un3 "VMA_INT_0.un3") (joined (portRef O (instanceRef VMA_INT_0_r)) @@ -2351,18 +2316,6 @@ (portRef O (instanceRef VMA_INT_0_n)) (portRef I1 (instanceRef VMA_INT_0_p)) )) - (net (rename LDS_000_INT_0_un3 "LDS_000_INT_0.un3") (joined - (portRef O (instanceRef LDS_000_INT_0_r)) - (portRef I1 (instanceRef LDS_000_INT_0_n)) - )) - (net (rename LDS_000_INT_0_un1 "LDS_000_INT_0.un1") (joined - (portRef O (instanceRef LDS_000_INT_0_m)) - (portRef I0 (instanceRef LDS_000_INT_0_p)) - )) - (net (rename LDS_000_INT_0_un0 "LDS_000_INT_0.un0") (joined - (portRef O (instanceRef LDS_000_INT_0_n)) - (portRef I1 (instanceRef LDS_000_INT_0_p)) - )) (net (rename UDS_000_INT_0_un3 "UDS_000_INT_0.un3") (joined (portRef O (instanceRef UDS_000_INT_0_r)) (portRef I1 (instanceRef UDS_000_INT_0_n)) @@ -2375,6 +2328,78 @@ (portRef O (instanceRef UDS_000_INT_0_n)) (portRef I1 (instanceRef UDS_000_INT_0_p)) )) + (net (rename DTACK_SYNC_0_un3 "DTACK_SYNC_0.un3") (joined + (portRef O (instanceRef DTACK_SYNC_0_r)) + (portRef I1 (instanceRef DTACK_SYNC_0_n)) + )) + (net (rename DTACK_SYNC_0_un1 "DTACK_SYNC_0.un1") (joined + (portRef O (instanceRef DTACK_SYNC_0_m)) + (portRef I0 (instanceRef DTACK_SYNC_0_p)) + )) + (net (rename DTACK_SYNC_0_un0 "DTACK_SYNC_0.un0") (joined + (portRef O (instanceRef DTACK_SYNC_0_n)) + (portRef I1 (instanceRef DTACK_SYNC_0_p)) + )) + (net (rename VPA_SYNC_0_un3 "VPA_SYNC_0.un3") (joined + (portRef O (instanceRef VPA_SYNC_0_r)) + (portRef I1 (instanceRef VPA_SYNC_0_n)) + )) + (net (rename VPA_SYNC_0_un1 "VPA_SYNC_0.un1") (joined + (portRef O (instanceRef VPA_SYNC_0_m)) + (portRef I0 (instanceRef VPA_SYNC_0_p)) + )) + (net (rename VPA_SYNC_0_un0 "VPA_SYNC_0.un0") (joined + (portRef O (instanceRef VPA_SYNC_0_n)) + (portRef I1 (instanceRef VPA_SYNC_0_p)) + )) + (net (rename DSACK_INT_0_1__un3 "DSACK_INT_0_1_.un3") (joined + (portRef O (instanceRef DSACK_INT_0_1__r)) + (portRef I1 (instanceRef DSACK_INT_0_1__n)) + )) + (net (rename DSACK_INT_0_1__un1 "DSACK_INT_0_1_.un1") (joined + (portRef O (instanceRef DSACK_INT_0_1__m)) + (portRef I0 (instanceRef DSACK_INT_0_1__p)) + )) + (net (rename DSACK_INT_0_1__un0 "DSACK_INT_0_1_.un0") (joined + (portRef O (instanceRef DSACK_INT_0_1__n)) + (portRef I1 (instanceRef DSACK_INT_0_1__p)) + )) + (net (rename AS_030_000_SYNC_0_un3 "AS_030_000_SYNC_0.un3") (joined + (portRef O (instanceRef AS_030_000_SYNC_0_r)) + (portRef I1 (instanceRef AS_030_000_SYNC_0_n)) + )) + (net (rename AS_030_000_SYNC_0_un1 "AS_030_000_SYNC_0.un1") (joined + (portRef O (instanceRef AS_030_000_SYNC_0_m)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_p)) + )) + (net (rename AS_030_000_SYNC_0_un0 "AS_030_000_SYNC_0.un0") (joined + (portRef O (instanceRef AS_030_000_SYNC_0_n)) + (portRef I1 (instanceRef AS_030_000_SYNC_0_p)) + )) + (net (rename FPU_CS_INT_0_un3 "FPU_CS_INT_0.un3") (joined + (portRef O (instanceRef FPU_CS_INT_0_r)) + (portRef I1 (instanceRef FPU_CS_INT_0_n)) + )) + (net (rename FPU_CS_INT_0_un1 "FPU_CS_INT_0.un1") (joined + (portRef O (instanceRef FPU_CS_INT_0_m)) + (portRef I0 (instanceRef FPU_CS_INT_0_p)) + )) + (net (rename FPU_CS_INT_0_un0 "FPU_CS_INT_0.un0") (joined + (portRef O (instanceRef FPU_CS_INT_0_n)) + (portRef I1 (instanceRef FPU_CS_INT_0_p)) + )) + (net (rename LDS_000_INT_0_un3 "LDS_000_INT_0.un3") (joined + (portRef O (instanceRef LDS_000_INT_0_r)) + (portRef I1 (instanceRef LDS_000_INT_0_n)) + )) + (net (rename LDS_000_INT_0_un1 "LDS_000_INT_0.un1") (joined + (portRef O (instanceRef LDS_000_INT_0_m)) + (portRef I0 (instanceRef LDS_000_INT_0_p)) + )) + (net (rename LDS_000_INT_0_un0 "LDS_000_INT_0.un0") (joined + (portRef O (instanceRef LDS_000_INT_0_n)) + (portRef I1 (instanceRef LDS_000_INT_0_p)) + )) (net (rename cpu_est_0_3__un3 "cpu_est_0_3_.un3") (joined (portRef O (instanceRef cpu_est_0_3__r)) (portRef I1 (instanceRef cpu_est_0_3__n)) @@ -2399,101 +2424,17 @@ (portRef O (instanceRef cpu_est_0_2__n)) (portRef I1 (instanceRef cpu_est_0_2__p)) )) - (net (rename cpu_est_0_1__un3 "cpu_est_0_1_.un3") (joined - (portRef O (instanceRef cpu_est_0_1__r)) - (portRef I1 (instanceRef cpu_est_0_1__n)) + (net (rename BG_000_0_un3 "BG_000_0.un3") (joined + (portRef O (instanceRef BG_000_0_r)) + (portRef I1 (instanceRef BG_000_0_n)) )) - (net (rename cpu_est_0_1__un1 "cpu_est_0_1_.un1") (joined - (portRef O (instanceRef cpu_est_0_1__m)) - (portRef I0 (instanceRef cpu_est_0_1__p)) + (net (rename BG_000_0_un1 "BG_000_0.un1") (joined + (portRef O (instanceRef BG_000_0_m)) + (portRef I0 (instanceRef BG_000_0_p)) )) - (net (rename cpu_est_0_1__un0 "cpu_est_0_1_.un0") (joined - (portRef O (instanceRef cpu_est_0_1__n)) - (portRef I1 (instanceRef cpu_est_0_1__p)) - )) - (net (rename FPU_CS_INT_0_un3 "FPU_CS_INT_0.un3") (joined - (portRef O (instanceRef FPU_CS_INT_0_r)) - (portRef I1 (instanceRef FPU_CS_INT_0_n)) - )) - (net (rename FPU_CS_INT_0_un1 "FPU_CS_INT_0.un1") (joined - (portRef O (instanceRef FPU_CS_INT_0_m)) - (portRef I0 (instanceRef FPU_CS_INT_0_p)) - )) - (net (rename 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- )) - (net (rename IPL_030_0_1__un3 "IPL_030_0_1_.un3") (joined - (portRef O (instanceRef IPL_030_0_1__r)) - (portRef I1 (instanceRef IPL_030_0_1__n)) - )) - (net (rename IPL_030_0_1__un1 "IPL_030_0_1_.un1") (joined - (portRef O (instanceRef IPL_030_0_1__m)) - (portRef I0 (instanceRef IPL_030_0_1__p)) - )) - (net (rename IPL_030_0_1__un0 "IPL_030_0_1_.un0") (joined - (portRef O (instanceRef IPL_030_0_1__n)) - (portRef I1 (instanceRef IPL_030_0_1__p)) - )) - (net (rename IPL_030_0_0__un3 "IPL_030_0_0_.un3") (joined - (portRef O (instanceRef IPL_030_0_0__r)) - (portRef I1 (instanceRef IPL_030_0_0__n)) - )) - (net (rename IPL_030_0_0__un1 "IPL_030_0_0_.un1") (joined - (portRef O (instanceRef IPL_030_0_0__m)) - (portRef I0 (instanceRef IPL_030_0_0__p)) - )) - (net (rename IPL_030_0_0__un0 "IPL_030_0_0_.un0") (joined - (portRef O (instanceRef IPL_030_0_0__n)) - (portRef I1 (instanceRef IPL_030_0_0__p)) + (net (rename BG_000_0_un0 "BG_000_0.un0") (joined + (portRef O (instanceRef BG_000_0_n)) + (portRef I1 (instanceRef BG_000_0_p)) )) (net (rename BGACK_030_INT_0_un3 "BGACK_030_INT_0.un3") (joined (portRef O (instanceRef BGACK_030_INT_0_r)) @@ -2507,41 +2448,53 @@ (portRef O (instanceRef BGACK_030_INT_0_n)) (portRef I1 (instanceRef BGACK_030_INT_0_p)) )) - (net (rename DSACK_INT_0_1__un3 "DSACK_INT_0_1_.un3") (joined - (portRef O (instanceRef DSACK_INT_0_1__r)) - (portRef I1 (instanceRef DSACK_INT_0_1__n)) + (net (rename cpu_est_0_1__un3 "cpu_est_0_1_.un3") (joined + (portRef O (instanceRef cpu_est_0_1__r)) + (portRef I1 (instanceRef cpu_est_0_1__n)) )) - (net (rename DSACK_INT_0_1__un1 "DSACK_INT_0_1_.un1") (joined - (portRef O (instanceRef DSACK_INT_0_1__m)) - (portRef I0 (instanceRef DSACK_INT_0_1__p)) + (net (rename cpu_est_0_1__un1 "cpu_est_0_1_.un1") (joined + (portRef O (instanceRef cpu_est_0_1__m)) + (portRef I0 (instanceRef cpu_est_0_1__p)) )) - (net (rename DSACK_INT_0_1__un0 "DSACK_INT_0_1_.un0") (joined - (portRef O (instanceRef DSACK_INT_0_1__n)) - (portRef I1 (instanceRef DSACK_INT_0_1__p)) + (net (rename cpu_est_0_1__un0 "cpu_est_0_1_.un0") (joined + (portRef O (instanceRef cpu_est_0_1__n)) + (portRef I1 (instanceRef cpu_est_0_1__p)) )) - (net (rename BG_000_0_un3 "BG_000_0.un3") (joined - (portRef O (instanceRef BG_000_0_r)) - (portRef I1 (instanceRef BG_000_0_n)) + (net (rename IPL_030_0_0__un3 "IPL_030_0_0_.un3") (joined + (portRef O (instanceRef IPL_030_0_0__r)) + (portRef I1 (instanceRef IPL_030_0_0__n)) )) - (net (rename BG_000_0_un1 "BG_000_0.un1") (joined - (portRef O (instanceRef BG_000_0_m)) - (portRef I0 (instanceRef BG_000_0_p)) + (net (rename IPL_030_0_0__un1 "IPL_030_0_0_.un1") (joined + (portRef O (instanceRef IPL_030_0_0__m)) + (portRef I0 (instanceRef IPL_030_0_0__p)) )) - (net (rename BG_000_0_un0 "BG_000_0.un0") (joined - (portRef O (instanceRef BG_000_0_n)) - (portRef I1 (instanceRef BG_000_0_p)) + (net (rename IPL_030_0_0__un0 "IPL_030_0_0_.un0") (joined + (portRef O (instanceRef IPL_030_0_0__n)) + (portRef I1 (instanceRef IPL_030_0_0__p)) )) - (net (rename DTACK_SYNC_0_un3 "DTACK_SYNC_0.un3") (joined - (portRef O (instanceRef DTACK_SYNC_0_r)) - (portRef I1 (instanceRef DTACK_SYNC_0_n)) + (net (rename IPL_030_0_1__un3 "IPL_030_0_1_.un3") (joined + (portRef O (instanceRef IPL_030_0_1__r)) + (portRef I1 (instanceRef IPL_030_0_1__n)) )) - (net (rename DTACK_SYNC_0_un1 "DTACK_SYNC_0.un1") (joined - (portRef O (instanceRef DTACK_SYNC_0_m)) - (portRef I0 (instanceRef DTACK_SYNC_0_p)) + (net (rename IPL_030_0_1__un1 "IPL_030_0_1_.un1") (joined + (portRef O (instanceRef IPL_030_0_1__m)) + (portRef I0 (instanceRef IPL_030_0_1__p)) )) - (net (rename DTACK_SYNC_0_un0 "DTACK_SYNC_0.un0") (joined - (portRef O (instanceRef DTACK_SYNC_0_n)) - (portRef I1 (instanceRef DTACK_SYNC_0_p)) + (net (rename IPL_030_0_1__un0 "IPL_030_0_1_.un0") (joined + (portRef O (instanceRef IPL_030_0_1__n)) + (portRef I1 (instanceRef IPL_030_0_1__p)) + )) + (net (rename IPL_030_0_2__un3 "IPL_030_0_2_.un3") (joined + (portRef O (instanceRef IPL_030_0_2__r)) + (portRef I1 (instanceRef IPL_030_0_2__n)) + )) + (net (rename IPL_030_0_2__un1 "IPL_030_0_2_.un1") (joined + (portRef O (instanceRef IPL_030_0_2__m)) + (portRef I0 (instanceRef IPL_030_0_2__p)) + )) + (net (rename IPL_030_0_2__un0 "IPL_030_0_2_.un0") (joined + (portRef O (instanceRef IPL_030_0_2__n)) + (portRef I1 (instanceRef IPL_030_0_2__p)) )) ) (property orig_inst_of (string "BUS68030")) diff --git a/Logic/BUS68030.fse b/Logic/BUS68030.fse index f872732..3bf3322 100644 --- a/Logic/BUS68030.fse +++ b/Logic/BUS68030.fse @@ -1,20 +1,20 @@ -fsm_encoding {722022201} onehot +fsm_encoding {717621761} onehot -fsm_state_encoding {722022201} idle_p {00000001} +fsm_state_encoding {717621761} idle_p {00000001} -fsm_state_encoding {722022201} idle_n {00000010} +fsm_state_encoding {717621761} idle_n {00000010} -fsm_state_encoding {722022201} as_set_p {00000100} +fsm_state_encoding {717621761} as_set_p {00000100} -fsm_state_encoding {722022201} as_set_n {00001000} +fsm_state_encoding {717621761} as_set_n {00001000} -fsm_state_encoding {722022201} sample_dtack_p {00010000} +fsm_state_encoding {717621761} sample_dtack_p {00010000} -fsm_state_encoding {722022201} data_fetch_n {00100000} +fsm_state_encoding {717621761} data_fetch_n {00100000} -fsm_state_encoding {722022201} data_fetch_p {01000000} +fsm_state_encoding {717621761} data_fetch_p {01000000} -fsm_state_encoding {722022201} end_cycle_n {10000000} +fsm_state_encoding {717621761} end_cycle_n {10000000} -fsm_registers {722022201} {SM_AMIGA[0]} {SM_AMIGA[1]} {SM_AMIGA[2]} {SM_AMIGA[3]} {SM_AMIGA[4]} {SM_AMIGA[5]} {SM_AMIGA[6]} {SM_AMIGA[7]} +fsm_registers {717621761} {SM_AMIGA[0]} {SM_AMIGA[1]} {SM_AMIGA[2]} {SM_AMIGA[3]} {SM_AMIGA[4]} {SM_AMIGA[5]} {SM_AMIGA[6]} {SM_AMIGA[7]} diff --git a/Logic/BUS68030.prj b/Logic/BUS68030.prj index cb00d13..2780f25 100644 --- a/Logic/BUS68030.prj +++ b/Logic/BUS68030.prj @@ -1,6 +1,6 @@ #-- Lattice Semiconductor Corporation Ltd. #-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj -#-- Written on Thu May 15 22:21:47 2014 +#-- Written on Thu May 15 23:02:39 2014 #device options diff --git a/Logic/BUS68030.srm b/Logic/BUS68030.srm index a2f3fb9..881f675 100644 --- a/Logic/BUS68030.srm +++ b/Logic/BUS68030.srm @@ -33,9 +33,9 @@ af .is_vhdl 1; af .child_list "-1"; af .parent_list "-1"; VNAME 'mach.MACH_DFF.prim'; # view id 0 -VNAME 'mach.DFF.prim'; # view id 1 +VNAME 'mach.DFFRH.prim'; # view id 1 VNAME 'mach.DFFSH.prim'; # view id 2 -VNAME 'mach.DFFRH.prim'; # view id 3 +VNAME 'mach.DFF.prim'; # view id 3 VNAME 'mach.IBUF.prim'; # view id 4 VNAME 'mach.BUFTH.prim'; # view id 5 VNAME 'mach.OBUF.prim'; # view id 6 @@ -65,42 +65,6 @@ bfjj:RPHMR4kMR4kMR );bjRf:0jRsRkC0CskRBeB;R bfjj:RDVN#VCRNCD#R7th;R bfjj:RV8VsT#RR7TRRiBpR4kMRjkM;R -MROlNEwR7wsRbH -l;N3PRHs#bH4lR;R -FTMRkjH; -R -7;HpRBio; -MMRkjN; -M#R3N_PCM_C0VoDN#.4R6 -n;sjRf:ljRNROEv]qB_w7wRHbslhRQ1Sc -TM=kj7 -S=S7 -B=piB -piSe)=BSB -1B=eBh -SmwaQQ= )t;h7 -fbRjR:j0CskRk0sCBReBb; -R:fjjNRVDR#CV#NDChRt7M; -RNRlO7ERw]w1RHbslN; -PHR3#Hbsl;R4 -TFRRjkM;R -H7H; -RiBp;R -H1o; -MMRkjN; -M#R3N_PCM_C0VoDN#.4R6 -n;okMRM -4;N3MR#CNP_0MC_NVDoR#4.;6n -fsRjR:jlENORBvq]w_7wsRbHQlRh -16SkT=MSj -7 -=7SiBp=iBp -=S)e -BBSk1=MS4 -hQmaw)Q =7th;R -bfjj:RPHMR4kMR4kMR -1;bjRf:0jRsRkC0CskRBeB;R -bfjj:RDVN#VCRNCD#R7th;R MROlNEwR7wR)]blsH;P NR#3HblsHR 4;FRRTk;Mj @@ -121,6 +85,42 @@ SmwaQQ= )t;h7 fbRjR:jHRMPkRM4kRM4)b; R:fjjsR0k0CRsRkCe;BB fbRjR:jV#NDCNRVDR#Ct;h7 +RMRlENORw7w1b]Rs;Hl +RNP3bH#sRHl4F; +RkTRM +j;H;R7 +BHRp +i;H;R1 +RoMk;Mj +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR4kM;M +NRN3#PMC_CV0_D#No46R.ns; +R:fjjNRlOvERq_B]7RwwblsHR1Qh6T +S=jkM +=S77B +SpBi=pSi +)B=eB1 +S=4kM +mShaQQw t)=h +7;bjRf:HjRMkPRMk4RM14R;R +bfjj:Rk0sCsR0keCRB +B;bjRf:VjRNCD#RDVN#tCRh +7;MlRRNROE7RwwblsH;P +NR#3HblsHR +4;FRRTk;Mj +7HR;R +HB;pi +RoMk;Mj +RNM3P#NCC_M0D_VN4o#Rn.6;R +sfjj:ROlNEqRvB7]_wbwRsRHlQch1 +=STk +MjS77= +pSBip=Bi) +S=BeB +=S1e +BBSahmQ wQ)h=t7b; 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+RoM7BaqiY_1hjB_3dkM;M +NRN3#PMC_CV0_D#No46R.no; +MaR7q_Bi1BYh_kj3M +4;N3MR#CNP_0MC_NVDoR#4.;6n +RoM7BaqiY_1hjB_3jkM;M +NRN3#PMC_CV0_D#No46R.no; +MuReqY_1hjB_3dkM;M +NRN3#PMC_CV0_D#No46R.no; +MuReqY_1hjB_34kM;M +NRN3#PMC_CV0_D#No46R.no; +MuReqY_1hjB_3jkM;M +NRN3#PMC_CV0_D#No46R.no; +M1R7q_BiQ_haj__43dkM;M +NRN3#PMC_CV0_D#No46R.no; +M1R7q_BiQ_haj__434kM;M +NRN3#PMC_CV0_D#No46R.no; +M1R7q_BiQ_haj__43jkM;M +NRN3#PMC_CV0_D#No46R.no; +M1Rq_jjd_jjj_h1YB3_jk;Md +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR_q1j_djj_jj1BYh_kj3M +4;N3MR#CNP_0MC_NVDoR#4.;6n +RoMqj1_djj_j1j_Y_hBjM3kjN; +M#R3N_PCM_C0VoDN#.4R6 +n;owMRuBz_1h_Qa3_jk;Md +RNM3P#NCC_M0D_VN4o#Rn.6;M +oRzwu__B1Q_hajM3k4N; +M#R3N_PCM_C0VoDN#.4R6 +n;owMRuBz_1h_Qa3_jk;Mj RNM3P#NCC_M0D_VN4o#Rn.6;M oR1p7_jjj_aQh_kj3M d;N3MR#CNP_0MC_NVDoR#4.;6n @@ -384,71 +428,23 @@ RoMp_71j_jjQ_hajM3k4N; M#R3N_PCM_C0VoDN#.4R6 n;opMR7j1_jQj_hja_3jkM;M NRN3#PMC_CV0_D#No46R.no; -M7Rz1j_jjh_Qa3_jk;Md -RNM3P#NCC_M0D_VN4o#Rn.6;M -oR1z7_jjj_aQh_kj3M -4;N3MR#CNP_0MC_NVDoR#4.;6n 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+R:fjjNRlOQERhbeRsRHlB_piB_haH9rj +=SmB_piB_haH9rj +jSQ=iBp_aBhr;j9 +fsRjR:jlENOReQhRHbsltRAq_Bij_djQ_haHm +S=qAtBji_dQj_hHa_ +jSQ=qAtBji_dQj_h +a;sjRf:ljRNROEQRheblsHRzBu_q1uBH _ +=SmB_uz1Buq +_HS=QjB_uz1Buq ;_O +fsRjR:jlENOReQhRHbsluRwz1_B_aQh_SH +mu=wz1_B_aQh_SH +Qwj=uBz_1h_Qas; +R:fjjNRlOQERhbeRsRHlAjt_jjj_3Ss +mt=A_jjj_kj3MSd +Q#j=0CN0_OlNECHM\M3k4D_O d_jjs; +R:fjjNRlOqERhR7.blsHR_Atj_jjj +3lSAm=tj_jj3_jk +M4S=Qjk_M4Ljo_dSj +Q#4=0CN0_OlNECHM\M3k4D_O d_jjs; +R:fjjNRlOqERhR7.blsHR_Atj_jjj +3MSAm=tj_jj3_jk +MjS=QjAjt_jOj_ +4SQ=_Atj_jjjM3kds; +R:fjjNRlOmER)b.RsRHlAjt_jjj_3Sb +m_=hUQ +Sjt=A_jjj_kj3MS4 +QA4=tj_jj3_jk;Mj +fsRjR:jlENOReQhRHbsltRAq_Bij_djQ_haj +3sSAm=tiqB_jjd_aQh_kj3MSd +Q#j=0CN0_OlNECHM\M3kno_LN_O j;jj +fsRjR:jlENOR7qh.sRbHAlRtiqB_jjd_aQh_lj3 +=SmABtqid_jjh_Qa3_jk +M4S=QjABtqij_jj +_OS=Q4#00NCN_lOMEHCk\3MLn_o NO_jjj;R +sfjj:ROlNEhRq7b.RsRHlABtqid_jjh_Qa3_jMm +S=qAtBji_dQj_hja_3jkM +jSQ=qAtBji_dQj_hSa +QA4=tiqB_jjd_aQh_kj3M +d;sjRf:ljRNROEmR).blsHRqAtBji_dQj_hja_3Sb +m_=h4S4 +QAj=tiqB_jjd_aQh_kj3MS4 +QA4=tiqB_jjd_aQh_kj3M +j;sjRf:ljRNROEQRheblsHRkOb_0C#_4j__ +3sSOm=bCk_#j0__34_k +MdS=QjO\D 3ckM_ OD_jjj_;88 +fsRjR:jlENOR7qh.sRbHOlRbCk_#j0__34_lm +S=kOb_0C#_4j__M3k4Q +SjD=O O\3bCk_#40_49r4 +4SQ= OD\M3kcD_O j_jj8_8;R +sfjj:ROlNEhRq7b.RsRHlO_bkC_#0j__43SM +mb=Ok#_C0__j4k_3MSj +QOj=bCk_#40r9Q +S4b=Ok#_C0__j4k_3M +d;sjRf:ljRNROEmR).blsHRkOb_0C#_4j__ +3bShm=_ +4dS=QjO_bkC_#0j__434kM +4SQ=kOb_0C#_4j__M3kjs; +R:fjjNRlOQERhbeRsRHlQ_upj_djj__j3Ss +mu=Qpd_jj__jjk_3MSd +QOj=D3 \k_McO_D j_jj8 +8;sjRf:ljRNROEq.h7RHbsluRQpd_jj__jjl_3 +=SmQ_upj_djj__j34kM +jSQ=pQu_jOr9Q +S4D=O k\3MOc_Dj _j8j_8s; +R:fjjNRlOqERhR7.blsHRpQu_jjd_jj__ +3MSQm=ujp_djj__3j_k +MjS=QjQ_upj_djO9rj +4SQ=pQu_jjd_jj__M3kds; +R:fjjNRlOmER)b.RsRHlQ_upj_djj__j3Sb +m_=h4Sn +QQj=ujp_djj__3j_k +M4S=Q4Q_upj_djj__j3jkM;R +sfjj:ROlNEhRQesRbHQlRujp_djj__34_sm +S=pQu_jjd_4j__M3kdQ +SjD=O k\3MOc_Dj _j8j_8s; +R:fjjNRlOqERhR7.blsHRpQu_jjd_4j__ +3lSQm=ujp_djj__34_k +M4S=QjQ_upO9r4 +4SQ= OD\M3kcD_O j_jj8_8;R +sfjj:ROlNEhRq7b.RsRHlQ_upj_djj__43SM +mu=Qpd_jj__j4k_3MSj +QQj=ujp_dOj_r +49S=Q4Q_upj_djj__43dkM;R +sfjj:ROlNE)Rm.sRbHQlRujp_djj__34_bm +S=4h_(Q +Sju=Qpd_jj__j4k_3MS4 +QQ4=ujp_djj__34_k;Mj +fsRjR:jlENOReQhRHbsluRQpd_jj__j.s_3 +=SmQ_upj_djj__.3dkM +jSQ= OD\M3kcD_O j_jj8_8;R +sfjj:ROlNEhRq7b.RsRHlQ_upj_djj__.3Sl +mu=Qpd_jj__j.k_3MS4 +QQj=uOp_r +.9S=Q4O\D 3ckM_ OD_jjj_;88 +fsRjR:jlENOR7qh.sRbHQlRujp_djj__3._Mm +S=pQu_jjd_.j__M3kjQ +Sju=Qpd_jjr_O.S9 +QQ4=ujp_djj__3._k;Md +fsRjR:jlENOR.m)RHbsluRQpd_jj__j.b_3 +=SmhU_4 +jSQ=pQu_jjd_.j__M3k4Q +S4u=Qpd_jj__j.k_3M +j; diff --git a/Logic/BUS68030.srr b/Logic/BUS68030.srr index 051b806..4254163 100644 --- a/Logic/BUS68030.srr +++ b/Logic/BUS68030.srr @@ -6,7 +6,7 @@ #Implementation: logic $ Start of Compile -#Thu May 15 22:21:47 2014 +#Thu May 15 23:02:39 2014 Synopsys VHDL Compiler, version comp201209rcp1, Build 283R, built Mar 19 2013 @N|Running in 64-bit mode @@ -18,20 +18,17 @@ File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - VHDL syntax check successful! File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling @N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":6:7:6:14|Synthesizing work.bus68030.behavioral -@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:7:109:15|Signal clk_030_d is undriven +@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":106:7:106:15|Signal clk_030_d is undriven Post processing for work.bus68030.behavioral -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":100:29:100:31|Pruning register SM_AMIGA_D(2 downto 0) -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":105:52:105:55|Pruning register VMA_INT_D -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":91:32:91:34|Pruning register CLK_REF(1 downto 0) -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":220:2:220:3|Pruning register AS_000_START -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":113:38:113:40|Pruning register CLK_000_CNT(3 downto 0) -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":112:37:112:39|Pruning register FALLING_CLK_AMIGA -@W: CL190 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":100:29:100:31|Optimizing register bit DSACK_INT(0) to a constant 1 -@W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":100:29:100:31|Pruning register bit 0 of DSACK_INT(1 downto 0) -@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:2:124:3|Register bit CLK_CNT(1) is always 0, optimizing ... -@W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:2:124:3|Pruning register bit 1 of CLK_CNT(1 downto 0) -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":113:38:113:40|Trying to extract state machine for register cpu_est -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":220:2:220:3|Trying to extract state machine for register SM_AMIGA +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":176:2:176:3|Pruning register CLK_REF(1 downto 0) +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":108:32:108:34|Pruning register cpu_est_d(3 downto 0) +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":108:32:108:34|Pruning register CLK_000_CNT(3 downto 0) +@W: CL190 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":102:52:102:55|Optimizing register bit DSACK_INT(0) to a constant 1 +@W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":102:52:102:55|Pruning register bit 0 of DSACK_INT(1 downto 0) +@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":117:2:117:3|Register bit CLK_CNT(1) is always 0, optimizing ... +@W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":117:2:117:3|Pruning register bit 1 of CLK_CNT(1 downto 0) +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":108:32:108:34|Trying to extract state machine for register cpu_est +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":176:2:176:3|Trying to extract state machine for register SM_AMIGA Extracted state machine for register SM_AMIGA State machine has 8 reachable states with original encodings of: 000 @@ -42,10 +39,10 @@ State machine has 8 reachable states with original encodings of: 101 110 111 -@W: CL249 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":220:2:220:3|Initial value is not supported on state machine SM_AMIGA +@W: CL249 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":176:2:176:3|Initial value is not supported on state machine SM_AMIGA @END Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Thu May 15 22:21:47 2014 +# Thu May 15 23:02:39 2014 ###########################################################] Map & Optimize Report @@ -64,19 +61,19 @@ original code -> new code 101 -> 00100000 110 -> 01000000 111 -> 10000000 -@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":160:4:160:7|Found ROM, 'clk\.cpu_est_11[3:0]', 16 words by 4 bits +@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":145:4:145:7|Found ROM, 'clk\.cpu_est_11[3:0]', 16 words by 4 bits --------------------------------------- Resource Usage Report Simple gate primitives: -DFF 16 uses -DFFSH 16 uses DFFRH 7 uses +DFFSH 16 uses +DFF 11 uses IBUF 35 uses BUFTH 7 uses OBUF 15 uses BI_DIR 2 uses -AND2 149 uses +AND2 147 uses INV 119 uses OR2 17 uses XOR2 2 uses @@ -89,6 +86,6 @@ Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 95MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Thu May 15 22:21:49 2014 +# Thu May 15 23:02:41 2014 ###########################################################] diff --git a/Logic/BUS68030.srs b/Logic/BUS68030.srs index 1cdfca0..db16274 100644 Binary files a/Logic/BUS68030.srs and b/Logic/BUS68030.srs differ diff --git a/Logic/bus68030.exf b/Logic/bus68030.exf index d611d91..a1fb344 100644 --- a/Logic/bus68030.exf +++ b/Logic/bus68030.exf @@ -55,29 +55,133 @@ Section Member Rename Array-Notation Array Number Port FC_0_ FC[0] 4 1 End Section Cross Reference File -Design 'BUS68030' created Thu May 15 22:21:53 2014 +Design 'BUS68030' created Thu May 15 23:02:46 2014 Type New Name Original Name // ---------------------------------------------------------------------- - Inst i_z2J2J AS_000 - Inst i_z2L2L UDS_000 - Inst i_z2M2M LDS_000 - Inst i_z3B3B BERR - Inst i_z3U3U DTACK - Inst i_z4040 AVEC_EXP - Inst i_z4C4C CIIN - Inst LDS_000_INT_0_n LDS_000_INT_0.n - Inst LDS_000_INT_0_p LDS_000_INT_0.p + Inst i_z2E2E AS_000 + Inst i_z2G2G UDS_000 + Inst i_z2H2H LDS_000 + Inst i_z3636 BERR + Inst i_z3P3P DTACK + Inst i_z3R3R AVEC_EXP + Inst i_z4747 CIIN + Inst AS_000_INT_0_m AS_000_INT_0.m + Inst AS_000_INT_0_n AS_000_INT_0.n + Inst AS_000_INT_0_p AS_000_INT_0.p + Inst state_machine_un13_clk_000_d_1 state_machine.un13_clk_000_d_1 + Inst SM_AMIGA_ns_i_o2_6_ SM_AMIGA_ns_i_o2[6] + Inst SM_AMIGA_ns_i_o2_0_ SM_AMIGA_ns_i_o2[0] + Inst SM_AMIGA_ns_7_ SM_AMIGA_ns[7] + Inst SM_AMIGA_ns_i_6_ SM_AMIGA_ns_i[6] + Inst SM_AMIGA_ns_5_ SM_AMIGA_ns[5] + Inst SM_AMIGA_ns_2_ SM_AMIGA_ns[2] + Inst SM_AMIGA_ns_i_0_ SM_AMIGA_ns_i[0] + Inst state_machine_un13_clk_000_d_1_i state_machine.un13_clk_000_d_1_i + Inst SM_AMIGA_ns_a2_7_ SM_AMIGA_ns_a2[7] + Inst SM_AMIGA_i_2_ SM_AMIGA_i[2] + Inst SM_AMIGA_i_1_ SM_AMIGA_i[1] + Inst SM_AMIGA_ns_i_a2_0_6_ SM_AMIGA_ns_i_a2_0[6] + Inst SM_AMIGA_ns_i_a2_6_ SM_AMIGA_ns_i_a2[6] + Inst SM_AMIGA_i_3_ SM_AMIGA_i[3] + Inst SM_AMIGA_ns_i_o2_4_ SM_AMIGA_ns_i_o2[4] + Inst state_machine_un8_clk_000_d_1_i state_machine.un8_clk_000_d_1_i + Inst VMA_INT_0_r VMA_INT_0.r + Inst VMA_INT_0_m VMA_INT_0.m + Inst VMA_INT_0_n VMA_INT_0.n + Inst VMA_INT_0_p VMA_INT_0.p + Inst state_machine_un15_clk_000_d state_machine.un15_clk_000_d + Inst state_machine_un8_clk_000_d_1 state_machine.un8_clk_000_d_1 + Inst cpu_est_i_3_ cpu_est_i[3] + Inst cpu_est_i_0_ cpu_est_i[0] + Inst cpu_est_i_1_ cpu_est_i[1] Inst UDS_000_INT_0_r UDS_000_INT_0.r Inst UDS_000_INT_0_m UDS_000_INT_0.m Inst UDS_000_INT_0_n UDS_000_INT_0.n Inst UDS_000_INT_0_p UDS_000_INT_0.p - Inst state_machine_un13_clk_000_d_i state_machine.un13_clk_000_d_i - Inst state_machine_un8_clk_000_d_i state_machine.un8_clk_000_d_i - Inst state_machine_un13_as_000_int state_machine.un13_as_000_int - Inst clk_RISING_CLK_AMIGA_1 clk.RISING_CLK_AMIGA_1 - Inst cpu_est_d_i_3_ cpu_est_d_i[3] - Inst cpu_est_d_i_0_ cpu_est_d_i[0] + Inst state_machine_un60_clk_000_d state_machine.un60_clk_000_d + Inst DTACK_SYNC_0_r DTACK_SYNC_0.r + Inst SM_AMIGA_3_ SM_AMIGA[3] + Inst DTACK_SYNC_0_m DTACK_SYNC_0.m + Inst SM_AMIGA_2_ SM_AMIGA[2] + Inst DTACK_SYNC_0_n DTACK_SYNC_0.n + Inst SM_AMIGA_1_ SM_AMIGA[1] + Inst DTACK_SYNC_0_p DTACK_SYNC_0.p + Inst SM_AMIGA_0_ SM_AMIGA[0] + Inst VPA_SYNC_0_r VPA_SYNC_0.r + Inst IPL_030DFFSH_0_ IPL_030DFFSH[0] + Inst VPA_SYNC_0_m VPA_SYNC_0.m + Inst IPL_030DFFSH_1_ IPL_030DFFSH[1] + Inst VPA_SYNC_0_n VPA_SYNC_0.n + Inst IPL_030DFFSH_2_ IPL_030DFFSH[2] + Inst VPA_SYNC_0_p VPA_SYNC_0.p + Inst SM_AMIGA_7_ SM_AMIGA[7] + Inst SM_AMIGA_6_ SM_AMIGA[6] + Inst SM_AMIGA_5_ SM_AMIGA[5] + Inst SM_AMIGA_4_ SM_AMIGA[4] + Inst DSACK_INT_1_ DSACK_INT[1] + Inst SM_AMIGA_i_5_ SM_AMIGA_i[5] + Inst SM_AMIGA_ns_i_a2_3_ SM_AMIGA_ns_i_a2[3] + Inst SM_AMIGA_ns_i_a2_4_ SM_AMIGA_ns_i_a2[4] + Inst SM_AMIGA_i_4_ SM_AMIGA_i[4] + Inst cpu_est_0_ cpu_est[0] + Inst SM_AMIGA_ns_i_a2_0_4_ SM_AMIGA_ns_i_a2_0[4] + Inst cpu_est_1_ cpu_est[1] + Inst SM_AMIGA_ns_i_3_ SM_AMIGA_ns_i[3] + Inst cpu_est_2_ cpu_est[2] + Inst SM_AMIGA_ns_i_4_ SM_AMIGA_ns_i[4] + Inst cpu_est_3_ cpu_est[3] + Inst state_machine_LDS_000_INT_8 state_machine.LDS_000_INT_8 + Inst state_machine_UDS_000_INT_8 state_machine.UDS_000_INT_8 + Inst state_machine_un42_clk_030_i state_machine.un42_clk_030_i + Inst state_machine_un17_clk_030 state_machine.un17_clk_030 + Inst CLK_CNT_0_ CLK_CNT[0] + Inst DSACK_INT_0_1__r DSACK_INT_0_1_.r + Inst DSACK_INT_0_1__m DSACK_INT_0_1_.m + Inst DSACK_INT_0_1__n DSACK_INT_0_1_.n + Inst DSACK_INT_0_1__p DSACK_INT_0_1_.p + Inst AS_030_000_SYNC_0_r AS_030_000_SYNC_0.r + Inst AS_030_000_SYNC_0_m AS_030_000_SYNC_0.m + Inst AS_030_000_SYNC_0_n AS_030_000_SYNC_0.n + Inst AS_030_000_SYNC_0_p AS_030_000_SYNC_0.p + Inst FPU_CS_INT_0_r FPU_CS_INT_0.r + Inst FPU_CS_INT_0_m FPU_CS_INT_0.m + Inst SIZE_0_ SIZE[0] + Inst FPU_CS_INT_0_n FPU_CS_INT_0.n + Inst SIZE_1_ SIZE[1] + Inst FPU_CS_INT_0_p FPU_CS_INT_0.p + Inst A_0_ A[0] + Inst LDS_000_INT_0_r LDS_000_INT_0.r + Inst A_16_ A[16] + Inst LDS_000_INT_0_m LDS_000_INT_0.m + Inst A_17_ A[17] + Inst LDS_000_INT_0_n LDS_000_INT_0.n + Inst A_18_ A[18] + Inst LDS_000_INT_0_p LDS_000_INT_0.p + Inst A_19_ A[19] + Inst state_machine_un13_clk_000_d_2 state_machine.un13_clk_000_d_2 + Inst A_20_ A[20] + Inst clk_cpu_est_11_0_a4_1_3_ clk.cpu_est_11_0_a4_1[3] + Inst A_21_ A[21] + Inst state_machine_un13_clk_000_d_2_i state_machine.un13_clk_000_d_2_i + Inst A_22_ A[22] + Inst clk_cpu_est_11_0_o4_3_ clk.cpu_est_11_0_o4[3] + Inst A_23_ A[23] + Inst clk_cpu_est_11_0_o4_1_ clk.cpu_est_11_0_o4[1] + Inst A_24_ A[24] + Inst clk_cpu_est_11_i_2_ clk.cpu_est_11_i[2] + Inst A_25_ A[25] + Inst clk_cpu_est_11_0_a4_0_3_ clk.cpu_est_11_0_a4_0[3] + Inst A_26_ A[26] + Inst clk_cpu_est_11_0_a4_3_ clk.cpu_est_11_0_a4[3] + Inst A_27_ A[27] + Inst clk_cpu_est_11_0_a4_2_1_ clk.cpu_est_11_0_a4_2[1] + Inst A_28_ A[28] + Inst cpu_est_i_2_ cpu_est_i[2] + Inst A_29_ A[29] + Inst clk_cpu_est_11_0_a4_0_1_ clk.cpu_est_11_0_a4_0[1] + Inst A_30_ A[30] Inst cpu_est_0_3__r cpu_est_0_3_.r + Inst A_31_ A[31] Inst cpu_est_0_3__m cpu_est_0_3_.m Inst cpu_est_0_3__n cpu_est_0_3_.n Inst cpu_est_0_3__p cpu_est_0_3_.p @@ -85,408 +189,296 @@ Design 'BUS68030' created Thu May 15 22:21:53 2014 Inst cpu_est_0_2__m cpu_est_0_2_.m Inst cpu_est_0_2__n cpu_est_0_2_.n Inst cpu_est_0_2__p cpu_est_0_2_.p - Inst cpu_est_0_1__r cpu_est_0_1_.r - Inst cpu_est_0_1__m cpu_est_0_1_.m - Inst cpu_est_0_1__n cpu_est_0_1_.n - Inst cpu_est_0_1__p cpu_est_0_1_.p - Inst clk_un3_clk_000_dd_0_a2 clk.un3_clk_000_dd_0_a2 - Inst state_machine_un13_clk_000_d_1_i state_machine.un13_clk_000_d_1_i - Inst SM_AMIGA_ns_a2_7_ SM_AMIGA_ns_a2[7] - Inst SM_AMIGA_i_5_ SM_AMIGA_i[5] - Inst SM_AMIGA_i_4_ SM_AMIGA_i[4] - Inst SM_AMIGA_ns_i_a2_3_ SM_AMIGA_ns_i_a2[3] - Inst SM_AMIGA_ns_a2_0_2_ SM_AMIGA_ns_a2_0[2] - Inst SM_AMIGA_ns_a2_2_ SM_AMIGA_ns_a2[2] - Inst SM_AMIGA_ns_i_a2_1_ SM_AMIGA_ns_i_a2[1] - Inst SM_AMIGA_ns_i_a2_0_ SM_AMIGA_ns_i_a2[0] - Inst SM_AMIGA_i_6_ SM_AMIGA_i[6] - Inst SM_AMIGA_i_7_ SM_AMIGA_i[7] - Inst cpu_est_3_ cpu_est[3] - Inst state_machine_un5_clk_030_i_a2 state_machine.un5_clk_030_i_a2 - Inst SM_AMIGA_7_ SM_AMIGA[7] - Inst state_machine_LDS_000_INT_8 state_machine.LDS_000_INT_8 - Inst SM_AMIGA_6_ SM_AMIGA[6] - Inst state_machine_UDS_000_INT_8 state_machine.UDS_000_INT_8 - Inst SM_AMIGA_5_ SM_AMIGA[5] - Inst cpu_est_i_2_ cpu_est_i[2] - Inst SM_AMIGA_4_ SM_AMIGA[4] - Inst cpu_est_i_3_ cpu_est_i[3] - Inst SM_AMIGA_3_ SM_AMIGA[3] - Inst clk_cpu_est_11_0_a4_0_1_ clk.cpu_est_11_0_a4_0[1] - Inst SM_AMIGA_2_ SM_AMIGA[2] - Inst cpu_est_i_0_ cpu_est_i[0] - Inst SM_AMIGA_1_ SM_AMIGA[1] - Inst clk_cpu_est_11_0_a4_1_ clk.cpu_est_11_0_a4[1] - Inst SM_AMIGA_0_ SM_AMIGA[0] - Inst SM_AMIGA_ns_i_o2_1_ SM_AMIGA_ns_i_o2[1] - Inst cpu_est_d_0_ cpu_est_d[0] - Inst SM_AMIGA_ns_i_o2_0_ SM_AMIGA_ns_i_o2[0] - Inst cpu_est_d_1_ cpu_est_d[1] - Inst SM_AMIGA_ns_7_ SM_AMIGA_ns[7] - Inst cpu_est_d_2_ cpu_est_d[2] - Inst SM_AMIGA_ns_i_3_ SM_AMIGA_ns_i[3] - Inst cpu_est_d_3_ cpu_est_d[3] - Inst SM_AMIGA_ns_2_ SM_AMIGA_ns[2] - Inst IPL_030DFFSH_0_ IPL_030DFFSH[0] - Inst SM_AMIGA_ns_i_1_ SM_AMIGA_ns_i[1] - Inst IPL_030DFFSH_1_ IPL_030DFFSH[1] - Inst SM_AMIGA_ns_i_0_ SM_AMIGA_ns_i[0] - Inst IPL_030DFFSH_2_ IPL_030DFFSH[2] - Inst cpu_est_0_ cpu_est[0] - Inst SM_AMIGA_ns_i_a2_0_1_ SM_AMIGA_ns_i_a2_0[1] - Inst cpu_est_1_ cpu_est[1] - Inst cpu_est_2_ cpu_est[2] - Inst clk_cpu_est_11_0_a4_1_3_ clk.cpu_est_11_0_a4_1[3] - Inst DSACK_INT_1_ DSACK_INT[1] - Inst clk_cpu_est_11_0_o4_3_ clk.cpu_est_11_0_o4[3] - Inst clk_cpu_est_11_0_o4_1_ clk.cpu_est_11_0_o4[1] - Inst cpu_est_i_1_ cpu_est_i[1] - Inst clk_cpu_est_11_i_o4_2_ clk.cpu_est_11_i_o4[2] - Inst clk_cpu_est_11_i_2_ clk.cpu_est_11_i[2] - Inst clk_cpu_est_11_0_a4_0_3_ clk.cpu_est_11_0_a4_0[3] - Inst clk_cpu_est_11_0_a4_3_ clk.cpu_est_11_0_a4[3] - Inst clk_cpu_est_11_0_a4_2_1_ clk.cpu_est_11_0_a4_2[1] - Inst clk_cpu_est_11_0_a4_1_1_ clk.cpu_est_11_0_a4_1[1] - Inst CLK_CNT_0_ CLK_CNT[0] - Inst state_machine_un57_clk_000_d state_machine.un57_clk_000_d - Inst FPU_CS_INT_0_r FPU_CS_INT_0.r - Inst FPU_CS_INT_0_m FPU_CS_INT_0.m - Inst FPU_CS_INT_0_n FPU_CS_INT_0.n - Inst FPU_CS_INT_0_p FPU_CS_INT_0.p - Inst AS_000_INT_0_r AS_000_INT_0.r - Inst AS_000_INT_0_m AS_000_INT_0.m - Inst AS_000_INT_0_n AS_000_INT_0.n - Inst AS_000_INT_0_p AS_000_INT_0.p - Inst VPA_SYNC_0_r VPA_SYNC_0.r - Inst VPA_SYNC_0_m VPA_SYNC_0.m - Inst SIZE_0_ SIZE[0] - Inst VPA_SYNC_0_n VPA_SYNC_0.n - Inst SIZE_1_ SIZE[1] - Inst VPA_SYNC_0_p VPA_SYNC_0.p - Inst A_0_ A[0] - Inst AS_030_000_SYNC_0_r AS_030_000_SYNC_0.r - Inst A_16_ A[16] - Inst AS_030_000_SYNC_0_m AS_030_000_SYNC_0.m - Inst A_17_ A[17] - Inst AS_030_000_SYNC_0_n AS_030_000_SYNC_0.n - Inst A_18_ A[18] - Inst AS_030_000_SYNC_0_p AS_030_000_SYNC_0.p - Inst A_19_ A[19] - Inst state_machine_un17_clk_030 state_machine.un17_clk_030 - Inst A_20_ A[20] - Inst A_21_ A[21] - Inst A_22_ A[22] - Inst A_23_ A[23] - Inst A_24_ A[24] - Inst state_machine_un42_clk_030_i state_machine.un42_clk_030_i - Inst A_25_ A[25] - Inst A_26_ A[26] - Inst cpu_est_0_0_ cpu_est_0[0] - Inst A_27_ A[27] - Inst state_machine_un13_clk_000_d_1 state_machine.un13_clk_000_d_1 - Inst A_28_ A[28] - Inst A_29_ A[29] - Inst A_30_ A[30] Inst state_machine_un1_clk_030 state_machine.un1_clk_030 - Inst A_31_ A[31] - Inst state_machine_un4_bgack_000 state_machine.un4_bgack_000 - Inst A_i_19_ A_i[19] - Inst A_i_18_ A_i[18] - Inst A_i_16_ A_i[16] - Inst IPL_030_0_2__r IPL_030_0_2_.r - Inst IPL_030_0_2__m IPL_030_0_2_.m - Inst IPL_030_0_2__n IPL_030_0_2_.n - Inst IPL_030_0_2__p IPL_030_0_2_.p - Inst IPL_030_0_1__r IPL_030_0_1_.r - Inst IPL_030_0_1__m IPL_030_0_1_.m - Inst IPL_030_0_1__n IPL_030_0_1_.n - Inst IPL_030_0_1__p IPL_030_0_1_.p - Inst IPL_030_0_0__r IPL_030_0_0_.r + Inst state_machine_un6_bgack_000 state_machine.un6_bgack_000 + Inst state_machine_un5_clk_030_i_a2 state_machine.un5_clk_030_i_a2 Inst IPL_030_0_ IPL_030[0] - Inst IPL_030_0_0__m IPL_030_0_0_.m + Inst SM_AMIGA_i_6_ SM_AMIGA_i[6] Inst IPL_030_1_ IPL_030[1] - Inst IPL_030_0_0__n IPL_030_0_0_.n + Inst SM_AMIGA_ns_i_a2_1_ SM_AMIGA_ns_i_a2[1] Inst IPL_030_2_ IPL_030[2] - Inst IPL_030_0_0__p IPL_030_0_0_.p + Inst SM_AMIGA_ns_a2_0_2_ SM_AMIGA_ns_a2_0[2] Inst IPL_0_ IPL[0] - Inst BGACK_030_INT_0_r BGACK_030_INT_0.r Inst IPL_1_ IPL[1] - Inst BGACK_030_INT_0_m BGACK_030_INT_0.m + Inst clk_un4_clk_000_dd_0_a2 clk.un4_clk_000_dd_0_a2 Inst IPL_2_ IPL[2] - Inst BGACK_030_INT_0_n BGACK_030_INT_0.n + Inst SM_AMIGA_ns_i_a2_0_1_ SM_AMIGA_ns_i_a2_0[1] Inst DSACK_0_ DSACK[0] - Inst BGACK_030_INT_0_p BGACK_030_INT_0.p + Inst SM_AMIGA_ns_i_1_ SM_AMIGA_ns_i[1] Inst DSACK_1_ DSACK[1] - Inst DSACK_INT_0_1__r DSACK_INT_0_1_.r - Inst DSACK_INT_0_1__m DSACK_INT_0_1_.m - Inst DSACK_INT_0_1__n DSACK_INT_0_1_.n - Inst DSACK_INT_0_1__p DSACK_INT_0_1_.p + Inst SM_AMIGA_ns_i_o2_1_ SM_AMIGA_ns_i_o2[1] + Inst clk_cpu_est_11_0_a4_1_ clk.cpu_est_11_0_a4[1] + Inst clk_cpu_est_11_0_a4_1_1_ clk.cpu_est_11_0_a4_1[1] + Inst cpu_est_0_0_ cpu_est_0[0] + Inst A_i_16_ A_i[16] + Inst A_i_18_ A_i[18] + Inst A_i_19_ A_i[19] + Inst A_i_24_ A_i[24] + Inst A_i_25_ A_i[25] + Inst A_i_26_ A_i[26] + Inst FC_0_ FC[0] + Inst A_i_27_ A_i[27] + Inst FC_1_ FC[1] + Inst A_i_28_ A_i[28] + Inst A_i_29_ A_i[29] + Inst A_i_30_ A_i[30] + Inst A_i_31_ A_i[31] + Inst state_machine_un13_as_000_int_i state_machine.un13_as_000_int_i + Inst state_machine_un8_clk_000_d_2 state_machine.un8_clk_000_d_2 + Inst state_machine_un8_clk_000_d_3 state_machine.un8_clk_000_d_3 + Inst CLK_CNT_i_0_ CLK_CNT_i[0] + Inst state_machine_un8_clk_000_d state_machine.un8_clk_000_d + Inst state_machine_un13_clk_000_d_1_0 state_machine.un13_clk_000_d_1_0 + Inst state_machine_un13_clk_000_d_2_0 state_machine.un13_clk_000_d_2_0 + Inst state_machine_un13_clk_000_d state_machine.un13_clk_000_d Inst BG_000_0_r BG_000_0.r Inst BG_000_0_m BG_000_0.m Inst BG_000_0_n BG_000_0.n Inst BG_000_0_p BG_000_0.p - Inst FC_0_ FC[0] - Inst DTACK_SYNC_0_r DTACK_SYNC_0.r - Inst FC_1_ FC[1] - Inst DTACK_SYNC_0_m DTACK_SYNC_0.m - Inst DTACK_SYNC_0_n DTACK_SYNC_0.n - Inst DTACK_SYNC_0_p DTACK_SYNC_0.p - Inst SM_AMIGA_i_1_ SM_AMIGA_i[1] - Inst SM_AMIGA_i_2_ SM_AMIGA_i[2] - Inst SM_AMIGA_ns_i_a2_0_6_ SM_AMIGA_ns_i_a2_0[6] - Inst SM_AMIGA_ns_i_4_ SM_AMIGA_ns_i[4] - Inst SM_AMIGA_ns_5_ SM_AMIGA_ns[5] - Inst clk_cpu_est_11_i_a4_0_1_2_ clk.cpu_est_11_i_a4_0_1[2] - Inst SM_AMIGA_ns_i_6_ SM_AMIGA_ns_i[6] - Inst clk_cpu_est_11_i_a4_0_2_ clk.cpu_est_11_i_a4_0[2] - Inst SM_AMIGA_i_3_ SM_AMIGA_i[3] - Inst clk_cpu_est_11_i_a4_1_2_ clk.cpu_est_11_i_a4_1[2] - Inst SM_AMIGA_ns_i_o2_4_ SM_AMIGA_ns_i_o2[4] - Inst clk_cpu_est_11_i_a4_2_ clk.cpu_est_11_i_a4[2] - Inst SM_AMIGA_ns_i_o2_6_ SM_AMIGA_ns_i_o2[6] - Inst state_machine_AS_030_000_SYNC_3_1 state_machine.AS_030_000_SYNC_3_1 - Inst state_machine_AS_030_000_SYNC_3 state_machine.AS_030_000_SYNC_3 - Inst state_machine_un13_clk_000_d_1_0 state_machine.un13_clk_000_d_1_0 - Inst state_machine_un13_clk_000_d state_machine.un13_clk_000_d - Inst A_i_24_ A_i[24] - Inst state_machine_un13_clk_000_d_4_1 state_machine.un13_clk_000_d_4_1 - Inst A_i_25_ A_i[25] - Inst state_machine_un13_clk_000_d_4 state_machine.un13_clk_000_d_4 - Inst A_i_26_ A_i[26] - Inst state_machine_un8_clk_000_d_1 state_machine.un8_clk_000_d_1 - Inst A_i_27_ A_i[27] - Inst state_machine_un8_clk_000_d_2 state_machine.un8_clk_000_d_2 - Inst A_i_28_ A_i[28] - Inst state_machine_un8_clk_000_d_3 state_machine.un8_clk_000_d_3 - Inst A_i_29_ A_i[29] - Inst state_machine_un8_clk_000_d_4 state_machine.un8_clk_000_d_4 - Inst A_i_30_ A_i[30] - Inst state_machine_un8_clk_000_d state_machine.un8_clk_000_d - Inst A_i_31_ A_i[31] - Inst SM_AMIGA_ns_i_a2_4_ SM_AMIGA_ns_i_a2[4] - Inst state_machine_un42_clk_030_1 state_machine.un42_clk_030_1 - Inst SM_AMIGA_ns_i_a2_0_4_ SM_AMIGA_ns_i_a2_0[4] - Inst state_machine_un42_clk_030_2 state_machine.un42_clk_030_2 - Inst SM_AMIGA_ns_a2_5_ SM_AMIGA_ns_a2[5] - Inst state_machine_un42_clk_030_3 state_machine.un42_clk_030_3 - Inst SM_AMIGA_ns_i_a2_6_ SM_AMIGA_ns_i_a2[6] - Inst state_machine_un42_clk_030_4 state_machine.un42_clk_030_4 - Inst state_machine_un13_as_000_int_i state_machine.un13_as_000_int_i - Inst state_machine_un42_clk_030_5 state_machine.un42_clk_030_5 + Inst BGACK_030_INT_0_r BGACK_030_INT_0.r + Inst BGACK_030_INT_0_m BGACK_030_INT_0.m + Inst SM_AMIGA_ns_a2_0_1_5_ SM_AMIGA_ns_a2_0_1[5] + Inst BGACK_030_INT_0_n BGACK_030_INT_0.n + Inst SM_AMIGA_ns_a2_0_5_ SM_AMIGA_ns_a2_0[5] + Inst BGACK_030_INT_0_p BGACK_030_INT_0.p + Inst cpu_est_0_1__r cpu_est_0_1_.r + Inst cpu_est_0_1__m cpu_est_0_1_.m Inst state_machine_un42_clk_030 state_machine.un42_clk_030 - Inst CLK_CNT_i_0_ CLK_CNT_i[0] + Inst cpu_est_0_1__n cpu_est_0_1_.n + Inst clk_cpu_est_11_i_a4_0_1_2_ clk.cpu_est_11_i_a4_0_1[2] + Inst cpu_est_0_1__p cpu_est_0_1_.p + Inst clk_cpu_est_11_i_a4_0_2_ clk.cpu_est_11_i_a4_0[2] + Inst IPL_030_0_0__r IPL_030_0_0_.r + Inst clk_cpu_est_11_i_a4_1_2_ clk.cpu_est_11_i_a4_1[2] + Inst IPL_030_0_0__m IPL_030_0_0_.m + Inst clk_cpu_est_11_i_a4_2_ clk.cpu_est_11_i_a4[2] + Inst IPL_030_0_0__n IPL_030_0_0_.n + Inst IPL_030_0_0__p IPL_030_0_0_.p + Inst IPL_030_0_1__r IPL_030_0_1_.r + Inst IPL_030_0_1__m IPL_030_0_1_.m + Inst IPL_030_0_1__n IPL_030_0_1_.n + Inst IPL_030_0_1__p IPL_030_0_1_.p + Inst IPL_030_0_2__r IPL_030_0_2_.r + Inst IPL_030_0_2__m IPL_030_0_2_.m + Inst IPL_030_0_2__n IPL_030_0_2_.n + Inst IPL_030_0_2__p IPL_030_0_2_.p + Inst state_machine_un8_clk_000_d_1_0 state_machine.un8_clk_000_d_1_0 Inst clk_cpu_est_11_0_1_1_ clk.cpu_est_11_0_1[1] Inst clk_cpu_est_11_0_2_1_ clk.cpu_est_11_0_2[1] Inst clk_cpu_est_11_0_1_ clk.cpu_est_11_0[1] - Inst SM_AMIGA_ns_a2_0_1_5_ SM_AMIGA_ns_a2_0_1[5] - Inst SM_AMIGA_ns_a2_0_5_ SM_AMIGA_ns_a2_0[5] - Inst SM_AMIGA_ns_i_o2_i_4_ SM_AMIGA_ns_i_o2_i[4] - Inst SM_AMIGA_ns_i_5_ SM_AMIGA_ns_i[5] - Inst state_machine_un31_clk_000_d_1 state_machine.un31_clk_000_d_1 - Inst state_machine_un31_clk_000_d state_machine.un31_clk_000_d + Inst state_machine_un42_clk_030_1 state_machine.un42_clk_030_1 + Inst state_machine_un42_clk_030_2 state_machine.un42_clk_030_2 + Inst state_machine_un42_clk_030_3 state_machine.un42_clk_030_3 + Inst state_machine_un42_clk_030_4 state_machine.un42_clk_030_4 + Inst state_machine_un42_clk_030_5 state_machine.un42_clk_030_5 + Inst clk_un4_clk_000_dd_i clk.un4_clk_000_dd_i + Inst state_machine_un6_bgack_000_i state_machine.un6_bgack_000_i + Inst state_machine_un1_clk_030_i state_machine.un1_clk_030_i Inst clk_cpu_est_11_0_1_3_ clk.cpu_est_11_0_1[3] Inst clk_cpu_est_11_0_3_ clk.cpu_est_11_0[3] + Inst state_machine_un34_clk_000_d_1 state_machine.un34_clk_000_d_1 + Inst state_machine_un34_clk_000_d state_machine.un34_clk_000_d + Inst state_machine_AS_030_000_SYNC_3_1 state_machine.AS_030_000_SYNC_3_1 + Inst state_machine_AS_030_000_SYNC_3 state_machine.AS_030_000_SYNC_3 Inst clk_cpu_est_11_0_i_3_ clk.cpu_est_11_0_i[3] - Inst SIZE_c_i_1_ SIZE_c_i[1] - Inst state_machine_un31_clk_000_d_i_0 state_machine.un31_clk_000_d_i_0 - Inst state_machine_AS_030_000_SYNC_3_i state_machine.AS_030_000_SYNC_3_i - Inst state_machine_un17_clk_030_i state_machine.un17_clk_030_i - Inst state_machine_un57_clk_000_d_i state_machine.un57_clk_000_d_i - Inst state_machine_un4_bgack_000_i state_machine.un4_bgack_000_i - Inst state_machine_un1_clk_030_i state_machine.un1_clk_030_i - Inst SM_AMIGA_ns_i_o2_i_6_ SM_AMIGA_ns_i_o2_i[6] - Inst SM_AMIGA_ns_i_o2_i_0_ SM_AMIGA_ns_i_o2_i[0] - Inst SM_AMIGA_ns_i_o2_i_1_ SM_AMIGA_ns_i_o2_i[1] - Inst clk_cpu_est_11_i_o4_i_2_ clk.cpu_est_11_i_o4_i[2] - Inst clk_cpu_est_11_0_o4_i_1_ clk.cpu_est_11_0_o4_i[1] - Inst clk_cpu_est_11_0_o4_i_3_ clk.cpu_est_11_0_o4_i[3] Inst clk_cpu_est_11_0_i_1_ clk.cpu_est_11_0_i[1] + Inst SM_AMIGA_ns_i_o2_i_1_ SM_AMIGA_ns_i_o2_i[1] + Inst state_machine_un60_clk_000_d_i_0 state_machine.un60_clk_000_d_i_0 + Inst state_machine_un17_clk_030_i state_machine.un17_clk_030_i Inst A_c_i_0_ A_c_i[0] Inst state_machine_UDS_000_INT_8_i state_machine.UDS_000_INT_8_i Inst state_machine_LDS_000_INT_8_i state_machine.LDS_000_INT_8_i - Inst SM_AMIGA_ns_i_2_ SM_AMIGA_ns_i[2] + Inst state_machine_AS_030_000_SYNC_3_i state_machine.AS_030_000_SYNC_3_i + Inst SIZE_c_i_1_ SIZE_c_i[1] + Inst state_machine_un34_clk_000_d_i_0 state_machine.un34_clk_000_d_i_0 + Inst clk_cpu_est_11_0_o4_i_1_ clk.cpu_est_11_0_o4_i[1] + Inst clk_cpu_est_11_0_o4_i_3_ clk.cpu_est_11_0_o4_i[3] + Inst SM_AMIGA_ns_i_5_ SM_AMIGA_ns_i[5] Inst SM_AMIGA_ns_i_7_ SM_AMIGA_ns_i[7] - Inst VMA_INT_0_r VMA_INT_0.r - Inst VMA_INT_0_m VMA_INT_0.m - Inst VMA_INT_0_n VMA_INT_0.n - Inst VMA_INT_0_p VMA_INT_0.p - Inst LDS_000_INT_0_r LDS_000_INT_0.r - Inst LDS_000_INT_0_m LDS_000_INT_0.m - Net ipl_030_c_0__n IPL_030_c[0] - Net ipl_030_0__n IPL_030[0] + Inst SM_AMIGA_ns_i_o2_i_0_ SM_AMIGA_ns_i_o2_i[0] + Inst SM_AMIGA_ns_i_o2_i_6_ SM_AMIGA_ns_i_o2_i[6] + Inst state_machine_un8_clk_000_d_i state_machine.un8_clk_000_d_i + Inst state_machine_un13_clk_000_d_i state_machine.un13_clk_000_d_i + Inst state_machine_un15_clk_000_d_i state_machine.un15_clk_000_d_i + Inst SM_AMIGA_ns_i_o2_i_4_ SM_AMIGA_ns_i_o2_i[4] + Inst SM_AMIGA_ns_i_2_ SM_AMIGA_ns_i[2] + Inst SM_AMIGA_ns_a2_5_ SM_AMIGA_ns_a2[5] + Inst SM_AMIGA_ns_a2_2_ SM_AMIGA_ns_a2[2] + Inst SM_AMIGA_i_7_ SM_AMIGA_i[7] + Inst SM_AMIGA_ns_i_a2_0_ SM_AMIGA_ns_i_a2[0] + Inst state_machine_un13_as_000_int state_machine.un13_as_000_int + Inst AS_000_INT_0_r AS_000_INT_0.r Net ipl_030_c_1__n IPL_030_c[1] - Net cpu_est_3__n cpu_est[3] Net ipl_030_1__n IPL_030[1] Net ipl_030_c_2__n IPL_030_c[2] - Net gnd_n_n GND - Net cpu_est_0__n cpu_est[0] Net ipl_c_0__n IPL_c[0] - Net cpu_est_1__n cpu_est[1] Net ipl_0__n IPL[0] - Net cpu_est_d_0__n cpu_est_d[0] Net ipl_c_1__n IPL_c[1] - Net cpu_est_d_3__n cpu_est_d[3] Net ipl_1__n IPL[1] Net ipl_c_2__n IPL_c[2] + Net cpu_est_3__n cpu_est[3] Net dsack_0__n DSACK[0] + Net gnd_n_n GND Net dsack_c_1__n DSACK_c[1] + Net cpu_est_0__n cpu_est[0] + Net cpu_est_1__n cpu_est[1] Net vcc_n_n VCC - Net cpu_est_d_1__n cpu_est_d[1] - Net cpu_est_d_2__n cpu_est_d[2] Net cpu_est_2__n cpu_est[2] Net clk_cnt_0__n CLK_CNT[0] Net sm_amiga_6__n SM_AMIGA[6] Net sm_amiga_7__n SM_AMIGA[7] - Net clk_rising_clk_amiga_1_n clk.RISING_CLK_AMIGA_1 - Net state_machine_un57_clk_000_d_n state_machine.un57_clk_000_d Net fc_c_0__n FC_c[0] - Net sm_amiga_1__n SM_AMIGA[1] Net fc_0__n FC[0] - Net dsack_int_1__n DSACK_INT[1] + Net state_machine_un1_clk_030_n state_machine.un1_clk_030 Net fc_c_1__n FC_c[1] + Net sm_amiga_1__n SM_AMIGA[1] + Net dsack_int_1__n DSACK_INT[1] Net sm_amiga_4__n SM_AMIGA[4] + Net state_machine_un6_bgack_000_n state_machine.un6_bgack_000 Net sm_amiga_3__n SM_AMIGA[3] Net state_machine_un13_as_000_int_n state_machine.un13_as_000_int Net sm_amiga_5__n SM_AMIGA[5] + Net sm_amiga_ns_0_2__n SM_AMIGA_ns_0[2] Net sm_amiga_2__n SM_AMIGA[2] Net sm_amiga_0__n SM_AMIGA[0] - Net a_c_i_0__n A_c_i[0] - Net state_machine_uds_000_int_8_0_n state_machine.UDS_000_INT_8_0 - Net state_machine_lds_000_int_8_0_n state_machine.LDS_000_INT_8_0 - Net sm_amiga_ns_0_2__n SM_AMIGA_ns_0[2] + Net sm_amiga_ns_0_5__n SM_AMIGA_ns_0[5] Net sm_amiga_ns_0_7__n SM_AMIGA_ns_0[7] + Net state_machine_un8_clk_000_d_i_n state_machine.un8_clk_000_d_i + Net state_machine_un13_clk_000_d_i_n state_machine.un13_clk_000_d_i + Net state_machine_un15_clk_000_d_0_n state_machine.un15_clk_000_d_0 + Net state_machine_un60_clk_000_d_i_n state_machine.un60_clk_000_d_i Net sm_amiga_ns_2__n SM_AMIGA_ns[2] + Net state_machine_un17_clk_030_0_n state_machine.un17_clk_030_0 Net sm_amiga_ns_5__n SM_AMIGA_ns[5] Net sm_amiga_ns_7__n SM_AMIGA_ns[7] - Net clk_cpu_est_11_0_1__n clk.cpu_est_11_0[1] - Net clk_cpu_est_11_0_3__n clk.cpu_est_11_0[3] - Net size_c_i_1__n SIZE_c_i[1] - Net state_machine_un31_clk_000_d_i_n state_machine.un31_clk_000_d_i - Net state_machine_as_030_000_sync_3_0_n state_machine.AS_030_000_SYNC_3_0 - Net state_machine_un17_clk_030_0_n state_machine.un17_clk_030_0 - Net state_machine_un57_clk_000_d_0_n state_machine.un57_clk_000_d_0 + Net clk_un4_clk_000_dd_n clk.un4_clk_000_dd + Net a_c_i_0__n A_c_i[0] + Net clk_cpu_est_11_1__n clk.cpu_est_11[1] + Net state_machine_uds_000_int_8_0_n state_machine.UDS_000_INT_8_0 Net state_machine_un42_clk_030_n state_machine.un42_clk_030 - Net state_machine_un4_bgack_000_0_n state_machine.un4_bgack_000_0 - Net state_machine_un1_clk_030_0_n state_machine.un1_clk_030_0 - Net state_machine_un1_clk_030_n state_machine.un1_clk_030 - Net state_machine_un4_bgack_000_n state_machine.un4_bgack_000 - Net state_machine_un17_clk_030_n state_machine.un17_clk_030 + Net state_machine_lds_000_int_8_0_n state_machine.LDS_000_INT_8_0 + Net state_machine_as_030_000_sync_3_2_n state_machine.AS_030_000_SYNC_3_2 + Net size_c_i_1__n SIZE_c_i[1] + Net state_machine_un34_clk_000_d_i_n state_machine.un34_clk_000_d_i + Net clk_cpu_est_11_0_3__n clk.cpu_est_11_0[3] + Net clk_cpu_est_11_0_1__n clk.cpu_est_11_0[1] + Net state_machine_un13_clk_000_d_2_n state_machine.un13_clk_000_d_2 + Net clk_cpu_est_11_3__n clk.cpu_est_11[3] + Net state_machine_un34_clk_000_d_n state_machine.un34_clk_000_d + Net clk_un4_clk_000_dd_i_n clk.un4_clk_000_dd_i Net state_machine_as_030_000_sync_3_n state_machine.AS_030_000_SYNC_3 - Net clk_un3_clk_000_dd_n clk.un3_clk_000_dd - Net sm_amiga_ns_0_5__n SM_AMIGA_ns_0[5] - Net state_machine_un31_clk_000_d_n state_machine.un31_clk_000_d - Net state_machine_un13_clk_000_d_n state_machine.un13_clk_000_d - Net state_machine_un13_clk_000_d_4_n state_machine.un13_clk_000_d_4 - Net state_machine_un13_clk_000_d_1_n state_machine.un13_clk_000_d_1 - Net state_machine_un8_clk_000_d_n state_machine.un8_clk_000_d - Net state_machine_un31_clk_000_d_i_1_n state_machine.un31_clk_000_d_i_1 + Net state_machine_un6_bgack_000_0_n state_machine.un6_bgack_000_0 + Net state_machine_un1_clk_030_0_n state_machine.un1_clk_030_0 + Net state_machine_lds_000_int_8_n state_machine.LDS_000_INT_8 Net clk_cpu_est_11_0_1_3__n clk.cpu_est_11_0_1[3] + Net state_machine_uds_000_int_8_n state_machine.UDS_000_INT_8 + Net state_machine_un34_clk_000_d_i_1_n state_machine.un34_clk_000_d_i_1 + Net state_machine_as_030_000_sync_3_2_1_n state_machine.AS_030_000_SYNC_3_2_1 + Net state_machine_un17_clk_030_n state_machine.un17_clk_030 + Net state_machine_un60_clk_000_d_n state_machine.un60_clk_000_d Net clk_cpu_est_11_0_1_1__n clk.cpu_est_11_0_1[1] Net clk_cpu_est_11_0_2_1__n clk.cpu_est_11_0_2[1] - Net clk_cpu_est_11_3__n clk.cpu_est_11[3] - Net clk_cpu_est_11_1__n clk.cpu_est_11[1] Net state_machine_un42_clk_030_1_n state_machine.un42_clk_030_1 + Net state_machine_un15_clk_000_d_n state_machine.un15_clk_000_d Net state_machine_un42_clk_030_2_n state_machine.un42_clk_030_2 + Net state_machine_un13_clk_000_d_n state_machine.un13_clk_000_d Net state_machine_un42_clk_030_3_n state_machine.un42_clk_030_3 + Net state_machine_un8_clk_000_d_n state_machine.un8_clk_000_d Net state_machine_un42_clk_030_4_n state_machine.un42_clk_030_4 - Net state_machine_un42_clk_030_5_n state_machine.un42_clk_030_5 - Net state_machine_as_030_000_sync_3_0_1_n state_machine.AS_030_000_SYNC_3_0_1 - Net state_machine_lds_000_int_8_n state_machine.LDS_000_INT_8 - Net state_machine_uds_000_int_8_n state_machine.UDS_000_INT_8 - Net state_machine_un13_clk_000_d_1_0_n state_machine.un13_clk_000_d_1_0 - Net state_machine_un13_clk_000_d_4_1_n state_machine.un13_clk_000_d_4_1 Net state_machine_un8_clk_000_d_1_n state_machine.un8_clk_000_d_1 - Net cpu_est_d_i_3__n cpu_est_d_i[3] + Net state_machine_un42_clk_030_5_n state_machine.un42_clk_030_5 + Net state_machine_un13_clk_000_d_1_n state_machine.un13_clk_000_d_1 + Net state_machine_un8_clk_000_d_1_0_n state_machine.un8_clk_000_d_1_0 Net state_machine_un8_clk_000_d_2_n state_machine.un8_clk_000_d_2 - Net cpu_est_d_i_0__n cpu_est_d_i[0] Net state_machine_un8_clk_000_d_3_n state_machine.un8_clk_000_d_3 - Net state_machine_un8_clk_000_d_4_n state_machine.un8_clk_000_d_4 + Net state_machine_un13_clk_000_d_1_0_n state_machine.un13_clk_000_d_1_0 + Net state_machine_un13_clk_000_d_2_0_n state_machine.un13_clk_000_d_2_0 Net dsack_i_1__n DSACK_i[1] - Net state_machine_un13_clk_000_d_i_n state_machine.un13_clk_000_d_i - Net state_machine_un8_clk_000_d_i_n state_machine.un8_clk_000_d_i - Net sm_amiga_i_6__n SM_AMIGA_i[6] - Net vma_int_0_un3_n VMA_INT_0.un3 Net sm_amiga_i_7__n SM_AMIGA_i[7] - Net vma_int_0_un1_n VMA_INT_0.un1 - Net sm_amiga_i_5__n SM_AMIGA_i[5] - Net vma_int_0_un0_n VMA_INT_0.un0 - Net sm_amiga_i_4__n SM_AMIGA_i[4] - Net lds_000_int_0_un3_n LDS_000_INT_0.un3 - Net state_machine_un13_clk_000_d_1_i_n state_machine.un13_clk_000_d_1_i - Net lds_000_int_0_un1_n LDS_000_INT_0.un1 - Net lds_000_int_0_un0_n LDS_000_INT_0.un0 - Net uds_000_int_0_un3_n UDS_000_INT_0.un3 - Net cpu_est_i_0__n cpu_est_i[0] - Net uds_000_int_0_un1_n UDS_000_INT_0.un1 - Net cpu_est_i_2__n cpu_est_i[2] - Net uds_000_int_0_un0_n UDS_000_INT_0.un0 - Net cpu_est_i_3__n cpu_est_i[3] - Net cpu_est_0_3__un3_n cpu_est_0_3_.un3 - Net cpu_est_i_1__n cpu_est_i[1] - Net cpu_est_0_3__un1_n cpu_est_0_3_.un1 - Net cpu_est_0_3__un0_n cpu_est_0_3_.un0 - Net cpu_est_0_2__un3_n cpu_est_0_2_.un3 - Net cpu_est_0_2__un1_n cpu_est_0_2_.un1 - Net cpu_est_0_2__un0_n cpu_est_0_2_.un0 - Net state_machine_un42_clk_030_i_n state_machine.un42_clk_030_i - Net cpu_est_0_1__un3_n cpu_est_0_1_.un3 - Net cpu_est_0_1__un1_n cpu_est_0_1_.un1 - Net cpu_est_0_1__un0_n cpu_est_0_1_.un0 - Net fpu_cs_int_0_un3_n FPU_CS_INT_0.un3 - Net fpu_cs_int_0_un1_n FPU_CS_INT_0.un1 - Net a_i_18__n A_i[18] - Net fpu_cs_int_0_un0_n FPU_CS_INT_0.un0 - Net a_i_16__n A_i[16] + Net sm_amiga_i_2__n SM_AMIGA_i[2] + Net sm_amiga_i_1__n SM_AMIGA_i[1] Net as_000_int_0_un3_n AS_000_INT_0.un3 - Net a_i_19__n A_i[19] + Net state_machine_un13_clk_000_d_1_i_n state_machine.un13_clk_000_d_1_i Net as_000_int_0_un1_n AS_000_INT_0.un1 Net as_000_int_0_un0_n AS_000_INT_0.un0 + Net vma_int_0_un3_n VMA_INT_0.un3 + Net cpu_est_i_0__n cpu_est_i[0] + Net vma_int_0_un1_n VMA_INT_0.un1 + Net cpu_est_i_1__n cpu_est_i[1] + Net vma_int_0_un0_n VMA_INT_0.un0 + Net cpu_est_i_3__n cpu_est_i[3] + Net uds_000_int_0_un3_n UDS_000_INT_0.un3 + Net state_machine_un8_clk_000_d_1_i_0_n state_machine.un8_clk_000_d_1_i_0 + Net uds_000_int_0_un1_n UDS_000_INT_0.un1 + Net uds_000_int_0_un0_n UDS_000_INT_0.un0 + Net sm_amiga_i_3__n SM_AMIGA_i[3] + Net dtack_sync_0_un3_n DTACK_SYNC_0.un3 + Net sm_amiga_i_4__n SM_AMIGA_i[4] + Net dtack_sync_0_un1_n DTACK_SYNC_0.un1 + Net sm_amiga_i_5__n SM_AMIGA_i[5] + Net dtack_sync_0_un0_n DTACK_SYNC_0.un0 Net vpa_sync_0_un3_n VPA_SYNC_0.un3 Net vpa_sync_0_un1_n VPA_SYNC_0.un1 - Net sm_amiga_i_3__n SM_AMIGA_i[3] Net vpa_sync_0_un0_n VPA_SYNC_0.un0 - Net sm_amiga_i_1__n SM_AMIGA_i[1] - Net as_030_000_sync_0_un3_n AS_030_000_SYNC_0.un3 - Net sm_amiga_i_2__n SM_AMIGA_i[2] - Net as_030_000_sync_0_un1_n AS_030_000_SYNC_0.un1 - Net a_i_30__n A_i[30] - Net as_030_000_sync_0_un0_n AS_030_000_SYNC_0.un0 - Net a_i_31__n A_i[31] - Net ipl_030_0_2__un3_n IPL_030_0_2_.un3 - Net a_i_28__n A_i[28] - Net ipl_030_0_2__un1_n IPL_030_0_2_.un1 - Net a_i_29__n A_i[29] - Net ipl_030_0_2__un0_n IPL_030_0_2_.un0 - Net a_i_26__n A_i[26] - Net ipl_030_0_1__un3_n IPL_030_0_1_.un3 - Net a_i_27__n A_i[27] - Net ipl_030_0_1__un1_n IPL_030_0_1_.un1 - Net a_i_24__n A_i[24] - Net ipl_030_0_1__un0_n IPL_030_0_1_.un0 - Net a_i_25__n A_i[25] - Net ipl_030_0_0__un3_n IPL_030_0_0_.un3 - Net clk_cnt_i_0__n CLK_CNT_i[0] - Net ipl_030_0_0__un1_n IPL_030_0_0_.un1 - Net state_machine_un13_as_000_int_i_n state_machine.un13_as_000_int_i - Net ipl_030_0_0__un0_n IPL_030_0_0_.un0 - Net bgack_030_int_0_un3_n BGACK_030_INT_0.un3 - Net bgack_030_int_0_un1_n BGACK_030_INT_0.un1 - Net bgack_030_int_0_un0_n BGACK_030_INT_0.un0 + Net state_machine_un42_clk_030_i_n state_machine.un42_clk_030_i Net dsack_int_0_1__un3_n DSACK_INT_0_1_.un3 Net dsack_int_0_1__un1_n DSACK_INT_0_1_.un1 Net dsack_int_0_1__un0_n DSACK_INT_0_1_.un0 + Net as_030_000_sync_0_un3_n AS_030_000_SYNC_0.un3 + Net as_030_000_sync_0_un1_n AS_030_000_SYNC_0.un1 + Net cpu_est_i_2__n cpu_est_i[2] + Net as_030_000_sync_0_un0_n AS_030_000_SYNC_0.un0 + Net state_machine_un13_clk_000_d_2_i_n state_machine.un13_clk_000_d_2_i + Net fpu_cs_int_0_un3_n FPU_CS_INT_0.un3 + Net fpu_cs_int_0_un1_n FPU_CS_INT_0.un1 + Net sm_amiga_i_6__n SM_AMIGA_i[6] + Net fpu_cs_int_0_un0_n FPU_CS_INT_0.un0 + Net lds_000_int_0_un3_n LDS_000_INT_0.un3 + Net a_i_30__n A_i[30] + Net lds_000_int_0_un1_n LDS_000_INT_0.un1 + Net a_i_31__n A_i[31] + Net lds_000_int_0_un0_n LDS_000_INT_0.un0 + Net a_i_28__n A_i[28] + Net cpu_est_0_3__un3_n cpu_est_0_3_.un3 + Net a_i_29__n A_i[29] + Net cpu_est_0_3__un1_n cpu_est_0_3_.un1 + Net a_i_26__n A_i[26] + Net cpu_est_0_3__un0_n cpu_est_0_3_.un0 + Net a_i_27__n A_i[27] + Net cpu_est_0_2__un3_n cpu_est_0_2_.un3 + Net a_i_24__n A_i[24] + Net cpu_est_0_2__un1_n cpu_est_0_2_.un1 + Net a_i_25__n A_i[25] + Net cpu_est_0_2__un0_n cpu_est_0_2_.un0 + Net a_i_19__n A_i[19] Net bg_000_0_un3_n BG_000_0.un3 + Net a_i_16__n A_i[16] Net bg_000_0_un1_n BG_000_0.un1 + Net a_i_18__n A_i[18] Net bg_000_0_un0_n BG_000_0.un0 - Net dtack_sync_0_un3_n DTACK_SYNC_0.un3 - Net dtack_sync_0_un1_n DTACK_SYNC_0.un1 + Net clk_cnt_i_0__n CLK_CNT_i[0] + Net bgack_030_int_0_un3_n BGACK_030_INT_0.un3 + Net bgack_030_int_0_un1_n BGACK_030_INT_0.un1 + Net state_machine_un13_as_000_int_i_n state_machine.un13_as_000_int_i + Net bgack_030_int_0_un0_n BGACK_030_INT_0.un0 + Net cpu_est_0_1__un3_n cpu_est_0_1_.un3 + Net cpu_est_0_1__un1_n cpu_est_0_1_.un1 + Net cpu_est_0_1__un0_n cpu_est_0_1_.un0 + Net ipl_030_0_0__un3_n IPL_030_0_0_.un3 + Net ipl_030_0_0__un1_n IPL_030_0_0_.un1 + Net ipl_030_0_0__un0_n IPL_030_0_0_.un0 + Net ipl_030_0_1__un3_n IPL_030_0_1_.un3 + Net ipl_030_0_1__un1_n IPL_030_0_1_.un1 + Net ipl_030_0_1__un0_n IPL_030_0_1_.un0 + Net ipl_030_0_2__un3_n IPL_030_0_2_.un3 Net size_c_0__n SIZE_c[0] - Net dtack_sync_0_un0_n DTACK_SYNC_0.un0 + Net ipl_030_0_2__un1_n IPL_030_0_2_.un1 Net size_0__n SIZE[0] - Net a_15__n A[15] + Net ipl_030_0_2__un0_n IPL_030_0_2_.un0 Net size_c_1__n SIZE_c[1] - Net a_14__n A[14] + Net a_15__n A[15] Net a_c_0__n A_c[0] + Net a_14__n A[14] Net a_0__n A[0] Net a_13__n A[13] Net a_12__n A[12] @@ -497,20 +489,20 @@ Design 'BUS68030' created Thu May 15 22:21:53 2014 Net a_7__n A[7] Net a_6__n A[6] Net a_c_16__n A_c[16] - Net a_5__n A[5] Net a_16__n A[16] + Net a_5__n A[5] Net a_c_17__n A_c[17] - Net a_4__n A[4] Net a_17__n A[17] + Net a_4__n A[4] Net a_c_18__n A_c[18] - Net a_3__n A[3] Net a_18__n A[18] + Net a_3__n A[3] Net a_c_19__n A_c[19] - Net a_2__n A[2] Net a_19__n A[19] + Net a_2__n A[2] Net a_c_20__n A_c[20] - Net a_1__n A[1] Net a_20__n A[20] + Net a_1__n A[1] Net a_c_21__n A_c[21] Net a_21__n A[21] Net a_c_22__n A_c[22] @@ -532,6 +524,8 @@ Design 'BUS68030' created Thu May 15 22:21:53 2014 Net a_c_30__n A_c[30] Net a_30__n A[30] Net a_c_31__n A_c[31] + Net ipl_030_c_0__n IPL_030_c[0] + Net ipl_030_0__n IPL_030[0] End Section Type Name // ---------------------------------------------------------------------- diff --git a/Logic/bus68030.srf b/Logic/bus68030.srf index 051b806..4254163 100644 --- a/Logic/bus68030.srf +++ b/Logic/bus68030.srf @@ -6,7 +6,7 @@ #Implementation: logic $ Start of Compile -#Thu May 15 22:21:47 2014 +#Thu May 15 23:02:39 2014 Synopsys VHDL Compiler, version comp201209rcp1, Build 283R, built Mar 19 2013 @N|Running in 64-bit mode @@ -18,20 +18,17 @@ File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - VHDL syntax check successful! File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling @N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":6:7:6:14|Synthesizing work.bus68030.behavioral -@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:7:109:15|Signal clk_030_d is undriven +@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":106:7:106:15|Signal clk_030_d is undriven Post processing for work.bus68030.behavioral -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":100:29:100:31|Pruning register SM_AMIGA_D(2 downto 0) -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":105:52:105:55|Pruning register VMA_INT_D -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":91:32:91:34|Pruning register CLK_REF(1 downto 0) -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":220:2:220:3|Pruning register AS_000_START -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":113:38:113:40|Pruning register CLK_000_CNT(3 downto 0) -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":112:37:112:39|Pruning register FALLING_CLK_AMIGA -@W: CL190 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":100:29:100:31|Optimizing register bit DSACK_INT(0) to a constant 1 -@W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":100:29:100:31|Pruning register bit 0 of DSACK_INT(1 downto 0) -@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:2:124:3|Register bit CLK_CNT(1) is always 0, optimizing ... -@W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:2:124:3|Pruning register bit 1 of CLK_CNT(1 downto 0) -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":113:38:113:40|Trying to extract state machine for register cpu_est -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":220:2:220:3|Trying to extract state machine for register SM_AMIGA +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":176:2:176:3|Pruning register CLK_REF(1 downto 0) +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":108:32:108:34|Pruning register cpu_est_d(3 downto 0) +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":108:32:108:34|Pruning register CLK_000_CNT(3 downto 0) +@W: CL190 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":102:52:102:55|Optimizing register bit DSACK_INT(0) to a constant 1 +@W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":102:52:102:55|Pruning register bit 0 of DSACK_INT(1 downto 0) +@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":117:2:117:3|Register bit CLK_CNT(1) is always 0, optimizing ... +@W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":117:2:117:3|Pruning register bit 1 of CLK_CNT(1 downto 0) +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":108:32:108:34|Trying to extract state machine for register cpu_est +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":176:2:176:3|Trying to extract state machine for register SM_AMIGA Extracted state machine for register SM_AMIGA State machine has 8 reachable states with original encodings of: 000 @@ -42,10 +39,10 @@ State machine has 8 reachable states with original encodings of: 101 110 111 -@W: CL249 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":220:2:220:3|Initial value is not supported on state machine SM_AMIGA +@W: CL249 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":176:2:176:3|Initial value is not supported on state machine SM_AMIGA @END Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Thu May 15 22:21:47 2014 +# Thu May 15 23:02:39 2014 ###########################################################] Map & Optimize Report @@ -64,19 +61,19 @@ original code -> new code 101 -> 00100000 110 -> 01000000 111 -> 10000000 -@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":160:4:160:7|Found ROM, 'clk\.cpu_est_11[3:0]', 16 words by 4 bits +@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":145:4:145:7|Found ROM, 'clk\.cpu_est_11[3:0]', 16 words by 4 bits --------------------------------------- Resource Usage Report Simple gate primitives: -DFF 16 uses -DFFSH 16 uses DFFRH 7 uses +DFFSH 16 uses +DFF 11 uses IBUF 35 uses BUFTH 7 uses OBUF 15 uses BI_DIR 2 uses -AND2 149 uses +AND2 147 uses INV 119 uses OR2 17 uses XOR2 2 uses @@ -89,6 +86,6 @@ Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 95MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Thu May 15 22:21:49 2014 +# Thu May 15 23:02:41 2014 ###########################################################] diff --git a/Logic/run_options.txt b/Logic/run_options.txt index 7ede2e0..2cc9e7b 100644 --- a/Logic/run_options.txt +++ b/Logic/run_options.txt @@ -1,7 +1,7 @@ #-- Synopsys, Inc. #-- Version G-2012.09LC-SP1 #-- Project file C:\users\matze\documents\github\68030tk\logic\run_options.txt -#-- Written on Thu May 15 22:21:47 2014 +#-- Written on Thu May 15 23:02:39 2014 #project files diff --git a/Logic/synlog/bus68030_fpga_mapper.srr b/Logic/synlog/bus68030_fpga_mapper.srr index 767bd24..5d7699a 100644 --- a/Logic/synlog/bus68030_fpga_mapper.srr +++ b/Logic/synlog/bus68030_fpga_mapper.srr @@ -12,19 +12,19 @@ original code -> new code 101 -> 00100000 110 -> 01000000 111 -> 10000000 -@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":160:4:160:7|Found ROM, 'clk\.cpu_est_11[3:0]', 16 words by 4 bits +@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":145:4:145:7|Found ROM, 'clk\.cpu_est_11[3:0]', 16 words by 4 bits --------------------------------------- Resource Usage Report Simple gate primitives: -DFF 16 uses -DFFSH 16 uses DFFRH 7 uses +DFFSH 16 uses +DFF 11 uses IBUF 35 uses BUFTH 7 uses OBUF 15 uses BI_DIR 2 uses -AND2 149 uses +AND2 147 uses INV 119 uses OR2 17 uses XOR2 2 uses @@ -37,6 +37,6 @@ Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 95MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Thu May 15 22:21:49 2014 +# Thu May 15 23:02:41 2014 ###########################################################] diff --git a/Logic/synlog/report/BUS68030_compiler_errors.txt b/Logic/synlog/report/BUS68030_compiler_errors.txt index 226dbd1..cf2947a 100644 --- a/Logic/synlog/report/BUS68030_compiler_errors.txt +++ b/Logic/synlog/report/BUS68030_compiler_errors.txt @@ -1,3 +1,3 @@ -@E: CD255 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":317:36:317:36|No identifier "clk_00_dd" in scope +@E: CD200 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":184:3:184:11|Misspelled variable, signal or procedure name? @E|Parse errors encountered - exiting diff --git a/Logic/synlog/report/BUS68030_compiler_notes.txt b/Logic/synlog/report/BUS68030_compiler_notes.txt index 85f68a0..76d16db 100644 --- a/Logic/synlog/report/BUS68030_compiler_notes.txt +++ b/Logic/synlog/report/BUS68030_compiler_notes.txt @@ -2,6 +2,6 @@ @N: CD720 :"C:\Program Files (x86)\ispLever\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns @N:"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":6:7:6:14|Top entity is set to BUS68030. @N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":6:7:6:14|Synthesizing work.bus68030.behavioral -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":113:38:113:40|Trying to extract state machine for register cpu_est -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":220:2:220:3|Trying to extract state machine for register SM_AMIGA +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":108:32:108:34|Trying to extract state machine for register cpu_est +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":176:2:176:3|Trying to extract state machine for register SM_AMIGA diff --git a/Logic/synlog/report/BUS68030_compiler_runstatus.xml b/Logic/synlog/report/BUS68030_compiler_runstatus.xml index ca18850..a1431e9 100644 --- a/Logic/synlog/report/BUS68030_compiler_runstatus.xml +++ b/Logic/synlog/report/BUS68030_compiler_runstatus.xml @@ -18,7 +18,7 @@ The file contains the job information from compiler to be displayed as part of t C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_notes.txt - 12 + 9 C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_warnings.txt @@ -29,13 +29,13 @@ The file contains the job information from compiler to be displayed as part of t - - 0h:00m:00s + 0h:00m:01s - - 1400185307 + 1400187759 \ No newline at end of file diff --git a/Logic/synlog/report/BUS68030_compiler_warnings.txt b/Logic/synlog/report/BUS68030_compiler_warnings.txt index 2bed995..49bb8fc 100644 --- a/Logic/synlog/report/BUS68030_compiler_warnings.txt +++ b/Logic/synlog/report/BUS68030_compiler_warnings.txt @@ -1,13 +1,10 @@ -@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:7:109:15|Signal clk_030_d is undriven -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":100:29:100:31|Pruning register SM_AMIGA_D(2 downto 0) -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":105:52:105:55|Pruning register VMA_INT_D -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":91:32:91:34|Pruning register CLK_REF(1 downto 0) -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":220:2:220:3|Pruning register AS_000_START -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":113:38:113:40|Pruning register CLK_000_CNT(3 downto 0) -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":112:37:112:39|Pruning register FALLING_CLK_AMIGA -@W: CL190 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":100:29:100:31|Optimizing register bit DSACK_INT(0) to a constant 1 -@W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":100:29:100:31|Pruning register bit 0 of DSACK_INT(1 downto 0) -@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:2:124:3|Register bit CLK_CNT(1) is always 0, optimizing ... -@W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:2:124:3|Pruning register bit 1 of CLK_CNT(1 downto 0) -@W: CL249 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":220:2:220:3|Initial value is not supported on state machine SM_AMIGA +@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":106:7:106:15|Signal clk_030_d is undriven +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":176:2:176:3|Pruning register CLK_REF(1 downto 0) +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":108:32:108:34|Pruning register cpu_est_d(3 downto 0) +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":108:32:108:34|Pruning register CLK_000_CNT(3 downto 0) +@W: CL190 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":102:52:102:55|Optimizing register bit DSACK_INT(0) to a constant 1 +@W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":102:52:102:55|Pruning register bit 0 of DSACK_INT(1 downto 0) +@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":117:2:117:3|Register bit CLK_CNT(1) is always 0, optimizing ... +@W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":117:2:117:3|Pruning register bit 1 of CLK_CNT(1 downto 0) +@W: CL249 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":176:2:176:3|Initial value is not supported on state machine SM_AMIGA diff --git a/Logic/synlog/report/BUS68030_fpga_mapper_notes.txt b/Logic/synlog/report/BUS68030_fpga_mapper_notes.txt index f838e66..231518f 100644 --- a/Logic/synlog/report/BUS68030_fpga_mapper_notes.txt +++ b/Logic/synlog/report/BUS68030_fpga_mapper_notes.txt @@ -1,3 +1,3 @@ @N: MF248 |Running in 64-bit mode. -@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":160:4:160:7|Found ROM, 'clk\.cpu_est_11[3:0]', 16 words by 4 bits +@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":145:4:145:7|Found ROM, 'clk\.cpu_est_11[3:0]', 16 words by 4 bits @N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis. diff --git a/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml b/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml index e519c5c..12dba0d 100644 --- a/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml +++ b/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml @@ -39,7 +39,7 @@ The file contains the job information from mapper to be displayed as part of the 95MB -1400185309 +1400187761 diff --git a/Logic/syntmp/run_option.xml b/Logic/syntmp/run_option.xml index 19d9ce5..71da6a4 100644 --- a/Logic/syntmp/run_option.xml +++ b/Logic/syntmp/run_option.xml @@ -3,7 +3,7 @@ Synopsys, Inc. Version G-2012.09LC-SP1 Project file C:\users\matze\documents\github\68030tk\logic\syntmp\run_option.xml - Written on Thu May 15 22:21:47 2014 + Written on Thu May 15 23:02:39 2014 --> diff --git a/Logic/synwork/BUS68030_compiler.fdep b/Logic/synwork/BUS68030_compiler.fdep index 057f8f6..dacc04f 100644 --- a/Logic/synwork/BUS68030_compiler.fdep +++ b/Logic/synwork/BUS68030_compiler.fdep @@ -10,7 +10,7 @@ #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328 -#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1400185298 +#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1400187757 0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl # Dependency Lists (Uses list) diff --git a/Logic/synwork/BUS68030_compiler.fdeporig b/Logic/synwork/BUS68030_compiler.fdeporig index 94c6d2a..6d455e2 100644 --- a/Logic/synwork/BUS68030_compiler.fdeporig +++ b/Logic/synwork/BUS68030_compiler.fdeporig @@ -10,7 +10,7 @@ #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328 -#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1400185298 +#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1400187757 0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl # Dependency Lists (Uses list) diff --git a/Logic/synwork/BUS68030_compiler.srs b/Logic/synwork/BUS68030_compiler.srs index 1cdfca0..db16274 100644 Binary files a/Logic/synwork/BUS68030_compiler.srs and b/Logic/synwork/BUS68030_compiler.srs differ diff --git a/Logic/synwork/BUS68030_compiler.tlg b/Logic/synwork/BUS68030_compiler.tlg index 457e5e3..56fa794 100644 --- a/Logic/synwork/BUS68030_compiler.tlg +++ b/Logic/synwork/BUS68030_compiler.tlg @@ -1,18 +1,15 @@ @N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":6:7:6:14|Synthesizing work.bus68030.behavioral -@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:7:109:15|Signal clk_030_d is undriven +@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":106:7:106:15|Signal clk_030_d is undriven Post processing for work.bus68030.behavioral -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":100:29:100:31|Pruning register SM_AMIGA_D(2 downto 0) -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":105:52:105:55|Pruning register VMA_INT_D -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":91:32:91:34|Pruning register CLK_REF(1 downto 0) -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":220:2:220:3|Pruning register AS_000_START -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":113:38:113:40|Pruning register CLK_000_CNT(3 downto 0) -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":112:37:112:39|Pruning register FALLING_CLK_AMIGA -@W: CL190 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":100:29:100:31|Optimizing register bit DSACK_INT(0) to a constant 1 -@W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":100:29:100:31|Pruning register bit 0 of DSACK_INT(1 downto 0) -@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:2:124:3|Register bit CLK_CNT(1) is always 0, optimizing ... -@W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:2:124:3|Pruning register bit 1 of CLK_CNT(1 downto 0) -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":113:38:113:40|Trying to extract state machine for register cpu_est -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":220:2:220:3|Trying to extract state machine for register SM_AMIGA +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":176:2:176:3|Pruning register CLK_REF(1 downto 0) +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":108:32:108:34|Pruning register cpu_est_d(3 downto 0) +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":108:32:108:34|Pruning register CLK_000_CNT(3 downto 0) +@W: CL190 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":102:52:102:55|Optimizing register bit DSACK_INT(0) to a constant 1 +@W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":102:52:102:55|Pruning register bit 0 of DSACK_INT(1 downto 0) +@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":117:2:117:3|Register bit CLK_CNT(1) is always 0, optimizing ... +@W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":117:2:117:3|Pruning register bit 1 of CLK_CNT(1 downto 0) +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":108:32:108:34|Trying to extract state machine for register cpu_est +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":176:2:176:3|Trying to extract state machine for register SM_AMIGA Extracted state machine for register SM_AMIGA State machine has 8 reachable states with original encodings of: 000 @@ -23,4 +20,4 @@ State machine has 8 reachable states with original encodings of: 101 110 111 -@W: CL249 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":220:2:220:3|Initial value is not supported on state machine SM_AMIGA +@W: CL249 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":176:2:176:3|Initial value is not supported on state machine SM_AMIGA