diff --git a/Logic/68030-68000-bus.vhd b/Logic/68030-68000-bus.vhd index ca47a44..e5eabad 100644 --- a/Logic/68030-68000-bus.vhd +++ b/Logic/68030-68000-bus.vhd @@ -107,11 +107,13 @@ signal DS_030_D0:STD_LOGIC := '1'; signal AS_030_000_SYNC:STD_LOGIC := '1'; signal BGACK_030_INT:STD_LOGIC := '1'; signal BGACK_030_INT_D:STD_LOGIC := '1'; +signal BGACK_030_INT_PRE:STD_LOGIC := '1'; signal AS_000_DMA:STD_LOGIC := '1'; signal DS_000_DMA:STD_LOGIC := '1'; signal RW_000_DMA:STD_LOGIC := '1'; signal CYCLE_DMA: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00"; signal SIZE_DMA: STD_LOGIC_VECTOR ( 1 downto 0 ) := "11"; +signal IPL_D0: STD_LOGIC_VECTOR ( 2 downto 0 ) := "111"; signal A0_DMA: STD_LOGIC := '1'; signal VMA_INT: STD_LOGIC := '1'; signal VPA_D: STD_LOGIC := '1'; @@ -139,6 +141,7 @@ signal DTACK_D0: STD_LOGIC := '1'; signal RESET_OUT: STD_LOGIC := '0'; signal CLK_030_D0: STD_LOGIC := '0'; --signal NO_RESET: STD_LOGIC := '0'; +signal RST_DLY: STD_LOGIC_VECTOR ( 7 downto 0 ) := "00000000"; begin @@ -223,7 +226,9 @@ begin BG_000 <= '1'; BGACK_030_INT <= '1'; BGACK_030_INT_D <= '1'; + BGACK_030_INT_PRE<= '1'; DSACK1_INT <= '1'; + IPL_D0 <= "111"; IPL_030 <= "111"; AS_000_DMA <= '1'; DS_000_DMA <= '1'; @@ -237,10 +242,17 @@ begin DS_030_D0 <= '1'; CLK_030_H <= '0'; CYCLE_DMA <= "00"; + RST_DLY <= "00000000"; RESET_OUT <= '0'; else - - RESET_OUT <= '1'; + + if(CLK_000_NE='1')then + if(RST_DLY="11111111")then + RESET_OUT <= '1'; + else + RST_DLY <= RST_DLY+1; + end if; + end if; --now: 68000 state machine and signals @@ -259,7 +271,8 @@ begin AND CLK_000_PE='1' --AND CLK_000_D0='1' and CLK_000_D1='0' ) then -- BGACK_000 is high here! - BGACK_030_INT <= '1'; --hold this signal high until 7m clock goes high + BGACK_030_INT_PRE<= '1'; + BGACK_030_INT <= BGACK_030_INT_PRE; --hold this signal high until 7m clock goes low end if; BGACK_030_INT_D <= BGACK_030_INT; @@ -278,10 +291,13 @@ begin --interrupt buffering to avoid ghost interrupts - if(CLK_000_NE='1')then + --if(CLK_000_NE='1')then --if(CLK_000_D0='0' and CLK_000_D1='1')then - IPL_030<=IPL; - end if; + IPL_D0<=IPL; + if(IPL = IPL_D0)then + IPL_030<=IPL; + end if; + --end if; -- as030-sampling and FPU-Select @@ -476,10 +492,10 @@ begin end process pos_clk; --output clock assignment - CLK_DIV_OUT <= CLK_OUT_INT; - CLK_EXP <= CLK_OUT_INT; - --CLK_DIV_OUT <= 'Z'; - --CLK_EXP <= CLK_030; + --CLK_DIV_OUT <= CLK_OUT_INT; + --CLK_EXP <= CLK_OUT_INT; + CLK_DIV_OUT <= 'Z'; + CLK_EXP <= CLK_030; diff --git a/Logic/68030_TK.tcl b/Logic/68030_TK.tcl index 3da56d7..e2dcbe2 100644 --- a/Logic/68030_TK.tcl +++ b/Logic/68030_TK.tcl @@ -338702,3 +338702,1284 @@ if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 6 ########## Tcl recorder end at 03/28/15 22:02:32 ########### + +########## Tcl recorder starts at 04/08/15 17:22:08 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 04/08/15 17:22:08 ########### + + +########## Tcl recorder starts at 04/08/15 17:22:08 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 04/08/15 17:22:08 ########### + + +########## Tcl recorder starts at 04/08/15 20:17:33 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 04/08/15 20:17:33 ########### + + +########## Tcl recorder starts at 04/08/15 20:17:33 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 04/08/15 20:17:33 ########### + + +########## Tcl recorder starts at 04/08/15 20:28:50 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 04/08/15 20:28:50 ########### + + +########## Tcl recorder starts at 04/08/15 20:28:50 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 04/08/15 20:28:50 ########### + + +########## Tcl recorder starts at 05/13/15 22:45:25 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/13/15 22:45:25 ########### + + +########## Tcl recorder starts at 05/13/15 22:45:26 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/13/15 22:45:26 ########### + + +########## Tcl recorder starts at 05/13/15 22:46:04 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/13/15 22:46:04 ########### + + +########## Tcl recorder starts at 05/13/15 22:46:05 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/13/15 22:46:05 ########### + + +########## Tcl recorder starts at 05/13/15 22:46:37 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/13/15 22:46:37 ########### + + +########## Tcl recorder starts at 05/13/15 22:46:37 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/13/15 22:46:37 ########### + + +########## Tcl recorder starts at 05/13/15 22:59:07 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/13/15 22:59:07 ########### + + +########## Tcl recorder starts at 05/13/15 22:59:07 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/13/15 22:59:07 ########### + diff --git a/Logic/68030_tk.b2_ b/Logic/68030_tk.b2_ new file mode 100644 index 0000000..4ef6a67 --- /dev/null +++ b/Logic/68030_tk.b2_ @@ -0,0 +1 @@ + -collapse all -pterms 16 -nmax 32 -clust 5 -reduce bypin choose -xorsyn -dev M4A5_clk diff --git a/Logic/68030_tk.bl2 b/Logic/68030_tk.bl2 new file mode 100644 index 0000000..91eb977 --- /dev/null +++ b/Logic/68030_tk.bl2 @@ -0,0 +1,2434 @@ +#$ TOOL ispLEVER Classic 1.8.00.04.29.14 +#$ DATE Wed May 13 22:59:21 2015 +#$ MODULE 68030_tk +#$ PINS 75 A_28_ A_27_ SIZE_1_ A_26_ A_25_ A_31_ A_24_ A_23_ IPL_030_2_ A_22_ A_21_ \ +# IPL_2_ A_20_ A_19_ FC_1_ A_18_ AS_030 A_17_ AS_000 A_16_ RW_000 A_15_ DS_030 A_14_ UDS_000 \ +# A_13_ LDS_000 A_12_ A0 A_11_ A1 A_10_ nEXP_SPACE A_9_ BERR A_8_ BG_030 A_7_ BG_000 A_6_ \ +# BGACK_030 A_5_ BGACK_000 A_4_ CLK_030 A_3_ CLK_000 A_2_ CLK_OSZI IPL_030_1_ CLK_DIV_OUT \ +# IPL_030_0_ CLK_EXP IPL_1_ FPU_CS IPL_0_ FPU_SENSE FC_0_ DSACK1 DTACK AVEC E VPA VMA RST \ +# RESET RW AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ +# AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ A_30_ A_29_ +#$ NODES 695 N_310 un1_rst_dly_i_m_i_5__n sm_amiga_srsts_i_0_m2_3__un0_n N_220 \ +# sm_amiga_srsts_i_0_m2_1__un3_n pos_clk_cpu_est_11_1__n un1_rst_dly_i_m_i_6__n \ +# sm_amiga_srsts_i_0_m2_1__un1_n N_14 sm_amiga_srsts_i_0_m2_1__un0_n N_18 \ +# un1_rst_dly_i_m_i_7__n un1_amiga_bus_enable_dma_high_0_m2_0__un3_n N_22 \ +# un1_amiga_bus_enable_dma_high_0_m2_0__un1_n inst_BGACK_030_INTreg \ +# RESET_OUT_0_sqmuxa_1 un1_rst_dly_i_m_i_8__n \ +# un1_amiga_bus_enable_dma_high_0_m2_0__un0_n vcc_n_n N_205 \ +# un1_sm_amiga_7_i_m2_un3_n cpu_est_3_reg N_213 un1_rst_dly_i_m_i_2__n \ +# un1_sm_amiga_7_i_m2_un1_n inst_VMA_INTreg pos_clk_RST_DLY_5_iv_0_x2_0_ \ +# un1_sm_amiga_7_i_m2_un0_n inst_RESET_OUTreg N_105 N_98_i size_dma_0_0__un3_n \ +# gnd_n_n N_98 size_dma_0_0__un1_n un1_amiga_bus_enable_low RESET_OUT_0_sqmuxa \ +# N_105_i size_dma_0_0__un0_n un6_as_030 un1_rst_dly_i_m_2__n size_dma_0_1__un3_n \ +# un3_size G_137 N_22_i size_dma_0_1__un1_n un4_size un1_rst_dly_i_m_8__n N_33_0 \ +# size_dma_0_1__un0_n un5_ciin G_149 N_18_i ipl_030_0_0__un3_n un4_as_000 \ +# RESET_OUT_0_sqmuxa_5 N_37_0 ipl_030_0_0__un1_n un21_fpu_cs RESET_OUT_0_sqmuxa_7 \ +# N_14_i ipl_030_0_0__un0_n un22_berr G_147 N_41_0 ipl_030_0_1__un3_n un6_ds_030 G_145 \ +# N_10_i ipl_030_0_1__un1_n un6_uds_000 N_211 N_44_0 ipl_030_0_1__un0_n un6_lds_000 \ +# G_143 pos_clk_cpu_est_11_0_1__n ipl_030_0_2__un3_n cpu_est_0_ N_209 N_312_i \ +# ipl_030_0_2__un1_n cpu_est_1_ G_141 N_90_i ipl_030_0_2__un0_n inst_AS_000_INT G_139 \ +# N_88_i amiga_bus_enable_dma_high_0_un3_n SM_AMIGA_5_ un1_rst_dly_i_m_7__n N_299_i \ +# amiga_bus_enable_dma_high_0_un1_n inst_AMIGA_BUS_ENABLE_DMA_LOW \ +# un1_rst_dly_i_m_6__n N_275_0 amiga_bus_enable_dma_high_0_un0_n inst_AS_030_D0 \ +# un1_rst_dly_i_m_5__n N_274_0 bg_000_0_un3_n inst_nEXP_SPACE_D0reg \ +# un1_rst_dly_i_m_4__n N_273_i bg_000_0_un1_n inst_DS_030_D0 un1_rst_dly_i_m_3__n \ +# N_272_i bg_000_0_un0_n inst_AS_030_000_SYNC N_71_i N_270_i ds_000_dma_0_un3_n \ +# inst_BGACK_030_INT_D un1_amiga_bus_enable_low_i N_268_i ds_000_dma_0_un1_n \ +# inst_AS_000_DMA un21_fpu_cs_i N_310_i ds_000_dma_0_un0_n inst_DS_000_DMA \ +# RESET_OUT_i N_311_i as_000_dma_0_un3_n CYCLE_DMA_0_ BGACK_030_INT_i N_267_0 \ +# as_000_dma_0_un1_n CYCLE_DMA_1_ RESET_OUT_0_sqmuxa_i N_309_i as_000_dma_0_un0_n \ +# SIZE_DMA_0_ un1_rst_dly_i_3__n N_308_i a0_dma_0_un3_n SIZE_DMA_1_ \ +# un1_rst_dly_i_4__n pos_clk_un7_clk_000_pe_0_n a0_dma_0_un1_n inst_VPA_D \ +# un1_rst_dly_i_5__n N_264_0 a0_dma_0_un0_n inst_UDS_000_INT un1_rst_dly_i_6__n \ +# N_304_i dsack1_int_0_un3_n inst_LDS_000_INT un1_rst_dly_i_7__n N_303_i \ +# dsack1_int_0_un1_n inst_CLK_OUT_PRE_D un1_rst_dly_i_8__n N_186_i \ +# dsack1_int_0_un0_n inst_DTACK_D0 un1_rst_dly_i_2__n VPA_c_i as_000_int_0_un3_n \ +# inst_CLK_OUT_PRE_50 N_87_i_i N_56_0 as_000_int_0_un1_n inst_CLK_000_D1 \ +# cpu_est_i_3__n DTACK_c_i as_000_int_0_un0_n inst_CLK_000_D0 cpu_est_i_0__n N_57_0 \ +# ds_000_enable_0_un3_n inst_CLK_000_PE VPA_D_i N_97_i ds_000_enable_0_un1_n \ +# CLK_000_P_SYNC_9_ VMA_INT_i ds_000_enable_0_un0_n inst_CLK_000_NE cpu_est_i_1__n \ +# N_96_i as_030_000_sync_0_un3_n CLK_000_N_SYNC_11_ CLK_000_PE_i N_95_i \ +# as_030_000_sync_0_un1_n cpu_est_2_ BERR_i N_94_i as_030_000_sync_0_un0_n IPL_D0_0_ \ +# sm_amiga_i_4__n N_313_i lds_000_int_0_un3_n IPL_D0_1_ cpu_est_i_2__n N_136_i \ +# lds_000_int_0_un1_n IPL_D0_2_ sm_amiga_i_5__n N_81_0 lds_000_int_0_un0_n \ +# SM_AMIGA_3_ DTACK_D0_i N_116_i rw_000_dma_0_un3_n inst_CLK_000_NE_D0 \ +# sm_amiga_i_0__n N_77_i rw_000_dma_0_un1_n pos_clk_un6_bg_030_n sm_amiga_i_3__n \ +# N_73_i rw_000_dma_0_un0_n SM_AMIGA_0_ CLK_000_NE_i N_101_i uds_000_int_0_un3_n \ +# inst_AMIGA_BUS_ENABLE_DMA_HIGH sm_amiga_i_6__n uds_000_int_0_un1_n \ +# inst_DSACK1_INTreg sm_amiga_i_1__n clk_000_n_sync_i_10__n uds_000_int_0_un0_n \ +# CLK_OUT_PRE_D_i pos_clk_un9_clk_000_n_sync_i_n amiga_bus_enable_dma_low_0_un3_n \ +# pos_clk_ipl_n pos_clk_un11_clk_000_n_sync_i_n pos_clk_un14_clk_000_n_sync_0_n \ +# amiga_bus_enable_dma_low_0_un1_n pos_clk_un3_ds_030_d0_n LDS_000_i \ +# pos_clk_un22_bgack_030_int_i_n amiga_bus_enable_dma_low_0_un0_n SM_AMIGA_6_ \ +# UDS_000_i N_86_i a_15__n AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa nEXP_SPACE_D0_i N_93_i \ +# RST_DLY_0_ sm_amiga_i_2__n a_14__n RST_DLY_1_ AS_030_i N_99_i RST_DLY_2_ A1_i \ +# pos_clk_size_dma_6_0_1__n a_13__n RST_DLY_3_ CLK_000_D1_i N_100_i RST_DLY_4_ \ +# RW_000_i pos_clk_size_dma_6_0_0__n a_12__n RST_DLY_5_ CLK_030_H_i N_245_0 RST_DLY_6_ \ +# AS_000_DMA_i N_108_i a_11__n RST_DLY_7_ AS_000_i N_109_i pos_clk_un8_bg_030_n \ +# sm_amiga_i_i_7__n N_246_0 a_10__n CLK_000_P_SYNC_0_ RW_i un5_ciin_i \ +# CLK_000_P_SYNC_1_ AMIGA_BUS_ENABLE_DMA_HIGH_i N_247_0 a_9__n CLK_000_P_SYNC_2_ \ +# FPU_SENSE_i N_248_0 CLK_000_P_SYNC_3_ AS_030_D0_i CLK_000_D0_i a_8__n \ +# CLK_000_P_SYNC_4_ a_i_24__n N_249_i CLK_000_P_SYNC_5_ size_dma_i_0__n \ +# AS_030_000_SYNC_i a_7__n CLK_000_P_SYNC_6_ size_dma_i_1__n N_251_0 \ +# CLK_000_P_SYNC_7_ a_i_16__n pos_clk_un3_as_030_d0_i_n a_6__n CLK_000_P_SYNC_8_ \ +# a_i_18__n pos_clk_un5_bgack_030_int_d_i_n CLK_000_N_SYNC_0_ a_i_19__n N_75_i a_5__n \ +# CLK_000_N_SYNC_1_ a_i_31__n N_76_i CLK_000_N_SYNC_2_ a_i_29__n N_78_0 a_4__n \ +# CLK_000_N_SYNC_3_ a_i_30__n N_80_0 CLK_000_N_SYNC_4_ a_i_27__n CLK_EXP_c_i a_3__n \ +# CLK_000_N_SYNC_5_ a_i_28__n N_258_0 CLK_000_N_SYNC_6_ a_i_25__n N_283_i a_2__n \ +# CLK_000_N_SYNC_7_ a_i_26__n N_284_i CLK_000_N_SYNC_8_ UDS_000_INT_i \ +# CLK_000_N_SYNC_9_ LDS_000_INT_i N_290_i CLK_000_N_SYNC_10_ DS_030_i N_291_i \ +# pos_clk_un5_bgack_030_int_d_n N_224_i inst_RW_000_INT N_225_i N_279_i \ +# inst_RW_000_DMA N_226_i N_293_i inst_A0_DMA inst_CLK_030_H N_82_i SM_AMIGA_1_ N_83_i \ +# SM_AMIGA_4_ N_104_i N_259_0 SM_AMIGA_2_ N_103_i N_84_i pos_clk_un3_as_030_d0_n \ +# N_282_i N_115_0 inst_DS_000_ENABLE N_92_i N_85_i AS_000_INT_1_sqmuxa un6_lds_000_i \ +# N_294_i DS_000_ENABLE_1_sqmuxa_1 un6_uds_000_i N_296_i pos_clk_a0_dma_3_n \ +# un6_ds_030_i pos_clk_cpu_est_11_0_3__n pos_clk_ds_000_dma_4_n DS_000_DMA_i N_91_i \ +# N_3 un4_as_000_i N_260_0 AS_000_INT_i N_301_i un6_as_030_i pos_clk_ds_000_dma_4_0_n \ +# N_6 AMIGA_BUS_ENABLE_DMA_LOW_i N_305_i N_8 DS_030_D0_i N_306_i N_9 AS_030_c \ +# AMIGA_BUS_DATA_DIR_c_0 N_10 N_307_i N_11 AS_000_c N_12 N_13 RW_000_c N_15 N_265_0 N_16 \ +# DS_030_c N_269_i N_19 pos_clk_un24_bgack_030_int_i_0_i_n N_20 UDS_000_c N_62_0 N_21 \ +# N_276_0 N_23 LDS_000_c N_277_0 N_24 N_286_i N_25 size_c_0__n N_288_i N_289_i size_c_1__n \ +# pos_clk_un11_ds_030_d0_i_n A0_c_i size_c_i_1__n N_25_i N_32_0 N_24_i N_31_0 N_23_i \ +# N_30_0 ipl_c_i_2__n N_54_0 ipl_c_i_1__n N_53_0 ipl_c_i_0__n N_52_0 nEXP_SPACE_c_i \ +# N_55_0 N_50_0 N_3_i N_49_0 N_6_i N_48_0 N_8_i N_46_0 N_9_i N_45_0 N_12_i SM_AMIGA_i_7_ \ +# N_43_0 N_115 N_13_i pos_clk_size_dma_6_0__n a_c_16__n N_42_0 pos_clk_size_dma_6_1__n \ +# N_15_i pos_clk_cpu_est_11_3__n a_c_17__n N_40_0 G_165 N_16_i G_166 a_c_18__n N_39_0 \ +# G_167 N_19_i un6_uds_000_1 a_c_19__n N_36_0 pos_clk_un24_bgack_030_int_i_0_n N_20_i \ +# N_245 a_c_20__n N_35_0 N_246 N_21_i N_247 a_c_21__n N_34_0 N_248 BG_030_c_i N_89 \ +# a_c_22__n pos_clk_un6_bg_030_i_n N_92 pos_clk_un8_bg_030_0_n N_102 a_c_23__n \ +# N_127_i_1 N_103 N_127_i_2 N_104 a_c_24__n pos_clk_un24_bgack_030_int_i_0_i_1_n N_112 \ +# N_80_0_1 N_256 a_c_25__n N_75_i_1 N_258 N_251_0_1 a_c_26__n \ +# pos_clk_un11_ds_030_d0_i_1_n N_260 N_340_1 N_265 a_c_27__n N_340_2 N_282 N_340_3 N_71 \ +# a_c_28__n N_340_4 cpu_est_0_0_x2_0_ un5_ciin_1 pos_clk_un11_clk_000_n_sync_n \ +# a_c_29__n un5_ciin_2 N_76 un5_ciin_3 pos_clk_CYCLE_DMA_5_1_i_x2 a_c_30__n un5_ciin_4 \ +# pos_clk_CYCLE_DMA_5_0_i_x2 un5_ciin_5 pos_clk_un24_bgack_030_int_i_0_x2 a_c_31__n \ +# un5_ciin_6 pos_clk_un22_bgack_030_int_n un5_ciin_7 N_268 A0_c un5_ciin_8 N_270 \ +# un5_ciin_9 N_73 A1_c un5_ciin_10 N_75 un5_ciin_11 N_251 nEXP_SPACE_c un22_berr_1_0 \ +# un22_berr_1 un21_fpu_cs_1 N_95 BERR_c pos_clk_un6_bg_030_1_n N_94 N_131_i_1 N_288 \ +# BG_030_c N_131_i_2 N_289 N_131_i_3 N_286 BG_000DFFreg N_96_1 N_279 N_96_2 N_277 N_96_3 \ +# N_276 BGACK_000_c pos_clk_cpu_est_11_0_1_1__n N_62 pos_clk_cpu_est_11_0_2_1__n \ +# N_274 N_310_1 N_313 N_310_2 N_307 N_310_3 N_305 CLK_OSZI_c N_310_4 N_306 N_309_1 N_303 \ +# N_309_2 N_304 CLK_EXP_c N_308_1 N_301 N_308_2 N_91 RESET_OUT_0_sqmuxa_5_1 N_85 \ +# FPU_SENSE_c RESET_OUT_0_sqmuxa_7_1 N_294 RESET_OUT_0_sqmuxa_7_2 N_296 \ +# IPL_030DFF_0_reg RESET_OUT_0_sqmuxa_7_3 N_84 N_94_1 N_82 IPL_030DFF_1_reg N_95_1 N_83 \ +# N_119_i_1 N_293 IPL_030DFF_2_reg N_82_1 N_290 N_83_1 N_291 ipl_c_0__n N_296_1 N_283 \ +# N_303_1 N_284 ipl_c_1__n N_304_1 N_86 N_306_1 N_80 ipl_c_2__n N_129_i_1 N_78 N_125_i_1 \ +# N_108 N_123_i_1 N_109 DTACK_c N_115_0_1 N_100 pos_clk_cpu_est_11_0_1_3__n N_99 \ +# N_260_0_1 N_93 N_261_i_1 pos_clk_un14_clk_000_n_sync_n VPA_c N_262_i_1 \ +# pos_clk_un9_clk_000_n_sync_n N_263_i_1 N_340 pos_clk_ipl_1_n N_97 RST_c \ +# cpu_est_0_3__un3_n N_136 cpu_est_0_3__un1_n N_101 cpu_est_0_3__un0_n N_81 RW_c \ +# cpu_est_0_2__un3_n N_116 cpu_est_0_2__un1_n N_96 fc_c_0__n cpu_est_0_2__un0_n N_113 \ +# cpu_est_0_1__un3_n N_275 fc_c_1__n cpu_est_0_1__un1_n N_273 cpu_est_0_1__un0_n N_88 \ +# bgack_030_int_0_un3_n N_272 AMIGA_BUS_DATA_DIR_c bgack_030_int_0_un1_n N_299 \ +# bgack_030_int_0_un0_n N_90 vma_int_0_un3_n N_311 vma_int_0_un1_n N_312 \ +# vma_int_0_un0_n N_267 un1_as_000_i rw_000_int_0_un3_n N_264 un1_rst_dly_i_m_i_3__n \ +# rw_000_int_0_un1_n pos_clk_un7_clk_000_pe_n rw_000_int_0_un0_n N_308 \ +# un1_rst_dly_i_m_i_4__n sm_amiga_srsts_i_0_m2_3__un3_n N_309 \ +# sm_amiga_srsts_i_0_m2_3__un1_n +.model bus68030 +.inputs A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF A1.BLIF nEXP_SPACE.BLIF BG_030.BLIF \ +BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF FPU_SENSE.BLIF \ +DTACK.BLIF VPA.BLIF RST.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF \ +A_26_.BLIF A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF \ +A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF A_15_.BLIF A_14_.BLIF A_13_.BLIF \ +A_12_.BLIF A_11_.BLIF A_10_.BLIF A_9_.BLIF A_8_.BLIF A_7_.BLIF A_6_.BLIF \ +A_5_.BLIF A_4_.BLIF A_3_.BLIF A_2_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF \ +SIZE_1_.BLIF AS_030.BLIF AS_000.BLIF RW_000.BLIF DS_030.BLIF UDS_000.BLIF \ +LDS_000.BLIF A0.BLIF BERR.BLIF RW.BLIF SIZE_0_.BLIF N_310.BLIF \ +un1_rst_dly_i_m_i_5__n.BLIF sm_amiga_srsts_i_0_m2_3__un0_n.BLIF N_220.BLIF \ +sm_amiga_srsts_i_0_m2_1__un3_n.BLIF pos_clk_cpu_est_11_1__n.BLIF \ +un1_rst_dly_i_m_i_6__n.BLIF sm_amiga_srsts_i_0_m2_1__un1_n.BLIF N_14.BLIF \ +sm_amiga_srsts_i_0_m2_1__un0_n.BLIF N_18.BLIF un1_rst_dly_i_m_i_7__n.BLIF \ +un1_amiga_bus_enable_dma_high_0_m2_0__un3_n.BLIF N_22.BLIF \ +un1_amiga_bus_enable_dma_high_0_m2_0__un1_n.BLIF inst_BGACK_030_INTreg.BLIF \ +RESET_OUT_0_sqmuxa_1.BLIF un1_rst_dly_i_m_i_8__n.BLIF \ +un1_amiga_bus_enable_dma_high_0_m2_0__un0_n.BLIF vcc_n_n.BLIF N_205.BLIF \ +un1_sm_amiga_7_i_m2_un3_n.BLIF cpu_est_3_reg.BLIF N_213.BLIF \ +un1_rst_dly_i_m_i_2__n.BLIF un1_sm_amiga_7_i_m2_un1_n.BLIF \ +inst_VMA_INTreg.BLIF pos_clk_RST_DLY_5_iv_0_x2_0_.BLIF \ +un1_sm_amiga_7_i_m2_un0_n.BLIF inst_RESET_OUTreg.BLIF N_105.BLIF N_98_i.BLIF \ +size_dma_0_0__un3_n.BLIF gnd_n_n.BLIF N_98.BLIF size_dma_0_0__un1_n.BLIF \ +un1_amiga_bus_enable_low.BLIF RESET_OUT_0_sqmuxa.BLIF N_105_i.BLIF \ +size_dma_0_0__un0_n.BLIF un6_as_030.BLIF un1_rst_dly_i_m_2__n.BLIF \ +size_dma_0_1__un3_n.BLIF un3_size.BLIF G_137.BLIF N_22_i.BLIF \ +size_dma_0_1__un1_n.BLIF un4_size.BLIF un1_rst_dly_i_m_8__n.BLIF N_33_0.BLIF \ +size_dma_0_1__un0_n.BLIF un5_ciin.BLIF G_149.BLIF N_18_i.BLIF \ +ipl_030_0_0__un3_n.BLIF un4_as_000.BLIF RESET_OUT_0_sqmuxa_5.BLIF N_37_0.BLIF \ +ipl_030_0_0__un1_n.BLIF un21_fpu_cs.BLIF RESET_OUT_0_sqmuxa_7.BLIF N_14_i.BLIF \ +ipl_030_0_0__un0_n.BLIF un22_berr.BLIF G_147.BLIF N_41_0.BLIF \ +ipl_030_0_1__un3_n.BLIF un6_ds_030.BLIF G_145.BLIF N_10_i.BLIF \ +ipl_030_0_1__un1_n.BLIF un6_uds_000.BLIF N_211.BLIF N_44_0.BLIF \ +ipl_030_0_1__un0_n.BLIF un6_lds_000.BLIF G_143.BLIF \ +pos_clk_cpu_est_11_0_1__n.BLIF ipl_030_0_2__un3_n.BLIF cpu_est_0_.BLIF \ +N_209.BLIF N_312_i.BLIF ipl_030_0_2__un1_n.BLIF cpu_est_1_.BLIF G_141.BLIF \ +N_90_i.BLIF ipl_030_0_2__un0_n.BLIF inst_AS_000_INT.BLIF G_139.BLIF \ +N_88_i.BLIF amiga_bus_enable_dma_high_0_un3_n.BLIF SM_AMIGA_5_.BLIF \ +un1_rst_dly_i_m_7__n.BLIF N_299_i.BLIF amiga_bus_enable_dma_high_0_un1_n.BLIF \ +inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF un1_rst_dly_i_m_6__n.BLIF N_275_0.BLIF \ +amiga_bus_enable_dma_high_0_un0_n.BLIF inst_AS_030_D0.BLIF \ +un1_rst_dly_i_m_5__n.BLIF N_274_0.BLIF bg_000_0_un3_n.BLIF \ +inst_nEXP_SPACE_D0reg.BLIF un1_rst_dly_i_m_4__n.BLIF N_273_i.BLIF \ +bg_000_0_un1_n.BLIF inst_DS_030_D0.BLIF un1_rst_dly_i_m_3__n.BLIF N_272_i.BLIF \ +bg_000_0_un0_n.BLIF inst_AS_030_000_SYNC.BLIF N_71_i.BLIF N_270_i.BLIF \ +ds_000_dma_0_un3_n.BLIF inst_BGACK_030_INT_D.BLIF \ +un1_amiga_bus_enable_low_i.BLIF N_268_i.BLIF ds_000_dma_0_un1_n.BLIF \ +inst_AS_000_DMA.BLIF un21_fpu_cs_i.BLIF N_310_i.BLIF ds_000_dma_0_un0_n.BLIF \ +inst_DS_000_DMA.BLIF RESET_OUT_i.BLIF N_311_i.BLIF as_000_dma_0_un3_n.BLIF \ +CYCLE_DMA_0_.BLIF BGACK_030_INT_i.BLIF N_267_0.BLIF as_000_dma_0_un1_n.BLIF \ +CYCLE_DMA_1_.BLIF RESET_OUT_0_sqmuxa_i.BLIF N_309_i.BLIF \ +as_000_dma_0_un0_n.BLIF SIZE_DMA_0_.BLIF un1_rst_dly_i_3__n.BLIF N_308_i.BLIF \ +a0_dma_0_un3_n.BLIF SIZE_DMA_1_.BLIF un1_rst_dly_i_4__n.BLIF \ +pos_clk_un7_clk_000_pe_0_n.BLIF a0_dma_0_un1_n.BLIF inst_VPA_D.BLIF \ +un1_rst_dly_i_5__n.BLIF N_264_0.BLIF a0_dma_0_un0_n.BLIF inst_UDS_000_INT.BLIF \ +un1_rst_dly_i_6__n.BLIF N_304_i.BLIF dsack1_int_0_un3_n.BLIF \ +inst_LDS_000_INT.BLIF un1_rst_dly_i_7__n.BLIF N_303_i.BLIF \ +dsack1_int_0_un1_n.BLIF inst_CLK_OUT_PRE_D.BLIF un1_rst_dly_i_8__n.BLIF \ +N_186_i.BLIF dsack1_int_0_un0_n.BLIF inst_DTACK_D0.BLIF \ +un1_rst_dly_i_2__n.BLIF VPA_c_i.BLIF as_000_int_0_un3_n.BLIF \ +inst_CLK_OUT_PRE_50.BLIF N_87_i_i.BLIF N_56_0.BLIF as_000_int_0_un1_n.BLIF \ +inst_CLK_000_D1.BLIF cpu_est_i_3__n.BLIF DTACK_c_i.BLIF \ +as_000_int_0_un0_n.BLIF inst_CLK_000_D0.BLIF cpu_est_i_0__n.BLIF N_57_0.BLIF \ +ds_000_enable_0_un3_n.BLIF inst_CLK_000_PE.BLIF VPA_D_i.BLIF N_97_i.BLIF \ +ds_000_enable_0_un1_n.BLIF CLK_000_P_SYNC_9_.BLIF VMA_INT_i.BLIF \ +ds_000_enable_0_un0_n.BLIF inst_CLK_000_NE.BLIF cpu_est_i_1__n.BLIF \ +N_96_i.BLIF as_030_000_sync_0_un3_n.BLIF CLK_000_N_SYNC_11_.BLIF \ +CLK_000_PE_i.BLIF N_95_i.BLIF as_030_000_sync_0_un1_n.BLIF cpu_est_2_.BLIF \ +BERR_i.BLIF N_94_i.BLIF as_030_000_sync_0_un0_n.BLIF IPL_D0_0_.BLIF \ +sm_amiga_i_4__n.BLIF N_313_i.BLIF lds_000_int_0_un3_n.BLIF IPL_D0_1_.BLIF \ +cpu_est_i_2__n.BLIF N_136_i.BLIF lds_000_int_0_un1_n.BLIF IPL_D0_2_.BLIF \ +sm_amiga_i_5__n.BLIF N_81_0.BLIF lds_000_int_0_un0_n.BLIF SM_AMIGA_3_.BLIF \ +DTACK_D0_i.BLIF N_116_i.BLIF rw_000_dma_0_un3_n.BLIF inst_CLK_000_NE_D0.BLIF \ +sm_amiga_i_0__n.BLIF N_77_i.BLIF rw_000_dma_0_un1_n.BLIF \ +pos_clk_un6_bg_030_n.BLIF sm_amiga_i_3__n.BLIF N_73_i.BLIF \ +rw_000_dma_0_un0_n.BLIF SM_AMIGA_0_.BLIF CLK_000_NE_i.BLIF N_101_i.BLIF \ +uds_000_int_0_un3_n.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ +sm_amiga_i_6__n.BLIF uds_000_int_0_un1_n.BLIF inst_DSACK1_INTreg.BLIF \ +sm_amiga_i_1__n.BLIF clk_000_n_sync_i_10__n.BLIF uds_000_int_0_un0_n.BLIF \ +CLK_OUT_PRE_D_i.BLIF pos_clk_un9_clk_000_n_sync_i_n.BLIF \ +amiga_bus_enable_dma_low_0_un3_n.BLIF pos_clk_ipl_n.BLIF \ +pos_clk_un11_clk_000_n_sync_i_n.BLIF pos_clk_un14_clk_000_n_sync_0_n.BLIF \ +amiga_bus_enable_dma_low_0_un1_n.BLIF pos_clk_un3_ds_030_d0_n.BLIF \ +LDS_000_i.BLIF pos_clk_un22_bgack_030_int_i_n.BLIF \ +amiga_bus_enable_dma_low_0_un0_n.BLIF SM_AMIGA_6_.BLIF UDS_000_i.BLIF \ +N_86_i.BLIF a_15__n.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa.BLIF \ +nEXP_SPACE_D0_i.BLIF N_93_i.BLIF RST_DLY_0_.BLIF sm_amiga_i_2__n.BLIF \ +a_14__n.BLIF RST_DLY_1_.BLIF AS_030_i.BLIF N_99_i.BLIF RST_DLY_2_.BLIF \ +A1_i.BLIF pos_clk_size_dma_6_0_1__n.BLIF a_13__n.BLIF RST_DLY_3_.BLIF \ +CLK_000_D1_i.BLIF N_100_i.BLIF RST_DLY_4_.BLIF RW_000_i.BLIF \ +pos_clk_size_dma_6_0_0__n.BLIF a_12__n.BLIF RST_DLY_5_.BLIF CLK_030_H_i.BLIF \ +N_245_0.BLIF RST_DLY_6_.BLIF AS_000_DMA_i.BLIF N_108_i.BLIF a_11__n.BLIF \ +RST_DLY_7_.BLIF AS_000_i.BLIF N_109_i.BLIF pos_clk_un8_bg_030_n.BLIF \ +sm_amiga_i_i_7__n.BLIF N_246_0.BLIF a_10__n.BLIF CLK_000_P_SYNC_0_.BLIF \ +RW_i.BLIF un5_ciin_i.BLIF CLK_000_P_SYNC_1_.BLIF \ +AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF N_247_0.BLIF a_9__n.BLIF \ +CLK_000_P_SYNC_2_.BLIF FPU_SENSE_i.BLIF N_248_0.BLIF CLK_000_P_SYNC_3_.BLIF \ +AS_030_D0_i.BLIF CLK_000_D0_i.BLIF a_8__n.BLIF CLK_000_P_SYNC_4_.BLIF \ +a_i_24__n.BLIF N_249_i.BLIF CLK_000_P_SYNC_5_.BLIF size_dma_i_0__n.BLIF \ +AS_030_000_SYNC_i.BLIF a_7__n.BLIF CLK_000_P_SYNC_6_.BLIF size_dma_i_1__n.BLIF \ +N_251_0.BLIF CLK_000_P_SYNC_7_.BLIF a_i_16__n.BLIF \ +pos_clk_un3_as_030_d0_i_n.BLIF a_6__n.BLIF CLK_000_P_SYNC_8_.BLIF \ +a_i_18__n.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF CLK_000_N_SYNC_0_.BLIF \ +a_i_19__n.BLIF N_75_i.BLIF a_5__n.BLIF CLK_000_N_SYNC_1_.BLIF a_i_31__n.BLIF \ +N_76_i.BLIF CLK_000_N_SYNC_2_.BLIF a_i_29__n.BLIF N_78_0.BLIF a_4__n.BLIF \ +CLK_000_N_SYNC_3_.BLIF a_i_30__n.BLIF N_80_0.BLIF CLK_000_N_SYNC_4_.BLIF \ +a_i_27__n.BLIF CLK_EXP_c_i.BLIF a_3__n.BLIF CLK_000_N_SYNC_5_.BLIF \ +a_i_28__n.BLIF N_258_0.BLIF CLK_000_N_SYNC_6_.BLIF a_i_25__n.BLIF N_283_i.BLIF \ +a_2__n.BLIF CLK_000_N_SYNC_7_.BLIF a_i_26__n.BLIF N_284_i.BLIF \ +CLK_000_N_SYNC_8_.BLIF UDS_000_INT_i.BLIF CLK_000_N_SYNC_9_.BLIF \ +LDS_000_INT_i.BLIF N_290_i.BLIF CLK_000_N_SYNC_10_.BLIF DS_030_i.BLIF \ +N_291_i.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF N_224_i.BLIF \ +inst_RW_000_INT.BLIF N_225_i.BLIF N_279_i.BLIF inst_RW_000_DMA.BLIF \ +N_226_i.BLIF N_293_i.BLIF inst_A0_DMA.BLIF inst_CLK_030_H.BLIF N_82_i.BLIF \ +SM_AMIGA_1_.BLIF N_83_i.BLIF SM_AMIGA_4_.BLIF N_104_i.BLIF N_259_0.BLIF \ +SM_AMIGA_2_.BLIF N_103_i.BLIF N_84_i.BLIF pos_clk_un3_as_030_d0_n.BLIF \ +N_282_i.BLIF N_115_0.BLIF inst_DS_000_ENABLE.BLIF N_92_i.BLIF N_85_i.BLIF \ +AS_000_INT_1_sqmuxa.BLIF un6_lds_000_i.BLIF N_294_i.BLIF \ +DS_000_ENABLE_1_sqmuxa_1.BLIF un6_uds_000_i.BLIF N_296_i.BLIF \ +pos_clk_a0_dma_3_n.BLIF un6_ds_030_i.BLIF pos_clk_cpu_est_11_0_3__n.BLIF \ +pos_clk_ds_000_dma_4_n.BLIF DS_000_DMA_i.BLIF N_91_i.BLIF N_3.BLIF \ +un4_as_000_i.BLIF N_260_0.BLIF AS_000_INT_i.BLIF N_301_i.BLIF \ +un6_as_030_i.BLIF pos_clk_ds_000_dma_4_0_n.BLIF N_6.BLIF \ +AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF N_305_i.BLIF N_8.BLIF DS_030_D0_i.BLIF \ +N_306_i.BLIF N_9.BLIF AS_030_c.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF N_10.BLIF \ +N_307_i.BLIF N_11.BLIF AS_000_c.BLIF N_12.BLIF N_13.BLIF RW_000_c.BLIF \ +N_15.BLIF N_265_0.BLIF N_16.BLIF DS_030_c.BLIF N_269_i.BLIF N_19.BLIF \ +pos_clk_un24_bgack_030_int_i_0_i_n.BLIF N_20.BLIF UDS_000_c.BLIF N_62_0.BLIF \ +N_21.BLIF N_276_0.BLIF N_23.BLIF LDS_000_c.BLIF N_277_0.BLIF N_24.BLIF \ +N_286_i.BLIF N_25.BLIF size_c_0__n.BLIF N_288_i.BLIF N_289_i.BLIF \ +size_c_1__n.BLIF pos_clk_un11_ds_030_d0_i_n.BLIF A0_c_i.BLIF \ +size_c_i_1__n.BLIF N_25_i.BLIF N_32_0.BLIF N_24_i.BLIF N_31_0.BLIF N_23_i.BLIF \ +N_30_0.BLIF ipl_c_i_2__n.BLIF N_54_0.BLIF ipl_c_i_1__n.BLIF N_53_0.BLIF \ +ipl_c_i_0__n.BLIF N_52_0.BLIF nEXP_SPACE_c_i.BLIF N_55_0.BLIF N_50_0.BLIF \ +N_3_i.BLIF N_49_0.BLIF N_6_i.BLIF N_48_0.BLIF N_8_i.BLIF N_46_0.BLIF \ +N_9_i.BLIF N_45_0.BLIF N_12_i.BLIF SM_AMIGA_i_7_.BLIF N_43_0.BLIF N_115.BLIF \ +N_13_i.BLIF pos_clk_size_dma_6_0__n.BLIF a_c_16__n.BLIF N_42_0.BLIF \ +pos_clk_size_dma_6_1__n.BLIF N_15_i.BLIF pos_clk_cpu_est_11_3__n.BLIF \ +a_c_17__n.BLIF N_40_0.BLIF G_165.BLIF N_16_i.BLIF G_166.BLIF a_c_18__n.BLIF \ +N_39_0.BLIF G_167.BLIF N_19_i.BLIF un6_uds_000_1.BLIF a_c_19__n.BLIF \ +N_36_0.BLIF pos_clk_un24_bgack_030_int_i_0_n.BLIF N_20_i.BLIF N_245.BLIF \ +a_c_20__n.BLIF N_35_0.BLIF N_246.BLIF N_21_i.BLIF N_247.BLIF a_c_21__n.BLIF \ +N_34_0.BLIF N_248.BLIF BG_030_c_i.BLIF N_89.BLIF a_c_22__n.BLIF \ +pos_clk_un6_bg_030_i_n.BLIF N_92.BLIF pos_clk_un8_bg_030_0_n.BLIF N_102.BLIF \ +a_c_23__n.BLIF N_127_i_1.BLIF N_103.BLIF N_127_i_2.BLIF N_104.BLIF \ +a_c_24__n.BLIF pos_clk_un24_bgack_030_int_i_0_i_1_n.BLIF N_112.BLIF \ +N_80_0_1.BLIF N_256.BLIF a_c_25__n.BLIF N_75_i_1.BLIF N_258.BLIF \ +N_251_0_1.BLIF a_c_26__n.BLIF pos_clk_un11_ds_030_d0_i_1_n.BLIF N_260.BLIF \ +N_340_1.BLIF N_265.BLIF a_c_27__n.BLIF N_340_2.BLIF N_282.BLIF N_340_3.BLIF \ +N_71.BLIF a_c_28__n.BLIF N_340_4.BLIF cpu_est_0_0_x2_0_.BLIF un5_ciin_1.BLIF \ +pos_clk_un11_clk_000_n_sync_n.BLIF a_c_29__n.BLIF un5_ciin_2.BLIF N_76.BLIF \ +un5_ciin_3.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.BLIF a_c_30__n.BLIF un5_ciin_4.BLIF \ +pos_clk_CYCLE_DMA_5_0_i_x2.BLIF un5_ciin_5.BLIF \ +pos_clk_un24_bgack_030_int_i_0_x2.BLIF a_c_31__n.BLIF un5_ciin_6.BLIF \ +pos_clk_un22_bgack_030_int_n.BLIF un5_ciin_7.BLIF N_268.BLIF A0_c.BLIF \ +un5_ciin_8.BLIF N_270.BLIF un5_ciin_9.BLIF N_73.BLIF A1_c.BLIF \ +un5_ciin_10.BLIF N_75.BLIF un5_ciin_11.BLIF N_251.BLIF nEXP_SPACE_c.BLIF \ +un22_berr_1_0.BLIF un22_berr_1.BLIF un21_fpu_cs_1.BLIF N_95.BLIF BERR_c.BLIF \ +pos_clk_un6_bg_030_1_n.BLIF N_94.BLIF N_131_i_1.BLIF N_288.BLIF BG_030_c.BLIF \ +N_131_i_2.BLIF N_289.BLIF N_131_i_3.BLIF N_286.BLIF BG_000DFFreg.BLIF \ +N_96_1.BLIF N_279.BLIF N_96_2.BLIF N_277.BLIF N_96_3.BLIF N_276.BLIF \ +BGACK_000_c.BLIF pos_clk_cpu_est_11_0_1_1__n.BLIF N_62.BLIF \ +pos_clk_cpu_est_11_0_2_1__n.BLIF N_274.BLIF N_310_1.BLIF N_313.BLIF \ +N_310_2.BLIF N_307.BLIF N_310_3.BLIF N_305.BLIF CLK_OSZI_c.BLIF N_310_4.BLIF \ +N_306.BLIF N_309_1.BLIF N_303.BLIF N_309_2.BLIF N_304.BLIF CLK_EXP_c.BLIF \ +N_308_1.BLIF N_301.BLIF N_308_2.BLIF N_91.BLIF RESET_OUT_0_sqmuxa_5_1.BLIF \ +N_85.BLIF FPU_SENSE_c.BLIF RESET_OUT_0_sqmuxa_7_1.BLIF N_294.BLIF \ +RESET_OUT_0_sqmuxa_7_2.BLIF N_296.BLIF IPL_030DFF_0_reg.BLIF \ +RESET_OUT_0_sqmuxa_7_3.BLIF N_84.BLIF N_94_1.BLIF N_82.BLIF \ +IPL_030DFF_1_reg.BLIF N_95_1.BLIF N_83.BLIF N_119_i_1.BLIF N_293.BLIF \ +IPL_030DFF_2_reg.BLIF N_82_1.BLIF N_290.BLIF N_83_1.BLIF N_291.BLIF \ +ipl_c_0__n.BLIF N_296_1.BLIF N_283.BLIF N_303_1.BLIF N_284.BLIF \ +ipl_c_1__n.BLIF N_304_1.BLIF N_86.BLIF N_306_1.BLIF N_80.BLIF ipl_c_2__n.BLIF \ +N_129_i_1.BLIF N_78.BLIF N_125_i_1.BLIF N_108.BLIF N_123_i_1.BLIF N_109.BLIF \ +DTACK_c.BLIF N_115_0_1.BLIF N_100.BLIF pos_clk_cpu_est_11_0_1_3__n.BLIF \ +N_99.BLIF N_260_0_1.BLIF N_93.BLIF N_261_i_1.BLIF \ +pos_clk_un14_clk_000_n_sync_n.BLIF VPA_c.BLIF N_262_i_1.BLIF \ +pos_clk_un9_clk_000_n_sync_n.BLIF N_263_i_1.BLIF N_340.BLIF \ +pos_clk_ipl_1_n.BLIF N_97.BLIF RST_c.BLIF cpu_est_0_3__un3_n.BLIF N_136.BLIF \ +cpu_est_0_3__un1_n.BLIF N_101.BLIF cpu_est_0_3__un0_n.BLIF N_81.BLIF RW_c.BLIF \ +cpu_est_0_2__un3_n.BLIF N_116.BLIF cpu_est_0_2__un1_n.BLIF N_96.BLIF \ +fc_c_0__n.BLIF cpu_est_0_2__un0_n.BLIF N_113.BLIF cpu_est_0_1__un3_n.BLIF \ +N_275.BLIF fc_c_1__n.BLIF cpu_est_0_1__un1_n.BLIF N_273.BLIF \ +cpu_est_0_1__un0_n.BLIF N_88.BLIF bgack_030_int_0_un3_n.BLIF N_272.BLIF \ +AMIGA_BUS_DATA_DIR_c.BLIF bgack_030_int_0_un1_n.BLIF N_299.BLIF \ +bgack_030_int_0_un0_n.BLIF N_90.BLIF vma_int_0_un3_n.BLIF N_311.BLIF \ +vma_int_0_un1_n.BLIF N_312.BLIF vma_int_0_un0_n.BLIF N_267.BLIF \ +un1_as_000_i.BLIF rw_000_int_0_un3_n.BLIF N_264.BLIF \ +un1_rst_dly_i_m_i_3__n.BLIF rw_000_int_0_un1_n.BLIF \ +pos_clk_un7_clk_000_pe_n.BLIF rw_000_int_0_un0_n.BLIF N_308.BLIF \ +un1_rst_dly_i_m_i_4__n.BLIF sm_amiga_srsts_i_0_m2_3__un3_n.BLIF N_309.BLIF \ +sm_amiga_srsts_i_0_m2_3__un1_n.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF \ +RW_000.PIN.BLIF DS_030.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF \ +SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF A0.PIN.BLIF BERR.PIN.BLIF RW.PIN.BLIF +.outputs IPL_030_2_ BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 AVEC E \ +VMA RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ +AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ IPL_030DFF_2_reg.D \ +IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D \ +IPL_D0_2_.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C \ +SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.D \ +SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C \ +SM_AMIGA_0_.D SM_AMIGA_0_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D \ +cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_reg.D cpu_est_3_reg.C \ +IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C \ +CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.D \ +CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C RST_DLY_0_.D \ +RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C RST_DLY_3_.D \ +RST_DLY_3_.C RST_DLY_4_.D RST_DLY_4_.C RST_DLY_5_.D RST_DLY_5_.C RST_DLY_6_.D \ +RST_DLY_6_.C RST_DLY_7_.D RST_DLY_7_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C \ +CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D \ +SIZE_DMA_1_.C CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D \ +CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C \ +CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.D \ +CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C \ +CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.D \ +CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C \ +CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.D \ +CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_6_.C \ +CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.D \ +CLK_000_N_SYNC_8_.C CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C \ +CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.D \ +CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C \ +CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C inst_CLK_030_H.D inst_CLK_030_H.C \ +inst_RESET_OUTreg.D inst_RESET_OUTreg.C inst_DS_000_ENABLE.D \ +inst_DS_000_ENABLE.C inst_UDS_000_INT.D inst_UDS_000_INT.C inst_RW_000_DMA.D \ +inst_RW_000_DMA.C inst_RW_000_INT.D inst_RW_000_INT.C inst_LDS_000_INT.D \ +inst_LDS_000_INT.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \ +inst_AS_000_INT.D inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C \ +inst_A0_DMA.D inst_A0_DMA.C inst_AS_000_DMA.D inst_AS_000_DMA.C \ +inst_DS_000_DMA.D inst_DS_000_DMA.C inst_DS_030_D0.D inst_DS_030_D0.C \ +inst_AS_030_D0.D inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.D \ +inst_nEXP_SPACE_D0reg.C inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D \ +inst_DTACK_D0.C inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C BG_000DFFreg.D \ +BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D \ +inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D \ +inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_VMA_INTreg.D inst_VMA_INTreg.C \ +inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_CLK_000_PE.D \ +inst_CLK_000_PE.C inst_CLK_000_NE.D inst_CLK_000_NE.C inst_CLK_OUT_PRE_50.D \ +inst_CLK_OUT_PRE_50.C inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_NE_D0.D \ +inst_CLK_000_NE_D0.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C \ +inst_CLK_000_D0.D inst_CLK_000_D0.C SIZE_1_ AS_030 AS_000 RW_000 DS_030 \ +UDS_000 LDS_000 A0 BERR RW SIZE_0_ N_310 un1_rst_dly_i_m_i_5__n \ +sm_amiga_srsts_i_0_m2_3__un0_n N_220 sm_amiga_srsts_i_0_m2_1__un3_n \ +pos_clk_cpu_est_11_1__n un1_rst_dly_i_m_i_6__n sm_amiga_srsts_i_0_m2_1__un1_n \ +N_14 sm_amiga_srsts_i_0_m2_1__un0_n N_18 un1_rst_dly_i_m_i_7__n \ +un1_amiga_bus_enable_dma_high_0_m2_0__un3_n N_22 \ +un1_amiga_bus_enable_dma_high_0_m2_0__un1_n RESET_OUT_0_sqmuxa_1 \ +un1_rst_dly_i_m_i_8__n un1_amiga_bus_enable_dma_high_0_m2_0__un0_n vcc_n_n \ +N_205 un1_sm_amiga_7_i_m2_un3_n N_213 un1_rst_dly_i_m_i_2__n \ +un1_sm_amiga_7_i_m2_un1_n un1_sm_amiga_7_i_m2_un0_n N_105 N_98_i \ +size_dma_0_0__un3_n gnd_n_n N_98 size_dma_0_0__un1_n un1_amiga_bus_enable_low \ +RESET_OUT_0_sqmuxa N_105_i size_dma_0_0__un0_n un6_as_030 un1_rst_dly_i_m_2__n \ +size_dma_0_1__un3_n un3_size N_22_i size_dma_0_1__un1_n un4_size \ +un1_rst_dly_i_m_8__n N_33_0 size_dma_0_1__un0_n un5_ciin N_18_i \ +ipl_030_0_0__un3_n un4_as_000 RESET_OUT_0_sqmuxa_5 N_37_0 ipl_030_0_0__un1_n \ +un21_fpu_cs RESET_OUT_0_sqmuxa_7 N_14_i ipl_030_0_0__un0_n un22_berr N_41_0 \ +ipl_030_0_1__un3_n un6_ds_030 N_10_i ipl_030_0_1__un1_n un6_uds_000 N_211 \ +N_44_0 ipl_030_0_1__un0_n un6_lds_000 pos_clk_cpu_est_11_0_1__n \ +ipl_030_0_2__un3_n N_209 N_312_i ipl_030_0_2__un1_n N_90_i ipl_030_0_2__un0_n \ +N_88_i amiga_bus_enable_dma_high_0_un3_n un1_rst_dly_i_m_7__n N_299_i \ +amiga_bus_enable_dma_high_0_un1_n un1_rst_dly_i_m_6__n N_275_0 \ +amiga_bus_enable_dma_high_0_un0_n un1_rst_dly_i_m_5__n N_274_0 bg_000_0_un3_n \ +un1_rst_dly_i_m_4__n N_273_i bg_000_0_un1_n un1_rst_dly_i_m_3__n N_272_i \ +bg_000_0_un0_n N_71_i N_270_i ds_000_dma_0_un3_n un1_amiga_bus_enable_low_i \ +N_268_i ds_000_dma_0_un1_n un21_fpu_cs_i N_310_i ds_000_dma_0_un0_n \ +RESET_OUT_i N_311_i as_000_dma_0_un3_n BGACK_030_INT_i N_267_0 \ +as_000_dma_0_un1_n RESET_OUT_0_sqmuxa_i N_309_i as_000_dma_0_un0_n \ +un1_rst_dly_i_3__n N_308_i a0_dma_0_un3_n un1_rst_dly_i_4__n \ +pos_clk_un7_clk_000_pe_0_n a0_dma_0_un1_n un1_rst_dly_i_5__n N_264_0 \ +a0_dma_0_un0_n un1_rst_dly_i_6__n N_304_i dsack1_int_0_un3_n \ +un1_rst_dly_i_7__n N_303_i dsack1_int_0_un1_n un1_rst_dly_i_8__n N_186_i \ +dsack1_int_0_un0_n un1_rst_dly_i_2__n VPA_c_i as_000_int_0_un3_n N_87_i_i \ +N_56_0 as_000_int_0_un1_n cpu_est_i_3__n DTACK_c_i as_000_int_0_un0_n \ +cpu_est_i_0__n N_57_0 ds_000_enable_0_un3_n VPA_D_i N_97_i \ +ds_000_enable_0_un1_n VMA_INT_i ds_000_enable_0_un0_n cpu_est_i_1__n N_96_i \ +as_030_000_sync_0_un3_n CLK_000_PE_i N_95_i as_030_000_sync_0_un1_n BERR_i \ +N_94_i as_030_000_sync_0_un0_n sm_amiga_i_4__n N_313_i lds_000_int_0_un3_n \ +cpu_est_i_2__n N_136_i lds_000_int_0_un1_n sm_amiga_i_5__n N_81_0 \ +lds_000_int_0_un0_n DTACK_D0_i N_116_i rw_000_dma_0_un3_n sm_amiga_i_0__n \ +N_77_i rw_000_dma_0_un1_n pos_clk_un6_bg_030_n sm_amiga_i_3__n N_73_i \ +rw_000_dma_0_un0_n CLK_000_NE_i N_101_i uds_000_int_0_un3_n sm_amiga_i_6__n \ +uds_000_int_0_un1_n sm_amiga_i_1__n clk_000_n_sync_i_10__n uds_000_int_0_un0_n \ +CLK_OUT_PRE_D_i pos_clk_un9_clk_000_n_sync_i_n \ +amiga_bus_enable_dma_low_0_un3_n pos_clk_ipl_n pos_clk_un11_clk_000_n_sync_i_n \ +pos_clk_un14_clk_000_n_sync_0_n amiga_bus_enable_dma_low_0_un1_n \ +pos_clk_un3_ds_030_d0_n LDS_000_i pos_clk_un22_bgack_030_int_i_n \ +amiga_bus_enable_dma_low_0_un0_n UDS_000_i N_86_i a_15__n \ +AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa nEXP_SPACE_D0_i N_93_i sm_amiga_i_2__n \ +a_14__n AS_030_i N_99_i A1_i pos_clk_size_dma_6_0_1__n a_13__n CLK_000_D1_i \ +N_100_i RW_000_i pos_clk_size_dma_6_0_0__n a_12__n CLK_030_H_i N_245_0 \ +AS_000_DMA_i N_108_i a_11__n AS_000_i N_109_i pos_clk_un8_bg_030_n \ +sm_amiga_i_i_7__n N_246_0 a_10__n RW_i un5_ciin_i AMIGA_BUS_ENABLE_DMA_HIGH_i \ +N_247_0 a_9__n FPU_SENSE_i N_248_0 AS_030_D0_i CLK_000_D0_i a_8__n a_i_24__n \ +N_249_i size_dma_i_0__n AS_030_000_SYNC_i a_7__n size_dma_i_1__n N_251_0 \ +a_i_16__n pos_clk_un3_as_030_d0_i_n a_6__n a_i_18__n \ +pos_clk_un5_bgack_030_int_d_i_n a_i_19__n N_75_i a_5__n a_i_31__n N_76_i \ +a_i_29__n N_78_0 a_4__n a_i_30__n N_80_0 a_i_27__n CLK_EXP_c_i a_3__n \ +a_i_28__n N_258_0 a_i_25__n N_283_i a_2__n a_i_26__n N_284_i UDS_000_INT_i \ +LDS_000_INT_i N_290_i DS_030_i N_291_i pos_clk_un5_bgack_030_int_d_n N_224_i \ +N_225_i N_279_i N_226_i N_293_i N_82_i N_83_i N_104_i N_259_0 N_103_i N_84_i \ +pos_clk_un3_as_030_d0_n N_282_i N_115_0 N_92_i N_85_i AS_000_INT_1_sqmuxa \ +un6_lds_000_i N_294_i DS_000_ENABLE_1_sqmuxa_1 un6_uds_000_i N_296_i \ +pos_clk_a0_dma_3_n un6_ds_030_i pos_clk_cpu_est_11_0_3__n \ +pos_clk_ds_000_dma_4_n DS_000_DMA_i N_91_i N_3 un4_as_000_i N_260_0 \ +AS_000_INT_i N_301_i un6_as_030_i pos_clk_ds_000_dma_4_0_n N_6 \ +AMIGA_BUS_ENABLE_DMA_LOW_i N_305_i N_8 DS_030_D0_i N_306_i N_9 AS_030_c \ +AMIGA_BUS_DATA_DIR_c_0 N_10 N_307_i N_11 AS_000_c N_12 N_13 RW_000_c N_15 \ +N_265_0 N_16 DS_030_c N_269_i N_19 pos_clk_un24_bgack_030_int_i_0_i_n N_20 \ +UDS_000_c N_62_0 N_21 N_276_0 N_23 LDS_000_c N_277_0 N_24 N_286_i N_25 \ +size_c_0__n N_288_i N_289_i size_c_1__n pos_clk_un11_ds_030_d0_i_n A0_c_i \ +size_c_i_1__n N_25_i N_32_0 N_24_i N_31_0 N_23_i N_30_0 ipl_c_i_2__n N_54_0 \ +ipl_c_i_1__n N_53_0 ipl_c_i_0__n N_52_0 nEXP_SPACE_c_i N_55_0 N_50_0 N_3_i \ +N_49_0 N_6_i N_48_0 N_8_i N_46_0 N_9_i N_45_0 N_12_i N_43_0 N_115 N_13_i \ +pos_clk_size_dma_6_0__n a_c_16__n N_42_0 pos_clk_size_dma_6_1__n N_15_i \ +pos_clk_cpu_est_11_3__n a_c_17__n N_40_0 N_16_i a_c_18__n N_39_0 N_19_i \ +un6_uds_000_1 a_c_19__n N_36_0 pos_clk_un24_bgack_030_int_i_0_n N_20_i N_245 \ +a_c_20__n N_35_0 N_246 N_21_i N_247 a_c_21__n N_34_0 N_248 BG_030_c_i N_89 \ +a_c_22__n pos_clk_un6_bg_030_i_n N_92 pos_clk_un8_bg_030_0_n N_102 a_c_23__n \ +N_127_i_1 N_103 N_127_i_2 N_104 a_c_24__n pos_clk_un24_bgack_030_int_i_0_i_1_n \ +N_112 N_80_0_1 N_256 a_c_25__n N_75_i_1 N_258 N_251_0_1 a_c_26__n \ +pos_clk_un11_ds_030_d0_i_1_n N_260 N_340_1 N_265 a_c_27__n N_340_2 N_282 \ +N_340_3 N_71 a_c_28__n N_340_4 un5_ciin_1 pos_clk_un11_clk_000_n_sync_n \ +a_c_29__n un5_ciin_2 N_76 un5_ciin_3 a_c_30__n un5_ciin_4 un5_ciin_5 a_c_31__n \ +un5_ciin_6 pos_clk_un22_bgack_030_int_n un5_ciin_7 N_268 A0_c un5_ciin_8 N_270 \ +un5_ciin_9 N_73 A1_c un5_ciin_10 N_75 un5_ciin_11 N_251 nEXP_SPACE_c \ +un22_berr_1_0 un22_berr_1 un21_fpu_cs_1 N_95 BERR_c pos_clk_un6_bg_030_1_n \ +N_94 N_131_i_1 N_288 BG_030_c N_131_i_2 N_289 N_131_i_3 N_286 N_96_1 N_279 \ +N_96_2 N_277 N_96_3 N_276 BGACK_000_c pos_clk_cpu_est_11_0_1_1__n N_62 \ +pos_clk_cpu_est_11_0_2_1__n N_274 N_310_1 N_313 N_310_2 N_307 N_310_3 N_305 \ +CLK_OSZI_c N_310_4 N_306 N_309_1 N_303 N_309_2 N_304 CLK_EXP_c N_308_1 N_301 \ +N_308_2 N_91 RESET_OUT_0_sqmuxa_5_1 N_85 FPU_SENSE_c RESET_OUT_0_sqmuxa_7_1 \ +N_294 RESET_OUT_0_sqmuxa_7_2 N_296 RESET_OUT_0_sqmuxa_7_3 N_84 N_94_1 N_82 \ +N_95_1 N_83 N_119_i_1 N_293 N_82_1 N_290 N_83_1 N_291 ipl_c_0__n N_296_1 N_283 \ +N_303_1 N_284 ipl_c_1__n N_304_1 N_86 N_306_1 N_80 ipl_c_2__n N_129_i_1 N_78 \ +N_125_i_1 N_108 N_123_i_1 N_109 DTACK_c N_115_0_1 N_100 \ +pos_clk_cpu_est_11_0_1_3__n N_99 N_260_0_1 N_93 N_261_i_1 \ +pos_clk_un14_clk_000_n_sync_n VPA_c N_262_i_1 pos_clk_un9_clk_000_n_sync_n \ +N_263_i_1 N_340 pos_clk_ipl_1_n N_97 RST_c cpu_est_0_3__un3_n N_136 \ +cpu_est_0_3__un1_n N_101 cpu_est_0_3__un0_n N_81 RW_c cpu_est_0_2__un3_n N_116 \ +cpu_est_0_2__un1_n N_96 fc_c_0__n cpu_est_0_2__un0_n N_113 cpu_est_0_1__un3_n \ +N_275 fc_c_1__n cpu_est_0_1__un1_n N_273 cpu_est_0_1__un0_n N_88 \ +bgack_030_int_0_un3_n N_272 AMIGA_BUS_DATA_DIR_c bgack_030_int_0_un1_n N_299 \ +bgack_030_int_0_un0_n N_90 vma_int_0_un3_n N_311 vma_int_0_un1_n N_312 \ +vma_int_0_un0_n N_267 un1_as_000_i rw_000_int_0_un3_n N_264 \ +un1_rst_dly_i_m_i_3__n rw_000_int_0_un1_n pos_clk_un7_clk_000_pe_n \ +rw_000_int_0_un0_n N_308 un1_rst_dly_i_m_i_4__n sm_amiga_srsts_i_0_m2_3__un3_n \ +N_309 sm_amiga_srsts_i_0_m2_3__un1_n AS_030.OE AS_000.OE RW_000.OE DS_030.OE \ +UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE BERR.OE RW.OE CLK_DIV_OUT.OE \ +DSACK1.OE CIIN.OE pos_clk_RST_DLY_5_iv_0_x2_0_ G_137 G_149 G_147 G_145 G_143 \ +G_141 G_139 G_165 G_166 G_167 cpu_est_0_0_x2_0_ pos_clk_CYCLE_DMA_5_1_i_x2 \ +pos_clk_CYCLE_DMA_5_0_i_x2 pos_clk_un24_bgack_030_int_i_0_x2 +.names N_32_0.BLIF IPL_030DFF_2_reg.D +0 1 +.names N_52_0.BLIF IPL_D0_0_.D +0 1 +.names N_53_0.BLIF IPL_D0_1_.D +0 1 +.names N_54_0.BLIF IPL_D0_2_.D +0 1 +.names N_131_i_3.BLIF N_96_i.BLIF SM_AMIGA_i_7_.D +11 1 +.names N_129_i_1.BLIF RST_c.BLIF SM_AMIGA_6_.D +11 1 +.names N_127_i_1.BLIF N_127_i_2.BLIF SM_AMIGA_5_.D +11 1 +.names N_125_i_1.BLIF RST_c.BLIF SM_AMIGA_4_.D +11 1 +.names N_123_i_1.BLIF RST_c.BLIF SM_AMIGA_3_.D +11 1 +.names N_259_0.BLIF SM_AMIGA_2_.D +0 1 +.names N_119_i_1.BLIF RST_c.BLIF SM_AMIGA_1_.D +11 1 +.names N_77_i.BLIF N_101_i.BLIF SM_AMIGA_0_.D +11 1 +.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D +1- 1 +-1 1 +.names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D +1- 1 +-1 1 +.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_reg.D +1- 1 +-1 1 +.names N_30_0.BLIF IPL_030DFF_0_reg.D +0 1 +.names N_31_0.BLIF IPL_030DFF_1_reg.D +0 1 +.names N_98_i.BLIF RST_c.BLIF RST_DLY_0_.D +11 1 +.names RST_c.BLIF un1_rst_dly_i_m_i_2__n.BLIF RST_DLY_1_.D +11 1 +.names RST_c.BLIF un1_rst_dly_i_m_i_3__n.BLIF RST_DLY_2_.D +11 1 +.names RST_c.BLIF un1_rst_dly_i_m_i_4__n.BLIF RST_DLY_3_.D +11 1 +.names RST_c.BLIF un1_rst_dly_i_m_i_5__n.BLIF RST_DLY_4_.D +11 1 +.names RST_c.BLIF un1_rst_dly_i_m_i_6__n.BLIF RST_DLY_5_.D +11 1 +.names RST_c.BLIF un1_rst_dly_i_m_i_7__n.BLIF RST_DLY_6_.D +11 1 +.names RST_c.BLIF un1_rst_dly_i_m_i_8__n.BLIF RST_DLY_7_.D +11 1 +.names N_263_i_1.BLIF RST_c.BLIF CYCLE_DMA_0_.D +11 1 +.names N_262_i_1.BLIF RST_c.BLIF CYCLE_DMA_1_.D +11 1 +.names size_dma_0_0__un1_n.BLIF size_dma_0_0__un0_n.BLIF SIZE_DMA_0_.D +1- 1 +-1 1 +.names size_dma_0_1__un1_n.BLIF size_dma_0_1__un0_n.BLIF SIZE_DMA_1_.D +1- 1 +-1 1 +.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF CLK_000_P_SYNC_0_.D +11 1 +.names N_261_i_1.BLIF pos_clk_un24_bgack_030_int_i_0_i_n.BLIF inst_CLK_030_H.D +11 1 +.names N_105_i.BLIF RST_c.BLIF inst_RESET_OUTreg.D +11 1 +.names N_11.BLIF RST_c.BLIF inst_DS_000_ENABLE.D +11 1 +.names N_39_0.BLIF inst_UDS_000_INT.D +0 1 +.names N_40_0.BLIF inst_RW_000_DMA.D +0 1 +.names N_41_0.BLIF inst_RW_000_INT.D +0 1 +.names N_42_0.BLIF inst_LDS_000_INT.D +0 1 +.names N_43_0.BLIF inst_AS_030_000_SYNC.D +0 1 +.names N_44_0.BLIF inst_AS_000_INT.D +0 1 +.names N_45_0.BLIF inst_DSACK1_INTreg.D +0 1 +.names N_46_0.BLIF inst_A0_DMA.D +0 1 +.names N_48_0.BLIF inst_AS_000_DMA.D +0 1 +.names N_49_0.BLIF inst_DS_000_DMA.D +0 1 +.names N_50_0.BLIF inst_DS_030_D0.D +0 1 +.names N_102.BLIF inst_AS_030_D0.D +0 1 +.names N_55_0.BLIF inst_nEXP_SPACE_D0reg.D +0 1 +.names N_56_0.BLIF inst_VPA_D.D +0 1 +.names N_57_0.BLIF inst_DTACK_D0.D +0 1 +.names N_33_0.BLIF inst_BGACK_030_INTreg.D +0 1 +.names N_34_0.BLIF BG_000DFFreg.D +0 1 +.names N_35_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D +0 1 +.names N_36_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D +0 1 +.names N_37_0.BLIF inst_VMA_INTreg.D +0 1 +.names AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa.BLIF inst_BGACK_030_INT_D.D +0 1 +.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D +0 1 +.names N_310_4.BLIF N_310_3.BLIF N_310 +11 1 +.names un1_rst_dly_i_m_5__n.BLIF un1_rst_dly_i_m_i_5__n +0 1 +.names CLK_000_PE_i.BLIF sm_amiga_srsts_i_0_m2_3__un3_n.BLIF \ +sm_amiga_srsts_i_0_m2_3__un0_n +11 1 +.names inst_CLK_000_PE.BLIF CYCLE_DMA_0_.BLIF N_220 +11 1 +.names SM_AMIGA_1_.BLIF sm_amiga_srsts_i_0_m2_1__un3_n +0 1 +.names pos_clk_cpu_est_11_0_1__n.BLIF pos_clk_cpu_est_11_1__n +0 1 +.names un1_rst_dly_i_m_6__n.BLIF un1_rst_dly_i_m_i_6__n +0 1 +.names BERR_i.BLIF SM_AMIGA_1_.BLIF sm_amiga_srsts_i_0_m2_1__un1_n +11 1 +.names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF N_14 +1- 1 +-1 1 +.names CLK_000_PE_i.BLIF sm_amiga_srsts_i_0_m2_1__un3_n.BLIF \ +sm_amiga_srsts_i_0_m2_1__un0_n +11 1 +.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF N_18 +1- 1 +-1 1 +.names un1_rst_dly_i_m_7__n.BLIF un1_rst_dly_i_m_i_7__n +0 1 +.names inst_BGACK_030_INTreg.BLIF un1_amiga_bus_enable_dma_high_0_m2_0__un3_n +0 1 +.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF N_22 +1- 1 +-1 1 +.names SM_AMIGA_i_7_.BLIF inst_BGACK_030_INTreg.BLIF \ +un1_amiga_bus_enable_dma_high_0_m2_0__un1_n +11 1 +.names inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF RESET_OUT_0_sqmuxa_1 +11 1 +.names un1_rst_dly_i_m_8__n.BLIF un1_rst_dly_i_m_i_8__n +0 1 +.names AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF \ +un1_amiga_bus_enable_dma_high_0_m2_0__un3_n.BLIF \ +un1_amiga_bus_enable_dma_high_0_m2_0__un0_n +11 1 +.names vcc_n_n + 1 +.names RESET_OUT_0_sqmuxa_1.BLIF RST_DLY_1_.BLIF N_205 +11 1 +.names SM_AMIGA_5_.BLIF un1_sm_amiga_7_i_m2_un3_n +0 1 +.names N_211.BLIF RST_DLY_5_.BLIF N_213 +11 1 +.names un1_rst_dly_i_m_2__n.BLIF un1_rst_dly_i_m_i_2__n +0 1 +.names RW_i.BLIF SM_AMIGA_5_.BLIF un1_sm_amiga_7_i_m2_un1_n +11 1 +.names sm_amiga_i_3__n.BLIF un1_sm_amiga_7_i_m2_un3_n.BLIF \ +un1_sm_amiga_7_i_m2_un0_n +11 1 +.names RESET_OUT_0_sqmuxa_i.BLIF RESET_OUT_i.BLIF N_105 +11 1 +.names N_98.BLIF N_98_i +0 1 +.names N_248.BLIF size_dma_0_0__un3_n +0 1 +.names gnd_n_n +.names N_87_i_i.BLIF RESET_OUT_0_sqmuxa_i.BLIF N_98 +11 1 +.names pos_clk_size_dma_6_0__n.BLIF N_248.BLIF size_dma_0_0__un1_n +11 1 +.names AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF BGACK_030_INT_i.BLIF \ +un1_amiga_bus_enable_low +11 1 +.names RESET_OUT_0_sqmuxa_7.BLIF RST_DLY_7_.BLIF RESET_OUT_0_sqmuxa +11 1 +.names N_105.BLIF N_105_i +0 1 +.names SIZE_DMA_0_.BLIF size_dma_0_0__un3_n.BLIF size_dma_0_0__un0_n +11 1 +.names AS_000_DMA_i.BLIF AS_000_i.BLIF un6_as_030 +11 1 +.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_2__n.BLIF un1_rst_dly_i_m_2__n +11 1 +.names N_248.BLIF size_dma_0_1__un3_n +0 1 +.names SIZE_DMA_1_.BLIF size_dma_i_0__n.BLIF un3_size +11 1 +.names N_22.BLIF N_22_i +0 1 +.names pos_clk_size_dma_6_1__n.BLIF N_248.BLIF size_dma_0_1__un1_n +11 1 +.names SIZE_DMA_0_.BLIF size_dma_i_1__n.BLIF un4_size +11 1 +.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_8__n.BLIF un1_rst_dly_i_m_8__n +11 1 +.names N_22_i.BLIF RST_c.BLIF N_33_0 +11 1 +.names SIZE_DMA_1_.BLIF size_dma_0_1__un3_n.BLIF size_dma_0_1__un0_n +11 1 +.names un5_ciin_10.BLIF un5_ciin_11.BLIF un5_ciin +11 1 +.names N_18.BLIF N_18_i +0 1 +.names pos_clk_ipl_n.BLIF ipl_030_0_0__un3_n +0 1 +.names AS_000_INT_i.BLIF AS_030_i.BLIF un4_as_000 +11 1 +.names RESET_OUT_0_sqmuxa_5_1.BLIF RST_DLY_2_.BLIF RESET_OUT_0_sqmuxa_5 +11 1 +.names N_18_i.BLIF RST_c.BLIF N_37_0 +11 1 +.names ipl_c_0__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_0__un1_n +11 1 +.names un21_fpu_cs_1.BLIF un22_berr_1.BLIF un21_fpu_cs +11 1 +.names RESET_OUT_0_sqmuxa_7_3.BLIF RST_DLY_6_.BLIF RESET_OUT_0_sqmuxa_7 +11 1 +.names N_14.BLIF N_14_i +0 1 +.names IPL_030DFF_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n +11 1 +.names un22_berr_1_0.BLIF N_340.BLIF un22_berr +11 1 +.names N_14_i.BLIF RST_c.BLIF N_41_0 +11 1 +.names pos_clk_ipl_n.BLIF ipl_030_0_1__un3_n +0 1 +.names AS_000_i.BLIF DS_000_DMA_i.BLIF un6_ds_030 +11 1 +.names N_10.BLIF N_10_i +0 1 +.names ipl_c_1__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_1__un1_n +11 1 +.names UDS_000_INT_i.BLIF un6_uds_000_1.BLIF un6_uds_000 +11 1 +.names N_209.BLIF RST_DLY_4_.BLIF N_211 +11 1 +.names N_10_i.BLIF RST_c.BLIF N_44_0 +11 1 +.names IPL_030DFF_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n +11 1 +.names LDS_000_INT_i.BLIF un6_uds_000_1.BLIF un6_lds_000 +11 1 +.names pos_clk_cpu_est_11_0_1_1__n.BLIF pos_clk_cpu_est_11_0_2_1__n.BLIF \ +pos_clk_cpu_est_11_0_1__n +11 1 +.names pos_clk_ipl_n.BLIF ipl_030_0_2__un3_n +0 1 +.names RESET_OUT_0_sqmuxa_5.BLIF RST_DLY_3_.BLIF N_209 +11 1 +.names N_312.BLIF N_312_i +0 1 +.names ipl_c_2__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_2__un1_n +11 1 +.names N_90.BLIF N_90_i +0 1 +.names IPL_030DFF_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n +11 1 +.names N_88.BLIF N_88_i +0 1 +.names pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_high_0_un3_n +0 1 +.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_7__n.BLIF un1_rst_dly_i_m_7__n +11 1 +.names N_299.BLIF N_299_i +0 1 +.names N_104_i.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF \ +amiga_bus_enable_dma_high_0_un1_n +11 1 +.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_6__n.BLIF un1_rst_dly_i_m_6__n +11 1 +.names N_268_i.BLIF SM_AMIGA_4_.BLIF N_275_0 +11 1 +.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ +amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n +11 1 +.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_5__n.BLIF un1_rst_dly_i_m_5__n +11 1 +.names N_268.BLIF sm_amiga_i_3__n.BLIF N_274_0 +11 1 +.names pos_clk_un8_bg_030_n.BLIF bg_000_0_un3_n +0 1 +.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_4__n.BLIF un1_rst_dly_i_m_4__n +11 1 +.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_273_i +11 1 +.names BG_030_c.BLIF pos_clk_un8_bg_030_n.BLIF bg_000_0_un1_n +11 1 +.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_3__n.BLIF un1_rst_dly_i_m_3__n +11 1 +.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF N_272_i +11 1 +.names BG_000DFFreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n +11 1 +.names N_71.BLIF N_71_i +0 1 +.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_270_i +11 1 +.names N_260.BLIF ds_000_dma_0_un3_n +0 1 +.names un1_amiga_bus_enable_low.BLIF un1_amiga_bus_enable_low_i +0 1 +.names BERR_c.BLIF CLK_000_PE_i.BLIF N_268_i +11 1 +.names pos_clk_ds_000_dma_4_n.BLIF N_260.BLIF ds_000_dma_0_un1_n +11 1 +.names un21_fpu_cs.BLIF un21_fpu_cs_i +0 1 +.names N_310.BLIF N_310_i +0 1 +.names inst_DS_000_DMA.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n +11 1 +.names inst_RESET_OUTreg.BLIF RESET_OUT_i +0 1 +.names N_311.BLIF N_311_i +0 1 +.names N_258.BLIF as_000_dma_0_un3_n +0 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i +0 1 +.names N_310_i.BLIF N_311_i.BLIF N_267_0 +11 1 +.names pos_clk_un24_bgack_030_int_i_0_n.BLIF N_258.BLIF as_000_dma_0_un1_n +11 1 +.names RESET_OUT_0_sqmuxa.BLIF RESET_OUT_0_sqmuxa_i +0 1 +.names N_309.BLIF N_309_i +0 1 +.names inst_AS_000_DMA.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n +11 1 +.names G_139.BLIF un1_rst_dly_i_3__n +0 1 +.names N_308.BLIF N_308_i +0 1 +.names pos_clk_un5_bgack_030_int_d_n.BLIF a0_dma_0_un3_n +0 1 +.names G_141.BLIF un1_rst_dly_i_4__n +0 1 +.names N_308_i.BLIF N_309_i.BLIF pos_clk_un7_clk_000_pe_0_n +11 1 +.names pos_clk_a0_dma_3_n.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF \ +a0_dma_0_un1_n +11 1 +.names G_143.BLIF un1_rst_dly_i_5__n +0 1 +.names RW_i.BLIF SM_AMIGA_5_.BLIF N_264_0 +11 1 +.names inst_A0_DMA.BLIF a0_dma_0_un3_n.BLIF a0_dma_0_un0_n +11 1 +.names G_145.BLIF un1_rst_dly_i_6__n +0 1 +.names N_304.BLIF N_304_i +0 1 +.names N_245.BLIF dsack1_int_0_un3_n +0 1 +.names G_147.BLIF un1_rst_dly_i_7__n +0 1 +.names N_303.BLIF N_303_i +0 1 +.names N_92_i.BLIF N_245.BLIF dsack1_int_0_un1_n +11 1 +.names G_149.BLIF un1_rst_dly_i_8__n +0 1 +.names N_303_i.BLIF N_304_i.BLIF N_186_i +11 1 +.names inst_DSACK1_INTreg.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n +11 1 +.names G_137.BLIF un1_rst_dly_i_2__n +0 1 +.names VPA_c.BLIF VPA_c_i +0 1 +.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n +0 1 +.names pos_clk_RST_DLY_5_iv_0_x2_0_.BLIF N_87_i_i +0 1 +.names RST_c.BLIF VPA_c_i.BLIF N_56_0 +11 1 +.names inst_AS_000_INT.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n +11 1 +.names cpu_est_3_reg.BLIF cpu_est_i_3__n +0 1 +.names DTACK_c.BLIF DTACK_c_i +0 1 +.names sm_amiga_i_5__n.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n +11 1 +.names cpu_est_0_.BLIF cpu_est_i_0__n +0 1 +.names DTACK_c_i.BLIF RST_c.BLIF N_57_0 +11 1 +.names DS_000_ENABLE_1_sqmuxa_1.BLIF ds_000_enable_0_un3_n +0 1 +.names inst_VPA_D.BLIF VPA_D_i +0 1 +.names N_97.BLIF N_97_i +0 1 +.names inst_DS_000_ENABLE.BLIF DS_000_ENABLE_1_sqmuxa_1.BLIF \ +ds_000_enable_0_un1_n +11 1 +.names inst_VMA_INTreg.BLIF VMA_INT_i +0 1 +.names N_282_i.BLIF ds_000_enable_0_un3_n.BLIF ds_000_enable_0_un0_n +11 1 +.names cpu_est_1_.BLIF cpu_est_i_1__n +0 1 +.names N_96.BLIF N_96_i +0 1 +.names N_246.BLIF as_030_000_sync_0_un3_n +0 1 +.names inst_CLK_000_PE.BLIF CLK_000_PE_i +0 1 +.names N_95.BLIF N_95_i +0 1 +.names inst_AS_030_000_SYNC.BLIF N_246.BLIF as_030_000_sync_0_un1_n +11 1 +.names BERR_c.BLIF BERR_i +0 1 +.names N_94.BLIF N_94_i +0 1 +.names pos_clk_un3_as_030_d0_n.BLIF as_030_000_sync_0_un3_n.BLIF \ +as_030_000_sync_0_un0_n +11 1 +.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n +0 1 +.names N_313.BLIF N_313_i +0 1 +.names pos_clk_un3_ds_030_d0_n.BLIF lds_000_int_0_un3_n +0 1 +.names cpu_est_2_.BLIF cpu_est_i_2__n +0 1 +.names N_313_i.BLIF SM_AMIGA_3_.BLIF N_136_i +11 1 +.names pos_clk_un11_ds_030_d0_i_n.BLIF pos_clk_un3_ds_030_d0_n.BLIF \ +lds_000_int_0_un1_n +11 1 +.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +0 1 +.names inst_CLK_000_NE.BLIF SM_AMIGA_1_.BLIF N_81_0 +11 1 +.names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n +11 1 +.names inst_DTACK_D0.BLIF DTACK_D0_i +0 1 +.names N_116.BLIF N_116_i +0 1 +.names pos_clk_un5_bgack_030_int_d_n.BLIF rw_000_dma_0_un3_n +0 1 +.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n +0 1 +.names N_116_i.BLIF RST_c.BLIF N_77_i +11 1 +.names N_265.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF rw_000_dma_0_un1_n +11 1 +.names pos_clk_un6_bg_030_1_n.BLIF inst_CLK_000_D0.BLIF pos_clk_un6_bg_030_n +11 1 +.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n +0 1 +.names sm_amiga_i_1__n.BLIF sm_amiga_i_5__n.BLIF N_73_i +11 1 +.names inst_RW_000_DMA.BLIF rw_000_dma_0_un3_n.BLIF rw_000_dma_0_un0_n +11 1 +.names inst_CLK_000_NE.BLIF CLK_000_NE_i +0 1 +.names N_101.BLIF N_101_i +0 1 +.names pos_clk_un3_ds_030_d0_n.BLIF uds_000_int_0_un3_n +0 1 +.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n +0 1 +.names A0_c.BLIF pos_clk_un3_ds_030_d0_n.BLIF uds_000_int_0_un1_n +11 1 +.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n +0 1 +.names CLK_000_N_SYNC_10_.BLIF clk_000_n_sync_i_10__n +0 1 +.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n +11 1 +.names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_PRE_D_i +0 1 +.names pos_clk_un9_clk_000_n_sync_n.BLIF pos_clk_un9_clk_000_n_sync_i_n +0 1 +.names pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_low_0_un3_n +0 1 +.names pos_clk_ipl_1_n.BLIF N_225_i.BLIF pos_clk_ipl_n +11 1 +.names pos_clk_un11_clk_000_n_sync_n.BLIF pos_clk_un11_clk_000_n_sync_i_n +0 1 +.names clk_000_n_sync_i_10__n.BLIF pos_clk_un9_clk_000_n_sync_i_n.BLIF \ +pos_clk_un14_clk_000_n_sync_0_n +11 1 +.names N_103_i.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF \ +amiga_bus_enable_dma_low_0_un1_n +11 1 +.names DS_030_D0_i.BLIF SM_AMIGA_6_.BLIF pos_clk_un3_ds_030_d0_n +11 1 +.names LDS_000_c.BLIF LDS_000_i +0 1 +.names LDS_000_c.BLIF UDS_000_c.BLIF pos_clk_un22_bgack_030_int_i_n +11 1 +.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF \ +amiga_bus_enable_dma_low_0_un3_n.BLIF amiga_bus_enable_dma_low_0_un0_n +11 1 +.names UDS_000_c.BLIF UDS_000_i +0 1 +.names N_86.BLIF N_86_i +0 1 +.names BGACK_030_INT_i.BLIF RST_c.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa +11 1 +.names inst_nEXP_SPACE_D0reg.BLIF nEXP_SPACE_D0_i +0 1 +.names N_93.BLIF N_93_i +0 1 +.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n +0 1 +.names AS_030_c.BLIF AS_030_i +0 1 +.names N_99.BLIF N_99_i +0 1 +.names A1_c.BLIF A1_i +0 1 +.names N_99_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n +11 1 +.names inst_CLK_000_D1.BLIF CLK_000_D1_i +0 1 +.names N_100.BLIF N_100_i +0 1 +.names RW_000_c.BLIF RW_000_i +0 1 +.names N_100_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n +11 1 +.names inst_CLK_030_H.BLIF CLK_030_H_i +0 1 +.names N_92_i.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_245_0 +11 1 +.names inst_AS_000_DMA.BLIF AS_000_DMA_i +0 1 +.names N_108.BLIF N_108_i +0 1 +.names AS_000_c.BLIF AS_000_i +0 1 +.names N_109.BLIF N_109_i +0 1 +.names pos_clk_un8_bg_030_0_n.BLIF pos_clk_un8_bg_030_n +0 1 +.names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n +0 1 +.names N_108_i.BLIF N_109_i.BLIF N_246_0 +11 1 +.names RW_c.BLIF RW_i +0 1 +.names un5_ciin.BLIF un5_ciin_i +0 1 +.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i +0 1 +.names nEXP_SPACE_D0_i.BLIF un5_ciin_i.BLIF N_247_0 +11 1 +.names FPU_SENSE_c.BLIF FPU_SENSE_i +0 1 +.names RST_c.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF N_248_0 +11 1 +.names inst_AS_030_D0.BLIF AS_030_D0_i +0 1 +.names inst_CLK_000_D0.BLIF CLK_000_D0_i +0 1 +.names a_c_24__n.BLIF a_i_24__n +0 1 +.names CLK_000_D0_i.BLIF inst_CLK_000_D1.BLIF N_249_i +11 1 +.names SIZE_DMA_0_.BLIF size_dma_i_0__n +0 1 +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +0 1 +.names SIZE_DMA_1_.BLIF size_dma_i_1__n +0 1 +.names N_251_0_1.BLIF inst_nEXP_SPACE_D0reg.BLIF N_251_0 +11 1 +.names a_c_16__n.BLIF a_i_16__n +0 1 +.names AS_030_D0_i.BLIF BERR_c.BLIF pos_clk_un3_as_030_d0_i_n +11 1 +.names a_c_18__n.BLIF a_i_18__n +0 1 +.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ +pos_clk_un5_bgack_030_int_d_i_n +11 1 +.names a_c_19__n.BLIF a_i_19__n +0 1 +.names N_75_i_1.BLIF sm_amiga_i_4__n.BLIF N_75_i +11 1 +.names a_c_31__n.BLIF a_i_31__n +0 1 +.names LDS_000_i.BLIF UDS_000_i.BLIF N_76_i +11 1 +.names a_c_29__n.BLIF a_i_29__n +0 1 +.names CLK_000_NE_i.BLIF SM_AMIGA_1_.BLIF N_78_0 +11 1 +.names a_c_30__n.BLIF a_i_30__n +0 1 +.names N_80_0_1.BLIF sm_amiga_i_i_7__n.BLIF N_80_0 +11 1 +.names a_c_27__n.BLIF a_i_27__n +0 1 +.names CLK_EXP_c.BLIF CLK_EXP_c_i +0 1 +.names a_c_28__n.BLIF a_i_28__n +0 1 +.names CLK_EXP_c_i.BLIF pos_clk_un24_bgack_030_int_i_0_i_n.BLIF N_258_0 +11 1 +.names a_c_25__n.BLIF a_i_25__n +0 1 +.names N_283.BLIF N_283_i +0 1 +.names a_c_26__n.BLIF a_i_26__n +0 1 +.names N_284.BLIF N_284_i +0 1 +.names inst_UDS_000_INT.BLIF UDS_000_INT_i +0 1 +.names inst_LDS_000_INT.BLIF LDS_000_INT_i +0 1 +.names N_290.BLIF N_290_i +0 1 +.names DS_030_c.BLIF DS_030_i +0 1 +.names N_291.BLIF N_291_i +0 1 +.names pos_clk_un5_bgack_030_int_d_i_n.BLIF pos_clk_un5_bgack_030_int_d_n +0 1 +.names G_165.BLIF N_224_i +0 1 +.names G_166.BLIF N_225_i +0 1 +.names N_279.BLIF N_279_i +0 1 +.names G_167.BLIF N_226_i +0 1 +.names N_293.BLIF N_293_i +0 1 +.names N_82.BLIF N_82_i +0 1 +.names N_83.BLIF N_83_i +0 1 +.names N_104.BLIF N_104_i +0 1 +.names N_82_i.BLIF N_83_i.BLIF N_259_0 +11 1 +.names N_103.BLIF N_103_i +0 1 +.names N_84.BLIF N_84_i +0 1 +.names pos_clk_un3_as_030_d0_i_n.BLIF pos_clk_un3_as_030_d0_n +0 1 +.names N_282.BLIF N_282_i +0 1 +.names N_115_0_1.BLIF SM_AMIGA_i_7_.BLIF N_115_0 +11 1 +.names N_92.BLIF N_92_i +0 1 +.names N_85.BLIF N_85_i +0 1 +.names sm_amiga_i_5__n.BLIF pos_clk_un3_as_030_d0_i_n.BLIF AS_000_INT_1_sqmuxa +11 1 +.names un6_lds_000.BLIF un6_lds_000_i +0 1 +.names N_294.BLIF N_294_i +0 1 +.names N_282.BLIF pos_clk_un3_as_030_d0_i_n.BLIF DS_000_ENABLE_1_sqmuxa_1 +11 1 +.names un6_uds_000.BLIF un6_uds_000_i +0 1 +.names N_296.BLIF N_296_i +0 1 +.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF pos_clk_a0_dma_3_n +11 1 +.names un6_ds_030.BLIF un6_ds_030_i +0 1 +.names pos_clk_cpu_est_11_0_1_3__n.BLIF N_294_i.BLIF pos_clk_cpu_est_11_0_3__n +11 1 +.names pos_clk_ds_000_dma_4_0_n.BLIF pos_clk_ds_000_dma_4_n +0 1 +.names inst_DS_000_DMA.BLIF DS_000_DMA_i +0 1 +.names N_91.BLIF N_91_i +0 1 +.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3 +1- 1 +-1 1 +.names un4_as_000.BLIF un4_as_000_i +0 1 +.names N_260_0_1.BLIF pos_clk_un24_bgack_030_int_i_0_i_n.BLIF N_260_0 +11 1 +.names inst_AS_000_INT.BLIF AS_000_INT_i +0 1 +.names N_301.BLIF N_301_i +0 1 +.names un6_as_030.BLIF un6_as_030_i +0 1 +.names N_301_i.BLIF pos_clk_un24_bgack_030_int_i_0_i_n.BLIF \ +pos_clk_ds_000_dma_4_0_n +11 1 +.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF N_6 +1- 1 +-1 1 +.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i +0 1 +.names N_305.BLIF N_305_i +0 1 +.names a0_dma_0_un1_n.BLIF a0_dma_0_un0_n.BLIF N_8 +1- 1 +-1 1 +.names inst_DS_030_D0.BLIF DS_030_D0_i +0 1 +.names N_306.BLIF N_306_i +0 1 +.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF N_9 +1- 1 +-1 1 +.names N_305_i.BLIF N_306_i.BLIF AMIGA_BUS_DATA_DIR_c_0 +11 1 +.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF N_10 +1- 1 +-1 1 +.names N_307.BLIF N_307_i +0 1 +.names ds_000_enable_0_un1_n.BLIF ds_000_enable_0_un0_n.BLIF N_11 +1- 1 +-1 1 +.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF N_12 +1- 1 +-1 1 +.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF N_13 +1- 1 +-1 1 +.names rw_000_dma_0_un1_n.BLIF rw_000_dma_0_un0_n.BLIF N_15 +1- 1 +-1 1 +.names BGACK_030_INT_i.BLIF RW_000_i.BLIF N_265_0 +11 1 +.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_16 +1- 1 +-1 1 +.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_269_i +11 1 +.names amiga_bus_enable_dma_low_0_un1_n.BLIF \ +amiga_bus_enable_dma_low_0_un0_n.BLIF N_19 +1- 1 +-1 1 +.names pos_clk_un24_bgack_030_int_i_0_i_1_n.BLIF \ +pos_clk_un22_bgack_030_int_n.BLIF pos_clk_un24_bgack_030_int_i_0_i_n +11 1 +.names amiga_bus_enable_dma_high_0_un1_n.BLIF \ +amiga_bus_enable_dma_high_0_un0_n.BLIF N_20 +1- 1 +-1 1 +.names N_268_i.BLIF SM_AMIGA_6_.BLIF N_62_0 +11 1 +.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF N_21 +1- 1 +-1 1 +.names inst_CLK_000_PE.BLIF SM_AMIGA_6_.BLIF N_276_0 +11 1 +.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF N_23 +1- 1 +-1 1 +.names AS_000_DMA_i.BLIF CLK_EXP_c_i.BLIF N_277_0 +11 1 +.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF N_24 +1- 1 +-1 1 +.names N_286.BLIF N_286_i +0 1 +.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_25 +1- 1 +-1 1 +.names N_288.BLIF N_288_i +0 1 +.names N_289.BLIF N_289_i +0 1 +.names pos_clk_un11_ds_030_d0_i_1_n.BLIF size_c_0__n.BLIF \ +pos_clk_un11_ds_030_d0_i_n +11 1 +.names A0_c.BLIF A0_c_i +0 1 +.names size_c_1__n.BLIF size_c_i_1__n +0 1 +.names N_25.BLIF N_25_i +0 1 +.names N_25_i.BLIF RST_c.BLIF N_32_0 +11 1 +.names N_24.BLIF N_24_i +0 1 +.names N_24_i.BLIF RST_c.BLIF N_31_0 +11 1 +.names N_23.BLIF N_23_i +0 1 +.names N_23_i.BLIF RST_c.BLIF N_30_0 +11 1 +.names ipl_c_2__n.BLIF ipl_c_i_2__n +0 1 +.names ipl_c_i_2__n.BLIF RST_c.BLIF N_54_0 +11 1 +.names ipl_c_1__n.BLIF ipl_c_i_1__n +0 1 +.names ipl_c_i_1__n.BLIF RST_c.BLIF N_53_0 +11 1 +.names ipl_c_0__n.BLIF ipl_c_i_0__n +0 1 +.names ipl_c_i_0__n.BLIF RST_c.BLIF N_52_0 +11 1 +.names nEXP_SPACE_c.BLIF nEXP_SPACE_c_i +0 1 +.names RST_c.BLIF nEXP_SPACE_c_i.BLIF N_55_0 +11 1 +.names DS_030_i.BLIF RST_c.BLIF N_50_0 +11 1 +.names N_3.BLIF N_3_i +0 1 +.names N_3_i.BLIF RST_c.BLIF N_49_0 +11 1 +.names N_6.BLIF N_6_i +0 1 +.names N_6_i.BLIF RST_c.BLIF N_48_0 +11 1 +.names N_8.BLIF N_8_i +0 1 +.names N_8_i.BLIF RST_c.BLIF N_46_0 +11 1 +.names N_9.BLIF N_9_i +0 1 +.names N_9_i.BLIF RST_c.BLIF N_45_0 +11 1 +.names N_12.BLIF N_12_i +0 1 +.names N_12_i.BLIF RST_c.BLIF N_43_0 +11 1 +.names N_115_0.BLIF N_115 +0 1 +.names N_13.BLIF N_13_i +0 1 +.names pos_clk_size_dma_6_0_0__n.BLIF pos_clk_size_dma_6_0__n +0 1 +.names N_13_i.BLIF RST_c.BLIF N_42_0 +11 1 +.names pos_clk_size_dma_6_0_1__n.BLIF pos_clk_size_dma_6_1__n +0 1 +.names N_15.BLIF N_15_i +0 1 +.names pos_clk_cpu_est_11_0_3__n.BLIF pos_clk_cpu_est_11_3__n +0 1 +.names N_15_i.BLIF RST_c.BLIF N_40_0 +11 1 +.names N_16.BLIF N_16_i +0 1 +.names N_16_i.BLIF RST_c.BLIF N_39_0 +11 1 +.names N_19.BLIF N_19_i +0 1 +.names inst_DS_000_ENABLE.BLIF DS_030_i.BLIF un6_uds_000_1 +11 1 +.names N_19_i.BLIF RST_c.BLIF N_36_0 +11 1 +.names pos_clk_un24_bgack_030_int_i_0_i_n.BLIF \ +pos_clk_un24_bgack_030_int_i_0_n +0 1 +.names N_20.BLIF N_20_i +0 1 +.names N_245_0.BLIF N_245 +0 1 +.names N_20_i.BLIF RST_c.BLIF N_35_0 +11 1 +.names N_246_0.BLIF N_246 +0 1 +.names N_21.BLIF N_21_i +0 1 +.names N_247_0.BLIF N_247 +0 1 +.names N_21_i.BLIF RST_c.BLIF N_34_0 +11 1 +.names N_248_0.BLIF N_248 +0 1 +.names BG_030_c.BLIF BG_030_c_i +0 1 +.names BGACK_030_INT_i.BLIF nEXP_SPACE_D0_i.BLIF N_89 +11 1 +.names pos_clk_un6_bg_030_n.BLIF pos_clk_un6_bg_030_i_n +0 1 +.names SM_AMIGA_1_.BLIF pos_clk_un14_clk_000_n_sync_n.BLIF N_92 +11 1 +.names BG_030_c_i.BLIF pos_clk_un6_bg_030_i_n.BLIF pos_clk_un8_bg_030_0_n +11 1 +.names AS_030_i.BLIF RST_c.BLIF N_102 +11 1 +.names N_286_i.BLIF RST_c.BLIF N_127_i_1 +11 1 +.names A1_c.BLIF BGACK_030_INT_i.BLIF N_103 +11 1 +.names N_288_i.BLIF N_289_i.BLIF N_127_i_2 +11 1 +.names A1_i.BLIF BGACK_030_INT_i.BLIF N_104 +11 1 +.names pos_clk_un24_bgack_030_int_i_0_x2.BLIF N_269_i.BLIF \ +pos_clk_un24_bgack_030_int_i_0_i_1_n +11 1 +.names N_256.BLIF nEXP_SPACE_D0_i.BLIF N_112 +11 1 +.names inst_nEXP_SPACE_D0reg.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF \ +N_80_0_1 +11 1 +.names BGACK_030_INT_i.BLIF inst_RESET_OUTreg.BLIF N_256 +11 1 +.names sm_amiga_i_2__n.BLIF sm_amiga_i_6__n.BLIF N_75_i_1 +11 1 +.names N_258_0.BLIF N_258 +0 1 +.names N_249_i.BLIF AS_030_000_SYNC_i.BLIF N_251_0_1 +11 1 +.names size_c_i_1__n.BLIF A0_c_i.BLIF pos_clk_un11_ds_030_d0_i_1_n +11 1 +.names N_260_0.BLIF N_260 +0 1 +.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_340_1 +11 1 +.names N_265_0.BLIF N_265 +0 1 +.names a_c_17__n.BLIF a_i_16__n.BLIF N_340_2 +11 1 +.names un1_sm_amiga_7_i_m2_un1_n.BLIF un1_sm_amiga_7_i_m2_un0_n.BLIF N_282 +1- 1 +-1 1 +.names a_i_18__n.BLIF a_i_19__n.BLIF N_340_3 +11 1 +.names un1_amiga_bus_enable_dma_high_0_m2_0__un1_n.BLIF \ +un1_amiga_bus_enable_dma_high_0_m2_0__un0_n.BLIF N_71 +1- 1 +-1 1 +.names N_340_1.BLIF N_340_2.BLIF N_340_4 +11 1 +.names AS_030_D0_i.BLIF a_c_20__n.BLIF un5_ciin_1 +11 1 +.names CLK_EXP_c.BLIF CLK_OUT_PRE_D_i.BLIF pos_clk_un11_clk_000_n_sync_n +11 1 +.names a_c_21__n.BLIF a_c_22__n.BLIF un5_ciin_2 +11 1 +.names N_76_i.BLIF N_76 +0 1 +.names a_c_23__n.BLIF a_i_24__n.BLIF un5_ciin_3 +11 1 +.names a_i_25__n.BLIF a_i_26__n.BLIF un5_ciin_4 +11 1 +.names a_i_31__n.BLIF a_i_27__n.BLIF un5_ciin_5 +11 1 +.names a_i_28__n.BLIF a_i_29__n.BLIF un5_ciin_6 +11 1 +.names pos_clk_un22_bgack_030_int_i_n.BLIF pos_clk_un22_bgack_030_int_n +0 1 +.names un5_ciin_1.BLIF un5_ciin_2.BLIF un5_ciin_7 +11 1 +.names N_268_i.BLIF N_268 +0 1 +.names un5_ciin_3.BLIF un5_ciin_4.BLIF un5_ciin_8 +11 1 +.names N_270_i.BLIF N_270 +0 1 +.names un5_ciin_5.BLIF un5_ciin_6.BLIF un5_ciin_9 +11 1 +.names N_73_i.BLIF N_73 +0 1 +.names un5_ciin_7.BLIF un5_ciin_8.BLIF un5_ciin_10 +11 1 +.names N_75_i.BLIF N_75 +0 1 +.names un5_ciin_9.BLIF a_i_30__n.BLIF un5_ciin_11 +11 1 +.names N_251_0.BLIF N_251 +0 1 +.names un22_berr_1.BLIF FPU_SENSE_c.BLIF un22_berr_1_0 +11 1 +.names AS_030_i.BLIF BGACK_000_c.BLIF un22_berr_1 +11 1 +.names FPU_SENSE_i.BLIF N_340.BLIF un21_fpu_cs_1 +11 1 +.names N_95_1.BLIF CLK_000_NE_i.BLIF N_95 +11 1 +.names inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_D0.BLIF pos_clk_un6_bg_030_1_n +11 1 +.names N_94_1.BLIF CLK_000_PE_i.BLIF N_94 +11 1 +.names N_97_i.BLIF N_77_i.BLIF N_131_i_1 +11 1 +.names BERR_i.BLIF SM_AMIGA_5_.BLIF N_288 +11 1 +.names N_94_i.BLIF N_95_i.BLIF N_131_i_2 +11 1 +.names inst_CLK_000_NE.BLIF sm_amiga_i_6__n.BLIF N_289 +11 1 +.names N_131_i_1.BLIF N_131_i_2.BLIF N_131_i_3 +11 1 +.names N_276.BLIF sm_amiga_i_5__n.BLIF N_286 +11 1 +.names N_73_i.BLIF N_75_i.BLIF N_96_1 +11 1 +.names sm_amiga_srsts_i_0_m2_3__un1_n.BLIF sm_amiga_srsts_i_0_m2_3__un0_n.BLIF \ +N_279 +1- 1 +-1 1 +.names N_251.BLIF sm_amiga_i_0__n.BLIF N_96_2 +11 1 +.names N_277_0.BLIF N_277 +0 1 +.names N_96_1.BLIF N_96_2.BLIF N_96_3 +11 1 +.names N_276_0.BLIF N_276 +0 1 +.names N_88_i.BLIF N_90_i.BLIF pos_clk_cpu_est_11_0_1_1__n +11 1 +.names N_62_0.BLIF N_62 +0 1 +.names N_299_i.BLIF N_312_i.BLIF pos_clk_cpu_est_11_0_2_1__n +11 1 +.names N_274_0.BLIF N_274 +0 1 +.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_310_1 +11 1 +.names inst_CLK_000_NE_D0.BLIF N_267.BLIF N_313 +11 1 +.names VMA_INT_i.BLIF VPA_D_i.BLIF N_310_2 +11 1 +.names CLK_030_H_i.BLIF N_277.BLIF N_307 +11 1 +.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF N_310_3 +11 1 +.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_305 +11 1 +.names N_310_1.BLIF N_310_2.BLIF N_310_4 +11 1 +.names N_306_1.BLIF nEXP_SPACE_D0_i.BLIF N_306 +11 1 +.names inst_CLK_000_NE.BLIF N_312.BLIF N_309_1 +11 1 +.names N_303_1.BLIF cpu_est_i_3__n.BLIF N_303 +11 1 +.names VPA_D_i.BLIF cpu_est_2_.BLIF N_309_2 +11 1 +.names N_304_1.BLIF cpu_est_i_2__n.BLIF N_304 +11 1 +.names inst_CLK_000_PE.BLIF N_270_i.BLIF N_308_1 +11 1 +.names inst_AS_000_DMA.BLIF RW_000_i.BLIF N_301 +11 1 +.names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF N_308_2 +11 1 +.names inst_CLK_030_H.BLIF CLK_EXP_c.BLIF N_91 +11 1 +.names RESET_OUT_0_sqmuxa_1.BLIF RST_DLY_1_.BLIF RESET_OUT_0_sqmuxa_5_1 +11 1 +.names N_273.BLIF cpu_est_3_reg.BLIF N_85 +11 1 +.names RESET_OUT_0_sqmuxa_5.BLIF RST_DLY_3_.BLIF RESET_OUT_0_sqmuxa_7_1 +11 1 +.names N_273_i.BLIF cpu_est_i_2__n.BLIF N_294 +11 1 +.names RST_DLY_4_.BLIF RST_DLY_5_.BLIF RESET_OUT_0_sqmuxa_7_2 +11 1 +.names N_296_1.BLIF cpu_est_i_2__n.BLIF N_296 +11 1 +.names RESET_OUT_0_sqmuxa_7_1.BLIF RESET_OUT_0_sqmuxa_7_2.BLIF \ +RESET_OUT_0_sqmuxa_7_3 +11 1 +.names inst_CLK_000_PE.BLIF SM_AMIGA_0_.BLIF N_84 +11 1 +.names N_75.BLIF BERR_i.BLIF N_94_1 +11 1 +.names N_82_1.BLIF SM_AMIGA_2_.BLIF N_82 +11 1 +.names N_73.BLIF BERR_i.BLIF N_95_1 +11 1 +.names N_83_1.BLIF SM_AMIGA_3_.BLIF N_83 +11 1 +.names N_86_i.BLIF N_93_i.BLIF N_119_i_1 +11 1 +.names N_136.BLIF sm_amiga_i_4__n.BLIF N_293 +11 1 +.names N_274.BLIF RST_c.BLIF N_82_1 +11 1 +.names N_275.BLIF sm_amiga_i_5__n.BLIF N_290 +11 1 +.names N_313.BLIF RST_c.BLIF N_83_1 +11 1 +.names CLK_000_NE_i.BLIF sm_amiga_i_4__n.BLIF N_291 +11 1 +.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_296_1 +11 1 +.names N_62.BLIF SM_AMIGA_i_7_.BLIF N_283 +11 1 +.names N_270.BLIF cpu_est_0_.BLIF N_303_1 +11 1 +.names N_251.BLIF sm_amiga_i_6__n.BLIF N_284 +11 1 +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_304_1 +11 1 +.names sm_amiga_srsts_i_0_m2_1__un1_n.BLIF sm_amiga_srsts_i_0_m2_1__un0_n.BLIF \ +N_86 +1- 1 +-1 1 +.names N_269_i.BLIF RW_000_c.BLIF N_306_1 +11 1 +.names N_80_0.BLIF N_80 +0 1 +.names N_283_i.BLIF N_284_i.BLIF N_129_i_1 +11 1 +.names N_78_0.BLIF N_78 +0 1 +.names N_290_i.BLIF N_291_i.BLIF N_125_i_1 +11 1 +.names N_80.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_108 +11 1 +.names N_279_i.BLIF N_293_i.BLIF N_123_i_1 +11 1 +.names N_340.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_109 +11 1 +.names N_84_i.BLIF sm_amiga_i_5__n.BLIF N_115_0_1 +11 1 +.names BGACK_030_INT_i.BLIF N_76.BLIF N_100 +11 1 +.names N_296_i.BLIF N_85_i.BLIF pos_clk_cpu_est_11_0_1_3__n +11 1 +.names BGACK_030_INT_i.BLIF N_76_i.BLIF N_99 +11 1 +.names N_91_i.BLIF RW_000_i.BLIF N_260_0_1 +11 1 +.names N_78.BLIF sm_amiga_i_2__n.BLIF N_93 +11 1 +.names N_307_i.BLIF RST_c.BLIF N_261_i_1 +11 1 +.names pos_clk_un14_clk_000_n_sync_0_n.BLIF pos_clk_un14_clk_000_n_sync_n +0 1 +.names pos_clk_CYCLE_DMA_5_1_i_x2.BLIF N_269_i.BLIF N_262_i_1 +11 1 +.names CLK_000_N_SYNC_9_.BLIF pos_clk_un11_clk_000_n_sync_i_n.BLIF \ +pos_clk_un9_clk_000_n_sync_n +11 1 +.names pos_clk_CYCLE_DMA_5_0_i_x2.BLIF N_269_i.BLIF N_263_i_1 +11 1 +.names N_340_4.BLIF N_340_3.BLIF N_340 +11 1 +.names N_226_i.BLIF N_224_i.BLIF pos_clk_ipl_1_n +11 1 +.names BERR_i.BLIF N_136_i.BLIF N_97 +11 1 +.names inst_CLK_000_NE_D0.BLIF cpu_est_0_3__un3_n +0 1 +.names N_136_i.BLIF N_136 +0 1 +.names pos_clk_cpu_est_11_3__n.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_3__un1_n +11 1 +.names N_81.BLIF sm_amiga_i_0__n.BLIF N_101 +11 1 +.names cpu_est_3_reg.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n +11 1 +.names N_81_0.BLIF N_81 +0 1 +.names inst_CLK_000_NE_D0.BLIF cpu_est_0_2__un3_n +0 1 +.names N_268.BLIF SM_AMIGA_0_.BLIF N_116 +11 1 +.names N_186_i.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_2__un1_n +11 1 +.names N_96_3.BLIF sm_amiga_i_3__n.BLIF N_96 +11 1 +.names cpu_est_2_.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n +11 1 +.names BGACK_000_c.BLIF CLK_000_PE_i.BLIF N_113 +11 1 +.names inst_CLK_000_NE_D0.BLIF cpu_est_0_1__un3_n +0 1 +.names N_275_0.BLIF N_275 +0 1 +.names pos_clk_cpu_est_11_1__n.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_1__un1_n +11 1 +.names N_273_i.BLIF N_273 +0 1 +.names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n +11 1 +.names N_272.BLIF cpu_est_i_0__n.BLIF N_88 +11 1 +.names N_113.BLIF bgack_030_int_0_un3_n +0 1 +.names N_272_i.BLIF N_272 +0 1 +.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c +0 1 +.names inst_BGACK_030_INTreg.BLIF N_113.BLIF bgack_030_int_0_un1_n +11 1 +.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_299 +11 1 +.names BGACK_000_c.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un0_n +11 1 +.names N_270_i.BLIF cpu_est_3_reg.BLIF N_90 +11 1 +.names pos_clk_un7_clk_000_pe_n.BLIF vma_int_0_un3_n +0 1 +.names DTACK_D0_i.BLIF inst_VPA_D.BLIF N_311 +11 1 +.names cpu_est_1_.BLIF pos_clk_un7_clk_000_pe_n.BLIF vma_int_0_un1_n +11 1 +.names N_272_i.BLIF cpu_est_0_.BLIF N_312 +11 1 +.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n +11 1 +.names N_267_0.BLIF N_267 +0 1 +.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUTreg.BLIF un1_as_000_i +11 1 +.names N_115.BLIF rw_000_int_0_un3_n +0 1 +.names N_264_0.BLIF N_264 +0 1 +.names un1_rst_dly_i_m_3__n.BLIF un1_rst_dly_i_m_i_3__n +0 1 +.names N_264.BLIF N_115.BLIF rw_000_int_0_un1_n +11 1 +.names pos_clk_un7_clk_000_pe_0_n.BLIF pos_clk_un7_clk_000_pe_n +0 1 +.names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n +11 1 +.names N_308_1.BLIF N_308_2.BLIF N_308 +11 1 +.names un1_rst_dly_i_m_4__n.BLIF un1_rst_dly_i_m_i_4__n +0 1 +.names SM_AMIGA_3_.BLIF sm_amiga_srsts_i_0_m2_3__un3_n +0 1 +.names N_309_1.BLIF N_309_2.BLIF N_309 +11 1 +.names BERR_i.BLIF SM_AMIGA_3_.BLIF sm_amiga_srsts_i_0_m2_3__un1_n +11 1 +.names inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF pos_clk_RST_DLY_5_iv_0_x2_0_ +01 1 +10 1 +11 0 +00 0 +.names RESET_OUT_0_sqmuxa_1.BLIF RST_DLY_1_.BLIF G_137 +01 1 +10 1 +11 0 +00 0 +.names RESET_OUT_0_sqmuxa_7.BLIF RST_DLY_7_.BLIF G_149 +01 1 +10 1 +11 0 +00 0 +.names N_213.BLIF RST_DLY_6_.BLIF G_147 +01 1 +10 1 +11 0 +00 0 +.names N_211.BLIF RST_DLY_5_.BLIF G_145 +01 1 +10 1 +11 0 +00 0 +.names N_209.BLIF RST_DLY_4_.BLIF G_143 +01 1 +10 1 +11 0 +00 0 +.names RESET_OUT_0_sqmuxa_5.BLIF RST_DLY_3_.BLIF G_141 +01 1 +10 1 +11 0 +00 0 +.names N_205.BLIF RST_DLY_2_.BLIF G_139 +01 1 +10 1 +11 0 +00 0 +.names IPL_D0_0_.BLIF ipl_c_0__n.BLIF G_165 +01 1 +10 1 +11 0 +00 0 +.names IPL_D0_1_.BLIF ipl_c_1__n.BLIF G_166 +01 1 +10 1 +11 0 +00 0 +.names IPL_D0_2_.BLIF ipl_c_2__n.BLIF G_167 +01 1 +10 1 +11 0 +00 0 +.names cpu_est_0_.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_0_x2_0_ +01 1 +10 1 +11 0 +00 0 +.names N_220.BLIF CYCLE_DMA_1_.BLIF pos_clk_CYCLE_DMA_5_1_i_x2 +01 1 +10 1 +11 0 +00 0 +.names CYCLE_DMA_0_.BLIF inst_CLK_000_PE.BLIF pos_clk_CYCLE_DMA_5_0_i_x2 +01 1 +10 1 +11 0 +00 0 +.names CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF pos_clk_un24_bgack_030_int_i_0_x2 +01 1 +10 1 +11 0 +00 0 +.names IPL_030DFF_2_reg.BLIF IPL_030_2_ +1 1 +0 0 +.names BG_000DFFreg.BLIF BG_000 +1 1 +0 0 +.names inst_BGACK_030_INTreg.BLIF BGACK_030 +1 1 +0 0 +.names gnd_n_n.BLIF CLK_DIV_OUT +1 1 +0 0 +.names CLK_EXP_c.BLIF CLK_EXP +1 1 +0 0 +.names un21_fpu_cs_i.BLIF FPU_CS +1 1 +0 0 +.names inst_DSACK1_INTreg.BLIF DSACK1 +1 1 +0 0 +.names vcc_n_n.BLIF AVEC +1 1 +0 0 +.names cpu_est_3_reg.BLIF E +1 1 +0 0 +.names inst_VMA_INTreg.BLIF VMA +1 1 +0 0 +.names inst_RESET_OUTreg.BLIF RESET +1 1 +0 0 +.names gnd_n_n.BLIF AMIGA_ADDR_ENABLE +1 1 +0 0 +.names AMIGA_BUS_DATA_DIR_c.BLIF AMIGA_BUS_DATA_DIR +1 1 +0 0 +.names un1_amiga_bus_enable_low_i.BLIF AMIGA_BUS_ENABLE_LOW +1 1 +0 0 +.names N_71_i.BLIF AMIGA_BUS_ENABLE_HIGH +1 1 +0 0 +.names un5_ciin.BLIF CIIN +1 1 +0 0 +.names IPL_030DFF_1_reg.BLIF IPL_030_1_ +1 1 +0 0 +.names IPL_030DFF_0_reg.BLIF IPL_030_0_ +1 1 +0 0 +.names CLK_OSZI_c.BLIF IPL_030DFF_2_reg.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF IPL_D0_0_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF IPL_D0_1_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF IPL_D0_2_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_i_7_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C +1 1 +0 0 +.names cpu_est_0_0_x2_0_.BLIF cpu_est_0_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF cpu_est_0_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF cpu_est_1_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF cpu_est_2_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF cpu_est_3_reg.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF IPL_030DFF_0_reg.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF IPL_030DFF_1_reg.C +1 1 +0 0 +.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_9_.C +1 1 +0 0 +.names CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_10_.C +1 1 +0 0 +.names CLK_000_N_SYNC_10_.BLIF CLK_000_N_SYNC_11_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_11_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF RST_DLY_0_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF RST_DLY_1_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF RST_DLY_2_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF RST_DLY_3_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF RST_DLY_4_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF RST_DLY_5_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF RST_DLY_6_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF RST_DLY_7_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF CYCLE_DMA_0_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF CYCLE_DMA_1_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF SIZE_DMA_0_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C +1 1 +0 0 +.names CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_5_.C +1 1 +0 0 +.names CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_6_.C +1 1 +0 0 +.names CLK_000_P_SYNC_6_.BLIF CLK_000_P_SYNC_7_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_7_.C +1 1 +0 0 +.names CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_8_.C +1 1 +0 0 +.names CLK_000_P_SYNC_8_.BLIF CLK_000_P_SYNC_9_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_9_.C +1 1 +0 0 +.names N_249_i.BLIF CLK_000_N_SYNC_0_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_0_.C +1 1 +0 0 +.names CLK_000_N_SYNC_0_.BLIF CLK_000_N_SYNC_1_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_1_.C +1 1 +0 0 +.names CLK_000_N_SYNC_1_.BLIF CLK_000_N_SYNC_2_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_2_.C +1 1 +0 0 +.names CLK_000_N_SYNC_2_.BLIF CLK_000_N_SYNC_3_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_3_.C +1 1 +0 0 +.names CLK_000_N_SYNC_3_.BLIF CLK_000_N_SYNC_4_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_4_.C +1 1 +0 0 +.names CLK_000_N_SYNC_4_.BLIF CLK_000_N_SYNC_5_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_5_.C +1 1 +0 0 +.names CLK_000_N_SYNC_5_.BLIF CLK_000_N_SYNC_6_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_6_.C +1 1 +0 0 +.names CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_7_.C +1 1 +0 0 +.names CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_8_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_0_.C +1 1 +0 0 +.names CLK_000_P_SYNC_0_.BLIF CLK_000_P_SYNC_1_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_1_.C +1 1 +0 0 +.names CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_2_.C +1 1 +0 0 +.names CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_3_.C +1 1 +0 0 +.names CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_4_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_CLK_030_H.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_RESET_OUTreg.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_RW_000_DMA.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_RW_000_INT.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AS_000_INT.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_DSACK1_INTreg.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_A0_DMA.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_DS_000_DMA.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_DS_030_D0.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AS_030_D0.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_nEXP_SPACE_D0reg.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_VPA_D.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_DTACK_D0.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF BG_000DFFreg.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C +1 1 +0 0 +.names CLK_000_P_SYNC_9_.BLIF inst_CLK_000_PE.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_CLK_000_PE.C +1 1 +0 0 +.names CLK_000_N_SYNC_11_.BLIF inst_CLK_000_NE.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_CLK_000_NE.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C +1 1 +0 0 +.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_CLK_000_D1.C +1 1 +0 0 +.names inst_CLK_000_NE.BLIF inst_CLK_000_NE_D0.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_CLK_000_NE_D0.C +1 1 +0 0 +.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_D.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_D.C +1 1 +0 0 +.names CLK_000.BLIF inst_CLK_000_D0.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_CLK_000_D0.C +1 1 +0 0 +.names un3_size.BLIF SIZE_1_ +1 1 +0 0 +.names un6_as_030_i.BLIF AS_030 +1 1 +0 0 +.names un4_as_000_i.BLIF AS_000 +1 1 +0 0 +.names inst_RW_000_INT.BLIF RW_000 +1 1 +0 0 +.names un6_ds_030_i.BLIF DS_030 +1 1 +0 0 +.names un6_uds_000_i.BLIF UDS_000 +1 1 +0 0 +.names un6_lds_000_i.BLIF LDS_000 +1 1 +0 0 +.names inst_A0_DMA.BLIF A0 +1 1 +0 0 +.names gnd_n_n.BLIF BERR +1 1 +0 0 +.names inst_RW_000_DMA.BLIF RW +1 1 +0 0 +.names un4_size.BLIF SIZE_0_ +1 1 +0 0 +.names A_15_.BLIF a_15__n +1 1 +0 0 +.names A_14_.BLIF a_14__n +1 1 +0 0 +.names A_13_.BLIF a_13__n +1 1 +0 0 +.names A_12_.BLIF a_12__n +1 1 +0 0 +.names A_11_.BLIF a_11__n +1 1 +0 0 +.names A_10_.BLIF a_10__n +1 1 +0 0 +.names A_9_.BLIF a_9__n +1 1 +0 0 +.names A_8_.BLIF a_8__n +1 1 +0 0 +.names A_7_.BLIF a_7__n +1 1 +0 0 +.names A_6_.BLIF a_6__n +1 1 +0 0 +.names A_5_.BLIF a_5__n +1 1 +0 0 +.names A_4_.BLIF a_4__n +1 1 +0 0 +.names A_3_.BLIF a_3__n +1 1 +0 0 +.names A_2_.BLIF a_2__n +1 1 +0 0 +.names AS_030.PIN.BLIF AS_030_c +1 1 +0 0 +.names AS_000.PIN.BLIF AS_000_c +1 1 +0 0 +.names RW_000.PIN.BLIF RW_000_c +1 1 +0 0 +.names DS_030.PIN.BLIF DS_030_c +1 1 +0 0 +.names UDS_000.PIN.BLIF UDS_000_c +1 1 +0 0 +.names LDS_000.PIN.BLIF LDS_000_c +1 1 +0 0 +.names SIZE_0_.PIN.BLIF size_c_0__n +1 1 +0 0 +.names SIZE_1_.PIN.BLIF size_c_1__n +1 1 +0 0 +.names A_16_.BLIF a_c_16__n +1 1 +0 0 +.names A_17_.BLIF a_c_17__n +1 1 +0 0 +.names A_18_.BLIF a_c_18__n +1 1 +0 0 +.names A_19_.BLIF a_c_19__n +1 1 +0 0 +.names A_20_.BLIF a_c_20__n +1 1 +0 0 +.names A_21_.BLIF a_c_21__n +1 1 +0 0 +.names A_22_.BLIF a_c_22__n +1 1 +0 0 +.names A_23_.BLIF a_c_23__n +1 1 +0 0 +.names A_24_.BLIF a_c_24__n +1 1 +0 0 +.names A_25_.BLIF a_c_25__n +1 1 +0 0 +.names A_26_.BLIF a_c_26__n +1 1 +0 0 +.names A_27_.BLIF a_c_27__n +1 1 +0 0 +.names A_28_.BLIF a_c_28__n +1 1 +0 0 +.names A_29_.BLIF a_c_29__n +1 1 +0 0 +.names A_30_.BLIF a_c_30__n +1 1 +0 0 +.names A_31_.BLIF a_c_31__n +1 1 +0 0 +.names A0.PIN.BLIF A0_c +1 1 +0 0 +.names A1.BLIF A1_c +1 1 +0 0 +.names nEXP_SPACE.BLIF nEXP_SPACE_c +1 1 +0 0 +.names BERR.PIN.BLIF BERR_c +1 1 +0 0 +.names BG_030.BLIF BG_030_c +1 1 +0 0 +.names BGACK_000.BLIF BGACK_000_c +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_OSZI_c +1 1 +0 0 +.names CLK_030.BLIF CLK_EXP_c +1 1 +0 0 +.names FPU_SENSE.BLIF FPU_SENSE_c +1 1 +0 0 +.names IPL_0_.BLIF ipl_c_0__n +1 1 +0 0 +.names IPL_1_.BLIF ipl_c_1__n +1 1 +0 0 +.names IPL_2_.BLIF ipl_c_2__n +1 1 +0 0 +.names DTACK.BLIF DTACK_c +1 1 +0 0 +.names VPA.BLIF VPA_c +1 1 +0 0 +.names RST.BLIF RST_c +1 1 +0 0 +.names RW.PIN.BLIF RW_c +1 1 +0 0 +.names FC_0_.BLIF fc_c_0__n +1 1 +0 0 +.names FC_1_.BLIF fc_c_1__n +1 1 +0 0 +.names N_112.BLIF AS_030.OE +1 1 +0 0 +.names un1_as_000_i.BLIF AS_000.OE +1 1 +0 0 +.names un1_as_000_i.BLIF RW_000.OE +1 1 +0 0 +.names N_112.BLIF DS_030.OE +1 1 +0 0 +.names un1_as_000_i.BLIF UDS_000.OE +1 1 +0 0 +.names un1_as_000_i.BLIF LDS_000.OE +1 1 +0 0 +.names N_89.BLIF SIZE_0_.OE +1 1 +0 0 +.names N_89.BLIF SIZE_1_.OE +1 1 +0 0 +.names N_112.BLIF A0.OE +1 1 +0 0 +.names un22_berr.BLIF BERR.OE +1 1 +0 0 +.names N_256.BLIF RW.OE +1 1 +0 0 +.names gnd_n_n.BLIF CLK_DIV_OUT.OE +1 1 +0 0 +.names inst_nEXP_SPACE_D0reg.BLIF DSACK1.OE +1 1 +0 0 +.names N_247.BLIF CIIN.OE +1 1 +0 0 +.end diff --git a/Logic/68030_tk.bl3 b/Logic/68030_tk.bl3 new file mode 100644 index 0000000..e7d2be1 --- /dev/null +++ b/Logic/68030_tk.bl3 @@ -0,0 +1,1375 @@ +#$ TOOL ispLEVER Classic 1.8.00.04.29.14 +#$ DATE Wed May 13 22:59:21 2015 +#$ MODULE 68030_tk +#$ PINS 61 A_28_ A_27_ SIZE_1_ A_26_ A_25_ A_31_ A_24_ A_23_ IPL_030_2_ A_22_ A_21_ \ +# IPL_2_ A_20_ A_19_ FC_1_ A_18_ AS_030 A_17_ AS_000 A_16_ RW_000 DS_030 UDS_000 LDS_000 A0 A1 \ +# nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI IPL_030_1_ \ +# CLK_DIV_OUT IPL_030_0_ CLK_EXP IPL_1_ FPU_CS IPL_0_ FPU_SENSE FC_0_ DSACK1 DTACK AVEC E \ +# VPA VMA RST RESET RW AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ +# AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ A_30_ A_29_ +#$ NODES 84 inst_BGACK_030_INTreg cpu_est_3_reg inst_VMA_INTreg inst_RESET_OUTreg \ +# cpu_est_0_ cpu_est_1_ inst_AS_000_INT SM_AMIGA_5_ inst_AMIGA_BUS_ENABLE_DMA_LOW \ +# inst_AS_030_D0 inst_nEXP_SPACE_D0reg inst_DS_030_D0 inst_AS_030_000_SYNC \ +# inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ \ +# SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT \ +# inst_CLK_OUT_PRE_D inst_DTACK_D0 inst_CLK_OUT_PRE_50 inst_CLK_000_D1 \ +# inst_CLK_000_D0 inst_CLK_000_PE CLK_000_P_SYNC_9_ inst_CLK_000_NE N_96_i \ +# CLK_000_N_SYNC_11_ cpu_est_2_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ SM_AMIGA_3_ \ +# inst_CLK_000_NE_D0 SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_DSACK1_INTreg \ +# SM_AMIGA_6_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ RST_DLY_3_ RST_DLY_4_ RST_DLY_5_ \ +# RST_DLY_6_ RST_DLY_7_ CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ \ +# CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ \ +# CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ \ +# CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ \ +# CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ \ +# CLK_000_N_SYNC_10_ inst_RW_000_INT inst_RW_000_DMA inst_A0_DMA inst_CLK_030_H \ +# SM_AMIGA_1_ SM_AMIGA_4_ SM_AMIGA_2_ inst_DS_000_ENABLE SM_AMIGA_i_7_ BG_000DFFreg \ +# IPL_030DFF_0_reg IPL_030DFF_1_reg IPL_030DFF_2_reg +.model bus68030 +.inputs A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF A1.BLIF nEXP_SPACE.BLIF BG_030.BLIF \ +BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF FPU_SENSE.BLIF \ +DTACK.BLIF VPA.BLIF RST.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF \ +A_26_.BLIF A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF \ +A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF \ +inst_BGACK_030_INTreg.BLIF cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF \ +inst_RESET_OUTreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_AS_000_INT.BLIF \ +SM_AMIGA_5_.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF inst_AS_030_D0.BLIF \ +inst_nEXP_SPACE_D0reg.BLIF inst_DS_030_D0.BLIF inst_AS_030_000_SYNC.BLIF \ +inst_BGACK_030_INT_D.BLIF inst_AS_000_DMA.BLIF inst_DS_000_DMA.BLIF \ +CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF \ +inst_VPA_D.BLIF inst_UDS_000_INT.BLIF inst_LDS_000_INT.BLIF \ +inst_CLK_OUT_PRE_D.BLIF inst_DTACK_D0.BLIF inst_CLK_OUT_PRE_50.BLIF \ +inst_CLK_000_D1.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_PE.BLIF \ +CLK_000_P_SYNC_9_.BLIF inst_CLK_000_NE.BLIF N_96_i.BLIF \ +CLK_000_N_SYNC_11_.BLIF cpu_est_2_.BLIF IPL_D0_0_.BLIF IPL_D0_1_.BLIF \ +IPL_D0_2_.BLIF SM_AMIGA_3_.BLIF inst_CLK_000_NE_D0.BLIF SM_AMIGA_0_.BLIF \ +inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF inst_DSACK1_INTreg.BLIF SM_AMIGA_6_.BLIF \ +RST_DLY_0_.BLIF RST_DLY_1_.BLIF RST_DLY_2_.BLIF RST_DLY_3_.BLIF \ +RST_DLY_4_.BLIF RST_DLY_5_.BLIF RST_DLY_6_.BLIF RST_DLY_7_.BLIF \ +CLK_000_P_SYNC_0_.BLIF CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.BLIF \ +CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.BLIF \ +CLK_000_P_SYNC_6_.BLIF CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.BLIF \ +CLK_000_N_SYNC_0_.BLIF CLK_000_N_SYNC_1_.BLIF CLK_000_N_SYNC_2_.BLIF \ +CLK_000_N_SYNC_3_.BLIF CLK_000_N_SYNC_4_.BLIF CLK_000_N_SYNC_5_.BLIF \ +CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.BLIF \ +CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.BLIF inst_RW_000_INT.BLIF \ +inst_RW_000_DMA.BLIF inst_A0_DMA.BLIF inst_CLK_030_H.BLIF SM_AMIGA_1_.BLIF \ +SM_AMIGA_4_.BLIF SM_AMIGA_2_.BLIF inst_DS_000_ENABLE.BLIF SM_AMIGA_i_7_.BLIF \ +BG_000DFFreg.BLIF IPL_030DFF_0_reg.BLIF IPL_030DFF_1_reg.BLIF \ +IPL_030DFF_2_reg.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF \ +DS_030.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF \ +SIZE_1_.PIN.BLIF A0.PIN.BLIF BERR.PIN.BLIF RW.PIN.BLIF +.outputs IPL_030_2_ BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 AVEC E \ +VMA RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ +AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ IPL_030DFF_2_reg.D \ +IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D \ +IPL_D0_2_.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C \ +SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.C \ +SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D \ +SM_AMIGA_0_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D \ +cpu_est_2_.C cpu_est_3_reg.C IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C \ +IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C \ +CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.D \ +CLK_000_N_SYNC_11_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C \ +RST_DLY_2_.D RST_DLY_2_.C RST_DLY_3_.D RST_DLY_3_.C RST_DLY_4_.C RST_DLY_5_.C \ +RST_DLY_6_.C RST_DLY_7_.D RST_DLY_7_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C \ +CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D \ +SIZE_DMA_1_.C CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D \ +CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C \ +CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.D \ +CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C \ +CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.D \ +CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C \ +CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.D \ +CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_6_.C \ +CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.D \ +CLK_000_N_SYNC_8_.C CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C \ +CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.D \ +CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C \ +CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C inst_CLK_030_H.C inst_RESET_OUTreg.D \ +inst_RESET_OUTreg.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C \ +inst_UDS_000_INT.D inst_UDS_000_INT.C inst_RW_000_DMA.D inst_RW_000_DMA.C \ +inst_RW_000_INT.D inst_RW_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C \ +inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_000_INT.D \ +inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C inst_A0_DMA.D \ +inst_A0_DMA.C inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D \ +inst_DS_000_DMA.C inst_DS_030_D0.D inst_DS_030_D0.C inst_AS_030_D0.D \ +inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.D inst_nEXP_SPACE_D0reg.C inst_VPA_D.D \ +inst_VPA_D.C inst_DTACK_D0.D inst_DTACK_D0.C inst_BGACK_030_INTreg.D \ +inst_BGACK_030_INTreg.C BG_000DFFreg.D BG_000DFFreg.C \ +inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.C \ +inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AMIGA_BUS_ENABLE_DMA_LOW.C \ +inst_VMA_INTreg.D inst_VMA_INTreg.C inst_BGACK_030_INT_D.D \ +inst_BGACK_030_INT_D.C inst_CLK_000_PE.D inst_CLK_000_PE.C inst_CLK_000_NE.D \ +inst_CLK_000_NE.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C \ +inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C \ +inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C inst_CLK_000_D0.D inst_CLK_000_D0.C \ +SIZE_1_ AS_030 AS_000 RW_000 DS_030 UDS_000 LDS_000 A0 BERR RW SIZE_0_ N_96_i \ +AS_030.OE AS_000.OE RW_000.OE DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE \ +SIZE_1_.OE A0.OE BERR.OE RW.OE CLK_DIV_OUT.OE DSACK1.OE CIIN.OE \ +cpu_est_3_reg.D.X1 cpu_est_3_reg.D.X2 SM_AMIGA_3_.D.X1 SM_AMIGA_3_.D.X2 \ +RST_DLY_4_.D.X1 RST_DLY_4_.D.X2 RST_DLY_5_.D.X1 RST_DLY_5_.D.X2 \ +RST_DLY_6_.D.X1 RST_DLY_6_.D.X2 inst_CLK_030_H.D.X1 inst_CLK_030_H.D.X2 +.names IPL_2_.BLIF RST.BLIF IPL_1_.BLIF IPL_0_.BLIF IPL_D0_0_.BLIF \ +IPL_D0_1_.BLIF IPL_D0_2_.BLIF IPL_030DFF_2_reg.BLIF IPL_030DFF_2_reg.D +1-00001- 1 +1-01101- 1 +1-10011- 1 +1-11111- 1 +1------1 1 +------11 1 +--1--0-1 1 +--0--1-1 1 +---10--1 1 +---01--1 1 +-0------ 1 +0100000- 0 +0101100- 0 +0110010- 0 +0111110- 0 +-11--0-0 0 +-10--1-0 0 +-1-10--0 0 +-1-01--0 0 +-1----00 0 +01-----0 0 +.names RST.BLIF IPL_0_.BLIF IPL_D0_0_.D +0- 1 +-1 1 +10 0 +.names RST.BLIF IPL_1_.BLIF IPL_D0_1_.D +0- 1 +-1 1 +10 0 +.names IPL_2_.BLIF RST.BLIF IPL_D0_2_.D +1- 1 +-0 1 +01 0 +.names RST.BLIF cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF \ +cpu_est_1_.BLIF SM_AMIGA_5_.BLIF inst_VPA_D.BLIF inst_DTACK_D0.BLIF \ +inst_CLK_000_PE.BLIF inst_CLK_000_NE.BLIF N_96_i.BLIF cpu_est_2_.BLIF \ +SM_AMIGA_3_.BLIF inst_CLK_000_NE_D0.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_6_.BLIF \ +SM_AMIGA_1_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_2_.BLIF BERR.PIN.BLIF \ +SM_AMIGA_i_7_.D +1100000---11-100000- 1 +11000-0--111-100-00- 1 +1100000-1-11-10-0--- 1 +11000-0-1111-10----- 1 +1----010--1--100000- 1 +1-----10-11--100-00- 1 +1----0----1-0-00000- 1 +1----0101-1--10-0--- 1 +1--------11-0-00-00- 1 +1-----10111--10----- 1 +1----0--1-1-0-0-0--- 1 +1-------111-0-0----- 1 +1-------0-1--------1 1 +1---------1---0----1 1 +------11----1------0 0 +--------1-----1----- 0 +------0----01------0 0 +----1-0-----1------0 0 +---1--0-----1------0 0 +--1---0-----1------0 0 +-0----0-----1------0 0 +---------0------1--0 0 +-----1---0---------0 0 +--------0---------10 0 +--------0--------1-0 0 +--------0------1---0 0 +------------10-----0 0 +----------0--------- 0 +0------------------- 0 +--------------1----0 0 +.names RST.BLIF inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_000_SYNC.BLIF \ +inst_CLK_000_D1.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_PE.BLIF \ +SM_AMIGA_6_.BLIF SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF SM_AMIGA_6_.D +11010--0- 1 +1----01-1 1 +1-----10- 1 +-----1-1- 0 +----1-0-- 0 +---0--0-- 0 +--1---0-- 0 +-0----0-- 0 +------01- 0 +0-------- 0 +-------10 0 +.names RST.BLIF SM_AMIGA_5_.BLIF inst_CLK_000_PE.BLIF inst_CLK_000_NE.BLIF \ +SM_AMIGA_6_.BLIF BERR.PIN.BLIF SM_AMIGA_5_.D +101-1- 1 +11-0-1 1 +11--11 1 +---10- 0 +-00--- 0 +-0--0- 0 +-1---0 0 +0----- 0 +.names RST.BLIF SM_AMIGA_5_.BLIF inst_CLK_000_PE.BLIF inst_CLK_000_NE.BLIF \ +SM_AMIGA_4_.BLIF BERR.PIN.BLIF SM_AMIGA_4_.D +1-0-11 1 +11-1-- 1 +11--1- 1 +---00- 0 +-01--- 0 +-0--0- 0 +0----- 0 +-0---0 0 +.names RST.BLIF cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF \ +cpu_est_1_.BLIF inst_VPA_D.BLIF inst_DTACK_D0.BLIF inst_CLK_000_PE.BLIF \ +cpu_est_2_.BLIF SM_AMIGA_3_.BLIF inst_CLK_000_NE_D0.BLIF SM_AMIGA_2_.BLIF \ +BERR.PIN.BLIF SM_AMIGA_2_.D +110000--111-- 1 +1----10--11-- 1 +1------0---11 1 +1--------1-1- 1 +-----11----0- 0 +-------1-0--- 0 +-----0--0--0- 0 +----10-----0- 0 +---1-0-----0- 0 +--1--0-----0- 0 +-0---0-----0- 0 +----------00- 0 +---------0-0- 0 +0------------ 0 +---------0--0 0 +.names RST.BLIF inst_CLK_000_PE.BLIF inst_CLK_000_NE.BLIF SM_AMIGA_1_.BLIF \ +SM_AMIGA_2_.BLIF BERR.PIN.BLIF SM_AMIGA_1_.D +11-01- 1 +1-01-1 1 +1--111 1 +--1-0- 0 +-0-0-- 0 +---00- 0 +---1-0 0 +0----- 0 +.names RST.BLIF inst_CLK_000_PE.BLIF inst_CLK_000_NE.BLIF SM_AMIGA_0_.BLIF \ +SM_AMIGA_1_.BLIF BERR.PIN.BLIF SM_AMIGA_0_.D +1-101- 1 +10-1-1 1 +-1-1-- 0 +---00- 0 +--00-- 0 +---1-0 0 +0----- 0 +.names cpu_est_3_reg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF \ +inst_CLK_000_NE_D0.BLIF cpu_est_1_.D +0--01 1 +010-1 1 +1-11- 1 +10--1 1 +--1-0 1 +-01-- 1 +0001- 0 +01111 0 +11-01 0 +110-- 0 +--0-0 0 +.names cpu_est_3_reg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF \ +inst_CLK_000_NE_D0.BLIF cpu_est_2_.D +-00-1 1 +11--1 1 +--11- 1 +---10 1 +0-10- 0 +-010- 0 +010-1 0 +---00 0 +.names IPL_2_.BLIF RST.BLIF IPL_1_.BLIF IPL_0_.BLIF IPL_D0_0_.BLIF \ +IPL_D0_1_.BLIF IPL_D0_2_.BLIF IPL_030DFF_0_reg.BLIF IPL_030DFF_0_reg.D +0-01100- 1 +0-11110- 1 +1-01101- 1 +1-11111- 1 +1-----01 1 +0-----11 1 +--1--0-1 1 +--0--1-1 1 +---1---1 1 +----1--1 1 +-0------ 1 +0100000- 0 +0110010- 0 +1100001- 0 +1110011- 0 +11----00 0 +01----10 0 +-11--0-0 0 +-10--1-0 0 +-1--0--0 0 +-1-0---0 0 +.names IPL_2_.BLIF RST.BLIF IPL_1_.BLIF IPL_0_.BLIF IPL_D0_0_.BLIF \ +IPL_D0_1_.BLIF IPL_D0_2_.BLIF IPL_030DFF_1_reg.BLIF IPL_030DFF_1_reg.D +0-10010- 1 +0-11110- 1 +1-10011- 1 +1-11111- 1 +1-----01 1 +0-----11 1 +--1----1 1 +-----1-1 1 +---10--1 1 +---01--1 1 +-0------ 1 +0100000- 0 +0101100- 0 +1100001- 0 +1101101- 0 +11----00 0 +01----10 0 +-1-10--0 0 +-1-01--0 0 +-1---0-0 0 +-10----0 0 +.names RST.BLIF inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF \ +RST_DLY_2_.BLIF RST_DLY_3_.BLIF RST_DLY_4_.BLIF RST_DLY_5_.BLIF \ +RST_DLY_6_.BLIF RST_DLY_7_.BLIF RST_DLY_0_.D +1-11111111 1 +110------- 1 +101------- 1 +-00------- 0 +-11-----0- 0 +-11----0-- 0 +-11---0--- 0 +-11--0---- 0 +-11-0----- 0 +-110------ 0 +0--------- 0 +-11------0 0 +.names RST.BLIF inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF \ +RST_DLY_2_.BLIF RST_DLY_3_.BLIF RST_DLY_4_.BLIF RST_DLY_5_.BLIF \ +RST_DLY_6_.BLIF RST_DLY_7_.BLIF RST_DLY_1_.D +1--1111111 1 +1110------ 1 +1-01------ 1 +10-1------ 1 +-111----0- 0 +-111---0-- 0 +-111--0--- 0 +-111-0---- 0 +-1110----- 0 +--00------ 0 +-0-0------ 0 +-111-----0 0 +0--------- 0 +.names RST.BLIF inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF \ +RST_DLY_2_.BLIF RST_DLY_3_.BLIF RST_DLY_4_.BLIF RST_DLY_5_.BLIF \ +RST_DLY_6_.BLIF RST_DLY_7_.BLIF RST_DLY_2_.D +1---111111 1 +11110----- 1 +1--01----- 1 +1-0-1----- 1 +10--1----- 1 +-1111---0- 0 +-1111--0-- 0 +-1111-0--- 0 +-11110---- 0 +-1111----0 0 +---00----- 0 +--0-0----- 0 +-0--0----- 0 +0--------- 0 +.names RST.BLIF inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF \ +RST_DLY_2_.BLIF RST_DLY_3_.BLIF RST_DLY_4_.BLIF RST_DLY_5_.BLIF \ +RST_DLY_6_.BLIF RST_DLY_7_.BLIF RST_DLY_3_.D +1----11111 1 +111110---- 1 +1---01---- 1 +1--0-1---- 1 +1-0--1---- 1 +10---1---- 1 +-11111--0- 0 +-11111-0-- 0 +-111110--- 0 +-11111---0 0 +----00---- 0 +---0-0---- 0 +--0--0---- 0 +-0---0---- 0 +0--------- 0 +.names RST.BLIF inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF \ +RST_DLY_2_.BLIF RST_DLY_3_.BLIF RST_DLY_4_.BLIF RST_DLY_5_.BLIF \ +RST_DLY_6_.BLIF RST_DLY_7_.BLIF RST_DLY_7_.D +111111111- 1 +1--------1 1 +0--------- 0 +--------00 0 +-------0-0 0 +------0--0 0 +-----0---0 0 +----0----0 0 +---0-----0 0 +--0------0 0 +-0-------0 0 +.names RST.BLIF inst_BGACK_030_INTreg.BLIF CYCLE_DMA_0_.BLIF \ +inst_CLK_000_PE.BLIF AS_000.PIN.BLIF CYCLE_DMA_0_.D +10100 1 +10010 1 +--00- 0 +--11- 0 +-1--- 0 +0---- 0 +----1 0 +.names RST.BLIF inst_BGACK_030_INTreg.BLIF CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF \ +inst_CLK_000_PE.BLIF AS_000.PIN.BLIF CYCLE_DMA_1_.D +101010 1 +10-100 1 +1001-0 1 +--111- 0 +---00- 0 +--00-- 0 +-1---- 0 +0----- 0 +-----1 0 +.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ +SIZE_DMA_0_.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_DMA_0_.D +-111-- 1 +-0--1- 1 +0----- 1 +-0---1 1 +10--00 0 +11-0-- 0 +110--- 0 +.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ +SIZE_DMA_1_.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_DMA_1_.D +-111-- 1 +-0--00 1 +0----- 1 +10--1- 0 +11-0-- 0 +110--- 0 +10---1 0 +.names inst_CLK_000_D1.BLIF inst_CLK_000_D0.BLIF CLK_000_P_SYNC_0_.D +01 1 +1- 0 +-0 0 +.names RST.BLIF inst_RESET_OUTreg.BLIF inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF \ +RST_DLY_1_.BLIF RST_DLY_2_.BLIF RST_DLY_3_.BLIF RST_DLY_4_.BLIF \ +RST_DLY_5_.BLIF RST_DLY_6_.BLIF RST_DLY_7_.BLIF inst_RESET_OUTreg.D +1-111111111 1 +11--------- 1 +0---------- 0 +-0-------0- 0 +-0------0-- 0 +-0-----0--- 0 +-0----0---- 0 +-0---0----- 0 +-0--0------ 0 +-0-0------- 0 +-00-------- 0 +-0--------0 0 +.names RST.BLIF SM_AMIGA_5_.BLIF inst_AS_030_D0.BLIF SM_AMIGA_3_.BLIF \ +inst_DS_000_ENABLE.BLIF BERR.PIN.BLIF RW.PIN.BLIF inst_DS_000_ENABLE.D +1-0-11- 1 +10-1--- 1 +11----1 1 +-0-0-0- 0 +-0-00-- 0 +-010--- 0 +-1---00 0 +-1--0-0 0 +-11---0 0 +0------ 0 +.names RST.BLIF inst_DS_030_D0.BLIF inst_UDS_000_INT.BLIF SM_AMIGA_6_.BLIF \ +A0.PIN.BLIF inst_UDS_000_INT.D +-0-11 1 +--10- 1 +-11-- 1 +0---- 1 +10-10 0 +1-00- 0 +110-- 0 +.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ +inst_RW_000_DMA.BLIF RW_000.PIN.BLIF inst_RW_000_DMA.D +-1-1- 1 +-10-- 1 +0---- 1 +-0--1 1 +1110- 0 +10--0 0 +.names RST.BLIF SM_AMIGA_5_.BLIF inst_CLK_000_PE.BLIF SM_AMIGA_0_.BLIF \ +inst_RW_000_INT.BLIF SM_AMIGA_i_7_.BLIF RW.PIN.BLIF inst_RW_000_INT.D +-0--1-- 1 +-011--- 1 +-0---0- 1 +0------ 1 +-1----1 1 +10-001- 0 +100-01- 0 +11----0 0 +.names RST.BLIF inst_DS_030_D0.BLIF inst_LDS_000_INT.BLIF SM_AMIGA_6_.BLIF \ +SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF A0.PIN.BLIF inst_LDS_000_INT.D +-0-1100 1 +--10--- 1 +-11---- 1 +0------ 1 +10-1-1- 0 +10-10-- 0 +10-1--1 0 +1-00--- 0 +110---- 0 +.names FC_1_.BLIF RST.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF \ +FC_0_.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_030_D0.BLIF \ +inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INT_D.BLIF \ +SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF inst_AS_030_000_SYNC.D +1-00101---1--- 1 +----------1-1- 1 +----------10-- 1 +---------01--- 1 +-------0--1--- 1 +--------1----- 1 +-0------------ 1 +-------------0 1 +-1----0101-101 0 +-1---1-101-101 0 +-1--0--101-101 0 +-1-1---101-101 0 +-11----101-101 0 +01-----101-101 0 +-1------0-0--1 0 +.names RST.BLIF inst_AS_000_INT.BLIF SM_AMIGA_5_.BLIF inst_AS_030_D0.BLIF \ +BERR.PIN.BLIF inst_AS_000_INT.D +-10-- 1 +--01- 1 +0---- 1 +--0-0 1 +10-01 0 +1-1-- 0 +.names CLK_030.BLIF RST.BLIF inst_AS_030_D0.BLIF inst_CLK_OUT_PRE_D.BLIF \ +inst_DSACK1_INTreg.BLIF CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.BLIF \ +SM_AMIGA_1_.BLIF BERR.PIN.BLIF inst_DSACK1_INTreg.D +1--01-0-- 1 +----100-- 1 +1-10--0-- 1 +1--0--0-0 1 +----1--0- 1 +--1--00-- 1 +-----00-0 1 +--1----0- 1 +-0------- 1 +-------00 1 +-10-0---1 0 +-1-1-1-1- 0 +01---1-1- 0 +-1----11- 0 +.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ +inst_A0_DMA.BLIF UDS_000.PIN.BLIF inst_A0_DMA.D +-111- 1 +0---- 1 +-0--1 1 +11-0- 0 +110-- 0 +10--0 0 +.names CLK_030.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \ +CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF AS_000.PIN.BLIF UDS_000.PIN.BLIF \ +LDS_000.PIN.BLIF inst_AS_000_DMA.D +----00--- 1 +----11--- 1 +0--1----- 1 +------1-- 1 +--1------ 1 +-0------- 1 +-------11 1 +-1001000- 0 +110-1000- 0 +-1000100- 0 +110-0100- 0 +-100100-0 0 +110-100-0 0 +-100010-0 0 +110-010-0 0 +.names CLK_030.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \ +inst_DS_000_DMA.BLIF CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF inst_CLK_030_H.BLIF \ +AS_000.PIN.BLIF RW_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF \ +inst_DS_000_DMA.D +1--1---1-0-- 1 +----1--0-0-- 1 +0---1----0-- 1 +-----00----- 1 +-----11----- 1 +--------1--- 1 +--1--------- 1 +-0---------- 1 +----------11 1 +1100-1010-0- 0 +1100-0110-0- 0 +1100-1010--0 0 +1100-0110--0 0 +-10-01000-0- 0 +-10-00100-0- 0 +010-010-0-0- 0 +010-001-0-0- 0 +-10-01000--0 0 +-10-00100--0 0 +010-010-0--0 0 +010-001-0--0 0 +-10--10-010- 0 +-10--01-010- 0 +-10--10-01-0 0 +-10--01-01-0 0 +.names RST.BLIF DS_030.PIN.BLIF inst_DS_030_D0.D +0- 1 +-1 1 +10 0 +.names RST.BLIF AS_030.PIN.BLIF inst_AS_030_D0.D +0- 1 +-1 1 +10 0 +.names nEXP_SPACE.BLIF RST.BLIF inst_nEXP_SPACE_D0reg.D +1- 1 +-0 1 +01 0 +.names VPA.BLIF RST.BLIF inst_VPA_D.D +1- 1 +-0 1 +01 0 +.names DTACK.BLIF RST.BLIF inst_DTACK_D0.D +1- 1 +-0 1 +01 0 +.names BGACK_000.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_CLK_000_PE.BLIF \ +inst_BGACK_030_INTreg.D +1-1- 1 +-0-- 1 +1--1 1 +-100 0 +01-- 0 +.names BG_030.BLIF RST.BLIF inst_AS_030_D0.BLIF inst_nEXP_SPACE_D0reg.BLIF \ +inst_CLK_000_D0.BLIF BG_000DFFreg.BLIF BG_000DFFreg.D +----01 1 +---0-1 1 +--0--1 1 +-0---- 1 +1----- 1 +01111- 0 +01---0 0 +.names A1.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ +inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D +--1-1 1 +1-0-- 1 +--10- 1 +-0--- 1 +-1110 0 +010-- 0 +.names A1.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF \ +inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF inst_BGACK_030_INT_D.BLIF \ +inst_AMIGA_BUS_ENABLE_DMA_LOW.D +--11- 1 +0-0-- 1 +--1-0 1 +-0--- 1 +-1101 0 +110-- 0 +.names RST.BLIF cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF \ +cpu_est_1_.BLIF inst_VPA_D.BLIF inst_CLK_000_PE.BLIF inst_CLK_000_NE.BLIF \ +cpu_est_2_.BLIF inst_VMA_INTreg.D +-0-01-1-1 1 +0-------- 1 +--1----0- 1 +--1--1--- 1 +-11------ 1 +--1-1---- 1 +--10----- 1 +--1-----0 1 +10-100-11 0 +1-0---0-- 0 +110------ 0 +1-0-----0 0 +1-0-0---- 0 +1-01----- 0 +.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.D +0- 1 +-1 1 +10 0 +.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D +0 1 +1 0 +.names SM_AMIGA_5_.BLIF inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_000_SYNC.BLIF \ +inst_CLK_000_D1.BLIF inst_CLK_000_D0.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_0_.BLIF \ +SM_AMIGA_6_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_2_.BLIF N_96_i +-1010------ 1 +---------1- 1 +--------1-- 1 +-------1--- 1 +------1---- 1 +-----1----- 1 +1---------- 1 +----------1 1 +0---1000000 0 +0--0-000000 0 +0-1--000000 0 +00---000000 0 +.names IPL_030DFF_2_reg.BLIF IPL_030_2_ +1 1 +0 0 +.names BG_000DFFreg.BLIF BG_000 +1 1 +0 0 +.names inst_BGACK_030_INTreg.BLIF BGACK_030 +1 1 +0 0 +.names CLK_DIV_OUT + 0 +.names CLK_030.BLIF CLK_EXP +1 1 +0 0 +.names FC_1_.BLIF BGACK_000.BLIF FPU_SENSE.BLIF A_19_.BLIF A_18_.BLIF \ +A_17_.BLIF A_16_.BLIF FC_0_.BLIF AS_030.PIN.BLIF FPU_CS +-------0- 1 +------1-- 1 +-----0--- 1 +----1---- 1 +---1----- 1 +--1------ 1 +-0------- 1 +0-------- 1 +--------1 1 +110001010 0 +.names inst_DSACK1_INTreg.BLIF DSACK1 +1 1 +0 0 +.names AVEC + 1 +.names cpu_est_3_reg.BLIF E +1 1 +0 0 +.names inst_VMA_INTreg.BLIF VMA +1 1 +0 0 +.names inst_RESET_OUTreg.BLIF RESET +1 1 +0 0 +.names AMIGA_ADDR_ENABLE + 0 +.names inst_BGACK_030_INTreg.BLIF inst_nEXP_SPACE_D0reg.BLIF AS_000.PIN.BLIF \ +RW_000.PIN.BLIF AMIGA_BUS_DATA_DIR +0001 1 +1--0 1 +-1-1 0 +--11 0 +0--0 0 +1--1 0 +.names inst_BGACK_030_INTreg.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF \ +AMIGA_BUS_ENABLE_LOW +1- 1 +-1 1 +00 0 +.names inst_BGACK_030_INTreg.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ +SM_AMIGA_i_7_.BLIF AMIGA_BUS_ENABLE_HIGH +01- 1 +1-0 1 +00- 0 +1-1 0 +.names A_31_.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF \ +A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF \ +inst_AS_030_D0.BLIF CIIN +0000000011110 1 +-----------0- 0 +----------0-- 0 +---------0--- 0 +--------0---- 0 +-------1----- 0 +------1------ 0 +-----1------- 0 +----1-------- 0 +---1--------- 0 +--1---------- 0 +-1----------- 0 +1------------ 0 +------------1 0 +.names IPL_030DFF_1_reg.BLIF IPL_030_1_ +1 1 +0 0 +.names IPL_030DFF_0_reg.BLIF IPL_030_0_ +1 1 +0 0 +.names CLK_OSZI.BLIF IPL_030DFF_2_reg.C +1 1 +0 0 +.names CLK_OSZI.BLIF IPL_D0_0_.C +1 1 +0 0 +.names CLK_OSZI.BLIF IPL_D0_1_.C +1 1 +0 0 +.names CLK_OSZI.BLIF IPL_D0_2_.C +1 1 +0 0 +.names CLK_OSZI.BLIF SM_AMIGA_i_7_.C +1 1 +0 0 +.names CLK_OSZI.BLIF SM_AMIGA_6_.C +1 1 +0 0 +.names CLK_OSZI.BLIF SM_AMIGA_5_.C +1 1 +0 0 +.names CLK_OSZI.BLIF SM_AMIGA_4_.C +1 1 +0 0 +.names CLK_OSZI.BLIF SM_AMIGA_3_.C +1 1 +0 0 +.names CLK_OSZI.BLIF SM_AMIGA_2_.C +1 1 +0 0 +.names CLK_OSZI.BLIF SM_AMIGA_1_.C +1 1 +0 0 +.names CLK_OSZI.BLIF SM_AMIGA_0_.C +1 1 +0 0 +.names cpu_est_0_.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_.D +10 1 +01 1 +00 0 +11 0 +.names CLK_OSZI.BLIF cpu_est_0_.C +1 1 +0 0 +.names CLK_OSZI.BLIF cpu_est_1_.C +1 1 +0 0 +.names CLK_OSZI.BLIF cpu_est_2_.C +1 1 +0 0 +.names CLK_OSZI.BLIF cpu_est_3_reg.C +1 1 +0 0 +.names CLK_OSZI.BLIF IPL_030DFF_0_reg.C +1 1 +0 0 +.names CLK_OSZI.BLIF IPL_030DFF_1_reg.C +1 1 +0 0 +.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_N_SYNC_9_.C +1 1 +0 0 +.names CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_N_SYNC_10_.C +1 1 +0 0 +.names CLK_000_N_SYNC_10_.BLIF CLK_000_N_SYNC_11_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_N_SYNC_11_.C +1 1 +0 0 +.names CLK_OSZI.BLIF RST_DLY_0_.C +1 1 +0 0 +.names CLK_OSZI.BLIF RST_DLY_1_.C +1 1 +0 0 +.names CLK_OSZI.BLIF RST_DLY_2_.C +1 1 +0 0 +.names CLK_OSZI.BLIF RST_DLY_3_.C +1 1 +0 0 +.names CLK_OSZI.BLIF RST_DLY_4_.C +1 1 +0 0 +.names CLK_OSZI.BLIF RST_DLY_5_.C +1 1 +0 0 +.names CLK_OSZI.BLIF RST_DLY_6_.C +1 1 +0 0 +.names CLK_OSZI.BLIF RST_DLY_7_.C +1 1 +0 0 +.names CLK_OSZI.BLIF CYCLE_DMA_0_.C +1 1 +0 0 +.names CLK_OSZI.BLIF CYCLE_DMA_1_.C +1 1 +0 0 +.names CLK_OSZI.BLIF SIZE_DMA_0_.C +1 1 +0 0 +.names CLK_OSZI.BLIF SIZE_DMA_1_.C +1 1 +0 0 +.names CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_P_SYNC_5_.C +1 1 +0 0 +.names CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_P_SYNC_6_.C +1 1 +0 0 +.names CLK_000_P_SYNC_6_.BLIF CLK_000_P_SYNC_7_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_P_SYNC_7_.C +1 1 +0 0 +.names CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_P_SYNC_8_.C +1 1 +0 0 +.names CLK_000_P_SYNC_8_.BLIF CLK_000_P_SYNC_9_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_P_SYNC_9_.C +1 1 +0 0 +.names inst_CLK_000_D1.BLIF inst_CLK_000_D0.BLIF CLK_000_N_SYNC_0_.D +10 1 +0- 0 +-1 0 +.names CLK_OSZI.BLIF CLK_000_N_SYNC_0_.C +1 1 +0 0 +.names CLK_000_N_SYNC_0_.BLIF CLK_000_N_SYNC_1_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_N_SYNC_1_.C +1 1 +0 0 +.names CLK_000_N_SYNC_1_.BLIF CLK_000_N_SYNC_2_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_N_SYNC_2_.C +1 1 +0 0 +.names CLK_000_N_SYNC_2_.BLIF CLK_000_N_SYNC_3_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_N_SYNC_3_.C +1 1 +0 0 +.names CLK_000_N_SYNC_3_.BLIF CLK_000_N_SYNC_4_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_N_SYNC_4_.C +1 1 +0 0 +.names CLK_000_N_SYNC_4_.BLIF CLK_000_N_SYNC_5_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_N_SYNC_5_.C +1 1 +0 0 +.names CLK_000_N_SYNC_5_.BLIF CLK_000_N_SYNC_6_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_N_SYNC_6_.C +1 1 +0 0 +.names CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_N_SYNC_7_.C +1 1 +0 0 +.names CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_N_SYNC_8_.C +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_P_SYNC_0_.C +1 1 +0 0 +.names CLK_000_P_SYNC_0_.BLIF CLK_000_P_SYNC_1_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_P_SYNC_1_.C +1 1 +0 0 +.names CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_P_SYNC_2_.C +1 1 +0 0 +.names CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_P_SYNC_3_.C +1 1 +0 0 +.names CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_P_SYNC_4_.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_CLK_030_H.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_RESET_OUTreg.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_DS_000_ENABLE.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_UDS_000_INT.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_RW_000_DMA.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_RW_000_INT.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_LDS_000_INT.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_AS_030_000_SYNC.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_AS_000_INT.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_DSACK1_INTreg.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_A0_DMA.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_AS_000_DMA.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_DS_000_DMA.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_DS_030_D0.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_AS_030_D0.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_nEXP_SPACE_D0reg.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_VPA_D.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_DTACK_D0.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_BGACK_030_INTreg.C +1 1 +0 0 +.names CLK_OSZI.BLIF BG_000DFFreg.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_VMA_INTreg.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_BGACK_030_INT_D.C +1 1 +0 0 +.names CLK_000_P_SYNC_9_.BLIF inst_CLK_000_PE.D +1 1 +0 0 +.names CLK_OSZI.BLIF inst_CLK_000_PE.C +1 1 +0 0 +.names CLK_000_N_SYNC_11_.BLIF inst_CLK_000_NE.D +1 1 +0 0 +.names CLK_OSZI.BLIF inst_CLK_000_NE.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_CLK_OUT_PRE_50.C +1 1 +0 0 +.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D +1 1 +0 0 +.names CLK_OSZI.BLIF inst_CLK_000_D1.C +1 1 +0 0 +.names inst_CLK_000_NE.BLIF inst_CLK_000_NE_D0.D +1 1 +0 0 +.names CLK_OSZI.BLIF inst_CLK_000_NE_D0.C +1 1 +0 0 +.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_D.D +1 1 +0 0 +.names CLK_OSZI.BLIF inst_CLK_OUT_PRE_D.C +1 1 +0 0 +.names CLK_000.BLIF inst_CLK_000_D0.D +1 1 +0 0 +.names CLK_OSZI.BLIF inst_CLK_000_D0.C +1 1 +0 0 +.names SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF SIZE_1_ +01 1 +1- 0 +-0 0 +.names inst_AS_000_DMA.BLIF AS_000.PIN.BLIF AS_030 +1- 1 +-1 1 +00 0 +.names inst_AS_000_INT.BLIF AS_030.PIN.BLIF AS_000 +1- 1 +-1 1 +00 0 +.names inst_RW_000_INT.BLIF RW_000 +1 1 +0 0 +.names inst_DS_000_DMA.BLIF AS_000.PIN.BLIF DS_030 +1- 1 +-1 1 +00 0 +.names inst_UDS_000_INT.BLIF inst_DS_000_ENABLE.BLIF DS_030.PIN.BLIF UDS_000 +-0- 1 +1-- 1 +--1 1 +010 0 +.names inst_LDS_000_INT.BLIF inst_DS_000_ENABLE.BLIF DS_030.PIN.BLIF LDS_000 +-0- 1 +1-- 1 +--1 1 +010 0 +.names inst_A0_DMA.BLIF A0 +1 1 +0 0 +.names BERR + 0 +.names inst_RW_000_DMA.BLIF RW +1 1 +0 0 +.names SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF SIZE_0_ +10 1 +0- 0 +-1 0 +.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUTreg.BLIF \ +inst_nEXP_SPACE_D0reg.BLIF AS_030.OE +010 1 +-0- 0 +1-- 0 +--1 0 +.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUTreg.BLIF AS_000.OE +11 1 +0- 0 +-0 0 +.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUTreg.BLIF RW_000.OE +11 1 +0- 0 +-0 0 +.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUTreg.BLIF \ +inst_nEXP_SPACE_D0reg.BLIF DS_030.OE +010 1 +-0- 0 +1-- 0 +--1 0 +.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUTreg.BLIF UDS_000.OE +11 1 +0- 0 +-0 0 +.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUTreg.BLIF LDS_000.OE +11 1 +0- 0 +-0 0 +.names inst_BGACK_030_INTreg.BLIF inst_nEXP_SPACE_D0reg.BLIF SIZE_0_.OE +00 1 +1- 0 +-1 0 +.names inst_BGACK_030_INTreg.BLIF inst_nEXP_SPACE_D0reg.BLIF SIZE_1_.OE +00 1 +1- 0 +-1 0 +.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUTreg.BLIF \ +inst_nEXP_SPACE_D0reg.BLIF A0.OE +010 1 +-0- 0 +1-- 0 +--1 0 +.names FC_1_.BLIF BGACK_000.BLIF FPU_SENSE.BLIF A_19_.BLIF A_18_.BLIF \ +A_17_.BLIF A_16_.BLIF FC_0_.BLIF AS_030.PIN.BLIF BERR.OE +111001010 1 +-------0- 0 +------1-- 0 +-----0--- 0 +----1---- 0 +---1----- 0 +--0------ 0 +-0------- 0 +0-------- 0 +--------1 0 +.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUTreg.BLIF RW.OE +01 1 +1- 0 +-0 0 +.names CLK_DIV_OUT.OE + 0 +.names inst_nEXP_SPACE_D0reg.BLIF DSACK1.OE +1 1 +0 0 +.names A_31_.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF \ +A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF \ +inst_AS_030_D0.BLIF inst_nEXP_SPACE_D0reg.BLIF CIIN.OE +0000000011110- 1 +-------------1 1 +------------10 0 +-----------0-0 0 +----------0--0 0 +---------0---0 0 +--------0----0 0 +-------1-----0 0 +------1------0 0 +-----1-------0 0 +----1--------0 0 +---1---------0 0 +--1----------0 0 +-1-----------0 0 +1------------0 0 +.names cpu_est_3_reg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF \ +inst_CLK_000_NE_D0.BLIF cpu_est_3_reg.D.X1 +11111 1 +0---- 0 +-0--- 0 +--0-- 0 +---0- 0 +----0 0 +.names cpu_est_3_reg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF \ +inst_CLK_000_NE_D0.BLIF cpu_est_3_reg.D.X2 +1---- 1 +-0001 1 +-1101 1 +0--1- 0 +0---0 0 +001-- 0 +010-- 0 +.names RST.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_3_.D.X1 +11 1 +0- 0 +-0 0 +.names RST.BLIF cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF \ +cpu_est_1_.BLIF inst_VPA_D.BLIF inst_DTACK_D0.BLIF inst_CLK_000_PE.BLIF \ +cpu_est_2_.BLIF SM_AMIGA_3_.BLIF inst_CLK_000_NE_D0.BLIF SM_AMIGA_4_.BLIF \ +BERR.PIN.BLIF SM_AMIGA_3_.D.X2 +1------1-0-1- 1 +1--------1--0 1 +110000--1110- 1 +1----10--110- 1 +0------------ 0 +-------0-0--- 0 +---------0-0- 0 +---------10-1 0 +---------1-11 0 +-0---0---1--1 0 +--1--0---1--1 0 +---1-0---1--1 0 +----10---1--1 0 +-----11--1--1 0 +-----0--01--1 0 +.names RST.BLIF RST_DLY_4_.BLIF RST_DLY_4_.D.X1 +11 1 +0- 0 +-0 0 +.names RST.BLIF inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF \ +RST_DLY_2_.BLIF RST_DLY_3_.BLIF RST_DLY_4_.BLIF RST_DLY_5_.BLIF \ +RST_DLY_6_.BLIF RST_DLY_7_.BLIF RST_DLY_4_.D.X2 +1111110--- 1 +111111-0-- 1 +111111--0- 1 +111111---0 1 +0--------- 0 +-0-------- 0 +--0------- 0 +---0------ 0 +----0----- 0 +-----0---- 0 +------1111 0 +.names RST_DLY_5_.BLIF RST_DLY_5_.D.X1 +1 1 +0 0 +.names RST.BLIF inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF \ +RST_DLY_2_.BLIF RST_DLY_3_.BLIF RST_DLY_4_.BLIF RST_DLY_5_.BLIF \ +RST_DLY_6_.BLIF RST_DLY_7_.BLIF RST_DLY_5_.D.X2 +11111110-- 1 +0------1-- 1 +-11111110- 1 +-1111111-0 1 +10-------- 0 +1-0------- 0 +1--0------ 0 +1---0----- 0 +1----0---- 0 +1-----0--- 0 +0------0-- 0 +-0-----0-- 0 +--0----0-- 0 +---0---0-- 0 +----0--0-- 0 +-----0-0-- 0 +------00-- 0 +1------111 0 +.names RST_DLY_6_.BLIF RST_DLY_6_.D.X1 +1 1 +0 0 +.names RST.BLIF inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF \ +RST_DLY_2_.BLIF RST_DLY_3_.BLIF RST_DLY_4_.BLIF RST_DLY_5_.BLIF \ +RST_DLY_6_.BLIF RST_DLY_7_.BLIF RST_DLY_6_.D.X2 +111111110- 1 +0-------1- 1 +-111111110 1 +10-------- 0 +1-0------- 0 +1--0------ 0 +1---0----- 0 +1----0---- 0 +1-----0--- 0 +1------0-- 0 +0-------0- 0 +-0------0- 0 +--0-----0- 0 +---0----0- 0 +----0---0- 0 +-----0--0- 0 +------0-0- 0 +-------00- 0 +1-------11 0 +.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_CLK_030_H.D.X1 +10 1 +0- 0 +-1 0 +.names CLK_030.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \ +CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF inst_CLK_030_H.BLIF AS_000.PIN.BLIF \ +UDS_000.PIN.BLIF LDS_000.PIN.BLIF inst_CLK_030_H.D.X2 +-10-00---- 1 +-10----1-- 1 +110---0--- 1 +-101--0--- 1 +-10-----11 1 +-10-11---- 1 +-0-------- 0 +--1------- 0 +----01100- 0 +----10100- 0 +----0110-0 0 +----1010-0 0 +0--001-00- 0 +0--010-00- 0 +0--001-0-0 0 +0--010-0-0 0 +.end diff --git a/Logic/68030_tk.crf b/Logic/68030_tk.crf index 2307e5b..91dfbd7 100644 --- a/Logic/68030_tk.crf +++ b/Logic/68030_tk.crf @@ -1,7 +1,7 @@ // Signal Name Cross Reference File // ispLEVER Classic 1.8.00.04.29.14 -// Design '68030_tk' created Sat Mar 28 22:02:48 2015 +// Design '68030_tk' created Wed May 13 22:59:21 2015 // LEGEND: '>' Functional Block Port Separator diff --git a/Logic/68030_tk.d0 b/Logic/68030_tk.d0 new file mode 100644 index 0000000..0541d3b --- /dev/null +++ b/Logic/68030_tk.d0 @@ -0,0 +1 @@ + -dev mach4a_DT_NCE -clust 5 diff --git a/Logic/68030_tk.eq3 b/Logic/68030_tk.eq3 new file mode 100644 index 0000000..3bd7bcd --- /dev/null +++ b/Logic/68030_tk.eq3 @@ -0,0 +1,773 @@ + ispLEVER Classic 1.8.00.04.29.14 Linked Equations File +Copyright(C), 1992-2014, Lattice Semiconductor Corp. +All Rights Reserved. + +Design bus68030 created Wed May 13 22:59:21 2015 + + + P-Terms Fan-in Fan-out Type Name (attributes) +--------- ------ ------- ---- ----------------- + 1 2 1 Pin SIZE_1_ + 1 2 1 Pin SIZE_1_.OE + 1 2 1 Pin AS_030- + 1 3 1 Pin AS_030.OE + 1 2 1 Pin AS_000- + 1 2 1 Pin AS_000.OE + 1 2 1 Pin DS_030- + 1 3 1 Pin DS_030.OE + 1 3 1 Pin UDS_000- + 1 2 1 Pin UDS_000.OE + 1 3 1 Pin LDS_000- + 1 2 1 Pin LDS_000.OE + 0 0 1 Pin BERR + 1 9 1 Pin BERR.OE + 0 0 1 Pin CLK_DIV_OUT + 0 0 1 Pin CLK_DIV_OUT.OE + 1 1 1 Pin CLK_EXP + 1 9 1 Pin FPU_CS- + 1 0 1 Pin AVEC + 0 0 1 Pin AMIGA_ADDR_ENABLE + 2 4 1 Pin AMIGA_BUS_DATA_DIR + 1 2 1 Pin AMIGA_BUS_ENABLE_LOW- + 2 3 1 Pin AMIGA_BUS_ENABLE_HIGH + 1 13 1 Pin CIIN + 1 1 1 Pin CIIN.OE + 1 2 1 Pin SIZE_0_ + 1 2 1 Pin SIZE_0_.OE + 10 8 1 Pin IPL_030_2_.D- + 1 1 1 Pin IPL_030_2_.C + 1 2 1 Pin RW_000.OE + 3 7 1 Pin RW_000.D- + 1 1 1 Pin RW_000.C + 1 3 1 Pin A0.OE + 3 5 1 Pin A0.D + 1 1 1 Pin A0.C + 2 6 1 Pin BG_000.D- + 1 1 1 Pin BG_000.C + 2 4 1 Pin BGACK_030.D- + 1 1 1 Pin BGACK_030.C + 10 8 1 Pin IPL_030_1_.D- + 1 1 1 Pin IPL_030_1_.C + 10 8 1 Pin IPL_030_0_.D- + 1 1 1 Pin IPL_030_0_.C + 1 1 1 Pin DSACK1.OE + 4 9 1 Pin DSACK1.D- + 1 1 1 Pin DSACK1.C + 5 5 1 Pin E.D + 1 1 1 Pin E.C + 3 9 1 Pin VMA.T + 1 1 1 Pin VMA.C + 2 11 1 Pin RESET.D + 1 1 1 Pin RESET.C + 1 2 1 Pin RW.OE + 2 5 1 Pin RW.D- + 1 1 1 Pin RW.C + 2 2 1 Node cpu_est_0_.D + 1 1 1 Node cpu_est_0_.C + 5 5 1 Node cpu_est_1_.D- + 1 1 1 Node cpu_est_1_.C + 2 5 1 Node inst_AS_000_INT.D- + 1 1 1 Node inst_AS_000_INT.C + 3 6 1 Node SM_AMIGA_5_.D + 1 1 1 Node SM_AMIGA_5_.C + 2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.D- + 1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.C + 1 2 1 Node inst_AS_030_D0.D- + 1 1 1 Node inst_AS_030_D0.C + 1 2 1 Node inst_nEXP_SPACE_D0reg.D- + 1 1 1 Node inst_nEXP_SPACE_D0reg.C + 1 2 1 Node inst_DS_030_D0.D- + 1 1 1 Node inst_DS_030_D0.C + 7 14 1 Node inst_AS_030_000_SYNC.D- + 1 1 1 Node inst_AS_030_000_SYNC.C + 1 2 1 Node inst_BGACK_030_INT_D.D- + 1 1 1 Node inst_BGACK_030_INT_D.C + 7 9 1 Node inst_AS_000_DMA.D + 1 1 1 Node inst_AS_000_DMA.C + 9 12 1 Node inst_DS_000_DMA.D + 1 1 1 Node inst_DS_000_DMA.C + 2 5 1 Node CYCLE_DMA_0_.D + 1 1 1 Node CYCLE_DMA_0_.C + 3 6 1 Node CYCLE_DMA_1_.D + 1 1 1 Node CYCLE_DMA_1_.C + 3 6 1 Node SIZE_DMA_0_.D- + 1 1 1 Node SIZE_DMA_0_.C + 3 6 1 Node SIZE_DMA_1_.D + 1 1 1 Node SIZE_DMA_1_.C + 1 2 1 Node inst_VPA_D.D- + 1 1 1 Node inst_VPA_D.C + 3 5 1 Node inst_UDS_000_INT.D- + 1 1 1 Node inst_UDS_000_INT.C + 4 7 1 Node inst_LDS_000_INT.D + 1 1 1 Node inst_LDS_000_INT.C + 1 1 1 Node inst_CLK_OUT_PRE_D.D + 1 1 1 Node inst_CLK_OUT_PRE_D.C + 1 2 1 Node inst_DTACK_D0.D- + 1 1 1 Node inst_DTACK_D0.C + 1 1 1 Node inst_CLK_OUT_PRE_50.D + 1 1 1 Node inst_CLK_OUT_PRE_50.C + 1 1 1 Node inst_CLK_000_D1.D + 1 1 1 Node inst_CLK_000_D1.C + 1 1 1 Node inst_CLK_000_D0.D + 1 1 1 Node inst_CLK_000_D0.C + 1 1 1 Node inst_CLK_000_PE.D + 1 1 1 Node inst_CLK_000_PE.C + 1 1 1 Node CLK_000_P_SYNC_9_.D + 1 1 1 Node CLK_000_P_SYNC_9_.C + 1 1 1 Node inst_CLK_000_NE.D + 1 1 1 Node inst_CLK_000_NE.C + 4 11 1 Node N_96_i- + 1 1 1 Node CLK_000_N_SYNC_11_.D + 1 1 1 Node CLK_000_N_SYNC_11_.C + 4 5 1 Node cpu_est_2_.D + 1 1 1 Node cpu_est_2_.C + 1 2 1 Node IPL_D0_0_.D- + 1 1 1 Node IPL_D0_0_.C + 1 2 1 Node IPL_D0_1_.D- + 1 1 1 Node IPL_D0_1_.C + 1 2 1 Node IPL_D0_2_.D- + 1 1 1 Node IPL_D0_2_.C + 5 13 1 Node SM_AMIGA_3_.T + 1 1 1 Node SM_AMIGA_3_.C + 1 1 1 Node inst_CLK_000_NE_D0.D + 1 1 1 Node inst_CLK_000_NE_D0.C + 2 6 1 Node SM_AMIGA_0_.D + 1 1 1 Node SM_AMIGA_0_.C + 2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- + 1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.C + 3 9 1 Node SM_AMIGA_6_.D + 1 1 1 Node SM_AMIGA_6_.C + 3 10 1 Node RST_DLY_0_.D + 1 1 1 Node RST_DLY_0_.C + 4 10 1 Node RST_DLY_1_.D + 1 1 1 Node RST_DLY_1_.C + 5 10 1 Node RST_DLY_2_.D + 1 1 1 Node RST_DLY_2_.C + 6 10 1 Node RST_DLY_3_.D + 1 1 1 Node RST_DLY_3_.C + 2 7 1 NodeX1 RST_DLY_4_.T.X1 + 1 10 1 NodeX2 RST_DLY_4_.T.X2 + 1 1 1 Node RST_DLY_4_.C + 4 10 1 Node RST_DLY_5_.T + 1 1 1 Node RST_DLY_5_.C + 3 10 1 Node RST_DLY_6_.T + 1 1 1 Node RST_DLY_6_.C + 2 10 1 Node RST_DLY_7_.D + 1 1 1 Node RST_DLY_7_.C + 1 2 1 Node CLK_000_P_SYNC_0_.D + 1 1 1 Node CLK_000_P_SYNC_0_.C + 1 1 1 Node CLK_000_P_SYNC_1_.D + 1 1 1 Node CLK_000_P_SYNC_1_.C + 1 1 1 Node CLK_000_P_SYNC_2_.D + 1 1 1 Node CLK_000_P_SYNC_2_.C + 1 1 1 Node CLK_000_P_SYNC_3_.D + 1 1 1 Node CLK_000_P_SYNC_3_.C + 1 1 1 Node CLK_000_P_SYNC_4_.D + 1 1 1 Node CLK_000_P_SYNC_4_.C + 1 1 1 Node CLK_000_P_SYNC_5_.D + 1 1 1 Node CLK_000_P_SYNC_5_.C + 1 1 1 Node CLK_000_P_SYNC_6_.D + 1 1 1 Node CLK_000_P_SYNC_6_.C + 1 1 1 Node CLK_000_P_SYNC_7_.D + 1 1 1 Node CLK_000_P_SYNC_7_.C + 1 1 1 Node CLK_000_P_SYNC_8_.D + 1 1 1 Node CLK_000_P_SYNC_8_.C + 1 2 1 Node CLK_000_N_SYNC_0_.D + 1 1 1 Node CLK_000_N_SYNC_0_.C + 1 1 1 Node CLK_000_N_SYNC_1_.D + 1 1 1 Node CLK_000_N_SYNC_1_.C + 1 1 1 Node CLK_000_N_SYNC_2_.D + 1 1 1 Node CLK_000_N_SYNC_2_.C + 1 1 1 Node CLK_000_N_SYNC_3_.D + 1 1 1 Node CLK_000_N_SYNC_3_.C + 1 1 1 Node CLK_000_N_SYNC_4_.D + 1 1 1 Node CLK_000_N_SYNC_4_.C + 1 1 1 Node CLK_000_N_SYNC_5_.D + 1 1 1 Node CLK_000_N_SYNC_5_.C + 1 1 1 Node CLK_000_N_SYNC_6_.D + 1 1 1 Node CLK_000_N_SYNC_6_.C + 1 1 1 Node CLK_000_N_SYNC_7_.D + 1 1 1 Node CLK_000_N_SYNC_7_.C + 1 1 1 Node CLK_000_N_SYNC_8_.D + 1 1 1 Node CLK_000_N_SYNC_8_.C + 1 1 1 Node CLK_000_N_SYNC_9_.D + 1 1 1 Node CLK_000_N_SYNC_9_.C + 1 1 1 Node CLK_000_N_SYNC_10_.D + 1 1 1 Node CLK_000_N_SYNC_10_.C + 8 10 1 Node inst_CLK_030_H.D + 1 1 1 Node inst_CLK_030_H.C + 3 6 1 Node SM_AMIGA_1_.D + 1 1 1 Node SM_AMIGA_1_.C + 3 6 1 Node SM_AMIGA_4_.D + 1 1 1 Node SM_AMIGA_4_.C + 4 13 1 Node SM_AMIGA_2_.D + 1 1 1 Node SM_AMIGA_2_.C + 3 7 1 Node inst_DS_000_ENABLE.D + 1 1 1 Node inst_DS_000_ENABLE.C + 14 20 1 Node SM_AMIGA_i_7_.D + 1 1 1 Node SM_AMIGA_i_7_.C + 2 14 1 Node CIIN_0 +========= + 348 P-Term Total: 348 + Total Pins: 61 + Total Nodes: 73 + Average P-Term/Output: 2 + + +Equations: + +SIZE_1_ = (!SIZE_DMA_0_.Q & SIZE_DMA_1_.Q); + +SIZE_1_.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q); + +!AS_030 = (!inst_AS_000_DMA.Q & !AS_000.PIN); + +AS_030.OE = (!BGACK_030.Q & RESET.Q & !inst_nEXP_SPACE_D0reg.Q); + +!AS_000 = (!inst_AS_000_INT.Q & !AS_030.PIN); + +AS_000.OE = (BGACK_030.Q & RESET.Q); + +!DS_030 = (!inst_DS_000_DMA.Q & !AS_000.PIN); + +DS_030.OE = (!BGACK_030.Q & RESET.Q & !inst_nEXP_SPACE_D0reg.Q); + +!UDS_000 = (!inst_UDS_000_INT.Q & inst_DS_000_ENABLE.Q & !DS_030.PIN); + +UDS_000.OE = (BGACK_030.Q & RESET.Q); + +!LDS_000 = (!inst_LDS_000_INT.Q & inst_DS_000_ENABLE.Q & !DS_030.PIN); + +LDS_000.OE = (BGACK_030.Q & RESET.Q); + +BERR = (0); + +BERR.OE = (FC_1_ & BGACK_000 & FPU_SENSE & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN); + +CLK_DIV_OUT = (0); + +CLK_DIV_OUT.OE = (0); + +CLK_EXP = (CLK_030); + +!FPU_CS = (FC_1_ & BGACK_000 & !FPU_SENSE & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN); + +AVEC = (1); + +AMIGA_ADDR_ENABLE = (0); + +AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW_000.PIN + # !BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q & !AS_000.PIN & RW_000.PIN); + +!AMIGA_BUS_ENABLE_LOW = (!BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_LOW.Q); + +AMIGA_BUS_ENABLE_HIGH = (!BGACK_030.Q & inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q + # BGACK_030.Q & !SM_AMIGA_i_7_.Q); + +CIIN = (!A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_ & A_23_ & A_22_ & A_21_ & A_20_ & !inst_AS_030_D0.Q); + +CIIN.OE = (CIIN_0); + +SIZE_0_ = (SIZE_DMA_0_.Q & !SIZE_DMA_1_.Q); + +SIZE_0_.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q); + +!IPL_030_2_.D = (!IPL_2_ & RST & !IPL_030_2_.Q + # RST & !IPL_D0_2_.Q & !IPL_030_2_.Q + # RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_2_.Q + # RST & IPL_0_ & !IPL_D0_0_.Q & !IPL_030_2_.Q + # RST & !IPL_1_ & IPL_D0_1_.Q & !IPL_030_2_.Q + # RST & IPL_1_ & !IPL_D0_1_.Q & !IPL_030_2_.Q + # !IPL_2_ & RST & IPL_1_ & IPL_0_ & IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q + # !IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q + # !IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q + # !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q); + +IPL_030_2_.C = (CLK_OSZI); + +RW_000.OE = (BGACK_030.Q & RESET.Q); + +!RW_000.D = (RST & SM_AMIGA_5_.Q & !RW.PIN + # RST & !SM_AMIGA_5_.Q & !inst_CLK_000_PE.Q & !RW_000.Q & SM_AMIGA_i_7_.Q + # RST & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q); + +RW_000.C = (CLK_OSZI); + +A0.OE = (!BGACK_030.Q & RESET.Q & !inst_nEXP_SPACE_D0reg.Q); + +A0.D = (!RST + # !BGACK_030.Q & UDS_000.PIN + # BGACK_030.Q & inst_BGACK_030_INT_D.Q & A0.Q); + +A0.C = (CLK_OSZI); + +!BG_000.D = (!BG_030 & RST & !BG_000.Q + # !BG_030 & RST & inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_CLK_000_D0.Q); + +BG_000.C = (CLK_OSZI); + +!BGACK_030.D = (!BGACK_000 & RST + # RST & !BGACK_030.Q & !inst_CLK_000_PE.Q); + +BGACK_030.C = (CLK_OSZI); + +!IPL_030_1_.D = (RST & !IPL_1_ & !IPL_030_1_.Q + # RST & !IPL_D0_1_.Q & !IPL_030_1_.Q + # RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_1_.Q + # RST & IPL_0_ & !IPL_D0_0_.Q & !IPL_030_1_.Q + # !IPL_2_ & RST & IPL_D0_2_.Q & !IPL_030_1_.Q + # IPL_2_ & RST & !IPL_D0_2_.Q & !IPL_030_1_.Q + # IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q + # IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q + # !IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q + # !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q); + +IPL_030_1_.C = (CLK_OSZI); + +!IPL_030_0_.D = (RST & !IPL_0_ & !IPL_030_0_.Q + # RST & !IPL_D0_0_.Q & !IPL_030_0_.Q + # RST & !IPL_1_ & IPL_D0_1_.Q & !IPL_030_0_.Q + # RST & IPL_1_ & !IPL_D0_1_.Q & !IPL_030_0_.Q + # !IPL_2_ & RST & IPL_D0_2_.Q & !IPL_030_0_.Q + # IPL_2_ & RST & !IPL_D0_2_.Q & !IPL_030_0_.Q + # IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & IPL_D0_2_.Q + # IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q + # !IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q + # !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q); + +IPL_030_0_.C = (CLK_OSZI); + +DSACK1.OE = (inst_nEXP_SPACE_D0reg.Q); + +!DSACK1.D = (RST & CLK_000_N_SYNC_10_.Q & SM_AMIGA_1_.Q + # !CLK_030 & RST & CLK_000_N_SYNC_9_.Q & SM_AMIGA_1_.Q + # RST & inst_CLK_OUT_PRE_D.Q & CLK_000_N_SYNC_9_.Q & SM_AMIGA_1_.Q + # RST & !inst_AS_030_D0.Q & !DSACK1.Q & BERR.PIN); + +DSACK1.C = (CLK_OSZI); + +E.D = (E.Q & !cpu_est_0_.Q + # E.Q & !cpu_est_1_.Q + # E.Q & !inst_CLK_000_NE_D0.Q + # cpu_est_0_.Q & cpu_est_1_.Q & !cpu_est_2_.Q & inst_CLK_000_NE_D0.Q + # !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & inst_CLK_000_NE_D0.Q); + +E.C = (CLK_OSZI); + +VMA.T = (!RST & !VMA.Q + # !E.Q & !VMA.Q & !cpu_est_0_.Q & cpu_est_1_.Q & inst_CLK_000_PE.Q & cpu_est_2_.Q + # RST & !E.Q & VMA.Q & cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_NE.Q & cpu_est_2_.Q); + +VMA.C = (CLK_OSZI); + +RESET.D = (RST & RESET.Q + # RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & RST_DLY_6_.Q & RST_DLY_7_.Q); + +RESET.C = (CLK_OSZI); + +RW.OE = (!BGACK_030.Q & RESET.Q); + +!RW.D = (RST & !BGACK_030.Q & !RW_000.PIN + # RST & BGACK_030.Q & inst_BGACK_030_INT_D.Q & !RW.Q); + +RW.C = (CLK_OSZI); + +cpu_est_0_.D = (!cpu_est_0_.Q & inst_CLK_000_NE_D0.Q + # cpu_est_0_.Q & !inst_CLK_000_NE_D0.Q); + +cpu_est_0_.C = (CLK_OSZI); + +!cpu_est_1_.D = (!cpu_est_1_.Q & !inst_CLK_000_NE_D0.Q + # E.Q & cpu_est_0_.Q & !cpu_est_1_.Q + # !E.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & cpu_est_2_.Q + # E.Q & cpu_est_0_.Q & !cpu_est_2_.Q & inst_CLK_000_NE_D0.Q + # !E.Q & cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q); + +cpu_est_1_.C = (CLK_OSZI); + +!inst_AS_000_INT.D = (RST & SM_AMIGA_5_.Q + # RST & !inst_AS_000_INT.Q & !inst_AS_030_D0.Q & BERR.PIN); + +inst_AS_000_INT.C = (CLK_OSZI); + +SM_AMIGA_5_.D = (RST & !SM_AMIGA_5_.Q & inst_CLK_000_PE.Q & SM_AMIGA_6_.Q + # RST & SM_AMIGA_5_.Q & !inst_CLK_000_NE.Q & BERR.PIN + # RST & SM_AMIGA_5_.Q & SM_AMIGA_6_.Q & BERR.PIN); + +SM_AMIGA_5_.C = (CLK_OSZI); + +!inst_AMIGA_BUS_ENABLE_DMA_LOW.D = (A1 & RST & !BGACK_030.Q + # RST & BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_LOW.Q & inst_BGACK_030_INT_D.Q); + +inst_AMIGA_BUS_ENABLE_DMA_LOW.C = (CLK_OSZI); + +!inst_AS_030_D0.D = (RST & !AS_030.PIN); + +inst_AS_030_D0.C = (CLK_OSZI); + +!inst_nEXP_SPACE_D0reg.D = (!nEXP_SPACE & RST); + +inst_nEXP_SPACE_D0reg.C = (CLK_OSZI); + +!inst_DS_030_D0.D = (RST & !DS_030.PIN); + +inst_DS_030_D0.C = (CLK_OSZI); + +!inst_AS_030_000_SYNC.D = (RST & !inst_AS_030_D0.Q & !inst_AS_030_000_SYNC.Q & BERR.PIN + # !FC_1_ & RST & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN + # RST & A_19_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN + # RST & A_18_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN + # RST & !A_17_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN + # RST & A_16_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN + # RST & !FC_0_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN); + +inst_AS_030_000_SYNC.C = (CLK_OSZI); + +!inst_BGACK_030_INT_D.D = (RST & !BGACK_030.Q); + +inst_BGACK_030_INT_D.C = (CLK_OSZI); + +inst_AS_000_DMA.D = (!RST + # BGACK_030.Q + # AS_000.PIN + # !CLK_030 & inst_AS_000_DMA.Q + # CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q + # !CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q + # UDS_000.PIN & LDS_000.PIN); + +inst_AS_000_DMA.C = (CLK_OSZI); + +inst_DS_000_DMA.D = (!RST + # BGACK_030.Q + # AS_000.PIN + # CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q + # !CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q + # UDS_000.PIN & LDS_000.PIN + # !CLK_030 & inst_DS_000_DMA.Q & !RW_000.PIN + # inst_DS_000_DMA.Q & !inst_CLK_030_H.Q & !RW_000.PIN + # CLK_030 & inst_AS_000_DMA.Q & inst_CLK_030_H.Q & !RW_000.PIN); + +inst_DS_000_DMA.C = (CLK_OSZI); + +CYCLE_DMA_0_.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & inst_CLK_000_PE.Q & !AS_000.PIN + # RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !inst_CLK_000_PE.Q & !AS_000.PIN); + +CYCLE_DMA_0_.C = (CLK_OSZI); + +CYCLE_DMA_1_.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_000.PIN + # RST & !BGACK_030.Q & CYCLE_DMA_1_.Q & !inst_CLK_000_PE.Q & !AS_000.PIN + # RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & inst_CLK_000_PE.Q & !AS_000.PIN); + +CYCLE_DMA_1_.C = (CLK_OSZI); + +!SIZE_DMA_0_.D = (RST & BGACK_030.Q & !inst_BGACK_030_INT_D.Q + # RST & BGACK_030.Q & !SIZE_DMA_0_.Q + # RST & !BGACK_030.Q & !UDS_000.PIN & !LDS_000.PIN); + +SIZE_DMA_0_.C = (CLK_OSZI); + +SIZE_DMA_1_.D = (!RST + # BGACK_030.Q & inst_BGACK_030_INT_D.Q & SIZE_DMA_1_.Q + # !BGACK_030.Q & !UDS_000.PIN & !LDS_000.PIN); + +SIZE_DMA_1_.C = (CLK_OSZI); + +!inst_VPA_D.D = (!VPA & RST); + +inst_VPA_D.C = (CLK_OSZI); + +!inst_UDS_000_INT.D = (RST & inst_DS_030_D0.Q & !inst_UDS_000_INT.Q + # RST & !inst_UDS_000_INT.Q & !SM_AMIGA_6_.Q + # RST & !inst_DS_030_D0.Q & SM_AMIGA_6_.Q & !A0.PIN); + +inst_UDS_000_INT.C = (CLK_OSZI); + +inst_LDS_000_INT.D = (!RST + # inst_DS_030_D0.Q & inst_LDS_000_INT.Q + # inst_LDS_000_INT.Q & !SM_AMIGA_6_.Q + # !inst_DS_030_D0.Q & SM_AMIGA_6_.Q & SIZE_0_.PIN & !SIZE_1_.PIN & !A0.PIN); + +inst_LDS_000_INT.C = (CLK_OSZI); + +inst_CLK_OUT_PRE_D.D = (inst_CLK_OUT_PRE_50.Q); + +inst_CLK_OUT_PRE_D.C = (CLK_OSZI); + +!inst_DTACK_D0.D = (!DTACK & RST); + +inst_DTACK_D0.C = (CLK_OSZI); + +inst_CLK_OUT_PRE_50.D = (!inst_CLK_OUT_PRE_50.Q); + +inst_CLK_OUT_PRE_50.C = (CLK_OSZI); + +inst_CLK_000_D1.D = (inst_CLK_000_D0.Q); + +inst_CLK_000_D1.C = (CLK_OSZI); + +inst_CLK_000_D0.D = (CLK_000); + +inst_CLK_000_D0.C = (CLK_OSZI); + +inst_CLK_000_PE.D = (CLK_000_P_SYNC_9_.Q); + +inst_CLK_000_PE.C = (CLK_OSZI); + +CLK_000_P_SYNC_9_.D = (CLK_000_P_SYNC_8_.Q); + +CLK_000_P_SYNC_9_.C = (CLK_OSZI); + +inst_CLK_000_NE.D = (CLK_000_N_SYNC_11_.Q); + +inst_CLK_000_NE.C = (CLK_OSZI); + +!N_96_i = (!SM_AMIGA_5_.Q & !inst_nEXP_SPACE_D0reg.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q + # !SM_AMIGA_5_.Q & inst_AS_030_000_SYNC.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q + # !SM_AMIGA_5_.Q & !inst_CLK_000_D1.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q + # !SM_AMIGA_5_.Q & inst_CLK_000_D0.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q); + +CLK_000_N_SYNC_11_.D = (CLK_000_N_SYNC_10_.Q); + +CLK_000_N_SYNC_11_.C = (CLK_OSZI); + +cpu_est_2_.D = (cpu_est_1_.Q & cpu_est_2_.Q + # cpu_est_2_.Q & !inst_CLK_000_NE_D0.Q + # E.Q & cpu_est_0_.Q & inst_CLK_000_NE_D0.Q + # !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_NE_D0.Q); + +cpu_est_2_.C = (CLK_OSZI); + +!IPL_D0_0_.D = (RST & !IPL_0_); + +IPL_D0_0_.C = (CLK_OSZI); + +!IPL_D0_1_.D = (RST & !IPL_1_); + +IPL_D0_1_.C = (CLK_OSZI); + +!IPL_D0_2_.D = (!IPL_2_ & RST); + +IPL_D0_2_.C = (CLK_OSZI); + +SM_AMIGA_3_.T = (!RST & SM_AMIGA_3_.Q + # SM_AMIGA_3_.Q & !BERR.PIN + # RST & inst_CLK_000_PE.Q & !SM_AMIGA_3_.Q & SM_AMIGA_4_.Q + # inst_VPA_D.Q & !inst_DTACK_D0.Q & SM_AMIGA_3_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_4_.Q + # E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & cpu_est_2_.Q & SM_AMIGA_3_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_4_.Q); + +SM_AMIGA_3_.C = (CLK_OSZI); + +inst_CLK_000_NE_D0.D = (inst_CLK_000_NE.Q); + +inst_CLK_000_NE_D0.C = (CLK_OSZI); + +SM_AMIGA_0_.D = (RST & inst_CLK_000_NE.Q & !SM_AMIGA_0_.Q & SM_AMIGA_1_.Q + # RST & !inst_CLK_000_PE.Q & SM_AMIGA_0_.Q & BERR.PIN); + +SM_AMIGA_0_.C = (CLK_OSZI); + +!inst_AMIGA_BUS_ENABLE_DMA_HIGH.D = (!A1 & RST & !BGACK_030.Q + # RST & BGACK_030.Q & inst_BGACK_030_INT_D.Q & !inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q); + +inst_AMIGA_BUS_ENABLE_DMA_HIGH.C = (CLK_OSZI); + +SM_AMIGA_6_.D = (RST & SM_AMIGA_6_.Q & !SM_AMIGA_i_7_.Q + # RST & !inst_CLK_000_PE.Q & SM_AMIGA_6_.Q & BERR.PIN + # RST & inst_nEXP_SPACE_D0reg.Q & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D1.Q & !inst_CLK_000_D0.Q & !SM_AMIGA_i_7_.Q); + +SM_AMIGA_6_.C = (CLK_OSZI); + +RST_DLY_0_.D = (RST & !inst_CLK_000_NE.Q & RST_DLY_0_.Q + # RST & inst_CLK_000_NE.Q & !RST_DLY_0_.Q + # RST & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & RST_DLY_6_.Q & RST_DLY_7_.Q); + +RST_DLY_0_.C = (CLK_OSZI); + +RST_DLY_1_.D = (RST & !inst_CLK_000_NE.Q & RST_DLY_1_.Q + # RST & !RST_DLY_0_.Q & RST_DLY_1_.Q + # RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & !RST_DLY_1_.Q + # RST & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & RST_DLY_6_.Q & RST_DLY_7_.Q); + +RST_DLY_1_.C = (CLK_OSZI); + +RST_DLY_2_.D = (RST & !inst_CLK_000_NE.Q & RST_DLY_2_.Q + # RST & !RST_DLY_0_.Q & RST_DLY_2_.Q + # RST & !RST_DLY_1_.Q & RST_DLY_2_.Q + # RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & !RST_DLY_2_.Q + # RST & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & RST_DLY_6_.Q & RST_DLY_7_.Q); + +RST_DLY_2_.C = (CLK_OSZI); + +RST_DLY_3_.D = (RST & !inst_CLK_000_NE.Q & RST_DLY_3_.Q + # RST & !RST_DLY_0_.Q & RST_DLY_3_.Q + # RST & !RST_DLY_1_.Q & RST_DLY_3_.Q + # RST & !RST_DLY_2_.Q & RST_DLY_3_.Q + # RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & !RST_DLY_3_.Q + # RST & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & RST_DLY_6_.Q & RST_DLY_7_.Q); + +RST_DLY_3_.C = (CLK_OSZI); + +RST_DLY_4_.T.X1 = (!RST & RST_DLY_4_.Q + # RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q); + +RST_DLY_4_.T.X2 = (RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & RST_DLY_6_.Q & RST_DLY_7_.Q); + +RST_DLY_4_.C = (CLK_OSZI); + +RST_DLY_5_.T = (!RST & RST_DLY_5_.Q + # RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & !RST_DLY_5_.Q + # inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & !RST_DLY_6_.Q + # inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & !RST_DLY_7_.Q); + +RST_DLY_5_.C = (CLK_OSZI); + +RST_DLY_6_.T = (!RST & RST_DLY_6_.Q + # RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & !RST_DLY_6_.Q + # inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & RST_DLY_6_.Q & !RST_DLY_7_.Q); + +RST_DLY_6_.C = (CLK_OSZI); + +RST_DLY_7_.D = (RST & RST_DLY_7_.Q + # RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & RST_DLY_6_.Q); + +RST_DLY_7_.C = (CLK_OSZI); + +CLK_000_P_SYNC_0_.D = (!inst_CLK_000_D1.Q & inst_CLK_000_D0.Q); + +CLK_000_P_SYNC_0_.C = (CLK_OSZI); + +CLK_000_P_SYNC_1_.D = (CLK_000_P_SYNC_0_.Q); + +CLK_000_P_SYNC_1_.C = (CLK_OSZI); + +CLK_000_P_SYNC_2_.D = (CLK_000_P_SYNC_1_.Q); + +CLK_000_P_SYNC_2_.C = (CLK_OSZI); + +CLK_000_P_SYNC_3_.D = (CLK_000_P_SYNC_2_.Q); + +CLK_000_P_SYNC_3_.C = (CLK_OSZI); + +CLK_000_P_SYNC_4_.D = (CLK_000_P_SYNC_3_.Q); + +CLK_000_P_SYNC_4_.C = (CLK_OSZI); + +CLK_000_P_SYNC_5_.D = (CLK_000_P_SYNC_4_.Q); + +CLK_000_P_SYNC_5_.C = (CLK_OSZI); + +CLK_000_P_SYNC_6_.D = (CLK_000_P_SYNC_5_.Q); + +CLK_000_P_SYNC_6_.C = (CLK_OSZI); + +CLK_000_P_SYNC_7_.D = (CLK_000_P_SYNC_6_.Q); + +CLK_000_P_SYNC_7_.C = (CLK_OSZI); + +CLK_000_P_SYNC_8_.D = (CLK_000_P_SYNC_7_.Q); + +CLK_000_P_SYNC_8_.C = (CLK_OSZI); + +CLK_000_N_SYNC_0_.D = (inst_CLK_000_D1.Q & !inst_CLK_000_D0.Q); + +CLK_000_N_SYNC_0_.C = (CLK_OSZI); + +CLK_000_N_SYNC_1_.D = (CLK_000_N_SYNC_0_.Q); + +CLK_000_N_SYNC_1_.C = (CLK_OSZI); + +CLK_000_N_SYNC_2_.D = (CLK_000_N_SYNC_1_.Q); + +CLK_000_N_SYNC_2_.C = (CLK_OSZI); + +CLK_000_N_SYNC_3_.D = (CLK_000_N_SYNC_2_.Q); + +CLK_000_N_SYNC_3_.C = (CLK_OSZI); + +CLK_000_N_SYNC_4_.D = (CLK_000_N_SYNC_3_.Q); + +CLK_000_N_SYNC_4_.C = (CLK_OSZI); + +CLK_000_N_SYNC_5_.D = (CLK_000_N_SYNC_4_.Q); + +CLK_000_N_SYNC_5_.C = (CLK_OSZI); + +CLK_000_N_SYNC_6_.D = (CLK_000_N_SYNC_5_.Q); + +CLK_000_N_SYNC_6_.C = (CLK_OSZI); + +CLK_000_N_SYNC_7_.D = (CLK_000_N_SYNC_6_.Q); + +CLK_000_N_SYNC_7_.C = (CLK_OSZI); + +CLK_000_N_SYNC_8_.D = (CLK_000_N_SYNC_7_.Q); + +CLK_000_N_SYNC_8_.C = (CLK_OSZI); + +CLK_000_N_SYNC_9_.D = (CLK_000_N_SYNC_8_.Q); + +CLK_000_N_SYNC_9_.C = (CLK_OSZI); + +CLK_000_N_SYNC_10_.D = (CLK_000_N_SYNC_9_.Q); + +CLK_000_N_SYNC_10_.C = (CLK_OSZI); + +inst_CLK_030_H.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !UDS_000.PIN + # RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !UDS_000.PIN + # RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !LDS_000.PIN + # RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !LDS_000.PIN + # !CLK_030 & RST & !BGACK_030.Q & !inst_AS_000_DMA.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_000.PIN & !UDS_000.PIN + # !CLK_030 & RST & !BGACK_030.Q & !inst_AS_000_DMA.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & !AS_000.PIN & !UDS_000.PIN + # !CLK_030 & RST & !BGACK_030.Q & !inst_AS_000_DMA.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_000.PIN & !LDS_000.PIN + # !CLK_030 & RST & !BGACK_030.Q & !inst_AS_000_DMA.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & !AS_000.PIN & !LDS_000.PIN); + +inst_CLK_030_H.C = (CLK_OSZI); + +SM_AMIGA_1_.D = (RST & inst_CLK_000_PE.Q & !SM_AMIGA_1_.Q & SM_AMIGA_2_.Q + # RST & !inst_CLK_000_NE.Q & SM_AMIGA_1_.Q & BERR.PIN + # RST & SM_AMIGA_1_.Q & SM_AMIGA_2_.Q & BERR.PIN); + +SM_AMIGA_1_.C = (CLK_OSZI); + +SM_AMIGA_4_.D = (RST & SM_AMIGA_5_.Q & inst_CLK_000_NE.Q + # RST & SM_AMIGA_5_.Q & SM_AMIGA_4_.Q + # RST & !inst_CLK_000_PE.Q & SM_AMIGA_4_.Q & BERR.PIN); + +SM_AMIGA_4_.C = (CLK_OSZI); + +SM_AMIGA_2_.D = (RST & SM_AMIGA_3_.Q & SM_AMIGA_2_.Q + # RST & !inst_CLK_000_PE.Q & SM_AMIGA_2_.Q & BERR.PIN + # RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & SM_AMIGA_3_.Q & inst_CLK_000_NE_D0.Q + # RST & E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & cpu_est_2_.Q & SM_AMIGA_3_.Q & inst_CLK_000_NE_D0.Q); + +SM_AMIGA_2_.C = (CLK_OSZI); + +inst_DS_000_ENABLE.D = (RST & !SM_AMIGA_5_.Q & SM_AMIGA_3_.Q + # RST & SM_AMIGA_5_.Q & RW.PIN + # RST & !inst_AS_030_D0.Q & inst_DS_000_ENABLE.Q & BERR.PIN); + +inst_DS_000_ENABLE.C = (CLK_OSZI); + +SM_AMIGA_i_7_.D = (RST & !inst_CLK_000_PE.Q & N_96_i & BERR.PIN + # RST & N_96_i & !SM_AMIGA_0_.Q & BERR.PIN + # RST & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & N_96_i & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q + # RST & !SM_AMIGA_5_.Q & inst_CLK_000_PE.Q & N_96_i & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q + # RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & N_96_i & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q + # RST & inst_CLK_000_NE.Q & N_96_i & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q + # RST & !SM_AMIGA_5_.Q & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_PE.Q & N_96_i & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q + # RST & !SM_AMIGA_5_.Q & N_96_i & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q + # RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE.Q & N_96_i & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q + # RST & !SM_AMIGA_5_.Q & inst_VPA_D.Q & !inst_DTACK_D0.Q & N_96_i & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q + # RST & E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & N_96_i & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q + # RST & E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !SM_AMIGA_5_.Q & !inst_VPA_D.Q & inst_CLK_000_PE.Q & N_96_i & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q + # RST & E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_NE.Q & N_96_i & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q + # RST & E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !SM_AMIGA_5_.Q & !inst_VPA_D.Q & N_96_i & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q); + +SM_AMIGA_i_7_.C = (CLK_OSZI); + +CIIN_0 = (inst_nEXP_SPACE_D0reg.Q + # !A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_ & A_23_ & A_22_ & A_21_ & A_20_ & !inst_AS_030_D0.Q); + + +Reverse-Polarity Equations: + diff --git a/Logic/68030_tk.err b/Logic/68030_tk.err new file mode 100644 index 0000000..e69de29 diff --git a/Logic/68030_tk.fti b/Logic/68030_tk.fti new file mode 100644 index 0000000..04969e8 --- /dev/null +++ b/Logic/68030_tk.fti @@ -0,0 +1,488 @@ +#PLAFILE 68030_tk.tt4 +#DATE 03/16/2015 +#DESIGN +#DEVICE mach447a + +DATA LOCATION A0:G_8_69 // IO {RN_A0} +DATA LOCATION A1:F_*_60 // INP +DATA LOCATION AMIGA_ADDR_ENABLE:D_5_33 // OUT +DATA LOCATION AMIGA_BUS_DATA_DIR:E_1_48 // OUT +DATA LOCATION AMIGA_BUS_ENABLE_HIGH:D_4_34 // OUT +DATA LOCATION AMIGA_BUS_ENABLE_LOW:C_0_20 // OUT +DATA LOCATION AS_000:E_4_42 // IO +DATA LOCATION AS_030:H_8_82 // IO +DATA LOCATION AVEC:A_4_92 // OUT +DATA LOCATION A_16_:A_*_96 // INP +DATA LOCATION A_17_:F_*_59 // INP +DATA LOCATION A_18_:A_*_95 // INP +DATA LOCATION A_19_:A_*_97 // INP +DATA LOCATION A_20_:A_*_93 // INP +DATA LOCATION A_21_:A_*_94 // INP +DATA LOCATION A_22_:H_*_84 // INP +DATA LOCATION A_23_:H_*_85 // INP +DATA LOCATION A_24_:C_*_19 // INP +DATA LOCATION A_25_:C_*_18 // INP +DATA LOCATION A_26_:C_*_17 // INP +DATA LOCATION A_27_:C_*_16 // INP +DATA LOCATION A_28_:C_*_15 // INP +DATA LOCATION A_29_:B_*_6 // INP +DATA LOCATION A_30_:B_*_5 // INP +DATA LOCATION A_31_:B_*_4 // INP +DATA LOCATION BERR:E_0_41 // IO +DATA LOCATION BGACK_000:D_*_28 // INP +DATA LOCATION BGACK_030:H_4_83 // IO {RN_BGACK_030} +DATA LOCATION BG_000:D_1_29 // IO {RN_BG_000} +DATA LOCATION BG_030:C_*_21 // INP +DATA LOCATION CIIN:E_12_47 // OUT +DATA LOCATION CIIN_0:E_5 // NOD +DATA LOCATION CLK_000:*_*_11 // INP +DATA LOCATION CLK_000_N_SYNC_0_:D_11 // NOD +DATA LOCATION CLK_000_N_SYNC_10_:H_2 // NOD +DATA LOCATION CLK_000_N_SYNC_11_:H_6 // NOD +DATA LOCATION CLK_000_N_SYNC_1_:B_3 // NOD +DATA LOCATION CLK_000_N_SYNC_2_:D_7 // NOD +DATA LOCATION CLK_000_N_SYNC_3_:D_3 // NOD +DATA LOCATION CLK_000_N_SYNC_4_:A_14 // NOD +DATA LOCATION CLK_000_N_SYNC_5_:C_13 // NOD +DATA LOCATION CLK_000_N_SYNC_6_:D_14 // NOD +DATA LOCATION CLK_000_N_SYNC_7_:D_10 // NOD +DATA LOCATION CLK_000_N_SYNC_8_:A_10 // NOD +DATA LOCATION CLK_000_N_SYNC_9_:G_6 // NOD +DATA LOCATION CLK_000_P_SYNC_0_:D_15 // NOD +DATA LOCATION CLK_000_P_SYNC_1_:G_7 // NOD +DATA LOCATION CLK_000_P_SYNC_2_:G_3 // NOD +DATA LOCATION CLK_000_P_SYNC_3_:B_11 // NOD +DATA LOCATION CLK_000_P_SYNC_4_:B_7 // NOD +DATA LOCATION CLK_000_P_SYNC_5_:G_14 // NOD +DATA LOCATION CLK_000_P_SYNC_6_:G_10 // NOD +DATA LOCATION CLK_000_P_SYNC_7_:A_7 // NOD +DATA LOCATION CLK_000_P_SYNC_8_:A_3 // NOD +DATA LOCATION CLK_000_P_SYNC_9_:A_11 // NOD +DATA LOCATION CLK_030:*_*_64 // INP +DATA LOCATION CLK_DIV_OUT:G_1_65 // OUT +DATA LOCATION CLK_EXP:B_1_10 // OUT +DATA LOCATION CLK_OSZI:*_*_61 // Cin +DATA LOCATION CYCLE_DMA_0_:A_6 // NOD +DATA LOCATION CYCLE_DMA_1_:A_2 // NOD +DATA LOCATION DSACK1:H_9_81 // IO {RN_DSACK1} +DATA LOCATION DS_030:A_0_98 // IO +DATA LOCATION DTACK:D_*_30 // INP +DATA LOCATION E:G_4_66 // IO {RN_E} +DATA LOCATION FC_0_:F_*_57 // INP +DATA LOCATION FC_1_:F_*_58 // INP +DATA LOCATION FPU_CS:H_1_78 // OUT +DATA LOCATION FPU_SENSE:A_*_91 // INP +DATA LOCATION IPL_030_0_:B_8_8 // IO {RN_IPL_030_0_} +DATA LOCATION IPL_030_1_:B_12_7 // IO {RN_IPL_030_1_} +DATA LOCATION IPL_030_2_:B_4_9 // IO {RN_IPL_030_2_} +DATA LOCATION IPL_0_:G_*_67 // INP +DATA LOCATION IPL_1_:F_*_56 // INP +DATA LOCATION IPL_2_:G_*_68 // INP +DATA LOCATION IPL_D0_0_:B_15 // NOD +DATA LOCATION IPL_D0_1_:G_15 // NOD +DATA LOCATION IPL_D0_2_:G_11 // NOD +DATA LOCATION LDS_000:D_12_31 // IO +DATA LOCATION N_96_i:F_6 // NOD +DATA LOCATION RESET:B_0_3 // IO {RN_RESET} +DATA LOCATION RN_A0:G_8 // NOD {A0} +DATA LOCATION RN_BGACK_030:H_4 // NOD {BGACK_030} +DATA LOCATION RN_BG_000:D_1 // NOD {BG_000} +DATA LOCATION RN_DSACK1:H_9 // NOD {DSACK1} +DATA LOCATION RN_E:G_4 // NOD {E} +DATA LOCATION RN_IPL_030_0_:B_8 // NOD {IPL_030_0_} +DATA LOCATION RN_IPL_030_1_:B_12 // NOD {IPL_030_1_} +DATA LOCATION RN_IPL_030_2_:B_4 // NOD {IPL_030_2_} +DATA LOCATION RN_RESET:B_0 // NOD {RESET} +DATA LOCATION RN_RW:G_0 // NOD {RW} +DATA LOCATION RN_RW_000:H_0 // NOD {RW_000} +DATA LOCATION RN_VMA:D_0 // NOD {VMA} +DATA LOCATION RST:*_*_86 // INP +DATA LOCATION RST_DLY_0_:B_6 // NOD +DATA LOCATION RST_DLY_1_:A_1 // NOD +DATA LOCATION RST_DLY_2_:B_9 // NOD +DATA LOCATION RST_DLY_3_:A_12 // NOD +DATA LOCATION RST_DLY_4_:A_5 // NOD +DATA LOCATION RST_DLY_5_:B_13 // NOD +DATA LOCATION RST_DLY_6_:B_2 // NOD +DATA LOCATION RST_DLY_7_:B_10 // NOD +DATA LOCATION RW:G_0_71 // IO {RN_RW} +DATA LOCATION RW_000:H_0_80 // IO {RN_RW_000} +DATA LOCATION SIZE_0_:G_12_70 // IO +DATA LOCATION SIZE_1_:H_12_79 // IO +DATA LOCATION SIZE_DMA_0_:G_13 // NOD +DATA LOCATION SIZE_DMA_1_:G_9 // NOD +DATA LOCATION SM_AMIGA_0_:B_5 // NOD +DATA LOCATION SM_AMIGA_1_:F_8 // NOD +DATA LOCATION SM_AMIGA_2_:F_2 // NOD +DATA LOCATION SM_AMIGA_3_:F_13 // NOD +DATA LOCATION SM_AMIGA_4_:F_10 // NOD +DATA LOCATION SM_AMIGA_5_:F_12 // NOD +DATA LOCATION SM_AMIGA_6_:F_9 // NOD +DATA LOCATION SM_AMIGA_i_7_:F_4 // NOD +DATA LOCATION UDS_000:D_8_32 // IO +DATA LOCATION VMA:D_0_35 // IO {RN_VMA} +DATA LOCATION VPA:*_*_36 // INP +DATA LOCATION cpu_est_0_:F_1 // NOD +DATA LOCATION cpu_est_1_:D_9 // NOD +DATA LOCATION cpu_est_2_:D_13 // NOD +DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_HIGH:C_1 // NOD +DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_LOW:C_9 // NOD +DATA LOCATION inst_AS_000_DMA:A_8 // NOD +DATA LOCATION inst_AS_000_INT:C_5 // NOD +DATA LOCATION inst_AS_030_000_SYNC:C_4 // NOD +DATA LOCATION inst_AS_030_D0:H_5 // NOD +DATA LOCATION inst_BGACK_030_INT_D:H_13 // NOD +DATA LOCATION inst_CLK_000_D0:D_6 // NOD +DATA LOCATION inst_CLK_000_D1:G_2 // NOD +DATA LOCATION inst_CLK_000_NE:E_8 // NOD +DATA LOCATION inst_CLK_000_NE_D0:D_2 // NOD +DATA LOCATION inst_CLK_000_PE:F_0 // NOD +DATA LOCATION inst_CLK_030_H:A_13 // NOD +DATA LOCATION inst_CLK_OUT_PRE_50:E_9 // NOD +DATA LOCATION inst_CLK_OUT_PRE_D:E_13 // NOD +DATA LOCATION inst_DS_000_DMA:A_9 // NOD +DATA LOCATION inst_DS_000_ENABLE:F_5 // NOD +DATA LOCATION inst_DS_030_D0:A_15 // NOD +DATA LOCATION inst_DTACK_D0:C_2 // NOD +DATA LOCATION inst_LDS_000_INT:C_8 // NOD +DATA LOCATION inst_UDS_000_INT:C_12 // NOD +DATA LOCATION inst_VPA_D:B_14 // NOD +DATA LOCATION inst_nEXP_SPACE_D0reg:G_5 // NOD +DATA LOCATION nEXP_SPACE:*_*_14 // INP +DATA IO_DIR A0:BI +DATA IO_DIR A1:IN +DATA IO_DIR AMIGA_ADDR_ENABLE:OUT +DATA IO_DIR AMIGA_BUS_DATA_DIR:OUT +DATA IO_DIR AMIGA_BUS_ENABLE_HIGH:OUT +DATA IO_DIR AMIGA_BUS_ENABLE_LOW:OUT +DATA IO_DIR AS_000:BI +DATA IO_DIR AS_030:BI +DATA IO_DIR AVEC:OUT +DATA IO_DIR A_16_:IN +DATA IO_DIR A_17_:IN +DATA IO_DIR A_18_:IN +DATA IO_DIR A_19_:IN +DATA IO_DIR A_20_:IN +DATA IO_DIR A_21_:IN +DATA IO_DIR A_22_:IN +DATA IO_DIR A_23_:IN +DATA IO_DIR A_24_:IN +DATA IO_DIR A_25_:IN +DATA IO_DIR A_26_:IN +DATA IO_DIR A_27_:IN +DATA IO_DIR A_28_:IN +DATA IO_DIR A_29_:IN +DATA IO_DIR A_30_:IN +DATA IO_DIR A_31_:IN +DATA IO_DIR BERR:BI +DATA IO_DIR BGACK_000:IN +DATA IO_DIR BGACK_030:OUT +DATA IO_DIR BG_000:OUT +DATA IO_DIR BG_030:IN +DATA IO_DIR CIIN:OUT +DATA IO_DIR CLK_000:IN +DATA IO_DIR CLK_030:IN +DATA IO_DIR CLK_DIV_OUT:OUT +DATA IO_DIR CLK_EXP:OUT +DATA IO_DIR CLK_OSZI:IN +DATA IO_DIR DSACK1:OUT +DATA IO_DIR DS_030:BI +DATA IO_DIR DTACK:IN +DATA IO_DIR E:OUT +DATA IO_DIR FC_0_:IN +DATA IO_DIR FC_1_:IN +DATA IO_DIR FPU_CS:OUT +DATA IO_DIR FPU_SENSE:IN +DATA IO_DIR IPL_030_0_:OUT +DATA IO_DIR IPL_030_1_:OUT +DATA IO_DIR IPL_030_2_:OUT +DATA IO_DIR IPL_0_:IN +DATA IO_DIR IPL_1_:IN +DATA IO_DIR IPL_2_:IN +DATA IO_DIR LDS_000:BI +DATA IO_DIR RESET:OUT +DATA IO_DIR RST:IN +DATA IO_DIR RW:BI +DATA IO_DIR RW_000:BI +DATA IO_DIR SIZE_0_:BI +DATA IO_DIR SIZE_1_:BI +DATA IO_DIR UDS_000:BI +DATA IO_DIR VMA:OUT +DATA IO_DIR VPA:IN +DATA IO_DIR nEXP_SPACE:IN +DATA GLB_CLOCK CLK_OSZI +DATA PW_LEVEL A_28_:1 +DATA SLEW A_28_:1 +DATA PW_LEVEL A_27_:1 +DATA SLEW A_27_:1 +DATA PW_LEVEL SIZE_1_:1 +DATA SLEW SIZE_1_:1 +DATA PW_LEVEL A_26_:1 +DATA SLEW A_26_:1 +DATA PW_LEVEL A_25_:1 +DATA SLEW A_25_:1 +DATA PW_LEVEL A_31_:1 +DATA SLEW A_31_:1 +DATA PW_LEVEL A_24_:1 +DATA SLEW A_24_:1 +DATA PW_LEVEL A_23_:1 +DATA SLEW A_23_:1 +DATA PW_LEVEL A_22_:1 +DATA SLEW A_22_:1 +DATA PW_LEVEL A_21_:1 +DATA SLEW A_21_:1 +DATA PW_LEVEL IPL_2_:1 +DATA SLEW IPL_2_:1 +DATA PW_LEVEL A_20_:1 +DATA SLEW A_20_:1 +DATA PW_LEVEL A_19_:1 +DATA SLEW A_19_:1 +DATA PW_LEVEL FC_1_:1 +DATA SLEW FC_1_:1 +DATA PW_LEVEL A_18_:1 +DATA SLEW A_18_:1 +DATA PW_LEVEL AS_030:1 +DATA SLEW AS_030:1 +DATA PW_LEVEL A_17_:1 +DATA SLEW A_17_:1 +DATA PW_LEVEL AS_000:1 +DATA SLEW AS_000:1 +DATA PW_LEVEL A_16_:1 +DATA SLEW A_16_:1 +DATA PW_LEVEL DS_030:1 +DATA SLEW DS_030:1 +DATA PW_LEVEL UDS_000:1 +DATA SLEW UDS_000:1 +DATA PW_LEVEL LDS_000:1 +DATA SLEW LDS_000:1 +DATA PW_LEVEL A1:1 +DATA SLEW A1:1 +DATA SLEW nEXP_SPACE:1 +DATA PW_LEVEL BERR:1 +DATA SLEW BERR:1 +DATA PW_LEVEL BG_030:1 +DATA SLEW BG_030:1 +DATA PW_LEVEL BGACK_000:1 +DATA SLEW BGACK_000:1 +DATA SLEW CLK_030:1 +DATA SLEW CLK_000:1 +DATA SLEW CLK_OSZI:1 +DATA PW_LEVEL CLK_DIV_OUT:1 +DATA SLEW CLK_DIV_OUT:0 +DATA PW_LEVEL CLK_EXP:1 +DATA SLEW CLK_EXP:0 +DATA PW_LEVEL IPL_1_:1 +DATA SLEW IPL_1_:1 +DATA PW_LEVEL FPU_CS:1 +DATA SLEW FPU_CS:0 +DATA PW_LEVEL IPL_0_:1 +DATA SLEW IPL_0_:1 +DATA PW_LEVEL FPU_SENSE:1 +DATA SLEW FPU_SENSE:1 +DATA PW_LEVEL FC_0_:1 +DATA SLEW FC_0_:1 +DATA PW_LEVEL DTACK:1 +DATA SLEW DTACK:1 +DATA PW_LEVEL AVEC:1 +DATA SLEW AVEC:1 +DATA SLEW VPA:1 +DATA SLEW RST:1 +DATA PW_LEVEL AMIGA_ADDR_ENABLE:1 +DATA SLEW AMIGA_ADDR_ENABLE:0 +DATA PW_LEVEL AMIGA_BUS_DATA_DIR:1 +DATA SLEW AMIGA_BUS_DATA_DIR:0 +DATA PW_LEVEL AMIGA_BUS_ENABLE_LOW:1 +DATA SLEW AMIGA_BUS_ENABLE_LOW:0 +DATA PW_LEVEL AMIGA_BUS_ENABLE_HIGH:1 +DATA SLEW AMIGA_BUS_ENABLE_HIGH:0 +DATA PW_LEVEL CIIN:1 +DATA SLEW CIIN:1 +DATA PW_LEVEL SIZE_0_:1 +DATA SLEW SIZE_0_:1 +DATA PW_LEVEL A_30_:1 +DATA SLEW A_30_:1 +DATA PW_LEVEL A_29_:1 +DATA SLEW A_29_:1 +DATA PW_LEVEL IPL_030_2_:1 +DATA SLEW IPL_030_2_:1 +DATA PW_LEVEL RW_000:1 +DATA SLEW RW_000:1 +DATA PW_LEVEL A0:1 +DATA SLEW A0:1 +DATA PW_LEVEL BG_000:1 +DATA SLEW BG_000:1 +DATA PW_LEVEL BGACK_030:1 +DATA SLEW BGACK_030:1 +DATA PW_LEVEL IPL_030_1_:1 +DATA SLEW IPL_030_1_:1 +DATA PW_LEVEL IPL_030_0_:1 +DATA SLEW IPL_030_0_:1 +DATA PW_LEVEL DSACK1:1 +DATA SLEW DSACK1:1 +DATA PW_LEVEL E:1 +DATA SLEW E:1 +DATA PW_LEVEL VMA:1 +DATA SLEW VMA:1 +DATA PW_LEVEL RESET:1 +DATA SLEW RESET:1 +DATA PW_LEVEL RW:1 +DATA SLEW RW:1 +DATA PW_LEVEL cpu_est_0_:1 +DATA SLEW cpu_est_0_:1 +DATA PW_LEVEL cpu_est_1_:1 +DATA SLEW cpu_est_1_:1 +DATA PW_LEVEL inst_AS_000_INT:1 +DATA SLEW inst_AS_000_INT:1 +DATA PW_LEVEL SM_AMIGA_5_:1 +DATA SLEW SM_AMIGA_5_:1 +DATA PW_LEVEL inst_AMIGA_BUS_ENABLE_DMA_LOW:1 +DATA SLEW inst_AMIGA_BUS_ENABLE_DMA_LOW:1 +DATA PW_LEVEL inst_AS_030_D0:1 +DATA SLEW inst_AS_030_D0:1 +DATA PW_LEVEL inst_nEXP_SPACE_D0reg:1 +DATA SLEW inst_nEXP_SPACE_D0reg:1 +DATA PW_LEVEL inst_DS_030_D0:1 +DATA SLEW inst_DS_030_D0:1 +DATA PW_LEVEL inst_AS_030_000_SYNC:1 +DATA SLEW inst_AS_030_000_SYNC:1 +DATA PW_LEVEL inst_BGACK_030_INT_D:1 +DATA SLEW inst_BGACK_030_INT_D:1 +DATA PW_LEVEL inst_AS_000_DMA:1 +DATA SLEW inst_AS_000_DMA:1 +DATA PW_LEVEL inst_DS_000_DMA:1 +DATA SLEW inst_DS_000_DMA:1 +DATA PW_LEVEL CYCLE_DMA_0_:1 +DATA SLEW CYCLE_DMA_0_:1 +DATA PW_LEVEL CYCLE_DMA_1_:1 +DATA SLEW CYCLE_DMA_1_:1 +DATA PW_LEVEL SIZE_DMA_0_:1 +DATA SLEW SIZE_DMA_0_:1 +DATA PW_LEVEL SIZE_DMA_1_:1 +DATA SLEW SIZE_DMA_1_:1 +DATA PW_LEVEL inst_VPA_D:1 +DATA SLEW inst_VPA_D:1 +DATA PW_LEVEL inst_UDS_000_INT:1 +DATA SLEW inst_UDS_000_INT:1 +DATA PW_LEVEL inst_LDS_000_INT:1 +DATA SLEW inst_LDS_000_INT:1 +DATA PW_LEVEL inst_CLK_OUT_PRE_D:1 +DATA SLEW inst_CLK_OUT_PRE_D:1 +DATA PW_LEVEL inst_DTACK_D0:1 +DATA SLEW inst_DTACK_D0:1 +DATA PW_LEVEL inst_CLK_OUT_PRE_50:1 +DATA SLEW inst_CLK_OUT_PRE_50:1 +DATA PW_LEVEL inst_CLK_000_D1:1 +DATA SLEW inst_CLK_000_D1:1 +DATA PW_LEVEL inst_CLK_000_D0:1 +DATA SLEW inst_CLK_000_D0:1 +DATA PW_LEVEL inst_CLK_000_PE:1 +DATA SLEW inst_CLK_000_PE:1 +DATA PW_LEVEL CLK_000_P_SYNC_9_:1 +DATA SLEW CLK_000_P_SYNC_9_:1 +DATA PW_LEVEL inst_CLK_000_NE:1 +DATA SLEW inst_CLK_000_NE:1 +DATA PW_LEVEL N_96_i:1 +DATA SLEW N_96_i:1 +DATA PW_LEVEL CLK_000_N_SYNC_11_:1 +DATA SLEW CLK_000_N_SYNC_11_:1 +DATA PW_LEVEL cpu_est_2_:1 +DATA SLEW cpu_est_2_:1 +DATA PW_LEVEL IPL_D0_0_:1 +DATA SLEW IPL_D0_0_:1 +DATA PW_LEVEL IPL_D0_1_:1 +DATA SLEW IPL_D0_1_:1 +DATA PW_LEVEL IPL_D0_2_:1 +DATA SLEW IPL_D0_2_:1 +DATA PW_LEVEL SM_AMIGA_3_:1 +DATA SLEW SM_AMIGA_3_:1 +DATA PW_LEVEL inst_CLK_000_NE_D0:1 +DATA SLEW inst_CLK_000_NE_D0:1 +DATA PW_LEVEL SM_AMIGA_0_:1 +DATA SLEW SM_AMIGA_0_:1 +DATA PW_LEVEL inst_AMIGA_BUS_ENABLE_DMA_HIGH:1 +DATA SLEW inst_AMIGA_BUS_ENABLE_DMA_HIGH:1 +DATA PW_LEVEL SM_AMIGA_6_:1 +DATA SLEW SM_AMIGA_6_:1 +DATA PW_LEVEL RST_DLY_0_:1 +DATA SLEW RST_DLY_0_:1 +DATA PW_LEVEL RST_DLY_1_:1 +DATA SLEW RST_DLY_1_:1 +DATA PW_LEVEL RST_DLY_2_:1 +DATA SLEW RST_DLY_2_:1 +DATA PW_LEVEL RST_DLY_3_:1 +DATA SLEW RST_DLY_3_:1 +DATA PW_LEVEL RST_DLY_4_:1 +DATA SLEW RST_DLY_4_:1 +DATA PW_LEVEL RST_DLY_5_:1 +DATA SLEW RST_DLY_5_:1 +DATA PW_LEVEL RST_DLY_6_:1 +DATA SLEW RST_DLY_6_:1 +DATA PW_LEVEL RST_DLY_7_:1 +DATA SLEW RST_DLY_7_:1 +DATA PW_LEVEL CLK_000_P_SYNC_0_:1 +DATA SLEW CLK_000_P_SYNC_0_:1 +DATA PW_LEVEL CLK_000_P_SYNC_1_:1 +DATA SLEW CLK_000_P_SYNC_1_:1 +DATA PW_LEVEL CLK_000_P_SYNC_2_:1 +DATA SLEW CLK_000_P_SYNC_2_:1 +DATA PW_LEVEL CLK_000_P_SYNC_3_:1 +DATA SLEW CLK_000_P_SYNC_3_:1 +DATA PW_LEVEL CLK_000_P_SYNC_4_:1 +DATA SLEW CLK_000_P_SYNC_4_:1 +DATA PW_LEVEL CLK_000_P_SYNC_5_:1 +DATA SLEW CLK_000_P_SYNC_5_:1 +DATA PW_LEVEL CLK_000_P_SYNC_6_:1 +DATA SLEW CLK_000_P_SYNC_6_:1 +DATA PW_LEVEL CLK_000_P_SYNC_7_:1 +DATA SLEW CLK_000_P_SYNC_7_:1 +DATA PW_LEVEL CLK_000_P_SYNC_8_:1 +DATA SLEW CLK_000_P_SYNC_8_:1 +DATA PW_LEVEL CLK_000_N_SYNC_0_:1 +DATA SLEW CLK_000_N_SYNC_0_:1 +DATA PW_LEVEL CLK_000_N_SYNC_1_:1 +DATA SLEW CLK_000_N_SYNC_1_:1 +DATA PW_LEVEL CLK_000_N_SYNC_2_:1 +DATA SLEW CLK_000_N_SYNC_2_:1 +DATA PW_LEVEL CLK_000_N_SYNC_3_:1 +DATA SLEW CLK_000_N_SYNC_3_:1 +DATA PW_LEVEL CLK_000_N_SYNC_4_:1 +DATA SLEW CLK_000_N_SYNC_4_:1 +DATA PW_LEVEL CLK_000_N_SYNC_5_:1 +DATA SLEW CLK_000_N_SYNC_5_:1 +DATA PW_LEVEL CLK_000_N_SYNC_6_:1 +DATA SLEW CLK_000_N_SYNC_6_:1 +DATA PW_LEVEL CLK_000_N_SYNC_7_:1 +DATA SLEW CLK_000_N_SYNC_7_:1 +DATA PW_LEVEL CLK_000_N_SYNC_8_:1 +DATA SLEW CLK_000_N_SYNC_8_:1 +DATA PW_LEVEL CLK_000_N_SYNC_9_:1 +DATA SLEW CLK_000_N_SYNC_9_:1 +DATA PW_LEVEL CLK_000_N_SYNC_10_:1 +DATA SLEW CLK_000_N_SYNC_10_:1 +DATA PW_LEVEL inst_CLK_030_H:1 +DATA SLEW inst_CLK_030_H:1 +DATA PW_LEVEL SM_AMIGA_1_:1 +DATA SLEW SM_AMIGA_1_:1 +DATA PW_LEVEL SM_AMIGA_4_:1 +DATA SLEW SM_AMIGA_4_:1 +DATA PW_LEVEL SM_AMIGA_2_:1 +DATA SLEW SM_AMIGA_2_:1 +DATA PW_LEVEL inst_DS_000_ENABLE:1 +DATA SLEW inst_DS_000_ENABLE:1 +DATA PW_LEVEL SM_AMIGA_i_7_:1 +DATA SLEW SM_AMIGA_i_7_:1 +DATA PW_LEVEL CIIN_0:1 +DATA SLEW CIIN_0:1 +DATA PW_LEVEL RN_IPL_030_2_:1 +DATA PW_LEVEL RN_RW_000:1 +DATA PW_LEVEL RN_A0:1 +DATA PW_LEVEL RN_BG_000:1 +DATA PW_LEVEL RN_BGACK_030:1 +DATA PW_LEVEL RN_IPL_030_1_:1 +DATA PW_LEVEL RN_IPL_030_0_:1 +DATA PW_LEVEL RN_DSACK1:1 +DATA PW_LEVEL RN_E:1 +DATA PW_LEVEL RN_VMA:1 +DATA PW_LEVEL RN_RESET:1 +DATA PW_LEVEL RN_RW:1 +END diff --git a/Logic/68030_tk.grp b/Logic/68030_tk.grp new file mode 100644 index 0000000..e641f7b --- /dev/null +++ b/Logic/68030_tk.grp @@ -0,0 +1,28 @@ + +GROUP MACH_SEG_A inst_DS_000_DMA inst_CLK_030_H RST_DLY_3_ RST_DLY_1_ RST_DLY_4_ + inst_AS_000_DMA CYCLE_DMA_1_ CYCLE_DMA_0_ inst_DS_030_D0 CLK_000_P_SYNC_9_ + CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_N_SYNC_4_ CLK_000_N_SYNC_8_ + DS_030 AVEC +GROUP MACH_SEG_B RESET RN_RESET IPL_030_1_ RN_IPL_030_1_ IPL_030_0_ RN_IPL_030_0_ + IPL_030_2_ RN_IPL_030_2_ RST_DLY_0_ RST_DLY_2_ RST_DLY_5_ RST_DLY_6_ + RST_DLY_7_ SM_AMIGA_0_ inst_VPA_D IPL_D0_0_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ + CLK_000_N_SYNC_1_ CLK_EXP +GROUP MACH_SEG_C inst_AS_030_000_SYNC inst_LDS_000_INT inst_UDS_000_INT + inst_AS_000_INT inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AMIGA_BUS_ENABLE_DMA_HIGH + inst_DTACK_D0 CLK_000_N_SYNC_5_ AMIGA_BUS_ENABLE_LOW +GROUP MACH_SEG_D VMA RN_VMA BG_000 RN_BG_000 cpu_est_1_ cpu_est_2_ CLK_000_P_SYNC_0_ + CLK_000_N_SYNC_0_ inst_CLK_000_D0 CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ + CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ inst_CLK_000_NE_D0 LDS_000 UDS_000 + AMIGA_BUS_ENABLE_HIGH AMIGA_ADDR_ENABLE +GROUP MACH_SEG_E inst_CLK_000_NE inst_CLK_OUT_PRE_D inst_CLK_OUT_PRE_50 + CIIN BERR AMIGA_BUS_DATA_DIR AS_000 CIIN_0 +GROUP MACH_SEG_F SM_AMIGA_i_7_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_6_ inst_DS_000_ENABLE + SM_AMIGA_1_ SM_AMIGA_4_ SM_AMIGA_5_ cpu_est_0_ inst_CLK_000_PE N_96_i + +GROUP MACH_SEG_G A0 RN_A0 RW RN_RW E RN_E SIZE_DMA_0_ SIZE_DMA_1_ inst_nEXP_SPACE_D0reg + IPL_D0_1_ IPL_D0_2_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_5_ + CLK_000_P_SYNC_6_ CLK_000_N_SYNC_9_ inst_CLK_000_D1 SIZE_0_ CLK_DIV_OUT + +GROUP MACH_SEG_H DSACK1 RN_DSACK1 RW_000 RN_RW_000 BGACK_030 RN_BGACK_030 + inst_AS_030_D0 inst_BGACK_030_INT_D CLK_000_N_SYNC_11_ CLK_000_N_SYNC_10_ + FPU_CS AS_030 SIZE_1_ \ No newline at end of file diff --git a/Logic/68030_tk.imp b/Logic/68030_tk.imp new file mode 100644 index 0000000..18a49d6 --- /dev/null +++ b/Logic/68030_tk.imp @@ -0,0 +1,2 @@ +No pin assignment or valid property. +No source constraints were imported. \ No newline at end of file diff --git a/Logic/68030_tk.ipr b/Logic/68030_tk.ipr index f211431..48c85be 100644 --- a/Logic/68030_tk.ipr +++ b/Logic/68030_tk.ipr @@ -1 +1 @@ -8775301*z5Kd \ No newline at end of file +2753107yCgL9*V \ No newline at end of file diff --git a/Logic/68030_tk.jed b/Logic/68030_tk.jed new file mode 100644 index 0000000..e6617b9 --- /dev/null +++ b/Logic/68030_tk.jed @@ -0,0 +1,1115 @@ +|--------------------------------------------| +|- ispLEVER Fitter Report File -| +|- Version 1.8.00.04.29.14 -| +|- (c)Copyright, Lattice Semiconductor 2002 -| +|--------------------------------------------| + + +TITLE: +AUTHOR: +PATTERN: +COMPANY: +REVISION: +DATE: Wed May 13 22:59:29 2015 + +ABEL mach447a + * +QP100* +QF54096* +G0*F0* +NOTE Part Number : M4A5-128/64-10VC * +NOTE Handling of Preplacements No Change * +NOTE Use placement data from 68030_tk.vct * +NOTE Global clocks routable as PT clocks? N * +NOTE 22V10/MACH1XX/2XX S/R Compatibility? Y * +NOTE SET/RESET treated as DONT_CARE? N * +NOTE Reduce Unforced Global Clocks? N * +NOTE Iterate between partitioning and place/route? Y * +NOTE Balanced partitioning? Y * +NOTE Reduce Routes Per Placement? N * +NOTE Spread Placement? Y * +NOTE Run Time Upper Bound in 15 minutes 0 * +NOTE Zero Hold Time For Input Registers? Y * +NOTE Table of pin names and numbers* +NOTE PINS A_28_:15 A_27_:16 SIZE_1_:79 A_26_:17 A_25_:18* +NOTE PINS A_31_:4 A_24_:19 A_23_:85 A_22_:84 A_21_:94 IPL_2_:68* +NOTE PINS A_20_:93 A_19_:97 FC_1_:58 A_18_:95 AS_030:82 A_17_:59* +NOTE PINS AS_000:42 A_16_:96 DS_030:98 UDS_000:32 LDS_000:31* +NOTE PINS A1:60 nEXP_SPACE:14 BERR:41 BG_030:21 BGACK_000:28* +NOTE PINS CLK_030:64 CLK_000:11 CLK_OSZI:61 CLK_DIV_OUT:65* +NOTE PINS CLK_EXP:10 IPL_1_:56 FPU_CS:78 IPL_0_:67 FPU_SENSE:91* +NOTE PINS FC_0_:57 DTACK:30 AVEC:92 VPA:36 RST:86 AMIGA_ADDR_ENABLE:33* +NOTE PINS AMIGA_BUS_DATA_DIR:48 AMIGA_BUS_ENABLE_LOW:20 AMIGA_BUS_ENABLE_HIGH:34* +NOTE PINS CIIN:47 SIZE_0_:70 A_30_:5 A_29_:6 IPL_030_2_:9* +NOTE PINS RW_000:80 A0:69 BG_000:29 BGACK_030:83 IPL_030_1_:7* +NOTE PINS IPL_030_0_:8 DSACK1:81 E:66 VMA:35 RESET:3 RW:71* +NOTE Table of node names and numbers* +NOTE NODES RN_SIZE_1_:287 RN_AS_030:281 RN_AS_000:203 RN_DS_030:101 * +NOTE NODES RN_UDS_000:185 RN_LDS_000:191 RN_BERR:197 RN_SIZE_0_:263 * +NOTE NODES RN_IPL_030_2_:131 RN_RW_000:269 RN_A0:257 RN_BG_000:175 * +NOTE NODES RN_BGACK_030:275 RN_IPL_030_1_:143 RN_IPL_030_0_:137 * +NOTE NODES RN_DSACK1:283 RN_E:251 RN_VMA:173 RN_RESET:125 * +NOTE NODES RN_RW:245 cpu_est_0_:223 cpu_est_1_:187 inst_AS_000_INT:157 * +NOTE NODES SM_AMIGA_5_:239 inst_AMIGA_BUS_ENABLE_DMA_LOW:163 * +NOTE NODES inst_AS_030_D0:277 inst_nEXP_SPACE_D0reg:253 * +NOTE NODES inst_DS_030_D0:124 inst_AS_030_000_SYNC:155 inst_BGACK_030_INT_D:289 * +NOTE NODES inst_AS_000_DMA:113 inst_DS_000_DMA:115 CYCLE_DMA_0_:110 * +NOTE NODES CYCLE_DMA_1_:104 SIZE_DMA_0_:265 SIZE_DMA_1_:259 * +NOTE NODES inst_VPA_D:146 inst_UDS_000_INT:167 inst_LDS_000_INT:161 * +NOTE NODES inst_CLK_OUT_PRE_D:217 inst_DTACK_D0:152 inst_CLK_OUT_PRE_50:211 * +NOTE NODES inst_CLK_000_D1:248 inst_CLK_000_D0:182 inst_CLK_000_PE:221 * +NOTE NODES CLK_000_P_SYNC_9_:118 inst_CLK_000_NE:209 N_96_i:230 * +NOTE NODES CLK_000_N_SYNC_11_:278 cpu_est_2_:193 IPL_D0_0_:148 * +NOTE NODES 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11111011111111* +E1 +1 +01111100 +1 +01110010 +1 +00000000 +1 +01000011 +1 +01011001 +1 +00000000 +1 +10001110 +1 +10000010 +1 +* +C979F* +U00000000000000000000000000000000* +06AF diff --git a/Logic/68030_tk.l0 b/Logic/68030_tk.l0 new file mode 100644 index 0000000..0bb3cee --- /dev/null +++ b/Logic/68030_tk.l0 @@ -0,0 +1 @@ + -ck Min -ce On -ar On -ap On -oe On -split 16 -clust 5 -xor on -speed -ifb yes -sr no -device M4A5 diff --git a/Logic/68030_tk.l2v b/Logic/68030_tk.l2v new file mode 100644 index 0000000..e69de29 diff --git a/Logic/68030_tk.lco b/Logic/68030_tk.lco new file mode 100644 index 0000000..5af8739 --- /dev/null +++ b/Logic/68030_tk.lco @@ -0,0 +1,259 @@ +[DEVICE] +Family = M4A5; +PartType = M4A5-128/64; +Package = 100TQFP; +PartNumber = M4A5-128/64-10VC; +Speed = -10; +Operating_condition = COM; +EN_Segment = No; +Pin_MC_1to1 = No; +EN_PinReserve_IO = Yes; +EN_PinReserve_BIDIR = Yes; +Voltage = 5.0; + +[REVISION] +RCS = "$Revision: 1.2 $"; +Parent = m4a5.lci; +SDS_File = m4a5.sds; +Design = 68030_tk.tt4; +DATE = 5/13/15; +TIME = 22:59:29; +Source_Format = Pure_VHDL; +Type = TT2; +Pre_Fit_Time = 1; + +[IGNORE ASSIGNMENTS] +Pin_Assignments = No; +Pin_Keep_Block = No; +Pin_Keep_Segment = No; +Group_Assignments = No; +Macrocell_Assignments = No; +Macrocell_Keep_Block = No; +Macrocell_Keep_Segment = No; +Pin_Reservation = No; +Block_Reservation = No; +Segment_Reservation = No; +Timing_Constraints = No; + +[CLEAR ASSIGNMENTS] +Pin_Assignments = No; +Pin_Keep_Block = No; +Pin_Keep_Segment = No; +Group_Assignments = No; +Macrocell_Assignments = No; +Macrocell_Keep_Block = No; +Macrocell_Keep_Segment = No; +Pin_Reservation = No; +Block_Reservation = No; +Segment_Reservation = No; +Timing_Constraints = No; + +[BACKANNOTATE ASSIGNMENTS] +Pin_Block = No; +Pin_Macrocell_Block = No; +Routing = No; + +[GLOBAL CONSTRAINTS] +Max_PTerm_Split = 16; +Max_PTerm_Collapse = 16; +Max_Pin_Percent = 100; +Max_Macrocell_Percent = 100; +Max_GLB_Input_Percent = 100; +Max_Seg_In_Percent = 100; +Logic_Reduction = Yes; +XOR_Synthesis = Yes; +DT_Synthesis = Yes; +Node_Collapse = Yes; +Run_Time = 0; +Set_Reset_Dont_Care = No; +Clock_Optimize = No; +In_Reg_Optimize = Yes; +Balanced_Partitioning = Yes; +Device_max_fanin = 33; +Device_max_pterms = 20; +Usercode = 0; +Usercode_Format = Hex; + +[LOCATION ASSIGNMENTS] +Layer = OFF; +A_28_ = pin,15,-,C,-; +A_27_ = pin,16,-,C,-; +SIZE_1_ = pin,79,-,H,-; +A_26_ = pin,17,-,C,-; +A_25_ = pin,18,-,C,-; +A_31_ = pin,4,-,B,-; +A_24_ = pin,19,-,C,-; +A_23_ = pin,85,-,H,-; +A_22_ = pin,84,-,H,-; +A_21_ = pin,94,-,A,-; +IPL_2_ = pin,68,-,G,-; +A_20_ = pin,93,-,A,-; +A_19_ = pin,97,-,A,-; +FC_1_ = pin,58,-,F,-; +A_18_ = pin,95,-,A,-; +AS_030 = pin,82,-,H,-; +A_17_ = pin,59,-,F,-; +AS_000 = pin,42,-,E,-; +A_16_ = pin,96,-,A,-; +DS_030 = pin,98,-,A,-; +UDS_000 = pin,32,-,D,-; +LDS_000 = pin,31,-,D,-; +A1 = pin,60,-,F,-; +nEXP_SPACE = pin,14,-,-,-; +BERR = pin,41,-,E,-; +BG_030 = pin,21,-,C,-; +BGACK_000 = pin,28,-,D,-; +CLK_030 = pin,64,-,-,-; +CLK_000 = pin,11,-,-,-; +CLK_OSZI = pin,61,-,-,-; +CLK_DIV_OUT = pin,65,-,G,-; +CLK_EXP = pin,10,-,B,-; +IPL_1_ = pin,56,-,F,-; +FPU_CS = pin,78,-,H,-; +IPL_0_ = pin,67,-,G,-; +FPU_SENSE = pin,91,-,A,-; +FC_0_ = pin,57,-,F,-; +DTACK = pin,30,-,D,-; +AVEC = pin,92,-,A,-; +VPA = pin,36,-,-,-; +RST = pin,86,-,-,-; +AMIGA_ADDR_ENABLE = pin,33,-,D,-; +AMIGA_BUS_DATA_DIR = pin,48,-,E,-; +AMIGA_BUS_ENABLE_LOW = pin,20,-,C,-; +AMIGA_BUS_ENABLE_HIGH = pin,34,-,D,-; +CIIN = pin,47,-,E,-; +SIZE_0_ = pin,70,-,G,-; +A_30_ = pin,5,-,B,-; +A_29_ = pin,6,-,B,-; +IPL_030_2_ = pin,9,-,B,-; +RW_000 = pin,80,-,H,-; +A0 = pin,69,-,G,-; +BG_000 = pin,29,-,D,-; +BGACK_030 = pin,83,-,H,-; +IPL_030_1_ = pin,7,-,B,-; +IPL_030_0_ = pin,8,-,B,-; +DSACK1 = pin,81,-,H,-; +E = pin,66,-,G,-; +VMA = pin,35,-,D,-; +RESET = pin,3,-,B,-; +RW = pin,71,-,G,-; +cpu_est_0_ = node,-,-,F,1; +cpu_est_1_ = node,-,-,D,9; +inst_AS_000_INT = node,-,-,C,5; +SM_AMIGA_5_ = node,-,-,F,12; +inst_AMIGA_BUS_ENABLE_DMA_LOW = node,-,-,C,9; +inst_AS_030_D0 = node,-,-,H,5; +inst_nEXP_SPACE_D0reg = node,-,-,G,5; +inst_DS_030_D0 = node,-,-,A,15; +inst_AS_030_000_SYNC = node,-,-,C,4; +inst_BGACK_030_INT_D = node,-,-,H,13; +inst_AS_000_DMA = node,-,-,A,8; +inst_DS_000_DMA = node,-,-,A,9; +CYCLE_DMA_0_ = node,-,-,A,6; +CYCLE_DMA_1_ = node,-,-,A,2; +SIZE_DMA_0_ = node,-,-,G,13; +SIZE_DMA_1_ = node,-,-,G,9; +inst_VPA_D = node,-,-,B,14; +inst_UDS_000_INT = node,-,-,C,12; +inst_LDS_000_INT = node,-,-,C,8; +inst_CLK_OUT_PRE_D = node,-,-,E,13; +inst_DTACK_D0 = node,-,-,C,2; +inst_CLK_OUT_PRE_50 = node,-,-,E,9; +inst_CLK_000_D1 = node,-,-,G,2; +inst_CLK_000_D0 = node,-,-,D,6; +inst_CLK_000_PE = node,-,-,F,0; +CLK_000_P_SYNC_9_ = node,-,-,A,11; +inst_CLK_000_NE = node,-,-,E,8; +N_96_i = node,-,-,F,6; +CLK_000_N_SYNC_11_ = node,-,-,H,6; +cpu_est_2_ = node,-,-,D,13; +IPL_D0_0_ = node,-,-,B,15; +IPL_D0_1_ = node,-,-,G,15; +IPL_D0_2_ = node,-,-,G,11; +SM_AMIGA_3_ = node,-,-,F,13; +inst_CLK_000_NE_D0 = node,-,-,D,2; +SM_AMIGA_0_ = node,-,-,B,5; +inst_AMIGA_BUS_ENABLE_DMA_HIGH = node,-,-,C,1; +SM_AMIGA_6_ = node,-,-,F,9; +RST_DLY_0_ = node,-,-,B,6; +RST_DLY_1_ = node,-,-,A,1; +RST_DLY_2_ = node,-,-,B,9; +RST_DLY_3_ = node,-,-,A,12; +RST_DLY_4_ = node,-,-,A,5; +RST_DLY_5_ = node,-,-,B,13; +RST_DLY_6_ = node,-,-,B,2; +RST_DLY_7_ = node,-,-,B,10; +CLK_000_P_SYNC_0_ = node,-,-,D,15; +CLK_000_P_SYNC_1_ = node,-,-,G,7; +CLK_000_P_SYNC_2_ = node,-,-,G,3; +CLK_000_P_SYNC_3_ = node,-,-,B,11; +CLK_000_P_SYNC_4_ = node,-,-,B,7; +CLK_000_P_SYNC_5_ = node,-,-,G,14; +CLK_000_P_SYNC_6_ = node,-,-,G,10; +CLK_000_P_SYNC_7_ = node,-,-,A,7; +CLK_000_P_SYNC_8_ = node,-,-,A,3; +CLK_000_N_SYNC_0_ = node,-,-,D,11; +CLK_000_N_SYNC_1_ = node,-,-,B,3; +CLK_000_N_SYNC_2_ = node,-,-,D,7; +CLK_000_N_SYNC_3_ = node,-,-,D,3; +CLK_000_N_SYNC_4_ = node,-,-,A,14; +CLK_000_N_SYNC_5_ = node,-,-,C,13; +CLK_000_N_SYNC_6_ = node,-,-,D,14; +CLK_000_N_SYNC_7_ = node,-,-,D,10; +CLK_000_N_SYNC_8_ = node,-,-,A,10; +CLK_000_N_SYNC_9_ = node,-,-,G,6; +CLK_000_N_SYNC_10_ = node,-,-,H,2; +inst_CLK_030_H = node,-,-,A,13; +SM_AMIGA_1_ = node,-,-,F,8; +SM_AMIGA_4_ = node,-,-,F,10; +SM_AMIGA_2_ = node,-,-,F,2; +inst_DS_000_ENABLE = node,-,-,F,5; +SM_AMIGA_i_7_ = node,-,-,F,4; +CIIN_0 = node,-,-,E,5; + +[GROUP ASSIGNMENTS] +Layer = OFF; + +[RESOURCE RESERVATIONS] +Layer = OFF; + +[SLEWRATE] +Default = SLOW; +FAST = CLK_DIV_OUT,CLK_EXP,FPU_CS,AMIGA_BUS_DATA_DIR,AMIGA_BUS_ENABLE_LOW,AMIGA_ADDR_ENABLE,AMIGA_BUS_ENABLE_HIGH; + +[PULLUP] +Default = Up; + +[NETLIST/DELAY FORMAT] +Delay_File = SDF; +Netlist = VHDL; + +[OSM BYPASS] + +[FITTER REPORT FORMAT] +Fitter_Options = Yes; +Pinout_Diagram = No; +Pinout_Listing = Yes; +Detailed_Block_Segment_Summary = Yes; +Input_Signal_List = Yes; +Output_Signal_List = Yes; +Bidir_Signal_List = Yes; +Node_Signal_List = Yes; +Signal_Fanout_List = Yes; +Block_Segment_Fanin_List = Yes; +Postfit_Eqn = Yes; +Prefit_Eqn = Yes; +Page_Break = Yes; + +[POWER] +Powerlevel = Low,High; +Default = High; +Low = H,G,F,E,D,C,B,A; +Type = GLB; + +[SOURCE CONSTRAINT OPTION] + +[TIMING ANALYZER] +Last_source=; +Last_source_type=Fmax; + diff --git a/Logic/68030_tk.out b/Logic/68030_tk.out new file mode 100644 index 0000000..5935574 --- /dev/null +++ b/Logic/68030_tk.out @@ -0,0 +1,728 @@ + +135 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 4 1 2 5 7 40 -1 1 0 21 + 79 RW_000 5 358 7 3 0 4 6 79 -1 3 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 70 RW 5 366 6 2 2 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 68 A0 5 359 6 1 0 68 -1 3 0 21 + 97 DS_030 5 -1 0 1 3 97 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 65 E 5 363 6 0 65 -1 5 0 21 + 80 DSACK1 5 362 7 0 80 -1 4 0 21 + 34 VMA 5 364 3 0 34 -1 3 0 21 + 82 BGACK_030 5 361 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 360 3 0 28 -1 2 0 21 + 8 IPL_030_2_ 5 355 1 0 8 -1 2 0 21 + 7 IPL_030_0_ 5 357 1 0 7 -1 2 0 21 + 6 IPL_030_1_ 5 356 1 0 6 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 5 365 1 0 2 -1 1 0 21 + 361 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 2 0 21 + 299 inst_nEXP_SPACE_D0reg 3 -1 1 7 0 1 3 4 5 6 7 -1 -1 1 0 21 + 298 inst_AS_030_D0 3 -1 7 6 1 2 3 4 5 7 -1 -1 1 0 21 + 365 RN_RESET 3 2 1 5 0 3 4 6 7 2 -1 1 0 21 + 319 inst_CLK_000_NE 3 -1 1 5 1 2 3 5 7 -1 -1 1 0 21 + 317 inst_CLK_000_PE 3 -1 0 5 0 2 3 5 7 -1 -1 1 0 21 + 352 SM_AMIGA_i_7_ 3 -1 5 4 1 3 5 7 -1 -1 15 0 21 + 323 inst_CLK_000_NE_D0 3 -1 7 4 2 3 5 6 -1 -1 1 0 21 + 363 RN_E 3 65 6 3 2 3 6 65 -1 5 0 21 + 294 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 5 0 21 + 321 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 4 0 21 + 348 SM_AMIGA_1_ 3 -1 2 3 2 5 7 -1 -1 3 0 21 + 296 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 + 293 cpu_est_0_ 3 -1 3 3 2 3 6 -1 -1 2 0 21 + 312 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 309 inst_VPA_D 3 -1 6 3 2 3 5 -1 -1 1 0 21 + 303 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 301 inst_AS_030_000_SYNC 3 -1 1 2 1 5 -1 -1 7 0 21 + 322 SM_AMIGA_3_ 3 -1 2 2 2 5 -1 -1 5 0 21 + 350 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 4 0 21 + 311 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 4 0 21 + 364 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 + 351 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 + 349 SM_AMIGA_4_ 3 -1 2 2 2 5 -1 -1 3 0 21 + 326 SM_AMIGA_6_ 3 -1 5 2 0 5 -1 -1 3 0 21 + 310 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 + 308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 325 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 324 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 2 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 + 295 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 + 345 CLK_000_N_SYNC_9_ 3 -1 6 2 1 7 -1 -1 1 0 21 + 316 inst_CLK_000_D0 3 -1 1 2 3 5 -1 -1 1 0 21 + 315 inst_CLK_000_D1 3 -1 5 2 3 5 -1 -1 1 0 21 + 313 inst_DTACK_D0 3 -1 2 2 2 5 -1 -1 1 0 21 + 302 inst_BGACK_030_INT_D 3 -1 7 2 1 6 -1 -1 1 0 21 + 304 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 347 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 362 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 359 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 358 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 306 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21 + 366 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 360 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 357 RN_IPL_030_0_ 3 7 1 1 1 7 -1 2 0 21 + 356 RN_IPL_030_1_ 3 6 1 1 1 6 -1 2 0 21 + 355 RN_IPL_030_2_ 3 8 1 1 1 8 -1 2 0 21 + 354 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 305 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21 + 353 N_302 3 -1 2 1 5 -1 -1 1 0 21 + 346 CLK_000_N_SYNC_10_ 3 -1 1 1 7 -1 -1 1 0 21 + 344 CLK_000_N_SYNC_8_ 3 -1 1 1 6 -1 -1 1 0 21 + 343 CLK_000_N_SYNC_7_ 3 -1 5 1 1 -1 -1 1 0 21 + 342 CLK_000_N_SYNC_6_ 3 -1 2 1 5 -1 -1 1 0 21 + 341 CLK_000_N_SYNC_5_ 3 -1 2 1 2 -1 -1 1 0 21 + 340 CLK_000_N_SYNC_4_ 3 -1 5 1 2 -1 -1 1 0 21 + 339 CLK_000_N_SYNC_3_ 3 -1 5 1 5 -1 -1 1 0 21 + 338 CLK_000_N_SYNC_2_ 3 -1 1 1 5 -1 -1 1 0 21 + 337 CLK_000_N_SYNC_1_ 3 -1 5 1 1 -1 -1 1 0 21 + 336 CLK_000_N_SYNC_0_ 3 -1 3 1 5 -1 -1 1 0 21 + 335 CLK_000_P_SYNC_8_ 3 -1 3 1 3 -1 -1 1 0 21 + 334 CLK_000_P_SYNC_7_ 3 -1 4 1 3 -1 -1 1 0 21 + 333 CLK_000_P_SYNC_6_ 3 -1 1 1 4 -1 -1 1 0 21 + 332 CLK_000_P_SYNC_5_ 3 -1 2 1 1 -1 -1 1 0 21 + 331 CLK_000_P_SYNC_4_ 3 -1 0 1 2 -1 -1 1 0 21 + 330 CLK_000_P_SYNC_3_ 3 -1 6 1 0 -1 -1 1 0 21 + 329 CLK_000_P_SYNC_2_ 3 -1 0 1 6 -1 -1 1 0 21 + 328 CLK_000_P_SYNC_1_ 3 -1 6 1 0 -1 -1 1 0 21 + 327 CLK_000_P_SYNC_0_ 3 -1 3 1 6 -1 -1 1 0 21 + 320 CLK_000_N_SYNC_11_ 3 -1 7 1 1 -1 -1 1 0 21 + 318 CLK_000_P_SYNC_9_ 3 -1 3 1 0 -1 -1 1 0 21 + 314 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 300 inst_DS_030_D0 3 -1 3 1 0 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_19_ 1 -1 -1 3 1 4 7 96 -1 + 95 A_16_ 1 -1 -1 3 1 4 7 95 -1 + 94 A_18_ 1 -1 -1 3 1 4 7 94 -1 + 58 A_17_ 1 -1 -1 3 1 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 1 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 1 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 59 A1 1 -1 -1 1 6 59 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 29 DTACK 1 -1 -1 1 2 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 1 13 -1 + 10 CLK_000 1 -1 -1 1 1 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +135 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 4 1 2 5 7 40 -1 1 0 21 + 79 RW_000 5 358 7 3 0 4 6 79 -1 3 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 70 RW 5 366 6 2 2 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 68 A0 5 359 6 1 0 68 -1 3 0 21 + 97 DS_030 5 -1 0 1 3 97 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 65 E 5 363 6 0 65 -1 5 0 21 + 80 DSACK1 5 362 7 0 80 -1 4 0 21 + 34 VMA 5 364 3 0 34 -1 3 0 21 + 82 BGACK_030 5 361 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 360 3 0 28 -1 2 0 21 + 8 IPL_030_2_ 5 355 1 0 8 -1 2 0 21 + 7 IPL_030_0_ 5 357 1 0 7 -1 2 0 21 + 6 IPL_030_1_ 5 356 1 0 6 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 5 365 1 0 2 -1 1 0 21 + 361 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 2 0 21 + 299 inst_nEXP_SPACE_D0reg 3 -1 1 7 0 1 3 4 5 6 7 -1 -1 1 0 21 + 298 inst_AS_030_D0 3 -1 7 6 1 2 3 4 5 7 -1 -1 1 0 21 + 365 RN_RESET 3 2 1 5 0 3 4 6 7 2 -1 1 0 21 + 319 inst_CLK_000_NE 3 -1 1 5 1 2 3 5 7 -1 -1 1 0 21 + 317 inst_CLK_000_PE 3 -1 0 5 0 2 3 5 7 -1 -1 1 0 21 + 352 SM_AMIGA_i_7_ 3 -1 5 4 1 3 5 7 -1 -1 15 0 21 + 323 inst_CLK_000_NE_D0 3 -1 7 4 2 3 5 6 -1 -1 1 0 21 + 363 RN_E 3 65 6 3 2 3 6 65 -1 5 0 21 + 294 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 5 0 21 + 321 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 4 0 21 + 348 SM_AMIGA_1_ 3 -1 2 3 2 5 7 -1 -1 3 0 21 + 296 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 + 293 cpu_est_0_ 3 -1 3 3 2 3 6 -1 -1 2 0 21 + 312 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 309 inst_VPA_D 3 -1 6 3 2 3 5 -1 -1 1 0 21 + 303 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 301 inst_AS_030_000_SYNC 3 -1 1 2 1 5 -1 -1 7 0 21 + 322 SM_AMIGA_3_ 3 -1 2 2 2 5 -1 -1 5 0 21 + 350 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 4 0 21 + 311 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 4 0 21 + 364 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 + 351 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 + 349 SM_AMIGA_4_ 3 -1 2 2 2 5 -1 -1 3 0 21 + 326 SM_AMIGA_6_ 3 -1 5 2 0 5 -1 -1 3 0 21 + 310 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 + 308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 325 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 324 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 2 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 + 295 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 + 345 CLK_000_N_SYNC_9_ 3 -1 6 2 1 7 -1 -1 1 0 21 + 316 inst_CLK_000_D0 3 -1 1 2 3 5 -1 -1 1 0 21 + 315 inst_CLK_000_D1 3 -1 5 2 3 5 -1 -1 1 0 21 + 313 inst_DTACK_D0 3 -1 2 2 2 5 -1 -1 1 0 21 + 302 inst_BGACK_030_INT_D 3 -1 7 2 1 6 -1 -1 1 0 21 + 304 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 347 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 362 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 359 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 358 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 306 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21 + 366 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 360 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 357 RN_IPL_030_0_ 3 7 1 1 1 7 -1 2 0 21 + 356 RN_IPL_030_1_ 3 6 1 1 1 6 -1 2 0 21 + 355 RN_IPL_030_2_ 3 8 1 1 1 8 -1 2 0 21 + 354 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 305 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21 + 353 N_302 3 -1 2 1 5 -1 -1 1 0 21 + 346 CLK_000_N_SYNC_10_ 3 -1 1 1 7 -1 -1 1 0 21 + 344 CLK_000_N_SYNC_8_ 3 -1 1 1 6 -1 -1 1 0 21 + 343 CLK_000_N_SYNC_7_ 3 -1 5 1 1 -1 -1 1 0 21 + 342 CLK_000_N_SYNC_6_ 3 -1 2 1 5 -1 -1 1 0 21 + 341 CLK_000_N_SYNC_5_ 3 -1 2 1 2 -1 -1 1 0 21 + 340 CLK_000_N_SYNC_4_ 3 -1 5 1 2 -1 -1 1 0 21 + 339 CLK_000_N_SYNC_3_ 3 -1 5 1 5 -1 -1 1 0 21 + 338 CLK_000_N_SYNC_2_ 3 -1 1 1 5 -1 -1 1 0 21 + 337 CLK_000_N_SYNC_1_ 3 -1 5 1 1 -1 -1 1 0 21 + 336 CLK_000_N_SYNC_0_ 3 -1 3 1 5 -1 -1 1 0 21 + 335 CLK_000_P_SYNC_8_ 3 -1 3 1 3 -1 -1 1 0 21 + 334 CLK_000_P_SYNC_7_ 3 -1 4 1 3 -1 -1 1 0 21 + 333 CLK_000_P_SYNC_6_ 3 -1 1 1 4 -1 -1 1 0 21 + 332 CLK_000_P_SYNC_5_ 3 -1 2 1 1 -1 -1 1 0 21 + 331 CLK_000_P_SYNC_4_ 3 -1 0 1 2 -1 -1 1 0 21 + 330 CLK_000_P_SYNC_3_ 3 -1 6 1 0 -1 -1 1 0 21 + 329 CLK_000_P_SYNC_2_ 3 -1 0 1 6 -1 -1 1 0 21 + 328 CLK_000_P_SYNC_1_ 3 -1 6 1 0 -1 -1 1 0 21 + 327 CLK_000_P_SYNC_0_ 3 -1 3 1 6 -1 -1 1 0 21 + 320 CLK_000_N_SYNC_11_ 3 -1 7 1 1 -1 -1 1 0 21 + 318 CLK_000_P_SYNC_9_ 3 -1 3 1 0 -1 -1 1 0 21 + 314 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 300 inst_DS_030_D0 3 -1 3 1 0 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_19_ 1 -1 -1 3 1 4 7 96 -1 + 95 A_16_ 1 -1 -1 3 1 4 7 95 -1 + 94 A_18_ 1 -1 -1 3 1 4 7 94 -1 + 58 A_17_ 1 -1 -1 3 1 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 1 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 1 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 59 A1 1 -1 -1 1 6 59 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 29 DTACK 1 -1 -1 1 2 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 1 13 -1 + 10 CLK_000 1 -1 -1 1 1 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +135 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 5 0 1 2 5 7 40 -1 1 0 21 + 79 RW_000 5 358 7 3 0 4 6 79 -1 3 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 68 A0 5 359 6 2 2 6 68 -1 3 0 21 + 70 RW 5 366 6 2 2 7 70 -1 2 0 21 + 97 DS_030 5 -1 0 2 0 3 97 -1 1 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 6 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 6 69 -1 1 0 21 + 65 E 5 363 6 0 65 -1 5 0 21 + 80 DSACK1 5 362 7 0 80 -1 4 0 21 + 34 VMA 5 364 3 0 34 -1 3 0 21 + 82 BGACK_030 5 361 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 360 3 0 28 -1 2 0 21 + 8 IPL_030_2_ 5 357 1 0 8 -1 2 0 21 + 7 IPL_030_0_ 5 356 1 0 7 -1 2 0 21 + 6 IPL_030_1_ 5 355 1 0 6 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 5 365 1 0 2 -1 1 0 21 + 361 RN_BGACK_030 3 82 7 7 0 2 3 4 5 6 7 82 -1 2 0 21 + 299 inst_nEXP_SPACE_D0reg 3 -1 3 7 0 1 3 4 5 6 7 -1 -1 1 0 21 + 365 RN_RESET 3 2 1 5 0 3 4 6 7 2 -1 1 0 21 + 317 inst_CLK_000_PE 3 -1 3 5 0 1 2 3 7 -1 -1 1 0 21 + 298 inst_AS_030_D0 3 -1 7 5 2 3 4 5 7 -1 -1 1 0 21 + 353 SM_AMIGA_i_7_ 3 -1 2 4 1 3 5 7 -1 -1 8 0 21 + 296 SM_AMIGA_5_ 3 -1 1 4 1 2 5 7 -1 -1 3 0 21 + 319 inst_CLK_000_NE 3 -1 3 4 0 1 3 5 -1 -1 1 0 21 + 363 RN_E 3 65 6 3 2 3 6 65 -1 5 0 21 + 294 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 5 0 21 + 351 SM_AMIGA_2_ 3 -1 2 3 0 1 2 -1 -1 4 0 21 + 321 cpu_est_2_ 3 -1 6 3 2 3 6 -1 -1 4 0 21 + 348 SM_AMIGA_1_ 3 -1 0 3 0 1 7 -1 -1 3 0 21 + 326 SM_AMIGA_6_ 3 -1 1 3 1 2 6 -1 -1 3 0 21 + 324 SM_AMIGA_0_ 3 -1 1 3 1 2 7 -1 -1 2 0 21 + 293 cpu_est_0_ 3 -1 6 3 2 3 6 -1 -1 2 0 21 + 323 inst_CLK_000_NE_D0 3 -1 5 3 2 3 6 -1 -1 1 0 21 + 312 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 303 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 301 inst_AS_030_000_SYNC 3 -1 5 2 1 5 -1 -1 7 0 21 + 322 SM_AMIGA_3_ 3 -1 2 2 1 2 -1 -1 5 0 21 + 311 inst_LDS_000_INT 3 -1 6 2 3 6 -1 -1 4 0 21 + 364 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 + 352 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 + 349 SM_AMIGA_4_ 3 -1 1 2 1 2 -1 -1 3 0 21 + 310 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 + 308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 325 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 2 3 5 -1 -1 2 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21 + 295 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 + 316 inst_CLK_000_D0 3 -1 5 2 1 3 -1 -1 1 0 21 + 309 inst_VPA_D 3 -1 0 2 2 3 -1 -1 1 0 21 + 302 inst_BGACK_030_INT_D 3 -1 7 2 5 6 -1 -1 1 0 21 + 300 inst_DS_030_D0 3 -1 0 2 2 6 -1 -1 1 0 21 + 304 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 347 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 350 N_125_i_2 3 -1 1 1 2 -1 -1 6 0 21 + 362 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 359 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 358 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 306 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21 + 366 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 360 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 357 RN_IPL_030_2_ 3 8 1 1 1 8 -1 2 0 21 + 356 RN_IPL_030_0_ 3 7 1 1 1 7 -1 2 0 21 + 355 RN_IPL_030_1_ 3 6 1 1 1 6 -1 2 0 21 + 354 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 305 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21 + 346 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21 + 345 CLK_000_N_SYNC_9_ 3 -1 0 1 7 -1 -1 1 0 21 + 344 CLK_000_N_SYNC_8_ 3 -1 1 1 0 -1 -1 1 0 21 + 343 CLK_000_N_SYNC_7_ 3 -1 0 1 1 -1 -1 1 0 21 + 342 CLK_000_N_SYNC_6_ 3 -1 5 1 0 -1 -1 1 0 21 + 341 CLK_000_N_SYNC_5_ 3 -1 5 1 5 -1 -1 1 0 21 + 340 CLK_000_N_SYNC_4_ 3 -1 0 1 5 -1 -1 1 0 21 + 339 CLK_000_N_SYNC_3_ 3 -1 5 1 0 -1 -1 1 0 21 + 338 CLK_000_N_SYNC_2_ 3 -1 1 1 5 -1 -1 1 0 21 + 337 CLK_000_N_SYNC_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 336 CLK_000_N_SYNC_0_ 3 -1 1 1 1 -1 -1 1 0 21 + 335 CLK_000_P_SYNC_8_ 3 -1 6 1 0 -1 -1 1 0 21 + 334 CLK_000_P_SYNC_7_ 3 -1 4 1 6 -1 -1 1 0 21 + 333 CLK_000_P_SYNC_6_ 3 -1 5 1 4 -1 -1 1 0 21 + 332 CLK_000_P_SYNC_5_ 3 -1 3 1 5 -1 -1 1 0 21 + 331 CLK_000_P_SYNC_4_ 3 -1 3 1 3 -1 -1 1 0 21 + 330 CLK_000_P_SYNC_3_ 3 -1 2 1 3 -1 -1 1 0 21 + 329 CLK_000_P_SYNC_2_ 3 -1 6 1 2 -1 -1 1 0 21 + 328 CLK_000_P_SYNC_1_ 3 -1 6 1 6 -1 -1 1 0 21 + 327 CLK_000_P_SYNC_0_ 3 -1 1 1 6 -1 -1 1 0 21 + 320 CLK_000_N_SYNC_11_ 3 -1 7 1 3 -1 -1 1 0 21 + 318 CLK_000_P_SYNC_9_ 3 -1 0 1 3 -1 -1 1 0 21 + 315 inst_CLK_000_D1 3 -1 3 1 1 -1 -1 1 0 21 + 314 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 313 inst_DTACK_D0 3 -1 6 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 59 A1 1 -1 -1 1 5 59 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 29 DTACK 1 -1 -1 1 6 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 3 13 -1 + 10 CLK_000 1 -1 -1 1 5 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +146 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 6 1 2 3 5 6 7 40 -1 1 0 21 + 79 RW_000 5 367 7 3 0 4 6 79 -1 3 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 70 RW 5 377 6 2 3 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 68 A0 5 368 6 1 0 68 -1 3 0 21 + 97 DS_030 5 -1 0 1 3 97 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 8 IPL_030_2_ 5 366 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 372 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 370 1 0 6 -1 10 0 21 + 65 E 5 374 6 0 65 -1 5 0 21 + 80 DSACK1 5 373 7 0 80 -1 4 0 21 + 34 VMA 5 375 3 0 34 -1 3 0 21 + 82 BGACK_030 5 371 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 369 3 0 28 -1 2 0 21 + 2 RESET 5 376 1 0 2 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 371 RN_BGACK_030 3 82 7 7 0 2 3 4 5 6 7 82 -1 2 0 21 + 376 RN_RESET 3 2 1 6 0 1 3 4 6 7 2 -1 2 0 21 + 317 inst_CLK_000_PE 3 -1 2 6 0 1 2 3 5 7 -1 -1 1 0 21 + 299 inst_nEXP_SPACE_D0reg 3 -1 1 6 0 3 4 5 6 7 -1 -1 1 0 21 + 296 SM_AMIGA_5_ 3 -1 1 5 1 3 5 6 7 -1 -1 3 0 21 + 298 inst_AS_030_D0 3 -1 7 5 3 4 5 6 7 -1 -1 1 0 21 + 319 inst_CLK_000_NE 3 -1 0 4 1 2 3 5 -1 -1 1 0 21 + 364 SM_AMIGA_i_7_ 3 -1 5 3 3 5 7 -1 -1 13 0 21 + 374 RN_E 3 65 6 3 2 3 6 65 -1 5 0 21 + 325 SM_AMIGA_3_ 3 -1 2 3 2 3 5 -1 -1 5 0 21 + 294 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 5 0 21 + 321 cpu_est_2_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 + 361 SM_AMIGA_4_ 3 -1 3 3 2 3 5 -1 -1 3 0 21 + 329 SM_AMIGA_6_ 3 -1 5 3 0 1 5 -1 -1 3 0 21 + 308 SIZE_DMA_1_ 3 -1 0 3 0 6 7 -1 -1 3 0 21 + 293 cpu_est_0_ 3 -1 2 3 2 3 6 -1 -1 2 0 21 + 326 inst_CLK_000_NE_D0 3 -1 5 3 2 3 6 -1 -1 1 0 21 + 316 inst_CLK_000_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 + 312 inst_CLK_OUT_PRE_D 3 -1 1 3 1 6 7 -1 -1 1 0 21 + 302 inst_BGACK_030_INT_D 3 -1 7 3 0 5 6 -1 -1 1 0 21 + 303 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 334 RST_DLY_3_ 3 -1 1 2 1 2 -1 -1 6 0 21 + 333 RST_DLY_2_ 3 -1 2 2 1 2 -1 -1 5 0 21 + 362 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 4 0 21 + 336 RST_DLY_5_ 3 -1 2 2 1 2 -1 -1 4 0 21 + 332 RST_DLY_1_ 3 -1 2 2 1 2 -1 -1 4 0 21 + 311 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 4 0 21 + 375 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 + 360 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 337 RST_DLY_6_ 3 -1 2 2 1 2 -1 -1 3 0 21 + 331 RST_DLY_0_ 3 -1 2 2 1 2 -1 -1 3 0 21 + 310 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 + 307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 338 RST_DLY_7_ 3 -1 2 2 1 2 -1 -1 2 0 21 + 335 RST_DLY_4_ 3 -1 1 2 1 2 -1 -1 2 1 21 + 328 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 2 0 3 -1 -1 2 0 21 + 327 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 2 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21 + 295 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21 + 309 inst_VPA_D 3 -1 6 2 2 3 -1 -1 1 0 21 + 372 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 370 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 366 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 304 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 359 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 301 inst_AS_030_000_SYNC 3 -1 5 1 5 -1 -1 7 0 21 + 373 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 368 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 367 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 363 inst_DS_000_ENABLE 3 -1 3 1 3 -1 -1 3 0 21 + 306 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21 + 377 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 369 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 365 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 330 N_180_i 3 -1 2 1 5 -1 -1 2 0 21 + 305 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21 + 358 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21 + 357 CLK_000_N_SYNC_9_ 3 -1 4 1 7 -1 -1 1 0 21 + 356 CLK_000_N_SYNC_8_ 3 -1 3 1 4 -1 -1 1 0 21 + 355 CLK_000_N_SYNC_7_ 3 -1 6 1 3 -1 -1 1 0 21 + 354 CLK_000_N_SYNC_6_ 3 -1 0 1 6 -1 -1 1 0 21 + 353 CLK_000_N_SYNC_5_ 3 -1 6 1 0 -1 -1 1 0 21 + 352 CLK_000_N_SYNC_4_ 3 -1 2 1 6 -1 -1 1 0 21 + 351 CLK_000_N_SYNC_3_ 3 -1 1 1 2 -1 -1 1 0 21 + 350 CLK_000_N_SYNC_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 349 CLK_000_N_SYNC_1_ 3 -1 2 1 1 -1 -1 1 0 21 + 348 CLK_000_N_SYNC_0_ 3 -1 5 1 2 -1 -1 1 0 21 + 347 CLK_000_P_SYNC_8_ 3 -1 5 1 2 -1 -1 1 0 21 + 346 CLK_000_P_SYNC_7_ 3 -1 3 1 5 -1 -1 1 0 21 + 345 CLK_000_P_SYNC_6_ 3 -1 5 1 3 -1 -1 1 0 21 + 344 CLK_000_P_SYNC_5_ 3 -1 6 1 5 -1 -1 1 0 21 + 343 CLK_000_P_SYNC_4_ 3 -1 1 1 6 -1 -1 1 0 21 + 342 CLK_000_P_SYNC_3_ 3 -1 6 1 1 -1 -1 1 0 21 + 341 CLK_000_P_SYNC_2_ 3 -1 6 1 6 -1 -1 1 0 21 + 340 CLK_000_P_SYNC_1_ 3 -1 6 1 6 -1 -1 1 0 21 + 339 CLK_000_P_SYNC_0_ 3 -1 5 1 6 -1 -1 1 0 21 + 324 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21 + 323 IPL_D0_1_ 3 -1 5 1 1 -1 -1 1 0 21 + 322 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 + 320 CLK_000_N_SYNC_11_ 3 -1 7 1 0 -1 -1 1 0 21 + 318 CLK_000_P_SYNC_9_ 3 -1 2 1 2 -1 -1 1 0 21 + 315 inst_CLK_000_D1 3 -1 4 1 5 -1 -1 1 0 21 + 314 inst_CLK_OUT_PRE_50 3 -1 1 1 1 -1 -1 1 0 21 + 313 inst_DTACK_D0 3 -1 2 1 2 -1 -1 1 0 21 + 300 inst_DS_030_D0 3 -1 3 1 0 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 3 67 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 55 IPL_1_ 1 -1 -1 2 1 5 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 59 A1 1 -1 -1 1 0 59 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 29 DTACK 1 -1 -1 1 2 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 1 13 -1 + 10 CLK_000 1 -1 -1 1 4 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +146 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 4 1 2 5 7 40 -1 1 0 21 + 79 RW_000 5 367 7 3 0 4 6 79 -1 3 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 70 RW 5 377 6 2 5 7 70 -1 2 0 21 + 97 DS_030 5 -1 0 2 0 3 97 -1 1 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 68 A0 5 368 6 1 2 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 2 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21 + 8 IPL_030_2_ 5 366 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 372 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 371 1 0 6 -1 10 0 21 + 65 E 5 374 6 0 65 -1 5 0 21 + 80 DSACK1 5 373 7 0 80 -1 4 0 21 + 34 VMA 5 375 3 0 34 -1 3 0 21 + 82 BGACK_030 5 370 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 369 3 0 28 -1 2 0 21 + 2 RESET 5 376 1 0 2 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 299 inst_nEXP_SPACE_D0reg 3 -1 6 7 0 2 3 4 5 6 7 -1 -1 1 0 21 + 376 RN_RESET 3 2 1 6 0 1 3 4 6 7 2 -1 2 0 21 + 370 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 2 0 21 + 317 inst_CLK_000_PE 3 -1 5 5 0 1 3 5 7 -1 -1 1 0 21 + 298 inst_AS_030_D0 3 -1 7 5 2 3 4 5 7 -1 -1 1 0 21 + 364 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 14 0 21 + 319 inst_CLK_000_NE 3 -1 4 4 0 1 3 5 -1 -1 1 0 21 + 374 RN_E 3 65 6 3 3 5 6 65 -1 5 0 21 + 294 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 5 0 21 + 322 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 + 360 SM_AMIGA_1_ 3 -1 5 3 1 5 7 -1 -1 3 0 21 + 296 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 + 328 SM_AMIGA_0_ 3 -1 1 3 1 5 7 -1 -1 2 0 21 + 293 cpu_est_0_ 3 -1 5 3 3 5 6 -1 -1 2 0 21 + 327 inst_CLK_000_NE_D0 3 -1 3 3 3 5 6 -1 -1 1 0 21 + 316 inst_CLK_000_D0 3 -1 3 3 3 5 6 -1 -1 1 0 21 + 303 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 301 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21 + 334 RST_DLY_3_ 3 -1 0 2 0 1 -1 -1 6 0 21 + 333 RST_DLY_2_ 3 -1 1 2 0 1 -1 -1 5 0 21 + 336 RST_DLY_5_ 3 -1 1 2 0 1 -1 -1 4 0 21 + 332 RST_DLY_1_ 3 -1 0 2 0 1 -1 -1 4 0 21 + 311 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 4 0 21 + 375 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 363 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 + 337 RST_DLY_6_ 3 -1 1 2 0 1 -1 -1 3 0 21 + 331 RST_DLY_0_ 3 -1 1 2 0 1 -1 -1 3 0 21 + 330 SM_AMIGA_6_ 3 -1 5 2 2 5 -1 -1 3 0 21 + 310 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 + 308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 338 RST_DLY_7_ 3 -1 1 2 0 1 -1 -1 2 0 21 + 335 RST_DLY_4_ 3 -1 0 2 0 1 -1 -1 2 1 21 + 329 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21 + 295 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 315 inst_CLK_000_D1 3 -1 6 2 3 5 -1 -1 1 0 21 + 309 inst_VPA_D 3 -1 1 2 3 5 -1 -1 1 0 21 + 302 inst_BGACK_030_INT_D 3 -1 7 2 2 6 -1 -1 1 0 21 + 372 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 371 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 366 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 304 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 359 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 326 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 + 373 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 362 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21 + 320 N_96_i 3 -1 5 1 5 -1 -1 4 0 21 + 368 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 367 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 361 SM_AMIGA_4_ 3 -1 5 1 5 -1 -1 3 0 21 + 306 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21 + 377 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 369 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 365 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 305 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 + 358 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21 + 357 CLK_000_N_SYNC_9_ 3 -1 6 1 7 -1 -1 1 0 21 + 356 CLK_000_N_SYNC_8_ 3 -1 0 1 6 -1 -1 1 0 21 + 355 CLK_000_N_SYNC_7_ 3 -1 3 1 0 -1 -1 1 0 21 + 354 CLK_000_N_SYNC_6_ 3 -1 3 1 3 -1 -1 1 0 21 + 353 CLK_000_N_SYNC_5_ 3 -1 2 1 3 -1 -1 1 0 21 + 352 CLK_000_N_SYNC_4_ 3 -1 0 1 2 -1 -1 1 0 21 + 351 CLK_000_N_SYNC_3_ 3 -1 3 1 0 -1 -1 1 0 21 + 350 CLK_000_N_SYNC_2_ 3 -1 3 1 3 -1 -1 1 0 21 + 349 CLK_000_N_SYNC_1_ 3 -1 1 1 3 -1 -1 1 0 21 + 348 CLK_000_N_SYNC_0_ 3 -1 3 1 1 -1 -1 1 0 21 + 347 CLK_000_P_SYNC_8_ 3 -1 0 1 0 -1 -1 1 0 21 + 346 CLK_000_P_SYNC_7_ 3 -1 0 1 0 -1 -1 1 0 21 + 345 CLK_000_P_SYNC_6_ 3 -1 6 1 0 -1 -1 1 0 21 + 344 CLK_000_P_SYNC_5_ 3 -1 6 1 6 -1 -1 1 0 21 + 343 CLK_000_P_SYNC_4_ 3 -1 1 1 6 -1 -1 1 0 21 + 342 CLK_000_P_SYNC_3_ 3 -1 1 1 1 -1 -1 1 0 21 + 341 CLK_000_P_SYNC_2_ 3 -1 6 1 1 -1 -1 1 0 21 + 340 CLK_000_P_SYNC_1_ 3 -1 6 1 6 -1 -1 1 0 21 + 339 CLK_000_P_SYNC_0_ 3 -1 3 1 6 -1 -1 1 0 21 + 325 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 + 324 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 + 323 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 + 321 CLK_000_N_SYNC_11_ 3 -1 7 1 4 -1 -1 1 0 21 + 318 CLK_000_P_SYNC_9_ 3 -1 0 1 5 -1 -1 1 0 21 + 314 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 313 inst_DTACK_D0 3 -1 2 1 5 -1 -1 1 0 21 + 312 inst_CLK_OUT_PRE_D 3 -1 4 1 7 -1 -1 1 0 21 + 300 inst_DS_030_D0 3 -1 0 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_18_ 1 -1 -1 3 2 4 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 1 7 63 -1 + 58 A_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 + 55 IPL_1_ 1 -1 -1 2 1 6 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 59 A1 1 -1 -1 1 2 59 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 29 DTACK 1 -1 -1 1 2 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 6 13 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 \ No newline at end of file diff --git a/Logic/68030_tk.plc b/Logic/68030_tk.plc new file mode 100644 index 0000000..574798b --- /dev/null +++ b/Logic/68030_tk.plc @@ -0,0 +1,169 @@ +|--------------------------------------------| +|- ispLEVER Fitter Report File -| +|- Version 1.8.00.04.29.14 -| +|- (c)Copyright, Lattice Semiconductor 2002 -| +|--------------------------------------------| + + +; Source file 68030_tk.tt4 +; FITTER-generated Placements. +; DEVICE mach447a +; DATE Wed May 13 22:59:29 2015 + + +Pin 15 A_28_ +Pin 16 A_27_ +Pin 79 SIZE_1_ Comb ; S6=1 S9=1 Pair 287 +Pin 17 A_26_ +Pin 18 A_25_ +Pin 4 A_31_ +Pin 19 A_24_ +Pin 85 A_23_ +Pin 84 A_22_ +Pin 94 A_21_ +Pin 68 IPL_2_ +Pin 93 A_20_ +Pin 97 A_19_ +Pin 58 FC_1_ +Pin 95 A_18_ +Pin 82 AS_030 Comb ; S6=1 S9=1 Pair 281 +Pin 59 A_17_ +Pin 42 AS_000 Comb ; S6=1 S9=1 Pair 203 +Pin 96 A_16_ +Pin 98 DS_030 Comb ; S6=1 S9=1 Pair 101 +Pin 32 UDS_000 Comb ; S6=1 S9=1 Pair 185 +Pin 31 LDS_000 Comb ; S6=1 S9=1 Pair 191 +Pin 60 A1 +Pin 14 nEXP_SPACE +Pin 41 BERR Comb ; S6=1 S9=1 Pair 197 +Pin 21 BG_030 +Pin 28 BGACK_000 +Pin 64 CLK_030 +Pin 11 CLK_000 +Pin 61 CLK_OSZI +Pin 65 CLK_DIV_OUT Comb ; S6=1 S9=1 Pair 247 +Pin 10 CLK_EXP Comb ; S6=1 S9=1 Pair 127 +Pin 56 IPL_1_ +Pin 78 FPU_CS Comb ; S6=1 S9=1 Pair 271 +Pin 67 IPL_0_ +Pin 91 FPU_SENSE +Pin 57 FC_0_ +Pin 30 DTACK +Pin 92 AVEC Comb ; S6=1 S9=1 Pair 107 +Pin 36 VPA +Pin 86 RST +Pin 33 AMIGA_ADDR_ENABLE Comb ; S6=1 S9=1 Pair 181 +Pin 48 AMIGA_BUS_DATA_DIR Comb ; S6=1 S9=1 Pair 199 +Pin 20 AMIGA_BUS_ENABLE_LOW Comb ; S6=1 S9=1 Pair 149 +Pin 34 AMIGA_BUS_ENABLE_HIGH Comb ; S6=1 S9=1 Pair 179 +Pin 47 CIIN Comb ; S6=1 S9=1 Pair 215 +Pin 70 SIZE_0_ Comb ; S6=1 S9=1 Pair 263 +Pin 5 A_30_ +Pin 6 A_29_ +Pin 9 IPL_030_2_ Reg ; S6=1 S9=1 Pair 131 +Pin 80 RW_000 Reg ; S6=1 S9=1 Pair 269 +Pin 69 A0 Reg ; S6=1 S9=1 Pair 257 +Pin 29 BG_000 Reg ; S6=1 S9=1 Pair 175 +Pin 83 BGACK_030 Reg ; S6=1 S9=1 Pair 275 +Pin 7 IPL_030_1_ Reg ; S6=1 S9=1 Pair 143 +Pin 8 IPL_030_0_ Reg ; S6=1 S9=1 Pair 137 +Pin 81 DSACK1 Reg ; S6=1 S9=1 Pair 283 +Pin 66 E Reg ; S6=1 S9=1 Pair 251 +Pin 35 VMA Reg ; S6=1 S9=1 Pair 173 +Pin 3 RESET Reg ; S6=1 S9=1 Pair 125 +Pin 71 RW Reg ; S6=1 S9=1 Pair 245 +Node 287 RN_SIZE_1_ Comb ; S6=1 S9=1 +Node 281 RN_AS_030 Comb ; S6=1 S9=1 +Node 203 RN_AS_000 Comb ; S6=1 S9=1 +Node 101 RN_DS_030 Comb ; S6=1 S9=1 +Node 185 RN_UDS_000 Comb ; S6=1 S9=1 +Node 191 RN_LDS_000 Comb ; S6=1 S9=1 +Node 197 RN_BERR Comb ; S6=1 S9=1 +Node 263 RN_SIZE_0_ Comb ; S6=1 S9=1 +Node 131 RN_IPL_030_2_ Reg ; S6=1 S9=1 +Node 269 RN_RW_000 Reg ; S6=1 S9=1 +Node 257 RN_A0 Reg ; S6=1 S9=1 +Node 175 RN_BG_000 Reg ; S6=1 S9=1 +Node 275 RN_BGACK_030 Reg ; S6=1 S9=1 +Node 143 RN_IPL_030_1_ Reg ; S6=1 S9=1 +Node 137 RN_IPL_030_0_ Reg ; S6=1 S9=1 +Node 283 RN_DSACK1 Reg ; S6=1 S9=1 +Node 251 RN_E Reg ; S6=1 S9=1 +Node 173 RN_VMA Reg ; S6=1 S9=1 +Node 125 RN_RESET Reg ; S6=1 S9=1 +Node 245 RN_RW Reg ; S6=1 S9=1 +Node 223 cpu_est_0_ Reg ; S6=1 S9=1 +Node 187 cpu_est_1_ Reg ; S6=1 S9=1 +Node 157 inst_AS_000_INT Reg ; S6=1 S9=1 +Node 239 SM_AMIGA_5_ Reg ; S6=1 S9=1 +Node 163 inst_AMIGA_BUS_ENABLE_DMA_LOW Reg ; S6=1 S9=1 +Node 277 inst_AS_030_D0 Reg ; S6=1 S9=1 +Node 253 inst_nEXP_SPACE_D0reg Reg ; S6=1 S9=1 +Node 124 inst_DS_030_D0 Reg ; S6=1 S9=1 +Node 155 inst_AS_030_000_SYNC Reg ; S6=1 S9=1 +Node 289 inst_BGACK_030_INT_D Reg ; S6=1 S9=1 +Node 113 inst_AS_000_DMA Reg ; S6=1 S9=1 +Node 115 inst_DS_000_DMA Reg ; S6=1 S9=1 +Node 110 CYCLE_DMA_0_ Reg ; S6=1 S9=1 +Node 104 CYCLE_DMA_1_ Reg ; S6=1 S9=1 +Node 265 SIZE_DMA_0_ Reg ; S6=1 S9=1 +Node 259 SIZE_DMA_1_ Reg ; S6=1 S9=1 +Node 146 inst_VPA_D Reg ; S6=1 S9=1 +Node 167 inst_UDS_000_INT Reg ; S6=1 S9=1 +Node 161 inst_LDS_000_INT Reg ; S6=1 S9=1 +Node 217 inst_CLK_OUT_PRE_D Reg ; S6=1 S9=1 +Node 152 inst_DTACK_D0 Reg ; S6=1 S9=1 +Node 211 inst_CLK_OUT_PRE_50 Reg ; S6=1 S9=1 +Node 248 inst_CLK_000_D1 Reg ; S6=1 S9=1 +Node 182 inst_CLK_000_D0 Reg ; S6=1 S9=1 +Node 221 inst_CLK_000_PE Reg ; S6=1 S9=1 +Node 118 CLK_000_P_SYNC_9_ Reg ; S6=1 S9=1 +Node 209 inst_CLK_000_NE Reg ; S6=1 S9=1 +Node 230 N_96_i Comb ; S6=1 S9=1 +Node 278 CLK_000_N_SYNC_11_ Reg ; S6=1 S9=1 +Node 193 cpu_est_2_ Reg ; S6=1 S9=1 +Node 148 IPL_D0_0_ Reg ; S6=1 S9=1 +Node 268 IPL_D0_1_ Reg ; S6=1 S9=1 +Node 262 IPL_D0_2_ Reg ; S6=1 S9=1 +Node 241 SM_AMIGA_3_ Reg ; S6=1 S9=1 +Node 176 inst_CLK_000_NE_D0 Reg ; S6=1 S9=1 +Node 133 SM_AMIGA_0_ Reg ; S6=1 S9=1 +Node 151 inst_AMIGA_BUS_ENABLE_DMA_HIGH Reg ; S6=1 S9=1 +Node 235 SM_AMIGA_6_ Reg ; S6=1 S9=1 +Node 134 RST_DLY_0_ Reg ; S6=1 S9=1 +Node 103 RST_DLY_1_ Reg ; S6=1 S9=1 +Node 139 RST_DLY_2_ Reg ; S6=1 S9=1 +Node 119 RST_DLY_3_ Reg ; S6=1 S9=1 +Node 109 RST_DLY_4_ Reg ; S6=1 S9=1 +Node 145 RST_DLY_5_ Reg ; S6=1 S9=1 +Node 128 RST_DLY_6_ Reg ; S6=1 S9=1 +Node 140 RST_DLY_7_ Reg ; S6=1 S9=1 +Node 196 CLK_000_P_SYNC_0_ Reg ; S6=1 S9=1 +Node 256 CLK_000_P_SYNC_1_ Reg ; S6=1 S9=1 +Node 250 CLK_000_P_SYNC_2_ Reg ; S6=1 S9=1 +Node 142 CLK_000_P_SYNC_3_ Reg ; S6=1 S9=1 +Node 136 CLK_000_P_SYNC_4_ Reg ; S6=1 S9=1 +Node 266 CLK_000_P_SYNC_5_ Reg ; S6=1 S9=1 +Node 260 CLK_000_P_SYNC_6_ Reg ; S6=1 S9=1 +Node 112 CLK_000_P_SYNC_7_ Reg ; S6=1 S9=1 +Node 106 CLK_000_P_SYNC_8_ Reg ; S6=1 S9=1 +Node 190 CLK_000_N_SYNC_0_ Reg ; S6=1 S9=1 +Node 130 CLK_000_N_SYNC_1_ Reg ; S6=1 S9=1 +Node 184 CLK_000_N_SYNC_2_ Reg ; S6=1 S9=1 +Node 178 CLK_000_N_SYNC_3_ Reg ; S6=1 S9=1 +Node 122 CLK_000_N_SYNC_4_ Reg ; S6=1 S9=1 +Node 169 CLK_000_N_SYNC_5_ Reg ; S6=1 S9=1 +Node 194 CLK_000_N_SYNC_6_ Reg ; S6=1 S9=1 +Node 188 CLK_000_N_SYNC_7_ Reg ; S6=1 S9=1 +Node 116 CLK_000_N_SYNC_8_ Reg ; S6=1 S9=1 +Node 254 CLK_000_N_SYNC_9_ Reg ; S6=1 S9=1 +Node 272 CLK_000_N_SYNC_10_ Reg ; S6=1 S9=1 +Node 121 inst_CLK_030_H Reg ; S6=1 S9=1 +Node 233 SM_AMIGA_1_ Reg ; S6=1 S9=1 +Node 236 SM_AMIGA_4_ Reg ; S6=1 S9=1 +Node 224 SM_AMIGA_2_ Reg ; S6=1 S9=1 +Node 229 inst_DS_000_ENABLE Reg ; S6=1 S9=1 +Node 227 SM_AMIGA_i_7_ Reg ; S6=1 S9=1 +Node 205 CIIN_0 Comb ; S6=1 S9=1 +; Unused Pins & Nodes +; -> None Found. diff --git a/Logic/68030_tk.prd b/Logic/68030_tk.prd new file mode 100644 index 0000000..50bdaf1 --- /dev/null +++ b/Logic/68030_tk.prd @@ -0,0 +1,1982 @@ +|--------------------------------------------| +|- ispLEVER Fitter Report File -| +|- Version 1.8.00.04.29.14 -| +|- (c)Copyright, Lattice Semiconductor 2002 -| +|--------------------------------------------| + + +Start: Wed May 13 22:59:29 2015 +End : Wed May 13 22:59:29 2015 $$$ Elapsed time: 00:00:00 +=========================================================================== +Part [C:/ispLever/ispcpld/dat/mach4a/mach447a] Design [68030_tk.tt4] + +* Place/Route options (keycode = 540674) + = Spread Placement: ON + = No. Routing Attempts/Placement 2 + +* Placement Completion + + +- Block +------- IO Pins Available + | +- Macrocells Available | +-- IO Pins Used + | | +- Signals to Place | | +----- Logic Array Inputs + | | | +- Placed | | | +- Array Inputs Used +_|____|____|____|_______________|____|_____________|___|________________ + 0 | 16 | 16 | 16 => 100% | 8 | 8 => 100% | 33 | 30 => 90% + 1 | 16 | 16 | 16 => 100% | 8 | 8 => 100% | 33 | 29 => 87% + 2 | 16 | 9 | 9 => 100% | 8 | 7 => 87% | 33 | 28 => 84% + 3 | 16 | 16 | 16 => 100% | 8 | 8 => 100% | 33 | 29 => 87% + 4 | 16 | 8 | 8 => 100% | 8 | 4 => 50% | 33 | 31 => 93% + 5 | 16 | 11 | 11 => 100% | 8 | 5 => 62% | 33 | 29 => 87% + 6 | 16 | 16 | 16 => 100% | 8 | 7 => 87% | 33 | 26 => 78% + 7 | 16 | 10 | 10 => 100% | 8 | 8 => 100% | 33 | 31 => 93% +---|----|----|------------|-------|------------|-----|------------------ + | Avg number of array inputs in used blocks : 29.13 => 88% + +* Input/Clock Signal count: 32 -> placed: 32 = 100% + + Resources Available Used +----------------------------------------------------------------- + Input Pins : 2 2 => 100% + I/O Pins : 64 55 => 85% + Clock Only Pins : 0 0 => 0% + Clock/Input Pins : 4 4 => 100% + Logic Blocks : 8 8 => 100% + Macrocells : 128 102 => 79% + PT Clusters : 128 59 => 46% + - Single PT Clusters : 128 53 => 41% + Input Registers : 0 + +* Routing Completion: 100% +* Attempts: Place [ 146] Route [ 0] +=========================================================================== + Signal Fanout Table +=========================================================================== + +- Signal Number + | +- Block Location ('+' for dedicated inputs) + | | +- Sig Type + | | | +- Signal-to-Pin Assignment + | | | | Fanout to Logic Blocks Signal Name +___|__|__|____|____________________________________________________________ + 1| 6| IO| 69|=> ..2.|....| A0 + |=> Paired w/: RN_A0 + 2| 5|INP| 60|=> ..2.|....| A1 + 3| 3|OUT| 33|=> ....|....| AMIGA_ADDR_ENABLE + 4| 4|OUT| 48|=> ....|....| AMIGA_BUS_DATA_DIR + 5| 3|OUT| 34|=> ....|....| AMIGA_BUS_ENABLE_HIGH + 6| 2|OUT| 20|=> ....|....| AMIGA_BUS_ENABLE_LOW + 7| 4| IO| 42|=> 0...|4..7| AS_000 + 8| 7| IO| 82|=> ....|4..7| AS_030 + 9| 0|OUT| 92|=> ....|....| AVEC + 10| 0|INP| 96|=> ..2.|4..7| A_16_ + 11| 5|INP| 59|=> ..2.|4..7| A_17_ + 12| 0|INP| 95|=> ..2.|4..7| A_18_ + 13| 0|INP| 97|=> ..2.|4..7| A_19_ + 14| 0|INP| 93|=> ....|4...| A_20_ + 15| 0|INP| 94|=> ....|4...| A_21_ + 16| 7|INP| 84|=> ....|4...| A_22_ + 17| 7|INP| 85|=> ....|4...| A_23_ + 18| 2|INP| 19|=> ....|4...| A_24_ + 19| 2|INP| 18|=> ....|4...| A_25_ + 20| 2|INP| 17|=> ....|4...| A_26_ + 21| 2|INP| 16|=> ....|4...| A_27_ + 22| 2|INP| 15|=> ....|4...| A_28_ + 23| 1|INP| 6|=> ....|4...| A_29_ + 24| 1|INP| 5|=> ....|4...| A_30_ + 25| 1|INP| 4|=> ....|4...| A_31_ + 26| 4| IO| 41|=> .12.|.5.7| BERR + 27| 3|INP| 28|=> ....|4..7| BGACK_000 + 28| 7| IO| 83|=> ....|....| BGACK_030 + |=> Paired w/: RN_BGACK_030 + 29| 3| IO| 29|=> ....|....| BG_000 + |=> Paired w/: RN_BG_000 + 30| 2|INP| 21|=> ...3|....| BG_030 + 31| 4|OUT| 47|=> ....|....| CIIN + 32| 4|NOD| . |=> ....|4...| CIIN_0 + 33| +|INP| 11|=> ...3|....| CLK_000 + 34| 3|NOD| . |=> .1..|....| CLK_000_N_SYNC_0_ + 35| 7|NOD| . |=> ....|...7| CLK_000_N_SYNC_10_ + 36| 7|NOD| . |=> ....|4...| CLK_000_N_SYNC_11_ + 37| 1|NOD| . |=> ...3|....| CLK_000_N_SYNC_1_ + 38| 3|NOD| . |=> ...3|....| CLK_000_N_SYNC_2_ + 39| 3|NOD| . |=> 0...|....| CLK_000_N_SYNC_3_ + 40| 0|NOD| . |=> ..2.|....| CLK_000_N_SYNC_4_ + 41| 2|NOD| . |=> ...3|....| CLK_000_N_SYNC_5_ + 42| 3|NOD| . |=> ...3|....| CLK_000_N_SYNC_6_ + 43| 3|NOD| . |=> 0...|....| CLK_000_N_SYNC_7_ + 44| 0|NOD| . |=> ....|..6.| CLK_000_N_SYNC_8_ + 45| 6|NOD| . |=> ....|...7| CLK_000_N_SYNC_9_ + 46| 3|NOD| . |=> ....|..6.| CLK_000_P_SYNC_0_ + 47| 6|NOD| . |=> ....|..6.| CLK_000_P_SYNC_1_ + 48| 6|NOD| . |=> .1..|....| CLK_000_P_SYNC_2_ + 49| 1|NOD| . |=> .1..|....| CLK_000_P_SYNC_3_ + 50| 1|NOD| . |=> ....|..6.| CLK_000_P_SYNC_4_ + 51| 6|NOD| . |=> ....|..6.| CLK_000_P_SYNC_5_ + 52| 6|NOD| . |=> 0...|....| CLK_000_P_SYNC_6_ + 53| 0|NOD| . |=> 0...|....| CLK_000_P_SYNC_7_ + 54| 0|NOD| . |=> 0...|....| CLK_000_P_SYNC_8_ + 55| 0|NOD| . |=> ....|.5..| CLK_000_P_SYNC_9_ + 56| +|INP| 64|=> 01..|...7| CLK_030 + 57| 6|OUT| 65|=> ....|....| CLK_DIV_OUT + 58| 1|OUT| 10|=> ....|....| CLK_EXP + 59| +|Cin| 61|=> ....|....| CLK_OSZI + 60| 0|NOD| . |=> 0...|....| CYCLE_DMA_0_ + 61| 0|NOD| . |=> 0...|....| CYCLE_DMA_1_ + 62| 7| IO| 81|=> ....|....| DSACK1 + |=> Paired w/: RN_DSACK1 + 63| 0| IO| 98|=> 0..3|....| DS_030 + 64| 3|INP| 30|=> ..2.|....| DTACK + 65| 6| IO| 66|=> ....|....| E + |=> Paired w/: RN_E + 66| 5|INP| 57|=> ..2.|4..7| FC_0_ + 67| 5|INP| 58|=> ..2.|4..7| FC_1_ + 68| 7|OUT| 78|=> ....|....| FPU_CS + 69| 0|INP| 91|=> ....|4..7| FPU_SENSE + 70| 1| IO| 8|=> ....|....| IPL_030_0_ + |=> Paired w/: RN_IPL_030_0_ + 71| 1| IO| 7|=> ....|....| IPL_030_1_ + |=> Paired w/: RN_IPL_030_1_ + 72| 1| IO| 9|=> ....|....| IPL_030_2_ + |=> Paired w/: RN_IPL_030_2_ + 73| 6|INP| 67|=> .1..|....| IPL_0_ + 74| 5|INP| 56|=> .1..|..6.| IPL_1_ + 75| 6|INP| 68|=> .1..|..6.| IPL_2_ + 76| 1|NOD| . |=> .1..|....| IPL_D0_0_ + 77| 6|NOD| . |=> .1..|....| IPL_D0_1_ + 78| 6|NOD| . |=> .1..|....| IPL_D0_2_ + 79| 3| IO| 31|=> 0...|..6.| LDS_000 + 80| 5|NOD| . |=> ....|.5..| N_96_i + 81| 1| IO| 3|=> ....|....| RESET + |=> Paired w/: RN_RESET + 82| 6|NOD| . |=> ....|..6.| RN_A0 + |=> Paired w/: A0 + 83| 7|NOD| . |=> 0.23|4.67| RN_BGACK_030 + |=> Paired w/: BGACK_030 + 84| 3|NOD| . |=> ...3|....| RN_BG_000 + |=> Paired w/: BG_000 + 85| 7|NOD| . |=> ....|...7| RN_DSACK1 + |=> Paired w/: DSACK1 + 86| 6|NOD| . |=> ...3|.56.| RN_E + |=> Paired w/: E + 87| 1|NOD| . |=> .1..|....| RN_IPL_030_0_ + |=> Paired w/: IPL_030_0_ + 88| 1|NOD| . |=> .1..|....| RN_IPL_030_1_ + |=> Paired w/: IPL_030_1_ + 89| 1|NOD| . |=> .1..|....| RN_IPL_030_2_ + |=> Paired w/: IPL_030_2_ + 90| 1|NOD| . |=> 01.3|4.67| RN_RESET + |=> Paired w/: RESET + 91| 6|NOD| . |=> ....|..6.| RN_RW + |=> Paired w/: RW + 92| 7|NOD| . |=> ....|...7| RN_RW_000 + |=> Paired w/: RW_000 + 93| 3|NOD| . |=> ...3|.5..| RN_VMA + |=> Paired w/: VMA + 94| +|INP| 86|=> 0123|.567| RST + 95| 1|NOD| . |=> 01..|....| RST_DLY_0_ + 96| 0|NOD| . |=> 01..|....| RST_DLY_1_ + 97| 1|NOD| . |=> 01..|....| RST_DLY_2_ + 98| 0|NOD| . |=> 01..|....| RST_DLY_3_ + 99| 0|NOD| . |=> 01..|....| RST_DLY_4_ + 100| 1|NOD| . |=> 01..|....| RST_DLY_5_ + 101| 1|NOD| . |=> 01..|....| RST_DLY_6_ + 102| 1|NOD| . |=> 01..|....| RST_DLY_7_ + 103| 6| IO| 71|=> ....|.5.7| RW + |=> Paired w/: RN_RW + 104| 7| IO| 80|=> 0...|4.6.| RW_000 + |=> Paired w/: RN_RW_000 + 105| 6| IO| 70|=> ..2.|....| SIZE_0_ + 106| 7| IO| 79|=> ..2.|....| SIZE_1_ + 107| 6|NOD| . |=> ....|..67| SIZE_DMA_0_ + 108| 6|NOD| . |=> ....|..67| SIZE_DMA_1_ + 109| 1|NOD| . |=> .1..|.5.7| SM_AMIGA_0_ + 110| 5|NOD| . |=> .1..|.5.7| SM_AMIGA_1_ + 111| 5|NOD| . |=> ....|.5..| SM_AMIGA_2_ + 112| 5|NOD| . |=> ....|.5..| SM_AMIGA_3_ + 113| 5|NOD| . |=> ....|.5..| SM_AMIGA_4_ + 114| 5|NOD| . |=> ..2.|.5.7| SM_AMIGA_5_ + 115| 5|NOD| . |=> ..2.|.5..| SM_AMIGA_6_ + 116| 5|NOD| . |=> ..23|.5.7| SM_AMIGA_i_7_ + 117| 3| IO| 32|=> 0...|..6.| UDS_000 + 118| 3| IO| 35|=> ....|....| VMA + |=> Paired w/: RN_VMA + 119| +|INP| 36|=> .1..|....| VPA + 120| 5|NOD| . |=> ...3|.56.| cpu_est_0_ + 121| 3|NOD| . |=> ...3|.56.| cpu_est_1_ + 122| 3|NOD| . |=> ...3|.56.| cpu_est_2_ + 123| 2|NOD| . |=> ..23|....| inst_AMIGA_BUS_ENABLE_DMA_HIGH + 124| 2|NOD| . |=> ..2.|....| inst_AMIGA_BUS_ENABLE_DMA_LOW + 125| 0|NOD| . |=> 0...|...7| inst_AS_000_DMA + 126| 2|NOD| . |=> ..2.|4...| inst_AS_000_INT + 127| 2|NOD| . |=> ..2.|.5..| inst_AS_030_000_SYNC + 128| 7|NOD| . |=> ..23|45.7| inst_AS_030_D0 + 129| 7|NOD| . |=> ..2.|..6.| inst_BGACK_030_INT_D + 130| 3|NOD| . |=> ...3|.56.| inst_CLK_000_D0 + 131| 6|NOD| . |=> ...3|.5..| inst_CLK_000_D1 + 132| 4|NOD| . |=> 01.3|.5..| inst_CLK_000_NE + 133| 3|NOD| . |=> ...3|.56.| inst_CLK_000_NE_D0 + 134| 5|NOD| . |=> 01.3|.5.7| inst_CLK_000_PE + 135| 0|NOD| . |=> 0...|....| inst_CLK_030_H + 136| 4|NOD| . |=> ....|4...| inst_CLK_OUT_PRE_50 + 137| 4|NOD| . |=> ....|...7| inst_CLK_OUT_PRE_D + 138| 0|NOD| . |=> 0...|....| inst_DS_000_DMA + 139| 5|NOD| . |=> ...3|.5..| inst_DS_000_ENABLE + 140| 0|NOD| . |=> ..2.|....| inst_DS_030_D0 + 141| 2|NOD| . |=> ....|.5..| inst_DTACK_D0 + 142| 2|NOD| . |=> ..23|....| inst_LDS_000_INT + 143| 2|NOD| . |=> ..23|....| inst_UDS_000_INT + 144| 1|NOD| . |=> ...3|.5..| inst_VPA_D + 145| 6|NOD| . |=> 0.23|4567| inst_nEXP_SPACE_D0reg + 146| +|INP| 14|=> ....|..6.| nEXP_SPACE +--------------------------------------------------------------------------- +=========================================================================== + < C:/ispLever/ispcpld/dat/mach4a/mach447a Device Pin Assignments > +=========================================================================== + +- Device Pin No + | Pin Type +- Signal Fixed (*) + | | | Signal Name +____|_____|_________|______________________________________________________ + 1 | GND | | | (pwr/test) + 2 | JTAG | | | (pwr/test) + 3 | I_O | 1_07|*| RESET + 4 | I_O | 1_06|*| A_31_ + 5 | I_O | 1_05|*| A_30_ + 6 | I_O | 1_04|*| A_29_ + 7 | I_O | 1_03|*| IPL_030_1_ + 8 | I_O | 1_02|*| IPL_030_0_ + 9 | I_O | 1_01|*| IPL_030_2_ + 10 | I_O | 1_00|*| CLK_EXP + 11 | CkIn | |*| CLK_000 + 12 | Vcc | | | (pwr/test) + 13 | GND | | | (pwr/test) + 14 | CkIn | |*| nEXP_SPACE + 15 | I_O | 2_00|*| A_28_ + 16 | I_O | 2_01|*| A_27_ + 17 | I_O | 2_02|*| A_26_ + 18 | I_O | 2_03|*| A_25_ + 19 | I_O | 2_04|*| A_24_ + 20 | I_O | 2_05|*| AMIGA_BUS_ENABLE_LOW + 21 | I_O | 2_06|*| BG_030 + 22 | I_O | 2_07| | - + 23 | JTAG | | | (pwr/test) + 24 | JTAG | | | (pwr/test) + 25 | GND | | | (pwr/test) + 26 | GND | | | (pwr/test) + 27 | GND | | | (pwr/test) + 28 | I_O | 3_07|*| BGACK_000 + 29 | I_O | 3_06|*| BG_000 + 30 | I_O | 3_05|*| DTACK + 31 | I_O | 3_04|*| LDS_000 + 32 | I_O | 3_03|*| UDS_000 + 33 | I_O | 3_02|*| AMIGA_ADDR_ENABLE + 34 | I_O | 3_01|*| AMIGA_BUS_ENABLE_HIGH + 35 | I_O | 3_00|*| VMA + 36 | Inp | |*| VPA + 37 | Vcc | | | (pwr/test) + 38 | GND | | | (pwr/test) + 39 | GND | | | (pwr/test) + 40 | Vcc | | | (pwr/test) + 41 | I_O | 4_00|*| BERR + 42 | I_O | 4_01|*| AS_000 + 43 | I_O | 4_02| | - + 44 | I_O | 4_03| | - + 45 | I_O | 4_04| | - + 46 | I_O | 4_05| | - + 47 | I_O | 4_06|*| CIIN + 48 | I_O | 4_07|*| AMIGA_BUS_DATA_DIR + 49 | GND | | | (pwr/test) + 50 | GND | | | (pwr/test) + 51 | GND | | | (pwr/test) + 52 | JTAG | | | (pwr/test) + 53 | I_O | 5_07| | - + 54 | I_O | 5_06| | - + 55 | I_O | 5_05| | - + 56 | I_O | 5_04|*| IPL_1_ + 57 | I_O | 5_03|*| FC_0_ + 58 | I_O | 5_02|*| FC_1_ + 59 | I_O | 5_01|*| A_17_ + 60 | I_O | 5_00|*| A1 + 61 | CkIn | |*| CLK_OSZI + 62 | Vcc | | | (pwr/test) + 63 | GND | | | (pwr/test) + 64 | CkIn | |*| CLK_030 + 65 | I_O | 6_00|*| CLK_DIV_OUT + 66 | I_O | 6_01|*| E + 67 | I_O | 6_02|*| IPL_0_ + 68 | I_O | 6_03|*| IPL_2_ + 69 | I_O | 6_04|*| A0 + 70 | I_O | 6_05|*| SIZE_0_ + 71 | I_O | 6_06|*| RW + 72 | I_O | 6_07| | - + 73 | JTAG | | | (pwr/test) + 74 | JTAG | | | (pwr/test) + 75 | GND | | | (pwr/test) + 76 | GND | | | (pwr/test) + 77 | GND | | | (pwr/test) + 78 | I_O | 7_07|*| FPU_CS + 79 | I_O | 7_06|*| SIZE_1_ + 80 | I_O | 7_05|*| RW_000 + 81 | I_O | 7_04|*| DSACK1 + 82 | I_O | 7_03|*| AS_030 + 83 | I_O | 7_02|*| BGACK_030 + 84 | I_O | 7_01|*| A_22_ + 85 | I_O | 7_00|*| A_23_ + 86 | Inp | |*| RST + 87 | Vcc | | | (pwr/test) + 88 | GND | | | (pwr/test) + 89 | GND | | | (pwr/test) + 90 | Vcc | | | (pwr/test) + 91 | I_O | 0_00|*| FPU_SENSE + 92 | I_O | 0_01|*| AVEC + 93 | I_O | 0_02|*| A_20_ + 94 | I_O | 0_03|*| A_21_ + 95 | I_O | 0_04|*| A_18_ + 96 | I_O | 0_05|*| A_16_ + 97 | I_O | 0_06|*| A_19_ + 98 | I_O | 0_07|*| DS_030 + 99 | GND | | | (pwr/test) + 100 | GND | | | (pwr/test) +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 0] > Macrocell (MCell) Cluster Assignments +=========================================================================== + + Macrocell Number + | PT Requirements------ Logic XOR+ +--- Macrocell PT Cluster Size + | Sync/Async-------+ | | | Cluster to Mcell Assignment + | Node Fixed(*)----+ | | | | | +- XOR PT Size + | Sig Type-+ | | | | | | | XOR to Mcell Assignment + | Signal Name | | | | | | | | | +_|_________________|__|__|___|_____|__|______|___|__________|______________ + 0| DS_030| IO| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig + 1| RST_DLY_1_|NOD| | S | 4 | 4 to [ 1]| 1 XOR free + 2| CYCLE_DMA_1_|NOD| | S | 3 | 4 to [ 2]| 1 XOR free + 3|CLK_000_P_SYNC_8_|NOD| | S | 1 | 4 free | 1 XOR to [ 3] for 1 PT sig + 4| AVEC|OUT| | S | 1 | 4 free | 1 XOR to [ 4] for 1 PT sig + 5| RST_DLY_4_|NOD| | S | 2 :+: 1| 4 to [ 5]| 1 XOR to [ 5] + 6| CYCLE_DMA_0_|NOD| | S | 2 | 4 to [ 6]| 1 XOR free + 7|CLK_000_P_SYNC_7_|NOD| | S | 1 | 4 to [ 8]| 1 XOR to [ 7] for 1 PT sig + 8|inst_AS_000_DMA|NOD| | S | 7 | 4 to [ 8]| 1 XOR to [ 8] as logic PT + 9|inst_DS_000_DMA|NOD| | S | 9 | 4 to [ 9]| 1 XOR to [ 9] as logic PT +10|CLK_000_N_SYNC_8_|NOD| | S | 1 | 4 to [ 9]| 1 XOR to [10] for 1 PT sig +11|CLK_000_P_SYNC_9_|NOD| | S | 1 | 4 to [12]| 1 XOR to [11] for 1 PT sig +12| RST_DLY_3_|NOD| | S | 6 | 4 to [12]| 1 XOR to [12] as logic PT +13|inst_CLK_030_H|NOD| | S | 8 | 4 to [13]| 1 XOR to [13] as logic PT +14|CLK_000_N_SYNC_4_|NOD| | S | 1 | 4 to [13]| 1 XOR to [14] for 1 PT sig +15|inst_DS_030_D0|NOD| | S | 1 | 4 free | 1 XOR to [15] for 1 PT sig +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 0] > Maximum PT Capacity +=========================================================================== + + Macrocell Number + | PT Requirements------ Logic XOR+ + | Sync/Async-------+ | | + | Node Fixed(*)----+ | | | + | Sig Type-+ | | | | + | Signal Name | | | | | Maximum PT Capacity +_|_________________|__|__|___|_____|_______________________________________ + 0| DS_030| IO| | S | 1 |=> can support up to [ 5] logic PT(s) + 1| RST_DLY_1_|NOD| | S | 4 |=> can support up to [ 13] logic PT(s) + 2| CYCLE_DMA_1_|NOD| | S | 3 |=> can support up to [ 13] logic PT(s) + 3|CLK_000_P_SYNC_8_|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) + 4| AVEC|OUT| | S | 1 |=> can support up to [ 9] logic PT(s) + 5| RST_DLY_4_|NOD| | S | 2 :+: 1|=> can support up to [ 8] logic PT(s) + 6| CYCLE_DMA_0_|NOD| | S | 2 |=> can support up to [ 5] logic PT(s) + 7|CLK_000_P_SYNC_7_|NOD| | S | 1 |=> can support up to [ 1] logic PT(s) + 8|inst_AS_000_DMA|NOD| | S | 7 |=> can support up to [ 9] logic PT(s) + 9|inst_DS_000_DMA|NOD| | S | 9 |=> can support up to [ 9] logic PT(s) +10|CLK_000_N_SYNC_8_|NOD| | S | 1 |=> can support up to [ 1] logic PT(s) +11|CLK_000_P_SYNC_9_|NOD| | S | 1 |=> can support up to [ 1] logic PT(s) +12| RST_DLY_3_|NOD| | S | 6 |=> can support up to [ 9] logic PT(s) +13|inst_CLK_030_H|NOD| | S | 8 |=> can support up to [ 13] logic PT(s) +14|CLK_000_N_SYNC_4_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) +15|inst_DS_030_D0|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 0] > Node-Pin Assignments +=========================================================================== + + Macrocell Number + | Node Fixed(*)------+ + | Sig Type---+ | to | Block [ 0] IO Pin | Device Pin + | Signal Name | | pin | Numbers | Numbers +_|_________________|__|_____|____________________|________________________ + 0| DS_030| IO| | => | 5 6 ( 7) 0 | 96 97 ( 98) 91 + 1| RST_DLY_1_|NOD| | => | 5 6 7 0 | 96 97 98 91 + 2| CYCLE_DMA_1_|NOD| | => | 6 7 0 1 | 97 98 91 92 + 3|CLK_000_P_SYNC_8_|NOD| | => | 6 7 0 1 | 97 98 91 92 + 4| AVEC|OUT| | => | 7 0 ( 1) 2 | 98 91 ( 92) 93 + 5| RST_DLY_4_|NOD| | => | 7 0 1 2 | 98 91 92 93 + 6| CYCLE_DMA_0_|NOD| | => | 0 1 2 3 | 91 92 93 94 + 7|CLK_000_P_SYNC_7_|NOD| | => | 0 1 2 3 | 91 92 93 94 + 8|inst_AS_000_DMA|NOD| | => | 1 2 3 4 | 92 93 94 95 + 9|inst_DS_000_DMA|NOD| | => | 1 2 3 4 | 92 93 94 95 +10|CLK_000_N_SYNC_8_|NOD| | => | 2 3 4 5 | 93 94 95 96 +11|CLK_000_P_SYNC_9_|NOD| | => | 2 3 4 5 | 93 94 95 96 +12| RST_DLY_3_|NOD| | => | 3 4 5 6 | 94 95 96 97 +13|inst_CLK_030_H|NOD| | => | 3 4 5 6 | 94 95 96 97 +14|CLK_000_N_SYNC_4_|NOD| | => | 4 5 6 7 | 95 96 97 98 +15|inst_DS_030_D0|NOD| | => | 4 5 6 7 | 95 96 97 98 +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 0] > IO-to-Node Pin Mapping +=========================================================================== + +- Block IO Pin + | Device Pin No.--------+ + | Pin Fixed(*)----+ | + | Sig Type--+ | | | + | Signal Name | | | | Node Destinations Via Output Matrix +_|_________________|__|___|_____|___________________________________________ + 0| FPU_SENSE|INP|*| 91| => | 0 1 2 3 4 5 6 7 + 1| AVEC|OUT|*| 92| => | 2 3 ( 4) 5 6 7 8 9 + 2| A_20_|INP|*| 93| => | 4 5 6 7 8 9 10 11 + 3| A_21_|INP|*| 94| => | 6 7 8 9 10 11 12 13 + 4| A_18_|INP|*| 95| => | 8 9 10 11 12 13 14 15 + 5| A_16_|INP|*| 96| => | 10 11 12 13 14 15 0 1 + 6| A_19_|INP|*| 97| => | 12 13 14 15 0 1 2 3 + 7| DS_030| IO|*| 98| => | 14 15 ( 0) 1 2 3 4 5 +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 0] > IO/Node and IO/Input Macrocell Pairing Table +=========================================================================== + +- Block IO Pin + | Device Pin No.--------+ + | Pin Fixed(*)----+ | + | Sig Type--+ | | | + | Signal Name | | | | Input Macrocell and Node Pairs +_|_________________|__|___|_____|__________________________________________ + 0| FPU_SENSE|INP|*| 91| => | Input macrocell [ -] + 1| AVEC|OUT|*| 92| => | Input macrocell [ -] + 2| A_20_|INP|*| 93| => | Input macrocell [ -] + 3| A_21_|INP|*| 94| => | Input macrocell [ -] + 4| A_18_|INP|*| 95| => | Input macrocell [ -] + 5| A_16_|INP|*| 96| => | Input macrocell [ -] + 6| A_19_|INP|*| 97| => | Input macrocell [ -] + 7| DS_030| IO|*| 98| => | Input macrocell [ -] +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 0] > Input Multiplexer (IMX) Assignments +=========================================================================== + +----- IO pin/Input Register, or Macrocell +IMX No. | +---- Block IO Pin or Macrocell Number + | | | ABEL Node/ +-- Signal using the Pin or Macrocell + | | | Pin Number | +- Signal Fixed (*) to Pin/Mcell + | | | | Sig Type | | +- Feedback Required (*) +---|-------|----|---|---|----------|------|-|------------------------------ + 0 [IOpin 0 | 91|INP FPU_SENSE|*|*] + [RegIn 0 |102| -| | ] + [MCell 0 |101| IO DS_030| | ] + [MCell 1 |103|NOD RST_DLY_1_| |*] + + 1 [IOpin 1 | 92|OUT AVEC|*| ] + [RegIn 1 |105| -| | ] + [MCell 2 |104|NOD CYCLE_DMA_1_| |*] + [MCell 3 |106|NOD CLK_000_P_SYNC_8_| |*] + + 2 [IOpin 2 | 93|INP A_20_|*|*] + [RegIn 2 |108| -| | ] + [MCell 4 |107|OUT AVEC| | ] + [MCell 5 |109|NOD RST_DLY_4_| |*] + + 3 [IOpin 3 | 94|INP A_21_|*|*] + [RegIn 3 |111| -| | ] + [MCell 6 |110|NOD CYCLE_DMA_0_| |*] + [MCell 7 |112|NOD CLK_000_P_SYNC_7_| |*] + + 4 [IOpin 4 | 95|INP A_18_|*|*] + [RegIn 4 |114| -| | ] + [MCell 8 |113|NOD inst_AS_000_DMA| |*] + [MCell 9 |115|NOD inst_DS_000_DMA| |*] + + 5 [IOpin 5 | 96|INP A_16_|*|*] + [RegIn 5 |117| -| | ] + [MCell 10 |116|NOD CLK_000_N_SYNC_8_| |*] + [MCell 11 |118|NOD CLK_000_P_SYNC_9_| |*] + + 6 [IOpin 6 | 97|INP A_19_|*|*] + [RegIn 6 |120| -| | ] + [MCell 12 |119|NOD RST_DLY_3_| |*] + [MCell 13 |121|NOD inst_CLK_030_H| |*] + + 7 [IOpin 7 | 98| IO DS_030|*|*] + [RegIn 7 |123| -| | ] + [MCell 14 |122|NOD CLK_000_N_SYNC_4_| |*] + [MCell 15 |124|NOD inst_DS_030_D0| |*] +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 0] > Logic Array Fan-in +=========================================================================== + +- Central Switch Matrix No. + | Src (ABEL Node/Pin#) Signal +--|--|--------------------|--------------------------------------------------- +Mux00| Mcel 0 2 ( 104)| CYCLE_DMA_1_ +Mux01| Mcel 0 7 ( 112)| CLK_000_P_SYNC_7_ +Mux02| Mcel 1 10 ( 140)| RST_DLY_7_ +Mux03| Mcel 6 5 ( 253)| inst_nEXP_SPACE_D0reg +Mux04| Input Pin ( 64)| CLK_030 +Mux05| IOPin 0 7 ( 98)| DS_030 +Mux06| IOPin 7 5 ( 80)| RW_000 +Mux07| ... | ... +Mux08| Mcel 4 8 ( 209)| inst_CLK_000_NE +Mux09| Mcel 0 12 ( 119)| RST_DLY_3_ +Mux10| Mcel 1 2 ( 128)| RST_DLY_6_ +Mux11| Mcel 1 6 ( 134)| RST_DLY_0_ +Mux12| IOPin 3 3 ( 32)| UDS_000 +Mux13| Mcel 3 3 ( 178)| CLK_000_N_SYNC_3_ +Mux14| ... | ... +Mux15| Mcel 0 6 ( 110)| CYCLE_DMA_0_ +Mux16| Mcel 1 9 ( 139)| RST_DLY_2_ +Mux17| ... | ... +Mux18| Mcel 0 5 ( 109)| RST_DLY_4_ +Mux19| Mcel 0 9 ( 115)| inst_DS_000_DMA +Mux20| Mcel 3 10 ( 188)| CLK_000_N_SYNC_7_ +Mux21| Mcel 0 1 ( 103)| RST_DLY_1_ +Mux22| Mcel 6 10 ( 260)| CLK_000_P_SYNC_6_ +Mux23| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux24| Input Pin ( 86)| RST +Mux25| Mcel 0 13 ( 121)| inst_CLK_030_H +Mux26| IOPin 4 1 ( 42)| AS_000 +Mux27| IOPin 3 4 ( 31)| LDS_000 +Mux28| Mcel 1 13 ( 145)| RST_DLY_5_ +Mux29| Mcel 1 0 ( 125)| RN_RESET +Mux30| Mcel 0 8 ( 113)| inst_AS_000_DMA +Mux31| Mcel 5 0 ( 221)| inst_CLK_000_PE +Mux32| Mcel 0 3 ( 106)| CLK_000_P_SYNC_8_ +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 1] > Macrocell (MCell) Cluster Assignments +=========================================================================== + + Macrocell Number + | PT Requirements------ Logic XOR+ +--- Macrocell PT Cluster Size + | Sync/Async-------+ | | | Cluster to Mcell Assignment + | Node Fixed(*)----+ | | | | | +- XOR PT Size + | Sig Type-+ | | | | | | | XOR to Mcell Assignment + | Signal Name | | | | | | | | | +_|_________________|__|__|___|_____|__|______|___|__________|______________ + 0| RESET| IO| | S | 2 | 4 to [ 0]| 1 XOR free + 1| CLK_EXP|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig + 2| RST_DLY_6_|NOD| | S | 3 | 4 to [ 2]| 1 XOR free + 3|CLK_000_N_SYNC_1_|NOD| | S | 1 | 4 free | 1 XOR to [ 3] for 1 PT sig + 4| IPL_030_2_| IO| | S |10 | 4 to [ 4]| 1 XOR to [ 4] as logic PT + 5| SM_AMIGA_0_|NOD| | S | 2 | 4 to [ 4]| 1 XOR to [ 4] as logic PT + 6| RST_DLY_0_|NOD| | S | 3 | 4 to [ 5]| 1 XOR free + 7|CLK_000_P_SYNC_4_|NOD| | S | 1 | 4 to [ 6]| 1 XOR to [ 7] for 1 PT sig + 8| IPL_030_0_| IO| | S |10 | 4 to [ 8]| 1 XOR to [ 8] as logic PT + 9| RST_DLY_2_|NOD| | S | 5 | 4 to [ 8]| 1 XOR to [ 8] as logic PT +10| RST_DLY_7_|NOD| | S | 2 | 4 to [ 9]| 1 XOR to [ 9] as logic PT +11|CLK_000_P_SYNC_3_|NOD| | S | 1 | 4 to [10]| 1 XOR to [11] for 1 PT sig +12| IPL_030_1_| IO| | S |10 | 4 to [12]| 1 XOR to [12] as logic PT +13| RST_DLY_5_|NOD| | S | 4 | 4 to [12]| 1 XOR to [12] as logic PT +14| inst_VPA_D|NOD| | S | 1 | 4 free | 1 XOR to [14] for 1 PT sig +15| IPL_D0_0_|NOD| | S | 1 | 4 to [13]| 1 XOR to [15] for 1 PT sig +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 1] > Maximum PT Capacity +=========================================================================== + + Macrocell Number + | PT Requirements------ Logic XOR+ + | Sync/Async-------+ | | + | Node Fixed(*)----+ | | | + | Sig Type-+ | | | | + | Signal Name | | | | | Maximum PT Capacity +_|_________________|__|__|___|_____|_______________________________________ + 0| RESET| IO| | S | 2 |=> can support up to [ 9] logic PT(s) + 1| CLK_EXP|OUT| | S | 1 |=> can support up to [ 9] logic PT(s) + 2| RST_DLY_6_|NOD| | S | 3 |=> can support up to [ 13] logic PT(s) + 3|CLK_000_N_SYNC_1_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) + 4| IPL_030_2_| IO| | S |10 |=> can support up to [ 14] logic PT(s) + 5| SM_AMIGA_0_|NOD| | S | 2 |=> can support up to [ 5] logic PT(s) + 6| RST_DLY_0_|NOD| | S | 3 |=> can support up to [ 4] logic PT(s) + 7|CLK_000_P_SYNC_4_|NOD| | S | 1 |=> can support up to [ 1] logic PT(s) + 8| IPL_030_0_| IO| | S |10 |=> can support up to [ 10] logic PT(s) + 9| RST_DLY_2_|NOD| | S | 5 |=> can support up to [ 5] logic PT(s) +10| RST_DLY_7_|NOD| | S | 2 |=> can support up to [ 4] logic PT(s) +11|CLK_000_P_SYNC_3_|NOD| | S | 1 |=> can support up to [ 1] logic PT(s) +12| IPL_030_1_| IO| | S |10 |=> can support up to [ 14] logic PT(s) +13| RST_DLY_5_|NOD| | S | 4 |=> can support up to [ 8] logic PT(s) +14| inst_VPA_D|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) +15| IPL_D0_0_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 1] > Node-Pin Assignments +=========================================================================== + + Macrocell Number + | Node Fixed(*)------+ + | Sig Type---+ | to | Block [ 1] IO Pin | Device Pin + | Signal Name | | pin | Numbers | Numbers +_|_________________|__|_____|____________________|________________________ + 0| RESET| IO| | => | 5 6 ( 7) 0 | 5 4 ( 3) 10 + 1| CLK_EXP|OUT| | => | 5 6 7 ( 0)| 5 4 3 ( 10) + 2| RST_DLY_6_|NOD| | => | 6 7 0 1 | 4 3 10 9 + 3|CLK_000_N_SYNC_1_|NOD| | => | 6 7 0 1 | 4 3 10 9 + 4| IPL_030_2_| IO| | => | 7 0 ( 1) 2 | 3 10 ( 9) 8 + 5| SM_AMIGA_0_|NOD| | => | 7 0 1 2 | 3 10 9 8 + 6| RST_DLY_0_|NOD| | => | 0 1 2 3 | 10 9 8 7 + 7|CLK_000_P_SYNC_4_|NOD| | => | 0 1 2 3 | 10 9 8 7 + 8| IPL_030_0_| IO| | => | 1 ( 2) 3 4 | 9 ( 8) 7 6 + 9| RST_DLY_2_|NOD| | => | 1 2 3 4 | 9 8 7 6 +10| RST_DLY_7_|NOD| | => | 2 3 4 5 | 8 7 6 5 +11|CLK_000_P_SYNC_3_|NOD| | => | 2 3 4 5 | 8 7 6 5 +12| IPL_030_1_| IO| | => |( 3) 4 5 6 |( 7) 6 5 4 +13| RST_DLY_5_|NOD| | => | 3 4 5 6 | 7 6 5 4 +14| inst_VPA_D|NOD| | => | 4 5 6 7 | 6 5 4 3 +15| IPL_D0_0_|NOD| | => | 4 5 6 7 | 6 5 4 3 +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 1] > IO-to-Node Pin Mapping +=========================================================================== + +- Block IO Pin + | Device Pin No.--------+ + | Pin Fixed(*)----+ | + | Sig Type--+ | | | + | Signal Name | | | | Node Destinations Via Output Matrix +_|_________________|__|___|_____|___________________________________________ + 0| CLK_EXP|OUT|*| 10| => | 0 ( 1) 2 3 4 5 6 7 + 1| IPL_030_2_| IO|*| 9| => | 2 3 ( 4) 5 6 7 8 9 + 2| IPL_030_0_| IO|*| 8| => | 4 5 6 7 ( 8) 9 10 11 + 3| IPL_030_1_| IO|*| 7| => | 6 7 8 9 10 11 (12) 13 + 4| A_29_|INP|*| 6| => | 8 9 10 11 12 13 14 15 + 5| A_30_|INP|*| 5| => | 10 11 12 13 14 15 0 1 + 6| A_31_|INP|*| 4| => | 12 13 14 15 0 1 2 3 + 7| RESET| IO|*| 3| => | 14 15 ( 0) 1 2 3 4 5 +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 1] > IO/Node and IO/Input Macrocell Pairing Table +=========================================================================== + +- Block IO Pin + | Device Pin No.--------+ + | Pin Fixed(*)----+ | + | Sig Type--+ | | | + | Signal Name | | | | Input Macrocell and Node Pairs +_|_________________|__|___|_____|__________________________________________ + 0| CLK_EXP|OUT|*| 10| => | Input macrocell [ -] + 1| IPL_030_2_| IO|*| 9| => | Input macrocell [ -] + | | | | | | IO paired w/ node [ RN_IPL_030_2_] + 2| IPL_030_0_| IO|*| 8| => | Input macrocell [ -] + | | | | | | IO paired w/ node [ RN_IPL_030_0_] + 3| IPL_030_1_| IO|*| 7| => | Input macrocell [ -] + | | | | | | IO paired w/ node [ RN_IPL_030_1_] + 4| A_29_|INP|*| 6| => | Input macrocell [ -] + 5| A_30_|INP|*| 5| => | Input macrocell [ -] + 6| A_31_|INP|*| 4| => | Input macrocell [ -] + 7| RESET| IO|*| 3| => | Input macrocell [ -] + | | | | | | IO paired w/ node [ RN_RESET] +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 1] > Input Multiplexer (IMX) Assignments +=========================================================================== + +----- IO pin/Input Register, or Macrocell +IMX No. | +---- Block IO Pin or Macrocell Number + | | | ABEL Node/ +-- Signal using the Pin or Macrocell + | | | Pin Number | +- Signal Fixed (*) to Pin/Mcell + | | | | Sig Type | | +- Feedback Required (*) +---|-------|----|---|---|----------|------|-|------------------------------ + 0 [IOpin 0 | 10|OUT CLK_EXP|*| ] + [RegIn 0 |126| -| | ] + [MCell 0 |125|NOD RN_RESET| |*] paired w/[ RESET] + [MCell 1 |127|OUT CLK_EXP| | ] + + 1 [IOpin 1 | 9| IO IPL_030_2_|*| ] paired w/[ RN_IPL_030_2_] + [RegIn 1 |129| -| | ] + [MCell 2 |128|NOD RST_DLY_6_| |*] + [MCell 3 |130|NOD CLK_000_N_SYNC_1_| |*] + + 2 [IOpin 2 | 8| IO IPL_030_0_|*| ] paired w/[ RN_IPL_030_0_] + [RegIn 2 |132| -| | ] + [MCell 4 |131|NOD RN_IPL_030_2_| |*] paired w/[ IPL_030_2_] + [MCell 5 |133|NOD SM_AMIGA_0_| |*] + + 3 [IOpin 3 | 7| IO IPL_030_1_|*| ] paired w/[ RN_IPL_030_1_] + [RegIn 3 |135| -| | ] + [MCell 6 |134|NOD RST_DLY_0_| |*] + [MCell 7 |136|NOD CLK_000_P_SYNC_4_| |*] + + 4 [IOpin 4 | 6|INP A_29_|*|*] + [RegIn 4 |138| -| | ] + [MCell 8 |137|NOD RN_IPL_030_0_| |*] paired w/[ IPL_030_0_] + [MCell 9 |139|NOD RST_DLY_2_| |*] + + 5 [IOpin 5 | 5|INP A_30_|*|*] + [RegIn 5 |141| -| | ] + [MCell 10 |140|NOD RST_DLY_7_| |*] + [MCell 11 |142|NOD CLK_000_P_SYNC_3_| |*] + + 6 [IOpin 6 | 4|INP A_31_|*|*] + [RegIn 6 |144| -| | ] + [MCell 12 |143|NOD RN_IPL_030_1_| |*] paired w/[ IPL_030_1_] + [MCell 13 |145|NOD RST_DLY_5_| |*] + + 7 [IOpin 7 | 3| IO RESET|*| ] paired w/[ RN_RESET] + [RegIn 7 |147| -| | ] + [MCell 14 |146|NOD inst_VPA_D| |*] + [MCell 15 |148|NOD IPL_D0_0_| |*] +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 1] > Logic Array Fan-in +=========================================================================== + +- Central Switch Matrix No. + | Src (ABEL Node/Pin#) Signal +--|--|--------------------|--------------------------------------------------- +Mux00| Input Pin ( 86)| RST +Mux01| IOPin 4 0 ( 41)| BERR +Mux02| Mcel 1 10 ( 140)| RST_DLY_7_ +Mux03| IOPin 5 4 ( 56)| IPL_1_ +Mux04| IOPin 6 3 ( 68)| IPL_2_ +Mux05| Mcel 5 0 ( 221)| inst_CLK_000_PE +Mux06| Mcel 1 9 ( 139)| RST_DLY_2_ +Mux07| Mcel 1 11 ( 142)| CLK_000_P_SYNC_3_ +Mux08| Mcel 4 8 ( 209)| inst_CLK_000_NE +Mux09| Mcel 6 11 ( 262)| IPL_D0_2_ +Mux10| Mcel 1 13 ( 145)| RST_DLY_5_ +Mux11| Mcel 1 6 ( 134)| RST_DLY_0_ +Mux12| Mcel 1 12 ( 143)| RN_IPL_030_1_ +Mux13| Input Pin ( 36)| VPA +Mux14| ... | ... +Mux15| Mcel 0 12 ( 119)| RST_DLY_3_ +Mux16| IOPin 6 2 ( 67)| IPL_0_ +Mux17| Mcel 1 8 ( 137)| RN_IPL_030_0_ +Mux18| Mcel 6 15 ( 268)| IPL_D0_1_ +Mux19| Mcel 3 11 ( 190)| CLK_000_N_SYNC_0_ +Mux20| Input Pin ( 64)| CLK_030 +Mux21| Mcel 0 1 ( 103)| RST_DLY_1_ +Mux22| ... | ... +Mux23| ... | ... +Mux24| Mcel 6 3 ( 250)| CLK_000_P_SYNC_2_ +Mux25| Mcel 1 2 ( 128)| RST_DLY_6_ +Mux26| Mcel 1 0 ( 125)| RN_RESET +Mux27| Mcel 1 15 ( 148)| IPL_D0_0_ +Mux28| Mcel 0 5 ( 109)| RST_DLY_4_ +Mux29| ... | ... +Mux30| Mcel 1 4 ( 131)| RN_IPL_030_2_ +Mux31| Mcel 1 5 ( 133)| SM_AMIGA_0_ +Mux32| Mcel 5 8 ( 233)| SM_AMIGA_1_ +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 2] > Macrocell (MCell) Cluster Assignments +=========================================================================== + + Macrocell Number + | PT Requirements------ Logic XOR+ +--- Macrocell PT Cluster Size + | Sync/Async-------+ | | | Cluster to Mcell Assignment + | Node Fixed(*)----+ | | | | | +- XOR PT Size + | Sig Type-+ | | | | | | | XOR to Mcell Assignment + | Signal Name | | | | | | | | | +_|_________________|__|__|___|_____|__|______|___|__________|______________ + 0|AMIGA_BUS_ENABLE_LOW|OUT| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig + 1|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | S | 2 | 4 to [ 1]| 1 XOR free + 2| inst_DTACK_D0|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig + 3| | ? | | S | | 4 free | 1 XOR free + 4|inst_AS_030_000_SYNC|NOD| | S | 7 | 4 to [ 4]| 1 XOR to [ 4] as logic PT + 5|inst_AS_000_INT|NOD| | S | 2 | 4 to [ 5]| 1 XOR free + 6| | ? | | S | | 4 to [ 4]| 1 XOR free + 7| | ? | | S | | 4 free | 1 XOR free + 8|inst_LDS_000_INT|NOD| | S | 4 | 4 to [ 8]| 1 XOR free + 9|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | S | 2 | 4 to [ 9]| 1 XOR free +10| | ? | | S | | 4 free | 1 XOR free +11| | ? | | S | | 4 free | 1 XOR free +12|inst_UDS_000_INT|NOD| | S | 3 | 4 to [12]| 1 XOR free +13|CLK_000_N_SYNC_5_|NOD| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig +14| | ? | | S | | 4 free | 1 XOR free +15| | ? | | S | | 4 free | 1 XOR free +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 2] > Maximum PT Capacity +=========================================================================== + + Macrocell Number + | PT Requirements------ Logic XOR+ + | Sync/Async-------+ | | + | Node Fixed(*)----+ | | | + | Sig Type-+ | | | | + | Signal Name | | | | | Maximum PT Capacity +_|_________________|__|__|___|_____|_______________________________________ + 0|AMIGA_BUS_ENABLE_LOW|OUT| | S | 1 |=> can support up to [ 9] logic PT(s) + 1|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | S | 2 |=> can support up to [ 18] logic PT(s) + 2| inst_DTACK_D0|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) + 3| | ? | | S | |=> can support up to [ 9] logic PT(s) + 4|inst_AS_030_000_SYNC|NOD| | S | 7 |=> can support up to [ 15] logic PT(s) + 5|inst_AS_000_INT|NOD| | S | 2 |=> can support up to [ 10] logic PT(s) + 6| | ? | | S | |=> can support up to [ 6] logic PT(s) + 7| | ? | | S | |=> can support up to [ 5] logic PT(s) + 8|inst_LDS_000_INT|NOD| | S | 4 |=> can support up to [ 15] logic PT(s) + 9|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | S | 2 |=> can support up to [ 15] logic PT(s) +10| | ? | | S | |=> can support up to [ 10] logic PT(s) +11| | ? | | S | |=> can support up to [ 14] logic PT(s) +12|inst_UDS_000_INT|NOD| | S | 3 |=> can support up to [ 19] logic PT(s) +13|CLK_000_N_SYNC_5_|NOD| | S | 1 |=> can support up to [ 15] logic PT(s) +14| | ? | | S | |=> can support up to [ 14] logic PT(s) +15| | ? | | S | |=> can support up to [ 10] logic PT(s) +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 2] > Node-Pin Assignments +=========================================================================== + + Macrocell Number + | Node Fixed(*)------+ + | Sig Type---+ | to | Block [ 2] IO Pin | Device Pin + | Signal Name | | pin | Numbers | Numbers +_|_________________|__|_____|____________________|________________________ + 0|AMIGA_BUS_ENABLE_LOW|OUT| | => |( 5) 6 7 0 |( 20) 21 22 15 + 1|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | => | 5 6 7 0 | 20 21 22 15 + 2| inst_DTACK_D0|NOD| | => | 6 7 0 1 | 21 22 15 16 + 3| | | | => | 6 7 0 1 | 21 22 15 16 + 4|inst_AS_030_000_SYNC|NOD| | => | 7 0 1 2 | 22 15 16 17 + 5|inst_AS_000_INT|NOD| | => | 7 0 1 2 | 22 15 16 17 + 6| | | | => | 0 1 2 3 | 15 16 17 18 + 7| | | | => | 0 1 2 3 | 15 16 17 18 + 8|inst_LDS_000_INT|NOD| | => | 1 2 3 4 | 16 17 18 19 + 9|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | => | 1 2 3 4 | 16 17 18 19 +10| | | | => | 2 3 4 5 | 17 18 19 20 +11| | | | => | 2 3 4 5 | 17 18 19 20 +12|inst_UDS_000_INT|NOD| | => | 3 4 5 6 | 18 19 20 21 +13|CLK_000_N_SYNC_5_|NOD| | => | 3 4 5 6 | 18 19 20 21 +14| | | | => | 4 5 6 7 | 19 20 21 22 +15| | | | => | 4 5 6 7 | 19 20 21 22 +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 2] > IO-to-Node Pin Mapping +=========================================================================== + +- Block IO Pin + | Device Pin No.--------+ + | Pin Fixed(*)----+ | + | Sig Type--+ | | | + | Signal Name | | | | Node Destinations Via Output Matrix +_|_________________|__|___|_____|___________________________________________ + 0| A_28_|INP|*| 15| => | 0 1 2 3 4 5 6 7 + 1| A_27_|INP|*| 16| => | 2 3 4 5 6 7 8 9 + 2| A_26_|INP|*| 17| => | 4 5 6 7 8 9 10 11 + 3| A_25_|INP|*| 18| => | 6 7 8 9 10 11 12 13 + 4| A_24_|INP|*| 19| => | 8 9 10 11 12 13 14 15 + 5|AMIGA_BUS_ENABLE_LOW|OUT|*| 20| => | 10 11 12 13 14 15 ( 0) 1 + 6| BG_030|INP|*| 21| => | 12 13 14 15 0 1 2 3 + 7| | | | 22| => | 14 15 0 1 2 3 4 5 +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 2] > IO/Node and IO/Input Macrocell Pairing Table +=========================================================================== + +- Block IO Pin + | Device Pin No.--------+ + | Pin Fixed(*)----+ | + | Sig Type--+ | | | + | Signal Name | | | | Input Macrocell and Node Pairs +_|_________________|__|___|_____|__________________________________________ + 0| A_28_|INP|*| 15| => | Input macrocell [ -] + 1| A_27_|INP|*| 16| => | Input macrocell [ -] + 2| A_26_|INP|*| 17| => | Input macrocell [ -] + 3| A_25_|INP|*| 18| => | Input macrocell [ -] + 4| A_24_|INP|*| 19| => | Input macrocell [ -] + 5|AMIGA_BUS_ENABLE_LOW|OUT|*| 20| => | Input macrocell [ -] + 6| BG_030|INP|*| 21| => | Input macrocell [ -] + 7| | | | 22| => | Input macrocell [ -] +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 2] > Input Multiplexer (IMX) Assignments +=========================================================================== + +----- IO pin/Input Register, or Macrocell +IMX No. | +---- Block IO Pin or Macrocell Number + | | | ABEL Node/ +-- Signal using the Pin or Macrocell + | | | Pin Number | +- Signal Fixed (*) to Pin/Mcell + | | | | Sig Type | | +- Feedback Required (*) +---|-------|----|---|---|----------|------|-|------------------------------ + 0 [IOpin 0 | 15|INP A_28_|*|*] + [RegIn 0 |150| -| | ] + [MCell 0 |149|OUT AMIGA_BUS_ENABLE_LOW| | ] + [MCell 1 |151|NOD inst_AMIGA_BUS_ENABLE_DMA_HIGH| |*] + + 1 [IOpin 1 | 16|INP A_27_|*|*] + [RegIn 1 |153| -| | ] + [MCell 2 |152|NOD inst_DTACK_D0| |*] + [MCell 3 |154| -| | ] + + 2 [IOpin 2 | 17|INP A_26_|*|*] + [RegIn 2 |156| -| | ] + [MCell 4 |155|NOD inst_AS_030_000_SYNC| |*] + [MCell 5 |157|NOD inst_AS_000_INT| |*] + + 3 [IOpin 3 | 18|INP A_25_|*|*] + [RegIn 3 |159| -| | ] + [MCell 6 |158| -| | ] + [MCell 7 |160| -| | ] + + 4 [IOpin 4 | 19|INP A_24_|*|*] + [RegIn 4 |162| -| | ] + [MCell 8 |161|NOD inst_LDS_000_INT| |*] + [MCell 9 |163|NOD inst_AMIGA_BUS_ENABLE_DMA_LOW| |*] + + 5 [IOpin 5 | 20|OUT AMIGA_BUS_ENABLE_LOW|*| ] + [RegIn 5 |165| -| | ] + [MCell 10 |164| -| | ] + [MCell 11 |166| -| | ] + + 6 [IOpin 6 | 21|INP BG_030|*|*] + [RegIn 6 |168| -| | ] + [MCell 12 |167|NOD inst_UDS_000_INT| |*] + [MCell 13 |169|NOD CLK_000_N_SYNC_5_| |*] + + 7 [IOpin 7 | 22| -| | ] + [RegIn 7 |171| -| | ] + [MCell 14 |170| -| | ] + [MCell 15 |172| -| | ] +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 2] > Logic Array Fan-in +=========================================================================== + +- Central Switch Matrix No. + | Src (ABEL Node/Pin#) Signal +--|--|--------------------|--------------------------------------------------- +Mux00| IOPin 6 4 ( 69)| A0 +Mux01| IOPin 5 2 ( 58)| FC_1_ +Mux02| ... | ... +Mux03| Mcel 0 14 ( 122)| CLK_000_N_SYNC_4_ +Mux04| Mcel 7 5 ( 277)| inst_AS_030_D0 +Mux05| ... | ... +Mux06| IOPin 0 5 ( 96)| A_16_ +Mux07| Mcel 2 5 ( 157)| inst_AS_000_INT +Mux08| IOPin 5 1 ( 59)| A_17_ +Mux09| IOPin 3 5 ( 30)| DTACK +Mux10| Mcel 5 4 ( 227)| SM_AMIGA_i_7_ +Mux11| IOPin 5 0 ( 60)| A1 +Mux12| IOPin 0 6 ( 97)| A_19_ +Mux13| Mcel 0 15 ( 124)| inst_DS_030_D0 +Mux14| IOPin 6 5 ( 70)| SIZE_0_ +Mux15| Mcel 2 12 ( 167)| inst_UDS_000_INT +Mux16| Mcel 2 8 ( 161)| inst_LDS_000_INT +Mux17| IOPin 0 4 ( 95)| A_18_ +Mux18| Mcel 5 9 ( 235)| SM_AMIGA_6_ +Mux19| Mcel 7 13 ( 289)| inst_BGACK_030_INT_D +Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux21| Input Pin ( 86)| RST +Mux22| Mcel 2 1 ( 151)| inst_AMIGA_BUS_ENABLE_DMA_HIGH +Mux23| Mcel 2 9 ( 163)| inst_AMIGA_BUS_ENABLE_DMA_LOW +Mux24| IOPin 5 3 ( 57)| FC_0_ +Mux25| IOPin 4 0 ( 41)| BERR +Mux26| ... | ... +Mux27| IOPin 7 6 ( 79)| SIZE_1_ +Mux28| ... | ... +Mux29| Mcel 2 4 ( 155)| inst_AS_030_000_SYNC +Mux30| ... | ... +Mux31| Mcel 5 12 ( 239)| SM_AMIGA_5_ +Mux32| Mcel 6 5 ( 253)| inst_nEXP_SPACE_D0reg +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 3] > Macrocell (MCell) Cluster Assignments +=========================================================================== + + Macrocell Number + | PT Requirements------ Logic XOR+ +--- Macrocell PT Cluster Size + | Sync/Async-------+ | | | Cluster to Mcell Assignment + | Node Fixed(*)----+ | | | | | +- XOR PT Size + | Sig Type-+ | | | | | | | XOR to Mcell Assignment + | Signal Name | | | | | | | | | +_|_________________|__|__|___|_____|__|______|___|__________|______________ + 0| VMA| IO| | S | 3 | 4 to [ 0]| 1 XOR free + 1| BG_000| IO| | S | 2 | 4 to [ 1]| 1 XOR free + 2|inst_CLK_000_NE_D0|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig + 3|CLK_000_N_SYNC_3_|NOD| | S | 1 | 4 free | 1 XOR to [ 3] for 1 PT sig + 4|AMIGA_BUS_ENABLE_HIGH|OUT| | S | 2 | 4 to [ 4]| 1 XOR free + 5|AMIGA_ADDR_ENABLE|OUT| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig + 6|inst_CLK_000_D0|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig + 7|CLK_000_N_SYNC_2_|NOD| | S | 1 | 4 free | 1 XOR to [ 7] for 1 PT sig + 8| UDS_000| IO| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig + 9| cpu_est_1_|NOD| | S | 5 | 4 to [ 9]| 1 XOR to [ 9] as logic PT +10|CLK_000_N_SYNC_7_|NOD| | S | 1 | 4 free | 1 XOR to [10] for 1 PT sig +11|CLK_000_N_SYNC_0_|NOD| | S | 1 | 4 free | 1 XOR to [11] for 1 PT sig +12| LDS_000| IO| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig +13| cpu_est_2_|NOD| | S | 4 | 4 to [13]| 1 XOR free +14|CLK_000_N_SYNC_6_|NOD| | S | 1 | 4 free | 1 XOR to [14] for 1 PT sig +15|CLK_000_P_SYNC_0_|NOD| | S | 1 | 4 free | 1 XOR to [15] for 1 PT sig +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 3] > Maximum PT Capacity +=========================================================================== + + Macrocell Number + | PT Requirements------ Logic XOR+ + | Sync/Async-------+ | | + | Node Fixed(*)----+ | | | + | Sig Type-+ | | | | + | Signal Name | | | | | Maximum PT Capacity +_|_________________|__|__|___|_____|_______________________________________ + 0| VMA| IO| | S | 3 |=> can support up to [ 9] logic PT(s) + 1| BG_000| IO| | S | 2 |=> can support up to [ 13] logic PT(s) + 2|inst_CLK_000_NE_D0|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) + 3|CLK_000_N_SYNC_3_|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) + 4|AMIGA_BUS_ENABLE_HIGH|OUT| | S | 2 |=> can support up to [ 17] logic PT(s) + 5|AMIGA_ADDR_ENABLE|OUT| | S | 1 |=> can support up to [ 13] logic PT(s) + 6|inst_CLK_000_D0|NOD| | S | 1 |=> can support up to [ 17] logic PT(s) + 7|CLK_000_N_SYNC_2_|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) + 8| UDS_000| IO| | S | 1 |=> can support up to [ 13] logic PT(s) + 9| cpu_est_1_|NOD| | S | 5 |=> can support up to [ 17] logic PT(s) +10|CLK_000_N_SYNC_7_|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) +11|CLK_000_N_SYNC_0_|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) +12| LDS_000| IO| | S | 1 |=> can support up to [ 13] logic PT(s) +13| cpu_est_2_|NOD| | S | 4 |=> can support up to [ 17] logic PT(s) +14|CLK_000_N_SYNC_6_|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) +15|CLK_000_P_SYNC_0_|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 3] > Node-Pin Assignments +=========================================================================== + + Macrocell Number + | Node Fixed(*)------+ + | Sig Type---+ | to | Block [ 3] IO Pin | Device Pin + | Signal Name | | pin | Numbers | Numbers +_|_________________|__|_____|____________________|________________________ + 0| VMA| IO| | => | 5 6 7 ( 0)| 30 29 28 ( 35) + 1| BG_000| IO| | => | 5 ( 6) 7 0 | 30 ( 29) 28 35 + 2|inst_CLK_000_NE_D0|NOD| | => | 6 7 0 1 | 29 28 35 34 + 3|CLK_000_N_SYNC_3_|NOD| | => | 6 7 0 1 | 29 28 35 34 + 4|AMIGA_BUS_ENABLE_HIGH|OUT| | => | 7 0 ( 1) 2 | 28 35 ( 34) 33 + 5|AMIGA_ADDR_ENABLE|OUT| | => | 7 0 1 ( 2)| 28 35 34 ( 33) + 6|inst_CLK_000_D0|NOD| | => | 0 1 2 3 | 35 34 33 32 + 7|CLK_000_N_SYNC_2_|NOD| | => | 0 1 2 3 | 35 34 33 32 + 8| UDS_000| IO| | => | 1 2 ( 3) 4 | 34 33 ( 32) 31 + 9| cpu_est_1_|NOD| | => | 1 2 3 4 | 34 33 32 31 +10|CLK_000_N_SYNC_7_|NOD| | => | 2 3 4 5 | 33 32 31 30 +11|CLK_000_N_SYNC_0_|NOD| | => | 2 3 4 5 | 33 32 31 30 +12| LDS_000| IO| | => | 3 ( 4) 5 6 | 32 ( 31) 30 29 +13| cpu_est_2_|NOD| | => | 3 4 5 6 | 32 31 30 29 +14|CLK_000_N_SYNC_6_|NOD| | => | 4 5 6 7 | 31 30 29 28 +15|CLK_000_P_SYNC_0_|NOD| | => | 4 5 6 7 | 31 30 29 28 +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 3] > IO-to-Node Pin Mapping +=========================================================================== + +- Block IO Pin + | Device Pin No.--------+ + | Pin Fixed(*)----+ | + | Sig Type--+ | | | + | Signal Name | | | | Node Destinations Via Output Matrix +_|_________________|__|___|_____|___________________________________________ + 0| VMA| IO|*| 35| => | ( 0) 1 2 3 4 5 6 7 + 1|AMIGA_BUS_ENABLE_HIGH|OUT|*| 34| => | 2 3 ( 4) 5 6 7 8 9 + 2|AMIGA_ADDR_ENABLE|OUT|*| 33| => | 4 ( 5) 6 7 8 9 10 11 + 3| UDS_000| IO|*| 32| => | 6 7 ( 8) 9 10 11 12 13 + 4| LDS_000| IO|*| 31| => | 8 9 10 11 (12) 13 14 15 + 5| DTACK|INP|*| 30| => | 10 11 12 13 14 15 0 1 + 6| BG_000| IO|*| 29| => | 12 13 14 15 0 ( 1) 2 3 + 7| BGACK_000|INP|*| 28| => | 14 15 0 1 2 3 4 5 +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 3] > IO/Node and IO/Input Macrocell Pairing Table +=========================================================================== + +- Block IO Pin + | Device Pin No.--------+ + | Pin Fixed(*)----+ | + | Sig Type--+ | | | + | Signal Name | | | | Input Macrocell and Node Pairs +_|_________________|__|___|_____|__________________________________________ + 0| VMA| IO|*| 35| => | Input macrocell [ -] + | | | | | | IO paired w/ node [ RN_VMA] + 1|AMIGA_BUS_ENABLE_HIGH|OUT|*| 34| => | Input macrocell [ -] + 2|AMIGA_ADDR_ENABLE|OUT|*| 33| => | Input macrocell [ -] + 3| UDS_000| IO|*| 32| => | Input macrocell [ -] + 4| LDS_000| IO|*| 31| => | Input macrocell [ -] + 5| DTACK|INP|*| 30| => | Input macrocell [ -] + 6| BG_000| IO|*| 29| => | Input macrocell [ -] + | | | | | | IO paired w/ node [ RN_BG_000] + 7| BGACK_000|INP|*| 28| => | Input macrocell [ -] +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 3] > Input Multiplexer (IMX) Assignments +=========================================================================== + +----- IO pin/Input Register, or Macrocell +IMX No. | +---- Block IO Pin or Macrocell Number + | | | ABEL Node/ +-- Signal using the Pin or Macrocell + | | | Pin Number | +- Signal Fixed (*) to Pin/Mcell + | | | | Sig Type | | +- Feedback Required (*) +---|-------|----|---|---|----------|------|-|------------------------------ + 0 [IOpin 0 | 35| IO VMA|*| ] paired w/[ RN_VMA] + [RegIn 0 |174| -| | ] + [MCell 0 |173|NOD RN_VMA| |*] paired w/[ VMA] + [MCell 1 |175|NOD RN_BG_000| |*] paired w/[ BG_000] + + 1 [IOpin 1 | 34|OUT AMIGA_BUS_ENABLE_HIGH|*| ] + [RegIn 1 |177| -| | ] + [MCell 2 |176|NOD inst_CLK_000_NE_D0| |*] + [MCell 3 |178|NOD CLK_000_N_SYNC_3_| |*] + + 2 [IOpin 2 | 33|OUT AMIGA_ADDR_ENABLE|*| ] + [RegIn 2 |180| -| | ] + [MCell 4 |179|OUT AMIGA_BUS_ENABLE_HIGH| | ] + [MCell 5 |181|OUT AMIGA_ADDR_ENABLE| | ] + + 3 [IOpin 3 | 32| IO UDS_000|*|*] + [RegIn 3 |183| -| | ] + [MCell 6 |182|NOD inst_CLK_000_D0| |*] + [MCell 7 |184|NOD CLK_000_N_SYNC_2_| |*] + + 4 [IOpin 4 | 31| IO LDS_000|*|*] + [RegIn 4 |186| -| | ] + [MCell 8 |185| IO UDS_000| | ] + [MCell 9 |187|NOD cpu_est_1_| |*] + + 5 [IOpin 5 | 30|INP DTACK|*|*] + [RegIn 5 |189| -| | ] + [MCell 10 |188|NOD CLK_000_N_SYNC_7_| |*] + [MCell 11 |190|NOD CLK_000_N_SYNC_0_| |*] + + 6 [IOpin 6 | 29| IO BG_000|*| ] paired w/[ RN_BG_000] + [RegIn 6 |192| -| | ] + [MCell 12 |191| IO LDS_000| | ] + [MCell 13 |193|NOD cpu_est_2_| |*] + + 7 [IOpin 7 | 28|INP BGACK_000|*|*] + [RegIn 7 |195| -| | ] + [MCell 14 |194|NOD CLK_000_N_SYNC_6_| |*] + [MCell 15 |196|NOD CLK_000_P_SYNC_0_| |*] +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 3] > Logic Array Fan-in +=========================================================================== + +- Central Switch Matrix No. + | Src (ABEL Node/Pin#) Signal +--|--|--------------------|--------------------------------------------------- +Mux00| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux01| Mcel 3 13 ( 193)| cpu_est_2_ +Mux02| Mcel 6 4 ( 251)| RN_E +Mux03| Mcel 6 5 ( 253)| inst_nEXP_SPACE_D0reg +Mux04| Mcel 3 6 ( 182)| inst_CLK_000_D0 +Mux05| IOPin 0 7 ( 98)| DS_030 +Mux06| ... | ... +Mux07| Mcel 2 8 ( 161)| inst_LDS_000_INT +Mux08| Mcel 3 7 ( 184)| CLK_000_N_SYNC_2_ +Mux09| Mcel 5 5 ( 229)| inst_DS_000_ENABLE +Mux10| Mcel 3 14 ( 194)| CLK_000_N_SYNC_6_ +Mux11| Mcel 2 13 ( 169)| CLK_000_N_SYNC_5_ +Mux12| Mcel 3 9 ( 187)| cpu_est_1_ +Mux13| Mcel 1 3 ( 130)| CLK_000_N_SYNC_1_ +Mux14| IOPin 2 6 ( 21)| BG_030 +Mux15| Mcel 2 12 ( 167)| inst_UDS_000_INT +Mux16| Mcel 4 8 ( 209)| inst_CLK_000_NE +Mux17| Mcel 3 1 ( 175)| RN_BG_000 +Mux18| Mcel 3 0 ( 173)| RN_VMA +Mux19| ... | ... +Mux20| Mcel 1 14 ( 146)| inst_VPA_D +Mux21| Input Pin ( 86)| RST +Mux22| Mcel 2 1 ( 151)| inst_AMIGA_BUS_ENABLE_DMA_HIGH +Mux23| Mcel 6 2 ( 248)| inst_CLK_000_D1 +Mux24| Input Pin ( 11)| CLK_000 +Mux25| Mcel 5 0 ( 221)| inst_CLK_000_PE +Mux26| Mcel 1 0 ( 125)| RN_RESET +Mux27| Mcel 7 5 ( 277)| inst_AS_030_D0 +Mux28| Mcel 3 2 ( 176)| inst_CLK_000_NE_D0 +Mux29| Mcel 5 4 ( 227)| SM_AMIGA_i_7_ +Mux30| Mcel 5 1 ( 223)| cpu_est_0_ +Mux31| ... | ... +Mux32| ... | ... +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 4] > Macrocell (MCell) Cluster Assignments +=========================================================================== + + Macrocell Number + | PT Requirements------ Logic XOR+ +--- Macrocell PT Cluster Size + | Sync/Async-------+ | | | Cluster to Mcell Assignment + | Node Fixed(*)----+ | | | | | +- XOR PT Size + | Sig Type-+ | | | | | | | XOR to Mcell Assignment + | Signal Name | | | | | | | | | +_|_________________|__|__|___|_____|__|______|___|__________|______________ + 0| BERR| IO| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig + 1|AMIGA_BUS_DATA_DIR|OUT| | S | 2 | 4 to [ 1]| 1 XOR free + 2| | ? | | S | | 4 free | 1 XOR free + 3| | ? | | S | | 4 free | 1 XOR free + 4| AS_000| IO| | S | 1 | 4 free | 1 XOR to [ 4] for 1 PT sig + 5| CIIN_0|NOD| | S | 2 | 4 to [ 5]| 1 XOR free + 6| | ? | | S | | 4 free | 1 XOR free + 7| | ? | | S | | 4 free | 1 XOR free + 8|inst_CLK_000_NE|NOD| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig + 9|inst_CLK_OUT_PRE_50|NOD| | S | 1 | 4 free | 1 XOR to [ 9] for 1 PT sig +10| | ? | | S | | 4 free | 1 XOR free +11| | ? | | S | | 4 free | 1 XOR free +12| CIIN|OUT| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig +13|inst_CLK_OUT_PRE_D|NOD| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig +14| | ? | | S | | 4 free | 1 XOR free +15| | ? | | S | | 4 free | 1 XOR free +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 4] > Maximum PT Capacity +=========================================================================== + + Macrocell Number + | PT Requirements------ Logic XOR+ + | Sync/Async-------+ | | + | Node Fixed(*)----+ | | | + | Sig Type-+ | | | | + | Signal Name | | | | | Maximum PT Capacity +_|_________________|__|__|___|_____|_______________________________________ + 0| BERR| IO| | S | 1 |=> can support up to [ 10] logic PT(s) + 1|AMIGA_BUS_DATA_DIR|OUT| | S | 2 |=> can support up to [ 19] logic PT(s) + 2| | ? | | S | |=> can support up to [ 14] logic PT(s) + 3| | ? | | S | |=> can support up to [ 14] logic PT(s) + 4| AS_000| IO| | S | 1 |=> can support up to [ 15] logic PT(s) + 5| CIIN_0|NOD| | S | 2 |=> can support up to [ 19] logic PT(s) + 6| | ? | | S | |=> can support up to [ 14] logic PT(s) + 7| | ? | | S | |=> can support up to [ 18] logic PT(s) + 8|inst_CLK_000_NE|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) + 9|inst_CLK_OUT_PRE_50|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) +10| | ? | | S | |=> can support up to [ 18] logic PT(s) +11| | ? | | S | |=> can support up to [ 18] logic PT(s) +12| CIIN|OUT| | S | 1 |=> can support up to [ 19] logic PT(s) +13|inst_CLK_OUT_PRE_D|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) +14| | ? | | S | |=> can support up to [ 14] logic PT(s) +15| | ? | | S | |=> can support up to [ 10] logic PT(s) +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 4] > Node-Pin Assignments +=========================================================================== + + Macrocell Number + | Node Fixed(*)------+ + | Sig Type---+ | to | Block [ 4] IO Pin | Device Pin + | Signal Name | | pin | Numbers | Numbers +_|_________________|__|_____|____________________|________________________ + 0| BERR| IO| | => | 5 6 7 ( 0)| 46 47 48 ( 41) + 1|AMIGA_BUS_DATA_DIR|OUT| | => | 5 6 ( 7) 0 | 46 47 ( 48) 41 + 2| | | | => | 6 7 0 1 | 47 48 41 42 + 3| | | | => | 6 7 0 1 | 47 48 41 42 + 4| AS_000| IO| | => | 7 0 ( 1) 2 | 48 41 ( 42) 43 + 5| CIIN_0|NOD| | => | 7 0 1 2 | 48 41 42 43 + 6| | | | => | 0 1 2 3 | 41 42 43 44 + 7| | | | => | 0 1 2 3 | 41 42 43 44 + 8|inst_CLK_000_NE|NOD| | => | 1 2 3 4 | 42 43 44 45 + 9|inst_CLK_OUT_PRE_50|NOD| | => | 1 2 3 4 | 42 43 44 45 +10| | | | => | 2 3 4 5 | 43 44 45 46 +11| | | | => | 2 3 4 5 | 43 44 45 46 +12| CIIN|OUT| | => | 3 4 5 ( 6)| 44 45 46 ( 47) +13|inst_CLK_OUT_PRE_D|NOD| | => | 3 4 5 6 | 44 45 46 47 +14| | | | => | 4 5 6 7 | 45 46 47 48 +15| | | | => | 4 5 6 7 | 45 46 47 48 +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 4] > IO-to-Node Pin Mapping +=========================================================================== + +- Block IO Pin + | Device Pin No.--------+ + | Pin Fixed(*)----+ | + | Sig Type--+ | | | + | Signal Name | | | | Node Destinations Via Output Matrix +_|_________________|__|___|_____|___________________________________________ + 0| BERR| IO|*| 41| => | ( 0) 1 2 3 4 5 6 7 + 1| AS_000| IO|*| 42| => | 2 3 ( 4) 5 6 7 8 9 + 2| | | | 43| => | 4 5 6 7 8 9 10 11 + 3| | | | 44| => | 6 7 8 9 10 11 12 13 + 4| | | | 45| => | 8 9 10 11 12 13 14 15 + 5| | | | 46| => | 10 11 12 13 14 15 0 1 + 6| CIIN|OUT|*| 47| => | (12) 13 14 15 0 1 2 3 + 7|AMIGA_BUS_DATA_DIR|OUT|*| 48| => | 14 15 0 ( 1) 2 3 4 5 +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 4] > IO/Node and IO/Input Macrocell Pairing Table +=========================================================================== + +- Block IO Pin + | Device Pin No.--------+ + | Pin Fixed(*)----+ | + | Sig Type--+ | | | + | Signal Name | | | | Input Macrocell and Node Pairs +_|_________________|__|___|_____|__________________________________________ + 0| BERR| IO|*| 41| => | Input macrocell [ -] + 1| AS_000| IO|*| 42| => | Input macrocell [ -] + 2| | | | 43| => | Input macrocell [ -] + 3| | | | 44| => | Input macrocell [ -] + 4| | | | 45| => | Input macrocell [ -] + 5| | | | 46| => | Input macrocell [ -] + 6| CIIN|OUT|*| 47| => | Input macrocell [ -] + 7|AMIGA_BUS_DATA_DIR|OUT|*| 48| => | Input macrocell [ -] +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 4] > Input Multiplexer (IMX) Assignments +=========================================================================== + +----- IO pin/Input Register, or Macrocell +IMX No. | +---- Block IO Pin or Macrocell Number + | | | ABEL Node/ +-- Signal using the Pin or Macrocell + | | | Pin Number | +- Signal Fixed (*) to Pin/Mcell + | | | | Sig Type | | +- Feedback Required (*) +---|-------|----|---|---|----------|------|-|------------------------------ + 0 [IOpin 0 | 41| IO BERR|*|*] + [RegIn 0 |198| -| | ] + [MCell 0 |197| IO BERR| | ] + [MCell 1 |199|OUT AMIGA_BUS_DATA_DIR| | ] + + 1 [IOpin 1 | 42| IO AS_000|*|*] + [RegIn 1 |201| -| | ] + [MCell 2 |200| -| | ] + [MCell 3 |202| -| | ] + + 2 [IOpin 2 | 43| -| | ] + [RegIn 2 |204| -| | ] + [MCell 4 |203| IO AS_000| | ] + [MCell 5 |205|NOD CIIN_0| |*] + + 3 [IOpin 3 | 44| -| | ] + [RegIn 3 |207| -| | ] + [MCell 6 |206| -| | ] + [MCell 7 |208| -| | ] + + 4 [IOpin 4 | 45| -| | ] + [RegIn 4 |210| -| | ] + [MCell 8 |209|NOD inst_CLK_000_NE| |*] + [MCell 9 |211|NOD inst_CLK_OUT_PRE_50| |*] + + 5 [IOpin 5 | 46| -| | ] + [RegIn 5 |213| -| | ] + [MCell 10 |212| -| | ] + [MCell 11 |214| -| | ] + + 6 [IOpin 6 | 47|OUT CIIN|*| ] + [RegIn 6 |216| -| | ] + [MCell 12 |215|OUT CIIN| | ] + [MCell 13 |217|NOD inst_CLK_OUT_PRE_D| |*] + + 7 [IOpin 7 | 48|OUT AMIGA_BUS_DATA_DIR|*| ] + [RegIn 7 |219| -| | ] + [MCell 14 |218| -| | ] + [MCell 15 |220| -| | ] +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 4] > Logic Array Fan-in +=========================================================================== + +- Central Switch Matrix No. + | Src (ABEL Node/Pin#) Signal +--|--|--------------------|--------------------------------------------------- +Mux00| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux01| IOPin 5 2 ( 58)| FC_1_ +Mux02| Mcel 4 9 ( 211)| inst_CLK_OUT_PRE_50 +Mux03| IOPin 2 3 ( 18)| A_25_ +Mux04| IOPin 1 4 ( 6)| A_29_ +Mux05| IOPin 0 3 ( 94)| A_21_ +Mux06| IOPin 7 5 ( 80)| RW_000 +Mux07| IOPin 2 0 ( 15)| A_28_ +Mux08| IOPin 0 0 ( 91)| FPU_SENSE +Mux09| IOPin 7 1 ( 84)| A_22_ +Mux10| ... | ... +Mux11| IOPin 0 5 ( 96)| A_16_ +Mux12| IOPin 0 6 ( 97)| A_19_ +Mux13| IOPin 5 1 ( 59)| A_17_ +Mux14| Mcel 4 5 ( 205)| CIIN_0 +Mux15| Mcel 2 5 ( 157)| inst_AS_000_INT +Mux16| IOPin 4 1 ( 42)| AS_000 +Mux17| IOPin 2 2 ( 17)| A_26_ +Mux18| IOPin 7 0 ( 85)| A_23_ +Mux19| IOPin 7 3 ( 82)| AS_030 +Mux20| IOPin 2 4 ( 19)| A_24_ +Mux21| IOPin 2 1 ( 16)| A_27_ +Mux22| Mcel 6 5 ( 253)| inst_nEXP_SPACE_D0reg +Mux23| ... | ... +Mux24| IOPin 5 3 ( 57)| FC_0_ +Mux25| IOPin 1 6 ( 4)| A_31_ +Mux26| Mcel 1 0 ( 125)| RN_RESET +Mux27| Mcel 7 5 ( 277)| inst_AS_030_D0 +Mux28| IOPin 1 5 ( 5)| A_30_ +Mux29| IOPin 0 2 ( 93)| A_20_ +Mux30| Mcel 7 6 ( 278)| CLK_000_N_SYNC_11_ +Mux31| IOPin 0 4 ( 95)| A_18_ +Mux32| IOPin 3 7 ( 28)| BGACK_000 +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 5] > Macrocell (MCell) Cluster Assignments +=========================================================================== + + Macrocell Number + | PT Requirements------ Logic XOR+ +--- Macrocell PT Cluster Size + | Sync/Async-------+ | | | Cluster to Mcell Assignment + | Node Fixed(*)----+ | | | | | +- XOR PT Size + | Sig Type-+ | | | | | | | XOR to Mcell Assignment + | Signal Name | | | | | | | | | +_|_________________|__|__|___|_____|__|______|___|__________|______________ + 0|inst_CLK_000_PE|NOD| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig + 1| cpu_est_0_|NOD| | S | 2 | 4 to [ 1]| 1 XOR free + 2| SM_AMIGA_2_|NOD| | S | 4 | 4 to [ 2]| 1 XOR free + 3| | ? | | S | | 4 to [ 4]| 1 XOR free + 4| SM_AMIGA_i_7_|NOD| | S |14 | 4 to [ 4]| 1 XOR to [ 4] as logic PT + 5|inst_DS_000_ENABLE|NOD| | S | 3 | 4 to [ 4]| 1 XOR to [ 4] as logic PT + 6| N_96_i|NOD| | S | 4 | 4 to [ 6]| 1 XOR free + 7| | ? | | S | | 4 to [ 5]| 1 XOR free + 8| SM_AMIGA_1_|NOD| | S | 3 | 4 to [ 8]| 1 XOR free + 9| SM_AMIGA_6_|NOD| | S | 3 | 4 to [ 9]| 1 XOR free +10| SM_AMIGA_4_|NOD| | S | 3 | 4 to [10]| 1 XOR free +11| | ? | | S | | 4 free | 1 XOR free +12| SM_AMIGA_5_|NOD| | S | 3 | 4 to [12]| 1 XOR free +13| SM_AMIGA_3_|NOD| | S | 5 | 4 to [13]| 1 XOR to [13] as logic PT +14| | ? | | S | | 4 free | 1 XOR free +15| | ? | | S | | 4 free | 1 XOR free +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 5] > Maximum PT Capacity +=========================================================================== + + Macrocell Number + | PT Requirements------ Logic XOR+ + | Sync/Async-------+ | | + | Node Fixed(*)----+ | | | + | Sig Type-+ | | | | + | Signal Name | | | | | Maximum PT Capacity +_|_________________|__|__|___|_____|_______________________________________ + 0|inst_CLK_000_PE|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) + 1| cpu_est_0_|NOD| | S | 2 |=> can support up to [ 9] logic PT(s) + 2| SM_AMIGA_2_|NOD| | S | 4 |=> can support up to [ 5] logic PT(s) + 3| | ? | | S | |=> can support up to [ 1] logic PT(s) + 4| SM_AMIGA_i_7_|NOD| | S |14 |=> can support up to [ 15] logic PT(s) + 5|inst_DS_000_ENABLE|NOD| | S | 3 |=> can support up to [ 5] logic PT(s) + 6| N_96_i|NOD| | S | 4 |=> can support up to [ 5] logic PT(s) + 7| | ? | | S | |=> can support up to [ 1] logic PT(s) + 8| SM_AMIGA_1_|NOD| | S | 3 |=> can support up to [ 5] logic PT(s) + 9| SM_AMIGA_6_|NOD| | S | 3 |=> can support up to [ 10] logic PT(s) +10| SM_AMIGA_4_|NOD| | S | 3 |=> can support up to [ 10] logic PT(s) +11| | ? | | S | |=> can support up to [ 5] logic PT(s) +12| SM_AMIGA_5_|NOD| | S | 3 |=> can support up to [ 15] logic PT(s) +13| SM_AMIGA_3_|NOD| | S | 5 |=> can support up to [ 15] logic PT(s) +14| | ? | | S | |=> can support up to [ 10] logic PT(s) +15| | ? | | S | |=> can support up to [ 10] logic PT(s) +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 5] > Node-Pin Assignments +=========================================================================== + + Macrocell Number + | Node Fixed(*)------+ + | Sig Type---+ | to | Block [ 5] IO Pin | Device Pin + | Signal Name | | pin | Numbers | Numbers +_|_________________|__|_____|____________________|________________________ + 0|inst_CLK_000_PE|NOD| | => | 5 6 7 0 | 55 54 53 60 + 1| cpu_est_0_|NOD| | => | 5 6 7 0 | 55 54 53 60 + 2| SM_AMIGA_2_|NOD| | => | 6 7 0 1 | 54 53 60 59 + 3| | | | => | 6 7 0 1 | 54 53 60 59 + 4| SM_AMIGA_i_7_|NOD| | => | 7 0 1 2 | 53 60 59 58 + 5|inst_DS_000_ENABLE|NOD| | => | 7 0 1 2 | 53 60 59 58 + 6| N_96_i|NOD| | => | 0 1 2 3 | 60 59 58 57 + 7| | | | => | 0 1 2 3 | 60 59 58 57 + 8| SM_AMIGA_1_|NOD| | => | 1 2 3 4 | 59 58 57 56 + 9| SM_AMIGA_6_|NOD| | => | 1 2 3 4 | 59 58 57 56 +10| SM_AMIGA_4_|NOD| | => | 2 3 4 5 | 58 57 56 55 +11| | | | => | 2 3 4 5 | 58 57 56 55 +12| SM_AMIGA_5_|NOD| | => | 3 4 5 6 | 57 56 55 54 +13| SM_AMIGA_3_|NOD| | => | 3 4 5 6 | 57 56 55 54 +14| | | | => | 4 5 6 7 | 56 55 54 53 +15| | | | => | 4 5 6 7 | 56 55 54 53 +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 5] > IO-to-Node Pin Mapping +=========================================================================== + +- Block IO Pin + | Device Pin No.--------+ + | Pin Fixed(*)----+ | + | Sig Type--+ | | | + | Signal Name | | | | Node Destinations Via Output Matrix +_|_________________|__|___|_____|___________________________________________ + 0| A1|INP|*| 60| => | 0 1 2 3 4 5 6 7 + 1| A_17_|INP|*| 59| => | 2 3 4 5 6 7 8 9 + 2| FC_1_|INP|*| 58| => | 4 5 6 7 8 9 10 11 + 3| FC_0_|INP|*| 57| => | 6 7 8 9 10 11 12 13 + 4| IPL_1_|INP|*| 56| => | 8 9 10 11 12 13 14 15 + 5| | | | 55| => | 10 11 12 13 14 15 0 1 + 6| | | | 54| => | 12 13 14 15 0 1 2 3 + 7| | | | 53| => | 14 15 0 1 2 3 4 5 +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 5] > IO/Node and IO/Input Macrocell Pairing Table +=========================================================================== + +- Block IO Pin + | Device Pin No.--------+ + | Pin Fixed(*)----+ | + | Sig Type--+ | | | + | Signal Name | | | | Input Macrocell and Node Pairs +_|_________________|__|___|_____|__________________________________________ + 0| A1|INP|*| 60| => | Input macrocell [ -] + 1| A_17_|INP|*| 59| => | Input macrocell [ -] + 2| FC_1_|INP|*| 58| => | Input macrocell [ -] + 3| FC_0_|INP|*| 57| => | Input macrocell [ -] + 4| IPL_1_|INP|*| 56| => | Input macrocell [ -] + 5| | | | 55| => | Input macrocell [ -] + 6| | | | 54| => | Input macrocell [ -] + 7| | | | 53| => | Input macrocell [ -] +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 5] > Input Multiplexer (IMX) Assignments +=========================================================================== + +----- IO pin/Input Register, or Macrocell +IMX No. | +---- Block IO Pin or Macrocell Number + | | | ABEL Node/ +-- Signal using the Pin or Macrocell + | | | Pin Number | +- Signal Fixed (*) to Pin/Mcell + | | | | Sig Type | | +- Feedback Required (*) +---|-------|----|---|---|----------|------|-|------------------------------ + 0 [IOpin 0 | 60|INP A1|*|*] + [RegIn 0 |222| -| | ] + [MCell 0 |221|NOD inst_CLK_000_PE| |*] + [MCell 1 |223|NOD cpu_est_0_| |*] + + 1 [IOpin 1 | 59|INP A_17_|*|*] + [RegIn 1 |225| -| | ] + [MCell 2 |224|NOD SM_AMIGA_2_| |*] + [MCell 3 |226| -| | ] + + 2 [IOpin 2 | 58|INP FC_1_|*|*] + [RegIn 2 |228| -| | ] + [MCell 4 |227|NOD SM_AMIGA_i_7_| |*] + [MCell 5 |229|NOD inst_DS_000_ENABLE| |*] + + 3 [IOpin 3 | 57|INP FC_0_|*|*] + [RegIn 3 |231| -| | ] + [MCell 6 |230|NOD N_96_i| |*] + [MCell 7 |232| -| | ] + + 4 [IOpin 4 | 56|INP IPL_1_|*|*] + [RegIn 4 |234| -| | ] + [MCell 8 |233|NOD SM_AMIGA_1_| |*] + [MCell 9 |235|NOD SM_AMIGA_6_| |*] + + 5 [IOpin 5 | 55| -| | ] + [RegIn 5 |237| -| | ] + [MCell 10 |236|NOD SM_AMIGA_4_| |*] + [MCell 11 |238| -| | ] + + 6 [IOpin 6 | 54| -| | ] + [RegIn 6 |240| -| | ] + [MCell 12 |239|NOD SM_AMIGA_5_| |*] + [MCell 13 |241|NOD SM_AMIGA_3_| |*] + + 7 [IOpin 7 | 53| -| | ] + [RegIn 7 |243| -| | ] + [MCell 14 |242| -| | ] + [MCell 15 |244| -| | ] +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 5] > Logic Array Fan-in +=========================================================================== + +- Central Switch Matrix No. + | Src (ABEL Node/Pin#) Signal +--|--|--------------------|--------------------------------------------------- +Mux00| Input Pin ( 86)| RST +Mux01| IOPin 4 0 ( 41)| BERR +Mux02| Mcel 6 4 ( 251)| RN_E +Mux03| Mcel 6 5 ( 253)| inst_nEXP_SPACE_D0reg +Mux04| Mcel 3 6 ( 182)| inst_CLK_000_D0 +Mux05| Mcel 5 0 ( 221)| inst_CLK_000_PE +Mux06| Mcel 5 13 ( 241)| SM_AMIGA_3_ +Mux07| Mcel 0 11 ( 118)| CLK_000_P_SYNC_9_ +Mux08| Mcel 4 8 ( 209)| inst_CLK_000_NE +Mux09| Mcel 5 2 ( 224)| SM_AMIGA_2_ +Mux10| Mcel 5 4 ( 227)| SM_AMIGA_i_7_ +Mux11| Mcel 5 6 ( 230)| N_96_i +Mux12| Mcel 3 9 ( 187)| cpu_est_1_ +Mux13| Mcel 7 5 ( 277)| inst_AS_030_D0 +Mux14| Mcel 5 5 ( 229)| inst_DS_000_ENABLE +Mux15| Mcel 5 1 ( 223)| cpu_est_0_ +Mux16| Mcel 3 2 ( 176)| inst_CLK_000_NE_D0 +Mux17| Mcel 5 12 ( 239)| SM_AMIGA_5_ +Mux18| Mcel 5 9 ( 235)| SM_AMIGA_6_ +Mux19| Mcel 5 10 ( 236)| SM_AMIGA_4_ +Mux20| Mcel 1 14 ( 146)| inst_VPA_D +Mux21| Mcel 3 13 ( 193)| cpu_est_2_ +Mux22| Mcel 2 2 ( 152)| inst_DTACK_D0 +Mux23| Mcel 6 2 ( 248)| inst_CLK_000_D1 +Mux24| ... | ... +Mux25| IOPin 6 6 ( 71)| RW +Mux26| Mcel 3 0 ( 173)| RN_VMA +Mux27| ... | ... +Mux28| Mcel 1 5 ( 133)| SM_AMIGA_0_ +Mux29| Mcel 2 4 ( 155)| inst_AS_030_000_SYNC +Mux30| ... | ... +Mux31| ... | ... +Mux32| Mcel 5 8 ( 233)| SM_AMIGA_1_ +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 6] > Macrocell (MCell) Cluster Assignments +=========================================================================== + + Macrocell Number + | PT Requirements------ Logic XOR+ +--- Macrocell PT Cluster Size + | Sync/Async-------+ | | | Cluster to Mcell Assignment + | Node Fixed(*)----+ | | | | | +- XOR PT Size + | Sig Type-+ | | | | | | | XOR to Mcell Assignment + | Signal Name | | | | | | | | | +_|_________________|__|__|___|_____|__|______|___|__________|______________ + 0| RW| IO| | S | 2 | 4 to [ 0]| 1 XOR free + 1| CLK_DIV_OUT|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig + 2|inst_CLK_000_D1|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig + 3|CLK_000_P_SYNC_2_|NOD| | S | 1 | 4 free | 1 XOR to [ 3] for 1 PT sig + 4| E| IO| | S | 5 | 4 to [ 4]| 1 XOR to [ 4] as logic PT + 5|inst_nEXP_SPACE_D0reg|NOD| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig + 6|CLK_000_N_SYNC_9_|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig + 7|CLK_000_P_SYNC_1_|NOD| | S | 1 | 4 free | 1 XOR to [ 7] for 1 PT sig + 8| A0| IO| | S | 3 | 4 to [ 8]| 1 XOR free + 9| SIZE_DMA_1_|NOD| | S | 3 | 4 to [ 9]| 1 XOR free +10|CLK_000_P_SYNC_6_|NOD| | S | 1 | 4 free | 1 XOR to [10] for 1 PT sig +11| IPL_D0_2_|NOD| | S | 1 | 4 free | 1 XOR to [11] for 1 PT sig +12| SIZE_0_| IO| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig +13| SIZE_DMA_0_|NOD| | S | 3 | 4 to [13]| 1 XOR free +14|CLK_000_P_SYNC_5_|NOD| | S | 1 | 4 free | 1 XOR to [14] for 1 PT sig +15| IPL_D0_1_|NOD| | S | 1 | 4 free | 1 XOR to [15] for 1 PT sig +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 6] > Maximum PT Capacity +=========================================================================== + + Macrocell Number + | PT Requirements------ Logic XOR+ + | Sync/Async-------+ | | + | Node Fixed(*)----+ | | | + | Sig Type-+ | | | | + | Signal Name | | | | | Maximum PT Capacity +_|_________________|__|__|___|_____|_______________________________________ + 0| RW| IO| | S | 2 |=> can support up to [ 13] logic PT(s) + 1| CLK_DIV_OUT|OUT| | S | 1 |=> can support up to [ 13] logic PT(s) + 2|inst_CLK_000_D1|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) + 3|CLK_000_P_SYNC_2_|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) + 4| E| IO| | S | 5 |=> can support up to [ 17] logic PT(s) + 5|inst_nEXP_SPACE_D0reg|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) + 6|CLK_000_N_SYNC_9_|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) + 7|CLK_000_P_SYNC_1_|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) + 8| A0| IO| | S | 3 |=> can support up to [ 13] logic PT(s) + 9| SIZE_DMA_1_|NOD| | S | 3 |=> can support up to [ 13] logic PT(s) +10|CLK_000_P_SYNC_6_|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) +11| IPL_D0_2_|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) +12| SIZE_0_| IO| | S | 1 |=> can support up to [ 13] logic PT(s) +13| SIZE_DMA_0_|NOD| | S | 3 |=> can support up to [ 17] logic PT(s) +14|CLK_000_P_SYNC_5_|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) +15| IPL_D0_1_|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 6] > Node-Pin Assignments +=========================================================================== + + Macrocell Number + | Node Fixed(*)------+ + | Sig Type---+ | to | Block [ 6] IO Pin | Device Pin + | Signal Name | | pin | Numbers | Numbers +_|_________________|__|_____|____________________|________________________ + 0| RW| IO| | => | 5 ( 6) 7 0 | 70 ( 71) 72 65 + 1| CLK_DIV_OUT|OUT| | => | 5 6 7 ( 0)| 70 71 72 ( 65) + 2|inst_CLK_000_D1|NOD| | => | 6 7 0 1 | 71 72 65 66 + 3|CLK_000_P_SYNC_2_|NOD| | => | 6 7 0 1 | 71 72 65 66 + 4| E| IO| | => | 7 0 ( 1) 2 | 72 65 ( 66) 67 + 5|inst_nEXP_SPACE_D0reg|NOD| | => | 7 0 1 2 | 72 65 66 67 + 6|CLK_000_N_SYNC_9_|NOD| | => | 0 1 2 3 | 65 66 67 68 + 7|CLK_000_P_SYNC_1_|NOD| | => | 0 1 2 3 | 65 66 67 68 + 8| A0| IO| | => | 1 2 3 ( 4)| 66 67 68 ( 69) + 9| SIZE_DMA_1_|NOD| | => | 1 2 3 4 | 66 67 68 69 +10|CLK_000_P_SYNC_6_|NOD| | => | 2 3 4 5 | 67 68 69 70 +11| IPL_D0_2_|NOD| | => | 2 3 4 5 | 67 68 69 70 +12| SIZE_0_| IO| | => | 3 4 ( 5) 6 | 68 69 ( 70) 71 +13| SIZE_DMA_0_|NOD| | => | 3 4 5 6 | 68 69 70 71 +14|CLK_000_P_SYNC_5_|NOD| | => | 4 5 6 7 | 69 70 71 72 +15| IPL_D0_1_|NOD| | => | 4 5 6 7 | 69 70 71 72 +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 6] > IO-to-Node Pin Mapping +=========================================================================== + +- Block IO Pin + | Device Pin No.--------+ + | Pin Fixed(*)----+ | + | Sig Type--+ | | | + | Signal Name | | | | Node Destinations Via Output Matrix +_|_________________|__|___|_____|___________________________________________ + 0| CLK_DIV_OUT|OUT|*| 65| => | 0 ( 1) 2 3 4 5 6 7 + 1| E| IO|*| 66| => | 2 3 ( 4) 5 6 7 8 9 + 2| IPL_0_|INP|*| 67| => | 4 5 6 7 8 9 10 11 + 3| IPL_2_|INP|*| 68| => | 6 7 8 9 10 11 12 13 + 4| A0| IO|*| 69| => | ( 8) 9 10 11 12 13 14 15 + 5| SIZE_0_| IO|*| 70| => | 10 11 (12) 13 14 15 0 1 + 6| RW| IO|*| 71| => | 12 13 14 15 ( 0) 1 2 3 + 7| | | | 72| => | 14 15 0 1 2 3 4 5 +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 6] > IO/Node and IO/Input Macrocell Pairing Table +=========================================================================== + +- Block IO Pin + | Device Pin No.--------+ + | Pin Fixed(*)----+ | + | Sig Type--+ | | | + | Signal Name | | | | Input Macrocell and Node Pairs +_|_________________|__|___|_____|__________________________________________ + 0| CLK_DIV_OUT|OUT|*| 65| => | Input macrocell [ -] + 1| E| IO|*| 66| => | Input macrocell [ -] + | | | | | | IO paired w/ node [ RN_E] + 2| IPL_0_|INP|*| 67| => | Input macrocell [ -] + 3| IPL_2_|INP|*| 68| => | Input macrocell [ -] + 4| A0| IO|*| 69| => | Input macrocell [ -] + | | | | | | IO paired w/ node [ RN_A0] + 5| SIZE_0_| IO|*| 70| => | Input macrocell [ -] + 6| RW| IO|*| 71| => | Input macrocell [ -] + | | | | | | IO paired w/ node [ RN_RW] + 7| | | | 72| => | Input macrocell [ -] +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 6] > Input Multiplexer (IMX) Assignments +=========================================================================== + +----- IO pin/Input Register, or Macrocell +IMX No. | +---- Block IO Pin or Macrocell Number + | | | ABEL Node/ +-- Signal using the Pin or Macrocell + | | | Pin Number | +- Signal Fixed (*) to Pin/Mcell + | | | | Sig Type | | +- Feedback Required (*) +---|-------|----|---|---|----------|------|-|------------------------------ + 0 [IOpin 0 | 65|OUT CLK_DIV_OUT|*| ] + [RegIn 0 |246| -| | ] + [MCell 0 |245|NOD RN_RW| |*] paired w/[ RW] + [MCell 1 |247|OUT CLK_DIV_OUT| | ] + + 1 [IOpin 1 | 66| IO E|*| ] paired w/[ RN_E] + [RegIn 1 |249| -| | ] + [MCell 2 |248|NOD inst_CLK_000_D1| |*] + [MCell 3 |250|NOD CLK_000_P_SYNC_2_| |*] + + 2 [IOpin 2 | 67|INP IPL_0_|*|*] + [RegIn 2 |252| -| | ] + [MCell 4 |251|NOD RN_E| |*] paired w/[ E] + [MCell 5 |253|NOD inst_nEXP_SPACE_D0reg| |*] + + 3 [IOpin 3 | 68|INP IPL_2_|*|*] + [RegIn 3 |255| -| | ] + [MCell 6 |254|NOD CLK_000_N_SYNC_9_| |*] + [MCell 7 |256|NOD CLK_000_P_SYNC_1_| |*] + + 4 [IOpin 4 | 69| IO A0|*|*] paired w/[ RN_A0] + [RegIn 4 |258| -| | ] + [MCell 8 |257|NOD RN_A0| |*] paired w/[ A0] + [MCell 9 |259|NOD SIZE_DMA_1_| |*] + + 5 [IOpin 5 | 70| IO SIZE_0_|*|*] + [RegIn 5 |261| -| | ] + [MCell 10 |260|NOD CLK_000_P_SYNC_6_| |*] + [MCell 11 |262|NOD IPL_D0_2_| |*] + + 6 [IOpin 6 | 71| IO RW|*|*] paired w/[ RN_RW] + [RegIn 6 |264| -| | ] + [MCell 12 |263| IO SIZE_0_| | ] + [MCell 13 |265|NOD SIZE_DMA_0_| |*] + + 7 [IOpin 7 | 72| -| | ] + [RegIn 7 |267| -| | ] + [MCell 14 |266|NOD CLK_000_P_SYNC_5_| |*] + [MCell 15 |268|NOD IPL_D0_1_| |*] +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 6] > Logic Array Fan-in +=========================================================================== + +- Central Switch Matrix No. + | Src (ABEL Node/Pin#) Signal +--|--|--------------------|--------------------------------------------------- +Mux00| Input Pin ( 86)| RST +Mux01| Mcel 3 13 ( 193)| cpu_est_2_ +Mux02| Mcel 6 4 ( 251)| RN_E +Mux03| IOPin 5 4 ( 56)| IPL_1_ +Mux04| IOPin 6 3 ( 68)| IPL_2_ +Mux05| Input Pin ( 14)| nEXP_SPACE +Mux06| IOPin 7 5 ( 80)| RW_000 +Mux07| Mcel 7 13 ( 289)| inst_BGACK_030_INT_D +Mux08| IOPin 3 3 ( 32)| UDS_000 +Mux09| Mcel 6 13 ( 265)| SIZE_DMA_0_ +Mux10| Mcel 6 9 ( 259)| SIZE_DMA_1_ +Mux11| Mcel 6 14 ( 266)| CLK_000_P_SYNC_5_ +Mux12| Mcel 6 7 ( 256)| CLK_000_P_SYNC_1_ +Mux13| Mcel 6 8 ( 257)| RN_A0 +Mux14| Mcel 0 10 ( 116)| CLK_000_N_SYNC_8_ +Mux15| Mcel 5 1 ( 223)| cpu_est_0_ +Mux16| Mcel 3 6 ( 182)| inst_CLK_000_D0 +Mux17| Mcel 6 0 ( 245)| RN_RW +Mux18| ... | ... +Mux19| ... | ... +Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux21| Mcel 3 15 ( 196)| CLK_000_P_SYNC_0_ +Mux22| Mcel 6 5 ( 253)| inst_nEXP_SPACE_D0reg +Mux23| ... | ... +Mux24| Mcel 1 7 ( 136)| CLK_000_P_SYNC_4_ +Mux25| Mcel 3 9 ( 187)| cpu_est_1_ +Mux26| Mcel 1 0 ( 125)| RN_RESET +Mux27| IOPin 3 4 ( 31)| LDS_000 +Mux28| Mcel 3 2 ( 176)| inst_CLK_000_NE_D0 +Mux29| ... | ... +Mux30| ... | ... +Mux31| ... | ... +Mux32| ... | ... +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 7] > Macrocell (MCell) Cluster Assignments +=========================================================================== + + Macrocell Number + | PT Requirements------ Logic XOR+ +--- Macrocell PT Cluster Size + | Sync/Async-------+ | | | Cluster to Mcell Assignment + | Node Fixed(*)----+ | | | | | +- XOR PT Size + | Sig Type-+ | | | | | | | XOR to Mcell Assignment + | Signal Name | | | | | | | | | +_|_________________|__|__|___|_____|__|______|___|__________|______________ + 0| RW_000| IO| | S | 3 | 4 to [ 0]| 1 XOR free + 1| FPU_CS|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig + 2|CLK_000_N_SYNC_10_|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig + 3| | ? | | S | | 4 free | 1 XOR free + 4| BGACK_030| IO| | S | 2 | 4 to [ 4]| 1 XOR free + 5|inst_AS_030_D0|NOD| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig + 6|CLK_000_N_SYNC_11_|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig + 7| | ? | | S | | 4 free | 1 XOR free + 8| AS_030| IO| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig + 9| DSACK1| IO| | S | 4 | 4 to [ 9]| 1 XOR free +10| | ? | | S | | 4 free | 1 XOR free +11| | ? | | S | | 4 free | 1 XOR free +12| SIZE_1_| IO| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig +13|inst_BGACK_030_INT_D|NOD| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig +14| | ? | | S | | 4 free | 1 XOR free +15| | ? | | S | | 4 free | 1 XOR free +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 7] > Maximum PT Capacity +=========================================================================== + + Macrocell Number + | PT Requirements------ Logic XOR+ + | Sync/Async-------+ | | + | Node Fixed(*)----+ | | | + | Sig Type-+ | | | | + | Signal Name | | | | | Maximum PT Capacity +_|_________________|__|__|___|_____|_______________________________________ + 0| RW_000| IO| | S | 3 |=> can support up to [ 13] logic PT(s) + 1| FPU_CS|OUT| | S | 1 |=> can support up to [ 14] logic PT(s) + 2|CLK_000_N_SYNC_10_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) + 3| | ? | | S | |=> can support up to [ 13] logic PT(s) + 4| BGACK_030| IO| | S | 2 |=> can support up to [ 18] logic PT(s) + 5|inst_AS_030_D0|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) + 6|CLK_000_N_SYNC_11_|NOD| | S | 1 |=> can support up to [ 18] logic PT(s) + 7| | ? | | S | |=> can support up to [ 13] logic PT(s) + 8| AS_030| IO| | S | 1 |=> can support up to [ 15] logic PT(s) + 9| DSACK1| IO| | S | 4 |=> can support up to [ 19] logic PT(s) +10| | ? | | S | |=> can support up to [ 14] logic PT(s) +11| | ? | | S | |=> can support up to [ 18] logic PT(s) +12| SIZE_1_| IO| | S | 1 |=> can support up to [ 19] logic PT(s) +13|inst_BGACK_030_INT_D|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) +14| | ? | | S | |=> can support up to [ 14] logic PT(s) +15| | ? | | S | |=> can support up to [ 10] logic PT(s) +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 7] > Node-Pin Assignments +=========================================================================== + + Macrocell Number + | Node Fixed(*)------+ + | Sig Type---+ | to | Block [ 7] IO Pin | Device Pin + | Signal Name | | pin | Numbers | Numbers +_|_________________|__|_____|____________________|________________________ + 0| RW_000| IO| | => |( 5) 6 7 0 |( 80) 79 78 85 + 1| FPU_CS|OUT| | => | 5 6 ( 7) 0 | 80 79 ( 78) 85 + 2|CLK_000_N_SYNC_10_|NOD| | => | 6 7 0 1 | 79 78 85 84 + 3| | | | => | 6 7 0 1 | 79 78 85 84 + 4| BGACK_030| IO| | => | 7 0 1 ( 2)| 78 85 84 ( 83) + 5|inst_AS_030_D0|NOD| | => | 7 0 1 2 | 78 85 84 83 + 6|CLK_000_N_SYNC_11_|NOD| | => | 0 1 2 3 | 85 84 83 82 + 7| | | | => | 0 1 2 3 | 85 84 83 82 + 8| AS_030| IO| | => | 1 2 ( 3) 4 | 84 83 ( 82) 81 + 9| DSACK1| IO| | => | 1 2 3 ( 4)| 84 83 82 ( 81) +10| | | | => | 2 3 4 5 | 83 82 81 80 +11| | | | => | 2 3 4 5 | 83 82 81 80 +12| SIZE_1_| IO| | => | 3 4 5 ( 6)| 82 81 80 ( 79) +13|inst_BGACK_030_INT_D|NOD| | => | 3 4 5 6 | 82 81 80 79 +14| | | | => | 4 5 6 7 | 81 80 79 78 +15| | | | => | 4 5 6 7 | 81 80 79 78 +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 7] > IO-to-Node Pin Mapping +=========================================================================== + +- Block IO Pin + | Device Pin No.--------+ + | Pin Fixed(*)----+ | + | Sig Type--+ | | | + | Signal Name | | | | Node Destinations Via Output Matrix +_|_________________|__|___|_____|___________________________________________ + 0| A_23_|INP|*| 85| => | 0 1 2 3 4 5 6 7 + 1| A_22_|INP|*| 84| => | 2 3 4 5 6 7 8 9 + 2| BGACK_030| IO|*| 83| => | ( 4) 5 6 7 8 9 10 11 + 3| AS_030| IO|*| 82| => | 6 7 ( 8) 9 10 11 12 13 + 4| DSACK1| IO|*| 81| => | 8 ( 9) 10 11 12 13 14 15 + 5| RW_000| IO|*| 80| => | 10 11 12 13 14 15 ( 0) 1 + 6| SIZE_1_| IO|*| 79| => | (12) 13 14 15 0 1 2 3 + 7| FPU_CS|OUT|*| 78| => | 14 15 0 ( 1) 2 3 4 5 +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 7] > IO/Node and IO/Input Macrocell Pairing Table +=========================================================================== + +- Block IO Pin + | Device Pin No.--------+ + | Pin Fixed(*)----+ | + | Sig Type--+ | | | + | Signal Name | | | | Input Macrocell and Node Pairs +_|_________________|__|___|_____|__________________________________________ + 0| A_23_|INP|*| 85| => | Input macrocell [ -] + 1| A_22_|INP|*| 84| => | Input macrocell [ -] + 2| BGACK_030| IO|*| 83| => | Input macrocell [ -] + | | | | | | IO paired w/ node [ RN_BGACK_030] + 3| AS_030| IO|*| 82| => | Input macrocell [ -] + 4| DSACK1| IO|*| 81| => | Input macrocell [ -] + | | | | | | IO paired w/ node [ RN_DSACK1] + 5| RW_000| IO|*| 80| => | Input macrocell [ -] + | | | | | | IO paired w/ node [ RN_RW_000] + 6| SIZE_1_| IO|*| 79| => | Input macrocell [ -] + 7| FPU_CS|OUT|*| 78| => | Input macrocell [ -] +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 7] > Input Multiplexer (IMX) Assignments +=========================================================================== + +----- IO pin/Input Register, or Macrocell +IMX No. | +---- Block IO Pin or Macrocell Number + | | | ABEL Node/ +-- Signal using the Pin or Macrocell + | | | Pin Number | +- Signal Fixed (*) to Pin/Mcell + | | | | Sig Type | | +- Feedback Required (*) +---|-------|----|---|---|----------|------|-|------------------------------ + 0 [IOpin 0 | 85|INP A_23_|*|*] + [RegIn 0 |270| -| | ] + [MCell 0 |269|NOD RN_RW_000| |*] paired w/[ RW_000] + [MCell 1 |271|OUT FPU_CS| | ] + + 1 [IOpin 1 | 84|INP A_22_|*|*] + [RegIn 1 |273| -| | ] + [MCell 2 |272|NOD CLK_000_N_SYNC_10_| |*] + [MCell 3 |274| -| | ] + + 2 [IOpin 2 | 83| IO BGACK_030|*| ] paired w/[ RN_BGACK_030] + [RegIn 2 |276| -| | ] + [MCell 4 |275|NOD RN_BGACK_030| |*] paired w/[ BGACK_030] + [MCell 5 |277|NOD inst_AS_030_D0| |*] + + 3 [IOpin 3 | 82| IO AS_030|*|*] + [RegIn 3 |279| -| | ] + [MCell 6 |278|NOD CLK_000_N_SYNC_11_| |*] + [MCell 7 |280| -| | ] + + 4 [IOpin 4 | 81| IO DSACK1|*| ] paired w/[ RN_DSACK1] + [RegIn 4 |282| -| | ] + [MCell 8 |281| IO AS_030| | ] + [MCell 9 |283|NOD RN_DSACK1| |*] paired w/[ DSACK1] + + 5 [IOpin 5 | 80| IO RW_000|*|*] paired w/[ RN_RW_000] + [RegIn 5 |285| -| | ] + [MCell 10 |284| -| | ] + [MCell 11 |286| -| | ] + + 6 [IOpin 6 | 79| IO SIZE_1_|*|*] + [RegIn 6 |288| -| | ] + [MCell 12 |287| IO SIZE_1_| | ] + [MCell 13 |289|NOD inst_BGACK_030_INT_D| |*] + + 7 [IOpin 7 | 78|OUT FPU_CS|*| ] + [RegIn 7 |291| -| | ] + [MCell 14 |290| -| | ] + [MCell 15 |292| -| | ] +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 7] > Logic Array Fan-in +=========================================================================== + +- Central Switch Matrix No. + | Src (ABEL Node/Pin#) Signal +--|--|--------------------|--------------------------------------------------- +Mux00| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux01| IOPin 4 0 ( 41)| BERR +Mux02| Mcel 4 13 ( 217)| inst_CLK_OUT_PRE_D +Mux03| Mcel 0 8 ( 113)| inst_AS_000_DMA +Mux04| Mcel 7 5 ( 277)| inst_AS_030_D0 +Mux05| Mcel 5 0 ( 221)| inst_CLK_000_PE +Mux06| IOPin 0 6 ( 97)| A_19_ +Mux07| ... | ... +Mux08| IOPin 0 0 ( 91)| FPU_SENSE +Mux09| Mcel 6 13 ( 265)| SIZE_DMA_0_ +Mux10| Mcel 6 9 ( 259)| SIZE_DMA_1_ +Mux11| IOPin 0 5 ( 96)| A_16_ +Mux12| IOPin 5 2 ( 58)| FC_1_ +Mux13| IOPin 5 1 ( 59)| A_17_ +Mux14| Mcel 7 2 ( 272)| CLK_000_N_SYNC_10_ +Mux15| ... | ... +Mux16| IOPin 4 1 ( 42)| AS_000 +Mux17| IOPin 0 4 ( 95)| A_18_ +Mux18| IOPin 3 7 ( 28)| BGACK_000 +Mux19| IOPin 7 3 ( 82)| AS_030 +Mux20| Input Pin ( 64)| CLK_030 +Mux21| Input Pin ( 86)| RST +Mux22| Mcel 6 5 ( 253)| inst_nEXP_SPACE_D0reg +Mux23| Mcel 6 6 ( 254)| CLK_000_N_SYNC_9_ +Mux24| IOPin 5 3 ( 57)| FC_0_ +Mux25| IOPin 6 6 ( 71)| RW +Mux26| Mcel 1 0 ( 125)| RN_RESET +Mux27| Mcel 7 9 ( 283)| RN_DSACK1 +Mux28| Mcel 1 5 ( 133)| SM_AMIGA_0_ +Mux29| Mcel 5 4 ( 227)| SM_AMIGA_i_7_ +Mux30| Mcel 7 0 ( 269)| RN_RW_000 +Mux31| Mcel 5 12 ( 239)| SM_AMIGA_5_ +Mux32| Mcel 5 8 ( 233)| SM_AMIGA_1_ +--------------------------------------------------------------------------- \ No newline at end of file diff --git a/Logic/68030_tk.rpt b/Logic/68030_tk.rpt new file mode 100644 index 0000000..efd6d25 --- /dev/null +++ b/Logic/68030_tk.rpt @@ -0,0 +1,1914 @@ +|--------------------------------------------| +|- ispLEVER Fitter Report File -| +|- Version 1.8.00.04.29.14 -| +|- (c)Copyright, Lattice Semiconductor 2002 -| +|--------------------------------------------| + + + + +Project_Summary +~~~~~~~~~~~~~~~ + +Project Name : 68030_tk +Project Path : C:\Users\Matze\Documents\GitHub\68030tk\Logic +Project Fitted on : Wed May 13 22:59:29 2015 + +Device : M4A5-128/64 +Package : 100TQFP +Speed : -10 +Partnumber : M4A5-128/64-10VC +Source Format : Pure_VHDL + + +// Project '68030_tk' was Fitted Successfully! // + + +Compilation_Times +~~~~~~~~~~~~~~~~~ +Reading/DRC 0 sec +Partition 0 sec +Place 0 sec +Route 0 sec +Jedec/Report generation 0 sec + -------- +Fitter 00:00:00 + + +Design_Summary +~~~~~~~~~~~~~~ + Total Input Pins : 32 + Total Output Pins : 18 + Total Bidir I/O Pins : 11 + Total Flip-Flops : 83 + Total Product Terms : 254 + Total Reserved Pins : 0 + Total Reserved Blocks : 0 + + +Device_Resource_Summary +~~~~~~~~~~~~~~~~~~~~~~~ + Total + Available Used Available Utilization +Dedicated Pins + Input-Only Pins 2 2 0 --> 100% + Clock/Input Pins 4 4 0 --> 100% +I/O Pins 64 55 9 --> 85% +Logic Macrocells 128 102 26 --> 79% + Input Registers 64 0 64 --> 0% + Unusable Macrocells .. 0 .. + +CSM Outputs/Total Block Inputs 264 233 31 --> 88% +Logical Product Terms 640 255 385 --> 39% +Product Term Clusters 128 59 69 --> 46% + + +Blocks_Resource_Summary +~~~~~~~~~~~~~~~~~~~~~~~ + # of PT + I/O Inp Macrocells Macrocells logic clusters + Fanin Pins Reg Used Unusable available PTs available Pwr +--------------------------------------------------------------------------------- +Maximum 33 8 8 -- -- 16 80 16 - +--------------------------------------------------------------------------------- +Block A 30 8 0 16 0 0 50 4 Lo +Block B 29 8 0 16 0 0 57 3 Lo +Block C 28 7 0 9 0 7 23 9 Lo +Block D 29 8 0 16 0 0 27 11 Lo +Block E 31 4 0 8 0 8 10 14 Lo +Block F 29 5 0 11 0 5 45 4 Lo +Block G 26 7 0 16 0 0 27 11 Lo +Block H 31 8 0 10 0 6 16 13 Lo +--------------------------------------------------------------------------------- + + Four rightmost columns above reflect last status of the placement process. + Pwr (Power) : Hi = High + Lo = Low. + + +Optimizer_and_Fitter_Options +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Pin Assignment : Yes +Group Assignment : No +Pin Reservation : No (1) +Block Reservation : No + +@Ignore_Project_Constraints : + Pin Assignments : No + Keep Block Assignment -- + Keep Segment Assignment -- + Group Assignments : No + Macrocell Assignment : No + Keep Block Assignment -- + Keep Segment Assignment -- + +@Backannotate_Project_Constraints + Pin Assignments : No + Pin And Block Assignments : No + Pin, Macrocell and Block : No + +@Timing_Constraints : No + +@Global_Project_Optimization : + Balanced Partitioning : Yes + Spread Placement : Yes + + Note : + Pack Design : + Balanced Partitioning = No + Spread Placement = No + Spread Design : + Balanced Partitioning = Yes + Spread Placement = Yes + +@Logic_Synthesis : + Logic Reduction : Yes + Node Collapsing : Yes + D/T Synthesis : Yes + Clock Optimization : No + Input Register Optimization : Yes + XOR Synthesis : Yes + Max. P-Term for Collapsing : 16 + Max. P-Term for Splitting : 16 + Max. Equation Fanin : 32 + Keep Xor : Yes + +@Utilization_options + Max. % of macrocells used : 100 + Max. % of block inputs used : 100 + Max. % of segment lines used : --- + Max. % of macrocells used : --- + + +@Import_Source_Constraint_Option No + +@Zero_Hold_Time Yes + +@Pull_up Yes + +@User_Signature #H0 + +@Output_Slew_Rate Default = Slow(2) + +@Power Default = High(2) + + +Device Options: + 1 : Reserved unused I/Os can be independently driven to Low or High, and does not + follow the drive level set for the Global Configure Unused I/O Option. + 2 : For user-specified constraints on individual signals, refer to the Output, + Bidir and Burried Signal Lists. + + + + +Pinout_Listing +~~~~~~~~~~~~~~ + | Pin |Blk |Assigned| +Pin No| Type |Pad |Pin | Signal name +--------------------------------------------------------------- + 1 | GND | | | + 2 | JTAG | | | + 3 | I_O | B7 | * |RESET +4 | I_O | B6 | * |A_31_ +5 | I_O | B5 | * |A_30_ +6 | I_O | B4 | * |A_29_ +7 | I_O | B3 | * |IPL_030_1_ +8 | I_O | B2 | * |IPL_030_0_ +9 | I_O | B1 | * |IPL_030_2_ +10 | I_O | B0 | * |CLK_EXP +11 | CkIn | | * |CLK_000 +12 | Vcc | | | +13 | GND | | | +14 | CkIn | | * |nEXP_SPACE +15 | I_O | C0 | * |A_28_ +16 | I_O | C1 | * |A_27_ +17 | I_O | C2 | * |A_26_ +18 | I_O | C3 | * |A_25_ +19 | I_O | C4 | * |A_24_ +20 | I_O | C5 | * |AMIGA_BUS_ENABLE_LOW +21 | I_O | C6 | * |BG_030 +22 | I_O | C7 | | +23 | JTAG | | | +24 | JTAG | | | +25 | GND | | | +26 | GND | | | +27 | GND | | | +28 | I_O | D7 | * |BGACK_000 +29 | I_O | D6 | * |BG_000 +30 | I_O | D5 | * |DTACK +31 | I_O | D4 | * |LDS_000 +32 | I_O | D3 | * |UDS_000 +33 | I_O | D2 | * |AMIGA_ADDR_ENABLE +34 | I_O | D1 | * |AMIGA_BUS_ENABLE_HIGH +35 | I_O | D0 | * |VMA +36 | Inp | | * |VPA +37 | Vcc | | | +38 | GND | | | +39 | GND | | | +40 | Vcc | | | +41 | I_O | E0 | * |BERR +42 | I_O | E1 | * |AS_000 +43 | I_O | E2 | | +44 | I_O | E3 | | +45 | I_O | E4 | | +46 | I_O | E5 | | +47 | I_O | E6 | * |CIIN +48 | I_O | E7 | * |AMIGA_BUS_DATA_DIR +49 | GND | | | +50 | GND | | | +51 | GND | | | +52 | JTAG | | | +53 | I_O | F7 | | +54 | I_O | F6 | | +55 | I_O | F5 | | +56 | I_O | F4 | * |IPL_1_ +57 | I_O | F3 | * |FC_0_ +58 | I_O | F2 | * |FC_1_ +59 | I_O | F1 | * |A_17_ +60 | I_O | F0 | * |A1 +61 | CkIn | | * |CLK_OSZI +62 | Vcc | | | +63 | GND | | | +64 | CkIn | | * |CLK_030 +65 | I_O | G0 | * |CLK_DIV_OUT +66 | I_O | G1 | * |E +67 | I_O | G2 | * |IPL_0_ +68 | I_O | G3 | * |IPL_2_ +69 | I_O | G4 | * |A0 +70 | I_O | G5 | * |SIZE_0_ +71 | I_O | G6 | * |RW +72 | I_O | G7 | | +73 | JTAG | | | +74 | JTAG | | | +75 | GND | | | +76 | GND | | | +77 | GND | | | +78 | I_O | H7 | * |FPU_CS +79 | I_O | H6 | * |SIZE_1_ +80 | I_O | H5 | * |RW_000 +81 | I_O | H4 | * |DSACK1 +82 | I_O | H3 | * |AS_030 +83 | I_O | H2 | * |BGACK_030 +84 | I_O | H1 | * |A_22_ +85 | I_O | H0 | * |A_23_ +86 | Inp | | * |RST +87 | Vcc | | | +88 | GND | | | +89 | GND | | | +90 | Vcc | | | +91 | I_O | A0 | * |FPU_SENSE +92 | I_O | A1 | * |AVEC +93 | I_O | A2 | * |A_20_ +94 | I_O | A3 | * |A_21_ +95 | I_O | A4 | * |A_18_ +96 | I_O | A5 | * |A_16_ +97 | I_O | A6 | * |A_19_ +98 | I_O | A7 | * |DS_030 +99 | GND | | | +100 | GND | | | + +--------------------------------------------------------------------------- + + Blk Pad : This notation refers to the Block I/O pad number in the device. + Assigned Pin : user or dedicated input assignment (E.g. Clock pins). + Pin Type : + CkIn : Dedicated input or clock pin + CLK : Dedicated clock pin + INP : Dedicated input pin + JTAG : JTAG Control and test pin + NC : No connected + + + +Input_Signal_List +~~~~~~~~~~~~~~~~~ + P R + Pin r e O Input +Pin Blk PTs Type e s E Fanout Pwr Slew Signal +---------------------------------------------------------------------- + 60 F . I/O --C----- Low Slow A1 + 96 A . I/O --C-E--H Low Slow A_16_ + 59 F . I/O --C-E--H Low Slow A_17_ + 95 A . I/O --C-E--H Low Slow A_18_ + 97 A . I/O --C-E--H Low Slow A_19_ + 93 A . I/O ----E--- Low Slow A_20_ + 94 A . I/O ----E--- Low Slow A_21_ + 84 H . I/O ----E--- Low Slow A_22_ + 85 H . I/O ----E--- Low Slow A_23_ + 19 C . I/O ----E--- Low Slow A_24_ + 18 C . I/O ----E--- Low Slow A_25_ + 17 C . I/O ----E--- Low Slow A_26_ + 16 C . I/O ----E--- Low Slow A_27_ + 15 C . I/O ----E--- Low Slow A_28_ + 6 B . I/O ----E--- Low Slow A_29_ + 5 B . I/O ----E--- Low Slow A_30_ + 4 B . I/O ----E--- Low Slow A_31_ + 28 D . I/O ----E--H Low Slow BGACK_000 + 21 C . I/O ---D---- Low Slow BG_030 + 30 D . I/O --C----- Low Slow DTACK + 57 F . I/O --C-E--H Low Slow FC_0_ + 58 F . I/O --C-E--H Low Slow FC_1_ + 91 A . I/O ----E--H Low Slow FPU_SENSE + 67 G . I/O -B------ Low Slow IPL_0_ + 56 F . I/O -B----G- Low Slow IPL_1_ + 68 G . I/O -B----G- Low Slow IPL_2_ + 11 . . Ck/I ---D---- - Slow CLK_000 + 14 . . Ck/I ------G- - Slow nEXP_SPACE + 36 . . Ded -B------ - Slow VPA + 61 . . Ck/I ABCDEFGH - Slow CLK_OSZI + 64 . . Ck/I AB-----H - Slow CLK_030 + 86 . . Ded ABCD-FGH - Slow RST +---------------------------------------------------------------------- + + Power : Hi = High + MH = Medium High + ML = Medium Low + Lo = Low + + + +Output_Signal_List +~~~~~~~~~~~~~~~~~~ + P R + Pin r e O Output +Pin Blk PTs Type e s E Fanout Pwr Slew Signal +---------------------------------------------------------------------- + 33 D 1 COM -------- Low Fast AMIGA_ADDR_ENABLE + 48 E 2 COM -------- Low Fast AMIGA_BUS_DATA_DIR + 34 D 2 COM -------- Low Fast AMIGA_BUS_ENABLE_HIGH + 20 C 1 COM -------- Low Fast AMIGA_BUS_ENABLE_LOW + 92 A 1 COM -------- Low Slow AVEC + 83 H 2 DFF * * -------- Low Slow BGACK_030 + 29 D 2 DFF * * -------- Low Slow BG_000 + 47 E 1 COM -------- Low Slow CIIN + 65 G 1 COM -------- Low Fast CLK_DIV_OUT + 10 B 1 COM -------- Low Fast CLK_EXP + 81 H 4 DFF * * -------- Low Slow DSACK1 + 66 G 5 DFF * * -------- Low Slow E + 78 H 1 COM -------- Low Fast FPU_CS + 8 B 10 DFF * * -------- Low Slow IPL_030_0_ + 7 B 10 DFF * * -------- Low Slow IPL_030_1_ + 9 B 10 DFF * * -------- Low Slow IPL_030_2_ + 3 B 2 DFF * * -------- Low Slow RESET + 35 D 3 TFF * * -------- Low Slow VMA +---------------------------------------------------------------------- + + Power : Hi = High + MH = Medium High + ML = Medium Low + Lo = Low + + + +Bidir_Signal_List +~~~~~~~~~~~~~~~~~ + P R + Pin r e O Bidir +Pin Blk PTs Type e s E Fanout Pwr Slew Signal +---------------------------------------------------------------------- + 69 G 3 DFF * * --C----- Low Slow A0 + 42 E 1 COM A---E--H Low Slow AS_000 + 82 H 1 COM ----E--H Low Slow AS_030 + 41 E 1 COM -BC--F-H Low Slow BERR + 98 A 1 COM A--D---- Low Slow DS_030 + 31 D 1 COM A-----G- Low Slow LDS_000 + 71 G 2 DFF * * -----F-H Low Slow RW + 80 H 3 DFF * * A---E-G- Low Slow RW_000 + 70 G 1 COM --C----- Low Slow SIZE_0_ + 79 H 1 COM --C----- Low Slow SIZE_1_ + 32 D 1 COM A-----G- Low Slow UDS_000 +---------------------------------------------------------------------- + + Power : Hi = High + MH = Medium High + ML = Medium Low + Lo = Low + + + +Buried_Signal_List +~~~~~~~~~~~~~~~~~~ + P R + Pin r e O Node +#Mc Blk PTs Type e s E Fanout Pwr Slew Signal +---------------------------------------------------------------------- + E5 E 2 COM ----E--- Low Slow CIIN_0 + D11 D 1 DFF * * -B------ Low Slow CLK_000_N_SYNC_0_ + H2 H 1 DFF * * -------H Low Slow CLK_000_N_SYNC_10_ + H6 H 1 DFF * * ----E--- Low Slow CLK_000_N_SYNC_11_ + B3 B 1 DFF * * ---D---- Low Slow CLK_000_N_SYNC_1_ + D7 D 1 DFF * * ---D---- Low Slow CLK_000_N_SYNC_2_ + D3 D 1 DFF * * A------- Low Slow CLK_000_N_SYNC_3_ + A14 A 1 DFF * * --C----- Low Slow CLK_000_N_SYNC_4_ + C13 C 1 DFF * * ---D---- Low Slow CLK_000_N_SYNC_5_ + D14 D 1 DFF * * ---D---- Low Slow CLK_000_N_SYNC_6_ + D10 D 1 DFF * * A------- Low Slow CLK_000_N_SYNC_7_ + A10 A 1 DFF * * ------G- Low Slow CLK_000_N_SYNC_8_ + G6 G 1 DFF * * -------H Low Slow CLK_000_N_SYNC_9_ + D15 D 1 DFF * * ------G- Low Slow CLK_000_P_SYNC_0_ + G7 G 1 DFF * * ------G- Low Slow CLK_000_P_SYNC_1_ + G3 G 1 DFF * * -B------ Low Slow CLK_000_P_SYNC_2_ + B11 B 1 DFF * * -B------ Low Slow CLK_000_P_SYNC_3_ + B7 B 1 DFF * * ------G- Low Slow CLK_000_P_SYNC_4_ + G14 G 1 DFF * * ------G- Low Slow CLK_000_P_SYNC_5_ + G10 G 1 DFF * * A------- Low Slow CLK_000_P_SYNC_6_ + A7 A 1 DFF * * A------- Low Slow CLK_000_P_SYNC_7_ + A3 A 1 DFF * * A------- Low Slow CLK_000_P_SYNC_8_ + A11 A 1 DFF * * -----F-- Low Slow CLK_000_P_SYNC_9_ + A6 A 2 DFF * * A------- Low Slow CYCLE_DMA_0_ + A2 A 3 DFF * * A------- Low Slow CYCLE_DMA_1_ + B15 B 1 DFF * * -B------ Low Slow IPL_D0_0_ + G15 G 1 DFF * * -B------ Low Slow IPL_D0_1_ + G11 G 1 DFF * * -B------ Low Slow IPL_D0_2_ + F6 F 4 COM -----F-- Low Slow N_96_i + G8 G 3 DFF * * ------G- Low - RN_A0 --> A0 + H4 H 2 DFF * * A-CDE-GH Low - RN_BGACK_030 --> BGACK_030 + D1 D 2 DFF * * ---D---- Low - RN_BG_000 --> BG_000 + H9 H 4 DFF * * -------H Low - RN_DSACK1 --> DSACK1 + G4 G 5 DFF * * ---D-FG- Low - RN_E --> E + B8 B 10 DFF * * -B------ Low - RN_IPL_030_0_ --> IPL_030_0_ + B12 B 10 DFF * * -B------ Low - RN_IPL_030_1_ --> IPL_030_1_ + B4 B 10 DFF * * -B------ Low - RN_IPL_030_2_ --> IPL_030_2_ + B0 B 2 DFF * * AB-DE-GH Low - RN_RESET --> RESET + G0 G 2 DFF * * ------G- Low - RN_RW --> RW + H0 H 3 DFF * * -------H Low - RN_RW_000 --> RW_000 + D0 D 3 TFF * * ---D-F-- Low - RN_VMA --> VMA + B6 B 3 DFF * * AB------ Low Slow RST_DLY_0_ + A1 A 4 DFF * * AB------ Low Slow RST_DLY_1_ + B9 B 5 DFF * * AB------ Low Slow RST_DLY_2_ + A12 A 6 DFF * * AB------ Low Slow RST_DLY_3_ + A5 A 2 TFF * * AB------ Low Slow RST_DLY_4_ + B13 B 4 TFF * * AB------ Low Slow RST_DLY_5_ + B2 B 3 TFF * * AB------ Low Slow RST_DLY_6_ + B10 B 2 DFF * * AB------ Low Slow RST_DLY_7_ + G13 G 3 DFF * * ------GH Low Slow SIZE_DMA_0_ + G9 G 3 DFF * * ------GH Low Slow SIZE_DMA_1_ + B5 B 2 DFF * * -B---F-H Low Slow SM_AMIGA_0_ + F8 F 3 DFF * * -B---F-H Low Slow SM_AMIGA_1_ + F2 F 4 DFF * * -----F-- Low Slow SM_AMIGA_2_ + F13 F 5 TFF * * -----F-- Low Slow SM_AMIGA_3_ + F10 F 3 DFF * * -----F-- Low Slow SM_AMIGA_4_ + F12 F 3 DFF * * --C--F-H Low Slow SM_AMIGA_5_ + F9 F 3 DFF * * --C--F-- Low Slow SM_AMIGA_6_ + F4 F 14 DFF * * --CD-F-H Low Slow SM_AMIGA_i_7_ + F1 F 2 DFF * * ---D-FG- Low Slow cpu_est_0_ + D9 D 5 DFF * * ---D-FG- Low Slow cpu_est_1_ + D13 D 4 DFF * * ---D-FG- Low Slow cpu_est_2_ + C1 C 2 DFF * * --CD---- Low Slow inst_AMIGA_BUS_ENABLE_DMA_HIGH + C9 C 2 DFF * * --C----- Low Slow inst_AMIGA_BUS_ENABLE_DMA_LOW + A8 A 7 DFF * * A------H Low Slow inst_AS_000_DMA + C5 C 2 DFF * * --C-E--- Low Slow inst_AS_000_INT + C4 C 7 DFF * * --C--F-- Low Slow inst_AS_030_000_SYNC + H5 H 1 DFF * * --CDEF-H Low Slow inst_AS_030_D0 + H13 H 1 DFF * * --C---G- Low Slow inst_BGACK_030_INT_D + D6 D 1 DFF * * ---D-FG- Low Slow inst_CLK_000_D0 + G2 G 1 DFF * * ---D-F-- Low Slow inst_CLK_000_D1 + E8 E 1 DFF * * AB-D-F-- Low Slow inst_CLK_000_NE + D2 D 1 DFF * * ---D-FG- Low Slow inst_CLK_000_NE_D0 + F0 F 1 DFF * * AB-D-F-H Low Slow inst_CLK_000_PE + A13 A 8 DFF * * A------- Low Slow inst_CLK_030_H + E9 E 1 DFF * * ----E--- Low Slow inst_CLK_OUT_PRE_50 + E13 E 1 DFF * * -------H Low Slow inst_CLK_OUT_PRE_D + A9 A 9 DFF * * A------- Low Slow inst_DS_000_DMA + F5 F 3 DFF * * ---D-F-- Low Slow inst_DS_000_ENABLE + A15 A 1 DFF * * --C----- Low Slow inst_DS_030_D0 + C2 C 1 DFF * * -----F-- Low Slow inst_DTACK_D0 + C8 C 4 DFF * * --CD---- Low Slow inst_LDS_000_INT + C12 C 3 DFF * * --CD---- Low Slow inst_UDS_000_INT + B14 B 1 DFF * * ---D-F-- Low Slow inst_VPA_D + G5 G 1 DFF * * A-CDEFGH Low Slow inst_nEXP_SPACE_D0reg +---------------------------------------------------------------------- + + Power : Hi = High + MH = Medium High + ML = Medium Low + Lo = Low + + + + +Signals_Fanout_List +~~~~~~~~~~~~~~~~~~~ +Signal Source : Fanout List +----------------------------------------------------------------------------- + A_28_{ D}: CIIN{ E} CIIN_0{ E} + A_27_{ D}: CIIN{ E} CIIN_0{ E} + SIZE_1_{ I}:inst_LDS_000_INT{ C} + A_26_{ D}: CIIN{ E} CIIN_0{ E} + A_25_{ D}: CIIN{ E} CIIN_0{ E} + A_31_{ C}: CIIN{ E} CIIN_0{ E} + A_24_{ D}: CIIN{ E} CIIN_0{ E} + A_23_{ I}: CIIN{ E} CIIN_0{ E} + A_22_{ I}: CIIN{ E} CIIN_0{ E} + A_21_{ B}: CIIN{ E} CIIN_0{ E} + IPL_2_{ H}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} + : IPL_D0_2_{ G} + A_20_{ B}: CIIN{ E} CIIN_0{ E} + A_19_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C} + FC_1_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C} + A_18_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C} + AS_030{ I}: AS_000{ E} BERR{ E} FPU_CS{ H} + : inst_AS_030_D0{ H} + A_17_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C} + AS_000{ F}: AS_030{ H} DS_030{ A}AMIGA_BUS_DATA_DIR{ E} + :inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} CYCLE_DMA_0_{ A} + : CYCLE_DMA_1_{ A} inst_CLK_030_H{ A} + A_16_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C} + DS_030{ B}: UDS_000{ D} LDS_000{ D} inst_DS_030_D0{ A} + UDS_000{ E}: A0{ G}inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} + : SIZE_DMA_0_{ G} SIZE_DMA_1_{ G} inst_CLK_030_H{ A} + LDS_000{ E}:inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} SIZE_DMA_0_{ G} + : SIZE_DMA_1_{ G} inst_CLK_030_H{ A} + A1{ G}:inst_AMIGA_BUS_ENABLE_DMA_LOW{ C}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ C} + nEXP_SPACE{. }:inst_nEXP_SPACE_D0reg{ G} + BERR{ F}: DSACK1{ H}inst_AS_000_INT{ C} SM_AMIGA_5_{ F} + :inst_AS_030_000_SYNC{ C} SM_AMIGA_3_{ F} SM_AMIGA_0_{ B} + : SM_AMIGA_6_{ F} SM_AMIGA_1_{ F} SM_AMIGA_4_{ F} + : SM_AMIGA_2_{ F}inst_DS_000_ENABLE{ F} SM_AMIGA_i_7_{ F} + BG_030{ D}: BG_000{ D} + BGACK_000{ E}: BERR{ E} FPU_CS{ H} BGACK_030{ H} + CLK_030{. }: CLK_EXP{ B} DSACK1{ H}inst_AS_000_DMA{ A} + :inst_DS_000_DMA{ A} inst_CLK_030_H{ A} + CLK_000{. }:inst_CLK_000_D0{ D} + IPL_1_{ G}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} + : IPL_D0_1_{ G} + IPL_0_{ H}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} + : IPL_D0_0_{ B} + FPU_SENSE{ B}: BERR{ E} FPU_CS{ H} + FC_0_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C} + DTACK{ E}: inst_DTACK_D0{ C} + VPA{. }: inst_VPA_D{ B} + RST{. }: IPL_030_2_{ B} RW_000{ H} A0{ G} + : BG_000{ D} BGACK_030{ H} IPL_030_1_{ B} + : IPL_030_0_{ B} DSACK1{ H} VMA{ D} + : RESET{ B} RW{ G}inst_AS_000_INT{ C} + : SM_AMIGA_5_{ F}inst_AMIGA_BUS_ENABLE_DMA_LOW{ C} inst_AS_030_D0{ H} + :inst_nEXP_SPACE_D0reg{ G} inst_DS_030_D0{ A}inst_AS_030_000_SYNC{ C} + :inst_BGACK_030_INT_D{ H}inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} + : CYCLE_DMA_0_{ A} CYCLE_DMA_1_{ A} SIZE_DMA_0_{ G} + : SIZE_DMA_1_{ G} inst_VPA_D{ B}inst_UDS_000_INT{ C} + :inst_LDS_000_INT{ C} inst_DTACK_D0{ C} IPL_D0_0_{ B} + : IPL_D0_1_{ G} IPL_D0_2_{ G} SM_AMIGA_3_{ F} + : SM_AMIGA_0_{ B}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ C} SM_AMIGA_6_{ F} + : RST_DLY_0_{ B} RST_DLY_1_{ A} RST_DLY_2_{ B} + : RST_DLY_3_{ A} RST_DLY_4_{ A} RST_DLY_5_{ B} + : RST_DLY_6_{ B} RST_DLY_7_{ B} inst_CLK_030_H{ A} + : SM_AMIGA_1_{ F} SM_AMIGA_4_{ F} SM_AMIGA_2_{ F} + :inst_DS_000_ENABLE{ F} SM_AMIGA_i_7_{ F} + SIZE_0_{ H}:inst_LDS_000_INT{ C} + A_30_{ C}: CIIN{ E} CIIN_0{ E} + A_29_{ C}: CIIN{ E} CIIN_0{ E} +RN_IPL_030_2_{ C}: IPL_030_2_{ B} + RW_000{ I}:AMIGA_BUS_DATA_DIR{ E} RW{ G}inst_DS_000_DMA{ A} + RN_RW_000{ I}: RW_000{ H} + A0{ H}:inst_UDS_000_INT{ C}inst_LDS_000_INT{ C} + RN_A0{ H}: A0{ G} + RN_BG_000{ E}: BG_000{ D} +RN_BGACK_030{ I}: SIZE_1_{ H} AS_030{ H} AS_000{ E} + : DS_030{ A} UDS_000{ D} LDS_000{ D} + :AMIGA_BUS_DATA_DIR{ E}AMIGA_BUS_ENABLE_LOW{ C}AMIGA_BUS_ENABLE_HIGH{ D} + : SIZE_0_{ G} RW_000{ H} A0{ G} + : BGACK_030{ H} RW{ G}inst_AMIGA_BUS_ENABLE_DMA_LOW{ C} + :inst_AS_030_000_SYNC{ C}inst_BGACK_030_INT_D{ H}inst_AS_000_DMA{ A} + :inst_DS_000_DMA{ A} CYCLE_DMA_0_{ A} CYCLE_DMA_1_{ A} + : SIZE_DMA_0_{ G} SIZE_DMA_1_{ G}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ C} + : inst_CLK_030_H{ A} +RN_IPL_030_1_{ C}: IPL_030_1_{ B} +RN_IPL_030_0_{ C}: IPL_030_0_{ B} + RN_DSACK1{ I}: DSACK1{ H} + RN_E{ H}: E{ G} VMA{ D} cpu_est_1_{ D} + : cpu_est_2_{ D} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} + : SM_AMIGA_i_7_{ F} + RN_VMA{ E}: VMA{ D} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} + : SM_AMIGA_i_7_{ F} + RN_RESET{ C}: AS_030{ H} AS_000{ E} DS_030{ A} + : UDS_000{ D} LDS_000{ D} RW_000{ H} + : A0{ G} RESET{ B} RW{ G} + RW{ H}: RW_000{ H}inst_DS_000_ENABLE{ F} + RN_RW{ H}: RW{ G} + cpu_est_0_{ G}: E{ G} VMA{ D} cpu_est_0_{ F} + : cpu_est_1_{ D} cpu_est_2_{ D} SM_AMIGA_3_{ F} + : SM_AMIGA_2_{ F} SM_AMIGA_i_7_{ F} + cpu_est_1_{ E}: E{ G} VMA{ D} cpu_est_1_{ D} + : cpu_est_2_{ D} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} + : SM_AMIGA_i_7_{ F} +inst_AS_000_INT{ D}: AS_000{ E}inst_AS_000_INT{ C} +SM_AMIGA_5_{ G}: RW_000{ H}inst_AS_000_INT{ C} SM_AMIGA_5_{ F} + : N_96_i{ F} SM_AMIGA_4_{ F}inst_DS_000_ENABLE{ F} + : SM_AMIGA_i_7_{ F} +inst_AMIGA_BUS_ENABLE_DMA_LOW{ D}:AMIGA_BUS_ENABLE_LOW{ C}inst_AMIGA_BUS_ENABLE_DMA_LOW{ C} +inst_AS_030_D0{ I}: CIIN{ E} BG_000{ D} DSACK1{ H} + :inst_AS_000_INT{ C}inst_AS_030_000_SYNC{ C}inst_DS_000_ENABLE{ F} + : CIIN_0{ E} +inst_nEXP_SPACE_D0reg{ H}: SIZE_1_{ H} AS_030{ H} DS_030{ A} + :AMIGA_BUS_DATA_DIR{ E} SIZE_0_{ G} A0{ G} + : BG_000{ D} DSACK1{ H}inst_AS_030_000_SYNC{ C} + : N_96_i{ F} SM_AMIGA_6_{ F} CIIN_0{ E} +inst_DS_030_D0{ B}:inst_UDS_000_INT{ C}inst_LDS_000_INT{ C} +inst_AS_030_000_SYNC{ D}:inst_AS_030_000_SYNC{ C} N_96_i{ F} SM_AMIGA_6_{ F} +inst_BGACK_030_INT_D{ I}: A0{ G} RW{ G}inst_AMIGA_BUS_ENABLE_DMA_LOW{ C} + :inst_AS_030_000_SYNC{ C} SIZE_DMA_0_{ G} SIZE_DMA_1_{ G} + :inst_AMIGA_BUS_ENABLE_DMA_HIGH{ C} +inst_AS_000_DMA{ B}: AS_030{ H}inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} + : inst_CLK_030_H{ A} +inst_DS_000_DMA{ B}: DS_030{ A}inst_DS_000_DMA{ A} +CYCLE_DMA_0_{ B}:inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} CYCLE_DMA_0_{ A} + : CYCLE_DMA_1_{ A} inst_CLK_030_H{ A} +CYCLE_DMA_1_{ B}:inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} CYCLE_DMA_1_{ A} + : inst_CLK_030_H{ A} +SIZE_DMA_0_{ H}: SIZE_1_{ H} SIZE_0_{ G} SIZE_DMA_0_{ G} +SIZE_DMA_1_{ H}: SIZE_1_{ H} SIZE_0_{ G} SIZE_DMA_1_{ G} + inst_VPA_D{ C}: VMA{ D} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} + : SM_AMIGA_i_7_{ F} +inst_UDS_000_INT{ D}: UDS_000{ D}inst_UDS_000_INT{ C} +inst_LDS_000_INT{ D}: LDS_000{ D}inst_LDS_000_INT{ C} +inst_CLK_OUT_PRE_D{ F}: DSACK1{ H} +inst_DTACK_D0{ D}: SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} SM_AMIGA_i_7_{ F} +inst_CLK_OUT_PRE_50{ F}:inst_CLK_OUT_PRE_D{ E}inst_CLK_OUT_PRE_50{ E} +inst_CLK_000_D1{ H}: N_96_i{ F} SM_AMIGA_6_{ F}CLK_000_P_SYNC_0_{ D} + :CLK_000_N_SYNC_0_{ D} +inst_CLK_000_D0{ E}: BG_000{ D}inst_CLK_000_D1{ G} N_96_i{ F} + : SM_AMIGA_6_{ F}CLK_000_P_SYNC_0_{ D}CLK_000_N_SYNC_0_{ D} +inst_CLK_000_PE{ G}: RW_000{ H} BGACK_030{ H} VMA{ D} + : SM_AMIGA_5_{ F} CYCLE_DMA_0_{ A} CYCLE_DMA_1_{ A} + : SM_AMIGA_3_{ F} SM_AMIGA_0_{ B} SM_AMIGA_6_{ F} + : SM_AMIGA_1_{ F} SM_AMIGA_4_{ F} SM_AMIGA_2_{ F} + : SM_AMIGA_i_7_{ F} +CLK_000_P_SYNC_9_{ B}:inst_CLK_000_PE{ F} +inst_CLK_000_NE{ F}: VMA{ D} RESET{ B} SM_AMIGA_5_{ F} + :inst_CLK_000_NE_D0{ D} SM_AMIGA_0_{ B} RST_DLY_0_{ B} + : RST_DLY_1_{ A} RST_DLY_2_{ B} RST_DLY_3_{ A} + : RST_DLY_4_{ A} RST_DLY_5_{ B} RST_DLY_6_{ B} + : RST_DLY_7_{ B} SM_AMIGA_1_{ F} SM_AMIGA_4_{ F} + : SM_AMIGA_i_7_{ F} + N_96_i{ G}: SM_AMIGA_i_7_{ F} +CLK_000_N_SYNC_11_{ I}:inst_CLK_000_NE{ E} + cpu_est_2_{ E}: E{ G} VMA{ D} cpu_est_1_{ D} + : cpu_est_2_{ D} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} + : SM_AMIGA_i_7_{ F} + IPL_D0_0_{ C}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} + IPL_D0_1_{ H}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} + IPL_D0_2_{ H}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} +SM_AMIGA_3_{ G}: N_96_i{ F} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} + :inst_DS_000_ENABLE{ F} SM_AMIGA_i_7_{ F} +inst_CLK_000_NE_D0{ E}: E{ G} cpu_est_0_{ F} cpu_est_1_{ D} + : cpu_est_2_{ D} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} + : SM_AMIGA_i_7_{ F} +SM_AMIGA_0_{ C}: RW_000{ H} N_96_i{ F} SM_AMIGA_0_{ B} + : SM_AMIGA_i_7_{ F} +inst_AMIGA_BUS_ENABLE_DMA_HIGH{ D}:AMIGA_BUS_ENABLE_HIGH{ D}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ C} +SM_AMIGA_6_{ G}: SM_AMIGA_5_{ F}inst_UDS_000_INT{ C}inst_LDS_000_INT{ C} + : N_96_i{ F} SM_AMIGA_6_{ F} SM_AMIGA_i_7_{ F} + RST_DLY_0_{ C}: RESET{ B} RST_DLY_0_{ B} RST_DLY_1_{ A} + : RST_DLY_2_{ B} RST_DLY_3_{ A} RST_DLY_4_{ A} + : RST_DLY_5_{ B} RST_DLY_6_{ B} RST_DLY_7_{ B} + RST_DLY_1_{ B}: RESET{ B} RST_DLY_0_{ B} RST_DLY_1_{ A} + : RST_DLY_2_{ B} RST_DLY_3_{ A} RST_DLY_4_{ A} + : RST_DLY_5_{ B} RST_DLY_6_{ B} RST_DLY_7_{ B} + RST_DLY_2_{ C}: RESET{ B} RST_DLY_0_{ B} RST_DLY_1_{ A} + : RST_DLY_2_{ B} RST_DLY_3_{ A} RST_DLY_4_{ A} + : RST_DLY_5_{ B} RST_DLY_6_{ B} RST_DLY_7_{ B} + RST_DLY_3_{ B}: RESET{ B} RST_DLY_0_{ B} RST_DLY_1_{ A} + : RST_DLY_2_{ B} RST_DLY_3_{ A} RST_DLY_4_{ A} + : RST_DLY_5_{ B} RST_DLY_6_{ B} RST_DLY_7_{ B} + RST_DLY_4_{ B}: RESET{ B} RST_DLY_0_{ B} RST_DLY_1_{ A} + : RST_DLY_2_{ B} RST_DLY_3_{ A} RST_DLY_4_{ A} + : RST_DLY_5_{ B} RST_DLY_6_{ B} RST_DLY_7_{ B} + RST_DLY_5_{ C}: RESET{ B} RST_DLY_0_{ B} RST_DLY_1_{ A} + : RST_DLY_2_{ B} RST_DLY_3_{ A} RST_DLY_4_{ A} + : RST_DLY_5_{ B} RST_DLY_6_{ B} RST_DLY_7_{ B} + RST_DLY_6_{ C}: RESET{ B} RST_DLY_0_{ B} RST_DLY_1_{ A} + : RST_DLY_2_{ B} RST_DLY_3_{ A} RST_DLY_4_{ A} + : RST_DLY_5_{ B} RST_DLY_6_{ B} RST_DLY_7_{ B} + RST_DLY_7_{ C}: RESET{ B} RST_DLY_0_{ B} RST_DLY_1_{ A} + : RST_DLY_2_{ B} RST_DLY_3_{ A} RST_DLY_4_{ A} + : RST_DLY_5_{ B} RST_DLY_6_{ B} RST_DLY_7_{ B} +CLK_000_P_SYNC_0_{ E}:CLK_000_P_SYNC_1_{ G} +CLK_000_P_SYNC_1_{ H}:CLK_000_P_SYNC_2_{ G} +CLK_000_P_SYNC_2_{ H}:CLK_000_P_SYNC_3_{ B} +CLK_000_P_SYNC_3_{ C}:CLK_000_P_SYNC_4_{ B} +CLK_000_P_SYNC_4_{ C}:CLK_000_P_SYNC_5_{ G} +CLK_000_P_SYNC_5_{ H}:CLK_000_P_SYNC_6_{ G} +CLK_000_P_SYNC_6_{ H}:CLK_000_P_SYNC_7_{ A} +CLK_000_P_SYNC_7_{ B}:CLK_000_P_SYNC_8_{ A} +CLK_000_P_SYNC_8_{ B}:CLK_000_P_SYNC_9_{ A} +CLK_000_N_SYNC_0_{ E}:CLK_000_N_SYNC_1_{ B} +CLK_000_N_SYNC_1_{ C}:CLK_000_N_SYNC_2_{ D} +CLK_000_N_SYNC_2_{ E}:CLK_000_N_SYNC_3_{ D} +CLK_000_N_SYNC_3_{ E}:CLK_000_N_SYNC_4_{ A} +CLK_000_N_SYNC_4_{ B}:CLK_000_N_SYNC_5_{ C} +CLK_000_N_SYNC_5_{ D}:CLK_000_N_SYNC_6_{ D} +CLK_000_N_SYNC_6_{ E}:CLK_000_N_SYNC_7_{ D} +CLK_000_N_SYNC_7_{ E}:CLK_000_N_SYNC_8_{ A} +CLK_000_N_SYNC_8_{ B}:CLK_000_N_SYNC_9_{ G} +CLK_000_N_SYNC_9_{ H}: DSACK1{ H}CLK_000_N_SYNC_10_{ H} +CLK_000_N_SYNC_10_{ I}: DSACK1{ H}CLK_000_N_SYNC_11_{ H} +inst_CLK_030_H{ B}:inst_DS_000_DMA{ A} inst_CLK_030_H{ A} +SM_AMIGA_1_{ G}: DSACK1{ H} N_96_i{ F} SM_AMIGA_0_{ B} + : SM_AMIGA_1_{ F} SM_AMIGA_i_7_{ F} +SM_AMIGA_4_{ G}: N_96_i{ F} SM_AMIGA_3_{ F} SM_AMIGA_4_{ F} + : SM_AMIGA_i_7_{ F} +SM_AMIGA_2_{ G}: N_96_i{ F} SM_AMIGA_1_{ F} SM_AMIGA_2_{ F} + : SM_AMIGA_i_7_{ F} +inst_DS_000_ENABLE{ G}: UDS_000{ D} LDS_000{ D}inst_DS_000_ENABLE{ F} +SM_AMIGA_i_7_{ G}:AMIGA_BUS_ENABLE_HIGH{ D} RW_000{ H}inst_AS_030_000_SYNC{ C} + : SM_AMIGA_6_{ F} + CIIN_0{ F}: CIIN{ E} +----------------------------------------------------------------------------- + + {.} : Indicates block location of signal + + +Set_Reset_Summary +~~~~~~~~~~~~~~~~~ + +Block A +block level set pt : GND +block level reset pt : GND +Equations : +| | |Block|Block| Signal +| Reg |Mode |Set |Reset| Name ++-----+-----+-----+-----+------------------------ +| | | | | DS_030 +| | | | | AVEC +| * | S | BS | BR | inst_AS_000_DMA +| * | S | BS | BR | RST_DLY_3_ +| * | S | BS | BR | RST_DLY_1_ +| * | S | BS | BR | RST_DLY_4_ +| * | S | BS | BR | inst_DS_000_DMA +| * | S | BS | BR | inst_CLK_030_H +| * | S | BS | BR | CYCLE_DMA_1_ +| * | S | BS | BR | CYCLE_DMA_0_ +| * | S | BS | BR | CLK_000_N_SYNC_8_ +| * | S | BS | BR | CLK_000_N_SYNC_4_ +| * | S | BS | BR | CLK_000_P_SYNC_8_ +| * | S | BS | BR | CLK_000_P_SYNC_7_ +| * | S | BS | BR | CLK_000_P_SYNC_9_ +| * | S | BS | BR | inst_DS_030_D0 +| | | | | A_19_ +| | | | | A_16_ +| | | | | A_18_ +| | | | | FPU_SENSE +| | | | | A_21_ +| | | | | A_20_ + + +Block B +block level set pt : GND +block level reset pt : GND +Equations : +| | |Block|Block| Signal +| Reg |Mode |Set |Reset| Name ++-----+-----+-----+-----+------------------------ +| * | S | BS | BR | IPL_030_2_ +| * | S | BS | BR | IPL_030_0_ +| * | S | BS | BR | IPL_030_1_ +| * | S | BS | BR | RESET +| | | | | CLK_EXP +| * | S | BS | BR | RN_RESET +| * | S | BS | BR | SM_AMIGA_0_ +| * | S | BS | BR | RST_DLY_2_ +| * | S | BS | BR | RST_DLY_5_ +| * | S | BS | BR | RST_DLY_6_ +| * | S | BS | BR | RST_DLY_0_ +| * | S | BS | BR | RST_DLY_7_ +| * | S | BS | BR | inst_VPA_D +| * | S | BS | BR | RN_IPL_030_0_ +| * | S | BS | BR | RN_IPL_030_1_ +| * | S | BS | BR | RN_IPL_030_2_ +| * | S | BS | BR | CLK_000_N_SYNC_1_ +| * | S | BS | BR | CLK_000_P_SYNC_4_ +| * | S | BS | BR | CLK_000_P_SYNC_3_ +| * | S | BS | BR | IPL_D0_0_ +| | | | | A_29_ +| | | | | A_30_ +| | | | | A_31_ + + +Block C +block level set pt : GND +block level reset pt : GND +Equations : +| | |Block|Block| Signal +| Reg |Mode |Set |Reset| Name ++-----+-----+-----+-----+------------------------ +| | | | | AMIGA_BUS_ENABLE_LOW +| * | S | BS | BR | inst_AS_030_000_SYNC +| * | S | BS | BR | inst_LDS_000_INT +| * | S | BS | BR | inst_UDS_000_INT +| * | S | BS | BR | inst_AMIGA_BUS_ENABLE_DMA_HIGH +| * | S | BS | BR | inst_AS_000_INT +| * | S | BS | BR | inst_AMIGA_BUS_ENABLE_DMA_LOW +| * | S | BS | BR | CLK_000_N_SYNC_5_ +| * | S | BS | BR | inst_DTACK_D0 +| | | | | BG_030 +| | | | | A_24_ +| | | | | A_25_ +| | | | | A_26_ +| | | | | A_27_ +| | | | | A_28_ + + +Block D +block level set pt : GND +block level reset pt : GND +Equations : +| | |Block|Block| Signal +| Reg |Mode |Set |Reset| Name ++-----+-----+-----+-----+------------------------ +| | | | | UDS_000 +| | | | | LDS_000 +| * | S | BS | BR | VMA +| | | | | AMIGA_BUS_ENABLE_HIGH +| * | S | BS | BR | BG_000 +| | | | | AMIGA_ADDR_ENABLE +| * | S | BS | BR | cpu_est_1_ +| * | S | BS | BR | cpu_est_2_ +| * | S | BS | BR | inst_CLK_000_NE_D0 +| * | S | BS | BR | inst_CLK_000_D0 +| * | S | BS | BR | RN_VMA +| * | S | BS | BR | RN_BG_000 +| * | S | BS | BR | CLK_000_N_SYNC_7_ +| * | S | BS | BR | CLK_000_N_SYNC_6_ +| * | S | BS | BR | CLK_000_N_SYNC_3_ +| * | S | BS | BR | CLK_000_N_SYNC_2_ +| * | S | BS | BR | CLK_000_N_SYNC_0_ +| * | S | BS | BR | CLK_000_P_SYNC_0_ +| | | | | BGACK_000 +| | | | | DTACK + + +Block E +block level set pt : GND +block level reset pt : GND +Equations : +| | |Block|Block| Signal +| Reg |Mode |Set |Reset| Name ++-----+-----+-----+-----+------------------------ +| | | | | BERR +| | | | | AS_000 +| | | | | AMIGA_BUS_DATA_DIR +| | | | | CIIN +| * | S | BS | BR | inst_CLK_000_NE +| | | | | CIIN_0 +| * | S | BS | BR | inst_CLK_OUT_PRE_50 +| * | S | BS | BR | inst_CLK_OUT_PRE_D + + +Block F +block level set pt : GND +block level reset pt : GND +Equations : +| | |Block|Block| Signal +| Reg |Mode |Set |Reset| Name ++-----+-----+-----+-----+------------------------ +| * | S | BS | BR | inst_CLK_000_PE +| * | S | BS | BR | SM_AMIGA_i_7_ +| * | S | BS | BR | SM_AMIGA_1_ +| * | S | BS | BR | SM_AMIGA_5_ +| * | S | BS | BR | cpu_est_0_ +| * | S | BS | BR | inst_DS_000_ENABLE +| * | S | BS | BR | SM_AMIGA_6_ +| * | S | BS | BR | SM_AMIGA_3_ +| * | S | BS | BR | SM_AMIGA_2_ +| | | | | N_96_i +| * | S | BS | BR | SM_AMIGA_4_ +| | | | | A_17_ +| | | | | FC_1_ +| | | | | FC_0_ +| | | | | IPL_1_ +| | | | | A1 + + +Block G +block level set pt : GND +block level reset pt : GND +Equations : +| | |Block|Block| Signal +| Reg |Mode |Set |Reset| Name ++-----+-----+-----+-----+------------------------ +| * | S | BS | BR | RW +| * | S | BS | BR | A0 +| | | | | SIZE_0_ +| * | S | BS | BR | E +| | | | | CLK_DIV_OUT +| * | S | BS | BR | inst_nEXP_SPACE_D0reg +| * | S | BS | BR | RN_E +| * | S | BS | BR | SIZE_DMA_1_ +| * | S | BS | BR | SIZE_DMA_0_ +| * | S | BS | BR | inst_CLK_000_D1 +| * | S | BS | BR | RN_A0 +| * | S | BS | BR | RN_RW +| * | S | BS | BR | CLK_000_N_SYNC_9_ +| * | S | BS | BR | CLK_000_P_SYNC_6_ +| * | S | BS | BR | CLK_000_P_SYNC_5_ +| * | S | BS | BR | CLK_000_P_SYNC_2_ +| * | S | BS | BR | CLK_000_P_SYNC_1_ +| * | S | BS | BR | IPL_D0_2_ +| * | S | BS | BR | IPL_D0_1_ +| | | | | IPL_2_ +| | | | | IPL_0_ + + +Block H +block level set pt : GND +block level reset pt : GND +Equations : +| | |Block|Block| Signal +| Reg |Mode |Set |Reset| Name ++-----+-----+-----+-----+------------------------ +| * | S | BS | BR | RW_000 +| | | | | AS_030 +| | | | | SIZE_1_ +| * | S | BS | BR | DSACK1 +| * | S | BS | BR | BGACK_030 +| | | | | FPU_CS +| * | S | BS | BR | RN_BGACK_030 +| * | S | BS | BR | inst_AS_030_D0 +| * | S | BS | BR | inst_BGACK_030_INT_D +| * | S | BS | BR | RN_DSACK1 +| * | S | BS | BR | RN_RW_000 +| * | S | BS | BR | CLK_000_N_SYNC_10_ +| * | S | BS | BR | CLK_000_N_SYNC_11_ +| | | | | A_23_ +| | | | | A_22_ + + + (S) means the macrocell is configured in synchronous mode + i.e. it uses the block-level set and reset pt. + (A) means the macrocell is configured in asynchronous mode + i.e. it can have its independant set or reset pt. + (BS) means the block-level set pt is selected. + (BR) means the block-level reset pt is selected. + + + + +BLOCK_A_LOGIC_ARRAY_FANIN +~~~~~~~~~~~~~~~~~~~~~~~~~ +CSM Signal Source CSM Signal Source +------------------------------------ ------------------------------------ +mx A0 CYCLE_DMA_1_ mcell A2 mx A17 ... ... +mx A1CLK_000_P_SYNC_7_ mcell A7 mx A18 RST_DLY_4_ mcell A5 +mx A2 RST_DLY_7_ mcell B10 mx A19 inst_DS_000_DMA mcell A9 +mx A3inst_nEXP_SPACE_D0reg mcell G5 mx A20CLK_000_N_SYNC_7_ mcell D10 +mx A4 CLK_030 pin 64 mx A21 RST_DLY_1_ mcell A1 +mx A5 DS_030 pin 98 mx A22CLK_000_P_SYNC_6_ mcell G10 +mx A6 RW_000 pin 80 mx A23 RN_BGACK_030 mcell H4 +mx A7 ... ... mx A24 RST pin 86 +mx A8 inst_CLK_000_NE mcell E8 mx A25 inst_CLK_030_H mcell A13 +mx A9 RST_DLY_3_ mcell A12 mx A26 AS_000 pin 42 +mx A10 RST_DLY_6_ mcell B2 mx A27 LDS_000 pin 31 +mx A11 RST_DLY_0_ mcell B6 mx A28 RST_DLY_5_ mcell B13 +mx A12 UDS_000 pin 32 mx A29 RN_RESET mcell B0 +mx A13CLK_000_N_SYNC_3_ mcell D3 mx A30 inst_AS_000_DMA mcell A8 +mx A14 ... ... mx A31 inst_CLK_000_PE mcell F0 +mx A15 CYCLE_DMA_0_ mcell A6 mx A32CLK_000_P_SYNC_8_ mcell A3 +mx A16 RST_DLY_2_ mcell B9 +---------------------------------------------------------------------------- + + +BLOCK_B_LOGIC_ARRAY_FANIN +~~~~~~~~~~~~~~~~~~~~~~~~~ +CSM Signal Source CSM Signal Source +------------------------------------ ------------------------------------ +mx B0 RST pin 86 mx B17 RN_IPL_030_0_ mcell B8 +mx B1 BERR pin 41 mx B18 IPL_D0_1_ mcell G15 +mx B2 RST_DLY_7_ mcell B10 mx B19CLK_000_N_SYNC_0_ mcell D11 +mx B3 IPL_1_ pin 56 mx B20 CLK_030 pin 64 +mx B4 IPL_2_ pin 68 mx B21 RST_DLY_1_ mcell A1 +mx B5 inst_CLK_000_PE mcell F0 mx B22 ... ... +mx B6 RST_DLY_2_ mcell B9 mx B23 ... ... +mx B7CLK_000_P_SYNC_3_ mcell B11 mx B24CLK_000_P_SYNC_2_ mcell G3 +mx B8 inst_CLK_000_NE mcell E8 mx B25 RST_DLY_6_ mcell B2 +mx B9 IPL_D0_2_ mcell G11 mx B26 RN_RESET mcell B0 +mx B10 RST_DLY_5_ mcell B13 mx B27 IPL_D0_0_ mcell B15 +mx B11 RST_DLY_0_ mcell B6 mx B28 RST_DLY_4_ mcell A5 +mx B12 RN_IPL_030_1_ mcell B12 mx B29 ... ... +mx B13 VPA pin 36 mx B30 RN_IPL_030_2_ mcell B4 +mx B14 ... ... mx B31 SM_AMIGA_0_ mcell B5 +mx B15 RST_DLY_3_ mcell A12 mx B32 SM_AMIGA_1_ mcell F8 +mx B16 IPL_0_ pin 67 +---------------------------------------------------------------------------- + + +BLOCK_C_LOGIC_ARRAY_FANIN +~~~~~~~~~~~~~~~~~~~~~~~~~ +CSM Signal Source CSM Signal Source +------------------------------------ ------------------------------------ +mx C0 A0 pin 69 mx C17 A_18_ pin 95 +mx C1 FC_1_ pin 58 mx C18 SM_AMIGA_6_ mcell F9 +mx C2 ... ... mx C19inst_BGACK_030_INT_D mcell H13 +mx C3CLK_000_N_SYNC_4_ mcell A14 mx C20 RN_BGACK_030 mcell H4 +mx C4 inst_AS_030_D0 mcell H5 mx C21 RST pin 86 +mx C5 ... ... mx C22inst_AMIGA_BUS_ENABLE_DMA_HIGH mcell C1 +mx C6 A_16_ pin 96 mx C23inst_AMIGA_BUS_ENABLE_DMA_LOW mcell C9 +mx C7 inst_AS_000_INT mcell C5 mx C24 FC_0_ pin 57 +mx C8 A_17_ pin 59 mx C25 BERR pin 41 +mx C9 DTACK pin 30 mx C26 ... ... +mx C10 SM_AMIGA_i_7_ mcell F4 mx C27 SIZE_1_ pin 79 +mx C11 A1 pin 60 mx C28 ... ... +mx C12 A_19_ pin 97 mx C29inst_AS_030_000_SYNC mcell C4 +mx C13 inst_DS_030_D0 mcell A15 mx C30 ... ... +mx C14 SIZE_0_ pin 70 mx C31 SM_AMIGA_5_ mcell F12 +mx C15inst_UDS_000_INT mcell C12 mx C32inst_nEXP_SPACE_D0reg mcell G5 +mx C16inst_LDS_000_INT mcell C8 +---------------------------------------------------------------------------- + + +BLOCK_D_LOGIC_ARRAY_FANIN +~~~~~~~~~~~~~~~~~~~~~~~~~ +CSM Signal Source CSM Signal Source +------------------------------------ ------------------------------------ +mx D0 RN_BGACK_030 mcell H4 mx D17 RN_BG_000 mcell D1 +mx D1 cpu_est_2_ mcell D13 mx D18 RN_VMA mcell D0 +mx D2 RN_E mcell G4 mx D19 ... ... +mx D3inst_nEXP_SPACE_D0reg mcell G5 mx D20 inst_VPA_D mcell B14 +mx D4 inst_CLK_000_D0 mcell D6 mx D21 RST pin 86 +mx D5 DS_030 pin 98 mx D22inst_AMIGA_BUS_ENABLE_DMA_HIGH mcell C1 +mx D6 ... ... mx D23 inst_CLK_000_D1 mcell G2 +mx D7inst_LDS_000_INT mcell C8 mx D24 CLK_000 pin 11 +mx D8CLK_000_N_SYNC_2_ mcell D7 mx D25 inst_CLK_000_PE mcell F0 +mx D9inst_DS_000_ENABLE mcell F5 mx D26 RN_RESET mcell B0 +mx D10CLK_000_N_SYNC_6_ mcell D14 mx D27 inst_AS_030_D0 mcell H5 +mx D11CLK_000_N_SYNC_5_ mcell C13 mx D28inst_CLK_000_NE_D0 mcell D2 +mx D12 cpu_est_1_ mcell D9 mx D29 SM_AMIGA_i_7_ mcell F4 +mx D13CLK_000_N_SYNC_1_ mcell B3 mx D30 cpu_est_0_ mcell F1 +mx D14 BG_030 pin 21 mx D31 ... ... +mx D15inst_UDS_000_INT mcell C12 mx D32 ... ... +mx D16 inst_CLK_000_NE mcell E8 +---------------------------------------------------------------------------- + + +BLOCK_E_LOGIC_ARRAY_FANIN +~~~~~~~~~~~~~~~~~~~~~~~~~ +CSM Signal Source CSM Signal Source +------------------------------------ ------------------------------------ +mx E0 RN_BGACK_030 mcell H4 mx E17 A_26_ pin 17 +mx E1 FC_1_ pin 58 mx E18 A_23_ pin 85 +mx E2inst_CLK_OUT_PRE_50 mcell E9 mx E19 AS_030 pin 82 +mx E3 A_25_ pin 18 mx E20 A_24_ pin 19 +mx E4 A_29_ pin 6 mx E21 A_27_ pin 16 +mx E5 A_21_ pin 94 mx E22inst_nEXP_SPACE_D0reg mcell G5 +mx E6 RW_000 pin 80 mx E23 ... ... +mx E7 A_28_ pin 15 mx E24 FC_0_ pin 57 +mx E8 FPU_SENSE pin 91 mx E25 A_31_ pin 4 +mx E9 A_22_ pin 84 mx E26 RN_RESET mcell B0 +mx E10 ... ... mx E27 inst_AS_030_D0 mcell H5 +mx E11 A_16_ pin 96 mx E28 A_30_ pin 5 +mx E12 A_19_ pin 97 mx E29 A_20_ pin 93 +mx E13 A_17_ pin 59 mx E30CLK_000_N_SYNC_11_ mcell H6 +mx E14 CIIN_0 mcell E5 mx E31 A_18_ pin 95 +mx E15 inst_AS_000_INT mcell C5 mx E32 BGACK_000 pin 28 +mx E16 AS_000 pin 42 +---------------------------------------------------------------------------- + + +BLOCK_F_LOGIC_ARRAY_FANIN +~~~~~~~~~~~~~~~~~~~~~~~~~ +CSM Signal Source CSM Signal Source +------------------------------------ ------------------------------------ +mx F0 RST pin 86 mx F17 SM_AMIGA_5_ mcell F12 +mx F1 BERR pin 41 mx F18 SM_AMIGA_6_ mcell F9 +mx F2 RN_E mcell G4 mx F19 SM_AMIGA_4_ mcell F10 +mx F3inst_nEXP_SPACE_D0reg mcell G5 mx F20 inst_VPA_D mcell B14 +mx F4 inst_CLK_000_D0 mcell D6 mx F21 cpu_est_2_ mcell D13 +mx F5 inst_CLK_000_PE mcell F0 mx F22 inst_DTACK_D0 mcell C2 +mx F6 SM_AMIGA_3_ mcell F13 mx F23 inst_CLK_000_D1 mcell G2 +mx F7CLK_000_P_SYNC_9_ mcell A11 mx F24 ... ... +mx F8 inst_CLK_000_NE mcell E8 mx F25 RW pin 71 +mx F9 SM_AMIGA_2_ mcell F2 mx F26 RN_VMA mcell D0 +mx F10 SM_AMIGA_i_7_ mcell F4 mx F27 ... ... +mx F11 N_96_i mcell F6 mx F28 SM_AMIGA_0_ mcell B5 +mx F12 cpu_est_1_ mcell D9 mx F29inst_AS_030_000_SYNC mcell C4 +mx F13 inst_AS_030_D0 mcell H5 mx F30 ... ... +mx F14inst_DS_000_ENABLE mcell F5 mx F31 ... ... +mx F15 cpu_est_0_ mcell F1 mx F32 SM_AMIGA_1_ mcell F8 +mx F16inst_CLK_000_NE_D0 mcell D2 +---------------------------------------------------------------------------- + + +BLOCK_G_LOGIC_ARRAY_FANIN +~~~~~~~~~~~~~~~~~~~~~~~~~ +CSM Signal Source CSM Signal Source +------------------------------------ ------------------------------------ +mx G0 RST pin 86 mx G17 RN_RW mcell G0 +mx G1 cpu_est_2_ mcell D13 mx G18 ... ... +mx G2 RN_E mcell G4 mx G19 ... ... +mx G3 IPL_1_ pin 56 mx G20 RN_BGACK_030 mcell H4 +mx G4 IPL_2_ pin 68 mx G21CLK_000_P_SYNC_0_ mcell D15 +mx G5 nEXP_SPACE pin 14 mx G22inst_nEXP_SPACE_D0reg mcell G5 +mx G6 RW_000 pin 80 mx G23 ... ... +mx G7inst_BGACK_030_INT_D mcell H13 mx G24CLK_000_P_SYNC_4_ mcell B7 +mx G8 UDS_000 pin 32 mx G25 cpu_est_1_ mcell D9 +mx G9 SIZE_DMA_0_ mcell G13 mx G26 RN_RESET mcell B0 +mx G10 SIZE_DMA_1_ mcell G9 mx G27 LDS_000 pin 31 +mx G11CLK_000_P_SYNC_5_ mcell G14 mx G28inst_CLK_000_NE_D0 mcell D2 +mx G12CLK_000_P_SYNC_1_ mcell G7 mx G29 ... ... +mx G13 RN_A0 mcell G8 mx G30 ... ... +mx G14CLK_000_N_SYNC_8_ mcell A10 mx G31 ... ... +mx G15 cpu_est_0_ mcell F1 mx G32 ... ... +mx G16 inst_CLK_000_D0 mcell D6 +---------------------------------------------------------------------------- + + +BLOCK_H_LOGIC_ARRAY_FANIN +~~~~~~~~~~~~~~~~~~~~~~~~~ +CSM Signal Source CSM Signal Source +------------------------------------ ------------------------------------ +mx H0 RN_BGACK_030 mcell H4 mx H17 A_18_ pin 95 +mx H1 BERR pin 41 mx H18 BGACK_000 pin 28 +mx H2inst_CLK_OUT_PRE_D mcell E13 mx H19 AS_030 pin 82 +mx H3 inst_AS_000_DMA mcell A8 mx H20 CLK_030 pin 64 +mx H4 inst_AS_030_D0 mcell H5 mx H21 RST pin 86 +mx H5 inst_CLK_000_PE mcell F0 mx H22inst_nEXP_SPACE_D0reg mcell G5 +mx H6 A_19_ pin 97 mx H23CLK_000_N_SYNC_9_ mcell G6 +mx H7 ... ... mx H24 FC_0_ pin 57 +mx H8 FPU_SENSE pin 91 mx H25 RW pin 71 +mx H9 SIZE_DMA_0_ mcell G13 mx H26 RN_RESET mcell B0 +mx H10 SIZE_DMA_1_ mcell G9 mx H27 RN_DSACK1 mcell H9 +mx H11 A_16_ pin 96 mx H28 SM_AMIGA_0_ mcell B5 +mx H12 FC_1_ pin 58 mx H29 SM_AMIGA_i_7_ mcell F4 +mx H13 A_17_ pin 59 mx H30 RN_RW_000 mcell H0 +mx H14CLK_000_N_SYNC_10_ mcell H2 mx H31 SM_AMIGA_5_ mcell F12 +mx H15 ... ... mx H32 SM_AMIGA_1_ mcell F8 +mx H16 AS_000 pin 42 +---------------------------------------------------------------------------- + + CSM indicates the mux inputs from the Central Switch Matrix. + Source indicates where the signal comes from (pin or macrocell). + + + + +PostFit_Equations +~~~~~~~~~~~~~~~~~ + + + P-Terms Fan-in Fan-out Type Name (attributes) +--------- ------ ------- ---- ----------------- + 1 2 1 Pin SIZE_1_ + 1 2 1 Pin SIZE_1_.OE + 1 2 1 Pin AS_030- + 1 3 1 Pin AS_030.OE + 1 2 1 Pin AS_000- + 1 2 1 Pin AS_000.OE + 1 2 1 Pin DS_030- + 1 3 1 Pin DS_030.OE + 1 3 1 Pin UDS_000- + 1 2 1 Pin UDS_000.OE + 1 3 1 Pin LDS_000- + 1 2 1 Pin LDS_000.OE + 0 0 1 Pin BERR + 1 9 1 Pin BERR.OE + 0 0 1 Pin CLK_DIV_OUT + 0 0 1 Pin CLK_DIV_OUT.OE + 1 1 1 Pin CLK_EXP + 1 9 1 Pin FPU_CS- + 1 0 1 Pin AVEC + 0 0 1 Pin AMIGA_ADDR_ENABLE + 2 4 1 Pin AMIGA_BUS_DATA_DIR + 1 2 1 Pin AMIGA_BUS_ENABLE_LOW- + 2 3 1 Pin AMIGA_BUS_ENABLE_HIGH + 1 13 1 Pin CIIN + 1 1 1 Pin CIIN.OE + 1 2 1 Pin SIZE_0_ + 1 2 1 Pin SIZE_0_.OE + 10 8 1 Pin IPL_030_2_.D- + 1 1 1 Pin IPL_030_2_.C + 1 2 1 Pin RW_000.OE + 3 7 1 Pin RW_000.D- + 1 1 1 Pin RW_000.C + 1 3 1 Pin A0.OE + 3 5 1 Pin A0.D + 1 1 1 Pin A0.C + 2 6 1 Pin BG_000.D- + 1 1 1 Pin BG_000.C + 2 4 1 Pin BGACK_030.D- + 1 1 1 Pin BGACK_030.C + 10 8 1 Pin IPL_030_1_.D- + 1 1 1 Pin IPL_030_1_.C + 10 8 1 Pin IPL_030_0_.D- + 1 1 1 Pin IPL_030_0_.C + 1 1 1 Pin DSACK1.OE + 4 9 1 Pin DSACK1.D- + 1 1 1 Pin DSACK1.C + 5 5 1 Pin E.D + 1 1 1 Pin E.C + 3 9 1 Pin VMA.T + 1 1 1 Pin VMA.C + 2 11 1 Pin RESET.D + 1 1 1 Pin RESET.C + 1 2 1 Pin RW.OE + 2 5 1 Pin RW.D- + 1 1 1 Pin RW.C + 2 2 1 Node cpu_est_0_.D + 1 1 1 Node cpu_est_0_.C + 5 5 1 Node cpu_est_1_.D- + 1 1 1 Node cpu_est_1_.C + 2 5 1 Node inst_AS_000_INT.D- + 1 1 1 Node inst_AS_000_INT.C + 3 6 1 Node SM_AMIGA_5_.D + 1 1 1 Node SM_AMIGA_5_.C + 2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.D- + 1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.C + 1 2 1 Node inst_AS_030_D0.D- + 1 1 1 Node inst_AS_030_D0.C + 1 2 1 Node inst_nEXP_SPACE_D0reg.D- + 1 1 1 Node inst_nEXP_SPACE_D0reg.C + 1 2 1 Node inst_DS_030_D0.D- + 1 1 1 Node inst_DS_030_D0.C + 7 14 1 Node inst_AS_030_000_SYNC.D- + 1 1 1 Node inst_AS_030_000_SYNC.C + 1 2 1 Node inst_BGACK_030_INT_D.D- + 1 1 1 Node inst_BGACK_030_INT_D.C + 7 9 1 Node inst_AS_000_DMA.D + 1 1 1 Node inst_AS_000_DMA.C + 9 12 1 Node inst_DS_000_DMA.D + 1 1 1 Node inst_DS_000_DMA.C + 2 5 1 Node CYCLE_DMA_0_.D + 1 1 1 Node CYCLE_DMA_0_.C + 3 6 1 Node CYCLE_DMA_1_.D + 1 1 1 Node CYCLE_DMA_1_.C + 3 6 1 Node SIZE_DMA_0_.D- + 1 1 1 Node SIZE_DMA_0_.C + 3 6 1 Node SIZE_DMA_1_.D + 1 1 1 Node SIZE_DMA_1_.C + 1 2 1 Node inst_VPA_D.D- + 1 1 1 Node inst_VPA_D.C + 3 5 1 Node inst_UDS_000_INT.D- + 1 1 1 Node inst_UDS_000_INT.C + 4 7 1 Node inst_LDS_000_INT.D + 1 1 1 Node inst_LDS_000_INT.C + 1 1 1 Node inst_CLK_OUT_PRE_D.D + 1 1 1 Node inst_CLK_OUT_PRE_D.C + 1 2 1 Node inst_DTACK_D0.D- + 1 1 1 Node inst_DTACK_D0.C + 1 1 1 Node inst_CLK_OUT_PRE_50.D + 1 1 1 Node inst_CLK_OUT_PRE_50.C + 1 1 1 Node inst_CLK_000_D1.D + 1 1 1 Node inst_CLK_000_D1.C + 1 1 1 Node inst_CLK_000_D0.D + 1 1 1 Node inst_CLK_000_D0.C + 1 1 1 Node inst_CLK_000_PE.D + 1 1 1 Node inst_CLK_000_PE.C + 1 1 1 Node CLK_000_P_SYNC_9_.D + 1 1 1 Node CLK_000_P_SYNC_9_.C + 1 1 1 Node inst_CLK_000_NE.D + 1 1 1 Node inst_CLK_000_NE.C + 4 11 1 Node N_96_i- + 1 1 1 Node CLK_000_N_SYNC_11_.D + 1 1 1 Node CLK_000_N_SYNC_11_.C + 4 5 1 Node cpu_est_2_.D + 1 1 1 Node cpu_est_2_.C + 1 2 1 Node IPL_D0_0_.D- + 1 1 1 Node IPL_D0_0_.C + 1 2 1 Node IPL_D0_1_.D- + 1 1 1 Node IPL_D0_1_.C + 1 2 1 Node IPL_D0_2_.D- + 1 1 1 Node IPL_D0_2_.C + 5 13 1 Node SM_AMIGA_3_.T + 1 1 1 Node SM_AMIGA_3_.C + 1 1 1 Node inst_CLK_000_NE_D0.D + 1 1 1 Node inst_CLK_000_NE_D0.C + 2 6 1 Node SM_AMIGA_0_.D + 1 1 1 Node SM_AMIGA_0_.C + 2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- + 1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.C + 3 9 1 Node SM_AMIGA_6_.D + 1 1 1 Node SM_AMIGA_6_.C + 3 10 1 Node RST_DLY_0_.D + 1 1 1 Node RST_DLY_0_.C + 4 10 1 Node RST_DLY_1_.D + 1 1 1 Node RST_DLY_1_.C + 5 10 1 Node RST_DLY_2_.D + 1 1 1 Node RST_DLY_2_.C + 6 10 1 Node RST_DLY_3_.D + 1 1 1 Node RST_DLY_3_.C + 2 7 1 NodeX1 RST_DLY_4_.T.X1 + 1 10 1 NodeX2 RST_DLY_4_.T.X2 + 1 1 1 Node RST_DLY_4_.C + 4 10 1 Node RST_DLY_5_.T + 1 1 1 Node RST_DLY_5_.C + 3 10 1 Node RST_DLY_6_.T + 1 1 1 Node RST_DLY_6_.C + 2 10 1 Node RST_DLY_7_.D + 1 1 1 Node RST_DLY_7_.C + 1 2 1 Node CLK_000_P_SYNC_0_.D + 1 1 1 Node CLK_000_P_SYNC_0_.C + 1 1 1 Node CLK_000_P_SYNC_1_.D + 1 1 1 Node CLK_000_P_SYNC_1_.C + 1 1 1 Node CLK_000_P_SYNC_2_.D + 1 1 1 Node CLK_000_P_SYNC_2_.C + 1 1 1 Node CLK_000_P_SYNC_3_.D + 1 1 1 Node CLK_000_P_SYNC_3_.C + 1 1 1 Node CLK_000_P_SYNC_4_.D + 1 1 1 Node CLK_000_P_SYNC_4_.C + 1 1 1 Node CLK_000_P_SYNC_5_.D + 1 1 1 Node CLK_000_P_SYNC_5_.C + 1 1 1 Node CLK_000_P_SYNC_6_.D + 1 1 1 Node CLK_000_P_SYNC_6_.C + 1 1 1 Node CLK_000_P_SYNC_7_.D + 1 1 1 Node CLK_000_P_SYNC_7_.C + 1 1 1 Node CLK_000_P_SYNC_8_.D + 1 1 1 Node CLK_000_P_SYNC_8_.C + 1 2 1 Node CLK_000_N_SYNC_0_.D + 1 1 1 Node CLK_000_N_SYNC_0_.C + 1 1 1 Node CLK_000_N_SYNC_1_.D + 1 1 1 Node CLK_000_N_SYNC_1_.C + 1 1 1 Node CLK_000_N_SYNC_2_.D + 1 1 1 Node CLK_000_N_SYNC_2_.C + 1 1 1 Node CLK_000_N_SYNC_3_.D + 1 1 1 Node CLK_000_N_SYNC_3_.C + 1 1 1 Node CLK_000_N_SYNC_4_.D + 1 1 1 Node CLK_000_N_SYNC_4_.C + 1 1 1 Node CLK_000_N_SYNC_5_.D + 1 1 1 Node CLK_000_N_SYNC_5_.C + 1 1 1 Node CLK_000_N_SYNC_6_.D + 1 1 1 Node CLK_000_N_SYNC_6_.C + 1 1 1 Node CLK_000_N_SYNC_7_.D + 1 1 1 Node CLK_000_N_SYNC_7_.C + 1 1 1 Node CLK_000_N_SYNC_8_.D + 1 1 1 Node CLK_000_N_SYNC_8_.C + 1 1 1 Node CLK_000_N_SYNC_9_.D + 1 1 1 Node CLK_000_N_SYNC_9_.C + 1 1 1 Node CLK_000_N_SYNC_10_.D + 1 1 1 Node CLK_000_N_SYNC_10_.C + 8 10 1 Node inst_CLK_030_H.D + 1 1 1 Node inst_CLK_030_H.C + 3 6 1 Node SM_AMIGA_1_.D + 1 1 1 Node SM_AMIGA_1_.C + 3 6 1 Node SM_AMIGA_4_.D + 1 1 1 Node SM_AMIGA_4_.C + 4 13 1 Node SM_AMIGA_2_.D + 1 1 1 Node SM_AMIGA_2_.C + 3 7 1 Node inst_DS_000_ENABLE.D + 1 1 1 Node inst_DS_000_ENABLE.C + 14 20 1 Node SM_AMIGA_i_7_.D + 1 1 1 Node SM_AMIGA_i_7_.C + 2 14 1 Node CIIN_0 +========= + 348 P-Term Total: 348 + Total Pins: 61 + Total Nodes: 73 + Average P-Term/Output: 2 + + +Equations: + +SIZE_1_ = (!SIZE_DMA_0_.Q & SIZE_DMA_1_.Q); + +SIZE_1_.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q); + +!AS_030 = (!inst_AS_000_DMA.Q & !AS_000.PIN); + +AS_030.OE = (!BGACK_030.Q & RESET.Q & !inst_nEXP_SPACE_D0reg.Q); + +!AS_000 = (!inst_AS_000_INT.Q & !AS_030.PIN); + +AS_000.OE = (BGACK_030.Q & RESET.Q); + +!DS_030 = (!inst_DS_000_DMA.Q & !AS_000.PIN); + +DS_030.OE = (!BGACK_030.Q & RESET.Q & !inst_nEXP_SPACE_D0reg.Q); + +!UDS_000 = (!inst_UDS_000_INT.Q & inst_DS_000_ENABLE.Q & !DS_030.PIN); + +UDS_000.OE = (BGACK_030.Q & RESET.Q); + +!LDS_000 = (!inst_LDS_000_INT.Q & inst_DS_000_ENABLE.Q & !DS_030.PIN); + +LDS_000.OE = (BGACK_030.Q & RESET.Q); + +BERR = (0); + +BERR.OE = (FC_1_ & BGACK_000 & FPU_SENSE & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN); + +CLK_DIV_OUT = (0); + +CLK_DIV_OUT.OE = (0); + +CLK_EXP = (CLK_030); + +!FPU_CS = (FC_1_ & BGACK_000 & !FPU_SENSE & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN); + +AVEC = (1); + +AMIGA_ADDR_ENABLE = (0); + +AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW_000.PIN + # !BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q & !AS_000.PIN & RW_000.PIN); + +!AMIGA_BUS_ENABLE_LOW = (!BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_LOW.Q); + +AMIGA_BUS_ENABLE_HIGH = (!BGACK_030.Q & inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q + # BGACK_030.Q & !SM_AMIGA_i_7_.Q); + +CIIN = (!A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_ & A_23_ & A_22_ & A_21_ & A_20_ & !inst_AS_030_D0.Q); + +CIIN.OE = (CIIN_0); + +SIZE_0_ = (SIZE_DMA_0_.Q & !SIZE_DMA_1_.Q); + +SIZE_0_.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q); + +!IPL_030_2_.D = (!IPL_2_ & RST & !IPL_030_2_.Q + # RST & !IPL_D0_2_.Q & !IPL_030_2_.Q + # RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_2_.Q + # RST & IPL_0_ & !IPL_D0_0_.Q & !IPL_030_2_.Q + # RST & !IPL_1_ & IPL_D0_1_.Q & !IPL_030_2_.Q + # RST & IPL_1_ & !IPL_D0_1_.Q & !IPL_030_2_.Q + # !IPL_2_ & RST & IPL_1_ & IPL_0_ & IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q + # !IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q + # !IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q + # !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q); + +IPL_030_2_.C = (CLK_OSZI); + +RW_000.OE = (BGACK_030.Q & RESET.Q); + +!RW_000.D = (RST & SM_AMIGA_5_.Q & !RW.PIN + # RST & !SM_AMIGA_5_.Q & !inst_CLK_000_PE.Q & !RW_000.Q & SM_AMIGA_i_7_.Q + # RST & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q); + +RW_000.C = (CLK_OSZI); + +A0.OE = (!BGACK_030.Q & RESET.Q & !inst_nEXP_SPACE_D0reg.Q); + +A0.D = (!RST + # !BGACK_030.Q & UDS_000.PIN + # BGACK_030.Q & inst_BGACK_030_INT_D.Q & A0.Q); + +A0.C = (CLK_OSZI); + +!BG_000.D = (!BG_030 & RST & !BG_000.Q + # !BG_030 & RST & inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_CLK_000_D0.Q); + +BG_000.C = (CLK_OSZI); + +!BGACK_030.D = (!BGACK_000 & RST + # RST & !BGACK_030.Q & !inst_CLK_000_PE.Q); + +BGACK_030.C = (CLK_OSZI); + +!IPL_030_1_.D = (RST & !IPL_1_ & !IPL_030_1_.Q + # RST & !IPL_D0_1_.Q & !IPL_030_1_.Q + # RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_1_.Q + # RST & IPL_0_ & !IPL_D0_0_.Q & !IPL_030_1_.Q + # !IPL_2_ & RST & IPL_D0_2_.Q & !IPL_030_1_.Q + # IPL_2_ & RST & !IPL_D0_2_.Q & !IPL_030_1_.Q + # IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q + # IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q + # !IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q + # !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q); + +IPL_030_1_.C = (CLK_OSZI); + +!IPL_030_0_.D = (RST & !IPL_0_ & !IPL_030_0_.Q + # RST & !IPL_D0_0_.Q & !IPL_030_0_.Q + # RST & !IPL_1_ & IPL_D0_1_.Q & !IPL_030_0_.Q + # RST & IPL_1_ & !IPL_D0_1_.Q & !IPL_030_0_.Q + # !IPL_2_ & RST & IPL_D0_2_.Q & !IPL_030_0_.Q + # IPL_2_ & RST & !IPL_D0_2_.Q & !IPL_030_0_.Q + # IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & IPL_D0_2_.Q + # IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q + # !IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q + # !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q); + +IPL_030_0_.C = (CLK_OSZI); + +DSACK1.OE = (inst_nEXP_SPACE_D0reg.Q); + +!DSACK1.D = (RST & CLK_000_N_SYNC_10_.Q & SM_AMIGA_1_.Q + # !CLK_030 & RST & CLK_000_N_SYNC_9_.Q & SM_AMIGA_1_.Q + # RST & inst_CLK_OUT_PRE_D.Q & CLK_000_N_SYNC_9_.Q & SM_AMIGA_1_.Q + # RST & !inst_AS_030_D0.Q & !DSACK1.Q & BERR.PIN); + +DSACK1.C = (CLK_OSZI); + +E.D = (E.Q & !cpu_est_0_.Q + # E.Q & !cpu_est_1_.Q + # E.Q & !inst_CLK_000_NE_D0.Q + # cpu_est_0_.Q & cpu_est_1_.Q & !cpu_est_2_.Q & inst_CLK_000_NE_D0.Q + # !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & inst_CLK_000_NE_D0.Q); + +E.C = (CLK_OSZI); + +VMA.T = (!RST & !VMA.Q + # !E.Q & !VMA.Q & !cpu_est_0_.Q & cpu_est_1_.Q & inst_CLK_000_PE.Q & cpu_est_2_.Q + # RST & !E.Q & VMA.Q & cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_NE.Q & cpu_est_2_.Q); + +VMA.C = (CLK_OSZI); + +RESET.D = (RST & RESET.Q + # RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & RST_DLY_6_.Q & RST_DLY_7_.Q); + +RESET.C = (CLK_OSZI); + +RW.OE = (!BGACK_030.Q & RESET.Q); + +!RW.D = (RST & !BGACK_030.Q & !RW_000.PIN + # RST & BGACK_030.Q & inst_BGACK_030_INT_D.Q & !RW.Q); + +RW.C = (CLK_OSZI); + +cpu_est_0_.D = (!cpu_est_0_.Q & inst_CLK_000_NE_D0.Q + # cpu_est_0_.Q & !inst_CLK_000_NE_D0.Q); + +cpu_est_0_.C = (CLK_OSZI); + +!cpu_est_1_.D = (!cpu_est_1_.Q & !inst_CLK_000_NE_D0.Q + # E.Q & cpu_est_0_.Q & !cpu_est_1_.Q + # !E.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & cpu_est_2_.Q + # E.Q & cpu_est_0_.Q & !cpu_est_2_.Q & inst_CLK_000_NE_D0.Q + # !E.Q & cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q); + +cpu_est_1_.C = (CLK_OSZI); + +!inst_AS_000_INT.D = (RST & SM_AMIGA_5_.Q + # RST & !inst_AS_000_INT.Q & !inst_AS_030_D0.Q & BERR.PIN); + +inst_AS_000_INT.C = (CLK_OSZI); + +SM_AMIGA_5_.D = (RST & !SM_AMIGA_5_.Q & inst_CLK_000_PE.Q & SM_AMIGA_6_.Q + # RST & SM_AMIGA_5_.Q & !inst_CLK_000_NE.Q & BERR.PIN + # RST & SM_AMIGA_5_.Q & SM_AMIGA_6_.Q & BERR.PIN); + +SM_AMIGA_5_.C = (CLK_OSZI); + +!inst_AMIGA_BUS_ENABLE_DMA_LOW.D = (A1 & RST & !BGACK_030.Q + # RST & BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_LOW.Q & inst_BGACK_030_INT_D.Q); + +inst_AMIGA_BUS_ENABLE_DMA_LOW.C = (CLK_OSZI); + +!inst_AS_030_D0.D = (RST & !AS_030.PIN); + +inst_AS_030_D0.C = (CLK_OSZI); + +!inst_nEXP_SPACE_D0reg.D = (!nEXP_SPACE & RST); + +inst_nEXP_SPACE_D0reg.C = (CLK_OSZI); + +!inst_DS_030_D0.D = (RST & !DS_030.PIN); + +inst_DS_030_D0.C = (CLK_OSZI); + +!inst_AS_030_000_SYNC.D = (RST & !inst_AS_030_D0.Q & !inst_AS_030_000_SYNC.Q & BERR.PIN + # !FC_1_ & RST & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN + # RST & A_19_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN + # RST & A_18_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN + # RST & !A_17_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN + # RST & A_16_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN + # RST & !FC_0_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN); + +inst_AS_030_000_SYNC.C = (CLK_OSZI); + +!inst_BGACK_030_INT_D.D = (RST & !BGACK_030.Q); + +inst_BGACK_030_INT_D.C = (CLK_OSZI); + +inst_AS_000_DMA.D = (!RST + # BGACK_030.Q + # AS_000.PIN + # !CLK_030 & inst_AS_000_DMA.Q + # CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q + # !CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q + # UDS_000.PIN & LDS_000.PIN); + +inst_AS_000_DMA.C = (CLK_OSZI); + +inst_DS_000_DMA.D = (!RST + # BGACK_030.Q + # AS_000.PIN + # CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q + # !CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q + # UDS_000.PIN & LDS_000.PIN + # !CLK_030 & inst_DS_000_DMA.Q & !RW_000.PIN + # inst_DS_000_DMA.Q & !inst_CLK_030_H.Q & !RW_000.PIN + # CLK_030 & inst_AS_000_DMA.Q & inst_CLK_030_H.Q & !RW_000.PIN); + +inst_DS_000_DMA.C = (CLK_OSZI); + +CYCLE_DMA_0_.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & inst_CLK_000_PE.Q & !AS_000.PIN + # RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !inst_CLK_000_PE.Q & !AS_000.PIN); + +CYCLE_DMA_0_.C = (CLK_OSZI); + +CYCLE_DMA_1_.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_000.PIN + # RST & !BGACK_030.Q & CYCLE_DMA_1_.Q & !inst_CLK_000_PE.Q & !AS_000.PIN + # RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & inst_CLK_000_PE.Q & !AS_000.PIN); + +CYCLE_DMA_1_.C = (CLK_OSZI); + +!SIZE_DMA_0_.D = (RST & BGACK_030.Q & !inst_BGACK_030_INT_D.Q + # RST & BGACK_030.Q & !SIZE_DMA_0_.Q + # RST & !BGACK_030.Q & !UDS_000.PIN & !LDS_000.PIN); + +SIZE_DMA_0_.C = (CLK_OSZI); + +SIZE_DMA_1_.D = (!RST + # BGACK_030.Q & inst_BGACK_030_INT_D.Q & SIZE_DMA_1_.Q + # !BGACK_030.Q & !UDS_000.PIN & !LDS_000.PIN); + +SIZE_DMA_1_.C = (CLK_OSZI); + +!inst_VPA_D.D = (!VPA & RST); + +inst_VPA_D.C = (CLK_OSZI); + +!inst_UDS_000_INT.D = (RST & inst_DS_030_D0.Q & !inst_UDS_000_INT.Q + # RST & !inst_UDS_000_INT.Q & !SM_AMIGA_6_.Q + # RST & !inst_DS_030_D0.Q & SM_AMIGA_6_.Q & !A0.PIN); + +inst_UDS_000_INT.C = (CLK_OSZI); + +inst_LDS_000_INT.D = (!RST + # inst_DS_030_D0.Q & inst_LDS_000_INT.Q + # inst_LDS_000_INT.Q & !SM_AMIGA_6_.Q + # !inst_DS_030_D0.Q & SM_AMIGA_6_.Q & SIZE_0_.PIN & !SIZE_1_.PIN & !A0.PIN); + +inst_LDS_000_INT.C = (CLK_OSZI); + +inst_CLK_OUT_PRE_D.D = (inst_CLK_OUT_PRE_50.Q); + +inst_CLK_OUT_PRE_D.C = (CLK_OSZI); + +!inst_DTACK_D0.D = (!DTACK & RST); + +inst_DTACK_D0.C = (CLK_OSZI); + +inst_CLK_OUT_PRE_50.D = (!inst_CLK_OUT_PRE_50.Q); + +inst_CLK_OUT_PRE_50.C = (CLK_OSZI); + +inst_CLK_000_D1.D = (inst_CLK_000_D0.Q); + +inst_CLK_000_D1.C = (CLK_OSZI); + +inst_CLK_000_D0.D = (CLK_000); + +inst_CLK_000_D0.C = (CLK_OSZI); + +inst_CLK_000_PE.D = (CLK_000_P_SYNC_9_.Q); + +inst_CLK_000_PE.C = (CLK_OSZI); + +CLK_000_P_SYNC_9_.D = (CLK_000_P_SYNC_8_.Q); + +CLK_000_P_SYNC_9_.C = (CLK_OSZI); + +inst_CLK_000_NE.D = (CLK_000_N_SYNC_11_.Q); + +inst_CLK_000_NE.C = (CLK_OSZI); + +!N_96_i = (!SM_AMIGA_5_.Q & !inst_nEXP_SPACE_D0reg.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q + # !SM_AMIGA_5_.Q & inst_AS_030_000_SYNC.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q + # !SM_AMIGA_5_.Q & !inst_CLK_000_D1.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q + # !SM_AMIGA_5_.Q & inst_CLK_000_D0.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q); + +CLK_000_N_SYNC_11_.D = (CLK_000_N_SYNC_10_.Q); + +CLK_000_N_SYNC_11_.C = (CLK_OSZI); + +cpu_est_2_.D = (cpu_est_1_.Q & cpu_est_2_.Q + # cpu_est_2_.Q & !inst_CLK_000_NE_D0.Q + # E.Q & cpu_est_0_.Q & inst_CLK_000_NE_D0.Q + # !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_NE_D0.Q); + +cpu_est_2_.C = (CLK_OSZI); + +!IPL_D0_0_.D = (RST & !IPL_0_); + +IPL_D0_0_.C = (CLK_OSZI); + +!IPL_D0_1_.D = (RST & !IPL_1_); + +IPL_D0_1_.C = (CLK_OSZI); + +!IPL_D0_2_.D = (!IPL_2_ & RST); + +IPL_D0_2_.C = (CLK_OSZI); + +SM_AMIGA_3_.T = (!RST & SM_AMIGA_3_.Q + # SM_AMIGA_3_.Q & !BERR.PIN + # RST & inst_CLK_000_PE.Q & !SM_AMIGA_3_.Q & SM_AMIGA_4_.Q + # inst_VPA_D.Q & !inst_DTACK_D0.Q & SM_AMIGA_3_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_4_.Q + # E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & cpu_est_2_.Q & SM_AMIGA_3_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_4_.Q); + +SM_AMIGA_3_.C = (CLK_OSZI); + +inst_CLK_000_NE_D0.D = (inst_CLK_000_NE.Q); + +inst_CLK_000_NE_D0.C = (CLK_OSZI); + +SM_AMIGA_0_.D = (RST & inst_CLK_000_NE.Q & !SM_AMIGA_0_.Q & SM_AMIGA_1_.Q + # RST & !inst_CLK_000_PE.Q & SM_AMIGA_0_.Q & BERR.PIN); + +SM_AMIGA_0_.C = (CLK_OSZI); + +!inst_AMIGA_BUS_ENABLE_DMA_HIGH.D = (!A1 & RST & !BGACK_030.Q + # RST & BGACK_030.Q & inst_BGACK_030_INT_D.Q & !inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q); + +inst_AMIGA_BUS_ENABLE_DMA_HIGH.C = (CLK_OSZI); + +SM_AMIGA_6_.D = (RST & SM_AMIGA_6_.Q & !SM_AMIGA_i_7_.Q + # RST & !inst_CLK_000_PE.Q & SM_AMIGA_6_.Q & BERR.PIN + # RST & inst_nEXP_SPACE_D0reg.Q & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D1.Q & !inst_CLK_000_D0.Q & !SM_AMIGA_i_7_.Q); + +SM_AMIGA_6_.C = (CLK_OSZI); + +RST_DLY_0_.D = (RST & !inst_CLK_000_NE.Q & RST_DLY_0_.Q + # RST & inst_CLK_000_NE.Q & !RST_DLY_0_.Q + # RST & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & RST_DLY_6_.Q & RST_DLY_7_.Q); + +RST_DLY_0_.C = (CLK_OSZI); + +RST_DLY_1_.D = (RST & !inst_CLK_000_NE.Q & RST_DLY_1_.Q + # RST & !RST_DLY_0_.Q & RST_DLY_1_.Q + # RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & !RST_DLY_1_.Q + # RST & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & RST_DLY_6_.Q & RST_DLY_7_.Q); + +RST_DLY_1_.C = (CLK_OSZI); + +RST_DLY_2_.D = (RST & !inst_CLK_000_NE.Q & RST_DLY_2_.Q + # RST & !RST_DLY_0_.Q & RST_DLY_2_.Q + # RST & !RST_DLY_1_.Q & RST_DLY_2_.Q + # RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & !RST_DLY_2_.Q + # RST & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & RST_DLY_6_.Q & RST_DLY_7_.Q); + +RST_DLY_2_.C = (CLK_OSZI); + +RST_DLY_3_.D = (RST & !inst_CLK_000_NE.Q & RST_DLY_3_.Q + # RST & !RST_DLY_0_.Q & RST_DLY_3_.Q + # RST & !RST_DLY_1_.Q & RST_DLY_3_.Q + # RST & !RST_DLY_2_.Q & RST_DLY_3_.Q + # RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & !RST_DLY_3_.Q + # RST & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & RST_DLY_6_.Q & RST_DLY_7_.Q); + +RST_DLY_3_.C = (CLK_OSZI); + +RST_DLY_4_.T.X1 = (!RST & RST_DLY_4_.Q + # RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q); + +RST_DLY_4_.T.X2 = (RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & RST_DLY_6_.Q & RST_DLY_7_.Q); + +RST_DLY_4_.C = (CLK_OSZI); + +RST_DLY_5_.T = (!RST & RST_DLY_5_.Q + # RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & !RST_DLY_5_.Q + # inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & !RST_DLY_6_.Q + # inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & !RST_DLY_7_.Q); + +RST_DLY_5_.C = (CLK_OSZI); + +RST_DLY_6_.T = (!RST & RST_DLY_6_.Q + # RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & !RST_DLY_6_.Q + # inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & RST_DLY_6_.Q & !RST_DLY_7_.Q); + +RST_DLY_6_.C = (CLK_OSZI); + +RST_DLY_7_.D = (RST & RST_DLY_7_.Q + # RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & RST_DLY_6_.Q); + +RST_DLY_7_.C = (CLK_OSZI); + +CLK_000_P_SYNC_0_.D = (!inst_CLK_000_D1.Q & inst_CLK_000_D0.Q); + +CLK_000_P_SYNC_0_.C = (CLK_OSZI); + +CLK_000_P_SYNC_1_.D = (CLK_000_P_SYNC_0_.Q); + +CLK_000_P_SYNC_1_.C = (CLK_OSZI); + +CLK_000_P_SYNC_2_.D = (CLK_000_P_SYNC_1_.Q); + +CLK_000_P_SYNC_2_.C = (CLK_OSZI); + +CLK_000_P_SYNC_3_.D = (CLK_000_P_SYNC_2_.Q); + +CLK_000_P_SYNC_3_.C = (CLK_OSZI); + +CLK_000_P_SYNC_4_.D = (CLK_000_P_SYNC_3_.Q); + +CLK_000_P_SYNC_4_.C = (CLK_OSZI); + +CLK_000_P_SYNC_5_.D = (CLK_000_P_SYNC_4_.Q); + +CLK_000_P_SYNC_5_.C = (CLK_OSZI); + +CLK_000_P_SYNC_6_.D = (CLK_000_P_SYNC_5_.Q); + +CLK_000_P_SYNC_6_.C = (CLK_OSZI); + +CLK_000_P_SYNC_7_.D = (CLK_000_P_SYNC_6_.Q); + +CLK_000_P_SYNC_7_.C = (CLK_OSZI); + +CLK_000_P_SYNC_8_.D = (CLK_000_P_SYNC_7_.Q); + +CLK_000_P_SYNC_8_.C = (CLK_OSZI); + +CLK_000_N_SYNC_0_.D = (inst_CLK_000_D1.Q & !inst_CLK_000_D0.Q); + +CLK_000_N_SYNC_0_.C = (CLK_OSZI); + +CLK_000_N_SYNC_1_.D = (CLK_000_N_SYNC_0_.Q); + +CLK_000_N_SYNC_1_.C = (CLK_OSZI); + +CLK_000_N_SYNC_2_.D = (CLK_000_N_SYNC_1_.Q); + +CLK_000_N_SYNC_2_.C = (CLK_OSZI); + +CLK_000_N_SYNC_3_.D = (CLK_000_N_SYNC_2_.Q); + +CLK_000_N_SYNC_3_.C = (CLK_OSZI); + +CLK_000_N_SYNC_4_.D = (CLK_000_N_SYNC_3_.Q); + +CLK_000_N_SYNC_4_.C = (CLK_OSZI); + +CLK_000_N_SYNC_5_.D = (CLK_000_N_SYNC_4_.Q); + +CLK_000_N_SYNC_5_.C = (CLK_OSZI); + +CLK_000_N_SYNC_6_.D = (CLK_000_N_SYNC_5_.Q); + +CLK_000_N_SYNC_6_.C = (CLK_OSZI); + +CLK_000_N_SYNC_7_.D = (CLK_000_N_SYNC_6_.Q); + +CLK_000_N_SYNC_7_.C = (CLK_OSZI); + +CLK_000_N_SYNC_8_.D = (CLK_000_N_SYNC_7_.Q); + +CLK_000_N_SYNC_8_.C = (CLK_OSZI); + +CLK_000_N_SYNC_9_.D = (CLK_000_N_SYNC_8_.Q); + +CLK_000_N_SYNC_9_.C = (CLK_OSZI); + +CLK_000_N_SYNC_10_.D = (CLK_000_N_SYNC_9_.Q); + +CLK_000_N_SYNC_10_.C = (CLK_OSZI); + +inst_CLK_030_H.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !UDS_000.PIN + # RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !UDS_000.PIN + # RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !LDS_000.PIN + # RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !LDS_000.PIN + # !CLK_030 & RST & !BGACK_030.Q & !inst_AS_000_DMA.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_000.PIN & !UDS_000.PIN + # !CLK_030 & RST & !BGACK_030.Q & !inst_AS_000_DMA.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & !AS_000.PIN & !UDS_000.PIN + # !CLK_030 & RST & !BGACK_030.Q & !inst_AS_000_DMA.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_000.PIN & !LDS_000.PIN + # !CLK_030 & RST & !BGACK_030.Q & !inst_AS_000_DMA.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & !AS_000.PIN & !LDS_000.PIN); + +inst_CLK_030_H.C = (CLK_OSZI); + +SM_AMIGA_1_.D = (RST & inst_CLK_000_PE.Q & !SM_AMIGA_1_.Q & SM_AMIGA_2_.Q + # RST & !inst_CLK_000_NE.Q & SM_AMIGA_1_.Q & BERR.PIN + # RST & SM_AMIGA_1_.Q & SM_AMIGA_2_.Q & BERR.PIN); + +SM_AMIGA_1_.C = (CLK_OSZI); + +SM_AMIGA_4_.D = (RST & SM_AMIGA_5_.Q & inst_CLK_000_NE.Q + # RST & SM_AMIGA_5_.Q & SM_AMIGA_4_.Q + # RST & !inst_CLK_000_PE.Q & SM_AMIGA_4_.Q & BERR.PIN); + +SM_AMIGA_4_.C = (CLK_OSZI); + +SM_AMIGA_2_.D = (RST & SM_AMIGA_3_.Q & SM_AMIGA_2_.Q + # RST & !inst_CLK_000_PE.Q & SM_AMIGA_2_.Q & BERR.PIN + # RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & SM_AMIGA_3_.Q & inst_CLK_000_NE_D0.Q + # RST & E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & cpu_est_2_.Q & SM_AMIGA_3_.Q & inst_CLK_000_NE_D0.Q); + +SM_AMIGA_2_.C = (CLK_OSZI); + +inst_DS_000_ENABLE.D = (RST & !SM_AMIGA_5_.Q & SM_AMIGA_3_.Q + # RST & SM_AMIGA_5_.Q & RW.PIN + # RST & !inst_AS_030_D0.Q & inst_DS_000_ENABLE.Q & BERR.PIN); + +inst_DS_000_ENABLE.C = (CLK_OSZI); + +SM_AMIGA_i_7_.D = (RST & !inst_CLK_000_PE.Q & N_96_i & BERR.PIN + # RST & N_96_i & !SM_AMIGA_0_.Q & BERR.PIN + # RST & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & N_96_i & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q + # RST & !SM_AMIGA_5_.Q & inst_CLK_000_PE.Q & N_96_i & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q + # RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & N_96_i & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q + # RST & inst_CLK_000_NE.Q & N_96_i & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q + # RST & !SM_AMIGA_5_.Q & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_PE.Q & N_96_i & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q + # RST & !SM_AMIGA_5_.Q & N_96_i & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q + # RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE.Q & N_96_i & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q + # RST & !SM_AMIGA_5_.Q & inst_VPA_D.Q & !inst_DTACK_D0.Q & N_96_i & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q + # RST & E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & N_96_i & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q + # RST & E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !SM_AMIGA_5_.Q & !inst_VPA_D.Q & inst_CLK_000_PE.Q & N_96_i & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q + # RST & E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_NE.Q & N_96_i & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q + # RST & E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !SM_AMIGA_5_.Q & !inst_VPA_D.Q & N_96_i & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q); + +SM_AMIGA_i_7_.C = (CLK_OSZI); + +CIIN_0 = (inst_nEXP_SPACE_D0reg.Q + # !A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_ & A_23_ & A_22_ & A_21_ & A_20_ & !inst_AS_030_D0.Q); + + +Reverse-Polarity Equations: + diff --git a/Logic/68030_tk.svl b/Logic/68030_tk.svl new file mode 100644 index 0000000..579ba2b --- /dev/null +++ b/Logic/68030_tk.svl @@ -0,0 +1,2 @@ +Part Number: M4A5-128/64-10VC +Need not generate svf file according to the constraints, exit diff --git a/Logic/68030_tk.tal b/Logic/68030_tk.tal new file mode 100644 index 0000000..c5e0400 --- /dev/null +++ b/Logic/68030_tk.tal @@ -0,0 +1,139 @@ + + +Design Name = 68030_tk.tt4 +~~~~~~~~~~~~~~~~~~~~~~~~~~ + + +******************* +* TIMING ANALYSIS * +******************* + +Timing Analysis KEY: +One unit of delay time is equivalent to one pass + through the Central Switch Matrix. +.. Delay ( in this column ) not applicable to the indicated signal. +TSU, Set-Up Time ( 0 for input-paired signals ), + represents the number of switch matrix passes between + an input pin and a register setup before clock. + TSU is reported on the register. +TCO, Clocked Output-to-Pin Time ( 0 for output-paired signals ), + represents the number of switch matrix passes between + a clocked register and an output pin. + TCO is reported on the register. +TPD, Propagation Delay Time ( calculated only for combinatorial eqns.), + represents the number of switch matrix passes between + an input pin and an output pin. + TPD is reported on the output pin. +TCR, Clocked Output-to-Register Time, + represents the number of switch matrix passes between + a clocked register and the register it drives ( before clock ). + TCR is reported on the driving register. + + TSU TCO TPD TCR + #passes #passes #passes #passes +SIGNAL NAME min max min max min max min max + inst_AS_000_DMA 1 4 1 4 .. .. 1 5 + A0 1 4 0 0 .. .. 1 1 + RN_A0 1 4 0 0 .. .. 1 1 + inst_AS_000_INT 1 1 1 3 .. .. 2 4 + inst_DS_000_DMA 1 4 1 2 .. .. 2 3 + SIZE_DMA_0_ 1 4 1 1 .. .. 2 2 + SIZE_DMA_1_ 1 4 1 1 .. .. 2 2 + inst_CLK_030_H 1 4 .. .. .. .. 1 1 + UDS_000 .. .. .. .. 1 3 .. .. + LDS_000 .. .. .. .. 1 3 .. .. + inst_DS_030_D0 1 3 .. .. .. .. 1 1 + DS_030 .. .. .. .. 1 2 .. .. + FPU_CS .. .. .. .. 1 2 .. .. +AMIGA_BUS_DATA_DIR .. .. .. .. 1 2 .. .. + SM_AMIGA_5_ 1 1 .. .. .. .. 1 2 + inst_AS_030_D0 1 2 1 1 .. .. 1 1 +inst_nEXP_SPACE_D0reg 1 1 1 1 .. .. 1 2 +inst_AS_030_000_SYNC 1 1 .. .. .. .. 1 2 + CYCLE_DMA_0_ 1 2 .. .. .. .. 1 1 + CYCLE_DMA_1_ 1 2 .. .. .. .. 1 1 +inst_UDS_000_INT 1 1 1 1 .. .. 2 2 +inst_LDS_000_INT 1 1 1 1 .. .. 2 2 + inst_CLK_000_D1 .. .. .. .. .. .. 1 2 + inst_CLK_000_D0 1 1 .. .. .. .. 1 2 + SM_AMIGA_3_ 1 1 .. .. .. .. 1 2 + SM_AMIGA_0_ 1 1 .. .. .. .. 1 2 + SM_AMIGA_6_ 1 1 .. .. .. .. 1 2 + SM_AMIGA_1_ 1 1 .. .. .. .. 1 2 + SM_AMIGA_4_ 1 1 .. .. .. .. 1 2 + SM_AMIGA_2_ 1 1 .. .. .. .. 1 2 +inst_DS_000_ENABLE 1 1 1 1 .. .. 2 2 + AS_030 .. .. .. .. 1 1 .. .. + AS_000 .. .. .. .. 1 1 .. .. + CLK_EXP .. .. .. .. 1 1 .. .. + CIIN .. .. .. .. 1 1 .. .. + IPL_030_2_ 1 1 0 0 .. .. 1 1 + RN_IPL_030_2_ 1 1 0 0 .. .. 1 1 + RW_000 1 1 0 0 .. .. 1 1 + RN_RW_000 1 1 0 0 .. .. 1 1 + BG_000 1 1 0 0 .. .. 1 1 + RN_BG_000 1 1 0 0 .. .. 1 1 + BGACK_030 1 1 0 1 .. .. 1 1 + RN_BGACK_030 1 1 0 1 .. .. 1 1 + IPL_030_1_ 1 1 0 0 .. .. 1 1 + RN_IPL_030_1_ 1 1 0 0 .. .. 1 1 + IPL_030_0_ 1 1 0 0 .. .. 1 1 + RN_IPL_030_0_ 1 1 0 0 .. .. 1 1 + DSACK1 1 1 0 0 .. .. 1 1 + RN_DSACK1 1 1 0 0 .. .. 1 1 + E .. .. 0 0 .. .. 1 1 + RN_E .. .. 0 0 .. .. 1 1 + VMA 1 1 0 0 .. .. 1 1 + RN_VMA 1 1 0 0 .. .. 1 1 + RESET 1 1 0 0 .. .. 1 1 + RN_RESET 1 1 0 0 .. .. 1 1 + RW 1 1 0 0 .. .. 1 1 + RN_RW 1 1 0 0 .. .. 1 1 + cpu_est_0_ .. .. .. .. .. .. 1 1 + cpu_est_1_ .. .. .. .. .. .. 1 1 +inst_AMIGA_BUS_ENABLE_DMA_LOW 1 1 1 1 .. .. .. .. +inst_BGACK_030_INT_D 1 1 .. .. .. .. 1 1 + inst_VPA_D 1 1 .. .. .. .. 1 1 +inst_CLK_OUT_PRE_D .. .. .. .. .. .. 1 1 + inst_DTACK_D0 1 1 .. .. .. .. 1 1 +inst_CLK_OUT_PRE_50 .. .. .. .. .. .. 1 1 + inst_CLK_000_PE .. .. .. .. .. .. 1 1 +CLK_000_P_SYNC_9_ .. .. .. .. .. .. 1 1 + inst_CLK_000_NE .. .. .. .. .. .. 1 1 +CLK_000_N_SYNC_11_ .. .. .. .. .. .. 1 1 + cpu_est_2_ .. .. .. .. .. .. 1 1 + IPL_D0_0_ 1 1 .. .. .. .. 1 1 + IPL_D0_1_ 1 1 .. .. .. .. 1 1 + IPL_D0_2_ 1 1 .. .. .. .. 1 1 +inst_CLK_000_NE_D0 .. .. .. .. .. .. 1 1 +inst_AMIGA_BUS_ENABLE_DMA_HIGH 1 1 1 1 .. .. .. .. + RST_DLY_0_ 1 1 .. .. .. .. 1 1 + RST_DLY_1_ 1 1 .. .. .. .. 1 1 + RST_DLY_2_ 1 1 .. .. .. .. 1 1 + RST_DLY_3_ 1 1 .. .. .. .. 1 1 + RST_DLY_4_ 1 1 .. .. .. .. 1 1 + RST_DLY_5_ 1 1 .. .. .. .. 1 1 + RST_DLY_6_ 1 1 .. .. .. .. 1 1 + RST_DLY_7_ 1 1 .. .. .. .. 1 1 +CLK_000_P_SYNC_0_ .. .. .. .. .. .. 1 1 +CLK_000_P_SYNC_1_ .. .. .. .. .. .. 1 1 +CLK_000_P_SYNC_2_ .. .. .. .. .. .. 1 1 +CLK_000_P_SYNC_3_ .. .. .. .. .. .. 1 1 +CLK_000_P_SYNC_4_ .. .. .. .. .. .. 1 1 +CLK_000_P_SYNC_5_ .. .. .. .. .. .. 1 1 +CLK_000_P_SYNC_6_ .. .. .. .. .. .. 1 1 +CLK_000_P_SYNC_7_ .. .. .. .. .. .. 1 1 +CLK_000_P_SYNC_8_ .. .. .. .. .. .. 1 1 +CLK_000_N_SYNC_0_ .. .. .. .. .. .. 1 1 +CLK_000_N_SYNC_1_ .. .. .. .. .. .. 1 1 +CLK_000_N_SYNC_2_ .. .. .. .. .. .. 1 1 +CLK_000_N_SYNC_3_ .. .. .. .. .. .. 1 1 +CLK_000_N_SYNC_4_ .. .. .. .. .. .. 1 1 +CLK_000_N_SYNC_5_ .. .. .. .. .. .. 1 1 +CLK_000_N_SYNC_6_ .. .. .. .. .. .. 1 1 +CLK_000_N_SYNC_7_ .. .. .. .. .. .. 1 1 +CLK_000_N_SYNC_8_ .. .. .. .. .. .. 1 1 +CLK_000_N_SYNC_9_ .. .. .. .. .. .. 1 1 +CLK_000_N_SYNC_10_ .. .. .. .. .. .. 1 1 + SM_AMIGA_i_7_ 1 1 1 1 .. .. 1 1 + CIIN_0 .. .. .. .. 1 1 .. .. \ No newline at end of file diff --git a/Logic/68030_tk.tt2 b/Logic/68030_tk.tt2 new file mode 100644 index 0000000..c0cfd00 --- /dev/null +++ b/Logic/68030_tk.tt2 @@ -0,0 +1,633 @@ +#$ TOOL ispLEVER Classic 1.8.00.04.29.14 +#$ DATE Wed May 13 22:59:21 2015 +#$ MODULE 68030_tk +#$ PINS 61 A_28_ A_27_ SIZE_1_ A_26_ A_25_ A_31_ A_24_ A_23_ A_22_ A_21_ IPL_2_ A_20_ A_19_ FC_1_ A_18_ AS_030 A_17_ AS_000 A_16_ DS_030 UDS_000 LDS_000 A1 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP IPL_1_ FPU_CS IPL_0_ FPU_SENSE FC_0_ DTACK AVEC VPA RST AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ A_30_ A_29_ IPL_030_2_ RW_000 A0 BG_000 BGACK_030 IPL_030_1_ IPL_030_0_ DSACK1 E VMA RESET RW +#$ NODES 72 cpu_est_0_ cpu_est_1_ inst_AS_000_INT SM_AMIGA_5_ inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_nEXP_SPACE_D0reg inst_DS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0 inst_CLK_OUT_PRE_50 inst_CLK_000_D1 inst_CLK_000_D0 inst_CLK_000_PE CLK_000_P_SYNC_9_ inst_CLK_000_NE N_96_i CLK_000_N_SYNC_11_ cpu_est_2_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ SM_AMIGA_3_ inst_CLK_000_NE_D0 SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_6_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ RST_DLY_3_ RST_DLY_4_ RST_DLY_5_ RST_DLY_6_ RST_DLY_7_ CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_4_ SM_AMIGA_2_ inst_DS_000_ENABLE SM_AMIGA_i_7_ +.type fr +.i 127 +.o 198 +.ilb A_31_ IPL_2_ FC_1_ A1 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q E.Q VMA.Q RESET.Q cpu_est_0_.Q cpu_est_1_.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_nEXP_SPACE_D0reg.Q inst_DS_030_D0.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q inst_DTACK_D0.Q inst_CLK_OUT_PRE_50.Q inst_CLK_000_D1.Q inst_CLK_000_D0.Q inst_CLK_000_PE.Q CLK_000_P_SYNC_9_.Q inst_CLK_000_NE.Q N_96_i CLK_000_N_SYNC_11_.Q cpu_est_2_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q SM_AMIGA_3_.Q inst_CLK_000_NE_D0.Q SM_AMIGA_0_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q SM_AMIGA_6_.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q RST_DLY_3_.Q RST_DLY_4_.Q RST_DLY_5_.Q RST_DLY_6_.Q RST_DLY_7_.Q CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q CLK_000_N_SYNC_0_.Q CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q CLK_000_N_SYNC_5_.Q CLK_000_N_SYNC_6_.Q CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q RW_000.Q RW.Q A0.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_4_.Q SM_AMIGA_2_.Q inst_DS_000_ENABLE.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN DS_030.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN BERR.PIN RW.PIN +.ob CLK_DIV_OUT CLK_EXP FPU_CS AVEC AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_2_.C IPL_D0_0_.C IPL_D0_1_.C IPL_D0_2_.C SM_AMIGA_i_7_.C SM_AMIGA_6_.C SM_AMIGA_5_.C SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.C SM_AMIGA_1_.C SM_AMIGA_0_.C cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C E.C IPL_030_0_.C IPL_030_1_.C CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.C RST_DLY_0_.C RST_DLY_1_.C RST_DLY_2_.C RST_DLY_3_.C RST_DLY_4_.C RST_DLY_5_.C RST_DLY_6_.C RST_DLY_7_.C CYCLE_DMA_0_.C CYCLE_DMA_1_.C SIZE_DMA_0_.C SIZE_DMA_1_.C CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.C CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.C inst_CLK_030_H.C RESET.C inst_DS_000_ENABLE.C inst_UDS_000_INT.C RW.C RW_000.C inst_LDS_000_INT.C inst_AS_030_000_SYNC.C inst_AS_000_INT.C DSACK1.C A0.C inst_AS_000_DMA.C inst_DS_000_DMA.C inst_DS_030_D0.C inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.C inst_VPA_D.C inst_DTACK_D0.C BGACK_030.C BG_000.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.C VMA.C inst_BGACK_030_INT_D.C inst_CLK_000_PE.C inst_CLK_000_NE.C inst_CLK_OUT_PRE_50.C inst_CLK_000_D1.C inst_CLK_000_NE_D0.C inst_CLK_OUT_PRE_D.C inst_CLK_000_D0.C SIZE_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 BERR SIZE_0_ N_96_i AS_030.OE AS_000.OE RW_000.OE DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE BERR.OE RW.OE CLK_DIV_OUT.OE DSACK1.OE CIIN.OE BGACK_030.D E.D VMA.T RESET.D cpu_est_0_.D cpu_est_1_.D inst_AS_000_INT.D SM_AMIGA_5_.D inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AS_030_D0.D inst_nEXP_SPACE_D0reg.D inst_DS_030_D0.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D inst_AS_000_DMA.D inst_DS_000_DMA.D CYCLE_DMA_0_.D CYCLE_DMA_1_.D SIZE_DMA_0_.D SIZE_DMA_1_.D inst_VPA_D.D inst_UDS_000_INT.D inst_LDS_000_INT.D inst_CLK_OUT_PRE_D.D inst_DTACK_D0.D inst_CLK_OUT_PRE_50.D inst_CLK_000_D1.D inst_CLK_000_D0.D inst_CLK_000_PE.D CLK_000_P_SYNC_9_.D inst_CLK_000_NE.D CLK_000_N_SYNC_11_.D cpu_est_2_.D IPL_D0_0_.D IPL_D0_1_.D IPL_D0_2_.D SM_AMIGA_3_.T inst_CLK_000_NE_D0.D SM_AMIGA_0_.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.D DSACK1.D SM_AMIGA_6_.D RST_DLY_0_.D RST_DLY_1_.D RST_DLY_2_.D RST_DLY_3_.D RST_DLY_4_.T RST_DLY_5_.T RST_DLY_6_.T RST_DLY_7_.D CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_8_.D CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_10_.D RW_000.D RW.D A0.D inst_CLK_030_H.D SM_AMIGA_1_.D SM_AMIGA_4_.D SM_AMIGA_2_.D inst_DS_000_ENABLE.D SM_AMIGA_i_7_.D BG_000.D IPL_030_0_.D IPL_030_1_.D IPL_030_2_.D +.p 621 +------------------------------------------------------------------------------------------------------------------------------- ~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-1----------------------------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--0---------------------------------------------------------------------------------------------------------------------------- ~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1-------------------------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----1------------------------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ +------0------------------------------------------------------------------------------------------------------------------------ ~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------1----------------------------------------------------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------1---------------------------------------------------------------------------------------------------------------------- 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------1------------------------------------------------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------0----------------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~1~11111111~~11111~1~~~~~~~~111~~~11~~~~~~~~~~~~~~~~~~~~~~~~~~~~~111~~~~~~1111 +-------------------------1----------------------------------------------------------------------------------------------------- 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~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------1---------------------------------------------------------------------------------------------- ~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~111~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------1-------------------------1---------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1----------------------------0---------------------------------------------------------------------------------------------- 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------1--1------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~11~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------0--1------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------1--0------------------------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------01----------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------1---0----------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1---------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------1--------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------10--------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------1-------------------------------------------------------------------------------------- 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +0-------------00000001111----------------0------------------------------------------------------------------------------------- ~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------1------------------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------0---------0------------------------------------------------------------------------------------ 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------0-1---------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------1------------0--------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +--------------------------------------------10--------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------1-------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------0--------------------------------------1-------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------1------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------11----------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------00----------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------1------------1----1---------------------------------------------------------------------------- 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------1------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------1---------1------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------------1------------------------------------------------------------------------ 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11 +-1---------------------------01-----------------------------------101---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1 +-1---------------------------00-----------------------------------001---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +-0---------------------------11-----------------------------------110---------------------------------------------------------- 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------------------1------------11111-0--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------------------1------------1111110--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1------------------------------------------------1------------1111110--------------------------------------------- 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ +-------------------------------------------------------------------------------------------------0----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ +--------------------------------------------------------------------------------------------------0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ +---------------------------------------------------------------------------------------------------0--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ +----------------------------------------------------------------------------------------------------0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ +-----------------------------------------------------------------------------------------------------0------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +------------------------------------------------------------------------------------------------------0------------------------ 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~ +----------------------------------------------1-----------------------------------------------------------0-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~ +-------0-----1---------------------------------------------------------------------------------------1-----1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1-----------------------------------------1---------------------------------------------1-----1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1----------------------------------------------------------------------------------------1----1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------------------0----------------------------------------------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~ +-----------------------------------------------------------------------0-----------------------------------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------0--------------------------------------------------------------------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ +--------------------------------------------------------------0---------------------------------------------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ +---------------------------------------------------------------------0--------------------------------------0------------------ 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~ +----------------------------------------------------0------------0-------------------------------------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +---------------------------------------------------------------------0---------------------------------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +----------------------------------------------------------------------0--------------------------------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +-----------------------------------------------------------------------------------------------------------0-0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~ +---------------------------------------0--0--------------------------0-0--0--------------------------------000----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------0----1------------------------0-0--0--------------------------------000----------------- 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------0-------------------------------------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ +---------------------------------------1----------------------0--------------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +---------------------------------0------------------0----------------1-------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +----------------------------------1-----------------0----------------1-------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +------------------------------------1---------------0----------------1-------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +-------------------------------------1--------------0----------------1-------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +----------------------------------------------------1---1------------1-------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +----------------------------------------------------0------------0---1-------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +---------------------------------------------------------------------0-------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +---------------------------------------0-----------------------------0-------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +---------------------------------------------------------------------10------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +-----------------------------------------------------------------------1-----------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +------------------------------------------------------------0-------------1--------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +-----------------------------------------------------------------------------------------------------------1-----------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~ +--------------------------------------------------------------0--------------------------------------------1-----------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +------------------------------------------------------------0-----------------------------------------------1----------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +------------------------------------------------------------0------------------------------------------------1---------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +---------------------------------------------------------------------------------------------------------------1-------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1-------------------------1--------------------------------------------------------------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ +---------------------------------------1-1------------------------------------------------------------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +---------------------------------------1----------------------------------------------------------------------0---------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +---------------------------------------1-------------------------------------------------------------------------------------00 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +.end diff --git a/Logic/68030_tk.tt3 b/Logic/68030_tk.tt3 new file mode 100644 index 0000000..665f2bf --- /dev/null +++ b/Logic/68030_tk.tt3 @@ -0,0 +1,633 @@ +#$ TOOL ispLEVER Classic 1.8.00.04.29.14 +#$ DATE Wed May 13 22:59:21 2015 +#$ MODULE 68030_tk +#$ PINS 61 A_28_ A_27_ SIZE_1_ A_26_ A_25_ A_31_ A_24_ A_23_ A_22_ A_21_ IPL_2_ A_20_ A_19_ FC_1_ A_18_ AS_030 A_17_ AS_000 A_16_ DS_030 UDS_000 LDS_000 A1 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP IPL_1_ FPU_CS IPL_0_ FPU_SENSE FC_0_ DTACK AVEC VPA RST AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ A_30_ A_29_ IPL_030_2_ RW_000 A0 BG_000 BGACK_030 IPL_030_1_ IPL_030_0_ DSACK1 E VMA RESET RW +#$ NODES 72 cpu_est_0_ cpu_est_1_ inst_AS_000_INT SM_AMIGA_5_ inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_nEXP_SPACE_D0reg inst_DS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0 inst_CLK_OUT_PRE_50 inst_CLK_000_D1 inst_CLK_000_D0 inst_CLK_000_PE CLK_000_P_SYNC_9_ inst_CLK_000_NE N_96_i CLK_000_N_SYNC_11_ cpu_est_2_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ SM_AMIGA_3_ inst_CLK_000_NE_D0 SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_6_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ RST_DLY_3_ RST_DLY_4_ RST_DLY_5_ RST_DLY_6_ RST_DLY_7_ CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_4_ SM_AMIGA_2_ inst_DS_000_ENABLE SM_AMIGA_i_7_ +.type fr +.i 127 +.o 198 +.ilb A_31_ IPL_2_ FC_1_ A1 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q E.Q VMA.Q RESET.Q cpu_est_0_.Q cpu_est_1_.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_nEXP_SPACE_D0reg.Q inst_DS_030_D0.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q inst_DTACK_D0.Q inst_CLK_OUT_PRE_50.Q inst_CLK_000_D1.Q inst_CLK_000_D0.Q inst_CLK_000_PE.Q CLK_000_P_SYNC_9_.Q inst_CLK_000_NE.Q N_96_i CLK_000_N_SYNC_11_.Q cpu_est_2_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q SM_AMIGA_3_.Q inst_CLK_000_NE_D0.Q SM_AMIGA_0_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q SM_AMIGA_6_.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q RST_DLY_3_.Q RST_DLY_4_.Q RST_DLY_5_.Q RST_DLY_6_.Q RST_DLY_7_.Q CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q CLK_000_N_SYNC_0_.Q CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q CLK_000_N_SYNC_5_.Q CLK_000_N_SYNC_6_.Q CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q RW_000.Q RW.Q A0.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_4_.Q SM_AMIGA_2_.Q inst_DS_000_ENABLE.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN DS_030.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN BERR.PIN RW.PIN +.ob CLK_DIV_OUT CLK_EXP FPU_CS AVEC AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_2_.C IPL_D0_0_.C IPL_D0_1_.C IPL_D0_2_.C SM_AMIGA_i_7_.C SM_AMIGA_6_.C SM_AMIGA_5_.C SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.C SM_AMIGA_1_.C SM_AMIGA_0_.C cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C E.C IPL_030_0_.C IPL_030_1_.C CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.C RST_DLY_0_.C RST_DLY_1_.C RST_DLY_2_.C RST_DLY_3_.C RST_DLY_4_.C RST_DLY_5_.C RST_DLY_6_.C RST_DLY_7_.C CYCLE_DMA_0_.C CYCLE_DMA_1_.C SIZE_DMA_0_.C SIZE_DMA_1_.C CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.C CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.C inst_CLK_030_H.C RESET.C inst_DS_000_ENABLE.C inst_UDS_000_INT.C RW.C RW_000.C inst_LDS_000_INT.C inst_AS_030_000_SYNC.C inst_AS_000_INT.C DSACK1.C A0.C inst_AS_000_DMA.C inst_DS_000_DMA.C inst_DS_030_D0.C inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.C inst_VPA_D.C inst_DTACK_D0.C BGACK_030.C BG_000.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.C VMA.C inst_BGACK_030_INT_D.C inst_CLK_000_PE.C inst_CLK_000_NE.C inst_CLK_OUT_PRE_50.C inst_CLK_000_D1.C inst_CLK_000_NE_D0.C inst_CLK_OUT_PRE_D.C inst_CLK_000_D0.C SIZE_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 BERR SIZE_0_ N_96_i AS_030.OE AS_000.OE RW_000.OE DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE BERR.OE RW.OE CLK_DIV_OUT.OE DSACK1.OE CIIN.OE BGACK_030.D E.D VMA.T RESET.D cpu_est_0_.D cpu_est_1_.D inst_AS_000_INT.D SM_AMIGA_5_.D inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AS_030_D0.D inst_nEXP_SPACE_D0reg.D inst_DS_030_D0.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D inst_AS_000_DMA.D inst_DS_000_DMA.D CYCLE_DMA_0_.D CYCLE_DMA_1_.D SIZE_DMA_0_.D SIZE_DMA_1_.D inst_VPA_D.D inst_UDS_000_INT.D inst_LDS_000_INT.D inst_CLK_OUT_PRE_D.D inst_DTACK_D0.D inst_CLK_OUT_PRE_50.D inst_CLK_000_D1.D inst_CLK_000_D0.D inst_CLK_000_PE.D CLK_000_P_SYNC_9_.D inst_CLK_000_NE.D CLK_000_N_SYNC_11_.D cpu_est_2_.D IPL_D0_0_.D IPL_D0_1_.D IPL_D0_2_.D SM_AMIGA_3_.T inst_CLK_000_NE_D0.D SM_AMIGA_0_.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.D DSACK1.D SM_AMIGA_6_.D RST_DLY_0_.D RST_DLY_1_.D RST_DLY_2_.D RST_DLY_3_.D RST_DLY_4_.T RST_DLY_5_.T RST_DLY_6_.T RST_DLY_7_.D CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_8_.D CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_10_.D RW_000.D RW.D A0.D inst_CLK_030_H.D SM_AMIGA_1_.D SM_AMIGA_4_.D SM_AMIGA_2_.D inst_DS_000_ENABLE.D SM_AMIGA_i_7_.D BG_000.D IPL_030_0_.D IPL_030_1_.D IPL_030_2_.D +.p 621 +------------------------------------------------------------------------------------------------------------------------------- ~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-1----------------------------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--0---------------------------------------------------------------------------------------------------------------------------- ~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1-------------------------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----1------------------------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ +------0------------------------------------------------------------------------------------------------------------------------ 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +.end diff --git a/Logic/68030_tk.tt4 b/Logic/68030_tk.tt4 new file mode 100644 index 0000000..5a3e5d2 --- /dev/null +++ b/Logic/68030_tk.tt4 @@ -0,0 +1,341 @@ +#$ TOOL ispLEVER Classic 1.8.00.04.29.14 +#$ DATE Wed May 13 22:59:21 2015 +#$ MODULE BUS68030 +#$ PINS 61 A_28_ A_27_ SIZE_1_ A_26_ A_25_ A_31_ A_24_ A_23_ A_22_ A_21_ IPL_2_ + A_20_ A_19_ FC_1_ A_18_ AS_030 A_17_ AS_000 A_16_ DS_030 UDS_000 LDS_000 A1 + nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP + IPL_1_ FPU_CS IPL_0_ FPU_SENSE FC_0_ DTACK AVEC VPA RST AMIGA_ADDR_ENABLE + AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ A_30_ + A_29_ IPL_030_2_ RW_000 A0 BG_000 BGACK_030 IPL_030_1_ IPL_030_0_ DSACK1 E VMA + RESET RW +#$ NODES 73 cpu_est_0_ cpu_est_1_ inst_AS_000_INT SM_AMIGA_5_ + inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_nEXP_SPACE_D0reg + inst_DS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA + inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D + inst_UDS_000_INT inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0 + inst_CLK_OUT_PRE_50 inst_CLK_000_D1 inst_CLK_000_D0 inst_CLK_000_PE + CLK_000_P_SYNC_9_ inst_CLK_000_NE N_96_i CLK_000_N_SYNC_11_ cpu_est_2_ IPL_D0_0_ + IPL_D0_1_ IPL_D0_2_ SM_AMIGA_3_ inst_CLK_000_NE_D0 SM_AMIGA_0_ + inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_6_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ + RST_DLY_3_ RST_DLY_4_ RST_DLY_5_ RST_DLY_6_ RST_DLY_7_ CLK_000_P_SYNC_0_ + CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ + CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ + CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ + CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ + CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ inst_CLK_030_H + SM_AMIGA_1_ SM_AMIGA_4_ SM_AMIGA_2_ inst_DS_000_ENABLE SM_AMIGA_i_7_ CIIN_0 +.type f +.i 128 +.o 200 +.ilb A_31_ IPL_2_ FC_1_ A1 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI + FPU_SENSE DTACK VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ + A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q E.Q VMA.Q + RESET.Q cpu_est_0_.Q cpu_est_1_.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q + inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_nEXP_SPACE_D0reg.Q + inst_DS_030_D0.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q + inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q + inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q + inst_DTACK_D0.Q inst_CLK_OUT_PRE_50.Q inst_CLK_000_D1.Q inst_CLK_000_D0.Q + inst_CLK_000_PE.Q CLK_000_P_SYNC_9_.Q inst_CLK_000_NE.Q N_96_i + CLK_000_N_SYNC_11_.Q cpu_est_2_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q + SM_AMIGA_3_.Q inst_CLK_000_NE_D0.Q SM_AMIGA_0_.Q + inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q SM_AMIGA_6_.Q RST_DLY_0_.Q + RST_DLY_1_.Q RST_DLY_2_.Q RST_DLY_3_.Q RST_DLY_4_.Q RST_DLY_5_.Q RST_DLY_6_.Q + RST_DLY_7_.Q CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q CLK_000_P_SYNC_2_.Q + CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q CLK_000_P_SYNC_6_.Q + CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q CLK_000_N_SYNC_0_.Q CLK_000_N_SYNC_1_.Q + CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q CLK_000_N_SYNC_5_.Q + CLK_000_N_SYNC_6_.Q CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q + CLK_000_N_SYNC_10_.Q RW_000.Q RW.Q A0.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q + SM_AMIGA_4_.Q SM_AMIGA_2_.Q inst_DS_000_ENABLE.Q SM_AMIGA_i_7_.Q BG_000.Q + IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN + DS_030.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN BERR.PIN + RW.PIN CIIN_0 +.ob SIZE_1_ SIZE_1_.OE AS_030% AS_030.OE AS_000% AS_000.OE DS_030% DS_030.OE + UDS_000% UDS_000.OE LDS_000% LDS_000.OE BERR BERR.OE CLK_DIV_OUT CLK_DIV_OUT.OE + CLK_EXP FPU_CS% AVEC AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW% + AMIGA_BUS_ENABLE_HIGH CIIN CIIN.OE SIZE_0_ SIZE_0_.OE IPL_030_2_.D% IPL_030_2_.C + RW_000.D% RW_000.C RW_000.OE A0.D A0.C A0.OE BG_000.D% BG_000.C BGACK_030.D% + BGACK_030.C IPL_030_1_.D% IPL_030_1_.C IPL_030_0_.D% IPL_030_0_.C DSACK1.D% + DSACK1.C DSACK1.OE E.D E.C VMA.T VMA.C RESET.D RESET.C RW.D% RW.C RW.OE + cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D% cpu_est_1_.C inst_AS_000_INT.D% + inst_AS_000_INT.C SM_AMIGA_5_.D SM_AMIGA_5_.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D% + inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_AS_030_D0.D% inst_AS_030_D0.C + inst_nEXP_SPACE_D0reg.D% inst_nEXP_SPACE_D0reg.C inst_DS_030_D0.D% + inst_DS_030_D0.C inst_AS_030_000_SYNC.D% inst_AS_030_000_SYNC.C + inst_BGACK_030_INT_D.D% inst_BGACK_030_INT_D.C inst_AS_000_DMA.D + inst_AS_000_DMA.C inst_DS_000_DMA.D inst_DS_000_DMA.C CYCLE_DMA_0_.D + CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D% SIZE_DMA_0_.C + SIZE_DMA_1_.D SIZE_DMA_1_.C inst_VPA_D.D% inst_VPA_D.C inst_UDS_000_INT.D% + inst_UDS_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C inst_CLK_OUT_PRE_D.D + inst_CLK_OUT_PRE_D.C inst_DTACK_D0.D% inst_DTACK_D0.C inst_CLK_OUT_PRE_50.D + inst_CLK_OUT_PRE_50.C inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_D0.D + inst_CLK_000_D0.C inst_CLK_000_PE.D inst_CLK_000_PE.C CLK_000_P_SYNC_9_.D + CLK_000_P_SYNC_9_.C inst_CLK_000_NE.D inst_CLK_000_NE.C N_96_i% + CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C cpu_est_2_.D cpu_est_2_.C IPL_D0_0_.D% + IPL_D0_0_.C IPL_D0_1_.D% IPL_D0_1_.C IPL_D0_2_.D% IPL_D0_2_.C SM_AMIGA_3_.T + SM_AMIGA_3_.C inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C SM_AMIGA_0_.D + SM_AMIGA_0_.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D% inst_AMIGA_BUS_ENABLE_DMA_HIGH.C + SM_AMIGA_6_.D SM_AMIGA_6_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C + RST_DLY_2_.D RST_DLY_2_.C RST_DLY_3_.D RST_DLY_3_.C RST_DLY_4_.T.X1 + RST_DLY_4_.T.X2 RST_DLY_4_.C RST_DLY_5_.T RST_DLY_5_.C RST_DLY_6_.T RST_DLY_6_.C + RST_DLY_7_.D RST_DLY_7_.C CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C + CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_2_.C + CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C + CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_6_.C + CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C + CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C + CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C + CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C + CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C + CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C + CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_10_.C inst_CLK_030_H.D inst_CLK_030_H.C + SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_4_.D 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00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 +-------------1-------------------------------------------------1-------0-----------------------------------------------------1-- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 +.end diff --git a/Logic/68030_tk.tte b/Logic/68030_tk.tte new file mode 100644 index 0000000..9d7e34c --- /dev/null +++ b/Logic/68030_tk.tte @@ -0,0 +1,341 @@ +#$ TOOL ispLEVER Classic 1.8.00.04.29.14 +#$ DATE Wed May 13 22:59:21 2015 +#$ MODULE BUS68030 +#$ PINS 61 A_28_ A_27_ SIZE_1_ A_26_ A_25_ A_31_ A_24_ A_23_ A_22_ A_21_ IPL_2_ + A_20_ A_19_ FC_1_ A_18_ AS_030 A_17_ AS_000 A_16_ DS_030 UDS_000 LDS_000 A1 + nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP + IPL_1_ FPU_CS IPL_0_ FPU_SENSE FC_0_ DTACK AVEC VPA RST AMIGA_ADDR_ENABLE + AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ A_30_ + A_29_ IPL_030_2_ RW_000 A0 BG_000 BGACK_030 IPL_030_1_ IPL_030_0_ DSACK1 E VMA + RESET RW +#$ NODES 73 cpu_est_0_ cpu_est_1_ inst_AS_000_INT SM_AMIGA_5_ + inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_nEXP_SPACE_D0reg + inst_DS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA + inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D + inst_UDS_000_INT inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0 + inst_CLK_OUT_PRE_50 inst_CLK_000_D1 inst_CLK_000_D0 inst_CLK_000_PE + CLK_000_P_SYNC_9_ inst_CLK_000_NE N_96_i CLK_000_N_SYNC_11_ cpu_est_2_ IPL_D0_0_ + IPL_D0_1_ IPL_D0_2_ SM_AMIGA_3_ inst_CLK_000_NE_D0 SM_AMIGA_0_ + inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_6_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ + RST_DLY_3_ RST_DLY_4_ RST_DLY_5_ RST_DLY_6_ RST_DLY_7_ CLK_000_P_SYNC_0_ + CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ + CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ + CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ + CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ + CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ inst_CLK_030_H + SM_AMIGA_1_ SM_AMIGA_4_ SM_AMIGA_2_ inst_DS_000_ENABLE SM_AMIGA_i_7_ CIIN_0 +.type f +.i 128 +.o 200 +.ilb A_31_ IPL_2_ FC_1_ A1 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI + FPU_SENSE DTACK VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ + A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q E.Q VMA.Q + RESET.Q cpu_est_0_.Q cpu_est_1_.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q + inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_nEXP_SPACE_D0reg.Q + inst_DS_030_D0.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q + inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q + inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q + inst_DTACK_D0.Q inst_CLK_OUT_PRE_50.Q inst_CLK_000_D1.Q inst_CLK_000_D0.Q + inst_CLK_000_PE.Q CLK_000_P_SYNC_9_.Q inst_CLK_000_NE.Q N_96_i + CLK_000_N_SYNC_11_.Q cpu_est_2_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q + SM_AMIGA_3_.Q inst_CLK_000_NE_D0.Q SM_AMIGA_0_.Q + inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q SM_AMIGA_6_.Q RST_DLY_0_.Q + RST_DLY_1_.Q RST_DLY_2_.Q RST_DLY_3_.Q RST_DLY_4_.Q RST_DLY_5_.Q RST_DLY_6_.Q + RST_DLY_7_.Q CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q CLK_000_P_SYNC_2_.Q + CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q CLK_000_P_SYNC_6_.Q + CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q CLK_000_N_SYNC_0_.Q CLK_000_N_SYNC_1_.Q + CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q CLK_000_N_SYNC_5_.Q + CLK_000_N_SYNC_6_.Q CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q + CLK_000_N_SYNC_10_.Q RW_000.Q RW.Q A0.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q + SM_AMIGA_4_.Q SM_AMIGA_2_.Q inst_DS_000_ENABLE.Q SM_AMIGA_i_7_.Q BG_000.Q + IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN + DS_030.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN BERR.PIN + RW.PIN CIIN_0 +.ob SIZE_1_ SIZE_1_.OE AS_030- AS_030.OE AS_000- AS_000.OE DS_030- DS_030.OE + UDS_000- UDS_000.OE LDS_000- LDS_000.OE BERR BERR.OE CLK_DIV_OUT CLK_DIV_OUT.OE + CLK_EXP FPU_CS- AVEC AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW- + AMIGA_BUS_ENABLE_HIGH CIIN CIIN.OE SIZE_0_ SIZE_0_.OE IPL_030_2_.D- IPL_030_2_.C + RW_000.D- RW_000.C RW_000.OE A0.D A0.C A0.OE BG_000.D- BG_000.C BGACK_030.D- + BGACK_030.C IPL_030_1_.D- IPL_030_1_.C IPL_030_0_.D- IPL_030_0_.C DSACK1.D- + DSACK1.C DSACK1.OE E.D E.C VMA.T VMA.C RESET.D RESET.C RW.D- RW.C RW.OE + cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D- cpu_est_1_.C inst_AS_000_INT.D- + inst_AS_000_INT.C SM_AMIGA_5_.D SM_AMIGA_5_.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D- + inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_AS_030_D0.D- inst_AS_030_D0.C + inst_nEXP_SPACE_D0reg.D- inst_nEXP_SPACE_D0reg.C inst_DS_030_D0.D- + inst_DS_030_D0.C inst_AS_030_000_SYNC.D- inst_AS_030_000_SYNC.C + inst_BGACK_030_INT_D.D- inst_BGACK_030_INT_D.C inst_AS_000_DMA.D + inst_AS_000_DMA.C inst_DS_000_DMA.D inst_DS_000_DMA.C CYCLE_DMA_0_.D + CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D- SIZE_DMA_0_.C + SIZE_DMA_1_.D SIZE_DMA_1_.C inst_VPA_D.D- inst_VPA_D.C inst_UDS_000_INT.D- + inst_UDS_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C inst_CLK_OUT_PRE_D.D + inst_CLK_OUT_PRE_D.C inst_DTACK_D0.D- inst_DTACK_D0.C inst_CLK_OUT_PRE_50.D + inst_CLK_OUT_PRE_50.C inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_D0.D + inst_CLK_000_D0.C inst_CLK_000_PE.D inst_CLK_000_PE.C CLK_000_P_SYNC_9_.D + CLK_000_P_SYNC_9_.C inst_CLK_000_NE.D inst_CLK_000_NE.C N_96_i- + CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C cpu_est_2_.D cpu_est_2_.C IPL_D0_0_.D- + IPL_D0_0_.C IPL_D0_1_.D- IPL_D0_1_.C IPL_D0_2_.D- IPL_D0_2_.C SM_AMIGA_3_.T + SM_AMIGA_3_.C inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C SM_AMIGA_0_.D + SM_AMIGA_0_.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- inst_AMIGA_BUS_ENABLE_DMA_HIGH.C + SM_AMIGA_6_.D SM_AMIGA_6_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C + RST_DLY_2_.D RST_DLY_2_.C RST_DLY_3_.D RST_DLY_3_.C RST_DLY_4_.T.X1 + RST_DLY_4_.T.X2 RST_DLY_4_.C RST_DLY_5_.T RST_DLY_5_.C RST_DLY_6_.T RST_DLY_6_.C + RST_DLY_7_.D RST_DLY_7_.C CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C + CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_2_.C + CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C + CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_6_.C + CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C + CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C + CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C + 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b/Logic/68030_tk.vcl new file mode 100644 index 0000000..b318b17 --- /dev/null +++ b/Logic/68030_tk.vcl @@ -0,0 +1,253 @@ +[DEVICE] + +Family = M4A5; +PartType = M4A5-128/64; +Package = 100TQFP; +PartNumber = M4A5-128/64-10VC; +Speed = -10; +Operating_condition = COM; +EN_Segment = NO; +Pin_MC_1to1 = NO; +Voltage = 5.0; + +[REVISION] + +RCS = "$Revision: 1.2 $"; +Parent = m4a5.lci; +SDS_file = m4a5.sds; +Design = 68030_tk.tt4; +Rev = 0.01; +DATE = 5/13/15; +TIME = 22:59:29; +Type = TT2; +Pre_Fit_Time = 1; +Source_Format = Pure_VHDL; + +[IGNORE ASSIGNMENTS] + +Pin_Assignments = NO; +Pin_Keep_Block = NO; +Pin_Keep_Segment = NO; +Group_Assignments = NO; +Macrocell_Assignments = NO; +Macrocell_Keep_Block = NO; +Macrocell_Keep_Segment = NO; +Pin_Reservation = NO; +Timing_Constraints = NO; +Block_Reservation = NO; +Segment_Reservation = NO; +Ignore_Source_Location = NO; +Ignore_Source_Optimization = NO; +Ignore_Source_Timing = NO; + +[CLEAR ASSIGNMENTS] + +Pin_Assignments = NO; +Pin_Keep_Block = NO; +Pin_Keep_Segment = NO; +Group_Assignments = NO; +Macrocell_Assignments = NO; +Macrocell_Keep_Block = NO; +Macrocell_Keep_Segment = NO; +Pin_Reservation = NO; +Timing_Constraints = NO; +Block_Reservation = NO; +Segment_Reservation = NO; +Ignore_Source_Location = NO; +Ignore_Source_Optimization = NO; +Ignore_Source_Timing = NO; + +[BACKANNOTATE NETLIST] + +Netlist = VHDL; +Delay_File = SDF; +Generic_VCC = ; +Generic_GND = ; + +[BACKANNOTATE ASSIGNMENTS] + +Pin_Assignment = NO; +Pin_Block = NO; +Pin_Macrocell_Block = NO; +Routing = NO; + +[GLOBAL PROJECT OPTIMIZATION] + +Balanced_Partitioning = YES; +Spread_Placement = YES; +Max_Pin_Percent = 100; +Max_Macrocell_Percent = 100; +Max_Inter_Seg_Percent = 100; +Max_Seg_In_Percent = 100; +Max_Blk_In_Percent = 100; + +[FITTER REPORT FORMAT] + +Fitter_Options = YES; +Pinout_Diagram = NO; +Pinout_Listing = YES; +Detailed_Block_Segment_Summary = YES; +Input_Signal_List = YES; +Output_Signal_List = YES; +Bidir_Signal_List = YES; +Node_Signal_List = YES; +Signal_Fanout_List = YES; +Block_Segment_Fanin_List = YES; +Prefit_Eqn = YES; +Postfit_Eqn = YES; +Page_Break = YES; + +[OPTIMIZATION OPTIONS] + +Logic_Reduction = YES; +Max_PTerm_Split = 16; +Max_PTerm_Collapse = 16; +XOR_Synthesis = YES; +Node_Collapse = Yes; +DT_Synthesis = Yes; + +[FITTER GLOBAL OPTIONS] + +Run_Time = 0; +Set_Reset_Dont_Care = NO; +In_Reg_Optimize = YES; +Clock_Optimize = NO; +Conf_Unused_IOs = OUT_LOW; + +[POWER] +Powerlevel = Low, High; +Default = High; +Low = 8, H, G, F, E, D, C, B, A; +Type = GLB; + +[HARDWARE DEVICE OPTIONS] +Zero_Hold_Time = Yes; +Signature_Word = 0; +Pull_up = Yes; +Out_Slew_Rate = SLOW, FAST, 7, CLK_DIV_OUT, CLK_EXP, FPU_CS, AMIGA_BUS_DATA_DIR, AMIGA_BUS_ENABLE_LOW, + AMIGA_ADDR_ENABLE, AMIGA_BUS_ENABLE_HIGH; +Device_max_fanin = 33; +Device_max_pterms = 20; +Usercode_Format = Hex; + +[PIN RESERVATIONS] +layer = OFF; + +[LOCATION ASSIGNMENT] + +Layer = OFF +BERR = OUTPUT,41,4,-; +RW_000 = BIDIR,80,7,-; +AS_000 = OUTPUT,42,4,-; +RW = BIDIR,71,6,-; +DS_030 = OUTPUT,98,0,-; +AS_030 = OUTPUT,82,7,-; +UDS_000 = OUTPUT,32,3,-; +LDS_000 = OUTPUT,31,3,-; +A0 = BIDIR,69,6,-; +SIZE_1_ = OUTPUT,79,7,-; +SIZE_0_ = OUTPUT,70,6,-; +IPL_030_2_ = OUTPUT,9,1,-; +IPL_030_0_ = OUTPUT,8,1,-; +IPL_030_1_ = OUTPUT,7,1,-; +E = OUTPUT,66,6,-; +DSACK1 = OUTPUT,81,7,-; +VMA = OUTPUT,35,3,-; +BGACK_030 = OUTPUT,83,7,-; +AMIGA_BUS_DATA_DIR = OUTPUT,48,4,-; +AMIGA_BUS_ENABLE_HIGH = OUTPUT,34,3,-; +BG_000 = OUTPUT,29,3,-; +RESET = OUTPUT,3,1,-; +AVEC = OUTPUT,92,0,-; +FPU_CS = OUTPUT,78,7,-; +CLK_DIV_OUT = OUTPUT,65,6,-; +CIIN = OUTPUT,47,4,-; +AMIGA_ADDR_ENABLE = OUTPUT,33,3,-; +AMIGA_BUS_ENABLE_LOW = OUTPUT,20,2,-; +CLK_EXP = OUTPUT,10,1,-; +inst_nEXP_SPACE_D0reg = NODE,*,6,-; +RN_RESET = NODE,-1,1,-; +RN_BGACK_030 = NODE,-1,7,-; +inst_CLK_000_PE = NODE,*,5,-; +inst_AS_030_D0 = NODE,*,7,-; +SM_AMIGA_i_7_ = NODE,*,5,-; +inst_CLK_000_NE = NODE,*,4,-; +RN_E = NODE,-1,6,-; +cpu_est_1_ = NODE,*,3,-; +cpu_est_2_ = NODE,*,3,-; +SM_AMIGA_1_ = NODE,*,5,-; +SM_AMIGA_5_ = NODE,*,5,-; +SM_AMIGA_0_ = NODE,*,1,-; +cpu_est_0_ = NODE,*,5,-; +inst_CLK_000_NE_D0 = NODE,*,3,-; +inst_CLK_000_D0 = NODE,*,3,-; +inst_AS_000_DMA = NODE,*,0,-; +inst_AS_030_000_SYNC = NODE,*,2,-; +RST_DLY_3_ = NODE,*,0,-; +RST_DLY_2_ = NODE,*,1,-; +RST_DLY_5_ = NODE,*,1,-; +RST_DLY_1_ = NODE,*,0,-; +inst_LDS_000_INT = NODE,*,2,-; +RN_VMA = NODE,-1,3,-; +inst_DS_000_ENABLE = NODE,*,5,-; +RST_DLY_6_ = NODE,*,1,-; +RST_DLY_0_ = NODE,*,1,-; +SM_AMIGA_6_ = NODE,*,5,-; +inst_UDS_000_INT = NODE,*,2,-; +SIZE_DMA_1_ = NODE,*,6,-; +SIZE_DMA_0_ = NODE,*,6,-; +RST_DLY_7_ = NODE,*,1,-; +RST_DLY_4_ = NODE,*,0,-; +inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,*,2,-; +inst_AS_000_INT = NODE,*,2,-; +inst_CLK_000_D1 = NODE,*,6,-; +inst_VPA_D = NODE,*,1,-; +inst_BGACK_030_INT_D = NODE,*,7,-; +RN_IPL_030_0_ = NODE,-1,1,-; +RN_IPL_030_1_ = NODE,-1,1,-; +RN_IPL_030_2_ = NODE,-1,1,-; +inst_DS_000_DMA = NODE,*,0,-; +inst_CLK_030_H = NODE,*,0,-; +SM_AMIGA_3_ = NODE,*,5,-; +RN_DSACK1 = NODE,-1,7,-; +SM_AMIGA_2_ = NODE,*,5,-; +N_96_i = NODE,*,5,-; +RN_A0 = NODE,-1,6,-; +RN_RW_000 = NODE,-1,7,-; +SM_AMIGA_4_ = NODE,*,5,-; +CYCLE_DMA_1_ = NODE,*,0,-; +RN_RW = NODE,-1,6,-; +RN_BG_000 = NODE,-1,3,-; +CIIN_0 = NODE,*,4,-; +CYCLE_DMA_0_ = NODE,*,0,-; +inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,*,2,-; +CLK_000_N_SYNC_10_ = NODE,*,7,-; +CLK_000_N_SYNC_9_ = NODE,*,6,-; +CLK_000_N_SYNC_8_ = NODE,*,0,-; +CLK_000_N_SYNC_7_ = NODE,*,3,-; +CLK_000_N_SYNC_6_ = NODE,*,3,-; +CLK_000_N_SYNC_5_ = NODE,*,2,-; +CLK_000_N_SYNC_4_ = NODE,*,0,-; +CLK_000_N_SYNC_3_ = NODE,*,3,-; +CLK_000_N_SYNC_2_ = NODE,*,3,-; +CLK_000_N_SYNC_1_ = NODE,*,1,-; +CLK_000_N_SYNC_0_ = NODE,*,3,-; +CLK_000_P_SYNC_8_ = NODE,*,0,-; +CLK_000_P_SYNC_7_ = NODE,*,0,-; +CLK_000_P_SYNC_6_ = NODE,*,6,-; +CLK_000_P_SYNC_5_ = NODE,*,6,-; +CLK_000_P_SYNC_4_ = NODE,*,1,-; +CLK_000_P_SYNC_3_ = NODE,*,1,-; +CLK_000_P_SYNC_2_ = NODE,*,6,-; +CLK_000_P_SYNC_1_ = NODE,*,6,-; +CLK_000_P_SYNC_0_ = NODE,*,3,-; +IPL_D0_2_ = NODE,*,6,-; +IPL_D0_1_ = NODE,*,6,-; +IPL_D0_0_ = NODE,*,1,-; +CLK_000_N_SYNC_11_ = NODE,*,7,-; +CLK_000_P_SYNC_9_ = NODE,*,0,-; +inst_CLK_OUT_PRE_50 = NODE,*,4,-; +inst_DTACK_D0 = NODE,*,2,-; +inst_CLK_OUT_PRE_D = NODE,*,4,-; +inst_DS_030_D0 = NODE,*,0,-; +CLK_OSZI = INPUT,61,-,-; diff --git a/Logic/68030_tk.vco b/Logic/68030_tk.vco new file mode 100644 index 0000000..057043e --- /dev/null +++ b/Logic/68030_tk.vco @@ -0,0 +1,272 @@ +[DEVICE] + +Family = M4A5; +PartType = M4A5-128/64; +Package = 100TQFP; +PartNumber = M4A5-128/64-10VC; +Speed = -10; +Operating_condition = COM; +EN_Segment = NO; +Pin_MC_1to1 = NO; +Voltage = 5.0; + +[REVISION] + +RCS = "$Revision: 1.2 $"; +Parent = m4a5.lci; +SDS_file = m4a5.sds; +Design = 68030_tk.tt4; +Rev = 0.01; +DATE = 5/13/15; +TIME = 22:59:29; +Type = TT2; +Pre_Fit_Time = 1; +Source_Format = Pure_VHDL; + +[IGNORE ASSIGNMENTS] + +Pin_Assignments = NO; +Pin_Keep_Block = NO; +Pin_Keep_Segment = NO; +Group_Assignments = NO; +Macrocell_Assignments = NO; +Macrocell_Keep_Block = NO; +Macrocell_Keep_Segment = NO; +Pin_Reservation = NO; +Timing_Constraints = NO; +Block_Reservation = NO; +Segment_Reservation = NO; +Ignore_Source_Location = NO; +Ignore_Source_Optimization = NO; +Ignore_Source_Timing = NO; + +[CLEAR ASSIGNMENTS] + +Pin_Assignments = NO; +Pin_Keep_Block = NO; +Pin_Keep_Segment = NO; +Group_Assignments = NO; +Macrocell_Assignments = NO; +Macrocell_Keep_Block = NO; +Macrocell_Keep_Segment = NO; +Pin_Reservation = NO; +Timing_Constraints = NO; +Block_Reservation = NO; +Segment_Reservation = NO; +Ignore_Source_Location = NO; +Ignore_Source_Optimization = NO; +Ignore_Source_Timing = NO; + +[BACKANNOTATE NETLIST] + +Netlist = VHDL; +Delay_File = SDF; +Generic_VCC = ; +Generic_GND = ; + +[BACKANNOTATE ASSIGNMENTS] + +Pin_Assignment = NO; +Pin_Block = NO; +Pin_Macrocell_Block = NO; +Routing = NO; + +[GLOBAL PROJECT OPTIMIZATION] + +Balanced_Partitioning = YES; +Spread_Placement = YES; +Max_Pin_Percent = 100; +Max_Macrocell_Percent = 100; +Max_Inter_Seg_Percent = 100; +Max_Seg_In_Percent = 100; +Max_Blk_In_Percent = 100; + +[FITTER REPORT FORMAT] + +Fitter_Options = YES; +Pinout_Diagram = NO; +Pinout_Listing = YES; +Detailed_Block_Segment_Summary = YES; +Input_Signal_List = YES; +Output_Signal_List = YES; +Bidir_Signal_List = YES; +Node_Signal_List = YES; +Signal_Fanout_List = YES; +Block_Segment_Fanin_List = YES; +Prefit_Eqn = YES; +Postfit_Eqn = YES; +Page_Break = YES; + +[OPTIMIZATION OPTIONS] + +Logic_Reduction = YES; +Max_PTerm_Split = 16; +Max_PTerm_Collapse = 16; +XOR_Synthesis = YES; +Node_Collapse = Yes; +DT_Synthesis = Yes; + +[FITTER GLOBAL OPTIONS] + +Run_Time = 0; +Set_Reset_Dont_Care = NO; +In_Reg_Optimize = YES; +Clock_Optimize = NO; +Conf_Unused_IOs = OUT_LOW; + +[POWER] +Powerlevel = Low, High; +Default = High; +Low = 8, H, G, F, E, D, C, B, A; +Type = GLB; + +[HARDWARE DEVICE OPTIONS] +Zero_Hold_Time = Yes; +Signature_Word = 0; +Pull_up = Yes; +Out_Slew_Rate = SLOW, FAST, 7, CLK_DIV_OUT, CLK_EXP, FPU_CS, AMIGA_BUS_DATA_DIR, AMIGA_BUS_ENABLE_LOW, + AMIGA_ADDR_ENABLE, AMIGA_BUS_ENABLE_HIGH; +Device_max_fanin = 33; +Device_max_pterms = 20; +Usercode_Format = Hex; + +[PIN RESERVATIONS] +layer = OFF; + +[LOCATION ASSIGNMENT] + +Layer = OFF; +A_28_ = INPUT,15, C,-; +A_27_ = INPUT,16, C,-; +SIZE_1_ = BIDIR,79, H,-; +A_26_ = INPUT,17, C,-; +A_25_ = INPUT,18, C,-; +A_31_ = INPUT,4, B,-; +A_24_ = INPUT,19, C,-; +A_23_ = INPUT,85, H,-; +A_22_ = INPUT,84, H,-; +A_21_ = INPUT,94, A,-; +IPL_2_ = INPUT,68, G,-; +A_20_ = INPUT,93, A,-; +A_19_ = INPUT,97, A,-; +FC_1_ = INPUT,58, F,-; +A_18_ = INPUT,95, A,-; +AS_030 = BIDIR,82, H,-; +A_17_ = INPUT,59, F,-; +AS_000 = BIDIR,42, E,-; +A_16_ = INPUT,96, A,-; +DS_030 = BIDIR,98, A,-; +UDS_000 = BIDIR,32, D,-; +LDS_000 = BIDIR,31, D,-; +A1 = INPUT,60, F,-; +nEXP_SPACE = INPUT,14,-,-; +BERR = BIDIR,41, E,-; +BG_030 = INPUT,21, C,-; +BGACK_000 = INPUT,28, D,-; +CLK_030 = INPUT,64,-,-; +CLK_000 = INPUT,11,-,-; +CLK_OSZI = INPUT,61,-,-; +CLK_DIV_OUT = OUTPUT,65, G,-; +CLK_EXP = OUTPUT,10, B,-; +IPL_1_ = INPUT,56, F,-; +FPU_CS = OUTPUT,78, H,-; +IPL_0_ = INPUT,67, G,-; +FPU_SENSE = INPUT,91, A,-; +FC_0_ = INPUT,57, F,-; +DTACK = INPUT,30, D,-; +AVEC = OUTPUT,92, A,-; +VPA = INPUT,36,-,-; +RST = INPUT,86,-,-; +AMIGA_ADDR_ENABLE = OUTPUT,33, D,-; +AMIGA_BUS_DATA_DIR = OUTPUT,48, E,-; +AMIGA_BUS_ENABLE_LOW = OUTPUT,20, C,-; +AMIGA_BUS_ENABLE_HIGH = OUTPUT,34, D,-; +CIIN = OUTPUT,47, E,-; +SIZE_0_ = BIDIR,70, G,-; +A_30_ = INPUT,5, B,-; +A_29_ = INPUT,6, B,-; +IPL_030_2_ = OUTPUT,9, B,-; +RW_000 = BIDIR,80, H,-; +A0 = BIDIR,69, G,-; +BG_000 = OUTPUT,29, D,-; +BGACK_030 = OUTPUT,83, H,-; +IPL_030_1_ = OUTPUT,7, B,-; +IPL_030_0_ = OUTPUT,8, B,-; +DSACK1 = OUTPUT,81, H,-; +E = OUTPUT,66, G,-; +VMA = OUTPUT,35, D,-; +RESET = OUTPUT,3, B,-; +RW = BIDIR,71, G,-; +cpu_est_0_ = NODE,1, F,-; +cpu_est_1_ = NODE,9, D,-; +inst_AS_000_INT = NODE,5, C,-; +SM_AMIGA_5_ = NODE,12, F,-; +inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,9, C,-; +inst_AS_030_D0 = NODE,5, H,-; +inst_nEXP_SPACE_D0reg = NODE,5, G,-; +inst_DS_030_D0 = NODE,15, A,-; +inst_AS_030_000_SYNC = NODE,4, C,-; +inst_BGACK_030_INT_D = NODE,13, H,-; +inst_AS_000_DMA = NODE,8, A,-; +inst_DS_000_DMA = NODE,9, A,-; +CYCLE_DMA_0_ = NODE,6, A,-; +CYCLE_DMA_1_ = NODE,2, A,-; +SIZE_DMA_0_ = NODE,13, G,-; +SIZE_DMA_1_ = NODE,9, G,-; +inst_VPA_D = NODE,14, B,-; +inst_UDS_000_INT = NODE,12, C,-; +inst_LDS_000_INT = NODE,8, C,-; +inst_CLK_OUT_PRE_D = NODE,13, E,-; +inst_DTACK_D0 = NODE,2, C,-; +inst_CLK_OUT_PRE_50 = NODE,9, E,-; +inst_CLK_000_D1 = NODE,2, G,-; +inst_CLK_000_D0 = NODE,6, D,-; +inst_CLK_000_PE = NODE,0, F,-; +CLK_000_P_SYNC_9_ = NODE,11, A,-; +inst_CLK_000_NE = NODE,8, E,-; +N_96_i = NODE,6, F,-; +CLK_000_N_SYNC_11_ = NODE,6, H,-; +cpu_est_2_ = NODE,13, D,-; +IPL_D0_0_ = NODE,15, B,-; +IPL_D0_1_ = NODE,15, G,-; +IPL_D0_2_ = NODE,11, G,-; +SM_AMIGA_3_ = NODE,13, F,-; +inst_CLK_000_NE_D0 = NODE,2, D,-; +SM_AMIGA_0_ = NODE,5, B,-; +inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,1, C,-; +SM_AMIGA_6_ = NODE,9, F,-; +RST_DLY_0_ = NODE,6, B,-; +RST_DLY_1_ = NODE,1, A,-; +RST_DLY_2_ = NODE,9, B,-; +RST_DLY_3_ = NODE,12, A,-; +RST_DLY_4_ = NODE,5, A,-; +RST_DLY_5_ = NODE,13, B,-; +RST_DLY_6_ = NODE,2, B,-; +RST_DLY_7_ = NODE,10, B,-; +CLK_000_P_SYNC_0_ = NODE,15, D,-; +CLK_000_P_SYNC_1_ = NODE,7, G,-; +CLK_000_P_SYNC_2_ = NODE,3, G,-; +CLK_000_P_SYNC_3_ = NODE,11, B,-; +CLK_000_P_SYNC_4_ = NODE,7, B,-; +CLK_000_P_SYNC_5_ = NODE,14, G,-; +CLK_000_P_SYNC_6_ = NODE,10, G,-; +CLK_000_P_SYNC_7_ = NODE,7, A,-; +CLK_000_P_SYNC_8_ = NODE,3, A,-; +CLK_000_N_SYNC_0_ = NODE,11, D,-; +CLK_000_N_SYNC_1_ = NODE,3, B,-; +CLK_000_N_SYNC_2_ = NODE,7, D,-; +CLK_000_N_SYNC_3_ = NODE,3, D,-; +CLK_000_N_SYNC_4_ = NODE,14, A,-; +CLK_000_N_SYNC_5_ = NODE,13, C,-; +CLK_000_N_SYNC_6_ = NODE,14, D,-; +CLK_000_N_SYNC_7_ = NODE,10, D,-; +CLK_000_N_SYNC_8_ = NODE,10, A,-; +CLK_000_N_SYNC_9_ = NODE,6, G,-; +CLK_000_N_SYNC_10_ = NODE,2, H,-; +inst_CLK_030_H = NODE,13, A,-; +SM_AMIGA_1_ = NODE,8, F,-; +SM_AMIGA_4_ = NODE,10, F,-; +SM_AMIGA_2_ = NODE,2, F,-; +inst_DS_000_ENABLE = NODE,5, F,-; +SM_AMIGA_i_7_ = NODE,4, F,-; +CIIN_0 = NODE,5, E,-; diff --git a/Logic/68030_tk.vct b/Logic/68030_tk.vct new file mode 100644 index 0000000..c26f14d --- /dev/null +++ b/Logic/68030_tk.vct @@ -0,0 +1,221 @@ +[DEVICE] +Family = M4A5; +PartType = M4A5-128/64; +Package = 100TQFP; +PartNumber = M4A5-128/64-10VC; +Speed = -10; +Operating_condition = COM; +EN_Segment = No; +Pin_MC_1to1 = No; +EN_PinReserve_IO = Yes; +EN_PinReserve_BIDIR = Yes; +Voltage = 5.0; + +[REVISION] +RCS = "$Revision: 1.2 $"; +Parent = m4a5.lci; +SDS_File = m4a5.sds; +DATE = 03/16/2015; +TIME = 21:53:52; +Source_Format = Pure_VHDL; +Type = TT2; +Pre_Fit_Time = 1; + +[IGNORE ASSIGNMENTS] +Pin_Assignments = No; +Pin_Keep_Block = No; +Pin_Keep_Segment = No; +Group_Assignments = No; +Macrocell_Assignments = No; +Macrocell_Keep_Block = No; +Macrocell_Keep_Segment = No; +Pin_Reservation = No; +Block_Reservation = No; +Segment_Reservation = No; +Timing_Constraints = No; + +[CLEAR ASSIGNMENTS] +Pin_Assignments = No; +Pin_Keep_Block = No; +Pin_Keep_Segment = No; +Group_Assignments = No; +Macrocell_Assignments = No; +Macrocell_Keep_Block = No; +Macrocell_Keep_Segment = No; +Pin_Reservation = No; +Block_Reservation = No; +Segment_Reservation = No; +Timing_Constraints = No; + +[BACKANNOTATE ASSIGNMENTS] +Pin_Block = No; +Pin_Macrocell_Block = No; +Routing = No; + +[GLOBAL PROJECT OPTIMIZATION] +Balanced_Partitioning = Yes; +Spread_Placement = Yes; +Max_Pin_Percent = 100; +Max_Macrocell_Percent = 100; +Max_Blk_In_Percent = 100; + +[OPTIMIZATION OPTIONS] +Logic_Reduction = Yes; +Max_PTerm_Split = 16; +Max_PTerm_Collapse = 16; +XOR_Synthesis = Yes; +EN_XOR_Synthesis = Yes; +XOR_Gate = Yes; +Node_Collapse = Yes; +Keep_XOR = Yes; +DT_Synthesis = Yes; +Clock_PTerm = Min; +Reset_PTerm = On; +Preset_PTerm = On; +Clock_Enable_PTerm = On; +Output_Enable_PTerm = On; +EN_DT_Synthesis = Yes; +Cluster_PTerm = 5; +FF_inv = No; +EN_Use_CE = No; +Use_CE = No; +Use_Internal_COM_FB = Yes; +EN_use_Internal_COM_FB = Yes; +Set_Reset_Swap = No; +EN_Set_Reset_Swap = No; +Density = No; +DeMorgan = Yes; +T_FF = Yes; +Max_Symbols = 32; + +[FITTER GLOBAL OPTIONS] +Run_Time = 0; +Set_Reset_Dont_Care = No; +EN_Set_Reset_Dont_Care = Yes; +In_Reg_Optimize = Yes; +EN_In_Reg_Optimize = No; +Clock_Optimize = No; +Global_Clock_As_Pterm = No; +Show_Iterations = No; +Routing_Attempts = 2; +Conf_Unused_IOs = Out_Low; + +[HARDWARE DEVICE OPTIONS] +Zero_Hold_Time = Yes; +Signature_Word = 0; +Pull_up = Yes; +Out_Slew_Rate = SLOW,FAST,7,CLK_DIV_OUT,CLK_EXP,FPU_CS,AMIGA_BUS_DATA_DIR,AMIGA_BUS_ENABLE_LOW,AMIGA_ADDR_ENABLE,AMIGA_BUS_ENABLE_HIGH; +Device_max_fanin = 33; +Device_max_pterms = 20; +Usercode_Format = Hex; + +[PIN RESERVATIONS] +Layer = OFF; + +[LOCATION ASSIGNMENT] +Layer = OFF; +AS_030 = input,82,H,-; +A_16_ = input,96,A,-; +A_17_ = input,59,F,-; +A_18_ = input,95,A,-; +A_19_ = input,97,A,-; +BGACK_000 = input,28,D,-; +BG_030 = input,21,C,-; +CLK_000 = input,11,-,-; +CLK_030 = input,64,-,-; +CLK_OSZI = input,61,-,-; +FC_0_ = input,57,F,-; +FC_1_ = input,58,F,-; +IPL_0_ = input,67,G,-; +IPL_1_ = input,56,F,-; +IPL_2_ = input,68,G,-; +RST = input,86,-,-; +RW = input,71,G,-; +SIZE_1_ = input,79,H,-; +SIZE_0_ = input,70,G,-; +VPA = input,36,-,-; +AVEC = input,92,A,-; +BGACK_030 = input,83,H,-; +BG_000 = input,29,D,-; +CLK_DIV_OUT = input,65,G,-; +CLK_EXP = input,10,B,-; +E = input,66,G,-; +FPU_CS = input,78,H,-; +IPL_030_0_ = input,8,B,-; +IPL_030_1_ = input,7,B,-; +IPL_030_2_ = input,9,B,-; +LDS_000 = input,31,D,-; +UDS_000 = input,32,D,-; +VMA = input,35,D,-; +DTACK = input,30,D,-; +RESET = input,3,B,-; +AMIGA_BUS_DATA_DIR = input,48,E,-; +AMIGA_BUS_ENABLE_LOW = input,20,C,-; +CIIN = input,47,E,-; +A_20_ = input,93,A,-; +A_21_ = input,94,A,-; +A_22_ = input,84,H,-; +A_24_ = input,19,C,-; +A_25_ = input,18,C,-; +A_26_ = input,17,C,-; +A_27_ = input,16,C,-; +A_28_ = input,15,C,-; +A_29_ = input,6,B,-; +A_30_ = input,5,B,-; +A_31_ = input,4,B,-; +DS_030 = input,98,A,-; +BERR = input,41,E,-; +nEXP_SPACE = input,14,-,-; +A0 = input,69,G,-; +DSACK1 = input,81,H,-; +RW_000 = input,80,H,-; +AS_000 = input,42,E,-; +AMIGA_ADDR_ENABLE = input,33,D,-; +AMIGA_BUS_ENABLE_HIGH = input,34,D,-; +A_23_ = input,85,H,-; +FPU_SENSE = input,91,A,-; +A1 = input,60,F,-; +A_3_ = input,44,E,-; +A_2_ = input,43,E,-; + +[GROUP ASSIGNMENT] +Layer = OFF; + +[SPACE RESERVATIONS] +Layer = OFF; + +[BACKANNOTATE NETLIST] +Delay_File = SDF; +Netlist = VHDL; +VCC_GND = Cell; + +[FITTER REPORT FORMAT] +Fitter_Options = Yes; +Pinout_Diagram = No; +Pinout_Listing = Yes; +Detailed_Block_Segment_Summary = Yes; +Input_Signal_List = Yes; +Output_Signal_List = Yes; +Bidir_Signal_List = Yes; +Node_Signal_List = Yes; +Signal_Fanout_List = Yes; +Block_Segment_Fanin_List = Yes; +Postfit_Eqn = Yes; +Page_Break = Yes; + +[POWER] +Powerlevel = Low,High; +Default = High; +Low = 8,H,G,F,E,D,C,B,A; +Type = GLB; + +[SOURCE CONSTRAINT OPTION] +Import_source_constraint = Yes; +Disable_warning_message = No; + +[TIMING ANALYZER] +Last_source=; +Last_source_type=Fmax; + +[INPUT REGISTERS] + diff --git a/Logic/68030_tk.xrf b/Logic/68030_tk.xrf new file mode 100644 index 0000000..c8d6f14 --- /dev/null +++ b/Logic/68030_tk.xrf @@ -0,0 +1,16 @@ +Signal Name Cross Reference File + +ispLEVER Classic 1.8.00.04.29.14 + +Design '68030_tk' created Wed May 13 22:59:21 2015 + + + LEGEND: '>' Functional Block Port Separator + '/' Hierarchy Path Separator + '@' Automatically Generated Node + + +Short Name Hierarchical Name +---------- ----------------- + + *** Shortened names not required for this design. *** diff --git a/Logic/BUS68030.bl0 b/Logic/BUS68030.bl0 new file mode 100644 index 0000000..fcc325f --- /dev/null +++ b/Logic/BUS68030.bl0 @@ -0,0 +1,1935 @@ +#$ DATE Wed May 13 22:59:21 2015 +#$ TOOL EDIF2BLIF version IspLever 1.0 +#$ MODULE bus68030 +#$ PINS 75 A_28_ A_27_ SIZE_1_ A_26_ A_25_ A_31_ A_24_ A_23_ IPL_030_2_ A_22_ A_21_ IPL_2_ A_20_ A_19_ FC_1_ A_18_ AS_030 A_17_ AS_000 A_16_ RW_000 A_15_ DS_030 A_14_ UDS_000 A_13_ LDS_000 A_12_ A0 A_11_ A1 A_10_ nEXP_SPACE A_9_ BERR A_8_ BG_030 A_7_ BG_000 A_6_ BGACK_030 A_5_ BGACK_000 A_4_ CLK_030 A_3_ CLK_000 A_2_ CLK_OSZI IPL_030_1_ CLK_DIV_OUT IPL_030_0_ CLK_EXP IPL_1_ FPU_CS IPL_0_ FPU_SENSE FC_0_ DSACK1 DTACK AVEC E VPA VMA RST RESET RW AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ A_30_ A_29_ +#$ NODES 695 N_310 un1_rst_dly_i_m_i_5__n sm_amiga_srsts_i_0_m2_3__un0_n N_220 sm_amiga_srsts_i_0_m2_1__un3_n pos_clk_cpu_est_11_1__n un1_rst_dly_i_m_i_6__n sm_amiga_srsts_i_0_m2_1__un1_n N_14 sm_amiga_srsts_i_0_m2_1__un0_n \ +# N_18 un1_rst_dly_i_m_i_7__n un1_amiga_bus_enable_dma_high_0_m2_0__un3_n N_22 un1_amiga_bus_enable_dma_high_0_m2_0__un1_n inst_BGACK_030_INTreg RESET_OUT_0_sqmuxa_1 un1_rst_dly_i_m_i_8__n un1_amiga_bus_enable_dma_high_0_m2_0__un0_n vcc_n_n \ +# N_205 un1_sm_amiga_7_i_m2_un3_n cpu_est_3_reg N_213 un1_rst_dly_i_m_i_2__n un1_sm_amiga_7_i_m2_un1_n inst_VMA_INTreg pos_clk_RST_DLY_5_iv_0_x2_0_ un1_sm_amiga_7_i_m2_un0_n inst_RESET_OUTreg \ +# N_105 N_98_i size_dma_0_0__un3_n gnd_n_n N_98 size_dma_0_0__un1_n un1_amiga_bus_enable_low RESET_OUT_0_sqmuxa N_105_i size_dma_0_0__un0_n \ +# un6_as_030 un1_rst_dly_i_m_2__n size_dma_0_1__un3_n un3_size G_137 N_22_i size_dma_0_1__un1_n un4_size un1_rst_dly_i_m_8__n N_33_0 \ +# size_dma_0_1__un0_n un5_ciin G_149 N_18_i ipl_030_0_0__un3_n un4_as_000 RESET_OUT_0_sqmuxa_5 N_37_0 ipl_030_0_0__un1_n un21_fpu_cs \ +# RESET_OUT_0_sqmuxa_7 N_14_i ipl_030_0_0__un0_n un22_berr G_147 N_41_0 ipl_030_0_1__un3_n un6_ds_030 G_145 N_10_i \ +# ipl_030_0_1__un1_n un6_uds_000 N_211 N_44_0 ipl_030_0_1__un0_n un6_lds_000 G_143 pos_clk_cpu_est_11_0_1__n ipl_030_0_2__un3_n cpu_est_0_ \ +# N_209 N_312_i ipl_030_0_2__un1_n cpu_est_1_ G_141 N_90_i ipl_030_0_2__un0_n inst_AS_000_INT G_139 N_88_i \ +# amiga_bus_enable_dma_high_0_un3_n SM_AMIGA_5_ un1_rst_dly_i_m_7__n N_299_i amiga_bus_enable_dma_high_0_un1_n inst_AMIGA_BUS_ENABLE_DMA_LOW un1_rst_dly_i_m_6__n N_275_0 amiga_bus_enable_dma_high_0_un0_n inst_AS_030_D0 \ +# un1_rst_dly_i_m_5__n N_274_0 bg_000_0_un3_n inst_nEXP_SPACE_D0reg un1_rst_dly_i_m_4__n N_273_i bg_000_0_un1_n inst_DS_030_D0 un1_rst_dly_i_m_3__n N_272_i \ +# bg_000_0_un0_n inst_AS_030_000_SYNC N_71_i N_270_i ds_000_dma_0_un3_n inst_BGACK_030_INT_D un1_amiga_bus_enable_low_i N_268_i ds_000_dma_0_un1_n inst_AS_000_DMA \ +# un21_fpu_cs_i N_310_i ds_000_dma_0_un0_n inst_DS_000_DMA RESET_OUT_i N_311_i as_000_dma_0_un3_n CYCLE_DMA_0_ BGACK_030_INT_i N_267_0 \ +# as_000_dma_0_un1_n CYCLE_DMA_1_ RESET_OUT_0_sqmuxa_i N_309_i as_000_dma_0_un0_n SIZE_DMA_0_ un1_rst_dly_i_3__n N_308_i a0_dma_0_un3_n SIZE_DMA_1_ \ +# un1_rst_dly_i_4__n pos_clk_un7_clk_000_pe_0_n a0_dma_0_un1_n inst_VPA_D un1_rst_dly_i_5__n N_264_0 a0_dma_0_un0_n inst_UDS_000_INT un1_rst_dly_i_6__n N_304_i \ +# dsack1_int_0_un3_n inst_LDS_000_INT un1_rst_dly_i_7__n N_303_i dsack1_int_0_un1_n inst_CLK_OUT_PRE_D un1_rst_dly_i_8__n N_186_i dsack1_int_0_un0_n inst_DTACK_D0 \ +# un1_rst_dly_i_2__n VPA_c_i as_000_int_0_un3_n inst_CLK_OUT_PRE_50 N_87_i_i N_56_0 as_000_int_0_un1_n inst_CLK_000_D1 cpu_est_i_3__n DTACK_c_i \ +# as_000_int_0_un0_n inst_CLK_000_D0 cpu_est_i_0__n N_57_0 ds_000_enable_0_un3_n inst_CLK_000_PE VPA_D_i N_97_i ds_000_enable_0_un1_n CLK_000_P_SYNC_9_ \ +# VMA_INT_i ds_000_enable_0_un0_n inst_CLK_000_NE cpu_est_i_1__n N_96_i as_030_000_sync_0_un3_n CLK_000_N_SYNC_11_ CLK_000_PE_i N_95_i as_030_000_sync_0_un1_n \ +# cpu_est_2_ BERR_i N_94_i as_030_000_sync_0_un0_n IPL_D0_0_ sm_amiga_i_4__n N_313_i lds_000_int_0_un3_n IPL_D0_1_ cpu_est_i_2__n \ +# N_136_i lds_000_int_0_un1_n IPL_D0_2_ sm_amiga_i_5__n N_81_0 lds_000_int_0_un0_n SM_AMIGA_3_ DTACK_D0_i N_116_i rw_000_dma_0_un3_n \ +# inst_CLK_000_NE_D0 sm_amiga_i_0__n N_77_i rw_000_dma_0_un1_n pos_clk_un6_bg_030_n sm_amiga_i_3__n N_73_i rw_000_dma_0_un0_n SM_AMIGA_0_ CLK_000_NE_i \ +# N_101_i uds_000_int_0_un3_n inst_AMIGA_BUS_ENABLE_DMA_HIGH sm_amiga_i_6__n uds_000_int_0_un1_n inst_DSACK1_INTreg sm_amiga_i_1__n clk_000_n_sync_i_10__n uds_000_int_0_un0_n CLK_OUT_PRE_D_i \ +# pos_clk_un9_clk_000_n_sync_i_n amiga_bus_enable_dma_low_0_un3_n pos_clk_ipl_n pos_clk_un11_clk_000_n_sync_i_n pos_clk_un14_clk_000_n_sync_0_n amiga_bus_enable_dma_low_0_un1_n pos_clk_un3_ds_030_d0_n LDS_000_i pos_clk_un22_bgack_030_int_i_n amiga_bus_enable_dma_low_0_un0_n \ +# SM_AMIGA_6_ UDS_000_i N_86_i a_15__n AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa nEXP_SPACE_D0_i N_93_i RST_DLY_0_ sm_amiga_i_2__n a_14__n \ +# RST_DLY_1_ AS_030_i N_99_i RST_DLY_2_ A1_i pos_clk_size_dma_6_0_1__n a_13__n RST_DLY_3_ CLK_000_D1_i N_100_i \ +# RST_DLY_4_ RW_000_i pos_clk_size_dma_6_0_0__n a_12__n RST_DLY_5_ CLK_030_H_i N_245_0 RST_DLY_6_ AS_000_DMA_i N_108_i \ +# a_11__n RST_DLY_7_ AS_000_i N_109_i pos_clk_un8_bg_030_n sm_amiga_i_i_7__n N_246_0 a_10__n CLK_000_P_SYNC_0_ RW_i \ +# un5_ciin_i CLK_000_P_SYNC_1_ AMIGA_BUS_ENABLE_DMA_HIGH_i N_247_0 a_9__n CLK_000_P_SYNC_2_ FPU_SENSE_i N_248_0 CLK_000_P_SYNC_3_ AS_030_D0_i \ +# CLK_000_D0_i a_8__n CLK_000_P_SYNC_4_ a_i_24__n N_249_i CLK_000_P_SYNC_5_ size_dma_i_0__n AS_030_000_SYNC_i a_7__n CLK_000_P_SYNC_6_ \ +# size_dma_i_1__n N_251_0 CLK_000_P_SYNC_7_ a_i_16__n pos_clk_un3_as_030_d0_i_n a_6__n CLK_000_P_SYNC_8_ a_i_18__n pos_clk_un5_bgack_030_int_d_i_n CLK_000_N_SYNC_0_ \ +# a_i_19__n N_75_i a_5__n CLK_000_N_SYNC_1_ a_i_31__n N_76_i CLK_000_N_SYNC_2_ a_i_29__n N_78_0 a_4__n \ +# CLK_000_N_SYNC_3_ a_i_30__n N_80_0 CLK_000_N_SYNC_4_ a_i_27__n CLK_EXP_c_i a_3__n CLK_000_N_SYNC_5_ a_i_28__n N_258_0 \ +# CLK_000_N_SYNC_6_ a_i_25__n N_283_i a_2__n CLK_000_N_SYNC_7_ a_i_26__n N_284_i CLK_000_N_SYNC_8_ UDS_000_INT_i CLK_000_N_SYNC_9_ \ +# LDS_000_INT_i N_290_i CLK_000_N_SYNC_10_ DS_030_i N_291_i pos_clk_un5_bgack_030_int_d_n N_224_i inst_RW_000_INT N_225_i N_279_i \ +# inst_RW_000_DMA N_226_i N_293_i inst_A0_DMA inst_CLK_030_H N_82_i SM_AMIGA_1_ N_83_i SM_AMIGA_4_ N_104_i \ +# N_259_0 SM_AMIGA_2_ N_103_i N_84_i pos_clk_un3_as_030_d0_n N_282_i N_115_0 inst_DS_000_ENABLE N_92_i N_85_i \ +# AS_000_INT_1_sqmuxa un6_lds_000_i N_294_i DS_000_ENABLE_1_sqmuxa_1 un6_uds_000_i N_296_i pos_clk_a0_dma_3_n un6_ds_030_i pos_clk_cpu_est_11_0_3__n pos_clk_ds_000_dma_4_n \ +# DS_000_DMA_i N_91_i N_3 un4_as_000_i N_260_0 AS_000_INT_i N_301_i un6_as_030_i pos_clk_ds_000_dma_4_0_n N_6 \ +# AMIGA_BUS_ENABLE_DMA_LOW_i N_305_i N_8 DS_030_D0_i N_306_i N_9 AS_030_c AMIGA_BUS_DATA_DIR_c_0 N_10 N_307_i \ +# N_11 AS_000_c N_12 N_13 RW_000_c N_15 N_265_0 N_16 DS_030_c N_269_i \ +# N_19 pos_clk_un24_bgack_030_int_i_0_i_n N_20 UDS_000_c N_62_0 N_21 N_276_0 N_23 LDS_000_c N_277_0 \ +# N_24 N_286_i N_25 size_c_0__n N_288_i N_289_i size_c_1__n pos_clk_un11_ds_030_d0_i_n A0_c_i size_c_i_1__n \ +# N_25_i N_32_0 N_24_i N_31_0 N_23_i N_30_0 ipl_c_i_2__n N_54_0 ipl_c_i_1__n N_53_0 \ +# ipl_c_i_0__n N_52_0 nEXP_SPACE_c_i N_55_0 N_50_0 N_3_i N_49_0 N_6_i N_48_0 N_8_i \ +# N_46_0 N_9_i N_45_0 N_12_i SM_AMIGA_i_7_ N_43_0 N_115 N_13_i pos_clk_size_dma_6_0__n a_c_16__n \ +# N_42_0 pos_clk_size_dma_6_1__n N_15_i pos_clk_cpu_est_11_3__n a_c_17__n N_40_0 G_165 N_16_i G_166 a_c_18__n \ +# N_39_0 G_167 N_19_i un6_uds_000_1 a_c_19__n N_36_0 pos_clk_un24_bgack_030_int_i_0_n N_20_i N_245 a_c_20__n \ +# N_35_0 N_246 N_21_i N_247 a_c_21__n N_34_0 N_248 BG_030_c_i N_89 a_c_22__n \ +# pos_clk_un6_bg_030_i_n N_92 pos_clk_un8_bg_030_0_n N_102 a_c_23__n N_127_i_1 N_103 N_127_i_2 N_104 a_c_24__n \ +# pos_clk_un24_bgack_030_int_i_0_i_1_n N_112 N_80_0_1 N_256 a_c_25__n N_75_i_1 N_258 N_251_0_1 a_c_26__n pos_clk_un11_ds_030_d0_i_1_n \ +# N_260 N_340_1 N_265 a_c_27__n N_340_2 N_282 N_340_3 N_71 a_c_28__n N_340_4 \ +# cpu_est_0_0_x2_0_ un5_ciin_1 pos_clk_un11_clk_000_n_sync_n a_c_29__n un5_ciin_2 N_76 un5_ciin_3 pos_clk_CYCLE_DMA_5_1_i_x2 a_c_30__n un5_ciin_4 \ +# pos_clk_CYCLE_DMA_5_0_i_x2 un5_ciin_5 pos_clk_un24_bgack_030_int_i_0_x2 a_c_31__n un5_ciin_6 pos_clk_un22_bgack_030_int_n un5_ciin_7 N_268 A0_c un5_ciin_8 \ +# N_270 un5_ciin_9 N_73 A1_c un5_ciin_10 N_75 un5_ciin_11 N_251 nEXP_SPACE_c un22_berr_1_0 \ +# un22_berr_1 un21_fpu_cs_1 N_95 BERR_c pos_clk_un6_bg_030_1_n N_94 N_131_i_1 N_288 BG_030_c N_131_i_2 \ +# N_289 N_131_i_3 N_286 BG_000DFFreg N_96_1 N_279 N_96_2 N_277 N_96_3 N_276 \ +# BGACK_000_c pos_clk_cpu_est_11_0_1_1__n N_62 pos_clk_cpu_est_11_0_2_1__n N_274 N_310_1 N_313 N_310_2 N_307 N_310_3 \ +# N_305 CLK_OSZI_c N_310_4 N_306 N_309_1 N_303 N_309_2 N_304 CLK_EXP_c N_308_1 \ +# N_301 N_308_2 N_91 RESET_OUT_0_sqmuxa_5_1 N_85 FPU_SENSE_c RESET_OUT_0_sqmuxa_7_1 N_294 RESET_OUT_0_sqmuxa_7_2 N_296 \ +# IPL_030DFF_0_reg RESET_OUT_0_sqmuxa_7_3 N_84 N_94_1 N_82 IPL_030DFF_1_reg N_95_1 N_83 N_119_i_1 N_293 \ +# IPL_030DFF_2_reg N_82_1 N_290 N_83_1 N_291 ipl_c_0__n N_296_1 N_283 N_303_1 N_284 \ +# ipl_c_1__n N_304_1 N_86 N_306_1 N_80 ipl_c_2__n N_129_i_1 N_78 N_125_i_1 N_108 \ +# N_123_i_1 N_109 DTACK_c N_115_0_1 N_100 pos_clk_cpu_est_11_0_1_3__n N_99 N_260_0_1 N_93 N_261_i_1 \ +# pos_clk_un14_clk_000_n_sync_n VPA_c N_262_i_1 pos_clk_un9_clk_000_n_sync_n N_263_i_1 N_340 pos_clk_ipl_1_n N_97 RST_c cpu_est_0_3__un3_n \ +# N_136 cpu_est_0_3__un1_n N_101 cpu_est_0_3__un0_n N_81 RW_c cpu_est_0_2__un3_n N_116 cpu_est_0_2__un1_n N_96 \ +# fc_c_0__n cpu_est_0_2__un0_n N_113 cpu_est_0_1__un3_n N_275 fc_c_1__n cpu_est_0_1__un1_n N_273 cpu_est_0_1__un0_n N_88 \ +# bgack_030_int_0_un3_n N_272 AMIGA_BUS_DATA_DIR_c bgack_030_int_0_un1_n N_299 bgack_030_int_0_un0_n N_90 vma_int_0_un3_n N_311 vma_int_0_un1_n \ +# N_312 vma_int_0_un0_n N_267 un1_as_000_i rw_000_int_0_un3_n N_264 un1_rst_dly_i_m_i_3__n rw_000_int_0_un1_n pos_clk_un7_clk_000_pe_n rw_000_int_0_un0_n \ +# N_308 un1_rst_dly_i_m_i_4__n sm_amiga_srsts_i_0_m2_3__un3_n N_309 sm_amiga_srsts_i_0_m2_3__un1_n +.model bus68030 +.inputs A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF A1.BLIF nEXP_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF \ + CLK_OSZI.BLIF FPU_SENSE.BLIF DTACK.BLIF VPA.BLIF RST.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF \ + A_26_.BLIF A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF \ + A_17_.BLIF A_16_.BLIF A_15_.BLIF A_14_.BLIF A_13_.BLIF A_12_.BLIF A_11_.BLIF A_10_.BLIF A_9_.BLIF \ + A_8_.BLIF A_7_.BLIF A_6_.BLIF A_5_.BLIF A_4_.BLIF A_3_.BLIF A_2_.BLIF IPL_1_.BLIF IPL_0_.BLIF \ + FC_0_.BLIF SIZE_1_.BLIF AS_030.BLIF AS_000.BLIF RW_000.BLIF DS_030.BLIF UDS_000.BLIF LDS_000.BLIF A0.BLIF BERR.BLIF RW.BLIF SIZE_0_.BLIF N_310.BLIF un1_rst_dly_i_m_i_5__n.BLIF sm_amiga_srsts_i_0_m2_3__un0_n.BLIF N_220.BLIF sm_amiga_srsts_i_0_m2_1__un3_n.BLIF pos_clk_cpu_est_11_1__n.BLIF un1_rst_dly_i_m_i_6__n.BLIF sm_amiga_srsts_i_0_m2_1__un1_n.BLIF \ + N_14.BLIF sm_amiga_srsts_i_0_m2_1__un0_n.BLIF N_18.BLIF un1_rst_dly_i_m_i_7__n.BLIF un1_amiga_bus_enable_dma_high_0_m2_0__un3_n.BLIF N_22.BLIF un1_amiga_bus_enable_dma_high_0_m2_0__un1_n.BLIF inst_BGACK_030_INTreg.BLIF RESET_OUT_0_sqmuxa_1.BLIF \ + un1_rst_dly_i_m_i_8__n.BLIF un1_amiga_bus_enable_dma_high_0_m2_0__un0_n.BLIF vcc_n_n.BLIF N_205.BLIF un1_sm_amiga_7_i_m2_un3_n.BLIF cpu_est_3_reg.BLIF N_213.BLIF un1_rst_dly_i_m_i_2__n.BLIF un1_sm_amiga_7_i_m2_un1_n.BLIF \ + inst_VMA_INTreg.BLIF pos_clk_RST_DLY_5_iv_0_x2_0_.BLIF un1_sm_amiga_7_i_m2_un0_n.BLIF inst_RESET_OUTreg.BLIF N_105.BLIF N_98_i.BLIF size_dma_0_0__un3_n.BLIF gnd_n_n.BLIF N_98.BLIF \ + size_dma_0_0__un1_n.BLIF un1_amiga_bus_enable_low.BLIF RESET_OUT_0_sqmuxa.BLIF N_105_i.BLIF size_dma_0_0__un0_n.BLIF un6_as_030.BLIF un1_rst_dly_i_m_2__n.BLIF size_dma_0_1__un3_n.BLIF un3_size.BLIF \ + G_137.BLIF N_22_i.BLIF size_dma_0_1__un1_n.BLIF un4_size.BLIF un1_rst_dly_i_m_8__n.BLIF N_33_0.BLIF size_dma_0_1__un0_n.BLIF un5_ciin.BLIF G_149.BLIF \ + N_18_i.BLIF ipl_030_0_0__un3_n.BLIF un4_as_000.BLIF RESET_OUT_0_sqmuxa_5.BLIF N_37_0.BLIF ipl_030_0_0__un1_n.BLIF un21_fpu_cs.BLIF RESET_OUT_0_sqmuxa_7.BLIF N_14_i.BLIF \ + ipl_030_0_0__un0_n.BLIF un22_berr.BLIF G_147.BLIF N_41_0.BLIF ipl_030_0_1__un3_n.BLIF un6_ds_030.BLIF G_145.BLIF N_10_i.BLIF ipl_030_0_1__un1_n.BLIF \ + un6_uds_000.BLIF N_211.BLIF N_44_0.BLIF ipl_030_0_1__un0_n.BLIF un6_lds_000.BLIF G_143.BLIF pos_clk_cpu_est_11_0_1__n.BLIF ipl_030_0_2__un3_n.BLIF cpu_est_0_.BLIF \ + N_209.BLIF N_312_i.BLIF ipl_030_0_2__un1_n.BLIF cpu_est_1_.BLIF G_141.BLIF N_90_i.BLIF ipl_030_0_2__un0_n.BLIF inst_AS_000_INT.BLIF G_139.BLIF \ + N_88_i.BLIF amiga_bus_enable_dma_high_0_un3_n.BLIF SM_AMIGA_5_.BLIF un1_rst_dly_i_m_7__n.BLIF N_299_i.BLIF amiga_bus_enable_dma_high_0_un1_n.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF un1_rst_dly_i_m_6__n.BLIF N_275_0.BLIF \ + amiga_bus_enable_dma_high_0_un0_n.BLIF inst_AS_030_D0.BLIF un1_rst_dly_i_m_5__n.BLIF N_274_0.BLIF bg_000_0_un3_n.BLIF inst_nEXP_SPACE_D0reg.BLIF un1_rst_dly_i_m_4__n.BLIF N_273_i.BLIF bg_000_0_un1_n.BLIF \ + inst_DS_030_D0.BLIF un1_rst_dly_i_m_3__n.BLIF N_272_i.BLIF bg_000_0_un0_n.BLIF inst_AS_030_000_SYNC.BLIF N_71_i.BLIF N_270_i.BLIF ds_000_dma_0_un3_n.BLIF inst_BGACK_030_INT_D.BLIF \ + un1_amiga_bus_enable_low_i.BLIF N_268_i.BLIF ds_000_dma_0_un1_n.BLIF inst_AS_000_DMA.BLIF un21_fpu_cs_i.BLIF N_310_i.BLIF ds_000_dma_0_un0_n.BLIF inst_DS_000_DMA.BLIF RESET_OUT_i.BLIF \ + N_311_i.BLIF as_000_dma_0_un3_n.BLIF CYCLE_DMA_0_.BLIF BGACK_030_INT_i.BLIF N_267_0.BLIF as_000_dma_0_un1_n.BLIF CYCLE_DMA_1_.BLIF RESET_OUT_0_sqmuxa_i.BLIF N_309_i.BLIF \ + as_000_dma_0_un0_n.BLIF SIZE_DMA_0_.BLIF un1_rst_dly_i_3__n.BLIF N_308_i.BLIF a0_dma_0_un3_n.BLIF SIZE_DMA_1_.BLIF un1_rst_dly_i_4__n.BLIF pos_clk_un7_clk_000_pe_0_n.BLIF a0_dma_0_un1_n.BLIF \ + inst_VPA_D.BLIF un1_rst_dly_i_5__n.BLIF N_264_0.BLIF a0_dma_0_un0_n.BLIF inst_UDS_000_INT.BLIF un1_rst_dly_i_6__n.BLIF N_304_i.BLIF dsack1_int_0_un3_n.BLIF inst_LDS_000_INT.BLIF \ + un1_rst_dly_i_7__n.BLIF N_303_i.BLIF dsack1_int_0_un1_n.BLIF inst_CLK_OUT_PRE_D.BLIF un1_rst_dly_i_8__n.BLIF N_186_i.BLIF dsack1_int_0_un0_n.BLIF inst_DTACK_D0.BLIF un1_rst_dly_i_2__n.BLIF \ + VPA_c_i.BLIF as_000_int_0_un3_n.BLIF inst_CLK_OUT_PRE_50.BLIF N_87_i_i.BLIF N_56_0.BLIF as_000_int_0_un1_n.BLIF inst_CLK_000_D1.BLIF cpu_est_i_3__n.BLIF DTACK_c_i.BLIF \ + as_000_int_0_un0_n.BLIF inst_CLK_000_D0.BLIF cpu_est_i_0__n.BLIF N_57_0.BLIF ds_000_enable_0_un3_n.BLIF inst_CLK_000_PE.BLIF VPA_D_i.BLIF N_97_i.BLIF ds_000_enable_0_un1_n.BLIF \ + CLK_000_P_SYNC_9_.BLIF VMA_INT_i.BLIF ds_000_enable_0_un0_n.BLIF inst_CLK_000_NE.BLIF cpu_est_i_1__n.BLIF N_96_i.BLIF as_030_000_sync_0_un3_n.BLIF CLK_000_N_SYNC_11_.BLIF CLK_000_PE_i.BLIF \ + N_95_i.BLIF as_030_000_sync_0_un1_n.BLIF cpu_est_2_.BLIF BERR_i.BLIF N_94_i.BLIF as_030_000_sync_0_un0_n.BLIF IPL_D0_0_.BLIF sm_amiga_i_4__n.BLIF N_313_i.BLIF \ + lds_000_int_0_un3_n.BLIF IPL_D0_1_.BLIF cpu_est_i_2__n.BLIF N_136_i.BLIF lds_000_int_0_un1_n.BLIF IPL_D0_2_.BLIF sm_amiga_i_5__n.BLIF N_81_0.BLIF lds_000_int_0_un0_n.BLIF \ + SM_AMIGA_3_.BLIF DTACK_D0_i.BLIF N_116_i.BLIF rw_000_dma_0_un3_n.BLIF inst_CLK_000_NE_D0.BLIF sm_amiga_i_0__n.BLIF N_77_i.BLIF rw_000_dma_0_un1_n.BLIF pos_clk_un6_bg_030_n.BLIF \ + sm_amiga_i_3__n.BLIF N_73_i.BLIF rw_000_dma_0_un0_n.BLIF SM_AMIGA_0_.BLIF CLK_000_NE_i.BLIF N_101_i.BLIF uds_000_int_0_un3_n.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF sm_amiga_i_6__n.BLIF \ + uds_000_int_0_un1_n.BLIF inst_DSACK1_INTreg.BLIF sm_amiga_i_1__n.BLIF clk_000_n_sync_i_10__n.BLIF uds_000_int_0_un0_n.BLIF CLK_OUT_PRE_D_i.BLIF pos_clk_un9_clk_000_n_sync_i_n.BLIF amiga_bus_enable_dma_low_0_un3_n.BLIF pos_clk_ipl_n.BLIF \ + pos_clk_un11_clk_000_n_sync_i_n.BLIF pos_clk_un14_clk_000_n_sync_0_n.BLIF amiga_bus_enable_dma_low_0_un1_n.BLIF pos_clk_un3_ds_030_d0_n.BLIF LDS_000_i.BLIF pos_clk_un22_bgack_030_int_i_n.BLIF amiga_bus_enable_dma_low_0_un0_n.BLIF SM_AMIGA_6_.BLIF UDS_000_i.BLIF \ + N_86_i.BLIF a_15__n.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa.BLIF nEXP_SPACE_D0_i.BLIF N_93_i.BLIF RST_DLY_0_.BLIF sm_amiga_i_2__n.BLIF a_14__n.BLIF RST_DLY_1_.BLIF \ + AS_030_i.BLIF N_99_i.BLIF RST_DLY_2_.BLIF A1_i.BLIF pos_clk_size_dma_6_0_1__n.BLIF a_13__n.BLIF RST_DLY_3_.BLIF CLK_000_D1_i.BLIF N_100_i.BLIF \ + RST_DLY_4_.BLIF RW_000_i.BLIF pos_clk_size_dma_6_0_0__n.BLIF a_12__n.BLIF RST_DLY_5_.BLIF CLK_030_H_i.BLIF N_245_0.BLIF RST_DLY_6_.BLIF AS_000_DMA_i.BLIF \ + N_108_i.BLIF a_11__n.BLIF RST_DLY_7_.BLIF AS_000_i.BLIF N_109_i.BLIF pos_clk_un8_bg_030_n.BLIF sm_amiga_i_i_7__n.BLIF N_246_0.BLIF a_10__n.BLIF \ + CLK_000_P_SYNC_0_.BLIF RW_i.BLIF un5_ciin_i.BLIF CLK_000_P_SYNC_1_.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF N_247_0.BLIF a_9__n.BLIF CLK_000_P_SYNC_2_.BLIF FPU_SENSE_i.BLIF \ + N_248_0.BLIF CLK_000_P_SYNC_3_.BLIF AS_030_D0_i.BLIF CLK_000_D0_i.BLIF a_8__n.BLIF CLK_000_P_SYNC_4_.BLIF a_i_24__n.BLIF N_249_i.BLIF CLK_000_P_SYNC_5_.BLIF \ + size_dma_i_0__n.BLIF AS_030_000_SYNC_i.BLIF a_7__n.BLIF CLK_000_P_SYNC_6_.BLIF size_dma_i_1__n.BLIF N_251_0.BLIF CLK_000_P_SYNC_7_.BLIF a_i_16__n.BLIF pos_clk_un3_as_030_d0_i_n.BLIF \ + a_6__n.BLIF CLK_000_P_SYNC_8_.BLIF a_i_18__n.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF CLK_000_N_SYNC_0_.BLIF a_i_19__n.BLIF N_75_i.BLIF a_5__n.BLIF CLK_000_N_SYNC_1_.BLIF \ + a_i_31__n.BLIF N_76_i.BLIF CLK_000_N_SYNC_2_.BLIF a_i_29__n.BLIF N_78_0.BLIF a_4__n.BLIF CLK_000_N_SYNC_3_.BLIF a_i_30__n.BLIF N_80_0.BLIF \ + CLK_000_N_SYNC_4_.BLIF a_i_27__n.BLIF CLK_EXP_c_i.BLIF a_3__n.BLIF CLK_000_N_SYNC_5_.BLIF a_i_28__n.BLIF N_258_0.BLIF CLK_000_N_SYNC_6_.BLIF a_i_25__n.BLIF \ + N_283_i.BLIF a_2__n.BLIF CLK_000_N_SYNC_7_.BLIF a_i_26__n.BLIF N_284_i.BLIF CLK_000_N_SYNC_8_.BLIF UDS_000_INT_i.BLIF CLK_000_N_SYNC_9_.BLIF LDS_000_INT_i.BLIF \ + N_290_i.BLIF CLK_000_N_SYNC_10_.BLIF DS_030_i.BLIF N_291_i.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF N_224_i.BLIF inst_RW_000_INT.BLIF N_225_i.BLIF N_279_i.BLIF \ + inst_RW_000_DMA.BLIF N_226_i.BLIF N_293_i.BLIF inst_A0_DMA.BLIF inst_CLK_030_H.BLIF N_82_i.BLIF SM_AMIGA_1_.BLIF N_83_i.BLIF SM_AMIGA_4_.BLIF \ + N_104_i.BLIF N_259_0.BLIF SM_AMIGA_2_.BLIF N_103_i.BLIF N_84_i.BLIF pos_clk_un3_as_030_d0_n.BLIF N_282_i.BLIF N_115_0.BLIF inst_DS_000_ENABLE.BLIF \ + N_92_i.BLIF N_85_i.BLIF AS_000_INT_1_sqmuxa.BLIF un6_lds_000_i.BLIF N_294_i.BLIF DS_000_ENABLE_1_sqmuxa_1.BLIF un6_uds_000_i.BLIF N_296_i.BLIF pos_clk_a0_dma_3_n.BLIF \ + un6_ds_030_i.BLIF pos_clk_cpu_est_11_0_3__n.BLIF pos_clk_ds_000_dma_4_n.BLIF DS_000_DMA_i.BLIF N_91_i.BLIF N_3.BLIF un4_as_000_i.BLIF N_260_0.BLIF AS_000_INT_i.BLIF \ + N_301_i.BLIF un6_as_030_i.BLIF pos_clk_ds_000_dma_4_0_n.BLIF N_6.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF N_305_i.BLIF N_8.BLIF DS_030_D0_i.BLIF N_306_i.BLIF \ + N_9.BLIF AS_030_c.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF N_10.BLIF N_307_i.BLIF N_11.BLIF AS_000_c.BLIF N_12.BLIF N_13.BLIF \ + RW_000_c.BLIF N_15.BLIF N_265_0.BLIF N_16.BLIF DS_030_c.BLIF N_269_i.BLIF N_19.BLIF pos_clk_un24_bgack_030_int_i_0_i_n.BLIF N_20.BLIF \ + UDS_000_c.BLIF N_62_0.BLIF N_21.BLIF N_276_0.BLIF N_23.BLIF LDS_000_c.BLIF N_277_0.BLIF N_24.BLIF N_286_i.BLIF \ + N_25.BLIF size_c_0__n.BLIF N_288_i.BLIF N_289_i.BLIF size_c_1__n.BLIF pos_clk_un11_ds_030_d0_i_n.BLIF A0_c_i.BLIF size_c_i_1__n.BLIF N_25_i.BLIF \ + N_32_0.BLIF N_24_i.BLIF N_31_0.BLIF N_23_i.BLIF N_30_0.BLIF ipl_c_i_2__n.BLIF N_54_0.BLIF ipl_c_i_1__n.BLIF N_53_0.BLIF \ + ipl_c_i_0__n.BLIF N_52_0.BLIF nEXP_SPACE_c_i.BLIF N_55_0.BLIF N_50_0.BLIF N_3_i.BLIF N_49_0.BLIF N_6_i.BLIF N_48_0.BLIF \ + N_8_i.BLIF N_46_0.BLIF N_9_i.BLIF N_45_0.BLIF N_12_i.BLIF SM_AMIGA_i_7_.BLIF N_43_0.BLIF N_115.BLIF N_13_i.BLIF \ + pos_clk_size_dma_6_0__n.BLIF a_c_16__n.BLIF N_42_0.BLIF pos_clk_size_dma_6_1__n.BLIF N_15_i.BLIF pos_clk_cpu_est_11_3__n.BLIF a_c_17__n.BLIF N_40_0.BLIF G_165.BLIF \ + N_16_i.BLIF G_166.BLIF a_c_18__n.BLIF N_39_0.BLIF G_167.BLIF N_19_i.BLIF un6_uds_000_1.BLIF a_c_19__n.BLIF N_36_0.BLIF \ + pos_clk_un24_bgack_030_int_i_0_n.BLIF N_20_i.BLIF N_245.BLIF a_c_20__n.BLIF N_35_0.BLIF N_246.BLIF N_21_i.BLIF N_247.BLIF a_c_21__n.BLIF \ + N_34_0.BLIF N_248.BLIF BG_030_c_i.BLIF N_89.BLIF a_c_22__n.BLIF pos_clk_un6_bg_030_i_n.BLIF N_92.BLIF pos_clk_un8_bg_030_0_n.BLIF N_102.BLIF \ + a_c_23__n.BLIF N_127_i_1.BLIF N_103.BLIF N_127_i_2.BLIF N_104.BLIF a_c_24__n.BLIF pos_clk_un24_bgack_030_int_i_0_i_1_n.BLIF N_112.BLIF N_80_0_1.BLIF \ + N_256.BLIF a_c_25__n.BLIF N_75_i_1.BLIF N_258.BLIF N_251_0_1.BLIF a_c_26__n.BLIF pos_clk_un11_ds_030_d0_i_1_n.BLIF N_260.BLIF N_340_1.BLIF \ + N_265.BLIF a_c_27__n.BLIF N_340_2.BLIF N_282.BLIF N_340_3.BLIF N_71.BLIF a_c_28__n.BLIF N_340_4.BLIF cpu_est_0_0_x2_0_.BLIF \ + un5_ciin_1.BLIF pos_clk_un11_clk_000_n_sync_n.BLIF a_c_29__n.BLIF un5_ciin_2.BLIF N_76.BLIF un5_ciin_3.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.BLIF a_c_30__n.BLIF un5_ciin_4.BLIF \ + pos_clk_CYCLE_DMA_5_0_i_x2.BLIF un5_ciin_5.BLIF pos_clk_un24_bgack_030_int_i_0_x2.BLIF a_c_31__n.BLIF un5_ciin_6.BLIF pos_clk_un22_bgack_030_int_n.BLIF un5_ciin_7.BLIF N_268.BLIF A0_c.BLIF \ + un5_ciin_8.BLIF N_270.BLIF un5_ciin_9.BLIF N_73.BLIF A1_c.BLIF un5_ciin_10.BLIF N_75.BLIF un5_ciin_11.BLIF N_251.BLIF \ + nEXP_SPACE_c.BLIF un22_berr_1_0.BLIF un22_berr_1.BLIF un21_fpu_cs_1.BLIF N_95.BLIF BERR_c.BLIF pos_clk_un6_bg_030_1_n.BLIF N_94.BLIF N_131_i_1.BLIF \ + N_288.BLIF BG_030_c.BLIF N_131_i_2.BLIF N_289.BLIF N_131_i_3.BLIF N_286.BLIF BG_000DFFreg.BLIF N_96_1.BLIF N_279.BLIF \ + N_96_2.BLIF N_277.BLIF N_96_3.BLIF N_276.BLIF BGACK_000_c.BLIF pos_clk_cpu_est_11_0_1_1__n.BLIF N_62.BLIF pos_clk_cpu_est_11_0_2_1__n.BLIF N_274.BLIF \ + N_310_1.BLIF N_313.BLIF N_310_2.BLIF N_307.BLIF N_310_3.BLIF N_305.BLIF CLK_OSZI_c.BLIF N_310_4.BLIF N_306.BLIF \ + N_309_1.BLIF N_303.BLIF N_309_2.BLIF N_304.BLIF CLK_EXP_c.BLIF N_308_1.BLIF N_301.BLIF N_308_2.BLIF N_91.BLIF \ + RESET_OUT_0_sqmuxa_5_1.BLIF N_85.BLIF FPU_SENSE_c.BLIF RESET_OUT_0_sqmuxa_7_1.BLIF N_294.BLIF RESET_OUT_0_sqmuxa_7_2.BLIF N_296.BLIF IPL_030DFF_0_reg.BLIF RESET_OUT_0_sqmuxa_7_3.BLIF \ + N_84.BLIF N_94_1.BLIF N_82.BLIF IPL_030DFF_1_reg.BLIF N_95_1.BLIF N_83.BLIF N_119_i_1.BLIF N_293.BLIF IPL_030DFF_2_reg.BLIF \ + N_82_1.BLIF N_290.BLIF N_83_1.BLIF N_291.BLIF ipl_c_0__n.BLIF N_296_1.BLIF N_283.BLIF N_303_1.BLIF N_284.BLIF \ + ipl_c_1__n.BLIF N_304_1.BLIF N_86.BLIF N_306_1.BLIF N_80.BLIF ipl_c_2__n.BLIF N_129_i_1.BLIF N_78.BLIF N_125_i_1.BLIF \ + N_108.BLIF N_123_i_1.BLIF N_109.BLIF DTACK_c.BLIF N_115_0_1.BLIF N_100.BLIF pos_clk_cpu_est_11_0_1_3__n.BLIF N_99.BLIF N_260_0_1.BLIF \ + N_93.BLIF N_261_i_1.BLIF pos_clk_un14_clk_000_n_sync_n.BLIF VPA_c.BLIF N_262_i_1.BLIF pos_clk_un9_clk_000_n_sync_n.BLIF N_263_i_1.BLIF N_340.BLIF pos_clk_ipl_1_n.BLIF \ + N_97.BLIF RST_c.BLIF cpu_est_0_3__un3_n.BLIF N_136.BLIF cpu_est_0_3__un1_n.BLIF N_101.BLIF cpu_est_0_3__un0_n.BLIF N_81.BLIF RW_c.BLIF \ + cpu_est_0_2__un3_n.BLIF N_116.BLIF cpu_est_0_2__un1_n.BLIF N_96.BLIF fc_c_0__n.BLIF cpu_est_0_2__un0_n.BLIF N_113.BLIF cpu_est_0_1__un3_n.BLIF N_275.BLIF \ + fc_c_1__n.BLIF cpu_est_0_1__un1_n.BLIF N_273.BLIF cpu_est_0_1__un0_n.BLIF N_88.BLIF bgack_030_int_0_un3_n.BLIF N_272.BLIF AMIGA_BUS_DATA_DIR_c.BLIF bgack_030_int_0_un1_n.BLIF \ + N_299.BLIF bgack_030_int_0_un0_n.BLIF N_90.BLIF vma_int_0_un3_n.BLIF N_311.BLIF vma_int_0_un1_n.BLIF N_312.BLIF vma_int_0_un0_n.BLIF N_267.BLIF \ + un1_as_000_i.BLIF rw_000_int_0_un3_n.BLIF N_264.BLIF un1_rst_dly_i_m_i_3__n.BLIF rw_000_int_0_un1_n.BLIF pos_clk_un7_clk_000_pe_n.BLIF rw_000_int_0_un0_n.BLIF N_308.BLIF un1_rst_dly_i_m_i_4__n.BLIF \ + sm_amiga_srsts_i_0_m2_3__un3_n.BLIF N_309.BLIF sm_amiga_srsts_i_0_m2_3__un1_n.BLIF AS_030.PIN AS_000.PIN RW_000.PIN DS_030.PIN UDS_000.PIN LDS_000.PIN \ + SIZE_0_.PIN SIZE_1_.PIN A0.PIN BERR.PIN RW.PIN +.outputs IPL_030_2_ BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 AVEC E VMA RESET \ + AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ IPL_030DFF_2_reg.D IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C \ + IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_4_.D \ + SM_AMIGA_4_.C SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C cpu_est_0_.D cpu_est_0_.C \ + cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_reg.D cpu_est_3_reg.C IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C CLK_000_N_SYNC_9_.D \ + CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C \ + RST_DLY_3_.D RST_DLY_3_.C RST_DLY_4_.D RST_DLY_4_.C RST_DLY_5_.D RST_DLY_5_.C RST_DLY_6_.D RST_DLY_6_.C RST_DLY_7_.D RST_DLY_7_.C CYCLE_DMA_0_.D \ + CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_6_.C \ + CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.D \ + CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C \ + CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.D \ + CLK_000_P_SYNC_4_.C inst_CLK_030_H.D inst_CLK_030_H.C inst_RESET_OUTreg.D inst_RESET_OUTreg.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C inst_UDS_000_INT.D inst_UDS_000_INT.C inst_RW_000_DMA.D inst_RW_000_DMA.C \ + inst_RW_000_INT.D inst_RW_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_000_INT.D inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C inst_A0_DMA.D \ + inst_A0_DMA.C inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D inst_DS_000_DMA.C inst_DS_030_D0.D inst_DS_030_D0.C inst_AS_030_D0.D inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.D inst_nEXP_SPACE_D0reg.C \ + inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D inst_DTACK_D0.C inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C BG_000DFFreg.D BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D \ + inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_VMA_INTreg.D inst_VMA_INTreg.C inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_CLK_000_PE.D inst_CLK_000_PE.C inst_CLK_000_NE.D inst_CLK_000_NE.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C \ + inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C inst_CLK_000_D0.D inst_CLK_000_D0.C pos_clk_RST_DLY_5_iv_0_x2_0_.X1 pos_clk_RST_DLY_5_iv_0_x2_0_.X2 cpu_est_0_0_x2_0_.X1 \ + cpu_est_0_0_x2_0_.X2 pos_clk_CYCLE_DMA_5_1_i_x2.X1 pos_clk_CYCLE_DMA_5_1_i_x2.X2 pos_clk_CYCLE_DMA_5_0_i_x2.X1 pos_clk_CYCLE_DMA_5_0_i_x2.X2 pos_clk_un24_bgack_030_int_i_0_x2.X1 pos_clk_un24_bgack_030_int_i_0_x2.X2 G_167.X1 G_167.X2 G_165.X1 G_165.X2 \ + G_166.X1 G_166.X2 G_141.X1 G_141.X2 G_139.X1 G_139.X2 G_137.X1 G_137.X2 G_149.X1 G_149.X2 G_147.X1 \ + G_147.X2 G_145.X1 G_145.X2 G_143.X1 G_143.X2 SIZE_1_ AS_030 AS_000 RW_000 DS_030 UDS_000 LDS_000 A0 BERR RW SIZE_0_ N_310 un1_rst_dly_i_m_i_5__n sm_amiga_srsts_i_0_m2_3__un0_n N_220 sm_amiga_srsts_i_0_m2_1__un3_n pos_clk_cpu_est_11_1__n \ + un1_rst_dly_i_m_i_6__n sm_amiga_srsts_i_0_m2_1__un1_n N_14 sm_amiga_srsts_i_0_m2_1__un0_n N_18 un1_rst_dly_i_m_i_7__n un1_amiga_bus_enable_dma_high_0_m2_0__un3_n N_22 un1_amiga_bus_enable_dma_high_0_m2_0__un1_n RESET_OUT_0_sqmuxa_1 un1_rst_dly_i_m_i_8__n \ + un1_amiga_bus_enable_dma_high_0_m2_0__un0_n vcc_n_n N_205 un1_sm_amiga_7_i_m2_un3_n N_213 un1_rst_dly_i_m_i_2__n un1_sm_amiga_7_i_m2_un1_n un1_sm_amiga_7_i_m2_un0_n N_105 N_98_i size_dma_0_0__un3_n \ + gnd_n_n N_98 size_dma_0_0__un1_n un1_amiga_bus_enable_low RESET_OUT_0_sqmuxa N_105_i size_dma_0_0__un0_n un6_as_030 un1_rst_dly_i_m_2__n size_dma_0_1__un3_n un3_size \ + N_22_i size_dma_0_1__un1_n un4_size un1_rst_dly_i_m_8__n N_33_0 size_dma_0_1__un0_n un5_ciin N_18_i ipl_030_0_0__un3_n un4_as_000 RESET_OUT_0_sqmuxa_5 \ + N_37_0 ipl_030_0_0__un1_n un21_fpu_cs RESET_OUT_0_sqmuxa_7 N_14_i ipl_030_0_0__un0_n un22_berr N_41_0 ipl_030_0_1__un3_n un6_ds_030 N_10_i \ + ipl_030_0_1__un1_n un6_uds_000 N_211 N_44_0 ipl_030_0_1__un0_n un6_lds_000 pos_clk_cpu_est_11_0_1__n ipl_030_0_2__un3_n N_209 N_312_i ipl_030_0_2__un1_n \ + N_90_i ipl_030_0_2__un0_n N_88_i amiga_bus_enable_dma_high_0_un3_n un1_rst_dly_i_m_7__n N_299_i amiga_bus_enable_dma_high_0_un1_n un1_rst_dly_i_m_6__n N_275_0 amiga_bus_enable_dma_high_0_un0_n un1_rst_dly_i_m_5__n \ + N_274_0 bg_000_0_un3_n un1_rst_dly_i_m_4__n N_273_i bg_000_0_un1_n un1_rst_dly_i_m_3__n N_272_i bg_000_0_un0_n N_71_i N_270_i ds_000_dma_0_un3_n \ + un1_amiga_bus_enable_low_i N_268_i ds_000_dma_0_un1_n un21_fpu_cs_i N_310_i ds_000_dma_0_un0_n RESET_OUT_i N_311_i as_000_dma_0_un3_n BGACK_030_INT_i N_267_0 \ + as_000_dma_0_un1_n RESET_OUT_0_sqmuxa_i N_309_i as_000_dma_0_un0_n un1_rst_dly_i_3__n N_308_i a0_dma_0_un3_n un1_rst_dly_i_4__n pos_clk_un7_clk_000_pe_0_n a0_dma_0_un1_n un1_rst_dly_i_5__n \ + N_264_0 a0_dma_0_un0_n un1_rst_dly_i_6__n N_304_i dsack1_int_0_un3_n un1_rst_dly_i_7__n N_303_i dsack1_int_0_un1_n un1_rst_dly_i_8__n N_186_i dsack1_int_0_un0_n \ + un1_rst_dly_i_2__n VPA_c_i as_000_int_0_un3_n N_87_i_i N_56_0 as_000_int_0_un1_n cpu_est_i_3__n DTACK_c_i as_000_int_0_un0_n cpu_est_i_0__n N_57_0 \ + ds_000_enable_0_un3_n VPA_D_i N_97_i ds_000_enable_0_un1_n VMA_INT_i ds_000_enable_0_un0_n cpu_est_i_1__n N_96_i as_030_000_sync_0_un3_n CLK_000_PE_i N_95_i \ + as_030_000_sync_0_un1_n BERR_i N_94_i as_030_000_sync_0_un0_n sm_amiga_i_4__n N_313_i lds_000_int_0_un3_n cpu_est_i_2__n N_136_i lds_000_int_0_un1_n sm_amiga_i_5__n \ + N_81_0 lds_000_int_0_un0_n DTACK_D0_i N_116_i rw_000_dma_0_un3_n sm_amiga_i_0__n N_77_i rw_000_dma_0_un1_n pos_clk_un6_bg_030_n sm_amiga_i_3__n N_73_i \ + rw_000_dma_0_un0_n CLK_000_NE_i N_101_i uds_000_int_0_un3_n sm_amiga_i_6__n uds_000_int_0_un1_n sm_amiga_i_1__n clk_000_n_sync_i_10__n uds_000_int_0_un0_n CLK_OUT_PRE_D_i pos_clk_un9_clk_000_n_sync_i_n \ + amiga_bus_enable_dma_low_0_un3_n pos_clk_ipl_n pos_clk_un11_clk_000_n_sync_i_n pos_clk_un14_clk_000_n_sync_0_n amiga_bus_enable_dma_low_0_un1_n pos_clk_un3_ds_030_d0_n LDS_000_i pos_clk_un22_bgack_030_int_i_n amiga_bus_enable_dma_low_0_un0_n UDS_000_i N_86_i \ + a_15__n AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa nEXP_SPACE_D0_i N_93_i sm_amiga_i_2__n a_14__n AS_030_i N_99_i A1_i pos_clk_size_dma_6_0_1__n a_13__n \ + CLK_000_D1_i N_100_i RW_000_i pos_clk_size_dma_6_0_0__n a_12__n CLK_030_H_i N_245_0 AS_000_DMA_i N_108_i a_11__n AS_000_i \ + N_109_i pos_clk_un8_bg_030_n sm_amiga_i_i_7__n N_246_0 a_10__n RW_i un5_ciin_i AMIGA_BUS_ENABLE_DMA_HIGH_i N_247_0 a_9__n FPU_SENSE_i \ + N_248_0 AS_030_D0_i CLK_000_D0_i a_8__n a_i_24__n N_249_i size_dma_i_0__n AS_030_000_SYNC_i a_7__n size_dma_i_1__n N_251_0 \ + a_i_16__n pos_clk_un3_as_030_d0_i_n a_6__n a_i_18__n pos_clk_un5_bgack_030_int_d_i_n a_i_19__n N_75_i a_5__n a_i_31__n N_76_i a_i_29__n \ + N_78_0 a_4__n a_i_30__n N_80_0 a_i_27__n CLK_EXP_c_i a_3__n a_i_28__n N_258_0 a_i_25__n N_283_i \ + a_2__n a_i_26__n N_284_i UDS_000_INT_i LDS_000_INT_i N_290_i DS_030_i N_291_i pos_clk_un5_bgack_030_int_d_n N_224_i N_225_i \ + N_279_i N_226_i N_293_i N_82_i N_83_i N_104_i N_259_0 N_103_i N_84_i pos_clk_un3_as_030_d0_n N_282_i \ + N_115_0 N_92_i N_85_i AS_000_INT_1_sqmuxa un6_lds_000_i N_294_i DS_000_ENABLE_1_sqmuxa_1 un6_uds_000_i N_296_i pos_clk_a0_dma_3_n un6_ds_030_i \ + pos_clk_cpu_est_11_0_3__n pos_clk_ds_000_dma_4_n DS_000_DMA_i N_91_i N_3 un4_as_000_i N_260_0 AS_000_INT_i N_301_i un6_as_030_i pos_clk_ds_000_dma_4_0_n \ + N_6 AMIGA_BUS_ENABLE_DMA_LOW_i N_305_i N_8 DS_030_D0_i N_306_i N_9 AS_030_c AMIGA_BUS_DATA_DIR_c_0 N_10 N_307_i \ + N_11 AS_000_c N_12 N_13 RW_000_c N_15 N_265_0 N_16 DS_030_c N_269_i N_19 \ + pos_clk_un24_bgack_030_int_i_0_i_n N_20 UDS_000_c N_62_0 N_21 N_276_0 N_23 LDS_000_c N_277_0 N_24 N_286_i \ + N_25 size_c_0__n N_288_i N_289_i size_c_1__n pos_clk_un11_ds_030_d0_i_n A0_c_i size_c_i_1__n N_25_i N_32_0 N_24_i \ + N_31_0 N_23_i N_30_0 ipl_c_i_2__n N_54_0 ipl_c_i_1__n N_53_0 ipl_c_i_0__n N_52_0 nEXP_SPACE_c_i N_55_0 \ + N_50_0 N_3_i N_49_0 N_6_i N_48_0 N_8_i N_46_0 N_9_i N_45_0 N_12_i N_43_0 \ + N_115 N_13_i pos_clk_size_dma_6_0__n a_c_16__n N_42_0 pos_clk_size_dma_6_1__n N_15_i pos_clk_cpu_est_11_3__n a_c_17__n N_40_0 N_16_i \ + a_c_18__n N_39_0 N_19_i un6_uds_000_1 a_c_19__n N_36_0 pos_clk_un24_bgack_030_int_i_0_n N_20_i N_245 a_c_20__n N_35_0 \ + N_246 N_21_i N_247 a_c_21__n N_34_0 N_248 BG_030_c_i N_89 a_c_22__n pos_clk_un6_bg_030_i_n N_92 \ + pos_clk_un8_bg_030_0_n N_102 a_c_23__n N_127_i_1 N_103 N_127_i_2 N_104 a_c_24__n pos_clk_un24_bgack_030_int_i_0_i_1_n N_112 N_80_0_1 \ + N_256 a_c_25__n N_75_i_1 N_258 N_251_0_1 a_c_26__n pos_clk_un11_ds_030_d0_i_1_n N_260 N_340_1 N_265 a_c_27__n \ + N_340_2 N_282 N_340_3 N_71 a_c_28__n N_340_4 un5_ciin_1 pos_clk_un11_clk_000_n_sync_n a_c_29__n un5_ciin_2 N_76 \ + un5_ciin_3 a_c_30__n un5_ciin_4 un5_ciin_5 a_c_31__n un5_ciin_6 pos_clk_un22_bgack_030_int_n un5_ciin_7 N_268 A0_c un5_ciin_8 \ + N_270 un5_ciin_9 N_73 A1_c un5_ciin_10 N_75 un5_ciin_11 N_251 nEXP_SPACE_c un22_berr_1_0 un22_berr_1 \ + un21_fpu_cs_1 N_95 BERR_c pos_clk_un6_bg_030_1_n N_94 N_131_i_1 N_288 BG_030_c N_131_i_2 N_289 N_131_i_3 \ + N_286 N_96_1 N_279 N_96_2 N_277 N_96_3 N_276 BGACK_000_c pos_clk_cpu_est_11_0_1_1__n N_62 pos_clk_cpu_est_11_0_2_1__n \ + N_274 N_310_1 N_313 N_310_2 N_307 N_310_3 N_305 CLK_OSZI_c N_310_4 N_306 N_309_1 \ + N_303 N_309_2 N_304 CLK_EXP_c N_308_1 N_301 N_308_2 N_91 RESET_OUT_0_sqmuxa_5_1 N_85 FPU_SENSE_c \ + RESET_OUT_0_sqmuxa_7_1 N_294 RESET_OUT_0_sqmuxa_7_2 N_296 RESET_OUT_0_sqmuxa_7_3 N_84 N_94_1 N_82 N_95_1 N_83 N_119_i_1 \ + N_293 N_82_1 N_290 N_83_1 N_291 ipl_c_0__n N_296_1 N_283 N_303_1 N_284 ipl_c_1__n \ + N_304_1 N_86 N_306_1 N_80 ipl_c_2__n N_129_i_1 N_78 N_125_i_1 N_108 N_123_i_1 N_109 \ + DTACK_c N_115_0_1 N_100 pos_clk_cpu_est_11_0_1_3__n N_99 N_260_0_1 N_93 N_261_i_1 pos_clk_un14_clk_000_n_sync_n VPA_c N_262_i_1 \ + pos_clk_un9_clk_000_n_sync_n N_263_i_1 N_340 pos_clk_ipl_1_n N_97 RST_c cpu_est_0_3__un3_n N_136 cpu_est_0_3__un1_n N_101 cpu_est_0_3__un0_n \ + N_81 RW_c cpu_est_0_2__un3_n N_116 cpu_est_0_2__un1_n N_96 fc_c_0__n cpu_est_0_2__un0_n N_113 cpu_est_0_1__un3_n N_275 \ + fc_c_1__n cpu_est_0_1__un1_n N_273 cpu_est_0_1__un0_n N_88 bgack_030_int_0_un3_n N_272 AMIGA_BUS_DATA_DIR_c bgack_030_int_0_un1_n N_299 bgack_030_int_0_un0_n \ + N_90 vma_int_0_un3_n N_311 vma_int_0_un1_n N_312 vma_int_0_un0_n N_267 un1_as_000_i rw_000_int_0_un3_n N_264 un1_rst_dly_i_m_i_3__n \ + rw_000_int_0_un1_n pos_clk_un7_clk_000_pe_n rw_000_int_0_un0_n N_308 un1_rst_dly_i_m_i_4__n sm_amiga_srsts_i_0_m2_3__un3_n N_309 sm_amiga_srsts_i_0_m2_3__un1_n AS_030.OE \ + AS_000.OE RW_000.OE DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE BERR.OE \ + RW.OE CLK_DIV_OUT.OE DSACK1.OE CIIN.OE +.names un6_as_030_i.BLIF AS_030 +1 1 +.names AS_030.PIN AS_030_c +1 1 +.names N_112.BLIF AS_030.OE +1 1 +.names un4_as_000_i.BLIF AS_000 +1 1 +.names AS_000.PIN AS_000_c +1 1 +.names un1_as_000_i.BLIF AS_000.OE +1 1 +.names inst_RW_000_INT.BLIF RW_000 +1 1 +.names RW_000.PIN RW_000_c +1 1 +.names un1_as_000_i.BLIF RW_000.OE +1 1 +.names un6_ds_030_i.BLIF DS_030 +1 1 +.names DS_030.PIN DS_030_c +1 1 +.names N_112.BLIF DS_030.OE +1 1 +.names un6_uds_000_i.BLIF UDS_000 +1 1 +.names UDS_000.PIN UDS_000_c +1 1 +.names un1_as_000_i.BLIF UDS_000.OE +1 1 +.names un6_lds_000_i.BLIF LDS_000 +1 1 +.names LDS_000.PIN LDS_000_c +1 1 +.names un1_as_000_i.BLIF LDS_000.OE +1 1 +.names un4_size.BLIF SIZE_0_ +1 1 +.names SIZE_0_.PIN size_c_0__n +1 1 +.names N_89.BLIF SIZE_0_.OE +1 1 +.names un3_size.BLIF SIZE_1_ +1 1 +.names SIZE_1_.PIN size_c_1__n +1 1 +.names N_89.BLIF SIZE_1_.OE +1 1 +.names inst_A0_DMA.BLIF A0 +1 1 +.names A0.PIN A0_c +1 1 +.names N_112.BLIF A0.OE +1 1 +.names gnd_n_n.BLIF BERR +1 1 +.names BERR.PIN BERR_c +1 1 +.names un22_berr.BLIF BERR.OE +1 1 +.names inst_RW_000_DMA.BLIF RW +1 1 +.names RW.PIN RW_c +1 1 +.names N_256.BLIF RW.OE +1 1 +.names gnd_n_n.BLIF CLK_DIV_OUT +1 1 +.names gnd_n_n.BLIF CLK_DIV_OUT.OE +1 1 +.names inst_DSACK1_INTreg.BLIF DSACK1 +1 1 +.names inst_nEXP_SPACE_D0reg.BLIF DSACK1.OE +1 1 +.names un5_ciin.BLIF CIIN +1 1 +.names N_247.BLIF CIIN.OE +1 1 +.names N_308_1.BLIF N_308_2.BLIF N_308 +11 1 +.names N_10_i.BLIF RST_c.BLIF N_44_0 +11 1 +.names inst_DSACK1_INTreg.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n +11 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_1_.C +1 1 +.names CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.D +1 1 +.names RESET_OUT_0_sqmuxa_1.BLIF RST_DLY_1_.BLIF RESET_OUT_0_sqmuxa_5_1 +11 1 +.names N_14_i.BLIF RST_c.BLIF N_41_0 +11 1 +.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF N_9 +1- 1 +-1 1 +.names CLK_000_P_SYNC_6_.BLIF CLK_000_P_SYNC_7_.D +1 1 +.names RESET_OUT_0_sqmuxa_5_1.BLIF RST_DLY_2_.BLIF RESET_OUT_0_sqmuxa_5 +11 1 +.names N_18_i.BLIF RST_c.BLIF N_37_0 +11 1 +.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n +0 1 +.names CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.D +1 1 +.names RESET_OUT_0_sqmuxa_5.BLIF RST_DLY_3_.BLIF RESET_OUT_0_sqmuxa_7_1 +11 1 +.names N_22_i.BLIF RST_c.BLIF N_33_0 +11 1 +.names inst_AS_000_INT.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n +11 1 +.names CLK_000_P_SYNC_8_.BLIF CLK_000_P_SYNC_9_.D +1 1 +.names un22_berr_1_0.BLIF N_340.BLIF un22_berr +11 1 +.names N_113.BLIF bgack_030_int_0_un3_n +0 1 +.names sm_amiga_i_5__n.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n +11 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_2_.C +1 1 +.names CLK_000_N_SYNC_0_.BLIF CLK_000_N_SYNC_1_.D +1 1 +.names FPU_SENSE_i.BLIF N_340.BLIF un21_fpu_cs_1 +11 1 +.names inst_BGACK_030_INTreg.BLIF N_113.BLIF bgack_030_int_0_un1_n +11 1 +.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF N_10 +1- 1 +-1 1 +.names CLK_000_N_SYNC_1_.BLIF CLK_000_N_SYNC_2_.D +1 1 +.names un21_fpu_cs_1.BLIF un22_berr_1.BLIF un21_fpu_cs +11 1 +.names BGACK_000_c.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un0_n +11 1 +.names N_282.BLIF N_282_i +0 1 +.names CLK_000_N_SYNC_2_.BLIF CLK_000_N_SYNC_3_.D +1 1 +.names inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_D0.BLIF pos_clk_un6_bg_030_1_n +11 1 +.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF N_22 +1- 1 +-1 1 +.names DS_000_ENABLE_1_sqmuxa_1.BLIF ds_000_enable_0_un3_n +0 1 +.names CLK_000_N_SYNC_3_.BLIF CLK_000_N_SYNC_4_.D +1 1 +.names pos_clk_un6_bg_030_1_n.BLIF inst_CLK_000_D0.BLIF pos_clk_un6_bg_030_n +11 1 +.names pos_clk_un7_clk_000_pe_n.BLIF vma_int_0_un3_n +0 1 +.names inst_DS_000_ENABLE.BLIF DS_000_ENABLE_1_sqmuxa_1.BLIF ds_000_enable_0_un1_n +11 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_3_.C +1 1 +.names CLK_000_N_SYNC_4_.BLIF CLK_000_N_SYNC_5_.D +1 1 +.names N_97_i.BLIF N_77_i.BLIF N_131_i_1 +11 1 +.names cpu_est_1_.BLIF pos_clk_un7_clk_000_pe_n.BLIF vma_int_0_un1_n +11 1 +.names N_282_i.BLIF ds_000_enable_0_un3_n.BLIF ds_000_enable_0_un0_n +11 1 +.names CLK_000_N_SYNC_5_.BLIF CLK_000_N_SYNC_6_.D +1 1 +.names N_94_i.BLIF N_95_i.BLIF N_131_i_2 +11 1 +.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n +11 1 +.names ds_000_enable_0_un1_n.BLIF ds_000_enable_0_un0_n.BLIF N_11 +1- 1 +-1 1 +.names CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.D +1 1 +.names N_131_i_1.BLIF N_131_i_2.BLIF N_131_i_3 +11 1 +.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF N_18 +1- 1 +-1 1 +.names N_246.BLIF as_030_000_sync_0_un3_n +0 1 +.names CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.D +1 1 +.names N_131_i_3.BLIF N_96_i.BLIF SM_AMIGA_i_7_.D +11 1 +.names N_115.BLIF rw_000_int_0_un3_n +0 1 +.names inst_AS_030_000_SYNC.BLIF N_246.BLIF as_030_000_sync_0_un1_n +11 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_4_.C +1 1 +.names CLK_000_P_SYNC_0_.BLIF CLK_000_P_SYNC_1_.D +1 1 +.names N_73_i.BLIF N_75_i.BLIF N_96_1 +11 1 +.names N_264.BLIF N_115.BLIF rw_000_int_0_un1_n +11 1 +.names pos_clk_un3_as_030_d0_n.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n +11 1 +.names CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.D +1 1 +.names N_251.BLIF sm_amiga_i_0__n.BLIF N_96_2 +11 1 +.names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n +11 1 +.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF N_12 +1- 1 +-1 1 +.names CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.D +1 1 +.names N_96_1.BLIF N_96_2.BLIF N_96_3 +11 1 +.names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF N_14 +1- 1 +-1 1 +.names pos_clk_un3_ds_030_d0_n.BLIF lds_000_int_0_un3_n +0 1 +.names CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.D +1 1 +.names N_96_3.BLIF sm_amiga_i_3__n.BLIF N_96 +11 1 +.names inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF RESET_OUT_0_sqmuxa_1 +11 1 +.names pos_clk_un11_ds_030_d0_i_n.BLIF pos_clk_un3_ds_030_d0_n.BLIF lds_000_int_0_un1_n +11 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_5_.C +1 1 +.names CLK_000_P_SYNC_9_.BLIF inst_CLK_000_PE.D +1 1 +.names N_88_i.BLIF N_90_i.BLIF pos_clk_cpu_est_11_0_1_1__n +11 1 +.names RESET_OUT_0_sqmuxa_1.BLIF RST_DLY_1_.BLIF N_205 +11 1 +.names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n +11 1 +.names CLK_000_N_SYNC_11_.BLIF inst_CLK_000_NE.D +1 1 +.names N_299_i.BLIF N_312_i.BLIF pos_clk_cpu_est_11_0_2_1__n +11 1 +.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF N_13 +1- 1 +-1 1 +.names N_340_1.BLIF N_340_2.BLIF N_340_4 +11 1 +.names N_105_i.BLIF RST_c.BLIF inst_RESET_OUTreg.D +11 1 +.names pos_clk_un5_bgack_030_int_d_n.BLIF rw_000_dma_0_un3_n +0 1 +.names N_340_4.BLIF N_340_3.BLIF N_340 +11 1 +.names N_98_i.BLIF RST_c.BLIF RST_DLY_0_.D +11 1 +.names N_265.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF rw_000_dma_0_un1_n +11 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_6_.C +1 1 +.names AS_030_D0_i.BLIF a_c_20__n.BLIF un5_ciin_1 +11 1 +.names N_268.BLIF sm_amiga_i_3__n.BLIF N_274_0 +11 1 +.names inst_RW_000_DMA.BLIF rw_000_dma_0_un3_n.BLIF rw_000_dma_0_un0_n +11 1 +.names a_c_21__n.BLIF a_c_22__n.BLIF un5_ciin_2 +11 1 +.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n +0 1 +.names rw_000_dma_0_un1_n.BLIF rw_000_dma_0_un0_n.BLIF N_15 +1- 1 +-1 1 +.names a_c_23__n.BLIF a_i_24__n.BLIF un5_ciin_3 +11 1 +.names N_268_i.BLIF SM_AMIGA_4_.BLIF N_275_0 +11 1 +.names pos_clk_un3_ds_030_d0_n.BLIF uds_000_int_0_un3_n +0 1 +.names a_i_25__n.BLIF a_i_26__n.BLIF un5_ciin_4 +11 1 +.names A0_c.BLIF pos_clk_un3_ds_030_d0_n.BLIF uds_000_int_0_un1_n +11 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_7_.C +1 1 +.names a_i_31__n.BLIF a_i_27__n.BLIF un5_ciin_5 +11 1 +.names inst_CLK_000_PE.BLIF CLK_000_PE_i +0 1 +.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n +11 1 +.names a_i_28__n.BLIF a_i_29__n.BLIF un5_ciin_6 +11 1 +.names BERR_c.BLIF BERR_i +0 1 +.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_16 +1- 1 +-1 1 +.names un5_ciin_1.BLIF un5_ciin_2.BLIF un5_ciin_7 +11 1 +.names SM_AMIGA_3_.BLIF sm_amiga_srsts_i_0_m2_3__un3_n +0 1 +.names N_103.BLIF N_103_i +0 1 +.names un5_ciin_3.BLIF un5_ciin_4.BLIF un5_ciin_8 +11 1 +.names BERR_i.BLIF SM_AMIGA_3_.BLIF sm_amiga_srsts_i_0_m2_3__un1_n +11 1 +.names pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_low_0_un3_n +0 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_8_.C +1 1 +.names un5_ciin_5.BLIF un5_ciin_6.BLIF un5_ciin_9 +11 1 +.names CLK_000_PE_i.BLIF sm_amiga_srsts_i_0_m2_3__un3_n.BLIF sm_amiga_srsts_i_0_m2_3__un0_n +11 1 +.names N_103_i.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_low_0_un1_n +11 1 +.names un5_ciin_7.BLIF un5_ciin_8.BLIF un5_ciin_10 +11 1 +.names sm_amiga_srsts_i_0_m2_3__un1_n.BLIF sm_amiga_srsts_i_0_m2_3__un0_n.BLIF N_279 +1- 1 +-1 1 +.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF amiga_bus_enable_dma_low_0_un3_n.BLIF amiga_bus_enable_dma_low_0_un0_n +11 1 +.names un5_ciin_9.BLIF a_i_30__n.BLIF un5_ciin_11 +11 1 +.names amiga_bus_enable_dma_low_0_un1_n.BLIF amiga_bus_enable_dma_low_0_un0_n.BLIF N_19 +1- 1 +-1 1 +.names un5_ciin_10.BLIF un5_ciin_11.BLIF un5_ciin +11 1 +.names inst_DS_030_D0.BLIF DS_030_D0_i +0 1 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_0_.C +1 1 +.names un22_berr_1.BLIF FPU_SENSE_c.BLIF un22_berr_1_0 +11 1 +.names cpu_est_1_.BLIF cpu_est_i_1__n +0 1 +.names DS_030_D0_i.BLIF SM_AMIGA_6_.BLIF pos_clk_un3_ds_030_d0_n +11 1 +.names N_288_i.BLIF N_289_i.BLIF N_127_i_2 +11 1 +.names inst_VMA_INTreg.BLIF VMA_INT_i +0 1 +.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i +0 1 +.names N_127_i_1.BLIF N_127_i_2.BLIF SM_AMIGA_5_.D +11 1 +.names inst_VPA_D.BLIF VPA_D_i +0 1 +.names AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF BGACK_030_INT_i.BLIF un1_amiga_bus_enable_low +11 1 +.names pos_clk_un24_bgack_030_int_i_0_x2.BLIF N_269_i.BLIF pos_clk_un24_bgack_030_int_i_0_i_1_n +11 1 +.names cpu_est_3_reg.BLIF cpu_est_i_3__n +0 1 +.names BG_030_c_i.BLIF pos_clk_un6_bg_030_i_n.BLIF pos_clk_un8_bg_030_0_n +11 1 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_1_.C +1 1 +.names pos_clk_un24_bgack_030_int_i_0_i_1_n.BLIF pos_clk_un22_bgack_030_int_n.BLIF pos_clk_un24_bgack_030_int_i_0_i_n +11 1 +.names cpu_est_0_.BLIF cpu_est_i_0__n +0 1 +.names un6_as_030.BLIF un6_as_030_i +0 1 +.names inst_nEXP_SPACE_D0reg.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF N_80_0_1 +11 1 +.names inst_CLK_000_PE.BLIF CYCLE_DMA_0_.BLIF N_220 +11 1 +.names inst_AS_000_INT.BLIF AS_000_INT_i +0 1 +.names N_80_0_1.BLIF sm_amiga_i_i_7__n.BLIF N_80_0 +11 1 +.names N_270_i.BLIF cpu_est_3_reg.BLIF N_90 +11 1 +.names AS_000_INT_i.BLIF AS_030_i.BLIF un4_as_000 +11 1 +.names sm_amiga_i_2__n.BLIF sm_amiga_i_6__n.BLIF N_75_i_1 +11 1 +.names inst_DTACK_D0.BLIF DTACK_D0_i +0 1 +.names un4_as_000.BLIF un4_as_000_i +0 1 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_2_.C +1 1 +.names N_75_i_1.BLIF sm_amiga_i_4__n.BLIF N_75_i +11 1 +.names DTACK_D0_i.BLIF inst_VPA_D.BLIF N_311 +11 1 +.names inst_DS_000_DMA.BLIF DS_000_DMA_i +0 1 +.names N_249_i.BLIF AS_030_000_SYNC_i.BLIF N_251_0_1 +11 1 +.names N_272_i.BLIF cpu_est_0_.BLIF N_312 +11 1 +.names AS_000_i.BLIF DS_000_DMA_i.BLIF un6_ds_030 +11 1 +.names N_251_0_1.BLIF inst_nEXP_SPACE_D0reg.BLIF N_251_0 +11 1 +.names inst_CLK_000_NE_D0.BLIF N_267.BLIF N_313 +11 1 +.names un6_ds_030.BLIF un6_ds_030_i +0 1 +.names size_c_i_1__n.BLIF A0_c_i.BLIF pos_clk_un11_ds_030_d0_i_1_n +11 1 +.names N_303_i.BLIF N_304_i.BLIF N_186_i +11 1 +.names un6_uds_000.BLIF un6_uds_000_i +0 1 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_3_.C +1 1 +.names pos_clk_un11_ds_030_d0_i_1_n.BLIF size_c_0__n.BLIF pos_clk_un11_ds_030_d0_i_n +11 1 +.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +0 1 +.names vcc_n_n +1 +.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_340_1 +11 1 +.names RW_i.BLIF SM_AMIGA_5_.BLIF N_264_0 +11 1 +.names gnd_n_n +.names a_c_17__n.BLIF a_i_16__n.BLIF N_340_2 +11 1 +.names N_308_i.BLIF N_309_i.BLIF pos_clk_un7_clk_000_pe_0_n +11 1 +.names A_15_.BLIF a_15__n +1 1 +.names a_i_18__n.BLIF a_i_19__n.BLIF N_340_3 +11 1 +.names N_310_i.BLIF N_311_i.BLIF N_267_0 +11 1 +.names A_14_.BLIF a_14__n +1 1 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_4_.C +1 1 +.names N_42_0.BLIF inst_LDS_000_INT.D +0 1 +.names BERR_c.BLIF CLK_000_PE_i.BLIF N_268_i +11 1 +.names A_13_.BLIF a_13__n +1 1 +.names N_15.BLIF N_15_i +0 1 +.names cpu_est_2_.BLIF cpu_est_i_2__n +0 1 +.names A_12_.BLIF a_12__n +1 1 +.names N_40_0.BLIF inst_RW_000_DMA.D +0 1 +.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_270_i +11 1 +.names A_11_.BLIF a_11__n +1 1 +.names N_16.BLIF N_16_i +0 1 +.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF N_272_i +11 1 +.names A_10_.BLIF a_10__n +1 1 +.names CLK_OSZI_c.BLIF inst_CLK_030_H.C +1 1 +.names N_39_0.BLIF inst_UDS_000_INT.D +0 1 +.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_273_i +11 1 +.names A_9_.BLIF a_9__n +1 1 +.names N_19.BLIF N_19_i +0 1 +.names N_136.BLIF sm_amiga_i_4__n.BLIF N_293 +11 1 +.names A_8_.BLIF a_8__n +1 1 +.names N_36_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D +0 1 +.names N_313_i.BLIF SM_AMIGA_3_.BLIF N_136_i +11 1 +.names A_7_.BLIF a_7__n +1 1 +.names N_20.BLIF N_20_i +0 1 +.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n +0 1 +.names A_6_.BLIF a_6__n +1 1 +.names CLK_OSZI_c.BLIF inst_RESET_OUTreg.C +1 1 +.names N_35_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D +0 1 +.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n +0 1 +.names A_5_.BLIF a_5__n +1 1 +.names N_21.BLIF N_21_i +0 1 +.names DTACK_c_i.BLIF RST_c.BLIF N_57_0 +11 1 +.names A_4_.BLIF a_4__n +1 1 +.names N_34_0.BLIF BG_000DFFreg.D +0 1 +.names RST_c.BLIF VPA_c_i.BLIF N_56_0 +11 1 +.names A_3_.BLIF a_3__n +1 1 +.names BG_030_c.BLIF BG_030_c_i +0 1 +.names BGACK_000_c.BLIF CLK_000_PE_i.BLIF N_113 +11 1 +.names A_2_.BLIF a_2__n +1 1 +.names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C +1 1 +.names pos_clk_un6_bg_030_n.BLIF pos_clk_un6_bg_030_i_n +0 1 +.names BGACK_030_INT_i.BLIF RST_c.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa +11 1 +.names pos_clk_un8_bg_030_0_n.BLIF pos_clk_un8_bg_030_n +0 1 +.names SM_AMIGA_1_.BLIF sm_amiga_srsts_i_0_m2_1__un3_n +0 1 +.names N_286_i.BLIF RST_c.BLIF N_127_i_1 +11 1 +.names BERR_i.BLIF SM_AMIGA_1_.BLIF sm_amiga_srsts_i_0_m2_1__un1_n +11 1 +.names N_52_0.BLIF IPL_D0_0_.D +0 1 +.names CLK_000_PE_i.BLIF sm_amiga_srsts_i_0_m2_1__un3_n.BLIF sm_amiga_srsts_i_0_m2_1__un0_n +11 1 +.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C +1 1 +.names nEXP_SPACE_c.BLIF nEXP_SPACE_c_i +0 1 +.names sm_amiga_srsts_i_0_m2_1__un1_n.BLIF sm_amiga_srsts_i_0_m2_1__un0_n.BLIF N_86 +1- 1 +-1 1 +.names N_55_0.BLIF inst_nEXP_SPACE_D0reg.D +0 1 +.names N_275.BLIF sm_amiga_i_5__n.BLIF N_290 +11 1 +.names N_50_0.BLIF inst_DS_030_D0.D +0 1 +.names inst_CLK_000_PE.BLIF SM_AMIGA_0_.BLIF N_84 +11 1 +.names N_3.BLIF N_3_i +0 1 +.names N_273.BLIF cpu_est_3_reg.BLIF N_85 +11 1 +.names CLK_OSZI_c.BLIF inst_RW_000_DMA.C +1 1 +.names N_49_0.BLIF inst_DS_000_DMA.D +0 1 +.names N_273_i.BLIF cpu_est_i_2__n.BLIF N_294 +11 1 +.names N_6.BLIF N_6_i +0 1 +.names N_272.BLIF cpu_est_i_0__n.BLIF N_88 +11 1 +.names N_48_0.BLIF inst_AS_000_DMA.D +0 1 +.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_299 +11 1 +.names N_8.BLIF N_8_i +0 1 +.names CLK_000_N_SYNC_9_.BLIF pos_clk_un11_clk_000_n_sync_i_n.BLIF pos_clk_un9_clk_000_n_sync_n +11 1 +.names CLK_OSZI_c.BLIF inst_RW_000_INT.C +1 1 +.names N_46_0.BLIF inst_A0_DMA.D +0 1 +.names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_PRE_D_i +0 1 +.names N_9.BLIF N_9_i +0 1 +.names CLK_EXP_c.BLIF CLK_OUT_PRE_D_i.BLIF pos_clk_un11_clk_000_n_sync_n +11 1 +.names N_45_0.BLIF inst_DSACK1_INTreg.D +0 1 +.names BERR_i.BLIF N_136_i.BLIF N_97 +11 1 +.names N_12.BLIF N_12_i +0 1 +.names N_81.BLIF sm_amiga_i_0__n.BLIF N_101 +11 1 +.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C +1 1 +.names N_43_0.BLIF inst_AS_030_000_SYNC.D +0 1 +.names N_268.BLIF SM_AMIGA_0_.BLIF N_116 +11 1 +.names N_13.BLIF N_13_i +0 1 +.names N_77_i.BLIF N_101_i.BLIF SM_AMIGA_0_.D +11 1 +.names N_288.BLIF N_288_i +0 1 +.names sm_amiga_i_1__n.BLIF sm_amiga_i_5__n.BLIF N_73_i +11 1 +.names N_289.BLIF N_289_i +0 1 +.names N_116_i.BLIF RST_c.BLIF N_77_i +11 1 +.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C +1 1 +.names A0_c.BLIF A0_c_i +0 1 +.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n +0 1 +.names size_c_1__n.BLIF size_c_i_1__n +0 1 +.names inst_CLK_000_NE.BLIF SM_AMIGA_1_.BLIF N_81_0 +11 1 +.names N_25.BLIF N_25_i +0 1 +.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n +0 1 +.names N_32_0.BLIF IPL_030DFF_2_reg.D +0 1 +.names N_251.BLIF sm_amiga_i_6__n.BLIF N_284 +11 1 +.names CLK_OSZI_c.BLIF inst_AS_000_INT.C +1 1 +.names N_24.BLIF N_24_i +0 1 +.names inst_CLK_000_NE.BLIF CLK_000_NE_i +0 1 +.names N_31_0.BLIF IPL_030DFF_1_reg.D +0 1 +.names CLK_000_NE_i.BLIF sm_amiga_i_4__n.BLIF N_291 +11 1 +.names N_23.BLIF N_23_i +0 1 +.names AS_030_c.BLIF AS_030_i +0 1 +.names N_30_0.BLIF IPL_030DFF_0_reg.D +0 1 +.names AS_030_i.BLIF RST_c.BLIF N_102 +11 1 +.names CLK_OSZI_c.BLIF inst_DSACK1_INTreg.C +1 1 +.names ipl_c_2__n.BLIF ipl_c_i_2__n +0 1 +.names BGACK_030_INT_i.BLIF N_76.BLIF N_100 +11 1 +.names N_54_0.BLIF IPL_D0_2_.D +0 1 +.names BGACK_030_INT_i.BLIF N_76_i.BLIF N_99 +11 1 +.names ipl_c_1__n.BLIF ipl_c_i_1__n +0 1 +.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n +0 1 +.names N_53_0.BLIF IPL_D0_1_.D +0 1 +.names N_78.BLIF sm_amiga_i_2__n.BLIF N_93 +11 1 +.names CLK_OSZI_c.BLIF inst_A0_DMA.C +1 1 +.names ipl_c_0__n.BLIF ipl_c_i_0__n +0 1 +.names SM_AMIGA_1_.BLIF pos_clk_un14_clk_000_n_sync_n.BLIF N_92 +11 1 +.names pos_clk_cpu_est_11_0_3__n.BLIF pos_clk_cpu_est_11_3__n +0 1 +.names inst_nEXP_SPACE_D0reg.BLIF nEXP_SPACE_D0_i +0 1 +.names N_91.BLIF N_91_i +0 1 +.names BGACK_030_INT_i.BLIF nEXP_SPACE_D0_i.BLIF N_89 +11 1 +.names N_260_0.BLIF N_260 +0 1 +.names LDS_000_c.BLIF LDS_000_i +0 1 +.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C +1 1 +.names N_301.BLIF N_301_i +0 1 +.names UDS_000_c.BLIF UDS_000_i +0 1 +.names CLK_OSZI_c.BLIF IPL_030DFF_2_reg.C +1 1 +.names pos_clk_ds_000_dma_4_0_n.BLIF pos_clk_ds_000_dma_4_n +0 1 +.names LDS_000_c.BLIF UDS_000_c.BLIF pos_clk_un22_bgack_030_int_i_n +11 1 +.names N_305.BLIF N_305_i +0 1 +.names N_282.BLIF pos_clk_un3_as_030_d0_i_n.BLIF DS_000_ENABLE_1_sqmuxa_1 +11 1 +.names N_306.BLIF N_306_i +0 1 +.names clk_000_n_sync_i_10__n.BLIF pos_clk_un9_clk_000_n_sync_i_n.BLIF pos_clk_un14_clk_000_n_sync_0_n +11 1 +.names CLK_OSZI_c.BLIF inst_DS_000_DMA.C +1 1 +.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c +0 1 +.names pos_clk_un11_clk_000_n_sync_n.BLIF pos_clk_un11_clk_000_n_sync_i_n +0 1 +.names CLK_OSZI_c.BLIF IPL_D0_0_.C +1 1 +.names N_307.BLIF N_307_i +0 1 +.names N_108_i.BLIF N_109_i.BLIF N_246_0 +11 1 +.names N_265_0.BLIF N_265 +0 1 +.names N_92_i.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_245_0 +11 1 +.names pos_clk_un24_bgack_030_int_i_0_i_n.BLIF pos_clk_un24_bgack_030_int_i_0_n +0 1 +.names N_100_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n +11 1 +.names CLK_OSZI_c.BLIF inst_DS_030_D0.C +1 1 +.names N_62_0.BLIF N_62 +0 1 +.names N_99_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n +11 1 +.names CLK_OSZI_c.BLIF IPL_D0_1_.C +1 1 +.names N_276_0.BLIF N_276 +0 1 +.names BGACK_030_INT_i.BLIF inst_RESET_OUTreg.BLIF N_256 +11 1 +.names N_277_0.BLIF N_277 +0 1 +.names inst_CLK_000_D1.BLIF CLK_000_D1_i +0 1 +.names N_286.BLIF N_286_i +0 1 +.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF CLK_000_P_SYNC_0_.D +11 1 +.names CLK_OSZI_c.BLIF inst_AS_030_D0.C +1 1 +.names N_258_0.BLIF N_258 +0 1 +.names N_256.BLIF nEXP_SPACE_D0_i.BLIF N_112 +11 1 +.names CLK_OSZI_c.BLIF IPL_D0_2_.C +1 1 +.names N_283.BLIF N_283_i +0 1 +.names N_340.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_109 +11 1 +.names N_284.BLIF N_284_i +0 1 +.names N_80.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_108 +11 1 +.names N_290.BLIF N_290_i +0 1 +.names sm_amiga_i_5__n.BLIF pos_clk_un3_as_030_d0_i_n.BLIF AS_000_INT_1_sqmuxa +11 1 +.names CLK_OSZI_c.BLIF inst_nEXP_SPACE_D0reg.C +1 1 +.names N_291.BLIF N_291_i +0 1 +.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF pos_clk_a0_dma_3_n +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_i_7_.C +1 1 +.names N_279.BLIF N_279_i +0 1 +.names A1_c.BLIF A1_i +0 1 +.names N_293.BLIF N_293_i +0 1 +.names A1_i.BLIF BGACK_030_INT_i.BLIF N_104 +11 1 +.names N_82.BLIF N_82_i +0 1 +.names A1_c.BLIF BGACK_030_INT_i.BLIF N_103 +11 1 +.names CLK_OSZI_c.BLIF inst_VPA_D.C +1 1 +.names N_83.BLIF N_83_i +0 1 +.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_305 +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C +1 1 +.names N_259_0.BLIF SM_AMIGA_2_.D +0 1 +.names RW_000_c.BLIF RW_000_i +0 1 +.names N_84.BLIF N_84_i +0 1 +.names inst_AS_000_DMA.BLIF RW_000_i.BLIF N_301 +11 1 +.names N_115_0.BLIF N_115 +0 1 +.names inst_CLK_030_H.BLIF CLK_EXP_c.BLIF N_91 +11 1 +.names CLK_OSZI_c.BLIF inst_DTACK_D0.C +1 1 +.names N_85.BLIF N_85_i +0 1 +.names inst_CLK_000_NE.BLIF sm_amiga_i_6__n.BLIF N_289 +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C +1 1 +.names N_294.BLIF N_294_i +0 1 +.names BERR_i.BLIF SM_AMIGA_5_.BLIF N_288 +11 1 +.names N_296.BLIF N_296_i +0 1 +.names N_276.BLIF sm_amiga_i_5__n.BLIF N_286 +11 1 +.names N_109.BLIF N_109_i +0 1 +.names N_62.BLIF SM_AMIGA_i_7_.BLIF N_283 +11 1 +.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C +1 1 +.names N_246_0.BLIF N_246 +0 1 +.names CLK_000_NE_i.BLIF SM_AMIGA_1_.BLIF N_78_0 +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C +1 1 +.names un5_ciin.BLIF un5_ciin_i +0 1 +.names LDS_000_i.BLIF UDS_000_i.BLIF N_76_i +11 1 +.names N_247_0.BLIF N_247 +0 1 +.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF pos_clk_un5_bgack_030_int_d_i_n +11 1 +.names N_248_0.BLIF N_248 +0 1 +.names AS_030_D0_i.BLIF BERR_c.BLIF pos_clk_un3_as_030_d0_i_n +11 1 +.names CLK_OSZI_c.BLIF BG_000DFFreg.C +1 1 +.names inst_CLK_000_D0.BLIF CLK_000_D0_i +0 1 +.names CLK_000_D0_i.BLIF inst_CLK_000_D1.BLIF N_249_i +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C +1 1 +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +0 1 +.names RST_c.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF N_248_0 +11 1 +.names N_251_0.BLIF N_251 +0 1 +.names nEXP_SPACE_D0_i.BLIF un5_ciin_i.BLIF N_247_0 +11 1 +.names pos_clk_un3_as_030_d0_i_n.BLIF pos_clk_un3_as_030_d0_n +0 1 +.names inst_CLK_000_PE.BLIF SM_AMIGA_6_.BLIF N_276_0 +11 1 +.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.C +1 1 +.names pos_clk_un5_bgack_030_int_d_i_n.BLIF pos_clk_un5_bgack_030_int_d_n +0 1 +.names N_268_i.BLIF SM_AMIGA_6_.BLIF N_62_0 +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C +1 1 +.names N_75_i.BLIF N_75 +0 1 +.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_269_i +11 1 +.names N_76_i.BLIF N_76 +0 1 +.names N_78_0.BLIF N_78 +0 1 +.names BGACK_030_INT_i.BLIF RW_000_i.BLIF N_265_0 +11 1 +.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C +1 1 +.names N_80_0.BLIF N_80 +0 1 +.names N_305_i.BLIF N_306_i.BLIF AMIGA_BUS_DATA_DIR_c_0 +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C +1 1 +.names CLK_EXP_c.BLIF CLK_EXP_c_i +0 1 +.names N_301_i.BLIF pos_clk_un24_bgack_030_int_i_0_i_n.BLIF pos_clk_ds_000_dma_4_0_n +11 1 +.names N_116.BLIF N_116_i +0 1 +.names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n +0 1 +.names N_73_i.BLIF N_73 +0 1 +.names N_82_i.BLIF N_83_i.BLIF N_259_0 +11 1 +.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C +1 1 +.names N_101.BLIF N_101_i +0 1 +.names CLK_EXP_c_i.BLIF pos_clk_un24_bgack_030_int_i_0_i_n.BLIF N_258_0 +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C +1 1 +.names CLK_000_N_SYNC_10_.BLIF clk_000_n_sync_i_10__n +0 1 +.names inst_AS_000_DMA.BLIF AS_000_DMA_i +0 1 +.names pos_clk_un9_clk_000_n_sync_n.BLIF pos_clk_un9_clk_000_n_sync_i_n +0 1 +.names AS_000_c.BLIF AS_000_i +0 1 +.names pos_clk_un14_clk_000_n_sync_0_n.BLIF pos_clk_un14_clk_000_n_sync_n +0 1 +.names AS_000_DMA_i.BLIF AS_000_i.BLIF un6_as_030 +11 1 +.names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C +1 1 +.names pos_clk_un22_bgack_030_int_i_n.BLIF pos_clk_un22_bgack_030_int_n +0 1 +.names inst_CLK_030_H.BLIF CLK_030_H_i +0 1 +.names CLK_OSZI_c.BLIF cpu_est_0_.C +1 1 +.names N_86.BLIF N_86_i +0 1 +.names CLK_030_H_i.BLIF N_277.BLIF N_307 +11 1 +.names N_93.BLIF N_93_i +0 1 +.names N_99.BLIF N_99_i +0 1 +.names a_c_16__n.BLIF a_i_16__n +0 1 +.names CLK_OSZI_c.BLIF inst_CLK_000_PE.C +1 1 +.names pos_clk_size_dma_6_0_1__n.BLIF pos_clk_size_dma_6_1__n +0 1 +.names SIZE_DMA_1_.BLIF size_dma_i_1__n +0 1 +.names CLK_OSZI_c.BLIF cpu_est_1_.C +1 1 +.names N_100.BLIF N_100_i +0 1 +.names SIZE_DMA_0_.BLIF size_dma_i_1__n.BLIF un4_size +11 1 +.names A_16_.BLIF a_c_16__n +1 1 +.names pos_clk_size_dma_6_0_0__n.BLIF pos_clk_size_dma_6_0__n +0 1 +.names SIZE_DMA_0_.BLIF size_dma_i_0__n +0 1 +.names A_17_.BLIF a_c_17__n +1 1 +.names N_245_0.BLIF N_245 +0 1 +.names SIZE_DMA_1_.BLIF size_dma_i_0__n.BLIF un3_size +11 1 +.names CLK_OSZI_c.BLIF inst_CLK_000_NE.C +1 1 +.names A_18_.BLIF a_c_18__n +1 1 +.names N_108.BLIF N_108_i +0 1 +.names inst_AS_030_D0.BLIF AS_030_D0_i +0 1 +.names CLK_OSZI_c.BLIF cpu_est_2_.C +1 1 +.names A_19_.BLIF a_c_19__n +1 1 +.names pos_clk_un7_clk_000_pe_0_n.BLIF pos_clk_un7_clk_000_pe_n +0 1 +.names a_c_24__n.BLIF a_i_24__n +0 1 +.names A_20_.BLIF a_c_20__n +1 1 +.names N_264_0.BLIF N_264 +0 1 +.names AS_030_i.BLIF BGACK_000_c.BLIF un22_berr_1 +11 1 +.names A_21_.BLIF a_c_21__n +1 1 +.names N_304.BLIF N_304_i +0 1 +.names FPU_SENSE_c.BLIF FPU_SENSE_i +0 1 +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C +1 1 +.names A_22_.BLIF a_c_22__n +1 1 +.names N_303.BLIF N_303_i +0 1 +.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i +0 1 +.names CLK_OSZI_c.BLIF cpu_est_3_reg.C +1 1 +.names A_23_.BLIF a_c_23__n +1 1 +.names VPA_c.BLIF VPA_c_i +0 1 +.names inst_BGACK_030_INTreg.BLIF un1_amiga_bus_enable_dma_high_0_m2_0__un3_n +0 1 +.names A_24_.BLIF a_c_24__n +1 1 +.names N_56_0.BLIF inst_VPA_D.D +0 1 +.names SM_AMIGA_i_7_.BLIF inst_BGACK_030_INTreg.BLIF un1_amiga_bus_enable_dma_high_0_m2_0__un1_n +11 1 +.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D +1 1 +.names A_25_.BLIF a_c_25__n +1 1 +.names DTACK_c.BLIF DTACK_c_i +0 1 +.names AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF un1_amiga_bus_enable_dma_high_0_m2_0__un3_n.BLIF un1_amiga_bus_enable_dma_high_0_m2_0__un0_n +11 1 +.names A_26_.BLIF a_c_26__n +1 1 +.names N_57_0.BLIF inst_DTACK_D0.D +0 1 +.names un1_amiga_bus_enable_dma_high_0_m2_0__un1_n.BLIF un1_amiga_bus_enable_dma_high_0_m2_0__un0_n.BLIF N_71 +1- 1 +-1 1 +.names CLK_OSZI_c.BLIF IPL_030DFF_0_reg.C +1 1 +.names CLK_OSZI_c.BLIF inst_CLK_000_D1.C +1 1 +.names A_27_.BLIF a_c_27__n +1 1 +.names N_97.BLIF N_97_i +0 1 +.names RW_c.BLIF RW_i +0 1 +.names A_28_.BLIF a_c_28__n +1 1 +.names N_96.BLIF N_96_i +0 1 +.names SM_AMIGA_5_.BLIF un1_sm_amiga_7_i_m2_un3_n +0 1 +.names A_29_.BLIF a_c_29__n +1 1 +.names N_95.BLIF N_95_i +0 1 +.names RW_i.BLIF SM_AMIGA_5_.BLIF un1_sm_amiga_7_i_m2_un1_n +11 1 +.names inst_CLK_000_NE.BLIF inst_CLK_000_NE_D0.D +1 1 +.names A_30_.BLIF a_c_30__n +1 1 +.names N_94.BLIF N_94_i +0 1 +.names sm_amiga_i_3__n.BLIF un1_sm_amiga_7_i_m2_un3_n.BLIF un1_sm_amiga_7_i_m2_un0_n +11 1 +.names CLK_OSZI_c.BLIF IPL_030DFF_1_reg.C +1 1 +.names A_31_.BLIF a_c_31__n +1 1 +.names N_313.BLIF N_313_i +0 1 +.names un1_sm_amiga_7_i_m2_un1_n.BLIF un1_sm_amiga_7_i_m2_un0_n.BLIF N_282 +1- 1 +-1 1 +.names CLK_OSZI_c.BLIF inst_CLK_000_NE_D0.C +1 1 +.names N_136_i.BLIF N_136 +0 1 +.names AS_000_DMA_i.BLIF CLK_EXP_c_i.BLIF N_277_0 +11 1 +.names A1.BLIF A1_c +1 1 +.names N_81_0.BLIF N_81 +0 1 +.names inst_LDS_000_INT.BLIF LDS_000_INT_i +0 1 +.names nEXP_SPACE.BLIF nEXP_SPACE_c +1 1 +.names N_312.BLIF N_312_i +0 1 +.names LDS_000_INT_i.BLIF un6_uds_000_1.BLIF un6_lds_000 +11 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_9_.C +1 1 +.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_D.D +1 1 +.names N_90.BLIF N_90_i +0 1 +.names inst_UDS_000_INT.BLIF UDS_000_INT_i +0 1 +.names BG_030.BLIF BG_030_c +1 1 +.names N_88.BLIF N_88_i +0 1 +.names UDS_000_INT_i.BLIF un6_uds_000_1.BLIF un6_uds_000 +11 1 +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_D.C +1 1 +.names BG_000DFFreg.BLIF BG_000 +1 1 +.names N_299.BLIF N_299_i +0 1 +.names a_c_25__n.BLIF a_i_25__n +0 1 +.names CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D +1 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030 +1 1 +.names N_275_0.BLIF N_275 +0 1 +.names a_c_26__n.BLIF a_i_26__n +0 1 +.names BGACK_000.BLIF BGACK_000_c +1 1 +.names N_274_0.BLIF N_274 +0 1 +.names a_c_27__n.BLIF a_i_27__n +0 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_10_.C +1 1 +.names CLK_030.BLIF CLK_EXP_c +1 1 +.names N_273_i.BLIF N_273 +0 1 +.names a_c_28__n.BLIF a_i_28__n +0 1 +.names CLK_OSZI_c.BLIF inst_CLK_000_D0.C +1 1 +.names CLK_000.BLIF inst_CLK_000_D0.D +1 1 +.names N_272_i.BLIF N_272 +0 1 +.names a_c_29__n.BLIF a_i_29__n +0 1 +.names CLK_OSZI.BLIF CLK_OSZI_c +1 1 +.names N_270_i.BLIF N_270 +0 1 +.names a_c_30__n.BLIF a_i_30__n +0 1 +.names CLK_000_N_SYNC_10_.BLIF CLK_000_N_SYNC_11_.D +1 1 +.names N_268_i.BLIF N_268 +0 1 +.names a_c_31__n.BLIF a_i_31__n +0 1 +.names inst_CLK_000_NE.BLIF pos_clk_RST_DLY_5_iv_0_x2_0_.X1 +1 1 +.names CLK_EXP_c.BLIF CLK_EXP +1 1 +.names N_310.BLIF N_310_i +0 1 +.names a_c_18__n.BLIF a_i_18__n +0 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_11_.C +1 1 +.names un21_fpu_cs_i.BLIF FPU_CS +1 1 +.names N_311.BLIF N_311_i +0 1 +.names a_c_19__n.BLIF a_i_19__n +0 1 +.names RST_DLY_0_.BLIF pos_clk_RST_DLY_5_iv_0_x2_0_.X2 +1 1 +.names FPU_SENSE.BLIF FPU_SENSE_c +1 1 +.names N_267_0.BLIF N_267 +0 1 +.names IPL_030DFF_0_reg.BLIF IPL_030_0_ +1 1 +.names N_309.BLIF N_309_i +0 1 +.names IPL_030DFF_1_reg.BLIF IPL_030_1_ +1 1 +.names N_308.BLIF N_308_i +0 1 +.names AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa.BLIF inst_BGACK_030_INT_D.D +0 1 +.names CLK_OSZI_c.BLIF RST_DLY_0_.C +1 1 +.names inst_CLK_000_NE_D0.BLIF cpu_est_0_0_x2_0_.X1 +1 1 +.names IPL_030DFF_2_reg.BLIF IPL_030_2_ +1 1 +.names un1_rst_dly_i_m_6__n.BLIF un1_rst_dly_i_m_i_6__n +0 1 +.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D +0 1 +.names IPL_0_.BLIF ipl_c_0__n +1 1 +.names un1_rst_dly_i_m_7__n.BLIF un1_rst_dly_i_m_i_7__n +0 1 +.names G_165.BLIF N_224_i +0 1 +.names cpu_est_0_.BLIF cpu_est_0_0_x2_0_.X2 +1 1 +.names IPL_1_.BLIF ipl_c_1__n +1 1 +.names un1_rst_dly_i_m_8__n.BLIF un1_rst_dly_i_m_i_8__n +0 1 +.names G_166.BLIF N_225_i +0 1 +.names IPL_2_.BLIF ipl_c_2__n +1 1 +.names un1_rst_dly_i_m_2__n.BLIF un1_rst_dly_i_m_i_2__n +0 1 +.names G_167.BLIF N_226_i +0 1 +.names CLK_OSZI_c.BLIF RST_DLY_1_.C +1 1 +.names N_98.BLIF N_98_i +0 1 +.names DS_030_c.BLIF DS_030_i +0 1 +.names CYCLE_DMA_1_.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.X1 +1 1 +.names DTACK.BLIF DTACK_c +1 1 +.names N_105.BLIF N_105_i +0 1 +.names inst_DS_000_ENABLE.BLIF DS_030_i.BLIF un6_uds_000_1 +11 1 +.names vcc_n_n.BLIF AVEC +1 1 +.names N_22.BLIF N_22_i +0 1 +.names N_102.BLIF inst_AS_030_D0.D +0 1 +.names N_220.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.X2 +1 1 +.names cpu_est_3_reg.BLIF E +1 1 +.names N_33_0.BLIF inst_BGACK_030_INTreg.D +0 1 +.names DS_030_i.BLIF RST_c.BLIF N_50_0 +11 1 +.names CLK_OSZI_c.BLIF RST_DLY_2_.C +1 1 +.names VPA.BLIF VPA_c +1 1 +.names N_18.BLIF N_18_i +0 1 +.names RST_c.BLIF nEXP_SPACE_c_i.BLIF N_55_0 +11 1 +.names inst_VMA_INTreg.BLIF VMA +1 1 +.names N_37_0.BLIF inst_VMA_INTreg.D +0 1 +.names ipl_c_i_0__n.BLIF RST_c.BLIF N_52_0 +11 1 +.names inst_CLK_000_PE.BLIF pos_clk_CYCLE_DMA_5_0_i_x2.X1 +1 1 +.names RST.BLIF RST_c +1 1 +.names N_14.BLIF N_14_i +0 1 +.names ipl_c_i_1__n.BLIF RST_c.BLIF N_53_0 +11 1 +.names inst_RESET_OUTreg.BLIF RESET +1 1 +.names N_41_0.BLIF inst_RW_000_INT.D +0 1 +.names ipl_c_i_2__n.BLIF RST_c.BLIF N_54_0 +11 1 +.names CLK_OSZI_c.BLIF RST_DLY_3_.C +1 1 +.names CYCLE_DMA_0_.BLIF pos_clk_CYCLE_DMA_5_0_i_x2.X2 +1 1 +.names N_10.BLIF N_10_i +0 1 +.names N_23_i.BLIF RST_c.BLIF N_30_0 +11 1 +.names FC_0_.BLIF fc_c_0__n +1 1 +.names N_44_0.BLIF inst_AS_000_INT.D +0 1 +.names N_24_i.BLIF RST_c.BLIF N_31_0 +11 1 +.names FC_1_.BLIF fc_c_1__n +1 1 +.names pos_clk_cpu_est_11_0_1__n.BLIF pos_clk_cpu_est_11_1__n +0 1 +.names N_25_i.BLIF RST_c.BLIF N_32_0 +11 1 +.names CYCLE_DMA_0_.BLIF pos_clk_un24_bgack_030_int_i_0_x2.X1 +1 1 +.names gnd_n_n.BLIF AMIGA_ADDR_ENABLE +1 1 +.names un1_rst_dly_i_m_3__n.BLIF un1_rst_dly_i_m_i_3__n +0 1 +.names N_248.BLIF size_dma_0_0__un3_n +0 1 +.names CLK_OSZI_c.BLIF RST_DLY_4_.C +1 1 +.names AMIGA_BUS_DATA_DIR_c.BLIF AMIGA_BUS_DATA_DIR +1 1 +.names un1_rst_dly_i_m_4__n.BLIF un1_rst_dly_i_m_i_4__n +0 1 +.names pos_clk_size_dma_6_0__n.BLIF N_248.BLIF size_dma_0_0__un1_n +11 1 +.names CYCLE_DMA_1_.BLIF pos_clk_un24_bgack_030_int_i_0_x2.X2 +1 1 +.names un1_amiga_bus_enable_low_i.BLIF AMIGA_BUS_ENABLE_LOW +1 1 +.names un1_rst_dly_i_m_5__n.BLIF un1_rst_dly_i_m_i_5__n +0 1 +.names SIZE_DMA_0_.BLIF size_dma_0_0__un3_n.BLIF size_dma_0_0__un0_n +11 1 +.names N_71_i.BLIF AMIGA_BUS_ENABLE_HIGH +1 1 +.names RESET_OUT_0_sqmuxa.BLIF RESET_OUT_0_sqmuxa_i +0 1 +.names size_dma_0_0__un1_n.BLIF size_dma_0_0__un0_n.BLIF SIZE_DMA_0_.D +1- 1 +-1 1 +.names G_139.BLIF un1_rst_dly_i_3__n +0 1 +.names N_248.BLIF size_dma_0_1__un3_n +0 1 +.names CLK_OSZI_c.BLIF RST_DLY_5_.C +1 1 +.names IPL_D0_2_.BLIF G_167.X1 +1 1 +.names pos_clk_cpu_est_11_0_1_3__n.BLIF N_294_i.BLIF pos_clk_cpu_est_11_0_3__n +11 1 +.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_3__n.BLIF un1_rst_dly_i_m_3__n +11 1 +.names pos_clk_size_dma_6_1__n.BLIF N_248.BLIF size_dma_0_1__un1_n +11 1 +.names N_91_i.BLIF RW_000_i.BLIF N_260_0_1 +11 1 +.names inst_RESET_OUTreg.BLIF RESET_OUT_i +0 1 +.names SIZE_DMA_1_.BLIF size_dma_0_1__un3_n.BLIF size_dma_0_1__un0_n +11 1 +.names ipl_c_2__n.BLIF G_167.X2 +1 1 +.names N_260_0_1.BLIF pos_clk_un24_bgack_030_int_i_0_i_n.BLIF N_260_0 +11 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i +0 1 +.names size_dma_0_1__un1_n.BLIF size_dma_0_1__un0_n.BLIF SIZE_DMA_1_.D +1- 1 +-1 1 +.names N_307_i.BLIF RST_c.BLIF N_261_i_1 +11 1 +.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUTreg.BLIF un1_as_000_i +11 1 +.names pos_clk_ipl_n.BLIF ipl_030_0_0__un3_n +0 1 +.names CLK_OSZI_c.BLIF RST_DLY_6_.C +1 1 +.names N_261_i_1.BLIF pos_clk_un24_bgack_030_int_i_0_i_n.BLIF inst_CLK_030_H.D +11 1 +.names N_211.BLIF RST_DLY_5_.BLIF N_213 +11 1 +.names ipl_c_0__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_0__un1_n +11 1 +.names IPL_D0_0_.BLIF G_165.X1 +1 1 +.names pos_clk_CYCLE_DMA_5_1_i_x2.BLIF N_269_i.BLIF N_262_i_1 +11 1 +.names N_209.BLIF RST_DLY_4_.BLIF N_211 +11 1 +.names IPL_030DFF_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n +11 1 +.names N_262_i_1.BLIF RST_c.BLIF CYCLE_DMA_1_.D +11 1 +.names RESET_OUT_0_sqmuxa_5.BLIF RST_DLY_3_.BLIF N_209 +11 1 +.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF N_23 +1- 1 +-1 1 +.names ipl_c_0__n.BLIF G_165.X2 +1 1 +.names pos_clk_CYCLE_DMA_5_0_i_x2.BLIF N_269_i.BLIF N_263_i_1 +11 1 +.names N_71.BLIF N_71_i +0 1 +.names pos_clk_ipl_n.BLIF ipl_030_0_1__un3_n +0 1 +.names CLK_OSZI_c.BLIF RST_DLY_7_.C +1 1 +.names N_263_i_1.BLIF RST_c.BLIF CYCLE_DMA_0_.D +11 1 +.names un1_amiga_bus_enable_low.BLIF un1_amiga_bus_enable_low_i +0 1 +.names ipl_c_1__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_1__un1_n +11 1 +.names N_226_i.BLIF N_224_i.BLIF pos_clk_ipl_1_n +11 1 +.names un21_fpu_cs.BLIF un21_fpu_cs_i +0 1 +.names IPL_030DFF_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n +11 1 +.names IPL_D0_1_.BLIF G_166.X1 +1 1 +.names pos_clk_ipl_1_n.BLIF N_225_i.BLIF pos_clk_ipl_n +11 1 +.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF N_24 +1- 1 +-1 1 +.names N_270.BLIF cpu_est_0_.BLIF N_303_1 +11 1 +.names pos_clk_ipl_n.BLIF ipl_030_0_2__un3_n +0 1 +.names CLK_OSZI_c.BLIF CYCLE_DMA_0_.C +1 1 +.names ipl_c_1__n.BLIF G_166.X2 +1 1 +.names N_303_1.BLIF cpu_est_i_3__n.BLIF N_303 +11 1 +.names RST_c.BLIF un1_rst_dly_i_m_i_7__n.BLIF RST_DLY_6_.D +11 1 +.names ipl_c_2__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_2__un1_n +11 1 +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_304_1 +11 1 +.names G_147.BLIF un1_rst_dly_i_7__n +0 1 +.names IPL_030DFF_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n +11 1 +.names N_304_1.BLIF cpu_est_i_2__n.BLIF N_304 +11 1 +.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_7__n.BLIF un1_rst_dly_i_m_7__n +11 1 +.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_25 +1- 1 +-1 1 +.names RESET_OUT_0_sqmuxa_5.BLIF G_141.X1 +1 1 +.names N_269_i.BLIF RW_000_c.BLIF N_306_1 +11 1 +.names RST_c.BLIF un1_rst_dly_i_m_i_6__n.BLIF RST_DLY_5_.D +11 1 +.names N_104.BLIF N_104_i +0 1 +.names CLK_OSZI_c.BLIF CYCLE_DMA_1_.C +1 1 +.names N_306_1.BLIF nEXP_SPACE_D0_i.BLIF N_306 +11 1 +.names G_145.BLIF un1_rst_dly_i_6__n +0 1 +.names pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_high_0_un3_n +0 1 +.names RST_DLY_3_.BLIF G_141.X2 +1 1 +.names N_283_i.BLIF N_284_i.BLIF N_129_i_1 +11 1 +.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_6__n.BLIF un1_rst_dly_i_m_6__n +11 1 +.names N_104_i.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_high_0_un1_n +11 1 +.names N_129_i_1.BLIF RST_c.BLIF SM_AMIGA_6_.D +11 1 +.names RST_c.BLIF un1_rst_dly_i_m_i_5__n.BLIF RST_DLY_4_.D +11 1 +.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n +11 1 +.names N_290_i.BLIF N_291_i.BLIF N_125_i_1 +11 1 +.names G_143.BLIF un1_rst_dly_i_5__n +0 1 +.names amiga_bus_enable_dma_high_0_un1_n.BLIF amiga_bus_enable_dma_high_0_un0_n.BLIF N_20 +1- 1 +-1 1 +.names CLK_OSZI_c.BLIF SIZE_DMA_0_.C +1 1 +.names N_205.BLIF G_139.X1 +1 1 +.names N_125_i_1.BLIF RST_c.BLIF SM_AMIGA_4_.D +11 1 +.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_5__n.BLIF un1_rst_dly_i_m_5__n +11 1 +.names pos_clk_un8_bg_030_n.BLIF bg_000_0_un3_n +0 1 +.names N_279_i.BLIF N_293_i.BLIF N_123_i_1 +11 1 +.names RST_c.BLIF un1_rst_dly_i_m_i_4__n.BLIF RST_DLY_3_.D +11 1 +.names BG_030_c.BLIF pos_clk_un8_bg_030_n.BLIF bg_000_0_un1_n +11 1 +.names RST_DLY_2_.BLIF G_139.X2 +1 1 +.names N_123_i_1.BLIF RST_c.BLIF SM_AMIGA_3_.D +11 1 +.names G_141.BLIF un1_rst_dly_i_4__n +0 1 +.names BG_000DFFreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n +11 1 +.names N_84_i.BLIF sm_amiga_i_5__n.BLIF N_115_0_1 +11 1 +.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_4__n.BLIF un1_rst_dly_i_m_4__n +11 1 +.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF N_21 +1- 1 +-1 1 +.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C +1 1 +.names N_115_0_1.BLIF SM_AMIGA_i_7_.BLIF N_115_0 +11 1 +.names RST_c.BLIF un1_rst_dly_i_m_i_3__n.BLIF RST_DLY_2_.D +11 1 +.names N_11.BLIF RST_c.BLIF inst_DS_000_ENABLE.D +11 1 +.names RESET_OUT_0_sqmuxa_1.BLIF G_137.X1 +1 1 +.names N_296_i.BLIF N_85_i.BLIF pos_clk_cpu_est_11_0_1_3__n +11 1 +.names RESET_OUT_0_sqmuxa_i.BLIF RESET_OUT_i.BLIF N_105 +11 1 +.names N_21_i.BLIF RST_c.BLIF N_34_0 +11 1 +.names RST_DLY_4_.BLIF RST_DLY_5_.BLIF RESET_OUT_0_sqmuxa_7_2 +11 1 +.names pos_clk_RST_DLY_5_iv_0_x2_0_.BLIF N_87_i_i +0 1 +.names N_20_i.BLIF RST_c.BLIF N_35_0 +11 1 +.names RST_DLY_1_.BLIF G_137.X2 +1 1 +.names RESET_OUT_0_sqmuxa_7_1.BLIF RESET_OUT_0_sqmuxa_7_2.BLIF RESET_OUT_0_sqmuxa_7_3 +11 1 +.names N_87_i_i.BLIF RESET_OUT_0_sqmuxa_i.BLIF N_98 +11 1 +.names N_19_i.BLIF RST_c.BLIF N_36_0 +11 1 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_5_.C +1 1 +.names RESET_OUT_0_sqmuxa_7_3.BLIF RST_DLY_6_.BLIF RESET_OUT_0_sqmuxa_7 +11 1 +.names G_137.BLIF un1_rst_dly_i_2__n +0 1 +.names N_16_i.BLIF RST_c.BLIF N_39_0 +11 1 +.names N_75.BLIF BERR_i.BLIF N_94_1 +11 1 +.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_2__n.BLIF un1_rst_dly_i_m_2__n +11 1 +.names N_15_i.BLIF RST_c.BLIF N_40_0 +11 1 +.names RESET_OUT_0_sqmuxa_7.BLIF G_149.X1 +1 1 +.names N_94_1.BLIF CLK_000_PE_i.BLIF N_94 +11 1 +.names RST_c.BLIF un1_rst_dly_i_m_i_2__n.BLIF RST_DLY_1_.D +11 1 +.names N_13_i.BLIF RST_c.BLIF N_42_0 +11 1 +.names N_73.BLIF BERR_i.BLIF N_95_1 +11 1 +.names G_149.BLIF un1_rst_dly_i_8__n +0 1 +.names N_12_i.BLIF RST_c.BLIF N_43_0 +11 1 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_6_.C +1 1 +.names RST_DLY_7_.BLIF G_149.X2 +1 1 +.names N_95_1.BLIF CLK_000_NE_i.BLIF N_95 +11 1 +.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_8__n.BLIF un1_rst_dly_i_m_8__n +11 1 +.names N_9_i.BLIF RST_c.BLIF N_45_0 +11 1 +.names N_86_i.BLIF N_93_i.BLIF N_119_i_1 +11 1 +.names RST_c.BLIF un1_rst_dly_i_m_i_8__n.BLIF RST_DLY_7_.D +11 1 +.names N_8_i.BLIF RST_c.BLIF N_46_0 +11 1 +.names N_119_i_1.BLIF RST_c.BLIF SM_AMIGA_1_.D +11 1 +.names RESET_OUT_0_sqmuxa_7.BLIF RST_DLY_7_.BLIF RESET_OUT_0_sqmuxa +11 1 +.names N_6_i.BLIF RST_c.BLIF N_48_0 +11 1 +.names N_213.BLIF G_147.X1 +1 1 +.names N_274.BLIF RST_c.BLIF N_82_1 +11 1 +.names N_3_i.BLIF RST_c.BLIF N_49_0 +11 1 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_7_.C +1 1 +.names N_82_1.BLIF SM_AMIGA_2_.BLIF N_82 +11 1 +.names un6_lds_000.BLIF un6_lds_000_i +0 1 +.names RST_DLY_6_.BLIF G_147.X2 +1 1 +.names N_313.BLIF RST_c.BLIF N_83_1 +11 1 +.names N_260.BLIF ds_000_dma_0_un3_n +0 1 +.names N_83_1.BLIF SM_AMIGA_3_.BLIF N_83 +11 1 +.names pos_clk_ds_000_dma_4_n.BLIF N_260.BLIF ds_000_dma_0_un1_n +11 1 +.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_296_1 +11 1 +.names inst_DS_000_DMA.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n +11 1 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_8_.C +1 1 +.names N_211.BLIF G_145.X1 +1 1 +.names N_296_1.BLIF cpu_est_i_2__n.BLIF N_296 +11 1 +.names inst_CLK_000_NE_D0.BLIF cpu_est_0_3__un3_n +0 1 +.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3 +1- 1 +-1 1 +.names pos_clk_cpu_est_11_0_1_1__n.BLIF pos_clk_cpu_est_11_0_2_1__n.BLIF pos_clk_cpu_est_11_0_1__n +11 1 +.names pos_clk_cpu_est_11_3__n.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_3__un1_n +11 1 +.names N_258.BLIF as_000_dma_0_un3_n +0 1 +.names RST_DLY_5_.BLIF G_145.X2 +1 1 +.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_310_1 +11 1 +.names cpu_est_3_reg.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n +11 1 +.names pos_clk_un24_bgack_030_int_i_0_n.BLIF N_258.BLIF as_000_dma_0_un1_n +11 1 +.names VMA_INT_i.BLIF VPA_D_i.BLIF N_310_2 +11 1 +.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_reg.D +1- 1 +-1 1 +.names inst_AS_000_DMA.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n +11 1 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_9_.C +1 1 +.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF N_310_3 +11 1 +.names inst_CLK_000_NE_D0.BLIF cpu_est_0_2__un3_n +0 1 +.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF N_6 +1- 1 +-1 1 +.names N_209.BLIF G_143.X1 +1 1 +.names N_310_1.BLIF N_310_2.BLIF N_310_4 +11 1 +.names N_186_i.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_2__un1_n +11 1 +.names pos_clk_un5_bgack_030_int_d_n.BLIF a0_dma_0_un3_n +0 1 +.names N_310_4.BLIF N_310_3.BLIF N_310 +11 1 +.names cpu_est_2_.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n +11 1 +.names pos_clk_a0_dma_3_n.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF a0_dma_0_un1_n +11 1 +.names N_249_i.BLIF CLK_000_N_SYNC_0_.D +1 1 +.names RST_DLY_4_.BLIF G_143.X2 +1 1 +.names inst_CLK_000_NE.BLIF N_312.BLIF N_309_1 +11 1 +.names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D +1- 1 +-1 1 +.names inst_A0_DMA.BLIF a0_dma_0_un3_n.BLIF a0_dma_0_un0_n +11 1 +.names VPA_D_i.BLIF cpu_est_2_.BLIF N_309_2 +11 1 +.names inst_CLK_000_NE_D0.BLIF cpu_est_0_1__un3_n +0 1 +.names a0_dma_0_un1_n.BLIF a0_dma_0_un0_n.BLIF N_8 +1- 1 +-1 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_0_.C +1 1 +.names N_309_1.BLIF N_309_2.BLIF N_309 +11 1 +.names pos_clk_cpu_est_11_1__n.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_1__un1_n +11 1 +.names N_92.BLIF N_92_i +0 1 +.names cpu_est_0_0_x2_0_.BLIF cpu_est_0_.D +1 1 +.names inst_CLK_000_PE.BLIF N_270_i.BLIF N_308_1 +11 1 +.names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n +11 1 +.names N_245.BLIF dsack1_int_0_un3_n +0 1 +.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D +1 1 +.names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF N_308_2 +11 1 +.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D +1- 1 +-1 1 +.names N_92_i.BLIF N_245.BLIF dsack1_int_0_un1_n +11 1 +.names CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.D +1 1 +.end diff --git a/Logic/BUS68030.bl1 b/Logic/BUS68030.bl1 new file mode 100644 index 0000000..0f57947 --- /dev/null +++ b/Logic/BUS68030.bl1 @@ -0,0 +1,2434 @@ +#$ TOOL ispLEVER Classic 1.8.00.04.29.14 +#$ DATE Wed May 13 22:59:21 2015 +#$ MODULE bus68030 +#$ PINS 75 A_28_ A_27_ SIZE_1_ A_26_ A_25_ A_31_ A_24_ A_23_ IPL_030_2_ A_22_ A_21_ \ +# IPL_2_ A_20_ A_19_ FC_1_ A_18_ AS_030 A_17_ AS_000 A_16_ RW_000 A_15_ DS_030 A_14_ UDS_000 \ +# A_13_ LDS_000 A_12_ A0 A_11_ A1 A_10_ nEXP_SPACE A_9_ BERR A_8_ BG_030 A_7_ BG_000 A_6_ \ +# BGACK_030 A_5_ BGACK_000 A_4_ CLK_030 A_3_ CLK_000 A_2_ CLK_OSZI IPL_030_1_ CLK_DIV_OUT \ +# IPL_030_0_ CLK_EXP IPL_1_ FPU_CS IPL_0_ FPU_SENSE FC_0_ DSACK1 DTACK AVEC E VPA VMA RST \ +# RESET RW AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ +# AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ A_30_ A_29_ +#$ NODES 695 N_310 un1_rst_dly_i_m_i_5__n sm_amiga_srsts_i_0_m2_3__un0_n N_220 \ +# sm_amiga_srsts_i_0_m2_1__un3_n pos_clk_cpu_est_11_1__n un1_rst_dly_i_m_i_6__n \ +# sm_amiga_srsts_i_0_m2_1__un1_n N_14 sm_amiga_srsts_i_0_m2_1__un0_n N_18 \ +# un1_rst_dly_i_m_i_7__n un1_amiga_bus_enable_dma_high_0_m2_0__un3_n N_22 \ +# un1_amiga_bus_enable_dma_high_0_m2_0__un1_n inst_BGACK_030_INTreg \ +# RESET_OUT_0_sqmuxa_1 un1_rst_dly_i_m_i_8__n \ +# un1_amiga_bus_enable_dma_high_0_m2_0__un0_n vcc_n_n N_205 \ +# un1_sm_amiga_7_i_m2_un3_n cpu_est_3_reg N_213 un1_rst_dly_i_m_i_2__n \ +# un1_sm_amiga_7_i_m2_un1_n inst_VMA_INTreg pos_clk_RST_DLY_5_iv_0_x2_0_ \ +# un1_sm_amiga_7_i_m2_un0_n inst_RESET_OUTreg N_105 N_98_i size_dma_0_0__un3_n \ +# gnd_n_n N_98 size_dma_0_0__un1_n un1_amiga_bus_enable_low RESET_OUT_0_sqmuxa \ +# N_105_i size_dma_0_0__un0_n un6_as_030 un1_rst_dly_i_m_2__n size_dma_0_1__un3_n \ +# un3_size G_137 N_22_i size_dma_0_1__un1_n un4_size un1_rst_dly_i_m_8__n N_33_0 \ +# size_dma_0_1__un0_n un5_ciin G_149 N_18_i ipl_030_0_0__un3_n un4_as_000 \ +# RESET_OUT_0_sqmuxa_5 N_37_0 ipl_030_0_0__un1_n un21_fpu_cs RESET_OUT_0_sqmuxa_7 \ +# N_14_i ipl_030_0_0__un0_n un22_berr G_147 N_41_0 ipl_030_0_1__un3_n un6_ds_030 G_145 \ +# N_10_i ipl_030_0_1__un1_n un6_uds_000 N_211 N_44_0 ipl_030_0_1__un0_n un6_lds_000 \ +# G_143 pos_clk_cpu_est_11_0_1__n ipl_030_0_2__un3_n cpu_est_0_ N_209 N_312_i \ +# ipl_030_0_2__un1_n cpu_est_1_ G_141 N_90_i ipl_030_0_2__un0_n inst_AS_000_INT G_139 \ +# N_88_i amiga_bus_enable_dma_high_0_un3_n SM_AMIGA_5_ un1_rst_dly_i_m_7__n N_299_i \ +# amiga_bus_enable_dma_high_0_un1_n inst_AMIGA_BUS_ENABLE_DMA_LOW \ +# un1_rst_dly_i_m_6__n N_275_0 amiga_bus_enable_dma_high_0_un0_n inst_AS_030_D0 \ +# un1_rst_dly_i_m_5__n N_274_0 bg_000_0_un3_n inst_nEXP_SPACE_D0reg \ +# un1_rst_dly_i_m_4__n N_273_i bg_000_0_un1_n inst_DS_030_D0 un1_rst_dly_i_m_3__n \ +# N_272_i bg_000_0_un0_n inst_AS_030_000_SYNC N_71_i N_270_i ds_000_dma_0_un3_n \ +# inst_BGACK_030_INT_D un1_amiga_bus_enable_low_i N_268_i ds_000_dma_0_un1_n \ +# inst_AS_000_DMA un21_fpu_cs_i N_310_i ds_000_dma_0_un0_n inst_DS_000_DMA \ +# RESET_OUT_i N_311_i as_000_dma_0_un3_n CYCLE_DMA_0_ BGACK_030_INT_i N_267_0 \ +# as_000_dma_0_un1_n CYCLE_DMA_1_ RESET_OUT_0_sqmuxa_i N_309_i as_000_dma_0_un0_n \ +# SIZE_DMA_0_ un1_rst_dly_i_3__n N_308_i a0_dma_0_un3_n SIZE_DMA_1_ \ +# un1_rst_dly_i_4__n pos_clk_un7_clk_000_pe_0_n a0_dma_0_un1_n inst_VPA_D \ +# un1_rst_dly_i_5__n N_264_0 a0_dma_0_un0_n inst_UDS_000_INT un1_rst_dly_i_6__n \ +# N_304_i dsack1_int_0_un3_n inst_LDS_000_INT un1_rst_dly_i_7__n N_303_i \ +# dsack1_int_0_un1_n inst_CLK_OUT_PRE_D un1_rst_dly_i_8__n N_186_i \ +# dsack1_int_0_un0_n inst_DTACK_D0 un1_rst_dly_i_2__n VPA_c_i as_000_int_0_un3_n \ +# inst_CLK_OUT_PRE_50 N_87_i_i N_56_0 as_000_int_0_un1_n inst_CLK_000_D1 \ +# cpu_est_i_3__n DTACK_c_i as_000_int_0_un0_n inst_CLK_000_D0 cpu_est_i_0__n N_57_0 \ +# ds_000_enable_0_un3_n inst_CLK_000_PE VPA_D_i N_97_i ds_000_enable_0_un1_n \ +# CLK_000_P_SYNC_9_ VMA_INT_i ds_000_enable_0_un0_n inst_CLK_000_NE cpu_est_i_1__n \ +# N_96_i as_030_000_sync_0_un3_n CLK_000_N_SYNC_11_ CLK_000_PE_i N_95_i \ +# as_030_000_sync_0_un1_n cpu_est_2_ BERR_i N_94_i as_030_000_sync_0_un0_n IPL_D0_0_ \ +# sm_amiga_i_4__n N_313_i lds_000_int_0_un3_n IPL_D0_1_ cpu_est_i_2__n N_136_i \ +# lds_000_int_0_un1_n IPL_D0_2_ sm_amiga_i_5__n N_81_0 lds_000_int_0_un0_n \ +# SM_AMIGA_3_ DTACK_D0_i N_116_i rw_000_dma_0_un3_n inst_CLK_000_NE_D0 \ +# sm_amiga_i_0__n N_77_i rw_000_dma_0_un1_n pos_clk_un6_bg_030_n sm_amiga_i_3__n \ +# N_73_i rw_000_dma_0_un0_n SM_AMIGA_0_ CLK_000_NE_i N_101_i uds_000_int_0_un3_n \ +# inst_AMIGA_BUS_ENABLE_DMA_HIGH sm_amiga_i_6__n uds_000_int_0_un1_n \ +# inst_DSACK1_INTreg sm_amiga_i_1__n clk_000_n_sync_i_10__n uds_000_int_0_un0_n \ +# CLK_OUT_PRE_D_i pos_clk_un9_clk_000_n_sync_i_n amiga_bus_enable_dma_low_0_un3_n \ +# pos_clk_ipl_n pos_clk_un11_clk_000_n_sync_i_n pos_clk_un14_clk_000_n_sync_0_n \ +# amiga_bus_enable_dma_low_0_un1_n pos_clk_un3_ds_030_d0_n LDS_000_i \ +# pos_clk_un22_bgack_030_int_i_n amiga_bus_enable_dma_low_0_un0_n SM_AMIGA_6_ \ +# UDS_000_i N_86_i a_15__n AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa nEXP_SPACE_D0_i N_93_i \ +# RST_DLY_0_ sm_amiga_i_2__n a_14__n RST_DLY_1_ AS_030_i N_99_i RST_DLY_2_ A1_i \ +# pos_clk_size_dma_6_0_1__n a_13__n RST_DLY_3_ CLK_000_D1_i N_100_i RST_DLY_4_ \ +# RW_000_i pos_clk_size_dma_6_0_0__n a_12__n RST_DLY_5_ CLK_030_H_i N_245_0 RST_DLY_6_ \ +# AS_000_DMA_i N_108_i a_11__n RST_DLY_7_ AS_000_i N_109_i pos_clk_un8_bg_030_n \ +# sm_amiga_i_i_7__n N_246_0 a_10__n CLK_000_P_SYNC_0_ RW_i un5_ciin_i \ +# CLK_000_P_SYNC_1_ AMIGA_BUS_ENABLE_DMA_HIGH_i N_247_0 a_9__n CLK_000_P_SYNC_2_ \ +# FPU_SENSE_i N_248_0 CLK_000_P_SYNC_3_ AS_030_D0_i CLK_000_D0_i a_8__n \ +# CLK_000_P_SYNC_4_ a_i_24__n N_249_i CLK_000_P_SYNC_5_ size_dma_i_0__n \ +# AS_030_000_SYNC_i a_7__n CLK_000_P_SYNC_6_ size_dma_i_1__n N_251_0 \ +# CLK_000_P_SYNC_7_ a_i_16__n pos_clk_un3_as_030_d0_i_n a_6__n CLK_000_P_SYNC_8_ \ +# a_i_18__n pos_clk_un5_bgack_030_int_d_i_n CLK_000_N_SYNC_0_ a_i_19__n N_75_i a_5__n \ +# CLK_000_N_SYNC_1_ a_i_31__n N_76_i CLK_000_N_SYNC_2_ a_i_29__n N_78_0 a_4__n \ +# CLK_000_N_SYNC_3_ a_i_30__n N_80_0 CLK_000_N_SYNC_4_ a_i_27__n CLK_EXP_c_i a_3__n \ +# CLK_000_N_SYNC_5_ a_i_28__n N_258_0 CLK_000_N_SYNC_6_ a_i_25__n N_283_i a_2__n \ +# CLK_000_N_SYNC_7_ a_i_26__n N_284_i CLK_000_N_SYNC_8_ UDS_000_INT_i \ +# CLK_000_N_SYNC_9_ LDS_000_INT_i N_290_i CLK_000_N_SYNC_10_ DS_030_i N_291_i \ +# pos_clk_un5_bgack_030_int_d_n N_224_i inst_RW_000_INT N_225_i N_279_i \ +# inst_RW_000_DMA N_226_i N_293_i inst_A0_DMA inst_CLK_030_H N_82_i SM_AMIGA_1_ N_83_i \ +# SM_AMIGA_4_ N_104_i N_259_0 SM_AMIGA_2_ N_103_i N_84_i pos_clk_un3_as_030_d0_n \ +# N_282_i N_115_0 inst_DS_000_ENABLE N_92_i N_85_i AS_000_INT_1_sqmuxa un6_lds_000_i \ +# N_294_i DS_000_ENABLE_1_sqmuxa_1 un6_uds_000_i N_296_i pos_clk_a0_dma_3_n \ +# un6_ds_030_i pos_clk_cpu_est_11_0_3__n pos_clk_ds_000_dma_4_n DS_000_DMA_i N_91_i \ +# N_3 un4_as_000_i N_260_0 AS_000_INT_i N_301_i un6_as_030_i pos_clk_ds_000_dma_4_0_n \ +# N_6 AMIGA_BUS_ENABLE_DMA_LOW_i N_305_i N_8 DS_030_D0_i N_306_i N_9 AS_030_c \ +# AMIGA_BUS_DATA_DIR_c_0 N_10 N_307_i N_11 AS_000_c N_12 N_13 RW_000_c N_15 N_265_0 N_16 \ +# DS_030_c N_269_i N_19 pos_clk_un24_bgack_030_int_i_0_i_n N_20 UDS_000_c N_62_0 N_21 \ +# N_276_0 N_23 LDS_000_c N_277_0 N_24 N_286_i N_25 size_c_0__n N_288_i N_289_i size_c_1__n \ +# pos_clk_un11_ds_030_d0_i_n A0_c_i size_c_i_1__n N_25_i N_32_0 N_24_i N_31_0 N_23_i \ +# N_30_0 ipl_c_i_2__n N_54_0 ipl_c_i_1__n N_53_0 ipl_c_i_0__n N_52_0 nEXP_SPACE_c_i \ +# N_55_0 N_50_0 N_3_i N_49_0 N_6_i N_48_0 N_8_i N_46_0 N_9_i N_45_0 N_12_i SM_AMIGA_i_7_ \ +# N_43_0 N_115 N_13_i pos_clk_size_dma_6_0__n a_c_16__n N_42_0 pos_clk_size_dma_6_1__n \ +# N_15_i pos_clk_cpu_est_11_3__n a_c_17__n N_40_0 G_165 N_16_i G_166 a_c_18__n N_39_0 \ +# G_167 N_19_i un6_uds_000_1 a_c_19__n N_36_0 pos_clk_un24_bgack_030_int_i_0_n N_20_i \ +# N_245 a_c_20__n N_35_0 N_246 N_21_i N_247 a_c_21__n N_34_0 N_248 BG_030_c_i N_89 \ +# a_c_22__n pos_clk_un6_bg_030_i_n N_92 pos_clk_un8_bg_030_0_n N_102 a_c_23__n \ +# N_127_i_1 N_103 N_127_i_2 N_104 a_c_24__n pos_clk_un24_bgack_030_int_i_0_i_1_n N_112 \ +# N_80_0_1 N_256 a_c_25__n N_75_i_1 N_258 N_251_0_1 a_c_26__n \ +# pos_clk_un11_ds_030_d0_i_1_n N_260 N_340_1 N_265 a_c_27__n N_340_2 N_282 N_340_3 N_71 \ +# a_c_28__n N_340_4 cpu_est_0_0_x2_0_ un5_ciin_1 pos_clk_un11_clk_000_n_sync_n \ +# a_c_29__n un5_ciin_2 N_76 un5_ciin_3 pos_clk_CYCLE_DMA_5_1_i_x2 a_c_30__n un5_ciin_4 \ +# pos_clk_CYCLE_DMA_5_0_i_x2 un5_ciin_5 pos_clk_un24_bgack_030_int_i_0_x2 a_c_31__n \ +# un5_ciin_6 pos_clk_un22_bgack_030_int_n un5_ciin_7 N_268 A0_c un5_ciin_8 N_270 \ +# un5_ciin_9 N_73 A1_c un5_ciin_10 N_75 un5_ciin_11 N_251 nEXP_SPACE_c un22_berr_1_0 \ +# un22_berr_1 un21_fpu_cs_1 N_95 BERR_c pos_clk_un6_bg_030_1_n N_94 N_131_i_1 N_288 \ +# BG_030_c N_131_i_2 N_289 N_131_i_3 N_286 BG_000DFFreg N_96_1 N_279 N_96_2 N_277 N_96_3 \ +# N_276 BGACK_000_c pos_clk_cpu_est_11_0_1_1__n N_62 pos_clk_cpu_est_11_0_2_1__n \ +# N_274 N_310_1 N_313 N_310_2 N_307 N_310_3 N_305 CLK_OSZI_c N_310_4 N_306 N_309_1 N_303 \ +# N_309_2 N_304 CLK_EXP_c N_308_1 N_301 N_308_2 N_91 RESET_OUT_0_sqmuxa_5_1 N_85 \ +# FPU_SENSE_c RESET_OUT_0_sqmuxa_7_1 N_294 RESET_OUT_0_sqmuxa_7_2 N_296 \ +# IPL_030DFF_0_reg RESET_OUT_0_sqmuxa_7_3 N_84 N_94_1 N_82 IPL_030DFF_1_reg N_95_1 N_83 \ +# N_119_i_1 N_293 IPL_030DFF_2_reg N_82_1 N_290 N_83_1 N_291 ipl_c_0__n N_296_1 N_283 \ +# N_303_1 N_284 ipl_c_1__n N_304_1 N_86 N_306_1 N_80 ipl_c_2__n N_129_i_1 N_78 N_125_i_1 \ +# N_108 N_123_i_1 N_109 DTACK_c N_115_0_1 N_100 pos_clk_cpu_est_11_0_1_3__n N_99 \ +# N_260_0_1 N_93 N_261_i_1 pos_clk_un14_clk_000_n_sync_n VPA_c N_262_i_1 \ +# pos_clk_un9_clk_000_n_sync_n N_263_i_1 N_340 pos_clk_ipl_1_n N_97 RST_c \ +# cpu_est_0_3__un3_n N_136 cpu_est_0_3__un1_n N_101 cpu_est_0_3__un0_n N_81 RW_c \ +# cpu_est_0_2__un3_n N_116 cpu_est_0_2__un1_n N_96 fc_c_0__n cpu_est_0_2__un0_n N_113 \ +# cpu_est_0_1__un3_n N_275 fc_c_1__n cpu_est_0_1__un1_n N_273 cpu_est_0_1__un0_n N_88 \ +# bgack_030_int_0_un3_n N_272 AMIGA_BUS_DATA_DIR_c bgack_030_int_0_un1_n N_299 \ +# bgack_030_int_0_un0_n N_90 vma_int_0_un3_n N_311 vma_int_0_un1_n N_312 \ +# vma_int_0_un0_n N_267 un1_as_000_i rw_000_int_0_un3_n N_264 un1_rst_dly_i_m_i_3__n \ +# rw_000_int_0_un1_n pos_clk_un7_clk_000_pe_n rw_000_int_0_un0_n N_308 \ +# un1_rst_dly_i_m_i_4__n sm_amiga_srsts_i_0_m2_3__un3_n N_309 \ +# sm_amiga_srsts_i_0_m2_3__un1_n +.model bus68030 +.inputs A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF A1.BLIF nEXP_SPACE.BLIF BG_030.BLIF \ +BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF FPU_SENSE.BLIF \ +DTACK.BLIF VPA.BLIF RST.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF \ +A_26_.BLIF A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF \ +A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF A_15_.BLIF A_14_.BLIF A_13_.BLIF \ +A_12_.BLIF A_11_.BLIF A_10_.BLIF A_9_.BLIF A_8_.BLIF A_7_.BLIF A_6_.BLIF \ +A_5_.BLIF A_4_.BLIF A_3_.BLIF A_2_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF \ +SIZE_1_.BLIF AS_030.BLIF AS_000.BLIF RW_000.BLIF DS_030.BLIF UDS_000.BLIF \ +LDS_000.BLIF A0.BLIF BERR.BLIF RW.BLIF SIZE_0_.BLIF N_310.BLIF \ +un1_rst_dly_i_m_i_5__n.BLIF sm_amiga_srsts_i_0_m2_3__un0_n.BLIF N_220.BLIF \ +sm_amiga_srsts_i_0_m2_1__un3_n.BLIF pos_clk_cpu_est_11_1__n.BLIF \ +un1_rst_dly_i_m_i_6__n.BLIF sm_amiga_srsts_i_0_m2_1__un1_n.BLIF N_14.BLIF \ +sm_amiga_srsts_i_0_m2_1__un0_n.BLIF N_18.BLIF un1_rst_dly_i_m_i_7__n.BLIF \ +un1_amiga_bus_enable_dma_high_0_m2_0__un3_n.BLIF N_22.BLIF \ +un1_amiga_bus_enable_dma_high_0_m2_0__un1_n.BLIF inst_BGACK_030_INTreg.BLIF \ +RESET_OUT_0_sqmuxa_1.BLIF un1_rst_dly_i_m_i_8__n.BLIF \ +un1_amiga_bus_enable_dma_high_0_m2_0__un0_n.BLIF vcc_n_n.BLIF N_205.BLIF \ +un1_sm_amiga_7_i_m2_un3_n.BLIF cpu_est_3_reg.BLIF N_213.BLIF \ +un1_rst_dly_i_m_i_2__n.BLIF un1_sm_amiga_7_i_m2_un1_n.BLIF \ +inst_VMA_INTreg.BLIF pos_clk_RST_DLY_5_iv_0_x2_0_.BLIF \ +un1_sm_amiga_7_i_m2_un0_n.BLIF inst_RESET_OUTreg.BLIF N_105.BLIF N_98_i.BLIF \ +size_dma_0_0__un3_n.BLIF gnd_n_n.BLIF N_98.BLIF size_dma_0_0__un1_n.BLIF \ +un1_amiga_bus_enable_low.BLIF RESET_OUT_0_sqmuxa.BLIF N_105_i.BLIF \ +size_dma_0_0__un0_n.BLIF un6_as_030.BLIF un1_rst_dly_i_m_2__n.BLIF \ +size_dma_0_1__un3_n.BLIF un3_size.BLIF G_137.BLIF N_22_i.BLIF \ +size_dma_0_1__un1_n.BLIF un4_size.BLIF un1_rst_dly_i_m_8__n.BLIF N_33_0.BLIF \ +size_dma_0_1__un0_n.BLIF un5_ciin.BLIF G_149.BLIF N_18_i.BLIF \ +ipl_030_0_0__un3_n.BLIF un4_as_000.BLIF RESET_OUT_0_sqmuxa_5.BLIF N_37_0.BLIF \ +ipl_030_0_0__un1_n.BLIF un21_fpu_cs.BLIF RESET_OUT_0_sqmuxa_7.BLIF N_14_i.BLIF \ +ipl_030_0_0__un0_n.BLIF un22_berr.BLIF G_147.BLIF N_41_0.BLIF \ +ipl_030_0_1__un3_n.BLIF un6_ds_030.BLIF G_145.BLIF N_10_i.BLIF \ +ipl_030_0_1__un1_n.BLIF un6_uds_000.BLIF N_211.BLIF N_44_0.BLIF \ +ipl_030_0_1__un0_n.BLIF un6_lds_000.BLIF G_143.BLIF \ +pos_clk_cpu_est_11_0_1__n.BLIF ipl_030_0_2__un3_n.BLIF cpu_est_0_.BLIF \ +N_209.BLIF N_312_i.BLIF ipl_030_0_2__un1_n.BLIF cpu_est_1_.BLIF G_141.BLIF \ +N_90_i.BLIF ipl_030_0_2__un0_n.BLIF inst_AS_000_INT.BLIF G_139.BLIF \ +N_88_i.BLIF amiga_bus_enable_dma_high_0_un3_n.BLIF SM_AMIGA_5_.BLIF \ +un1_rst_dly_i_m_7__n.BLIF N_299_i.BLIF amiga_bus_enable_dma_high_0_un1_n.BLIF \ +inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF un1_rst_dly_i_m_6__n.BLIF N_275_0.BLIF \ +amiga_bus_enable_dma_high_0_un0_n.BLIF inst_AS_030_D0.BLIF \ +un1_rst_dly_i_m_5__n.BLIF N_274_0.BLIF bg_000_0_un3_n.BLIF \ +inst_nEXP_SPACE_D0reg.BLIF un1_rst_dly_i_m_4__n.BLIF N_273_i.BLIF \ +bg_000_0_un1_n.BLIF inst_DS_030_D0.BLIF un1_rst_dly_i_m_3__n.BLIF N_272_i.BLIF \ +bg_000_0_un0_n.BLIF inst_AS_030_000_SYNC.BLIF N_71_i.BLIF N_270_i.BLIF \ +ds_000_dma_0_un3_n.BLIF inst_BGACK_030_INT_D.BLIF \ +un1_amiga_bus_enable_low_i.BLIF N_268_i.BLIF ds_000_dma_0_un1_n.BLIF \ +inst_AS_000_DMA.BLIF un21_fpu_cs_i.BLIF N_310_i.BLIF ds_000_dma_0_un0_n.BLIF \ +inst_DS_000_DMA.BLIF RESET_OUT_i.BLIF N_311_i.BLIF as_000_dma_0_un3_n.BLIF \ +CYCLE_DMA_0_.BLIF BGACK_030_INT_i.BLIF N_267_0.BLIF as_000_dma_0_un1_n.BLIF \ +CYCLE_DMA_1_.BLIF RESET_OUT_0_sqmuxa_i.BLIF N_309_i.BLIF \ +as_000_dma_0_un0_n.BLIF SIZE_DMA_0_.BLIF un1_rst_dly_i_3__n.BLIF N_308_i.BLIF \ +a0_dma_0_un3_n.BLIF SIZE_DMA_1_.BLIF un1_rst_dly_i_4__n.BLIF \ +pos_clk_un7_clk_000_pe_0_n.BLIF a0_dma_0_un1_n.BLIF inst_VPA_D.BLIF \ +un1_rst_dly_i_5__n.BLIF N_264_0.BLIF a0_dma_0_un0_n.BLIF inst_UDS_000_INT.BLIF \ +un1_rst_dly_i_6__n.BLIF N_304_i.BLIF dsack1_int_0_un3_n.BLIF \ +inst_LDS_000_INT.BLIF un1_rst_dly_i_7__n.BLIF N_303_i.BLIF \ +dsack1_int_0_un1_n.BLIF inst_CLK_OUT_PRE_D.BLIF un1_rst_dly_i_8__n.BLIF \ +N_186_i.BLIF dsack1_int_0_un0_n.BLIF inst_DTACK_D0.BLIF \ +un1_rst_dly_i_2__n.BLIF VPA_c_i.BLIF as_000_int_0_un3_n.BLIF \ +inst_CLK_OUT_PRE_50.BLIF N_87_i_i.BLIF N_56_0.BLIF as_000_int_0_un1_n.BLIF \ +inst_CLK_000_D1.BLIF cpu_est_i_3__n.BLIF DTACK_c_i.BLIF \ +as_000_int_0_un0_n.BLIF inst_CLK_000_D0.BLIF cpu_est_i_0__n.BLIF N_57_0.BLIF \ +ds_000_enable_0_un3_n.BLIF inst_CLK_000_PE.BLIF VPA_D_i.BLIF N_97_i.BLIF \ +ds_000_enable_0_un1_n.BLIF CLK_000_P_SYNC_9_.BLIF VMA_INT_i.BLIF \ +ds_000_enable_0_un0_n.BLIF inst_CLK_000_NE.BLIF cpu_est_i_1__n.BLIF \ +N_96_i.BLIF as_030_000_sync_0_un3_n.BLIF CLK_000_N_SYNC_11_.BLIF \ +CLK_000_PE_i.BLIF N_95_i.BLIF as_030_000_sync_0_un1_n.BLIF cpu_est_2_.BLIF \ +BERR_i.BLIF N_94_i.BLIF as_030_000_sync_0_un0_n.BLIF IPL_D0_0_.BLIF \ +sm_amiga_i_4__n.BLIF N_313_i.BLIF lds_000_int_0_un3_n.BLIF IPL_D0_1_.BLIF \ +cpu_est_i_2__n.BLIF N_136_i.BLIF lds_000_int_0_un1_n.BLIF IPL_D0_2_.BLIF \ +sm_amiga_i_5__n.BLIF N_81_0.BLIF lds_000_int_0_un0_n.BLIF SM_AMIGA_3_.BLIF \ +DTACK_D0_i.BLIF N_116_i.BLIF rw_000_dma_0_un3_n.BLIF inst_CLK_000_NE_D0.BLIF \ +sm_amiga_i_0__n.BLIF N_77_i.BLIF rw_000_dma_0_un1_n.BLIF \ +pos_clk_un6_bg_030_n.BLIF sm_amiga_i_3__n.BLIF N_73_i.BLIF \ +rw_000_dma_0_un0_n.BLIF SM_AMIGA_0_.BLIF CLK_000_NE_i.BLIF N_101_i.BLIF \ +uds_000_int_0_un3_n.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ +sm_amiga_i_6__n.BLIF uds_000_int_0_un1_n.BLIF inst_DSACK1_INTreg.BLIF \ +sm_amiga_i_1__n.BLIF clk_000_n_sync_i_10__n.BLIF uds_000_int_0_un0_n.BLIF \ +CLK_OUT_PRE_D_i.BLIF pos_clk_un9_clk_000_n_sync_i_n.BLIF \ +amiga_bus_enable_dma_low_0_un3_n.BLIF pos_clk_ipl_n.BLIF \ +pos_clk_un11_clk_000_n_sync_i_n.BLIF pos_clk_un14_clk_000_n_sync_0_n.BLIF \ +amiga_bus_enable_dma_low_0_un1_n.BLIF pos_clk_un3_ds_030_d0_n.BLIF \ +LDS_000_i.BLIF pos_clk_un22_bgack_030_int_i_n.BLIF \ +amiga_bus_enable_dma_low_0_un0_n.BLIF SM_AMIGA_6_.BLIF UDS_000_i.BLIF \ +N_86_i.BLIF a_15__n.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa.BLIF \ +nEXP_SPACE_D0_i.BLIF N_93_i.BLIF RST_DLY_0_.BLIF sm_amiga_i_2__n.BLIF \ +a_14__n.BLIF RST_DLY_1_.BLIF AS_030_i.BLIF N_99_i.BLIF RST_DLY_2_.BLIF \ +A1_i.BLIF pos_clk_size_dma_6_0_1__n.BLIF a_13__n.BLIF RST_DLY_3_.BLIF \ +CLK_000_D1_i.BLIF N_100_i.BLIF RST_DLY_4_.BLIF RW_000_i.BLIF \ +pos_clk_size_dma_6_0_0__n.BLIF a_12__n.BLIF RST_DLY_5_.BLIF CLK_030_H_i.BLIF \ +N_245_0.BLIF RST_DLY_6_.BLIF AS_000_DMA_i.BLIF N_108_i.BLIF a_11__n.BLIF \ +RST_DLY_7_.BLIF AS_000_i.BLIF N_109_i.BLIF pos_clk_un8_bg_030_n.BLIF \ +sm_amiga_i_i_7__n.BLIF N_246_0.BLIF a_10__n.BLIF CLK_000_P_SYNC_0_.BLIF \ +RW_i.BLIF un5_ciin_i.BLIF CLK_000_P_SYNC_1_.BLIF \ +AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF N_247_0.BLIF a_9__n.BLIF \ +CLK_000_P_SYNC_2_.BLIF FPU_SENSE_i.BLIF N_248_0.BLIF CLK_000_P_SYNC_3_.BLIF \ +AS_030_D0_i.BLIF CLK_000_D0_i.BLIF a_8__n.BLIF CLK_000_P_SYNC_4_.BLIF \ +a_i_24__n.BLIF N_249_i.BLIF CLK_000_P_SYNC_5_.BLIF size_dma_i_0__n.BLIF \ +AS_030_000_SYNC_i.BLIF a_7__n.BLIF CLK_000_P_SYNC_6_.BLIF size_dma_i_1__n.BLIF \ +N_251_0.BLIF CLK_000_P_SYNC_7_.BLIF a_i_16__n.BLIF \ +pos_clk_un3_as_030_d0_i_n.BLIF a_6__n.BLIF CLK_000_P_SYNC_8_.BLIF \ +a_i_18__n.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF CLK_000_N_SYNC_0_.BLIF \ +a_i_19__n.BLIF N_75_i.BLIF a_5__n.BLIF CLK_000_N_SYNC_1_.BLIF a_i_31__n.BLIF \ +N_76_i.BLIF CLK_000_N_SYNC_2_.BLIF a_i_29__n.BLIF N_78_0.BLIF a_4__n.BLIF \ +CLK_000_N_SYNC_3_.BLIF a_i_30__n.BLIF N_80_0.BLIF CLK_000_N_SYNC_4_.BLIF \ +a_i_27__n.BLIF CLK_EXP_c_i.BLIF a_3__n.BLIF CLK_000_N_SYNC_5_.BLIF \ +a_i_28__n.BLIF N_258_0.BLIF CLK_000_N_SYNC_6_.BLIF a_i_25__n.BLIF N_283_i.BLIF \ +a_2__n.BLIF CLK_000_N_SYNC_7_.BLIF a_i_26__n.BLIF N_284_i.BLIF \ +CLK_000_N_SYNC_8_.BLIF UDS_000_INT_i.BLIF CLK_000_N_SYNC_9_.BLIF \ +LDS_000_INT_i.BLIF N_290_i.BLIF CLK_000_N_SYNC_10_.BLIF DS_030_i.BLIF \ +N_291_i.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF N_224_i.BLIF \ +inst_RW_000_INT.BLIF N_225_i.BLIF N_279_i.BLIF inst_RW_000_DMA.BLIF \ +N_226_i.BLIF N_293_i.BLIF inst_A0_DMA.BLIF inst_CLK_030_H.BLIF N_82_i.BLIF \ +SM_AMIGA_1_.BLIF N_83_i.BLIF SM_AMIGA_4_.BLIF N_104_i.BLIF N_259_0.BLIF \ +SM_AMIGA_2_.BLIF N_103_i.BLIF N_84_i.BLIF pos_clk_un3_as_030_d0_n.BLIF \ +N_282_i.BLIF N_115_0.BLIF inst_DS_000_ENABLE.BLIF N_92_i.BLIF N_85_i.BLIF \ +AS_000_INT_1_sqmuxa.BLIF un6_lds_000_i.BLIF N_294_i.BLIF \ +DS_000_ENABLE_1_sqmuxa_1.BLIF un6_uds_000_i.BLIF N_296_i.BLIF \ +pos_clk_a0_dma_3_n.BLIF un6_ds_030_i.BLIF pos_clk_cpu_est_11_0_3__n.BLIF \ +pos_clk_ds_000_dma_4_n.BLIF DS_000_DMA_i.BLIF N_91_i.BLIF N_3.BLIF \ +un4_as_000_i.BLIF N_260_0.BLIF AS_000_INT_i.BLIF N_301_i.BLIF \ +un6_as_030_i.BLIF pos_clk_ds_000_dma_4_0_n.BLIF N_6.BLIF \ +AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF N_305_i.BLIF N_8.BLIF DS_030_D0_i.BLIF \ +N_306_i.BLIF N_9.BLIF AS_030_c.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF N_10.BLIF \ +N_307_i.BLIF N_11.BLIF AS_000_c.BLIF N_12.BLIF N_13.BLIF RW_000_c.BLIF \ +N_15.BLIF N_265_0.BLIF N_16.BLIF DS_030_c.BLIF N_269_i.BLIF N_19.BLIF \ +pos_clk_un24_bgack_030_int_i_0_i_n.BLIF N_20.BLIF UDS_000_c.BLIF N_62_0.BLIF \ +N_21.BLIF N_276_0.BLIF N_23.BLIF LDS_000_c.BLIF N_277_0.BLIF N_24.BLIF \ +N_286_i.BLIF N_25.BLIF size_c_0__n.BLIF N_288_i.BLIF N_289_i.BLIF \ +size_c_1__n.BLIF pos_clk_un11_ds_030_d0_i_n.BLIF A0_c_i.BLIF \ +size_c_i_1__n.BLIF N_25_i.BLIF N_32_0.BLIF N_24_i.BLIF N_31_0.BLIF N_23_i.BLIF \ +N_30_0.BLIF ipl_c_i_2__n.BLIF N_54_0.BLIF ipl_c_i_1__n.BLIF N_53_0.BLIF \ +ipl_c_i_0__n.BLIF N_52_0.BLIF nEXP_SPACE_c_i.BLIF N_55_0.BLIF N_50_0.BLIF \ +N_3_i.BLIF N_49_0.BLIF N_6_i.BLIF N_48_0.BLIF N_8_i.BLIF N_46_0.BLIF \ +N_9_i.BLIF N_45_0.BLIF N_12_i.BLIF SM_AMIGA_i_7_.BLIF N_43_0.BLIF N_115.BLIF \ +N_13_i.BLIF pos_clk_size_dma_6_0__n.BLIF a_c_16__n.BLIF N_42_0.BLIF \ +pos_clk_size_dma_6_1__n.BLIF N_15_i.BLIF pos_clk_cpu_est_11_3__n.BLIF \ +a_c_17__n.BLIF N_40_0.BLIF G_165.BLIF N_16_i.BLIF G_166.BLIF a_c_18__n.BLIF \ +N_39_0.BLIF G_167.BLIF N_19_i.BLIF un6_uds_000_1.BLIF a_c_19__n.BLIF \ +N_36_0.BLIF pos_clk_un24_bgack_030_int_i_0_n.BLIF N_20_i.BLIF N_245.BLIF \ +a_c_20__n.BLIF N_35_0.BLIF N_246.BLIF N_21_i.BLIF N_247.BLIF a_c_21__n.BLIF \ +N_34_0.BLIF N_248.BLIF BG_030_c_i.BLIF N_89.BLIF a_c_22__n.BLIF \ +pos_clk_un6_bg_030_i_n.BLIF N_92.BLIF pos_clk_un8_bg_030_0_n.BLIF N_102.BLIF \ +a_c_23__n.BLIF N_127_i_1.BLIF N_103.BLIF N_127_i_2.BLIF N_104.BLIF \ +a_c_24__n.BLIF pos_clk_un24_bgack_030_int_i_0_i_1_n.BLIF N_112.BLIF \ +N_80_0_1.BLIF N_256.BLIF a_c_25__n.BLIF N_75_i_1.BLIF N_258.BLIF \ +N_251_0_1.BLIF a_c_26__n.BLIF pos_clk_un11_ds_030_d0_i_1_n.BLIF N_260.BLIF \ +N_340_1.BLIF N_265.BLIF a_c_27__n.BLIF N_340_2.BLIF N_282.BLIF N_340_3.BLIF \ +N_71.BLIF a_c_28__n.BLIF N_340_4.BLIF cpu_est_0_0_x2_0_.BLIF un5_ciin_1.BLIF \ +pos_clk_un11_clk_000_n_sync_n.BLIF a_c_29__n.BLIF un5_ciin_2.BLIF N_76.BLIF \ +un5_ciin_3.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.BLIF a_c_30__n.BLIF un5_ciin_4.BLIF \ +pos_clk_CYCLE_DMA_5_0_i_x2.BLIF un5_ciin_5.BLIF \ +pos_clk_un24_bgack_030_int_i_0_x2.BLIF a_c_31__n.BLIF un5_ciin_6.BLIF \ +pos_clk_un22_bgack_030_int_n.BLIF un5_ciin_7.BLIF N_268.BLIF A0_c.BLIF \ +un5_ciin_8.BLIF N_270.BLIF un5_ciin_9.BLIF N_73.BLIF A1_c.BLIF \ +un5_ciin_10.BLIF N_75.BLIF un5_ciin_11.BLIF N_251.BLIF nEXP_SPACE_c.BLIF \ +un22_berr_1_0.BLIF un22_berr_1.BLIF un21_fpu_cs_1.BLIF N_95.BLIF BERR_c.BLIF \ +pos_clk_un6_bg_030_1_n.BLIF N_94.BLIF N_131_i_1.BLIF N_288.BLIF BG_030_c.BLIF \ +N_131_i_2.BLIF N_289.BLIF N_131_i_3.BLIF N_286.BLIF BG_000DFFreg.BLIF \ +N_96_1.BLIF N_279.BLIF N_96_2.BLIF N_277.BLIF N_96_3.BLIF N_276.BLIF \ +BGACK_000_c.BLIF pos_clk_cpu_est_11_0_1_1__n.BLIF N_62.BLIF \ +pos_clk_cpu_est_11_0_2_1__n.BLIF N_274.BLIF N_310_1.BLIF N_313.BLIF \ +N_310_2.BLIF N_307.BLIF N_310_3.BLIF N_305.BLIF CLK_OSZI_c.BLIF N_310_4.BLIF \ +N_306.BLIF N_309_1.BLIF N_303.BLIF N_309_2.BLIF N_304.BLIF CLK_EXP_c.BLIF \ +N_308_1.BLIF N_301.BLIF N_308_2.BLIF N_91.BLIF RESET_OUT_0_sqmuxa_5_1.BLIF \ +N_85.BLIF FPU_SENSE_c.BLIF RESET_OUT_0_sqmuxa_7_1.BLIF N_294.BLIF \ +RESET_OUT_0_sqmuxa_7_2.BLIF N_296.BLIF IPL_030DFF_0_reg.BLIF \ +RESET_OUT_0_sqmuxa_7_3.BLIF N_84.BLIF N_94_1.BLIF N_82.BLIF \ +IPL_030DFF_1_reg.BLIF N_95_1.BLIF N_83.BLIF N_119_i_1.BLIF N_293.BLIF \ +IPL_030DFF_2_reg.BLIF N_82_1.BLIF N_290.BLIF N_83_1.BLIF N_291.BLIF \ +ipl_c_0__n.BLIF N_296_1.BLIF N_283.BLIF N_303_1.BLIF N_284.BLIF \ +ipl_c_1__n.BLIF N_304_1.BLIF N_86.BLIF N_306_1.BLIF N_80.BLIF ipl_c_2__n.BLIF \ +N_129_i_1.BLIF N_78.BLIF N_125_i_1.BLIF N_108.BLIF N_123_i_1.BLIF N_109.BLIF \ +DTACK_c.BLIF N_115_0_1.BLIF N_100.BLIF pos_clk_cpu_est_11_0_1_3__n.BLIF \ +N_99.BLIF N_260_0_1.BLIF N_93.BLIF N_261_i_1.BLIF \ +pos_clk_un14_clk_000_n_sync_n.BLIF VPA_c.BLIF N_262_i_1.BLIF \ +pos_clk_un9_clk_000_n_sync_n.BLIF N_263_i_1.BLIF N_340.BLIF \ +pos_clk_ipl_1_n.BLIF N_97.BLIF RST_c.BLIF cpu_est_0_3__un3_n.BLIF N_136.BLIF \ +cpu_est_0_3__un1_n.BLIF N_101.BLIF cpu_est_0_3__un0_n.BLIF N_81.BLIF RW_c.BLIF \ +cpu_est_0_2__un3_n.BLIF N_116.BLIF cpu_est_0_2__un1_n.BLIF N_96.BLIF \ +fc_c_0__n.BLIF cpu_est_0_2__un0_n.BLIF N_113.BLIF cpu_est_0_1__un3_n.BLIF \ +N_275.BLIF fc_c_1__n.BLIF cpu_est_0_1__un1_n.BLIF N_273.BLIF \ +cpu_est_0_1__un0_n.BLIF N_88.BLIF bgack_030_int_0_un3_n.BLIF N_272.BLIF \ +AMIGA_BUS_DATA_DIR_c.BLIF bgack_030_int_0_un1_n.BLIF N_299.BLIF \ +bgack_030_int_0_un0_n.BLIF N_90.BLIF vma_int_0_un3_n.BLIF N_311.BLIF \ +vma_int_0_un1_n.BLIF N_312.BLIF vma_int_0_un0_n.BLIF N_267.BLIF \ +un1_as_000_i.BLIF rw_000_int_0_un3_n.BLIF N_264.BLIF \ +un1_rst_dly_i_m_i_3__n.BLIF rw_000_int_0_un1_n.BLIF \ +pos_clk_un7_clk_000_pe_n.BLIF rw_000_int_0_un0_n.BLIF N_308.BLIF \ +un1_rst_dly_i_m_i_4__n.BLIF sm_amiga_srsts_i_0_m2_3__un3_n.BLIF N_309.BLIF \ +sm_amiga_srsts_i_0_m2_3__un1_n.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF \ +RW_000.PIN.BLIF DS_030.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF \ +SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF A0.PIN.BLIF BERR.PIN.BLIF RW.PIN.BLIF +.outputs IPL_030_2_ BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 AVEC E \ +VMA RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ +AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ IPL_030DFF_2_reg.D \ +IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D \ +IPL_D0_2_.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C \ +SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.D \ +SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C \ +SM_AMIGA_0_.D SM_AMIGA_0_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D \ +cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_reg.D cpu_est_3_reg.C \ +IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C \ +CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.D \ +CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C RST_DLY_0_.D \ +RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C RST_DLY_3_.D \ +RST_DLY_3_.C RST_DLY_4_.D RST_DLY_4_.C RST_DLY_5_.D RST_DLY_5_.C RST_DLY_6_.D \ +RST_DLY_6_.C RST_DLY_7_.D RST_DLY_7_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C \ +CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D \ +SIZE_DMA_1_.C CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D \ +CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C \ +CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.D \ +CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C \ +CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.D \ +CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C \ +CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.D \ +CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_6_.C \ +CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.D \ +CLK_000_N_SYNC_8_.C CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C \ +CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.D \ +CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C \ +CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C inst_CLK_030_H.D inst_CLK_030_H.C \ +inst_RESET_OUTreg.D inst_RESET_OUTreg.C inst_DS_000_ENABLE.D \ +inst_DS_000_ENABLE.C inst_UDS_000_INT.D inst_UDS_000_INT.C inst_RW_000_DMA.D \ +inst_RW_000_DMA.C inst_RW_000_INT.D inst_RW_000_INT.C inst_LDS_000_INT.D \ +inst_LDS_000_INT.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \ +inst_AS_000_INT.D inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C \ +inst_A0_DMA.D inst_A0_DMA.C inst_AS_000_DMA.D inst_AS_000_DMA.C \ +inst_DS_000_DMA.D inst_DS_000_DMA.C inst_DS_030_D0.D inst_DS_030_D0.C \ +inst_AS_030_D0.D inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.D \ +inst_nEXP_SPACE_D0reg.C inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D \ +inst_DTACK_D0.C inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C BG_000DFFreg.D \ +BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D \ +inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D \ +inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_VMA_INTreg.D inst_VMA_INTreg.C \ +inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_CLK_000_PE.D \ +inst_CLK_000_PE.C inst_CLK_000_NE.D inst_CLK_000_NE.C inst_CLK_OUT_PRE_50.D \ +inst_CLK_OUT_PRE_50.C inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_NE_D0.D \ +inst_CLK_000_NE_D0.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C \ +inst_CLK_000_D0.D inst_CLK_000_D0.C SIZE_1_ AS_030 AS_000 RW_000 DS_030 \ +UDS_000 LDS_000 A0 BERR RW SIZE_0_ N_310 un1_rst_dly_i_m_i_5__n \ +sm_amiga_srsts_i_0_m2_3__un0_n N_220 sm_amiga_srsts_i_0_m2_1__un3_n \ +pos_clk_cpu_est_11_1__n un1_rst_dly_i_m_i_6__n sm_amiga_srsts_i_0_m2_1__un1_n \ +N_14 sm_amiga_srsts_i_0_m2_1__un0_n N_18 un1_rst_dly_i_m_i_7__n \ +un1_amiga_bus_enable_dma_high_0_m2_0__un3_n N_22 \ +un1_amiga_bus_enable_dma_high_0_m2_0__un1_n RESET_OUT_0_sqmuxa_1 \ +un1_rst_dly_i_m_i_8__n un1_amiga_bus_enable_dma_high_0_m2_0__un0_n vcc_n_n \ +N_205 un1_sm_amiga_7_i_m2_un3_n N_213 un1_rst_dly_i_m_i_2__n \ +un1_sm_amiga_7_i_m2_un1_n un1_sm_amiga_7_i_m2_un0_n N_105 N_98_i \ +size_dma_0_0__un3_n gnd_n_n N_98 size_dma_0_0__un1_n un1_amiga_bus_enable_low \ +RESET_OUT_0_sqmuxa N_105_i size_dma_0_0__un0_n un6_as_030 un1_rst_dly_i_m_2__n \ +size_dma_0_1__un3_n un3_size N_22_i size_dma_0_1__un1_n un4_size \ +un1_rst_dly_i_m_8__n N_33_0 size_dma_0_1__un0_n un5_ciin N_18_i \ +ipl_030_0_0__un3_n un4_as_000 RESET_OUT_0_sqmuxa_5 N_37_0 ipl_030_0_0__un1_n \ +un21_fpu_cs RESET_OUT_0_sqmuxa_7 N_14_i ipl_030_0_0__un0_n un22_berr N_41_0 \ +ipl_030_0_1__un3_n un6_ds_030 N_10_i ipl_030_0_1__un1_n un6_uds_000 N_211 \ +N_44_0 ipl_030_0_1__un0_n un6_lds_000 pos_clk_cpu_est_11_0_1__n \ +ipl_030_0_2__un3_n N_209 N_312_i ipl_030_0_2__un1_n N_90_i ipl_030_0_2__un0_n \ +N_88_i amiga_bus_enable_dma_high_0_un3_n un1_rst_dly_i_m_7__n N_299_i \ +amiga_bus_enable_dma_high_0_un1_n un1_rst_dly_i_m_6__n N_275_0 \ +amiga_bus_enable_dma_high_0_un0_n un1_rst_dly_i_m_5__n N_274_0 bg_000_0_un3_n \ +un1_rst_dly_i_m_4__n N_273_i bg_000_0_un1_n un1_rst_dly_i_m_3__n N_272_i \ +bg_000_0_un0_n N_71_i N_270_i ds_000_dma_0_un3_n un1_amiga_bus_enable_low_i \ +N_268_i ds_000_dma_0_un1_n un21_fpu_cs_i N_310_i ds_000_dma_0_un0_n \ +RESET_OUT_i N_311_i as_000_dma_0_un3_n BGACK_030_INT_i N_267_0 \ +as_000_dma_0_un1_n RESET_OUT_0_sqmuxa_i N_309_i as_000_dma_0_un0_n \ +un1_rst_dly_i_3__n N_308_i a0_dma_0_un3_n un1_rst_dly_i_4__n \ +pos_clk_un7_clk_000_pe_0_n a0_dma_0_un1_n un1_rst_dly_i_5__n N_264_0 \ +a0_dma_0_un0_n un1_rst_dly_i_6__n N_304_i dsack1_int_0_un3_n \ +un1_rst_dly_i_7__n N_303_i dsack1_int_0_un1_n un1_rst_dly_i_8__n N_186_i \ +dsack1_int_0_un0_n un1_rst_dly_i_2__n VPA_c_i as_000_int_0_un3_n N_87_i_i \ +N_56_0 as_000_int_0_un1_n cpu_est_i_3__n DTACK_c_i as_000_int_0_un0_n \ +cpu_est_i_0__n N_57_0 ds_000_enable_0_un3_n VPA_D_i N_97_i \ +ds_000_enable_0_un1_n VMA_INT_i ds_000_enable_0_un0_n cpu_est_i_1__n N_96_i \ +as_030_000_sync_0_un3_n CLK_000_PE_i N_95_i as_030_000_sync_0_un1_n BERR_i \ +N_94_i as_030_000_sync_0_un0_n sm_amiga_i_4__n N_313_i lds_000_int_0_un3_n \ +cpu_est_i_2__n N_136_i lds_000_int_0_un1_n sm_amiga_i_5__n N_81_0 \ +lds_000_int_0_un0_n DTACK_D0_i N_116_i rw_000_dma_0_un3_n sm_amiga_i_0__n \ +N_77_i rw_000_dma_0_un1_n pos_clk_un6_bg_030_n sm_amiga_i_3__n N_73_i \ +rw_000_dma_0_un0_n CLK_000_NE_i N_101_i uds_000_int_0_un3_n sm_amiga_i_6__n \ +uds_000_int_0_un1_n sm_amiga_i_1__n clk_000_n_sync_i_10__n uds_000_int_0_un0_n \ +CLK_OUT_PRE_D_i pos_clk_un9_clk_000_n_sync_i_n \ +amiga_bus_enable_dma_low_0_un3_n pos_clk_ipl_n pos_clk_un11_clk_000_n_sync_i_n \ +pos_clk_un14_clk_000_n_sync_0_n amiga_bus_enable_dma_low_0_un1_n \ +pos_clk_un3_ds_030_d0_n LDS_000_i pos_clk_un22_bgack_030_int_i_n \ +amiga_bus_enable_dma_low_0_un0_n UDS_000_i N_86_i a_15__n \ +AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa nEXP_SPACE_D0_i N_93_i sm_amiga_i_2__n \ +a_14__n AS_030_i N_99_i A1_i pos_clk_size_dma_6_0_1__n a_13__n CLK_000_D1_i \ +N_100_i RW_000_i pos_clk_size_dma_6_0_0__n a_12__n CLK_030_H_i N_245_0 \ +AS_000_DMA_i N_108_i a_11__n AS_000_i N_109_i pos_clk_un8_bg_030_n \ +sm_amiga_i_i_7__n N_246_0 a_10__n RW_i un5_ciin_i AMIGA_BUS_ENABLE_DMA_HIGH_i \ +N_247_0 a_9__n FPU_SENSE_i N_248_0 AS_030_D0_i CLK_000_D0_i a_8__n a_i_24__n \ +N_249_i size_dma_i_0__n AS_030_000_SYNC_i a_7__n size_dma_i_1__n N_251_0 \ +a_i_16__n pos_clk_un3_as_030_d0_i_n a_6__n a_i_18__n \ +pos_clk_un5_bgack_030_int_d_i_n a_i_19__n N_75_i a_5__n a_i_31__n N_76_i \ +a_i_29__n N_78_0 a_4__n a_i_30__n N_80_0 a_i_27__n CLK_EXP_c_i a_3__n \ +a_i_28__n N_258_0 a_i_25__n N_283_i a_2__n a_i_26__n N_284_i UDS_000_INT_i \ +LDS_000_INT_i N_290_i DS_030_i N_291_i pos_clk_un5_bgack_030_int_d_n N_224_i \ +N_225_i N_279_i N_226_i N_293_i N_82_i N_83_i N_104_i N_259_0 N_103_i N_84_i \ +pos_clk_un3_as_030_d0_n N_282_i N_115_0 N_92_i N_85_i AS_000_INT_1_sqmuxa \ +un6_lds_000_i N_294_i DS_000_ENABLE_1_sqmuxa_1 un6_uds_000_i N_296_i \ +pos_clk_a0_dma_3_n un6_ds_030_i pos_clk_cpu_est_11_0_3__n \ +pos_clk_ds_000_dma_4_n DS_000_DMA_i N_91_i N_3 un4_as_000_i N_260_0 \ +AS_000_INT_i N_301_i un6_as_030_i pos_clk_ds_000_dma_4_0_n N_6 \ +AMIGA_BUS_ENABLE_DMA_LOW_i N_305_i N_8 DS_030_D0_i N_306_i N_9 AS_030_c \ +AMIGA_BUS_DATA_DIR_c_0 N_10 N_307_i N_11 AS_000_c N_12 N_13 RW_000_c N_15 \ +N_265_0 N_16 DS_030_c N_269_i N_19 pos_clk_un24_bgack_030_int_i_0_i_n N_20 \ +UDS_000_c N_62_0 N_21 N_276_0 N_23 LDS_000_c N_277_0 N_24 N_286_i N_25 \ +size_c_0__n N_288_i N_289_i size_c_1__n pos_clk_un11_ds_030_d0_i_n A0_c_i \ +size_c_i_1__n N_25_i N_32_0 N_24_i N_31_0 N_23_i N_30_0 ipl_c_i_2__n N_54_0 \ +ipl_c_i_1__n N_53_0 ipl_c_i_0__n N_52_0 nEXP_SPACE_c_i N_55_0 N_50_0 N_3_i \ +N_49_0 N_6_i N_48_0 N_8_i N_46_0 N_9_i N_45_0 N_12_i N_43_0 N_115 N_13_i \ +pos_clk_size_dma_6_0__n a_c_16__n N_42_0 pos_clk_size_dma_6_1__n N_15_i \ +pos_clk_cpu_est_11_3__n a_c_17__n N_40_0 N_16_i a_c_18__n N_39_0 N_19_i \ +un6_uds_000_1 a_c_19__n N_36_0 pos_clk_un24_bgack_030_int_i_0_n N_20_i N_245 \ +a_c_20__n N_35_0 N_246 N_21_i N_247 a_c_21__n N_34_0 N_248 BG_030_c_i N_89 \ +a_c_22__n pos_clk_un6_bg_030_i_n N_92 pos_clk_un8_bg_030_0_n N_102 a_c_23__n \ +N_127_i_1 N_103 N_127_i_2 N_104 a_c_24__n pos_clk_un24_bgack_030_int_i_0_i_1_n \ +N_112 N_80_0_1 N_256 a_c_25__n N_75_i_1 N_258 N_251_0_1 a_c_26__n \ +pos_clk_un11_ds_030_d0_i_1_n N_260 N_340_1 N_265 a_c_27__n N_340_2 N_282 \ +N_340_3 N_71 a_c_28__n N_340_4 un5_ciin_1 pos_clk_un11_clk_000_n_sync_n \ +a_c_29__n un5_ciin_2 N_76 un5_ciin_3 a_c_30__n un5_ciin_4 un5_ciin_5 a_c_31__n \ +un5_ciin_6 pos_clk_un22_bgack_030_int_n un5_ciin_7 N_268 A0_c un5_ciin_8 N_270 \ +un5_ciin_9 N_73 A1_c un5_ciin_10 N_75 un5_ciin_11 N_251 nEXP_SPACE_c \ +un22_berr_1_0 un22_berr_1 un21_fpu_cs_1 N_95 BERR_c pos_clk_un6_bg_030_1_n \ +N_94 N_131_i_1 N_288 BG_030_c N_131_i_2 N_289 N_131_i_3 N_286 N_96_1 N_279 \ +N_96_2 N_277 N_96_3 N_276 BGACK_000_c pos_clk_cpu_est_11_0_1_1__n N_62 \ +pos_clk_cpu_est_11_0_2_1__n N_274 N_310_1 N_313 N_310_2 N_307 N_310_3 N_305 \ +CLK_OSZI_c N_310_4 N_306 N_309_1 N_303 N_309_2 N_304 CLK_EXP_c N_308_1 N_301 \ +N_308_2 N_91 RESET_OUT_0_sqmuxa_5_1 N_85 FPU_SENSE_c RESET_OUT_0_sqmuxa_7_1 \ +N_294 RESET_OUT_0_sqmuxa_7_2 N_296 RESET_OUT_0_sqmuxa_7_3 N_84 N_94_1 N_82 \ +N_95_1 N_83 N_119_i_1 N_293 N_82_1 N_290 N_83_1 N_291 ipl_c_0__n N_296_1 N_283 \ +N_303_1 N_284 ipl_c_1__n N_304_1 N_86 N_306_1 N_80 ipl_c_2__n N_129_i_1 N_78 \ +N_125_i_1 N_108 N_123_i_1 N_109 DTACK_c N_115_0_1 N_100 \ +pos_clk_cpu_est_11_0_1_3__n N_99 N_260_0_1 N_93 N_261_i_1 \ +pos_clk_un14_clk_000_n_sync_n VPA_c N_262_i_1 pos_clk_un9_clk_000_n_sync_n \ +N_263_i_1 N_340 pos_clk_ipl_1_n N_97 RST_c cpu_est_0_3__un3_n N_136 \ +cpu_est_0_3__un1_n N_101 cpu_est_0_3__un0_n N_81 RW_c cpu_est_0_2__un3_n N_116 \ +cpu_est_0_2__un1_n N_96 fc_c_0__n cpu_est_0_2__un0_n N_113 cpu_est_0_1__un3_n \ +N_275 fc_c_1__n cpu_est_0_1__un1_n N_273 cpu_est_0_1__un0_n N_88 \ +bgack_030_int_0_un3_n N_272 AMIGA_BUS_DATA_DIR_c bgack_030_int_0_un1_n N_299 \ +bgack_030_int_0_un0_n N_90 vma_int_0_un3_n N_311 vma_int_0_un1_n N_312 \ +vma_int_0_un0_n N_267 un1_as_000_i rw_000_int_0_un3_n N_264 \ +un1_rst_dly_i_m_i_3__n rw_000_int_0_un1_n pos_clk_un7_clk_000_pe_n \ +rw_000_int_0_un0_n N_308 un1_rst_dly_i_m_i_4__n sm_amiga_srsts_i_0_m2_3__un3_n \ +N_309 sm_amiga_srsts_i_0_m2_3__un1_n AS_030.OE AS_000.OE RW_000.OE DS_030.OE \ +UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE BERR.OE RW.OE CLK_DIV_OUT.OE \ +DSACK1.OE CIIN.OE pos_clk_RST_DLY_5_iv_0_x2_0_ G_137 G_149 G_147 G_145 G_143 \ +G_141 G_139 G_165 G_166 G_167 cpu_est_0_0_x2_0_ pos_clk_CYCLE_DMA_5_1_i_x2 \ +pos_clk_CYCLE_DMA_5_0_i_x2 pos_clk_un24_bgack_030_int_i_0_x2 +.names N_32_0.BLIF IPL_030DFF_2_reg.D +0 1 +.names N_52_0.BLIF IPL_D0_0_.D +0 1 +.names N_53_0.BLIF IPL_D0_1_.D +0 1 +.names N_54_0.BLIF IPL_D0_2_.D +0 1 +.names N_131_i_3.BLIF N_96_i.BLIF SM_AMIGA_i_7_.D +11 1 +.names N_129_i_1.BLIF RST_c.BLIF SM_AMIGA_6_.D +11 1 +.names N_127_i_1.BLIF N_127_i_2.BLIF SM_AMIGA_5_.D +11 1 +.names N_125_i_1.BLIF RST_c.BLIF SM_AMIGA_4_.D +11 1 +.names N_123_i_1.BLIF RST_c.BLIF SM_AMIGA_3_.D +11 1 +.names N_259_0.BLIF SM_AMIGA_2_.D +0 1 +.names N_119_i_1.BLIF RST_c.BLIF SM_AMIGA_1_.D +11 1 +.names N_77_i.BLIF N_101_i.BLIF SM_AMIGA_0_.D +11 1 +.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D +1- 1 +-1 1 +.names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D +1- 1 +-1 1 +.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_reg.D +1- 1 +-1 1 +.names N_30_0.BLIF IPL_030DFF_0_reg.D +0 1 +.names N_31_0.BLIF IPL_030DFF_1_reg.D +0 1 +.names N_98_i.BLIF RST_c.BLIF RST_DLY_0_.D +11 1 +.names RST_c.BLIF un1_rst_dly_i_m_i_2__n.BLIF RST_DLY_1_.D +11 1 +.names RST_c.BLIF un1_rst_dly_i_m_i_3__n.BLIF RST_DLY_2_.D +11 1 +.names RST_c.BLIF un1_rst_dly_i_m_i_4__n.BLIF RST_DLY_3_.D +11 1 +.names RST_c.BLIF un1_rst_dly_i_m_i_5__n.BLIF RST_DLY_4_.D +11 1 +.names RST_c.BLIF un1_rst_dly_i_m_i_6__n.BLIF RST_DLY_5_.D +11 1 +.names RST_c.BLIF un1_rst_dly_i_m_i_7__n.BLIF RST_DLY_6_.D +11 1 +.names RST_c.BLIF un1_rst_dly_i_m_i_8__n.BLIF RST_DLY_7_.D +11 1 +.names N_263_i_1.BLIF RST_c.BLIF CYCLE_DMA_0_.D +11 1 +.names N_262_i_1.BLIF RST_c.BLIF CYCLE_DMA_1_.D +11 1 +.names size_dma_0_0__un1_n.BLIF size_dma_0_0__un0_n.BLIF SIZE_DMA_0_.D +1- 1 +-1 1 +.names size_dma_0_1__un1_n.BLIF size_dma_0_1__un0_n.BLIF SIZE_DMA_1_.D +1- 1 +-1 1 +.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF CLK_000_P_SYNC_0_.D +11 1 +.names N_261_i_1.BLIF pos_clk_un24_bgack_030_int_i_0_i_n.BLIF inst_CLK_030_H.D +11 1 +.names N_105_i.BLIF RST_c.BLIF inst_RESET_OUTreg.D +11 1 +.names N_11.BLIF RST_c.BLIF inst_DS_000_ENABLE.D +11 1 +.names N_39_0.BLIF inst_UDS_000_INT.D +0 1 +.names N_40_0.BLIF inst_RW_000_DMA.D +0 1 +.names N_41_0.BLIF inst_RW_000_INT.D +0 1 +.names N_42_0.BLIF inst_LDS_000_INT.D +0 1 +.names N_43_0.BLIF inst_AS_030_000_SYNC.D +0 1 +.names N_44_0.BLIF inst_AS_000_INT.D +0 1 +.names N_45_0.BLIF inst_DSACK1_INTreg.D +0 1 +.names N_46_0.BLIF inst_A0_DMA.D +0 1 +.names N_48_0.BLIF inst_AS_000_DMA.D +0 1 +.names N_49_0.BLIF inst_DS_000_DMA.D +0 1 +.names N_50_0.BLIF inst_DS_030_D0.D +0 1 +.names N_102.BLIF inst_AS_030_D0.D +0 1 +.names N_55_0.BLIF inst_nEXP_SPACE_D0reg.D +0 1 +.names N_56_0.BLIF inst_VPA_D.D +0 1 +.names N_57_0.BLIF inst_DTACK_D0.D +0 1 +.names N_33_0.BLIF inst_BGACK_030_INTreg.D +0 1 +.names N_34_0.BLIF BG_000DFFreg.D +0 1 +.names N_35_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D +0 1 +.names N_36_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D +0 1 +.names N_37_0.BLIF inst_VMA_INTreg.D +0 1 +.names AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa.BLIF inst_BGACK_030_INT_D.D +0 1 +.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D +0 1 +.names N_310_4.BLIF N_310_3.BLIF N_310 +11 1 +.names un1_rst_dly_i_m_5__n.BLIF un1_rst_dly_i_m_i_5__n +0 1 +.names CLK_000_PE_i.BLIF sm_amiga_srsts_i_0_m2_3__un3_n.BLIF \ +sm_amiga_srsts_i_0_m2_3__un0_n +11 1 +.names inst_CLK_000_PE.BLIF CYCLE_DMA_0_.BLIF N_220 +11 1 +.names SM_AMIGA_1_.BLIF sm_amiga_srsts_i_0_m2_1__un3_n +0 1 +.names pos_clk_cpu_est_11_0_1__n.BLIF pos_clk_cpu_est_11_1__n +0 1 +.names un1_rst_dly_i_m_6__n.BLIF un1_rst_dly_i_m_i_6__n +0 1 +.names BERR_i.BLIF SM_AMIGA_1_.BLIF sm_amiga_srsts_i_0_m2_1__un1_n +11 1 +.names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF N_14 +1- 1 +-1 1 +.names CLK_000_PE_i.BLIF sm_amiga_srsts_i_0_m2_1__un3_n.BLIF \ +sm_amiga_srsts_i_0_m2_1__un0_n +11 1 +.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF N_18 +1- 1 +-1 1 +.names un1_rst_dly_i_m_7__n.BLIF un1_rst_dly_i_m_i_7__n +0 1 +.names inst_BGACK_030_INTreg.BLIF un1_amiga_bus_enable_dma_high_0_m2_0__un3_n +0 1 +.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF N_22 +1- 1 +-1 1 +.names SM_AMIGA_i_7_.BLIF inst_BGACK_030_INTreg.BLIF \ +un1_amiga_bus_enable_dma_high_0_m2_0__un1_n +11 1 +.names inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF RESET_OUT_0_sqmuxa_1 +11 1 +.names un1_rst_dly_i_m_8__n.BLIF un1_rst_dly_i_m_i_8__n +0 1 +.names AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF \ +un1_amiga_bus_enable_dma_high_0_m2_0__un3_n.BLIF \ +un1_amiga_bus_enable_dma_high_0_m2_0__un0_n +11 1 +.names vcc_n_n + 1 +.names RESET_OUT_0_sqmuxa_1.BLIF RST_DLY_1_.BLIF N_205 +11 1 +.names SM_AMIGA_5_.BLIF un1_sm_amiga_7_i_m2_un3_n +0 1 +.names N_211.BLIF RST_DLY_5_.BLIF N_213 +11 1 +.names un1_rst_dly_i_m_2__n.BLIF un1_rst_dly_i_m_i_2__n +0 1 +.names RW_i.BLIF SM_AMIGA_5_.BLIF un1_sm_amiga_7_i_m2_un1_n +11 1 +.names sm_amiga_i_3__n.BLIF un1_sm_amiga_7_i_m2_un3_n.BLIF \ +un1_sm_amiga_7_i_m2_un0_n +11 1 +.names RESET_OUT_0_sqmuxa_i.BLIF RESET_OUT_i.BLIF N_105 +11 1 +.names N_98.BLIF N_98_i +0 1 +.names N_248.BLIF size_dma_0_0__un3_n +0 1 +.names gnd_n_n +.names N_87_i_i.BLIF RESET_OUT_0_sqmuxa_i.BLIF N_98 +11 1 +.names pos_clk_size_dma_6_0__n.BLIF N_248.BLIF size_dma_0_0__un1_n +11 1 +.names AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF BGACK_030_INT_i.BLIF \ +un1_amiga_bus_enable_low +11 1 +.names RESET_OUT_0_sqmuxa_7.BLIF RST_DLY_7_.BLIF RESET_OUT_0_sqmuxa +11 1 +.names N_105.BLIF N_105_i +0 1 +.names SIZE_DMA_0_.BLIF size_dma_0_0__un3_n.BLIF size_dma_0_0__un0_n +11 1 +.names AS_000_DMA_i.BLIF AS_000_i.BLIF un6_as_030 +11 1 +.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_2__n.BLIF un1_rst_dly_i_m_2__n +11 1 +.names N_248.BLIF size_dma_0_1__un3_n +0 1 +.names SIZE_DMA_1_.BLIF size_dma_i_0__n.BLIF un3_size +11 1 +.names N_22.BLIF N_22_i +0 1 +.names pos_clk_size_dma_6_1__n.BLIF N_248.BLIF size_dma_0_1__un1_n +11 1 +.names SIZE_DMA_0_.BLIF size_dma_i_1__n.BLIF un4_size +11 1 +.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_8__n.BLIF un1_rst_dly_i_m_8__n +11 1 +.names N_22_i.BLIF RST_c.BLIF N_33_0 +11 1 +.names SIZE_DMA_1_.BLIF size_dma_0_1__un3_n.BLIF size_dma_0_1__un0_n +11 1 +.names un5_ciin_10.BLIF un5_ciin_11.BLIF un5_ciin +11 1 +.names N_18.BLIF N_18_i +0 1 +.names pos_clk_ipl_n.BLIF ipl_030_0_0__un3_n +0 1 +.names AS_000_INT_i.BLIF AS_030_i.BLIF un4_as_000 +11 1 +.names RESET_OUT_0_sqmuxa_5_1.BLIF RST_DLY_2_.BLIF RESET_OUT_0_sqmuxa_5 +11 1 +.names N_18_i.BLIF RST_c.BLIF N_37_0 +11 1 +.names ipl_c_0__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_0__un1_n +11 1 +.names un21_fpu_cs_1.BLIF un22_berr_1.BLIF un21_fpu_cs +11 1 +.names RESET_OUT_0_sqmuxa_7_3.BLIF RST_DLY_6_.BLIF RESET_OUT_0_sqmuxa_7 +11 1 +.names N_14.BLIF N_14_i +0 1 +.names IPL_030DFF_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n +11 1 +.names un22_berr_1_0.BLIF N_340.BLIF un22_berr +11 1 +.names N_14_i.BLIF RST_c.BLIF N_41_0 +11 1 +.names pos_clk_ipl_n.BLIF ipl_030_0_1__un3_n +0 1 +.names AS_000_i.BLIF DS_000_DMA_i.BLIF un6_ds_030 +11 1 +.names N_10.BLIF N_10_i +0 1 +.names ipl_c_1__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_1__un1_n +11 1 +.names UDS_000_INT_i.BLIF un6_uds_000_1.BLIF un6_uds_000 +11 1 +.names N_209.BLIF RST_DLY_4_.BLIF N_211 +11 1 +.names N_10_i.BLIF RST_c.BLIF N_44_0 +11 1 +.names IPL_030DFF_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n +11 1 +.names LDS_000_INT_i.BLIF un6_uds_000_1.BLIF un6_lds_000 +11 1 +.names pos_clk_cpu_est_11_0_1_1__n.BLIF pos_clk_cpu_est_11_0_2_1__n.BLIF \ +pos_clk_cpu_est_11_0_1__n +11 1 +.names pos_clk_ipl_n.BLIF ipl_030_0_2__un3_n +0 1 +.names RESET_OUT_0_sqmuxa_5.BLIF RST_DLY_3_.BLIF N_209 +11 1 +.names N_312.BLIF N_312_i +0 1 +.names ipl_c_2__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_2__un1_n +11 1 +.names N_90.BLIF N_90_i +0 1 +.names IPL_030DFF_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n +11 1 +.names N_88.BLIF N_88_i +0 1 +.names pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_high_0_un3_n +0 1 +.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_7__n.BLIF un1_rst_dly_i_m_7__n +11 1 +.names N_299.BLIF N_299_i +0 1 +.names N_104_i.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF \ +amiga_bus_enable_dma_high_0_un1_n +11 1 +.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_6__n.BLIF un1_rst_dly_i_m_6__n +11 1 +.names N_268_i.BLIF SM_AMIGA_4_.BLIF N_275_0 +11 1 +.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ +amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n +11 1 +.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_5__n.BLIF un1_rst_dly_i_m_5__n +11 1 +.names N_268.BLIF sm_amiga_i_3__n.BLIF N_274_0 +11 1 +.names pos_clk_un8_bg_030_n.BLIF bg_000_0_un3_n +0 1 +.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_4__n.BLIF un1_rst_dly_i_m_4__n +11 1 +.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_273_i +11 1 +.names BG_030_c.BLIF pos_clk_un8_bg_030_n.BLIF bg_000_0_un1_n +11 1 +.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_3__n.BLIF un1_rst_dly_i_m_3__n +11 1 +.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF N_272_i +11 1 +.names BG_000DFFreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n +11 1 +.names N_71.BLIF N_71_i +0 1 +.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_270_i +11 1 +.names N_260.BLIF ds_000_dma_0_un3_n +0 1 +.names un1_amiga_bus_enable_low.BLIF un1_amiga_bus_enable_low_i +0 1 +.names BERR_c.BLIF CLK_000_PE_i.BLIF N_268_i +11 1 +.names pos_clk_ds_000_dma_4_n.BLIF N_260.BLIF ds_000_dma_0_un1_n +11 1 +.names un21_fpu_cs.BLIF un21_fpu_cs_i +0 1 +.names N_310.BLIF N_310_i +0 1 +.names inst_DS_000_DMA.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n +11 1 +.names inst_RESET_OUTreg.BLIF RESET_OUT_i +0 1 +.names N_311.BLIF N_311_i +0 1 +.names N_258.BLIF as_000_dma_0_un3_n +0 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i +0 1 +.names N_310_i.BLIF N_311_i.BLIF N_267_0 +11 1 +.names pos_clk_un24_bgack_030_int_i_0_n.BLIF N_258.BLIF as_000_dma_0_un1_n +11 1 +.names RESET_OUT_0_sqmuxa.BLIF RESET_OUT_0_sqmuxa_i +0 1 +.names N_309.BLIF N_309_i +0 1 +.names inst_AS_000_DMA.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n +11 1 +.names G_139.BLIF un1_rst_dly_i_3__n +0 1 +.names N_308.BLIF N_308_i +0 1 +.names pos_clk_un5_bgack_030_int_d_n.BLIF a0_dma_0_un3_n +0 1 +.names G_141.BLIF un1_rst_dly_i_4__n +0 1 +.names N_308_i.BLIF N_309_i.BLIF pos_clk_un7_clk_000_pe_0_n +11 1 +.names pos_clk_a0_dma_3_n.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF \ +a0_dma_0_un1_n +11 1 +.names G_143.BLIF un1_rst_dly_i_5__n +0 1 +.names RW_i.BLIF SM_AMIGA_5_.BLIF N_264_0 +11 1 +.names inst_A0_DMA.BLIF a0_dma_0_un3_n.BLIF a0_dma_0_un0_n +11 1 +.names G_145.BLIF un1_rst_dly_i_6__n +0 1 +.names N_304.BLIF N_304_i +0 1 +.names N_245.BLIF dsack1_int_0_un3_n +0 1 +.names G_147.BLIF un1_rst_dly_i_7__n +0 1 +.names N_303.BLIF N_303_i +0 1 +.names N_92_i.BLIF N_245.BLIF dsack1_int_0_un1_n +11 1 +.names G_149.BLIF un1_rst_dly_i_8__n +0 1 +.names N_303_i.BLIF N_304_i.BLIF N_186_i +11 1 +.names inst_DSACK1_INTreg.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n +11 1 +.names G_137.BLIF un1_rst_dly_i_2__n +0 1 +.names VPA_c.BLIF VPA_c_i +0 1 +.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n +0 1 +.names pos_clk_RST_DLY_5_iv_0_x2_0_.BLIF N_87_i_i +0 1 +.names RST_c.BLIF VPA_c_i.BLIF N_56_0 +11 1 +.names inst_AS_000_INT.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n +11 1 +.names cpu_est_3_reg.BLIF cpu_est_i_3__n +0 1 +.names DTACK_c.BLIF DTACK_c_i +0 1 +.names sm_amiga_i_5__n.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n +11 1 +.names cpu_est_0_.BLIF cpu_est_i_0__n +0 1 +.names DTACK_c_i.BLIF RST_c.BLIF N_57_0 +11 1 +.names DS_000_ENABLE_1_sqmuxa_1.BLIF ds_000_enable_0_un3_n +0 1 +.names inst_VPA_D.BLIF VPA_D_i +0 1 +.names N_97.BLIF N_97_i +0 1 +.names inst_DS_000_ENABLE.BLIF DS_000_ENABLE_1_sqmuxa_1.BLIF \ +ds_000_enable_0_un1_n +11 1 +.names inst_VMA_INTreg.BLIF VMA_INT_i +0 1 +.names N_282_i.BLIF ds_000_enable_0_un3_n.BLIF ds_000_enable_0_un0_n +11 1 +.names cpu_est_1_.BLIF cpu_est_i_1__n +0 1 +.names N_96.BLIF N_96_i +0 1 +.names N_246.BLIF as_030_000_sync_0_un3_n +0 1 +.names inst_CLK_000_PE.BLIF CLK_000_PE_i +0 1 +.names N_95.BLIF N_95_i +0 1 +.names inst_AS_030_000_SYNC.BLIF N_246.BLIF as_030_000_sync_0_un1_n +11 1 +.names BERR_c.BLIF BERR_i +0 1 +.names N_94.BLIF N_94_i +0 1 +.names pos_clk_un3_as_030_d0_n.BLIF as_030_000_sync_0_un3_n.BLIF \ +as_030_000_sync_0_un0_n +11 1 +.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n +0 1 +.names N_313.BLIF N_313_i +0 1 +.names pos_clk_un3_ds_030_d0_n.BLIF lds_000_int_0_un3_n +0 1 +.names cpu_est_2_.BLIF cpu_est_i_2__n +0 1 +.names N_313_i.BLIF SM_AMIGA_3_.BLIF N_136_i +11 1 +.names pos_clk_un11_ds_030_d0_i_n.BLIF pos_clk_un3_ds_030_d0_n.BLIF \ +lds_000_int_0_un1_n +11 1 +.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +0 1 +.names inst_CLK_000_NE.BLIF SM_AMIGA_1_.BLIF N_81_0 +11 1 +.names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n +11 1 +.names inst_DTACK_D0.BLIF DTACK_D0_i +0 1 +.names N_116.BLIF N_116_i +0 1 +.names pos_clk_un5_bgack_030_int_d_n.BLIF rw_000_dma_0_un3_n +0 1 +.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n +0 1 +.names N_116_i.BLIF RST_c.BLIF N_77_i +11 1 +.names N_265.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF rw_000_dma_0_un1_n +11 1 +.names pos_clk_un6_bg_030_1_n.BLIF inst_CLK_000_D0.BLIF pos_clk_un6_bg_030_n +11 1 +.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n +0 1 +.names sm_amiga_i_1__n.BLIF sm_amiga_i_5__n.BLIF N_73_i +11 1 +.names inst_RW_000_DMA.BLIF rw_000_dma_0_un3_n.BLIF rw_000_dma_0_un0_n +11 1 +.names inst_CLK_000_NE.BLIF CLK_000_NE_i +0 1 +.names N_101.BLIF N_101_i +0 1 +.names pos_clk_un3_ds_030_d0_n.BLIF uds_000_int_0_un3_n +0 1 +.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n +0 1 +.names A0_c.BLIF pos_clk_un3_ds_030_d0_n.BLIF uds_000_int_0_un1_n +11 1 +.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n +0 1 +.names CLK_000_N_SYNC_10_.BLIF clk_000_n_sync_i_10__n +0 1 +.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n +11 1 +.names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_PRE_D_i +0 1 +.names pos_clk_un9_clk_000_n_sync_n.BLIF pos_clk_un9_clk_000_n_sync_i_n +0 1 +.names pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_low_0_un3_n +0 1 +.names pos_clk_ipl_1_n.BLIF N_225_i.BLIF pos_clk_ipl_n +11 1 +.names pos_clk_un11_clk_000_n_sync_n.BLIF pos_clk_un11_clk_000_n_sync_i_n +0 1 +.names clk_000_n_sync_i_10__n.BLIF pos_clk_un9_clk_000_n_sync_i_n.BLIF \ +pos_clk_un14_clk_000_n_sync_0_n +11 1 +.names N_103_i.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF \ +amiga_bus_enable_dma_low_0_un1_n +11 1 +.names DS_030_D0_i.BLIF SM_AMIGA_6_.BLIF pos_clk_un3_ds_030_d0_n +11 1 +.names LDS_000_c.BLIF LDS_000_i +0 1 +.names LDS_000_c.BLIF UDS_000_c.BLIF pos_clk_un22_bgack_030_int_i_n +11 1 +.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF \ +amiga_bus_enable_dma_low_0_un3_n.BLIF amiga_bus_enable_dma_low_0_un0_n +11 1 +.names UDS_000_c.BLIF UDS_000_i +0 1 +.names N_86.BLIF N_86_i +0 1 +.names BGACK_030_INT_i.BLIF RST_c.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa +11 1 +.names inst_nEXP_SPACE_D0reg.BLIF nEXP_SPACE_D0_i +0 1 +.names N_93.BLIF N_93_i +0 1 +.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n +0 1 +.names AS_030_c.BLIF AS_030_i +0 1 +.names N_99.BLIF N_99_i +0 1 +.names A1_c.BLIF A1_i +0 1 +.names N_99_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n +11 1 +.names inst_CLK_000_D1.BLIF CLK_000_D1_i +0 1 +.names N_100.BLIF N_100_i +0 1 +.names RW_000_c.BLIF RW_000_i +0 1 +.names N_100_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n +11 1 +.names inst_CLK_030_H.BLIF CLK_030_H_i +0 1 +.names N_92_i.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_245_0 +11 1 +.names inst_AS_000_DMA.BLIF AS_000_DMA_i +0 1 +.names N_108.BLIF N_108_i +0 1 +.names AS_000_c.BLIF AS_000_i +0 1 +.names N_109.BLIF N_109_i +0 1 +.names pos_clk_un8_bg_030_0_n.BLIF pos_clk_un8_bg_030_n +0 1 +.names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n +0 1 +.names N_108_i.BLIF N_109_i.BLIF N_246_0 +11 1 +.names RW_c.BLIF RW_i +0 1 +.names un5_ciin.BLIF un5_ciin_i +0 1 +.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i +0 1 +.names nEXP_SPACE_D0_i.BLIF un5_ciin_i.BLIF N_247_0 +11 1 +.names FPU_SENSE_c.BLIF FPU_SENSE_i +0 1 +.names RST_c.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF N_248_0 +11 1 +.names inst_AS_030_D0.BLIF AS_030_D0_i +0 1 +.names inst_CLK_000_D0.BLIF CLK_000_D0_i +0 1 +.names a_c_24__n.BLIF a_i_24__n +0 1 +.names CLK_000_D0_i.BLIF inst_CLK_000_D1.BLIF N_249_i +11 1 +.names SIZE_DMA_0_.BLIF size_dma_i_0__n +0 1 +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +0 1 +.names SIZE_DMA_1_.BLIF size_dma_i_1__n +0 1 +.names N_251_0_1.BLIF inst_nEXP_SPACE_D0reg.BLIF N_251_0 +11 1 +.names a_c_16__n.BLIF a_i_16__n +0 1 +.names AS_030_D0_i.BLIF BERR_c.BLIF pos_clk_un3_as_030_d0_i_n +11 1 +.names a_c_18__n.BLIF a_i_18__n +0 1 +.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ +pos_clk_un5_bgack_030_int_d_i_n +11 1 +.names a_c_19__n.BLIF a_i_19__n +0 1 +.names N_75_i_1.BLIF sm_amiga_i_4__n.BLIF N_75_i +11 1 +.names a_c_31__n.BLIF a_i_31__n +0 1 +.names LDS_000_i.BLIF UDS_000_i.BLIF N_76_i +11 1 +.names a_c_29__n.BLIF a_i_29__n +0 1 +.names CLK_000_NE_i.BLIF SM_AMIGA_1_.BLIF N_78_0 +11 1 +.names a_c_30__n.BLIF a_i_30__n +0 1 +.names N_80_0_1.BLIF sm_amiga_i_i_7__n.BLIF N_80_0 +11 1 +.names a_c_27__n.BLIF a_i_27__n +0 1 +.names CLK_EXP_c.BLIF CLK_EXP_c_i +0 1 +.names a_c_28__n.BLIF a_i_28__n +0 1 +.names CLK_EXP_c_i.BLIF pos_clk_un24_bgack_030_int_i_0_i_n.BLIF N_258_0 +11 1 +.names a_c_25__n.BLIF a_i_25__n +0 1 +.names N_283.BLIF N_283_i +0 1 +.names a_c_26__n.BLIF a_i_26__n +0 1 +.names N_284.BLIF N_284_i +0 1 +.names inst_UDS_000_INT.BLIF UDS_000_INT_i +0 1 +.names inst_LDS_000_INT.BLIF LDS_000_INT_i +0 1 +.names N_290.BLIF N_290_i +0 1 +.names DS_030_c.BLIF DS_030_i +0 1 +.names N_291.BLIF N_291_i +0 1 +.names pos_clk_un5_bgack_030_int_d_i_n.BLIF pos_clk_un5_bgack_030_int_d_n +0 1 +.names G_165.BLIF N_224_i +0 1 +.names G_166.BLIF N_225_i +0 1 +.names N_279.BLIF N_279_i +0 1 +.names G_167.BLIF N_226_i +0 1 +.names N_293.BLIF N_293_i +0 1 +.names N_82.BLIF N_82_i +0 1 +.names N_83.BLIF N_83_i +0 1 +.names N_104.BLIF N_104_i +0 1 +.names N_82_i.BLIF N_83_i.BLIF N_259_0 +11 1 +.names N_103.BLIF N_103_i +0 1 +.names N_84.BLIF N_84_i +0 1 +.names pos_clk_un3_as_030_d0_i_n.BLIF pos_clk_un3_as_030_d0_n +0 1 +.names N_282.BLIF N_282_i +0 1 +.names N_115_0_1.BLIF SM_AMIGA_i_7_.BLIF N_115_0 +11 1 +.names N_92.BLIF N_92_i +0 1 +.names N_85.BLIF N_85_i +0 1 +.names sm_amiga_i_5__n.BLIF pos_clk_un3_as_030_d0_i_n.BLIF AS_000_INT_1_sqmuxa +11 1 +.names un6_lds_000.BLIF un6_lds_000_i +0 1 +.names N_294.BLIF N_294_i +0 1 +.names N_282.BLIF pos_clk_un3_as_030_d0_i_n.BLIF DS_000_ENABLE_1_sqmuxa_1 +11 1 +.names un6_uds_000.BLIF un6_uds_000_i +0 1 +.names N_296.BLIF N_296_i +0 1 +.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF pos_clk_a0_dma_3_n +11 1 +.names un6_ds_030.BLIF un6_ds_030_i +0 1 +.names pos_clk_cpu_est_11_0_1_3__n.BLIF N_294_i.BLIF pos_clk_cpu_est_11_0_3__n +11 1 +.names pos_clk_ds_000_dma_4_0_n.BLIF pos_clk_ds_000_dma_4_n +0 1 +.names inst_DS_000_DMA.BLIF DS_000_DMA_i +0 1 +.names N_91.BLIF N_91_i +0 1 +.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3 +1- 1 +-1 1 +.names un4_as_000.BLIF un4_as_000_i +0 1 +.names N_260_0_1.BLIF pos_clk_un24_bgack_030_int_i_0_i_n.BLIF N_260_0 +11 1 +.names inst_AS_000_INT.BLIF AS_000_INT_i +0 1 +.names N_301.BLIF N_301_i +0 1 +.names un6_as_030.BLIF un6_as_030_i +0 1 +.names N_301_i.BLIF pos_clk_un24_bgack_030_int_i_0_i_n.BLIF \ +pos_clk_ds_000_dma_4_0_n +11 1 +.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF N_6 +1- 1 +-1 1 +.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i +0 1 +.names N_305.BLIF N_305_i +0 1 +.names a0_dma_0_un1_n.BLIF a0_dma_0_un0_n.BLIF N_8 +1- 1 +-1 1 +.names inst_DS_030_D0.BLIF DS_030_D0_i +0 1 +.names N_306.BLIF N_306_i +0 1 +.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF N_9 +1- 1 +-1 1 +.names N_305_i.BLIF N_306_i.BLIF AMIGA_BUS_DATA_DIR_c_0 +11 1 +.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF N_10 +1- 1 +-1 1 +.names N_307.BLIF N_307_i +0 1 +.names ds_000_enable_0_un1_n.BLIF ds_000_enable_0_un0_n.BLIF N_11 +1- 1 +-1 1 +.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF N_12 +1- 1 +-1 1 +.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF N_13 +1- 1 +-1 1 +.names rw_000_dma_0_un1_n.BLIF rw_000_dma_0_un0_n.BLIF N_15 +1- 1 +-1 1 +.names BGACK_030_INT_i.BLIF RW_000_i.BLIF N_265_0 +11 1 +.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_16 +1- 1 +-1 1 +.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_269_i +11 1 +.names amiga_bus_enable_dma_low_0_un1_n.BLIF \ +amiga_bus_enable_dma_low_0_un0_n.BLIF N_19 +1- 1 +-1 1 +.names pos_clk_un24_bgack_030_int_i_0_i_1_n.BLIF \ +pos_clk_un22_bgack_030_int_n.BLIF pos_clk_un24_bgack_030_int_i_0_i_n +11 1 +.names amiga_bus_enable_dma_high_0_un1_n.BLIF \ +amiga_bus_enable_dma_high_0_un0_n.BLIF N_20 +1- 1 +-1 1 +.names N_268_i.BLIF SM_AMIGA_6_.BLIF N_62_0 +11 1 +.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF N_21 +1- 1 +-1 1 +.names inst_CLK_000_PE.BLIF SM_AMIGA_6_.BLIF N_276_0 +11 1 +.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF N_23 +1- 1 +-1 1 +.names AS_000_DMA_i.BLIF CLK_EXP_c_i.BLIF N_277_0 +11 1 +.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF N_24 +1- 1 +-1 1 +.names N_286.BLIF N_286_i +0 1 +.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_25 +1- 1 +-1 1 +.names N_288.BLIF N_288_i +0 1 +.names N_289.BLIF N_289_i +0 1 +.names pos_clk_un11_ds_030_d0_i_1_n.BLIF size_c_0__n.BLIF \ +pos_clk_un11_ds_030_d0_i_n +11 1 +.names A0_c.BLIF A0_c_i +0 1 +.names size_c_1__n.BLIF size_c_i_1__n +0 1 +.names N_25.BLIF N_25_i +0 1 +.names N_25_i.BLIF RST_c.BLIF N_32_0 +11 1 +.names N_24.BLIF N_24_i +0 1 +.names N_24_i.BLIF RST_c.BLIF N_31_0 +11 1 +.names N_23.BLIF N_23_i +0 1 +.names N_23_i.BLIF RST_c.BLIF N_30_0 +11 1 +.names ipl_c_2__n.BLIF ipl_c_i_2__n +0 1 +.names ipl_c_i_2__n.BLIF RST_c.BLIF N_54_0 +11 1 +.names ipl_c_1__n.BLIF ipl_c_i_1__n +0 1 +.names ipl_c_i_1__n.BLIF RST_c.BLIF N_53_0 +11 1 +.names ipl_c_0__n.BLIF ipl_c_i_0__n +0 1 +.names ipl_c_i_0__n.BLIF RST_c.BLIF N_52_0 +11 1 +.names nEXP_SPACE_c.BLIF nEXP_SPACE_c_i +0 1 +.names RST_c.BLIF nEXP_SPACE_c_i.BLIF N_55_0 +11 1 +.names DS_030_i.BLIF RST_c.BLIF N_50_0 +11 1 +.names N_3.BLIF N_3_i +0 1 +.names N_3_i.BLIF RST_c.BLIF N_49_0 +11 1 +.names N_6.BLIF N_6_i +0 1 +.names N_6_i.BLIF RST_c.BLIF N_48_0 +11 1 +.names N_8.BLIF N_8_i +0 1 +.names N_8_i.BLIF RST_c.BLIF N_46_0 +11 1 +.names N_9.BLIF N_9_i +0 1 +.names N_9_i.BLIF RST_c.BLIF N_45_0 +11 1 +.names N_12.BLIF N_12_i +0 1 +.names N_12_i.BLIF RST_c.BLIF N_43_0 +11 1 +.names N_115_0.BLIF N_115 +0 1 +.names N_13.BLIF N_13_i +0 1 +.names pos_clk_size_dma_6_0_0__n.BLIF pos_clk_size_dma_6_0__n +0 1 +.names N_13_i.BLIF RST_c.BLIF N_42_0 +11 1 +.names pos_clk_size_dma_6_0_1__n.BLIF pos_clk_size_dma_6_1__n +0 1 +.names N_15.BLIF N_15_i +0 1 +.names pos_clk_cpu_est_11_0_3__n.BLIF pos_clk_cpu_est_11_3__n +0 1 +.names N_15_i.BLIF RST_c.BLIF N_40_0 +11 1 +.names N_16.BLIF N_16_i +0 1 +.names N_16_i.BLIF RST_c.BLIF N_39_0 +11 1 +.names N_19.BLIF N_19_i +0 1 +.names inst_DS_000_ENABLE.BLIF DS_030_i.BLIF un6_uds_000_1 +11 1 +.names N_19_i.BLIF RST_c.BLIF N_36_0 +11 1 +.names pos_clk_un24_bgack_030_int_i_0_i_n.BLIF \ +pos_clk_un24_bgack_030_int_i_0_n +0 1 +.names N_20.BLIF N_20_i +0 1 +.names N_245_0.BLIF N_245 +0 1 +.names N_20_i.BLIF RST_c.BLIF N_35_0 +11 1 +.names N_246_0.BLIF N_246 +0 1 +.names N_21.BLIF N_21_i +0 1 +.names N_247_0.BLIF N_247 +0 1 +.names N_21_i.BLIF RST_c.BLIF N_34_0 +11 1 +.names N_248_0.BLIF N_248 +0 1 +.names BG_030_c.BLIF BG_030_c_i +0 1 +.names BGACK_030_INT_i.BLIF nEXP_SPACE_D0_i.BLIF N_89 +11 1 +.names pos_clk_un6_bg_030_n.BLIF pos_clk_un6_bg_030_i_n +0 1 +.names SM_AMIGA_1_.BLIF pos_clk_un14_clk_000_n_sync_n.BLIF N_92 +11 1 +.names BG_030_c_i.BLIF pos_clk_un6_bg_030_i_n.BLIF pos_clk_un8_bg_030_0_n +11 1 +.names AS_030_i.BLIF RST_c.BLIF N_102 +11 1 +.names N_286_i.BLIF RST_c.BLIF N_127_i_1 +11 1 +.names A1_c.BLIF BGACK_030_INT_i.BLIF N_103 +11 1 +.names N_288_i.BLIF N_289_i.BLIF N_127_i_2 +11 1 +.names A1_i.BLIF BGACK_030_INT_i.BLIF N_104 +11 1 +.names pos_clk_un24_bgack_030_int_i_0_x2.BLIF N_269_i.BLIF \ +pos_clk_un24_bgack_030_int_i_0_i_1_n +11 1 +.names N_256.BLIF nEXP_SPACE_D0_i.BLIF N_112 +11 1 +.names inst_nEXP_SPACE_D0reg.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF \ +N_80_0_1 +11 1 +.names BGACK_030_INT_i.BLIF inst_RESET_OUTreg.BLIF N_256 +11 1 +.names sm_amiga_i_2__n.BLIF sm_amiga_i_6__n.BLIF N_75_i_1 +11 1 +.names N_258_0.BLIF N_258 +0 1 +.names N_249_i.BLIF AS_030_000_SYNC_i.BLIF N_251_0_1 +11 1 +.names size_c_i_1__n.BLIF A0_c_i.BLIF pos_clk_un11_ds_030_d0_i_1_n +11 1 +.names N_260_0.BLIF N_260 +0 1 +.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_340_1 +11 1 +.names N_265_0.BLIF N_265 +0 1 +.names a_c_17__n.BLIF a_i_16__n.BLIF N_340_2 +11 1 +.names un1_sm_amiga_7_i_m2_un1_n.BLIF un1_sm_amiga_7_i_m2_un0_n.BLIF N_282 +1- 1 +-1 1 +.names a_i_18__n.BLIF a_i_19__n.BLIF N_340_3 +11 1 +.names un1_amiga_bus_enable_dma_high_0_m2_0__un1_n.BLIF \ +un1_amiga_bus_enable_dma_high_0_m2_0__un0_n.BLIF N_71 +1- 1 +-1 1 +.names N_340_1.BLIF N_340_2.BLIF N_340_4 +11 1 +.names AS_030_D0_i.BLIF a_c_20__n.BLIF un5_ciin_1 +11 1 +.names CLK_EXP_c.BLIF CLK_OUT_PRE_D_i.BLIF pos_clk_un11_clk_000_n_sync_n +11 1 +.names a_c_21__n.BLIF a_c_22__n.BLIF un5_ciin_2 +11 1 +.names N_76_i.BLIF N_76 +0 1 +.names a_c_23__n.BLIF a_i_24__n.BLIF un5_ciin_3 +11 1 +.names a_i_25__n.BLIF a_i_26__n.BLIF un5_ciin_4 +11 1 +.names a_i_31__n.BLIF a_i_27__n.BLIF un5_ciin_5 +11 1 +.names a_i_28__n.BLIF a_i_29__n.BLIF un5_ciin_6 +11 1 +.names pos_clk_un22_bgack_030_int_i_n.BLIF pos_clk_un22_bgack_030_int_n +0 1 +.names un5_ciin_1.BLIF un5_ciin_2.BLIF un5_ciin_7 +11 1 +.names N_268_i.BLIF N_268 +0 1 +.names un5_ciin_3.BLIF un5_ciin_4.BLIF un5_ciin_8 +11 1 +.names N_270_i.BLIF N_270 +0 1 +.names un5_ciin_5.BLIF un5_ciin_6.BLIF un5_ciin_9 +11 1 +.names N_73_i.BLIF N_73 +0 1 +.names un5_ciin_7.BLIF un5_ciin_8.BLIF un5_ciin_10 +11 1 +.names N_75_i.BLIF N_75 +0 1 +.names un5_ciin_9.BLIF a_i_30__n.BLIF un5_ciin_11 +11 1 +.names N_251_0.BLIF N_251 +0 1 +.names un22_berr_1.BLIF FPU_SENSE_c.BLIF un22_berr_1_0 +11 1 +.names AS_030_i.BLIF BGACK_000_c.BLIF un22_berr_1 +11 1 +.names FPU_SENSE_i.BLIF N_340.BLIF un21_fpu_cs_1 +11 1 +.names N_95_1.BLIF CLK_000_NE_i.BLIF N_95 +11 1 +.names inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_D0.BLIF pos_clk_un6_bg_030_1_n +11 1 +.names N_94_1.BLIF CLK_000_PE_i.BLIF N_94 +11 1 +.names N_97_i.BLIF N_77_i.BLIF N_131_i_1 +11 1 +.names BERR_i.BLIF SM_AMIGA_5_.BLIF N_288 +11 1 +.names N_94_i.BLIF N_95_i.BLIF N_131_i_2 +11 1 +.names inst_CLK_000_NE.BLIF sm_amiga_i_6__n.BLIF N_289 +11 1 +.names N_131_i_1.BLIF N_131_i_2.BLIF N_131_i_3 +11 1 +.names N_276.BLIF sm_amiga_i_5__n.BLIF N_286 +11 1 +.names N_73_i.BLIF N_75_i.BLIF N_96_1 +11 1 +.names sm_amiga_srsts_i_0_m2_3__un1_n.BLIF sm_amiga_srsts_i_0_m2_3__un0_n.BLIF \ +N_279 +1- 1 +-1 1 +.names N_251.BLIF sm_amiga_i_0__n.BLIF N_96_2 +11 1 +.names N_277_0.BLIF N_277 +0 1 +.names N_96_1.BLIF N_96_2.BLIF N_96_3 +11 1 +.names N_276_0.BLIF N_276 +0 1 +.names N_88_i.BLIF N_90_i.BLIF pos_clk_cpu_est_11_0_1_1__n +11 1 +.names N_62_0.BLIF N_62 +0 1 +.names N_299_i.BLIF N_312_i.BLIF pos_clk_cpu_est_11_0_2_1__n +11 1 +.names N_274_0.BLIF N_274 +0 1 +.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_310_1 +11 1 +.names inst_CLK_000_NE_D0.BLIF N_267.BLIF N_313 +11 1 +.names VMA_INT_i.BLIF VPA_D_i.BLIF N_310_2 +11 1 +.names CLK_030_H_i.BLIF N_277.BLIF N_307 +11 1 +.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF N_310_3 +11 1 +.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_305 +11 1 +.names N_310_1.BLIF N_310_2.BLIF N_310_4 +11 1 +.names N_306_1.BLIF nEXP_SPACE_D0_i.BLIF N_306 +11 1 +.names inst_CLK_000_NE.BLIF N_312.BLIF N_309_1 +11 1 +.names N_303_1.BLIF cpu_est_i_3__n.BLIF N_303 +11 1 +.names VPA_D_i.BLIF cpu_est_2_.BLIF N_309_2 +11 1 +.names N_304_1.BLIF cpu_est_i_2__n.BLIF N_304 +11 1 +.names inst_CLK_000_PE.BLIF N_270_i.BLIF N_308_1 +11 1 +.names inst_AS_000_DMA.BLIF RW_000_i.BLIF N_301 +11 1 +.names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF N_308_2 +11 1 +.names inst_CLK_030_H.BLIF CLK_EXP_c.BLIF N_91 +11 1 +.names RESET_OUT_0_sqmuxa_1.BLIF RST_DLY_1_.BLIF RESET_OUT_0_sqmuxa_5_1 +11 1 +.names N_273.BLIF cpu_est_3_reg.BLIF N_85 +11 1 +.names RESET_OUT_0_sqmuxa_5.BLIF RST_DLY_3_.BLIF RESET_OUT_0_sqmuxa_7_1 +11 1 +.names N_273_i.BLIF cpu_est_i_2__n.BLIF N_294 +11 1 +.names RST_DLY_4_.BLIF RST_DLY_5_.BLIF RESET_OUT_0_sqmuxa_7_2 +11 1 +.names N_296_1.BLIF cpu_est_i_2__n.BLIF N_296 +11 1 +.names RESET_OUT_0_sqmuxa_7_1.BLIF RESET_OUT_0_sqmuxa_7_2.BLIF \ +RESET_OUT_0_sqmuxa_7_3 +11 1 +.names inst_CLK_000_PE.BLIF SM_AMIGA_0_.BLIF N_84 +11 1 +.names N_75.BLIF BERR_i.BLIF N_94_1 +11 1 +.names N_82_1.BLIF SM_AMIGA_2_.BLIF N_82 +11 1 +.names N_73.BLIF BERR_i.BLIF N_95_1 +11 1 +.names N_83_1.BLIF SM_AMIGA_3_.BLIF N_83 +11 1 +.names N_86_i.BLIF N_93_i.BLIF N_119_i_1 +11 1 +.names N_136.BLIF sm_amiga_i_4__n.BLIF N_293 +11 1 +.names N_274.BLIF RST_c.BLIF N_82_1 +11 1 +.names N_275.BLIF sm_amiga_i_5__n.BLIF N_290 +11 1 +.names N_313.BLIF RST_c.BLIF N_83_1 +11 1 +.names CLK_000_NE_i.BLIF sm_amiga_i_4__n.BLIF N_291 +11 1 +.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_296_1 +11 1 +.names N_62.BLIF SM_AMIGA_i_7_.BLIF N_283 +11 1 +.names N_270.BLIF cpu_est_0_.BLIF N_303_1 +11 1 +.names N_251.BLIF sm_amiga_i_6__n.BLIF N_284 +11 1 +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_304_1 +11 1 +.names sm_amiga_srsts_i_0_m2_1__un1_n.BLIF sm_amiga_srsts_i_0_m2_1__un0_n.BLIF \ +N_86 +1- 1 +-1 1 +.names N_269_i.BLIF RW_000_c.BLIF N_306_1 +11 1 +.names N_80_0.BLIF N_80 +0 1 +.names N_283_i.BLIF N_284_i.BLIF N_129_i_1 +11 1 +.names N_78_0.BLIF N_78 +0 1 +.names N_290_i.BLIF N_291_i.BLIF N_125_i_1 +11 1 +.names N_80.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_108 +11 1 +.names N_279_i.BLIF N_293_i.BLIF N_123_i_1 +11 1 +.names N_340.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_109 +11 1 +.names N_84_i.BLIF sm_amiga_i_5__n.BLIF N_115_0_1 +11 1 +.names BGACK_030_INT_i.BLIF N_76.BLIF N_100 +11 1 +.names N_296_i.BLIF N_85_i.BLIF pos_clk_cpu_est_11_0_1_3__n +11 1 +.names BGACK_030_INT_i.BLIF N_76_i.BLIF N_99 +11 1 +.names N_91_i.BLIF RW_000_i.BLIF N_260_0_1 +11 1 +.names N_78.BLIF sm_amiga_i_2__n.BLIF N_93 +11 1 +.names N_307_i.BLIF RST_c.BLIF N_261_i_1 +11 1 +.names pos_clk_un14_clk_000_n_sync_0_n.BLIF pos_clk_un14_clk_000_n_sync_n +0 1 +.names pos_clk_CYCLE_DMA_5_1_i_x2.BLIF N_269_i.BLIF N_262_i_1 +11 1 +.names CLK_000_N_SYNC_9_.BLIF pos_clk_un11_clk_000_n_sync_i_n.BLIF \ +pos_clk_un9_clk_000_n_sync_n +11 1 +.names pos_clk_CYCLE_DMA_5_0_i_x2.BLIF N_269_i.BLIF N_263_i_1 +11 1 +.names N_340_4.BLIF N_340_3.BLIF N_340 +11 1 +.names N_226_i.BLIF N_224_i.BLIF pos_clk_ipl_1_n +11 1 +.names BERR_i.BLIF N_136_i.BLIF N_97 +11 1 +.names inst_CLK_000_NE_D0.BLIF cpu_est_0_3__un3_n +0 1 +.names N_136_i.BLIF N_136 +0 1 +.names pos_clk_cpu_est_11_3__n.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_3__un1_n +11 1 +.names N_81.BLIF sm_amiga_i_0__n.BLIF N_101 +11 1 +.names cpu_est_3_reg.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n +11 1 +.names N_81_0.BLIF N_81 +0 1 +.names inst_CLK_000_NE_D0.BLIF cpu_est_0_2__un3_n +0 1 +.names N_268.BLIF SM_AMIGA_0_.BLIF N_116 +11 1 +.names N_186_i.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_2__un1_n +11 1 +.names N_96_3.BLIF sm_amiga_i_3__n.BLIF N_96 +11 1 +.names cpu_est_2_.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n +11 1 +.names BGACK_000_c.BLIF CLK_000_PE_i.BLIF N_113 +11 1 +.names inst_CLK_000_NE_D0.BLIF cpu_est_0_1__un3_n +0 1 +.names N_275_0.BLIF N_275 +0 1 +.names pos_clk_cpu_est_11_1__n.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_1__un1_n +11 1 +.names N_273_i.BLIF N_273 +0 1 +.names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n +11 1 +.names N_272.BLIF cpu_est_i_0__n.BLIF N_88 +11 1 +.names N_113.BLIF bgack_030_int_0_un3_n +0 1 +.names N_272_i.BLIF N_272 +0 1 +.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c +0 1 +.names inst_BGACK_030_INTreg.BLIF N_113.BLIF bgack_030_int_0_un1_n +11 1 +.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_299 +11 1 +.names BGACK_000_c.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un0_n +11 1 +.names N_270_i.BLIF cpu_est_3_reg.BLIF N_90 +11 1 +.names pos_clk_un7_clk_000_pe_n.BLIF vma_int_0_un3_n +0 1 +.names DTACK_D0_i.BLIF inst_VPA_D.BLIF N_311 +11 1 +.names cpu_est_1_.BLIF pos_clk_un7_clk_000_pe_n.BLIF vma_int_0_un1_n +11 1 +.names N_272_i.BLIF cpu_est_0_.BLIF N_312 +11 1 +.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n +11 1 +.names N_267_0.BLIF N_267 +0 1 +.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUTreg.BLIF un1_as_000_i +11 1 +.names N_115.BLIF rw_000_int_0_un3_n +0 1 +.names N_264_0.BLIF N_264 +0 1 +.names un1_rst_dly_i_m_3__n.BLIF un1_rst_dly_i_m_i_3__n +0 1 +.names N_264.BLIF N_115.BLIF rw_000_int_0_un1_n +11 1 +.names pos_clk_un7_clk_000_pe_0_n.BLIF pos_clk_un7_clk_000_pe_n +0 1 +.names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n +11 1 +.names N_308_1.BLIF N_308_2.BLIF N_308 +11 1 +.names un1_rst_dly_i_m_4__n.BLIF un1_rst_dly_i_m_i_4__n +0 1 +.names SM_AMIGA_3_.BLIF sm_amiga_srsts_i_0_m2_3__un3_n +0 1 +.names N_309_1.BLIF N_309_2.BLIF N_309 +11 1 +.names BERR_i.BLIF SM_AMIGA_3_.BLIF sm_amiga_srsts_i_0_m2_3__un1_n +11 1 +.names IPL_030DFF_2_reg.BLIF IPL_030_2_ +1 1 +0 0 +.names BG_000DFFreg.BLIF BG_000 +1 1 +0 0 +.names inst_BGACK_030_INTreg.BLIF BGACK_030 +1 1 +0 0 +.names gnd_n_n.BLIF CLK_DIV_OUT +1 1 +0 0 +.names CLK_EXP_c.BLIF CLK_EXP +1 1 +0 0 +.names un21_fpu_cs_i.BLIF FPU_CS +1 1 +0 0 +.names inst_DSACK1_INTreg.BLIF DSACK1 +1 1 +0 0 +.names vcc_n_n.BLIF AVEC +1 1 +0 0 +.names cpu_est_3_reg.BLIF E +1 1 +0 0 +.names inst_VMA_INTreg.BLIF VMA +1 1 +0 0 +.names inst_RESET_OUTreg.BLIF RESET +1 1 +0 0 +.names gnd_n_n.BLIF AMIGA_ADDR_ENABLE +1 1 +0 0 +.names AMIGA_BUS_DATA_DIR_c.BLIF AMIGA_BUS_DATA_DIR +1 1 +0 0 +.names un1_amiga_bus_enable_low_i.BLIF AMIGA_BUS_ENABLE_LOW +1 1 +0 0 +.names N_71_i.BLIF AMIGA_BUS_ENABLE_HIGH +1 1 +0 0 +.names un5_ciin.BLIF CIIN +1 1 +0 0 +.names IPL_030DFF_1_reg.BLIF IPL_030_1_ +1 1 +0 0 +.names IPL_030DFF_0_reg.BLIF IPL_030_0_ +1 1 +0 0 +.names CLK_OSZI_c.BLIF IPL_030DFF_2_reg.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF IPL_D0_0_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF IPL_D0_1_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF IPL_D0_2_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_i_7_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C +1 1 +0 0 +.names cpu_est_0_0_x2_0_.BLIF cpu_est_0_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF cpu_est_0_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF cpu_est_1_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF cpu_est_2_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF cpu_est_3_reg.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF IPL_030DFF_0_reg.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF IPL_030DFF_1_reg.C +1 1 +0 0 +.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_9_.C +1 1 +0 0 +.names CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_10_.C +1 1 +0 0 +.names CLK_000_N_SYNC_10_.BLIF CLK_000_N_SYNC_11_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_11_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF RST_DLY_0_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF RST_DLY_1_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF RST_DLY_2_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF RST_DLY_3_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF RST_DLY_4_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF RST_DLY_5_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF RST_DLY_6_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF RST_DLY_7_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF CYCLE_DMA_0_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF CYCLE_DMA_1_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF SIZE_DMA_0_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C +1 1 +0 0 +.names CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_5_.C +1 1 +0 0 +.names CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_6_.C +1 1 +0 0 +.names CLK_000_P_SYNC_6_.BLIF CLK_000_P_SYNC_7_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_7_.C +1 1 +0 0 +.names CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_8_.C +1 1 +0 0 +.names CLK_000_P_SYNC_8_.BLIF CLK_000_P_SYNC_9_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_9_.C +1 1 +0 0 +.names N_249_i.BLIF CLK_000_N_SYNC_0_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_0_.C +1 1 +0 0 +.names CLK_000_N_SYNC_0_.BLIF CLK_000_N_SYNC_1_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_1_.C +1 1 +0 0 +.names CLK_000_N_SYNC_1_.BLIF CLK_000_N_SYNC_2_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_2_.C +1 1 +0 0 +.names CLK_000_N_SYNC_2_.BLIF CLK_000_N_SYNC_3_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_3_.C +1 1 +0 0 +.names CLK_000_N_SYNC_3_.BLIF CLK_000_N_SYNC_4_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_4_.C +1 1 +0 0 +.names CLK_000_N_SYNC_4_.BLIF CLK_000_N_SYNC_5_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_5_.C +1 1 +0 0 +.names CLK_000_N_SYNC_5_.BLIF CLK_000_N_SYNC_6_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_6_.C +1 1 +0 0 +.names CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_7_.C +1 1 +0 0 +.names CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_8_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_0_.C +1 1 +0 0 +.names CLK_000_P_SYNC_0_.BLIF CLK_000_P_SYNC_1_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_1_.C +1 1 +0 0 +.names CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_2_.C +1 1 +0 0 +.names CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_3_.C +1 1 +0 0 +.names CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_4_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_CLK_030_H.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_RESET_OUTreg.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_RW_000_DMA.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_RW_000_INT.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AS_000_INT.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_DSACK1_INTreg.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_A0_DMA.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_DS_000_DMA.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_DS_030_D0.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AS_030_D0.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_nEXP_SPACE_D0reg.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_VPA_D.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_DTACK_D0.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF BG_000DFFreg.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C +1 1 +0 0 +.names CLK_000_P_SYNC_9_.BLIF inst_CLK_000_PE.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_CLK_000_PE.C +1 1 +0 0 +.names CLK_000_N_SYNC_11_.BLIF inst_CLK_000_NE.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_CLK_000_NE.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C +1 1 +0 0 +.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_CLK_000_D1.C +1 1 +0 0 +.names inst_CLK_000_NE.BLIF inst_CLK_000_NE_D0.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_CLK_000_NE_D0.C +1 1 +0 0 +.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_D.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_D.C +1 1 +0 0 +.names CLK_000.BLIF inst_CLK_000_D0.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_CLK_000_D0.C +1 1 +0 0 +.names un3_size.BLIF SIZE_1_ +1 1 +0 0 +.names un6_as_030_i.BLIF AS_030 +1 1 +0 0 +.names un4_as_000_i.BLIF AS_000 +1 1 +0 0 +.names inst_RW_000_INT.BLIF RW_000 +1 1 +0 0 +.names un6_ds_030_i.BLIF DS_030 +1 1 +0 0 +.names un6_uds_000_i.BLIF UDS_000 +1 1 +0 0 +.names un6_lds_000_i.BLIF LDS_000 +1 1 +0 0 +.names inst_A0_DMA.BLIF A0 +1 1 +0 0 +.names gnd_n_n.BLIF BERR +1 1 +0 0 +.names inst_RW_000_DMA.BLIF RW +1 1 +0 0 +.names un4_size.BLIF SIZE_0_ +1 1 +0 0 +.names A_15_.BLIF a_15__n +1 1 +0 0 +.names A_14_.BLIF a_14__n +1 1 +0 0 +.names A_13_.BLIF a_13__n +1 1 +0 0 +.names A_12_.BLIF a_12__n +1 1 +0 0 +.names A_11_.BLIF a_11__n +1 1 +0 0 +.names A_10_.BLIF a_10__n +1 1 +0 0 +.names A_9_.BLIF a_9__n +1 1 +0 0 +.names A_8_.BLIF a_8__n +1 1 +0 0 +.names A_7_.BLIF a_7__n +1 1 +0 0 +.names A_6_.BLIF a_6__n +1 1 +0 0 +.names A_5_.BLIF a_5__n +1 1 +0 0 +.names A_4_.BLIF a_4__n +1 1 +0 0 +.names A_3_.BLIF a_3__n +1 1 +0 0 +.names A_2_.BLIF a_2__n +1 1 +0 0 +.names AS_030.PIN.BLIF AS_030_c +1 1 +0 0 +.names AS_000.PIN.BLIF AS_000_c +1 1 +0 0 +.names RW_000.PIN.BLIF RW_000_c +1 1 +0 0 +.names DS_030.PIN.BLIF DS_030_c +1 1 +0 0 +.names UDS_000.PIN.BLIF UDS_000_c +1 1 +0 0 +.names LDS_000.PIN.BLIF LDS_000_c +1 1 +0 0 +.names SIZE_0_.PIN.BLIF size_c_0__n +1 1 +0 0 +.names SIZE_1_.PIN.BLIF size_c_1__n +1 1 +0 0 +.names A_16_.BLIF a_c_16__n +1 1 +0 0 +.names A_17_.BLIF a_c_17__n +1 1 +0 0 +.names A_18_.BLIF a_c_18__n +1 1 +0 0 +.names A_19_.BLIF a_c_19__n +1 1 +0 0 +.names A_20_.BLIF a_c_20__n +1 1 +0 0 +.names A_21_.BLIF a_c_21__n +1 1 +0 0 +.names A_22_.BLIF a_c_22__n +1 1 +0 0 +.names A_23_.BLIF a_c_23__n +1 1 +0 0 +.names A_24_.BLIF a_c_24__n +1 1 +0 0 +.names A_25_.BLIF a_c_25__n +1 1 +0 0 +.names A_26_.BLIF a_c_26__n +1 1 +0 0 +.names A_27_.BLIF a_c_27__n +1 1 +0 0 +.names A_28_.BLIF a_c_28__n +1 1 +0 0 +.names A_29_.BLIF a_c_29__n +1 1 +0 0 +.names A_30_.BLIF a_c_30__n +1 1 +0 0 +.names A_31_.BLIF a_c_31__n +1 1 +0 0 +.names A0.PIN.BLIF A0_c +1 1 +0 0 +.names A1.BLIF A1_c +1 1 +0 0 +.names nEXP_SPACE.BLIF nEXP_SPACE_c +1 1 +0 0 +.names BERR.PIN.BLIF BERR_c +1 1 +0 0 +.names BG_030.BLIF BG_030_c +1 1 +0 0 +.names BGACK_000.BLIF BGACK_000_c +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_OSZI_c +1 1 +0 0 +.names CLK_030.BLIF CLK_EXP_c +1 1 +0 0 +.names FPU_SENSE.BLIF FPU_SENSE_c +1 1 +0 0 +.names IPL_0_.BLIF ipl_c_0__n +1 1 +0 0 +.names IPL_1_.BLIF ipl_c_1__n +1 1 +0 0 +.names IPL_2_.BLIF ipl_c_2__n +1 1 +0 0 +.names DTACK.BLIF DTACK_c +1 1 +0 0 +.names VPA.BLIF VPA_c +1 1 +0 0 +.names RST.BLIF RST_c +1 1 +0 0 +.names RW.PIN.BLIF RW_c +1 1 +0 0 +.names FC_0_.BLIF fc_c_0__n +1 1 +0 0 +.names FC_1_.BLIF fc_c_1__n +1 1 +0 0 +.names N_112.BLIF AS_030.OE +1 1 +0 0 +.names un1_as_000_i.BLIF AS_000.OE +1 1 +0 0 +.names un1_as_000_i.BLIF RW_000.OE +1 1 +0 0 +.names N_112.BLIF DS_030.OE +1 1 +0 0 +.names un1_as_000_i.BLIF UDS_000.OE +1 1 +0 0 +.names un1_as_000_i.BLIF LDS_000.OE +1 1 +0 0 +.names N_89.BLIF SIZE_0_.OE +1 1 +0 0 +.names N_89.BLIF SIZE_1_.OE +1 1 +0 0 +.names N_112.BLIF A0.OE +1 1 +0 0 +.names un22_berr.BLIF BERR.OE +1 1 +0 0 +.names N_256.BLIF RW.OE +1 1 +0 0 +.names gnd_n_n.BLIF CLK_DIV_OUT.OE +1 1 +0 0 +.names inst_nEXP_SPACE_D0reg.BLIF DSACK1.OE +1 1 +0 0 +.names N_247.BLIF CIIN.OE +1 1 +0 0 +.names inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF pos_clk_RST_DLY_5_iv_0_x2_0_ +01 1 +10 1 +11 0 +00 0 +.names RESET_OUT_0_sqmuxa_1.BLIF RST_DLY_1_.BLIF G_137 +01 1 +10 1 +11 0 +00 0 +.names RESET_OUT_0_sqmuxa_7.BLIF RST_DLY_7_.BLIF G_149 +01 1 +10 1 +11 0 +00 0 +.names N_213.BLIF RST_DLY_6_.BLIF G_147 +01 1 +10 1 +11 0 +00 0 +.names N_211.BLIF RST_DLY_5_.BLIF G_145 +01 1 +10 1 +11 0 +00 0 +.names N_209.BLIF RST_DLY_4_.BLIF G_143 +01 1 +10 1 +11 0 +00 0 +.names RESET_OUT_0_sqmuxa_5.BLIF RST_DLY_3_.BLIF G_141 +01 1 +10 1 +11 0 +00 0 +.names N_205.BLIF RST_DLY_2_.BLIF G_139 +01 1 +10 1 +11 0 +00 0 +.names IPL_D0_0_.BLIF ipl_c_0__n.BLIF G_165 +01 1 +10 1 +11 0 +00 0 +.names IPL_D0_1_.BLIF ipl_c_1__n.BLIF G_166 +01 1 +10 1 +11 0 +00 0 +.names IPL_D0_2_.BLIF ipl_c_2__n.BLIF G_167 +01 1 +10 1 +11 0 +00 0 +.names cpu_est_0_.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_0_x2_0_ +01 1 +10 1 +11 0 +00 0 +.names N_220.BLIF CYCLE_DMA_1_.BLIF pos_clk_CYCLE_DMA_5_1_i_x2 +01 1 +10 1 +11 0 +00 0 +.names CYCLE_DMA_0_.BLIF inst_CLK_000_PE.BLIF pos_clk_CYCLE_DMA_5_0_i_x2 +01 1 +10 1 +11 0 +00 0 +.names CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF pos_clk_un24_bgack_030_int_i_0_x2 +01 1 +10 1 +11 0 +00 0 +.end diff --git a/Logic/BUS68030.cmd b/Logic/BUS68030.cmd new file mode 100644 index 0000000..e7c37a0 --- /dev/null +++ b/Logic/BUS68030.cmd @@ -0,0 +1,8 @@ +STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: "c:/users/matze/documents/github/68030tk/logic" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC diff --git a/Logic/BUS68030.edi b/Logic/BUS68030.edi new file mode 100644 index 0000000..dc02bf2 --- /dev/null +++ b/Logic/BUS68030.edi @@ -0,0 +1,4714 @@ +(edif BUS68030 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timeStamp 2015 5 13 22 59 16) + (author "Synopsys, Inc.") + (program "Synplify Pro" (version "I-2014.03LC , mapper maplat, Build 923R")) + ) + ) + (external mach + (edifLevel 0) + (technology (numberDefinition )) + (cell AND2 (cellType GENERIC) + (view prim (viewType NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + ) + ) + ) + (cell BI_DIR (cellType GENERIC) + (view prim (viewType NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port IO (direction INOUT)) + (port OE (direction INPUT)) + ) + ) + ) + (cell BUFTH (cellType GENERIC) + (view prim (viewType NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port OE (direction INPUT)) + ) + ) + ) + (cell DFF (cellType GENERIC) + (view prim (viewType NETLIST) + (interface + (port Q (direction OUTPUT)) + (port D (direction INPUT)) + (port CLK (direction INPUT)) + ) + ) + ) + (cell IBUF (cellType GENERIC) + (view prim (viewType NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + ) + ) + ) + (cell INV (cellType GENERIC) + (view prim (viewType NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + ) + ) + ) + (cell OBUF (cellType GENERIC) + (view prim (viewType NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + ) + ) + ) + (cell OR2 (cellType GENERIC) + (view prim (viewType NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + ) + ) + ) + (cell XOR2 (cellType GENERIC) + (view prim (viewType NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + ) + ) + ) + ) + (library work + (edifLevel 0) + (technology (numberDefinition )) + (cell BUS68030 (cellType GENERIC) + (view behavioral (viewType NETLIST) + (interface + (port (array (rename size "SIZE(1:0)") 2) (direction INOUT)) + (port (array (rename a "A(31:2)") 30) (direction INPUT)) + (port (array (rename ipl_030 "IPL_030(2:0)") 3) (direction OUTPUT)) + (port (array (rename ipl "IPL(2:0)") 3) (direction INPUT)) + (port (array (rename fc "FC(1:0)") 2) (direction INPUT)) + (port AS_030 (direction INOUT)) + (port AS_000 (direction INOUT)) + (port RW_000 (direction INOUT)) + (port DS_030 (direction INOUT)) + (port UDS_000 (direction INOUT)) + (port LDS_000 (direction INOUT)) + (port A0 (direction INOUT)) + (port A1 (direction INPUT)) + (port nEXP_SPACE (direction INPUT)) + (port BERR (direction INOUT)) + (port BG_030 (direction INPUT)) + (port BG_000 (direction OUTPUT)) + (port BGACK_030 (direction OUTPUT)) + (port BGACK_000 (direction INPUT)) + (port CLK_030 (direction INPUT)) + (port CLK_000 (direction INPUT)) + (port CLK_OSZI (direction INPUT)) + (port CLK_DIV_OUT (direction OUTPUT)) + (port CLK_EXP (direction OUTPUT)) + (port FPU_CS (direction OUTPUT)) + (port FPU_SENSE (direction INPUT)) + (port DSACK1 (direction OUTPUT)) + (port DTACK (direction INPUT)) + (port AVEC (direction OUTPUT)) + (port E (direction OUTPUT)) + (port VPA (direction INPUT)) + (port VMA (direction OUTPUT)) + (port RST (direction INPUT)) + (port RESET (direction OUTPUT)) + (port RW (direction INOUT)) + (port AMIGA_ADDR_ENABLE (direction OUTPUT)) + (port AMIGA_BUS_DATA_DIR (direction OUTPUT)) + (port AMIGA_BUS_ENABLE_LOW (direction OUTPUT)) + (port AMIGA_BUS_ENABLE_HIGH (direction OUTPUT)) + (port CIIN (direction OUTPUT)) + ) + (contents + (instance (rename IPL_030DFF_2 "IPL_030DFF[2]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename IPL_D0_0 "IPL_D0[0]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename IPL_D0_1 "IPL_D0[1]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename IPL_D0_2 "IPL_D0[2]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename SM_AMIGA_6 "SM_AMIGA[6]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename SM_AMIGA_5 "SM_AMIGA[5]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename SM_AMIGA_4 "SM_AMIGA[4]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename SM_AMIGA_3 "SM_AMIGA[3]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename SM_AMIGA_2 "SM_AMIGA[2]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename SM_AMIGA_1 "SM_AMIGA[1]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename SM_AMIGA_0 "SM_AMIGA[0]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename cpu_est_0 "cpu_est[0]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename cpu_est_1 "cpu_est[1]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename cpu_est_2 "cpu_est[2]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename cpu_est_3 "cpu_est[3]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename IPL_030DFF_0 "IPL_030DFF[0]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename IPL_030DFF_1 "IPL_030DFF[1]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_N_SYNC_9 "CLK_000_N_SYNC[9]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_N_SYNC_10 "CLK_000_N_SYNC[10]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_N_SYNC_11 "CLK_000_N_SYNC[11]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename RST_DLY_0 "RST_DLY[0]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename RST_DLY_1 "RST_DLY[1]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename RST_DLY_2 "RST_DLY[2]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename RST_DLY_3 "RST_DLY[3]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename RST_DLY_4 "RST_DLY[4]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename RST_DLY_5 "RST_DLY[5]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename RST_DLY_6 "RST_DLY[6]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename RST_DLY_7 "RST_DLY[7]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CYCLE_DMA_0 "CYCLE_DMA[0]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CYCLE_DMA_1 "CYCLE_DMA[1]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename SIZE_DMA_0 "SIZE_DMA[0]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename SIZE_DMA_1 "SIZE_DMA[1]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_P_SYNC_5 "CLK_000_P_SYNC[5]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_P_SYNC_6 "CLK_000_P_SYNC[6]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_P_SYNC_7 "CLK_000_P_SYNC[7]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_P_SYNC_8 "CLK_000_P_SYNC[8]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_P_SYNC_9 "CLK_000_P_SYNC[9]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_N_SYNC_0 "CLK_000_N_SYNC[0]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_N_SYNC_1 "CLK_000_N_SYNC[1]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_N_SYNC_2 "CLK_000_N_SYNC[2]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_N_SYNC_3 "CLK_000_N_SYNC[3]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_N_SYNC_4 "CLK_000_N_SYNC[4]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_N_SYNC_5 "CLK_000_N_SYNC[5]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_N_SYNC_6 "CLK_000_N_SYNC[6]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_N_SYNC_7 "CLK_000_N_SYNC[7]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_N_SYNC_8 "CLK_000_N_SYNC[8]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_P_SYNC_0 "CLK_000_P_SYNC[0]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_P_SYNC_1 "CLK_000_P_SYNC[1]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_P_SYNC_2 "CLK_000_P_SYNC[2]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_P_SYNC_3 "CLK_000_P_SYNC[3]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_P_SYNC_4 "CLK_000_P_SYNC[4]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance CLK_030_H (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance RESET_OUT (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance DS_000_ENABLE (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance UDS_000_INT (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance RW_000_DMA (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance RW_000_INT (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance LDS_000_INT (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance AS_030_000_SYNC (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance AS_000_INT (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance DSACK1_INT (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance A0_DMA (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance AS_000_DMA (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance DS_000_DMA (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance DS_030_D0 (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance AS_030_D0 (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance nEXP_SPACE_D0 (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance VPA_D (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance DTACK_D0 (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance BGACK_030_INT (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance BG_000DFF (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance AMIGA_BUS_ENABLE_DMA_HIGH (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance AMIGA_BUS_ENABLE_DMA_LOW (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance VMA_INT (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance BGACK_030_INT_D (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance CLK_000_PE (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance CLK_000_NE (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance CLK_OUT_PRE_50 (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance CLK_000_D1 (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance CLK_000_NE_D0 (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance CLK_OUT_PRE_D (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance CLK_000_D0 (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance AS_030 (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) + (instance AS_000 (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) + (instance RW_000 (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) + (instance DS_030 (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) + (instance UDS_000 (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) + (instance LDS_000 (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) + (instance (rename SIZE_0 "SIZE[0]") (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) + (instance (rename SIZE_1 "SIZE[1]") (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) + (instance (rename A_2 "A[2]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_3 "A[3]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_4 "A[4]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_5 "A[5]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_6 "A[6]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_7 "A[7]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_8 "A[8]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_9 "A[9]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_10 "A[10]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_11 "A[11]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_12 "A[12]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_13 "A[13]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_14 "A[14]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_15 "A[15]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_16 "A[16]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_17 "A[17]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_18 "A[18]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_19 "A[19]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_20 "A[20]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_21 "A[21]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_22 "A[22]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_23 "A[23]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_24 "A[24]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_25 "A[25]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_26 "A[26]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_27 "A[27]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_28 "A[28]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_29 "A[29]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_30 "A[30]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_31 "A[31]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance A0 (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) + (instance A1 (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance nEXP_SPACE (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance BERR (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) + (instance BG_030 (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance BG_000 (viewRef prim (cellRef OBUF (libraryRef mach))) ) + (instance BGACK_030 (viewRef prim (cellRef OBUF (libraryRef mach))) ) + (instance BGACK_000 (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance CLK_030 (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance CLK_000 (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance CLK_OSZI (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance CLK_DIV_OUT (viewRef prim (cellRef BUFTH (libraryRef mach))) ) + (instance CLK_EXP (viewRef prim (cellRef OBUF (libraryRef mach))) ) + (instance FPU_CS (viewRef prim (cellRef OBUF (libraryRef mach))) ) + (instance FPU_SENSE (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename IPL_030_0 "IPL_030[0]") (viewRef prim (cellRef OBUF (libraryRef mach))) ) + (instance (rename IPL_030_1 "IPL_030[1]") (viewRef prim (cellRef OBUF (libraryRef mach))) ) + (instance (rename IPL_030_2 "IPL_030[2]") (viewRef prim (cellRef OBUF (libraryRef mach))) ) + (instance (rename IPL_0 "IPL[0]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename IPL_1 "IPL[1]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename IPL_2 "IPL[2]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance DSACK1 (viewRef prim (cellRef BUFTH (libraryRef mach))) ) + (instance DTACK (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance AVEC (viewRef prim (cellRef OBUF (libraryRef mach))) ) + (instance E (viewRef prim (cellRef OBUF (libraryRef mach))) ) + (instance VPA (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance VMA (viewRef prim (cellRef OBUF (libraryRef mach))) ) + (instance RST (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance RESET (viewRef prim (cellRef OBUF (libraryRef mach))) ) + (instance RW (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) + (instance (rename FC_0 "FC[0]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename FC_1 "FC[1]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance AMIGA_ADDR_ENABLE (viewRef prim (cellRef OBUF (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR (viewRef prim (cellRef OBUF (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_LOW (viewRef prim (cellRef OBUF (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_HIGH (viewRef prim (cellRef OBUF (libraryRef mach))) ) + (instance CIIN (viewRef prim (cellRef BUFTH (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_0_3 "pos_clk.cpu_est_11_0_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DS_000_DMA_2_sqmuxa_i_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DS_000_DMA_2_sqmuxa_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_030_H_2_i_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_030_H_2_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_1_i_1 "pos_clk.CYCLE_DMA_5_1_i_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_1_i "pos_clk.CYCLE_DMA_5_1_i") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_0_i_1 "pos_clk.CYCLE_DMA_5_0_i_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_0_i "pos_clk.CYCLE_DMA_5_0_i") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance G_168_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance G_168 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_i_0_a2_1_2 "pos_clk.cpu_est_11_i_0_a2_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_i_0_a2_2 "pos_clk.cpu_est_11_i_0_a2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_i_0_a2_0_1_2 "pos_clk.cpu_est_11_i_0_a2_0_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_i_0_a2_0_2 "pos_clk.cpu_est_11_i_0_a2_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_0_0_a2_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_0_0_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_1_6 "SM_AMIGA_srsts_i_0_1[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_6 "SM_AMIGA_srsts_i_0[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_1_4 "SM_AMIGA_srsts_i_0_1[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_4 "SM_AMIGA_srsts_i_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_1_3 "SM_AMIGA_srsts_i_0_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_3 "SM_AMIGA_srsts_i_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_SM_AMIGA_5_i_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_SM_AMIGA_5_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_0_1_3 "pos_clk.cpu_est_11_0_0_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_OUT_0_sqmuxa_7_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_OUT_0_sqmuxa_7_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_OUT_0_sqmuxa_7 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_a2_1_0_0 "SM_AMIGA_nss_i_i_0_a2_1_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_a2_0 "SM_AMIGA_nss_i_i_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_a2_0_1_0 "SM_AMIGA_nss_i_i_0_a2_0_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_a2_0_0 "SM_AMIGA_nss_i_i_0_a2_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_1_1 "SM_AMIGA_srsts_i_0_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_1 "SM_AMIGA_srsts_i_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_i_a2_1_0_2 "SM_AMIGA_srsts_i_i_a2_1_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_i_a2_2 "SM_AMIGA_srsts_i_i_a2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_i_a2_0_1_2 "SM_AMIGA_srsts_i_i_a2_0_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_i_a2_0_2 "SM_AMIGA_srsts_i_i_a2_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_0_a2_1_1_3 "pos_clk.cpu_est_11_0_0_a2_1_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_0_a2_1_3 "pos_clk.cpu_est_11_0_0_a2_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_0_1 "pos_clk.cpu_est_11_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_i_a2_2_1_2 "SM_AMIGA_srsts_i_i_a2_2_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_i_a2_2_2_2 "SM_AMIGA_srsts_i_i_a2_2_2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_i_a2_2_3_2 "SM_AMIGA_srsts_i_i_a2_2_3[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_i_a2_2_4_2 "SM_AMIGA_srsts_i_i_a2_2_4[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_i_a2_2_2 "SM_AMIGA_srsts_i_i_a2_2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un7_clk_000_pe_0_a2_0_1 "pos_clk.un7_clk_000_pe_0_a2_0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un7_clk_000_pe_0_a2_0_2 "pos_clk.un7_clk_000_pe_0_a2_0_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un7_clk_000_pe_0_a2_0 "pos_clk.un7_clk_000_pe_0_a2_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un7_clk_000_pe_0_a2_1 "pos_clk.un7_clk_000_pe_0_a2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un7_clk_000_pe_0_a2_2 "pos_clk.un7_clk_000_pe_0_a2_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un7_clk_000_pe_0_a2 "pos_clk.un7_clk_000_pe_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_OUT_0_sqmuxa_5_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_OUT_0_sqmuxa_5 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_OUT_0_sqmuxa_7_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un22_berr_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un21_fpu_cs_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un21_fpu_cs_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un6_bg_030_1 "pos_clk.un6_bg_030_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un6_bg_030 "pos_clk.un6_bg_030") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_1_0 "SM_AMIGA_nss_i_i_0_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_2_0 "SM_AMIGA_nss_i_i_0_2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_3_0 "SM_AMIGA_nss_i_i_0_3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_0 "SM_AMIGA_nss_i_i_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_a2_1_1_0 "SM_AMIGA_nss_i_i_0_a2_1_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_a2_1_2_0 "SM_AMIGA_nss_i_i_0_a2_1_2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_a2_1_3_0 "SM_AMIGA_nss_i_i_0_a2_1_3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_a2_1_0 "SM_AMIGA_nss_i_i_0_a2_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_0_1_1 "pos_clk.cpu_est_11_0_0_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_0_2_1 "pos_clk.cpu_est_11_0_0_2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un37_as_030_d0_i_a2_1_4 "pos_clk.un37_as_030_d0_i_a2_1_4") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un37_as_030_d0_i_a2_1 "pos_clk.un37_as_030_d0_i_a2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_ciin_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_ciin_0_a2_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_ciin_0_a2_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_ciin_0_a2_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_ciin_0_a2_5 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_ciin_0_a2_6 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_ciin_0_a2_7 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_ciin_0_a2_8 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_ciin_0_a2_9 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_ciin_0_a2_10 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_ciin_0_a2_11 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_ciin_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un22_berr_0_a2_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_2_5 "SM_AMIGA_srsts_i_0_2[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_5 "SM_AMIGA_srsts_i_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un24_bgack_030_int_i_0_o2_1 "pos_clk.un24_bgack_030_int_i_0_o2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un24_bgack_030_int_i_0_o2 "pos_clk.un24_bgack_030_int_i_0_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un37_as_030_d0_i_o4_1 "pos_clk.un37_as_030_d0_i_o4_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un37_as_030_d0_i_o4 "pos_clk.un37_as_030_d0_i_o4") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_o4_1_1_0 "SM_AMIGA_nss_i_i_0_o4_1_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_o4_1_0 "SM_AMIGA_nss_i_i_0_o4_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_o4_1_0_0 "SM_AMIGA_nss_i_i_0_o4_1_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_o4_0 "SM_AMIGA_nss_i_i_0_o4[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un11_ds_030_d0_1 "pos_clk.un11_ds_030_d0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un11_ds_030_d0 "pos_clk.un11_ds_030_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un37_as_030_d0_i_a2_1_1 "pos_clk.un37_as_030_d0_i_a2_1_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un37_as_030_d0_i_a2_1_2 "pos_clk.un37_as_030_d0_i_a2_1_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un37_as_030_d0_i_a2_1_3 "pos_clk.un37_as_030_d0_i_a2_1_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance LDS_000_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_15_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RW_000_DMA_2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_16_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance UDS_000_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_19_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_LOW_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_20_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_HIGH_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_21_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance BG_000_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance BG_030_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un6_bg_030_i "pos_clk.un6_bg_030_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un8_bg_030_i "pos_clk.un8_bg_030_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_1_5 "SM_AMIGA_srsts_i_0_1[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_D0_0_i_0 "IPL_D0_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance nEXP_SPACE_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance nEXP_SPACE_D0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DS_030_D0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_3_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DS_000_DMA_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_6_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_000_DMA_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_8_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance A0_DMA_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_9_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DSACK1_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_12_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_030_000_SYNC_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_13_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_288_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_289_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance A0_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SIZE_c_i_1 "SIZE_c_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_25_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_1_i_2 "IPL_030_1_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_24_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_1_i_1 "IPL_030_1_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_23_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_1_i_0 "IPL_030_1_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_c_i_2 "IPL_c_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_D0_0_i_2 "IPL_D0_0_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_c_i_1 "IPL_c_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_D0_0_i_1 "IPL_D0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_c_i_0 "IPL_c_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_0_i_3 "pos_clk.cpu_est_11_0_0_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_91_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DS_000_DMA_2_sqmuxa_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_301_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_DS_000_DMA_4_f0_0_i "pos_clk.DS_000_DMA_4_f0_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_305_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_306_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_307_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un14_amiga_bus_data_dir_i_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un24_bgack_030_int_i_0_o2_i "pos_clk.un24_bgack_030_int_i_0_o2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o2_i_6 "SM_AMIGA_srsts_i_0_o2_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o2_i_5 "SM_AMIGA_srsts_i_0_o2_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_030_H_2_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_286_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_000_DMA_1_sqmuxa_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_283_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_284_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_290_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_291_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_279_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_293_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_82_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_83_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_i_i_2 "SM_AMIGA_srsts_i_i_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_84_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_SM_AMIGA_5_i_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_85_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_294_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_296_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_109_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un37_as_030_d0_i_i "pos_clk.un37_as_030_d0_i_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un5_ciin_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un8_ciin_i_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance SIZE_DMA_3_sqmuxa_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_000_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_030_000_SYNC_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_o4_i_0 "SM_AMIGA_nss_i_i_0_o4_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un3_as_030_d0_i_i_o2_i "pos_clk.un3_as_030_d0_i_i_o2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance SIZE_DMA_3_sqmuxa_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_o4_1_i_0 "SM_AMIGA_nss_i_i_0_o4_1_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_o4_i_0 "pos_clk.SIZE_DMA_6_0_0_o4_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o4_i_1 "SM_AMIGA_srsts_i_0_o4_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un37_as_030_d0_i_o4_i "pos_clk.un37_as_030_d0_i_o4_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_EXP_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_116_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_o4_0_i_0 "SM_AMIGA_nss_i_i_0_o4_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_101_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename CLK_000_N_SYNC_i_10 "CLK_000_N_SYNC_i[10]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_n_sync_i "pos_clk.un9_clk_000_n_sync_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un14_clk_000_n_sync_i "pos_clk.un14_clk_000_n_sync_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un22_bgack_030_int_i_0 "pos_clk.un22_bgack_030_int_i_0") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_86_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_93_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_99_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_i_1 "pos_clk.SIZE_DMA_6_0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_100_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_i_0 "pos_clk.SIZE_DMA_6_0_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DSACK1_INT_1_sqmuxa_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_108_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un7_clk_000_pe_0_i "pos_clk.un7_clk_000_pe_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DS_000_ENABLE_1_sqmuxa_i_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_304_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_303_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance VPA_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance VPA_D_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DTACK_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DTACK_D0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_97_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_96_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_95_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_94_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_313_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_o3_0_o2_i_3 "SM_AMIGA_srsts_i_o3_0_o2_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o4_i_0 "SM_AMIGA_srsts_i_0_o4_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_312_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_90_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_88_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_299_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o2_i_4 "SM_AMIGA_srsts_i_0_o2_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_i_o2_i_2 "SM_AMIGA_srsts_i_i_o2_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_0_o2_i_3 "pos_clk.cpu_est_11_0_0_o2_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_0_o2_i_1 "pos_clk.cpu_est_11_0_0_o2_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_i_0_o2_i_2 "pos_clk.cpu_est_11_i_0_o2_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_o3_0_i_o2_i_0 "SM_AMIGA_srsts_i_o3_0_i_o2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_310_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_311_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_i_o2_0_i_2 "SM_AMIGA_srsts_i_i_o2_0_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_309_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_308_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename un1_RST_DLY_i_m_i_6 "un1_RST_DLY_i_m_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename un1_RST_DLY_i_m_i_7 "un1_RST_DLY_i_m_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename un1_RST_DLY_i_m_i_8 "un1_RST_DLY_i_m_i[8]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename un1_RST_DLY_i_m_i_2 "un1_RST_DLY_i_m_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_98_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_105_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_22_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance BGACK_030_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_18_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance VMA_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_14_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RW_000_INT_2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_10_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_000_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_0_i_1 "pos_clk.cpu_est_11_0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename un1_RST_DLY_i_m_i_3 "un1_RST_DLY_i_m_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename un1_RST_DLY_i_m_i_4 "un1_RST_DLY_i_m_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename un1_RST_DLY_i_m_i_5 "un1_RST_DLY_i_m_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RESET_OUT_0_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename un1_RST_DLY_i_3 "un1_RST_DLY_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename un1_RST_DLY_i_m_3 "un1_RST_DLY_i_m[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_OUT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance BGACK_030_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_as_000_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance G_146 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance G_144 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance G_142 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance N_71_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_amiga_bus_enable_low_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un21_fpu_cs_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance G_141 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance G_139 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance (rename pos_clk_RST_DLY_5_iv_6 "pos_clk.RST_DLY_5_iv[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename un1_RST_DLY_i_7 "un1_RST_DLY_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename un1_RST_DLY_i_m_7 "un1_RST_DLY_i_m[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_RST_DLY_5_iv_5 "pos_clk.RST_DLY_5_iv[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename un1_RST_DLY_i_6 "un1_RST_DLY_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename un1_RST_DLY_i_m_6 "un1_RST_DLY_i_m[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_RST_DLY_5_iv_4 "pos_clk.RST_DLY_5_iv[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename un1_RST_DLY_i_5 "un1_RST_DLY_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename un1_RST_DLY_i_m_5 "un1_RST_DLY_i_m[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_RST_DLY_5_iv_3 "pos_clk.RST_DLY_5_iv[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename un1_RST_DLY_i_4 "un1_RST_DLY_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename un1_RST_DLY_i_m_4 "un1_RST_DLY_i_m[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_RST_DLY_5_iv_2 "pos_clk.RST_DLY_5_iv[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_OUT_2_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance N_87_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_RST_DLY_5_iv_0_a2_0 "pos_clk.RST_DLY_5_iv_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename un1_RST_DLY_i_2 "un1_RST_DLY_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename un1_RST_DLY_i_m_2 "un1_RST_DLY_i_m[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_RST_DLY_5_iv_1 "pos_clk.RST_DLY_5_iv[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename un1_RST_DLY_i_8 "un1_RST_DLY_i[8]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename un1_RST_DLY_i_m_8 "un1_RST_DLY_i_m[8]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_RST_DLY_5_iv_7 "pos_clk.RST_DLY_5_iv[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_OUT_0_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance G_137 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance G_149 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance G_147 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance G_145 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance G_143 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance (rename cpu_est_0_3__r "cpu_est_0_3_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_0_3__m "cpu_est_0_3_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_3__n "cpu_est_0_3_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_3__p "cpu_est_0_3_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename cpu_est_0_2__r "cpu_est_0_2_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_0_2__m "cpu_est_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_2__n "cpu_est_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_2__p "cpu_est_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename cpu_est_0_1__r "cpu_est_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_0_1__m "cpu_est_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_1__n "cpu_est_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_1__p "cpu_est_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance AS_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RW_000_INT_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VMA_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance BGACK_030_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BGACK_030_INT_0_r "BGACK_030_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename BGACK_030_INT_0_m "BGACK_030_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BGACK_030_INT_0_n "BGACK_030_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BGACK_030_INT_0_p "BGACK_030_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename VMA_INT_0_r "VMA_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename VMA_INT_0_m "VMA_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename VMA_INT_0_n "VMA_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename VMA_INT_0_p "VMA_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename RW_000_INT_0_r "RW_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename RW_000_INT_0_m "RW_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename RW_000_INT_0_n "RW_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename RW_000_INT_0_p "RW_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance G_136 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance G_138 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_RST_DLY_5_iv_0_x2_0 "pos_clk.RST_DLY_5_iv_0_x2[0]") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance RESET_OUT_2_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_RST_DLY_5_iv_0_0 "pos_clk.RST_DLY_5_iv_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_i_o2_2 "SM_AMIGA_srsts_i_i_o2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o2_4 "SM_AMIGA_srsts_i_0_o2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_0_x2_0 "cpu_est_0_0_x2[0]") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance CLK_000_PE_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_234 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_m2_3__r "SM_AMIGA_srsts_i_0_m2_3_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_m2_3__m "SM_AMIGA_srsts_i_0_m2_3_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_m2_3__n "SM_AMIGA_srsts_i_0_m2_3_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_m2_3__p "SM_AMIGA_srsts_i_0_m2_3_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_1_i_x2 "pos_clk.CYCLE_DMA_5_1_i_x2") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_0_i_x2 "pos_clk.CYCLE_DMA_5_0_i_x2") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance (rename cpu_est_i_1 "cpu_est_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance VMA_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance VPA_D_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_i_3 "cpu_est_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_i_0 "cpu_est_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance G_160 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_0_a2_1_1 "pos_clk.cpu_est_11_0_0_a2_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DTACK_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_i_a2_3_2 "SM_AMIGA_srsts_i_i_a2_3[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_0_a2_2_1 "pos_clk.cpu_est_11_0_0_a2_2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_i_a2_1_2 "SM_AMIGA_srsts_i_i_a2_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_i_0_2 "pos_clk.cpu_est_11_i_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DS_000_ENABLE_1_sqmuxa_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un7_clk_000_pe_0 "pos_clk.un7_clk_000_pe_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_i_o2_0_2 "SM_AMIGA_srsts_i_i_o2_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_o3_0_i_o2_0 "SM_AMIGA_srsts_i_o3_0_i_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_i_2 "cpu_est_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_i_0_o2_2 "pos_clk.cpu_est_11_i_0_o2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_0_o2_1 "pos_clk.cpu_est_11_0_0_o2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_0_o2_3 "pos_clk.cpu_est_11_0_0_o2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_a2_3 "SM_AMIGA_srsts_i_0_a2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_o3_0_o2_3 "SM_AMIGA_srsts_i_o3_0_o2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DTACK_D0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VPA_D_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un4_bgack_000_i_a2 "pos_clk.un4_bgack_000_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_m2_1__r "SM_AMIGA_srsts_i_0_m2_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_m2_1__m "SM_AMIGA_srsts_i_0_m2_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_m2_1__n "SM_AMIGA_srsts_i_0_m2_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_m2_1__p "SM_AMIGA_srsts_i_0_m2_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_a2_4 "SM_AMIGA_srsts_i_0_a2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_SM_AMIGA_5_i_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_0_a2_3 "pos_clk.cpu_est_11_0_0_a2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_0_a2_0_3 "pos_clk.cpu_est_11_0_0_a2_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_0_a2_1 "pos_clk.cpu_est_11_0_0_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_0_a2_0_1 "pos_clk.cpu_est_11_0_0_a2_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_n_sync "pos_clk.un9_clk_000_n_sync") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_OUT_PRE_D_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un11_clk_000_n_sync "pos_clk.un11_clk_000_n_sync") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_a2_2_0 "SM_AMIGA_nss_i_i_0_a2_2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_a2_0 "SM_AMIGA_srsts_i_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_a4_0 "SM_AMIGA_nss_i_i_0_a4[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0 "SM_AMIGA_srsts_i_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_o4_0_0 "SM_AMIGA_nss_i_i_0_o4_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_o2_0 "SM_AMIGA_nss_i_i_0_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o4_0 "SM_AMIGA_srsts_i_0_o4[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_a2_0_6 "SM_AMIGA_srsts_i_0_a2_0[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_000_NE_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_a2_0_4 "SM_AMIGA_srsts_i_0_a2_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance I_237 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_030_D0_0_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_a2_0 "pos_clk.SIZE_DMA_6_0_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_a2_1 "pos_clk.SIZE_DMA_6_0_0_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_a2_1 "SM_AMIGA_srsts_i_0_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DSACK1_INT_0_sqmuxa_i_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance nEXP_SPACE_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_as_030_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance I_235 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_236 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un22_bgack_030_int "pos_clk.un22_bgack_030_int") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DS_000_ENABLE_1_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un14_clk_000_n_sync "pos_clk.un14_clk_000_n_sync") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un11_clk_000_n_sync_i "pos_clk.un11_clk_000_n_sync_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un37_as_030_d0_i "pos_clk.un37_as_030_d0_i") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DSACK1_INT_1_sqmuxa_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_0 "pos_clk.SIZE_DMA_6_0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_1 "pos_clk.SIZE_DMA_6_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un2_rw_i_a4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_000_D1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_CLK_000_P_SYNC_2_0_a2_0 "pos_clk.CLK_000_P_SYNC_2_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un3_as_030_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un37_as_030_d0_i_a2_0 "pos_clk.un37_as_030_d0_i_a2_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un37_as_030_d0_i_a2 "pos_clk.un37_as_030_d0_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_INT_1_sqmuxa_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_A0_DMA_3_0_a2 "pos_clk.A0_DMA_3_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance A1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2 "pos_clk.AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2 "pos_clk.AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_0_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance I_238 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_DS_000_DMA_4_f0_0_a2 "pos_clk.DS_000_DMA_4_f0_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DS_000_DMA_2_sqmuxa_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_a2_1_5 "SM_AMIGA_srsts_i_0_a2_1[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_a2_0_5 "SM_AMIGA_srsts_i_0_a2_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_a2_5 "SM_AMIGA_srsts_i_0_a2[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_a2_6 "SM_AMIGA_srsts_i_0_a2[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o4_1 "SM_AMIGA_srsts_i_0_o4[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_o4_0 "pos_clk.SIZE_DMA_6_0_0_o4[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance SIZE_DMA_3_sqmuxa_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un3_as_030_d0_i_i_o2 "pos_clk.un3_as_030_d0_i_i_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_CLK_000_N_SYNC_2_0_o4_0 "pos_clk.CLK_000_N_SYNC_2_0_o4[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance SIZE_DMA_3_sqmuxa_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un8_ciin_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o2_5 "SM_AMIGA_srsts_i_0_o2[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o2_6 "SM_AMIGA_srsts_i_0_o2[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_1_i_o2 "pos_clk.CYCLE_DMA_5_1_i_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un24_bgack_030_int_i_0_x2 "pos_clk.un24_bgack_030_int_i_0_x2") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance un14_amiga_bus_data_dir_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_DS_000_DMA_4_f0_0 "pos_clk.DS_000_DMA_4_f0_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_i_7 "SM_AMIGA_i_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_i_2 "SM_AMIGA_srsts_i_i[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_DMA_1_sqmuxa_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_DMA_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_239 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un6_as_030_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_030_H_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_030_H_2_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance G_167 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance (rename A_i_16 "A_i[16]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SIZE_DMA_i_1 "SIZE_DMA_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un4_size (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SIZE_DMA_i_0 "SIZE_DMA_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un3_size (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_24 "A_i[24]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un22_berr_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance FPU_SENSE_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_HIGH_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__r "un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__m "un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__n "un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__p "un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance I_240 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename un1_SM_AMIGA_7_i_m2_r "un1_SM_AMIGA_7_i_m2.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename un1_SM_AMIGA_7_i_m2_m "un1_SM_AMIGA_7_i_m2.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename un1_SM_AMIGA_7_i_m2_n "un1_SM_AMIGA_7_i_m2.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename un1_SM_AMIGA_7_i_m2_p "un1_SM_AMIGA_7_i_m2.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance CLK_030_H_2_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance LDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un6_lds_000 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance UDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un6_uds_000 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename A_i_25 "A_i[25]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_26 "A_i[26]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_27 "A_i[27]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_28 "A_i[28]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_29 "A_i[29]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_30 "A_i[30]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_31 "A_i[31]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_18 "A_i[18]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_19 "A_i[19]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance G_165 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance G_166 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_OUT_PRE_50_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_224_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_225_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_226_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_242 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un6_lds_000_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance N_102_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DS_030_D0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance nEXP_SPACE_D0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_D0_0_0 "IPL_D0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_D0_0_1 "IPL_D0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_D0_0_2 "IPL_D0_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_1_0 "IPL_030_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_1_1 "IPL_030_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_1_2 "IPL_030_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_0__r "SIZE_DMA_0_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_0__m "SIZE_DMA_0_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_0__n "SIZE_DMA_0_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_0__p "SIZE_DMA_0_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_1__r "SIZE_DMA_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_1__m "SIZE_DMA_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_1__n "SIZE_DMA_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_1__p "SIZE_DMA_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename IPL_030_0_0__r "IPL_030_0_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_0_0__m "IPL_030_0_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_0__n "IPL_030_0_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_0__p "IPL_030_0_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename IPL_030_0_1__r "IPL_030_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_0_1__m "IPL_030_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_1__n "IPL_030_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_1__p "IPL_030_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename IPL_030_0_2__r "IPL_030_0_2_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_0_2__m "IPL_030_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_2__n "IPL_030_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_2__p "IPL_030_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance N_104_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_r "AMIGA_BUS_ENABLE_DMA_HIGH_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_m "AMIGA_BUS_ENABLE_DMA_HIGH_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_n "AMIGA_BUS_ENABLE_DMA_HIGH_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_p "AMIGA_BUS_ENABLE_DMA_HIGH_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename BG_000_0_r "BG_000_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename BG_000_0_m "BG_000_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BG_000_0_n "BG_000_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BG_000_0_p "BG_000_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance DS_000_ENABLE_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance BG_000_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_HIGH_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_LOW_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance UDS_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RW_000_DMA_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance LDS_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_000_SYNC_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DSACK1_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance A0_DMA_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_DMA_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DS_000_DMA_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un6_lds_000_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename DS_000_DMA_0_r "DS_000_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename DS_000_DMA_0_m "DS_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DS_000_DMA_0_n "DS_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DS_000_DMA_0_p "DS_000_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename AS_000_DMA_0_r "AS_000_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AS_000_DMA_0_m "AS_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_000_DMA_0_n "AS_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_000_DMA_0_p "AS_000_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename A0_DMA_0_r "A0_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A0_DMA_0_m "A0_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename A0_DMA_0_n "A0_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename A0_DMA_0_p "A0_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance N_92_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename DSACK1_INT_0_r "DSACK1_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename DSACK1_INT_0_m "DSACK1_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DSACK1_INT_0_n "DSACK1_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DSACK1_INT_0_p "DSACK1_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename AS_000_INT_0_r "AS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AS_000_INT_0_m "AS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_000_INT_0_n "AS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_000_INT_0_p "AS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance N_282_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename DS_000_ENABLE_0_r "DS_000_ENABLE_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename DS_000_ENABLE_0_m "DS_000_ENABLE_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DS_000_ENABLE_0_n "DS_000_ENABLE_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DS_000_ENABLE_0_p "DS_000_ENABLE_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename AS_030_000_SYNC_0_r "AS_030_000_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AS_030_000_SYNC_0_m "AS_030_000_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_030_000_SYNC_0_n "AS_030_000_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_030_000_SYNC_0_p "AS_030_000_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename LDS_000_INT_0_r "LDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename LDS_000_INT_0_m "LDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename LDS_000_INT_0_n "LDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename LDS_000_INT_0_p "LDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename RW_000_DMA_0_r "RW_000_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename RW_000_DMA_0_m "RW_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename RW_000_DMA_0_n "RW_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename RW_000_DMA_0_p "RW_000_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_r "UDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_m "UDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_n "UDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_p "UDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance N_103_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_r "AMIGA_BUS_ENABLE_DMA_LOW_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_m "AMIGA_BUS_ENABLE_DMA_LOW_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_n "AMIGA_BUS_ENABLE_DMA_LOW_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_p "AMIGA_BUS_ENABLE_DMA_LOW_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance DS_030_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un3_ds_030_d0 "pos_clk.un3_ds_030_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_LOW_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_amiga_bus_enable_low (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un8_bg_030 "pos_clk.un8_bg_030") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un6_as_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un4_as_000 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un4_as_000_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DS_000_DMA_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un6_ds_030 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un6_ds_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un6_uds_000_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (net BGACK_030_INT (joined + (portRef Q (instanceRef BGACK_030_INT)) + (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__m)) + (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__r)) + (portRef I0 (instanceRef SIZE_DMA_3_sqmuxa_i_o2)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_a2)) + (portRef I0 (instanceRef BGACK_030_INT_0_m)) + (portRef I0 (instanceRef un1_as_000_0)) + (portRef I0 (instanceRef BGACK_030_INT_i)) + (portRef I0 (instanceRef BGACK_030)) + )) + (net VCC (joined + (portRef I0 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(instanceRef pos_clk_cpu_est_11_i_0_a2_0_1_2)) + )) + (net AS_000_INT (joined + (portRef Q (instanceRef AS_000_INT)) + (portRef I0 (instanceRef AS_000_INT_i)) + (portRef I0 (instanceRef AS_000_INT_0_m)) + )) + (net (rename SM_AMIGA_5 "SM_AMIGA[5]") (joined + (portRef Q (instanceRef SM_AMIGA_5)) + (portRef I1 (instanceRef un1_SM_AMIGA_7_i_m2_m)) + (portRef I0 (instanceRef un1_SM_AMIGA_7_i_m2_r)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a2_0_5)) + (portRef I1 (instanceRef DS_000_ENABLE_1_sqmuxa_i_0)) + (portRef I0 (instanceRef SM_AMIGA_i_5)) + )) + (net AMIGA_BUS_ENABLE_DMA_LOW (joined + (portRef Q (instanceRef AMIGA_BUS_ENABLE_DMA_LOW)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_i)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_n)) + )) + (net AS_030_D0 (joined + (portRef Q (instanceRef AS_030_D0)) + (portRef I0 (instanceRef AS_030_D0_i)) + (portRef I1 (instanceRef pos_clk_un6_bg_030_1)) + )) + (net nEXP_SPACE_D0 (joined + (portRef Q (instanceRef nEXP_SPACE_D0)) + (portRef I0 (instanceRef nEXP_SPACE_D0_i)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_o4_0)) + (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_o4_1)) + (portRef I0 (instanceRef pos_clk_un6_bg_030_1)) + (portRef OE (instanceRef DSACK1)) + )) + (net DS_030_D0 (joined + (portRef Q (instanceRef DS_030_D0)) + (portRef I0 (instanceRef DS_030_D0_i)) + )) + (net AS_030_000_SYNC (joined + (portRef Q (instanceRef AS_030_000_SYNC)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_m)) + (portRef I0 (instanceRef AS_030_000_SYNC_i)) + )) + (net BGACK_030_INT_D (joined + (portRef Q (instanceRef BGACK_030_INT_D)) + (portRef I1 (instanceRef SIZE_DMA_3_sqmuxa_i_o2)) + )) + (net AS_000_DMA (joined + (portRef Q (instanceRef AS_000_DMA)) + (portRef I0 (instanceRef AS_000_DMA_0_n)) + (portRef I0 (instanceRef AS_000_DMA_i)) + (portRef I0 (instanceRef pos_clk_DS_000_DMA_4_f0_0_a2)) + )) + (net DS_000_DMA (joined + (portRef Q (instanceRef DS_000_DMA)) + (portRef I0 (instanceRef DS_000_DMA_i)) + (portRef I0 (instanceRef DS_000_DMA_0_n)) + )) + (net (rename CYCLE_DMA_0 "CYCLE_DMA[0]") (joined + (portRef Q (instanceRef CYCLE_DMA_0)) + (portRef I0 (instanceRef pos_clk_un24_bgack_030_int_i_0_x2)) + (portRef I1 (instanceRef G_160)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i_x2)) + )) + (net (rename CYCLE_DMA_1 "CYCLE_DMA[1]") (joined + (portRef Q (instanceRef CYCLE_DMA_1)) + (portRef I1 (instanceRef pos_clk_un24_bgack_030_int_i_0_x2)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_1_i_x2)) + )) + (net (rename SIZE_DMA_0 "SIZE_DMA[0]") (joined + (portRef Q (instanceRef SIZE_DMA_0)) + (portRef I0 (instanceRef SIZE_DMA_0_0__n)) + (portRef I0 (instanceRef SIZE_DMA_i_0)) + (portRef I0 (instanceRef un4_size)) + )) + (net (rename SIZE_DMA_1 "SIZE_DMA[1]") (joined + (portRef Q (instanceRef SIZE_DMA_1)) + (portRef I0 (instanceRef SIZE_DMA_0_1__n)) + (portRef I0 (instanceRef un3_size)) + (portRef I0 (instanceRef SIZE_DMA_i_1)) + )) + (net VPA_D (joined + (portRef Q (instanceRef VPA_D)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_a2_3_2)) + (portRef I0 (instanceRef VPA_D_i)) + )) + (net UDS_000_INT (joined + (portRef Q (instanceRef UDS_000_INT)) + (portRef I0 (instanceRef UDS_000_INT_0_n)) + (portRef I0 (instanceRef UDS_000_INT_i)) + )) + (net LDS_000_INT (joined + (portRef Q (instanceRef LDS_000_INT)) + (portRef I0 (instanceRef LDS_000_INT_0_n)) + (portRef I0 (instanceRef LDS_000_INT_i)) + )) + (net CLK_OUT_PRE_D (joined + (portRef Q (instanceRef CLK_OUT_PRE_D)) + (portRef I0 (instanceRef CLK_OUT_PRE_D_i)) + )) + (net DTACK_D0 (joined + (portRef Q (instanceRef DTACK_D0)) + (portRef I0 (instanceRef DTACK_D0_i)) + )) + (net CLK_OUT_PRE_50 (joined + (portRef Q (instanceRef CLK_OUT_PRE_50)) + (portRef I0 (instanceRef CLK_OUT_PRE_50_i)) + (portRef D (instanceRef CLK_OUT_PRE_D)) + )) + (net CLK_000_D1 (joined + (portRef Q (instanceRef CLK_000_D1)) + (portRef I1 (instanceRef pos_clk_CLK_000_N_SYNC_2_0_o4_0)) + (portRef I0 (instanceRef CLK_000_D1_i)) + )) + (net CLK_000_D0 (joined + (portRef Q (instanceRef CLK_000_D0)) + (portRef I0 (instanceRef pos_clk_CLK_000_P_SYNC_2_0_a2_0)) + (portRef I0 (instanceRef CLK_000_D0_i)) + (portRef I1 (instanceRef pos_clk_un6_bg_030)) + (portRef D (instanceRef CLK_000_D1)) + )) + (net CLK_000_PE (joined + (portRef Q (instanceRef CLK_000_PE)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_5)) + (portRef I0 (instanceRef un1_SM_AMIGA_5_i_0_a2)) + (portRef I0 (instanceRef G_160)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i_x2)) + (portRef I0 (instanceRef CLK_000_PE_i)) + (portRef I0 (instanceRef pos_clk_un7_clk_000_pe_0_a2_1)) + )) + (net (rename CLK_000_P_SYNC_9 "CLK_000_P_SYNC[9]") (joined + (portRef Q (instanceRef CLK_000_P_SYNC_9)) + (portRef D (instanceRef CLK_000_PE)) + )) + (net CLK_000_NE (joined + (portRef Q (instanceRef CLK_000_NE)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_a2_1_5)) + (portRef I0 (instanceRef CLK_000_NE_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o4_0)) + (portRef I0 (instanceRef pos_clk_RST_DLY_5_iv_0_x2_0)) + (portRef I0 (instanceRef G_136)) + (portRef I0 (instanceRef pos_clk_un7_clk_000_pe_0_a2_0_1)) + (portRef D (instanceRef CLK_000_NE_D0)) + )) + (net (rename CLK_000_N_SYNC_11 "CLK_000_N_SYNC[11]") (joined + (portRef Q (instanceRef CLK_000_N_SYNC_11)) + (portRef D (instanceRef CLK_000_NE)) + )) + (net (rename cpu_est_2 "cpu_est[2]") (joined + (portRef Q (instanceRef cpu_est_2)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_i_0_o2_2)) + (portRef I0 (instanceRef cpu_est_i_2)) + (portRef I0 (instanceRef cpu_est_0_2__n)) + (portRef I1 (instanceRef pos_clk_un7_clk_000_pe_0_a2_0_2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_a2_2_3_2)) + )) + (net (rename IPL_D0_0 "IPL_D0[0]") (joined + (portRef Q (instanceRef IPL_D0_0)) + (portRef I0 (instanceRef G_165)) + )) + (net (rename IPL_D0_1 "IPL_D0[1]") (joined + (portRef Q (instanceRef IPL_D0_1)) + (portRef I0 (instanceRef G_166)) + )) + (net (rename IPL_D0_2 "IPL_D0[2]") (joined + (portRef Q (instanceRef IPL_D0_2)) + (portRef I0 (instanceRef G_167)) + )) + (net (rename SM_AMIGA_3 "SM_AMIGA[3]") (joined + (portRef Q (instanceRef SM_AMIGA_3)) + (portRef I0 (instanceRef SM_AMIGA_i_3)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_o3_0_o2_3)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_m2_3__m)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_m2_3__r)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_a2_0_2)) + )) + (net CLK_000_NE_D0 (joined + (portRef Q (instanceRef CLK_000_NE_D0)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_a2_1_2)) + (portRef I0 (instanceRef cpu_est_0_0_x2_0)) + (portRef I1 (instanceRef cpu_est_0_1__m)) + (portRef I0 (instanceRef cpu_est_0_1__r)) + (portRef I1 (instanceRef cpu_est_0_2__m)) + (portRef I0 (instanceRef cpu_est_0_2__r)) + (portRef I1 (instanceRef cpu_est_0_3__m)) + (portRef I0 (instanceRef cpu_est_0_3__r)) + )) + (net (rename pos_clk_un6_bg_030 "pos_clk.un6_bg_030") (joined + (portRef O (instanceRef pos_clk_un6_bg_030)) + (portRef I0 (instanceRef pos_clk_un6_bg_030_i)) + )) + (net (rename SM_AMIGA_0 "SM_AMIGA[0]") (joined + (portRef Q (instanceRef SM_AMIGA_0)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_a4_0)) + (portRef I1 (instanceRef un1_SM_AMIGA_5_i_0_a2)) + (portRef I0 (instanceRef SM_AMIGA_i_0)) + )) + (net AMIGA_BUS_ENABLE_DMA_HIGH (joined + (portRef Q (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_n)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_i)) + )) + (net DSACK1_INT (joined + (portRef Q (instanceRef DSACK1_INT)) + (portRef I0 (instanceRef DSACK1_INT_0_n)) + (portRef I0 (instanceRef DSACK1)) + )) + (net (rename pos_clk_CLK_000_P_SYNC_2_0 "pos_clk.CLK_000_P_SYNC_2[0]") (joined + (portRef O (instanceRef pos_clk_CLK_000_P_SYNC_2_0_a2_0)) + (portRef D (instanceRef CLK_000_P_SYNC_0)) + )) + (net (rename pos_clk_ipl "pos_clk.ipl") (joined + (portRef O (instanceRef G_168)) + (portRef I1 (instanceRef IPL_030_0_2__m)) + (portRef I0 (instanceRef IPL_030_0_2__r)) + (portRef I1 (instanceRef IPL_030_0_1__m)) + (portRef I0 (instanceRef IPL_030_0_1__r)) + (portRef I1 (instanceRef IPL_030_0_0__m)) + (portRef I0 (instanceRef IPL_030_0_0__r)) + )) + (net (rename pos_clk_un3_ds_030_d0 "pos_clk.un3_ds_030_d0") (joined + (portRef O (instanceRef pos_clk_un3_ds_030_d0)) + (portRef I1 (instanceRef UDS_000_INT_0_m)) + (portRef I0 (instanceRef UDS_000_INT_0_r)) + (portRef I1 (instanceRef LDS_000_INT_0_m)) + (portRef I0 (instanceRef LDS_000_INT_0_r)) + )) + (net (rename SM_AMIGA_6 "SM_AMIGA[6]") (joined + (portRef Q (instanceRef SM_AMIGA_6)) + (portRef I1 (instanceRef pos_clk_un3_ds_030_d0)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_o2_6)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_o2_5)) + (portRef I0 (instanceRef SM_AMIGA_i_6)) + )) + (net AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa_0_a2)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa_i)) + )) + (net (rename RST_DLY_0 "RST_DLY[0]") (joined + (portRef Q (instanceRef RST_DLY_0)) + (portRef I1 (instanceRef pos_clk_RST_DLY_5_iv_0_x2_0)) + (portRef I1 (instanceRef G_136)) + )) + (net (rename RST_DLY_1 "RST_DLY[1]") (joined + (portRef Q (instanceRef RST_DLY_1)) + (portRef I1 (instanceRef G_138)) + (portRef I1 (instanceRef G_137)) + (portRef I1 (instanceRef RESET_OUT_0_sqmuxa_5_1)) + )) + (net (rename RST_DLY_2 "RST_DLY[2]") (joined + (portRef Q (instanceRef RST_DLY_2)) + (portRef I1 (instanceRef G_139)) + (portRef I1 (instanceRef RESET_OUT_0_sqmuxa_5)) + )) + (net (rename RST_DLY_3 "RST_DLY[3]") (joined + (portRef Q (instanceRef RST_DLY_3)) + (portRef I1 (instanceRef G_141)) + (portRef I1 (instanceRef G_142)) + (portRef I1 (instanceRef RESET_OUT_0_sqmuxa_7_1)) + )) + (net (rename RST_DLY_4 "RST_DLY[4]") (joined + (portRef Q (instanceRef RST_DLY_4)) + (portRef I1 (instanceRef G_143)) + (portRef I1 (instanceRef G_144)) + (portRef I0 (instanceRef RESET_OUT_0_sqmuxa_7_2)) + )) + (net (rename RST_DLY_5 "RST_DLY[5]") (joined + (portRef Q (instanceRef RST_DLY_5)) + (portRef I1 (instanceRef G_145)) + (portRef I1 (instanceRef G_146)) + (portRef I1 (instanceRef RESET_OUT_0_sqmuxa_7_2)) + )) + (net (rename RST_DLY_6 "RST_DLY[6]") (joined + (portRef Q (instanceRef RST_DLY_6)) + (portRef I1 (instanceRef G_147)) + (portRef I1 (instanceRef RESET_OUT_0_sqmuxa_7)) + )) + (net (rename RST_DLY_7 "RST_DLY[7]") (joined + (portRef Q (instanceRef RST_DLY_7)) + (portRef I1 (instanceRef G_149)) + (portRef I1 (instanceRef RESET_OUT_0_sqmuxa)) + )) + (net (rename pos_clk_un8_bg_030 "pos_clk.un8_bg_030") (joined + (portRef O (instanceRef pos_clk_un8_bg_030_i)) + (portRef I1 (instanceRef BG_000_0_m)) + (portRef I0 (instanceRef BG_000_0_r)) + )) + (net (rename CLK_000_P_SYNC_0 "CLK_000_P_SYNC[0]") (joined + (portRef Q (instanceRef CLK_000_P_SYNC_0)) + (portRef D (instanceRef CLK_000_P_SYNC_1)) + )) + (net (rename CLK_000_P_SYNC_1 "CLK_000_P_SYNC[1]") (joined + (portRef Q (instanceRef CLK_000_P_SYNC_1)) + (portRef D (instanceRef CLK_000_P_SYNC_2)) + )) + (net (rename CLK_000_P_SYNC_2 "CLK_000_P_SYNC[2]") (joined + (portRef Q (instanceRef CLK_000_P_SYNC_2)) + (portRef D (instanceRef CLK_000_P_SYNC_3)) + )) + (net (rename CLK_000_P_SYNC_3 "CLK_000_P_SYNC[3]") (joined + (portRef Q (instanceRef CLK_000_P_SYNC_3)) + (portRef D (instanceRef CLK_000_P_SYNC_4)) + )) + (net (rename CLK_000_P_SYNC_4 "CLK_000_P_SYNC[4]") (joined + (portRef Q (instanceRef CLK_000_P_SYNC_4)) + (portRef D (instanceRef CLK_000_P_SYNC_5)) + )) + (net (rename CLK_000_P_SYNC_5 "CLK_000_P_SYNC[5]") (joined + (portRef Q (instanceRef CLK_000_P_SYNC_5)) + (portRef D (instanceRef CLK_000_P_SYNC_6)) + )) + (net (rename CLK_000_P_SYNC_6 "CLK_000_P_SYNC[6]") (joined + (portRef Q (instanceRef CLK_000_P_SYNC_6)) + (portRef D (instanceRef CLK_000_P_SYNC_7)) + )) + (net (rename CLK_000_P_SYNC_7 "CLK_000_P_SYNC[7]") (joined + (portRef Q (instanceRef CLK_000_P_SYNC_7)) + (portRef D (instanceRef CLK_000_P_SYNC_8)) + )) + (net (rename CLK_000_P_SYNC_8 "CLK_000_P_SYNC[8]") (joined + (portRef Q (instanceRef CLK_000_P_SYNC_8)) + (portRef D (instanceRef CLK_000_P_SYNC_9)) + )) + (net (rename CLK_000_N_SYNC_0 "CLK_000_N_SYNC[0]") (joined + (portRef Q (instanceRef CLK_000_N_SYNC_0)) + (portRef D (instanceRef CLK_000_N_SYNC_1)) + )) + (net (rename CLK_000_N_SYNC_1 "CLK_000_N_SYNC[1]") (joined + (portRef Q (instanceRef CLK_000_N_SYNC_1)) + (portRef D (instanceRef CLK_000_N_SYNC_2)) + )) + (net (rename CLK_000_N_SYNC_2 "CLK_000_N_SYNC[2]") (joined + (portRef Q (instanceRef CLK_000_N_SYNC_2)) + (portRef D (instanceRef CLK_000_N_SYNC_3)) + )) + (net (rename CLK_000_N_SYNC_3 "CLK_000_N_SYNC[3]") (joined + (portRef Q (instanceRef CLK_000_N_SYNC_3)) + (portRef D (instanceRef CLK_000_N_SYNC_4)) + )) + (net (rename CLK_000_N_SYNC_4 "CLK_000_N_SYNC[4]") (joined + (portRef Q (instanceRef CLK_000_N_SYNC_4)) + (portRef D (instanceRef CLK_000_N_SYNC_5)) + )) + (net (rename CLK_000_N_SYNC_5 "CLK_000_N_SYNC[5]") (joined + (portRef Q (instanceRef CLK_000_N_SYNC_5)) + (portRef D (instanceRef CLK_000_N_SYNC_6)) + )) + (net (rename CLK_000_N_SYNC_6 "CLK_000_N_SYNC[6]") (joined + (portRef Q (instanceRef CLK_000_N_SYNC_6)) + (portRef D (instanceRef CLK_000_N_SYNC_7)) + )) + (net (rename CLK_000_N_SYNC_7 "CLK_000_N_SYNC[7]") (joined + (portRef Q (instanceRef CLK_000_N_SYNC_7)) + (portRef D (instanceRef CLK_000_N_SYNC_8)) + )) + (net (rename CLK_000_N_SYNC_8 "CLK_000_N_SYNC[8]") (joined + (portRef Q (instanceRef CLK_000_N_SYNC_8)) + (portRef D (instanceRef CLK_000_N_SYNC_9)) + )) + (net (rename CLK_000_N_SYNC_9 "CLK_000_N_SYNC[9]") (joined + (portRef Q (instanceRef CLK_000_N_SYNC_9)) + (portRef I0 (instanceRef pos_clk_un9_clk_000_n_sync)) + (portRef D (instanceRef CLK_000_N_SYNC_10)) + )) + (net (rename CLK_000_N_SYNC_10 "CLK_000_N_SYNC[10]") (joined + (portRef Q (instanceRef CLK_000_N_SYNC_10)) + (portRef I0 (instanceRef CLK_000_N_SYNC_i_10)) + (portRef D (instanceRef CLK_000_N_SYNC_11)) + )) + (net (rename pos_clk_un5_bgack_030_int_d "pos_clk.un5_bgack_030_int_d") (joined + (portRef O (instanceRef SIZE_DMA_3_sqmuxa_i_o2_i)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_m)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_r)) + (portRef I1 (instanceRef RW_000_DMA_0_m)) + (portRef I0 (instanceRef RW_000_DMA_0_r)) + (portRef I1 (instanceRef A0_DMA_0_m)) + (portRef I0 (instanceRef A0_DMA_0_r)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_m)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_r)) + )) + (net RW_000_INT (joined + (portRef Q (instanceRef RW_000_INT)) + (portRef I0 (instanceRef RW_000_INT_0_n)) + (portRef I0 (instanceRef RW_000)) + )) + (net RW_000_DMA (joined + (portRef Q (instanceRef RW_000_DMA)) + (portRef I0 (instanceRef RW_000_DMA_0_n)) + (portRef I0 (instanceRef RW)) + )) + (net A0_DMA (joined + (portRef Q (instanceRef A0_DMA)) + (portRef I0 (instanceRef A0_DMA_0_n)) + (portRef I0 (instanceRef A0)) + )) + (net CLK_030_H (joined + (portRef Q (instanceRef CLK_030_H)) + (portRef I0 (instanceRef CLK_030_H_i)) + (portRef I0 (instanceRef DS_000_DMA_2_sqmuxa_i_a2)) + )) + (net (rename SM_AMIGA_1 "SM_AMIGA[1]") (joined + (portRef Q (instanceRef SM_AMIGA_1)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_o4_1)) + (portRef I0 (instanceRef DSACK1_INT_0_sqmuxa_i_i_a2)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_o4_0)) + (portRef I0 (instanceRef SM_AMIGA_i_1)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_m2_1__m)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_m2_1__r)) + )) + (net (rename SM_AMIGA_4 "SM_AMIGA[4]") (joined + (portRef Q (instanceRef SM_AMIGA_4)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_o2_4)) + (portRef I0 (instanceRef SM_AMIGA_i_4)) + )) + (net (rename SM_AMIGA_2 "SM_AMIGA[2]") (joined + (portRef Q (instanceRef SM_AMIGA_2)) + (portRef I0 (instanceRef SM_AMIGA_i_2)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_a2_2)) + )) + (net (rename pos_clk_un3_as_030_d0 "pos_clk.un3_as_030_d0") (joined + (portRef O (instanceRef pos_clk_un3_as_030_d0_i_i_o2_i)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_n)) + )) + (net DS_000_ENABLE (joined + (portRef Q (instanceRef DS_000_ENABLE)) + (portRef I0 (instanceRef DS_000_ENABLE_0_m)) + (portRef I0 (instanceRef un6_lds_000_1)) + )) + (net AS_000_INT_1_sqmuxa (joined + (portRef O (instanceRef AS_000_INT_1_sqmuxa_0_a2)) + (portRef I1 (instanceRef AS_000_INT_0_m)) + (portRef I0 (instanceRef AS_000_INT_0_r)) + )) + (net DS_000_ENABLE_1_sqmuxa_1 (joined + (portRef O (instanceRef DS_000_ENABLE_1_sqmuxa_1)) + (portRef I1 (instanceRef DS_000_ENABLE_0_m)) + (portRef I0 (instanceRef DS_000_ENABLE_0_r)) + )) + (net (rename pos_clk_A0_DMA_3 "pos_clk.A0_DMA_3") (joined + (portRef O (instanceRef pos_clk_A0_DMA_3_0_a2)) + (portRef I0 (instanceRef A0_DMA_0_m)) + )) + (net (rename pos_clk_DS_000_DMA_4 "pos_clk.DS_000_DMA_4") (joined + (portRef O (instanceRef pos_clk_DS_000_DMA_4_f0_0_i)) + (portRef I0 (instanceRef DS_000_DMA_0_m)) + )) + (net N_3 (joined + (portRef O (instanceRef DS_000_DMA_0_p)) + (portRef I0 (instanceRef N_3_i)) + )) + (net N_4 (joined + (portRef O (instanceRef SIZE_DMA_0_0__p)) + (portRef D (instanceRef SIZE_DMA_0)) + )) + (net N_5 (joined + (portRef O (instanceRef SIZE_DMA_0_1__p)) + (portRef D (instanceRef SIZE_DMA_1)) + )) + (net N_6 (joined + (portRef O (instanceRef AS_000_DMA_0_p)) + (portRef I0 (instanceRef N_6_i)) + )) + (net N_8 (joined + (portRef O (instanceRef A0_DMA_0_p)) + (portRef I0 (instanceRef N_8_i)) + )) + (net N_9 (joined + (portRef O (instanceRef DSACK1_INT_0_p)) + (portRef I0 (instanceRef N_9_i)) + )) + (net N_10 (joined + (portRef O (instanceRef AS_000_INT_0_p)) + (portRef I0 (instanceRef N_10_i)) + )) + (net N_11 (joined + (portRef O (instanceRef DS_000_ENABLE_0_p)) + (portRef I0 (instanceRef DS_000_ENABLE_1)) + )) + (net N_12 (joined + (portRef O (instanceRef AS_030_000_SYNC_0_p)) + (portRef I0 (instanceRef N_12_i)) + )) + (net N_13 (joined + (portRef O (instanceRef LDS_000_INT_0_p)) + (portRef I0 (instanceRef N_13_i)) + )) + (net N_15 (joined + (portRef O (instanceRef RW_000_DMA_0_p)) + (portRef I0 (instanceRef N_15_i)) + )) + (net N_16 (joined + (portRef O (instanceRef UDS_000_INT_0_p)) + (portRef I0 (instanceRef N_16_i)) + )) + (net N_19 (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_p)) + (portRef I0 (instanceRef N_19_i)) + )) + (net N_20 (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_p)) + (portRef I0 (instanceRef N_20_i)) + )) + (net N_21 (joined + (portRef O (instanceRef BG_000_0_p)) + (portRef I0 (instanceRef N_21_i)) + )) + (net N_23 (joined + (portRef O (instanceRef IPL_030_0_0__p)) + (portRef I0 (instanceRef N_23_i)) + )) + (net N_24 (joined + (portRef O (instanceRef IPL_030_0_1__p)) + (portRef I0 (instanceRef N_24_i)) + )) + (net N_25 (joined + (portRef O (instanceRef IPL_030_0_2__p)) + (portRef I0 (instanceRef N_25_i)) + )) + (net N_27 (joined + (portRef O (instanceRef cpu_est_0_1__p)) + (portRef D (instanceRef cpu_est_1)) + )) + (net N_28 (joined + (portRef O (instanceRef cpu_est_0_2__p)) + (portRef D (instanceRef cpu_est_2)) + )) + (net N_29 (joined + (portRef O (instanceRef cpu_est_0_3__p)) + (portRef D (instanceRef cpu_est_3)) + )) + (net N_30 (joined + (portRef O (instanceRef IPL_030_1_i_0)) + (portRef D (instanceRef IPL_030DFF_0)) + )) + (net N_31 (joined + (portRef O (instanceRef IPL_030_1_i_1)) + (portRef D (instanceRef IPL_030DFF_1)) + )) + (net N_32 (joined + (portRef O (instanceRef IPL_030_1_i_2)) + (portRef D (instanceRef IPL_030DFF_2)) + )) + (net N_33 (joined + (portRef O (instanceRef BGACK_030_INT_1_i)) + (portRef D (instanceRef BGACK_030_INT)) + )) + (net N_34 (joined + (portRef O (instanceRef BG_000_1_i)) + (portRef D (instanceRef BG_000DFF)) + )) + (net N_35 (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1_i)) + (portRef D (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH)) + )) + (net N_36 (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1_i)) + (portRef D (instanceRef AMIGA_BUS_ENABLE_DMA_LOW)) + )) + (net N_37 (joined + (portRef O (instanceRef VMA_INT_1_i)) + (portRef D (instanceRef VMA_INT)) + )) + (net N_39 (joined + (portRef O (instanceRef UDS_000_INT_1_i)) + (portRef D (instanceRef UDS_000_INT)) + )) + (net N_40 (joined + (portRef O (instanceRef RW_000_DMA_2_i)) + (portRef D (instanceRef RW_000_DMA)) + )) + (net N_41 (joined + (portRef O (instanceRef RW_000_INT_2_i)) + (portRef D (instanceRef RW_000_INT)) + )) + (net N_42 (joined + (portRef O (instanceRef LDS_000_INT_1_i)) + (portRef D (instanceRef LDS_000_INT)) + )) + (net N_43 (joined + (portRef O (instanceRef AS_030_000_SYNC_1_i)) + (portRef D (instanceRef AS_030_000_SYNC)) + )) + (net N_44 (joined + (portRef O (instanceRef AS_000_INT_1_i)) + (portRef D (instanceRef AS_000_INT)) + )) + (net N_45 (joined + (portRef O (instanceRef DSACK1_INT_1_i)) + (portRef D (instanceRef DSACK1_INT)) + )) + (net N_46 (joined + (portRef O (instanceRef A0_DMA_1_i)) + (portRef D (instanceRef A0_DMA)) + )) + (net N_48 (joined + (portRef O (instanceRef AS_000_DMA_1_i)) + (portRef D (instanceRef AS_000_DMA)) + )) + (net N_49 (joined + (portRef O (instanceRef DS_000_DMA_1_i)) + (portRef D (instanceRef DS_000_DMA)) + )) + (net N_50 (joined + (portRef O (instanceRef DS_030_D0_0_i)) + (portRef D (instanceRef DS_030_D0)) + )) + (net N_52 (joined + (portRef O (instanceRef IPL_D0_0_i_0)) + (portRef D (instanceRef IPL_D0_0)) + )) + (net N_53 (joined + (portRef O (instanceRef IPL_D0_0_i_1)) + (portRef D (instanceRef IPL_D0_1)) + )) + (net N_54 (joined + (portRef O (instanceRef IPL_D0_0_i_2)) + (portRef D (instanceRef IPL_D0_2)) + )) + (net N_55 (joined + (portRef O (instanceRef nEXP_SPACE_D0_0_i)) + (portRef D (instanceRef nEXP_SPACE_D0)) + )) + (net N_56 (joined + (portRef O (instanceRef VPA_D_0_i)) + (portRef D (instanceRef VPA_D)) + )) + (net N_57 (joined + (portRef O (instanceRef DTACK_D0_0_i)) + (portRef D (instanceRef DTACK_D0)) + )) + (net N_60 (joined + (portRef O (instanceRef DS_000_ENABLE_1)) + (portRef D (instanceRef DS_000_ENABLE)) + )) + (net (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (joined + (portRef Q (instanceRef SM_AMIGA_i_7)) + (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__m)) + (portRef I0 (instanceRef SM_AMIGA_i_i_7)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a2_6)) + (portRef I1 (instanceRef un1_SM_AMIGA_5_i_0)) + )) + (net N_115 (joined + (portRef O (instanceRef un1_SM_AMIGA_5_i_0_i)) + (portRef I1 (instanceRef RW_000_INT_0_m)) + (portRef I0 (instanceRef RW_000_INT_0_r)) + )) + (net (rename pos_clk_SIZE_DMA_6_0 "pos_clk.SIZE_DMA_6[0]") (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_i_0)) + (portRef I0 (instanceRef SIZE_DMA_0_0__m)) + )) + (net (rename pos_clk_SIZE_DMA_6_1 "pos_clk.SIZE_DMA_6[1]") (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_i_1)) + (portRef I0 (instanceRef SIZE_DMA_0_1__m)) + )) + (net (rename pos_clk_cpu_est_11_3 "pos_clk.cpu_est_11[3]") (joined + (portRef O (instanceRef pos_clk_cpu_est_11_0_0_i_3)) + (portRef I0 (instanceRef cpu_est_0_3__m)) + )) + (net N_224 (joined + (portRef O (instanceRef G_165)) + (portRef I0 (instanceRef N_224_i)) + )) + (net N_225 (joined + (portRef O (instanceRef G_166)) + (portRef I0 (instanceRef N_225_i)) + )) + (net N_226 (joined + (portRef O (instanceRef G_167)) + (portRef I0 (instanceRef N_226_i)) + )) + (net un6_uds_000_1 (joined + (portRef O (instanceRef un6_lds_000_1)) + (portRef I1 (instanceRef un6_uds_000)) + (portRef I1 (instanceRef un6_lds_000)) + )) + (net (rename pos_clk_un24_bgack_030_int_i_0 "pos_clk.un24_bgack_030_int_i_0") (joined + (portRef O (instanceRef pos_clk_un24_bgack_030_int_i_0_o2_i)) + (portRef I0 (instanceRef AS_000_DMA_0_m)) + )) + (net N_245 (joined + (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i_i)) + (portRef I1 (instanceRef DSACK1_INT_0_m)) + (portRef I0 (instanceRef DSACK1_INT_0_r)) + )) + (net N_246 (joined + (portRef O (instanceRef pos_clk_un37_as_030_d0_i_i)) + (portRef I1 (instanceRef AS_030_000_SYNC_0_m)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_r)) + )) + (net N_247 (joined + (portRef O (instanceRef un8_ciin_i_0_i)) + (portRef OE (instanceRef CIIN)) + )) + (net N_248 (joined + (portRef O (instanceRef SIZE_DMA_3_sqmuxa_i_i)) + (portRef I1 (instanceRef SIZE_DMA_0_1__m)) + (portRef I0 (instanceRef SIZE_DMA_0_1__r)) + (portRef I1 (instanceRef SIZE_DMA_0_0__m)) + (portRef I0 (instanceRef SIZE_DMA_0_0__r)) + )) + (net N_89 (joined + (portRef O (instanceRef un1_as_030_i_a2)) + (portRef OE (instanceRef SIZE_0)) + (portRef OE (instanceRef SIZE_1)) + )) + (net N_92 (joined + (portRef O (instanceRef DSACK1_INT_0_sqmuxa_i_i_a2)) + (portRef I0 (instanceRef N_92_i)) + )) + (net N_102 (joined + (portRef O (instanceRef AS_030_D0_0_i_a2)) + (portRef I0 (instanceRef N_102_i)) + )) + (net N_103 (joined + (portRef O (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2)) + (portRef I0 (instanceRef N_103_i)) + )) + (net N_104 (joined + (portRef O (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2)) + (portRef I0 (instanceRef N_104_i)) + )) + (net N_112 (joined + (portRef O (instanceRef un3_as_030_i_a2)) + (portRef OE (instanceRef A0)) + (portRef OE (instanceRef AS_030)) + (portRef OE (instanceRef DS_030)) + )) + (net N_256 (joined + (portRef O (instanceRef un2_rw_i_a4)) + (portRef I0 (instanceRef un3_as_030_i_a2)) + (portRef OE (instanceRef RW)) + )) + (net N_258 (joined + (portRef O (instanceRef AS_000_DMA_1_sqmuxa_i_i)) + (portRef I1 (instanceRef AS_000_DMA_0_m)) + (portRef I0 (instanceRef AS_000_DMA_0_r)) + )) + (net N_259 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_i_i_2)) + (portRef D (instanceRef SM_AMIGA_2)) + )) + (net N_260 (joined + (portRef O (instanceRef DS_000_DMA_2_sqmuxa_i_i)) + (portRef I1 (instanceRef DS_000_DMA_0_m)) + (portRef I0 (instanceRef DS_000_DMA_0_r)) + )) + (net N_265 (joined + (portRef O (instanceRef un14_amiga_bus_data_dir_i_0_i)) + (portRef I0 (instanceRef RW_000_DMA_0_m)) + )) + (net N_282 (joined + (portRef O (instanceRef un1_SM_AMIGA_7_i_m2_p)) + (portRef I0 (instanceRef N_282_i)) + (portRef I0 (instanceRef DS_000_ENABLE_1_sqmuxa_1)) + )) + (net N_71 (joined + (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__p)) + (portRef I0 (instanceRef N_71_i)) + )) + (net N_66_i (joined + (portRef O (instanceRef cpu_est_0_0_x2_0)) + (portRef D (instanceRef cpu_est_0)) + )) + (net (rename pos_clk_un11_clk_000_n_sync "pos_clk.un11_clk_000_n_sync") (joined + (portRef O (instanceRef pos_clk_un11_clk_000_n_sync)) + (portRef I0 (instanceRef pos_clk_un11_clk_000_n_sync_i)) + )) + (net N_76 (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_o4_i_0)) + (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_a2_0)) + )) + (net N_68_i (joined + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_1_i_x2)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_1_i_1)) + )) + (net N_69_i (joined + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i_x2)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i_1)) + )) + (net N_50_i (joined + (portRef O (instanceRef pos_clk_un24_bgack_030_int_i_0_x2)) + (portRef I0 (instanceRef pos_clk_un24_bgack_030_int_i_0_o2_1)) + )) + (net (rename pos_clk_un22_bgack_030_int "pos_clk.un22_bgack_030_int") (joined + (portRef O (instanceRef pos_clk_un22_bgack_030_int_i_0)) + (portRef I1 (instanceRef pos_clk_un24_bgack_030_int_i_0_o2)) + )) + (net N_268 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_o3_0_i_o2_i_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_a4_0)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_o2_2)) + )) + (net N_270 (joined + (portRef O (instanceRef pos_clk_cpu_est_11_i_0_o2_i_2)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_i_0_a2_1_2)) + )) + (net N_73 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_o4_0_i_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_a2_0_1_0)) + )) + (net N_75 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_o4_1_i_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_a2_1_0_0)) + )) + (net N_251 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_o4_i_0)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_a2_0_6)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_a2_1_2_0)) + )) + (net un22_berr_1 (joined + (portRef O (instanceRef un22_berr_0_a2_1)) + (portRef I0 (instanceRef un22_berr_0_a2_1_0)) + (portRef I1 (instanceRef un21_fpu_cs_0_a2)) + )) + (net N_95 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_a2_0_0)) + (portRef I0 (instanceRef N_95_i)) + )) + (net N_94 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_a2_0)) + (portRef I0 (instanceRef N_94_i)) + )) + (net N_288 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_a2_0_5)) + (portRef I0 (instanceRef N_288_i)) + )) + (net N_289 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_a2_1_5)) + (portRef I0 (instanceRef N_289_i)) + )) + (net N_286 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_a2_5)) + (portRef I0 (instanceRef N_286_i)) + )) + (net N_279 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_m2_3__p)) + (portRef I0 (instanceRef N_279_i)) + )) + (net N_277 (joined + (portRef O (instanceRef CLK_030_H_2_i_o2_i)) + (portRef I1 (instanceRef CLK_030_H_2_i_a2)) + )) + (net N_276 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_o2_i_5)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_a2_5)) + )) + (net N_62 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_o2_i_6)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_a2_6)) + )) + (net N_274 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_i_o2_i_2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_a2_1_0_2)) + )) + (net N_313 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_i_a2_1_2)) + (portRef I0 (instanceRef N_313_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_a2_0_1_2)) + )) + (net N_307 (joined + (portRef O (instanceRef CLK_030_H_2_i_a2)) + (portRef I0 (instanceRef N_307_i)) + )) + (net N_305 (joined + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0_a2)) + (portRef I0 (instanceRef N_305_i)) + )) + (net N_306 (joined + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0_a2_0)) + (portRef I0 (instanceRef N_306_i)) + )) + (net N_303 (joined + (portRef O (instanceRef pos_clk_cpu_est_11_i_0_a2_2)) + (portRef I0 (instanceRef N_303_i)) + )) + (net N_304 (joined + (portRef O (instanceRef pos_clk_cpu_est_11_i_0_a2_0_2)) + (portRef I0 (instanceRef N_304_i)) + )) + (net N_301 (joined + (portRef O (instanceRef pos_clk_DS_000_DMA_4_f0_0_a2)) + (portRef I0 (instanceRef N_301_i)) + )) + (net N_91 (joined + (portRef O (instanceRef DS_000_DMA_2_sqmuxa_i_a2)) + (portRef I0 (instanceRef N_91_i)) + )) + (net N_85 (joined + (portRef O (instanceRef pos_clk_cpu_est_11_0_0_a2_3)) + (portRef I0 (instanceRef N_85_i)) + )) + (net N_294 (joined + (portRef O (instanceRef pos_clk_cpu_est_11_0_0_a2_0_3)) + (portRef I0 (instanceRef N_294_i)) + )) + (net N_296 (joined + (portRef O (instanceRef pos_clk_cpu_est_11_0_0_a2_1_3)) + (portRef I0 (instanceRef N_296_i)) + )) + (net N_84 (joined + (portRef O (instanceRef un1_SM_AMIGA_5_i_0_a2)) + (portRef I0 (instanceRef N_84_i)) + )) + (net N_82 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_i_a2_2)) + (portRef I0 (instanceRef N_82_i)) + )) + (net N_83 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_i_a2_0_2)) + (portRef I0 (instanceRef N_83_i)) + )) + (net N_293 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_a2_3)) + (portRef I0 (instanceRef N_293_i)) + )) + (net N_290 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_a2_4)) + (portRef I0 (instanceRef N_290_i)) + )) + (net N_291 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_a2_0_4)) + (portRef I0 (instanceRef N_291_i)) + )) + (net N_283 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_a2_6)) + (portRef I0 (instanceRef N_283_i)) + )) + (net N_284 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_a2_0_6)) + (portRef I0 (instanceRef N_284_i)) + )) + (net N_86 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_m2_1__p)) + (portRef I0 (instanceRef N_86_i)) + )) + (net N_80 (joined + (portRef O (instanceRef pos_clk_un37_as_030_d0_i_o4_i)) + (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_a2)) + )) + (net N_78 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_o4_i_1)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_a2_1)) + )) + (net N_108 (joined + (portRef O (instanceRef pos_clk_un37_as_030_d0_i_a2)) + (portRef I0 (instanceRef N_108_i)) + )) + (net N_109 (joined + (portRef O (instanceRef pos_clk_un37_as_030_d0_i_a2_0)) + (portRef I0 (instanceRef N_109_i)) + )) + (net N_100 (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_a2_0)) + (portRef I0 (instanceRef N_100_i)) + )) + (net N_99 (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_a2_1)) + (portRef I0 (instanceRef N_99_i)) + )) + (net N_93 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_a2_1)) + (portRef I0 (instanceRef N_93_i)) + )) + (net (rename pos_clk_un14_clk_000_n_sync "pos_clk.un14_clk_000_n_sync") (joined + (portRef O (instanceRef pos_clk_un14_clk_000_n_sync_i)) + (portRef I1 (instanceRef DSACK1_INT_0_sqmuxa_i_i_a2)) + )) + (net (rename pos_clk_un9_clk_000_n_sync "pos_clk.un9_clk_000_n_sync") (joined + (portRef O (instanceRef pos_clk_un9_clk_000_n_sync)) + (portRef I0 (instanceRef pos_clk_un9_clk_000_n_sync_i)) + )) + (net N_340 (joined + (portRef O (instanceRef pos_clk_un37_as_030_d0_i_a2_1)) + (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_a2_0)) + (portRef I1 (instanceRef un21_fpu_cs_0_a2_1)) + (portRef I1 (instanceRef un22_berr_0_a2)) + )) + (net N_97 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_a2_2_0)) + (portRef I0 (instanceRef N_97_i)) + )) + (net N_136 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_o3_0_o2_i_3)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_a2_3)) + )) + (net N_101 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_a2_0)) + (portRef I0 (instanceRef N_101_i)) + )) + (net N_81 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_o4_i_0)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_a2_0)) + )) + (net N_116 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_a4_0)) + (portRef I0 (instanceRef N_116_i)) + )) + (net N_96 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_a2_1_0)) + (portRef I0 (instanceRef N_96_i)) + )) + (net N_113 (joined + (portRef O (instanceRef pos_clk_un4_bgack_000_i_a2)) + (portRef I1 (instanceRef BGACK_030_INT_0_m)) + (portRef I0 (instanceRef BGACK_030_INT_0_r)) + )) + (net N_275 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_o2_i_4)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_a2_4)) + )) + (net N_273 (joined + (portRef O (instanceRef pos_clk_cpu_est_11_0_0_o2_i_3)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_0_0_a2_3)) + )) + (net N_88 (joined + (portRef O (instanceRef pos_clk_cpu_est_11_0_0_a2_1)) + (portRef I0 (instanceRef N_88_i)) + )) + (net N_272 (joined + (portRef O (instanceRef pos_clk_cpu_est_11_0_0_o2_i_1)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_0_0_a2_1)) + )) + (net N_299 (joined + (portRef O (instanceRef pos_clk_cpu_est_11_0_0_a2_0_1)) + (portRef I0 (instanceRef N_299_i)) + )) + (net N_90 (joined + (portRef O (instanceRef pos_clk_cpu_est_11_0_0_a2_1_1)) + (portRef I0 (instanceRef N_90_i)) + )) + (net N_311 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_i_a2_3_2)) + (portRef I0 (instanceRef N_311_i)) + )) + (net N_312 (joined + (portRef O (instanceRef pos_clk_cpu_est_11_0_0_a2_2_1)) + (portRef I0 (instanceRef N_312_i)) + (portRef I1 (instanceRef pos_clk_un7_clk_000_pe_0_a2_0_1)) + )) + (net N_267 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_i_o2_0_i_2)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_a2_1_2)) + )) + (net N_264 (joined + (portRef O (instanceRef DS_000_ENABLE_1_sqmuxa_i_0_i)) + (portRef I0 (instanceRef RW_000_INT_0_m)) + )) + (net (rename pos_clk_un7_clk_000_pe "pos_clk.un7_clk_000_pe") (joined + (portRef O (instanceRef pos_clk_un7_clk_000_pe_0_i)) + (portRef I1 (instanceRef VMA_INT_0_m)) + (portRef I0 (instanceRef VMA_INT_0_r)) + )) + (net N_308 (joined + (portRef O (instanceRef pos_clk_un7_clk_000_pe_0_a2)) + (portRef I0 (instanceRef N_308_i)) + )) + (net N_309 (joined + (portRef O (instanceRef pos_clk_un7_clk_000_pe_0_a2_0)) + (portRef I0 (instanceRef N_309_i)) + )) + (net N_310 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_i_a2_2_2)) + (portRef I0 (instanceRef N_310_i)) + )) + (net N_220 (joined + (portRef O (instanceRef G_160)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_1_i_x2)) + )) + (net (rename pos_clk_cpu_est_11_1 "pos_clk.cpu_est_11[1]") (joined + (portRef O (instanceRef pos_clk_cpu_est_11_0_0_i_1)) + (portRef I0 (instanceRef cpu_est_0_1__m)) + )) + (net N_14 (joined + (portRef O (instanceRef RW_000_INT_0_p)) + (portRef I0 (instanceRef N_14_i)) + )) + (net N_18 (joined + (portRef O (instanceRef VMA_INT_0_p)) + (portRef I0 (instanceRef N_18_i)) + )) + (net N_22 (joined + (portRef O (instanceRef BGACK_030_INT_0_p)) + (portRef I0 (instanceRef N_22_i)) + )) + (net RESET_OUT_0_sqmuxa_1 (joined + (portRef O (instanceRef G_136)) + (portRef I0 (instanceRef G_138)) + (portRef I0 (instanceRef G_137)) + (portRef I0 (instanceRef RESET_OUT_0_sqmuxa_5_1)) + )) + (net N_205 (joined + (portRef O (instanceRef G_138)) + (portRef I0 (instanceRef G_139)) + )) + (net N_213 (joined + (portRef O (instanceRef G_146)) + (portRef I0 (instanceRef G_147)) + )) + (net N_87_i (joined + (portRef O (instanceRef pos_clk_RST_DLY_5_iv_0_x2_0)) + (portRef I0 (instanceRef N_87_i_i)) + )) + (net N_105 (joined + (portRef O (instanceRef RESET_OUT_2_i_a2)) + (portRef I0 (instanceRef N_105_i)) + )) + (net N_98 (joined + (portRef O (instanceRef pos_clk_RST_DLY_5_iv_0_a2_0)) + (portRef I0 (instanceRef N_98_i)) + )) + (net RESET_OUT_0_sqmuxa (joined + (portRef O (instanceRef RESET_OUT_0_sqmuxa)) + (portRef I0 (instanceRef RESET_OUT_0_sqmuxa_i)) + )) + (net (rename un1_RST_DLY_i_m_2 "un1_RST_DLY_i_m[2]") (joined + (portRef O (instanceRef un1_RST_DLY_i_m_2)) + (portRef I0 (instanceRef un1_RST_DLY_i_m_i_2)) + )) + (net (rename un1_RST_DLY_2 "un1_RST_DLY[2]") (joined + (portRef O (instanceRef G_137)) + (portRef I0 (instanceRef un1_RST_DLY_i_2)) + )) + (net (rename un1_RST_DLY_i_m_8 "un1_RST_DLY_i_m[8]") (joined + (portRef O (instanceRef un1_RST_DLY_i_m_8)) + (portRef I0 (instanceRef un1_RST_DLY_i_m_i_8)) + )) + (net (rename un1_RST_DLY_8 "un1_RST_DLY[8]") (joined + (portRef O (instanceRef G_149)) + (portRef I0 (instanceRef un1_RST_DLY_i_8)) + )) + (net RESET_OUT_0_sqmuxa_5 (joined + (portRef O (instanceRef RESET_OUT_0_sqmuxa_5)) + (portRef I0 (instanceRef G_141)) + (portRef I0 (instanceRef G_142)) + (portRef I0 (instanceRef RESET_OUT_0_sqmuxa_7_1)) + )) + (net RESET_OUT_0_sqmuxa_7 (joined + (portRef O (instanceRef RESET_OUT_0_sqmuxa_7)) + (portRef I0 (instanceRef G_149)) + (portRef I0 (instanceRef RESET_OUT_0_sqmuxa)) + )) + (net (rename un1_RST_DLY_7 "un1_RST_DLY[7]") (joined + (portRef O (instanceRef G_147)) + (portRef I0 (instanceRef un1_RST_DLY_i_7)) + )) + (net (rename un1_RST_DLY_6 "un1_RST_DLY[6]") (joined + (portRef O (instanceRef G_145)) + (portRef I0 (instanceRef un1_RST_DLY_i_6)) + )) + (net N_211 (joined + (portRef O (instanceRef G_144)) + (portRef I0 (instanceRef G_145)) + (portRef I0 (instanceRef G_146)) + )) + (net (rename un1_RST_DLY_5 "un1_RST_DLY[5]") (joined + (portRef O (instanceRef G_143)) + (portRef I0 (instanceRef un1_RST_DLY_i_5)) + )) + (net N_209 (joined + (portRef O (instanceRef G_142)) + (portRef I0 (instanceRef G_143)) + (portRef I0 (instanceRef G_144)) + )) + (net (rename un1_RST_DLY_4 "un1_RST_DLY[4]") (joined + (portRef O (instanceRef G_141)) + (portRef I0 (instanceRef un1_RST_DLY_i_4)) + )) + (net (rename un1_RST_DLY_3 "un1_RST_DLY[3]") (joined + (portRef O (instanceRef G_139)) + (portRef I0 (instanceRef un1_RST_DLY_i_3)) + )) + (net (rename un1_RST_DLY_i_m_7 "un1_RST_DLY_i_m[7]") (joined + (portRef O (instanceRef un1_RST_DLY_i_m_7)) + (portRef I0 (instanceRef un1_RST_DLY_i_m_i_7)) + )) + (net (rename un1_RST_DLY_i_m_6 "un1_RST_DLY_i_m[6]") (joined + (portRef O (instanceRef un1_RST_DLY_i_m_6)) + (portRef I0 (instanceRef un1_RST_DLY_i_m_i_6)) + )) + (net (rename un1_RST_DLY_i_m_5 "un1_RST_DLY_i_m[5]") (joined + (portRef O (instanceRef un1_RST_DLY_i_m_5)) + (portRef I0 (instanceRef un1_RST_DLY_i_m_i_5)) + )) + (net (rename un1_RST_DLY_i_m_4 "un1_RST_DLY_i_m[4]") (joined + (portRef O (instanceRef un1_RST_DLY_i_m_4)) + (portRef I0 (instanceRef un1_RST_DLY_i_m_i_4)) + )) + (net (rename un1_RST_DLY_i_m_3 "un1_RST_DLY_i_m[3]") (joined + (portRef O (instanceRef un1_RST_DLY_i_m_3)) + (portRef I0 (instanceRef un1_RST_DLY_i_m_i_3)) + )) + (net N_71_i (joined + (portRef O (instanceRef N_71_i)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_HIGH)) + )) + (net un1_amiga_bus_enable_low_i (joined + (portRef O (instanceRef un1_amiga_bus_enable_low_i)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_LOW)) + )) + (net un21_fpu_cs_i (joined + (portRef O (instanceRef un21_fpu_cs_i)) + (portRef I0 (instanceRef FPU_CS)) + )) + (net RESET_OUT_i (joined + (portRef O (instanceRef RESET_OUT_i)) + (portRef I1 (instanceRef RESET_OUT_2_i_a2)) + )) + (net BGACK_030_INT_i (joined + (portRef O (instanceRef BGACK_030_INT_i)) + (portRef I1 (instanceRef un1_amiga_bus_enable_low)) + (portRef I0 (instanceRef un14_amiga_bus_data_dir_i_0)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_1_i_o2)) + (portRef I1 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2)) + (portRef I1 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2)) + (portRef I0 (instanceRef pos_clk_A0_DMA_3_0_a2)) + (portRef I0 (instanceRef un2_rw_i_a4)) + (portRef I0 (instanceRef un1_as_030_i_a2)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_a2_1)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_a2_0)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa_0_a2)) + )) + (net RESET_OUT_0_sqmuxa_i (joined + (portRef O (instanceRef RESET_OUT_0_sqmuxa_i)) + (portRef I0 (instanceRef un1_RST_DLY_i_m_8)) + (portRef I0 (instanceRef un1_RST_DLY_i_m_2)) + (portRef I1 (instanceRef pos_clk_RST_DLY_5_iv_0_a2_0)) + (portRef I0 (instanceRef RESET_OUT_2_i_a2)) + (portRef I0 (instanceRef un1_RST_DLY_i_m_4)) + (portRef I0 (instanceRef un1_RST_DLY_i_m_5)) + (portRef I0 (instanceRef un1_RST_DLY_i_m_6)) + (portRef I0 (instanceRef un1_RST_DLY_i_m_7)) + (portRef I0 (instanceRef un1_RST_DLY_i_m_3)) + )) + (net (rename un1_RST_DLY_i_3 "un1_RST_DLY_i[3]") (joined + (portRef O (instanceRef un1_RST_DLY_i_3)) + (portRef I1 (instanceRef un1_RST_DLY_i_m_3)) + )) + (net (rename un1_RST_DLY_i_4 "un1_RST_DLY_i[4]") (joined + (portRef O (instanceRef un1_RST_DLY_i_4)) + (portRef I1 (instanceRef un1_RST_DLY_i_m_4)) + )) + (net (rename un1_RST_DLY_i_5 "un1_RST_DLY_i[5]") (joined + (portRef O (instanceRef un1_RST_DLY_i_5)) + (portRef I1 (instanceRef un1_RST_DLY_i_m_5)) + )) + (net (rename un1_RST_DLY_i_6 "un1_RST_DLY_i[6]") (joined + (portRef O (instanceRef un1_RST_DLY_i_6)) + (portRef I1 (instanceRef un1_RST_DLY_i_m_6)) + )) + (net (rename un1_RST_DLY_i_7 "un1_RST_DLY_i[7]") (joined + (portRef O (instanceRef un1_RST_DLY_i_7)) + (portRef I1 (instanceRef un1_RST_DLY_i_m_7)) + )) + (net (rename un1_RST_DLY_i_8 "un1_RST_DLY_i[8]") (joined + (portRef O (instanceRef un1_RST_DLY_i_8)) + (portRef I1 (instanceRef un1_RST_DLY_i_m_8)) + )) + (net (rename un1_RST_DLY_i_2 "un1_RST_DLY_i[2]") (joined + (portRef O (instanceRef un1_RST_DLY_i_2)) + (portRef I1 (instanceRef un1_RST_DLY_i_m_2)) + )) + (net N_87_i_i (joined + (portRef O (instanceRef N_87_i_i)) + (portRef I0 (instanceRef pos_clk_RST_DLY_5_iv_0_a2_0)) + )) + (net (rename cpu_est_i_3 "cpu_est_i[3]") (joined + (portRef O (instanceRef cpu_est_i_3)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_0_0_a2_0_1)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_0_0_o2_1)) + (portRef I1 (instanceRef pos_clk_un7_clk_000_pe_0_a2_2)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_i_0_a2_2)) + )) + (net (rename cpu_est_i_0 "cpu_est_i[0]") (joined + (portRef O (instanceRef cpu_est_i_0)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_0_0_a2_1)) + (portRef I0 (instanceRef pos_clk_un7_clk_000_pe_0_a2_2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_a2_2_1_2)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_0_0_a2_1_1_3)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_i_0_a2_0_1_2)) + )) + (net VPA_D_i (joined + (portRef O (instanceRef VPA_D_i)) + (portRef I0 (instanceRef pos_clk_un7_clk_000_pe_0_a2_0_2)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_a2_2_2_2)) + )) + (net VMA_INT_i (joined + (portRef O (instanceRef VMA_INT_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_a2_2_2_2)) + )) + (net (rename cpu_est_i_1 "cpu_est_i[1]") (joined + (portRef O (instanceRef cpu_est_i_1)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_0_0_o2_1)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_a2_2_1_2)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_0_0_a2_1_1_3)) + )) + (net CLK_000_PE_i (joined + (portRef O (instanceRef CLK_000_PE_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_m2_1__n)) + (portRef I1 (instanceRef pos_clk_un4_bgack_000_i_a2)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_o3_0_i_o2_0)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_m2_3__n)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_a2_0)) + )) + (net BERR_i (joined + (portRef O (instanceRef I_234)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_a2_0_5)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_a2_2_0)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_m2_1__m)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_m2_3__m)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_a2_0_1_0)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_a2_1_0_0)) + )) + (net (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (joined + (portRef O (instanceRef SM_AMIGA_i_4)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a2_0_4)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a2_3)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_o4_1_0)) + )) + (net (rename cpu_est_i_2 "cpu_est_i[2]") (joined + (portRef O (instanceRef cpu_est_i_2)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_0_0_a2_0_1)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_0_0_a2_0_3)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_0_0_a2_1_3)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_i_0_a2_0_2)) + )) + (net (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (joined + (portRef O (instanceRef SM_AMIGA_i_5)) + (portRef I0 (instanceRef AS_000_INT_0_n)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a2_5)) + (portRef I0 (instanceRef AS_000_INT_1_sqmuxa_0_a2)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_o4_0_0)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a2_4)) + (portRef I1 (instanceRef un1_SM_AMIGA_5_i_0_1)) + )) + (net DTACK_D0_i (joined + (portRef O (instanceRef DTACK_D0_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_a2_3_2)) + )) + (net (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (joined + (portRef O (instanceRef SM_AMIGA_i_0)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a2_0)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_a2_1_2_0)) + )) + (net (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (joined + (portRef O (instanceRef SM_AMIGA_i_3)) + (portRef I0 (instanceRef un1_SM_AMIGA_7_i_m2_n)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_o2_2)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_a2_1_0)) + )) + (net CLK_000_NE_i (joined + (portRef O (instanceRef CLK_000_NE_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o4_1)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_a2_0_4)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_a2_0_0)) + )) + (net (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (joined + (portRef O (instanceRef SM_AMIGA_i_6)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a2_1_5)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a2_0_6)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_o4_1_1_0)) + )) + (net (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (joined + (portRef O (instanceRef SM_AMIGA_i_1)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_o4_0_0)) + )) + (net CLK_OUT_PRE_D_i (joined + (portRef O (instanceRef CLK_OUT_PRE_D_i)) + (portRef I1 (instanceRef pos_clk_un11_clk_000_n_sync)) + )) + (net (rename pos_clk_un11_clk_000_n_sync_i "pos_clk.un11_clk_000_n_sync_i") (joined + (portRef O (instanceRef pos_clk_un11_clk_000_n_sync_i)) + (portRef I1 (instanceRef pos_clk_un9_clk_000_n_sync)) + )) + (net LDS_000_i (joined + (portRef O (instanceRef I_235)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_o4_0)) + )) + (net UDS_000_i (joined + (portRef O (instanceRef I_236)) + (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_o4_0)) + )) + (net nEXP_SPACE_D0_i (joined + (portRef O (instanceRef nEXP_SPACE_D0_i)) + (portRef I0 (instanceRef un8_ciin_i_0)) + (portRef I1 (instanceRef un3_as_030_i_a2)) + (portRef I1 (instanceRef un1_as_030_i_a2)) + (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_0_a2_0)) + )) + (net (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (joined + (portRef O (instanceRef SM_AMIGA_i_2)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a2_1)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_o4_1_1_0)) + )) + (net AS_030_i (joined + (portRef O (instanceRef I_237)) + (portRef I1 (instanceRef un4_as_000)) + (portRef I0 (instanceRef un22_berr_0_a2_1)) + (portRef I0 (instanceRef AS_030_D0_0_i_a2)) + )) + (net A1_i (joined + (portRef O (instanceRef A1_i)) + (portRef I0 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2)) + )) + (net CLK_000_D1_i (joined + (portRef O (instanceRef CLK_000_D1_i)) + (portRef I1 (instanceRef pos_clk_CLK_000_P_SYNC_2_0_a2_0)) + )) + (net RW_000_i (joined + (portRef O (instanceRef I_238)) + (portRef I1 (instanceRef un14_amiga_bus_data_dir_i_0)) + (portRef I1 (instanceRef pos_clk_DS_000_DMA_4_f0_0_a2)) + (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_0_a2)) + (portRef I1 (instanceRef DS_000_DMA_2_sqmuxa_i_1)) + )) + (net CLK_030_H_i (joined + (portRef O (instanceRef CLK_030_H_i)) + (portRef I0 (instanceRef CLK_030_H_2_i_a2)) + )) + (net AS_000_DMA_i (joined + (portRef O (instanceRef AS_000_DMA_i)) + (portRef I0 (instanceRef CLK_030_H_2_i_o2)) + (portRef I0 (instanceRef un6_as_030_0_a2)) + )) + (net AS_000_i (joined + (portRef O (instanceRef I_239)) + (portRef I0 (instanceRef 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(portRef I1 (instanceRef un5_ciin_0_a2_3)) + )) + (net (rename SIZE_DMA_i_0 "SIZE_DMA_i[0]") (joined + (portRef O (instanceRef SIZE_DMA_i_0)) + (portRef I1 (instanceRef un3_size)) + )) + (net (rename SIZE_DMA_i_1 "SIZE_DMA_i[1]") (joined + (portRef O (instanceRef SIZE_DMA_i_1)) + (portRef I1 (instanceRef un4_size)) + )) + (net (rename A_i_16 "A_i[16]") (joined + (portRef O (instanceRef A_i_16)) + (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i_a2_1_2)) + )) + (net (rename A_i_18 "A_i[18]") (joined + (portRef O (instanceRef A_i_18)) + (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_a2_1_3)) + )) + (net (rename A_i_19 "A_i[19]") (joined + (portRef O (instanceRef A_i_19)) + (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i_a2_1_3)) + )) + (net (rename A_i_31 "A_i[31]") (joined + (portRef O (instanceRef A_i_31)) + (portRef I0 (instanceRef un5_ciin_0_a2_5)) + )) + (net (rename A_i_29 "A_i[29]") (joined + (portRef O (instanceRef A_i_29)) + (portRef I1 (instanceRef un5_ciin_0_a2_6)) + )) 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)) + (net (rename SIZE_1 "SIZE[1]") (joined + (portRef (member size 0)) + (portRef IO (instanceRef SIZE_1)) + )) + (net (rename A_c_2 "A_c[2]") (joined + (portRef O (instanceRef A_2)) + )) + (net (rename A_2 "A[2]") (joined + (portRef (member a 29)) + (portRef I0 (instanceRef A_2)) + )) + (net (rename A_c_3 "A_c[3]") (joined + (portRef O (instanceRef A_3)) + )) + (net (rename A_3 "A[3]") (joined + (portRef (member a 28)) + (portRef I0 (instanceRef A_3)) + )) + (net (rename A_c_4 "A_c[4]") (joined + (portRef O (instanceRef A_4)) + )) + (net (rename A_4 "A[4]") (joined + (portRef (member a 27)) + (portRef I0 (instanceRef A_4)) + )) + (net (rename A_c_5 "A_c[5]") (joined + (portRef O (instanceRef A_5)) + )) + (net (rename A_5 "A[5]") (joined + (portRef (member a 26)) + (portRef I0 (instanceRef A_5)) + )) + (net (rename A_c_6 "A_c[6]") (joined + (portRef O (instanceRef A_6)) + )) + (net (rename A_6 "A[6]") (joined + (portRef (member a 25)) + (portRef I0 (instanceRef A_6)) + )) + (net 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+ (portRef I0 (instanceRef A_i_31)) + )) + (net (rename A_31 "A[31]") (joined + (portRef (member a 0)) + (portRef I0 (instanceRef A_31)) + )) + (net A0_c (joined + (portRef O (instanceRef A0)) + (portRef I0 (instanceRef UDS_000_INT_0_m)) + (portRef I0 (instanceRef A0_c_i)) + )) + (net A0 (joined + (portRef A0) + (portRef IO (instanceRef A0)) + )) + (net A1_c (joined + (portRef O (instanceRef A1)) + (portRef I0 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2)) + (portRef I0 (instanceRef A1_i)) + )) + (net A1 (joined + (portRef A1) + (portRef I0 (instanceRef A1)) + )) + (net nEXP_SPACE_c (joined + (portRef O (instanceRef nEXP_SPACE)) + (portRef I0 (instanceRef nEXP_SPACE_c_i)) + )) + (net nEXP_SPACE (joined + (portRef nEXP_SPACE) + (portRef I0 (instanceRef nEXP_SPACE)) + )) + (net BERR_c (joined + (portRef O (instanceRef BERR)) + (portRef I1 (instanceRef pos_clk_un3_as_030_d0_i_i_o2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_o3_0_i_o2_0)) + (portRef I0 (instanceRef I_234)) + )) + (net BERR (joined + (portRef BERR) + (portRef IO (instanceRef BERR)) + )) + (net BG_030_c (joined + (portRef O (instanceRef BG_030)) + (portRef I0 (instanceRef BG_000_0_m)) + (portRef I0 (instanceRef BG_030_c_i)) + )) + (net BG_030 (joined + (portRef BG_030) + (portRef I0 (instanceRef BG_030)) + )) + (net BG_000_c (joined + (portRef Q (instanceRef BG_000DFF)) + (portRef I0 (instanceRef BG_000_0_n)) + (portRef I0 (instanceRef BG_000)) + )) + (net BG_000 (joined + (portRef O (instanceRef BG_000)) + (portRef BG_000) + )) + (net BGACK_030 (joined + (portRef O (instanceRef BGACK_030)) + (portRef BGACK_030) + )) + (net BGACK_000_c (joined + (portRef O (instanceRef BGACK_000)) + (portRef I1 (instanceRef un22_berr_0_a2_1)) + (portRef I0 (instanceRef pos_clk_un4_bgack_000_i_a2)) + (portRef I0 (instanceRef BGACK_030_INT_0_n)) + )) + (net BGACK_000 (joined + (portRef BGACK_000) + (portRef I0 (instanceRef BGACK_000)) + )) + (net CLK_030 (joined + (portRef CLK_030) + (portRef I0 (instanceRef CLK_030)) + )) + (net CLK_000_c (joined + (portRef O (instanceRef CLK_000)) + (portRef D (instanceRef CLK_000_D0)) + )) + (net CLK_000 (joined + (portRef CLK_000) + (portRef I0 (instanceRef CLK_000)) + )) + (net CLK_OSZI_c (joined + (portRef O (instanceRef CLK_OSZI)) + (portRef CLK (instanceRef A0_DMA)) + (portRef CLK (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH)) + (portRef CLK (instanceRef AMIGA_BUS_ENABLE_DMA_LOW)) + (portRef CLK (instanceRef AS_000_DMA)) + (portRef CLK (instanceRef AS_000_INT)) + (portRef CLK (instanceRef AS_030_000_SYNC)) + (portRef CLK (instanceRef AS_030_D0)) + (portRef CLK (instanceRef BGACK_030_INT)) + (portRef CLK (instanceRef BGACK_030_INT_D)) + (portRef CLK (instanceRef BG_000DFF)) + (portRef CLK (instanceRef CLK_000_D0)) + (portRef CLK (instanceRef CLK_000_D1)) + (portRef CLK (instanceRef CLK_000_NE)) + (portRef CLK (instanceRef CLK_000_NE_D0)) + (portRef CLK (instanceRef CLK_000_N_SYNC_0)) + (portRef CLK (instanceRef CLK_000_N_SYNC_1)) + (portRef CLK (instanceRef CLK_000_N_SYNC_2)) + (portRef CLK (instanceRef CLK_000_N_SYNC_3)) + (portRef CLK (instanceRef CLK_000_N_SYNC_4)) + (portRef CLK (instanceRef CLK_000_N_SYNC_5)) + (portRef CLK (instanceRef CLK_000_N_SYNC_6)) + (portRef CLK (instanceRef CLK_000_N_SYNC_7)) + (portRef CLK (instanceRef CLK_000_N_SYNC_8)) + (portRef CLK (instanceRef CLK_000_N_SYNC_9)) + (portRef CLK (instanceRef CLK_000_N_SYNC_10)) + (portRef CLK (instanceRef CLK_000_N_SYNC_11)) + (portRef CLK (instanceRef CLK_000_PE)) + (portRef CLK (instanceRef CLK_000_P_SYNC_0)) + (portRef CLK (instanceRef CLK_000_P_SYNC_1)) + (portRef CLK (instanceRef CLK_000_P_SYNC_2)) + (portRef CLK (instanceRef CLK_000_P_SYNC_3)) + (portRef CLK (instanceRef CLK_000_P_SYNC_4)) + (portRef CLK (instanceRef CLK_000_P_SYNC_5)) + (portRef CLK (instanceRef CLK_000_P_SYNC_6)) + (portRef CLK (instanceRef CLK_000_P_SYNC_7)) + (portRef CLK (instanceRef CLK_000_P_SYNC_8)) + (portRef CLK (instanceRef CLK_000_P_SYNC_9)) + (portRef CLK (instanceRef CLK_030_H)) + (portRef CLK (instanceRef CLK_OUT_PRE_50)) + (portRef CLK (instanceRef CLK_OUT_PRE_D)) + (portRef CLK (instanceRef CYCLE_DMA_0)) + (portRef CLK (instanceRef CYCLE_DMA_1)) + (portRef CLK (instanceRef DSACK1_INT)) + (portRef CLK (instanceRef DS_000_DMA)) + (portRef CLK (instanceRef DS_000_ENABLE)) + (portRef CLK (instanceRef DS_030_D0)) + (portRef CLK (instanceRef DTACK_D0)) + (portRef CLK (instanceRef IPL_030DFF_0)) + (portRef CLK (instanceRef IPL_030DFF_1)) + (portRef CLK (instanceRef IPL_030DFF_2)) + (portRef CLK (instanceRef IPL_D0_0)) + (portRef CLK (instanceRef IPL_D0_1)) + (portRef CLK (instanceRef IPL_D0_2)) + (portRef CLK (instanceRef LDS_000_INT)) + (portRef CLK (instanceRef RESET_OUT)) + (portRef CLK (instanceRef RST_DLY_0)) + (portRef CLK (instanceRef RST_DLY_1)) + (portRef CLK (instanceRef RST_DLY_2)) + (portRef CLK (instanceRef RST_DLY_3)) + (portRef CLK (instanceRef RST_DLY_4)) + (portRef CLK (instanceRef RST_DLY_5)) + (portRef CLK (instanceRef RST_DLY_6)) + (portRef CLK (instanceRef RST_DLY_7)) + (portRef CLK (instanceRef RW_000_DMA)) + (portRef CLK (instanceRef RW_000_INT)) + (portRef CLK (instanceRef SIZE_DMA_0)) + (portRef CLK (instanceRef SIZE_DMA_1)) + (portRef CLK (instanceRef SM_AMIGA_0)) + (portRef CLK (instanceRef SM_AMIGA_1)) + (portRef CLK (instanceRef SM_AMIGA_2)) + (portRef CLK (instanceRef SM_AMIGA_3)) + (portRef CLK (instanceRef SM_AMIGA_4)) + (portRef CLK (instanceRef SM_AMIGA_5)) + (portRef CLK (instanceRef SM_AMIGA_6)) + (portRef CLK (instanceRef SM_AMIGA_i_7)) + (portRef CLK (instanceRef UDS_000_INT)) + (portRef CLK (instanceRef VMA_INT)) + (portRef CLK (instanceRef VPA_D)) + (portRef CLK (instanceRef cpu_est_0)) + (portRef CLK (instanceRef cpu_est_1)) + (portRef CLK (instanceRef cpu_est_2)) + (portRef CLK (instanceRef cpu_est_3)) + (portRef CLK (instanceRef nEXP_SPACE_D0)) + )) + (net CLK_OSZI (joined + (portRef CLK_OSZI) + (portRef I0 (instanceRef CLK_OSZI)) + )) + (net CLK_DIV_OUT (joined + (portRef O (instanceRef CLK_DIV_OUT)) + (portRef CLK_DIV_OUT) + )) + (net CLK_EXP_c (joined + (portRef O (instanceRef CLK_030)) + (portRef I1 (instanceRef DS_000_DMA_2_sqmuxa_i_a2)) + (portRef I0 (instanceRef pos_clk_un11_clk_000_n_sync)) + (portRef I0 (instanceRef CLK_EXP_c_i)) + (portRef I0 (instanceRef CLK_EXP)) + )) + (net CLK_EXP (joined + (portRef O (instanceRef CLK_EXP)) + (portRef CLK_EXP) + )) + (net FPU_CS (joined + (portRef O (instanceRef FPU_CS)) + (portRef FPU_CS) + )) + (net FPU_SENSE_c (joined + (portRef O (instanceRef FPU_SENSE)) + (portRef I0 (instanceRef FPU_SENSE_i)) + (portRef I1 (instanceRef un22_berr_0_a2_1_0)) + )) + (net FPU_SENSE (joined + (portRef FPU_SENSE) + (portRef I0 (instanceRef FPU_SENSE)) + )) + (net (rename IPL_030_c_0 "IPL_030_c[0]") (joined + (portRef Q (instanceRef IPL_030DFF_0)) + (portRef I0 (instanceRef IPL_030_0_0__n)) + (portRef I0 (instanceRef IPL_030_0)) + )) + (net (rename IPL_030_0 "IPL_030[0]") (joined + (portRef O (instanceRef IPL_030_0)) + (portRef (member ipl_030 2)) + )) + (net (rename IPL_030_c_1 "IPL_030_c[1]") (joined + (portRef Q (instanceRef IPL_030DFF_1)) + (portRef I0 (instanceRef IPL_030_0_1__n)) + (portRef I0 (instanceRef IPL_030_1)) + )) + (net (rename IPL_030_1 "IPL_030[1]") (joined + (portRef O (instanceRef IPL_030_1)) + (portRef (member ipl_030 1)) + )) + (net (rename IPL_030_c_2 "IPL_030_c[2]") (joined + (portRef Q (instanceRef IPL_030DFF_2)) + (portRef I0 (instanceRef IPL_030_0_2__n)) + (portRef I0 (instanceRef IPL_030_2)) + )) + (net (rename IPL_030_2 "IPL_030[2]") (joined + (portRef O (instanceRef IPL_030_2)) + (portRef (member ipl_030 0)) + )) + (net (rename IPL_c_0 "IPL_c[0]") (joined + (portRef O (instanceRef IPL_0)) + (portRef I0 (instanceRef IPL_030_0_0__m)) + (portRef I1 (instanceRef G_165)) + (portRef I0 (instanceRef IPL_c_i_0)) + )) + (net (rename IPL_0 "IPL[0]") (joined + (portRef (member ipl 2)) + (portRef I0 (instanceRef IPL_0)) + )) + (net (rename IPL_c_1 "IPL_c[1]") (joined + (portRef O (instanceRef IPL_1)) + (portRef I0 (instanceRef IPL_030_0_1__m)) + (portRef I1 (instanceRef G_166)) + (portRef I0 (instanceRef IPL_c_i_1)) + )) + (net (rename IPL_1 "IPL[1]") (joined + (portRef (member ipl 1)) + (portRef I0 (instanceRef IPL_1)) + )) + (net (rename IPL_c_2 "IPL_c[2]") (joined + (portRef O (instanceRef IPL_2)) + (portRef I0 (instanceRef IPL_030_0_2__m)) + (portRef I1 (instanceRef G_167)) + (portRef I0 (instanceRef IPL_c_i_2)) + )) + (net (rename IPL_2 "IPL[2]") (joined + (portRef (member ipl 0)) + (portRef I0 (instanceRef IPL_2)) + )) + (net DSACK1 (joined + (portRef O (instanceRef DSACK1)) + (portRef DSACK1) + )) + (net DTACK_c (joined + (portRef O (instanceRef DTACK)) + (portRef I0 (instanceRef DTACK_c_i)) + )) + (net DTACK (joined + (portRef DTACK) + (portRef I0 (instanceRef DTACK)) + )) + (net AVEC (joined + (portRef O (instanceRef AVEC)) + (portRef AVEC) + )) + (net E (joined + (portRef O (instanceRef E)) + (portRef E) + )) + (net VPA_c (joined + (portRef O (instanceRef VPA)) + (portRef I0 (instanceRef VPA_c_i)) + )) + (net VPA (joined + (portRef VPA) + (portRef I0 (instanceRef VPA)) + )) + (net VMA (joined + (portRef O (instanceRef VMA)) + (portRef VMA) + )) + (net RST_c (joined + (portRef O (instanceRef RST)) + (portRef I1 (instanceRef DS_000_DMA_1)) + (portRef I1 (instanceRef AS_000_DMA_1)) + (portRef I1 (instanceRef A0_DMA_1)) + (portRef I1 (instanceRef DSACK1_INT_1)) + (portRef I1 (instanceRef AS_030_000_SYNC_1)) + (portRef I1 (instanceRef LDS_000_INT_1)) + (portRef I1 (instanceRef RW_000_DMA_2)) + (portRef I1 (instanceRef UDS_000_INT_1)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1)) + (portRef I1 (instanceRef BG_000_1)) + (portRef I1 (instanceRef DS_000_ENABLE_1)) + (portRef I1 (instanceRef IPL_030_1_2)) + (portRef I1 (instanceRef IPL_030_1_1)) + (portRef I1 (instanceRef IPL_030_1_0)) + (portRef I1 (instanceRef IPL_D0_0_2)) + (portRef I1 (instanceRef IPL_D0_0_1)) + (portRef I1 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(instanceRef pos_clk_RST_DLY_5_iv_4)) + (portRef I0 (instanceRef pos_clk_RST_DLY_5_iv_5)) + (portRef I0 (instanceRef pos_clk_RST_DLY_5_iv_6)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_1_5)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_a2_0_1_2)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_a2_1_0_2)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_1)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_3)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_4)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_6)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_1_i)) + (portRef I1 (instanceRef CLK_030_H_2_i_1)) + )) + (net RST (joined + (portRef RST) + (portRef I0 (instanceRef RST)) + )) + (net RESET (joined + (portRef O (instanceRef RESET)) + (portRef RESET) + )) + (net RW_c (joined + (portRef O (instanceRef RW)) + (portRef I0 (instanceRef I_240)) + )) + (net RW (joined + (portRef IO (instanceRef RW)) + (portRef RW) + )) + (net (rename FC_c_0 "FC_c[0]") (joined + (portRef O (instanceRef FC_0)) + (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_a2_1_1)) + )) + (net (rename FC_0 "FC[0]") (joined + (portRef (member fc 1)) + (portRef I0 (instanceRef FC_0)) + )) + (net (rename FC_c_1 "FC_c[1]") (joined + (portRef O (instanceRef FC_1)) + (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i_a2_1_1)) + )) + (net (rename FC_1 "FC[1]") (joined + (portRef (member fc 0)) + (portRef I0 (instanceRef FC_1)) + )) + (net AMIGA_ADDR_ENABLE (joined + (portRef O (instanceRef AMIGA_ADDR_ENABLE)) + (portRef AMIGA_ADDR_ENABLE) + )) + (net AMIGA_BUS_DATA_DIR_c (joined + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0_i)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR)) + )) + (net AMIGA_BUS_DATA_DIR (joined + (portRef O (instanceRef AMIGA_BUS_DATA_DIR)) + (portRef AMIGA_BUS_DATA_DIR) + )) + (net AMIGA_BUS_ENABLE_LOW (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_LOW)) + (portRef AMIGA_BUS_ENABLE_LOW) + )) + (net AMIGA_BUS_ENABLE_HIGH (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_HIGH)) + (portRef AMIGA_BUS_ENABLE_HIGH) + )) + (net CIIN (joined + (portRef O (instanceRef CIIN)) + (portRef CIIN) + )) + (net un1_as_000_i (joined + (portRef O (instanceRef un1_as_000_0)) + (portRef OE (instanceRef AS_000)) + (portRef OE (instanceRef LDS_000)) + (portRef OE (instanceRef RW_000)) + (portRef OE (instanceRef UDS_000)) + )) + (net (rename un1_RST_DLY_i_m_i_3 "un1_RST_DLY_i_m_i[3]") (joined + (portRef O (instanceRef un1_RST_DLY_i_m_i_3)) + (portRef I1 (instanceRef pos_clk_RST_DLY_5_iv_2)) + )) + (net (rename pos_clk_RST_DLY_5_iv_i_2 "pos_clk.RST_DLY_5_iv_i[2]") (joined + (portRef O (instanceRef pos_clk_RST_DLY_5_iv_2)) + (portRef D (instanceRef RST_DLY_2)) + )) + (net (rename un1_RST_DLY_i_m_i_4 "un1_RST_DLY_i_m_i[4]") (joined + (portRef O (instanceRef un1_RST_DLY_i_m_i_4)) + (portRef I1 (instanceRef pos_clk_RST_DLY_5_iv_3)) + )) + (net (rename pos_clk_RST_DLY_5_iv_i_3 "pos_clk.RST_DLY_5_iv_i[3]") (joined + (portRef O (instanceRef pos_clk_RST_DLY_5_iv_3)) + (portRef D (instanceRef RST_DLY_3)) + )) + (net (rename un1_RST_DLY_i_m_i_5 "un1_RST_DLY_i_m_i[5]") (joined + (portRef O (instanceRef un1_RST_DLY_i_m_i_5)) + (portRef I1 (instanceRef pos_clk_RST_DLY_5_iv_4)) + )) + (net (rename pos_clk_RST_DLY_5_iv_i_4 "pos_clk.RST_DLY_5_iv_i[4]") (joined + (portRef O (instanceRef pos_clk_RST_DLY_5_iv_4)) + (portRef D (instanceRef RST_DLY_4)) + )) + (net (rename un1_RST_DLY_i_m_i_6 "un1_RST_DLY_i_m_i[6]") (joined + (portRef O (instanceRef un1_RST_DLY_i_m_i_6)) + (portRef I1 (instanceRef pos_clk_RST_DLY_5_iv_5)) + )) + (net (rename pos_clk_RST_DLY_5_iv_i_5 "pos_clk.RST_DLY_5_iv_i[5]") (joined + (portRef O (instanceRef pos_clk_RST_DLY_5_iv_5)) + (portRef D (instanceRef RST_DLY_5)) + )) + (net (rename un1_RST_DLY_i_m_i_7 "un1_RST_DLY_i_m_i[7]") (joined + (portRef O (instanceRef un1_RST_DLY_i_m_i_7)) + (portRef I1 (instanceRef pos_clk_RST_DLY_5_iv_6)) + )) + (net (rename pos_clk_RST_DLY_5_iv_i_6 "pos_clk.RST_DLY_5_iv_i[6]") (joined + (portRef O (instanceRef pos_clk_RST_DLY_5_iv_6)) + (portRef D (instanceRef RST_DLY_6)) + )) + (net (rename un1_RST_DLY_i_m_i_8 "un1_RST_DLY_i_m_i[8]") (joined + (portRef O (instanceRef un1_RST_DLY_i_m_i_8)) + (portRef I1 (instanceRef pos_clk_RST_DLY_5_iv_7)) + )) + (net (rename pos_clk_RST_DLY_5_iv_i_7 "pos_clk.RST_DLY_5_iv_i[7]") (joined + (portRef O (instanceRef pos_clk_RST_DLY_5_iv_7)) + (portRef D (instanceRef RST_DLY_7)) + )) + (net (rename un1_RST_DLY_i_m_i_2 "un1_RST_DLY_i_m_i[2]") (joined + (portRef O (instanceRef un1_RST_DLY_i_m_i_2)) + (portRef I1 (instanceRef pos_clk_RST_DLY_5_iv_1)) + )) + (net (rename pos_clk_RST_DLY_5_iv_i_1 "pos_clk.RST_DLY_5_iv_i[1]") (joined + (portRef O (instanceRef pos_clk_RST_DLY_5_iv_1)) + (portRef D (instanceRef RST_DLY_1)) + )) + (net N_98_i (joined + (portRef O (instanceRef N_98_i)) + (portRef I0 (instanceRef pos_clk_RST_DLY_5_iv_0_0)) + )) + (net (rename pos_clk_RST_DLY_5_iv_i_0 "pos_clk.RST_DLY_5_iv_i[0]") (joined + (portRef O (instanceRef pos_clk_RST_DLY_5_iv_0_0)) + (portRef D (instanceRef RST_DLY_0)) + )) + (net N_105_i (joined + (portRef O (instanceRef N_105_i)) + (portRef I0 (instanceRef RESET_OUT_2_i)) + )) + (net N_244_i (joined + (portRef O (instanceRef RESET_OUT_2_i)) + (portRef D (instanceRef RESET_OUT)) + )) + (net N_22_i (joined + (portRef O (instanceRef N_22_i)) + (portRef I0 (instanceRef BGACK_030_INT_1)) + )) + (net N_33_0 (joined + (portRef O (instanceRef BGACK_030_INT_1)) + (portRef I0 (instanceRef BGACK_030_INT_1_i)) + )) + (net N_18_i (joined + (portRef O (instanceRef N_18_i)) + (portRef I0 (instanceRef VMA_INT_1)) + )) + (net N_37_0 (joined + (portRef O (instanceRef VMA_INT_1)) + (portRef I0 (instanceRef VMA_INT_1_i)) + )) + (net N_14_i (joined + (portRef O (instanceRef N_14_i)) + (portRef I0 (instanceRef RW_000_INT_2)) + )) + (net N_41_0 (joined + (portRef O (instanceRef RW_000_INT_2)) + (portRef I0 (instanceRef RW_000_INT_2_i)) + )) + (net N_10_i (joined + (portRef O (instanceRef N_10_i)) + (portRef I0 (instanceRef AS_000_INT_1)) + )) + (net N_44_0 (joined + (portRef O (instanceRef AS_000_INT_1)) + (portRef I0 (instanceRef AS_000_INT_1_i)) + )) + (net (rename pos_clk_cpu_est_11_0_1 "pos_clk.cpu_est_11_0[1]") (joined + (portRef O (instanceRef pos_clk_cpu_est_11_0_0_1)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_0_0_i_1)) + )) + (net N_312_i (joined + (portRef O (instanceRef N_312_i)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_0_0_2_1)) + )) + (net N_90_i (joined + (portRef O (instanceRef N_90_i)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_0_0_1_1)) + )) + (net N_88_i (joined + (portRef O (instanceRef N_88_i)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_0_0_1_1)) + )) + (net N_299_i (joined + (portRef O (instanceRef N_299_i)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_0_0_2_1)) + )) + (net N_275_0 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_o2_4)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_i_4)) + )) + (net N_274_0 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_i_o2_2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_o2_i_2)) + )) + (net N_273_i (joined + (portRef O (instanceRef pos_clk_cpu_est_11_0_0_o2_3)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_0_0_a2_0_3)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_0_0_o2_i_3)) + )) + (net N_272_i (joined + (portRef O (instanceRef pos_clk_cpu_est_11_0_0_o2_1)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_0_0_a2_2_1)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_0_0_o2_i_1)) + )) + (net N_270_i (joined + (portRef O (instanceRef pos_clk_cpu_est_11_i_0_o2_2)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_0_0_a2_1_1)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_i_0_o2_i_2)) + (portRef I1 (instanceRef pos_clk_un7_clk_000_pe_0_a2_1)) + )) + (net N_268_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_o3_0_i_o2_0)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_6)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_4)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_o3_0_i_o2_i_0)) + )) + (net N_310_i (joined + (portRef O (instanceRef N_310_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_o2_0_2)) + )) + (net N_311_i (joined + (portRef O (instanceRef N_311_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_o2_0_2)) + )) + (net N_267_0 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_i_o2_0_2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_o2_0_i_2)) + )) + (net N_309_i (joined + (portRef O (instanceRef N_309_i)) + (portRef I1 (instanceRef pos_clk_un7_clk_000_pe_0)) + )) + (net N_308_i (joined + (portRef O (instanceRef N_308_i)) + (portRef I0 (instanceRef pos_clk_un7_clk_000_pe_0)) + )) + (net (rename pos_clk_un7_clk_000_pe_0 "pos_clk.un7_clk_000_pe_0") (joined + (portRef O (instanceRef pos_clk_un7_clk_000_pe_0)) + (portRef I0 (instanceRef pos_clk_un7_clk_000_pe_0_i)) + )) + (net N_264_0 (joined + (portRef O (instanceRef DS_000_ENABLE_1_sqmuxa_i_0)) + (portRef I0 (instanceRef DS_000_ENABLE_1_sqmuxa_i_0_i)) + )) + (net N_304_i (joined + (portRef O (instanceRef N_304_i)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_i_0_2)) + )) + (net N_303_i (joined + (portRef O (instanceRef N_303_i)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_i_0_2)) + )) + (net N_186_i (joined + (portRef O (instanceRef pos_clk_cpu_est_11_i_0_2)) + (portRef I0 (instanceRef cpu_est_0_2__m)) + )) + (net VPA_c_i (joined + (portRef O (instanceRef VPA_c_i)) + (portRef I1 (instanceRef VPA_D_0)) + )) + (net N_56_0 (joined + (portRef O (instanceRef VPA_D_0)) + (portRef I0 (instanceRef VPA_D_0_i)) + )) + (net DTACK_c_i (joined + (portRef O (instanceRef DTACK_c_i)) + (portRef I0 (instanceRef DTACK_D0_0)) + )) + (net N_57_0 (joined + (portRef O (instanceRef DTACK_D0_0)) + (portRef I0 (instanceRef DTACK_D0_0_i)) + )) + (net N_97_i (joined + (portRef O (instanceRef N_97_i)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_1_0)) + )) + (net N_131_i (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0)) + (portRef D (instanceRef SM_AMIGA_i_7)) + )) + (net N_96_i (joined + (portRef O (instanceRef N_96_i)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0)) + )) + (net N_95_i (joined + (portRef O (instanceRef N_95_i)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_2_0)) + )) + (net N_94_i (joined + (portRef O (instanceRef N_94_i)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_2_0)) + )) + (net N_313_i (joined + (portRef O (instanceRef N_313_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_o3_0_o2_3)) + )) + (net N_136_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_o3_0_o2_3)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_a2_2_0)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_o3_0_o2_i_3)) + )) + (net N_81_0 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_o4_0)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o4_i_0)) + )) + (net N_116_i (joined + (portRef O (instanceRef N_116_i)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_o2_0)) + )) + (net N_77_i (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_o2_0)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_1_0)) + )) + (net N_73_i (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_o4_0_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_o4_0_i_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_a2_1_1_0)) + )) + (net N_101_i (joined + (portRef O (instanceRef N_101_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0)) + )) + (net N_117_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0)) + (portRef D (instanceRef SM_AMIGA_0)) + )) + (net (rename CLK_000_N_SYNC_i_10 "CLK_000_N_SYNC_i[10]") (joined + (portRef O (instanceRef CLK_000_N_SYNC_i_10)) + (portRef I0 (instanceRef pos_clk_un14_clk_000_n_sync)) + )) + (net (rename pos_clk_un9_clk_000_n_sync_i "pos_clk.un9_clk_000_n_sync_i") (joined + (portRef O (instanceRef pos_clk_un9_clk_000_n_sync_i)) + (portRef I1 (instanceRef pos_clk_un14_clk_000_n_sync)) + )) + (net (rename pos_clk_un14_clk_000_n_sync_0 "pos_clk.un14_clk_000_n_sync_0") (joined + (portRef O (instanceRef pos_clk_un14_clk_000_n_sync)) + (portRef I0 (instanceRef pos_clk_un14_clk_000_n_sync_i)) + )) + (net (rename pos_clk_un22_bgack_030_int_i "pos_clk.un22_bgack_030_int_i") (joined + (portRef O (instanceRef pos_clk_un22_bgack_030_int)) + (portRef I0 (instanceRef pos_clk_un22_bgack_030_int_i_0)) + )) + (net N_86_i (joined + (portRef O (instanceRef N_86_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_1_1)) + )) + (net N_93_i (joined + (portRef O (instanceRef N_93_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_1_1)) + )) + (net N_119_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_1)) + (portRef D (instanceRef SM_AMIGA_1)) + )) + (net N_99_i (joined + (portRef O (instanceRef N_99_i)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_1)) + )) + (net (rename pos_clk_SIZE_DMA_6_0_1 "pos_clk.SIZE_DMA_6_0[1]") (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_1)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_i_1)) + )) + (net N_100_i (joined + (portRef O (instanceRef N_100_i)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0)) + )) + (net (rename pos_clk_SIZE_DMA_6_0_0 "pos_clk.SIZE_DMA_6_0[0]") (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_i_0)) + )) + (net N_245_0 (joined + (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i)) + (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_i)) + )) + (net N_108_i (joined + (portRef O (instanceRef N_108_i)) + (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i)) + )) + (net N_109_i (joined + (portRef O (instanceRef N_109_i)) + (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i)) + )) + (net N_246_0 (joined + (portRef O (instanceRef pos_clk_un37_as_030_d0_i)) + (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_i)) + )) + (net un5_ciin_i (joined + (portRef O (instanceRef un5_ciin_i)) + (portRef I1 (instanceRef un8_ciin_i_0)) + )) + (net N_247_0 (joined + (portRef O (instanceRef un8_ciin_i_0)) + (portRef I0 (instanceRef un8_ciin_i_0_i)) + )) + (net N_248_0 (joined + (portRef O (instanceRef SIZE_DMA_3_sqmuxa_i)) + (portRef I0 (instanceRef SIZE_DMA_3_sqmuxa_i_i)) + )) + (net CLK_000_D0_i (joined + (portRef O (instanceRef CLK_000_D0_i)) + (portRef I0 (instanceRef pos_clk_CLK_000_N_SYNC_2_0_o4_0)) + )) + (net N_249_i (joined + (portRef O (instanceRef pos_clk_CLK_000_N_SYNC_2_0_o4_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_o4_1_0_0)) + (portRef D (instanceRef CLK_000_N_SYNC_0)) + )) + (net AS_030_000_SYNC_i (joined + (portRef O (instanceRef AS_030_000_SYNC_i)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_o4_1_0_0)) + )) + (net N_251_0 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_o4_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_o4_i_0)) + )) + (net (rename pos_clk_un3_as_030_d0_i "pos_clk.un3_as_030_d0_i") (joined + (portRef O (instanceRef pos_clk_un3_as_030_d0_i_i_o2)) + (portRef I1 (instanceRef AS_000_INT_1_sqmuxa_0_a2)) + (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i_a2)) + (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i_a2_0)) + (portRef I1 (instanceRef DSACK1_INT_1_sqmuxa_i)) + (portRef I1 (instanceRef DS_000_ENABLE_1_sqmuxa_1)) + (portRef I0 (instanceRef pos_clk_un3_as_030_d0_i_i_o2_i)) + )) + (net (rename pos_clk_un5_bgack_030_int_d_i "pos_clk.un5_bgack_030_int_d_i") (joined + (portRef O (instanceRef SIZE_DMA_3_sqmuxa_i_o2)) + (portRef I1 (instanceRef SIZE_DMA_3_sqmuxa_i)) + (portRef I0 (instanceRef SIZE_DMA_3_sqmuxa_i_o2_i)) + (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i_o4_1)) + )) + (net N_75_i (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_o4_1_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_o4_1_i_0)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_a2_1_1_0)) + )) + (net N_76_i (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_o4_0)) + (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_a2_1)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_o4_i_0)) + )) + (net N_78_0 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_o4_1)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o4_i_1)) + )) + (net N_80_0 (joined + (portRef O (instanceRef pos_clk_un37_as_030_d0_i_o4)) + (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_o4_i)) + )) + (net CLK_EXP_c_i (joined + (portRef O (instanceRef CLK_EXP_c_i)) + (portRef I1 (instanceRef CLK_030_H_2_i_o2)) + (portRef I0 (instanceRef AS_000_DMA_1_sqmuxa_i)) + )) + (net N_258_0 (joined + (portRef O (instanceRef AS_000_DMA_1_sqmuxa_i)) + (portRef I0 (instanceRef AS_000_DMA_1_sqmuxa_i_i)) + )) + (net N_283_i (joined + (portRef O (instanceRef N_283_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_1_6)) + )) + (net N_284_i (joined + (portRef O (instanceRef N_284_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_1_6)) + )) + (net N_129_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_6)) + (portRef D (instanceRef SM_AMIGA_6)) + )) + (net N_290_i (joined + (portRef O (instanceRef N_290_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_1_4)) + )) + (net N_291_i (joined + (portRef O (instanceRef N_291_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_1_4)) + )) + (net N_125_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_4)) + (portRef D (instanceRef SM_AMIGA_4)) + )) + (net N_279_i (joined + (portRef O (instanceRef N_279_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_1_3)) + )) + (net N_293_i (joined + (portRef O (instanceRef N_293_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_1_3)) + )) + (net N_123_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_3)) + (portRef D (instanceRef SM_AMIGA_3)) + )) + (net N_82_i (joined + (portRef O (instanceRef N_82_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_2)) + )) + (net N_83_i (joined + (portRef O (instanceRef N_83_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_2)) + )) + (net N_259_0 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_i_2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_i_2)) + )) + (net N_84_i (joined + (portRef O (instanceRef N_84_i)) + (portRef I0 (instanceRef un1_SM_AMIGA_5_i_0_1)) + )) + (net N_115_0 (joined + (portRef O (instanceRef un1_SM_AMIGA_5_i_0)) + (portRef I0 (instanceRef un1_SM_AMIGA_5_i_0_i)) + )) + (net N_85_i (joined + (portRef O (instanceRef N_85_i)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_0_0_1_3)) + )) + (net N_294_i (joined + (portRef O (instanceRef N_294_i)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_0_0_3)) + )) + (net N_296_i (joined + (portRef O (instanceRef N_296_i)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_0_0_1_3)) + )) + (net (rename pos_clk_cpu_est_11_0_3 "pos_clk.cpu_est_11_0[3]") (joined + (portRef O (instanceRef pos_clk_cpu_est_11_0_0_3)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_0_0_i_3)) + )) + (net N_91_i (joined + (portRef O (instanceRef N_91_i)) + (portRef I0 (instanceRef DS_000_DMA_2_sqmuxa_i_1)) + )) + (net N_260_0 (joined + (portRef O (instanceRef DS_000_DMA_2_sqmuxa_i)) + (portRef I0 (instanceRef DS_000_DMA_2_sqmuxa_i_i)) + )) + (net N_301_i (joined + (portRef O (instanceRef N_301_i)) + (portRef I0 (instanceRef pos_clk_DS_000_DMA_4_f0_0)) + )) + (net (rename pos_clk_DS_000_DMA_4_0 "pos_clk.DS_000_DMA_4_0") (joined + (portRef O (instanceRef pos_clk_DS_000_DMA_4_f0_0)) + (portRef I0 (instanceRef pos_clk_DS_000_DMA_4_f0_0_i)) + )) + (net N_305_i (joined + (portRef O (instanceRef N_305_i)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0)) + )) + (net N_306_i (joined + (portRef O (instanceRef N_306_i)) + (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_0)) + )) + (net AMIGA_BUS_DATA_DIR_c_0 (joined + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_i)) + )) + (net N_307_i (joined + (portRef O (instanceRef N_307_i)) + (portRef I0 (instanceRef CLK_030_H_2_i_1)) + )) + (net N_261_i (joined + (portRef O (instanceRef CLK_030_H_2_i)) + (portRef D (instanceRef CLK_030_H)) + )) + (net N_262_i (joined + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_1_i)) + (portRef D (instanceRef CYCLE_DMA_1)) + )) + (net N_263_i (joined + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i)) + (portRef D (instanceRef CYCLE_DMA_0)) + )) + (net N_265_0 (joined + (portRef O (instanceRef un14_amiga_bus_data_dir_i_0)) + (portRef I0 (instanceRef un14_amiga_bus_data_dir_i_0_i)) + )) + (net N_269_i (joined + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_1_i_o2)) + (portRef I1 (instanceRef pos_clk_un24_bgack_030_int_i_0_o2_1)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_a2_0_1)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i_1)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_1_i_1)) + )) + (net (rename pos_clk_un24_bgack_030_int_i_0_i "pos_clk.un24_bgack_030_int_i_0_i") (joined + (portRef O (instanceRef pos_clk_un24_bgack_030_int_i_0_o2)) + (portRef I1 (instanceRef AS_000_DMA_1_sqmuxa_i)) + (portRef I1 (instanceRef pos_clk_DS_000_DMA_4_f0_0)) + (portRef I0 (instanceRef pos_clk_un24_bgack_030_int_i_0_o2_i)) + (portRef I1 (instanceRef CLK_030_H_2_i)) + (portRef I1 (instanceRef DS_000_DMA_2_sqmuxa_i)) + )) + (net N_62_0 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_o2_6)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_i_6)) + )) + (net N_276_0 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_o2_5)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_i_5)) + )) + (net N_277_0 (joined + (portRef O (instanceRef CLK_030_H_2_i_o2)) + (portRef I0 (instanceRef CLK_030_H_2_i_o2_i)) + )) + (net N_286_i (joined + (portRef O (instanceRef N_286_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_1_5)) + )) + (net N_288_i (joined + (portRef O (instanceRef N_288_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_2_5)) + )) + (net N_289_i (joined + (portRef O (instanceRef N_289_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_2_5)) + )) + (net N_127_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_5)) + (portRef D (instanceRef SM_AMIGA_5)) + )) + (net (rename pos_clk_un11_ds_030_d0_i "pos_clk.un11_ds_030_d0_i") (joined + (portRef O (instanceRef pos_clk_un11_ds_030_d0)) + (portRef I0 (instanceRef LDS_000_INT_0_m)) + )) + (net A0_c_i (joined + (portRef O (instanceRef A0_c_i)) + (portRef I1 (instanceRef pos_clk_un11_ds_030_d0_1)) + )) + (net (rename SIZE_c_i_1 "SIZE_c_i[1]") (joined + (portRef O (instanceRef SIZE_c_i_1)) + (portRef I0 (instanceRef pos_clk_un11_ds_030_d0_1)) + )) + (net N_25_i (joined + (portRef O (instanceRef N_25_i)) + (portRef I0 (instanceRef IPL_030_1_2)) + )) + (net N_32_0 (joined + (portRef O (instanceRef IPL_030_1_2)) + (portRef I0 (instanceRef IPL_030_1_i_2)) + )) + (net N_24_i (joined + (portRef O (instanceRef N_24_i)) + (portRef I0 (instanceRef IPL_030_1_1)) + )) + (net N_31_0 (joined + (portRef O (instanceRef IPL_030_1_1)) + (portRef I0 (instanceRef IPL_030_1_i_1)) + )) + (net N_23_i (joined + (portRef O (instanceRef N_23_i)) + (portRef I0 (instanceRef IPL_030_1_0)) + )) + (net N_30_0 (joined + (portRef O (instanceRef IPL_030_1_0)) + (portRef I0 (instanceRef IPL_030_1_i_0)) + )) + (net (rename IPL_c_i_2 "IPL_c_i[2]") (joined + (portRef O (instanceRef IPL_c_i_2)) + (portRef I0 (instanceRef IPL_D0_0_2)) + )) + (net N_54_0 (joined + (portRef O (instanceRef IPL_D0_0_2)) + (portRef I0 (instanceRef IPL_D0_0_i_2)) + )) + (net (rename IPL_c_i_1 "IPL_c_i[1]") (joined + (portRef O (instanceRef IPL_c_i_1)) + (portRef I0 (instanceRef IPL_D0_0_1)) + )) + (net N_53_0 (joined + (portRef O (instanceRef IPL_D0_0_1)) + (portRef I0 (instanceRef IPL_D0_0_i_1)) + )) + (net (rename IPL_c_i_0 "IPL_c_i[0]") (joined + (portRef O (instanceRef IPL_c_i_0)) + (portRef I0 (instanceRef IPL_D0_0_0)) + )) + (net N_52_0 (joined + (portRef O (instanceRef IPL_D0_0_0)) + (portRef I0 (instanceRef IPL_D0_0_i_0)) + )) + (net nEXP_SPACE_c_i (joined + (portRef O (instanceRef nEXP_SPACE_c_i)) + (portRef I1 (instanceRef nEXP_SPACE_D0_0)) + )) + (net N_55_0 (joined + (portRef O (instanceRef nEXP_SPACE_D0_0)) + (portRef I0 (instanceRef nEXP_SPACE_D0_0_i)) + )) + (net N_50_0 (joined + (portRef O (instanceRef DS_030_D0_0)) + (portRef I0 (instanceRef DS_030_D0_0_i)) + )) + (net N_3_i (joined + (portRef O (instanceRef N_3_i)) + (portRef I0 (instanceRef DS_000_DMA_1)) + )) + (net N_49_0 (joined + (portRef O (instanceRef DS_000_DMA_1)) + (portRef I0 (instanceRef DS_000_DMA_1_i)) + )) + (net N_6_i (joined + (portRef O (instanceRef N_6_i)) + (portRef I0 (instanceRef AS_000_DMA_1)) + )) + (net N_48_0 (joined + (portRef O (instanceRef AS_000_DMA_1)) + (portRef I0 (instanceRef AS_000_DMA_1_i)) + )) + (net N_8_i (joined + (portRef O (instanceRef N_8_i)) + (portRef I0 (instanceRef A0_DMA_1)) + )) + (net N_46_0 (joined + (portRef O (instanceRef A0_DMA_1)) + (portRef I0 (instanceRef A0_DMA_1_i)) + )) + (net N_9_i (joined + (portRef O (instanceRef N_9_i)) + (portRef I0 (instanceRef DSACK1_INT_1)) + )) + (net N_45_0 (joined + (portRef O (instanceRef DSACK1_INT_1)) + (portRef I0 (instanceRef DSACK1_INT_1_i)) + )) + (net N_12_i (joined + (portRef O (instanceRef N_12_i)) + (portRef I0 (instanceRef AS_030_000_SYNC_1)) + )) + (net N_43_0 (joined + (portRef O (instanceRef AS_030_000_SYNC_1)) + (portRef I0 (instanceRef AS_030_000_SYNC_1_i)) + )) + (net N_13_i (joined + (portRef O (instanceRef N_13_i)) + (portRef I0 (instanceRef LDS_000_INT_1)) + )) + (net N_42_0 (joined + (portRef O (instanceRef LDS_000_INT_1)) + (portRef I0 (instanceRef LDS_000_INT_1_i)) + )) + (net N_15_i (joined + (portRef O (instanceRef N_15_i)) + (portRef I0 (instanceRef RW_000_DMA_2)) + )) + (net N_40_0 (joined + (portRef O (instanceRef RW_000_DMA_2)) + (portRef I0 (instanceRef RW_000_DMA_2_i)) + )) + (net N_16_i (joined + (portRef O (instanceRef N_16_i)) + (portRef I0 (instanceRef UDS_000_INT_1)) + )) + (net N_39_0 (joined + (portRef O (instanceRef UDS_000_INT_1)) + (portRef I0 (instanceRef UDS_000_INT_1_i)) + )) + (net N_19_i (joined + (portRef O (instanceRef N_19_i)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1)) + )) + (net N_36_0 (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1_i)) + )) + (net N_20_i (joined + (portRef O (instanceRef N_20_i)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1)) + )) + (net N_35_0 (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1_i)) + )) + (net N_21_i (joined + (portRef O (instanceRef N_21_i)) + (portRef I0 (instanceRef BG_000_1)) + )) + (net N_34_0 (joined + (portRef O (instanceRef BG_000_1)) + (portRef I0 (instanceRef BG_000_1_i)) + )) + (net BG_030_c_i (joined + (portRef O (instanceRef BG_030_c_i)) + (portRef I0 (instanceRef pos_clk_un8_bg_030)) + )) + (net (rename pos_clk_un6_bg_030_i "pos_clk.un6_bg_030_i") (joined + (portRef O (instanceRef pos_clk_un6_bg_030_i)) + (portRef I1 (instanceRef pos_clk_un8_bg_030)) + )) + (net (rename pos_clk_un8_bg_030_0 "pos_clk.un8_bg_030_0") (joined + (portRef O (instanceRef pos_clk_un8_bg_030)) + (portRef I0 (instanceRef pos_clk_un8_bg_030_i)) + )) + (net N_127_i_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_1_5)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_5)) + )) + (net N_127_i_2 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_2_5)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_5)) + )) + (net (rename pos_clk_un24_bgack_030_int_i_0_i_1 "pos_clk.un24_bgack_030_int_i_0_i_1") (joined + (portRef O (instanceRef pos_clk_un24_bgack_030_int_i_0_o2_1)) + (portRef I0 (instanceRef pos_clk_un24_bgack_030_int_i_0_o2)) + )) + (net N_80_0_1 (joined + (portRef O (instanceRef pos_clk_un37_as_030_d0_i_o4_1)) + (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_o4)) + )) + (net N_75_i_1 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_o4_1_1_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_o4_1_0)) + )) + (net N_251_0_1 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_o4_1_0_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_o4_0)) + )) + (net (rename pos_clk_un11_ds_030_d0_i_1 "pos_clk.un11_ds_030_d0_i_1") (joined + (portRef O (instanceRef pos_clk_un11_ds_030_d0_1)) + (portRef I0 (instanceRef pos_clk_un11_ds_030_d0)) + )) + (net N_340_1 (joined + (portRef O (instanceRef pos_clk_un37_as_030_d0_i_a2_1_1)) + (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_a2_1_4)) + )) + (net N_340_2 (joined + (portRef O (instanceRef pos_clk_un37_as_030_d0_i_a2_1_2)) + (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i_a2_1_4)) + )) + (net N_340_3 (joined + (portRef O (instanceRef pos_clk_un37_as_030_d0_i_a2_1_3)) + (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i_a2_1)) + )) + (net N_340_4 (joined + (portRef O (instanceRef pos_clk_un37_as_030_d0_i_a2_1_4)) + (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_a2_1)) + )) + (net un5_ciin_1 (joined + (portRef O (instanceRef un5_ciin_0_a2_1)) + (portRef I0 (instanceRef un5_ciin_0_a2_7)) + )) + (net un5_ciin_2 (joined + (portRef O (instanceRef un5_ciin_0_a2_2)) + (portRef I1 (instanceRef un5_ciin_0_a2_7)) + )) + (net un5_ciin_3 (joined + (portRef O (instanceRef un5_ciin_0_a2_3)) + (portRef I0 (instanceRef un5_ciin_0_a2_8)) + )) + (net un5_ciin_4 (joined + (portRef O (instanceRef un5_ciin_0_a2_4)) + (portRef I1 (instanceRef un5_ciin_0_a2_8)) + )) + (net un5_ciin_5 (joined + (portRef O (instanceRef un5_ciin_0_a2_5)) + (portRef I0 (instanceRef un5_ciin_0_a2_9)) + )) + (net un5_ciin_6 (joined + (portRef O (instanceRef un5_ciin_0_a2_6)) + (portRef I1 (instanceRef un5_ciin_0_a2_9)) + )) + (net un5_ciin_7 (joined + (portRef O (instanceRef un5_ciin_0_a2_7)) + (portRef I0 (instanceRef un5_ciin_0_a2_10)) + )) + (net un5_ciin_8 (joined + (portRef O (instanceRef un5_ciin_0_a2_8)) + (portRef I1 (instanceRef un5_ciin_0_a2_10)) + )) + (net un5_ciin_9 (joined + (portRef O (instanceRef un5_ciin_0_a2_9)) + (portRef I0 (instanceRef un5_ciin_0_a2_11)) + )) + (net un5_ciin_10 (joined + (portRef O (instanceRef un5_ciin_0_a2_10)) + (portRef I0 (instanceRef un5_ciin_0_a2)) + )) + (net un5_ciin_11 (joined + (portRef O (instanceRef un5_ciin_0_a2_11)) + (portRef I1 (instanceRef un5_ciin_0_a2)) + )) + (net un22_berr_1_0 (joined + (portRef O (instanceRef un22_berr_0_a2_1_0)) + (portRef I0 (instanceRef un22_berr_0_a2)) + )) + (net un21_fpu_cs_1 (joined + (portRef O (instanceRef un21_fpu_cs_0_a2_1)) + (portRef I0 (instanceRef un21_fpu_cs_0_a2)) + )) + (net (rename pos_clk_un6_bg_030_1 "pos_clk.un6_bg_030_1") (joined + (portRef O (instanceRef pos_clk_un6_bg_030_1)) + (portRef I0 (instanceRef pos_clk_un6_bg_030)) + )) + (net N_131_i_1 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_1_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_3_0)) + )) + (net N_131_i_2 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_2_0)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_3_0)) + )) + (net N_131_i_3 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_3_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0)) + )) + (net N_96_1 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_a2_1_1_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_a2_1_3_0)) + )) + (net N_96_2 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_a2_1_2_0)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_a2_1_3_0)) + )) + (net N_96_3 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_a2_1_3_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_a2_1_0)) + )) + (net (rename pos_clk_cpu_est_11_0_1_1 "pos_clk.cpu_est_11_0_1[1]") (joined + (portRef O (instanceRef pos_clk_cpu_est_11_0_0_1_1)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_0_0_1)) + )) + (net (rename pos_clk_cpu_est_11_0_2_1 "pos_clk.cpu_est_11_0_2[1]") (joined + (portRef O (instanceRef pos_clk_cpu_est_11_0_0_2_1)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_0_0_1)) + )) + (net N_310_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_i_a2_2_1_2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_a2_2_4_2)) + )) + (net N_310_2 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_i_a2_2_2_2)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_a2_2_4_2)) + )) + (net N_310_3 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_i_a2_2_3_2)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_a2_2_2)) + )) + (net N_310_4 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_i_a2_2_4_2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_a2_2_2)) + )) + (net N_309_1 (joined + (portRef O (instanceRef pos_clk_un7_clk_000_pe_0_a2_0_1)) + (portRef I0 (instanceRef pos_clk_un7_clk_000_pe_0_a2_0)) + )) + (net N_309_2 (joined + (portRef O (instanceRef pos_clk_un7_clk_000_pe_0_a2_0_2)) + (portRef I1 (instanceRef pos_clk_un7_clk_000_pe_0_a2_0)) + )) + (net N_308_1 (joined + (portRef O (instanceRef pos_clk_un7_clk_000_pe_0_a2_1)) + (portRef I0 (instanceRef pos_clk_un7_clk_000_pe_0_a2)) + )) + (net N_308_2 (joined + (portRef O (instanceRef pos_clk_un7_clk_000_pe_0_a2_2)) + (portRef I1 (instanceRef pos_clk_un7_clk_000_pe_0_a2)) + )) + (net RESET_OUT_0_sqmuxa_5_1 (joined + (portRef O (instanceRef RESET_OUT_0_sqmuxa_5_1)) + (portRef I0 (instanceRef RESET_OUT_0_sqmuxa_5)) + )) + (net RESET_OUT_0_sqmuxa_7_1 (joined + (portRef O (instanceRef RESET_OUT_0_sqmuxa_7_1)) + (portRef I0 (instanceRef RESET_OUT_0_sqmuxa_7_3)) + )) + (net RESET_OUT_0_sqmuxa_7_2 (joined + (portRef O (instanceRef RESET_OUT_0_sqmuxa_7_2)) + (portRef I1 (instanceRef RESET_OUT_0_sqmuxa_7_3)) + )) + (net RESET_OUT_0_sqmuxa_7_3 (joined + (portRef O (instanceRef RESET_OUT_0_sqmuxa_7_3)) + (portRef I0 (instanceRef RESET_OUT_0_sqmuxa_7)) + )) + (net N_94_1 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_a2_1_0_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_a2_0)) + )) + (net N_95_1 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_a2_0_1_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_a2_0_0)) + )) + (net N_119_i_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_1_1)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_1)) + )) + (net N_82_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_i_a2_1_0_2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_a2_2)) + )) + (net N_83_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_i_a2_0_1_2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_a2_0_2)) + )) + (net N_296_1 (joined + (portRef O (instanceRef pos_clk_cpu_est_11_0_0_a2_1_1_3)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_0_0_a2_1_3)) + )) + (net N_303_1 (joined + (portRef O (instanceRef pos_clk_cpu_est_11_i_0_a2_1_2)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_i_0_a2_2)) + )) + (net N_304_1 (joined + (portRef O (instanceRef pos_clk_cpu_est_11_i_0_a2_0_1_2)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_i_0_a2_0_2)) + )) + (net N_306_1 (joined + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0_a2_0_1)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_a2_0)) + )) + (net N_129_i_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_1_6)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_6)) + )) + (net N_125_i_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_1_4)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_4)) + )) + (net N_123_i_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_1_3)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_3)) + )) + (net N_115_0_1 (joined + (portRef O (instanceRef un1_SM_AMIGA_5_i_0_1)) + (portRef I0 (instanceRef un1_SM_AMIGA_5_i_0)) + )) + (net (rename pos_clk_cpu_est_11_0_1_3 "pos_clk.cpu_est_11_0_1[3]") (joined + (portRef O (instanceRef pos_clk_cpu_est_11_0_0_1_3)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_0_0_3)) + )) + (net N_260_0_1 (joined + (portRef O (instanceRef DS_000_DMA_2_sqmuxa_i_1)) + (portRef I0 (instanceRef DS_000_DMA_2_sqmuxa_i)) + )) + (net N_261_i_1 (joined + (portRef O (instanceRef CLK_030_H_2_i_1)) + (portRef I0 (instanceRef CLK_030_H_2_i)) + )) + (net N_262_i_1 (joined + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_1_i_1)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_1_i)) + )) + (net N_263_i_1 (joined + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i_1)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i)) + )) + (net (rename pos_clk_ipl_1 "pos_clk.ipl_1") (joined + (portRef O (instanceRef G_168_1)) + (portRef I0 (instanceRef G_168)) + )) + (net (rename cpu_est_0_3__un3 "cpu_est_0_3_.un3") (joined + (portRef O (instanceRef cpu_est_0_3__r)) + (portRef I1 (instanceRef cpu_est_0_3__n)) + )) + (net (rename cpu_est_0_3__un1 "cpu_est_0_3_.un1") (joined + (portRef O (instanceRef cpu_est_0_3__m)) + (portRef I0 (instanceRef cpu_est_0_3__p)) + )) + (net (rename cpu_est_0_3__un0 "cpu_est_0_3_.un0") (joined + (portRef O (instanceRef cpu_est_0_3__n)) + (portRef I1 (instanceRef cpu_est_0_3__p)) + )) + (net (rename cpu_est_0_2__un3 "cpu_est_0_2_.un3") (joined + (portRef O (instanceRef cpu_est_0_2__r)) + (portRef I1 (instanceRef cpu_est_0_2__n)) + )) + (net (rename cpu_est_0_2__un1 "cpu_est_0_2_.un1") (joined + (portRef O (instanceRef cpu_est_0_2__m)) + (portRef I0 (instanceRef cpu_est_0_2__p)) + )) + (net (rename cpu_est_0_2__un0 "cpu_est_0_2_.un0") (joined + (portRef O (instanceRef cpu_est_0_2__n)) + (portRef I1 (instanceRef cpu_est_0_2__p)) + )) + (net (rename cpu_est_0_1__un3 "cpu_est_0_1_.un3") (joined + (portRef O (instanceRef cpu_est_0_1__r)) + (portRef I1 (instanceRef cpu_est_0_1__n)) + )) + (net (rename cpu_est_0_1__un1 "cpu_est_0_1_.un1") (joined + (portRef O (instanceRef cpu_est_0_1__m)) + (portRef I0 (instanceRef cpu_est_0_1__p)) + )) + (net (rename cpu_est_0_1__un0 "cpu_est_0_1_.un0") (joined + (portRef O (instanceRef cpu_est_0_1__n)) + (portRef I1 (instanceRef cpu_est_0_1__p)) + )) + (net (rename BGACK_030_INT_0_un3 "BGACK_030_INT_0.un3") (joined + (portRef O (instanceRef BGACK_030_INT_0_r)) + (portRef I1 (instanceRef BGACK_030_INT_0_n)) + )) + (net (rename BGACK_030_INT_0_un1 "BGACK_030_INT_0.un1") (joined + (portRef O (instanceRef BGACK_030_INT_0_m)) + (portRef I0 (instanceRef BGACK_030_INT_0_p)) + )) + (net (rename BGACK_030_INT_0_un0 "BGACK_030_INT_0.un0") (joined + (portRef O (instanceRef BGACK_030_INT_0_n)) + (portRef I1 (instanceRef BGACK_030_INT_0_p)) + )) + (net (rename VMA_INT_0_un3 "VMA_INT_0.un3") (joined + (portRef O (instanceRef VMA_INT_0_r)) + (portRef I1 (instanceRef VMA_INT_0_n)) + )) + (net (rename VMA_INT_0_un1 "VMA_INT_0.un1") (joined + (portRef O (instanceRef VMA_INT_0_m)) + (portRef I0 (instanceRef VMA_INT_0_p)) + )) + (net (rename VMA_INT_0_un0 "VMA_INT_0.un0") (joined + (portRef O (instanceRef VMA_INT_0_n)) + (portRef I1 (instanceRef VMA_INT_0_p)) + )) + (net (rename RW_000_INT_0_un3 "RW_000_INT_0.un3") (joined + (portRef O (instanceRef RW_000_INT_0_r)) + (portRef I1 (instanceRef RW_000_INT_0_n)) + )) + (net (rename RW_000_INT_0_un1 "RW_000_INT_0.un1") (joined + (portRef O (instanceRef RW_000_INT_0_m)) + (portRef I0 (instanceRef RW_000_INT_0_p)) + )) + (net (rename RW_000_INT_0_un0 "RW_000_INT_0.un0") (joined + (portRef O (instanceRef RW_000_INT_0_n)) + (portRef I1 (instanceRef RW_000_INT_0_p)) + )) + (net (rename SM_AMIGA_srsts_i_0_m2_3__un3 "SM_AMIGA_srsts_i_0_m2_3_.un3") (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_m2_3__r)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_m2_3__n)) + )) + (net (rename SM_AMIGA_srsts_i_0_m2_3__un1 "SM_AMIGA_srsts_i_0_m2_3_.un1") (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_m2_3__m)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_m2_3__p)) + )) + (net (rename SM_AMIGA_srsts_i_0_m2_3__un0 "SM_AMIGA_srsts_i_0_m2_3_.un0") (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_m2_3__n)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_m2_3__p)) + )) + (net (rename SM_AMIGA_srsts_i_0_m2_1__un3 "SM_AMIGA_srsts_i_0_m2_1_.un3") (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_m2_1__r)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_m2_1__n)) + )) + (net (rename SM_AMIGA_srsts_i_0_m2_1__un1 "SM_AMIGA_srsts_i_0_m2_1_.un1") (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_m2_1__m)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_m2_1__p)) + )) + (net (rename SM_AMIGA_srsts_i_0_m2_1__un0 "SM_AMIGA_srsts_i_0_m2_1_.un0") (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_m2_1__n)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_m2_1__p)) + )) + (net (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__un3 "un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0_.un3") (joined + (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__r)) + (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__n)) + )) + (net (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__un1 "un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0_.un1") (joined + (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__m)) + (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__p)) + )) + (net (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__un0 "un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0_.un0") (joined + (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__n)) + (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__p)) + )) + (net (rename un1_SM_AMIGA_7_i_m2_un3 "un1_SM_AMIGA_7_i_m2.un3") (joined + (portRef O (instanceRef un1_SM_AMIGA_7_i_m2_r)) + (portRef I1 (instanceRef un1_SM_AMIGA_7_i_m2_n)) + )) + (net (rename un1_SM_AMIGA_7_i_m2_un1 "un1_SM_AMIGA_7_i_m2.un1") (joined + (portRef O (instanceRef un1_SM_AMIGA_7_i_m2_m)) + (portRef I0 (instanceRef un1_SM_AMIGA_7_i_m2_p)) + )) + (net (rename un1_SM_AMIGA_7_i_m2_un0 "un1_SM_AMIGA_7_i_m2.un0") (joined + (portRef O (instanceRef un1_SM_AMIGA_7_i_m2_n)) + (portRef I1 (instanceRef un1_SM_AMIGA_7_i_m2_p)) + )) + (net (rename SIZE_DMA_0_0__un3 "SIZE_DMA_0_0_.un3") (joined + (portRef O (instanceRef SIZE_DMA_0_0__r)) + (portRef I1 (instanceRef SIZE_DMA_0_0__n)) + )) + (net (rename SIZE_DMA_0_0__un1 "SIZE_DMA_0_0_.un1") (joined + (portRef O (instanceRef SIZE_DMA_0_0__m)) + (portRef I0 (instanceRef SIZE_DMA_0_0__p)) + )) + (net (rename SIZE_DMA_0_0__un0 "SIZE_DMA_0_0_.un0") (joined + (portRef O (instanceRef SIZE_DMA_0_0__n)) + (portRef I1 (instanceRef SIZE_DMA_0_0__p)) + )) + (net (rename SIZE_DMA_0_1__un3 "SIZE_DMA_0_1_.un3") (joined + (portRef O (instanceRef SIZE_DMA_0_1__r)) + (portRef I1 (instanceRef SIZE_DMA_0_1__n)) + )) + (net (rename SIZE_DMA_0_1__un1 "SIZE_DMA_0_1_.un1") (joined + (portRef O (instanceRef SIZE_DMA_0_1__m)) + (portRef I0 (instanceRef SIZE_DMA_0_1__p)) + )) + (net (rename SIZE_DMA_0_1__un0 "SIZE_DMA_0_1_.un0") (joined + (portRef O (instanceRef SIZE_DMA_0_1__n)) + (portRef I1 (instanceRef SIZE_DMA_0_1__p)) + )) + (net (rename IPL_030_0_0__un3 "IPL_030_0_0_.un3") (joined + (portRef O (instanceRef IPL_030_0_0__r)) + (portRef I1 (instanceRef IPL_030_0_0__n)) + )) + (net (rename IPL_030_0_0__un1 "IPL_030_0_0_.un1") (joined + (portRef O (instanceRef IPL_030_0_0__m)) + (portRef I0 (instanceRef IPL_030_0_0__p)) + )) + (net (rename IPL_030_0_0__un0 "IPL_030_0_0_.un0") (joined + (portRef O (instanceRef IPL_030_0_0__n)) + (portRef I1 (instanceRef IPL_030_0_0__p)) + )) + (net (rename IPL_030_0_1__un3 "IPL_030_0_1_.un3") (joined + (portRef O (instanceRef IPL_030_0_1__r)) + (portRef I1 (instanceRef IPL_030_0_1__n)) + )) + (net (rename IPL_030_0_1__un1 "IPL_030_0_1_.un1") (joined + (portRef O (instanceRef IPL_030_0_1__m)) + (portRef I0 (instanceRef IPL_030_0_1__p)) + )) + (net (rename IPL_030_0_1__un0 "IPL_030_0_1_.un0") (joined + (portRef O (instanceRef IPL_030_0_1__n)) + (portRef I1 (instanceRef IPL_030_0_1__p)) + )) + (net (rename IPL_030_0_2__un3 "IPL_030_0_2_.un3") (joined + (portRef O (instanceRef IPL_030_0_2__r)) + (portRef I1 (instanceRef IPL_030_0_2__n)) + )) + (net (rename IPL_030_0_2__un1 "IPL_030_0_2_.un1") (joined + (portRef O (instanceRef IPL_030_0_2__m)) + (portRef I0 (instanceRef IPL_030_0_2__p)) + )) + (net (rename IPL_030_0_2__un0 "IPL_030_0_2_.un0") (joined + (portRef O (instanceRef IPL_030_0_2__n)) + (portRef I1 (instanceRef IPL_030_0_2__p)) + )) + (net (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_un3 "AMIGA_BUS_ENABLE_DMA_HIGH_0.un3") (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_r)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_n)) + )) + (net (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_un1 "AMIGA_BUS_ENABLE_DMA_HIGH_0.un1") (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_m)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_p)) + )) + (net (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_un0 "AMIGA_BUS_ENABLE_DMA_HIGH_0.un0") (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_n)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_p)) + )) + (net (rename BG_000_0_un3 "BG_000_0.un3") (joined + (portRef O (instanceRef BG_000_0_r)) + (portRef I1 (instanceRef BG_000_0_n)) + )) + (net (rename BG_000_0_un1 "BG_000_0.un1") (joined + (portRef O (instanceRef BG_000_0_m)) + (portRef I0 (instanceRef BG_000_0_p)) + )) + (net (rename BG_000_0_un0 "BG_000_0.un0") (joined + (portRef O (instanceRef BG_000_0_n)) + (portRef I1 (instanceRef BG_000_0_p)) + )) + (net (rename DS_000_DMA_0_un3 "DS_000_DMA_0.un3") (joined + (portRef O (instanceRef DS_000_DMA_0_r)) + (portRef I1 (instanceRef DS_000_DMA_0_n)) + )) + (net (rename DS_000_DMA_0_un1 "DS_000_DMA_0.un1") (joined + (portRef O (instanceRef DS_000_DMA_0_m)) + (portRef I0 (instanceRef DS_000_DMA_0_p)) + )) + (net (rename DS_000_DMA_0_un0 "DS_000_DMA_0.un0") (joined + (portRef O (instanceRef DS_000_DMA_0_n)) + (portRef I1 (instanceRef DS_000_DMA_0_p)) + )) + (net (rename AS_000_DMA_0_un3 "AS_000_DMA_0.un3") (joined + (portRef O (instanceRef AS_000_DMA_0_r)) + (portRef I1 (instanceRef AS_000_DMA_0_n)) + )) + (net (rename AS_000_DMA_0_un1 "AS_000_DMA_0.un1") (joined + (portRef O (instanceRef AS_000_DMA_0_m)) + (portRef I0 (instanceRef AS_000_DMA_0_p)) + )) + (net (rename AS_000_DMA_0_un0 "AS_000_DMA_0.un0") (joined + (portRef O (instanceRef AS_000_DMA_0_n)) + (portRef I1 (instanceRef AS_000_DMA_0_p)) + )) + (net (rename A0_DMA_0_un3 "A0_DMA_0.un3") (joined + (portRef O (instanceRef A0_DMA_0_r)) + (portRef I1 (instanceRef A0_DMA_0_n)) + )) + (net (rename A0_DMA_0_un1 "A0_DMA_0.un1") (joined + (portRef O (instanceRef A0_DMA_0_m)) + (portRef I0 (instanceRef A0_DMA_0_p)) + )) + (net (rename A0_DMA_0_un0 "A0_DMA_0.un0") (joined + (portRef O (instanceRef A0_DMA_0_n)) + (portRef I1 (instanceRef A0_DMA_0_p)) + )) + (net (rename DSACK1_INT_0_un3 "DSACK1_INT_0.un3") (joined + (portRef O (instanceRef DSACK1_INT_0_r)) + (portRef I1 (instanceRef DSACK1_INT_0_n)) + )) + (net (rename DSACK1_INT_0_un1 "DSACK1_INT_0.un1") (joined + (portRef O (instanceRef DSACK1_INT_0_m)) + (portRef I0 (instanceRef DSACK1_INT_0_p)) + )) + (net (rename DSACK1_INT_0_un0 "DSACK1_INT_0.un0") (joined + (portRef O (instanceRef DSACK1_INT_0_n)) + (portRef I1 (instanceRef DSACK1_INT_0_p)) + )) + (net (rename AS_000_INT_0_un3 "AS_000_INT_0.un3") (joined + (portRef O (instanceRef AS_000_INT_0_r)) + (portRef I1 (instanceRef AS_000_INT_0_n)) + )) + (net (rename AS_000_INT_0_un1 "AS_000_INT_0.un1") (joined + (portRef O (instanceRef AS_000_INT_0_m)) + (portRef I0 (instanceRef AS_000_INT_0_p)) + )) + (net (rename AS_000_INT_0_un0 "AS_000_INT_0.un0") (joined + (portRef O (instanceRef AS_000_INT_0_n)) + (portRef I1 (instanceRef AS_000_INT_0_p)) + )) + (net (rename DS_000_ENABLE_0_un3 "DS_000_ENABLE_0.un3") (joined + (portRef O (instanceRef DS_000_ENABLE_0_r)) + (portRef I1 (instanceRef DS_000_ENABLE_0_n)) + )) + (net (rename DS_000_ENABLE_0_un1 "DS_000_ENABLE_0.un1") (joined + (portRef O (instanceRef DS_000_ENABLE_0_m)) + (portRef I0 (instanceRef DS_000_ENABLE_0_p)) + )) + (net (rename DS_000_ENABLE_0_un0 "DS_000_ENABLE_0.un0") (joined + (portRef O (instanceRef DS_000_ENABLE_0_n)) + (portRef I1 (instanceRef DS_000_ENABLE_0_p)) + )) + (net (rename AS_030_000_SYNC_0_un3 "AS_030_000_SYNC_0.un3") (joined + (portRef O (instanceRef AS_030_000_SYNC_0_r)) + (portRef I1 (instanceRef AS_030_000_SYNC_0_n)) + )) + (net (rename AS_030_000_SYNC_0_un1 "AS_030_000_SYNC_0.un1") (joined + (portRef O (instanceRef AS_030_000_SYNC_0_m)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_p)) + )) + (net (rename AS_030_000_SYNC_0_un0 "AS_030_000_SYNC_0.un0") (joined + (portRef O (instanceRef AS_030_000_SYNC_0_n)) + (portRef I1 (instanceRef AS_030_000_SYNC_0_p)) + )) + (net (rename LDS_000_INT_0_un3 "LDS_000_INT_0.un3") (joined + (portRef O (instanceRef LDS_000_INT_0_r)) + (portRef I1 (instanceRef LDS_000_INT_0_n)) + )) + (net (rename LDS_000_INT_0_un1 "LDS_000_INT_0.un1") (joined + (portRef O (instanceRef LDS_000_INT_0_m)) + (portRef I0 (instanceRef LDS_000_INT_0_p)) + )) + (net (rename LDS_000_INT_0_un0 "LDS_000_INT_0.un0") (joined + (portRef O (instanceRef LDS_000_INT_0_n)) + (portRef I1 (instanceRef LDS_000_INT_0_p)) + )) + (net (rename RW_000_DMA_0_un3 "RW_000_DMA_0.un3") (joined + (portRef O (instanceRef RW_000_DMA_0_r)) + (portRef I1 (instanceRef RW_000_DMA_0_n)) + )) + (net (rename RW_000_DMA_0_un1 "RW_000_DMA_0.un1") (joined + (portRef O (instanceRef RW_000_DMA_0_m)) + (portRef I0 (instanceRef RW_000_DMA_0_p)) + )) + (net (rename RW_000_DMA_0_un0 "RW_000_DMA_0.un0") (joined + (portRef O (instanceRef RW_000_DMA_0_n)) + (portRef I1 (instanceRef RW_000_DMA_0_p)) + )) + (net (rename UDS_000_INT_0_un3 "UDS_000_INT_0.un3") (joined + (portRef O (instanceRef UDS_000_INT_0_r)) + (portRef I1 (instanceRef UDS_000_INT_0_n)) + )) + (net (rename UDS_000_INT_0_un1 "UDS_000_INT_0.un1") (joined + (portRef O (instanceRef UDS_000_INT_0_m)) + (portRef I0 (instanceRef UDS_000_INT_0_p)) + )) + (net (rename UDS_000_INT_0_un0 "UDS_000_INT_0.un0") (joined + (portRef O (instanceRef UDS_000_INT_0_n)) + (portRef I1 (instanceRef UDS_000_INT_0_p)) + )) + (net (rename AMIGA_BUS_ENABLE_DMA_LOW_0_un3 "AMIGA_BUS_ENABLE_DMA_LOW_0.un3") (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_r)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_n)) + )) + (net (rename AMIGA_BUS_ENABLE_DMA_LOW_0_un1 "AMIGA_BUS_ENABLE_DMA_LOW_0.un1") (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_m)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_p)) + )) + (net (rename AMIGA_BUS_ENABLE_DMA_LOW_0_un0 "AMIGA_BUS_ENABLE_DMA_LOW_0.un0") (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_n)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_p)) + )) + ) + (property orig_inst_of (string "BUS68030")) + ) + ) + ) + (design BUS68030 (cellRef BUS68030 (libraryRef work))) +) diff --git a/Logic/BUS68030.fse b/Logic/BUS68030.fse index a0aadaa..b871b07 100644 --- a/Logic/BUS68030.fse +++ b/Logic/BUS68030.fse @@ -1,20 +1,20 @@ -fsm_encoding {7137371371} onehot +fsm_encoding {7139371391} onehot -fsm_state_encoding {7137371371} idle_p {00000000} +fsm_state_encoding {7139371391} idle_p {00000000} -fsm_state_encoding {7137371371} idle_n {00000011} +fsm_state_encoding {7139371391} idle_n {00000011} -fsm_state_encoding {7137371371} as_set_p {00000101} +fsm_state_encoding {7139371391} as_set_p {00000101} -fsm_state_encoding {7137371371} as_set_n {00001001} +fsm_state_encoding {7139371391} as_set_n {00001001} -fsm_state_encoding {7137371371} sample_dtack_p {00010001} +fsm_state_encoding {7139371391} sample_dtack_p {00010001} -fsm_state_encoding {7137371371} data_fetch_n {00100001} +fsm_state_encoding {7139371391} data_fetch_n {00100001} -fsm_state_encoding {7137371371} data_fetch_p {01000001} +fsm_state_encoding {7139371391} data_fetch_p {01000001} -fsm_state_encoding {7137371371} end_cycle_n {10000001} +fsm_state_encoding {7139371391} end_cycle_n {10000001} -fsm_registers {7137371371} {SM_AMIGA[0]} {SM_AMIGA[1]} {SM_AMIGA[2]} {SM_AMIGA[3]} {SM_AMIGA[4]} {SM_AMIGA[5]} {SM_AMIGA[6]} {SM_AMIGA_i[7]} +fsm_registers {7139371391} {SM_AMIGA[0]} {SM_AMIGA[1]} {SM_AMIGA[2]} {SM_AMIGA[3]} {SM_AMIGA[4]} {SM_AMIGA[5]} {SM_AMIGA[6]} {SM_AMIGA_i[7]} diff --git a/Logic/BUS68030.naf b/Logic/BUS68030.naf new file mode 100644 index 0000000..ed194d9 --- /dev/null +++ b/Logic/BUS68030.naf @@ -0,0 +1,75 @@ +AS_030 b +AS_000 b +RW_000 b +DS_030 b +UDS_000 b +LDS_000 b +SIZE[1] b +SIZE[0] b +A[31] i +A[30] i +A[29] i +A[28] i +A[27] i +A[26] i +A[25] i +A[24] i +A[23] i +A[22] i +A[21] i +A[20] i +A[19] i +A[18] i +A[17] i +A[16] i +A[15] i +A[14] i +A[13] i +A[12] i +A[11] i +A[10] i +A[9] i +A[8] i +A[7] i +A[6] i +A[5] i +A[4] i +A[3] i +A[2] i +A0 b +A1 i +nEXP_SPACE i +BERR b +BG_030 i +BG_000 o +BGACK_030 o +BGACK_000 i +CLK_030 i +CLK_000 i +CLK_OSZI i +CLK_DIV_OUT o +CLK_EXP o +FPU_CS o +FPU_SENSE i +IPL_030[2] o +IPL_030[1] o +IPL_030[0] o +IPL[2] i +IPL[1] i +IPL[0] i +DSACK1 b +DTACK b +AVEC o +E o +VPA i +VMA o +RST i +RESET o +RW b +FC[1] i +FC[0] i +AMIGA_ADDR_ENABLE o +AMIGA_BUS_DATA_DIR o +AMIGA_BUS_ENABLE_LOW o +AMIGA_BUS_ENABLE_HIGH o +CIIN o diff --git a/Logic/BUS68030.prj b/Logic/BUS68030.prj index ab9360c..a7013d8 100644 --- a/Logic/BUS68030.prj +++ b/Logic/BUS68030.prj @@ -1,6 +1,6 @@ #-- Lattice Semiconductor Corporation Ltd. #-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj -#-- Written on Sat Mar 28 22:02:32 2015 +#-- Written on Wed May 13 22:59:07 2015 #device options diff --git a/Logic/BUS68030.srm b/Logic/BUS68030.srm new file mode 100644 index 0000000..6e947bc --- /dev/null +++ b/Logic/BUS68030.srm @@ -0,0 +1,3765 @@ +%%% protect protected_file +f "c:\isplever\synpbase\lib\vhd\std.vhd"; #file 0 +af .is_vhdl 1; +af .child_list "-1"; +af .parent_list "-1"; +f "c:\isplever\synpbase\lib\vhd\snps_haps_pkg.vhd"; #file 1 +af .is_vhdl 1; +af .child_list "-1"; +af .parent_list "-1"; +f "c:\isplever\synpbase\lib\vhd\std1164.vhd"; #file 2 +af .is_vhdl 1; +af .child_list "-1"; +af .parent_list "-1"; +f "c:\isplever\synpbase\lib\vhd\numeric.vhd"; #file 3 +af .is_vhdl 1; +af .child_list "-1"; +af .parent_list "-1"; +f "c:\isplever\synpbase\lib\vhd\umr_capim.vhd"; #file 4 +af .is_vhdl 1; +af .child_list "-1"; +af .parent_list "-1"; +f "c:\isplever\synpbase\lib\vhd\arith.vhd"; #file 5 +af .is_vhdl 1; +af .child_list "-1"; +af .parent_list "-1"; +f "c:\isplever\synpbase\lib\vhd\unsigned.vhd"; #file 6 +af .is_vhdl 1; +af .child_list "-1"; +af .parent_list "-1"; +f "c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd"; #file 7 +af .is_vhdl 1; +af .child_list "-1"; +af .parent_list "-1"; +VNAME 'mach.MACH_DFF.prim'; # view id 0 +VNAME 'mach.DFF.prim'; # view id 1 +VNAME 'mach.BI_DIR.prim'; # view id 2 +VNAME 'mach.IBUF.prim'; # view id 3 +VNAME 'mach.OBUF.prim'; # view id 4 +VNAME 'mach.BUFTH.prim'; # view id 5 +VNAME 'mach.AND2.prim'; # view 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+Qqj=vqQt_1Az_q hA_p 7_vqp_mWjM3k4Q +S4v=qQ_tqA_z1 Ahqp7 _vpq_mjW_3jkM;R +sfjj:ROlNEhRQesRbH7lR1d_jjj_7_SH +m1=7_jjd__7jHQ +Sj1=7_jjd_;7j +fsRjR:jlENOR7qh.sRbHblRFO#_D3 \k_Md8j#_d8j_jm +S=#bF_ OD\M3kd#_8_jjd_ +8jS=Qj7j1_d7j_j +_HS=Q41qv_vqQtr;n9 +fsRjR:jlENOReQhRHbslvRqQ_tqA_z1 Ahqp7 _vpq_mHW_ +=SmqtvQqz_A1h_ q Ap_q7v_Wpm_SH +Qqj=vqQt_1Az_q hA_p 7_vqp;mW +fsRjR:jlENOR7qh.sRbHklRMN4_lNHo_#Lk_NCML_DCD +FISkm=MN4_lNHo_#Lk_NCML_DCD +FIS=QjqtvQqz_A1h_ q Ap_q7v_Wpm_SH +QA4=tiqB_jjd_aQh_ +H;sjRf:ljRNROEq.h7RHbslFRb#D_O k\3MLU_od_jjm +S=#bF_ OD\M3kUo_L_jjd_Sj +QAj=td_jj__OHQ +S4F=b#D_O k\3MLn_od_jj;_H +fsRjR:jlENOReQhRHbslMRkn#_N_jjd_SH +mM=kn#_N_jjd_SH +Qkj=MNn_#d_jjs; +R:fjjNRlOQERhbeRsRHlqj1_jQj_hHa_ +=Smqj1_jQj_hHa_ +jSQ=_q1j_jjQ;ha +fsRjR:jlENOR7qh.sRbHklRMNc_#j_jjm +S=ckM__N#j +jjS=Qjqj1_jQj_hHa_ +4SQ=_q1j_djHs; +R:fjjNRlOQERhbeRsRHlk_McNj#_jHj_ +=Smk_McNj#_jHj_ +jSQ=ckM__N#j;jj +fsRjR:jlENOReQhRHbsl1R7_jjj_q7v_SH +m1=7_jjj_q7v_SH +Q7j=1j_jjv_7qs; +R:fjjNRlOqERhR7.blsHRnkM__8#j +djSkm=M8n_#d_jjQ +Sj1=q_jjj_SH +Q74=1j_jjv_7q;_H +fsRjR:jlENOReQhRHbslMRkn#_8_jjd_SH +mM=kn#_8_jjd_SH +Qkj=M8n_#d_jjs; +R:fjjNRlOQERhbeRsRHlk_Mnk_8#j_jjHm +S=nkM_#k8_jjj_SH +Qkj=Mkn_8j#_j +j; + +@ diff --git a/Logic/BUS68030.srr b/Logic/BUS68030.srr new file mode 100644 index 0000000..6674fb8 --- /dev/null +++ b/Logic/BUS68030.srr @@ -0,0 +1,107 @@ +#Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014 +#install: C:\ispLever\synpbase +#OS: Windows 7 6.1 +#Hostname: DEEPTHOUGHT + +#Implementation: logic + +$ Start of Compile +#Wed May 13 22:59:14 2015 + +Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014 +@N|Running in 64-bit mode +Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. + +@N: CD720 :"C:\ispLever\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns +@N:"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Top entity is set to BUS68030. +File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling +VHDL syntax check successful! +File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling +@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral +@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:7:126:17|Signal clk_out_pre is undriven +Post processing for work.bus68030.behavioral +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Pruning register AMIGA_BUS_ENABLE_INT_4 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Pruning register CLK_000_D4_2 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_000_D3_2 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_000_D2_2 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:35:127:37|Pruning register CLK_OUT_INT_2 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:36:124:38|Pruning register CLK_OUT_PRE_50_D_2 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":155:2:155:3|Pruning register CLK_030_D0_2 +@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":135:61:135:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ... +@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:34:134:36|Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ... +@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ... +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register SM_AMIGA +Extracted state machine for register SM_AMIGA +State machine has 8 reachable states with original encodings of: + 000 + 001 + 010 + 011 + 100 + 101 + 110 + 111 +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register cpu_est +@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":23:1:23:1|Input port bits 15 to 2 of a(31 downto 2) are unused +@END + +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Wed May 13 22:59:15 2015 + +###########################################################] +Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014 +@N|Running in 64-bit mode +File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs changed - recompiling + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Wed May 13 22:59:16 2015 + +###########################################################] +Map & Optimize Report + +Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014 +Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited. +Product Version I-2014.03LC +@N: MF248 |Running in 64-bit mode. +@W: MO111 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":497:16:497:18|Tristate driver CLK_DIV_OUT_1 on net CLK_DIV_OUT_1 has its enable tied to GND (module BUS68030) +Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral)) +original code -> new code + 000 -> 00000000 + 001 -> 00000011 + 010 -> 00000101 + 011 -> 00001001 + 100 -> 00010001 + 101 -> 00100001 + 110 -> 01000001 + 111 -> 10000001 +@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":190:4:190:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits +@W: BN132 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:34:134:36|Removing instance CLK_000_P_SYNC[10], because it is equivalent to instance CLK_000_PE +--------------------------------------- +Resource Usage Report + +Simple gate primitives: +DFF 83 uses +BI_DIR 11 uses +IBUF 46 uses +OBUF 15 uses +BUFTH 3 uses +AND2 303 uses +INV 263 uses +XOR2 15 uses +OR2 28 uses + + +@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis. +I-2014.03LC +Mapper successful! + +At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Wed May 13 22:59:16 2015 + +###########################################################] diff --git a/Logic/BUS68030.srs b/Logic/BUS68030.srs new file mode 100644 index 0000000..d37a669 Binary files /dev/null and b/Logic/BUS68030.srs differ diff --git a/Logic/automake.err b/Logic/automake.err new file mode 100644 index 0000000..f964a6e --- /dev/null +++ b/Logic/automake.err @@ -0,0 +1 @@ +Need not generate svf file according to the constraints, exit diff --git a/Logic/bus68030.exf b/Logic/bus68030.exf new file mode 100644 index 0000000..370990e --- /dev/null +++ b/Logic/bus68030.exf @@ -0,0 +1,882 @@ +Section Type Array Num Name Real Name Base Number Increment +// ------------------------------------------------------------------------------------------------- + Port 1 A(31:2) A 31 30 -1 + Port 2 IPL(2:0) IPL 2 3 -1 + Port 3 FC(1:0) FC 1 2 -1 + Port 4 IPL_030(2:0) IPL_030 2 3 -1 + Port 5 SIZE(1:0) SIZE 1 2 -1 +End +Section Member Rename Array-Notation Array Number Index +// ------------------------------------------------------------------------------------- + Port SIZE_1_ SIZE[1] 5 0 + Port SIZE_0_ SIZE[0] 5 1 + Port A_31_ A[31] 1 0 + Port A_30_ A[30] 1 1 + Port A_29_ A[29] 1 2 + Port A_28_ A[28] 1 3 + Port A_27_ A[27] 1 4 + Port A_26_ A[26] 1 5 + Port A_25_ A[25] 1 6 + Port A_24_ A[24] 1 7 + Port A_23_ A[23] 1 8 + Port A_22_ A[22] 1 9 + Port A_21_ A[21] 1 10 + Port A_20_ A[20] 1 11 + Port A_19_ A[19] 1 12 + Port A_18_ A[18] 1 13 + Port A_17_ A[17] 1 14 + Port A_16_ A[16] 1 15 + Port A_15_ A[15] 1 16 + Port A_14_ A[14] 1 17 + Port A_13_ A[13] 1 18 + Port A_12_ A[12] 1 19 + Port A_11_ A[11] 1 20 + Port A_10_ A[10] 1 21 + Port A_9_ A[9] 1 22 + Port A_8_ A[8] 1 23 + Port A_7_ A[7] 1 24 + Port A_6_ A[6] 1 25 + Port A_5_ A[5] 1 26 + Port A_4_ A[4] 1 27 + Port A_3_ A[3] 1 28 + Port A_2_ A[2] 1 29 + Port IPL_030_2_ IPL_030[2] 4 0 + Port IPL_030_1_ IPL_030[1] 4 1 + Port IPL_030_0_ IPL_030[0] 4 2 + Port IPL_2_ IPL[2] 2 0 + Port IPL_1_ IPL[1] 2 1 + Port IPL_0_ IPL[0] 2 2 + Port FC_1_ FC[1] 3 0 + Port FC_0_ FC[0] 3 1 +End +Section Cross Reference File +Design 'BUS68030' created Wed May 13 22:59:21 2015 + Type New Name Original Name +// ---------------------------------------------------------------------- + Inst i_z4141 AS_030 + Inst i_z4242 AS_000 + Inst i_z4343 RW_000 + Inst i_z4444 DS_030 + Inst i_z4545 UDS_000 + Inst i_z4646 LDS_000 + Inst i_z5757 A0 + Inst i_z5A5A BERR + Inst i_z5I5I CLK_DIV_OUT + Inst i_z5S5S DSACK1 + Inst i_z6464 RW + Inst i_z6B6B CIIN + Inst pos_clk_un7_clk_000_pe_0_a2 pos_clk.un7_clk_000_pe_0_a2 + Inst DSACK1_INT_0_n DSACK1_INT_0.n + Inst DSACK1_INT_0_p DSACK1_INT_0.p + Inst AS_000_INT_0_r AS_000_INT_0.r + Inst AS_000_INT_0_m AS_000_INT_0.m + Inst BGACK_030_INT_0_r BGACK_030_INT_0.r + Inst AS_000_INT_0_n AS_000_INT_0.n + Inst BGACK_030_INT_0_m BGACK_030_INT_0.m + Inst AS_000_INT_0_p AS_000_INT_0.p + Inst BGACK_030_INT_0_n BGACK_030_INT_0.n + Inst pos_clk_un6_bg_030_1 pos_clk.un6_bg_030_1 + Inst BGACK_030_INT_0_p BGACK_030_INT_0.p + Inst DS_000_ENABLE_0_r DS_000_ENABLE_0.r + Inst pos_clk_un6_bg_030 pos_clk.un6_bg_030 + Inst VMA_INT_0_r VMA_INT_0.r + Inst DS_000_ENABLE_0_m DS_000_ENABLE_0.m + Inst SM_AMIGA_nss_i_i_0_1_0_ SM_AMIGA_nss_i_i_0_1[0] + Inst VMA_INT_0_m VMA_INT_0.m + Inst DS_000_ENABLE_0_n DS_000_ENABLE_0.n + Inst SM_AMIGA_nss_i_i_0_2_0_ SM_AMIGA_nss_i_i_0_2[0] + Inst VMA_INT_0_n VMA_INT_0.n + Inst DS_000_ENABLE_0_p DS_000_ENABLE_0.p + Inst SM_AMIGA_nss_i_i_0_3_0_ SM_AMIGA_nss_i_i_0_3[0] + Inst VMA_INT_0_p VMA_INT_0.p + Inst AS_030_000_SYNC_0_r AS_030_000_SYNC_0.r + Inst SM_AMIGA_nss_i_i_0_0_ SM_AMIGA_nss_i_i_0[0] + Inst RW_000_INT_0_r RW_000_INT_0.r + Inst AS_030_000_SYNC_0_m AS_030_000_SYNC_0.m + Inst SM_AMIGA_nss_i_i_0_a2_1_1_0_ SM_AMIGA_nss_i_i_0_a2_1_1[0] + Inst RW_000_INT_0_m RW_000_INT_0.m + Inst AS_030_000_SYNC_0_n AS_030_000_SYNC_0.n + Inst SM_AMIGA_nss_i_i_0_a2_1_2_0_ SM_AMIGA_nss_i_i_0_a2_1_2[0] + Inst RW_000_INT_0_n RW_000_INT_0.n + Inst AS_030_000_SYNC_0_p AS_030_000_SYNC_0.p + Inst SM_AMIGA_nss_i_i_0_a2_1_3_0_ SM_AMIGA_nss_i_i_0_a2_1_3[0] + Inst RW_000_INT_0_p RW_000_INT_0.p + Inst LDS_000_INT_0_r LDS_000_INT_0.r + Inst SM_AMIGA_nss_i_i_0_a2_1_0_ SM_AMIGA_nss_i_i_0_a2_1[0] + Inst LDS_000_INT_0_m LDS_000_INT_0.m + Inst pos_clk_cpu_est_11_0_0_1_1_ pos_clk.cpu_est_11_0_0_1[1] + Inst LDS_000_INT_0_n LDS_000_INT_0.n + Inst pos_clk_cpu_est_11_0_0_2_1_ pos_clk.cpu_est_11_0_0_2[1] + Inst pos_clk_RST_DLY_5_iv_0_x2_0_ pos_clk.RST_DLY_5_iv_0_x2[0] + Inst LDS_000_INT_0_p LDS_000_INT_0.p + Inst pos_clk_un37_as_030_d0_i_a2_1_4 pos_clk.un37_as_030_d0_i_a2_1_4 + Inst RW_000_DMA_0_r RW_000_DMA_0.r + Inst pos_clk_un37_as_030_d0_i_a2_1 pos_clk.un37_as_030_d0_i_a2_1 + Inst pos_clk_RST_DLY_5_iv_0_0_ pos_clk.RST_DLY_5_iv_0[0] + Inst RW_000_DMA_0_m RW_000_DMA_0.m + Inst SM_AMIGA_srsts_i_i_o2_2_ SM_AMIGA_srsts_i_i_o2[2] + Inst RW_000_DMA_0_n RW_000_DMA_0.n + Inst SM_AMIGA_i_4_ SM_AMIGA_i[4] + Inst RW_000_DMA_0_p RW_000_DMA_0.p + Inst SM_AMIGA_srsts_i_0_o2_4_ SM_AMIGA_srsts_i_0_o2[4] + Inst UDS_000_INT_0_r UDS_000_INT_0.r + Inst cpu_est_0_0_x2_0_ cpu_est_0_0_x2[0] + Inst UDS_000_INT_0_m UDS_000_INT_0.m + Inst UDS_000_INT_0_n UDS_000_INT_0.n + Inst UDS_000_INT_0_p UDS_000_INT_0.p + Inst SM_AMIGA_srsts_i_0_m2_3__r SM_AMIGA_srsts_i_0_m2_3_.r + Inst SM_AMIGA_srsts_i_0_m2_3__m SM_AMIGA_srsts_i_0_m2_3_.m + Inst AMIGA_BUS_ENABLE_DMA_LOW_0_r AMIGA_BUS_ENABLE_DMA_LOW_0.r + Inst SM_AMIGA_srsts_i_0_m2_3__n SM_AMIGA_srsts_i_0_m2_3_.n + Inst AMIGA_BUS_ENABLE_DMA_LOW_0_m AMIGA_BUS_ENABLE_DMA_LOW_0.m + Inst SM_AMIGA_srsts_i_0_m2_3__p SM_AMIGA_srsts_i_0_m2_3_.p + Inst AMIGA_BUS_ENABLE_DMA_LOW_0_n AMIGA_BUS_ENABLE_DMA_LOW_0.n + Inst pos_clk_CYCLE_DMA_5_1_i_x2 pos_clk.CYCLE_DMA_5_1_i_x2 + Inst AMIGA_BUS_ENABLE_DMA_LOW_0_p AMIGA_BUS_ENABLE_DMA_LOW_0.p + Inst pos_clk_CYCLE_DMA_5_0_i_x2 pos_clk.CYCLE_DMA_5_0_i_x2 + Inst cpu_est_i_1_ cpu_est_i[1] + Inst pos_clk_un3_ds_030_d0 pos_clk.un3_ds_030_d0 + Inst SM_AMIGA_srsts_i_0_2_5_ SM_AMIGA_srsts_i_0_2[5] + Inst SM_AMIGA_srsts_i_0_5_ SM_AMIGA_srsts_i_0[5] + Inst pos_clk_un24_bgack_030_int_i_0_o2_1 pos_clk.un24_bgack_030_int_i_0_o2_1 + Inst cpu_est_i_3_ cpu_est_i[3] + Inst pos_clk_un8_bg_030 pos_clk.un8_bg_030 + Inst pos_clk_un24_bgack_030_int_i_0_o2 pos_clk.un24_bgack_030_int_i_0_o2 + Inst cpu_est_i_0_ cpu_est_i[0] + Inst pos_clk_un37_as_030_d0_i_o4_1 pos_clk.un37_as_030_d0_i_o4_1 + Inst pos_clk_un37_as_030_d0_i_o4 pos_clk.un37_as_030_d0_i_o4 + Inst pos_clk_cpu_est_11_0_0_a2_1_1_ pos_clk.cpu_est_11_0_0_a2_1[1] + Inst SM_AMIGA_nss_i_i_0_o4_1_1_0_ SM_AMIGA_nss_i_i_0_o4_1_1[0] + Inst SM_AMIGA_nss_i_i_0_o4_1_0_ SM_AMIGA_nss_i_i_0_o4_1[0] + Inst SM_AMIGA_srsts_i_i_a2_3_2_ SM_AMIGA_srsts_i_i_a2_3[2] + Inst SM_AMIGA_nss_i_i_0_o4_1_0_0_ SM_AMIGA_nss_i_i_0_o4_1_0[0] + Inst pos_clk_cpu_est_11_0_0_a2_2_1_ pos_clk.cpu_est_11_0_0_a2_2[1] + Inst SM_AMIGA_nss_i_i_0_o4_0_ SM_AMIGA_nss_i_i_0_o4[0] + Inst SM_AMIGA_srsts_i_i_a2_1_2_ SM_AMIGA_srsts_i_i_a2_1[2] + Inst pos_clk_un11_ds_030_d0_1 pos_clk.un11_ds_030_d0_1 + Inst pos_clk_cpu_est_11_i_0_2_ pos_clk.cpu_est_11_i_0[2] + Inst pos_clk_un11_ds_030_d0 pos_clk.un11_ds_030_d0 + Inst SM_AMIGA_i_5_ SM_AMIGA_i[5] + Inst IPL_030DFF_2_ IPL_030DFF[2] + Inst pos_clk_un37_as_030_d0_i_a2_1_1 pos_clk.un37_as_030_d0_i_a2_1_1 + Inst IPL_D0_0_ IPL_D0[0] + Inst pos_clk_un37_as_030_d0_i_a2_1_2 pos_clk.un37_as_030_d0_i_a2_1_2 + Inst pos_clk_un7_clk_000_pe_0 pos_clk.un7_clk_000_pe_0 + Inst IPL_D0_1_ IPL_D0[1] + Inst pos_clk_un37_as_030_d0_i_a2_1_3 pos_clk.un37_as_030_d0_i_a2_1_3 + Inst SM_AMIGA_srsts_i_i_o2_0_2_ SM_AMIGA_srsts_i_i_o2_0[2] + Inst IPL_D0_2_ IPL_D0[2] + Inst SM_AMIGA_srsts_i_o3_0_i_o2_0_ SM_AMIGA_srsts_i_o3_0_i_o2[0] + Inst SM_AMIGA_i_7_ SM_AMIGA_i[7] + Inst cpu_est_i_2_ cpu_est_i[2] + Inst SM_AMIGA_6_ SM_AMIGA[6] + Inst pos_clk_cpu_est_11_i_0_o2_2_ pos_clk.cpu_est_11_i_0_o2[2] + Inst SM_AMIGA_5_ SM_AMIGA[5] + Inst pos_clk_cpu_est_11_0_0_o2_1_ pos_clk.cpu_est_11_0_0_o2[1] + Inst SM_AMIGA_4_ SM_AMIGA[4] + Inst pos_clk_cpu_est_11_0_0_o2_3_ pos_clk.cpu_est_11_0_0_o2[3] + Inst SM_AMIGA_3_ SM_AMIGA[3] + Inst SM_AMIGA_srsts_i_0_a2_3_ SM_AMIGA_srsts_i_0_a2[3] + Inst SM_AMIGA_2_ SM_AMIGA[2] + Inst SM_AMIGA_srsts_i_o3_0_o2_3_ SM_AMIGA_srsts_i_o3_0_o2[3] + Inst SM_AMIGA_1_ SM_AMIGA[1] + Inst SM_AMIGA_i_0_ SM_AMIGA_i[0] + Inst SM_AMIGA_0_ SM_AMIGA[0] + Inst SM_AMIGA_i_3_ SM_AMIGA_i[3] + Inst cpu_est_0_ cpu_est[0] + Inst cpu_est_1_ cpu_est[1] + Inst cpu_est_2_ cpu_est[2] + Inst pos_clk_un4_bgack_000_i_a2 pos_clk.un4_bgack_000_i_a2 + Inst cpu_est_3_ cpu_est[3] + Inst pos_clk_un6_bg_030_i pos_clk.un6_bg_030_i + Inst IPL_030DFF_0_ IPL_030DFF[0] + Inst pos_clk_un8_bg_030_i pos_clk.un8_bg_030_i + Inst SM_AMIGA_srsts_i_0_m2_1__r SM_AMIGA_srsts_i_0_m2_1_.r + Inst IPL_030DFF_1_ IPL_030DFF[1] + Inst SM_AMIGA_srsts_i_0_1_5_ SM_AMIGA_srsts_i_0_1[5] + Inst SM_AMIGA_srsts_i_0_m2_1__m SM_AMIGA_srsts_i_0_m2_1_.m + Inst CLK_000_N_SYNC_9_ CLK_000_N_SYNC[9] + Inst IPL_D0_0_i_0_ IPL_D0_0_i[0] + Inst SM_AMIGA_srsts_i_0_m2_1__n SM_AMIGA_srsts_i_0_m2_1_.n + Inst CLK_000_N_SYNC_10_ CLK_000_N_SYNC[10] + Inst SM_AMIGA_srsts_i_0_m2_1__p SM_AMIGA_srsts_i_0_m2_1_.p + Inst CLK_000_N_SYNC_11_ CLK_000_N_SYNC[11] + Inst SM_AMIGA_srsts_i_0_a2_4_ SM_AMIGA_srsts_i_0_a2[4] + Inst RST_DLY_0_ RST_DLY[0] + Inst RST_DLY_1_ RST_DLY[1] + Inst pos_clk_cpu_est_11_0_0_a2_3_ pos_clk.cpu_est_11_0_0_a2[3] + Inst RST_DLY_2_ RST_DLY[2] + Inst pos_clk_cpu_est_11_0_0_a2_0_3_ pos_clk.cpu_est_11_0_0_a2_0[3] + Inst RST_DLY_3_ RST_DLY[3] + Inst pos_clk_cpu_est_11_0_0_a2_1_ pos_clk.cpu_est_11_0_0_a2[1] + Inst RST_DLY_4_ RST_DLY[4] + Inst pos_clk_cpu_est_11_0_0_a2_0_1_ pos_clk.cpu_est_11_0_0_a2_0[1] + Inst RST_DLY_5_ RST_DLY[5] + Inst pos_clk_un9_clk_000_n_sync pos_clk.un9_clk_000_n_sync + Inst RST_DLY_6_ RST_DLY[6] + Inst RST_DLY_7_ RST_DLY[7] + Inst pos_clk_un11_clk_000_n_sync pos_clk.un11_clk_000_n_sync + Inst CYCLE_DMA_0_ CYCLE_DMA[0] + Inst SM_AMIGA_nss_i_i_0_a2_2_0_ SM_AMIGA_nss_i_i_0_a2_2[0] + Inst CYCLE_DMA_1_ CYCLE_DMA[1] + Inst SM_AMIGA_srsts_i_0_a2_0_ SM_AMIGA_srsts_i_0_a2[0] + Inst SIZE_DMA_0_ SIZE_DMA[0] + Inst SM_AMIGA_nss_i_i_0_a4_0_ SM_AMIGA_nss_i_i_0_a4[0] + Inst SIZE_DMA_1_ SIZE_DMA[1] + Inst SM_AMIGA_srsts_i_0_0_ SM_AMIGA_srsts_i_0[0] + Inst CLK_000_P_SYNC_5_ CLK_000_P_SYNC[5] + Inst SM_AMIGA_nss_i_i_0_o4_0_0_ SM_AMIGA_nss_i_i_0_o4_0[0] + Inst CLK_000_P_SYNC_6_ CLK_000_P_SYNC[6] + Inst SM_AMIGA_nss_i_i_0_o2_0_ SM_AMIGA_nss_i_i_0_o2[0] + Inst CLK_000_P_SYNC_7_ CLK_000_P_SYNC[7] + Inst SM_AMIGA_i_1_ SM_AMIGA_i[1] + Inst CLK_000_P_SYNC_8_ CLK_000_P_SYNC[8] + Inst SIZE_c_i_1_ SIZE_c_i[1] + Inst SM_AMIGA_srsts_i_0_o4_0_ SM_AMIGA_srsts_i_0_o4[0] + Inst CLK_000_P_SYNC_9_ CLK_000_P_SYNC[9] + Inst SM_AMIGA_i_6_ SM_AMIGA_i[6] + Inst CLK_000_N_SYNC_0_ CLK_000_N_SYNC[0] + Inst IPL_030_1_i_2_ IPL_030_1_i[2] + Inst SM_AMIGA_srsts_i_0_a2_0_6_ SM_AMIGA_srsts_i_0_a2_0[6] + Inst CLK_000_N_SYNC_1_ CLK_000_N_SYNC[1] + Inst CLK_000_N_SYNC_2_ CLK_000_N_SYNC[2] + Inst IPL_030_1_i_1_ IPL_030_1_i[1] + Inst SM_AMIGA_srsts_i_0_a2_0_4_ SM_AMIGA_srsts_i_0_a2_0[4] + Inst CLK_000_N_SYNC_3_ CLK_000_N_SYNC[3] + Inst CLK_000_N_SYNC_4_ CLK_000_N_SYNC[4] + Inst IPL_030_1_i_0_ IPL_030_1_i[0] + Inst CLK_000_N_SYNC_5_ CLK_000_N_SYNC[5] + Inst IPL_c_i_2_ IPL_c_i[2] + Inst pos_clk_SIZE_DMA_6_0_0_a2_0_ pos_clk.SIZE_DMA_6_0_0_a2[0] + Inst CLK_000_N_SYNC_6_ CLK_000_N_SYNC[6] + Inst IPL_D0_0_i_2_ IPL_D0_0_i[2] + Inst pos_clk_SIZE_DMA_6_0_0_a2_1_ pos_clk.SIZE_DMA_6_0_0_a2[1] + Inst CLK_000_N_SYNC_7_ CLK_000_N_SYNC[7] + Inst IPL_c_i_1_ IPL_c_i[1] + Inst SM_AMIGA_i_2_ SM_AMIGA_i[2] + Inst CLK_000_N_SYNC_8_ CLK_000_N_SYNC[8] + Inst IPL_D0_0_i_1_ IPL_D0_0_i[1] + Inst SM_AMIGA_srsts_i_0_a2_1_ SM_AMIGA_srsts_i_0_a2[1] + Inst CLK_000_P_SYNC_0_ CLK_000_P_SYNC[0] + Inst IPL_c_i_0_ IPL_c_i[0] + Inst CLK_000_P_SYNC_1_ CLK_000_P_SYNC[1] + Inst pos_clk_cpu_est_11_0_0_i_3_ pos_clk.cpu_est_11_0_0_i[3] + Inst CLK_000_P_SYNC_2_ CLK_000_P_SYNC[2] + Inst CLK_000_P_SYNC_3_ CLK_000_P_SYNC[3] + Inst CLK_000_P_SYNC_4_ CLK_000_P_SYNC[4] + Inst pos_clk_DS_000_DMA_4_f0_0_i pos_clk.DS_000_DMA_4_f0_0_i + Inst pos_clk_un22_bgack_030_int pos_clk.un22_bgack_030_int + Inst pos_clk_un14_clk_000_n_sync pos_clk.un14_clk_000_n_sync + Inst pos_clk_un11_clk_000_n_sync_i pos_clk.un11_clk_000_n_sync_i + Inst pos_clk_un37_as_030_d0_i pos_clk.un37_as_030_d0_i + Inst pos_clk_un24_bgack_030_int_i_0_o2_i pos_clk.un24_bgack_030_int_i_0_o2_i + Inst pos_clk_SIZE_DMA_6_0_0_0_ pos_clk.SIZE_DMA_6_0_0[0] + Inst SM_AMIGA_srsts_i_0_o2_i_6_ SM_AMIGA_srsts_i_0_o2_i[6] + Inst pos_clk_SIZE_DMA_6_0_0_1_ pos_clk.SIZE_DMA_6_0_0[1] + Inst SM_AMIGA_srsts_i_0_o2_i_5_ SM_AMIGA_srsts_i_0_o2_i[5] + Inst pos_clk_CLK_000_P_SYNC_2_0_a2_0_ pos_clk.CLK_000_P_SYNC_2_0_a2[0] + Inst pos_clk_un37_as_030_d0_i_a2_0 pos_clk.un37_as_030_d0_i_a2_0 + Inst pos_clk_un37_as_030_d0_i_a2 pos_clk.un37_as_030_d0_i_a2 + Inst pos_clk_A0_DMA_3_0_a2 pos_clk.A0_DMA_3_0_a2 + Inst pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2 pos_clk.AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2 + Inst pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2 pos_clk.AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2 + Inst SM_AMIGA_srsts_i_i_i_2_ SM_AMIGA_srsts_i_i_i[2] + Inst pos_clk_DS_000_DMA_4_f0_0_a2 pos_clk.DS_000_DMA_4_f0_0_a2 + Inst SM_AMIGA_srsts_i_0_a2_1_5_ SM_AMIGA_srsts_i_0_a2_1[5] + Inst SM_AMIGA_srsts_i_0_a2_0_5_ SM_AMIGA_srsts_i_0_a2_0[5] + Inst SM_AMIGA_srsts_i_0_a2_5_ SM_AMIGA_srsts_i_0_a2[5] + Inst SM_AMIGA_srsts_i_0_a2_6_ SM_AMIGA_srsts_i_0_a2[6] + Inst pos_clk_un37_as_030_d0_i_i pos_clk.un37_as_030_d0_i_i + Inst SM_AMIGA_srsts_i_0_o4_1_ SM_AMIGA_srsts_i_0_o4[1] + Inst pos_clk_SIZE_DMA_6_0_0_o4_0_ pos_clk.SIZE_DMA_6_0_0_o4[0] + Inst pos_clk_un3_as_030_d0_i_i_o2 pos_clk.un3_as_030_d0_i_i_o2 + Inst pos_clk_CLK_000_N_SYNC_2_0_o4_0_ pos_clk.CLK_000_N_SYNC_2_0_o4[0] + Inst SM_AMIGA_nss_i_i_0_o4_i_0_ SM_AMIGA_nss_i_i_0_o4_i[0] + Inst pos_clk_un3_as_030_d0_i_i_o2_i pos_clk.un3_as_030_d0_i_i_o2_i + Inst SM_AMIGA_srsts_i_0_o2_5_ SM_AMIGA_srsts_i_0_o2[5] + Inst SM_AMIGA_srsts_i_0_o2_6_ SM_AMIGA_srsts_i_0_o2[6] + Inst SM_AMIGA_nss_i_i_0_o4_1_i_0_ SM_AMIGA_nss_i_i_0_o4_1_i[0] + Inst pos_clk_CYCLE_DMA_5_1_i_o2 pos_clk.CYCLE_DMA_5_1_i_o2 + Inst SIZE_0_ SIZE[0] + Inst pos_clk_SIZE_DMA_6_0_0_o4_i_0_ pos_clk.SIZE_DMA_6_0_0_o4_i[0] + Inst pos_clk_un24_bgack_030_int_i_0_x2 pos_clk.un24_bgack_030_int_i_0_x2 + Inst SIZE_1_ SIZE[1] + Inst SM_AMIGA_srsts_i_0_o4_i_1_ SM_AMIGA_srsts_i_0_o4_i[1] + Inst pos_clk_un37_as_030_d0_i_o4_i pos_clk.un37_as_030_d0_i_o4_i + Inst pos_clk_DS_000_DMA_4_f0_0 pos_clk.DS_000_DMA_4_f0_0 + Inst SM_AMIGA_i_i_7_ SM_AMIGA_i_i[7] + Inst SM_AMIGA_nss_i_i_0_o4_0_i_0_ SM_AMIGA_nss_i_i_0_o4_0_i[0] + Inst SM_AMIGA_srsts_i_i_2_ SM_AMIGA_srsts_i_i[2] + Inst CLK_000_N_SYNC_i_10_ CLK_000_N_SYNC_i[10] + Inst pos_clk_un9_clk_000_n_sync_i pos_clk.un9_clk_000_n_sync_i + Inst pos_clk_un14_clk_000_n_sync_i pos_clk.un14_clk_000_n_sync_i + Inst pos_clk_un22_bgack_030_int_i_0 pos_clk.un22_bgack_030_int_i_0 + Inst A_i_16_ A_i[16] + Inst pos_clk_SIZE_DMA_6_0_0_i_1_ pos_clk.SIZE_DMA_6_0_0_i[1] + Inst SIZE_DMA_i_1_ SIZE_DMA_i[1] + Inst A_16_ A[16] + Inst pos_clk_SIZE_DMA_6_0_0_i_0_ pos_clk.SIZE_DMA_6_0_0_i[0] + Inst SIZE_DMA_i_0_ SIZE_DMA_i[0] + Inst A_17_ A[17] + Inst A_18_ A[18] + Inst A_19_ A[19] + Inst pos_clk_un7_clk_000_pe_0_i pos_clk.un7_clk_000_pe_0_i + Inst A_i_24_ A_i[24] + Inst A_20_ A[20] + Inst A_21_ A[21] + Inst A_22_ A[22] + Inst A_23_ A[23] + Inst un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__r un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0_.r + Inst A_24_ A[24] + Inst un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__m un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0_.m + Inst A_25_ A[25] + Inst un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__n un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0_.n + Inst A_26_ A[26] + Inst un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__p un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0_.p + Inst A_27_ A[27] + Inst A_28_ A[28] + Inst un1_SM_AMIGA_7_i_m2_r un1_SM_AMIGA_7_i_m2.r + Inst A_29_ A[29] + Inst un1_SM_AMIGA_7_i_m2_m un1_SM_AMIGA_7_i_m2.m + Inst A_30_ A[30] + Inst un1_SM_AMIGA_7_i_m2_n un1_SM_AMIGA_7_i_m2.n + Inst A_31_ A[31] + Inst un1_SM_AMIGA_7_i_m2_p un1_SM_AMIGA_7_i_m2.p + Inst SM_AMIGA_srsts_i_o3_0_o2_i_3_ SM_AMIGA_srsts_i_o3_0_o2_i[3] + Inst SM_AMIGA_srsts_i_0_o4_i_0_ SM_AMIGA_srsts_i_0_o4_i[0] + Inst A_i_25_ A_i[25] + Inst SM_AMIGA_srsts_i_0_o2_i_4_ SM_AMIGA_srsts_i_0_o2_i[4] + Inst A_i_26_ A_i[26] + Inst SM_AMIGA_srsts_i_i_o2_i_2_ SM_AMIGA_srsts_i_i_o2_i[2] + Inst A_i_27_ A_i[27] + Inst pos_clk_cpu_est_11_0_0_o2_i_3_ pos_clk.cpu_est_11_0_0_o2_i[3] + Inst A_i_28_ A_i[28] + Inst pos_clk_cpu_est_11_0_0_o2_i_1_ pos_clk.cpu_est_11_0_0_o2_i[1] + Inst A_i_29_ A_i[29] + Inst pos_clk_cpu_est_11_i_0_o2_i_2_ pos_clk.cpu_est_11_i_0_o2_i[2] + Inst A_i_30_ A_i[30] + Inst SM_AMIGA_srsts_i_o3_0_i_o2_i_0_ SM_AMIGA_srsts_i_o3_0_i_o2_i[0] + Inst A_i_31_ A_i[31] + Inst A_i_18_ A_i[18] + Inst A_i_19_ A_i[19] + Inst SM_AMIGA_srsts_i_i_o2_0_i_2_ SM_AMIGA_srsts_i_i_o2_0_i[2] + Inst IPL_030_0_ IPL_030[0] + Inst IPL_030_1_ IPL_030[1] + Inst IPL_030_2_ IPL_030[2] + Inst un1_RST_DLY_i_m_i_6_ un1_RST_DLY_i_m_i[6] + Inst IPL_0_ IPL[0] + Inst un1_RST_DLY_i_m_i_7_ un1_RST_DLY_i_m_i[7] + Inst IPL_1_ IPL[1] + Inst un1_RST_DLY_i_m_i_8_ un1_RST_DLY_i_m_i[8] + Inst IPL_2_ IPL[2] + Inst un1_RST_DLY_i_m_i_2_ un1_RST_DLY_i_m_i[2] + Inst IPL_D0_0_0_ IPL_D0_0[0] + Inst IPL_D0_0_1_ IPL_D0_0[1] + Inst IPL_D0_0_2_ IPL_D0_0[2] + Inst IPL_030_1_0_ IPL_030_1[0] + Inst FC_0_ FC[0] + Inst IPL_030_1_1_ IPL_030_1[1] + Inst FC_1_ FC[1] + Inst pos_clk_cpu_est_11_0_0_i_1_ pos_clk.cpu_est_11_0_0_i[1] + Inst IPL_030_1_2_ IPL_030_1[2] + Inst un1_RST_DLY_i_m_i_3_ un1_RST_DLY_i_m_i[3] + Inst SIZE_DMA_0_0__r SIZE_DMA_0_0_.r + Inst un1_RST_DLY_i_m_i_4_ un1_RST_DLY_i_m_i[4] + Inst SIZE_DMA_0_0__m SIZE_DMA_0_0_.m + Inst un1_RST_DLY_i_m_i_5_ un1_RST_DLY_i_m_i[5] + Inst SIZE_DMA_0_0__n SIZE_DMA_0_0_.n + Inst SIZE_DMA_0_0__p SIZE_DMA_0_0_.p + Inst un1_RST_DLY_i_3_ un1_RST_DLY_i[3] + Inst SIZE_DMA_0_1__r SIZE_DMA_0_1_.r + Inst pos_clk_cpu_est_11_0_0_3_ pos_clk.cpu_est_11_0_0[3] + Inst un1_RST_DLY_i_m_3_ un1_RST_DLY_i_m[3] + Inst SIZE_DMA_0_1__m SIZE_DMA_0_1_.m + Inst SIZE_DMA_0_1__n SIZE_DMA_0_1_.n + Inst SIZE_DMA_0_1__p SIZE_DMA_0_1_.p + Inst IPL_030_0_0__r IPL_030_0_0_.r + Inst IPL_030_0_0__m IPL_030_0_0_.m + Inst pos_clk_CYCLE_DMA_5_1_i_1 pos_clk.CYCLE_DMA_5_1_i_1 + Inst IPL_030_0_0__n IPL_030_0_0_.n + Inst pos_clk_CYCLE_DMA_5_1_i pos_clk.CYCLE_DMA_5_1_i + Inst IPL_030_0_0__p IPL_030_0_0_.p + Inst pos_clk_CYCLE_DMA_5_0_i_1 pos_clk.CYCLE_DMA_5_0_i_1 + Inst IPL_030_0_1__r IPL_030_0_1_.r + Inst pos_clk_CYCLE_DMA_5_0_i pos_clk.CYCLE_DMA_5_0_i + Inst IPL_030_0_1__m IPL_030_0_1_.m + Inst IPL_030_0_1__n IPL_030_0_1_.n + Inst IPL_030_0_1__p IPL_030_0_1_.p + Inst pos_clk_cpu_est_11_i_0_a2_1_2_ pos_clk.cpu_est_11_i_0_a2_1[2] + Inst IPL_030_0_2__r IPL_030_0_2_.r + Inst pos_clk_cpu_est_11_i_0_a2_2_ pos_clk.cpu_est_11_i_0_a2[2] + Inst pos_clk_RST_DLY_5_iv_6_ pos_clk.RST_DLY_5_iv[6] + Inst IPL_030_0_2__m IPL_030_0_2_.m + Inst pos_clk_cpu_est_11_i_0_a2_0_1_2_ pos_clk.cpu_est_11_i_0_a2_0_1[2] + Inst un1_RST_DLY_i_7_ un1_RST_DLY_i[7] + Inst IPL_030_0_2__n IPL_030_0_2_.n + Inst pos_clk_cpu_est_11_i_0_a2_0_2_ pos_clk.cpu_est_11_i_0_a2_0[2] + Inst un1_RST_DLY_i_m_7_ un1_RST_DLY_i_m[7] + Inst IPL_030_0_2__p IPL_030_0_2_.p + Inst pos_clk_RST_DLY_5_iv_5_ pos_clk.RST_DLY_5_iv[5] + Inst un1_RST_DLY_i_6_ un1_RST_DLY_i[6] + Inst AMIGA_BUS_ENABLE_DMA_HIGH_0_r AMIGA_BUS_ENABLE_DMA_HIGH_0.r + Inst SM_AMIGA_srsts_i_0_1_6_ SM_AMIGA_srsts_i_0_1[6] + Inst un1_RST_DLY_i_m_6_ un1_RST_DLY_i_m[6] + Inst AMIGA_BUS_ENABLE_DMA_HIGH_0_m AMIGA_BUS_ENABLE_DMA_HIGH_0.m + Inst SM_AMIGA_srsts_i_0_6_ SM_AMIGA_srsts_i_0[6] + Inst pos_clk_RST_DLY_5_iv_4_ pos_clk.RST_DLY_5_iv[4] + Inst AMIGA_BUS_ENABLE_DMA_HIGH_0_n AMIGA_BUS_ENABLE_DMA_HIGH_0.n + Inst SM_AMIGA_srsts_i_0_1_4_ SM_AMIGA_srsts_i_0_1[4] + Inst un1_RST_DLY_i_5_ un1_RST_DLY_i[5] + Inst AMIGA_BUS_ENABLE_DMA_HIGH_0_p AMIGA_BUS_ENABLE_DMA_HIGH_0.p + Inst SM_AMIGA_srsts_i_0_4_ SM_AMIGA_srsts_i_0[4] + Inst un1_RST_DLY_i_m_5_ un1_RST_DLY_i_m[5] + Inst BG_000_0_r BG_000_0.r + Inst SM_AMIGA_srsts_i_0_1_3_ SM_AMIGA_srsts_i_0_1[3] + Inst pos_clk_RST_DLY_5_iv_3_ pos_clk.RST_DLY_5_iv[3] + Inst BG_000_0_m BG_000_0.m + Inst SM_AMIGA_srsts_i_0_3_ SM_AMIGA_srsts_i_0[3] + Inst un1_RST_DLY_i_4_ un1_RST_DLY_i[4] + Inst BG_000_0_n BG_000_0.n + Inst un1_RST_DLY_i_m_4_ un1_RST_DLY_i_m[4] + Inst BG_000_0_p BG_000_0.p + Inst pos_clk_RST_DLY_5_iv_2_ pos_clk.RST_DLY_5_iv[2] + Inst pos_clk_cpu_est_11_0_0_1_3_ pos_clk.cpu_est_11_0_0_1[3] + Inst pos_clk_RST_DLY_5_iv_0_a2_0_ pos_clk.RST_DLY_5_iv_0_a2[0] + Inst un1_RST_DLY_i_2_ un1_RST_DLY_i[2] + Inst SM_AMIGA_nss_i_i_0_a2_1_0_0_ SM_AMIGA_nss_i_i_0_a2_1_0[0] + Inst un1_RST_DLY_i_m_2_ un1_RST_DLY_i_m[2] + Inst SM_AMIGA_nss_i_i_0_a2_0_ SM_AMIGA_nss_i_i_0_a2[0] + Inst pos_clk_RST_DLY_5_iv_1_ pos_clk.RST_DLY_5_iv[1] + Inst SM_AMIGA_nss_i_i_0_a2_0_1_0_ SM_AMIGA_nss_i_i_0_a2_0_1[0] + Inst un1_RST_DLY_i_8_ un1_RST_DLY_i[8] + Inst SM_AMIGA_nss_i_i_0_a2_0_0_ SM_AMIGA_nss_i_i_0_a2_0[0] + Inst un1_RST_DLY_i_m_8_ un1_RST_DLY_i_m[8] + Inst SM_AMIGA_srsts_i_0_1_1_ SM_AMIGA_srsts_i_0_1[1] + Inst pos_clk_RST_DLY_5_iv_7_ pos_clk.RST_DLY_5_iv[7] + Inst SM_AMIGA_srsts_i_0_1_ SM_AMIGA_srsts_i_0[1] + Inst SM_AMIGA_srsts_i_i_a2_1_0_2_ SM_AMIGA_srsts_i_i_a2_1_0[2] + Inst SM_AMIGA_srsts_i_i_a2_2_ SM_AMIGA_srsts_i_i_a2[2] + Inst SM_AMIGA_srsts_i_i_a2_0_1_2_ SM_AMIGA_srsts_i_i_a2_0_1[2] + Inst DS_000_DMA_0_r DS_000_DMA_0.r + Inst SM_AMIGA_srsts_i_i_a2_0_2_ SM_AMIGA_srsts_i_i_a2_0[2] + Inst DS_000_DMA_0_m DS_000_DMA_0.m + Inst pos_clk_cpu_est_11_0_0_a2_1_1_3_ pos_clk.cpu_est_11_0_0_a2_1_1[3] + Inst DS_000_DMA_0_n DS_000_DMA_0.n + Inst pos_clk_cpu_est_11_0_0_a2_1_3_ pos_clk.cpu_est_11_0_0_a2_1[3] + Inst cpu_est_0_3__r cpu_est_0_3_.r + Inst DS_000_DMA_0_p DS_000_DMA_0.p + Inst pos_clk_cpu_est_11_0_0_1_ pos_clk.cpu_est_11_0_0[1] + Inst cpu_est_0_3__m cpu_est_0_3_.m + Inst AS_000_DMA_0_r AS_000_DMA_0.r + Inst SM_AMIGA_srsts_i_i_a2_2_1_2_ SM_AMIGA_srsts_i_i_a2_2_1[2] + Inst cpu_est_0_3__n cpu_est_0_3_.n + Inst AS_000_DMA_0_m AS_000_DMA_0.m + Inst SM_AMIGA_srsts_i_i_a2_2_2_2_ SM_AMIGA_srsts_i_i_a2_2_2[2] + Inst cpu_est_0_3__p cpu_est_0_3_.p + Inst AS_000_DMA_0_n AS_000_DMA_0.n + Inst SM_AMIGA_srsts_i_i_a2_2_3_2_ SM_AMIGA_srsts_i_i_a2_2_3[2] + Inst cpu_est_0_2__r cpu_est_0_2_.r + Inst AS_000_DMA_0_p AS_000_DMA_0.p + Inst SM_AMIGA_srsts_i_i_a2_2_4_2_ SM_AMIGA_srsts_i_i_a2_2_4[2] + Inst cpu_est_0_2__m cpu_est_0_2_.m + Inst A0_DMA_0_r A0_DMA_0.r + Inst SM_AMIGA_srsts_i_i_a2_2_2_ SM_AMIGA_srsts_i_i_a2_2[2] + Inst cpu_est_0_2__n cpu_est_0_2_.n + Inst A0_DMA_0_m A0_DMA_0.m + Inst pos_clk_un7_clk_000_pe_0_a2_0_1 pos_clk.un7_clk_000_pe_0_a2_0_1 + Inst cpu_est_0_2__p cpu_est_0_2_.p + Inst A0_DMA_0_n A0_DMA_0.n + Inst pos_clk_un7_clk_000_pe_0_a2_0_2 pos_clk.un7_clk_000_pe_0_a2_0_2 + Inst cpu_est_0_1__r cpu_est_0_1_.r + Inst A0_DMA_0_p A0_DMA_0.p + Inst pos_clk_un7_clk_000_pe_0_a2_0 pos_clk.un7_clk_000_pe_0_a2_0 + Inst cpu_est_0_1__m cpu_est_0_1_.m + Inst pos_clk_un7_clk_000_pe_0_a2_1 pos_clk.un7_clk_000_pe_0_a2_1 + Inst cpu_est_0_1__n cpu_est_0_1_.n + Inst DSACK1_INT_0_r DSACK1_INT_0.r + Inst pos_clk_un7_clk_000_pe_0_a2_2 pos_clk.un7_clk_000_pe_0_a2_2 + Inst cpu_est_0_1__p cpu_est_0_1_.p + Inst DSACK1_INT_0_m DSACK1_INT_0.m + Net un1_rst_dly_i_m_i_5__n un1_RST_DLY_i_m_i[5] + Net sm_amiga_srsts_i_0_m2_3__un0_n SM_AMIGA_srsts_i_0_m2_3_.un0 + Net pos_clk_rst_dly_5_iv_i_4__n pos_clk.RST_DLY_5_iv_i[4] + Net sm_amiga_srsts_i_0_m2_1__un3_n SM_AMIGA_srsts_i_0_m2_1_.un3 + Net pos_clk_cpu_est_11_1__n pos_clk.cpu_est_11[1] + Net un1_rst_dly_i_m_i_6__n un1_RST_DLY_i_m_i[6] + Net sm_amiga_srsts_i_0_m2_1__un1_n SM_AMIGA_srsts_i_0_m2_1_.un1 + Net pos_clk_rst_dly_5_iv_i_5__n pos_clk.RST_DLY_5_iv_i[5] + Net sm_amiga_srsts_i_0_m2_1__un0_n SM_AMIGA_srsts_i_0_m2_1_.un0 + Net un1_rst_dly_i_m_i_7__n un1_RST_DLY_i_m_i[7] + Net un1_amiga_bus_enable_dma_high_0_m2_0__un3_n un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0_.un3 + Net pos_clk_rst_dly_5_iv_i_6__n pos_clk.RST_DLY_5_iv_i[6] + Net un1_amiga_bus_enable_dma_high_0_m2_0__un1_n un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0_.un1 + Net un1_rst_dly_i_m_i_8__n un1_RST_DLY_i_m_i[8] + Net un1_amiga_bus_enable_dma_high_0_m2_0__un0_n un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0_.un0 + Net vcc_n_n VCC + Net pos_clk_rst_dly_5_iv_i_7__n pos_clk.RST_DLY_5_iv_i[7] + Net un1_sm_amiga_7_i_m2_un3_n un1_SM_AMIGA_7_i_m2.un3 + Net cpu_est_3__n cpu_est[3] + Net un1_rst_dly_i_m_i_2__n un1_RST_DLY_i_m_i[2] + Net un1_sm_amiga_7_i_m2_un1_n un1_SM_AMIGA_7_i_m2.un1 + Net pos_clk_rst_dly_5_iv_i_1__n pos_clk.RST_DLY_5_iv_i[1] + Net un1_sm_amiga_7_i_m2_un0_n un1_SM_AMIGA_7_i_m2.un0 + Net size_dma_0_0__un3_n SIZE_DMA_0_0_.un3 + Net gnd_n_n GND + Net pos_clk_rst_dly_5_iv_i_0__n pos_clk.RST_DLY_5_iv_i[0] + Net size_dma_0_0__un1_n SIZE_DMA_0_0_.un1 + Net size_dma_0_0__un0_n SIZE_DMA_0_0_.un0 + Net un1_rst_dly_i_m_2__n un1_RST_DLY_i_m[2] + Net size_dma_0_1__un3_n SIZE_DMA_0_1_.un3 + Net un1_rst_dly_2__n un1_RST_DLY[2] + Net size_dma_0_1__un1_n SIZE_DMA_0_1_.un1 + Net un1_rst_dly_i_m_8__n un1_RST_DLY_i_m[8] + Net size_dma_0_1__un0_n SIZE_DMA_0_1_.un0 + Net un1_rst_dly_8__n un1_RST_DLY[8] + Net ipl_030_0_0__un3_n IPL_030_0_0_.un3 + Net ipl_030_0_0__un1_n IPL_030_0_0_.un1 + Net ipl_030_0_0__un0_n IPL_030_0_0_.un0 + Net un1_rst_dly_7__n un1_RST_DLY[7] + Net ipl_030_0_1__un3_n IPL_030_0_1_.un3 + Net un1_rst_dly_6__n un1_RST_DLY[6] + Net ipl_030_0_1__un1_n IPL_030_0_1_.un1 + Net ipl_030_0_1__un0_n IPL_030_0_1_.un0 + Net un1_rst_dly_5__n un1_RST_DLY[5] + Net pos_clk_cpu_est_11_0_1__n pos_clk.cpu_est_11_0[1] + Net ipl_030_0_2__un3_n IPL_030_0_2_.un3 + Net cpu_est_0__n cpu_est[0] + Net ipl_030_0_2__un1_n IPL_030_0_2_.un1 + Net cpu_est_1__n cpu_est[1] + Net un1_rst_dly_4__n un1_RST_DLY[4] + Net ipl_030_0_2__un0_n IPL_030_0_2_.un0 + Net un1_rst_dly_3__n un1_RST_DLY[3] + Net amiga_bus_enable_dma_high_0_un3_n AMIGA_BUS_ENABLE_DMA_HIGH_0.un3 + Net sm_amiga_5__n SM_AMIGA[5] + Net un1_rst_dly_i_m_7__n un1_RST_DLY_i_m[7] + Net amiga_bus_enable_dma_high_0_un1_n AMIGA_BUS_ENABLE_DMA_HIGH_0.un1 + Net un1_rst_dly_i_m_6__n un1_RST_DLY_i_m[6] + Net amiga_bus_enable_dma_high_0_un0_n AMIGA_BUS_ENABLE_DMA_HIGH_0.un0 + Net un1_rst_dly_i_m_5__n un1_RST_DLY_i_m[5] + Net bg_000_0_un3_n BG_000_0.un3 + Net un1_rst_dly_i_m_4__n un1_RST_DLY_i_m[4] + Net bg_000_0_un1_n BG_000_0.un1 + Net un1_rst_dly_i_m_3__n un1_RST_DLY_i_m[3] + Net bg_000_0_un0_n BG_000_0.un0 + Net ds_000_dma_0_un3_n DS_000_DMA_0.un3 + Net ds_000_dma_0_un1_n DS_000_DMA_0.un1 + Net ds_000_dma_0_un0_n DS_000_DMA_0.un0 + Net as_000_dma_0_un3_n AS_000_DMA_0.un3 + Net cycle_dma_0__n CYCLE_DMA[0] + Net as_000_dma_0_un1_n AS_000_DMA_0.un1 + Net cycle_dma_1__n CYCLE_DMA[1] + Net as_000_dma_0_un0_n AS_000_DMA_0.un0 + Net size_dma_0__n SIZE_DMA[0] + Net un1_rst_dly_i_3__n un1_RST_DLY_i[3] + Net a0_dma_0_un3_n A0_DMA_0.un3 + Net size_dma_1__n SIZE_DMA[1] + Net un1_rst_dly_i_4__n un1_RST_DLY_i[4] + Net pos_clk_un7_clk_000_pe_0_n pos_clk.un7_clk_000_pe_0 + Net a0_dma_0_un1_n A0_DMA_0.un1 + Net un1_rst_dly_i_5__n un1_RST_DLY_i[5] + Net a0_dma_0_un0_n A0_DMA_0.un0 + Net un1_rst_dly_i_6__n un1_RST_DLY_i[6] + Net dsack1_int_0_un3_n DSACK1_INT_0.un3 + Net un1_rst_dly_i_7__n un1_RST_DLY_i[7] + Net dsack1_int_0_un1_n DSACK1_INT_0.un1 + Net un1_rst_dly_i_8__n un1_RST_DLY_i[8] + Net dsack1_int_0_un0_n DSACK1_INT_0.un0 + Net un1_rst_dly_i_2__n un1_RST_DLY_i[2] + Net as_000_int_0_un3_n AS_000_INT_0.un3 + Net as_000_int_0_un1_n AS_000_INT_0.un1 + Net cpu_est_i_3__n cpu_est_i[3] + Net as_000_int_0_un0_n AS_000_INT_0.un0 + Net cpu_est_i_0__n cpu_est_i[0] + Net ds_000_enable_0_un3_n DS_000_ENABLE_0.un3 + Net ds_000_enable_0_un1_n DS_000_ENABLE_0.un1 + Net clk_000_p_sync_9__n CLK_000_P_SYNC[9] + Net ds_000_enable_0_un0_n DS_000_ENABLE_0.un0 + Net cpu_est_i_1__n cpu_est_i[1] + Net as_030_000_sync_0_un3_n AS_030_000_SYNC_0.un3 + Net clk_000_n_sync_11__n CLK_000_N_SYNC[11] + Net as_030_000_sync_0_un1_n AS_030_000_SYNC_0.un1 + Net cpu_est_2__n cpu_est[2] + Net as_030_000_sync_0_un0_n AS_030_000_SYNC_0.un0 + Net ipl_d0_0__n IPL_D0[0] + Net sm_amiga_i_4__n SM_AMIGA_i[4] + Net lds_000_int_0_un3_n LDS_000_INT_0.un3 + Net ipl_d0_1__n IPL_D0[1] + Net cpu_est_i_2__n cpu_est_i[2] + Net lds_000_int_0_un1_n LDS_000_INT_0.un1 + Net ipl_d0_2__n IPL_D0[2] + Net sm_amiga_i_5__n SM_AMIGA_i[5] + Net lds_000_int_0_un0_n LDS_000_INT_0.un0 + Net sm_amiga_3__n SM_AMIGA[3] + Net rw_000_dma_0_un3_n RW_000_DMA_0.un3 + Net sm_amiga_i_0__n SM_AMIGA_i[0] + Net rw_000_dma_0_un1_n RW_000_DMA_0.un1 + Net pos_clk_un6_bg_030_n pos_clk.un6_bg_030 + Net sm_amiga_i_3__n SM_AMIGA_i[3] + Net rw_000_dma_0_un0_n RW_000_DMA_0.un0 + Net sm_amiga_0__n SM_AMIGA[0] + Net uds_000_int_0_un3_n UDS_000_INT_0.un3 + Net sm_amiga_i_6__n SM_AMIGA_i[6] + Net uds_000_int_0_un1_n UDS_000_INT_0.un1 + Net sm_amiga_i_1__n SM_AMIGA_i[1] + Net clk_000_n_sync_i_10__n CLK_000_N_SYNC_i[10] + Net uds_000_int_0_un0_n UDS_000_INT_0.un0 + Net pos_clk_clk_000_p_sync_2_0__n pos_clk.CLK_000_P_SYNC_2[0] + Net pos_clk_un9_clk_000_n_sync_i_n pos_clk.un9_clk_000_n_sync_i + Net amiga_bus_enable_dma_low_0_un3_n AMIGA_BUS_ENABLE_DMA_LOW_0.un3 + Net pos_clk_ipl_n pos_clk.ipl + Net pos_clk_un11_clk_000_n_sync_i_n pos_clk.un11_clk_000_n_sync_i + Net pos_clk_un14_clk_000_n_sync_0_n pos_clk.un14_clk_000_n_sync_0 + Net amiga_bus_enable_dma_low_0_un1_n AMIGA_BUS_ENABLE_DMA_LOW_0.un1 + Net pos_clk_un3_ds_030_d0_n pos_clk.un3_ds_030_d0 + Net pos_clk_un22_bgack_030_int_i_n pos_clk.un22_bgack_030_int_i + Net amiga_bus_enable_dma_low_0_un0_n AMIGA_BUS_ENABLE_DMA_LOW_0.un0 + Net sm_amiga_6__n SM_AMIGA[6] + Net a_15__n A[15] + Net rst_dly_0__n RST_DLY[0] + Net sm_amiga_i_2__n SM_AMIGA_i[2] + Net a_14__n A[14] + Net rst_dly_1__n RST_DLY[1] + Net rst_dly_2__n RST_DLY[2] + Net pos_clk_size_dma_6_0_1__n pos_clk.SIZE_DMA_6_0[1] + Net a_13__n A[13] + Net rst_dly_3__n RST_DLY[3] + Net rst_dly_4__n RST_DLY[4] + Net pos_clk_size_dma_6_0_0__n pos_clk.SIZE_DMA_6_0[0] + Net a_12__n A[12] + Net rst_dly_5__n RST_DLY[5] + Net rst_dly_6__n RST_DLY[6] + Net a_11__n A[11] + Net rst_dly_7__n RST_DLY[7] + Net pos_clk_un8_bg_030_n pos_clk.un8_bg_030 + Net sm_amiga_i_i_7__n SM_AMIGA_i_i[7] + Net a_10__n A[10] + Net clk_000_p_sync_0__n CLK_000_P_SYNC[0] + Net clk_000_p_sync_1__n CLK_000_P_SYNC[1] + Net a_9__n A[9] + Net clk_000_p_sync_2__n CLK_000_P_SYNC[2] + Net clk_000_p_sync_3__n CLK_000_P_SYNC[3] + Net a_8__n A[8] + Net clk_000_p_sync_4__n CLK_000_P_SYNC[4] + Net a_i_24__n A_i[24] + Net clk_000_p_sync_5__n CLK_000_P_SYNC[5] + Net size_dma_i_0__n SIZE_DMA_i[0] + Net a_7__n A[7] + Net clk_000_p_sync_6__n CLK_000_P_SYNC[6] + Net size_dma_i_1__n SIZE_DMA_i[1] + Net clk_000_p_sync_7__n CLK_000_P_SYNC[7] + Net a_i_16__n A_i[16] + Net pos_clk_un3_as_030_d0_i_n pos_clk.un3_as_030_d0_i + Net a_6__n A[6] + Net clk_000_p_sync_8__n CLK_000_P_SYNC[8] + Net a_i_18__n A_i[18] + Net pos_clk_un5_bgack_030_int_d_i_n pos_clk.un5_bgack_030_int_d_i + Net clk_000_n_sync_0__n CLK_000_N_SYNC[0] + Net a_i_19__n A_i[19] + Net a_5__n A[5] + Net clk_000_n_sync_1__n CLK_000_N_SYNC[1] + Net a_i_31__n A_i[31] + Net clk_000_n_sync_2__n CLK_000_N_SYNC[2] + Net a_i_29__n A_i[29] + Net a_4__n A[4] + Net clk_000_n_sync_3__n CLK_000_N_SYNC[3] + Net a_i_30__n A_i[30] + Net clk_000_n_sync_4__n CLK_000_N_SYNC[4] + Net a_i_27__n A_i[27] + Net a_3__n A[3] + Net clk_000_n_sync_5__n CLK_000_N_SYNC[5] + Net a_i_28__n A_i[28] + Net clk_000_n_sync_6__n CLK_000_N_SYNC[6] + Net a_i_25__n A_i[25] + Net a_2__n A[2] + Net clk_000_n_sync_7__n CLK_000_N_SYNC[7] + Net a_i_26__n A_i[26] + Net clk_000_n_sync_8__n CLK_000_N_SYNC[8] + Net clk_000_n_sync_9__n CLK_000_N_SYNC[9] + Net clk_000_n_sync_10__n CLK_000_N_SYNC[10] + Net pos_clk_un5_bgack_030_int_d_n pos_clk.un5_bgack_030_int_d + Net sm_amiga_1__n SM_AMIGA[1] + Net sm_amiga_4__n SM_AMIGA[4] + Net sm_amiga_2__n SM_AMIGA[2] + Net pos_clk_un3_as_030_d0_n pos_clk.un3_as_030_d0 + Net pos_clk_a0_dma_3_n pos_clk.A0_DMA_3 + Net pos_clk_cpu_est_11_0_3__n pos_clk.cpu_est_11_0[3] + Net pos_clk_ds_000_dma_4_n pos_clk.DS_000_DMA_4 + Net pos_clk_ds_000_dma_4_0_n pos_clk.DS_000_DMA_4_0 + Net pos_clk_un24_bgack_030_int_i_0_i_n pos_clk.un24_bgack_030_int_i_0_i + Net size_c_0__n SIZE_c[0] + Net size_0__n SIZE[0] + Net size_c_1__n SIZE_c[1] + Net pos_clk_un11_ds_030_d0_i_n pos_clk.un11_ds_030_d0_i + Net size_c_i_1__n SIZE_c_i[1] + Net ipl_c_i_2__n IPL_c_i[2] + Net ipl_c_i_1__n IPL_c_i[1] + Net ipl_c_i_0__n IPL_c_i[0] + Net sm_amiga_i_7__n SM_AMIGA_i[7] + Net pos_clk_size_dma_6_0__n pos_clk.SIZE_DMA_6[0] + Net a_c_16__n A_c[16] + Net pos_clk_size_dma_6_1__n pos_clk.SIZE_DMA_6[1] + Net a_16__n A[16] + Net pos_clk_cpu_est_11_3__n pos_clk.cpu_est_11[3] + Net a_c_17__n A_c[17] + Net a_17__n A[17] + Net a_c_18__n A_c[18] + Net a_18__n A[18] + Net a_c_19__n A_c[19] + Net pos_clk_un24_bgack_030_int_i_0_n pos_clk.un24_bgack_030_int_i_0 + Net a_19__n A[19] + Net a_c_20__n A_c[20] + Net a_20__n A[20] + Net a_c_21__n A_c[21] + Net a_21__n A[21] + Net a_c_22__n A_c[22] + Net pos_clk_un6_bg_030_i_n pos_clk.un6_bg_030_i + Net a_22__n A[22] + Net pos_clk_un8_bg_030_0_n pos_clk.un8_bg_030_0 + Net a_c_23__n A_c[23] + Net a_23__n A[23] + Net a_c_24__n A_c[24] + Net pos_clk_un24_bgack_030_int_i_0_i_1_n pos_clk.un24_bgack_030_int_i_0_i_1 + Net a_24__n A[24] + Net a_c_25__n A_c[25] + Net a_25__n A[25] + Net a_c_26__n A_c[26] + Net pos_clk_un11_ds_030_d0_i_1_n pos_clk.un11_ds_030_d0_i_1 + Net a_26__n A[26] + Net a_c_27__n A_c[27] + Net a_27__n A[27] + Net a_c_28__n A_c[28] + Net a_28__n A[28] + Net pos_clk_un11_clk_000_n_sync_n pos_clk.un11_clk_000_n_sync + Net a_c_29__n A_c[29] + Net a_29__n A[29] + Net a_c_30__n A_c[30] + Net a_30__n A[30] + Net a_c_31__n A_c[31] + Net pos_clk_un22_bgack_030_int_n pos_clk.un22_bgack_030_int + Net pos_clk_un6_bg_030_1_n pos_clk.un6_bg_030_1 + Net pos_clk_cpu_est_11_0_1_1__n pos_clk.cpu_est_11_0_1[1] + Net pos_clk_cpu_est_11_0_2_1__n pos_clk.cpu_est_11_0_2[1] + Net ipl_030_c_0__n IPL_030_c[0] + Net ipl_030_0__n IPL_030[0] + Net ipl_030_c_1__n IPL_030_c[1] + Net ipl_030_1__n IPL_030[1] + Net ipl_030_c_2__n IPL_030_c[2] + Net ipl_c_0__n IPL_c[0] + Net ipl_0__n IPL[0] + Net ipl_c_1__n IPL_c[1] + Net ipl_1__n IPL[1] + Net ipl_c_2__n IPL_c[2] + Net pos_clk_cpu_est_11_0_1_3__n pos_clk.cpu_est_11_0_1[3] + Net pos_clk_un14_clk_000_n_sync_n pos_clk.un14_clk_000_n_sync + Net pos_clk_un9_clk_000_n_sync_n pos_clk.un9_clk_000_n_sync + Net pos_clk_ipl_1_n pos_clk.ipl_1 + Net cpu_est_0_3__un3_n cpu_est_0_3_.un3 + Net cpu_est_0_3__un1_n cpu_est_0_3_.un1 + Net cpu_est_0_3__un0_n cpu_est_0_3_.un0 + Net cpu_est_0_2__un3_n cpu_est_0_2_.un3 + Net cpu_est_0_2__un1_n cpu_est_0_2_.un1 + Net fc_c_0__n FC_c[0] + Net cpu_est_0_2__un0_n cpu_est_0_2_.un0 + Net fc_0__n FC[0] + Net cpu_est_0_1__un3_n cpu_est_0_1_.un3 + Net fc_c_1__n FC_c[1] + Net cpu_est_0_1__un1_n cpu_est_0_1_.un1 + Net cpu_est_0_1__un0_n cpu_est_0_1_.un0 + Net bgack_030_int_0_un3_n BGACK_030_INT_0.un3 + Net bgack_030_int_0_un1_n BGACK_030_INT_0.un1 + Net bgack_030_int_0_un0_n BGACK_030_INT_0.un0 + Net vma_int_0_un3_n VMA_INT_0.un3 + Net vma_int_0_un1_n VMA_INT_0.un1 + Net vma_int_0_un0_n VMA_INT_0.un0 + Net rw_000_int_0_un3_n RW_000_INT_0.un3 + Net un1_rst_dly_i_m_i_3__n un1_RST_DLY_i_m_i[3] + Net rw_000_int_0_un1_n RW_000_INT_0.un1 + Net pos_clk_un7_clk_000_pe_n pos_clk.un7_clk_000_pe + Net pos_clk_rst_dly_5_iv_i_2__n pos_clk.RST_DLY_5_iv_i[2] + Net rw_000_int_0_un0_n RW_000_INT_0.un0 + Net un1_rst_dly_i_m_i_4__n un1_RST_DLY_i_m_i[4] + Net sm_amiga_srsts_i_0_m2_3__un3_n SM_AMIGA_srsts_i_0_m2_3_.un3 + Net pos_clk_rst_dly_5_iv_i_3__n pos_clk.RST_DLY_5_iv_i[3] + Net sm_amiga_srsts_i_0_m2_3__un1_n SM_AMIGA_srsts_i_0_m2_3_.un1 +End +Section Type Name +// ---------------------------------------------------------------------- + Input A_31_ + Input IPL_2_ + Input FC_1_ + Input A1 + Input nEXP_SPACE + Input BG_030 + Input BGACK_000 + Input CLK_030 + Input CLK_000 + Input CLK_OSZI + Input FPU_SENSE + Input DTACK + Input VPA + Input RST + Input A_30_ + Input A_29_ + Input A_28_ + Input A_27_ + Input A_26_ + Input A_25_ + Input A_24_ + Input A_23_ + Input A_22_ + Input A_21_ + Input A_20_ + Input A_19_ + Input A_18_ + Input A_17_ + Input A_16_ + Input A_15_ + Input A_14_ + Input A_13_ + Input A_12_ + Input A_11_ + Input A_10_ + Input A_9_ + Input A_8_ + Input A_7_ + Input A_6_ + Input A_5_ + Input A_4_ + Input A_3_ + Input A_2_ + Input IPL_1_ + Input IPL_0_ + Input FC_0_ + Output IPL_030_2_ + Output BG_000 + Output BGACK_030 + Output CLK_DIV_OUT + Output CLK_EXP + Output FPU_CS + Output DSACK1 + Output AVEC + Output E + Output VMA + Output RESET + Output AMIGA_ADDR_ENABLE + Output AMIGA_BUS_DATA_DIR + Output AMIGA_BUS_ENABLE_LOW + Output AMIGA_BUS_ENABLE_HIGH + Output CIIN + Output IPL_030_1_ + Output IPL_030_0_ + Bidi SIZE_1_ + Bidi AS_030 + Bidi AS_000 + Bidi RW_000 + Bidi DS_030 + Bidi UDS_000 + Bidi LDS_000 + Bidi A0 + Bidi BERR + Bidi RW + Bidi SIZE_0_ +End diff --git a/Logic/bus68030.srf b/Logic/bus68030.srf index 97fd661..db9301c 100644 --- a/Logic/bus68030.srf +++ b/Logic/bus68030.srf @@ -6,7 +6,7 @@ #Implementation: logic $ Start of Compile -#Sat Mar 28 22:02:40 2015 +#Wed May 13 22:59:14 2015 Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014 @N|Running in 64-bit mode @@ -18,17 +18,19 @@ File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - VHDL syntax check successful! File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling @N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral -@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:7:124:17|Signal clk_out_pre is undriven +@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:7:126:17|Signal clk_out_pre is undriven Post processing for work.bus68030.behavioral -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:37:137:39|Pruning register AMIGA_BUS_ENABLE_INT_4 -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_000_D4_2 -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_000_D3_2 -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:34:129:36|Pruning register CLK_000_D2_2 -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":122:36:122:38|Pruning register CLK_OUT_PRE_50_D_2 -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":152:2:152:3|Pruning register CLK_030_D0_2 -@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:61:133:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ... -@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ... -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:37:137:39|Trying to extract state machine for register SM_AMIGA +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Pruning register AMIGA_BUS_ENABLE_INT_4 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Pruning register CLK_000_D4_2 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_000_D3_2 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_000_D2_2 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:35:127:37|Pruning register CLK_OUT_INT_2 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:36:124:38|Pruning register CLK_OUT_PRE_50_D_2 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":155:2:155:3|Pruning register CLK_030_D0_2 +@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":135:61:135:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ... +@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:34:134:36|Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ... +@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ... +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register SM_AMIGA Extracted state machine for register SM_AMIGA State machine has 8 reachable states with original encodings of: 000 @@ -39,14 +41,14 @@ State machine has 8 reachable states with original encodings of: 101 110 111 -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:37:137:39|Trying to extract state machine for register cpu_est +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register cpu_est @W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":23:1:23:1|Input port bits 15 to 2 of a(31 downto 2) are unused @END -At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB) +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Sat Mar 28 22:02:41 2015 +# Wed May 13 22:59:15 2015 ###########################################################] Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014 @@ -56,6 +58,6 @@ File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs cha At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Sat Mar 28 22:02:43 2015 +# Wed May 13 22:59:16 2015 ###########################################################] diff --git a/Logic/dm/BUS68030_comp.xdm b/Logic/dm/BUS68030_comp.xdm index a695b1d..dcd2adc 100644 --- a/Logic/dm/BUS68030_comp.xdm +++ b/Logic/dm/BUS68030_comp.xdm @@ -28,9 +28,13 @@ SRSqSSqSSqSS -S -SR"/ +/>SqS"/ + +SRSqS + + + /S<7>CV ]sC diff --git a/Logic/run_options.txt b/Logic/run_options.txt index 7e650e5..8e81509 100644 --- a/Logic/run_options.txt +++ b/Logic/run_options.txt @@ -1,7 +1,7 @@ #-- Synopsys, Inc. #-- Version I-2014.03LC #-- Project file C:\users\matze\documents\github\68030tk\logic\run_options.txt -#-- Written on Sat Mar 28 22:02:40 2015 +#-- Written on Wed May 13 22:59:14 2015 #project files diff --git a/Logic/syndos.env b/Logic/syndos.env new file mode 100644 index 0000000..dab14eb --- /dev/null +++ b/Logic/syndos.env @@ -0,0 +1,39 @@ +ABEL5DEV=C:\ispLever\ispcpld\lib5 +DIOEDA_ABEL5DEV=C:\ispLever\ispcpld\lib5 +DIOEDA_ActiveHDL=C:\ispLever\active-hdl\BIN +DIOEDA_ActiveHDLPath=C:\ispLever\active-hdl\BIN +DIOEDA_AppNotes=C:\ispLever\ispcpld\bin +DIOEDA_Bin=C:\ispLever\ispcpld\bin +DIOEDA_Config=C:\ispLever\ispcpld\config +DIOEDA_CONTEXT=ispLEVER CLASSIC +DIOEDA_DSPPATH=C:\ispLever\ispLeverDSP +DIOEDA_EPICPATH=C:\ispLever\ispfpga\bin\nt +DIOEDA_Examples=C:\ispLever\examples +DIOEDA_FPGABinPath=C:\ispLever\ispfpga\bin\nt +DIOEDA_FPGAPath=C:\ispLever\ispfpga +DIOEDA_HDLExplorer=C:\ispLever\hdle\win32 +DIOEDA_INI=C:\lsc_env +DIOEDA_ispVM=C:\ispLever\ispvmsystem +DIOEDA_ispVMSystem=C:\ispLever\ispvmsystem +DIOEDA_License=C:\ispLever\license +DIOEDA_MachPath=C:\ispLever\ispcpld\bin +DIOEDA_Manuals=C:\ispLever\ispcpld\manuals +DIOEDA_ModelSim=C:\ispLever\modelsim\win32loem +DIOEDA_ModelsimPath=C:\ispLever\modelsim\win32loem +DIOEDA_PDSPath=C:\ispLever\ispcomp +DIOEDA_Precision=C:\isptools\precision +DIOEDA_PrecisionPath=C:\isptools\precision +DIOEDA_ProductName=ispLEVER +DIOEDA_ProductPrefix=SYN +DIOEDA_ProductTitle=ispLEVER +DIOEDA_ProductType=1.8.00.04.29.14_LS_HDL_BASE_PC_N +DIOEDA_ProductVersion=1.8.00.04 +DIOEDA_ProgramFolder=Lattice Semiconductor ispLEVER Classic 1.8 +DIOEDA_Root=C:\ispLever\ispcpld +DIOEDA_Spectrum=C:\isptools\spectrum +DIOEDA_SpectrumPath=C:\isptools\spectrum +DIOEDA_Synplify=C:\ispLever\synpbase +DIOEDA_SynplifyPath=C:\ispLever\synpbase +DIOEDA_Tutorial=C:\ispLever\ispcpld\tutorial +DIOPRODUCT=ispLEVER +PATH=C:\ispLever\ispcpld\bin diff --git a/Logic/synlog/BUS68030_multi_srs_gen.srr b/Logic/synlog/BUS68030_multi_srs_gen.srr index 66337e7..5b8a83e 100644 --- a/Logic/synlog/BUS68030_multi_srs_gen.srr +++ b/Logic/synlog/BUS68030_multi_srs_gen.srr @@ -5,6 +5,6 @@ File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs cha At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Sat Mar 28 22:02:43 2015 +# Wed May 13 22:59:16 2015 ###########################################################] diff --git a/Logic/synlog/bus68030_fpga_mapper.srr b/Logic/synlog/bus68030_fpga_mapper.srr index f9a2ca5..e721902 100644 --- a/Logic/synlog/bus68030_fpga_mapper.srr +++ b/Logic/synlog/bus68030_fpga_mapper.srr @@ -2,6 +2,7 @@ Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014 Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited. Product Version I-2014.03LC @N: MF248 |Running in 64-bit mode. +@W: MO111 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":497:16:497:18|Tristate driver CLK_DIV_OUT_1 on net CLK_DIV_OUT_1 has its enable tied to GND (module BUS68030) Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral)) original code -> new code 000 -> 00000000 @@ -12,21 +13,21 @@ original code -> new code 101 -> 00100001 110 -> 01000001 111 -> 10000001 -@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":187:4:187:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits -@W: BN132 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Removing instance CLK_000_P_SYNC[10], because it is equivalent to instance CLK_000_PE +@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":190:4:190:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits +@W: BN132 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:34:134:36|Removing instance CLK_000_P_SYNC[10], because it is equivalent to instance CLK_000_PE --------------------------------------- Resource Usage Report Simple gate primitives: -DFF 73 uses +DFF 83 uses BI_DIR 11 uses IBUF 46 uses -OBUF 16 uses -BUFTH 2 uses -AND2 270 uses -INV 229 uses -OR2 26 uses -XOR2 4 uses +OBUF 15 uses +BUFTH 3 uses +AND2 303 uses +INV 263 uses +XOR2 15 uses +OR2 28 uses @N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis. @@ -36,6 +37,6 @@ Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Sat Mar 28 22:02:43 2015 +# Wed May 13 22:59:16 2015 ###########################################################] diff --git a/Logic/synlog/report/BUS68030_compiler_errors.txt b/Logic/synlog/report/BUS68030_compiler_errors.txt index 6838051..8305864 100644 --- a/Logic/synlog/report/BUS68030_compiler_errors.txt +++ b/Logic/synlog/report/BUS68030_compiler_errors.txt @@ -1,3 +1,2 @@ -@E: CD255 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":543:65:543:65|No identifier "a2" in scope -@E|Parse errors encountered - exiting +@E: CD395 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":144:53:144:62|Constant width 8 does not match context width 9 diff --git a/Logic/synlog/report/BUS68030_compiler_notes.txt b/Logic/synlog/report/BUS68030_compiler_notes.txt index 06b8af4..9e1730f 100644 --- a/Logic/synlog/report/BUS68030_compiler_notes.txt +++ b/Logic/synlog/report/BUS68030_compiler_notes.txt @@ -2,6 +2,6 @@ @N: CD720 :"C:\ispLever\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns @N:"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Top entity is set to BUS68030. @N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:37:137:39|Trying to extract state machine for register SM_AMIGA -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:37:137:39|Trying to extract state machine for register cpu_est +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register SM_AMIGA +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register cpu_est diff --git a/Logic/synlog/report/BUS68030_compiler_runstatus.xml b/Logic/synlog/report/BUS68030_compiler_runstatus.xml index 517cd1a..a497687 100644 --- a/Logic/synlog/report/BUS68030_compiler_runstatus.xml +++ b/Logic/synlog/report/BUS68030_compiler_runstatus.xml @@ -18,7 +18,7 @@ The file contains the job information from compiler to be displayed as part of t C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_notes.txt - 10 + 12 C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_warnings.txt @@ -35,7 +35,7 @@ The file contains the job information from compiler to be displayed as part of t - - 1427576561 + 1431550755 \ No newline at end of file diff --git a/Logic/synlog/report/BUS68030_compiler_warnings.txt b/Logic/synlog/report/BUS68030_compiler_warnings.txt index 665c44c..e8538f3 100644 --- a/Logic/synlog/report/BUS68030_compiler_warnings.txt +++ b/Logic/synlog/report/BUS68030_compiler_warnings.txt @@ -1,11 +1,13 @@ -@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:7:124:17|Signal clk_out_pre is undriven -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:37:137:39|Pruning register AMIGA_BUS_ENABLE_INT_4 -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_000_D4_2 -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_000_D3_2 -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:34:129:36|Pruning register CLK_000_D2_2 -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":122:36:122:38|Pruning register CLK_OUT_PRE_50_D_2 -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":152:2:152:3|Pruning register CLK_030_D0_2 -@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:61:133:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ... -@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ... +@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:7:126:17|Signal clk_out_pre is undriven +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Pruning register AMIGA_BUS_ENABLE_INT_4 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Pruning register CLK_000_D4_2 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_000_D3_2 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_000_D2_2 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:35:127:37|Pruning register CLK_OUT_INT_2 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:36:124:38|Pruning register CLK_OUT_PRE_50_D_2 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":155:2:155:3|Pruning register CLK_030_D0_2 +@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":135:61:135:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ... +@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:34:134:36|Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ... +@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ... @W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":23:1:23:1|Input port bits 15 to 2 of a(31 downto 2) are unused diff --git a/Logic/synlog/report/BUS68030_fpga_mapper_notes.txt b/Logic/synlog/report/BUS68030_fpga_mapper_notes.txt index 2e16505..9d279dd 100644 --- a/Logic/synlog/report/BUS68030_fpga_mapper_notes.txt +++ b/Logic/synlog/report/BUS68030_fpga_mapper_notes.txt @@ -1,3 +1,3 @@ @N: MF248 |Running in 64-bit mode. -@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":187:4:187:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits +@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":190:4:190:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits @N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis. diff --git a/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml b/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml index 338f393..29b0c54 100644 --- a/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml +++ b/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml @@ -19,7 +19,7 @@ The file contains the job information from mapper to be displayed as part of the -1 +2 C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_fpga_mapper_warnings.txt @@ -40,7 +40,7 @@ The file contains the job information from mapper to be displayed as part of the 105MB -1427576563 +1431550756 diff --git a/Logic/synlog/report/BUS68030_fpga_mapper_warnings.txt b/Logic/synlog/report/BUS68030_fpga_mapper_warnings.txt index ece4fb3..010fdf0 100644 --- a/Logic/synlog/report/BUS68030_fpga_mapper_warnings.txt +++ b/Logic/synlog/report/BUS68030_fpga_mapper_warnings.txt @@ -1 +1,2 @@ -@W: BN132 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Removing instance CLK_000_P_SYNC[10], because it is equivalent to instance CLK_000_PE +@W: MO111 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":497:16:497:18|Tristate driver CLK_DIV_OUT_1 on net CLK_DIV_OUT_1 has its enable tied to GND (module BUS68030) +@W: BN132 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:34:134:36|Removing instance CLK_000_P_SYNC[10], because it is equivalent to instance CLK_000_PE diff --git a/Logic/syntmp/BUS68030_srr.htm b/Logic/syntmp/BUS68030_srr.htm index c2772d9..d76f1ea 100644 --- a/Logic/syntmp/BUS68030_srr.htm +++ b/Logic/syntmp/BUS68030_srr.htm @@ -1,5 +1,5 @@ 
-
+
 #Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014
 #install: C:\ispLever\synpbase
 #OS: Windows 7 6.1
@@ -8,29 +8,31 @@
 #Implementation: logic
 
 $ Start of Compile
-#Sat Mar 28 22:02:40 2015
+#Wed May 13 22:59:14 2015
 
 Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
-@N: :  | Running in 64-bit mode 
+@N: :  | Running in 64-bit mode 
 Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
 
-@N:CD720 : std.vhd(123) | Setting time resolution to ns
-@N: : 68030-68000-bus.vhd(13) | Top entity is set to BUS68030.
+@N:CD720 : std.vhd(123) | Setting time resolution to ns
+@N: : 68030-68000-bus.vhd(13) | Top entity is set to BUS68030.
 File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
 VHDL syntax check successful!
 File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
-@N:CD630 : 68030-68000-bus.vhd(13) | Synthesizing work.bus68030.behavioral 
-@W:CD638 : 68030-68000-bus.vhd(124) | Signal clk_out_pre is undriven 
+@N:CD630 : 68030-68000-bus.vhd(13) | Synthesizing work.bus68030.behavioral 
+@W:CD638 : 68030-68000-bus.vhd(126) | Signal clk_out_pre is undriven 
 Post processing for work.bus68030.behavioral
-@W:CL169 : 68030-68000-bus.vhd(137) | Pruning register AMIGA_BUS_ENABLE_INT_4  
-@W:CL169 : 68030-68000-bus.vhd(131) | Pruning register CLK_000_D4_2  
-@W:CL169 : 68030-68000-bus.vhd(130) | Pruning register CLK_000_D3_2  
-@W:CL169 : 68030-68000-bus.vhd(129) | Pruning register CLK_000_D2_2  
-@W:CL169 : 68030-68000-bus.vhd(122) | Pruning register CLK_OUT_PRE_50_D_2  
-@W:CL169 : 68030-68000-bus.vhd(152) | Pruning register CLK_030_D0_2  
-@W:CL265 : 68030-68000-bus.vhd(133) | Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ... 
-@W:CL271 : 68030-68000-bus.vhd(132) | Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ... 
-@N:CL201 : 68030-68000-bus.vhd(137) | Trying to extract state machine for register SM_AMIGA
+@W:CL169 : 68030-68000-bus.vhd(139) | Pruning register AMIGA_BUS_ENABLE_INT_4  
+@W:CL169 : 68030-68000-bus.vhd(133) | Pruning register CLK_000_D4_2  
+@W:CL169 : 68030-68000-bus.vhd(132) | Pruning register CLK_000_D3_2  
+@W:CL169 : 68030-68000-bus.vhd(131) | Pruning register CLK_000_D2_2  
+@W:CL169 : 68030-68000-bus.vhd(127) | Pruning register CLK_OUT_INT_2  
+@W:CL169 : 68030-68000-bus.vhd(124) | Pruning register CLK_OUT_PRE_50_D_2  
+@W:CL169 : 68030-68000-bus.vhd(155) | Pruning register CLK_030_D0_2  
+@W:CL265 : 68030-68000-bus.vhd(135) | Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ... 
+@W:CL271 : 68030-68000-bus.vhd(134) | Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ... 
+@W:CL189 : 68030-68000-bus.vhd(139) | Register bit BGACK_030_INT_PRE is always 1, optimizing ...
+@N:CL201 : 68030-68000-bus.vhd(139) | Trying to extract state machine for register SM_AMIGA
 Extracted state machine for register SM_AMIGA
 State machine has 8 reachable states with original encodings of:
    000
@@ -41,24 +43,24 @@ State machine has 8 reachable states with original encodings of:
    101
    110
    111
-@N:CL201 : 68030-68000-bus.vhd(137) | Trying to extract state machine for register cpu_est
-@W:CL246 : 68030-68000-bus.vhd(23) | Input port bits 15 to 2 of a(31 downto 2) are unused 
+@N:CL201 : 68030-68000-bus.vhd(139) | Trying to extract state machine for register cpu_est
+@W:CL246 : 68030-68000-bus.vhd(23) | Input port bits 15 to 2 of a(31 downto 2) are unused 
 @END
 
-At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Sat Mar 28 22:02:41 2015
+# Wed May 13 22:59:15 2015
 
 ###########################################################]
 Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
-@N: :  | Running in 64-bit mode 
+@N: :  | Running in 64-bit mode 
 File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs changed - recompiling
 
 At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Sat Mar 28 22:02:43 2015
+# Wed May 13 22:59:16 2015
 
 ###########################################################]
 Map & Optimize Report
@@ -66,7 +68,8 @@ Map & Optimize Report
 Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May  6 2014
 Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
 Product Version I-2014.03LC 
-@N:MF248 :  | Running in 64-bit mode. 
+@N:MF248 :  | Running in 64-bit mode. 
+@W:MO111 : 68030-68000-bus.vhd(497) | Tristate driver CLK_DIV_OUT_1 on net CLK_DIV_OUT_1 has its enable tied to GND (module BUS68030) 
 Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
 original code -> new code
    000 -> 00000000
@@ -77,31 +80,31 @@ original code -> new code
    101 -> 00100001
    110 -> 01000001
    111 -> 10000001
-@N:MO106 : 68030-68000-bus.vhd(187) | Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits 
-@W:BN132 : 68030-68000-bus.vhd(132) | Removing instance CLK_000_P_SYNC[10],  because it is equivalent to instance CLK_000_PE
+@N:MO106 : 68030-68000-bus.vhd(190) | Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits 
+@W:BN132 : 68030-68000-bus.vhd(134) | Removing instance CLK_000_P_SYNC[10],  because it is equivalent to instance CLK_000_PE
 ---------------------------------------
 Resource Usage Report
 
 Simple gate primitives:
-DFF             73 uses
+DFF             83 uses
 BI_DIR          11 uses
 IBUF            46 uses
-OBUF            16 uses
-BUFTH           2 uses
-AND2            270 uses
-INV             229 uses
-OR2             26 uses
-XOR2            4 uses
+OBUF            15 uses
+BUFTH           3 uses
+AND2            303 uses
+INV             263 uses
+XOR2            15 uses
+OR2             28 uses
 
 
-@N:FC100 :  | Timing Report not generated for this device, please use place and route tools for timing analysis. 
+@N:FC100 :  | Timing Report not generated for this device, please use place and route tools for timing analysis. 
 I-2014.03LC 
 Mapper successful!
 
 At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Sat Mar 28 22:02:43 2015
+# Wed May 13 22:59:16 2015
 
 ###########################################################]
 
diff --git a/Logic/syntmp/BUS68030_toc.htm b/Logic/syntmp/BUS68030_toc.htm
index 46a86d6..f50f89c 100644
--- a/Logic/syntmp/BUS68030_toc.htm
+++ b/Logic/syntmp/BUS68030_toc.htm
@@ -16,7 +16,7 @@
 
  • Mapper Report  
 
    • 
-
  • Session Log (22:02 28-Mar)  
+
  • Session Log (22:59 13-May)  
 
      •          
         
    
diff --git a/Logic/syntmp/run_option.xml b/Logic/syntmp/run_option.xml
index 7f6b517..5e86169 100644
--- a/Logic/syntmp/run_option.xml
+++ b/Logic/syntmp/run_option.xml
@@ -3,7 +3,7 @@
   Synopsys, Inc.
   Version I-2014.03LC 
   Project file C:\users\matze\documents\github\68030tk\logic\syntmp\run_option.xml
-  Written on Sat Mar 28 22:02:40 2015
+  Written on Wed May 13 22:59:14 2015
 
 
 --> 
diff --git a/Logic/syntmp/statusReport.html b/Logic/syntmp/statusReport.html
index 0a17d8e..a6eedc5 100644
--- a/Logic/syntmp/statusReport.html
+++ b/Logic/syntmp/statusReport.html
@@ -33,28 +33,28 @@
   
   Compile InputComplete
  6
- 10
+ 12
 0
 -
 0m:01s
 -
-28.03.2015
      22:02:41
+13.05.2015
      22:59:15
  
 
  
   Map & OptimizeComplete
  3
- 1
+ 2
 0
 0m:00s
 0m:00s
 105MB
-28.03.2015
      22:02:43
+13.05.2015
      22:59:16
  
 
 
   Multi-srs Generator
-  Complete0m:01s28.03.2015
      22:02:43 		
+  Complete0m:00s13.05.2015
      22:59:16 		
      
   
  
\ No newline at end of file
diff --git a/Logic/synwork/BUS68030_comp.fdep b/Logic/synwork/BUS68030_comp.fdep
index 55a88ef..ab9335c 100644
--- a/Logic/synwork/BUS68030_comp.fdep
+++ b/Logic/synwork/BUS68030_comp.fdep
@@ -1,15 +1,15 @@
 #defaultlanguage:vhdl
 #OPTIONS:"|-top|BUS68030|-prodtype|synplify_pro|-nostructver|-dfltencoding|sequential|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
-#CUR:"C:\\ispLever\\synpbase\\bin64\\c_vhdl.exe":1401224104
-#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\location.map":1310457374
-#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\std.vhd":1401223722
-#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\snps_haps_pkg.vhd":1401223722
-#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\std1164.vhd":1401223722
-#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\numeric.vhd":1401223722
-#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1401223968
-#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1401223722
-#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1401223722
-#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1427576546
+#CUR:"C:\\ispLever\\synpbase\\bin64\\c_vhdl.exe":1401227704
+#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\location.map":1310460974
+#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\std.vhd":1401227322
+#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\snps_haps_pkg.vhd":1401227322
+#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\std1164.vhd":1401227322
+#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\numeric.vhd":1401227322
+#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1401227568
+#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1401227322
+#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1401227322
+#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1431550739
 0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
 
 # Dependency Lists (Uses list)
diff --git a/Logic/synwork/BUS68030_comp.fdeporig b/Logic/synwork/BUS68030_comp.fdeporig
index 8ff6dce..f759e8e 100644
--- a/Logic/synwork/BUS68030_comp.fdeporig
+++ b/Logic/synwork/BUS68030_comp.fdeporig
@@ -1,15 +1,15 @@
 #defaultlanguage:vhdl
 #OPTIONS:"|-top|BUS68030|-prodtype|synplify_pro|-nostructver|-dfltencoding|sequential|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
-#CUR:"C:\\ispLever\\synpbase\\bin64\\c_vhdl.exe":1401224104
-#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\location.map":1310457374
-#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\std.vhd":1401223722
-#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\snps_haps_pkg.vhd":1401223722
-#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\std1164.vhd":1401223722
-#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\numeric.vhd":1401223722
-#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1401223968
-#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1401223722
-#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1401223722
-#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1427576546
+#CUR:"C:\\ispLever\\synpbase\\bin64\\c_vhdl.exe":1401227704
+#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\location.map":1310460974
+#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\std.vhd":1401227322
+#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\snps_haps_pkg.vhd":1401227322
+#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\std1164.vhd":1401227322
+#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\numeric.vhd":1401227322
+#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1401227568
+#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1401227322
+#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1401227322
+#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1431550739
 0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
 
 # Dependency Lists (Uses list)
diff --git a/Logic/synwork/BUS68030_comp.srs b/Logic/synwork/BUS68030_comp.srs
index 53340a9..1cbd903 100644
Binary files a/Logic/synwork/BUS68030_comp.srs and b/Logic/synwork/BUS68030_comp.srs differ
diff --git a/Logic/synwork/BUS68030_comp.tlg b/Logic/synwork/BUS68030_comp.tlg
index c8805a7..6e1c810 100644
--- a/Logic/synwork/BUS68030_comp.tlg
+++ b/Logic/synwork/BUS68030_comp.tlg
@@ -1,15 +1,17 @@
 @N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral 
-@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:7:124:17|Signal clk_out_pre is undriven 
+@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:7:126:17|Signal clk_out_pre is undriven 
 Post processing for work.bus68030.behavioral
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:37:137:39|Pruning register AMIGA_BUS_ENABLE_INT_4  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_000_D4_2  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_000_D3_2  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:34:129:36|Pruning register CLK_000_D2_2  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":122:36:122:38|Pruning register CLK_OUT_PRE_50_D_2  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":152:2:152:3|Pruning register CLK_030_D0_2  
-@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:61:133:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ... 
-@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ... 
-@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:37:137:39|Trying to extract state machine for register SM_AMIGA
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Pruning register AMIGA_BUS_ENABLE_INT_4  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Pruning register CLK_000_D4_2  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_000_D3_2  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_000_D2_2  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:35:127:37|Pruning register CLK_OUT_INT_2  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:36:124:38|Pruning register CLK_OUT_PRE_50_D_2  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":155:2:155:3|Pruning register CLK_030_D0_2  
+@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":135:61:135:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ... 
+@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:34:134:36|Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ... 
+@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ...
+@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register SM_AMIGA
 Extracted state machine for register SM_AMIGA
 State machine has 8 reachable states with original encodings of:
    000
@@ -20,5 +22,5 @@ State machine has 8 reachable states with original encodings of:
    101
    110
    111
-@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:37:137:39|Trying to extract state machine for register cpu_est
+@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register cpu_est
 @W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":23:1:23:1|Input port bits 15 to 2 of a(31 downto 2) are unused 
diff --git a/Logic/synwork/BUS68030_mult.srs b/Logic/synwork/BUS68030_mult.srs
index 543949b..d37a669 100644
Binary files a/Logic/synwork/BUS68030_mult.srs and b/Logic/synwork/BUS68030_mult.srs differ
diff --git a/Logic/synwork/BUS68030_mult_srs/skeleton.srs b/Logic/synwork/BUS68030_mult_srs/skeleton.srs
index 3b4ed05..5ac7b10 100644
Binary files a/Logic/synwork/BUS68030_mult_srs/skeleton.srs and b/Logic/synwork/BUS68030_mult_srs/skeleton.srs differ
diff --git a/Logic/synwork/BUS68030_s.srs b/Logic/synwork/BUS68030_s.srs
index 53340a9..1cbd903 100644
Binary files a/Logic/synwork/BUS68030_s.srs and b/Logic/synwork/BUS68030_s.srs differ