diff --git a/Logic/68030-68000-bus.vhd b/Logic/68030-68000-bus.vhd index f8e30af..abf009a 100644 --- a/Logic/68030-68000-bus.vhd +++ b/Logic/68030-68000-bus.vhd @@ -105,7 +105,8 @@ signal VMA_INT: STD_LOGIC:='1'; signal UDS_000_INT: STD_LOGIC:='1'; signal LDS_000_INT: STD_LOGIC:='1'; signal DSACK_INT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "11"; -signal CLK_CNT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00"; +signal CLK_CNT_P: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00"; +signal CLK_CNT_N: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00"; signal CLK_REF: STD_LOGIC_VECTOR ( 1 downto 0 ) := "10"; signal CLK_OUT_PRE: STD_LOGIC:='1'; signal CLK_OUT_INT: STD_LOGIC:='1'; @@ -121,20 +122,55 @@ signal CLK_000_D6: STD_LOGIC := '1'; begin - --the clocks - clk: process(CLK_OSZI) + neg_clk: process(RST, CLK_OSZI) begin - if(rising_edge(CLK_OSZI)) then + if(RST = '0' ) then + CLK_CNT_N <= "00"; + elsif(falling_edge(CLK_OSZI)) then + --clk generation : up to now just half the clock + if(CLK_CNT_N = "10") then + --CLK_OUT_PRE <= not CLK_OUT_PRE; + CLK_CNT_N <= "00"; + else + CLK_CNT_N <= CLK_CNT_N+1; + end if; + end if; + end process neg_clk; + --the clocks + clk: process(RST, CLK_OSZI) + begin + if(RST = '0' ) then + CLK_CNT_P <= "00"; + RESET <= '0'; + CLK_OUT_PRE <= '0'; + CLK_OUT_INT <= '0'; + cpu_est <= E20; + cpu_est_d <= E20; + VPA_D <= '1'; + CLK_000_D0 <= '1'; + CLK_000_D1 <= '1'; + CLK_000_D2 <= '1'; + CLK_000_D3 <= '1'; + CLK_000_D4 <= '1'; + CLK_000_D5 <= '1'; + CLK_000_D6 <= '1'; + + elsif(rising_edge(CLK_OSZI)) then --reset buffer - RESET <= RST; + RESET <= '1'; --clk generation : up to now just half the clock - if(CLK_CNT = CLK_REF) then - CLK_OUT_PRE <= not CLK_OUT_PRE; - CLK_CNT <= "00"; + if(CLK_CNT_P = "10") then + --CLK_OUT_PRE <= not CLK_OUT_PRE; + CLK_CNT_P <= "00"; else - CLK_CNT <= CLK_CNT+1; + CLK_CNT_P <= CLK_CNT_P+1; + end if; + if(CLK_CNT_P ="00" or CLK_CNT_N ="00")then --33MHz Clock + CLK_OUT_PRE <= '0'; + else + CLK_OUT_PRE <= '1'; end if; -- the external clock to the processor is generated here CLK_OUT_INT <= CLK_OUT_PRE; --this way we know the clock of the next state: Its like looking in the future, cool! @@ -212,13 +248,12 @@ begin --bus grant only in idle state if(BG_030= '1')then BG_000 <= '1'; - elsif(CLK_030 ='0') then - if( BG_030= '0' AND (SM_AMIGA = IDLE_P) - and nEXP_SPACE = '0' and AS_030='1') then --bus granted no local access and no AS_030 running! + elsif( BG_030= '0' AND (SM_AMIGA = IDLE_P) + and nEXP_SPACE = '0' and AS_030='1' + and CLK_000_D0='1' AND CLK_000_D1='0') then --bus granted no local access and no AS_030 running! BG_000 <= '0'; - else - BG_000 <= '1'; - end if; + else + BG_000 <= '1'; end if; @@ -391,7 +426,7 @@ begin AVEC <= '1'; --as and uds/lds - AS_000 <= 'Z' when BGACK_030_INT ='0' else + AS_000 <= 'Z' when BGACK_030_INT ='0' else AS_000_INT; UDS_000 <= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle UDS_000_INT; diff --git a/Logic/68030_TK.tcl b/Logic/68030_TK.tcl index 995fc5f..bfacfe4 100644 --- a/Logic/68030_TK.tcl +++ b/Logic/68030_TK.tcl @@ -147793,3 +147793,918 @@ if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 6 ########## Tcl recorder end at 05/24/14 11:44:02 ########### + +########## Tcl recorder starts at 05/24/14 15:22:31 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 15:22:31 ########### + + +########## Tcl recorder starts at 05/24/14 15:22:31 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 15:22:31 ########### + + +########## Tcl recorder starts at 05/24/14 15:23:51 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 15:23:51 ########### + + +########## Tcl recorder starts at 05/24/14 15:23:51 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 15:23:51 ########### + + +########## Tcl recorder starts at 05/24/14 15:46:27 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 15:46:27 ########### + + +########## Tcl recorder starts at 05/24/14 15:46:27 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 15:46:27 ########### + + +########## Tcl recorder starts at 05/24/14 15:47:05 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 15:47:05 ########### + + +########## Tcl recorder starts at 05/24/14 15:47:05 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 15:47:05 ########### + + +########## Tcl recorder starts at 05/24/14 15:48:43 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 15:48:43 ########### + + +########## Tcl recorder starts at 05/24/14 15:48:43 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 15:48:43 ########### + diff --git a/Logic/68030_tk.bl2 b/Logic/68030_tk.bl2 index 0b9262c..736e544 100644 --- a/Logic/68030_tk.bl2 +++ b/Logic/68030_tk.bl2 @@ -1,75 +1,74 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Sat May 24 11:44:09 2014 +#$ DATE Sat May 24 15:48:50 2014 #$ MODULE 68030_tk -#$ PINS 74 SIZE_1_ A_31_ IPL_030_2_ IPL_2_ DSACK_1_ FC_1_ AS_030 AS_000 DS_030 UDS_000 \ -# LDS_000 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 SIZE_0_ \ -# CLK_OSZI A_30_ CLK_DIV_OUT A_29_ CLK_EXP A_28_ FPU_CS A_27_ DTACK A_26_ AVEC A_25_ \ -# AVEC_EXP A_24_ E A_23_ VPA A_22_ VMA A_21_ RST A_20_ RESET A_19_ RW A_18_ AMIGA_BUS_ENABLE \ -# A_17_ AMIGA_BUS_DATA_DIR A_16_ AMIGA_BUS_ENABLE_LOW A_15_ CIIN A_14_ A_13_ A_12_ A_11_ \ -# A_10_ A_9_ A_8_ A_7_ A_6_ A_5_ A_4_ A_3_ A_2_ A_1_ A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ IPL_0_ \ +#$ PINS 74 SIZE_1_ A_31_ IPL_030_2_ SIZE_0_ IPL_2_ A_30_ A_29_ DSACK_1_ A_28_ A_27_ \ +# FC_1_ A_26_ AS_030 A_25_ AS_000 A_24_ DS_030 A_23_ UDS_000 A_22_ LDS_000 A_21_ nEXP_SPACE \ +# A_20_ BERR A_19_ BG_030 A_18_ BG_000 A_17_ BGACK_030 A_16_ BGACK_000 A_15_ CLK_030 A_14_ \ +# CLK_000 A_13_ CLK_OSZI A_12_ CLK_DIV_OUT A_11_ CLK_EXP A_10_ FPU_CS A_9_ DTACK A_8_ AVEC \ +# A_7_ AVEC_EXP A_6_ E A_5_ VPA A_4_ VMA A_3_ RST A_2_ RESET A_1_ RW A_0_ AMIGA_BUS_ENABLE \ +# IPL_030_1_ AMIGA_BUS_DATA_DIR IPL_030_0_ AMIGA_BUS_ENABLE_LOW IPL_1_ CIIN IPL_0_ \ # DSACK_0_ FC_0_ -#$ NODES 376 BGACK_000_c CLK_030_c inst_BGACK_030_INTreg inst_FPU_CS_INTreg \ -# CLK_OSZI_c cpu_est_3_reg inst_VMA_INTreg cpu_est_0_ CLK_OUT_INTreg cpu_est_1_ \ -# inst_AS_000_INTreg inst_AS_030_000_SYNC IPL_030DFFSH_0_reg inst_DTACK_SYNC \ -# inst_VPA_D IPL_030DFFSH_1_reg inst_VPA_SYNC inst_CLK_000_D0 IPL_030DFFSH_2_reg \ -# inst_CLK_000_D1 inst_CLK_000_D2 ipl_c_0__n inst_CLK_000_D5 inst_CLK_OUT_PRE \ -# ipl_c_1__n SM_AMIGA_6_ SM_AMIGA_5_ ipl_c_2__n vcc_n_n gnd_n_n cpu_est_2_ dsack_c_1__n \ -# CLK_REF_1_ inst_UDS_000_INTreg DTACK_c inst_LDS_000_INTreg DSACK_INT_1_ SM_AMIGA_7_ \ -# AS_000_INT_1_sqmuxa state_machine_un8_clk_000_d2_n inst_CLK_000_D3 SM_AMIGA_4_ \ -# state_machine_un23_clk_000_d0_n RST_c state_machine_un6_clk_000_d4_n \ -# inst_CLK_000_D4 RESETDFFreg inst_DTACK_DMA clk_clk_cnt_n RW_c CLK_CNT_0_ CLK_CNT_1_ \ -# fc_c_0__n state_machine_un6_bgack_000_n SM_AMIGA_3_ fc_c_1__n SM_AMIGA_1_ \ -# SM_AMIGA_2_ AMIGA_BUS_ENABLEDFFreg SM_AMIGA_0_ state_machine_un7_as_000_int_n \ -# state_machine_un15_clk_000_d0_n clk_cpu_est_11_0_1__n \ -# state_machine_lds_000_int_5_n N_124_i state_machine_uds_000_int_5_n N_146_i \ -# un1_AMIGA_BUS_ENABLE_1_sqmuxa_2 N_121_i N_122_i N_66_0 N_65_0 N_145_i \ -# un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 DS_030_c_i N_63_i N_62_i \ -# state_machine_un6_clk_000_d4_i_n N_61_i CLK_OUT_PRE_0 N_60_i N_59_i N_58_i N_57_i \ -# CLK_000_D1_i N_56_i N_55_i N_52_i N_141_i N_142_i N_14_0 N_85_i N_139_i \ -# clk_cpu_est_11_1__n N_140_i clk_cpu_est_11_3__n sm_amiga_ns_0_0__n G_92 N_125_i G_96 \ -# N_138_i N_162 N_178_i N_163 clk_cpu_est_11_0_3__n N_164 N_119_i N_165 N_43_i N_30 \ -# N_117_i N_118_i N_51 N_123_i N_52 N_115_i N_55 N_116_i N_56 sm_amiga_ns_0_7__n N_57 \ -# N_98_i N_58 N_114_i N_59 N_39_0 N_60 N_94_i N_61 N_97_i N_62 sm_amiga_ns_0_5__n N_63 \ -# N_89_i N_65 N_90_i N_66 N_69 N_88_i N_72 N_73 N_86_i N_74 N_75 N_83_i N_76 N_77 N_81_i N_79 \ -# state_machine_lds_000_int_5_0_n N_81 state_machine_uds_000_int_5_0_n N_83 N_79_i \ -# N_85 N_30_0 N_86 N_165_0 N_88 N_76_i N_89 N_164_0 N_90 N_163_0 N_94 N_72_i N_97 N_73_i N_98 \ -# state_machine_un15_clk_000_d0_0_n N_114 N_162_0 N_115 \ -# state_machine_un6_bgack_000_0_n N_116 state_machine_un23_clk_000_d0_i_n N_117 \ -# N_188_1 N_118 N_188_2 N_119 N_188_3 N_120 N_188_4 N_121 N_188_5 N_122 N_188_6 N_124 \ -# N_191_1 N_125 N_191_2 N_178 state_machine_un8_clk_000_d2_1_n N_138 N_57_i_1 N_139 \ -# N_57_i_2 N_140 N_57_i_3 N_141 N_57_i_4 N_142 N_57_i_5 N_145 clk_cpu_est_11_0_1_1__n \ -# N_146 clk_cpu_est_11_0_2_1__n N_77_1 N_120_1 N_188 N_120_2 N_191 N_79_1 RW_i N_79_2 \ -# VPA_D_i N_77_1_0 CLK_000_D0_i N_75_1 cpu_est_i_0__n N_75_2 cpu_est_i_3__n N_75_3 \ -# VMA_INT_i N_75_4 cpu_est_i_1__n N_75_5 DTACK_i N_73_1 BG_030_i N_73_2 nEXP_SPACE_i \ -# N_72_1 sm_amiga_i_3__n N_72_2 AS_000_INT_i sm_amiga_ns_0_1_0__n sm_amiga_i_6__n \ -# clk_cpu_est_11_0_1_3__n cpu_est_i_2__n N_138_1 AMIGA_BUS_ENABLE_i N_119_1 AS_030_i \ -# N_118_1 sm_amiga_i_4__n N_117_1 sm_amiga_i_5__n N_97_1 \ -# state_machine_un8_clk_000_d2_i_n N_81_1 sm_amiga_i_7__n \ -# state_machine_uds_000_int_5_0_m2_un3_n a_i_0__n \ -# state_machine_uds_000_int_5_0_m2_un1_n size_i_1__n \ -# state_machine_uds_000_int_5_0_m2_un0_n dsack_i_1__n vpa_sync_0_un3_n \ -# clk_clk_cnt_i_n vpa_sync_0_un1_n clk_cnt_i_0__n vpa_sync_0_un0_n CLK_000_D2_i \ -# amiga_bus_enable_0_un3_n AS_030_000_SYNC_i amiga_bus_enable_0_un1_n a_i_30__n \ -# amiga_bus_enable_0_un0_n a_i_31__n uds_000_int_0_un3_n a_i_28__n \ -# uds_000_int_0_un1_n a_i_29__n uds_000_int_0_un0_n a_i_26__n lds_000_int_0_un3_n \ -# a_i_27__n lds_000_int_0_un1_n a_i_24__n lds_000_int_0_un0_n a_i_25__n \ -# vma_int_0_un3_n a_i_19__n vma_int_0_un1_n a_i_16__n vma_int_0_un0_n a_i_18__n \ -# bg_000_0_un3_n N_137_i bg_000_0_un1_n bg_000_0_un0_n RST_i bgack_030_int_0_un3_n \ -# N_120_i bgack_030_int_0_un1_n N_75_i bgack_030_int_0_un0_n N_74_i \ -# as_000_int_0_un3_n N_77_i as_000_int_0_un1_n FPU_CS_INT_i as_000_int_0_un0_n \ -# BGACK_030_INT_i cpu_est_0_1__un3_n CLK_000_D5_i cpu_est_0_1__un1_n AS_030_c \ -# cpu_est_0_1__un0_n cpu_est_0_2__un3_n cpu_est_0_2__un1_n DS_030_c \ -# cpu_est_0_2__un0_n cpu_est_0_3__un3_n cpu_est_0_3__un1_n cpu_est_0_3__un0_n \ -# size_c_0__n ipl_030_0_0__un3_n ipl_030_0_0__un1_n size_c_1__n ipl_030_0_0__un0_n \ -# ipl_030_0_1__un3_n a_c_0__n ipl_030_0_1__un1_n ipl_030_0_1__un0_n \ -# ipl_030_0_2__un3_n ipl_030_0_2__un1_n ipl_030_0_2__un0_n as_030_000_sync_0_un3_n \ -# as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n dtack_sync_0_un3_n \ -# dtack_sync_0_un1_n dtack_sync_0_un0_n fpu_cs_int_0_un3_n fpu_cs_int_0_un1_n \ -# fpu_cs_int_0_un0_n dsack_int_0_1__un3_n dsack_int_0_1__un1_n dsack_int_0_1__un0_n \ -# a_c_16__n a_15__n a_c_17__n a_14__n a_c_18__n a_13__n a_c_19__n a_12__n a_c_20__n \ -# a_11__n a_c_21__n a_10__n a_c_22__n a_9__n a_c_23__n a_8__n a_c_24__n a_7__n a_c_25__n \ -# a_6__n a_c_26__n a_5__n a_c_27__n a_4__n a_c_28__n a_3__n a_c_29__n a_2__n a_c_30__n \ -# a_1__n a_c_31__n nEXP_SPACE_c BG_030_c BG_000DFFSHreg +#$ NODES 357 CLK_OSZI_c CLK_OUT_INTreg IPL_030DFFSH_0_reg inst_BGACK_030_INTreg \ +# inst_FPU_CS_INTreg IPL_030DFFSH_1_reg inst_VMA_INTreg inst_AS_000_INTreg \ +# IPL_030DFFSH_2_reg inst_AS_030_000_SYNC inst_DTACK_SYNC ipl_c_0__n inst_VPA_D \ +# inst_VPA_SYNC ipl_c_1__n inst_CLK_000_D0 inst_CLK_000_D1 ipl_c_2__n inst_CLK_000_D2 \ +# inst_CLK_000_D5 SM_AMIGA_5_ dsack_c_1__n SM_AMIGA_6_ vcc_n_n DTACK_c gnd_n_n \ +# inst_UDS_000_INTreg inst_LDS_000_INTreg DSACK_INT_1_ AS_000_INT_1_sqmuxa \ +# state_machine_un8_clk_000_d2_n inst_CLK_000_D3 SM_AMIGA_4_ RST_c \ +# state_machine_un23_clk_000_d0_n state_machine_un6_clk_000_d4_n RESETDFFRHreg \ +# inst_CLK_000_D4 inst_DTACK_DMA RW_c state_machine_un10_bg_030_n SM_AMIGA_7_ \ +# fc_c_0__n SM_AMIGA_3_ state_machine_un6_bgack_000_n fc_c_1__n SM_AMIGA_1_ G_102 \ +# AMIGA_BUS_ENABLEDFFreg CLK_CNT_N_0_ CLK_CNT_N_1_ G_108 CLK_CNT_P_0_ CLK_CNT_P_1_ \ +# cpu_est_ns_0_1__n SM_AMIGA_2_ N_126_i SM_AMIGA_0_ N_128_i \ +# state_machine_un7_as_000_int_n N_216_i state_machine_un15_clk_000_d0_n N_217_i \ +# state_machine_lds_000_int_5_n N_61_0 state_machine_uds_000_int_5_n N_60_0 \ +# un1_AMIGA_BUS_ENABLE_1_sqmuxa_2 N_129_i inst_CLK_OUT_PRE \ +# un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 DS_030_c_i N_58_i N_57_i N_55_i N_54_i N_53_i \ +# N_50_i CLK_000_D1_i N_49_i N_48_i N_122_i N_123_i cpu_est_ns_e_0_0__n N_79_i N_226_i \ +# N_227_i sm_amiga_ns_0_0__n cpu_est_0_ N_222_i cpu_est_1_ N_223_i cpu_est_2_ N_225_i \ +# cpu_est_3_reg cpu_est_ns_0_2__n N_221_i N_41_i N_127_i N_220_i cpu_est_ns_1__n \ +# N_157_i cpu_est_ns_2__n N_214_i N_203 N_215_i N_204 sm_amiga_ns_0_7__n N_205 N_93_i \ +# N_23 N_94_i N_27 N_47 N_85_i N_48 N_86_i N_49 sm_amiga_ns_0_5__n N_50 N_84_i N_53 N_130_i \ +# N_54 N_55 N_82_i N_57 N_58 N_81_i N_60 N_61 N_77_i N_68 N_69 N_75_i N_70 \ +# state_machine_lds_000_int_5_0_n N_71 state_machine_uds_000_int_5_0_n N_72 N_73_i \ +# N_73 N_27_0 N_75 N_23_0 N_77 N_71_i N_79 N_205_0 N_81 N_204_0 N_82 N_68_i N_84 N_69_i N_85 \ +# state_machine_un15_clk_000_d0_0_n N_86 N_203_0 N_93 \ +# state_machine_un6_bgack_000_0_n N_94 N_214 state_machine_un23_clk_000_d0_0_n N_215 \ +# N_238_1 N_216 N_238_2 N_217 N_238_3 N_220 N_238_4 N_221 N_238_5 N_222 N_238_6 N_223 \ +# N_241_1 N_225 N_241_2 N_226 state_machine_un8_clk_000_d2_1_n N_227 N_53_i_1 N_122 \ +# N_53_i_2 N_123 N_53_i_3 N_126 N_53_i_4 N_127 N_53_i_5 N_128 cpu_est_ns_0_1_1__n N_129 \ +# cpu_est_ns_0_2_1__n N_130 state_machine_un10_bg_030_1_n N_238 \ +# state_machine_un10_bg_030_2_n N_241 state_machine_un10_bg_030_3_n RW_i N_73_1 \ +# VMA_INT_i N_73_2 VPA_D_i N_72_1 DTACK_i N_72_2 BG_030_i N_70_1 nEXP_SPACE_i N_70_2 \ +# CLK_000_D0_i N_70_3 sm_amiga_i_4__n sm_amiga_ns_0_1_0__n cpu_est_i_3__n \ +# cpu_est_ns_0_1_2__n sm_amiga_i_1__n N_221_1 state_machine_un6_clk_000_d4_i_n \ +# N_215_1 sm_amiga_i_6__n N_75_1 AS_000_INT_i N_69_1 cpu_est_i_1__n N_68_1 \ +# cpu_est_i_0__n state_machine_uds_000_int_5_0_m2_un3_n AMIGA_BUS_ENABLE_i \ +# state_machine_uds_000_int_5_0_m2_un1_n AS_030_i \ +# state_machine_uds_000_int_5_0_m2_un0_n cpu_est_i_2__n lds_000_int_0_un3_n \ +# sm_amiga_i_2__n lds_000_int_0_un1_n sm_amiga_i_3__n lds_000_int_0_un0_n \ +# sm_amiga_i_5__n vpa_sync_0_un3_n state_machine_un8_clk_000_d2_i_n \ +# vpa_sync_0_un1_n sm_amiga_i_7__n vpa_sync_0_un0_n a_i_0__n vma_int_0_un3_n \ +# size_i_1__n vma_int_0_un1_n dsack_i_1__n vma_int_0_un0_n CLK_000_D2_i \ +# bgack_030_int_0_un3_n AS_030_000_SYNC_i bgack_030_int_0_un1_n a_i_30__n \ +# bgack_030_int_0_un0_n a_i_31__n as_000_int_0_un3_n a_i_28__n as_000_int_0_un1_n \ +# a_i_29__n as_000_int_0_un0_n a_i_26__n ipl_030_0_0__un3_n a_i_27__n \ +# ipl_030_0_0__un1_n a_i_24__n ipl_030_0_0__un0_n a_i_25__n ipl_030_0_1__un3_n \ +# a_i_19__n ipl_030_0_1__un1_n a_i_16__n ipl_030_0_1__un0_n a_i_18__n \ +# ipl_030_0_2__un3_n RST_i ipl_030_0_2__un1_n ipl_030_0_2__un0_n cpu_estse_0_un3_n \ +# cpu_estse_0_un1_n CLK_OSZI_i cpu_estse_0_un0_n cpu_estse_1_un3_n N_70_i \ +# cpu_estse_1_un1_n N_72_i cpu_estse_1_un0_n FPU_CS_INT_i cpu_estse_2_un3_n \ +# BGACK_030_INT_i cpu_estse_2_un1_n CLK_000_D5_i cpu_estse_2_un0_n AS_030_c \ +# as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n DS_030_c \ +# dtack_sync_0_un3_n dtack_sync_0_un1_n dtack_sync_0_un0_n fpu_cs_int_0_un3_n \ +# size_c_0__n fpu_cs_int_0_un1_n fpu_cs_int_0_un0_n size_c_1__n dsack_int_0_1__un3_n \ +# dsack_int_0_1__un1_n a_c_0__n dsack_int_0_1__un0_n amiga_bus_enable_0_un3_n \ +# amiga_bus_enable_0_un1_n amiga_bus_enable_0_un0_n uds_000_int_0_un3_n \ +# uds_000_int_0_un1_n uds_000_int_0_un0_n a_15__n a_14__n a_13__n a_12__n a_11__n \ +# a_c_16__n a_10__n a_c_17__n a_9__n a_c_18__n a_8__n a_c_19__n a_7__n a_c_20__n a_6__n \ +# a_c_21__n a_5__n a_c_22__n a_4__n a_c_23__n a_3__n a_c_24__n a_2__n a_c_25__n a_1__n \ +# a_c_26__n a_c_27__n a_c_28__n a_c_29__n a_c_30__n a_c_31__n nEXP_SPACE_c BG_030_c \ +# BG_000DFFSHreg BGACK_000_c CLK_030_c .model bus68030 .inputs SIZE_1_.BLIF A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF AS_030.BLIF DS_030.BLIF \ nEXP_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF \ @@ -79,192 +78,214 @@ A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF A_15_.BLIF \ A_14_.BLIF A_13_.BLIF A_12_.BLIF A_11_.BLIF A_10_.BLIF A_9_.BLIF A_8_.BLIF \ A_7_.BLIF A_6_.BLIF A_5_.BLIF A_4_.BLIF A_3_.BLIF A_2_.BLIF A_1_.BLIF \ A_0_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF DSACK_1_.BLIF DTACK.BLIF \ -DSACK_0_.BLIF BGACK_000_c.BLIF CLK_030_c.BLIF inst_BGACK_030_INTreg.BLIF \ -inst_FPU_CS_INTreg.BLIF CLK_OSZI_c.BLIF cpu_est_3_reg.BLIF \ -inst_VMA_INTreg.BLIF cpu_est_0_.BLIF CLK_OUT_INTreg.BLIF cpu_est_1_.BLIF \ -inst_AS_000_INTreg.BLIF inst_AS_030_000_SYNC.BLIF IPL_030DFFSH_0_reg.BLIF \ -inst_DTACK_SYNC.BLIF inst_VPA_D.BLIF IPL_030DFFSH_1_reg.BLIF \ -inst_VPA_SYNC.BLIF inst_CLK_000_D0.BLIF IPL_030DFFSH_2_reg.BLIF \ -inst_CLK_000_D1.BLIF inst_CLK_000_D2.BLIF ipl_c_0__n.BLIF inst_CLK_000_D5.BLIF \ -inst_CLK_OUT_PRE.BLIF ipl_c_1__n.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_5_.BLIF \ -ipl_c_2__n.BLIF vcc_n_n.BLIF gnd_n_n.BLIF cpu_est_2_.BLIF dsack_c_1__n.BLIF \ -CLK_REF_1_.BLIF inst_UDS_000_INTreg.BLIF DTACK_c.BLIF inst_LDS_000_INTreg.BLIF \ -DSACK_INT_1_.BLIF SM_AMIGA_7_.BLIF AS_000_INT_1_sqmuxa.BLIF \ -state_machine_un8_clk_000_d2_n.BLIF inst_CLK_000_D3.BLIF SM_AMIGA_4_.BLIF \ -state_machine_un23_clk_000_d0_n.BLIF RST_c.BLIF \ -state_machine_un6_clk_000_d4_n.BLIF inst_CLK_000_D4.BLIF RESETDFFreg.BLIF \ -inst_DTACK_DMA.BLIF clk_clk_cnt_n.BLIF RW_c.BLIF CLK_CNT_0_.BLIF \ -CLK_CNT_1_.BLIF fc_c_0__n.BLIF state_machine_un6_bgack_000_n.BLIF \ -SM_AMIGA_3_.BLIF fc_c_1__n.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_2_.BLIF \ -AMIGA_BUS_ENABLEDFFreg.BLIF SM_AMIGA_0_.BLIF \ -state_machine_un7_as_000_int_n.BLIF state_machine_un15_clk_000_d0_n.BLIF \ -clk_cpu_est_11_0_1__n.BLIF state_machine_lds_000_int_5_n.BLIF N_124_i.BLIF \ -state_machine_uds_000_int_5_n.BLIF N_146_i.BLIF \ -un1_AMIGA_BUS_ENABLE_1_sqmuxa_2.BLIF N_121_i.BLIF N_122_i.BLIF N_66_0.BLIF \ -N_65_0.BLIF N_145_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0.BLIF \ -DS_030_c_i.BLIF N_63_i.BLIF N_62_i.BLIF state_machine_un6_clk_000_d4_i_n.BLIF \ -N_61_i.BLIF CLK_OUT_PRE_0.BLIF N_60_i.BLIF N_59_i.BLIF N_58_i.BLIF N_57_i.BLIF \ -CLK_000_D1_i.BLIF N_56_i.BLIF N_55_i.BLIF N_52_i.BLIF N_141_i.BLIF \ -N_142_i.BLIF N_14_0.BLIF N_85_i.BLIF N_139_i.BLIF clk_cpu_est_11_1__n.BLIF \ -N_140_i.BLIF clk_cpu_est_11_3__n.BLIF sm_amiga_ns_0_0__n.BLIF G_92.BLIF \ -N_125_i.BLIF G_96.BLIF N_138_i.BLIF N_162.BLIF N_178_i.BLIF N_163.BLIF \ -clk_cpu_est_11_0_3__n.BLIF N_164.BLIF N_119_i.BLIF N_165.BLIF N_43_i.BLIF \ -N_30.BLIF N_117_i.BLIF N_118_i.BLIF N_51.BLIF N_123_i.BLIF N_52.BLIF \ -N_115_i.BLIF N_55.BLIF N_116_i.BLIF N_56.BLIF sm_amiga_ns_0_7__n.BLIF \ -N_57.BLIF N_98_i.BLIF N_58.BLIF N_114_i.BLIF N_59.BLIF N_39_0.BLIF N_60.BLIF \ -N_94_i.BLIF N_61.BLIF N_97_i.BLIF N_62.BLIF sm_amiga_ns_0_5__n.BLIF N_63.BLIF \ -N_89_i.BLIF N_65.BLIF N_90_i.BLIF N_66.BLIF N_69.BLIF N_88_i.BLIF N_72.BLIF \ -N_73.BLIF N_86_i.BLIF N_74.BLIF N_75.BLIF N_83_i.BLIF N_76.BLIF N_77.BLIF \ -N_81_i.BLIF N_79.BLIF state_machine_lds_000_int_5_0_n.BLIF N_81.BLIF \ -state_machine_uds_000_int_5_0_n.BLIF N_83.BLIF N_79_i.BLIF N_85.BLIF \ -N_30_0.BLIF N_86.BLIF N_165_0.BLIF N_88.BLIF N_76_i.BLIF N_89.BLIF \ -N_164_0.BLIF N_90.BLIF N_163_0.BLIF N_94.BLIF N_72_i.BLIF N_97.BLIF \ -N_73_i.BLIF N_98.BLIF state_machine_un15_clk_000_d0_0_n.BLIF N_114.BLIF \ -N_162_0.BLIF N_115.BLIF state_machine_un6_bgack_000_0_n.BLIF N_116.BLIF \ -state_machine_un23_clk_000_d0_i_n.BLIF N_117.BLIF N_188_1.BLIF N_118.BLIF \ -N_188_2.BLIF N_119.BLIF N_188_3.BLIF N_120.BLIF N_188_4.BLIF N_121.BLIF \ -N_188_5.BLIF N_122.BLIF N_188_6.BLIF N_124.BLIF N_191_1.BLIF N_125.BLIF \ -N_191_2.BLIF N_178.BLIF state_machine_un8_clk_000_d2_1_n.BLIF N_138.BLIF \ -N_57_i_1.BLIF N_139.BLIF N_57_i_2.BLIF N_140.BLIF N_57_i_3.BLIF N_141.BLIF \ -N_57_i_4.BLIF N_142.BLIF N_57_i_5.BLIF N_145.BLIF clk_cpu_est_11_0_1_1__n.BLIF \ -N_146.BLIF clk_cpu_est_11_0_2_1__n.BLIF N_77_1.BLIF N_120_1.BLIF N_188.BLIF \ -N_120_2.BLIF N_191.BLIF N_79_1.BLIF RW_i.BLIF N_79_2.BLIF VPA_D_i.BLIF \ -N_77_1_0.BLIF CLK_000_D0_i.BLIF N_75_1.BLIF cpu_est_i_0__n.BLIF N_75_2.BLIF \ -cpu_est_i_3__n.BLIF N_75_3.BLIF VMA_INT_i.BLIF N_75_4.BLIF cpu_est_i_1__n.BLIF \ -N_75_5.BLIF DTACK_i.BLIF N_73_1.BLIF BG_030_i.BLIF N_73_2.BLIF \ -nEXP_SPACE_i.BLIF N_72_1.BLIF sm_amiga_i_3__n.BLIF N_72_2.BLIF \ -AS_000_INT_i.BLIF sm_amiga_ns_0_1_0__n.BLIF sm_amiga_i_6__n.BLIF \ -clk_cpu_est_11_0_1_3__n.BLIF cpu_est_i_2__n.BLIF N_138_1.BLIF \ -AMIGA_BUS_ENABLE_i.BLIF N_119_1.BLIF AS_030_i.BLIF N_118_1.BLIF \ -sm_amiga_i_4__n.BLIF N_117_1.BLIF sm_amiga_i_5__n.BLIF N_97_1.BLIF \ -state_machine_un8_clk_000_d2_i_n.BLIF N_81_1.BLIF sm_amiga_i_7__n.BLIF \ -state_machine_uds_000_int_5_0_m2_un3_n.BLIF a_i_0__n.BLIF \ -state_machine_uds_000_int_5_0_m2_un1_n.BLIF size_i_1__n.BLIF \ -state_machine_uds_000_int_5_0_m2_un0_n.BLIF dsack_i_1__n.BLIF \ -vpa_sync_0_un3_n.BLIF clk_clk_cnt_i_n.BLIF vpa_sync_0_un1_n.BLIF \ -clk_cnt_i_0__n.BLIF vpa_sync_0_un0_n.BLIF CLK_000_D2_i.BLIF \ -amiga_bus_enable_0_un3_n.BLIF AS_030_000_SYNC_i.BLIF \ -amiga_bus_enable_0_un1_n.BLIF a_i_30__n.BLIF amiga_bus_enable_0_un0_n.BLIF \ -a_i_31__n.BLIF uds_000_int_0_un3_n.BLIF a_i_28__n.BLIF \ -uds_000_int_0_un1_n.BLIF a_i_29__n.BLIF uds_000_int_0_un0_n.BLIF \ -a_i_26__n.BLIF lds_000_int_0_un3_n.BLIF a_i_27__n.BLIF \ -lds_000_int_0_un1_n.BLIF a_i_24__n.BLIF lds_000_int_0_un0_n.BLIF \ -a_i_25__n.BLIF vma_int_0_un3_n.BLIF a_i_19__n.BLIF vma_int_0_un1_n.BLIF \ -a_i_16__n.BLIF vma_int_0_un0_n.BLIF a_i_18__n.BLIF bg_000_0_un3_n.BLIF \ -N_137_i.BLIF bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF RST_i.BLIF \ -bgack_030_int_0_un3_n.BLIF N_120_i.BLIF bgack_030_int_0_un1_n.BLIF N_75_i.BLIF \ -bgack_030_int_0_un0_n.BLIF N_74_i.BLIF as_000_int_0_un3_n.BLIF N_77_i.BLIF \ -as_000_int_0_un1_n.BLIF FPU_CS_INT_i.BLIF as_000_int_0_un0_n.BLIF \ -BGACK_030_INT_i.BLIF cpu_est_0_1__un3_n.BLIF CLK_000_D5_i.BLIF \ -cpu_est_0_1__un1_n.BLIF AS_030_c.BLIF cpu_est_0_1__un0_n.BLIF \ -cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un1_n.BLIF DS_030_c.BLIF \ -cpu_est_0_2__un0_n.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un1_n.BLIF \ -cpu_est_0_3__un0_n.BLIF size_c_0__n.BLIF ipl_030_0_0__un3_n.BLIF \ -ipl_030_0_0__un1_n.BLIF size_c_1__n.BLIF ipl_030_0_0__un0_n.BLIF \ -ipl_030_0_1__un3_n.BLIF a_c_0__n.BLIF ipl_030_0_1__un1_n.BLIF \ -ipl_030_0_1__un0_n.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un1_n.BLIF \ -ipl_030_0_2__un0_n.BLIF as_030_000_sync_0_un3_n.BLIF \ -as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF \ -dtack_sync_0_un3_n.BLIF dtack_sync_0_un1_n.BLIF dtack_sync_0_un0_n.BLIF \ -fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF \ -dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF \ -a_c_16__n.BLIF a_15__n.BLIF a_c_17__n.BLIF a_14__n.BLIF a_c_18__n.BLIF \ -a_13__n.BLIF a_c_19__n.BLIF a_12__n.BLIF a_c_20__n.BLIF a_11__n.BLIF \ -a_c_21__n.BLIF a_10__n.BLIF a_c_22__n.BLIF a_9__n.BLIF a_c_23__n.BLIF \ -a_8__n.BLIF a_c_24__n.BLIF a_7__n.BLIF a_c_25__n.BLIF a_6__n.BLIF \ -a_c_26__n.BLIF a_5__n.BLIF a_c_27__n.BLIF a_4__n.BLIF a_c_28__n.BLIF \ -a_3__n.BLIF a_c_29__n.BLIF a_2__n.BLIF a_c_30__n.BLIF a_1__n.BLIF \ +DSACK_0_.BLIF CLK_OSZI_c.BLIF CLK_OUT_INTreg.BLIF IPL_030DFFSH_0_reg.BLIF \ +inst_BGACK_030_INTreg.BLIF inst_FPU_CS_INTreg.BLIF IPL_030DFFSH_1_reg.BLIF \ +inst_VMA_INTreg.BLIF inst_AS_000_INTreg.BLIF IPL_030DFFSH_2_reg.BLIF \ +inst_AS_030_000_SYNC.BLIF inst_DTACK_SYNC.BLIF ipl_c_0__n.BLIF inst_VPA_D.BLIF \ +inst_VPA_SYNC.BLIF ipl_c_1__n.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF \ +ipl_c_2__n.BLIF inst_CLK_000_D2.BLIF inst_CLK_000_D5.BLIF SM_AMIGA_5_.BLIF \ +dsack_c_1__n.BLIF SM_AMIGA_6_.BLIF vcc_n_n.BLIF DTACK_c.BLIF gnd_n_n.BLIF \ +inst_UDS_000_INTreg.BLIF inst_LDS_000_INTreg.BLIF DSACK_INT_1_.BLIF \ +AS_000_INT_1_sqmuxa.BLIF state_machine_un8_clk_000_d2_n.BLIF \ +inst_CLK_000_D3.BLIF SM_AMIGA_4_.BLIF RST_c.BLIF \ +state_machine_un23_clk_000_d0_n.BLIF state_machine_un6_clk_000_d4_n.BLIF \ +RESETDFFRHreg.BLIF inst_CLK_000_D4.BLIF inst_DTACK_DMA.BLIF RW_c.BLIF \ +state_machine_un10_bg_030_n.BLIF SM_AMIGA_7_.BLIF fc_c_0__n.BLIF \ +SM_AMIGA_3_.BLIF state_machine_un6_bgack_000_n.BLIF fc_c_1__n.BLIF \ +SM_AMIGA_1_.BLIF G_102.BLIF AMIGA_BUS_ENABLEDFFreg.BLIF CLK_CNT_N_0_.BLIF \ +CLK_CNT_N_1_.BLIF G_108.BLIF CLK_CNT_P_0_.BLIF CLK_CNT_P_1_.BLIF \ +cpu_est_ns_0_1__n.BLIF SM_AMIGA_2_.BLIF N_126_i.BLIF SM_AMIGA_0_.BLIF \ +N_128_i.BLIF state_machine_un7_as_000_int_n.BLIF N_216_i.BLIF \ +state_machine_un15_clk_000_d0_n.BLIF N_217_i.BLIF \ +state_machine_lds_000_int_5_n.BLIF N_61_0.BLIF \ +state_machine_uds_000_int_5_n.BLIF N_60_0.BLIF \ +un1_AMIGA_BUS_ENABLE_1_sqmuxa_2.BLIF N_129_i.BLIF inst_CLK_OUT_PRE.BLIF \ +un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0.BLIF DS_030_c_i.BLIF N_58_i.BLIF N_57_i.BLIF \ +N_55_i.BLIF N_54_i.BLIF N_53_i.BLIF N_50_i.BLIF CLK_000_D1_i.BLIF N_49_i.BLIF \ +N_48_i.BLIF N_122_i.BLIF N_123_i.BLIF cpu_est_ns_e_0_0__n.BLIF N_79_i.BLIF \ +N_226_i.BLIF N_227_i.BLIF sm_amiga_ns_0_0__n.BLIF cpu_est_0_.BLIF N_222_i.BLIF \ +cpu_est_1_.BLIF N_223_i.BLIF cpu_est_2_.BLIF N_225_i.BLIF cpu_est_3_reg.BLIF \ +cpu_est_ns_0_2__n.BLIF N_221_i.BLIF N_41_i.BLIF N_127_i.BLIF N_220_i.BLIF \ +cpu_est_ns_1__n.BLIF N_157_i.BLIF cpu_est_ns_2__n.BLIF N_214_i.BLIF N_203.BLIF \ +N_215_i.BLIF N_204.BLIF sm_amiga_ns_0_7__n.BLIF N_205.BLIF N_93_i.BLIF \ +N_23.BLIF N_94_i.BLIF N_27.BLIF N_47.BLIF N_85_i.BLIF N_48.BLIF N_86_i.BLIF \ +N_49.BLIF sm_amiga_ns_0_5__n.BLIF N_50.BLIF N_84_i.BLIF N_53.BLIF N_130_i.BLIF \ +N_54.BLIF N_55.BLIF N_82_i.BLIF N_57.BLIF N_58.BLIF N_81_i.BLIF N_60.BLIF \ +N_61.BLIF N_77_i.BLIF N_68.BLIF N_69.BLIF N_75_i.BLIF N_70.BLIF \ +state_machine_lds_000_int_5_0_n.BLIF N_71.BLIF \ +state_machine_uds_000_int_5_0_n.BLIF N_72.BLIF N_73_i.BLIF N_73.BLIF \ +N_27_0.BLIF N_75.BLIF N_23_0.BLIF N_77.BLIF N_71_i.BLIF N_79.BLIF N_205_0.BLIF \ +N_81.BLIF N_204_0.BLIF N_82.BLIF N_68_i.BLIF N_84.BLIF N_69_i.BLIF N_85.BLIF \ +state_machine_un15_clk_000_d0_0_n.BLIF N_86.BLIF N_203_0.BLIF N_93.BLIF \ +state_machine_un6_bgack_000_0_n.BLIF N_94.BLIF N_214.BLIF \ +state_machine_un23_clk_000_d0_0_n.BLIF N_215.BLIF N_238_1.BLIF N_216.BLIF \ +N_238_2.BLIF N_217.BLIF N_238_3.BLIF N_220.BLIF N_238_4.BLIF N_221.BLIF \ +N_238_5.BLIF N_222.BLIF N_238_6.BLIF N_223.BLIF N_241_1.BLIF N_225.BLIF \ +N_241_2.BLIF N_226.BLIF state_machine_un8_clk_000_d2_1_n.BLIF N_227.BLIF \ +N_53_i_1.BLIF N_122.BLIF N_53_i_2.BLIF N_123.BLIF N_53_i_3.BLIF N_126.BLIF \ +N_53_i_4.BLIF N_127.BLIF N_53_i_5.BLIF N_128.BLIF cpu_est_ns_0_1_1__n.BLIF \ +N_129.BLIF cpu_est_ns_0_2_1__n.BLIF N_130.BLIF \ +state_machine_un10_bg_030_1_n.BLIF N_238.BLIF \ +state_machine_un10_bg_030_2_n.BLIF N_241.BLIF \ +state_machine_un10_bg_030_3_n.BLIF RW_i.BLIF N_73_1.BLIF VMA_INT_i.BLIF \ +N_73_2.BLIF VPA_D_i.BLIF N_72_1.BLIF DTACK_i.BLIF N_72_2.BLIF BG_030_i.BLIF \ +N_70_1.BLIF nEXP_SPACE_i.BLIF N_70_2.BLIF CLK_000_D0_i.BLIF N_70_3.BLIF \ +sm_amiga_i_4__n.BLIF sm_amiga_ns_0_1_0__n.BLIF cpu_est_i_3__n.BLIF \ +cpu_est_ns_0_1_2__n.BLIF sm_amiga_i_1__n.BLIF N_221_1.BLIF \ +state_machine_un6_clk_000_d4_i_n.BLIF N_215_1.BLIF sm_amiga_i_6__n.BLIF \ +N_75_1.BLIF AS_000_INT_i.BLIF N_69_1.BLIF cpu_est_i_1__n.BLIF N_68_1.BLIF \ +cpu_est_i_0__n.BLIF state_machine_uds_000_int_5_0_m2_un3_n.BLIF \ +AMIGA_BUS_ENABLE_i.BLIF state_machine_uds_000_int_5_0_m2_un1_n.BLIF \ +AS_030_i.BLIF state_machine_uds_000_int_5_0_m2_un0_n.BLIF cpu_est_i_2__n.BLIF \ +lds_000_int_0_un3_n.BLIF sm_amiga_i_2__n.BLIF lds_000_int_0_un1_n.BLIF \ +sm_amiga_i_3__n.BLIF lds_000_int_0_un0_n.BLIF sm_amiga_i_5__n.BLIF \ +vpa_sync_0_un3_n.BLIF state_machine_un8_clk_000_d2_i_n.BLIF \ +vpa_sync_0_un1_n.BLIF sm_amiga_i_7__n.BLIF vpa_sync_0_un0_n.BLIF a_i_0__n.BLIF \ +vma_int_0_un3_n.BLIF size_i_1__n.BLIF vma_int_0_un1_n.BLIF dsack_i_1__n.BLIF \ +vma_int_0_un0_n.BLIF CLK_000_D2_i.BLIF bgack_030_int_0_un3_n.BLIF \ +AS_030_000_SYNC_i.BLIF bgack_030_int_0_un1_n.BLIF a_i_30__n.BLIF \ +bgack_030_int_0_un0_n.BLIF a_i_31__n.BLIF as_000_int_0_un3_n.BLIF \ +a_i_28__n.BLIF as_000_int_0_un1_n.BLIF a_i_29__n.BLIF as_000_int_0_un0_n.BLIF \ +a_i_26__n.BLIF ipl_030_0_0__un3_n.BLIF a_i_27__n.BLIF ipl_030_0_0__un1_n.BLIF \ +a_i_24__n.BLIF ipl_030_0_0__un0_n.BLIF a_i_25__n.BLIF ipl_030_0_1__un3_n.BLIF \ +a_i_19__n.BLIF ipl_030_0_1__un1_n.BLIF a_i_16__n.BLIF ipl_030_0_1__un0_n.BLIF \ +a_i_18__n.BLIF ipl_030_0_2__un3_n.BLIF RST_i.BLIF ipl_030_0_2__un1_n.BLIF \ +ipl_030_0_2__un0_n.BLIF cpu_estse_0_un3_n.BLIF cpu_estse_0_un1_n.BLIF \ +CLK_OSZI_i.BLIF cpu_estse_0_un0_n.BLIF cpu_estse_1_un3_n.BLIF N_70_i.BLIF \ +cpu_estse_1_un1_n.BLIF N_72_i.BLIF cpu_estse_1_un0_n.BLIF FPU_CS_INT_i.BLIF \ +cpu_estse_2_un3_n.BLIF BGACK_030_INT_i.BLIF cpu_estse_2_un1_n.BLIF \ +CLK_000_D5_i.BLIF cpu_estse_2_un0_n.BLIF AS_030_c.BLIF \ +as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un1_n.BLIF \ +as_030_000_sync_0_un0_n.BLIF DS_030_c.BLIF dtack_sync_0_un3_n.BLIF \ +dtack_sync_0_un1_n.BLIF dtack_sync_0_un0_n.BLIF fpu_cs_int_0_un3_n.BLIF \ +size_c_0__n.BLIF fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF \ +size_c_1__n.BLIF dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un1_n.BLIF \ +a_c_0__n.BLIF dsack_int_0_1__un0_n.BLIF amiga_bus_enable_0_un3_n.BLIF \ +amiga_bus_enable_0_un1_n.BLIF amiga_bus_enable_0_un0_n.BLIF \ +uds_000_int_0_un3_n.BLIF uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF \ +a_15__n.BLIF a_14__n.BLIF a_13__n.BLIF a_12__n.BLIF a_11__n.BLIF \ +a_c_16__n.BLIF a_10__n.BLIF a_c_17__n.BLIF a_9__n.BLIF a_c_18__n.BLIF \ +a_8__n.BLIF a_c_19__n.BLIF a_7__n.BLIF a_c_20__n.BLIF a_6__n.BLIF \ +a_c_21__n.BLIF a_5__n.BLIF a_c_22__n.BLIF a_4__n.BLIF a_c_23__n.BLIF \ +a_3__n.BLIF a_c_24__n.BLIF a_2__n.BLIF a_c_25__n.BLIF a_1__n.BLIF \ +a_c_26__n.BLIF a_c_27__n.BLIF a_c_28__n.BLIF a_c_29__n.BLIF a_c_30__n.BLIF \ a_c_31__n.BLIF nEXP_SPACE_c.BLIF BG_030_c.BLIF BG_000DFFSHreg.BLIF \ -DSACK_1_.PIN.BLIF DTACK.PIN.BLIF +BGACK_000_c.BLIF CLK_030_c.BLIF DSACK_1_.PIN.BLIF DTACK.PIN.BLIF .outputs IPL_030_2_ AS_000 UDS_000 LDS_000 BERR BG_000 BGACK_030 CLK_DIV_OUT \ CLK_EXP FPU_CS AVEC AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR \ -AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ IPL_030DFFSH_0_reg.D \ -IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP IPL_030DFFSH_1_reg.D \ -IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D \ -IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D SM_AMIGA_7_.C \ -SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.D \ -SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_4_.AR \ +AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ cpu_est_2_.D cpu_est_2_.C \ +cpu_est_2_.AR cpu_est_3_reg.D cpu_est_3_reg.C cpu_est_3_reg.AR cpu_est_0_.D \ +cpu_est_0_.C cpu_est_0_.AR cpu_est_1_.D cpu_est_1_.C cpu_est_1_.AR \ SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C \ SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.D \ -SM_AMIGA_0_.C SM_AMIGA_0_.AR CLK_CNT_0_.D CLK_CNT_0_.C CLK_CNT_1_.D \ -CLK_CNT_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D \ -cpu_est_2_.C cpu_est_3_reg.D cpu_est_3_reg.C inst_UDS_000_INTreg.D \ -inst_UDS_000_INTreg.C inst_UDS_000_INTreg.AP inst_LDS_000_INTreg.D \ -inst_LDS_000_INTreg.C inst_LDS_000_INTreg.AP inst_VMA_INTreg.D \ -inst_VMA_INTreg.C inst_VMA_INTreg.AP BG_000DFFSHreg.D BG_000DFFSHreg.C \ -BG_000DFFSHreg.AP inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C \ -inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP \ -inst_AS_000_INTreg.D inst_AS_000_INTreg.C inst_AS_000_INTreg.AP \ -inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP \ -inst_DTACK_SYNC.D inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_FPU_CS_INTreg.D \ -inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP DSACK_INT_1_.D DSACK_INT_1_.C \ -DSACK_INT_1_.AP inst_VPA_SYNC.D inst_VPA_SYNC.C inst_VPA_SYNC.AP \ -AMIGA_BUS_ENABLEDFFreg.D AMIGA_BUS_ENABLEDFFreg.C inst_CLK_000_D5.D \ -inst_CLK_000_D5.C inst_DTACK_DMA.D inst_DTACK_DMA.C inst_DTACK_DMA.AP \ -CLK_OUT_INTreg.D CLK_OUT_INTreg.C inst_CLK_000_D4.D inst_CLK_000_D4.C \ -inst_CLK_000_D2.D inst_CLK_000_D2.C inst_CLK_000_D3.D inst_CLK_000_D3.C \ -inst_VPA_D.D inst_VPA_D.C inst_CLK_000_D0.D inst_CLK_000_D0.C RESETDFFreg.D \ -RESETDFFreg.C inst_CLK_000_D1.D inst_CLK_000_D1.C CLK_REF_1_.D CLK_REF_1_.LH \ -CLK_REF_1_.AR DSACK_1_ DTACK DSACK_0_ BGACK_000_c CLK_030_c CLK_OSZI_c \ -ipl_c_0__n ipl_c_1__n ipl_c_2__n vcc_n_n gnd_n_n dsack_c_1__n DTACK_c \ -AS_000_INT_1_sqmuxa state_machine_un8_clk_000_d2_n \ -state_machine_un23_clk_000_d0_n RST_c state_machine_un6_clk_000_d4_n \ -clk_clk_cnt_n RW_c fc_c_0__n state_machine_un6_bgack_000_n fc_c_1__n \ -state_machine_un7_as_000_int_n state_machine_un15_clk_000_d0_n \ -clk_cpu_est_11_0_1__n state_machine_lds_000_int_5_n N_124_i \ -state_machine_uds_000_int_5_n N_146_i un1_AMIGA_BUS_ENABLE_1_sqmuxa_2 N_121_i \ -N_122_i N_66_0 N_65_0 N_145_i un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 DS_030_c_i \ -N_63_i N_62_i state_machine_un6_clk_000_d4_i_n N_61_i N_60_i N_59_i N_58_i \ -N_57_i CLK_000_D1_i N_56_i N_55_i N_52_i N_141_i N_142_i N_14_0 N_85_i N_139_i \ -clk_cpu_est_11_1__n N_140_i clk_cpu_est_11_3__n sm_amiga_ns_0_0__n N_125_i \ -N_138_i N_162 N_178_i N_163 clk_cpu_est_11_0_3__n N_164 N_119_i N_165 N_43_i \ -N_30 N_117_i N_118_i N_51 N_123_i N_52 N_115_i N_55 N_116_i N_56 \ -sm_amiga_ns_0_7__n N_57 N_98_i N_58 N_114_i N_59 N_39_0 N_60 N_94_i N_61 \ -N_97_i N_62 sm_amiga_ns_0_5__n N_63 N_89_i N_65 N_90_i N_66 N_69 N_88_i N_72 \ -N_73 N_86_i N_74 N_75 N_83_i N_76 N_77 N_81_i N_79 \ -state_machine_lds_000_int_5_0_n N_81 state_machine_uds_000_int_5_0_n N_83 \ -N_79_i N_85 N_30_0 N_86 N_165_0 N_88 N_76_i N_89 N_164_0 N_90 N_163_0 N_94 \ -N_72_i N_97 N_73_i N_98 state_machine_un15_clk_000_d0_0_n N_114 N_162_0 N_115 \ -state_machine_un6_bgack_000_0_n N_116 state_machine_un23_clk_000_d0_i_n N_117 \ -N_188_1 N_118 N_188_2 N_119 N_188_3 N_120 N_188_4 N_121 N_188_5 N_122 N_188_6 \ -N_124 N_191_1 N_125 N_191_2 N_178 state_machine_un8_clk_000_d2_1_n N_138 \ -N_57_i_1 N_139 N_57_i_2 N_140 N_57_i_3 N_141 N_57_i_4 N_142 N_57_i_5 N_145 \ -clk_cpu_est_11_0_1_1__n N_146 clk_cpu_est_11_0_2_1__n N_77_1 N_120_1 N_188 \ -N_120_2 N_191 N_79_1 RW_i N_79_2 VPA_D_i N_77_1_0 CLK_000_D0_i N_75_1 \ -cpu_est_i_0__n N_75_2 cpu_est_i_3__n N_75_3 VMA_INT_i N_75_4 cpu_est_i_1__n \ -N_75_5 DTACK_i N_73_1 BG_030_i N_73_2 nEXP_SPACE_i N_72_1 sm_amiga_i_3__n \ -N_72_2 AS_000_INT_i sm_amiga_ns_0_1_0__n sm_amiga_i_6__n \ -clk_cpu_est_11_0_1_3__n cpu_est_i_2__n N_138_1 AMIGA_BUS_ENABLE_i N_119_1 \ -AS_030_i N_118_1 sm_amiga_i_4__n N_117_1 sm_amiga_i_5__n N_97_1 \ -state_machine_un8_clk_000_d2_i_n N_81_1 sm_amiga_i_7__n \ -state_machine_uds_000_int_5_0_m2_un3_n a_i_0__n \ -state_machine_uds_000_int_5_0_m2_un1_n size_i_1__n \ -state_machine_uds_000_int_5_0_m2_un0_n dsack_i_1__n vpa_sync_0_un3_n \ -clk_clk_cnt_i_n vpa_sync_0_un1_n clk_cnt_i_0__n vpa_sync_0_un0_n CLK_000_D2_i \ -amiga_bus_enable_0_un3_n AS_030_000_SYNC_i amiga_bus_enable_0_un1_n a_i_30__n \ -amiga_bus_enable_0_un0_n a_i_31__n uds_000_int_0_un3_n a_i_28__n \ -uds_000_int_0_un1_n a_i_29__n uds_000_int_0_un0_n a_i_26__n \ -lds_000_int_0_un3_n a_i_27__n lds_000_int_0_un1_n a_i_24__n \ -lds_000_int_0_un0_n a_i_25__n vma_int_0_un3_n a_i_19__n vma_int_0_un1_n \ -a_i_16__n vma_int_0_un0_n a_i_18__n bg_000_0_un3_n N_137_i bg_000_0_un1_n \ -bg_000_0_un0_n RST_i bgack_030_int_0_un3_n N_120_i bgack_030_int_0_un1_n \ -N_75_i bgack_030_int_0_un0_n N_74_i as_000_int_0_un3_n N_77_i \ -as_000_int_0_un1_n FPU_CS_INT_i as_000_int_0_un0_n BGACK_030_INT_i \ -cpu_est_0_1__un3_n CLK_000_D5_i cpu_est_0_1__un1_n AS_030_c cpu_est_0_1__un0_n \ -cpu_est_0_2__un3_n cpu_est_0_2__un1_n DS_030_c cpu_est_0_2__un0_n \ -cpu_est_0_3__un3_n cpu_est_0_3__un1_n cpu_est_0_3__un0_n size_c_0__n \ -ipl_030_0_0__un3_n ipl_030_0_0__un1_n size_c_1__n ipl_030_0_0__un0_n \ -ipl_030_0_1__un3_n a_c_0__n ipl_030_0_1__un1_n ipl_030_0_1__un0_n \ -ipl_030_0_2__un3_n ipl_030_0_2__un1_n ipl_030_0_2__un0_n \ -as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n \ -dtack_sync_0_un3_n dtack_sync_0_un1_n dtack_sync_0_un0_n fpu_cs_int_0_un3_n \ -fpu_cs_int_0_un1_n fpu_cs_int_0_un0_n dsack_int_0_1__un3_n \ -dsack_int_0_1__un1_n dsack_int_0_1__un0_n a_c_16__n a_15__n a_c_17__n a_14__n \ -a_c_18__n a_13__n a_c_19__n a_12__n a_c_20__n a_11__n a_c_21__n a_10__n \ -a_c_22__n a_9__n a_c_23__n a_8__n a_c_24__n a_7__n a_c_25__n a_6__n a_c_26__n \ -a_5__n a_c_27__n a_4__n a_c_28__n a_3__n a_c_29__n a_2__n a_c_30__n a_1__n \ -a_c_31__n nEXP_SPACE_c BG_030_c DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE \ -LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_OUT_PRE_0 G_92 G_96 +SM_AMIGA_0_.C SM_AMIGA_0_.AR CLK_CNT_N_0_.D CLK_CNT_N_0_.C CLK_CNT_N_0_.AR \ +CLK_CNT_N_1_.D CLK_CNT_N_1_.C CLK_CNT_N_1_.AR CLK_CNT_P_0_.D CLK_CNT_P_0_.C \ +CLK_CNT_P_0_.AR CLK_CNT_P_1_.D CLK_CNT_P_1_.C CLK_CNT_P_1_.AR \ +IPL_030DFFSH_0_reg.D IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP \ +IPL_030DFFSH_1_reg.D IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP \ +IPL_030DFFSH_2_reg.D IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D \ +SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR \ +SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C \ +SM_AMIGA_4_.AR inst_UDS_000_INTreg.D inst_UDS_000_INTreg.C \ +inst_UDS_000_INTreg.AP inst_LDS_000_INTreg.D inst_LDS_000_INTreg.C \ +inst_LDS_000_INTreg.AP inst_VPA_SYNC.D inst_VPA_SYNC.C inst_VPA_SYNC.AP \ +inst_VMA_INTreg.D inst_VMA_INTreg.C inst_VMA_INTreg.AP inst_BGACK_030_INTreg.D \ +inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP inst_AS_000_INTreg.D \ +inst_AS_000_INTreg.C inst_AS_000_INTreg.AP inst_CLK_OUT_PRE.D \ +inst_CLK_OUT_PRE.C inst_CLK_OUT_PRE.AR CLK_OUT_INTreg.D CLK_OUT_INTreg.C \ +CLK_OUT_INTreg.AR inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \ +inst_AS_030_000_SYNC.AP inst_DTACK_SYNC.D inst_DTACK_SYNC.C inst_DTACK_SYNC.AP \ +inst_FPU_CS_INTreg.D inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP DSACK_INT_1_.D \ +DSACK_INT_1_.C DSACK_INT_1_.AP AMIGA_BUS_ENABLEDFFreg.D \ +AMIGA_BUS_ENABLEDFFreg.C inst_DTACK_DMA.D inst_DTACK_DMA.C inst_DTACK_DMA.AP \ +inst_CLK_000_D5.D inst_CLK_000_D5.C inst_CLK_000_D5.AP BG_000DFFSHreg.D \ +BG_000DFFSHreg.C BG_000DFFSHreg.AP inst_CLK_000_D4.D inst_CLK_000_D4.C \ +inst_CLK_000_D4.AP inst_CLK_000_D2.D inst_CLK_000_D2.C inst_CLK_000_D2.AP \ +inst_CLK_000_D3.D inst_CLK_000_D3.C inst_CLK_000_D3.AP inst_VPA_D.D \ +inst_VPA_D.C inst_VPA_D.AP inst_CLK_000_D0.D inst_CLK_000_D0.C \ +inst_CLK_000_D0.AP RESETDFFRHreg.D RESETDFFRHreg.C RESETDFFRHreg.AR \ +inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_D1.AP DSACK_1_ DTACK DSACK_0_ \ +CLK_OSZI_c ipl_c_0__n ipl_c_1__n ipl_c_2__n dsack_c_1__n vcc_n_n DTACK_c \ +gnd_n_n AS_000_INT_1_sqmuxa state_machine_un8_clk_000_d2_n RST_c \ +state_machine_un23_clk_000_d0_n state_machine_un6_clk_000_d4_n RW_c \ +state_machine_un10_bg_030_n fc_c_0__n state_machine_un6_bgack_000_n fc_c_1__n \ +cpu_est_ns_0_1__n N_126_i N_128_i state_machine_un7_as_000_int_n N_216_i \ +state_machine_un15_clk_000_d0_n N_217_i state_machine_lds_000_int_5_n N_61_0 \ +state_machine_uds_000_int_5_n N_60_0 un1_AMIGA_BUS_ENABLE_1_sqmuxa_2 N_129_i \ +un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 DS_030_c_i N_58_i N_57_i N_55_i N_54_i \ +N_53_i N_50_i CLK_000_D1_i N_49_i N_48_i N_122_i N_123_i cpu_est_ns_e_0_0__n \ +N_79_i N_226_i N_227_i sm_amiga_ns_0_0__n N_222_i N_223_i N_225_i \ +cpu_est_ns_0_2__n N_221_i N_41_i N_127_i N_220_i cpu_est_ns_1__n N_157_i \ +cpu_est_ns_2__n N_214_i N_203 N_215_i N_204 sm_amiga_ns_0_7__n N_205 N_93_i \ +N_23 N_94_i N_27 N_47 N_85_i N_48 N_86_i N_49 sm_amiga_ns_0_5__n N_50 N_84_i \ +N_53 N_130_i N_54 N_55 N_82_i N_57 N_58 N_81_i N_60 N_61 N_77_i N_68 N_69 \ +N_75_i N_70 state_machine_lds_000_int_5_0_n N_71 \ +state_machine_uds_000_int_5_0_n N_72 N_73_i N_73 N_27_0 N_75 N_23_0 N_77 \ +N_71_i N_79 N_205_0 N_81 N_204_0 N_82 N_68_i N_84 N_69_i N_85 \ +state_machine_un15_clk_000_d0_0_n N_86 N_203_0 N_93 \ +state_machine_un6_bgack_000_0_n N_94 N_214 state_machine_un23_clk_000_d0_0_n \ +N_215 N_238_1 N_216 N_238_2 N_217 N_238_3 N_220 N_238_4 N_221 N_238_5 N_222 \ +N_238_6 N_223 N_241_1 N_225 N_241_2 N_226 state_machine_un8_clk_000_d2_1_n \ +N_227 N_53_i_1 N_122 N_53_i_2 N_123 N_53_i_3 N_126 N_53_i_4 N_127 N_53_i_5 \ +N_128 cpu_est_ns_0_1_1__n N_129 cpu_est_ns_0_2_1__n N_130 \ +state_machine_un10_bg_030_1_n N_238 state_machine_un10_bg_030_2_n N_241 \ +state_machine_un10_bg_030_3_n RW_i N_73_1 VMA_INT_i N_73_2 VPA_D_i N_72_1 \ +DTACK_i N_72_2 BG_030_i N_70_1 nEXP_SPACE_i N_70_2 CLK_000_D0_i N_70_3 \ +sm_amiga_i_4__n sm_amiga_ns_0_1_0__n cpu_est_i_3__n cpu_est_ns_0_1_2__n \ +sm_amiga_i_1__n N_221_1 state_machine_un6_clk_000_d4_i_n N_215_1 \ +sm_amiga_i_6__n N_75_1 AS_000_INT_i N_69_1 cpu_est_i_1__n N_68_1 \ +cpu_est_i_0__n state_machine_uds_000_int_5_0_m2_un3_n AMIGA_BUS_ENABLE_i \ +state_machine_uds_000_int_5_0_m2_un1_n AS_030_i \ +state_machine_uds_000_int_5_0_m2_un0_n cpu_est_i_2__n lds_000_int_0_un3_n \ +sm_amiga_i_2__n lds_000_int_0_un1_n sm_amiga_i_3__n lds_000_int_0_un0_n \ +sm_amiga_i_5__n vpa_sync_0_un3_n state_machine_un8_clk_000_d2_i_n \ +vpa_sync_0_un1_n sm_amiga_i_7__n vpa_sync_0_un0_n a_i_0__n vma_int_0_un3_n \ +size_i_1__n vma_int_0_un1_n dsack_i_1__n vma_int_0_un0_n CLK_000_D2_i \ +bgack_030_int_0_un3_n AS_030_000_SYNC_i bgack_030_int_0_un1_n a_i_30__n \ +bgack_030_int_0_un0_n a_i_31__n as_000_int_0_un3_n a_i_28__n \ +as_000_int_0_un1_n a_i_29__n as_000_int_0_un0_n a_i_26__n ipl_030_0_0__un3_n \ +a_i_27__n ipl_030_0_0__un1_n a_i_24__n ipl_030_0_0__un0_n a_i_25__n \ +ipl_030_0_1__un3_n a_i_19__n ipl_030_0_1__un1_n a_i_16__n ipl_030_0_1__un0_n \ +a_i_18__n ipl_030_0_2__un3_n RST_i ipl_030_0_2__un1_n ipl_030_0_2__un0_n \ +cpu_estse_0_un3_n cpu_estse_0_un1_n CLK_OSZI_i cpu_estse_0_un0_n \ +cpu_estse_1_un3_n N_70_i cpu_estse_1_un1_n N_72_i cpu_estse_1_un0_n \ +FPU_CS_INT_i cpu_estse_2_un3_n BGACK_030_INT_i cpu_estse_2_un1_n CLK_000_D5_i \ +cpu_estse_2_un0_n AS_030_c as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n \ +as_030_000_sync_0_un0_n DS_030_c dtack_sync_0_un3_n dtack_sync_0_un1_n \ +dtack_sync_0_un0_n fpu_cs_int_0_un3_n size_c_0__n fpu_cs_int_0_un1_n \ +fpu_cs_int_0_un0_n size_c_1__n dsack_int_0_1__un3_n dsack_int_0_1__un1_n \ +a_c_0__n dsack_int_0_1__un0_n amiga_bus_enable_0_un3_n \ +amiga_bus_enable_0_un1_n amiga_bus_enable_0_un0_n uds_000_int_0_un3_n \ +uds_000_int_0_un1_n uds_000_int_0_un0_n a_15__n a_14__n a_13__n a_12__n \ +a_11__n a_c_16__n a_10__n a_c_17__n a_9__n a_c_18__n a_8__n a_c_19__n a_7__n \ +a_c_20__n a_6__n a_c_21__n a_5__n a_c_22__n a_4__n a_c_23__n a_3__n a_c_24__n \ +a_2__n a_c_25__n a_1__n a_c_26__n a_c_27__n a_c_28__n a_c_29__n a_c_30__n \ +a_c_31__n nEXP_SPACE_c BG_030_c BGACK_000_c CLK_030_c DSACK_1_.OE DTACK.OE \ +AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE G_102 \ +G_108 +.names cpu_estse_1_un1_n.BLIF cpu_estse_1_un0_n.BLIF cpu_est_2_.D +1- 1 +-1 1 +.names cpu_estse_2_un1_n.BLIF cpu_estse_2_un0_n.BLIF cpu_est_3_reg.D +1- 1 +-1 1 +.names cpu_est_ns_e_0_0__n.BLIF cpu_est_0_.D +0 1 +.names cpu_estse_0_un1_n.BLIF cpu_estse_0_un0_n.BLIF cpu_est_1_.D +1- 1 +-1 1 +.names N_84_i.BLIF N_130_i.BLIF SM_AMIGA_3_.D +11 1 +.names sm_amiga_ns_0_5__n.BLIF SM_AMIGA_2_.D +0 1 +.names N_93_i.BLIF N_94_i.BLIF SM_AMIGA_1_.D +11 1 +.names sm_amiga_ns_0_7__n.BLIF SM_AMIGA_0_.D +0 1 +.names G_102.BLIF CLK_CNT_N_0_.D +0 1 +.names G_108.BLIF CLK_CNT_P_0_.D +0 1 .names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF IPL_030DFFSH_0_reg.D 1- 1 -1 1 @@ -276,45 +297,22 @@ LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_OUT_PRE_0 G_92 G_96 -1 1 .names sm_amiga_ns_0_0__n.BLIF SM_AMIGA_7_.D 0 1 -.names N_83_i.BLIF N_85_i.BLIF SM_AMIGA_6_.D +.names N_77_i.BLIF N_79_i.BLIF SM_AMIGA_6_.D 11 1 -.names inst_CLK_000_D0.BLIF N_86_i.BLIF SM_AMIGA_5_.D +.names inst_CLK_000_D0.BLIF N_81_i.BLIF SM_AMIGA_5_.D 11 1 -.names CLK_000_D0_i.BLIF N_88_i.BLIF SM_AMIGA_4_.D +.names CLK_000_D0_i.BLIF N_82_i.BLIF SM_AMIGA_4_.D 11 1 -.names N_89_i.BLIF N_90_i.BLIF SM_AMIGA_3_.D -11 1 -.names sm_amiga_ns_0_5__n.BLIF SM_AMIGA_2_.D -0 1 -.names N_39_0.BLIF SM_AMIGA_1_.D -0 1 -.names sm_amiga_ns_0_7__n.BLIF SM_AMIGA_0_.D -0 1 -.names clk_cnt_i_0__n.BLIF clk_clk_cnt_i_n.BLIF CLK_CNT_0_.D -11 1 -.names clk_clk_cnt_i_n.BLIF G_96.BLIF CLK_CNT_1_.D -11 1 -.names N_14_0.BLIF cpu_est_0_.D -0 1 -.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D -1- 1 --1 1 -.names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D -1- 1 --1 1 -.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_reg.D -1- 1 --1 1 .names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INTreg.D 1- 1 -1 1 .names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF inst_LDS_000_INTreg.D 1- 1 -1 1 -.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D +.names vpa_sync_0_un1_n.BLIF vpa_sync_0_un0_n.BLIF inst_VPA_SYNC.D 1- 1 -1 1 -.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF BG_000DFFSHreg.D +.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D 1- 1 -1 1 .names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF \ @@ -324,6 +322,8 @@ inst_BGACK_030_INTreg.D .names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF inst_AS_000_INTreg.D 1- 1 -1 1 +.names G_108.BLIF G_102.BLIF inst_CLK_OUT_PRE.D +11 1 .names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF \ inst_AS_030_000_SYNC.D 1- 1 @@ -337,15 +337,14 @@ inst_AS_030_000_SYNC.D .names dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF DSACK_INT_1_.D 1- 1 -1 1 -.names vpa_sync_0_un1_n.BLIF vpa_sync_0_un0_n.BLIF inst_VPA_SYNC.D -1- 1 --1 1 .names amiga_bus_enable_0_un1_n.BLIF amiga_bus_enable_0_un0_n.BLIF \ AMIGA_BUS_ENABLEDFFreg.D 1- 1 -1 1 .names state_machine_un7_as_000_int_n.BLIF inst_DTACK_DMA.D 0 1 +.names state_machine_un10_bg_030_n.BLIF BG_000DFFSHreg.D +0 1 .names vcc_n_n 1 .names gnd_n_n @@ -354,583 +353,541 @@ AMIGA_BUS_ENABLEDFFreg.D .names state_machine_un8_clk_000_d2_1_n.BLIF CLK_000_D2_i.BLIF \ state_machine_un8_clk_000_d2_n 11 1 -.names state_machine_un23_clk_000_d0_i_n.BLIF state_machine_un23_clk_000_d0_n +.names state_machine_un23_clk_000_d0_0_n.BLIF state_machine_un23_clk_000_d0_n 0 1 .names inst_CLK_000_D4.BLIF CLK_000_D5_i.BLIF state_machine_un6_clk_000_d4_n 11 1 -.names clk_cnt_i_0__n.BLIF N_137_i.BLIF clk_clk_cnt_n +.names state_machine_un10_bg_030_3_n.BLIF SM_AMIGA_7_.BLIF \ +state_machine_un10_bg_030_n 11 1 .names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n 0 1 +.names cpu_est_ns_0_1_1__n.BLIF cpu_est_ns_0_2_1__n.BLIF cpu_est_ns_0_1__n +11 1 +.names N_126.BLIF N_126_i +0 1 +.names N_128.BLIF N_128_i +0 1 .names AS_000_INT_i.BLIF dsack_i_1__n.BLIF state_machine_un7_as_000_int_n 11 1 +.names N_216.BLIF N_216_i +0 1 .names state_machine_un15_clk_000_d0_0_n.BLIF state_machine_un15_clk_000_d0_n 0 1 -.names clk_cpu_est_11_0_1_1__n.BLIF clk_cpu_est_11_0_2_1__n.BLIF \ -clk_cpu_est_11_0_1__n -11 1 +.names N_217.BLIF N_217_i +0 1 .names state_machine_lds_000_int_5_0_n.BLIF state_machine_lds_000_int_5_n 0 1 -.names N_124.BLIF N_124_i -0 1 +.names inst_CLK_000_D0.BLIF SM_AMIGA_4_.BLIF N_61_0 +11 1 .names state_machine_uds_000_int_5_0_n.BLIF state_machine_uds_000_int_5_n 0 1 -.names N_146.BLIF N_146_i -0 1 +.names CLK_000_D0_i.BLIF N_54_i.BLIF N_60_0 +11 1 .names un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2 0 1 -.names N_121.BLIF N_121_i +.names N_129.BLIF N_129_i 0 1 -.names N_122.BLIF N_122_i -0 1 -.names SM_AMIGA_3_.BLIF state_machine_un23_clk_000_d0_i_n.BLIF N_66_0 -11 1 -.names CLK_000_D0_i.BLIF N_58_i.BLIF N_65_0 -11 1 -.names N_145.BLIF N_145_i -0 1 -.names N_52_i.BLIF N_145_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 +.names N_50_i.BLIF N_129_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 11 1 .names DS_030_c.BLIF DS_030_c_i 0 1 -.names DS_030_c_i.BLIF N_51.BLIF N_63_i +.names DS_030_c_i.BLIF N_47.BLIF N_58_i 11 1 -.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_62_i +.names cpu_est_3_reg.BLIF cpu_est_i_1__n.BLIF N_57_i 11 1 -.names state_machine_un6_clk_000_d4_n.BLIF state_machine_un6_clk_000_d4_i_n -0 1 -.names CLK_000_D0_i.BLIF state_machine_un6_clk_000_d4_i_n.BLIF N_61_i +.names SM_AMIGA_1_.BLIF state_machine_un6_clk_000_d4_n.BLIF N_55_i 11 1 -.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF N_60_i +.names SM_AMIGA_6_.BLIF nEXP_SPACE_c.BLIF N_54_i 11 1 -.names inst_AS_000_INTreg.BLIF inst_CLK_000_D0.BLIF N_59_i +.names N_53_i_4.BLIF N_53_i_5.BLIF N_53_i 11 1 -.names SM_AMIGA_6_.BLIF nEXP_SPACE_c.BLIF N_58_i -11 1 -.names N_57_i_4.BLIF N_57_i_5.BLIF N_57_i +.names AS_030_i.BLIF N_55.BLIF N_50_i 11 1 .names inst_CLK_000_D1.BLIF CLK_000_D1_i 0 1 -.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF N_56_i +.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF N_49_i 11 1 -.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_55_i +.names inst_AS_000_INTreg.BLIF inst_CLK_000_D0.BLIF N_48_i 11 1 -.names AS_030_i.BLIF N_74_i.BLIF N_52_i -11 1 -.names N_141.BLIF N_141_i +.names N_122.BLIF N_122_i 0 1 -.names N_142.BLIF N_142_i +.names N_123.BLIF N_123_i 0 1 -.names N_141_i.BLIF N_142_i.BLIF N_14_0 -11 1 -.names N_85.BLIF N_85_i -0 1 -.names N_139.BLIF N_139_i -0 1 -.names clk_cpu_est_11_0_1__n.BLIF clk_cpu_est_11_1__n -0 1 -.names N_140.BLIF N_140_i -0 1 -.names clk_cpu_est_11_0_3__n.BLIF clk_cpu_est_11_3__n -0 1 -.names sm_amiga_ns_0_1_0__n.BLIF N_139_i.BLIF sm_amiga_ns_0_0__n -11 1 -.names N_125.BLIF N_125_i -0 1 -.names N_138.BLIF N_138_i -0 1 -.names N_162_0.BLIF N_162 -0 1 -.names N_178.BLIF N_178_i -0 1 -.names N_163_0.BLIF N_163 -0 1 -.names clk_cpu_est_11_0_1_3__n.BLIF N_138_i.BLIF clk_cpu_est_11_0_3__n -11 1 -.names N_164_0.BLIF N_164 -0 1 -.names N_119.BLIF N_119_i -0 1 -.names N_165_0.BLIF N_165 -0 1 -.names N_58.BLIF N_119_i.BLIF N_43_i -11 1 -.names N_30_0.BLIF N_30 -0 1 -.names N_117.BLIF N_117_i -0 1 -.names N_118.BLIF N_118_i -0 1 -.names state_machine_uds_000_int_5_0_m2_un1_n.BLIF \ -state_machine_uds_000_int_5_0_m2_un0_n.BLIF N_51 -1- 1 --1 1 -.names N_117_i.BLIF N_118_i.BLIF N_123_i -11 1 -.names N_52_i.BLIF N_52 -0 1 -.names N_115.BLIF N_115_i -0 1 -.names N_55_i.BLIF N_55 -0 1 -.names N_116.BLIF N_116_i -0 1 -.names N_56_i.BLIF N_56 -0 1 -.names N_115_i.BLIF N_116_i.BLIF sm_amiga_ns_0_7__n -11 1 -.names N_57_i.BLIF N_57 -0 1 -.names N_98.BLIF N_98_i -0 1 -.names N_58_i.BLIF N_58 -0 1 -.names N_114.BLIF N_114_i -0 1 -.names N_59_i.BLIF N_59 -0 1 -.names N_98_i.BLIF N_114_i.BLIF N_39_0 -11 1 -.names N_60_i.BLIF N_60 -0 1 -.names N_94.BLIF N_94_i -0 1 -.names N_61_i.BLIF N_61 -0 1 -.names N_97.BLIF N_97_i -0 1 -.names N_62_i.BLIF N_62 -0 1 -.names N_94_i.BLIF N_97_i.BLIF sm_amiga_ns_0_5__n -11 1 -.names N_63_i.BLIF N_63 -0 1 -.names N_89.BLIF N_89_i -0 1 -.names N_65_0.BLIF N_65 -0 1 -.names N_90.BLIF N_90_i -0 1 -.names N_66_0.BLIF N_66 -0 1 -.names BG_030_i.BLIF CLK_030_c.BLIF N_69 -11 1 -.names N_88.BLIF N_88_i -0 1 -.names N_72_1.BLIF N_72_2.BLIF N_72 -11 1 -.names N_73_1.BLIF N_73_2.BLIF N_73 -11 1 -.names N_86.BLIF N_86_i -0 1 -.names SM_AMIGA_1_.BLIF state_machine_un6_clk_000_d4_n.BLIF N_74 -11 1 -.names N_75_4.BLIF N_75_5.BLIF N_75 -11 1 -.names N_83.BLIF N_83_i -0 1 -.names CLK_030_c.BLIF N_57_i.BLIF N_76 -11 1 -.names N_77_1_0.BLIF inst_VPA_D.BLIF N_77 -11 1 -.names N_81.BLIF N_81_i -0 1 -.names N_79_1.BLIF N_79_2.BLIF N_79 -11 1 -.names N_63_i.BLIF N_81_i.BLIF state_machine_lds_000_int_5_0_n -11 1 -.names N_81_1.BLIF size_i_1__n.BLIF N_81 -11 1 -.names a_i_0__n.BLIF N_63_i.BLIF state_machine_uds_000_int_5_0_n -11 1 -.names N_65.BLIF sm_amiga_i_7__n.BLIF N_83 +.names N_122_i.BLIF N_123_i.BLIF cpu_est_ns_e_0_0__n 11 1 .names N_79.BLIF N_79_i 0 1 -.names SM_AMIGA_7_.BLIF state_machine_un8_clk_000_d2_i_n.BLIF N_85 -11 1 -.names N_79_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0.BLIF N_30_0 -11 1 -.names sm_amiga_i_5__n.BLIF sm_amiga_i_6__n.BLIF N_86 -11 1 -.names AS_030_i.BLIF N_77_i.BLIF N_165_0 -11 1 -.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_88 -11 1 -.names N_76.BLIF N_76_i +.names N_226.BLIF N_226_i 0 1 -.names CLK_000_D0_i.BLIF N_66.BLIF N_89 -11 1 -.names AS_030_i.BLIF N_76_i.BLIF N_164_0 -11 1 -.names sm_amiga_i_3__n.BLIF sm_amiga_i_4__n.BLIF N_90 -11 1 -.names AS_030_i.BLIF N_75_i.BLIF N_163_0 -11 1 -.names CLK_000_D0_i.BLIF SM_AMIGA_2_.BLIF N_94 -11 1 -.names N_72.BLIF N_72_i +.names N_227.BLIF N_227_i 0 1 -.names N_97_1.BLIF state_machine_un23_clk_000_d0_n.BLIF N_97 +.names sm_amiga_ns_0_1_0__n.BLIF N_226_i.BLIF sm_amiga_ns_0_0__n +11 1 +.names N_222.BLIF N_222_i +0 1 +.names N_223.BLIF N_223_i +0 1 +.names N_225.BLIF N_225_i +0 1 +.names cpu_est_ns_0_1_2__n.BLIF N_223_i.BLIF cpu_est_ns_0_2__n +11 1 +.names N_221.BLIF N_221_i +0 1 +.names N_54.BLIF N_221_i.BLIF N_41_i +11 1 +.names N_127.BLIF N_127_i +0 1 +.names N_220.BLIF N_220_i +0 1 +.names cpu_est_ns_0_1__n.BLIF cpu_est_ns_1__n +0 1 +.names N_127_i.BLIF N_220_i.BLIF N_157_i +11 1 +.names cpu_est_ns_0_2__n.BLIF cpu_est_ns_2__n +0 1 +.names N_214.BLIF N_214_i +0 1 +.names N_203_0.BLIF N_203 +0 1 +.names N_215.BLIF N_215_i +0 1 +.names N_204_0.BLIF N_204 +0 1 +.names N_214_i.BLIF N_215_i.BLIF sm_amiga_ns_0_7__n +11 1 +.names N_205_0.BLIF N_205 +0 1 +.names N_93.BLIF N_93_i +0 1 +.names N_23_0.BLIF N_23 +0 1 +.names N_94.BLIF N_94_i +0 1 +.names N_27_0.BLIF N_27 +0 1 +.names state_machine_uds_000_int_5_0_m2_un1_n.BLIF \ +state_machine_uds_000_int_5_0_m2_un0_n.BLIF N_47 +1- 1 +-1 1 +.names N_85.BLIF N_85_i +0 1 +.names N_48_i.BLIF N_48 +0 1 +.names N_86.BLIF N_86_i +0 1 +.names N_49_i.BLIF N_49 +0 1 +.names N_85_i.BLIF N_86_i.BLIF sm_amiga_ns_0_5__n +11 1 +.names N_50_i.BLIF N_50 +0 1 +.names N_84.BLIF N_84_i +0 1 +.names N_53_i.BLIF N_53 +0 1 +.names N_130.BLIF N_130_i +0 1 +.names N_54_i.BLIF N_54 +0 1 +.names N_55_i.BLIF N_55 +0 1 +.names N_82.BLIF N_82_i +0 1 +.names N_57_i.BLIF N_57 +0 1 +.names N_58_i.BLIF N_58 +0 1 +.names N_81.BLIF N_81_i +0 1 +.names N_60_0.BLIF N_60 +0 1 +.names N_61_0.BLIF N_61 +0 1 +.names N_77.BLIF N_77_i +0 1 +.names N_68_1.BLIF VPA_D_i.BLIF N_68 +11 1 +.names N_69_1.BLIF cpu_est_2_.BLIF N_69 +11 1 +.names N_75.BLIF N_75_i +0 1 +.names N_70_3.BLIF VPA_D_i.BLIF N_70 +11 1 +.names N_58_i.BLIF N_75_i.BLIF state_machine_lds_000_int_5_0_n +11 1 +.names CLK_030_c.BLIF N_53_i.BLIF N_71 +11 1 +.names a_i_0__n.BLIF N_58_i.BLIF state_machine_uds_000_int_5_0_n +11 1 +.names N_72_1.BLIF N_72_2.BLIF N_72 11 1 .names N_73.BLIF N_73_i 0 1 -.names N_61.BLIF SM_AMIGA_1_.BLIF N_98 +.names N_73_1.BLIF N_73_2.BLIF N_73 11 1 -.names N_72_i.BLIF N_73_i.BLIF state_machine_un15_clk_000_d0_0_n +.names N_73_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0.BLIF N_27_0 11 1 -.names inst_CLK_000_D0.BLIF SM_AMIGA_2_.BLIF N_114 +.names N_75_1.BLIF size_i_1__n.BLIF N_75 11 1 -.names AS_030_i.BLIF N_63.BLIF N_162_0 +.names AS_030_i.BLIF N_72_i.BLIF N_23_0 11 1 -.names N_59.BLIF SM_AMIGA_0_.BLIF N_115 +.names N_60.BLIF sm_amiga_i_7__n.BLIF N_77 11 1 -.names BGACK_000_c.BLIF N_56.BLIF state_machine_un6_bgack_000_0_n +.names N_71.BLIF N_71_i +0 1 +.names SM_AMIGA_7_.BLIF state_machine_un8_clk_000_d2_i_n.BLIF N_79 11 1 -.names N_61_i.BLIF SM_AMIGA_1_.BLIF N_116 +.names AS_030_i.BLIF N_71_i.BLIF N_205_0 +11 1 +.names sm_amiga_i_5__n.BLIF sm_amiga_i_6__n.BLIF N_81 +11 1 +.names AS_030_i.BLIF N_70_i.BLIF N_204_0 +11 1 +.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_82 +11 1 +.names N_68.BLIF N_68_i +0 1 +.names N_61.BLIF sm_amiga_i_3__n.BLIF N_84 +11 1 +.names N_69.BLIF N_69_i +0 1 +.names CLK_000_D0_i.BLIF SM_AMIGA_2_.BLIF N_85 +11 1 +.names N_68_i.BLIF N_69_i.BLIF state_machine_un15_clk_000_d0_0_n +11 1 +.names N_130.BLIF SM_AMIGA_3_.BLIF N_86 +11 1 +.names AS_030_i.BLIF N_58.BLIF N_203_0 +11 1 +.names CLK_000_D0_i.BLIF N_55.BLIF N_93 +11 1 +.names BGACK_000_c.BLIF N_49.BLIF state_machine_un6_bgack_000_0_n +11 1 +.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_94 +11 1 +.names N_48.BLIF SM_AMIGA_0_.BLIF N_214 11 1 .names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF \ -state_machine_un23_clk_000_d0_i_n +state_machine_un23_clk_000_d0_0_n 11 1 -.names N_117_1.BLIF cpu_est_i_3__n.BLIF N_117 +.names N_215_1.BLIF state_machine_un6_clk_000_d4_i_n.BLIF N_215 11 1 -.names a_i_24__n.BLIF a_i_25__n.BLIF N_188_1 +.names a_i_24__n.BLIF a_i_25__n.BLIF N_238_1 11 1 -.names N_118_1.BLIF cpu_est_i_2__n.BLIF N_118 +.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF N_216 11 1 -.names a_i_26__n.BLIF a_i_27__n.BLIF N_188_2 +.names a_i_26__n.BLIF a_i_27__n.BLIF N_238_2 11 1 -.names N_119_1.BLIF sm_amiga_i_6__n.BLIF N_119 +.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_217 11 1 -.names a_i_28__n.BLIF a_i_29__n.BLIF N_188_3 +.names a_i_28__n.BLIF a_i_29__n.BLIF N_238_3 11 1 -.names N_120_1.BLIF N_120_2.BLIF N_120 +.names N_57.BLIF cpu_est_2_.BLIF N_220 11 1 -.names a_i_30__n.BLIF a_i_31__n.BLIF N_188_4 +.names a_i_30__n.BLIF a_i_31__n.BLIF N_238_4 11 1 -.names N_60.BLIF cpu_est_i_0__n.BLIF N_121 +.names N_221_1.BLIF sm_amiga_i_6__n.BLIF N_221 11 1 -.names N_188_1.BLIF N_188_2.BLIF N_188_5 +.names N_238_1.BLIF N_238_2.BLIF N_238_5 11 1 -.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_122 +.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_222 11 1 -.names N_188_3.BLIF N_188_4.BLIF N_188_6 +.names N_238_3.BLIF N_238_4.BLIF N_238_6 11 1 -.names N_55_i.BLIF cpu_est_3_reg.BLIF N_124 +.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_223 11 1 -.names a_c_20__n.BLIF a_c_21__n.BLIF N_191_1 +.names a_c_20__n.BLIF a_c_21__n.BLIF N_241_1 11 1 -.names N_62.BLIF cpu_est_3_reg.BLIF N_125 +.names cpu_est_0_.BLIF cpu_est_3_reg.BLIF N_225 11 1 -.names a_c_22__n.BLIF a_c_23__n.BLIF N_191_2 +.names a_c_22__n.BLIF a_c_23__n.BLIF N_241_2 11 1 -.names N_62_i.BLIF cpu_est_i_2__n.BLIF N_178 +.names CLK_000_D0_i.BLIF N_129.BLIF N_226 11 1 .names inst_CLK_000_D3.BLIF AS_030_000_SYNC_i.BLIF \ state_machine_un8_clk_000_d2_1_n 11 1 -.names N_138_1.BLIF cpu_est_i_2__n.BLIF N_138 +.names N_48_i.BLIF SM_AMIGA_0_.BLIF N_227 11 1 -.names a_c_17__n.BLIF BGACK_000_c.BLIF N_57_i_1 +.names a_c_17__n.BLIF BGACK_000_c.BLIF N_53_i_1 11 1 -.names CLK_000_D0_i.BLIF N_145.BLIF N_139 +.names N_49.BLIF cpu_est_0_.BLIF N_122 11 1 -.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_57_i_2 +.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_53_i_2 11 1 -.names N_59_i.BLIF SM_AMIGA_0_.BLIF N_140 +.names N_49_i.BLIF cpu_est_i_0__n.BLIF N_123 11 1 -.names a_i_19__n.BLIF a_i_16__n.BLIF N_57_i_3 +.names a_i_19__n.BLIF a_i_16__n.BLIF N_53_i_3 11 1 -.names N_56.BLIF cpu_est_0_.BLIF N_141 +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_126 11 1 -.names N_57_i_1.BLIF N_57_i_2.BLIF N_57_i_4 +.names N_53_i_1.BLIF N_53_i_2.BLIF N_53_i_4 11 1 -.names N_56_i.BLIF cpu_est_i_0__n.BLIF N_142 +.names N_126.BLIF cpu_est_i_3__n.BLIF N_127 11 1 -.names N_57_i_3.BLIF a_i_18__n.BLIF N_57_i_5 +.names N_53_i_3.BLIF a_i_18__n.BLIF N_53_i_5 11 1 -.names SM_AMIGA_6_.BLIF nEXP_SPACE_i.BLIF N_145 +.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_128 11 1 -.names N_121_i.BLIF N_122_i.BLIF clk_cpu_est_11_0_1_1__n +.names N_126_i.BLIF N_128_i.BLIF cpu_est_ns_0_1_1__n 11 1 -.names N_60_i.BLIF cpu_est_0_.BLIF N_146 +.names SM_AMIGA_6_.BLIF nEXP_SPACE_i.BLIF N_129 11 1 -.names N_124_i.BLIF N_146_i.BLIF clk_cpu_est_11_0_2_1__n +.names N_216_i.BLIF N_217_i.BLIF cpu_est_ns_0_2_1__n 11 1 -.names inst_CLK_000_D0.BLIF SM_AMIGA_3_.BLIF N_77_1 +.names CLK_000_D0_i.BLIF state_machine_un23_clk_000_d0_n.BLIF N_130 11 1 -.names AS_030_c.BLIF BG_030_i.BLIF N_120_1 +.names nEXP_SPACE_i.BLIF AS_030_c.BLIF state_machine_un10_bg_030_1_n 11 1 -.names N_188_5.BLIF N_188_6.BLIF N_188 +.names N_238_5.BLIF N_238_6.BLIF N_238 11 1 -.names SM_AMIGA_7_.BLIF nEXP_SPACE_i.BLIF N_120_2 +.names BG_030_i.BLIF N_49_i.BLIF state_machine_un10_bg_030_2_n 11 1 -.names N_191_1.BLIF N_191_2.BLIF N_191 +.names N_241_1.BLIF N_241_2.BLIF N_241 11 1 -.names CLK_030_c.BLIF N_57.BLIF N_79_1 +.names state_machine_un10_bg_030_1_n.BLIF state_machine_un10_bg_030_2_n.BLIF \ +state_machine_un10_bg_030_3_n 11 1 .names RW_c.BLIF RW_i 0 1 -.names SM_AMIGA_7_.BLIF nEXP_SPACE_c.BLIF N_79_2 -11 1 -.names inst_VPA_D.BLIF VPA_D_i -0 1 -.names DTACK_i.BLIF N_77_1.BLIF N_77_1_0 -11 1 -.names inst_CLK_000_D0.BLIF CLK_000_D0_i -0 1 -.names N_77_1.BLIF VMA_INT_i.BLIF N_75_1 -11 1 -.names cpu_est_0_.BLIF cpu_est_i_0__n -0 1 -.names VPA_D_i.BLIF cpu_est_2_.BLIF N_75_2 -11 1 -.names cpu_est_3_reg.BLIF cpu_est_i_3__n -0 1 -.names cpu_est_3_reg.BLIF cpu_est_i_0__n.BLIF N_75_3 +.names CLK_030_c.BLIF N_53.BLIF N_73_1 11 1 .names inst_VMA_INTreg.BLIF VMA_INT_i 0 1 -.names N_75_1.BLIF N_75_2.BLIF N_75_4 +.names SM_AMIGA_7_.BLIF nEXP_SPACE_c.BLIF N_73_2 11 1 -.names cpu_est_1_.BLIF cpu_est_i_1__n +.names inst_VPA_D.BLIF VPA_D_i 0 1 -.names N_75_3.BLIF cpu_est_i_1__n.BLIF N_75_5 +.names inst_CLK_000_D0.BLIF DTACK_i.BLIF N_72_1 11 1 .names DTACK_c.BLIF DTACK_i 0 1 -.names N_55_i.BLIF N_59_i.BLIF N_73_1 +.names SM_AMIGA_3_.BLIF inst_VPA_D.BLIF N_72_2 11 1 .names BG_030_c.BLIF BG_030_i 0 1 -.names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF N_73_2 +.names inst_CLK_000_D0.BLIF N_57_i.BLIF N_70_1 11 1 .names nEXP_SPACE_c.BLIF nEXP_SPACE_i 0 1 -.names CLK_000_D0_i.BLIF N_146.BLIF N_72_1 +.names SM_AMIGA_3_.BLIF VMA_INT_i.BLIF N_70_2 11 1 -.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n +.names inst_CLK_000_D0.BLIF CLK_000_D0_i 0 1 -.names VPA_D_i.BLIF cpu_est_2_.BLIF N_72_2 -11 1 -.names inst_AS_000_INTreg.BLIF AS_000_INT_i -0 1 -.names N_140_i.BLIF N_85_i.BLIF sm_amiga_ns_0_1_0__n -11 1 -.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n -0 1 -.names N_178_i.BLIF N_125_i.BLIF clk_cpu_est_11_0_1_3__n -11 1 -.names cpu_est_2_.BLIF cpu_est_i_2__n -0 1 -.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_138_1 -11 1 -.names AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLE_i -0 1 -.names AMIGA_BUS_ENABLE_i.BLIF AS_030_i.BLIF N_119_1 -11 1 -.names AS_030_c.BLIF AS_030_i -0 1 -.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_118_1 +.names N_70_1.BLIF N_70_2.BLIF N_70_3 11 1 .names SM_AMIGA_4_.BLIF sm_amiga_i_4__n 0 1 -.names N_55.BLIF cpu_est_0_.BLIF N_117_1 +.names N_227_i.BLIF N_79_i.BLIF sm_amiga_ns_0_1_0__n 11 1 -.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +.names cpu_est_3_reg.BLIF cpu_est_i_3__n 0 1 -.names CLK_000_D0_i.BLIF SM_AMIGA_3_.BLIF N_97_1 +.names N_225_i.BLIF N_222_i.BLIF cpu_est_ns_0_1_2__n 11 1 -.names state_machine_un8_clk_000_d2_n.BLIF state_machine_un8_clk_000_d2_i_n +.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n 0 1 -.names a_i_0__n.BLIF size_c_0__n.BLIF N_81_1 +.names AMIGA_BUS_ENABLE_i.BLIF AS_030_i.BLIF N_221_1 11 1 -.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n +.names state_machine_un6_clk_000_d4_n.BLIF state_machine_un6_clk_000_d4_i_n +0 1 +.names CLK_000_D0_i.BLIF SM_AMIGA_1_.BLIF N_215_1 +11 1 +.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n +0 1 +.names a_i_0__n.BLIF size_c_0__n.BLIF N_75_1 +11 1 +.names inst_AS_000_INTreg.BLIF AS_000_INT_i +0 1 +.names N_48_i.BLIF N_127.BLIF N_69_1 +11 1 +.names cpu_est_1_.BLIF cpu_est_i_1__n +0 1 +.names CLK_000_D0_i.BLIF N_128.BLIF N_68_1 +11 1 +.names cpu_est_0_.BLIF cpu_est_i_0__n 0 1 .names RW_c.BLIF state_machine_uds_000_int_5_0_m2_un3_n 0 1 -.names a_c_0__n.BLIF a_i_0__n +.names AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLE_i 0 1 .names SM_AMIGA_5_.BLIF RW_c.BLIF state_machine_uds_000_int_5_0_m2_un1_n 11 1 -.names size_c_1__n.BLIF size_i_1__n +.names AS_030_c.BLIF AS_030_i 0 1 .names SM_AMIGA_4_.BLIF state_machine_uds_000_int_5_0_m2_un3_n.BLIF \ state_machine_uds_000_int_5_0_m2_un0_n 11 1 -.names dsack_c_1__n.BLIF dsack_i_1__n +.names cpu_est_2_.BLIF cpu_est_i_2__n 0 1 -.names N_163.BLIF vpa_sync_0_un3_n +.names N_203.BLIF lds_000_int_0_un3_n 0 1 -.names clk_clk_cnt_n.BLIF clk_clk_cnt_i_n +.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n 0 1 -.names N_75_i.BLIF N_163.BLIF vpa_sync_0_un1_n +.names state_machine_lds_000_int_5_n.BLIF N_203.BLIF lds_000_int_0_un1_n 11 1 -.names CLK_CNT_0_.BLIF clk_cnt_i_0__n -0 1 -.names inst_VPA_SYNC.BLIF vpa_sync_0_un3_n.BLIF vpa_sync_0_un0_n -11 1 -.names inst_CLK_000_D2.BLIF CLK_000_D2_i -0 1 -.names RST_c.BLIF amiga_bus_enable_0_un3_n -0 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i -0 1 -.names N_43_i.BLIF RST_c.BLIF amiga_bus_enable_0_un1_n -11 1 -.names a_c_30__n.BLIF a_i_30__n -0 1 -.names AMIGA_BUS_ENABLEDFFreg.BLIF amiga_bus_enable_0_un3_n.BLIF \ -amiga_bus_enable_0_un0_n -11 1 -.names a_c_31__n.BLIF a_i_31__n -0 1 -.names N_162.BLIF uds_000_int_0_un3_n -0 1 -.names a_c_28__n.BLIF a_i_28__n -0 1 -.names state_machine_uds_000_int_5_n.BLIF N_162.BLIF uds_000_int_0_un1_n -11 1 -.names a_c_29__n.BLIF a_i_29__n -0 1 -.names inst_UDS_000_INTreg.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n -11 1 -.names a_c_26__n.BLIF a_i_26__n -0 1 -.names N_162.BLIF lds_000_int_0_un3_n -0 1 -.names a_c_27__n.BLIF a_i_27__n -0 1 -.names state_machine_lds_000_int_5_n.BLIF N_162.BLIF lds_000_int_0_un1_n -11 1 -.names a_c_24__n.BLIF a_i_24__n +.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n 0 1 .names inst_LDS_000_INTreg.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n 11 1 -.names a_c_25__n.BLIF a_i_25__n +.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +0 1 +.names N_204.BLIF vpa_sync_0_un3_n +0 1 +.names state_machine_un8_clk_000_d2_n.BLIF state_machine_un8_clk_000_d2_i_n +0 1 +.names N_70_i.BLIF N_204.BLIF vpa_sync_0_un1_n +11 1 +.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n +0 1 +.names inst_VPA_SYNC.BLIF vpa_sync_0_un3_n.BLIF vpa_sync_0_un0_n +11 1 +.names a_c_0__n.BLIF a_i_0__n 0 1 .names state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un3_n 0 1 -.names a_c_19__n.BLIF a_i_19__n +.names size_c_1__n.BLIF size_i_1__n 0 1 -.names cpu_est_1_.BLIF state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un1_n +.names N_48_i.BLIF state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un1_n 11 1 -.names a_c_16__n.BLIF a_i_16__n +.names dsack_c_1__n.BLIF dsack_i_1__n 0 1 .names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n 11 1 -.names a_c_18__n.BLIF a_i_18__n -0 1 -.names N_69.BLIF bg_000_0_un3_n -0 1 -.names G_92.BLIF N_137_i -0 1 -.names BG_000DFFSHreg.BLIF N_69.BLIF bg_000_0_un1_n -11 1 -.names N_120_i.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n -11 1 -.names RST_c.BLIF RST_i +.names inst_CLK_000_D2.BLIF CLK_000_D2_i 0 1 .names state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n 0 1 -.names N_120.BLIF N_120_i +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i 0 1 .names BGACK_000_c.BLIF state_machine_un6_bgack_000_n.BLIF \ bgack_030_int_0_un1_n 11 1 -.names N_75.BLIF N_75_i +.names a_c_30__n.BLIF a_i_30__n 0 1 .names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \ bgack_030_int_0_un0_n 11 1 -.names N_74.BLIF N_74_i +.names a_c_31__n.BLIF a_i_31__n 0 1 .names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n 0 1 -.names N_77.BLIF N_77_i +.names a_c_28__n.BLIF a_i_28__n 0 1 .names inst_AS_000_INTreg.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n 11 1 -.names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i +.names a_c_29__n.BLIF a_i_29__n 0 1 .names sm_amiga_i_5__n.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n 11 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i +.names a_c_26__n.BLIF a_i_26__n 0 1 -.names N_56.BLIF cpu_est_0_1__un3_n +.names N_49.BLIF ipl_030_0_0__un3_n 0 1 -.names inst_CLK_000_D5.BLIF CLK_000_D5_i +.names a_c_27__n.BLIF a_i_27__n 0 1 -.names cpu_est_1_.BLIF N_56.BLIF cpu_est_0_1__un1_n +.names IPL_030DFFSH_0_reg.BLIF N_49.BLIF ipl_030_0_0__un1_n 11 1 -.names clk_cpu_est_11_1__n.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n -11 1 -.names N_56.BLIF cpu_est_0_2__un3_n +.names a_c_24__n.BLIF a_i_24__n 0 1 -.names cpu_est_2_.BLIF N_56.BLIF cpu_est_0_2__un1_n -11 1 -.names N_123_i.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n -11 1 -.names N_56.BLIF cpu_est_0_3__un3_n -0 1 -.names cpu_est_3_reg.BLIF N_56.BLIF cpu_est_0_3__un1_n -11 1 -.names clk_cpu_est_11_3__n.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n -11 1 -.names N_56.BLIF ipl_030_0_0__un3_n -0 1 -.names IPL_030DFFSH_0_reg.BLIF N_56.BLIF ipl_030_0_0__un1_n -11 1 .names ipl_c_0__n.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n 11 1 -.names N_56.BLIF ipl_030_0_1__un3_n +.names a_c_25__n.BLIF a_i_25__n 0 1 -.names IPL_030DFFSH_1_reg.BLIF N_56.BLIF ipl_030_0_1__un1_n +.names N_49.BLIF ipl_030_0_1__un3_n +0 1 +.names a_c_19__n.BLIF a_i_19__n +0 1 +.names IPL_030DFFSH_1_reg.BLIF N_49.BLIF ipl_030_0_1__un1_n 11 1 +.names a_c_16__n.BLIF a_i_16__n +0 1 .names ipl_c_1__n.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n 11 1 -.names N_56.BLIF ipl_030_0_2__un3_n +.names a_c_18__n.BLIF a_i_18__n 0 1 -.names IPL_030DFFSH_2_reg.BLIF N_56.BLIF ipl_030_0_2__un1_n +.names N_49.BLIF ipl_030_0_2__un3_n +0 1 +.names RST_c.BLIF RST_i +0 1 +.names IPL_030DFFSH_2_reg.BLIF N_49.BLIF ipl_030_0_2__un1_n 11 1 .names ipl_c_2__n.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n 11 1 -.names N_30.BLIF as_030_000_sync_0_un3_n +.names N_49.BLIF cpu_estse_0_un3_n 0 1 -.names un1_AMIGA_BUS_ENABLE_1_sqmuxa_2.BLIF N_30.BLIF as_030_000_sync_0_un1_n +.names cpu_est_1_.BLIF N_49.BLIF cpu_estse_0_un1_n +11 1 +.names CLK_OSZI_c.BLIF CLK_OSZI_i +0 1 +.names cpu_est_ns_1__n.BLIF cpu_estse_0_un3_n.BLIF cpu_estse_0_un0_n +11 1 +.names N_49.BLIF cpu_estse_1_un3_n +0 1 +.names N_70.BLIF N_70_i +0 1 +.names cpu_est_2_.BLIF N_49.BLIF cpu_estse_1_un1_n +11 1 +.names N_72.BLIF N_72_i +0 1 +.names cpu_est_ns_2__n.BLIF cpu_estse_1_un3_n.BLIF cpu_estse_1_un0_n +11 1 +.names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i +0 1 +.names N_49.BLIF cpu_estse_2_un3_n +0 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i +0 1 +.names cpu_est_3_reg.BLIF N_49.BLIF cpu_estse_2_un1_n +11 1 +.names inst_CLK_000_D5.BLIF CLK_000_D5_i +0 1 +.names N_157_i.BLIF cpu_estse_2_un3_n.BLIF cpu_estse_2_un0_n +11 1 +.names N_27.BLIF as_030_000_sync_0_un3_n +0 1 +.names un1_AMIGA_BUS_ENABLE_1_sqmuxa_2.BLIF N_27.BLIF as_030_000_sync_0_un1_n 11 1 .names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF \ as_030_000_sync_0_un0_n 11 1 -.names N_165.BLIF dtack_sync_0_un3_n +.names N_23.BLIF dtack_sync_0_un3_n 0 1 -.names N_77_i.BLIF N_165.BLIF dtack_sync_0_un1_n +.names N_72_i.BLIF N_23.BLIF dtack_sync_0_un1_n 11 1 .names inst_DTACK_SYNC.BLIF dtack_sync_0_un3_n.BLIF dtack_sync_0_un0_n 11 1 -.names N_164.BLIF fpu_cs_int_0_un3_n +.names N_205.BLIF fpu_cs_int_0_un3_n 0 1 -.names AS_030_c.BLIF N_164.BLIF fpu_cs_int_0_un1_n +.names AS_030_c.BLIF N_205.BLIF fpu_cs_int_0_un1_n 11 1 .names inst_FPU_CS_INTreg.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un0_n 11 1 -.names N_52.BLIF dsack_int_0_1__un3_n +.names N_50.BLIF dsack_int_0_1__un3_n 0 1 -.names N_74_i.BLIF N_52.BLIF dsack_int_0_1__un1_n +.names N_55.BLIF N_50.BLIF dsack_int_0_1__un1_n 11 1 .names DSACK_INT_1_.BLIF dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un0_n 11 1 -.names inst_CLK_OUT_PRE.BLIF clk_clk_cnt_n.BLIF CLK_OUT_PRE_0 +.names RST_c.BLIF amiga_bus_enable_0_un3_n +0 1 +.names N_41_i.BLIF RST_c.BLIF amiga_bus_enable_0_un1_n +11 1 +.names AMIGA_BUS_ENABLEDFFreg.BLIF amiga_bus_enable_0_un3_n.BLIF \ +amiga_bus_enable_0_un0_n +11 1 +.names N_203.BLIF uds_000_int_0_un3_n +0 1 +.names state_machine_uds_000_int_5_n.BLIF N_203.BLIF uds_000_int_0_un1_n +11 1 +.names inst_UDS_000_INTreg.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n +11 1 +.names CLK_CNT_N_0_.BLIF CLK_CNT_N_1_.BLIF G_102 01 1 10 1 11 0 00 0 -.names CLK_REF_1_.BLIF CLK_CNT_1_.BLIF G_92 -01 1 -10 1 -11 0 -00 0 -.names CLK_CNT_0_.BLIF CLK_CNT_1_.BLIF G_96 +.names CLK_CNT_P_0_.BLIF CLK_CNT_P_1_.BLIF G_108 01 1 10 1 11 0 @@ -977,7 +934,7 @@ as_030_000_sync_0_un0_n .names inst_VMA_INTreg.BLIF VMA 1 1 0 0 -.names RESETDFFreg.BLIF RESET +.names RESETDFFRHreg.BLIF RESET 1 1 0 0 .names AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLE @@ -989,7 +946,7 @@ as_030_000_sync_0_un0_n .names vcc_n_n.BLIF AMIGA_BUS_ENABLE_LOW 1 1 0 0 -.names N_191.BLIF CIIN +.names N_241.BLIF CIIN 1 1 0 0 .names IPL_030DFFSH_1_reg.BLIF IPL_030_1_ @@ -998,6 +955,84 @@ as_030_000_sync_0_un0_n .names IPL_030DFFSH_0_reg.BLIF IPL_030_0_ 1 1 0 0 +.names CLK_OSZI_c.BLIF cpu_est_2_.C +1 1 +0 0 +.names RST_i.BLIF cpu_est_2_.AR +1 1 +0 0 +.names CLK_OSZI_c.BLIF cpu_est_3_reg.C +1 1 +0 0 +.names RST_i.BLIF cpu_est_3_reg.AR +1 1 +0 0 +.names CLK_OSZI_c.BLIF cpu_est_0_.C +1 1 +0 0 +.names RST_i.BLIF cpu_est_0_.AR +1 1 +0 0 +.names CLK_OSZI_c.BLIF cpu_est_1_.C +1 1 +0 0 +.names RST_i.BLIF cpu_est_1_.AR +1 1 +0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C +1 1 +0 0 +.names RST_i.BLIF SM_AMIGA_3_.AR +1 1 +0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C +1 1 +0 0 +.names RST_i.BLIF SM_AMIGA_2_.AR +1 1 +0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C +1 1 +0 0 +.names RST_i.BLIF SM_AMIGA_1_.AR +1 1 +0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C +1 1 +0 0 +.names RST_i.BLIF SM_AMIGA_0_.AR +1 1 +0 0 +.names CLK_OSZI_i.BLIF CLK_CNT_N_0_.C +1 1 +0 0 +.names RST_i.BLIF CLK_CNT_N_0_.AR +1 1 +0 0 +.names CLK_CNT_N_0_.BLIF CLK_CNT_N_1_.D +1 1 +0 0 +.names CLK_OSZI_i.BLIF CLK_CNT_N_1_.C +1 1 +0 0 +.names RST_i.BLIF CLK_CNT_N_1_.AR +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_CNT_P_0_.C +1 1 +0 0 +.names RST_i.BLIF CLK_CNT_P_0_.AR +1 1 +0 0 +.names CLK_CNT_P_0_.BLIF CLK_CNT_P_1_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_CNT_P_1_.C +1 1 +0 0 +.names RST_i.BLIF CLK_CNT_P_1_.AR +1 1 +0 0 .names CLK_OSZI_c.BLIF IPL_030DFFSH_0_reg.C 1 1 0 0 @@ -1040,48 +1075,6 @@ as_030_000_sync_0_un0_n .names RST_i.BLIF SM_AMIGA_4_.AR 1 1 0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C -1 1 -0 0 -.names RST_i.BLIF SM_AMIGA_3_.AR -1 1 -0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C -1 1 -0 0 -.names RST_i.BLIF SM_AMIGA_2_.AR -1 1 -0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C -1 1 -0 0 -.names RST_i.BLIF SM_AMIGA_1_.AR -1 1 -0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C -1 1 -0 0 -.names RST_i.BLIF SM_AMIGA_0_.AR -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_CNT_0_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_CNT_1_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF cpu_est_0_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF cpu_est_1_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF cpu_est_2_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF cpu_est_3_reg.C -1 1 -0 0 .names CLK_OSZI_c.BLIF inst_UDS_000_INTreg.C 1 1 0 0 @@ -1094,24 +1087,18 @@ as_030_000_sync_0_un0_n .names RST_i.BLIF inst_LDS_000_INTreg.AP 1 1 0 0 +.names CLK_OSZI_c.BLIF inst_VPA_SYNC.C +1 1 +0 0 +.names RST_i.BLIF inst_VPA_SYNC.AP +1 1 +0 0 .names CLK_OSZI_c.BLIF inst_VMA_INTreg.C 1 1 0 0 .names RST_i.BLIF inst_VMA_INTreg.AP 1 1 0 0 -.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C -1 1 -0 0 -.names RST_i.BLIF BG_000DFFSHreg.AP -1 1 -0 0 -.names CLK_OUT_PRE_0.BLIF inst_CLK_OUT_PRE.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE.C -1 1 -0 0 .names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C 1 1 0 0 @@ -1124,6 +1111,21 @@ as_030_000_sync_0_un0_n .names RST_i.BLIF inst_AS_000_INTreg.AP 1 1 0 0 +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE.C +1 1 +0 0 +.names RST_i.BLIF inst_CLK_OUT_PRE.AR +1 1 +0 0 +.names inst_CLK_OUT_PRE.BLIF CLK_OUT_INTreg.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C +1 1 +0 0 +.names RST_i.BLIF CLK_OUT_INTreg.AR +1 1 +0 0 .names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C 1 1 0 0 @@ -1148,31 +1150,28 @@ as_030_000_sync_0_un0_n .names RST_i.BLIF DSACK_INT_1_.AP 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_VPA_SYNC.C -1 1 -0 0 -.names RST_i.BLIF inst_VPA_SYNC.AP -1 1 -0 0 .names CLK_OSZI_c.BLIF AMIGA_BUS_ENABLEDFFreg.C 1 1 0 0 -.names inst_CLK_000_D4.BLIF inst_CLK_000_D5.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_CLK_000_D5.C -1 1 -0 0 .names CLK_OSZI_c.BLIF inst_DTACK_DMA.C 1 1 0 0 .names RST_i.BLIF inst_DTACK_DMA.AP 1 1 0 0 -.names inst_CLK_OUT_PRE.BLIF CLK_OUT_INTreg.D +.names inst_CLK_000_D4.BLIF inst_CLK_000_D5.D 1 1 0 0 -.names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C +.names CLK_OSZI_c.BLIF inst_CLK_000_D5.C +1 1 +0 0 +.names RST_i.BLIF inst_CLK_000_D5.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C +1 1 +0 0 +.names RST_i.BLIF BG_000DFFSHreg.AP 1 1 0 0 .names inst_CLK_000_D3.BLIF inst_CLK_000_D4.D @@ -1181,34 +1180,52 @@ as_030_000_sync_0_un0_n .names CLK_OSZI_c.BLIF inst_CLK_000_D4.C 1 1 0 0 +.names RST_i.BLIF inst_CLK_000_D4.AP +1 1 +0 0 .names inst_CLK_000_D1.BLIF inst_CLK_000_D2.D 1 1 0 0 .names CLK_OSZI_c.BLIF inst_CLK_000_D2.C 1 1 0 0 +.names RST_i.BLIF inst_CLK_000_D2.AP +1 1 +0 0 .names inst_CLK_000_D2.BLIF inst_CLK_000_D3.D 1 1 0 0 .names CLK_OSZI_c.BLIF inst_CLK_000_D3.C 1 1 0 0 +.names RST_i.BLIF inst_CLK_000_D3.AP +1 1 +0 0 .names VPA.BLIF inst_VPA_D.D 1 1 0 0 .names CLK_OSZI_c.BLIF inst_VPA_D.C 1 1 0 0 +.names RST_i.BLIF inst_VPA_D.AP +1 1 +0 0 .names CLK_000.BLIF inst_CLK_000_D0.D 1 1 0 0 .names CLK_OSZI_c.BLIF inst_CLK_000_D0.C 1 1 0 0 -.names RST_c.BLIF RESETDFFreg.D +.names RST_i.BLIF inst_CLK_000_D0.AP 1 1 0 0 -.names CLK_OSZI_c.BLIF RESETDFFreg.C +.names vcc_n_n.BLIF RESETDFFRHreg.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF RESETDFFRHreg.C +1 1 +0 0 +.names RST_i.BLIF RESETDFFRHreg.AR 1 1 0 0 .names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D @@ -1217,13 +1234,7 @@ as_030_000_sync_0_un0_n .names CLK_OSZI_c.BLIF inst_CLK_000_D1.C 1 1 0 0 -.names gnd_n_n.BLIF CLK_REF_1_.D -1 1 -0 0 -.names gnd_n_n.BLIF CLK_REF_1_.LH -1 1 -0 0 -.names RST_i.BLIF CLK_REF_1_.AR +.names RST_i.BLIF inst_CLK_000_D1.AP 1 1 0 0 .names DSACK_INT_1_.BLIF DSACK_1_ @@ -1235,12 +1246,6 @@ as_030_000_sync_0_un0_n .names vcc_n_n.BLIF DSACK_0_ 1 1 0 0 -.names BGACK_000.BLIF BGACK_000_c -1 1 -0 0 -.names CLK_030.BLIF CLK_030_c -1 1 -0 0 .names CLK_OSZI.BLIF CLK_OSZI_c 1 1 0 0 @@ -1286,96 +1291,96 @@ as_030_000_sync_0_un0_n .names A_0_.BLIF a_c_0__n 1 1 0 0 -.names A_16_.BLIF a_c_16__n -1 1 -0 0 .names A_15_.BLIF a_15__n 1 1 0 0 -.names A_17_.BLIF a_c_17__n -1 1 -0 0 .names A_14_.BLIF a_14__n 1 1 0 0 -.names A_18_.BLIF a_c_18__n -1 1 -0 0 .names A_13_.BLIF a_13__n 1 1 0 0 -.names A_19_.BLIF a_c_19__n -1 1 -0 0 .names A_12_.BLIF a_12__n 1 1 0 0 -.names A_20_.BLIF a_c_20__n -1 1 -0 0 .names A_11_.BLIF a_11__n 1 1 0 0 -.names A_21_.BLIF a_c_21__n +.names A_16_.BLIF a_c_16__n 1 1 0 0 .names A_10_.BLIF a_10__n 1 1 0 0 -.names A_22_.BLIF a_c_22__n +.names A_17_.BLIF a_c_17__n 1 1 0 0 .names A_9_.BLIF a_9__n 1 1 0 0 -.names A_23_.BLIF a_c_23__n +.names A_18_.BLIF a_c_18__n 1 1 0 0 .names A_8_.BLIF a_8__n 1 1 0 0 -.names A_24_.BLIF a_c_24__n +.names A_19_.BLIF a_c_19__n 1 1 0 0 .names A_7_.BLIF a_7__n 1 1 0 0 -.names A_25_.BLIF a_c_25__n +.names A_20_.BLIF a_c_20__n 1 1 0 0 .names A_6_.BLIF a_6__n 1 1 0 0 -.names A_26_.BLIF a_c_26__n +.names A_21_.BLIF a_c_21__n 1 1 0 0 .names A_5_.BLIF a_5__n 1 1 0 0 -.names A_27_.BLIF a_c_27__n +.names A_22_.BLIF a_c_22__n 1 1 0 0 .names A_4_.BLIF a_4__n 1 1 0 0 -.names A_28_.BLIF a_c_28__n +.names A_23_.BLIF a_c_23__n 1 1 0 0 .names A_3_.BLIF a_3__n 1 1 0 0 -.names A_29_.BLIF a_c_29__n +.names A_24_.BLIF a_c_24__n 1 1 0 0 .names A_2_.BLIF a_2__n 1 1 0 0 -.names A_30_.BLIF a_c_30__n +.names A_25_.BLIF a_c_25__n 1 1 0 0 .names A_1_.BLIF a_1__n 1 1 0 0 +.names A_26_.BLIF a_c_26__n +1 1 +0 0 +.names A_27_.BLIF a_c_27__n +1 1 +0 0 +.names A_28_.BLIF a_c_28__n +1 1 +0 0 +.names A_29_.BLIF a_c_29__n +1 1 +0 0 +.names A_30_.BLIF a_c_30__n +1 1 +0 0 .names A_31_.BLIF a_c_31__n 1 1 0 0 @@ -1385,6 +1390,12 @@ as_030_000_sync_0_un0_n .names BG_030.BLIF BG_030_c 1 1 0 0 +.names BGACK_000.BLIF BGACK_000_c +1 1 +0 0 +.names CLK_030.BLIF CLK_030_c +1 1 +0 0 .names nEXP_SPACE_c.BLIF DSACK_1_.OE 1 1 0 0 @@ -1409,7 +1420,7 @@ as_030_000_sync_0_un0_n .names FPU_CS_INT_i.BLIF AVEC_EXP.OE 1 1 0 0 -.names N_188.BLIF CIIN.OE +.names N_238.BLIF CIIN.OE 1 1 0 0 .end diff --git a/Logic/68030_tk.bl3 b/Logic/68030_tk.bl3 index e3eb963..f5887dc 100644 --- a/Logic/68030_tk.bl3 +++ b/Logic/68030_tk.bl3 @@ -1,133 +1,110 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Sat May 24 11:44:09 2014 +#$ DATE Sat May 24 15:48:50 2014 #$ MODULE 68030_tk -#$ PINS 59 SIZE_1_ A_31_ IPL_030_2_ IPL_2_ DSACK_1_ FC_1_ AS_030 AS_000 DS_030 UDS_000 \ -# LDS_000 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 SIZE_0_ \ -# CLK_OSZI A_30_ CLK_DIV_OUT A_29_ CLK_EXP A_28_ FPU_CS A_27_ DTACK A_26_ AVEC A_25_ \ -# AVEC_EXP A_24_ E A_23_ VPA A_22_ VMA A_21_ RST A_20_ RESET A_19_ RW A_18_ AMIGA_BUS_ENABLE \ -# A_17_ AMIGA_BUS_DATA_DIR A_16_ AMIGA_BUS_ENABLE_LOW CIIN A_0_ IPL_030_1_ IPL_030_0_ \ -# IPL_1_ IPL_0_ DSACK_0_ FC_0_ -#$ NODES 41 inst_BGACK_030_INTreg inst_FPU_CS_INTreg cpu_est_3_reg \ -# inst_VMA_INTreg cpu_est_0_ CLK_OUT_INTreg cpu_est_1_ inst_AS_000_INTreg \ -# inst_AS_030_000_SYNC IPL_030DFFSH_0_reg inst_DTACK_SYNC inst_VPA_D \ -# IPL_030DFFSH_1_reg inst_VPA_SYNC inst_CLK_000_D0 IPL_030DFFSH_2_reg \ -# inst_CLK_000_D1 inst_CLK_000_D2 inst_CLK_000_D5 inst_CLK_OUT_PRE SM_AMIGA_6_ \ -# SM_AMIGA_5_ cpu_est_2_ CLK_REF_1_ inst_UDS_000_INTreg inst_LDS_000_INTreg \ -# DSACK_INT_1_ SM_AMIGA_7_ inst_CLK_000_D3 SM_AMIGA_4_ inst_CLK_000_D4 RESETDFFreg \ -# inst_DTACK_DMA CLK_CNT_0_ CLK_CNT_1_ SM_AMIGA_3_ SM_AMIGA_1_ SM_AMIGA_2_ \ -# AMIGA_BUS_ENABLEDFFreg SM_AMIGA_0_ BG_000DFFSHreg +#$ PINS 59 SIZE_1_ A_31_ IPL_030_2_ SIZE_0_ IPL_2_ A_30_ A_29_ DSACK_1_ A_28_ A_27_ \ +# FC_1_ A_26_ AS_030 A_25_ AS_000 A_24_ DS_030 A_23_ UDS_000 A_22_ LDS_000 A_21_ nEXP_SPACE \ +# A_20_ BERR A_19_ BG_030 A_18_ BG_000 A_17_ BGACK_030 A_16_ BGACK_000 CLK_030 CLK_000 \ +# CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS DTACK AVEC AVEC_EXP E VPA VMA RST RESET RW A_0_ \ +# AMIGA_BUS_ENABLE IPL_030_1_ AMIGA_BUS_DATA_DIR IPL_030_0_ AMIGA_BUS_ENABLE_LOW \ +# IPL_1_ CIIN IPL_0_ DSACK_0_ FC_0_ +#$ NODES 42 CLK_OUT_INTreg IPL_030DFFSH_0_reg inst_BGACK_030_INTreg \ +# inst_FPU_CS_INTreg IPL_030DFFSH_1_reg inst_VMA_INTreg inst_AS_000_INTreg \ +# IPL_030DFFSH_2_reg inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC \ +# inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2 inst_CLK_000_D5 SM_AMIGA_5_ \ +# SM_AMIGA_6_ inst_UDS_000_INTreg inst_LDS_000_INTreg DSACK_INT_1_ inst_CLK_000_D3 \ +# SM_AMIGA_4_ RESETDFFRHreg inst_CLK_000_D4 inst_DTACK_DMA SM_AMIGA_7_ SM_AMIGA_3_ \ +# SM_AMIGA_1_ AMIGA_BUS_ENABLEDFFreg CLK_CNT_N_0_ CLK_CNT_N_1_ CLK_CNT_P_0_ \ +# CLK_CNT_P_1_ SM_AMIGA_2_ SM_AMIGA_0_ inst_CLK_OUT_PRE cpu_est_0_ cpu_est_1_ \ +# cpu_est_2_ cpu_est_3_reg BG_000DFFSHreg .model bus68030 .inputs SIZE_1_.BLIF A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF AS_030.BLIF DS_030.BLIF \ nEXP_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF \ CLK_OSZI.BLIF VPA.BLIF RST.BLIF RW.BLIF SIZE_0_.BLIF A_30_.BLIF A_29_.BLIF \ A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF \ A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF A_0_.BLIF \ -IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF inst_BGACK_030_INTreg.BLIF \ -inst_FPU_CS_INTreg.BLIF cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF \ -cpu_est_0_.BLIF CLK_OUT_INTreg.BLIF cpu_est_1_.BLIF inst_AS_000_INTreg.BLIF \ -inst_AS_030_000_SYNC.BLIF IPL_030DFFSH_0_reg.BLIF inst_DTACK_SYNC.BLIF \ -inst_VPA_D.BLIF IPL_030DFFSH_1_reg.BLIF inst_VPA_SYNC.BLIF \ -inst_CLK_000_D0.BLIF IPL_030DFFSH_2_reg.BLIF inst_CLK_000_D1.BLIF \ -inst_CLK_000_D2.BLIF inst_CLK_000_D5.BLIF inst_CLK_OUT_PRE.BLIF \ -SM_AMIGA_6_.BLIF SM_AMIGA_5_.BLIF cpu_est_2_.BLIF CLK_REF_1_.BLIF \ +IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF CLK_OUT_INTreg.BLIF IPL_030DFFSH_0_reg.BLIF \ +inst_BGACK_030_INTreg.BLIF inst_FPU_CS_INTreg.BLIF IPL_030DFFSH_1_reg.BLIF \ +inst_VMA_INTreg.BLIF inst_AS_000_INTreg.BLIF IPL_030DFFSH_2_reg.BLIF \ +inst_AS_030_000_SYNC.BLIF inst_DTACK_SYNC.BLIF inst_VPA_D.BLIF \ +inst_VPA_SYNC.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF \ +inst_CLK_000_D2.BLIF inst_CLK_000_D5.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_6_.BLIF \ inst_UDS_000_INTreg.BLIF inst_LDS_000_INTreg.BLIF DSACK_INT_1_.BLIF \ -SM_AMIGA_7_.BLIF inst_CLK_000_D3.BLIF SM_AMIGA_4_.BLIF inst_CLK_000_D4.BLIF \ -RESETDFFreg.BLIF inst_DTACK_DMA.BLIF CLK_CNT_0_.BLIF CLK_CNT_1_.BLIF \ -SM_AMIGA_3_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_2_.BLIF AMIGA_BUS_ENABLEDFFreg.BLIF \ -SM_AMIGA_0_.BLIF BG_000DFFSHreg.BLIF DSACK_1_.PIN.BLIF DTACK.PIN.BLIF +inst_CLK_000_D3.BLIF SM_AMIGA_4_.BLIF RESETDFFRHreg.BLIF inst_CLK_000_D4.BLIF \ +inst_DTACK_DMA.BLIF SM_AMIGA_7_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_1_.BLIF \ +AMIGA_BUS_ENABLEDFFreg.BLIF CLK_CNT_N_0_.BLIF CLK_CNT_N_1_.BLIF \ +CLK_CNT_P_0_.BLIF CLK_CNT_P_1_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_0_.BLIF \ +inst_CLK_OUT_PRE.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF \ +cpu_est_3_reg.BLIF BG_000DFFSHreg.BLIF DSACK_1_.PIN.BLIF DTACK.PIN.BLIF .outputs IPL_030_2_ AS_000 UDS_000 LDS_000 BERR BG_000 BGACK_030 CLK_DIV_OUT \ CLK_EXP FPU_CS AVEC AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR \ -AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ IPL_030DFFSH_0_reg.D \ +AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ cpu_est_2_.D cpu_est_2_.C \ +cpu_est_2_.AR cpu_est_3_reg.C cpu_est_3_reg.AR cpu_est_0_.D cpu_est_0_.C \ +cpu_est_0_.AR cpu_est_1_.D cpu_est_1_.C cpu_est_1_.AR SM_AMIGA_3_.D \ +SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR \ +SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C \ +SM_AMIGA_0_.AR CLK_CNT_N_0_.D CLK_CNT_N_0_.C CLK_CNT_N_0_.AR CLK_CNT_N_1_.D \ +CLK_CNT_N_1_.C CLK_CNT_N_1_.AR CLK_CNT_P_0_.D CLK_CNT_P_0_.C CLK_CNT_P_0_.AR \ +CLK_CNT_P_1_.D CLK_CNT_P_1_.C CLK_CNT_P_1_.AR IPL_030DFFSH_0_reg.D \ IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP IPL_030DFFSH_1_reg.D \ IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D \ IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D SM_AMIGA_7_.C \ SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.D \ SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_4_.AR \ -SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C \ -SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.D \ -SM_AMIGA_0_.C SM_AMIGA_0_.AR CLK_CNT_0_.D CLK_CNT_0_.C CLK_CNT_1_.D \ -CLK_CNT_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D \ -cpu_est_2_.C cpu_est_3_reg.C inst_UDS_000_INTreg.D inst_UDS_000_INTreg.C \ -inst_UDS_000_INTreg.AP inst_LDS_000_INTreg.D inst_LDS_000_INTreg.C \ -inst_LDS_000_INTreg.AP inst_VMA_INTreg.C inst_VMA_INTreg.AP BG_000DFFSHreg.D \ -BG_000DFFSHreg.C BG_000DFFSHreg.AP inst_CLK_OUT_PRE.C inst_BGACK_030_INTreg.D \ -inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP inst_AS_000_INTreg.D \ -inst_AS_000_INTreg.C inst_AS_000_INTreg.AP inst_AS_030_000_SYNC.D \ -inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_DTACK_SYNC.D \ -inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_FPU_CS_INTreg.D inst_FPU_CS_INTreg.C \ -inst_FPU_CS_INTreg.AP DSACK_INT_1_.D DSACK_INT_1_.C DSACK_INT_1_.AP \ -inst_VPA_SYNC.D inst_VPA_SYNC.C inst_VPA_SYNC.AP AMIGA_BUS_ENABLEDFFreg.D \ -AMIGA_BUS_ENABLEDFFreg.C inst_CLK_000_D5.D inst_CLK_000_D5.C inst_DTACK_DMA.D \ -inst_DTACK_DMA.C inst_DTACK_DMA.AP CLK_OUT_INTreg.D CLK_OUT_INTreg.C \ -inst_CLK_000_D4.D inst_CLK_000_D4.C inst_CLK_000_D2.D inst_CLK_000_D2.C \ -inst_CLK_000_D3.D inst_CLK_000_D3.C inst_VPA_D.D inst_VPA_D.C \ -inst_CLK_000_D0.D inst_CLK_000_D0.C RESETDFFreg.D RESETDFFreg.C \ -inst_CLK_000_D1.D inst_CLK_000_D1.C CLK_REF_1_.D CLK_REF_1_.LH CLK_REF_1_.AR \ -DSACK_1_ DTACK DSACK_0_ DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE \ -BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE cpu_est_3_reg.D.X1 cpu_est_3_reg.D.X2 \ -inst_VMA_INTreg.D.X1 inst_VMA_INTreg.D.X2 inst_CLK_OUT_PRE.D.X1 \ -inst_CLK_OUT_PRE.D.X2 -.names IPL_0_.BLIF IPL_030DFFSH_0_reg.BLIF inst_CLK_000_D0.BLIF \ -inst_CLK_000_D1.BLIF IPL_030DFFSH_0_reg.D -1-10 1 --10- 1 --1-1 1 -0-10 0 --00- 0 --0-1 0 -.names IPL_1_.BLIF IPL_030DFFSH_1_reg.BLIF inst_CLK_000_D0.BLIF \ -inst_CLK_000_D1.BLIF IPL_030DFFSH_1_reg.D -1-10 1 --10- 1 --1-1 1 -0-10 0 --00- 0 --0-1 0 -.names IPL_2_.BLIF inst_CLK_000_D0.BLIF IPL_030DFFSH_2_reg.BLIF \ -inst_CLK_000_D1.BLIF IPL_030DFFSH_2_reg.D -11-0 1 --01- 1 ---11 1 -01-0 0 --00- 0 ---01 0 -.names nEXP_SPACE.BLIF inst_AS_000_INTreg.BLIF inst_AS_030_000_SYNC.BLIF \ -inst_CLK_000_D0.BLIF inst_CLK_000_D2.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_7_.BLIF \ -inst_CLK_000_D3.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_7_.D -0--0-1--- 1 --1-1----1 1 -------10- 1 -----1-1-- 1 ---1---1-- 1 --0010--1- 0 ---0000-1- 0 -1-000--1- 0 ---010--10 0 --0-1--0-- 0 ----0-00-- 0 -1--0--0-- 0 ----1--0-0 0 -.names nEXP_SPACE.BLIF inst_AS_030_000_SYNC.BLIF inst_CLK_000_D0.BLIF \ -inst_CLK_000_D2.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_7_.BLIF inst_CLK_000_D3.BLIF \ -SM_AMIGA_6_.D --0-0-11 1 -1-0-10- 1 ----1-1- 0 --1---1- 0 -----00- 0 ---1--0- 0 -0----0- 0 ------10 0 -.names inst_CLK_000_D0.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_5_.D -11- 1 -1-1 1 --00 0 -0-- 0 -.names inst_CLK_000_D0.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_4_.D -01- 1 +inst_UDS_000_INTreg.D inst_UDS_000_INTreg.C inst_UDS_000_INTreg.AP \ +inst_LDS_000_INTreg.D inst_LDS_000_INTreg.C inst_LDS_000_INTreg.AP \ +inst_VPA_SYNC.D inst_VPA_SYNC.C inst_VPA_SYNC.AP inst_VMA_INTreg.C \ +inst_VMA_INTreg.AP inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C \ +inst_BGACK_030_INTreg.AP inst_AS_000_INTreg.D inst_AS_000_INTreg.C \ +inst_AS_000_INTreg.AP inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C \ +inst_CLK_OUT_PRE.AR CLK_OUT_INTreg.D CLK_OUT_INTreg.C CLK_OUT_INTreg.AR \ +inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP \ +inst_DTACK_SYNC.D inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_FPU_CS_INTreg.D \ +inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP DSACK_INT_1_.D DSACK_INT_1_.C \ +DSACK_INT_1_.AP AMIGA_BUS_ENABLEDFFreg.D AMIGA_BUS_ENABLEDFFreg.C \ +inst_DTACK_DMA.D inst_DTACK_DMA.C inst_DTACK_DMA.AP inst_CLK_000_D5.D \ +inst_CLK_000_D5.C inst_CLK_000_D5.AP BG_000DFFSHreg.D BG_000DFFSHreg.C \ +BG_000DFFSHreg.AP inst_CLK_000_D4.D inst_CLK_000_D4.C inst_CLK_000_D4.AP \ +inst_CLK_000_D2.D inst_CLK_000_D2.C inst_CLK_000_D2.AP inst_CLK_000_D3.D \ +inst_CLK_000_D3.C inst_CLK_000_D3.AP inst_VPA_D.D inst_VPA_D.C inst_VPA_D.AP \ +inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_D0.AP RESETDFFRHreg.D \ +RESETDFFRHreg.C RESETDFFRHreg.AR inst_CLK_000_D1.D inst_CLK_000_D1.C \ +inst_CLK_000_D1.AP DSACK_1_ DTACK DSACK_0_ DSACK_1_.OE DTACK.OE AS_000.OE \ +UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE \ +inst_VMA_INTreg.D.X1 inst_VMA_INTreg.D.X2 cpu_est_3_reg.D.X1 \ +cpu_est_3_reg.D.X2 +.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF cpu_est_0_.BLIF \ +cpu_est_1_.BLIF cpu_est_2_.BLIF cpu_est_3_reg.BLIF cpu_est_2_.D +1000-- 1 +---11- 1 +101--1 1 +-1--1- 1 +0---1- 1 +--1-00 0 +1010-0 0 +--010- 0 +-1--0- 0 +0---0- 0 +.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF cpu_est_0_.BLIF cpu_est_0_.D +100 1 +-11 1 0-1 1 --00 0 -1-- 0 +101 0 +-10 0 +0-0 0 +.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF cpu_est_0_.BLIF \ +cpu_est_1_.BLIF cpu_est_2_.BLIF cpu_est_3_reg.BLIF cpu_est_1_.D +1010-- 1 +--01-- 1 +10--00 1 +10--11 1 +-1-1-- 1 +0--1-- 1 +101110 0 +101101 0 +--0010 0 +--0001 0 +-1-0-- 0 +0--0-- 0 .names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D0.BLIF \ SM_AMIGA_4_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_3_.D --11- 1 @@ -164,52 +141,77 @@ inst_CLK_000_D4.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_0_.D --01-0 0 ----00 0 -1---0 0 -.names CLK_REF_1_.BLIF CLK_CNT_0_.BLIF CLK_CNT_1_.BLIF CLK_CNT_0_.D -100 1 -001 1 -0-0 0 -1-1 0 --1- 0 -.names CLK_REF_1_.BLIF CLK_CNT_0_.BLIF CLK_CNT_1_.BLIF CLK_CNT_1_.D -001 1 --10 1 -1-1 0 --00 0 --11 0 -.names cpu_est_0_.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF cpu_est_0_.D -010 1 -10- 1 +.names CLK_CNT_N_0_.BLIF CLK_CNT_N_1_.BLIF CLK_CNT_N_0_.D +00 1 +11 1 +10 0 +01 0 +.names CLK_CNT_P_0_.BLIF CLK_CNT_P_1_.BLIF CLK_CNT_P_0_.D +00 1 +11 1 +10 0 +01 0 +.names IPL_0_.BLIF IPL_030DFFSH_0_reg.BLIF inst_CLK_000_D0.BLIF \ +inst_CLK_000_D1.BLIF IPL_030DFFSH_0_reg.D +1-10 1 +-10- 1 +-1-1 1 +0-10 0 +-00- 0 +-0-1 0 +.names IPL_1_.BLIF IPL_030DFFSH_1_reg.BLIF inst_CLK_000_D0.BLIF \ +inst_CLK_000_D1.BLIF IPL_030DFFSH_1_reg.D +1-10 1 +-10- 1 +-1-1 1 +0-10 0 +-00- 0 +-0-1 0 +.names IPL_2_.BLIF IPL_030DFFSH_2_reg.BLIF inst_CLK_000_D0.BLIF \ +inst_CLK_000_D1.BLIF IPL_030DFFSH_2_reg.D +1-10 1 +-10- 1 +-1-1 1 +0-10 0 +-00- 0 +-0-1 0 +.names nEXP_SPACE.BLIF inst_AS_000_INTreg.BLIF inst_AS_030_000_SYNC.BLIF \ +inst_CLK_000_D0.BLIF inst_CLK_000_D2.BLIF SM_AMIGA_6_.BLIF \ +inst_CLK_000_D3.BLIF SM_AMIGA_7_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_7_.D +0--0-1--- 1 +-1-1----1 1 +------01- 1 +----1--1- 1 +--1----1- 1 +-0010-1-- 0 +--00001-- 0 +1-000-1-- 0 +--010-1-0 0 +-0-1---0- 0 +---0-0-0- 0 +1--0---0- 0 +---1---00 0 +.names nEXP_SPACE.BLIF inst_AS_030_000_SYNC.BLIF inst_CLK_000_D0.BLIF \ +inst_CLK_000_D2.BLIF SM_AMIGA_6_.BLIF inst_CLK_000_D3.BLIF SM_AMIGA_7_.BLIF \ +SM_AMIGA_6_.D +1-0-1-0 1 +-0-0-11 1 +----0-0 0 +--1---0 0 +0-----0 0 +-----01 0 +---1--1 0 +-1----1 0 +.names inst_CLK_000_D0.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_5_.D +11- 1 1-1 1 -110 0 -00- 0 -0-1 0 -.names cpu_est_3_reg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_CLK_000_D0.BLIF \ -inst_CLK_000_D1.BLIF cpu_est_2_.BLIF cpu_est_1_.D -0--100 1 -01010- 1 -10-10- 1 --01--- 1 -1-1--1 1 ---1-1- 1 ---10-- 1 -011101 0 -11-100 0 -000--1 0 -110--- 0 ---0-1- 0 ---00-- 0 -.names cpu_est_3_reg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_CLK_000_D0.BLIF \ -inst_CLK_000_D1.BLIF cpu_est_2_.BLIF cpu_est_2_.D --0010- 1 -11-10- 1 ---1--1 1 -----11 1 ----0-1 1 -0-1--0 0 -01010- 0 --01--0 0 -----10 0 ----0-0 0 +-00 0 +0-- 0 +.names inst_CLK_000_D0.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_4_.D +01- 1 +0-1 1 +-00 0 +1-- 0 .names AS_030.BLIF DS_030.BLIF RW.BLIF A_0_.BLIF SM_AMIGA_5_.BLIF \ inst_UDS_000_INTreg.BLIF SM_AMIGA_4_.BLIF inst_UDS_000_INTreg.D -0111-- 1 @@ -245,15 +247,23 @@ inst_LDS_000_INTreg.D --00-1--1 0 --000---1 0 1-00----1 0 -.names AS_030.BLIF nEXP_SPACE.BLIF BG_030.BLIF CLK_030.BLIF SM_AMIGA_7_.BLIF \ -BG_000DFFSHreg.BLIF BG_000DFFSHreg.D ----1-1 1 ----00- 1 --1-0-- 1 -0--0-- 1 ---1--- 1 -10001- 0 ---01-0 0 +.names AS_030.BLIF inst_VMA_INTreg.BLIF inst_VPA_D.BLIF inst_VPA_SYNC.BLIF \ +inst_CLK_000_D0.BLIF SM_AMIGA_3_.BLIF cpu_est_1_.BLIF cpu_est_3_reg.BLIF \ +inst_VPA_SYNC.D +---1--1- 1 +---1-0-- 1 +---10--- 1 +--11---- 1 +-1-1---- 1 +---1---0 1 +1-----1- 1 +1----0-- 1 +1---0--- 1 +1-1----- 1 +11------ 1 +1------0 1 +-00-1101 0 +0--0---- 0 .names BGACK_000.BLIF inst_BGACK_030_INTreg.BLIF inst_CLK_000_D0.BLIF \ inst_CLK_000_D1.BLIF inst_BGACK_030_INTreg.D 1-10 1 @@ -267,42 +277,52 @@ inst_AS_000_INTreg.D 1-0 1 00- 0 --1 0 +.names CLK_CNT_N_0_.BLIF CLK_CNT_N_1_.BLIF CLK_CNT_P_0_.BLIF CLK_CNT_P_1_.BLIF \ +inst_CLK_OUT_PRE.D +1010 1 +0110 1 +1001 1 +0101 1 +00-- 0 +11-- 0 +--00 0 +--11 0 .names FC_1_.BLIF AS_030.BLIF nEXP_SPACE.BLIF BGACK_000.BLIF CLK_030.BLIF \ A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF FC_0_.BLIF \ inst_AS_030_000_SYNC.BLIF inst_CLK_000_D5.BLIF SM_AMIGA_6_.BLIF \ -SM_AMIGA_7_.BLIF inst_CLK_000_D4.BLIF SM_AMIGA_1_.BLIF inst_AS_030_000_SYNC.D +inst_CLK_000_D4.BLIF SM_AMIGA_7_.BLIF SM_AMIGA_1_.BLIF inst_AS_030_000_SYNC.D 1--1-001011----- 1 ------------0--11 1 +-----------0-1-1 1 --0---------1--- 1 -----------1--0-- 1 +----------1---0- 1 ----0-----1----- 1 --0-------1----- 1 -1-------------- 1 --0--------0-0-0- 0 +-0--------0-00-- 0 -0--------010--- 0 --01-1----0---10- 0 --01-1---1----10- 0 --01-1--0-----10- 0 --01-1-1------10- 0 --01-11-------10- 0 --0101--------10- 0 -001-1--------10- 0 --01-1----0-1-1-- 0 --01-1---1--1-1-- 0 --01-1--0---1-1-- 0 --01-1-1----1-1-- 0 --01-11-----1-1-- 0 --0101------1-1-- 0 -001-1------1-1-- 0 +-01-1----0---01- 0 +-01-1---1----01- 0 +-01-1--0-----01- 0 +-01-1-1------01- 0 +-01-11-------01- 0 +-0101--------01- 0 +001-1--------01- 0 +-01-1----0-1--1- 0 +-01-1---1--1--1- 0 +-01-1--0---1--1- 0 +-01-1-1----1--1- 0 +-01-11-----1--1- 0 +-0101------1--1- 0 +001-1------1--1- 0 -0--------0-0--0 0 --01-1----0---1-0 0 --01-1---1----1-0 0 --01-1--0-----1-0 0 --01-1-1------1-0 0 --01-11-------1-0 0 --0101--------1-0 0 -001-1--------1-0 0 --01-------0---0- 0 +-01-1----0----10 0 +-01-1---1-----10 0 +-01-1--0------10 0 +-01-1-1-------10 0 +-01-11--------10 0 +-0101---------10 0 +001-1---------10 0 +-01-------0--0-- 0 -01-------01---- 0 -01-------0----0 0 .names AS_030.BLIF inst_DTACK_SYNC.BLIF inst_VPA_D.BLIF inst_CLK_000_D0.BLIF \ @@ -341,27 +361,6 @@ SM_AMIGA_1_.BLIF DSACK_INT_1_.D 1---0 1 -0-11 0 0-0-- 0 -.names AS_030.BLIF cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF \ -cpu_est_1_.BLIF inst_VPA_D.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D0.BLIF \ -cpu_est_2_.BLIF SM_AMIGA_3_.BLIF inst_VPA_SYNC.D -------1-0- 1 -------10-- 1 ------11--- 1 -----1-1--- 1 ----1--1--- 1 ---1---1--- 1 --0----1--- 1 -------1--0 1 -1-------0- 1 -1------0-- 1 -1----1---- 1 -1---1----- 1 -1--1------ 1 -1-1------- 1 -10-------- 1 -1--------0 1 --10000-111 0 -0-----0--- 0 .names AS_030.BLIF nEXP_SPACE.BLIF RST.BLIF SM_AMIGA_6_.BLIF \ AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLEDFFreg.D 1-10- 1 @@ -375,6 +374,15 @@ AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLEDFFreg.D 1- 1 -1 1 00 0 +.names AS_030.BLIF nEXP_SPACE.BLIF BG_030.BLIF inst_CLK_000_D0.BLIF \ +inst_CLK_000_D1.BLIF SM_AMIGA_7_.BLIF BG_000DFFSHreg.D +----1- 1 +---0-- 1 +--1--- 1 +-1---- 1 +0----- 1 +-----0 1 +100101 0 .names IPL_030DFFSH_2_reg.BLIF IPL_030_2_ 1 1 0 0 @@ -414,7 +422,7 @@ AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLEDFFreg.D .names inst_VMA_INTreg.BLIF VMA 1 1 0 0 -.names RESETDFFreg.BLIF RESET +.names RESETDFFRHreg.BLIF RESET 1 1 0 0 .names AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLE @@ -437,6 +445,84 @@ AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLEDFFreg.D .names IPL_030DFFSH_0_reg.BLIF IPL_030_0_ 1 1 0 0 +.names CLK_OSZI.BLIF cpu_est_2_.C +1 1 +0 0 +.names RST.BLIF cpu_est_2_.AR +0 1 +1 0 +.names CLK_OSZI.BLIF cpu_est_3_reg.C +1 1 +0 0 +.names RST.BLIF cpu_est_3_reg.AR +0 1 +1 0 +.names CLK_OSZI.BLIF cpu_est_0_.C +1 1 +0 0 +.names RST.BLIF cpu_est_0_.AR +0 1 +1 0 +.names CLK_OSZI.BLIF cpu_est_1_.C +1 1 +0 0 +.names RST.BLIF cpu_est_1_.AR +0 1 +1 0 +.names CLK_OSZI.BLIF SM_AMIGA_3_.C +1 1 +0 0 +.names RST.BLIF SM_AMIGA_3_.AR +0 1 +1 0 +.names CLK_OSZI.BLIF SM_AMIGA_2_.C +1 1 +0 0 +.names RST.BLIF SM_AMIGA_2_.AR +0 1 +1 0 +.names CLK_OSZI.BLIF SM_AMIGA_1_.C +1 1 +0 0 +.names RST.BLIF SM_AMIGA_1_.AR +0 1 +1 0 +.names CLK_OSZI.BLIF SM_AMIGA_0_.C +1 1 +0 0 +.names RST.BLIF SM_AMIGA_0_.AR +0 1 +1 0 +.names CLK_OSZI.BLIF CLK_CNT_N_0_.C +0 1 +1 0 +.names RST.BLIF CLK_CNT_N_0_.AR +0 1 +1 0 +.names CLK_CNT_N_0_.BLIF CLK_CNT_N_1_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_CNT_N_1_.C +0 1 +1 0 +.names RST.BLIF CLK_CNT_N_1_.AR +0 1 +1 0 +.names CLK_OSZI.BLIF CLK_CNT_P_0_.C +1 1 +0 0 +.names RST.BLIF CLK_CNT_P_0_.AR +0 1 +1 0 +.names CLK_CNT_P_0_.BLIF CLK_CNT_P_1_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_CNT_P_1_.C +1 1 +0 0 +.names RST.BLIF CLK_CNT_P_1_.AR +0 1 +1 0 .names CLK_OSZI.BLIF IPL_030DFFSH_0_reg.C 1 1 0 0 @@ -479,48 +565,6 @@ AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLEDFFreg.D .names RST.BLIF SM_AMIGA_4_.AR 0 1 1 0 -.names CLK_OSZI.BLIF SM_AMIGA_3_.C -1 1 -0 0 -.names RST.BLIF SM_AMIGA_3_.AR -0 1 -1 0 -.names CLK_OSZI.BLIF SM_AMIGA_2_.C -1 1 -0 0 -.names RST.BLIF SM_AMIGA_2_.AR -0 1 -1 0 -.names CLK_OSZI.BLIF SM_AMIGA_1_.C -1 1 -0 0 -.names RST.BLIF SM_AMIGA_1_.AR -0 1 -1 0 -.names CLK_OSZI.BLIF SM_AMIGA_0_.C -1 1 -0 0 -.names RST.BLIF SM_AMIGA_0_.AR -0 1 -1 0 -.names CLK_OSZI.BLIF CLK_CNT_0_.C -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_CNT_1_.C -1 1 -0 0 -.names CLK_OSZI.BLIF cpu_est_0_.C -1 1 -0 0 -.names CLK_OSZI.BLIF cpu_est_1_.C -1 1 -0 0 -.names CLK_OSZI.BLIF cpu_est_2_.C -1 1 -0 0 -.names CLK_OSZI.BLIF cpu_est_3_reg.C -1 1 -0 0 .names CLK_OSZI.BLIF inst_UDS_000_INTreg.C 1 1 0 0 @@ -533,21 +577,18 @@ AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLEDFFreg.D .names RST.BLIF inst_LDS_000_INTreg.AP 0 1 1 0 +.names CLK_OSZI.BLIF inst_VPA_SYNC.C +1 1 +0 0 +.names RST.BLIF inst_VPA_SYNC.AP +0 1 +1 0 .names CLK_OSZI.BLIF inst_VMA_INTreg.C 1 1 0 0 .names RST.BLIF inst_VMA_INTreg.AP 0 1 1 0 -.names CLK_OSZI.BLIF BG_000DFFSHreg.C -1 1 -0 0 -.names RST.BLIF BG_000DFFSHreg.AP -0 1 -1 0 -.names CLK_OSZI.BLIF inst_CLK_OUT_PRE.C -1 1 -0 0 .names CLK_OSZI.BLIF inst_BGACK_030_INTreg.C 1 1 0 0 @@ -560,6 +601,21 @@ AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLEDFFreg.D .names RST.BLIF inst_AS_000_INTreg.AP 0 1 1 0 +.names CLK_OSZI.BLIF inst_CLK_OUT_PRE.C +1 1 +0 0 +.names RST.BLIF inst_CLK_OUT_PRE.AR +0 1 +1 0 +.names inst_CLK_OUT_PRE.BLIF CLK_OUT_INTreg.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_OUT_INTreg.C +1 1 +0 0 +.names RST.BLIF CLK_OUT_INTreg.AR +0 1 +1 0 .names CLK_OSZI.BLIF inst_AS_030_000_SYNC.C 1 1 0 0 @@ -584,80 +640,90 @@ AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLEDFFreg.D .names RST.BLIF DSACK_INT_1_.AP 0 1 1 0 -.names CLK_OSZI.BLIF inst_VPA_SYNC.C -1 1 -0 0 -.names RST.BLIF inst_VPA_SYNC.AP -0 1 -1 0 .names CLK_OSZI.BLIF AMIGA_BUS_ENABLEDFFreg.C 1 1 0 0 -.names inst_CLK_000_D4.BLIF inst_CLK_000_D5.D -1 1 -0 0 -.names CLK_OSZI.BLIF inst_CLK_000_D5.C -1 1 -0 0 .names CLK_OSZI.BLIF inst_DTACK_DMA.C 1 1 0 0 .names RST.BLIF inst_DTACK_DMA.AP 0 1 1 0 -.names inst_CLK_OUT_PRE.BLIF CLK_OUT_INTreg.D +.names inst_CLK_000_D4.BLIF inst_CLK_000_D5.D 1 1 0 0 -.names CLK_OSZI.BLIF CLK_OUT_INTreg.C +.names CLK_OSZI.BLIF inst_CLK_000_D5.C 1 1 0 0 +.names RST.BLIF inst_CLK_000_D5.AP +0 1 +1 0 +.names CLK_OSZI.BLIF BG_000DFFSHreg.C +1 1 +0 0 +.names RST.BLIF BG_000DFFSHreg.AP +0 1 +1 0 .names inst_CLK_000_D3.BLIF inst_CLK_000_D4.D 1 1 0 0 .names CLK_OSZI.BLIF inst_CLK_000_D4.C 1 1 0 0 +.names RST.BLIF inst_CLK_000_D4.AP +0 1 +1 0 .names inst_CLK_000_D1.BLIF inst_CLK_000_D2.D 1 1 0 0 .names CLK_OSZI.BLIF inst_CLK_000_D2.C 1 1 0 0 +.names RST.BLIF inst_CLK_000_D2.AP +0 1 +1 0 .names inst_CLK_000_D2.BLIF inst_CLK_000_D3.D 1 1 0 0 .names CLK_OSZI.BLIF inst_CLK_000_D3.C 1 1 0 0 +.names RST.BLIF inst_CLK_000_D3.AP +0 1 +1 0 .names VPA.BLIF inst_VPA_D.D 1 1 0 0 .names CLK_OSZI.BLIF inst_VPA_D.C 1 1 0 0 +.names RST.BLIF inst_VPA_D.AP +0 1 +1 0 .names CLK_000.BLIF inst_CLK_000_D0.D 1 1 0 0 .names CLK_OSZI.BLIF inst_CLK_000_D0.C 1 1 0 0 -.names RST.BLIF RESETDFFreg.D -1 1 -0 0 -.names CLK_OSZI.BLIF RESETDFFreg.C +.names RST.BLIF inst_CLK_000_D0.AP +0 1 +1 0 +.names RESETDFFRHreg.D + 1 +.names CLK_OSZI.BLIF RESETDFFRHreg.C 1 1 0 0 +.names RST.BLIF RESETDFFRHreg.AR +0 1 +1 0 .names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D 1 1 0 0 .names CLK_OSZI.BLIF inst_CLK_000_D1.C 1 1 0 0 -.names CLK_REF_1_.D - 0 -.names CLK_REF_1_.LH - 0 -.names RST.BLIF CLK_REF_1_.AR +.names RST.BLIF inst_CLK_000_D1.AP 0 1 1 0 .names DSACK_INT_1_.BLIF DSACK_1_ @@ -703,53 +769,39 @@ A_25_.BLIF A_24_.BLIF CIIN.OE -1------ 0 1------- 0 -------1 0 -.names cpu_est_3_reg.BLIF cpu_est_0_.BLIF cpu_est_3_reg.D.X1 -11 1 +.names inst_VMA_INTreg.BLIF inst_CLK_000_D0.BLIF inst_VMA_INTreg.D.X1 +10 1 0- 0 --0 0 -.names cpu_est_3_reg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_CLK_000_D0.BLIF \ -inst_CLK_000_D1.BLIF cpu_est_2_.BLIF cpu_est_3_reg.D.X2 -10---- 1 --00100 1 -011100 1 -1-1101 1 --10--- 0 -0--0-- 0 --1-0-- 0 -0---1- 0 --1--1- 0 -0----1 0 -001--- 0 -11---0 0 -.names cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF inst_VMA_INTreg.D.X1 -01 1 -1- 0 --0 0 -.names cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \ -inst_AS_000_INTreg.BLIF inst_VPA_D.BLIF inst_CLK_000_D0.BLIF cpu_est_2_.BLIF \ -inst_VMA_INTreg.D.X2 -00011-11 1 --110-001 1 -11------ 1 -10------ 0 --01----- 0 --0-0---- 0 --0--0--- 0 --0----0- 0 -0------0 0 --0-----0 0 -010----- 0 -01-1---- 0 -01---1-- 0 -01----1- 0 -.names inst_CLK_OUT_PRE.BLIF inst_CLK_OUT_PRE.D.X1 -1 1 -0 0 -.names inst_CLK_OUT_PRE.BLIF CLK_REF_1_.BLIF CLK_CNT_0_.BLIF CLK_CNT_1_.BLIF \ -inst_CLK_OUT_PRE.D.X2 --000 1 --101 1 ---1- 0 --0-1 0 --1-0 0 +-1 0 +.names inst_VMA_INTreg.BLIF inst_AS_000_INTreg.BLIF inst_VPA_D.BLIF \ +inst_CLK_000_D0.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF \ +cpu_est_3_reg.BLIF inst_VMA_INTreg.D.X2 +1-0-10-- 1 +1--1---- 1 +-1-10110 1 +00------ 0 +--10---- 0 +0---1--- 0 +---00--- 0 +---0-1-- 0 +0----0-- 0 +0-----0- 0 +0------1 0 +.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF cpu_est_1_.BLIF \ +cpu_est_2_.BLIF cpu_est_3_reg.BLIF cpu_est_3_reg.D.X1 +10111 1 +0---- 0 +-1--- 0 +--0-- 0 +---0- 0 +----0 0 +.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF cpu_est_0_.BLIF \ +cpu_est_1_.BLIF cpu_est_2_.BLIF cpu_est_3_reg.BLIF cpu_est_3_reg.D.X2 +-----1 1 +101-0- 1 +10-00- 1 +0----0 0 +-1---0 0 +----10 0 +--01-0 0 .end diff --git a/Logic/68030_tk.crf b/Logic/68030_tk.crf index f425200..a7c5a7e 100644 --- a/Logic/68030_tk.crf +++ b/Logic/68030_tk.crf @@ -1,7 +1,7 @@ // Signal Name Cross Reference File // ispLEVER Classic 1.7.00.05.28.13 -// Design '68030_tk' created Sat May 24 11:44:09 2014 +// Design '68030_tk' created Sat May 24 15:48:50 2014 // LEGEND: '>' Functional Block Port Separator diff --git a/Logic/68030_tk.eq3 b/Logic/68030_tk.eq3 index 63b11ff..e28bc03 100644 --- a/Logic/68030_tk.eq3 +++ b/Logic/68030_tk.eq3 @@ -2,13 +2,14 @@ Copyright(C), 1992-2013, Lattice Semiconductor Corp. All Rights Reserved. -Design bus68030 created Sat May 24 11:44:09 2014 +Design bus68030 created Sat May 24 15:48:50 2014 P-Terms Fan-in Fan-out Type Name (attributes) --------- ------ ------- ---- ----------------- 0 0 1 Pin BERR 1 1 1 Pin BERR.OE + 1 1 1 Pin CLK_DIV_OUT.AR 1 1 1 Pin CLK_DIV_OUT.D 1 1 1 Pin CLK_DIV_OUT.C 1 0 1 Pin AVEC @@ -39,12 +40,13 @@ Design bus68030 created Sat May 24 11:44:09 2014 8 9 1 Pin LDS_000.D 1 1 1 Pin LDS_000.AP 1 1 1 Pin LDS_000.C - 2 6 1 Pin BG_000.D- + 1 6 1 Pin BG_000.D- 1 1 1 Pin BG_000.AP 1 1 1 Pin BG_000.C 2 4 1 Pin BGACK_030.D 1 1 1 Pin BGACK_030.AP 1 1 1 Pin BGACK_030.C + 1 1 1 Pin CLK_EXP.AR 1 1 1 Pin CLK_EXP.D 1 1 1 Pin CLK_EXP.C 2 10 1 Pin FPU_CS.D- @@ -54,12 +56,16 @@ Design bus68030 created Sat May 24 11:44:09 2014 1 2 1 Pin DTACK.D- 1 1 1 Pin DTACK.AP 1 1 1 Pin DTACK.C - 3 6 1 Pin E.T + 3 6 1 PinX1 E.D.X1 + 1 1 1 PinX2 E.D.X2 + 1 1 1 Pin E.AR 1 1 1 Pin E.C + 2 7 1 PinX1 VMA.D.X1 + 1 5 1 PinX2 VMA.D.X2 1 1 1 Pin VMA.AP - 2 8 1 Pin VMA.T 1 1 1 Pin VMA.C - 1 1 1 Pin RESET.D + 1 1 1 Pin RESET.AR + 1 0 1 Pin RESET.D 1 1 1 Pin RESET.C 3 5 1 Pin AMIGA_BUS_ENABLE.D- 1 1 1 Pin AMIGA_BUS_ENABLE.C @@ -69,10 +75,6 @@ Design bus68030 created Sat May 24 11:44:09 2014 3 4 1 Pin IPL_030_0_.D 1 1 1 Pin IPL_030_0_.AP 1 1 1 Pin IPL_030_0_.C - 3 3 1 Node cpu_est_0_.D - 1 1 1 Node cpu_est_0_.C - 4 6 1 Node cpu_est_1_.T - 1 1 1 Node cpu_est_1_.C 7 16 1 Node inst_AS_030_000_SYNC.D 1 1 1 Node inst_AS_030_000_SYNC.AP 1 1 1 Node inst_AS_030_000_SYNC.C @@ -80,63 +82,82 @@ Design bus68030 created Sat May 24 11:44:09 2014 1 1 1 Node inst_DTACK_SYNC.AP 1 1 1 Node inst_DTACK_SYNC.C 1 1 1 Node inst_VPA_D.D + 1 1 1 Node inst_VPA_D.AP 1 1 1 Node inst_VPA_D.C - 2 10 1 Node inst_VPA_SYNC.D- + 2 8 1 Node inst_VPA_SYNC.D- 1 1 1 Node inst_VPA_SYNC.AP 1 1 1 Node inst_VPA_SYNC.C 1 1 1 Node inst_CLK_000_D0.D + 1 1 1 Node inst_CLK_000_D0.AP 1 1 1 Node inst_CLK_000_D0.C 1 1 1 Node inst_CLK_000_D1.D + 1 1 1 Node inst_CLK_000_D1.AP 1 1 1 Node inst_CLK_000_D1.C 1 1 1 Node inst_CLK_000_D2.D + 1 1 1 Node inst_CLK_000_D2.AP 1 1 1 Node inst_CLK_000_D2.C 1 1 1 Node inst_CLK_000_D5.D + 1 1 1 Node inst_CLK_000_D5.AP 1 1 1 Node inst_CLK_000_D5.C - 3 3 1 NodeX1 inst_CLK_OUT_PRE.D.X1 - 1 2 1 NodeX2 inst_CLK_OUT_PRE.D.X2 - 1 1 1 Node inst_CLK_OUT_PRE.C - 1 1 1 Node SM_AMIGA_6_.AR - 2 7 1 Node SM_AMIGA_6_.D - 1 1 1 Node SM_AMIGA_6_.C 1 1 1 Node SM_AMIGA_5_.AR 2 3 1 Node SM_AMIGA_5_.D 1 1 1 Node SM_AMIGA_5_.C - 3 6 1 NodeX1 cpu_est_2_.D.X1 - 1 1 1 NodeX2 cpu_est_2_.D.X2 - 1 1 1 Node cpu_est_2_.C - 1 1 1 Node CLK_REF_1_.AR - 0 0 1 Node CLK_REF_1_.D - 0 0 1 Node CLK_REF_1_.LH - 5 9 1 Node SM_AMIGA_7_.D - 1 1 1 Node SM_AMIGA_7_.AP - 1 1 1 Node SM_AMIGA_7_.C + 1 1 1 Node SM_AMIGA_6_.AR + 2 7 1 Node SM_AMIGA_6_.D + 1 1 1 Node SM_AMIGA_6_.C 1 1 1 Node inst_CLK_000_D3.D + 1 1 1 Node inst_CLK_000_D3.AP 1 1 1 Node inst_CLK_000_D3.C 1 1 1 Node SM_AMIGA_4_.AR 2 3 1 Node SM_AMIGA_4_.D 1 1 1 Node SM_AMIGA_4_.C 1 1 1 Node inst_CLK_000_D4.D + 1 1 1 Node inst_CLK_000_D4.AP 1 1 1 Node inst_CLK_000_D4.C - 2 3 1 Node CLK_CNT_0_.D - 1 1 1 Node CLK_CNT_0_.C - 2 3 1 Node CLK_CNT_1_.D - 1 1 1 Node CLK_CNT_1_.C + 5 9 1 Node SM_AMIGA_7_.D + 1 1 1 Node SM_AMIGA_7_.AP + 1 1 1 Node SM_AMIGA_7_.C 1 1 1 Node SM_AMIGA_3_.AR 3 5 1 Node SM_AMIGA_3_.D 1 1 1 Node SM_AMIGA_3_.C 1 1 1 Node SM_AMIGA_1_.AR 3 5 1 Node SM_AMIGA_1_.D 1 1 1 Node SM_AMIGA_1_.C + 1 1 1 Node CLK_CNT_N_0_.AR + 2 2 1 Node CLK_CNT_N_0_.D + 1 1 1 Node CLK_CNT_N_0_.C + 1 1 1 Node CLK_CNT_N_1_.AR + 1 1 1 Node CLK_CNT_N_1_.D + 1 1 1 Node CLK_CNT_N_1_.C + 1 1 1 Node CLK_CNT_P_0_.AR + 2 2 1 Node CLK_CNT_P_0_.D + 1 1 1 Node CLK_CNT_P_0_.C + 1 1 1 Node CLK_CNT_P_1_.AR + 1 1 1 Node CLK_CNT_P_1_.D + 1 1 1 Node CLK_CNT_P_1_.C 1 1 1 Node SM_AMIGA_2_.AR 3 5 1 Node SM_AMIGA_2_.D 1 1 1 Node SM_AMIGA_2_.C 1 1 1 Node SM_AMIGA_0_.AR 4 6 1 Node SM_AMIGA_0_.D 1 1 1 Node SM_AMIGA_0_.C + 1 1 1 Node inst_CLK_OUT_PRE.AR + 4 4 1 Node inst_CLK_OUT_PRE.D + 1 1 1 Node inst_CLK_OUT_PRE.C + 1 1 1 Node cpu_est_0_.AR + 3 3 1 Node cpu_est_0_.D + 1 1 1 Node cpu_est_0_.C + 1 1 1 Node cpu_est_1_.AR + 4 6 1 Node cpu_est_1_.T + 1 1 1 Node cpu_est_1_.C + 3 6 1 NodeX1 cpu_est_2_.D.X1 + 1 1 1 NodeX2 cpu_est_2_.D.X2 + 1 1 1 Node cpu_est_2_.AR + 1 1 1 Node cpu_est_2_.C ========= - 184 P-Term Total: 184 + 207 P-Term Total: 207 Total Pins: 59 - Total Nodes: 25 + Total Nodes: 26 Average P-Term/Output: 2 @@ -146,6 +167,8 @@ BERR = (0); BERR.OE = (!FPU_CS.Q); +CLK_DIV_OUT.AR = (!RST); + CLK_DIV_OUT.D = (inst_CLK_OUT_PRE.Q); CLK_DIV_OUT.C = (CLK_OSZI); @@ -168,7 +191,7 @@ DSACK_0_ = (1); DSACK_0_.OE = (nEXP_SPACE); -IPL_030_2_.D = (!inst_CLK_000_D0.Q & IPL_030_2_.Q +IPL_030_2_.D = (IPL_030_2_.Q & !inst_CLK_000_D0.Q # IPL_030_2_.Q & inst_CLK_000_D1.Q # IPL_2_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q); @@ -221,8 +244,7 @@ LDS_000.AP = (!RST); LDS_000.C = (CLK_OSZI); -!BG_000.D = (!BG_030 & CLK_030 & !BG_000.Q - # AS_030 & !nEXP_SPACE & !BG_030 & !CLK_030 & SM_AMIGA_7_.Q); +!BG_000.D = (AS_030 & !nEXP_SPACE & !BG_030 & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & SM_AMIGA_7_.Q); BG_000.AP = (!RST); @@ -235,6 +257,8 @@ BGACK_030.AP = (!RST); BGACK_030.C = (CLK_OSZI); +CLK_EXP.AR = (!RST); + CLK_EXP.D = (inst_CLK_OUT_PRE.Q); CLK_EXP.C = (CLK_OSZI); @@ -254,20 +278,28 @@ DTACK.AP = (!RST); DTACK.C = (CLK_OSZI); -E.T = (E.Q & cpu_est_0_.Q & cpu_est_1_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_2_.Q - # !E.Q & cpu_est_0_.Q & cpu_est_1_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_2_.Q - # !E.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_2_.Q); +E.D.X1 = (inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_1_.Q & cpu_est_2_.Q & E.Q + # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_0_.Q & !cpu_est_2_.Q & !E.Q + # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !E.Q); + +E.D.X2 = (E.Q); + +E.AR = (!RST); E.C = (CLK_OSZI); -VMA.AP = (!RST); +VMA.D.X1 = (VMA.Q + # !VMA.Q & AS_000.Q & inst_CLK_000_D0.Q & !cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & !E.Q); -VMA.T = (!E.Q & !VMA.Q & !cpu_est_0_.Q & cpu_est_1_.Q & AS_000.Q & inst_CLK_000_D0.Q & cpu_est_2_.Q - # !E.Q & VMA.Q & cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & !inst_CLK_000_D0.Q & cpu_est_2_.Q); +VMA.D.X2 = (VMA.Q & !inst_VPA_D.Q & !inst_CLK_000_D0.Q & cpu_est_0_.Q & !cpu_est_1_.Q); + +VMA.AP = (!RST); VMA.C = (CLK_OSZI); -RESET.D = (RST); +RESET.AR = (!RST); + +RESET.D = (1); RESET.C = (CLK_OSZI); @@ -293,19 +325,6 @@ IPL_030_0_.AP = (!RST); IPL_030_0_.C = (CLK_OSZI); -cpu_est_0_.D = (cpu_est_0_.Q & !inst_CLK_000_D0.Q - # cpu_est_0_.Q & inst_CLK_000_D1.Q - # !cpu_est_0_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q); - -cpu_est_0_.C = (CLK_OSZI); - -cpu_est_1_.T = (E.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q - # !E.Q & cpu_est_0_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_2_.Q - # !E.Q & !cpu_est_1_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_2_.Q - # E.Q & cpu_est_0_.Q & cpu_est_1_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_2_.Q); - -cpu_est_1_.C = (CLK_OSZI); - inst_AS_030_000_SYNC.D = (AS_030 # !nEXP_SPACE & inst_AS_030_000_SYNC.Q # !CLK_030 & inst_AS_030_000_SYNC.Q @@ -327,10 +346,12 @@ inst_DTACK_SYNC.C = (CLK_OSZI); inst_VPA_D.D = (VPA); +inst_VPA_D.AP = (!RST); + inst_VPA_D.C = (CLK_OSZI); !inst_VPA_SYNC.D = (!AS_030 & !inst_VPA_SYNC.Q - # E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_D0.Q & cpu_est_2_.Q & SM_AMIGA_3_.Q); + # !VMA.Q & !inst_VPA_D.Q & inst_CLK_000_D0.Q & SM_AMIGA_3_.Q & !cpu_est_1_.Q & E.Q); inst_VPA_SYNC.AP = (!RST); @@ -338,68 +359,46 @@ inst_VPA_SYNC.C = (CLK_OSZI); inst_CLK_000_D0.D = (CLK_000); +inst_CLK_000_D0.AP = (!RST); + inst_CLK_000_D0.C = (CLK_OSZI); inst_CLK_000_D1.D = (inst_CLK_000_D0.Q); +inst_CLK_000_D1.AP = (!RST); + inst_CLK_000_D1.C = (CLK_OSZI); inst_CLK_000_D2.D = (inst_CLK_000_D1.Q); +inst_CLK_000_D2.AP = (!RST); + inst_CLK_000_D2.C = (CLK_OSZI); inst_CLK_000_D5.D = (inst_CLK_000_D4.Q); +inst_CLK_000_D5.AP = (!RST); + inst_CLK_000_D5.C = (CLK_OSZI); -inst_CLK_OUT_PRE.D.X1 = (inst_CLK_OUT_PRE.Q & CLK_CNT_0_.Q - # inst_CLK_OUT_PRE.Q & CLK_CNT_1_.Q - # !inst_CLK_OUT_PRE.Q & !CLK_CNT_0_.Q & !CLK_CNT_1_.Q); - -inst_CLK_OUT_PRE.D.X2 = (CLK_REF_1_.Q & !CLK_CNT_0_.Q); - -inst_CLK_OUT_PRE.C = (CLK_OSZI); - -SM_AMIGA_6_.AR = (!RST); - -SM_AMIGA_6_.D = (nEXP_SPACE & !inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !SM_AMIGA_7_.Q - # !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D2.Q & SM_AMIGA_7_.Q & inst_CLK_000_D3.Q); - -SM_AMIGA_6_.C = (CLK_OSZI); - SM_AMIGA_5_.AR = (!RST); -SM_AMIGA_5_.D = (inst_CLK_000_D0.Q & SM_AMIGA_6_.Q - # inst_CLK_000_D0.Q & SM_AMIGA_5_.Q); +SM_AMIGA_5_.D = (inst_CLK_000_D0.Q & SM_AMIGA_5_.Q + # inst_CLK_000_D0.Q & SM_AMIGA_6_.Q); SM_AMIGA_5_.C = (CLK_OSZI); -cpu_est_2_.D.X1 = (E.Q & cpu_est_0_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_2_.Q - # !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_2_.Q - # !E.Q & cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_2_.Q); +SM_AMIGA_6_.AR = (!RST); -cpu_est_2_.D.X2 = (cpu_est_2_.Q); +SM_AMIGA_6_.D = (!inst_AS_030_000_SYNC.Q & !inst_CLK_000_D2.Q & inst_CLK_000_D3.Q & SM_AMIGA_7_.Q + # nEXP_SPACE & !inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !SM_AMIGA_7_.Q); -cpu_est_2_.C = (CLK_OSZI); - -CLK_REF_1_.AR = (!RST); - -CLK_REF_1_.D = (0); - -CLK_REF_1_.LH = (0); - -SM_AMIGA_7_.D = (inst_AS_030_000_SYNC.Q & SM_AMIGA_7_.Q - # inst_CLK_000_D2.Q & SM_AMIGA_7_.Q - # SM_AMIGA_7_.Q & !inst_CLK_000_D3.Q - # !nEXP_SPACE & !inst_CLK_000_D0.Q & SM_AMIGA_6_.Q - # AS_000.Q & inst_CLK_000_D0.Q & SM_AMIGA_0_.Q); - -SM_AMIGA_7_.AP = (!RST); - -SM_AMIGA_7_.C = (CLK_OSZI); +SM_AMIGA_6_.C = (CLK_OSZI); inst_CLK_000_D3.D = (inst_CLK_000_D2.Q); +inst_CLK_000_D3.AP = (!RST); + inst_CLK_000_D3.C = (CLK_OSZI); SM_AMIGA_4_.AR = (!RST); @@ -411,17 +410,19 @@ SM_AMIGA_4_.C = (CLK_OSZI); inst_CLK_000_D4.D = (inst_CLK_000_D3.Q); +inst_CLK_000_D4.AP = (!RST); + inst_CLK_000_D4.C = (CLK_OSZI); -CLK_CNT_0_.D = (!CLK_REF_1_.Q & !CLK_CNT_0_.Q & CLK_CNT_1_.Q - # CLK_REF_1_.Q & !CLK_CNT_0_.Q & !CLK_CNT_1_.Q); +SM_AMIGA_7_.D = (inst_AS_030_000_SYNC.Q & SM_AMIGA_7_.Q + # inst_CLK_000_D2.Q & SM_AMIGA_7_.Q + # !inst_CLK_000_D3.Q & SM_AMIGA_7_.Q + # !nEXP_SPACE & !inst_CLK_000_D0.Q & SM_AMIGA_6_.Q + # AS_000.Q & inst_CLK_000_D0.Q & SM_AMIGA_0_.Q); -CLK_CNT_0_.C = (CLK_OSZI); +SM_AMIGA_7_.AP = (!RST); -CLK_CNT_1_.D = (CLK_CNT_0_.Q & !CLK_CNT_1_.Q - # !CLK_REF_1_.Q & !CLK_CNT_0_.Q & CLK_CNT_1_.Q); - -CLK_CNT_1_.C = (CLK_OSZI); +SM_AMIGA_7_.C = (CLK_OSZI); SM_AMIGA_3_.AR = (!RST); @@ -439,6 +440,32 @@ SM_AMIGA_1_.D = (inst_CLK_000_D0.Q & SM_AMIGA_1_.Q SM_AMIGA_1_.C = (CLK_OSZI); +CLK_CNT_N_0_.AR = (!RST); + +CLK_CNT_N_0_.D = (CLK_CNT_N_0_.Q & CLK_CNT_N_1_.Q + # !CLK_CNT_N_0_.Q & !CLK_CNT_N_1_.Q); + +CLK_CNT_N_0_.C = (!CLK_OSZI); + +CLK_CNT_N_1_.AR = (!RST); + +CLK_CNT_N_1_.D = (CLK_CNT_N_0_.Q); + +CLK_CNT_N_1_.C = (!CLK_OSZI); + +CLK_CNT_P_0_.AR = (!RST); + +CLK_CNT_P_0_.D = (CLK_CNT_P_0_.Q & CLK_CNT_P_1_.Q + # !CLK_CNT_P_0_.Q & !CLK_CNT_P_1_.Q); + +CLK_CNT_P_0_.C = (CLK_OSZI); + +CLK_CNT_P_1_.AR = (!RST); + +CLK_CNT_P_1_.D = (CLK_CNT_P_0_.Q); + +CLK_CNT_P_1_.C = (CLK_OSZI); + SM_AMIGA_2_.AR = (!RST); SM_AMIGA_2_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_2_.Q @@ -456,6 +483,42 @@ SM_AMIGA_0_.D = (!AS_000.Q & SM_AMIGA_0_.Q SM_AMIGA_0_.C = (CLK_OSZI); +inst_CLK_OUT_PRE.AR = (!RST); + +inst_CLK_OUT_PRE.D = (!CLK_CNT_N_0_.Q & CLK_CNT_N_1_.Q & !CLK_CNT_P_0_.Q & CLK_CNT_P_1_.Q + # CLK_CNT_N_0_.Q & !CLK_CNT_N_1_.Q & !CLK_CNT_P_0_.Q & CLK_CNT_P_1_.Q + # !CLK_CNT_N_0_.Q & CLK_CNT_N_1_.Q & CLK_CNT_P_0_.Q & !CLK_CNT_P_1_.Q + # CLK_CNT_N_0_.Q & !CLK_CNT_N_1_.Q & CLK_CNT_P_0_.Q & !CLK_CNT_P_1_.Q); + +inst_CLK_OUT_PRE.C = (CLK_OSZI); + +cpu_est_0_.AR = (!RST); + +cpu_est_0_.D = (!inst_CLK_000_D0.Q & cpu_est_0_.Q + # inst_CLK_000_D1.Q & cpu_est_0_.Q + # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_0_.Q); + +cpu_est_0_.C = (CLK_OSZI); + +cpu_est_1_.AR = (!RST); + +cpu_est_1_.T = (inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_1_.Q & cpu_est_2_.Q & E.Q + # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_0_.Q & !cpu_est_2_.Q & E.Q + # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_0_.Q & cpu_est_2_.Q & !E.Q + # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !E.Q); + +cpu_est_1_.C = (CLK_OSZI); + +cpu_est_2_.D.X1 = (inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q + # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_0_.Q & !cpu_est_2_.Q & E.Q + # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_0_.Q & !cpu_est_1_.Q & cpu_est_2_.Q & !E.Q); + +cpu_est_2_.D.X2 = (cpu_est_2_.Q); + +cpu_est_2_.AR = (!RST); + +cpu_est_2_.C = (CLK_OSZI); + Reverse-Polarity Equations: diff --git a/Logic/68030_tk.fti b/Logic/68030_tk.fti index 261fb98..2489c24 100644 --- a/Logic/68030_tk.fti +++ b/Logic/68030_tk.fti @@ -30,17 +30,18 @@ DATA LOCATION A_31_:B_*_4 // INP DATA LOCATION BERR:E_4_41 // OUT DATA LOCATION BGACK_000:D_*_28 // INP DATA LOCATION BGACK_030:H_4_83 // IO {RN_BGACK_030} -DATA LOCATION BG_000:D_13_29 // IO {RN_BG_000} +DATA LOCATION BG_000:D_13_29 // OUT DATA LOCATION BG_030:C_*_21 // INP DATA LOCATION CIIN:E_12_47 // OUT DATA LOCATION CLK_000:*_*_11 // INP DATA LOCATION CLK_030:*_*_64 // INP -DATA LOCATION CLK_CNT_0_:G_2 // NOD -DATA LOCATION CLK_CNT_1_:G_13 // NOD +DATA LOCATION CLK_CNT_N_0_:B_13 // NOD +DATA LOCATION CLK_CNT_N_1_:G_13 // NOD +DATA LOCATION CLK_CNT_P_0_:G_2 // NOD +DATA LOCATION CLK_CNT_P_1_:G_6 // NOD DATA LOCATION CLK_DIV_OUT:G_0_65 // OUT DATA LOCATION CLK_EXP:B_0_10 // OUT DATA LOCATION CLK_OSZI:*_*_61 // Cin -DATA LOCATION CLK_REF_1_:H_14 // NOD DATA LOCATION DSACK_0_:H_12_80 // OUT DATA LOCATION DSACK_1_:H_8_81 // IO {RN_DSACK_1_} DATA LOCATION DS_030:A_*_98 // INP @@ -60,7 +61,6 @@ DATA LOCATION RESET:B_1_3 // OUT DATA LOCATION RN_AMIGA_BUS_ENABLE:D_4 // NOD {AMIGA_BUS_ENABLE} DATA LOCATION RN_AS_000:D_5 // NOD {AS_000} DATA LOCATION RN_BGACK_030:H_4 // NOD {BGACK_030} -DATA LOCATION RN_BG_000:D_13 // NOD {BG_000} DATA LOCATION RN_DSACK_1_:H_8 // NOD {DSACK_1_} DATA LOCATION RN_E:G_4 // NOD {E} DATA LOCATION RN_FPU_CS:H_0 // NOD {FPU_CS} @@ -74,10 +74,10 @@ DATA LOCATION RST:*_*_86 // INP DATA LOCATION RW:G_*_71 // INP DATA LOCATION SIZE_0_:G_*_70 // INP DATA LOCATION SIZE_1_:H_*_79 // INP -DATA LOCATION SM_AMIGA_0_:H_6 // NOD -DATA LOCATION SM_AMIGA_1_:B_9 // NOD -DATA LOCATION SM_AMIGA_2_:G_5 // NOD -DATA LOCATION SM_AMIGA_3_:B_5 // NOD +DATA LOCATION SM_AMIGA_0_:H_10 // NOD +DATA LOCATION SM_AMIGA_1_:B_5 // NOD +DATA LOCATION SM_AMIGA_2_:B_2 // NOD +DATA LOCATION SM_AMIGA_3_:B_9 // NOD DATA LOCATION SM_AMIGA_4_:D_10 // NOD DATA LOCATION SM_AMIGA_5_:D_14 // NOD DATA LOCATION SM_AMIGA_6_:H_5 // NOD @@ -86,19 +86,19 @@ DATA LOCATION UDS_000:D_12_32 // IO {RN_UDS_000} DATA LOCATION VMA:D_1_35 // IO {RN_VMA} DATA LOCATION VPA:*_*_36 // INP DATA LOCATION cpu_est_0_:D_6 // NOD -DATA LOCATION cpu_est_1_:D_9 // NOD +DATA LOCATION cpu_est_1_:G_12 // NOD DATA LOCATION cpu_est_2_:D_2 // NOD -DATA LOCATION inst_AS_030_000_SYNC:H_2 // NOD +DATA LOCATION inst_AS_030_000_SYNC:H_6 // NOD DATA LOCATION inst_CLK_000_D0:G_8 // NOD -DATA LOCATION inst_CLK_000_D1:G_12 // NOD -DATA LOCATION inst_CLK_000_D2:G_6 // NOD -DATA LOCATION inst_CLK_000_D3:H_10 // NOD +DATA LOCATION inst_CLK_000_D1:D_9 // NOD +DATA LOCATION inst_CLK_000_D2:D_3 // NOD +DATA LOCATION inst_CLK_000_D3:H_14 // NOD DATA LOCATION inst_CLK_000_D4:H_9 // NOD DATA LOCATION inst_CLK_000_D5:H_13 // NOD -DATA LOCATION inst_CLK_OUT_PRE:G_9 // NOD -DATA LOCATION inst_DTACK_SYNC:A_0 // NOD -DATA LOCATION inst_VPA_D:G_1 // NOD -DATA LOCATION inst_VPA_SYNC:F_0 // NOD +DATA LOCATION inst_CLK_OUT_PRE:G_1 // NOD +DATA LOCATION inst_DTACK_SYNC:G_9 // NOD +DATA LOCATION inst_VPA_D:H_2 // NOD +DATA LOCATION inst_VPA_SYNC:G_5 // NOD DATA LOCATION nEXP_SPACE:*_*_14 // INP DATA IO_DIR AMIGA_BUS_DATA_DIR:OUT DATA IO_DIR AMIGA_BUS_ENABLE:OUT @@ -164,76 +164,76 @@ DATA PW_LEVEL SIZE_1_:0 DATA SLEW SIZE_1_:0 DATA PW_LEVEL A_31_:0 DATA SLEW A_31_:0 -DATA PW_LEVEL IPL_2_:0 -DATA SLEW IPL_2_:0 -DATA PW_LEVEL FC_1_:0 -DATA SLEW FC_1_:0 -DATA PW_LEVEL AS_030:0 -DATA SLEW AS_030:0 -DATA PW_LEVEL DS_030:0 -DATA SLEW DS_030:0 -DATA SLEW nEXP_SPACE:0 -DATA PW_LEVEL BERR:0 -DATA SLEW BERR:0 -DATA PW_LEVEL BG_030:0 -DATA SLEW BG_030:0 -DATA PW_LEVEL BGACK_000:0 -DATA SLEW BGACK_000:0 -DATA SLEW CLK_030:0 -DATA SLEW CLK_000:0 DATA PW_LEVEL SIZE_0_:0 DATA SLEW SIZE_0_:0 -DATA SLEW CLK_OSZI:0 +DATA PW_LEVEL IPL_2_:0 +DATA SLEW IPL_2_:0 DATA PW_LEVEL A_30_:0 DATA SLEW A_30_:0 -DATA PW_LEVEL CLK_DIV_OUT:0 -DATA SLEW CLK_DIV_OUT:0 DATA PW_LEVEL A_29_:0 DATA SLEW A_29_:0 DATA PW_LEVEL A_28_:0 DATA SLEW A_28_:0 DATA PW_LEVEL A_27_:0 DATA SLEW A_27_:0 +DATA PW_LEVEL FC_1_:0 +DATA SLEW FC_1_:0 DATA PW_LEVEL A_26_:0 DATA SLEW A_26_:0 -DATA PW_LEVEL AVEC:0 -DATA SLEW AVEC:0 +DATA PW_LEVEL AS_030:0 +DATA SLEW AS_030:0 DATA PW_LEVEL A_25_:0 DATA SLEW A_25_:0 -DATA PW_LEVEL AVEC_EXP:0 -DATA SLEW AVEC_EXP:0 DATA PW_LEVEL A_24_:0 DATA SLEW A_24_:0 +DATA PW_LEVEL DS_030:0 +DATA SLEW DS_030:0 DATA PW_LEVEL A_23_:0 DATA SLEW A_23_:0 -DATA SLEW VPA:0 DATA PW_LEVEL A_22_:0 DATA SLEW A_22_:0 DATA PW_LEVEL A_21_:0 DATA SLEW A_21_:0 -DATA SLEW RST:0 +DATA SLEW nEXP_SPACE:0 DATA PW_LEVEL A_20_:0 DATA SLEW A_20_:0 +DATA PW_LEVEL BERR:0 +DATA SLEW BERR:0 DATA PW_LEVEL A_19_:0 DATA SLEW A_19_:0 -DATA PW_LEVEL RW:0 -DATA SLEW RW:0 +DATA PW_LEVEL BG_030:0 +DATA SLEW BG_030:0 DATA PW_LEVEL A_18_:0 DATA SLEW A_18_:0 DATA PW_LEVEL A_17_:0 DATA SLEW A_17_:0 -DATA PW_LEVEL AMIGA_BUS_DATA_DIR:0 -DATA SLEW AMIGA_BUS_DATA_DIR:0 DATA PW_LEVEL A_16_:0 DATA SLEW A_16_:0 -DATA PW_LEVEL AMIGA_BUS_ENABLE_LOW:0 -DATA SLEW AMIGA_BUS_ENABLE_LOW:0 -DATA PW_LEVEL CIIN:0 -DATA SLEW CIIN:0 +DATA PW_LEVEL BGACK_000:0 +DATA SLEW BGACK_000:0 +DATA SLEW CLK_030:0 +DATA SLEW CLK_000:0 +DATA SLEW CLK_OSZI:0 +DATA PW_LEVEL CLK_DIV_OUT:0 +DATA SLEW CLK_DIV_OUT:0 +DATA PW_LEVEL AVEC:0 +DATA SLEW AVEC:0 +DATA PW_LEVEL AVEC_EXP:0 +DATA SLEW AVEC_EXP:0 +DATA SLEW VPA:0 +DATA SLEW RST:0 +DATA PW_LEVEL RW:0 +DATA SLEW RW:0 DATA PW_LEVEL A_0_:0 DATA SLEW A_0_:0 +DATA PW_LEVEL AMIGA_BUS_DATA_DIR:0 +DATA SLEW AMIGA_BUS_DATA_DIR:0 +DATA PW_LEVEL AMIGA_BUS_ENABLE_LOW:0 +DATA SLEW AMIGA_BUS_ENABLE_LOW:0 DATA PW_LEVEL IPL_1_:0 DATA SLEW IPL_1_:0 +DATA PW_LEVEL CIIN:0 +DATA SLEW CIIN:0 DATA PW_LEVEL IPL_0_:0 DATA SLEW IPL_0_:0 DATA PW_LEVEL DSACK_0_:0 @@ -272,10 +272,6 @@ DATA PW_LEVEL IPL_030_1_:0 DATA SLEW IPL_030_1_:0 DATA PW_LEVEL IPL_030_0_:0 DATA SLEW IPL_030_0_:0 -DATA PW_LEVEL cpu_est_0_:0 -DATA SLEW cpu_est_0_:0 -DATA PW_LEVEL cpu_est_1_:0 -DATA SLEW cpu_est_1_:0 DATA PW_LEVEL inst_AS_030_000_SYNC:0 DATA SLEW inst_AS_030_000_SYNC:0 DATA PW_LEVEL inst_DTACK_SYNC:0 @@ -292,42 +288,47 @@ DATA PW_LEVEL inst_CLK_000_D2:0 DATA SLEW inst_CLK_000_D2:0 DATA PW_LEVEL inst_CLK_000_D5:0 DATA SLEW inst_CLK_000_D5:0 -DATA PW_LEVEL inst_CLK_OUT_PRE:0 -DATA SLEW inst_CLK_OUT_PRE:0 -DATA PW_LEVEL SM_AMIGA_6_:0 -DATA SLEW SM_AMIGA_6_:0 DATA PW_LEVEL SM_AMIGA_5_:0 DATA SLEW SM_AMIGA_5_:0 -DATA PW_LEVEL cpu_est_2_:0 -DATA SLEW cpu_est_2_:0 -DATA PW_LEVEL CLK_REF_1_:0 -DATA SLEW CLK_REF_1_:0 -DATA PW_LEVEL SM_AMIGA_7_:0 -DATA SLEW SM_AMIGA_7_:0 +DATA PW_LEVEL SM_AMIGA_6_:0 +DATA SLEW SM_AMIGA_6_:0 DATA PW_LEVEL inst_CLK_000_D3:0 DATA SLEW inst_CLK_000_D3:0 DATA PW_LEVEL SM_AMIGA_4_:0 DATA SLEW SM_AMIGA_4_:0 DATA PW_LEVEL inst_CLK_000_D4:0 DATA SLEW inst_CLK_000_D4:0 -DATA PW_LEVEL CLK_CNT_0_:0 -DATA SLEW CLK_CNT_0_:0 -DATA PW_LEVEL CLK_CNT_1_:0 -DATA SLEW CLK_CNT_1_:0 +DATA PW_LEVEL SM_AMIGA_7_:0 +DATA SLEW SM_AMIGA_7_:0 DATA PW_LEVEL SM_AMIGA_3_:0 DATA SLEW SM_AMIGA_3_:0 DATA PW_LEVEL SM_AMIGA_1_:0 DATA SLEW SM_AMIGA_1_:0 +DATA PW_LEVEL CLK_CNT_N_0_:0 +DATA SLEW CLK_CNT_N_0_:0 +DATA PW_LEVEL CLK_CNT_N_1_:0 +DATA SLEW CLK_CNT_N_1_:0 +DATA PW_LEVEL CLK_CNT_P_0_:0 +DATA SLEW CLK_CNT_P_0_:0 +DATA PW_LEVEL CLK_CNT_P_1_:0 +DATA SLEW CLK_CNT_P_1_:0 DATA PW_LEVEL SM_AMIGA_2_:0 DATA SLEW SM_AMIGA_2_:0 DATA PW_LEVEL SM_AMIGA_0_:0 DATA SLEW SM_AMIGA_0_:0 +DATA PW_LEVEL inst_CLK_OUT_PRE:0 +DATA SLEW inst_CLK_OUT_PRE:0 +DATA PW_LEVEL cpu_est_0_:0 +DATA SLEW cpu_est_0_:0 +DATA PW_LEVEL cpu_est_1_:0 +DATA SLEW cpu_est_1_:0 +DATA PW_LEVEL cpu_est_2_:0 +DATA SLEW cpu_est_2_:0 DATA PW_LEVEL RN_IPL_030_2_:0 DATA PW_LEVEL RN_DSACK_1_:0 DATA PW_LEVEL RN_AS_000:0 DATA PW_LEVEL RN_UDS_000:0 DATA PW_LEVEL RN_LDS_000:0 -DATA PW_LEVEL RN_BG_000:0 DATA PW_LEVEL RN_BGACK_030:0 DATA PW_LEVEL RN_FPU_CS:0 DATA PW_LEVEL RN_E:0 diff --git a/Logic/68030_tk.grp b/Logic/68030_tk.grp index 0da7fcb..ece5a2d 100644 --- a/Logic/68030_tk.grp +++ b/Logic/68030_tk.grp @@ -1,16 +1,16 @@ -GROUP MACH_SEG_A inst_DTACK_SYNC AVEC -GROUP MACH_SEG_B SM_AMIGA_3_ SM_AMIGA_1_ IPL_030_1_ RN_IPL_030_1_ IPL_030_0_ - RN_IPL_030_0_ IPL_030_2_ RN_IPL_030_2_ CLK_EXP RESET +GROUP MACH_SEG_A AVEC +GROUP MACH_SEG_B SM_AMIGA_2_ SM_AMIGA_3_ SM_AMIGA_1_ IPL_030_1_ RN_IPL_030_1_ + IPL_030_0_ RN_IPL_030_0_ IPL_030_2_ RN_IPL_030_2_ CLK_CNT_N_0_ CLK_EXP + RESET GROUP MACH_SEG_C AVEC_EXP AMIGA_BUS_ENABLE_LOW -GROUP MACH_SEG_D LDS_000 RN_LDS_000 UDS_000 RN_UDS_000 VMA RN_VMA BG_000 - RN_BG_000 cpu_est_1_ cpu_est_2_ AMIGA_BUS_ENABLE RN_AMIGA_BUS_ENABLE - AS_000 RN_AS_000 SM_AMIGA_4_ SM_AMIGA_5_ DTACK cpu_est_0_ +GROUP MACH_SEG_D LDS_000 RN_LDS_000 UDS_000 RN_UDS_000 VMA RN_VMA cpu_est_2_ + BG_000 AMIGA_BUS_ENABLE RN_AMIGA_BUS_ENABLE AS_000 RN_AS_000 SM_AMIGA_4_ + SM_AMIGA_5_ cpu_est_0_ DTACK inst_CLK_000_D2 inst_CLK_000_D1 GROUP MACH_SEG_E CIIN BERR AMIGA_BUS_DATA_DIR -GROUP MACH_SEG_F inst_VPA_SYNC -GROUP MACH_SEG_G E RN_E SM_AMIGA_2_ inst_CLK_OUT_PRE CLK_CNT_0_ CLK_CNT_1_ - inst_VPA_D inst_CLK_000_D0 CLK_DIV_OUT inst_CLK_000_D2 inst_CLK_000_D1 +GROUP MACH_SEG_G inst_VPA_SYNC inst_DTACK_SYNC E RN_E cpu_est_1_ inst_CLK_OUT_PRE + CLK_CNT_P_0_ inst_CLK_000_D0 CLK_DIV_OUT CLK_CNT_N_1_ CLK_CNT_P_1_ GROUP MACH_SEG_H inst_AS_030_000_SYNC FPU_CS RN_FPU_CS SM_AMIGA_7_ SM_AMIGA_6_ - DSACK_1_ RN_DSACK_1_ SM_AMIGA_0_ BGACK_030 RN_BGACK_030 CLK_REF_1_ + DSACK_1_ RN_DSACK_1_ SM_AMIGA_0_ BGACK_030 RN_BGACK_030 inst_VPA_D inst_CLK_000_D3 inst_CLK_000_D4 inst_CLK_000_D5 DSACK_0_ \ No newline at end of file diff --git a/Logic/68030_tk.ipr b/Logic/68030_tk.ipr index d38d77d..78ec2ff 100644 --- a/Logic/68030_tk.ipr +++ b/Logic/68030_tk.ipr @@ -1 +1 @@ -95476<6qYWA7P \ No newline at end of file +021:7<6! i@>" \ No newline at end of file diff --git a/Logic/68030_tk.jed b/Logic/68030_tk.jed index 12b3bcd..c6c8f01 100644 --- a/Logic/68030_tk.jed +++ b/Logic/68030_tk.jed @@ -10,7 +10,7 @@ AUTHOR: PATTERN: COMPANY: REVISION: -DATE: Sat May 24 11:44:13 2014 +DATE: Sat May 24 15:48:54 2014 ABEL mach447a * @@ -31,50 +31,50 @@ NOTE Spread Placement? Y * NOTE Run Time Upper Bound in 15 minutes 0 * NOTE Zero Hold Time For Input Registers? Y * NOTE Table of pin names and numbers* -NOTE PINS SIZE_1_:79 A_31_:4 IPL_2_:68 FC_1_:58 AS_030:82* -NOTE PINS DS_030:98 nEXP_SPACE:14 BERR:41 BG_030:21 BGACK_000:28* -NOTE PINS CLK_030:64 CLK_000:11 SIZE_0_:70 CLK_OSZI:61 A_30_:5* -NOTE PINS CLK_DIV_OUT:65 A_29_:6 A_28_:15 A_27_:16 A_26_:17* -NOTE PINS AVEC:92 A_25_:18 AVEC_EXP:22 A_24_:19 A_23_:84* -NOTE PINS VPA:36 A_22_:85 A_21_:94 RST:86 A_20_:93 A_19_:97* -NOTE PINS RW:71 A_18_:95 A_17_:59 AMIGA_BUS_DATA_DIR:48 A_16_:96* -NOTE PINS AMIGA_BUS_ENABLE_LOW:20 CIIN:47 A_0_:69 IPL_1_:56* -NOTE PINS IPL_0_:67 DSACK_0_:80 FC_0_:57 IPL_030_2_:9 DSACK_1_:81* -NOTE PINS AS_000:33 UDS_000:32 LDS_000:31 BG_000:29 BGACK_030:83* -NOTE PINS CLK_EXP:10 FPU_CS:78 DTACK:30 E:66 VMA:35 RESET:3* -NOTE PINS AMIGA_BUS_ENABLE:34 IPL_030_1_:7 IPL_030_0_:8 * +NOTE PINS SIZE_1_:79 A_31_:4 SIZE_0_:70 IPL_2_:68 A_30_:5* +NOTE PINS A_29_:6 A_28_:15 A_27_:16 FC_1_:58 A_26_:17 AS_030:82* +NOTE PINS A_25_:18 A_24_:19 DS_030:98 A_23_:84 A_22_:85 A_21_:94* +NOTE PINS nEXP_SPACE:14 A_20_:93 BERR:41 A_19_:97 BG_030:21* +NOTE PINS A_18_:95 A_17_:59 A_16_:96 BGACK_000:28 CLK_030:64* +NOTE PINS CLK_000:11 CLK_OSZI:61 CLK_DIV_OUT:65 AVEC:92 AVEC_EXP:22* +NOTE PINS VPA:36 RST:86 RW:71 A_0_:69 AMIGA_BUS_DATA_DIR:48* +NOTE PINS AMIGA_BUS_ENABLE_LOW:20 IPL_1_:56 CIIN:47 IPL_0_:67* +NOTE PINS DSACK_0_:80 FC_0_:57 IPL_030_2_:9 DSACK_1_:81 AS_000:33* +NOTE PINS UDS_000:32 LDS_000:31 BG_000:29 BGACK_030:83 CLK_EXP:10* +NOTE PINS FPU_CS:78 DTACK:30 E:66 VMA:35 RESET:3 AMIGA_BUS_ENABLE:34* +NOTE PINS IPL_030_1_:7 IPL_030_0_:8 * NOTE Table of node names and numbers* NOTE NODES RN_IPL_030_2_:131 RN_DSACK_1_:281 RN_AS_000:181 * -NOTE NODES RN_UDS_000:191 RN_LDS_000:185 RN_BG_000:193 RN_BGACK_030:275 * +NOTE NODES RN_UDS_000:191 RN_LDS_000:185 RN_BGACK_030:275 * NOTE NODES RN_FPU_CS:269 RN_DTACK:173 RN_E:251 RN_VMA:175 * NOTE NODES RN_AMIGA_BUS_ENABLE:179 RN_IPL_030_1_:143 RN_IPL_030_0_:137 * -NOTE NODES cpu_est_0_:182 cpu_est_1_:187 inst_AS_030_000_SYNC:272 * -NOTE NODES inst_DTACK_SYNC:101 inst_VPA_D:247 inst_VPA_SYNC:221 * -NOTE NODES inst_CLK_000_D0:257 inst_CLK_000_D1:263 inst_CLK_000_D2:254 * -NOTE NODES inst_CLK_000_D5:289 inst_CLK_OUT_PRE:259 SM_AMIGA_6_:277 * -NOTE NODES SM_AMIGA_5_:194 cpu_est_2_:176 CLK_REF_1_:290 * -NOTE NODES SM_AMIGA_7_:271 inst_CLK_000_D3:284 SM_AMIGA_4_:188 * -NOTE NODES inst_CLK_000_D4:283 CLK_CNT_0_:248 CLK_CNT_1_:265 * -NOTE NODES SM_AMIGA_3_:133 SM_AMIGA_1_:139 SM_AMIGA_2_:253 * -NOTE NODES SM_AMIGA_0_:278 * +NOTE NODES inst_AS_030_000_SYNC:278 inst_DTACK_SYNC:259 * +NOTE NODES inst_VPA_D:272 inst_VPA_SYNC:253 inst_CLK_000_D0:257 * +NOTE NODES inst_CLK_000_D1:187 inst_CLK_000_D2:178 inst_CLK_000_D5:289 * +NOTE NODES SM_AMIGA_5_:194 SM_AMIGA_6_:277 inst_CLK_000_D3:290 * +NOTE NODES SM_AMIGA_4_:188 inst_CLK_000_D4:283 SM_AMIGA_7_:271 * +NOTE NODES SM_AMIGA_3_:139 SM_AMIGA_1_:133 CLK_CNT_N_0_:145 * +NOTE NODES CLK_CNT_N_1_:265 CLK_CNT_P_0_:248 CLK_CNT_P_1_:254 * +NOTE NODES SM_AMIGA_2_:128 SM_AMIGA_0_:284 inst_CLK_OUT_PRE:247 * +NOTE NODES cpu_est_0_:182 cpu_est_1_:263 cpu_est_2_:176 * NOTE BLOCK 0 * L000000 111111111111111111111111111111111111111111111111111111111111111111 - 111111111011111111111111111111111111111111111111111111111111111111 - 111111111111111111111011111111111111111111111111111111110111111111 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111101111111111111111 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111101111111111111111111111111111111111111 - 111111111111111111101111111111111111111111111111111111111111111111 - 101111111111111111111111111111011111111111111111111111111111111111* + 111111111111111111111111111111111111111111111111111111111111111111 + 111111111111111111111111111111111111111111111111111111111111111111 + 111111111111111111111111111111111111111111111111111111111111111111 + 111111111111111111111111111111111111111111111111111111111111111111 + 111111111111111111111111111111111111111111111111111111111111111111 + 111111111111111111111111111111111111111111111111111111111111111111* L000594 000000000000000000000000000000000000000000000000000000000000000000* -L000660 111111111111111111101111111111101111111111111111111111111111111111* -L000726 111111111111111111110111111110111111111111111111011111110111111111* -L000792 000000000000000000000000000000000000000000000000000000000000000000* -L000858 000000000000000000000000000000000000000000000000000000000000000000* -L000924 000000000000000000000000000000000000000000000000000000000000000000* +L000660 111111111111111111111111111111111111111111111111111111111111111111* +L000726 111111111111111111111111111111111111111111111111111111111111111111* +L000792 111111111111111111111111111111111111111111111111111111111111111111* +L000858 111111111111111111111111111111111111111111111111111111111111111111* +L000924 111111111111111111111111111111111111111111111111111111111111111111* L000990 111111111111111111111111111111111111111111111111111111111111111111* L001056 111111111111111111111111111111111111111111111111111111111111111111* L001122 111111111111111111111111111111111111111111111111111111111111111111* @@ -166,10 +166,10 @@ L006270 111111111111111111111111111111111111111111111111111111111111111111* L006336 111111111111111111111111111111111111111111111111111111111111111111* L006402 000000000000000000000000000000000000000000000000000000000000000000 - 101111111111111111111111111111111111111111111111111111111111111111* -L006534 0010* -L006538 11100110010000* -L006552 11011011111110* + 000000000000000000000000000000000000000000000000000000000000000000* +L006534 0000* +L006538 11010011110000* +L006552 11110111111111* L006566 11110011110101* L006580 11110111111111* L006594 00110011111000* @@ -186,34 +186,34 @@ L006734 11110111110001* L006748 11111111110011* NOTE BLOCK 1 * L006762 - 110111111111111111111111111110111111111111111111111111111111111111 - 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000000000000000000000000000000000000000000000000000000000000000000* -L007950 111111111111111111111111111111111111111111111111111111111111111111* -L008016 111111111111111111111111111111111111111111111111111111111111111111* +L007950 000000000000000000000000000000000000000000000000000000000000000000* +L008016 000000000000000000000000000000000000000000000000000000000000000000* L008082 111111111111111111111111111111111111111111111111111111111111111111* -L008148 111111111111111111111111111111111111111111111111111111111111111111* -L008214 111111111111111111111111111111111111111111111111111111111111111111* -L008280 111111111111111111111111111111111111111111111111111111111111111111* -L008346 111111111111111111111111111111111111111111111111111111111111111111* -L008412 111111111111111111111111111111111111111111111111111111111111111111* +L008148 111111111111011111111111101011111111111111111111111111111111111111* +L008214 111111111111011111111111111011111111111111111011111111111111111111* +L008280 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11110111110011* L040404 11110011111110* @@ -821,31 +821,31 @@ L040544 11110111111111* L040558 11111111111111* NOTE BLOCK 6 * L040572 - 111111011111111111101111111110111111111111111111111111111111111111 - 111111111011111111111111101111111111111111111111111111111111111111 - 111111111111111111111111111011111111111111111111111111111111110111 - 111111111111111111111110111111111111111111111010111111111111111111 - 111110111110111111111111111111111111111111111111111111111111111111 + 111111011111111011111111101111111111111111011111111111111111111111 + 111111111111011111111011111111111111111111111111111111111111111111 + 111111111110111111111111111011111111111111111111111111111111111111 + 111111111011111111111110111111111111111111111011111111111111111111 + 111111111111111111111111111111111111111111111111101111111111111111 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111110111111111111111111111111111111111111111111111111111 - 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000000000000000000000000000000000000000000000000000000000000000000* L042156 000000000000000000000000000000000000000000000000000000000000000000* L042222 000000000000000000000000000000000000000000000000000000000000000000* @@ -856,19 +856,19 @@ L042486 111111111111111111111111111111111111111111111111111111111111111111* L042552 111111111111111111111111111111111111111111111111111111111111111111* L042618 000000000000000000000000000000000000000000000000000000000000000000* -L042684 111111111111110111111101110110110111111111111111111111110111111111* -L042750 111111111111110111111110110110110111111111111111111111111011111111* -L042816 111111111111111011111110110110111011111111111111111111111011111111* -L042882 000000000000000000000000000000000000000000000000000000000000000000* +L042684 111111111111111111111101111111111111111111111111111111111111111111* +L042750 111111111111110111111101110111111111111111111111111011110111111111* +L042816 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000000000000000000000000000000000000000000000000000000000000000000* +L045918 111111111111111111111111111111111111111111011111111111111111111111* +L045984 111111111111111111111111111111111111111111111111111111111111111111* +L046050 111111111111111111111111111111111111111111111111111111111111111111* +L046116 111111111111111111111111111111111111111111111111111111111111111111* +L046182 111111111111111111111111111111111111111111111111111111111111111111* L046248 000000000000000000000000000000000000000000000000000000000000000000* L046314 111111111111111111111111111111111111111111111111111111111111111111* @@ -927,103 +927,103 @@ L046776 111111111111111111111111111111111111111111111111111111111111111111* L046842 111111111111111111111111111111111111111111111111111111111111111111* L046908 111111111111111111111111111111111111111111111111111111111111111111* L046974 - 000000000000000000000000000000000000000000000000000000000000000000 + 101111111111111111111111111111111111111111111111111111111111111111 000000000000000000000000000000000000000000000000000000000000000000* L047106 0010* L047110 00100110010000* -L047124 00100110011110* +L047124 10100110011110* L047138 10100110010100* -L047152 11100011111111* -L047166 10100111011001* -L047180 10101110000011* -L047194 00010110010000* -L047208 11101111110011* -L047222 00110110010001* -L047236 00100110010011* -L047250 11011011110000* -L047264 11111111110010* -L047278 00110110010000* -L047292 10100110010011* -L047306 11010011110000* -L047320 11111011111110* +L047152 11101011111111* +L047166 00100110011000* +L047180 11100100010010* +L047194 00010110010001* +L047208 11100011110011* +L047222 00110100010000* +L047236 11100100010010* +L047250 11011111110000* +L047264 11110011110011* +L047278 10100111010001* +L047292 00001110010011* +L047306 11011011110000* +L047320 11111111111111* NOTE BLOCK 7 * L047334 - 111111111011111011111111111111111111111111111111111111111111111111 - 111111111101111111111111111111110111111111111111111111111110111111 - 111111111111101111111111111111111111111111111110111111111011111111 + 111111111111111111111111111111111111111111111111111111111011111111 + 111111111111111111111111111111011111111111111111111111111111111111 + 111111111111111111111011111111111110111111111111111111111111110111 111011111111111110111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111011111111111101011111111111111111111111101 - 111111101111111111111101111111111101111111111111111111101111111111 - 111111111111111111101111111011111111111110101111011111111111111111 - 101111111111111111111011111110111111111111111111111111111111101111* + 111110111111111111111111111111111111111111111111111111111111111111 + 101111111111011111111111111111111111011011111111111111111111111111 + 111111100110111111111101111111111111111111111111110111111111111111 + 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111111111111111111111111111111111111111111011111011111110111111111* +L048324 111111111111111111111011111111101111111111111111111111011111111111* +L048390 111111111111110111111111011111111111111111111111111111111111111111* +L048456 111111111111111111111111010111111111111111111111111111111111111111* +L048522 111110111111111111111111011111111111111111111111111111111111111111* +L048588 011111111111111111110111111111111111111111111111011111111111111111* L048654 000000000000000000000000000000000000000000000000000000000000000000* -L048720 111111111111111111111111111111110111111011111111111111011111111111* -L048786 111111111111111111011111111111111111111111111111111111111111111111* -L048852 111111111110111111111111111101111111111111111111111111111111111111* -L048918 111111111011111111111111111101111111111111111111111111111111111111* -L048984 110111111111011101111110101101111110111111111111111111111111111101* -L049050 111111111110111111111111110111111111111111111111111111111111111111* -L049116 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111111111111111111111111111111111111111111111111111111111111111111* L049380 111111111111111111111111111111111111111111111111111111111111111111* -L049446 111111111111111111111111111111111111111101111111111111111111111101* -L049512 111111111111111011111111111111111111111111111111111111110111111101* +L049446 111111111111111111111111111111111111011111111101111111111111111111* +L049512 111111111111111111110111111111111111011111111111111011111111111111* L049578 000000000000000000000000000000000000000000000000000000000000000000* L049644 000000000000000000000000000000000000000000000000000000000000000000* L049710 000000000000000000000000000000000000000000000000000000000000000000* -L049776 111111111101111111111011110111111111111111111111111111111011111111* -L049842 111111111111111111110111111110111111011111111110111111111111111111* +L049776 111101111111111011111111011011111111111111111111111111111111111111* +L049842 111111111111111111111011101111011111111111111111111111011111111111* L049908 000000000000000000000000000000000000000000000000000000000000000000* L049974 000000000000000000000000000000000000000000000000000000000000000000* L050040 000000000000000000000000000000000000000000000000000000000000000000* L050106 000000000000000000000000000000000000000000000000000000000000000000* -L050172 111111111111111111111111111111110111110111111111111111111011111111* -L050238 111111111111111111111111111111110111111111111111111111101011111111* -L050304 111111111111111111111111111111111111111111011111101111111111111111* -L050370 111111111111111111111111111111111111111111011111111111111011111111* -L050436 000000000000000000000000000000000000000000000000000000000000000000* +L050172 111111111101111111111111111111111111111011111111111111111111110111* +L050238 111111111111111111011111111111111111111111111111111111111111111111* +L050304 111111111111110111111111111111101111111111111111111111111111111111* +L050370 111111111111110111111111111111111111111111111111111111111011111111* +L050436 110111111011100101111110111111111101011111111111111111111111111111* L050502 111111111111111111111111111111111111111111111111111111111111111111* L050568 111111111111111111111111111111111111111111111111111111111111111111* L050634 111111111111111111111111111111111111111111111111111111111111111111* L050700 111111111111111111111111111111111111111111111111111111111111111111* L050766 111111111111111111111111111111111111111111111111111111111111111111* L050832 - 111111111101111111111111111111111111111111111111111111111111111111* -L050898 111111111111111111111111111111111111111111111111111111111111111111* -L050964 111111111111111111111111111111111111111111111111111111111111111111* -L051030 111111111111111111111111111111111111111111111111111111111111111111* -L051096 111111111111111111111111111111111111111111111111111111111111111111* -L051162 111111111111111111111111111111111111111111111111111111111111111111* -L051228 111111111111111111111111111111111111011111111111111111111111111111* -L051294 111111111111111111111111111111111111111111111111111111111101111111* -L051360 000000000000000000000000000000000000000000000000000000000000000000* -L051426 111111101111111111101111111111111111111111111111111111111111111111* -L051492 111111111111111111111111111111110111111011111111111111011111111111* + 111111111111111111111111111111011111111111111111111111111111111111* +L050898 111111111111111111111111111111101111111111111111111111011111111111* +L050964 111111111111110111111111101111111111111111111111111111111111111111* +L051030 000000000000000000000000000000000000000000000000000000000000000000* +L051096 000000000000000000000000000000000000000000000000000000000000000000* +L051162 000000000000000000000000000000000000000000000000000000000000000000* +L051228 111101111111111111111111111111111111111111111111111111111111111111* +L051294 111111101111111111101111111111111111111111111111111111111111111111* +L051360 111111111101111111111111111111111111111011111111111111111111110111* +L051426 000000000000000000000000000000000000000000000000000000000000000000* +L051492 000000000000000000000000000000000000000000000000000000000000000000* L051558 - 111111111101111111111111111111111111111111111111111111111111111111* -L051624 111111111111111111111111111111111111111111111101111111111111111111* -L051690 111111111111111111111111111111111111111111111111111111111101111111* -L051756 000000000000000000000000000000000000000000000000000000000000000000* -L051822 111111111111111111111111111111111111111111111111111111111111111111* -L051888 111111111111111111111111111111111111111111111111111111111111111111* + 111111111111111111111111111111011111111111111111111111111111111111* +L051624 111111111111111111111011111111111111110111111111111111111111110111* +L051690 111111111110111111111011111111111111111111111111111111111111110111* +L051756 011111111111111111111111111111111111111111111111101111111111111111* +L051822 011111111111111111111011111111111111111111111111111111111111111111* +L051888 000000000000000000000000000000000000000000000000000000000000000000* L051954 111111111111111111111111111111111111111111111111111111111111111111* L052020 111111111111111111111111111111111111111111111111111111111111111111* L052086 111111111111111111111111111111111111111111111111111111111111111111* @@ -1036,16 +1036,16 @@ L052416 111111111111111111111111111111111111111111111111111111111111111111* L052482 111111111111111111111111111111111111111111111111111111111111111111* L052548 111111111111111111111111111111111111111111111111111111111111111111* L052614 111111111111111111111111111111111111111111111111111111111111111111* -L052680 111111111111111111111111111111111111111111111111111111011111111111* -L052746 111111111111111111111111111111111111111111111111111111111101111111* -L052812 000000000000000000000000000000000000000000000000000000000000000000* +L052680 111111111101111111111111111111111111111111111111111111111111111111* +L052746 111111111111111111111111111111111111111111111111111111111111111111* +L052812 111111111111111111111111111111111111111111111111111111111111111111* L052878 111111111111111111111111111111111111111111111111111111111111111111* L052944 111111111111111111111111111111111111111111111111111111111111111111* L053010 111111111111111111111111111111111111111111111111111111111111111111* -L053076 000000000000000000000000000000000000000000000000000000000000000000* -L053142 000000000000000000000000000000000000000000000000000000000000000000* -L053208 101111111111111111111111111111111111111111111111111111111111111111* +L053076 111111111111111111111111110111111111111111111111111111111111111111* +L053142 111111111111111111111111111111111111111111111111111111111111111111* +L053208 111111111111111111111111111111111111111111111111111111111111111111* L053274 111111111111111111111111111111111111111111111111111111111111111111* L053340 111111111111111111111111111111111111111111111111111111111111111111* L053406 111111111111111111111111111111111111111111111111111111111111111111* @@ -1055,23 +1055,23 @@ L053604 111111111111111111111111111111111111111111111111111111111111111111* L053670 111111111111111111111111111111111111111111111111111111111111111111* L053736 000000000000000000000000000000000000000000000000000000000000000000 - 101111111111111111111111111111111111111111111111111111111111111111* + 111111111111111111111111111111111111111111101111111111111111111111* L053868 0010* L053872 11100110011000* L053886 10100110010010* -L053900 10100110010000* -L053914 11110011110011* +L053900 00010110010000* +L053914 11100011110011* L053928 10100110010001* L053942 10100100011111* -L053956 10100100010000* +L053956 10100110010000* L053970 11101111110011* -L053984 11110110010001* -L053998 00111110000011* -L054012 00011110000100* +L053984 11000110010001* +L053998 00110110010011* +L054012 10100100010100* L054026 11101011111110* L054040 00111111111000* -L054054 00001110000011* -L054068 00011110100100* +L054054 00000110010011* +L054068 00010110010100* L054082 11100011111110* E1 0 @@ -1092,6 +1092,6 @@ E1 00000000 1 * -C5CE6* +C879E* U00000000000000000000000000000000* -CCD1 +D142 diff --git a/Logic/68030_tk.lco b/Logic/68030_tk.lco index 9167295..af35a32 100644 --- a/Logic/68030_tk.lco +++ b/Logic/68030_tk.lco @@ -17,7 +17,7 @@ Parent = m4a5.lci; SDS_File = m4a5.sds; Design = 68030_tk.tt4; DATE = 5/24/14; -TIME = 11:44:13; +TIME = 15:48:54; Source_Format = Pure_VHDL; Type = TT2; Pre_Fit_Time = 1; @@ -78,44 +78,44 @@ Usercode_Format = Hex; Layer = OFF; SIZE_1_ = pin,79,-,H,-; A_31_ = pin,4,-,B,-; -IPL_2_ = pin,68,-,G,-; -FC_1_ = pin,58,-,F,-; -AS_030 = pin,82,-,H,-; -DS_030 = pin,98,-,A,-; -nEXP_SPACE = pin,14,-,-,-; -BERR = pin,41,-,E,-; -BG_030 = pin,21,-,C,-; -BGACK_000 = pin,28,-,D,-; -CLK_030 = pin,64,-,-,-; -CLK_000 = pin,11,-,-,-; SIZE_0_ = pin,70,-,G,-; -CLK_OSZI = pin,61,-,-,-; +IPL_2_ = pin,68,-,G,-; A_30_ = pin,5,-,B,-; -CLK_DIV_OUT = pin,65,-,G,-; A_29_ = pin,6,-,B,-; A_28_ = pin,15,-,C,-; A_27_ = pin,16,-,C,-; +FC_1_ = pin,58,-,F,-; A_26_ = pin,17,-,C,-; -AVEC = pin,92,-,A,-; +AS_030 = pin,82,-,H,-; A_25_ = pin,18,-,C,-; -AVEC_EXP = pin,22,-,C,-; A_24_ = pin,19,-,C,-; +DS_030 = pin,98,-,A,-; A_23_ = pin,84,-,H,-; -VPA = pin,36,-,-,-; A_22_ = pin,85,-,H,-; A_21_ = pin,94,-,A,-; -RST = pin,86,-,-,-; +nEXP_SPACE = pin,14,-,-,-; A_20_ = pin,93,-,A,-; +BERR = pin,41,-,E,-; A_19_ = pin,97,-,A,-; -RW = pin,71,-,G,-; +BG_030 = pin,21,-,C,-; A_18_ = pin,95,-,A,-; A_17_ = pin,59,-,F,-; -AMIGA_BUS_DATA_DIR = pin,48,-,E,-; A_16_ = pin,96,-,A,-; -AMIGA_BUS_ENABLE_LOW = pin,20,-,C,-; -CIIN = pin,47,-,E,-; +BGACK_000 = pin,28,-,D,-; +CLK_030 = pin,64,-,-,-; +CLK_000 = pin,11,-,-,-; +CLK_OSZI = pin,61,-,-,-; +CLK_DIV_OUT = pin,65,-,G,-; +AVEC = pin,92,-,A,-; +AVEC_EXP = pin,22,-,C,-; +VPA = pin,36,-,-,-; +RST = pin,86,-,-,-; +RW = pin,71,-,G,-; A_0_ = pin,69,-,G,-; +AMIGA_BUS_DATA_DIR = pin,48,-,E,-; +AMIGA_BUS_ENABLE_LOW = pin,20,-,C,-; IPL_1_ = pin,56,-,F,-; +CIIN = pin,47,-,E,-; IPL_0_ = pin,67,-,G,-; DSACK_0_ = pin,80,-,H,-; FC_0_ = pin,57,-,F,-; @@ -135,31 +135,32 @@ RESET = pin,3,-,B,-; AMIGA_BUS_ENABLE = pin,34,-,D,-; IPL_030_1_ = pin,7,-,B,-; IPL_030_0_ = pin,8,-,B,-; -cpu_est_0_ = node,-,-,D,6; -cpu_est_1_ = node,-,-,D,9; -inst_AS_030_000_SYNC = node,-,-,H,2; -inst_DTACK_SYNC = node,-,-,A,0; -inst_VPA_D = node,-,-,G,1; -inst_VPA_SYNC = node,-,-,F,0; +inst_AS_030_000_SYNC = node,-,-,H,6; +inst_DTACK_SYNC = node,-,-,G,9; +inst_VPA_D = node,-,-,H,2; +inst_VPA_SYNC = node,-,-,G,5; inst_CLK_000_D0 = node,-,-,G,8; -inst_CLK_000_D1 = node,-,-,G,12; -inst_CLK_000_D2 = node,-,-,G,6; +inst_CLK_000_D1 = node,-,-,D,9; +inst_CLK_000_D2 = node,-,-,D,3; inst_CLK_000_D5 = node,-,-,H,13; -inst_CLK_OUT_PRE = node,-,-,G,9; -SM_AMIGA_6_ = node,-,-,H,5; SM_AMIGA_5_ = node,-,-,D,14; -cpu_est_2_ = node,-,-,D,2; -CLK_REF_1_ = node,-,-,H,14; -SM_AMIGA_7_ = node,-,-,H,1; -inst_CLK_000_D3 = node,-,-,H,10; +SM_AMIGA_6_ = node,-,-,H,5; +inst_CLK_000_D3 = node,-,-,H,14; SM_AMIGA_4_ = node,-,-,D,10; inst_CLK_000_D4 = node,-,-,H,9; -CLK_CNT_0_ = node,-,-,G,2; -CLK_CNT_1_ = node,-,-,G,13; -SM_AMIGA_3_ = node,-,-,B,5; -SM_AMIGA_1_ = node,-,-,B,9; -SM_AMIGA_2_ = node,-,-,G,5; -SM_AMIGA_0_ = node,-,-,H,6; +SM_AMIGA_7_ = node,-,-,H,1; +SM_AMIGA_3_ = node,-,-,B,9; +SM_AMIGA_1_ = node,-,-,B,5; +CLK_CNT_N_0_ = node,-,-,B,13; +CLK_CNT_N_1_ = node,-,-,G,13; +CLK_CNT_P_0_ = node,-,-,G,2; +CLK_CNT_P_1_ = node,-,-,G,6; +SM_AMIGA_2_ = node,-,-,B,2; +SM_AMIGA_0_ = node,-,-,H,10; +inst_CLK_OUT_PRE = node,-,-,G,1; +cpu_est_0_ = node,-,-,D,6; +cpu_est_1_ = node,-,-,G,12; +cpu_est_2_ = node,-,-,D,2; [GROUP ASSIGNMENTS] Layer = OFF; diff --git a/Logic/68030_tk.out b/Logic/68030_tk.out index 522b200..8b1d984 100644 --- a/Logic/68030_tk.out +++ b/Logic/68030_tk.out @@ -63062,4 +63062,314 @@ 5 A_29_ 1 -1 -1 1 4 5 -1 4 A_30_ 1 -1 -1 1 4 4 -1 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +98 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 321 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 + 30 LDS_000 5 324 3 0 30 -1 8 0 21 + 31 UDS_000 5 323 3 0 31 -1 5 0 21 + 65 E 5 328 6 0 65 -1 3 1 21 + 33 AMIGA_BUS_ENABLE 5 330 3 0 33 -1 3 0 20 + 8 IPL_030_2_ 5 320 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 332 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 331 1 0 6 -1 3 0 21 + 82 BGACK_030 5 326 7 0 82 -1 2 0 21 + 77 FPU_CS 5 327 7 0 77 -1 2 0 21 + 34 VMA 5 329 3 0 34 -1 2 1 21 + 32 AS_000 5 322 3 0 32 -1 2 0 21 + 28 BG_000 5 325 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 299 inst_CLK_000_D1 3 -1 3 4 1 3 6 7 -1 -1 1 0 21 + 298 inst_CLK_000_D0 3 -1 1 4 1 3 6 7 -1 -1 1 0 21 + 304 SM_AMIGA_7_ 3 -1 6 3 3 6 7 -1 -1 5 0 21 + 318 cpu_est_1_ 3 -1 1 3 1 3 6 -1 -1 4 0 21 + 328 RN_E 3 65 6 3 1 3 6 65 -1 3 1 21 + 319 cpu_est_2_ 3 -1 3 3 1 3 6 -1 -1 3 1 21 + 317 cpu_est_0_ 3 -1 3 3 1 3 6 -1 -1 3 0 21 + 327 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 322 RN_AS_000 3 32 3 3 1 3 6 32 -1 2 0 21 + 302 SM_AMIGA_6_ 3 -1 7 3 3 6 7 -1 -1 2 0 21 + 294 inst_AS_030_000_SYNC 3 -1 7 2 6 7 -1 -1 7 0 21 + 316 inst_CLK_OUT_PRE 3 -1 1 2 1 6 -1 -1 4 0 21 + 315 SM_AMIGA_0_ 3 -1 1 2 1 6 -1 -1 4 0 21 + 314 SM_AMIGA_2_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 309 SM_AMIGA_1_ 3 -1 7 2 1 7 -1 -1 3 0 21 + 329 RN_VMA 3 34 3 2 3 6 34 -1 2 1 21 + 326 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 310 CLK_CNT_N_0_ 3 -1 1 2 1 7 -1 -1 2 0 21 + 306 SM_AMIGA_4_ 3 -1 3 2 3 6 -1 -1 2 0 21 + 307 inst_CLK_000_D4 3 -1 7 2 1 7 -1 -1 1 0 21 + 305 inst_CLK_000_D3 3 -1 7 2 6 7 -1 -1 1 0 21 + 301 inst_CLK_000_D5 3 -1 7 2 1 7 -1 -1 1 0 21 + 300 inst_CLK_000_D2 3 -1 7 2 6 7 -1 -1 1 0 21 + 296 inst_VPA_D 3 -1 6 2 3 6 -1 -1 1 0 21 + 324 RN_LDS_000 3 30 3 1 3 30 -1 8 0 21 + 323 RN_UDS_000 3 31 3 1 3 31 -1 5 0 21 + 332 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 331 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 330 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 320 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 308 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 3 0 21 + 325 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 321 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 312 CLK_CNT_P_0_ 3 -1 1 1 1 -1 -1 2 0 21 + 303 SM_AMIGA_5_ 3 -1 3 1 3 -1 -1 2 0 21 + 297 inst_VPA_SYNC 3 -1 6 1 6 -1 -1 2 0 21 + 295 inst_DTACK_SYNC 3 -1 6 1 6 -1 -1 2 0 21 + 313 CLK_CNT_P_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 311 CLK_CNT_N_1_ 3 -1 7 1 1 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 1 3 60 -1 + 85 RST 1 -1 -1 4 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 3 3 6 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 1 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 3 3 6 7 -1 -1 +97 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 321 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 1 29 -1 1 0 21 + 30 LDS_000 5 324 3 0 30 -1 8 0 21 + 31 UDS_000 5 323 3 0 31 -1 5 0 21 + 65 E 5 327 6 0 65 -1 3 1 21 + 33 AMIGA_BUS_ENABLE 5 329 3 0 33 -1 3 0 20 + 8 IPL_030_2_ 5 320 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 331 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 330 1 0 6 -1 3 0 21 + 82 BGACK_030 5 325 7 0 82 -1 2 0 21 + 77 FPU_CS 5 326 7 0 77 -1 2 0 21 + 34 VMA 5 328 3 0 34 -1 2 1 21 + 32 AS_000 5 322 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 28 BG_000 0 3 0 28 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 299 inst_CLK_000_D1 3 -1 3 4 1 3 6 7 -1 -1 1 0 21 + 298 inst_CLK_000_D0 3 -1 6 4 1 3 6 7 -1 -1 1 0 21 + 318 cpu_est_1_ 3 -1 3 3 1 3 6 -1 -1 4 0 21 + 327 RN_E 3 65 6 3 1 3 6 65 -1 3 1 21 + 326 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 307 SM_AMIGA_7_ 3 -1 7 2 3 7 -1 -1 5 0 21 + 316 inst_CLK_OUT_PRE 3 -1 6 2 1 6 -1 -1 4 0 21 + 319 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 1 21 + 317 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 21 + 309 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 308 SM_AMIGA_3_ 3 -1 6 2 1 6 -1 -1 3 0 21 + 328 RN_VMA 3 34 3 2 1 3 34 -1 2 1 21 + 325 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 322 RN_AS_000 3 32 3 2 3 7 32 -1 2 0 21 + 310 CLK_CNT_N_0_ 3 -1 6 2 6 7 -1 -1 2 0 21 + 305 SM_AMIGA_4_ 3 -1 3 2 3 6 -1 -1 2 0 21 + 303 SM_AMIGA_6_ 3 -1 7 2 3 7 -1 -1 2 0 21 + 297 inst_VPA_SYNC 3 -1 1 2 1 6 -1 -1 2 0 21 + 295 inst_DTACK_SYNC 3 -1 1 2 1 6 -1 -1 2 0 21 + 306 inst_CLK_000_D4 3 -1 7 2 6 7 -1 -1 1 0 21 + 301 inst_CLK_000_D5 3 -1 7 2 6 7 -1 -1 1 0 21 + 296 inst_VPA_D 3 -1 1 2 1 3 -1 -1 1 0 21 + 324 RN_LDS_000 3 30 3 1 3 30 -1 8 0 21 + 294 inst_AS_030_000_SYNC 3 -1 7 1 7 -1 -1 7 0 21 + 323 RN_UDS_000 3 31 3 1 3 31 -1 5 0 21 + 315 SM_AMIGA_0_ 3 -1 7 1 7 -1 -1 4 0 21 + 331 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 330 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 329 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 320 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 314 SM_AMIGA_2_ 3 -1 6 1 6 -1 -1 3 0 21 + 321 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 312 CLK_CNT_P_0_ 3 -1 6 1 6 -1 -1 2 0 21 + 302 SM_AMIGA_5_ 3 -1 3 1 3 -1 -1 2 0 21 + 313 CLK_CNT_P_1_ 3 -1 6 1 6 -1 -1 1 0 21 + 311 CLK_CNT_N_1_ 3 -1 7 1 6 -1 -1 1 0 21 + 304 inst_CLK_000_D3 3 -1 7 1 7 -1 -1 1 0 21 + 300 inst_CLK_000_D2 3 -1 3 1 7 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 1 3 60 -1 + 85 RST 1 -1 -1 4 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 3 1 3 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 10 CLK_000 1 -1 -1 2 3 6 10 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 63 CLK_030 1 -1 -1 1 7 63 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +97 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 321 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 + 30 LDS_000 5 324 3 0 30 -1 8 0 21 + 31 UDS_000 5 323 3 0 31 -1 5 0 21 + 65 E 5 327 6 0 65 -1 3 1 21 + 33 AMIGA_BUS_ENABLE 5 329 3 0 33 -1 3 0 20 + 8 IPL_030_2_ 5 320 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 331 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 330 1 0 6 -1 3 0 21 + 82 BGACK_030 5 325 7 0 82 -1 2 0 21 + 77 FPU_CS 5 326 7 0 77 -1 2 0 21 + 34 VMA 5 328 3 0 34 -1 2 1 21 + 32 AS_000 5 322 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 28 BG_000 0 3 0 28 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 299 inst_CLK_000_D1 3 -1 3 4 1 3 6 7 -1 -1 1 0 21 + 298 inst_CLK_000_D0 3 -1 6 4 1 3 6 7 -1 -1 1 0 21 + 326 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 307 SM_AMIGA_7_ 3 -1 7 2 3 7 -1 -1 5 0 21 + 318 cpu_est_1_ 3 -1 6 2 3 6 -1 -1 4 0 21 + 316 inst_CLK_OUT_PRE 3 -1 6 2 1 6 -1 -1 4 0 21 + 327 RN_E 3 65 6 2 3 6 65 -1 3 1 21 + 319 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 1 21 + 317 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 21 + 309 SM_AMIGA_1_ 3 -1 1 2 1 7 -1 -1 3 0 21 + 308 SM_AMIGA_3_ 3 -1 1 2 1 6 -1 -1 3 0 21 + 328 RN_VMA 3 34 3 2 3 6 34 -1 2 1 21 + 325 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 322 RN_AS_000 3 32 3 2 3 7 32 -1 2 0 21 + 310 CLK_CNT_N_0_ 3 -1 1 2 1 6 -1 -1 2 0 21 + 305 SM_AMIGA_4_ 3 -1 3 2 1 3 -1 -1 2 0 21 + 303 SM_AMIGA_6_ 3 -1 7 2 3 7 -1 -1 2 0 21 + 297 inst_VPA_SYNC 3 -1 6 2 1 6 -1 -1 2 0 21 + 295 inst_DTACK_SYNC 3 -1 6 2 1 6 -1 -1 2 0 21 + 311 CLK_CNT_N_1_ 3 -1 6 2 1 6 -1 -1 1 0 21 + 306 inst_CLK_000_D4 3 -1 7 2 1 7 -1 -1 1 0 21 + 301 inst_CLK_000_D5 3 -1 7 2 1 7 -1 -1 1 0 21 + 296 inst_VPA_D 3 -1 7 2 3 6 -1 -1 1 0 21 + 324 RN_LDS_000 3 30 3 1 3 30 -1 8 0 21 + 294 inst_AS_030_000_SYNC 3 -1 7 1 7 -1 -1 7 0 21 + 323 RN_UDS_000 3 31 3 1 3 31 -1 5 0 21 + 315 SM_AMIGA_0_ 3 -1 7 1 7 -1 -1 4 0 21 + 331 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 330 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 329 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 320 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 314 SM_AMIGA_2_ 3 -1 1 1 1 -1 -1 3 0 21 + 321 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 312 CLK_CNT_P_0_ 3 -1 6 1 6 -1 -1 2 0 21 + 302 SM_AMIGA_5_ 3 -1 3 1 3 -1 -1 2 0 21 + 313 CLK_CNT_P_1_ 3 -1 6 1 6 -1 -1 1 0 21 + 304 inst_CLK_000_D3 3 -1 7 1 7 -1 -1 1 0 21 + 300 inst_CLK_000_D2 3 -1 3 1 7 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 1 3 60 -1 + 85 RST 1 -1 -1 4 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 3 3 6 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 63 CLK_030 1 -1 -1 1 7 63 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 7 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 6 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 \ No newline at end of file diff --git a/Logic/68030_tk.plc b/Logic/68030_tk.plc index ebb932a..9a84c24 100644 --- a/Logic/68030_tk.plc +++ b/Logic/68030_tk.plc @@ -8,49 +8,49 @@ ; Source file 68030_tk.tt4 ; FITTER-generated Placements. ; DEVICE mach447a -; DATE Sat May 24 11:44:13 2014 +; DATE Sat May 24 15:48:54 2014 Pin 79 SIZE_1_ Pin 4 A_31_ -Pin 68 IPL_2_ -Pin 58 FC_1_ -Pin 82 AS_030 -Pin 98 DS_030 -Pin 14 nEXP_SPACE -Pin 41 BERR Comb ; S6=1 S9=1 Pair 203 -Pin 21 BG_030 -Pin 28 BGACK_000 -Pin 64 CLK_030 -Pin 11 CLK_000 Pin 70 SIZE_0_ -Pin 61 CLK_OSZI +Pin 68 IPL_2_ Pin 5 A_30_ -Pin 65 CLK_DIV_OUT Reg ; S6=1 S9=1 Pair 245 Pin 6 A_29_ Pin 15 A_28_ Pin 16 A_27_ +Pin 58 FC_1_ Pin 17 A_26_ -Pin 92 AVEC Comb ; S6=1 S9=1 Pair 107 +Pin 82 AS_030 Pin 18 A_25_ -Pin 22 AVEC_EXP Comb ; S6=1 S9=1 Pair 149 Pin 19 A_24_ +Pin 98 DS_030 Pin 84 A_23_ -Pin 36 VPA Pin 85 A_22_ Pin 94 A_21_ -Pin 86 RST +Pin 14 nEXP_SPACE Pin 93 A_20_ +Pin 41 BERR Comb ; S6=1 S9=1 Pair 203 Pin 97 A_19_ -Pin 71 RW +Pin 21 BG_030 Pin 95 A_18_ Pin 59 A_17_ -Pin 48 AMIGA_BUS_DATA_DIR Comb ; S6=1 S9=1 Pair 197 Pin 96 A_16_ -Pin 20 AMIGA_BUS_ENABLE_LOW Comb ; S6=1 S9=1 Pair 167 -Pin 47 CIIN Comb ; S6=1 S9=1 Pair 215 +Pin 28 BGACK_000 +Pin 64 CLK_030 +Pin 11 CLK_000 +Pin 61 CLK_OSZI +Pin 65 CLK_DIV_OUT Reg ; S6=1 S9=1 Pair 245 +Pin 92 AVEC Comb ; S6=1 S9=1 Pair 107 +Pin 22 AVEC_EXP Comb ; S6=1 S9=1 Pair 149 +Pin 36 VPA +Pin 86 RST +Pin 71 RW Pin 69 A_0_ +Pin 48 AMIGA_BUS_DATA_DIR Comb ; S6=1 S9=1 Pair 197 +Pin 20 AMIGA_BUS_ENABLE_LOW Comb ; S6=1 S9=1 Pair 167 Pin 56 IPL_1_ +Pin 47 CIIN Comb ; S6=1 S9=1 Pair 215 Pin 67 IPL_0_ Pin 80 DSACK_0_ Comb ; S6=1 S9=1 Pair 287 Pin 57 FC_0_ @@ -61,12 +61,12 @@ Pin 32 UDS_000 Reg ; S6=1 S9=1 Pair 191 Pin 31 LDS_000 Reg ; S6=1 S9=1 Pair 185 Pin 29 BG_000 Reg ; S6=1 S9=1 Pair 193 Pin 83 BGACK_030 Reg ; S6=1 S9=1 Pair 275 -Pin 10 CLK_EXP Reg ; S6=1 S9=0 Pair 125 +Pin 10 CLK_EXP Reg ; S6=0 S9=1 Pair 125 Pin 78 FPU_CS Reg ; S6=1 S9=1 Pair 269 Pin 30 DTACK Reg ; S6=1 S9=1 Pair 173 Pin 66 E Reg ; S6=1 S9=1 Pair 251 Pin 35 VMA Reg ; S6=1 S9=1 Pair 175 -Pin 3 RESET Reg ; S6=1 S9=0 Pair 127 +Pin 3 RESET Reg ; S6=0 S9=1 Pair 127 Pin 34 AMIGA_BUS_ENABLE Reg ; S6=1 S9=0 Pair 179 Pin 7 IPL_030_1_ Reg ; S6=1 S9=1 Pair 143 Pin 8 IPL_030_0_ Reg ; S6=1 S9=1 Pair 137 @@ -75,7 +75,6 @@ Node 281 RN_DSACK_1_ Reg ; S6=1 S9=1 Node 181 RN_AS_000 Reg ; S6=1 S9=1 Node 191 RN_UDS_000 Reg ; S6=1 S9=1 Node 185 RN_LDS_000 Reg ; S6=1 S9=1 -Node 193 RN_BG_000 Reg ; S6=1 S9=1 Node 275 RN_BGACK_030 Reg ; S6=1 S9=1 Node 269 RN_FPU_CS Reg ; S6=1 S9=1 Node 173 RN_DTACK Reg ; S6=1 S9=1 @@ -84,30 +83,31 @@ Node 175 RN_VMA Reg ; S6=1 S9=1 Node 179 RN_AMIGA_BUS_ENABLE Reg ; S6=1 S9=0 Node 143 RN_IPL_030_1_ Reg ; S6=1 S9=1 Node 137 RN_IPL_030_0_ Reg ; S6=1 S9=1 -Node 182 cpu_est_0_ Reg ; S6=1 S9=0 -Node 187 cpu_est_1_ Reg ; S6=1 S9=0 -Node 272 inst_AS_030_000_SYNC Reg ; S6=1 S9=1 -Node 101 inst_DTACK_SYNC Reg ; S6=1 S9=1 -Node 247 inst_VPA_D Reg ; S6=1 S9=1 -Node 221 inst_VPA_SYNC Reg ; S6=1 S9=1 -Node 257 inst_CLK_000_D0 Reg ; S6=1 S9=1 -Node 263 inst_CLK_000_D1 Reg ; S6=1 S9=1 -Node 254 inst_CLK_000_D2 Reg ; S6=1 S9=1 -Node 289 inst_CLK_000_D5 Reg ; S6=1 S9=0 -Node 259 inst_CLK_OUT_PRE Reg ; S6=1 S9=1 -Node 277 SM_AMIGA_6_ Reg ; S6=0 S9=1 +Node 278 inst_AS_030_000_SYNC Reg ; S6=1 S9=1 +Node 259 inst_DTACK_SYNC Reg ; S6=0 S9=1 +Node 272 inst_VPA_D Reg ; S6=1 S9=1 +Node 253 inst_VPA_SYNC Reg ; S6=0 S9=1 +Node 257 inst_CLK_000_D0 Reg ; S6=0 S9=1 +Node 187 inst_CLK_000_D1 Reg ; S6=1 S9=1 +Node 178 inst_CLK_000_D2 Reg ; S6=1 S9=1 +Node 289 inst_CLK_000_D5 Reg ; S6=1 S9=1 Node 194 SM_AMIGA_5_ Reg ; S6=0 S9=1 -Node 176 cpu_est_2_ Reg ; S6=1 S9=0 -Node 290 CLK_REF_1_ Lat ; S6=1 S9=0 -Node 271 SM_AMIGA_7_ Reg ; S6=1 S9=1 -Node 284 inst_CLK_000_D3 Reg ; S6=1 S9=0 +Node 277 SM_AMIGA_6_ Reg ; S6=0 S9=1 +Node 290 inst_CLK_000_D3 Reg ; S6=1 S9=1 Node 188 SM_AMIGA_4_ Reg ; S6=0 S9=1 -Node 283 inst_CLK_000_D4 Reg ; S6=1 S9=0 -Node 248 CLK_CNT_0_ Reg ; S6=1 S9=1 -Node 265 CLK_CNT_1_ Reg ; S6=1 S9=1 -Node 133 SM_AMIGA_3_ Reg ; S6=0 S9=1 -Node 139 SM_AMIGA_1_ Reg ; S6=0 S9=1 -Node 253 SM_AMIGA_2_ Reg ; S6=1 S9=0 -Node 278 SM_AMIGA_0_ Reg ; S6=0 S9=1 +Node 283 inst_CLK_000_D4 Reg ; S6=1 S9=1 +Node 271 SM_AMIGA_7_ Reg ; S6=1 S9=1 +Node 139 SM_AMIGA_3_ Reg ; S6=0 S9=1 +Node 133 SM_AMIGA_1_ Reg ; S6=0 S9=1 +Node 145 CLK_CNT_N_0_ Reg ; S6=0 S9=1 +Node 265 CLK_CNT_N_1_ Reg ; S6=1 S9=1 +Node 248 CLK_CNT_P_0_ Reg ; S6=1 S9=1 +Node 254 CLK_CNT_P_1_ Reg ; S6=1 S9=1 +Node 128 SM_AMIGA_2_ Reg ; S6=0 S9=1 +Node 284 SM_AMIGA_0_ Reg ; S6=0 S9=1 +Node 247 inst_CLK_OUT_PRE Reg ; S6=1 S9=1 +Node 182 cpu_est_0_ Reg ; S6=0 S9=1 +Node 263 cpu_est_1_ Reg ; S6=1 S9=1 +Node 176 cpu_est_2_ Reg ; S6=0 S9=1 ; Unused Pins & Nodes ; -> None Found. diff --git a/Logic/68030_tk.prd b/Logic/68030_tk.prd index 2b55edc..c8a6e40 100644 --- a/Logic/68030_tk.prd +++ b/Logic/68030_tk.prd @@ -5,8 +5,8 @@ |--------------------------------------------| -Start: Sat May 24 11:44:13 2014 -End : Sat May 24 11:44:13 2014 $$$ Elapsed time: 00:00:00 +Start: Sat May 24 15:48:54 2014 +End : Sat May 24 15:48:54 2014 $$$ Elapsed time: 00:00:00 =========================================================================== Part [C:/Program Files (x86)/ispLever/ispcpld/dat/mach4a/mach447a] Design [68030_tk.tt4] @@ -21,16 +21,16 @@ Part [C:/Program Files (x86)/ispLever/ispcpld/dat/mach4a/mach447a] Design [68030 | | +- Signals to Place | | +----- Logic Array Inputs | | | +- Placed | | | +- Array Inputs Used _|____|____|____|_______________|____|_____________|___|________________ - 0 | 16 | 2 | 2 => 100% | 8 | 7 => 87% | 33 | 8 => 24% - 1 | 16 | 7 | 7 => 100% | 8 | 8 => 100% | 33 | 19 => 57% + 0 | 16 | 1 | 1 => 100% | 8 | 7 => 87% | 33 | 0 => 0% + 1 | 16 | 9 | 9 => 100% | 8 | 8 => 100% | 33 | 20 => 60% 2 | 16 | 2 | 2 => 100% | 8 | 8 => 100% | 33 | 1 => 3% - 3 | 16 | 12 | 12 => 100% | 8 | 8 => 100% | 33 | 30 => 90% + 3 | 16 | 13 | 13 => 100% | 8 | 8 => 100% | 33 | 28 => 84% 4 | 16 | 3 | 3 => 100% | 8 | 3 => 37% | 33 | 14 => 42% - 5 | 16 | 1 | 1 => 100% | 8 | 4 => 50% | 33 | 12 => 36% - 6 | 16 | 10 | 10 => 100% | 8 | 7 => 87% | 33 | 18 => 54% + 5 | 16 | 0 | 0 => n/a | 8 | 4 => 50% | 33 | 0 => 0% + 6 | 16 | 10 | 10 => 100% | 8 | 7 => 87% | 33 | 20 => 60% 7 | 16 | 12 | 12 => 100% | 8 | 8 => 100% | 33 | 27 => 81% ---|----|----|------------|-------|------------|-----|------------------ - | Avg number of array inputs in used blocks : 16.13 => 48% + | Avg number of array inputs in used blocks : 18.33 => 55% * Input/Clock Signal count: 35 -> placed: 35 = 100% @@ -40,10 +40,10 @@ _|____|____|____|_______________|____|_____________|___|________________ I/O Pins : 64 53 => 82% Clock Only Pins : 0 0 => 0% Clock/Input Pins : 4 4 => 100% - Logic Blocks : 8 8 => 100% - Macrocells : 128 49 => 38% - PT Clusters : 128 33 => 25% - - Single PT Clusters : 128 19 => 14% + Logic Blocks : 8 6 => 75% + Macrocells : 128 50 => 39% + PT Clusters : 128 31 => 24% + - Single PT Clusters : 128 21 => 16% Input Registers : 0 * Routing Completion: 100% @@ -63,7 +63,7 @@ ___|__|__|____|____________________________________________________________ 3| 2|OUT| 20|=> ....|....| AMIGA_BUS_ENABLE_LOW 4| 3| IO| 33|=> ....|....| AS_000 |=> Paired w/: RN_AS_000 - 5| 7|INP| 82|=> 0..3|.5.7| AS_030 + 5| 7|INP| 82|=> ...3|..67| AS_030 6| 0|OUT| 92|=> ....|....| AVEC 7| 2|OUT| 22|=> ....|....| AVEC_EXP 8| 6|INP| 69|=> ...3|....| A_0_ @@ -87,52 +87,50 @@ ___|__|__|____|____________________________________________________________ 26| 3|INP| 28|=> ....|...7| BGACK_000 27| 7| IO| 83|=> ....|....| BGACK_030 |=> Paired w/: RN_BGACK_030 - 28| 3| IO| 29|=> ....|....| BG_000 - |=> Paired w/: RN_BG_000 + 28| 3|OUT| 29|=> ....|....| BG_000 29| 2|INP| 21|=> ...3|....| BG_030 30| 4|OUT| 47|=> ....|....| CIIN 31| +|INP| 11|=> ....|..6.| CLK_000 - 32| +|INP| 64|=> ...3|...7| CLK_030 - 33| 6|NOD| . |=> ....|..6.| CLK_CNT_0_ - 34| 6|NOD| . |=> ....|..6.| CLK_CNT_1_ - 35| 6|OUT| 65|=> ....|....| CLK_DIV_OUT - 36| 1|OUT| 10|=> ....|....| CLK_EXP - 37| +|Cin| 61|=> 01.3|.567| CLK_OSZI - 38| 7|NOD| . |=> ....|..6.| CLK_REF_1_ - 39| 7|OUT| 80|=> ....|....| DSACK_0_ - 40| 7| IO| 81|=> ...3|....| DSACK_1_ + 32| +|INP| 64|=> ....|...7| CLK_030 + 33| 1|NOD| . |=> .1..|..6.| CLK_CNT_N_0_ + 34| 6|NOD| . |=> .1..|..6.| CLK_CNT_N_1_ + 35| 6|NOD| . |=> ....|..6.| CLK_CNT_P_0_ + 36| 6|NOD| . |=> ....|..6.| CLK_CNT_P_1_ + 37| 6|OUT| 65|=> ....|....| CLK_DIV_OUT + 38| 1|OUT| 10|=> ....|....| CLK_EXP + 39| +|Cin| 61|=> ...3|....| CLK_OSZI + 40| 7|OUT| 80|=> ....|....| DSACK_0_ + 41| 7| IO| 81|=> ...3|....| DSACK_1_ |=> Paired w/: RN_DSACK_1_ - 41| 0|INP| 98|=> ...3|....| DS_030 - 42| 3| IO| 30|=> 0...|....| DTACK - 43| 6| IO| 66|=> ....|....| E + 42| 0|INP| 98|=> ...3|....| DS_030 + 43| 3| IO| 30|=> ....|..6.| DTACK + 44| 6| IO| 66|=> ....|....| E |=> Paired w/: RN_E - 44| 5|INP| 57|=> ....|...7| FC_0_ - 45| 5|INP| 58|=> ....|...7| FC_1_ - 46| 7| IO| 78|=> ....|....| FPU_CS + 45| 5|INP| 57|=> ....|...7| FC_0_ + 46| 5|INP| 58|=> ....|...7| FC_1_ + 47| 7| IO| 78|=> ....|....| FPU_CS |=> Paired w/: RN_FPU_CS - 47| 1| IO| 8|=> ....|....| IPL_030_0_ + 48| 1| IO| 8|=> ....|....| IPL_030_0_ |=> Paired w/: RN_IPL_030_0_ - 48| 1| IO| 7|=> ....|....| IPL_030_1_ + 49| 1| IO| 7|=> ....|....| IPL_030_1_ |=> Paired w/: RN_IPL_030_1_ - 49| 1| IO| 9|=> ....|....| IPL_030_2_ + 50| 1| IO| 9|=> ....|....| IPL_030_2_ |=> Paired w/: RN_IPL_030_2_ - 50| 6|INP| 67|=> .1..|....| IPL_0_ - 51| 5|INP| 56|=> .1..|....| IPL_1_ - 52| 6|INP| 68|=> .1..|....| IPL_2_ - 53| 3| IO| 31|=> ....|....| LDS_000 + 51| 6|INP| 67|=> .1..|....| IPL_0_ + 52| 5|INP| 56|=> .1..|....| IPL_1_ + 53| 6|INP| 68|=> .1..|....| IPL_2_ + 54| 3| IO| 31|=> ....|....| LDS_000 |=> Paired w/: RN_LDS_000 - 54| 1|OUT| 3|=> ....|....| RESET - 55| 3|NOD| . |=> ...3|....| RN_AMIGA_BUS_ENABLE + 55| 1|OUT| 3|=> ....|....| RESET + 56| 3|NOD| . |=> ...3|....| RN_AMIGA_BUS_ENABLE |=> Paired w/: AMIGA_BUS_ENABLE - 56| 3|NOD| . |=> ...3|...7| RN_AS_000 + 57| 3|NOD| . |=> ...3|...7| RN_AS_000 |=> Paired w/: AS_000 - 57| 7|NOD| . |=> ...3|...7| RN_BGACK_030 + 58| 7|NOD| . |=> ...3|...7| RN_BGACK_030 |=> Paired w/: BGACK_030 - 58| 3|NOD| . |=> ...3|....| RN_BG_000 - |=> Paired w/: BG_000 59| 7|NOD| . |=> ....|...7| RN_DSACK_1_ |=> Paired w/: DSACK_1_ - 60| 6|NOD| . |=> ...3|.56.| RN_E + 60| 6|NOD| . |=> ...3|..6.| RN_E |=> Paired w/: E 61| 7|NOD| . |=> ..2.|4..7| RN_FPU_CS |=> Paired w/: FPU_CS @@ -146,16 +144,16 @@ ___|__|__|____|____________________________________________________________ |=> Paired w/: LDS_000 66| 3|NOD| . |=> ...3|....| RN_UDS_000 |=> Paired w/: UDS_000 - 67| 3|NOD| . |=> ...3|.5..| RN_VMA + 67| 3|NOD| . |=> ...3|..6.| RN_VMA |=> Paired w/: VMA - 68| +|INP| 86|=> 01.3|.567| RST + 68| +|INP| 86|=> .1.3|..67| RST 69| 6|INP| 71|=> ...3|4...| RW 70| 6|INP| 70|=> ...3|....| SIZE_0_ 71| 7|INP| 79|=> ...3|....| SIZE_1_ 72| 7|NOD| . |=> ....|...7| SM_AMIGA_0_ 73| 1|NOD| . |=> .1..|...7| SM_AMIGA_1_ - 74| 6|NOD| . |=> .1..|..6.| SM_AMIGA_2_ - 75| 1|NOD| . |=> 01..|.56.| SM_AMIGA_3_ + 74| 1|NOD| . |=> .1..|....| SM_AMIGA_2_ + 75| 1|NOD| . |=> .1..|..6.| SM_AMIGA_3_ 76| 3|NOD| . |=> .1.3|....| SM_AMIGA_4_ 77| 3|NOD| . |=> ...3|....| SM_AMIGA_5_ 78| 7|NOD| . |=> ...3|...7| SM_AMIGA_6_ @@ -164,21 +162,21 @@ ___|__|__|____|____________________________________________________________ |=> Paired w/: RN_UDS_000 81| 3| IO| 35|=> ....|....| VMA |=> Paired w/: RN_VMA - 82| +|INP| 36|=> ....|..6.| VPA - 83| 3|NOD| . |=> ...3|.56.| cpu_est_0_ - 84| 3|NOD| . |=> ...3|.56.| cpu_est_1_ - 85| 3|NOD| . |=> ...3|.56.| cpu_est_2_ + 82| +|INP| 36|=> ....|...7| VPA + 83| 3|NOD| . |=> ...3|..6.| cpu_est_0_ + 84| 6|NOD| . |=> ...3|..6.| cpu_est_1_ + 85| 3|NOD| . |=> ...3|..6.| cpu_est_2_ 86| 7|NOD| . |=> ....|...7| inst_AS_030_000_SYNC - 87| 6|NOD| . |=> 01.3|.567| inst_CLK_000_D0 - 88| 6|NOD| . |=> .1.3|..67| inst_CLK_000_D1 - 89| 6|NOD| . |=> ....|...7| inst_CLK_000_D2 + 87| 6|NOD| . |=> .1.3|..67| inst_CLK_000_D0 + 88| 3|NOD| . |=> .1.3|..67| inst_CLK_000_D1 + 89| 3|NOD| . |=> ....|...7| inst_CLK_000_D2 90| 7|NOD| . |=> ....|...7| inst_CLK_000_D3 91| 7|NOD| . |=> .1..|...7| inst_CLK_000_D4 92| 7|NOD| . |=> .1..|...7| inst_CLK_000_D5 93| 6|NOD| . |=> .1..|..6.| inst_CLK_OUT_PRE - 94| 0|NOD| . |=> 01..|..6.| inst_DTACK_SYNC - 95| 6|NOD| . |=> 0..3|.5..| inst_VPA_D - 96| 5|NOD| . |=> .1..|.56.| inst_VPA_SYNC + 94| 6|NOD| . |=> .1..|..6.| inst_DTACK_SYNC + 95| 7|NOD| . |=> ...3|..6.| inst_VPA_D + 96| 6|NOD| . |=> .1..|..6.| inst_VPA_SYNC 97| +|INP| 14|=> ...3|...7| nEXP_SPACE --------------------------------------------------------------------------- =========================================================================== @@ -299,7 +297,7 @@ ____|_____|_________|______________________________________________________ | Sig Type-+ | | | | | | | XOR to Mcell Assignment | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ - 0|inst_DTACK_SYNC|NOD| | S | 2 | 4 to [ 0]| 1 XOR free + 0| | ? | | S | | 4 free | 1 XOR free 1| | ? | | S | | 4 free | 1 XOR free 2| | ? | | S | | 4 free | 1 XOR free 3| | ? | | S | | 4 free | 1 XOR free @@ -326,8 +324,8 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0|inst_DTACK_SYNC|NOD| | S | 2 |=> can support up to [ 15] logic PT(s) - 1| | ? | | S | |=> can support up to [ 15] logic PT(s) + 0| | ? | | S | |=> can support up to [ 15] logic PT(s) + 1| | ? | | S | |=> can support up to [ 20] logic PT(s) 2| | ? | | S | |=> can support up to [ 19] logic PT(s) 3| | ? | | S | |=> can support up to [ 19] logic PT(s) 4| AVEC|OUT| | S | 1 |=> can support up to [ 20] logic PT(s) @@ -351,7 +349,7 @@ _|_________________|__|__|___|_____|_______________________________________ | Sig Type---+ | to | Block [ 0] IO Pin | Device Pin | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ - 0|inst_DTACK_SYNC|NOD| | => | 5 6 7 0 | 96 97 98 91 + 0| | | | => | 5 6 7 0 | 96 97 98 91 1| | | | => | 5 6 7 0 | 96 97 98 91 2| | | | => | 6 7 0 1 | 97 98 91 92 3| | | | => | 6 7 0 1 | 97 98 91 92 @@ -415,7 +413,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number ---|-------|----|---|---|----------|------|-|------------------------------ 0 [IOpin 0 | 91| -| | ] [RegIn 0 |102| -| | ] - [MCell 0 |101|NOD inst_DTACK_SYNC| |*] + [MCell 0 |101| -| | ] [MCell 1 |103| -| | ] 1 [IOpin 1 | 92|OUT AVEC|*| ] @@ -453,46 +451,6 @@ IMX No. | +---- Block IO Pin or Macrocell Number [MCell 14 |122| -| | ] [MCell 15 |124| -| | ] --------------------------------------------------------------------------- -=========================================================================== - < Block [ 0] > Logic Array Fan-in -=========================================================================== - +- Central Switch Matrix No. - | Src (ABEL Node/Pin#) Signal ---|--|--------------------|--------------------------------------------------- -Mux00| Input Pin ( 86)| RST -Mux01| ... | ... -Mux02| ... | ... -Mux03| ... | ... -Mux04| Input Pin ( 61)| CLK_OSZI -Mux05| ... | ... -Mux06| ... | ... -Mux07| ... | ... -Mux08| ... | ... -Mux09| IOPin 7 3 ( 82)| AS_030 -Mux10| Mcel 6 8 ( 257)| inst_CLK_000_D0 -Mux11| ... | ... -Mux12| ... | ... -Mux13| ... | ... -Mux14| IOPin 3 5 ( 30)| DTACK -Mux15| Mcel 0 0 ( 101)| inst_DTACK_SYNC -Mux16| ... | ... -Mux17| ... | ... -Mux18| ... | ... -Mux19| ... | ... -Mux20| ... | ... -Mux21| ... | ... -Mux22| ... | ... -Mux23| ... | ... -Mux24| Mcel 6 1 ( 247)| inst_VPA_D -Mux25| ... | ... -Mux26| ... | ... -Mux27| ... | ... -Mux28| Mcel 1 5 ( 133)| SM_AMIGA_3_ -Mux29| ... | ... -Mux30| ... | ... -Mux31| ... | ... -Mux32| ... | ... ---------------------------------------------------------------------------- =========================================================================== < Block [ 1] > Macrocell (MCell) Cluster Assignments =========================================================================== @@ -503,20 +461,20 @@ Mux32| ... | ... | Sig Type-+ | | | | | | | XOR to Mcell Assignment | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ - 0| CLK_EXP|OUT| | A | 1 | 2 free | 1 XOR to [ 0] for 1 PT sig - 1| RESET|OUT| | A | 1 | 2 free | 1 XOR to [ 1] for 1 PT sig - 2| | ? | | S | | 4 free | 1 XOR free + 0| CLK_EXP|OUT| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig + 1| RESET|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig + 2| SM_AMIGA_2_|NOD| | S | 3 | 4 to [ 2]| 1 XOR free 3| | ? | | S | | 4 free | 1 XOR free 4| IPL_030_2_| IO| | S | 3 | 4 to [ 4]| 1 XOR free - 5| SM_AMIGA_3_|NOD| | S | 3 | 4 to [ 5]| 1 XOR free + 5| SM_AMIGA_1_|NOD| | S | 3 | 4 to [ 5]| 1 XOR free 6| | ? | | S | | 4 free | 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free 8| IPL_030_0_| IO| | S | 3 | 4 to [ 8]| 1 XOR free - 9| SM_AMIGA_1_|NOD| | S | 3 | 4 to [ 9]| 1 XOR free + 9| SM_AMIGA_3_|NOD| | S | 3 | 4 to [ 9]| 1 XOR free 10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free 12| IPL_030_1_| IO| | S | 3 | 4 to [12]| 1 XOR free -13| | ? | | S | | 4 free | 1 XOR free +13| CLK_CNT_N_0_|NOD| | S | 2 | 4 to [13]| 1 XOR free 14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- @@ -530,21 +488,21 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| CLK_EXP|OUT| | A | 1 |=> can support up to [ 10] logic PT(s) - 1| RESET|OUT| | A | 1 |=> can support up to [ 15] logic PT(s) - 2| | ? | | S | |=> can support up to [ 12] logic PT(s) - 3| | ? | | S | |=> can support up to [ 10] logic PT(s) + 0| CLK_EXP|OUT| | S | 1 |=> can support up to [ 9] logic PT(s) + 1| RESET|OUT| | S | 1 |=> can support up to [ 14] logic PT(s) + 2| SM_AMIGA_2_|NOD| | S | 3 |=> can support up to [ 14] logic PT(s) + 3| | ? | | S | |=> can support up to [ 5] logic PT(s) 4| IPL_030_2_| IO| | S | 3 |=> can support up to [ 15] logic PT(s) - 5| SM_AMIGA_3_|NOD| | S | 3 |=> can support up to [ 15] logic PT(s) + 5| SM_AMIGA_1_|NOD| | S | 3 |=> can support up to [ 15] logic PT(s) 6| | ? | | S | |=> can support up to [ 10] logic PT(s) 7| | ? | | S | |=> can support up to [ 10] logic PT(s) 8| IPL_030_0_| IO| | S | 3 |=> can support up to [ 15] logic PT(s) - 9| SM_AMIGA_1_|NOD| | S | 3 |=> can support up to [ 15] logic PT(s) + 9| SM_AMIGA_3_|NOD| | S | 3 |=> can support up to [ 15] logic PT(s) 10| | ? | | S | |=> can support up to [ 10] logic PT(s) -11| | ? | | S | |=> can support up to [ 15] logic PT(s) -12| IPL_030_1_| IO| | S | 3 |=> can support up to [ 20] logic PT(s) -13| | ? | | S | |=> can support up to [ 15] logic PT(s) -14| | ? | | S | |=> can support up to [ 15] logic PT(s) +11| | ? | | S | |=> can support up to [ 10] logic PT(s) +12| IPL_030_1_| IO| | S | 3 |=> can support up to [ 15] logic PT(s) +13| CLK_CNT_N_0_|NOD| | S | 2 |=> can support up to [ 15] logic PT(s) +14| | ? | | S | |=> can support up to [ 10] logic PT(s) 15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- =========================================================================== @@ -557,18 +515,18 @@ _|_________________|__|__|___|_____|_______________________________________ _|_________________|__|_____|____________________|________________________ 0| CLK_EXP|OUT| | => | 5 6 7 ( 0)| 5 4 3 ( 10) 1| RESET|OUT| | => | 5 6 ( 7) 0 | 5 4 ( 3) 10 - 2| | | | => | 6 7 0 1 | 4 3 10 9 + 2| SM_AMIGA_2_|NOD| | => | 6 7 0 1 | 4 3 10 9 3| | | | => | 6 7 0 1 | 4 3 10 9 4| IPL_030_2_| IO| | => | 7 0 ( 1) 2 | 3 10 ( 9) 8 - 5| SM_AMIGA_3_|NOD| | => | 7 0 1 2 | 3 10 9 8 + 5| SM_AMIGA_1_|NOD| | => | 7 0 1 2 | 3 10 9 8 6| | | | => | 0 1 2 3 | 10 9 8 7 7| | | | => | 0 1 2 3 | 10 9 8 7 8| IPL_030_0_| IO| | => | 1 ( 2) 3 4 | 9 ( 8) 7 6 - 9| SM_AMIGA_1_|NOD| | => | 1 2 3 4 | 9 8 7 6 + 9| SM_AMIGA_3_|NOD| | => | 1 2 3 4 | 9 8 7 6 10| | | | => | 2 3 4 5 | 8 7 6 5 11| | | | => | 2 3 4 5 | 8 7 6 5 12| IPL_030_1_| IO| | => |( 3) 4 5 6 |( 7) 6 5 4 -13| | | | => | 3 4 5 6 | 7 6 5 4 +13| CLK_CNT_N_0_|NOD| | => | 3 4 5 6 | 7 6 5 4 14| | | | => | 4 5 6 7 | 6 5 4 3 15| | | | => | 4 5 6 7 | 6 5 4 3 --------------------------------------------------------------------------- @@ -627,13 +585,13 @@ IMX No. | +---- Block IO Pin or Macrocell Number 1 [IOpin 1 | 9| IO IPL_030_2_|*| ] paired w/[ RN_IPL_030_2_] [RegIn 1 |129| -| | ] - [MCell 2 |128| -| | ] + [MCell 2 |128|NOD SM_AMIGA_2_| |*] [MCell 3 |130| -| | ] 2 [IOpin 2 | 8| IO IPL_030_0_|*| ] paired w/[ RN_IPL_030_0_] [RegIn 2 |132| -| | ] [MCell 4 |131|NOD RN_IPL_030_2_| |*] paired w/[ IPL_030_2_] - [MCell 5 |133|NOD SM_AMIGA_3_| |*] + [MCell 5 |133|NOD SM_AMIGA_1_| |*] 3 [IOpin 3 | 7| IO IPL_030_1_|*| ] paired w/[ RN_IPL_030_1_] [RegIn 3 |135| -| | ] @@ -643,7 +601,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 4 [IOpin 4 | 6|INP A_29_|*|*] [RegIn 4 |138| -| | ] [MCell 8 |137|NOD RN_IPL_030_0_| |*] paired w/[ IPL_030_0_] - [MCell 9 |139|NOD SM_AMIGA_1_| |*] + [MCell 9 |139|NOD SM_AMIGA_3_| |*] 5 [IOpin 5 | 5|INP A_30_|*|*] [RegIn 5 |141| -| | ] @@ -653,7 +611,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 6 [IOpin 6 | 4|INP A_31_|*|*] [RegIn 6 |144| -| | ] [MCell 12 |143|NOD RN_IPL_030_1_| |*] paired w/[ IPL_030_1_] - [MCell 13 |145| -| | ] + [MCell 13 |145|NOD CLK_CNT_N_0_| |*] 7 [IOpin 7 | 3|OUT RESET|*| ] [RegIn 7 |147| -| | ] @@ -672,32 +630,32 @@ Mux02| Mcel 3 10 ( 188)| SM_AMIGA_4_ Mux03| IOPin 5 4 ( 56)| IPL_1_ Mux04| IOPin 6 3 ( 68)| IPL_2_ Mux05| Mcel 7 9 ( 283)| inst_CLK_000_D4 -Mux06| Mcel 1 9 ( 139)| SM_AMIGA_1_ +Mux06| Mcel 1 9 ( 139)| SM_AMIGA_3_ Mux07| Mcel 7 13 ( 289)| inst_CLK_000_D5 Mux08| Mcel 1 8 ( 137)| RN_IPL_030_0_ -Mux09| ... | ... -Mux10| Mcel 6 9 ( 259)| inst_CLK_OUT_PRE +Mux09| Mcel 6 13 ( 265)| CLK_CNT_N_1_ +Mux10| Mcel 1 2 ( 128)| SM_AMIGA_2_ Mux11| ... | ... -Mux12| ... | ... +Mux12| Mcel 6 9 ( 259)| inst_DTACK_SYNC Mux13| Mcel 6 8 ( 257)| inst_CLK_000_D0 -Mux14| Mcel 6 12 ( 263)| inst_CLK_000_D1 -Mux15| Mcel 0 0 ( 101)| inst_DTACK_SYNC +Mux14| ... | ... +Mux15| ... | ... Mux16| ... | ... Mux17| ... | ... Mux18| ... | ... Mux19| ... | ... Mux20| ... | ... Mux21| Input Pin ( 86)| RST -Mux22| Mcel 6 5 ( 253)| SM_AMIGA_2_ +Mux22| Mcel 6 5 ( 253)| inst_VPA_SYNC Mux23| ... | ... -Mux24| ... | ... -Mux25| Mcel 5 0 ( 221)| inst_VPA_SYNC +Mux24| Mcel 6 1 ( 247)| inst_CLK_OUT_PRE +Mux25| Mcel 3 9 ( 187)| inst_CLK_000_D1 Mux26| ... | ... Mux27| Mcel 1 4 ( 131)| RN_IPL_030_2_ -Mux28| Mcel 1 5 ( 133)| SM_AMIGA_3_ -Mux29| Input Pin ( 61)| CLK_OSZI +Mux28| Mcel 1 13 ( 145)| CLK_CNT_N_0_ +Mux29| ... | ... Mux30| ... | ... -Mux31| ... | ... +Mux31| Mcel 1 5 ( 133)| SM_AMIGA_1_ Mux32| ... | ... --------------------------------------------------------------------------- =========================================================================== @@ -915,19 +873,19 @@ Mux32| ... | ... | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| DTACK| IO| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig - 1| VMA| IO| | S | 2 | 4 to [ 1]| 1 XOR free - 2| cpu_est_2_|NOD| | A | 3 :+: 1| 2 to [ 2]| 1 XOR to [ 2] - 3| | ? | | S | | 4 to [ 2]| 1 XOR free + 1| VMA| IO| | S | 2 :+: 1| 4 to [ 1]| 1 XOR to [ 1] + 2| cpu_est_2_|NOD| | S | 3 :+: 1| 4 to [ 2]| 1 XOR to [ 2] + 3|inst_CLK_000_D2|NOD| | S | 1 | 4 free | 1 XOR to [ 3] for 1 PT sig 4|AMIGA_BUS_ENABLE| IO| | A | 3 | 2 to [ 4]| 1 XOR to [ 4] as logic PT 5| AS_000| IO| | S | 2 | 4 to [ 5]| 1 XOR free - 6| cpu_est_0_|NOD| | A | 3 | 2 to [ 6]| 1 XOR to [ 6] as logic PT + 6| cpu_est_0_|NOD| | S | 3 | 4 to [ 6]| 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free 8| LDS_000| IO| | S | 8 | 4 to [ 8]| 1 XOR to [ 8] as logic PT - 9| cpu_est_1_|NOD| | A | 4 | 2 to [ 8]| 1 XOR to [ 8] as logic PT + 9|inst_CLK_000_D1|NOD| | S | 1 | 4 to [ 8]| 1 XOR to [ 9] for 1 PT sig 10| SM_AMIGA_4_|NOD| | S | 2 | 4 to [10]| 1 XOR free -11| | ? | | S | | 4 to [ 9]| 1 XOR free +11| | ? | | S | | 4 free | 1 XOR free 12| UDS_000| IO| | S | 5 | 4 to [12]| 1 XOR to [12] as logic PT -13| BG_000| IO| | S | 2 | 4 to [13]| 1 XOR free +13| BG_000|OUT| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig 14| SM_AMIGA_5_|NOD| | S | 2 | 4 to [14]| 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- @@ -942,20 +900,20 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ 0| DTACK| IO| | S | 1 |=> can support up to [ 5] logic PT(s) - 1| VMA| IO| | S | 2 |=> can support up to [ 9] logic PT(s) - 2| cpu_est_2_|NOD| | A | 3 :+: 1|=> can support up to [ 7] logic PT(s) - 3| | ? | | S | |=> can support up to [ 1] logic PT(s) - 4|AMIGA_BUS_ENABLE| IO| | A | 3 |=> can support up to [ 3] logic PT(s) + 1| VMA| IO| | S | 2 :+: 1|=> can support up to [ 12] logic PT(s) + 2| cpu_est_2_|NOD| | S | 3 :+: 1|=> can support up to [ 8] logic PT(s) + 3|inst_CLK_000_D2|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) + 4|AMIGA_BUS_ENABLE| IO| | A | 3 |=> can support up to [ 7] logic PT(s) 5| AS_000| IO| | S | 2 |=> can support up to [ 10] logic PT(s) - 6| cpu_est_0_|NOD| | A | 3 |=> can support up to [ 8] logic PT(s) + 6| cpu_est_0_|NOD| | S | 3 |=> can support up to [ 10] logic PT(s) 7| | ? | | S | |=> can support up to [ 5] logic PT(s) - 8| LDS_000| IO| | S | 8 |=> can support up to [ 13] logic PT(s) - 9| cpu_est_1_|NOD| | A | 4 |=> can support up to [ 5] logic PT(s) -10| SM_AMIGA_4_|NOD| | S | 2 |=> can support up to [ 5] logic PT(s) -11| | ? | | S | |=> can support up to [ 1] logic PT(s) -12| UDS_000| IO| | S | 5 |=> can support up to [ 5] logic PT(s) -13| BG_000| IO| | S | 2 |=> can support up to [ 10] logic PT(s) -14| SM_AMIGA_5_|NOD| | S | 2 |=> can support up to [ 10] logic PT(s) + 8| LDS_000| IO| | S | 8 |=> can support up to [ 14] logic PT(s) + 9|inst_CLK_000_D1|NOD| | S | 1 |=> can support up to [ 6] logic PT(s) +10| SM_AMIGA_4_|NOD| | S | 2 |=> can support up to [ 10] logic PT(s) +11| | ? | | S | |=> can support up to [ 9] logic PT(s) +12| UDS_000| IO| | S | 5 |=> can support up to [ 14] logic PT(s) +13| BG_000|OUT| | S | 1 |=> can support up to [ 10] logic PT(s) +14| SM_AMIGA_5_|NOD| | S | 2 |=> can support up to [ 14] logic PT(s) 15| | ? | | S | |=> can support up to [ 5] logic PT(s) --------------------------------------------------------------------------- =========================================================================== @@ -969,17 +927,17 @@ _|_________________|__|_____|____________________|________________________ 0| DTACK| IO| | => |( 5) 6 7 0 |( 30) 29 28 35 1| VMA| IO| | => | 5 6 7 ( 0)| 30 29 28 ( 35) 2| cpu_est_2_|NOD| | => | 6 7 0 1 | 29 28 35 34 - 3| | | | => | 6 7 0 1 | 29 28 35 34 + 3|inst_CLK_000_D2|NOD| | => | 6 7 0 1 | 29 28 35 34 4|AMIGA_BUS_ENABLE| IO| | => | 7 0 ( 1) 2 | 28 35 ( 34) 33 5| AS_000| IO| | => | 7 0 1 ( 2)| 28 35 34 ( 33) 6| cpu_est_0_|NOD| | => | 0 1 2 3 | 35 34 33 32 7| | | | => | 0 1 2 3 | 35 34 33 32 8| LDS_000| IO| | => | 1 2 3 ( 4)| 34 33 32 ( 31) - 9| cpu_est_1_|NOD| | => | 1 2 3 4 | 34 33 32 31 + 9|inst_CLK_000_D1|NOD| | => | 1 2 3 4 | 34 33 32 31 10| SM_AMIGA_4_|NOD| | => | 2 3 4 5 | 33 32 31 30 11| | | | => | 2 3 4 5 | 33 32 31 30 12| UDS_000| IO| | => |( 3) 4 5 6 |( 32) 31 30 29 -13| BG_000| IO| | => | 3 4 5 ( 6)| 32 31 30 ( 29) +13| BG_000|OUT| | => | 3 4 5 ( 6)| 32 31 30 ( 29) 14| SM_AMIGA_5_|NOD| | => | 4 5 6 7 | 31 30 29 28 15| | | | => | 4 5 6 7 | 31 30 29 28 --------------------------------------------------------------------------- @@ -998,7 +956,7 @@ _|_________________|__|___|_____|___________________________________________ 3| UDS_000| IO|*| 32| => | 6 7 8 9 10 11 (12) 13 4| LDS_000| IO|*| 31| => | ( 8) 9 10 11 12 13 14 15 5| DTACK| IO|*| 30| => | 10 11 12 13 14 15 ( 0) 1 - 6| BG_000| IO|*| 29| => | 12 (13) 14 15 0 1 2 3 + 6| BG_000|OUT|*| 29| => | 12 (13) 14 15 0 1 2 3 7| BGACK_000|INP|*| 28| => | 14 15 0 1 2 3 4 5 --------------------------------------------------------------------------- =========================================================================== @@ -1021,8 +979,7 @@ _|_________________|__|___|_____|__________________________________________ 4| LDS_000| IO|*| 31| => | Input macrocell [ -] | | | | | | IO paired w/ node [ RN_LDS_000] 5| DTACK| IO|*| 30| => | Input macrocell [ -] - 6| BG_000| IO|*| 29| => | Input macrocell [ -] - | | | | | | IO paired w/ node [ RN_BG_000] + 6| BG_000|OUT|*| 29| => | Input macrocell [ -] 7| BGACK_000|INP|*| 28| => | Input macrocell [ -] --------------------------------------------------------------------------- =========================================================================== @@ -1042,7 +999,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 1 [IOpin 1 | 34| IO AMIGA_BUS_ENABLE|*| ] paired w/[RN_AMIGA_BUS_ENABLE] [RegIn 1 |177| -| | ] [MCell 2 |176|NOD cpu_est_2_| |*] - [MCell 3 |178| -| | ] + [MCell 3 |178|NOD inst_CLK_000_D2| |*] 2 [IOpin 2 | 33| IO AS_000|*| ] paired w/[ RN_AS_000] [RegIn 2 |180| -| | ] @@ -1057,17 +1014,17 @@ IMX No. | +---- Block IO Pin or Macrocell Number 4 [IOpin 4 | 31| IO LDS_000|*| ] paired w/[ RN_LDS_000] [RegIn 4 |186| -| | ] [MCell 8 |185|NOD RN_LDS_000| |*] paired w/[ LDS_000] - [MCell 9 |187|NOD cpu_est_1_| |*] + [MCell 9 |187|NOD inst_CLK_000_D1| |*] 5 [IOpin 5 | 30| IO DTACK|*|*] [RegIn 5 |189| -| | ] [MCell 10 |188|NOD SM_AMIGA_4_| |*] [MCell 11 |190| -| | ] - 6 [IOpin 6 | 29| IO BG_000|*| ] paired w/[ RN_BG_000] + 6 [IOpin 6 | 29|OUT BG_000|*| ] [RegIn 6 |192| -| | ] [MCell 12 |191|NOD RN_UDS_000| |*] paired w/[ UDS_000] - [MCell 13 |193|NOD RN_BG_000| |*] paired w/[ BG_000] + [MCell 13 |193|OUT BG_000| | ] 7 [IOpin 7 | 28|INP BGACK_000|*|*] [RegIn 7 |195| -| | ] @@ -1080,35 +1037,35 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| IOPin 6 5 ( 70)| SIZE_0_ -Mux01| Mcel 3 13 ( 193)| RN_BG_000 -Mux02| Mcel 6 4 ( 251)| RN_E +Mux00| IOPin 6 4 ( 69)| A_0_ +Mux01| ... | ... +Mux02| Mcel 3 1 ( 175)| RN_VMA Mux03| Mcel 3 2 ( 176)| cpu_est_2_ Mux04| Mcel 3 6 ( 182)| cpu_est_0_ Mux05| Mcel 3 12 ( 191)| RN_UDS_000 Mux06| IOPin 7 6 ( 79)| SIZE_1_ -Mux07| Mcel 6 12 ( 263)| inst_CLK_000_D1 +Mux07| Mcel 3 5 ( 181)| RN_AS_000 Mux08| IOPin 6 6 ( 71)| RW Mux09| IOPin 7 3 ( 82)| AS_030 -Mux10| Mcel 3 4 ( 179)| RN_AMIGA_BUS_ENABLE -Mux11| Mcel 3 5 ( 181)| RN_AS_000 +Mux10| Mcel 6 8 ( 257)| inst_CLK_000_D0 +Mux11| Mcel 6 4 ( 251)| RN_E Mux12| IOPin 0 7 ( 98)| DS_030 Mux13| Mcel 7 5 ( 277)| SM_AMIGA_6_ -Mux14| IOPin 2 6 ( 21)| BG_030 +Mux14| IOPin 6 5 ( 70)| SIZE_0_ Mux15| Input Pin ( 14)| nEXP_SPACE Mux16| Mcel 3 8 ( 185)| RN_LDS_000 Mux17| Mcel 3 14 ( 194)| SM_AMIGA_5_ -Mux18| IOPin 6 4 ( 69)| A_0_ +Mux18| ... | ... Mux19| Mcel 7 1 ( 271)| SM_AMIGA_7_ -Mux20| Input Pin ( 64)| CLK_030 -Mux21| Input Pin ( 86)| RST -Mux22| ... | ... -Mux23| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux24| Mcel 6 1 ( 247)| inst_VPA_D -Mux25| Mcel 3 9 ( 187)| cpu_est_1_ +Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux21| Mcel 3 4 ( 179)| RN_AMIGA_BUS_ENABLE +Mux22| IOPin 2 6 ( 21)| BG_030 +Mux23| Mcel 6 12 ( 263)| cpu_est_1_ +Mux24| Input Pin ( 86)| RST +Mux25| Mcel 3 9 ( 187)| inst_CLK_000_D1 Mux26| ... | ... -Mux27| Mcel 3 1 ( 175)| RN_VMA -Mux28| Mcel 6 8 ( 257)| inst_CLK_000_D0 +Mux27| ... | ... +Mux28| Mcel 7 2 ( 272)| inst_VPA_D Mux29| Input Pin ( 61)| CLK_OSZI Mux30| Mcel 3 10 ( 188)| SM_AMIGA_4_ Mux31| ... | ... @@ -1318,85 +1275,6 @@ Mux30| ... | ... Mux31| ... | ... Mux32| ... | ... --------------------------------------------------------------------------- -=========================================================================== - < Block [ 5] > Macrocell (MCell) Cluster Assignments -=========================================================================== - + Macrocell Number - | PT Requirements------ Logic XOR+ +--- Macrocell PT Cluster Size - | Sync/Async-------+ | | | Cluster to Mcell Assignment - | Node Fixed(*)----+ | | | | | +- XOR PT Size - | Sig Type-+ | | | | | | | XOR to Mcell Assignment - | Signal Name | | | | | | | | | -_|_________________|__|__|___|_____|__|______|___|__________|______________ - 0| inst_VPA_SYNC|NOD| | S | 2 | 4 to [ 0]| 1 XOR free - 1| | ? | | S | | 4 free | 1 XOR free - 2| | ? | | S | | 4 free | 1 XOR free - 3| | ? | | S | | 4 free | 1 XOR free - 4| | ? | | S | | 4 free | 1 XOR free - 5| | ? | | S | | 4 free | 1 XOR free - 6| | ? | | S | | 4 free | 1 XOR free - 7| | ? | | S | | 4 free | 1 XOR free - 8| | ? | | S | | 4 free | 1 XOR free - 9| | ? | | S | | 4 free | 1 XOR free -10| | ? | | S | | 4 free | 1 XOR free -11| | ? | | S | | 4 free | 1 XOR free -12| | ? | | S | | 4 free | 1 XOR free -13| | ? | | S | | 4 free | 1 XOR free -14| | ? | | S | | 4 free | 1 XOR free -15| | ? | | S | | 4 free | 1 XOR free ---------------------------------------------------------------------------- -=========================================================================== - < Block [ 5] > Maximum PT Capacity -=========================================================================== - + Macrocell Number - | PT Requirements------ Logic XOR+ - | Sync/Async-------+ | | - | Node Fixed(*)----+ | | | - | Sig Type-+ | | | | - | Signal Name | | | | | Maximum PT Capacity -_|_________________|__|__|___|_____|_______________________________________ - 0| inst_VPA_SYNC|NOD| | S | 2 |=> can support up to [ 15] logic PT(s) - 1| | ? | | S | |=> can support up to [ 15] logic PT(s) - 2| | ? | | S | |=> can support up to [ 20] logic PT(s) - 3| | ? | | S | |=> can support up to [ 20] logic PT(s) - 4| | ? | | S | |=> can support up to [ 20] logic PT(s) - 5| | ? | | S | |=> can support up to [ 20] logic PT(s) - 6| | ? | | S | |=> can support up to [ 20] logic PT(s) - 7| | ? | | S | |=> can support up to [ 20] logic PT(s) - 8| | ? | | S | |=> can support up to [ 20] logic PT(s) - 9| | ? | | S | |=> can support up to [ 20] logic PT(s) -10| | ? | | S | |=> can support up to [ 20] logic PT(s) -11| | ? | | S | |=> can support up to [ 20] logic PT(s) -12| | ? | | S | |=> can support up to [ 20] logic PT(s) -13| | ? | | S | |=> can support up to [ 20] logic PT(s) -14| | ? | | S | |=> can support up to [ 15] logic PT(s) -15| | ? | | S | |=> can support up to [ 10] logic PT(s) ---------------------------------------------------------------------------- -=========================================================================== - < Block [ 5] > Node-Pin Assignments -=========================================================================== - + Macrocell Number - | Node Fixed(*)------+ - | Sig Type---+ | to | Block [ 5] IO Pin | Device Pin - | Signal Name | | pin | Numbers | Numbers -_|_________________|__|_____|____________________|________________________ - 0| inst_VPA_SYNC|NOD| | => | 5 6 7 0 | 55 54 53 60 - 1| | | | => | 5 6 7 0 | 55 54 53 60 - 2| | | | => | 6 7 0 1 | 54 53 60 59 - 3| | | | => | 6 7 0 1 | 54 53 60 59 - 4| | | | => | 7 0 1 2 | 53 60 59 58 - 5| | | | => | 7 0 1 2 | 53 60 59 58 - 6| | | | => | 0 1 2 3 | 60 59 58 57 - 7| | | | => | 0 1 2 3 | 60 59 58 57 - 8| | | | => | 1 2 3 4 | 59 58 57 56 - 9| | | | => | 1 2 3 4 | 59 58 57 56 -10| | | | => | 2 3 4 5 | 58 57 56 55 -11| | | | => | 2 3 4 5 | 58 57 56 55 -12| | | | => | 3 4 5 6 | 57 56 55 54 -13| | | | => | 3 4 5 6 | 57 56 55 54 -14| | | | => | 4 5 6 7 | 56 55 54 53 -15| | | | => | 4 5 6 7 | 56 55 54 53 ---------------------------------------------------------------------------- =========================================================================== < Block [ 5] > IO-to-Node Pin Mapping =========================================================================== @@ -1444,7 +1322,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number ---|-------|----|---|---|----------|------|-|------------------------------ 0 [IOpin 0 | 60| -| | ] [RegIn 0 |222| -| | ] - [MCell 0 |221|NOD inst_VPA_SYNC| |*] + [MCell 0 |221| -| | ] [MCell 1 |223| -| | ] 1 [IOpin 1 | 59|INP A_17_|*|*] @@ -1482,46 +1360,6 @@ IMX No. | +---- Block IO Pin or Macrocell Number [MCell 14 |242| -| | ] [MCell 15 |244| -| | ] --------------------------------------------------------------------------- -=========================================================================== - < Block [ 5] > Logic Array Fan-in -=========================================================================== - +- Central Switch Matrix No. - | Src (ABEL Node/Pin#) Signal ---|--|--------------------|--------------------------------------------------- -Mux00| Input Pin ( 86)| RST -Mux01| ... | ... -Mux02| Mcel 3 1 ( 175)| RN_VMA -Mux03| Mcel 3 2 ( 176)| cpu_est_2_ -Mux04| Input Pin ( 61)| CLK_OSZI -Mux05| Mcel 5 0 ( 221)| inst_VPA_SYNC -Mux06| ... | ... -Mux07| Mcel 3 9 ( 187)| cpu_est_1_ -Mux08| ... | ... -Mux09| IOPin 7 3 ( 82)| AS_030 -Mux10| Mcel 6 8 ( 257)| inst_CLK_000_D0 -Mux11| Mcel 6 4 ( 251)| RN_E -Mux12| ... | ... -Mux13| ... | ... -Mux14| ... | ... -Mux15| ... | ... -Mux16| Mcel 3 6 ( 182)| cpu_est_0_ -Mux17| ... | ... -Mux18| ... | ... -Mux19| ... | ... -Mux20| ... | ... -Mux21| ... | ... -Mux22| ... | ... -Mux23| ... | ... -Mux24| Mcel 6 1 ( 247)| inst_VPA_D -Mux25| ... | ... -Mux26| ... | ... -Mux27| ... | ... -Mux28| Mcel 1 5 ( 133)| SM_AMIGA_3_ -Mux29| ... | ... -Mux30| ... | ... -Mux31| ... | ... -Mux32| ... | ... ---------------------------------------------------------------------------- =========================================================================== < Block [ 6] > Macrocell (MCell) Cluster Assignments =========================================================================== @@ -1533,19 +1371,19 @@ Mux32| ... | ... | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| CLK_DIV_OUT|OUT| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig - 1| inst_VPA_D|NOD| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig - 2| CLK_CNT_0_|NOD| | S | 2 | 4 to [ 2]| 1 XOR free + 1|inst_CLK_OUT_PRE|NOD| | S | 4 | 4 to [ 1]| 1 XOR free + 2| CLK_CNT_P_0_|NOD| | S | 2 | 4 to [ 2]| 1 XOR free 3| | ? | | S | | 4 free | 1 XOR free - 4| E| IO| | S | 3 | 4 to [ 4]| 1 XOR free - 5| SM_AMIGA_2_|NOD| | A | 3 | 2 to [ 5]| 1 XOR to [ 5] as logic PT - 6|inst_CLK_000_D2|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig + 4| E| IO| | S | 3 :+: 1| 4 to [ 4]| 1 XOR to [ 4] + 5| inst_VPA_SYNC|NOD| | S | 2 | 4 to [ 5]| 1 XOR free + 6| CLK_CNT_P_1_|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig 7| | ? | | S | | 4 free | 1 XOR free 8|inst_CLK_000_D0|NOD| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig - 9|inst_CLK_OUT_PRE|NOD| | S | 3 :+: 1| 4 to [ 9]| 1 XOR to [ 9] + 9|inst_DTACK_SYNC|NOD| | S | 2 | 4 to [ 9]| 1 XOR free 10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free -12|inst_CLK_000_D1|NOD| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig -13| CLK_CNT_1_|NOD| | S | 2 | 4 to [13]| 1 XOR free +12| cpu_est_1_|NOD| | S | 4 | 4 to [12]| 1 XOR free +13| CLK_CNT_N_1_|NOD| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig 14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- @@ -1559,21 +1397,21 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| CLK_DIV_OUT|OUT| | S | 1 |=> can support up to [ 9] logic PT(s) - 1| inst_VPA_D|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) - 2| CLK_CNT_0_|NOD| | S | 2 |=> can support up to [ 14] logic PT(s) + 0| CLK_DIV_OUT|OUT| | S | 1 |=> can support up to [ 5] logic PT(s) + 1|inst_CLK_OUT_PRE|NOD| | S | 4 |=> can support up to [ 14] logic PT(s) + 2| CLK_CNT_P_0_|NOD| | S | 2 |=> can support up to [ 10] logic PT(s) 3| | ? | | S | |=> can support up to [ 5] logic PT(s) - 4| E| IO| | S | 3 |=> can support up to [ 14] logic PT(s) - 5| SM_AMIGA_2_|NOD| | A | 3 |=> can support up to [ 12] logic PT(s) - 6|inst_CLK_000_D2|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) + 4| E| IO| | S | 3 :+: 1|=> can support up to [ 13] logic PT(s) + 5| inst_VPA_SYNC|NOD| | S | 2 |=> can support up to [ 14] logic PT(s) + 6| CLK_CNT_P_1_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) 7| | ? | | S | |=> can support up to [ 13] logic PT(s) 8|inst_CLK_000_D0|NOD| | S | 1 |=> can support up to [ 15] logic PT(s) - 9|inst_CLK_OUT_PRE|NOD| | S | 3 :+: 1|=> can support up to [ 18] logic PT(s) -10| | ? | | S | |=> can support up to [ 14] logic PT(s) + 9|inst_DTACK_SYNC|NOD| | S | 2 |=> can support up to [ 19] logic PT(s) +10| | ? | | S | |=> can support up to [ 10] logic PT(s) 11| | ? | | S | |=> can support up to [ 14] logic PT(s) -12|inst_CLK_000_D1|NOD| | S | 1 |=> can support up to [ 15] logic PT(s) -13| CLK_CNT_1_|NOD| | S | 2 |=> can support up to [ 19] logic PT(s) -14| | ? | | S | |=> can support up to [ 10] logic PT(s) +12| cpu_est_1_|NOD| | S | 4 |=> can support up to [ 19] logic PT(s) +13| CLK_CNT_N_1_|NOD| | S | 1 |=> can support up to [ 15] logic PT(s) +14| | ? | | S | |=> can support up to [ 14] logic PT(s) 15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- =========================================================================== @@ -1585,19 +1423,19 @@ _|_________________|__|__|___|_____|_______________________________________ | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ 0| CLK_DIV_OUT|OUT| | => | 5 6 7 ( 0)| 70 71 72 ( 65) - 1| inst_VPA_D|NOD| | => | 5 6 7 0 | 70 71 72 65 - 2| CLK_CNT_0_|NOD| | => | 6 7 0 1 | 71 72 65 66 + 1|inst_CLK_OUT_PRE|NOD| | => | 5 6 7 0 | 70 71 72 65 + 2| CLK_CNT_P_0_|NOD| | => | 6 7 0 1 | 71 72 65 66 3| | | | => | 6 7 0 1 | 71 72 65 66 4| E| IO| | => | 7 0 ( 1) 2 | 72 65 ( 66) 67 - 5| SM_AMIGA_2_|NOD| | => | 7 0 1 2 | 72 65 66 67 - 6|inst_CLK_000_D2|NOD| | => | 0 1 2 3 | 65 66 67 68 + 5| inst_VPA_SYNC|NOD| | => | 7 0 1 2 | 72 65 66 67 + 6| CLK_CNT_P_1_|NOD| | => | 0 1 2 3 | 65 66 67 68 7| | | | => | 0 1 2 3 | 65 66 67 68 8|inst_CLK_000_D0|NOD| | => | 1 2 3 4 | 66 67 68 69 - 9|inst_CLK_OUT_PRE|NOD| | => | 1 2 3 4 | 66 67 68 69 + 9|inst_DTACK_SYNC|NOD| | => | 1 2 3 4 | 66 67 68 69 10| | | | => | 2 3 4 5 | 67 68 69 70 11| | | | => | 2 3 4 5 | 67 68 69 70 -12|inst_CLK_000_D1|NOD| | => | 3 4 5 6 | 68 69 70 71 -13| CLK_CNT_1_|NOD| | => | 3 4 5 6 | 68 69 70 71 +12| cpu_est_1_|NOD| | => | 3 4 5 6 | 68 69 70 71 +13| CLK_CNT_N_1_|NOD| | => | 3 4 5 6 | 68 69 70 71 14| | | | => | 4 5 6 7 | 69 70 71 72 15| | | | => | 4 5 6 7 | 69 70 71 72 --------------------------------------------------------------------------- @@ -1650,27 +1488,27 @@ IMX No. | +---- Block IO Pin or Macrocell Number 0 [IOpin 0 | 65|OUT CLK_DIV_OUT|*| ] [RegIn 0 |246| -| | ] [MCell 0 |245|OUT CLK_DIV_OUT| | ] - [MCell 1 |247|NOD inst_VPA_D| |*] + [MCell 1 |247|NOD inst_CLK_OUT_PRE| |*] 1 [IOpin 1 | 66| IO E|*| ] paired w/[ RN_E] [RegIn 1 |249| -| | ] - [MCell 2 |248|NOD CLK_CNT_0_| |*] + [MCell 2 |248|NOD CLK_CNT_P_0_| |*] [MCell 3 |250| -| | ] 2 [IOpin 2 | 67|INP IPL_0_|*|*] [RegIn 2 |252| -| | ] [MCell 4 |251|NOD RN_E| |*] paired w/[ E] - [MCell 5 |253|NOD SM_AMIGA_2_| |*] + [MCell 5 |253|NOD inst_VPA_SYNC| |*] 3 [IOpin 3 | 68|INP IPL_2_|*|*] [RegIn 3 |255| -| | ] - [MCell 6 |254|NOD inst_CLK_000_D2| |*] + [MCell 6 |254|NOD CLK_CNT_P_1_| |*] [MCell 7 |256| -| | ] 4 [IOpin 4 | 69|INP A_0_|*|*] [RegIn 4 |258| -| | ] [MCell 8 |257|NOD inst_CLK_000_D0| |*] - [MCell 9 |259|NOD inst_CLK_OUT_PRE| |*] + [MCell 9 |259|NOD inst_DTACK_SYNC| |*] 5 [IOpin 5 | 70|INP SIZE_0_|*|*] [RegIn 5 |261| -| | ] @@ -1679,8 +1517,8 @@ IMX No. | +---- Block IO Pin or Macrocell Number 6 [IOpin 6 | 71|INP RW|*|*] [RegIn 6 |264| -| | ] - [MCell 12 |263|NOD inst_CLK_000_D1| |*] - [MCell 13 |265|NOD CLK_CNT_1_| |*] + [MCell 12 |263|NOD cpu_est_1_| |*] + [MCell 13 |265|NOD CLK_CNT_N_1_| |*] 7 [IOpin 7 | 72| -| | ] [RegIn 7 |267| -| | ] @@ -1695,36 +1533,36 @@ IMX No. | +---- Block IO Pin or Macrocell Number --|--|--------------------|--------------------------------------------------- Mux00| Input Pin ( 86)| RST Mux01| ... | ... -Mux02| Mcel 7 14 ( 290)| CLK_REF_1_ +Mux02| Mcel 3 1 ( 175)| RN_VMA Mux03| Input Pin ( 11)| CLK_000 -Mux04| Input Pin ( 61)| CLK_OSZI -Mux05| Mcel 5 0 ( 221)| inst_VPA_SYNC -Mux06| ... | ... -Mux07| Mcel 3 9 ( 187)| cpu_est_1_ +Mux04| Mcel 6 2 ( 248)| CLK_CNT_P_0_ +Mux05| Mcel 6 6 ( 254)| CLK_CNT_P_1_ +Mux06| Mcel 1 9 ( 139)| SM_AMIGA_3_ +Mux07| Mcel 6 12 ( 263)| cpu_est_1_ Mux08| ... | ... -Mux09| Mcel 6 13 ( 265)| CLK_CNT_1_ -Mux10| Input Pin ( 36)| VPA +Mux09| IOPin 7 3 ( 82)| AS_030 +Mux10| Mcel 6 9 ( 259)| inst_DTACK_SYNC Mux11| Mcel 6 4 ( 251)| RN_E -Mux12| Mcel 6 9 ( 259)| inst_CLK_OUT_PRE +Mux12| Mcel 6 13 ( 265)| CLK_CNT_N_1_ Mux13| Mcel 6 8 ( 257)| inst_CLK_000_D0 -Mux14| Mcel 6 12 ( 263)| inst_CLK_000_D1 -Mux15| Mcel 0 0 ( 101)| inst_DTACK_SYNC +Mux14| Mcel 7 2 ( 272)| inst_VPA_D +Mux15| ... | ... Mux16| Mcel 3 6 ( 182)| cpu_est_0_ Mux17| ... | ... Mux18| ... | ... Mux19| ... | ... Mux20| ... | ... -Mux21| ... | ... -Mux22| Mcel 6 5 ( 253)| SM_AMIGA_2_ -Mux23| Mcel 6 2 ( 248)| CLK_CNT_0_ -Mux24| ... | ... -Mux25| ... | ... +Mux21| Mcel 1 13 ( 145)| CLK_CNT_N_0_ +Mux22| Mcel 6 5 ( 253)| inst_VPA_SYNC +Mux23| IOPin 3 5 ( 30)| DTACK +Mux24| Mcel 6 1 ( 247)| inst_CLK_OUT_PRE +Mux25| Mcel 3 9 ( 187)| inst_CLK_000_D1 Mux26| ... | ... Mux27| ... | ... Mux28| Mcel 3 2 ( 176)| cpu_est_2_ Mux29| ... | ... Mux30| ... | ... -Mux31| Mcel 1 5 ( 133)| SM_AMIGA_3_ +Mux31| ... | ... Mux32| ... | ... --------------------------------------------------------------------------- =========================================================================== @@ -1739,19 +1577,19 @@ Mux32| ... | ... _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| FPU_CS| IO| | S | 2 | 4 to [ 0]| 1 XOR free 1| SM_AMIGA_7_|NOD| | S | 5 | 4 to [ 1]| 1 XOR to [ 1] as logic PT - 2|inst_AS_030_000_SYNC|NOD| | S | 7 | 4 to [ 2]| 1 XOR to [ 2] as logic PT - 3| | ? | | S | | 4 to [ 2]| 1 XOR free + 2| inst_VPA_D|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig + 3| | ? | | S | | 4 free | 1 XOR free 4| BGACK_030| IO| | S | 2 | 4 to [ 4]| 1 XOR free 5| SM_AMIGA_6_|NOD| | S | 2 | 4 to [ 5]| 1 XOR free - 6| SM_AMIGA_0_|NOD| | S | 4 | 4 to [ 6]| 1 XOR free + 6|inst_AS_030_000_SYNC|NOD| | S | 7 | 4 to [ 6]| 1 XOR to [ 6] as logic PT 7| | ? | | S | | 4 free | 1 XOR free - 8| DSACK_1_| IO| | S | 2 | 4 free | 1 XOR free - 9|inst_CLK_000_D4|NOD| | A | 1 | 2 to [ 8]| 1 XOR to [ 9] for 1 PT sig -10|inst_CLK_000_D3|NOD| | A | 1 | 2 free | 1 XOR to [10] for 1 PT sig + 8| DSACK_1_| IO| | S | 2 | 4 to [ 6]| 1 XOR free + 9|inst_CLK_000_D4|NOD| | S | 1 | 4 to [ 8]| 1 XOR to [ 9] for 1 PT sig +10| SM_AMIGA_0_|NOD| | S | 4 | 4 to [10]| 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free 12| DSACK_0_|OUT| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig -13|inst_CLK_000_D5|NOD| | A | 1 | 2 free | 1 XOR to [13] for 1 PT sig -14| CLK_REF_1_|NOD| | A | 1 | 2 free | 1 XOR to [14] for 1 PT sig +13|inst_CLK_000_D5|NOD| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig +14|inst_CLK_000_D3|NOD| | S | 1 | 4 free | 1 XOR to [14] for 1 PT sig 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== @@ -1764,22 +1602,22 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| FPU_CS| IO| | S | 2 |=> can support up to [ 5] logic PT(s) - 1| SM_AMIGA_7_|NOD| | S | 5 |=> can support up to [ 5] logic PT(s) - 2|inst_AS_030_000_SYNC|NOD| | S | 7 |=> can support up to [ 10] logic PT(s) - 3| | ? | | S | |=> can support up to [ 1] logic PT(s) - 4| BGACK_030| IO| | S | 2 |=> can support up to [ 5] logic PT(s) + 0| FPU_CS| IO| | S | 2 |=> can support up to [ 9] logic PT(s) + 1| SM_AMIGA_7_|NOD| | S | 5 |=> can support up to [ 14] logic PT(s) + 2| inst_VPA_D|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) + 3| | ? | | S | |=> can support up to [ 9] logic PT(s) + 4| BGACK_030| IO| | S | 2 |=> can support up to [ 10] logic PT(s) 5| SM_AMIGA_6_|NOD| | S | 2 |=> can support up to [ 10] logic PT(s) - 6| SM_AMIGA_0_|NOD| | S | 4 |=> can support up to [ 15] logic PT(s) - 7| | ? | | S | |=> can support up to [ 10] logic PT(s) - 8| DSACK_1_| IO| | S | 2 |=> can support up to [ 14] logic PT(s) - 9|inst_CLK_000_D4|NOD| | A | 1 |=> can support up to [ 13] logic PT(s) -10|inst_CLK_000_D3|NOD| | A | 1 |=> can support up to [ 12] logic PT(s) + 6|inst_AS_030_000_SYNC|NOD| | S | 7 |=> can support up to [ 15] logic PT(s) + 7| | ? | | S | |=> can support up to [ 5] logic PT(s) + 8| DSACK_1_| IO| | S | 2 |=> can support up to [ 9] logic PT(s) + 9|inst_CLK_000_D4|NOD| | S | 1 |=> can support up to [ 6] logic PT(s) +10| SM_AMIGA_0_|NOD| | S | 4 |=> can support up to [ 14] logic PT(s) 11| | ? | | S | |=> can support up to [ 13] logic PT(s) -12| DSACK_0_|OUT| | S | 1 |=> can support up to [ 14] logic PT(s) -13|inst_CLK_000_D5|NOD| | A | 1 |=> can support up to [ 14] logic PT(s) -14| CLK_REF_1_|NOD| | A | 1 |=> can support up to [ 10] logic PT(s) -15| | ? | | S | |=> can support up to [ 7] logic PT(s) +12| DSACK_0_|OUT| | S | 1 |=> can support up to [ 18] logic PT(s) +13|inst_CLK_000_D5|NOD| | S | 1 |=> can support up to [ 18] logic PT(s) +14|inst_CLK_000_D3|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) +15| | ? | | S | |=> can support up to [ 9] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 7] > Node-Pin Assignments @@ -1791,19 +1629,19 @@ _|_________________|__|__|___|_____|_______________________________________ _|_________________|__|_____|____________________|________________________ 0| FPU_CS| IO| | => | 5 6 ( 7) 0 | 80 79 ( 78) 85 1| SM_AMIGA_7_|NOD| | => | 5 6 7 0 | 80 79 78 85 - 2|inst_AS_030_000_SYNC|NOD| | => | 6 7 0 1 | 79 78 85 84 + 2| inst_VPA_D|NOD| | => | 6 7 0 1 | 79 78 85 84 3| | | | => | 6 7 0 1 | 79 78 85 84 4| BGACK_030| IO| | => | 7 0 1 ( 2)| 78 85 84 ( 83) 5| SM_AMIGA_6_|NOD| | => | 7 0 1 2 | 78 85 84 83 - 6| SM_AMIGA_0_|NOD| | => | 0 1 2 3 | 85 84 83 82 + 6|inst_AS_030_000_SYNC|NOD| | => | 0 1 2 3 | 85 84 83 82 7| | | | => | 0 1 2 3 | 85 84 83 82 8| DSACK_1_| IO| | => | 1 2 3 ( 4)| 84 83 82 ( 81) 9|inst_CLK_000_D4|NOD| | => | 1 2 3 4 | 84 83 82 81 -10|inst_CLK_000_D3|NOD| | => | 2 3 4 5 | 83 82 81 80 +10| SM_AMIGA_0_|NOD| | => | 2 3 4 5 | 83 82 81 80 11| | | | => | 2 3 4 5 | 83 82 81 80 12| DSACK_0_|OUT| | => | 3 4 ( 5) 6 | 82 81 ( 80) 79 13|inst_CLK_000_D5|NOD| | => | 3 4 5 6 | 82 81 80 79 -14| CLK_REF_1_|NOD| | => | 4 5 6 7 | 81 80 79 78 +14|inst_CLK_000_D3|NOD| | => | 4 5 6 7 | 81 80 79 78 15| | | | => | 4 5 6 7 | 81 80 79 78 --------------------------------------------------------------------------- =========================================================================== @@ -1861,7 +1699,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 1 [IOpin 1 | 84|INP A_23_|*|*] [RegIn 1 |273| -| | ] - [MCell 2 |272|NOD inst_AS_030_000_SYNC| |*] + [MCell 2 |272|NOD inst_VPA_D| |*] [MCell 3 |274| -| | ] 2 [IOpin 2 | 83| IO BGACK_030|*| ] paired w/[ RN_BGACK_030] @@ -1871,7 +1709,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 3 [IOpin 3 | 82|INP AS_030|*|*] [RegIn 3 |279| -| | ] - [MCell 6 |278|NOD SM_AMIGA_0_| |*] + [MCell 6 |278|NOD inst_AS_030_000_SYNC| |*] [MCell 7 |280| -| | ] 4 [IOpin 4 | 81| IO DSACK_1_|*|*] paired w/[ RN_DSACK_1_] @@ -1881,7 +1719,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 5 [IOpin 5 | 80|OUT DSACK_0_|*| ] [RegIn 5 |285| -| | ] - [MCell 10 |284|NOD inst_CLK_000_D3| |*] + [MCell 10 |284|NOD SM_AMIGA_0_| |*] [MCell 11 |286| -| | ] 6 [IOpin 6 | 79|INP SIZE_1_|*|*] @@ -1891,7 +1729,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 7 [IOpin 7 | 78| IO FPU_CS|*| ] paired w/[ RN_FPU_CS] [RegIn 7 |291| -| | ] - [MCell 14 |290|NOD CLK_REF_1_| |*] + [MCell 14 |290|NOD inst_CLK_000_D3| |*] [MCell 15 |292| -| | ] --------------------------------------------------------------------------- =========================================================================== @@ -1900,37 +1738,37 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| Input Pin ( 86)| RST +Mux00| Mcel 7 10 ( 284)| SM_AMIGA_0_ Mux01| IOPin 5 2 ( 58)| FC_1_ -Mux02| ... | ... +Mux02| Mcel 7 14 ( 290)| inst_CLK_000_D3 Mux03| Mcel 7 8 ( 281)| RN_DSACK_1_ -Mux04| Input Pin ( 64)| CLK_030 -Mux05| Input Pin ( 14)| nEXP_SPACE -Mux06| IOPin 5 3 ( 57)| FC_0_ -Mux07| Mcel 6 12 ( 263)| inst_CLK_000_D1 +Mux04| IOPin 0 4 ( 95)| A_18_ +Mux05| Mcel 7 9 ( 283)| inst_CLK_000_D4 +Mux06| IOPin 0 6 ( 97)| A_19_ +Mux07| Mcel 7 6 ( 278)| inst_AS_030_000_SYNC Mux08| IOPin 5 1 ( 59)| A_17_ Mux09| IOPin 7 3 ( 82)| AS_030 -Mux10| Mcel 7 1 ( 271)| SM_AMIGA_7_ +Mux10| Mcel 6 8 ( 257)| inst_CLK_000_D0 Mux11| IOPin 0 5 ( 96)| A_16_ -Mux12| IOPin 0 6 ( 97)| A_19_ -Mux13| Mcel 7 5 ( 277)| SM_AMIGA_6_ -Mux14| Mcel 7 2 ( 272)| inst_AS_030_000_SYNC -Mux15| ... | ... -Mux16| Mcel 1 9 ( 139)| SM_AMIGA_1_ -Mux17| IOPin 0 4 ( 95)| A_18_ -Mux18| Mcel 7 10 ( 284)| inst_CLK_000_D3 +Mux12| Mcel 7 1 ( 271)| SM_AMIGA_7_ +Mux13| Mcel 3 3 ( 178)| inst_CLK_000_D2 +Mux14| ... | ... +Mux15| Input Pin ( 14)| nEXP_SPACE +Mux16| ... | ... +Mux17| IOPin 5 3 ( 57)| FC_0_ +Mux18| IOPin 3 7 ( 28)| BGACK_000 Mux19| Mcel 7 13 ( 289)| inst_CLK_000_D5 -Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux21| Mcel 7 6 ( 278)| SM_AMIGA_0_ +Mux20| Input Pin ( 36)| VPA +Mux21| Input Pin ( 86)| RST Mux22| ... | ... -Mux23| Mcel 6 6 ( 254)| inst_CLK_000_D2 +Mux23| Mcel 7 4 ( 275)| RN_BGACK_030 Mux24| Mcel 3 5 ( 181)| RN_AS_000 -Mux25| ... | ... +Mux25| Mcel 3 9 ( 187)| inst_CLK_000_D1 Mux26| ... | ... -Mux27| Mcel 7 9 ( 283)| inst_CLK_000_D4 -Mux28| Mcel 6 8 ( 257)| inst_CLK_000_D0 -Mux29| Input Pin ( 61)| CLK_OSZI +Mux27| Mcel 7 5 ( 277)| SM_AMIGA_6_ +Mux28| Input Pin ( 64)| CLK_030 +Mux29| ... | ... Mux30| Mcel 7 0 ( 269)| RN_FPU_CS -Mux31| ... | ... -Mux32| IOPin 3 7 ( 28)| BGACK_000 +Mux31| Mcel 1 5 ( 133)| SM_AMIGA_1_ +Mux32| ... | ... --------------------------------------------------------------------------- \ No newline at end of file diff --git a/Logic/68030_tk.rpt b/Logic/68030_tk.rpt index 0274065..8ae8104 100644 --- a/Logic/68030_tk.rpt +++ b/Logic/68030_tk.rpt @@ -12,7 +12,7 @@ Project_Summary Project Name : 68030_tk Project Path : C:\Users\Matze\Documents\GitHub\68030tk\Logic -Project Fitted on : Sat May 24 11:44:13 2014 +Project Fitted on : Sat May 24 15:48:54 2014 Device : M4A5-128/64 Package : 100TQFP @@ -40,8 +40,8 @@ Design_Summary Total Input Pins : 35 Total Output Pins : 22 Total Bidir I/O Pins : 2 - Total Flip-Flops : 42 - Total Product Terms : 111 + Total Flip-Flops : 43 + Total Product Terms : 112 Total Reserved Pins : 0 Total Reserved Blocks : 0 @@ -54,13 +54,13 @@ Dedicated Pins Input-Only Pins 2 2 0 --> 100% Clock/Input Pins 4 4 0 --> 100% I/O Pins 64 53 11 --> 82% -Logic Macrocells 128 49 79 --> 38% +Logic Macrocells 128 50 78 --> 39% Input Registers 64 0 64 --> 0% Unusable Macrocells .. 0 .. -CSM Outputs/Total Block Inputs 264 129 135 --> 48% -Logical Product Terms 640 113 527 --> 17% -Product Term Clusters 128 40 88 --> 31% +CSM Outputs/Total Block Inputs 264 110 154 --> 41% +Logical Product Terms 640 115 525 --> 17% +Product Term Clusters 128 31 97 --> 24%  Blocks_Resource_Summary @@ -71,13 +71,13 @@ Blocks_Resource_Summary --------------------------------------------------------------------------------- Maximum 33 8 8 -- -- 16 80 16 - --------------------------------------------------------------------------------- -Block A 8 7 0 2 0 14 3 15 Hi -Block B 19 8 0 7 0 9 17 11 Hi +Block A 0 7 0 1 0 15 1 16 Hi +Block B 20 8 0 9 0 7 22 9 Hi Block C 1 8 0 2 0 14 2 16 Hi -Block D 30 8 0 12 0 4 38 3 Hi +Block D 28 8 0 13 0 3 36 6 Hi Block E 14 3 0 3 0 13 3 16 Hi -Block F 12 4 0 1 0 15 2 15 Hi -Block G 18 7 0 10 0 6 19 11 Hi +Block F 0 4 0 0 0 16 0 16 Hi +Block G 20 7 0 10 0 6 22 10 Hi Block H 27 8 0 12 0 4 29 8 Hi --------------------------------------------------------------------------------- @@ -287,7 +287,7 @@ Input_Signal_List Pin r e O Input Pin Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- - 82 H . I/O A--D-F-H Hi Fast AS_030 + 82 H . I/O ---D--GH Hi Fast AS_030 69 G . I/O ---D---- Hi Fast A_0_ 96 A . I/O -------H Hi Fast A_16_ 59 F . I/O -------H Hi Fast A_17_ @@ -318,10 +318,10 @@ Pin Blk PTs Type e s E Fanout Pwr Slew Signal 79 H . I/O ---D---- Hi Fast SIZE_1_ 11 . . Ck/I ------G- - Fast CLK_000 14 . . Ck/I ---D---H - Fast nEXP_SPACE - 36 . . Ded ------G- - Fast VPA - 61 . . Ck/I AB-D-FGH - Fast CLK_OSZI - 64 . . Ck/I ---D---H - Fast CLK_030 - 86 . . Ded AB-D-FGH - Fast RST + 36 . . Ded -------H - Fast VPA + 61 . . Ck/I -B-D--GH - Fast CLK_OSZI + 64 . . Ck/I -------H - Fast CLK_030 + 86 . . Ded -B-D--GH - Fast RST ---------------------------------------------------------------------- Power : Hi = High @@ -345,12 +345,12 @@ Pin Blk PTs Type e s E Fanout Pwr Slew Signal 22 C 1 COM -------- Hi Fast AVEC_EXP 41 E 1 COM -------- Hi Fast BERR 83 H 2 DFF * * -------- Hi Fast BGACK_030 - 29 D 2 DFF * * -------- Hi Fast BG_000 + 29 D 1 DFF * * -------- Hi Fast BG_000 47 E 1 COM -------- Hi Fast CIIN 65 G 1 DFF * * -------- Hi Fast CLK_DIV_OUT 10 B 1 DFF * * -------- Hi Fast CLK_EXP 80 H 1 COM -------- Hi Fast DSACK_0_ - 66 G 3 TFF * * -------- Hi Fast E + 66 G 3 DFF * * -------- Hi Fast E 78 H 2 DFF * * -------- Hi Fast FPU_CS 8 B 3 DFF * * -------- Hi Fast IPL_030_0_ 7 B 3 DFF * * -------- Hi Fast IPL_030_1_ @@ -358,7 +358,7 @@ Pin Blk PTs Type e s E Fanout Pwr Slew Signal 31 D 8 DFF * * -------- Hi Fast LDS_000 3 B 1 DFF * * -------- Hi Fast RESET 32 D 5 DFF * * -------- Hi Fast UDS_000 - 35 D 2 TFF * * -------- Hi Fast VMA + 35 D 2 DFF * * -------- Hi Fast VMA ---------------------------------------------------------------------- Power : Hi = High @@ -375,7 +375,7 @@ Bidir_Signal_List Pin Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- 81 H 2 DFF * * ---D---- Hi Fast DSACK_1_ - 30 D 1 DFF * * A------- Hi Fast DTACK + 30 D 1 DFF * * ------G- Hi Fast DTACK ---------------------------------------------------------------------- Power : Hi = High @@ -391,44 +391,44 @@ Buried_Signal_List Pin r e O Node #Mc Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- - G2 G 2 DFF * * ------G- Hi Fast CLK_CNT_0_ - G13 G 2 DFF * * ------G- Hi Fast CLK_CNT_1_ - H14 H 1 LAT * * ------G- Hi Fast CLK_REF_1_ + B13 B 2 DFF * * -B----G- Hi Fast CLK_CNT_N_0_ + G13 G 1 DFF * * -B----G- Hi Fast CLK_CNT_N_1_ + G2 G 2 DFF * * ------G- Hi Fast CLK_CNT_P_0_ + G6 G 1 DFF * * ------G- Hi Fast CLK_CNT_P_1_ D4 D 3 DFF * * ---D---- Hi - RN_AMIGA_BUS_ENABLE --> AMIGA_BUS_ENABLE D5 D 2 DFF * * ---D---H Hi - RN_AS_000 --> AS_000 H4 H 2 DFF * * ---D---H Hi - RN_BGACK_030 --> BGACK_030 - D13 D 2 DFF * * ---D---- Hi - RN_BG_000 --> BG_000 H8 H 2 DFF * * -------H Hi - RN_DSACK_1_ --> DSACK_1_ - G4 G 3 TFF * * ---D-FG- Hi - RN_E --> E + G4 G 3 DFF * * ---D--G- Hi - RN_E --> E H0 H 2 DFF * * --C-E--H Hi - RN_FPU_CS --> FPU_CS B8 B 3 DFF * * -B------ Hi - RN_IPL_030_0_ --> IPL_030_0_ B12 B 3 DFF * * -B------ Hi - RN_IPL_030_1_ --> IPL_030_1_ B4 B 3 DFF * * -B------ Hi - RN_IPL_030_2_ --> IPL_030_2_ D8 D 8 DFF * * ---D---- Hi - RN_LDS_000 --> LDS_000 D12 D 5 DFF * * ---D---- Hi - RN_UDS_000 --> UDS_000 - D1 D 2 TFF * * ---D-F-- Hi - RN_VMA --> VMA - H6 H 4 DFF * * -------H Hi Fast SM_AMIGA_0_ - B9 B 3 DFF * * -B-----H Hi Fast SM_AMIGA_1_ - G5 G 3 DFF * * -B----G- Hi Fast SM_AMIGA_2_ - B5 B 3 DFF * * AB---FG- Hi Fast SM_AMIGA_3_ + D1 D 2 DFF * * ---D--G- Hi - RN_VMA --> VMA + H10 H 4 DFF * * -------H Hi Fast SM_AMIGA_0_ + B5 B 3 DFF * * -B-----H Hi Fast SM_AMIGA_1_ + B2 B 3 DFF * * -B------ Hi Fast SM_AMIGA_2_ + B9 B 3 DFF * * -B----G- Hi Fast SM_AMIGA_3_ D10 D 2 DFF * * -B-D---- Hi Fast SM_AMIGA_4_ D14 D 2 DFF * * ---D---- Hi Fast SM_AMIGA_5_ H5 H 2 DFF * * ---D---H Hi Fast SM_AMIGA_6_ H1 H 5 DFF * * ---D---H Hi Fast SM_AMIGA_7_ - D6 D 3 DFF * * ---D-FG- Hi Fast cpu_est_0_ - D9 D 4 TFF * * ---D-FG- Hi Fast cpu_est_1_ - D2 D 3 DFF * * ---D-FG- Hi Fast cpu_est_2_ - H2 H 7 DFF * * -------H Hi Fast inst_AS_030_000_SYNC - G8 G 1 DFF * * AB-D-FGH Hi Fast inst_CLK_000_D0 - G12 G 1 DFF * * -B-D--GH Hi Fast inst_CLK_000_D1 - G6 G 1 DFF * * -------H Hi Fast inst_CLK_000_D2 - H10 H 1 DFF * * -------H Hi Fast inst_CLK_000_D3 + D6 D 3 DFF * * ---D--G- Hi Fast cpu_est_0_ + G12 G 4 TFF * * ---D--G- Hi Fast cpu_est_1_ + D2 D 3 DFF * * ---D--G- Hi Fast cpu_est_2_ + H6 H 7 DFF * * -------H Hi Fast inst_AS_030_000_SYNC + G8 G 1 DFF * * -B-D--GH Hi Fast inst_CLK_000_D0 + D9 D 1 DFF * * -B-D--GH Hi Fast inst_CLK_000_D1 + D3 D 1 DFF * * -------H Hi Fast inst_CLK_000_D2 + H14 H 1 DFF * * -------H Hi Fast inst_CLK_000_D3 H9 H 1 DFF * * -B-----H Hi Fast inst_CLK_000_D4 H13 H 1 DFF * * -B-----H Hi Fast inst_CLK_000_D5 - G9 G 3 DFF * * -B----G- Hi Fast inst_CLK_OUT_PRE - A0 A 2 DFF * * AB----G- Hi Fast inst_DTACK_SYNC - G1 G 1 DFF * * A--D-F-- Hi Fast inst_VPA_D - F0 F 2 DFF * * -B---FG- Hi Fast inst_VPA_SYNC + G1 G 4 DFF * * -B----G- Hi Fast inst_CLK_OUT_PRE + G9 G 2 DFF * * -B----G- Hi Fast inst_DTACK_SYNC + H2 H 1 DFF * * ---D--G- Hi Fast inst_VPA_D + G5 G 2 DFF * * -B----G- Hi Fast inst_VPA_SYNC ---------------------------------------------------------------------- Power : Hi = High @@ -445,47 +445,53 @@ Signal Source : Fanout List ----------------------------------------------------------------------------- SIZE_1_{ I}: LDS_000{ D} A_31_{ C}: CIIN{ E} - IPL_2_{ H}: IPL_030_2_{ B} - FC_1_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} - AS_030{ I}: DSACK_1_{ H} AS_000{ D} UDS_000{ D} - : LDS_000{ D} BG_000{ D} FPU_CS{ H} - :AMIGA_BUS_ENABLE{ D}inst_AS_030_000_SYNC{ H}inst_DTACK_SYNC{ A} - : inst_VPA_SYNC{ F} - DS_030{ B}: UDS_000{ D} LDS_000{ D} - nEXP_SPACE{. }: DSACK_0_{ H} DSACK_1_{ H} BG_000{ D} - :AMIGA_BUS_ENABLE{ D}inst_AS_030_000_SYNC{ H} SM_AMIGA_6_{ H} - : SM_AMIGA_7_{ H} - BG_030{ D}: BG_000{ D} - BGACK_000{ E}: BGACK_030{ H} FPU_CS{ H}inst_AS_030_000_SYNC{ H} - CLK_030{. }: BG_000{ D} FPU_CS{ H}inst_AS_030_000_SYNC{ H} - CLK_000{. }:inst_CLK_000_D0{ G} SIZE_0_{ H}: LDS_000{ D} + IPL_2_{ H}: IPL_030_2_{ B} A_30_{ C}: CIIN{ E} A_29_{ C}: CIIN{ E} A_28_{ D}: CIIN{ E} A_27_{ D}: CIIN{ E} + FC_1_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} A_26_{ D}: CIIN{ E} + AS_030{ I}: DSACK_1_{ H} AS_000{ D} UDS_000{ D} + : LDS_000{ D} BG_000{ D} FPU_CS{ H} + :AMIGA_BUS_ENABLE{ D}inst_AS_030_000_SYNC{ H}inst_DTACK_SYNC{ G} + : inst_VPA_SYNC{ G} A_25_{ D}: CIIN{ E} A_24_{ D}: CIIN{ E} + DS_030{ B}: UDS_000{ D} LDS_000{ D} A_23_{ I}: CIIN{ E} - VPA{. }: inst_VPA_D{ G} A_22_{ I}: CIIN{ E} A_21_{ B}: CIIN{ E} - RST{. }: IPL_030_2_{ B} DSACK_1_{ H} AS_000{ D} - : UDS_000{ D} LDS_000{ D} BG_000{ D} - : BGACK_030{ H} FPU_CS{ H} DTACK{ D} - : VMA{ D} RESET{ B}AMIGA_BUS_ENABLE{ D} - : IPL_030_1_{ B} IPL_030_0_{ B}inst_AS_030_000_SYNC{ H} - :inst_DTACK_SYNC{ A} inst_VPA_SYNC{ F} SM_AMIGA_6_{ H} - : SM_AMIGA_5_{ D} CLK_REF_1_{ H} SM_AMIGA_7_{ H} - : SM_AMIGA_4_{ D} SM_AMIGA_3_{ B} SM_AMIGA_1_{ B} - : SM_AMIGA_2_{ G} SM_AMIGA_0_{ H} + nEXP_SPACE{. }: DSACK_0_{ H} DSACK_1_{ H} BG_000{ D} + :AMIGA_BUS_ENABLE{ D}inst_AS_030_000_SYNC{ H} SM_AMIGA_6_{ H} + : SM_AMIGA_7_{ H} A_20_{ B}: CIIN{ E} A_19_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} - RW{ H}:AMIGA_BUS_DATA_DIR{ E} UDS_000{ D} LDS_000{ D} + BG_030{ D}: BG_000{ D} A_18_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} A_17_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} A_16_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} + BGACK_000{ E}: BGACK_030{ H} FPU_CS{ H}inst_AS_030_000_SYNC{ H} + CLK_030{. }: FPU_CS{ H}inst_AS_030_000_SYNC{ H} + CLK_000{. }:inst_CLK_000_D0{ G} + VPA{. }: inst_VPA_D{ H} + RST{. }: CLK_DIV_OUT{ G} IPL_030_2_{ B} DSACK_1_{ H} + : AS_000{ D} UDS_000{ D} LDS_000{ D} + : BG_000{ D} BGACK_030{ H} CLK_EXP{ B} + : FPU_CS{ H} DTACK{ D} E{ G} + : VMA{ D} RESET{ B}AMIGA_BUS_ENABLE{ D} + : IPL_030_1_{ B} IPL_030_0_{ B}inst_AS_030_000_SYNC{ H} + :inst_DTACK_SYNC{ G} inst_VPA_D{ H} inst_VPA_SYNC{ G} + :inst_CLK_000_D0{ G}inst_CLK_000_D1{ D}inst_CLK_000_D2{ D} + :inst_CLK_000_D5{ H} SM_AMIGA_5_{ D} SM_AMIGA_6_{ H} + :inst_CLK_000_D3{ H} SM_AMIGA_4_{ D}inst_CLK_000_D4{ H} + : SM_AMIGA_7_{ H} SM_AMIGA_3_{ B} SM_AMIGA_1_{ B} + : CLK_CNT_N_0_{ B} CLK_CNT_N_1_{ G} CLK_CNT_P_0_{ G} + : CLK_CNT_P_1_{ G} SM_AMIGA_2_{ B} SM_AMIGA_0_{ H} + :inst_CLK_OUT_PRE{ G} cpu_est_0_{ D} cpu_est_1_{ G} + : cpu_est_2_{ D} + RW{ H}:AMIGA_BUS_DATA_DIR{ E} UDS_000{ D} LDS_000{ D} A_0_{ H}: UDS_000{ D} LDS_000{ D} IPL_1_{ G}: IPL_030_1_{ B} IPL_0_{ H}: IPL_030_0_{ B} @@ -497,61 +503,62 @@ RN_DSACK_1_{ I}: DSACK_1_{ H} : SM_AMIGA_7_{ H} SM_AMIGA_0_{ H} RN_UDS_000{ E}: UDS_000{ D} RN_LDS_000{ E}: LDS_000{ D} - RN_BG_000{ E}: BG_000{ D} RN_BGACK_030{ I}: AS_000{ D} UDS_000{ D} LDS_000{ D} : BGACK_030{ H} DTACK{ D} RN_FPU_CS{ I}: BERR{ E} AVEC_EXP{ C} FPU_CS{ H} - DTACK{ E}:inst_DTACK_SYNC{ A} - RN_E{ H}: E{ G} VMA{ D} cpu_est_1_{ D} - : inst_VPA_SYNC{ F} cpu_est_2_{ D} - RN_VMA{ E}: VMA{ D} inst_VPA_SYNC{ F} + DTACK{ E}:inst_DTACK_SYNC{ G} + RN_E{ H}: E{ G} VMA{ D} inst_VPA_SYNC{ G} + : cpu_est_1_{ G} cpu_est_2_{ D} + RN_VMA{ E}: VMA{ D} inst_VPA_SYNC{ G} RN_AMIGA_BUS_ENABLE{ E}:AMIGA_BUS_ENABLE{ D} RN_IPL_030_1_{ C}: IPL_030_1_{ B} RN_IPL_030_0_{ C}: IPL_030_0_{ B} - cpu_est_0_{ E}: E{ G} VMA{ D} cpu_est_0_{ D} - : cpu_est_1_{ D} inst_VPA_SYNC{ F} cpu_est_2_{ D} - cpu_est_1_{ E}: E{ G} VMA{ D} cpu_est_1_{ D} - : inst_VPA_SYNC{ F} cpu_est_2_{ D} inst_AS_030_000_SYNC{ I}:inst_AS_030_000_SYNC{ H} SM_AMIGA_6_{ H} SM_AMIGA_7_{ H} -inst_DTACK_SYNC{ B}:inst_DTACK_SYNC{ A} SM_AMIGA_3_{ B} SM_AMIGA_2_{ G} - inst_VPA_D{ H}: VMA{ D}inst_DTACK_SYNC{ A} inst_VPA_SYNC{ F} -inst_VPA_SYNC{ G}: inst_VPA_SYNC{ F} SM_AMIGA_3_{ B} SM_AMIGA_2_{ G} -inst_CLK_000_D0{ H}: IPL_030_2_{ B} BGACK_030{ H} E{ G} - : VMA{ D} IPL_030_1_{ B} IPL_030_0_{ B} - : cpu_est_0_{ D} cpu_est_1_{ D}inst_DTACK_SYNC{ A} - : inst_VPA_SYNC{ F}inst_CLK_000_D1{ G} SM_AMIGA_6_{ H} - : SM_AMIGA_5_{ D} cpu_est_2_{ D} SM_AMIGA_7_{ H} - : SM_AMIGA_4_{ D} SM_AMIGA_3_{ B} SM_AMIGA_1_{ B} - : SM_AMIGA_2_{ G} SM_AMIGA_0_{ H} -inst_CLK_000_D1{ H}: IPL_030_2_{ B} BGACK_030{ H} E{ G} - : IPL_030_1_{ B} IPL_030_0_{ B} cpu_est_0_{ D} - : cpu_est_1_{ D}inst_CLK_000_D2{ G} cpu_est_2_{ D} -inst_CLK_000_D2{ H}: SM_AMIGA_6_{ H} SM_AMIGA_7_{ H}inst_CLK_000_D3{ H} +inst_DTACK_SYNC{ H}:inst_DTACK_SYNC{ G} SM_AMIGA_3_{ B} SM_AMIGA_2_{ B} + inst_VPA_D{ I}: VMA{ D}inst_DTACK_SYNC{ G} inst_VPA_SYNC{ G} +inst_VPA_SYNC{ H}: inst_VPA_SYNC{ G} SM_AMIGA_3_{ B} SM_AMIGA_2_{ B} +inst_CLK_000_D0{ H}: IPL_030_2_{ B} BG_000{ D} BGACK_030{ H} + : E{ G} VMA{ D} IPL_030_1_{ B} + : IPL_030_0_{ B}inst_DTACK_SYNC{ G} inst_VPA_SYNC{ G} + :inst_CLK_000_D1{ D} SM_AMIGA_5_{ D} SM_AMIGA_6_{ H} + : SM_AMIGA_4_{ D} SM_AMIGA_7_{ H} SM_AMIGA_3_{ B} + : SM_AMIGA_1_{ B} SM_AMIGA_2_{ B} SM_AMIGA_0_{ H} + : cpu_est_0_{ D} cpu_est_1_{ G} cpu_est_2_{ D} +inst_CLK_000_D1{ E}: IPL_030_2_{ B} BG_000{ D} BGACK_030{ H} + : E{ G} IPL_030_1_{ B} IPL_030_0_{ B} + :inst_CLK_000_D2{ D} cpu_est_0_{ D} cpu_est_1_{ G} + : cpu_est_2_{ D} +inst_CLK_000_D2{ E}: SM_AMIGA_6_{ H}inst_CLK_000_D3{ H} SM_AMIGA_7_{ H} inst_CLK_000_D5{ I}: DSACK_1_{ H}inst_AS_030_000_SYNC{ H} SM_AMIGA_1_{ B} : SM_AMIGA_0_{ H} -inst_CLK_OUT_PRE{ H}: CLK_DIV_OUT{ G} CLK_EXP{ B}inst_CLK_OUT_PRE{ G} -SM_AMIGA_6_{ I}:AMIGA_BUS_ENABLE{ D}inst_AS_030_000_SYNC{ H} SM_AMIGA_6_{ H} - : SM_AMIGA_5_{ D} SM_AMIGA_7_{ H} SM_AMIGA_5_{ E}: AS_000{ D} UDS_000{ D} LDS_000{ D} : SM_AMIGA_5_{ D} SM_AMIGA_4_{ D} - cpu_est_2_{ E}: E{ G} VMA{ D} cpu_est_1_{ D} - : inst_VPA_SYNC{ F} cpu_est_2_{ D} - CLK_REF_1_{ I}:inst_CLK_OUT_PRE{ G} CLK_CNT_0_{ G} CLK_CNT_1_{ G} -SM_AMIGA_7_{ I}: BG_000{ D}inst_AS_030_000_SYNC{ H} SM_AMIGA_6_{ H} - : SM_AMIGA_7_{ H} -inst_CLK_000_D3{ I}: SM_AMIGA_6_{ H} SM_AMIGA_7_{ H}inst_CLK_000_D4{ H} +SM_AMIGA_6_{ I}:AMIGA_BUS_ENABLE{ D}inst_AS_030_000_SYNC{ H} SM_AMIGA_5_{ D} + : SM_AMIGA_6_{ H} SM_AMIGA_7_{ H} +inst_CLK_000_D3{ I}: SM_AMIGA_6_{ H}inst_CLK_000_D4{ H} SM_AMIGA_7_{ H} SM_AMIGA_4_{ E}: UDS_000{ D} LDS_000{ D} SM_AMIGA_4_{ D} : SM_AMIGA_3_{ B} inst_CLK_000_D4{ I}: DSACK_1_{ H}inst_AS_030_000_SYNC{ H}inst_CLK_000_D5{ H} : SM_AMIGA_1_{ B} SM_AMIGA_0_{ H} - CLK_CNT_0_{ H}:inst_CLK_OUT_PRE{ G} CLK_CNT_0_{ G} CLK_CNT_1_{ G} - CLK_CNT_1_{ H}:inst_CLK_OUT_PRE{ G} CLK_CNT_0_{ G} CLK_CNT_1_{ G} -SM_AMIGA_3_{ C}:inst_DTACK_SYNC{ A} inst_VPA_SYNC{ F} SM_AMIGA_3_{ B} - : SM_AMIGA_2_{ G} +SM_AMIGA_7_{ I}: BG_000{ D}inst_AS_030_000_SYNC{ H} SM_AMIGA_6_{ H} + : SM_AMIGA_7_{ H} +SM_AMIGA_3_{ C}:inst_DTACK_SYNC{ G} inst_VPA_SYNC{ G} SM_AMIGA_3_{ B} + : SM_AMIGA_2_{ B} SM_AMIGA_1_{ C}: DSACK_1_{ H}inst_AS_030_000_SYNC{ H} SM_AMIGA_1_{ B} : SM_AMIGA_0_{ H} -SM_AMIGA_2_{ H}: SM_AMIGA_1_{ B} SM_AMIGA_2_{ G} +CLK_CNT_N_0_{ C}: CLK_CNT_N_0_{ B} CLK_CNT_N_1_{ G}inst_CLK_OUT_PRE{ G} +CLK_CNT_N_1_{ H}: CLK_CNT_N_0_{ B}inst_CLK_OUT_PRE{ G} +CLK_CNT_P_0_{ H}: CLK_CNT_P_0_{ G} CLK_CNT_P_1_{ G}inst_CLK_OUT_PRE{ G} +CLK_CNT_P_1_{ H}: CLK_CNT_P_0_{ G}inst_CLK_OUT_PRE{ G} +SM_AMIGA_2_{ C}: SM_AMIGA_1_{ B} SM_AMIGA_2_{ B} SM_AMIGA_0_{ I}: SM_AMIGA_7_{ H} SM_AMIGA_0_{ H} +inst_CLK_OUT_PRE{ H}: CLK_DIV_OUT{ G} CLK_EXP{ B} + cpu_est_0_{ E}: E{ G} VMA{ D} cpu_est_0_{ D} + : cpu_est_1_{ G} cpu_est_2_{ D} + cpu_est_1_{ H}: E{ G} VMA{ D} inst_VPA_SYNC{ G} + : cpu_est_1_{ G} cpu_est_2_{ D} + cpu_est_2_{ E}: E{ G} VMA{ D} cpu_est_1_{ G} + : cpu_est_2_{ D} ----------------------------------------------------------------------------- {.} : Indicates block location of signal @@ -561,14 +568,13 @@ Set_Reset_Summary ~~~~~~~~~~~~~~~~~ Block A -block level set pt : !RST -block level reset pt : GND +block level set pt : +block level reset pt : Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ | | | | | AVEC -| * | S | BS | BR | inst_DTACK_SYNC | | | | | DS_030 | | | | | A_19_ | | | | | A_16_ @@ -587,13 +593,15 @@ Equations : | * | S | BS | BR | IPL_030_2_ | * | S | BS | BR | IPL_030_0_ | * | S | BS | BR | IPL_030_1_ -| * | A | | | CLK_EXP -| * | A | | | RESET -| * | S | BR | BS | SM_AMIGA_3_ +| * | S | BR | BS | CLK_EXP +| * | S | BR | BS | RESET | * | S | BR | BS | SM_AMIGA_1_ +| * | S | BR | BS | SM_AMIGA_3_ +| * | S | BR | BS | CLK_CNT_N_0_ | * | S | BS | BR | RN_IPL_030_0_ | * | S | BS | BR | RN_IPL_030_1_ | * | S | BS | BR | RN_IPL_030_2_ +| * | S | BR | BS | SM_AMIGA_2_ | | | | | A_29_ | | | | | A_30_ | | | | | A_31_ @@ -630,17 +638,17 @@ Equations : | * | S | BS | BR | VMA | * | S | BS | BR | AS_000 | * | S | BS | BR | BG_000 -| * | A | | | cpu_est_1_ -| * | A | | | cpu_est_2_ -| * | A | | | cpu_est_0_ +| * | S | BS | BR | inst_CLK_000_D1 +| * | S | BR | BS | cpu_est_2_ +| * | S | BR | BS | cpu_est_0_ | * | S | BS | BR | RN_VMA | * | S | BS | BR | RN_AS_000 | * | S | BR | BS | SM_AMIGA_4_ | * | S | BS | BR | RN_LDS_000 | * | S | BS | BR | RN_UDS_000 | * | A | | | RN_AMIGA_BUS_ENABLE -| * | S | BS | BR | RN_BG_000 | * | S | BR | BS | SM_AMIGA_5_ +| * | S | BS | BR | inst_CLK_000_D2 | | | | | BGACK_000 @@ -657,13 +665,12 @@ Equations : Block F -block level set pt : !RST -block level reset pt : GND +block level set pt : +block level reset pt : Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ -| * | S | BS | BR | inst_VPA_SYNC | | | | | A_17_ | | | | | FC_1_ | | | | | FC_0_ @@ -672,22 +679,22 @@ Equations : Block G block level set pt : GND -block level reset pt : GND +block level reset pt : !RST Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ | * | S | BS | BR | E | * | S | BS | BR | CLK_DIV_OUT -| * | S | BS | BR | inst_CLK_000_D0 -| * | S | BS | BR | inst_CLK_000_D1 -| * | S | BS | BR | RN_E -| * | S | BS | BR | inst_VPA_D -| * | A | | | SM_AMIGA_2_ +| * | S | BR | BS | inst_CLK_000_D0 +| * | S | BS | BR | cpu_est_1_ | * | S | BS | BR | inst_CLK_OUT_PRE -| * | S | BS | BR | CLK_CNT_1_ -| * | S | BS | BR | CLK_CNT_0_ -| * | S | BS | BR | inst_CLK_000_D2 +| * | S | BS | BR | RN_E +| * | S | BR | BS | inst_VPA_SYNC +| * | S | BR | BS | inst_DTACK_SYNC +| * | S | BS | BR | CLK_CNT_N_1_ +| * | S | BS | BR | CLK_CNT_P_0_ +| * | S | BS | BR | CLK_CNT_P_1_ | | | | | RW | | | | | SIZE_0_ | | | | | A_0_ @@ -710,13 +717,13 @@ Equations : | * | S | BS | BR | SM_AMIGA_7_ | * | S | BS | BR | RN_BGACK_030 | * | S | BR | BS | SM_AMIGA_6_ -| * | A | | | inst_CLK_000_D4 -| * | A | | | inst_CLK_000_D5 +| * | S | BS | BR | inst_CLK_000_D4 +| * | S | BS | BR | inst_CLK_000_D5 +| * | S | BS | BR | inst_VPA_D | * | S | BS | BR | inst_AS_030_000_SYNC | * | S | BR | BS | SM_AMIGA_0_ | * | S | BS | BR | RN_DSACK_1_ -| * | A | | | inst_CLK_000_D3 -| * | A | | | CLK_REF_1_ +| * | S | BS | BR | inst_CLK_000_D3 | | | | | AS_030 | | | | | A_22_ | | | | | A_23_ @@ -733,30 +740,6 @@ Equations : -BLOCK_A_LOGIC_ARRAY_FANIN -~~~~~~~~~~~~~~~~~~~~~~~~~ -CSM Signal Source CSM Signal Source ------------------------------------- ------------------------------------ -mx A0 RST pin 86 mx A17 ... ... -mx A1 ... ... mx A18 ... ... -mx A2 ... ... mx A19 ... ... -mx A3 ... ... mx A20 ... ... -mx A4 CLK_OSZI pin 61 mx A21 ... ... -mx A5 ... ... mx A22 ... ... -mx A6 ... ... mx A23 ... ... -mx A7 ... ... mx A24 inst_VPA_D mcell G1 -mx A8 ... ... mx A25 ... ... -mx A9 AS_030 pin 82 mx A26 ... ... -mx A10 inst_CLK_000_D0 mcell G8 mx A27 ... ... -mx A11 ... ... mx A28 SM_AMIGA_3_ mcell B5 -mx A12 ... ... mx A29 ... ... -mx A13 ... ... mx A30 ... ... -mx A14 DTACK pin 30 mx A31 ... ... -mx A15 inst_DTACK_SYNC mcell A0 mx A32 ... ... -mx A16 ... ... ----------------------------------------------------------------------------- - - BLOCK_B_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source @@ -766,17 +749,17 @@ mx B1 RN_IPL_030_1_ mcell B12 mx B18 ... ... mx B2 SM_AMIGA_4_ mcell D10 mx B19 ... ... mx B3 IPL_1_ pin 56 mx B20 ... ... mx B4 IPL_2_ pin 68 mx B21 RST pin 86 -mx B5 inst_CLK_000_D4 mcell H9 mx B22 SM_AMIGA_2_ mcell G5 -mx B6 SM_AMIGA_1_ mcell B9 mx B23 ... ... -mx B7 inst_CLK_000_D5 mcell H13 mx B24 ... ... -mx B8 RN_IPL_030_0_ mcell B8 mx B25 inst_VPA_SYNC mcell F0 -mx B9 ... ... mx B26 ... ... -mx B10inst_CLK_OUT_PRE mcell G9 mx B27 RN_IPL_030_2_ mcell B4 -mx B11 ... ... mx B28 SM_AMIGA_3_ mcell B5 -mx B12 ... ... mx B29 CLK_OSZI pin 61 +mx B5 inst_CLK_000_D4 mcell H9 mx B22 inst_VPA_SYNC mcell G5 +mx B6 SM_AMIGA_3_ mcell B9 mx B23 ... ... +mx B7 inst_CLK_000_D5 mcell H13 mx B24inst_CLK_OUT_PRE mcell G1 +mx B8 RN_IPL_030_0_ mcell B8 mx B25 inst_CLK_000_D1 mcell D9 +mx B9 CLK_CNT_N_1_ mcell G13 mx B26 ... ... +mx B10 SM_AMIGA_2_ mcell B2 mx B27 RN_IPL_030_2_ mcell B4 +mx B11 ... ... mx B28 CLK_CNT_N_0_ mcell B13 +mx B12 inst_DTACK_SYNC mcell G9 mx B29 ... ... mx B13 inst_CLK_000_D0 mcell G8 mx B30 ... ... -mx B14 inst_CLK_000_D1 mcell G12 mx B31 ... ... -mx B15 inst_DTACK_SYNC mcell A0 mx B32 ... ... +mx B14 ... ... mx B31 SM_AMIGA_1_ mcell B5 +mx B15 ... ... mx B32 ... ... mx B16 ... ... ---------------------------------------------------------------------------- @@ -809,21 +792,21 @@ BLOCK_D_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx D0 SIZE_0_ pin 70 mx D17 SM_AMIGA_5_ mcell D14 -mx D1 RN_BG_000 mcell D13 mx D18 A_0_ pin 69 -mx D2 RN_E mcell G4 mx D19 SM_AMIGA_7_ mcell H1 -mx D3 cpu_est_2_ mcell D2 mx D20 CLK_030 pin 64 -mx D4 cpu_est_0_ mcell D6 mx D21 RST pin 86 -mx D5 RN_UDS_000 mcell D12 mx D22 ... ... -mx D6 SIZE_1_ pin 79 mx D23 RN_BGACK_030 mcell H4 -mx D7 inst_CLK_000_D1 mcell G12 mx D24 inst_VPA_D mcell G1 -mx D8 RW pin 71 mx D25 cpu_est_1_ mcell D9 +mx D0 A_0_ pin 69 mx D17 SM_AMIGA_5_ mcell D14 +mx D1 ... ... mx D18 ... ... +mx D2 RN_VMA mcell D1 mx D19 SM_AMIGA_7_ mcell H1 +mx D3 cpu_est_2_ mcell D2 mx D20 RN_BGACK_030 mcell H4 +mx D4 cpu_est_0_ mcell D6 mx D21RN_AMIGA_BUS_ENABLE mcell D4 +mx D5 RN_UDS_000 mcell D12 mx D22 BG_030 pin 21 +mx D6 SIZE_1_ pin 79 mx D23 cpu_est_1_ mcell G12 +mx D7 RN_AS_000 mcell D5 mx D24 RST pin 86 +mx D8 RW pin 71 mx D25 inst_CLK_000_D1 mcell D9 mx D9 AS_030 pin 82 mx D26 ... ... -mx D10RN_AMIGA_BUS_ENABLE mcell D4 mx D27 RN_VMA mcell D1 -mx D11 RN_AS_000 mcell D5 mx D28 inst_CLK_000_D0 mcell G8 +mx D10 inst_CLK_000_D0 mcell G8 mx D27 ... ... +mx D11 RN_E mcell G4 mx D28 inst_VPA_D mcell H2 mx D12 DS_030 pin 98 mx D29 CLK_OSZI pin 61 mx D13 SM_AMIGA_6_ mcell H5 mx D30 SM_AMIGA_4_ mcell D10 -mx D14 BG_030 pin 21 mx D31 ... ... +mx D14 SIZE_0_ pin 70 mx D31 ... ... mx D15 nEXP_SPACE pin 14 mx D32 DSACK_1_ pin 81 mx D16 RN_LDS_000 mcell D8 ---------------------------------------------------------------------------- @@ -853,50 +836,26 @@ mx E16 ... ... ---------------------------------------------------------------------------- -BLOCK_F_LOGIC_ARRAY_FANIN -~~~~~~~~~~~~~~~~~~~~~~~~~ -CSM Signal Source CSM Signal Source ------------------------------------- ------------------------------------ -mx F0 RST pin 86 mx F17 ... ... -mx F1 ... ... mx F18 ... ... -mx F2 RN_VMA mcell D1 mx F19 ... ... -mx F3 cpu_est_2_ mcell D2 mx F20 ... ... -mx F4 CLK_OSZI pin 61 mx F21 ... ... -mx F5 inst_VPA_SYNC mcell F0 mx F22 ... ... -mx F6 ... ... mx F23 ... ... -mx F7 cpu_est_1_ mcell D9 mx F24 inst_VPA_D mcell G1 -mx F8 ... ... mx F25 ... ... -mx F9 AS_030 pin 82 mx F26 ... ... -mx F10 inst_CLK_000_D0 mcell G8 mx F27 ... ... -mx F11 RN_E mcell G4 mx F28 SM_AMIGA_3_ mcell B5 -mx F12 ... ... mx F29 ... ... -mx F13 ... ... mx F30 ... ... -mx F14 ... ... mx F31 ... ... -mx F15 ... ... mx F32 ... ... -mx F16 cpu_est_0_ mcell D6 ----------------------------------------------------------------------------- - - BLOCK_G_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ mx G0 RST pin 86 mx G17 ... ... mx G1 ... ... mx G18 ... ... -mx G2 CLK_REF_1_ mcell H14 mx G19 ... ... +mx G2 RN_VMA mcell D1 mx G19 ... ... mx G3 CLK_000 pin 11 mx G20 ... ... -mx G4 CLK_OSZI pin 61 mx G21 ... ... -mx G5 inst_VPA_SYNC mcell F0 mx G22 SM_AMIGA_2_ mcell G5 -mx G6 ... ... mx G23 CLK_CNT_0_ mcell G2 -mx G7 cpu_est_1_ mcell D9 mx G24 ... ... -mx G8 ... ... mx G25 ... ... -mx G9 CLK_CNT_1_ mcell G13 mx G26 ... ... -mx G10 VPA pin 36 mx G27 ... ... +mx G4 CLK_CNT_P_0_ mcell G2 mx G21 CLK_CNT_N_0_ mcell B13 +mx G5 CLK_CNT_P_1_ mcell G6 mx G22 inst_VPA_SYNC mcell G5 +mx G6 SM_AMIGA_3_ mcell B9 mx G23 DTACK pin 30 +mx G7 cpu_est_1_ mcell G12 mx G24inst_CLK_OUT_PRE mcell G1 +mx G8 ... ... mx G25 inst_CLK_000_D1 mcell D9 +mx G9 AS_030 pin 82 mx G26 ... ... +mx G10 inst_DTACK_SYNC mcell G9 mx G27 ... ... mx G11 RN_E mcell G4 mx G28 cpu_est_2_ mcell D2 -mx G12inst_CLK_OUT_PRE mcell G9 mx G29 ... ... +mx G12 CLK_CNT_N_1_ mcell G13 mx G29 ... ... mx G13 inst_CLK_000_D0 mcell G8 mx G30 ... ... -mx G14 inst_CLK_000_D1 mcell G12 mx G31 SM_AMIGA_3_ mcell B5 -mx G15 inst_DTACK_SYNC mcell A0 mx G32 ... ... +mx G14 inst_VPA_D mcell H2 mx G31 ... ... +mx G15 ... ... mx G32 ... ... mx G16 cpu_est_0_ mcell D6 ---------------------------------------------------------------------------- @@ -905,23 +864,23 @@ BLOCK_H_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx H0 RST pin 86 mx H17 A_18_ pin 95 -mx H1 FC_1_ pin 58 mx H18 inst_CLK_000_D3 mcell H10 -mx H2 ... ... mx H19 inst_CLK_000_D5 mcell H13 -mx H3 RN_DSACK_1_ mcell H8 mx H20 RN_BGACK_030 mcell H4 -mx H4 CLK_030 pin 64 mx H21 SM_AMIGA_0_ mcell H6 -mx H5 nEXP_SPACE pin 14 mx H22 ... ... -mx H6 FC_0_ pin 57 mx H23 inst_CLK_000_D2 mcell G6 -mx H7 inst_CLK_000_D1 mcell G12 mx H24 RN_AS_000 mcell D5 -mx H8 A_17_ pin 59 mx H25 ... ... +mx H0 SM_AMIGA_0_ mcell H10 mx H17 FC_0_ pin 57 +mx H1 FC_1_ pin 58 mx H18 BGACK_000 pin 28 +mx H2 inst_CLK_000_D3 mcell H14 mx H19 inst_CLK_000_D5 mcell H13 +mx H3 RN_DSACK_1_ mcell H8 mx H20 VPA pin 36 +mx H4 A_18_ pin 95 mx H21 RST pin 86 +mx H5 inst_CLK_000_D4 mcell H9 mx H22 ... ... +mx H6 A_19_ pin 97 mx H23 RN_BGACK_030 mcell H4 +mx H7inst_AS_030_000_SYNC mcell H6 mx H24 RN_AS_000 mcell D5 +mx H8 A_17_ pin 59 mx H25 inst_CLK_000_D1 mcell D9 mx H9 AS_030 pin 82 mx H26 ... ... -mx H10 SM_AMIGA_7_ mcell H1 mx H27 inst_CLK_000_D4 mcell H9 -mx H11 A_16_ pin 96 mx H28 inst_CLK_000_D0 mcell G8 -mx H12 A_19_ pin 97 mx H29 CLK_OSZI pin 61 -mx H13 SM_AMIGA_6_ mcell H5 mx H30 RN_FPU_CS mcell H0 -mx H14inst_AS_030_000_SYNC mcell H2 mx H31 ... ... -mx H15 ... ... mx H32 BGACK_000 pin 28 -mx H16 SM_AMIGA_1_ mcell B9 +mx H10 inst_CLK_000_D0 mcell G8 mx H27 SM_AMIGA_6_ mcell H5 +mx H11 A_16_ pin 96 mx H28 CLK_030 pin 64 +mx H12 SM_AMIGA_7_ mcell H1 mx H29 ... ... +mx H13 inst_CLK_000_D2 mcell D3 mx H30 RN_FPU_CS mcell H0 +mx H14 ... ... mx H31 SM_AMIGA_1_ mcell B5 +mx H15 nEXP_SPACE pin 14 mx H32 ... ... +mx H16 ... ... ---------------------------------------------------------------------------- CSM indicates the mux inputs from the Central Switch Matrix. @@ -938,6 +897,7 @@ PostFit_Equations --------- ------ ------- ---- ----------------- 0 0 1 Pin BERR 1 1 1 Pin BERR.OE + 1 1 1 Pin CLK_DIV_OUT.AR 1 1 1 Pin CLK_DIV_OUT.D 1 1 1 Pin CLK_DIV_OUT.C 1 0 1 Pin AVEC @@ -968,12 +928,13 @@ PostFit_Equations 8 9 1 Pin LDS_000.D 1 1 1 Pin LDS_000.AP 1 1 1 Pin LDS_000.C - 2 6 1 Pin BG_000.D- + 1 6 1 Pin BG_000.D- 1 1 1 Pin BG_000.AP 1 1 1 Pin BG_000.C 2 4 1 Pin BGACK_030.D 1 1 1 Pin BGACK_030.AP 1 1 1 Pin BGACK_030.C + 1 1 1 Pin CLK_EXP.AR 1 1 1 Pin CLK_EXP.D 1 1 1 Pin CLK_EXP.C 2 10 1 Pin FPU_CS.D- @@ -983,12 +944,16 @@ PostFit_Equations 1 2 1 Pin DTACK.D- 1 1 1 Pin DTACK.AP 1 1 1 Pin DTACK.C - 3 6 1 Pin E.T + 3 6 1 PinX1 E.D.X1 + 1 1 1 PinX2 E.D.X2 + 1 1 1 Pin E.AR 1 1 1 Pin E.C + 2 7 1 PinX1 VMA.D.X1 + 1 5 1 PinX2 VMA.D.X2 1 1 1 Pin VMA.AP - 2 8 1 Pin VMA.T 1 1 1 Pin VMA.C - 1 1 1 Pin RESET.D + 1 1 1 Pin RESET.AR + 1 0 1 Pin RESET.D 1 1 1 Pin RESET.C 3 5 1 Pin AMIGA_BUS_ENABLE.D- 1 1 1 Pin AMIGA_BUS_ENABLE.C @@ -998,10 +963,6 @@ PostFit_Equations 3 4 1 Pin IPL_030_0_.D 1 1 1 Pin IPL_030_0_.AP 1 1 1 Pin IPL_030_0_.C - 3 3 1 Node cpu_est_0_.D - 1 1 1 Node cpu_est_0_.C - 4 6 1 Node cpu_est_1_.T - 1 1 1 Node cpu_est_1_.C 7 16 1 Node inst_AS_030_000_SYNC.D 1 1 1 Node inst_AS_030_000_SYNC.AP 1 1 1 Node inst_AS_030_000_SYNC.C @@ -1009,63 +970,82 @@ PostFit_Equations 1 1 1 Node inst_DTACK_SYNC.AP 1 1 1 Node inst_DTACK_SYNC.C 1 1 1 Node inst_VPA_D.D + 1 1 1 Node inst_VPA_D.AP 1 1 1 Node inst_VPA_D.C - 2 10 1 Node inst_VPA_SYNC.D- + 2 8 1 Node inst_VPA_SYNC.D- 1 1 1 Node inst_VPA_SYNC.AP 1 1 1 Node inst_VPA_SYNC.C 1 1 1 Node inst_CLK_000_D0.D + 1 1 1 Node inst_CLK_000_D0.AP 1 1 1 Node inst_CLK_000_D0.C 1 1 1 Node inst_CLK_000_D1.D + 1 1 1 Node inst_CLK_000_D1.AP 1 1 1 Node inst_CLK_000_D1.C 1 1 1 Node inst_CLK_000_D2.D + 1 1 1 Node inst_CLK_000_D2.AP 1 1 1 Node inst_CLK_000_D2.C 1 1 1 Node inst_CLK_000_D5.D + 1 1 1 Node inst_CLK_000_D5.AP 1 1 1 Node inst_CLK_000_D5.C - 3 3 1 NodeX1 inst_CLK_OUT_PRE.D.X1 - 1 2 1 NodeX2 inst_CLK_OUT_PRE.D.X2 - 1 1 1 Node inst_CLK_OUT_PRE.C - 1 1 1 Node SM_AMIGA_6_.AR - 2 7 1 Node SM_AMIGA_6_.D - 1 1 1 Node SM_AMIGA_6_.C 1 1 1 Node SM_AMIGA_5_.AR 2 3 1 Node SM_AMIGA_5_.D 1 1 1 Node SM_AMIGA_5_.C - 3 6 1 NodeX1 cpu_est_2_.D.X1 - 1 1 1 NodeX2 cpu_est_2_.D.X2 - 1 1 1 Node cpu_est_2_.C - 1 1 1 Node CLK_REF_1_.AR - 0 0 1 Node CLK_REF_1_.D - 0 0 1 Node CLK_REF_1_.LH - 5 9 1 Node SM_AMIGA_7_.D - 1 1 1 Node SM_AMIGA_7_.AP - 1 1 1 Node SM_AMIGA_7_.C + 1 1 1 Node SM_AMIGA_6_.AR + 2 7 1 Node SM_AMIGA_6_.D + 1 1 1 Node SM_AMIGA_6_.C 1 1 1 Node inst_CLK_000_D3.D + 1 1 1 Node inst_CLK_000_D3.AP 1 1 1 Node inst_CLK_000_D3.C 1 1 1 Node SM_AMIGA_4_.AR 2 3 1 Node SM_AMIGA_4_.D 1 1 1 Node SM_AMIGA_4_.C 1 1 1 Node inst_CLK_000_D4.D + 1 1 1 Node inst_CLK_000_D4.AP 1 1 1 Node inst_CLK_000_D4.C - 2 3 1 Node CLK_CNT_0_.D - 1 1 1 Node CLK_CNT_0_.C - 2 3 1 Node CLK_CNT_1_.D - 1 1 1 Node CLK_CNT_1_.C + 5 9 1 Node SM_AMIGA_7_.D + 1 1 1 Node SM_AMIGA_7_.AP + 1 1 1 Node SM_AMIGA_7_.C 1 1 1 Node SM_AMIGA_3_.AR 3 5 1 Node SM_AMIGA_3_.D 1 1 1 Node SM_AMIGA_3_.C 1 1 1 Node SM_AMIGA_1_.AR 3 5 1 Node SM_AMIGA_1_.D 1 1 1 Node SM_AMIGA_1_.C + 1 1 1 Node CLK_CNT_N_0_.AR + 2 2 1 Node CLK_CNT_N_0_.D + 1 1 1 Node CLK_CNT_N_0_.C + 1 1 1 Node CLK_CNT_N_1_.AR + 1 1 1 Node CLK_CNT_N_1_.D + 1 1 1 Node CLK_CNT_N_1_.C + 1 1 1 Node CLK_CNT_P_0_.AR + 2 2 1 Node CLK_CNT_P_0_.D + 1 1 1 Node CLK_CNT_P_0_.C + 1 1 1 Node CLK_CNT_P_1_.AR + 1 1 1 Node CLK_CNT_P_1_.D + 1 1 1 Node CLK_CNT_P_1_.C 1 1 1 Node SM_AMIGA_2_.AR 3 5 1 Node SM_AMIGA_2_.D 1 1 1 Node SM_AMIGA_2_.C 1 1 1 Node SM_AMIGA_0_.AR 4 6 1 Node SM_AMIGA_0_.D 1 1 1 Node SM_AMIGA_0_.C + 1 1 1 Node inst_CLK_OUT_PRE.AR + 4 4 1 Node inst_CLK_OUT_PRE.D + 1 1 1 Node inst_CLK_OUT_PRE.C + 1 1 1 Node cpu_est_0_.AR + 3 3 1 Node cpu_est_0_.D + 1 1 1 Node cpu_est_0_.C + 1 1 1 Node cpu_est_1_.AR + 4 6 1 Node cpu_est_1_.T + 1 1 1 Node cpu_est_1_.C + 3 6 1 NodeX1 cpu_est_2_.D.X1 + 1 1 1 NodeX2 cpu_est_2_.D.X2 + 1 1 1 Node cpu_est_2_.AR + 1 1 1 Node cpu_est_2_.C ========= - 184 P-Term Total: 184 + 207 P-Term Total: 207 Total Pins: 59 - Total Nodes: 25 + Total Nodes: 26 Average P-Term/Output: 2 @@ -1075,6 +1055,8 @@ BERR = (0); BERR.OE = (!FPU_CS.Q); +CLK_DIV_OUT.AR = (!RST); + CLK_DIV_OUT.D = (inst_CLK_OUT_PRE.Q); CLK_DIV_OUT.C = (CLK_OSZI); @@ -1097,7 +1079,7 @@ DSACK_0_ = (1); DSACK_0_.OE = (nEXP_SPACE); -IPL_030_2_.D = (!inst_CLK_000_D0.Q & IPL_030_2_.Q +IPL_030_2_.D = (IPL_030_2_.Q & !inst_CLK_000_D0.Q # IPL_030_2_.Q & inst_CLK_000_D1.Q # IPL_2_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q); @@ -1150,8 +1132,7 @@ LDS_000.AP = (!RST); LDS_000.C = (CLK_OSZI); -!BG_000.D = (!BG_030 & CLK_030 & !BG_000.Q - # AS_030 & !nEXP_SPACE & !BG_030 & !CLK_030 & SM_AMIGA_7_.Q); +!BG_000.D = (AS_030 & !nEXP_SPACE & !BG_030 & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & SM_AMIGA_7_.Q); BG_000.AP = (!RST); @@ -1164,6 +1145,8 @@ BGACK_030.AP = (!RST); BGACK_030.C = (CLK_OSZI); +CLK_EXP.AR = (!RST); + CLK_EXP.D = (inst_CLK_OUT_PRE.Q); CLK_EXP.C = (CLK_OSZI); @@ -1183,20 +1166,28 @@ DTACK.AP = (!RST); DTACK.C = (CLK_OSZI); -E.T = (E.Q & cpu_est_0_.Q & cpu_est_1_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_2_.Q - # !E.Q & cpu_est_0_.Q & cpu_est_1_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_2_.Q - # !E.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_2_.Q); +E.D.X1 = (inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_1_.Q & cpu_est_2_.Q & E.Q + # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_0_.Q & !cpu_est_2_.Q & !E.Q + # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !E.Q); + +E.D.X2 = (E.Q); + +E.AR = (!RST); E.C = (CLK_OSZI); -VMA.AP = (!RST); +VMA.D.X1 = (VMA.Q + # !VMA.Q & AS_000.Q & inst_CLK_000_D0.Q & !cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & !E.Q); -VMA.T = (!E.Q & !VMA.Q & !cpu_est_0_.Q & cpu_est_1_.Q & AS_000.Q & inst_CLK_000_D0.Q & cpu_est_2_.Q - # !E.Q & VMA.Q & cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & !inst_CLK_000_D0.Q & cpu_est_2_.Q); +VMA.D.X2 = (VMA.Q & !inst_VPA_D.Q & !inst_CLK_000_D0.Q & cpu_est_0_.Q & !cpu_est_1_.Q); + +VMA.AP = (!RST); VMA.C = (CLK_OSZI); -RESET.D = (RST); +RESET.AR = (!RST); + +RESET.D = (1); RESET.C = (CLK_OSZI); @@ -1222,19 +1213,6 @@ IPL_030_0_.AP = (!RST); IPL_030_0_.C = (CLK_OSZI); -cpu_est_0_.D = (cpu_est_0_.Q & !inst_CLK_000_D0.Q - # cpu_est_0_.Q & inst_CLK_000_D1.Q - # !cpu_est_0_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q); - -cpu_est_0_.C = (CLK_OSZI); - -cpu_est_1_.T = (E.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q - # !E.Q & cpu_est_0_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_2_.Q - # !E.Q & !cpu_est_1_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_2_.Q - # E.Q & cpu_est_0_.Q & cpu_est_1_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_2_.Q); - -cpu_est_1_.C = (CLK_OSZI); - inst_AS_030_000_SYNC.D = (AS_030 # !nEXP_SPACE & inst_AS_030_000_SYNC.Q # !CLK_030 & inst_AS_030_000_SYNC.Q @@ -1256,10 +1234,12 @@ inst_DTACK_SYNC.C = (CLK_OSZI); inst_VPA_D.D = (VPA); +inst_VPA_D.AP = (!RST); + inst_VPA_D.C = (CLK_OSZI); !inst_VPA_SYNC.D = (!AS_030 & !inst_VPA_SYNC.Q - # E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_D0.Q & cpu_est_2_.Q & SM_AMIGA_3_.Q); + # !VMA.Q & !inst_VPA_D.Q & inst_CLK_000_D0.Q & SM_AMIGA_3_.Q & !cpu_est_1_.Q & E.Q); inst_VPA_SYNC.AP = (!RST); @@ -1267,68 +1247,46 @@ inst_VPA_SYNC.C = (CLK_OSZI); inst_CLK_000_D0.D = (CLK_000); +inst_CLK_000_D0.AP = (!RST); + inst_CLK_000_D0.C = (CLK_OSZI); inst_CLK_000_D1.D = (inst_CLK_000_D0.Q); +inst_CLK_000_D1.AP = (!RST); + inst_CLK_000_D1.C = (CLK_OSZI); inst_CLK_000_D2.D = (inst_CLK_000_D1.Q); +inst_CLK_000_D2.AP = (!RST); + inst_CLK_000_D2.C = (CLK_OSZI); inst_CLK_000_D5.D = (inst_CLK_000_D4.Q); +inst_CLK_000_D5.AP = (!RST); + inst_CLK_000_D5.C = (CLK_OSZI); -inst_CLK_OUT_PRE.D.X1 = (inst_CLK_OUT_PRE.Q & CLK_CNT_0_.Q - # inst_CLK_OUT_PRE.Q & CLK_CNT_1_.Q - # !inst_CLK_OUT_PRE.Q & !CLK_CNT_0_.Q & !CLK_CNT_1_.Q); - -inst_CLK_OUT_PRE.D.X2 = (CLK_REF_1_.Q & !CLK_CNT_0_.Q); - -inst_CLK_OUT_PRE.C = (CLK_OSZI); - -SM_AMIGA_6_.AR = (!RST); - -SM_AMIGA_6_.D = (nEXP_SPACE & !inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !SM_AMIGA_7_.Q - # !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D2.Q & SM_AMIGA_7_.Q & inst_CLK_000_D3.Q); - -SM_AMIGA_6_.C = (CLK_OSZI); - SM_AMIGA_5_.AR = (!RST); -SM_AMIGA_5_.D = (inst_CLK_000_D0.Q & SM_AMIGA_6_.Q - # inst_CLK_000_D0.Q & SM_AMIGA_5_.Q); +SM_AMIGA_5_.D = (inst_CLK_000_D0.Q & SM_AMIGA_5_.Q + # inst_CLK_000_D0.Q & SM_AMIGA_6_.Q); SM_AMIGA_5_.C = (CLK_OSZI); -cpu_est_2_.D.X1 = (E.Q & cpu_est_0_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_2_.Q - # !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_2_.Q - # !E.Q & cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_2_.Q); +SM_AMIGA_6_.AR = (!RST); -cpu_est_2_.D.X2 = (cpu_est_2_.Q); +SM_AMIGA_6_.D = (!inst_AS_030_000_SYNC.Q & !inst_CLK_000_D2.Q & inst_CLK_000_D3.Q & SM_AMIGA_7_.Q + # nEXP_SPACE & !inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !SM_AMIGA_7_.Q); -cpu_est_2_.C = (CLK_OSZI); - -CLK_REF_1_.AR = (!RST); - -CLK_REF_1_.D = (0); - -CLK_REF_1_.LH = (0); - -SM_AMIGA_7_.D = (inst_AS_030_000_SYNC.Q & SM_AMIGA_7_.Q - # inst_CLK_000_D2.Q & SM_AMIGA_7_.Q - # SM_AMIGA_7_.Q & !inst_CLK_000_D3.Q - # !nEXP_SPACE & !inst_CLK_000_D0.Q & SM_AMIGA_6_.Q - # AS_000.Q & inst_CLK_000_D0.Q & SM_AMIGA_0_.Q); - -SM_AMIGA_7_.AP = (!RST); - -SM_AMIGA_7_.C = (CLK_OSZI); +SM_AMIGA_6_.C = (CLK_OSZI); inst_CLK_000_D3.D = (inst_CLK_000_D2.Q); +inst_CLK_000_D3.AP = (!RST); + inst_CLK_000_D3.C = (CLK_OSZI); SM_AMIGA_4_.AR = (!RST); @@ -1340,17 +1298,19 @@ SM_AMIGA_4_.C = (CLK_OSZI); inst_CLK_000_D4.D = (inst_CLK_000_D3.Q); +inst_CLK_000_D4.AP = (!RST); + inst_CLK_000_D4.C = (CLK_OSZI); -CLK_CNT_0_.D = (!CLK_REF_1_.Q & !CLK_CNT_0_.Q & CLK_CNT_1_.Q - # CLK_REF_1_.Q & !CLK_CNT_0_.Q & !CLK_CNT_1_.Q); +SM_AMIGA_7_.D = (inst_AS_030_000_SYNC.Q & SM_AMIGA_7_.Q + # inst_CLK_000_D2.Q & SM_AMIGA_7_.Q + # !inst_CLK_000_D3.Q & SM_AMIGA_7_.Q + # !nEXP_SPACE & !inst_CLK_000_D0.Q & SM_AMIGA_6_.Q + # AS_000.Q & inst_CLK_000_D0.Q & SM_AMIGA_0_.Q); -CLK_CNT_0_.C = (CLK_OSZI); +SM_AMIGA_7_.AP = (!RST); -CLK_CNT_1_.D = (CLK_CNT_0_.Q & !CLK_CNT_1_.Q - # !CLK_REF_1_.Q & !CLK_CNT_0_.Q & CLK_CNT_1_.Q); - -CLK_CNT_1_.C = (CLK_OSZI); +SM_AMIGA_7_.C = (CLK_OSZI); SM_AMIGA_3_.AR = (!RST); @@ -1368,6 +1328,32 @@ SM_AMIGA_1_.D = (inst_CLK_000_D0.Q & SM_AMIGA_1_.Q SM_AMIGA_1_.C = (CLK_OSZI); +CLK_CNT_N_0_.AR = (!RST); + +CLK_CNT_N_0_.D = (CLK_CNT_N_0_.Q & CLK_CNT_N_1_.Q + # !CLK_CNT_N_0_.Q & !CLK_CNT_N_1_.Q); + +CLK_CNT_N_0_.C = (!CLK_OSZI); + +CLK_CNT_N_1_.AR = (!RST); + +CLK_CNT_N_1_.D = (CLK_CNT_N_0_.Q); + +CLK_CNT_N_1_.C = (!CLK_OSZI); + +CLK_CNT_P_0_.AR = (!RST); + +CLK_CNT_P_0_.D = (CLK_CNT_P_0_.Q & CLK_CNT_P_1_.Q + # !CLK_CNT_P_0_.Q & !CLK_CNT_P_1_.Q); + +CLK_CNT_P_0_.C = (CLK_OSZI); + +CLK_CNT_P_1_.AR = (!RST); + +CLK_CNT_P_1_.D = (CLK_CNT_P_0_.Q); + +CLK_CNT_P_1_.C = (CLK_OSZI); + SM_AMIGA_2_.AR = (!RST); SM_AMIGA_2_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_2_.Q @@ -1385,6 +1371,42 @@ SM_AMIGA_0_.D = (!AS_000.Q & SM_AMIGA_0_.Q SM_AMIGA_0_.C = (CLK_OSZI); +inst_CLK_OUT_PRE.AR = (!RST); + +inst_CLK_OUT_PRE.D = (!CLK_CNT_N_0_.Q & CLK_CNT_N_1_.Q & !CLK_CNT_P_0_.Q & CLK_CNT_P_1_.Q + # CLK_CNT_N_0_.Q & !CLK_CNT_N_1_.Q & !CLK_CNT_P_0_.Q & CLK_CNT_P_1_.Q + # !CLK_CNT_N_0_.Q & CLK_CNT_N_1_.Q & CLK_CNT_P_0_.Q & !CLK_CNT_P_1_.Q + # CLK_CNT_N_0_.Q & !CLK_CNT_N_1_.Q & CLK_CNT_P_0_.Q & !CLK_CNT_P_1_.Q); + +inst_CLK_OUT_PRE.C = (CLK_OSZI); + +cpu_est_0_.AR = (!RST); + +cpu_est_0_.D = (!inst_CLK_000_D0.Q & cpu_est_0_.Q + # inst_CLK_000_D1.Q & cpu_est_0_.Q + # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_0_.Q); + +cpu_est_0_.C = (CLK_OSZI); + +cpu_est_1_.AR = (!RST); + +cpu_est_1_.T = (inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_1_.Q & cpu_est_2_.Q & E.Q + # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_0_.Q & !cpu_est_2_.Q & E.Q + # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_0_.Q & cpu_est_2_.Q & !E.Q + # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !E.Q); + +cpu_est_1_.C = (CLK_OSZI); + +cpu_est_2_.D.X1 = (inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q + # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_0_.Q & !cpu_est_2_.Q & E.Q + # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_0_.Q & !cpu_est_1_.Q & cpu_est_2_.Q & !E.Q); + +cpu_est_2_.D.X2 = (cpu_est_2_.Q); + +cpu_est_2_.AR = (!RST); + +cpu_est_2_.C = (CLK_OSZI); + Reverse-Polarity Equations: diff --git a/Logic/68030_tk.tal b/Logic/68030_tk.tal index 128a8d7..f30acc8 100644 --- a/Logic/68030_tk.tal +++ b/Logic/68030_tk.tal @@ -44,8 +44,7 @@ AMIGA_BUS_DATA_DIR .. .. .. .. 1 1 .. .. RN_UDS_000 1 1 0 0 .. .. 1 1 LDS_000 1 1 0 0 .. .. 1 1 RN_LDS_000 1 1 0 0 .. .. 1 1 - BG_000 1 1 0 0 .. .. 1 1 - RN_BG_000 1 1 0 0 .. .. 1 1 + BG_000 1 1 0 0 .. .. .. .. BGACK_030 1 1 0 0 .. .. 1 1 RN_BGACK_030 1 1 0 0 .. .. 1 1 FPU_CS 1 1 0 0 .. .. 1 1 @@ -55,15 +54,12 @@ AMIGA_BUS_DATA_DIR .. .. .. .. 1 1 .. .. RN_E .. .. 0 0 .. .. 1 1 VMA .. .. 0 0 .. .. 1 1 RN_VMA .. .. 0 0 .. .. 1 1 - RESET 1 1 0 0 .. .. .. .. AMIGA_BUS_ENABLE 1 1 0 0 .. .. 1 1 RN_AMIGA_BUS_ENABLE 1 1 0 0 .. .. 1 1 IPL_030_1_ 1 1 0 0 .. .. 1 1 RN_IPL_030_1_ 1 1 0 0 .. .. 1 1 IPL_030_0_ 1 1 0 0 .. .. 1 1 RN_IPL_030_0_ 1 1 0 0 .. .. 1 1 - cpu_est_0_ .. .. .. .. .. .. 1 1 - cpu_est_1_ .. .. .. .. .. .. 1 1 inst_AS_030_000_SYNC 1 1 .. .. .. .. 1 1 inst_DTACK_SYNC 1 1 .. .. .. .. 1 1 inst_VPA_D 1 1 .. .. .. .. 1 1 @@ -72,18 +68,21 @@ inst_AS_030_000_SYNC 1 1 .. .. .. .. 1 1 inst_CLK_000_D1 .. .. .. .. .. .. 1 1 inst_CLK_000_D2 .. .. .. .. .. .. 1 1 inst_CLK_000_D5 .. .. .. .. .. .. 1 1 -inst_CLK_OUT_PRE .. .. .. .. .. .. 1 1 - SM_AMIGA_6_ 1 1 .. .. .. .. 1 1 SM_AMIGA_5_ .. .. .. .. .. .. 1 1 - cpu_est_2_ .. .. .. .. .. .. 1 1 - CLK_REF_1_ .. .. .. .. .. .. 1 1 - SM_AMIGA_7_ 1 1 .. .. .. .. 1 1 + SM_AMIGA_6_ 1 1 .. .. .. .. 1 1 inst_CLK_000_D3 .. .. .. .. .. .. 1 1 SM_AMIGA_4_ .. .. .. .. .. .. 1 1 inst_CLK_000_D4 .. .. .. .. .. .. 1 1 - CLK_CNT_0_ .. .. .. .. .. .. 1 1 - CLK_CNT_1_ .. .. .. .. .. .. 1 1 + SM_AMIGA_7_ 1 1 .. .. .. .. 1 1 SM_AMIGA_3_ .. .. .. .. .. .. 1 1 SM_AMIGA_1_ .. .. .. .. .. .. 1 1 + CLK_CNT_N_0_ .. .. .. .. .. .. 1 1 + CLK_CNT_N_1_ .. .. .. .. .. .. 1 1 + CLK_CNT_P_0_ .. .. .. .. .. .. 1 1 + CLK_CNT_P_1_ .. .. .. .. .. .. 1 1 SM_AMIGA_2_ .. .. .. .. .. .. 1 1 - SM_AMIGA_0_ .. .. .. .. .. .. 1 1 \ No newline at end of file + SM_AMIGA_0_ .. .. .. .. .. .. 1 1 +inst_CLK_OUT_PRE .. .. .. .. .. .. 1 1 + cpu_est_0_ .. .. .. .. .. .. 1 1 + cpu_est_1_ .. .. .. .. .. .. 1 1 + cpu_est_2_ .. .. .. .. .. .. 1 1 \ No newline at end of file diff --git a/Logic/68030_tk.tt2 b/Logic/68030_tk.tt2 index 8a20921..ed9ad86 100644 --- a/Logic/68030_tk.tt2 +++ b/Logic/68030_tk.tt2 @@ -1,323 +1,325 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Sat May 24 11:44:09 2014 +#$ DATE Sat May 24 15:48:50 2014 #$ MODULE 68030_tk -#$ PINS 59 SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 SIZE_0_ CLK_OSZI A_30_ CLK_DIV_OUT A_29_ A_28_ A_27_ A_26_ AVEC A_25_ AVEC_EXP A_24_ A_23_ VPA A_22_ A_21_ RST A_20_ A_19_ RW A_18_ A_17_ AMIGA_BUS_DATA_DIR A_16_ AMIGA_BUS_ENABLE_LOW CIIN A_0_ IPL_1_ IPL_0_ DSACK_0_ FC_0_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 BG_000 BGACK_030 CLK_EXP FPU_CS DTACK E VMA RESET AMIGA_BUS_ENABLE IPL_030_1_ IPL_030_0_ -#$ NODES 25 cpu_est_0_ cpu_est_1_ inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2 inst_CLK_000_D5 inst_CLK_OUT_PRE SM_AMIGA_6_ SM_AMIGA_5_ cpu_est_2_ CLK_REF_1_ SM_AMIGA_7_ inst_CLK_000_D3 SM_AMIGA_4_ inst_CLK_000_D4 CLK_CNT_0_ CLK_CNT_1_ SM_AMIGA_3_ SM_AMIGA_1_ SM_AMIGA_2_ SM_AMIGA_0_ +#$ PINS 59 SIZE_1_ A_31_ SIZE_0_ IPL_2_ A_30_ A_29_ A_28_ A_27_ FC_1_ A_26_ AS_030 A_25_ A_24_ DS_030 A_23_ A_22_ A_21_ nEXP_SPACE A_20_ BERR A_19_ BG_030 A_18_ A_17_ A_16_ BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT AVEC AVEC_EXP VPA RST RW A_0_ AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW IPL_1_ CIIN IPL_0_ DSACK_0_ FC_0_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 BG_000 BGACK_030 CLK_EXP FPU_CS DTACK E VMA RESET AMIGA_BUS_ENABLE IPL_030_1_ IPL_030_0_ +#$ NODES 26 inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2 inst_CLK_000_D5 SM_AMIGA_5_ SM_AMIGA_6_ inst_CLK_000_D3 SM_AMIGA_4_ inst_CLK_000_D4 SM_AMIGA_7_ SM_AMIGA_3_ SM_AMIGA_1_ CLK_CNT_N_0_ CLK_CNT_N_1_ CLK_CNT_P_0_ CLK_CNT_P_1_ SM_AMIGA_2_ SM_AMIGA_0_ inst_CLK_OUT_PRE cpu_est_0_ cpu_est_1_ cpu_est_2_ .type fr .i 75 -.o 124 -.ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q FPU_CS.Q E.Q VMA.Q cpu_est_0_.Q cpu_est_1_.Q AS_000.Q inst_AS_030_000_SYNC.Q IPL_030_0_.Q inst_DTACK_SYNC.Q inst_VPA_D.Q IPL_030_1_.Q inst_VPA_SYNC.Q inst_CLK_000_D0.Q IPL_030_2_.Q inst_CLK_000_D1.Q inst_CLK_000_D2.Q inst_CLK_000_D5.Q inst_CLK_OUT_PRE.Q SM_AMIGA_6_.Q SM_AMIGA_5_.Q cpu_est_2_.Q CLK_REF_1_.Q UDS_000.Q LDS_000.Q DSACK_1_.Q SM_AMIGA_7_.Q inst_CLK_000_D3.Q SM_AMIGA_4_.Q inst_CLK_000_D4.Q CLK_CNT_0_.Q CLK_CNT_1_.Q SM_AMIGA_3_.Q SM_AMIGA_1_.Q SM_AMIGA_2_.Q AMIGA_BUS_ENABLE.Q SM_AMIGA_0_.Q BG_000.Q DSACK_1_.PIN DTACK.PIN -.ob BERR AVEC AVEC_EXP AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN IPL_030_0_.C IPL_030_0_.AP IPL_030_1_.C IPL_030_1_.AP IPL_030_2_.C IPL_030_2_.AP SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.C SM_AMIGA_0_.AR CLK_CNT_0_.C CLK_CNT_1_.C cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C E.C UDS_000.C UDS_000.AP LDS_000.C LDS_000.AP VMA.C VMA.AP BG_000.C BG_000.AP inst_CLK_OUT_PRE.C BGACK_030.C BGACK_030.AP AS_000.C AS_000.AP inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_DTACK_SYNC.C inst_DTACK_SYNC.AP FPU_CS.C FPU_CS.AP DSACK_1_.C DSACK_1_.AP inst_VPA_SYNC.C inst_VPA_SYNC.AP AMIGA_BUS_ENABLE.C inst_CLK_000_D5.C DTACK.C DTACK.AP CLK_EXP.C inst_CLK_000_D4.C inst_CLK_000_D2.C inst_CLK_000_D3.C inst_VPA_D.C inst_CLK_000_D0.C RESET.C inst_CLK_000_D1.C CLK_REF_1_.LH CLK_REF_1_.AR DSACK_0_ DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_DIV_OUT.C CLK_DIV_OUT.D BGACK_030.D FPU_CS.D E.T VMA.T cpu_est_0_.D CLK_EXP.D cpu_est_1_.T AS_000.D inst_AS_030_000_SYNC.D IPL_030_0_.D inst_DTACK_SYNC.D inst_VPA_D.D IPL_030_1_.D inst_VPA_SYNC.D inst_CLK_000_D0.D IPL_030_2_.D inst_CLK_000_D1.D inst_CLK_000_D2.D inst_CLK_000_D5.D inst_CLK_OUT_PRE.D SM_AMIGA_6_.D SM_AMIGA_5_.D cpu_est_2_.D CLK_REF_1_.D UDS_000.D LDS_000.D DSACK_1_.D SM_AMIGA_7_.D inst_CLK_000_D3.D SM_AMIGA_4_.D inst_CLK_000_D4.D RESET.D DTACK.D CLK_CNT_0_.D CLK_CNT_1_.D SM_AMIGA_3_.D SM_AMIGA_1_.D SM_AMIGA_2_.D AMIGA_BUS_ENABLE.D SM_AMIGA_0_.D BG_000.D -.p 311 ---------------------------------------------------------------------------- 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1------------------------0-----------------1--------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------0------------------------------------------------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------1------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ ------------------------------------------0------1------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ -------1-----------------------------------------0------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ -------------------------------------------------------0------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------0-----0------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ ------------------------------------------00-----1--0----------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ -------1-----------------------------------0-----0--0----------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ -------------------------------------------0-----0--0--0-------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ ---------------------------------------------------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ --------------------------------------------------------------10------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ -1----0--------0------------------------------------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ ------0--------00-----------------------------------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ ------0--------0----------------1-------------------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ ------0--------0----------------0-------------------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ --------------------------------------------------------0-------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~ -----0---------0-------------------------------------------0----0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ -----0---------0--------------------------------------------0---0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ -----------------------------------------------------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ -----0-1-----------------------------------0---------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------0---------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ -----0-------------------------------------0-----------0---------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----00-1--1---------------------------------------------------1--0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1-01---------------------------------------------------1--0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1-----------------1---------------------------------1--0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1------------------1--------------------------------1--0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1-------------------0-------------------------------1--0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1--------------------1------------------------------1--0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1------------------------0--------------------------1--0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------------------------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ ------------------------------------------------------0-----------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------------1--------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~00~~~~~~ ------------------------------------------------------0---0--------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------------------------------11-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ ------------------------------------------------------1---1-------01-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------------------0---1--------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------------0--------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ ------------------------------------------------------------------00-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ ------------------------------------------------------1---0-------00-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ --------------------------------------1000----0--1-------1----------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------0------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ----------------------------------------------------------------0---0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ -----------------------------------------------------0-----------1---1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ -----0-1-----------------------------------0-------------------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------0-------------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ -----0-------------------------------------0-----------0-------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----00-1--1---------------------------------------------------1------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1-01---------------------------------------------------1------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1-----------------1---------------------------------1------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1------------------1--------------------------------1------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1-------------------0-------------------------------1------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1--------------------1------------------------------1------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1------------------------0--------------------------1------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------1--1---------------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ --------------------------------------------------------------------0-0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ ---------------------------------------------------------------------00----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ --------------0--------------------------------------------------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ -----0-------------------------------------------------0---------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ -------------------------------------------------1----------------------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ -------------------------------------------------1------------0---------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ -------------------------------------------0-----1--0----------1--------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ -----------------------------------------------------0-----------1------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ ---------------------------------------------------------------------0--0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ --------0-1--------------------------------------------------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 ------------------------------------------0-------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~ ----------------------------------------------1--1------------------1------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +.o 144 +.ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_ IPL_030_0_.Q BGACK_030.Q FPU_CS.Q IPL_030_1_.Q VMA.Q AS_000.Q IPL_030_2_.Q inst_AS_030_000_SYNC.Q inst_DTACK_SYNC.Q inst_VPA_D.Q inst_VPA_SYNC.Q inst_CLK_000_D0.Q inst_CLK_000_D1.Q inst_CLK_000_D2.Q inst_CLK_000_D5.Q SM_AMIGA_5_.Q SM_AMIGA_6_.Q UDS_000.Q LDS_000.Q DSACK_1_.Q inst_CLK_000_D3.Q SM_AMIGA_4_.Q inst_CLK_000_D4.Q SM_AMIGA_7_.Q SM_AMIGA_3_.Q SM_AMIGA_1_.Q AMIGA_BUS_ENABLE.Q CLK_CNT_N_0_.Q CLK_CNT_N_1_.Q CLK_CNT_P_0_.Q CLK_CNT_P_1_.Q SM_AMIGA_2_.Q SM_AMIGA_0_.Q inst_CLK_OUT_PRE.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q E.Q DSACK_1_.PIN DTACK.PIN +.ob BERR AVEC AVEC_EXP AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN cpu_est_2_.C cpu_est_2_.AR E.C E.AR cpu_est_0_.C cpu_est_0_.AR cpu_est_1_.C cpu_est_1_.AR SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.C SM_AMIGA_0_.AR CLK_CNT_N_0_.C CLK_CNT_N_0_.AR CLK_CNT_N_1_.C CLK_CNT_N_1_.AR CLK_CNT_P_0_.C CLK_CNT_P_0_.AR CLK_CNT_P_1_.C CLK_CNT_P_1_.AR IPL_030_0_.C IPL_030_0_.AP IPL_030_1_.C IPL_030_1_.AP IPL_030_2_.C IPL_030_2_.AP SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.C SM_AMIGA_4_.AR UDS_000.C UDS_000.AP LDS_000.C LDS_000.AP inst_VPA_SYNC.C inst_VPA_SYNC.AP VMA.C VMA.AP BGACK_030.C BGACK_030.AP AS_000.C AS_000.AP inst_CLK_OUT_PRE.C inst_CLK_OUT_PRE.AR CLK_EXP.C CLK_EXP.AR inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_DTACK_SYNC.C inst_DTACK_SYNC.AP FPU_CS.C FPU_CS.AP DSACK_1_.C DSACK_1_.AP AMIGA_BUS_ENABLE.C DTACK.C DTACK.AP inst_CLK_000_D5.C inst_CLK_000_D5.AP BG_000.C BG_000.AP inst_CLK_000_D4.C inst_CLK_000_D4.AP inst_CLK_000_D2.C inst_CLK_000_D2.AP inst_CLK_000_D3.C inst_CLK_000_D3.AP inst_VPA_D.C inst_VPA_D.AP inst_CLK_000_D0.C inst_CLK_000_D0.AP RESET.C RESET.AR inst_CLK_000_D1.C inst_CLK_000_D1.AP DSACK_0_ DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_DIV_OUT.AR CLK_DIV_OUT.C CLK_DIV_OUT.D CLK_EXP.D IPL_030_0_.D BGACK_030.D FPU_CS.D IPL_030_1_.D VMA.D AS_000.D IPL_030_2_.D inst_AS_030_000_SYNC.D inst_DTACK_SYNC.D inst_VPA_D.D inst_VPA_SYNC.D inst_CLK_000_D0.D inst_CLK_000_D1.D inst_CLK_000_D2.D inst_CLK_000_D5.D SM_AMIGA_5_.D SM_AMIGA_6_.D UDS_000.D LDS_000.D DSACK_1_.D inst_CLK_000_D3.D SM_AMIGA_4_.D RESET.D inst_CLK_000_D4.D DTACK.D SM_AMIGA_7_.D SM_AMIGA_3_.D SM_AMIGA_1_.D AMIGA_BUS_ENABLE.D CLK_CNT_N_0_.D CLK_CNT_N_1_.D CLK_CNT_P_0_.D CLK_CNT_P_1_.D SM_AMIGA_2_.D SM_AMIGA_0_.D inst_CLK_OUT_PRE.D cpu_est_0_.D cpu_est_1_.T cpu_est_2_.D E.D BG_000.D +.p 313 +--------------------------------------------------------------------------- ~1~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ +----1---------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0---------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +----11--------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~~~~ +------1-------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +-------1------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +----------1---------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1--------------------------------------------------------------- ~~~~~~1~1~1~1~1~1~1~1~~~~~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~11~1~1~1~1~1~1~1~1~1~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------0--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------1-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------0------------------------------------------------------------- ~~~~~~~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~~1~1~1~1~1~1~1~1~1~1~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------0------------------------------------------------------------ ~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-0--------------0000000---------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------1111------------------------------------------------ ~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------1-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~111~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------1---------------------------1-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------0-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---0---------------------------------1------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------0----------------------------1------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------0---------------------------1------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------1---------1------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------1--------1------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------0-------1------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------1------1------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------0--1------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------0------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1----------------------------------1----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------1---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~ +------0-----------------------------------1-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------0--------------------------------1-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1----1------------------0010---1-------1-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1---------------------------------------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------1----1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1---------------------------------------0------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------10------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------1-----1----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------11----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------1---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------1------1---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +----1-----------------------------------------0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------1----------0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-------0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------1----0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------1--0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------10---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~1 +-----------------------------------1-----------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1--------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------1-----1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--1-------------------------------------------10--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------1-------------------------------------10--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------1-------------10--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------1------------10--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~ +----1--------------------------------------------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +-----0--------1----------------1------------------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ +0----0--------11---------------0------------------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------1---1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------0---1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ +----1---------------------------------------------0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1---------1-----------------------------------0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------1---------0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------0--------------------------------------------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------0------1-------------------------------------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +----------------------------------------------1----1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +------0---------------------------------------0----1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~ +----1--------1-------------------------------------0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +-----1----------------------------------------------1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ +--------------1-----------------------------------0-1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ +-----1-----------------------------------------------1--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +--------------1-----------------------------------0--1--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------1----1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~ +-----0--------0----------------1------------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ +0----0--------01---------------0------------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------1---------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +----------------------------------------------0---------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ +----1---------0-----------------------------------------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~~~~ +--------------0-------------------------------------1---0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ +--------------0--------------------------------------1--0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1----------------------------------------------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------------1--0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------1---------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~ +------------------------------------------------1---------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~ +------------------------------------------0-----0------1--1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------------0--1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~ +----------------------------------------------------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +------------------------------------------1---------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------1---------------------------------------0----1------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------1-1-------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +----------------------------------------------1------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +-------------------------------------------0--0------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~ +---------------------------------------------00------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~ +----1------------------------------------------------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------1---------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------1-------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------1-------------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +----------------------------------------------0--1----------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ +-------------------------------------------------0-------1--1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +----------------------------------------------0----------0--1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ +----1-------------------------------------------------------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------------1-----0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +-------------0-----------------------------------------------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +---------------------------------------------------0---------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +--------------------------------------------------------------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~ +--------------------------------------------------------------11----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +--------------------------------------------------------------00----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +----------------------------------------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~ +----------------------------------------------------------------11--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~ +--------------------------------------------------------------0101--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~ +--------------------------------------------------------------1001--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~ +--------------------------------------------------------------0110--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~ +--------------------------------------------------------------1010--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~ +----------------------------------------------------------------00--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~ +----------------------------------------------1-------------------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +----------------------------------------------0-------------------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~ +----------------------------------------0--------------------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ +----------------------------------------1-----1--------------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~ +----------------------------------------------0--------------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ +--------------------------------------------------------------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------0----------------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ +-----------------------------------------------1---------------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ +---------------------------------------1-----------------------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------10---------------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ +----1-----------------------------------------------------------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------1------------------------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------1------------------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------10---------------------00---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +----------------------------------------------0------------------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +-----------------------------------------------1-----------------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +----------------------------------------------------------------------11--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +----------------------------------------------10---------------------1-0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +----------------------------------------------10----------------------00--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +----------------------------------------------0-------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +-----------------------------------------------1------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +----------------------------------------------10---------------------1--1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +----------------------------------------------------------------------0-1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +----------------------------------------------10----------------------011-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ +-----------------------------------------------------------------------01-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +----------------------------------------------10---------------------1-01-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ +----1-------------------------------------------------------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------1--------------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------10---------------------1-10-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ +----------------------------------------1-----1----------------------0110-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------10----------------------000-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ +-------------------------------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~ +----1---------------------------------------------------------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------1------------------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------------------------------- 0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-1------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------0-------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------0------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------0---------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------0--------------------------------------------------------------- ~~~~~~0~0~0~0~0~0~0~0~~~~~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~00~0~0~0~0~0~0~0~0~0~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------0-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1------------------------------------------------------------- ~~~~~~~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~~0~0~0~0~0~0~0~0~0~0~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------1------------------------------------------------------------ ~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------1---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------1--------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------1-------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------1------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------1------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------1----------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------1---------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------0--------------------------------------------------- ~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------0-------------------------------------------------- ~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------0------------------------------------------------- ~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------0------------------------------------------------ ~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---10---11-----------------0010---1---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------1-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------0-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~000~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------1------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0--------------------------------0------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-----------------------------------0---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------00---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0--------------------------------------0------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0----------------------------------------0----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------1---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~0~~~~~~~ +----------------------------------------1-----1---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +----------------------------------------------0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~0~~~~~~~~~~~~~~~~~~~~~0~~~ +-----------------------------------0----------0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------0---------0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0-------0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------0------0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------0----0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------0--0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ +---------------------------------------------00---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ +-----------------------------------------------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ +-----------------------------------0-----------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------0----------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0--------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------0-----1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------0--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--0-------------------------------------------10--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------0-------------10--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------0------------10--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ +----0-1-----------------------------------0------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------0--1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +--------------------------------------------------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +1----0--------1-----------------------------------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ +-----0--------10----------------------------------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ +-----0--------1----------------1------------------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ +-----0--------1----------------0------------------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~ +------1------1-------------------------------------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ +----0-------------------------------------0------1-0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------00----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ +----01----------------------------------------------0---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~ +----0---------1-----------------------------------0-0---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~ +----01-----------------------------------------------0--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ +----0---------1-----------------------------------0--0--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ +----0-------------------------------------------------0-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------0-0---1-0------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ +------1-----------------------------------0---0-0------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ +------------------------------------------0---0-0--0---1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ +-------------------------------------------------------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ +1----0--------0-----------------------------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ +-----0--------00----------------------------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ +-----0--------0----------------1------------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ +-----0--------0----------------0------------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------0-----0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ +----0---------0-------------------------------------0---0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~ +----0---------0--------------------------------------0--0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1-----------------------------------0--------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------0----------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +----0-------------------------------------0--------0-----0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------1---------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~ +----1-00--------------------------------------10----------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 +------------------------------------------------1---------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~ +---00-1--1---------------------------------------1--------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1-01---------------------------------------1--------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1-----------------1---------------------1--------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1------------------1--------------------1--------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1-------------------0-------------------1--------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1--------------------1------------------1--------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1------------------------0--------------1--------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------------0--1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~ +---00-1--1-----------------------------------------------01---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1-01-----------------------------------------------01---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1-----------------1-----------------------------01---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1------------------1----------------------------01---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1-------------------0---------------------------01---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1--------------------1--------------------------01---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1------------------------0----------------------01---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------0---------------------------------------------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------1-----------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------0-----1-----------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ +------1---------------------------------------0-----------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ +---------------------------------------------------0------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------0----0------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ +----------------------------------------------0------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ +--------------------------------------------------------0--0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ +-------------------------------------------------0-------1--1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ +----0-1-----------------------------------0-----------------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------0-------------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +----0-------------------------------------0--------0--------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---00-1--1------------------------------------------------1-0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1-01------------------------------------------------1-0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1-----------------1------------------------------1-0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1------------------1-----------------------------1-0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1-------------------0----------------------------1-0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1--------------------1---------------------------1-0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1------------------------0-----------------------1-0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------0-----------------------------------------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ +----0----------------------------------------------0---------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ +--------------------------------------------------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ +--------------------------------------------------------------11----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +--------------------------------------------------------------01----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~ +--------------------------------------------------------------10----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~ +--------------------------------------------------------------00----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +----------------------------------------------------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~ +----------------------------------------------------------------11--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +----------------------------------------------------------------01--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~ +----------------------------------------------------------------10--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~ +----------------------------------------------------------------00--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +-------------------------------------------1-1--------------------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ +-----------------------------------------------------------0------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ +------------------------------------------------------------0-----0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +----------------------------------------------1--------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +------------------------------------------0---1-0------1-----------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ +-------------------------------------------------0-------1---------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +----------------------------------------------1-----------0--------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ +------------------------------------------------------------0------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +--------------------------------------------------------------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~00~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------0-----------------------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------10---------------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +----------------------------------------------0----------------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +-----------------------------------------------1---------------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +---------------------------------------0------------------------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------0-0----------------------10---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------10----------------------11--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ +---------------------------------------0-------------------------------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------0------------------------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ +-----------------------------------------------1-----------------------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ +---------------------------------------------------------------------010--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ +---------------------------------------0--------------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------0----0-1------------1----------0-1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------------------------------111-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ +---------------------------------------------------------------------0-01-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ +----------------------------------------------0-------------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ +-----------------------------------------------1------------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ +---------------------------------------------------------------------01-0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ +----------------------------------------------10---------------------10-0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ +-----------------------------------------------------------------------10-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ +---------------------------------------------------------------------0-10-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ +---------------------------------------------------------------------1-00-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ +----------------------------------------------------------------------100-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ +----------------------------------------0--------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ +--------------------------------------------1-1------------1--------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ .end diff --git a/Logic/68030_tk.tt3 b/Logic/68030_tk.tt3 index 5fa70f8..a0bd885 100644 --- a/Logic/68030_tk.tt3 +++ b/Logic/68030_tk.tt3 @@ -1,323 +1,325 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Sat May 24 11:44:09 2014 +#$ DATE Sat May 24 15:48:50 2014 #$ MODULE 68030_tk -#$ PINS 59 SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 SIZE_0_ CLK_OSZI A_30_ CLK_DIV_OUT A_29_ A_28_ A_27_ A_26_ AVEC A_25_ AVEC_EXP A_24_ A_23_ VPA A_22_ A_21_ RST A_20_ A_19_ RW A_18_ A_17_ AMIGA_BUS_DATA_DIR A_16_ AMIGA_BUS_ENABLE_LOW CIIN A_0_ IPL_1_ IPL_0_ DSACK_0_ FC_0_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 BG_000 BGACK_030 CLK_EXP FPU_CS DTACK E VMA RESET AMIGA_BUS_ENABLE IPL_030_1_ IPL_030_0_ -#$ NODES 25 cpu_est_0_ cpu_est_1_ inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2 inst_CLK_000_D5 inst_CLK_OUT_PRE SM_AMIGA_6_ SM_AMIGA_5_ cpu_est_2_ CLK_REF_1_ SM_AMIGA_7_ inst_CLK_000_D3 SM_AMIGA_4_ inst_CLK_000_D4 CLK_CNT_0_ CLK_CNT_1_ SM_AMIGA_3_ SM_AMIGA_1_ SM_AMIGA_2_ SM_AMIGA_0_ +#$ PINS 59 SIZE_1_ A_31_ SIZE_0_ IPL_2_ A_30_ A_29_ A_28_ A_27_ FC_1_ A_26_ AS_030 A_25_ A_24_ DS_030 A_23_ A_22_ A_21_ nEXP_SPACE A_20_ BERR A_19_ BG_030 A_18_ A_17_ A_16_ BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT AVEC AVEC_EXP VPA RST RW A_0_ AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW IPL_1_ CIIN IPL_0_ DSACK_0_ FC_0_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 BG_000 BGACK_030 CLK_EXP FPU_CS DTACK E VMA RESET AMIGA_BUS_ENABLE IPL_030_1_ IPL_030_0_ +#$ NODES 26 inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2 inst_CLK_000_D5 SM_AMIGA_5_ SM_AMIGA_6_ inst_CLK_000_D3 SM_AMIGA_4_ inst_CLK_000_D4 SM_AMIGA_7_ SM_AMIGA_3_ SM_AMIGA_1_ CLK_CNT_N_0_ CLK_CNT_N_1_ CLK_CNT_P_0_ CLK_CNT_P_1_ SM_AMIGA_2_ SM_AMIGA_0_ inst_CLK_OUT_PRE cpu_est_0_ cpu_est_1_ cpu_est_2_ .type fr .i 75 -.o 124 -.ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q FPU_CS.Q E.Q VMA.Q cpu_est_0_.Q cpu_est_1_.Q AS_000.Q inst_AS_030_000_SYNC.Q IPL_030_0_.Q inst_DTACK_SYNC.Q inst_VPA_D.Q IPL_030_1_.Q inst_VPA_SYNC.Q inst_CLK_000_D0.Q IPL_030_2_.Q inst_CLK_000_D1.Q inst_CLK_000_D2.Q inst_CLK_000_D5.Q inst_CLK_OUT_PRE.Q SM_AMIGA_6_.Q SM_AMIGA_5_.Q cpu_est_2_.Q CLK_REF_1_.Q UDS_000.Q LDS_000.Q DSACK_1_.Q SM_AMIGA_7_.Q inst_CLK_000_D3.Q SM_AMIGA_4_.Q inst_CLK_000_D4.Q CLK_CNT_0_.Q CLK_CNT_1_.Q SM_AMIGA_3_.Q SM_AMIGA_1_.Q SM_AMIGA_2_.Q AMIGA_BUS_ENABLE.Q SM_AMIGA_0_.Q BG_000.Q DSACK_1_.PIN DTACK.PIN -.ob BERR AVEC AVEC_EXP AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN IPL_030_0_.C IPL_030_0_.AP IPL_030_1_.C IPL_030_1_.AP IPL_030_2_.C IPL_030_2_.AP SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.C SM_AMIGA_0_.AR CLK_CNT_0_.C CLK_CNT_1_.C cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C E.C UDS_000.C UDS_000.AP LDS_000.C LDS_000.AP VMA.C VMA.AP BG_000.C BG_000.AP inst_CLK_OUT_PRE.C BGACK_030.C BGACK_030.AP AS_000.C AS_000.AP inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_DTACK_SYNC.C inst_DTACK_SYNC.AP FPU_CS.C FPU_CS.AP DSACK_1_.C DSACK_1_.AP inst_VPA_SYNC.C inst_VPA_SYNC.AP AMIGA_BUS_ENABLE.C inst_CLK_000_D5.C DTACK.C DTACK.AP CLK_EXP.C inst_CLK_000_D4.C inst_CLK_000_D2.C inst_CLK_000_D3.C inst_VPA_D.C inst_CLK_000_D0.C RESET.C inst_CLK_000_D1.C CLK_REF_1_.LH CLK_REF_1_.AR DSACK_0_ DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_DIV_OUT.C CLK_DIV_OUT.D BGACK_030.D FPU_CS.D E.T VMA.T cpu_est_0_.D CLK_EXP.D cpu_est_1_.T AS_000.D inst_AS_030_000_SYNC.D IPL_030_0_.D inst_DTACK_SYNC.D inst_VPA_D.D IPL_030_1_.D inst_VPA_SYNC.D inst_CLK_000_D0.D IPL_030_2_.D inst_CLK_000_D1.D inst_CLK_000_D2.D inst_CLK_000_D5.D inst_CLK_OUT_PRE.D SM_AMIGA_6_.D SM_AMIGA_5_.D cpu_est_2_.D CLK_REF_1_.D UDS_000.D LDS_000.D DSACK_1_.D SM_AMIGA_7_.D inst_CLK_000_D3.D SM_AMIGA_4_.D inst_CLK_000_D4.D RESET.D DTACK.D CLK_CNT_0_.D CLK_CNT_1_.D SM_AMIGA_3_.D SM_AMIGA_1_.D SM_AMIGA_2_.D AMIGA_BUS_ENABLE.D SM_AMIGA_0_.D BG_000.D -.p 311 ---------------------------------------------------------------------------- ~1~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----1---------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----11--------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~ -------1-------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------1------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 -----0----0----------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 -------1--0----------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 -----------1---------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~ 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------01---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------10---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------1-10---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------00---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0------------------------------------0--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0---------------------------------------0------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0------------------------------------------0--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~0~~~ ---------------------------------------1---------1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------1------1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ ------------------------------------------0------1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~0~~~~~~~~~0~~~~0~~~~~~~~~~~~~~~~~~~ ------------------------------------0------------0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------0--------0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------1-------0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------0----0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------0---0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ----------------------------------------------1--0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------0-0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------------00-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ -------------------------------------------------00------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------0--------------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------0----------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------0------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------0---1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------------01------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~ ---0---------------------------------------------1-0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------0---------------1-0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------0--------------1-0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------1--------1-0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------0-10-------1-0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ ----------------------------------------------------0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ -----0-1-----------------------------------0---------1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------0---1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ ------------------------------------------------------0--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------1------1----------------------------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ -----0-------------------------------------0---------1-0-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -1----0--------1----------------------------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ ------0--------10---------------------------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ ------0--------1----------------1-----------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ ------0--------1----------------0-----------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ -------------------------------------------------------00------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ --------------------------------------0------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------0----------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------0-0----------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------1--1---------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------1------------------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------0--1---------------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ ----------------------------------------01---------------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ -------------------------------------------------0-------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ ---------------------------------------------------1-----0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ -----01----------------------------------------------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ -----0---------1----------------------------------------0--0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ -----01-----------------------------------------------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ -----0---------1----------------------------------------0---0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ -----0-------------------------------------------------------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ -----1-00-0---------------------------------------------------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 -------------------------------------------1------------------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------1---------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ ----00-1--1------------------------------------------1--------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1-01------------------------------------------1--------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1-----------------1------------------------1--------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1------------------1-----------------------1--------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1-------------------0----------------------1--------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1--------------------1---------------------1--------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1------------------------0-----------------1--------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------0------------------------------------------------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------1------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ ------------------------------------------0------1------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ -------1-----------------------------------------0------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ -------------------------------------------------------0------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------0-----0------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ ------------------------------------------00-----1--0----------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ -------1-----------------------------------0-----0--0----------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ -------------------------------------------0-----0--0--0-------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ ---------------------------------------------------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ --------------------------------------------------------------10------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ -1----0--------0------------------------------------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ ------0--------00-----------------------------------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ ------0--------0----------------1-------------------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ ------0--------0----------------0-------------------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ --------------------------------------------------------0-------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~ -----0---------0-------------------------------------------0----0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ -----0---------0--------------------------------------------0---0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ -----------------------------------------------------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ -----0-1-----------------------------------0---------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------0---------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ -----0-------------------------------------0-----------0---------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----00-1--1---------------------------------------------------1--0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1-01---------------------------------------------------1--0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1-----------------1---------------------------------1--0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1------------------1--------------------------------1--0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1-------------------0-------------------------------1--0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1--------------------1------------------------------1--0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1------------------------0--------------------------1--0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------------------------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ ------------------------------------------------------0-----------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------------1--------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~00~~~~~~ ------------------------------------------------------0---0--------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------------------------------11-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ ------------------------------------------------------1---1-------01-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------------------0---1--------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------------0--------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ ------------------------------------------------------------------00-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ ------------------------------------------------------1---0-------00-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ --------------------------------------1000----0--1-------1----------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------0------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ----------------------------------------------------------------0---0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ -----------------------------------------------------0-----------1---1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ -----0-1-----------------------------------0-------------------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------0-------------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ -----0-------------------------------------0-----------0-------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----00-1--1---------------------------------------------------1------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1-01---------------------------------------------------1------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1-----------------1---------------------------------1------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1------------------1--------------------------------1------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1-------------------0-------------------------------1------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1--------------------1------------------------------1------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1------------------------0--------------------------1------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------1--1---------------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ --------------------------------------------------------------------0-0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ ---------------------------------------------------------------------00----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ --------------0--------------------------------------------------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ -----0-------------------------------------------------0---------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ -------------------------------------------------1----------------------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ -------------------------------------------------1------------0---------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ -------------------------------------------0-----1--0----------1--------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ -----------------------------------------------------0-----------1------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ ---------------------------------------------------------------------0--0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ --------0-1--------------------------------------------------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 ------------------------------------------0-------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~ ----------------------------------------------1--1------------------1------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +.o 144 +.ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_ IPL_030_0_.Q BGACK_030.Q FPU_CS.Q IPL_030_1_.Q VMA.Q AS_000.Q IPL_030_2_.Q inst_AS_030_000_SYNC.Q inst_DTACK_SYNC.Q inst_VPA_D.Q inst_VPA_SYNC.Q inst_CLK_000_D0.Q inst_CLK_000_D1.Q inst_CLK_000_D2.Q inst_CLK_000_D5.Q SM_AMIGA_5_.Q SM_AMIGA_6_.Q UDS_000.Q LDS_000.Q DSACK_1_.Q inst_CLK_000_D3.Q SM_AMIGA_4_.Q inst_CLK_000_D4.Q SM_AMIGA_7_.Q SM_AMIGA_3_.Q SM_AMIGA_1_.Q AMIGA_BUS_ENABLE.Q CLK_CNT_N_0_.Q CLK_CNT_N_1_.Q CLK_CNT_P_0_.Q CLK_CNT_P_1_.Q SM_AMIGA_2_.Q SM_AMIGA_0_.Q inst_CLK_OUT_PRE.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q E.Q DSACK_1_.PIN DTACK.PIN +.ob BERR AVEC AVEC_EXP AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN cpu_est_2_.C cpu_est_2_.AR E.C E.AR cpu_est_0_.C cpu_est_0_.AR cpu_est_1_.C cpu_est_1_.AR SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.C SM_AMIGA_0_.AR CLK_CNT_N_0_.C CLK_CNT_N_0_.AR CLK_CNT_N_1_.C CLK_CNT_N_1_.AR CLK_CNT_P_0_.C CLK_CNT_P_0_.AR CLK_CNT_P_1_.C CLK_CNT_P_1_.AR IPL_030_0_.C IPL_030_0_.AP IPL_030_1_.C IPL_030_1_.AP IPL_030_2_.C IPL_030_2_.AP SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.C SM_AMIGA_4_.AR UDS_000.C UDS_000.AP LDS_000.C LDS_000.AP inst_VPA_SYNC.C inst_VPA_SYNC.AP VMA.C VMA.AP BGACK_030.C BGACK_030.AP AS_000.C AS_000.AP inst_CLK_OUT_PRE.C inst_CLK_OUT_PRE.AR CLK_EXP.C CLK_EXP.AR inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_DTACK_SYNC.C inst_DTACK_SYNC.AP FPU_CS.C FPU_CS.AP DSACK_1_.C DSACK_1_.AP AMIGA_BUS_ENABLE.C DTACK.C DTACK.AP inst_CLK_000_D5.C inst_CLK_000_D5.AP BG_000.C BG_000.AP inst_CLK_000_D4.C inst_CLK_000_D4.AP inst_CLK_000_D2.C inst_CLK_000_D2.AP inst_CLK_000_D3.C inst_CLK_000_D3.AP inst_VPA_D.C inst_VPA_D.AP inst_CLK_000_D0.C inst_CLK_000_D0.AP RESET.C RESET.AR inst_CLK_000_D1.C inst_CLK_000_D1.AP DSACK_0_ DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_DIV_OUT.AR CLK_DIV_OUT.C CLK_DIV_OUT.D CLK_EXP.D IPL_030_0_.D BGACK_030.D FPU_CS.D IPL_030_1_.D VMA.D AS_000.D IPL_030_2_.D inst_AS_030_000_SYNC.D inst_DTACK_SYNC.D inst_VPA_D.D inst_VPA_SYNC.D inst_CLK_000_D0.D inst_CLK_000_D1.D inst_CLK_000_D2.D inst_CLK_000_D5.D SM_AMIGA_5_.D SM_AMIGA_6_.D UDS_000.D LDS_000.D DSACK_1_.D inst_CLK_000_D3.D SM_AMIGA_4_.D RESET.D inst_CLK_000_D4.D DTACK.D SM_AMIGA_7_.D SM_AMIGA_3_.D SM_AMIGA_1_.D AMIGA_BUS_ENABLE.D CLK_CNT_N_0_.D CLK_CNT_N_1_.D CLK_CNT_P_0_.D CLK_CNT_P_1_.D SM_AMIGA_2_.D SM_AMIGA_0_.D inst_CLK_OUT_PRE.D cpu_est_0_.D cpu_est_1_.T cpu_est_2_.D E.D BG_000.D +.p 313 +--------------------------------------------------------------------------- ~1~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ +----1---------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0---------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +----11--------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~~~~ +------1-------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +-------1------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +----------1---------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1--------------------------------------------------------------- ~~~~~~1~1~1~1~1~1~1~1~~~~~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~11~1~1~1~1~1~1~1~1~1~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------0--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------1-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------0------------------------------------------------------------- ~~~~~~~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~~1~1~1~1~1~1~1~1~1~1~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------0------------------------------------------------------------ ~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-0--------------0000000---------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------1111------------------------------------------------ ~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------1-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~111~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------1---------------------------1-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------0-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---0---------------------------------1------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------0----------------------------1------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------0---------------------------1------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------1---------1------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------1--------1------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------0-------1------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------1------1------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------0--1------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------0------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1----------------------------------1----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------1---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~ +------0-----------------------------------1-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------0--------------------------------1-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1----1------------------0010---1-------1-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1---------------------------------------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------1----1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1---------------------------------------0------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------10------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------1-----1----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------11----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------1---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------1------1---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +----1-----------------------------------------0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------1----------0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-------0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------1----0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------1--0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------10---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~1 +-----------------------------------1-----------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1--------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------1-----1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--1-------------------------------------------10--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------1-------------------------------------10--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------1-------------10--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------1------------10--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~ +----1--------------------------------------------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +-----0--------1----------------1------------------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ +0----0--------11---------------0------------------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------1---1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------0---1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ +----1---------------------------------------------0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1---------1-----------------------------------0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------1---------0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------0--------------------------------------------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------0------1-------------------------------------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +----------------------------------------------1----1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +------0---------------------------------------0----1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~ +----1--------1-------------------------------------0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +-----1----------------------------------------------1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ +--------------1-----------------------------------0-1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ +-----1-----------------------------------------------1--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +--------------1-----------------------------------0--1--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------1----1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~ +-----0--------0----------------1------------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ +0----0--------01---------------0------------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------1---------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +----------------------------------------------0---------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ +----1---------0-----------------------------------------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~~~~ +--------------0-------------------------------------1---0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ +--------------0--------------------------------------1--0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1----------------------------------------------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------------1--0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------1---------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~ +------------------------------------------------1---------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~ +------------------------------------------0-----0------1--1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------------0--1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~ +----------------------------------------------------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +------------------------------------------1---------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------1---------------------------------------0----1------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------1-1-------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +----------------------------------------------1------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +-------------------------------------------0--0------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~ +---------------------------------------------00------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~ +----1------------------------------------------------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------1---------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------1-------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------1-------------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +----------------------------------------------0--1----------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ +-------------------------------------------------0-------1--1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +----------------------------------------------0----------0--1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ +----1-------------------------------------------------------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------------1-----0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +-------------0-----------------------------------------------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +---------------------------------------------------0---------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +--------------------------------------------------------------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~ +--------------------------------------------------------------11----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +--------------------------------------------------------------00----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +----------------------------------------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~ +----------------------------------------------------------------11--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~ +--------------------------------------------------------------0101--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~ +--------------------------------------------------------------1001--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~ +--------------------------------------------------------------0110--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~ +--------------------------------------------------------------1010--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~ +----------------------------------------------------------------00--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~ +----------------------------------------------1-------------------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +----------------------------------------------0-------------------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~ +----------------------------------------0--------------------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ +----------------------------------------1-----1--------------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~ +----------------------------------------------0--------------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ +--------------------------------------------------------------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------0----------------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ +-----------------------------------------------1---------------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ +---------------------------------------1-----------------------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------10---------------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ +----1-----------------------------------------------------------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------1------------------------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------1------------------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------10---------------------00---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +----------------------------------------------0------------------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +-----------------------------------------------1-----------------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +----------------------------------------------------------------------11--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +----------------------------------------------10---------------------1-0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +----------------------------------------------10----------------------00--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +----------------------------------------------0-------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +-----------------------------------------------1------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +----------------------------------------------10---------------------1--1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +----------------------------------------------------------------------0-1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +----------------------------------------------10----------------------011-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ +-----------------------------------------------------------------------01-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +----------------------------------------------10---------------------1-01-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ +----1-------------------------------------------------------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------1--------------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------10---------------------1-10-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ +----------------------------------------1-----1----------------------0110-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------10----------------------000-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ +-------------------------------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~ +----1---------------------------------------------------------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------1------------------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------------------------------- 0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-1------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------0-------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------0------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------0---------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------0--------------------------------------------------------------- ~~~~~~0~0~0~0~0~0~0~0~~~~~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~00~0~0~0~0~0~0~0~0~0~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------0-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1------------------------------------------------------------- ~~~~~~~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~~0~0~0~0~0~0~0~0~0~0~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------1------------------------------------------------------------ ~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------1---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------1--------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------1-------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------1------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------1------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------1----------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------1---------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------0--------------------------------------------------- ~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------0-------------------------------------------------- ~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------0------------------------------------------------- ~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------0------------------------------------------------ ~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---10---11-----------------0010---1---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------1-------------------------------------- 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ +---------------------------------------------------------------------1-00-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ +----------------------------------------------------------------------100-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ +----------------------------------------0--------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ +--------------------------------------------1-1------------1--------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ .end diff --git a/Logic/68030_tk.tt4 b/Logic/68030_tk.tt4 index f3204d7..cb94159 100644 --- a/Logic/68030_tk.tt4 +++ b/Logic/68030_tk.tt4 @@ -1,165 +1,172 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Sat May 24 11:44:09 2014 +#$ DATE Sat May 24 15:48:50 2014 #$ MODULE BUS68030 -#$ PINS 59 SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 nEXP_SPACE BERR BG_030 - BGACK_000 CLK_030 CLK_000 SIZE_0_ CLK_OSZI A_30_ CLK_DIV_OUT A_29_ A_28_ A_27_ - A_26_ AVEC A_25_ AVEC_EXP A_24_ A_23_ VPA A_22_ A_21_ RST A_20_ A_19_ RW A_18_ - A_17_ AMIGA_BUS_DATA_DIR A_16_ AMIGA_BUS_ENABLE_LOW CIIN A_0_ IPL_1_ IPL_0_ +#$ PINS 59 SIZE_1_ A_31_ SIZE_0_ IPL_2_ A_30_ A_29_ A_28_ A_27_ FC_1_ A_26_ + AS_030 A_25_ A_24_ DS_030 A_23_ A_22_ A_21_ nEXP_SPACE A_20_ BERR A_19_ BG_030 + A_18_ A_17_ A_16_ BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT AVEC AVEC_EXP + VPA RST RW A_0_ AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW IPL_1_ CIIN IPL_0_ DSACK_0_ FC_0_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 BG_000 BGACK_030 CLK_EXP FPU_CS DTACK E VMA RESET AMIGA_BUS_ENABLE IPL_030_1_ IPL_030_0_ -#$ NODES 25 cpu_est_0_ cpu_est_1_ inst_AS_030_000_SYNC inst_DTACK_SYNC - inst_VPA_D inst_VPA_SYNC inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2 - inst_CLK_000_D5 inst_CLK_OUT_PRE SM_AMIGA_6_ SM_AMIGA_5_ cpu_est_2_ CLK_REF_1_ - SM_AMIGA_7_ inst_CLK_000_D3 SM_AMIGA_4_ inst_CLK_000_D4 CLK_CNT_0_ CLK_CNT_1_ - SM_AMIGA_3_ SM_AMIGA_1_ SM_AMIGA_2_ SM_AMIGA_0_ +#$ NODES 26 inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC + inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2 inst_CLK_000_D5 SM_AMIGA_5_ + SM_AMIGA_6_ inst_CLK_000_D3 SM_AMIGA_4_ inst_CLK_000_D4 SM_AMIGA_7_ SM_AMIGA_3_ + SM_AMIGA_1_ CLK_CNT_N_0_ CLK_CNT_N_1_ CLK_CNT_P_0_ CLK_CNT_P_1_ SM_AMIGA_2_ + SM_AMIGA_0_ inst_CLK_OUT_PRE cpu_est_0_ cpu_est_1_ cpu_est_2_ .type f .i 75 -.o 126 +.o 147 .ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_ - BGACK_030.Q FPU_CS.Q E.Q VMA.Q cpu_est_0_.Q cpu_est_1_.Q AS_000.Q - inst_AS_030_000_SYNC.Q IPL_030_0_.Q inst_DTACK_SYNC.Q inst_VPA_D.Q IPL_030_1_.Q - inst_VPA_SYNC.Q inst_CLK_000_D0.Q IPL_030_2_.Q inst_CLK_000_D1.Q - inst_CLK_000_D2.Q inst_CLK_000_D5.Q inst_CLK_OUT_PRE.Q SM_AMIGA_6_.Q - SM_AMIGA_5_.Q cpu_est_2_.Q CLK_REF_1_.Q UDS_000.Q LDS_000.Q DSACK_1_.Q - SM_AMIGA_7_.Q inst_CLK_000_D3.Q SM_AMIGA_4_.Q inst_CLK_000_D4.Q CLK_CNT_0_.Q - CLK_CNT_1_.Q SM_AMIGA_3_.Q SM_AMIGA_1_.Q SM_AMIGA_2_.Q AMIGA_BUS_ENABLE.Q - SM_AMIGA_0_.Q BG_000.Q DSACK_1_.PIN DTACK.PIN -.ob BERR BERR.OE CLK_DIV_OUT.D CLK_DIV_OUT.C AVEC AVEC_EXP AVEC_EXP.OE - AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN CIIN.OE DSACK_0_ DSACK_0_.OE - IPL_030_2_.D IPL_030_2_.C IPL_030_2_.AP DSACK_1_.D% DSACK_1_.C DSACK_1_.AP - DSACK_1_.OE AS_000.D AS_000.C AS_000.AP AS_000.OE UDS_000.D% UDS_000.C - UDS_000.AP UDS_000.OE LDS_000.D LDS_000.C LDS_000.AP LDS_000.OE BG_000.D% - BG_000.C BG_000.AP BGACK_030.D BGACK_030.C BGACK_030.AP CLK_EXP.D CLK_EXP.C - FPU_CS.D% FPU_CS.C FPU_CS.AP DTACK.D% DTACK.C DTACK.AP DTACK.OE E.T E.C VMA.T - VMA.C VMA.AP RESET.D RESET.C AMIGA_BUS_ENABLE.D% AMIGA_BUS_ENABLE.C IPL_030_1_.D - IPL_030_1_.C IPL_030_1_.AP IPL_030_0_.D IPL_030_0_.C IPL_030_0_.AP cpu_est_0_.D - cpu_est_0_.C cpu_est_1_.T cpu_est_1_.C inst_AS_030_000_SYNC.D + IPL_030_0_.Q BGACK_030.Q FPU_CS.Q IPL_030_1_.Q VMA.Q AS_000.Q IPL_030_2_.Q + inst_AS_030_000_SYNC.Q inst_DTACK_SYNC.Q inst_VPA_D.Q inst_VPA_SYNC.Q + inst_CLK_000_D0.Q inst_CLK_000_D1.Q inst_CLK_000_D2.Q inst_CLK_000_D5.Q + SM_AMIGA_5_.Q SM_AMIGA_6_.Q UDS_000.Q LDS_000.Q DSACK_1_.Q inst_CLK_000_D3.Q + SM_AMIGA_4_.Q inst_CLK_000_D4.Q SM_AMIGA_7_.Q SM_AMIGA_3_.Q SM_AMIGA_1_.Q + AMIGA_BUS_ENABLE.Q CLK_CNT_N_0_.Q CLK_CNT_N_1_.Q CLK_CNT_P_0_.Q CLK_CNT_P_1_.Q + SM_AMIGA_2_.Q SM_AMIGA_0_.Q inst_CLK_OUT_PRE.Q cpu_est_0_.Q cpu_est_1_.Q + cpu_est_2_.Q E.Q DSACK_1_.PIN DTACK.PIN +.ob BERR BERR.OE CLK_DIV_OUT.D CLK_DIV_OUT.C CLK_DIV_OUT.AR AVEC AVEC_EXP + AVEC_EXP.OE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN CIIN.OE DSACK_0_ + DSACK_0_.OE IPL_030_2_.D IPL_030_2_.C IPL_030_2_.AP DSACK_1_.D% DSACK_1_.C + DSACK_1_.AP DSACK_1_.OE AS_000.D AS_000.C AS_000.AP AS_000.OE UDS_000.D% + UDS_000.C UDS_000.AP UDS_000.OE LDS_000.D LDS_000.C LDS_000.AP LDS_000.OE + BG_000.D% BG_000.C BG_000.AP BGACK_030.D BGACK_030.C BGACK_030.AP CLK_EXP.D + CLK_EXP.C CLK_EXP.AR FPU_CS.D% FPU_CS.C FPU_CS.AP DTACK.D% DTACK.C DTACK.AP + DTACK.OE E.D.X1 E.D.X2 E.C E.AR VMA.D.X1 VMA.D.X2 VMA.C VMA.AP RESET.D RESET.C + RESET.AR AMIGA_BUS_ENABLE.D% AMIGA_BUS_ENABLE.C IPL_030_1_.D IPL_030_1_.C + IPL_030_1_.AP IPL_030_0_.D IPL_030_0_.C IPL_030_0_.AP inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_DTACK_SYNC.D% - inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_VPA_D.D inst_VPA_D.C inst_VPA_SYNC.D% - inst_VPA_SYNC.C inst_VPA_SYNC.AP inst_CLK_000_D0.D inst_CLK_000_D0.C - inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_D2.D inst_CLK_000_D2.C - inst_CLK_000_D5.D inst_CLK_000_D5.C inst_CLK_OUT_PRE.D.X1 inst_CLK_OUT_PRE.D.X2 - inst_CLK_OUT_PRE.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.D - SM_AMIGA_5_.C SM_AMIGA_5_.AR cpu_est_2_.D.X1 cpu_est_2_.D.X2 cpu_est_2_.C - CLK_REF_1_.D CLK_REF_1_.LH CLK_REF_1_.AR SM_AMIGA_7_.D SM_AMIGA_7_.C - SM_AMIGA_7_.AP inst_CLK_000_D3.D inst_CLK_000_D3.C SM_AMIGA_4_.D SM_AMIGA_4_.C - SM_AMIGA_4_.AR inst_CLK_000_D4.D inst_CLK_000_D4.C CLK_CNT_0_.D CLK_CNT_0_.C - CLK_CNT_1_.D CLK_CNT_1_.C SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR - SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C - SM_AMIGA_2_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR -.phase 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000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000 +-----------------------------------------------------------------------1--- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 .end diff --git a/Logic/68030_tk.tte b/Logic/68030_tk.tte index 999debc..903d435 100644 --- a/Logic/68030_tk.tte +++ b/Logic/68030_tk.tte @@ -1,165 +1,172 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Sat May 24 11:44:09 2014 +#$ DATE Sat May 24 15:48:50 2014 #$ MODULE BUS68030 -#$ PINS 59 SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 nEXP_SPACE BERR BG_030 - BGACK_000 CLK_030 CLK_000 SIZE_0_ CLK_OSZI A_30_ CLK_DIV_OUT A_29_ A_28_ A_27_ - A_26_ AVEC A_25_ AVEC_EXP A_24_ A_23_ VPA A_22_ A_21_ RST A_20_ A_19_ RW A_18_ - A_17_ AMIGA_BUS_DATA_DIR A_16_ AMIGA_BUS_ENABLE_LOW CIIN A_0_ IPL_1_ IPL_0_ +#$ PINS 59 SIZE_1_ A_31_ SIZE_0_ IPL_2_ A_30_ A_29_ A_28_ A_27_ FC_1_ A_26_ + AS_030 A_25_ A_24_ DS_030 A_23_ A_22_ A_21_ nEXP_SPACE A_20_ BERR A_19_ BG_030 + A_18_ A_17_ A_16_ BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT AVEC AVEC_EXP + VPA RST RW A_0_ AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW IPL_1_ CIIN IPL_0_ DSACK_0_ FC_0_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 BG_000 BGACK_030 CLK_EXP FPU_CS DTACK E VMA RESET AMIGA_BUS_ENABLE IPL_030_1_ IPL_030_0_ -#$ NODES 25 cpu_est_0_ cpu_est_1_ inst_AS_030_000_SYNC inst_DTACK_SYNC - inst_VPA_D inst_VPA_SYNC inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2 - inst_CLK_000_D5 inst_CLK_OUT_PRE SM_AMIGA_6_ SM_AMIGA_5_ cpu_est_2_ CLK_REF_1_ - SM_AMIGA_7_ inst_CLK_000_D3 SM_AMIGA_4_ inst_CLK_000_D4 CLK_CNT_0_ CLK_CNT_1_ - SM_AMIGA_3_ SM_AMIGA_1_ SM_AMIGA_2_ SM_AMIGA_0_ +#$ NODES 26 inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC + inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2 inst_CLK_000_D5 SM_AMIGA_5_ + SM_AMIGA_6_ inst_CLK_000_D3 SM_AMIGA_4_ inst_CLK_000_D4 SM_AMIGA_7_ SM_AMIGA_3_ + SM_AMIGA_1_ CLK_CNT_N_0_ CLK_CNT_N_1_ CLK_CNT_P_0_ CLK_CNT_P_1_ SM_AMIGA_2_ + SM_AMIGA_0_ inst_CLK_OUT_PRE cpu_est_0_ cpu_est_1_ cpu_est_2_ .type f .i 75 -.o 126 +.o 147 .ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_ - BGACK_030.Q FPU_CS.Q E.Q VMA.Q cpu_est_0_.Q cpu_est_1_.Q AS_000.Q - inst_AS_030_000_SYNC.Q IPL_030_0_.Q inst_DTACK_SYNC.Q inst_VPA_D.Q IPL_030_1_.Q - inst_VPA_SYNC.Q inst_CLK_000_D0.Q IPL_030_2_.Q inst_CLK_000_D1.Q - inst_CLK_000_D2.Q inst_CLK_000_D5.Q inst_CLK_OUT_PRE.Q SM_AMIGA_6_.Q - SM_AMIGA_5_.Q cpu_est_2_.Q CLK_REF_1_.Q UDS_000.Q LDS_000.Q DSACK_1_.Q - SM_AMIGA_7_.Q inst_CLK_000_D3.Q SM_AMIGA_4_.Q inst_CLK_000_D4.Q CLK_CNT_0_.Q - CLK_CNT_1_.Q SM_AMIGA_3_.Q SM_AMIGA_1_.Q SM_AMIGA_2_.Q AMIGA_BUS_ENABLE.Q - SM_AMIGA_0_.Q BG_000.Q DSACK_1_.PIN DTACK.PIN -.ob BERR BERR.OE CLK_DIV_OUT.D CLK_DIV_OUT.C AVEC AVEC_EXP AVEC_EXP.OE - AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN CIIN.OE DSACK_0_ DSACK_0_.OE - IPL_030_2_.D IPL_030_2_.C IPL_030_2_.AP DSACK_1_.D- DSACK_1_.C DSACK_1_.AP - DSACK_1_.OE AS_000.D AS_000.C AS_000.AP AS_000.OE UDS_000.D- UDS_000.C - UDS_000.AP UDS_000.OE LDS_000.D LDS_000.C LDS_000.AP LDS_000.OE BG_000.D- - BG_000.C BG_000.AP BGACK_030.D BGACK_030.C BGACK_030.AP CLK_EXP.D CLK_EXP.C - FPU_CS.D- FPU_CS.C FPU_CS.AP DTACK.D- DTACK.C DTACK.AP DTACK.OE E.T E.C VMA.T - VMA.C VMA.AP RESET.D RESET.C AMIGA_BUS_ENABLE.D- AMIGA_BUS_ENABLE.C IPL_030_1_.D - IPL_030_1_.C IPL_030_1_.AP IPL_030_0_.D IPL_030_0_.C IPL_030_0_.AP cpu_est_0_.D - cpu_est_0_.C cpu_est_1_.T cpu_est_1_.C inst_AS_030_000_SYNC.D + IPL_030_0_.Q BGACK_030.Q FPU_CS.Q IPL_030_1_.Q VMA.Q AS_000.Q IPL_030_2_.Q + inst_AS_030_000_SYNC.Q inst_DTACK_SYNC.Q inst_VPA_D.Q inst_VPA_SYNC.Q + inst_CLK_000_D0.Q inst_CLK_000_D1.Q inst_CLK_000_D2.Q inst_CLK_000_D5.Q + SM_AMIGA_5_.Q SM_AMIGA_6_.Q UDS_000.Q LDS_000.Q DSACK_1_.Q inst_CLK_000_D3.Q + SM_AMIGA_4_.Q inst_CLK_000_D4.Q SM_AMIGA_7_.Q SM_AMIGA_3_.Q SM_AMIGA_1_.Q + AMIGA_BUS_ENABLE.Q CLK_CNT_N_0_.Q CLK_CNT_N_1_.Q CLK_CNT_P_0_.Q CLK_CNT_P_1_.Q + SM_AMIGA_2_.Q SM_AMIGA_0_.Q inst_CLK_OUT_PRE.Q cpu_est_0_.Q cpu_est_1_.Q + cpu_est_2_.Q E.Q DSACK_1_.PIN DTACK.PIN +.ob BERR BERR.OE CLK_DIV_OUT.D CLK_DIV_OUT.C CLK_DIV_OUT.AR AVEC AVEC_EXP + AVEC_EXP.OE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN CIIN.OE DSACK_0_ + DSACK_0_.OE IPL_030_2_.D IPL_030_2_.C IPL_030_2_.AP DSACK_1_.D- DSACK_1_.C + DSACK_1_.AP DSACK_1_.OE AS_000.D AS_000.C AS_000.AP AS_000.OE UDS_000.D- + UDS_000.C UDS_000.AP UDS_000.OE LDS_000.D LDS_000.C LDS_000.AP LDS_000.OE + BG_000.D- BG_000.C BG_000.AP BGACK_030.D BGACK_030.C BGACK_030.AP CLK_EXP.D + CLK_EXP.C CLK_EXP.AR FPU_CS.D- FPU_CS.C FPU_CS.AP DTACK.D- DTACK.C DTACK.AP + DTACK.OE E.D.X1 E.D.X2 E.C E.AR VMA.D.X1 VMA.D.X2 VMA.C VMA.AP RESET.D RESET.C + RESET.AR AMIGA_BUS_ENABLE.D- AMIGA_BUS_ENABLE.C IPL_030_1_.D IPL_030_1_.C + IPL_030_1_.AP IPL_030_0_.D IPL_030_0_.C IPL_030_0_.AP inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_DTACK_SYNC.D- - inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_VPA_D.D inst_VPA_D.C inst_VPA_SYNC.D- - inst_VPA_SYNC.C inst_VPA_SYNC.AP inst_CLK_000_D0.D inst_CLK_000_D0.C - inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_D2.D inst_CLK_000_D2.C - inst_CLK_000_D5.D inst_CLK_000_D5.C inst_CLK_OUT_PRE.D.X1 inst_CLK_OUT_PRE.D.X2 - inst_CLK_OUT_PRE.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.D - SM_AMIGA_5_.C SM_AMIGA_5_.AR cpu_est_2_.D.X1 cpu_est_2_.D.X2 cpu_est_2_.C - CLK_REF_1_.D CLK_REF_1_.LH CLK_REF_1_.AR SM_AMIGA_7_.D SM_AMIGA_7_.C - SM_AMIGA_7_.AP inst_CLK_000_D3.D inst_CLK_000_D3.C SM_AMIGA_4_.D SM_AMIGA_4_.C - SM_AMIGA_4_.AR inst_CLK_000_D4.D inst_CLK_000_D4.C CLK_CNT_0_.D CLK_CNT_0_.C - CLK_CNT_1_.D CLK_CNT_1_.C SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR - SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR 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inst_CLK_000_D0.AP inst_CLK_000_D1.D inst_CLK_000_D1.C + inst_CLK_000_D1.AP inst_CLK_000_D2.D inst_CLK_000_D2.C inst_CLK_000_D2.AP + inst_CLK_000_D5.D inst_CLK_000_D5.C inst_CLK_000_D5.AP SM_AMIGA_5_.D + SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR + inst_CLK_000_D3.D inst_CLK_000_D3.C inst_CLK_000_D3.AP SM_AMIGA_4_.D + SM_AMIGA_4_.C SM_AMIGA_4_.AR inst_CLK_000_D4.D inst_CLK_000_D4.C + inst_CLK_000_D4.AP SM_AMIGA_7_.D SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_3_.D + SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR + CLK_CNT_N_0_.D CLK_CNT_N_0_.C CLK_CNT_N_0_.AR CLK_CNT_N_1_.D CLK_CNT_N_1_.C + CLK_CNT_N_1_.AR CLK_CNT_P_0_.D CLK_CNT_P_0_.C CLK_CNT_P_0_.AR CLK_CNT_P_1_.D + CLK_CNT_P_1_.C CLK_CNT_P_1_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR + SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C + inst_CLK_OUT_PRE.AR cpu_est_0_.D cpu_est_0_.C cpu_est_0_.AR cpu_est_1_.T + cpu_est_1_.C cpu_est_1_.AR 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000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000 +-----------------------------------------------------------------------1--- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 .end diff --git a/Logic/68030_tk.vcl b/Logic/68030_tk.vcl index 30f3d16..40a42ed 100644 --- a/Logic/68030_tk.vcl +++ b/Logic/68030_tk.vcl @@ -18,7 +18,7 @@ SDS_file = m4a5.sds; Design = 68030_tk.tt4; Rev = 0.01; DATE = 5/24/14; -TIME = 11:44:13; +TIME = 15:48:54; Type = TT2; Pre_Fit_Time = 1; Source_Format = Pure_VHDL; @@ -144,39 +144,40 @@ BGACK_030 = OUTPUT,83,7,-; FPU_CS = OUTPUT,78,7,-; VMA = OUTPUT,35,3,-; AS_000 = OUTPUT,33,3,-; -BG_000 = OUTPUT,29,3,-; AVEC = OUTPUT,92,0,-; DSACK_0_ = OUTPUT,80,7,-; CLK_DIV_OUT = OUTPUT,65,6,-; AMIGA_BUS_DATA_DIR = OUTPUT,48,4,-; CIIN = OUTPUT,47,4,-; BERR = OUTPUT,41,4,-; +BG_000 = OUTPUT,29,3,-; AVEC_EXP = OUTPUT,22,2,-; AMIGA_BUS_ENABLE_LOW = OUTPUT,20,2,-; CLK_EXP = OUTPUT,10,1,-; RESET = OUTPUT,3,1,-; +inst_CLK_000_D1 = NODE,*,3,-; inst_CLK_000_D0 = NODE,*,6,-; -SM_AMIGA_3_ = NODE,*,1,-; -inst_CLK_000_D1 = NODE,*,6,-; -cpu_est_1_ = NODE,*,3,-; +RN_FPU_CS = NODE,-1,7,-; +SM_AMIGA_7_ = NODE,*,7,-; +cpu_est_1_ = NODE,*,6,-; +inst_CLK_OUT_PRE = NODE,*,6,-; RN_E = NODE,-1,6,-; cpu_est_2_ = NODE,*,3,-; cpu_est_0_ = NODE,*,3,-; -RN_FPU_CS = NODE,-1,7,-; -inst_VPA_SYNC = NODE,*,5,-; -inst_DTACK_SYNC = NODE,*,0,-; -inst_VPA_D = NODE,*,6,-; -SM_AMIGA_7_ = NODE,*,7,-; -SM_AMIGA_2_ = NODE,*,6,-; SM_AMIGA_1_ = NODE,*,1,-; -inst_CLK_OUT_PRE = NODE,*,6,-; +SM_AMIGA_3_ = NODE,*,1,-; RN_VMA = NODE,-1,3,-; RN_BGACK_030 = NODE,-1,7,-; RN_AS_000 = NODE,-1,3,-; +CLK_CNT_N_0_ = NODE,*,1,-; SM_AMIGA_4_ = NODE,*,3,-; SM_AMIGA_6_ = NODE,*,7,-; +inst_VPA_SYNC = NODE,*,6,-; +inst_DTACK_SYNC = NODE,*,6,-; +CLK_CNT_N_1_ = NODE,*,6,-; inst_CLK_000_D4 = NODE,*,7,-; inst_CLK_000_D5 = NODE,*,7,-; +inst_VPA_D = NODE,*,7,-; RN_LDS_000 = NODE,-1,3,-; inst_AS_030_000_SYNC = NODE,*,7,-; RN_UDS_000 = NODE,-1,3,-; @@ -185,12 +186,11 @@ RN_IPL_030_0_ = NODE,-1,1,-; RN_IPL_030_1_ = NODE,-1,1,-; RN_AMIGA_BUS_ENABLE = NODE,-1,3,-; RN_IPL_030_2_ = NODE,-1,1,-; -RN_BG_000 = NODE,-1,3,-; +SM_AMIGA_2_ = NODE,*,1,-; RN_DSACK_1_ = NODE,-1,7,-; -CLK_CNT_1_ = NODE,*,6,-; -CLK_CNT_0_ = NODE,*,6,-; +CLK_CNT_P_0_ = NODE,*,6,-; SM_AMIGA_5_ = NODE,*,3,-; +CLK_CNT_P_1_ = NODE,*,6,-; inst_CLK_000_D3 = NODE,*,7,-; -CLK_REF_1_ = NODE,*,7,-; -inst_CLK_000_D2 = NODE,*,6,-; +inst_CLK_000_D2 = NODE,*,3,-; CLK_OSZI = INPUT,61,-,-; diff --git a/Logic/68030_tk.vco b/Logic/68030_tk.vco index 8ef3d9c..b6e9988 100644 --- a/Logic/68030_tk.vco +++ b/Logic/68030_tk.vco @@ -18,7 +18,7 @@ SDS_file = m4a5.sds; Design = 68030_tk.tt4; Rev = 0.01; DATE = 5/24/14; -TIME = 11:44:13; +TIME = 15:48:54; Type = TT2; Pre_Fit_Time = 1; Source_Format = Pure_VHDL; @@ -133,44 +133,44 @@ Usercode_Format = Hex; Layer = OFF; SIZE_1_ = INPUT,79, H,-; A_31_ = INPUT,4, B,-; -IPL_2_ = INPUT,68, G,-; -FC_1_ = INPUT,58, F,-; -AS_030 = INPUT,82, H,-; -DS_030 = INPUT,98, A,-; -nEXP_SPACE = INPUT,14,-,-; -BERR = OUTPUT,41, E,-; -BG_030 = INPUT,21, C,-; -BGACK_000 = INPUT,28, D,-; -CLK_030 = INPUT,64,-,-; -CLK_000 = INPUT,11,-,-; SIZE_0_ = INPUT,70, G,-; -CLK_OSZI = INPUT,61,-,-; +IPL_2_ = INPUT,68, G,-; A_30_ = INPUT,5, B,-; -CLK_DIV_OUT = OUTPUT,65, G,-; A_29_ = INPUT,6, B,-; A_28_ = INPUT,15, C,-; A_27_ = INPUT,16, C,-; +FC_1_ = INPUT,58, F,-; A_26_ = INPUT,17, C,-; -AVEC = OUTPUT,92, A,-; +AS_030 = INPUT,82, H,-; A_25_ = INPUT,18, C,-; -AVEC_EXP = OUTPUT,22, C,-; A_24_ = INPUT,19, C,-; +DS_030 = INPUT,98, A,-; A_23_ = INPUT,84, H,-; -VPA = INPUT,36,-,-; A_22_ = INPUT,85, H,-; A_21_ = INPUT,94, A,-; -RST = INPUT,86,-,-; +nEXP_SPACE = INPUT,14,-,-; A_20_ = INPUT,93, A,-; +BERR = OUTPUT,41, E,-; A_19_ = INPUT,97, A,-; -RW = INPUT,71, G,-; +BG_030 = INPUT,21, C,-; A_18_ = INPUT,95, A,-; A_17_ = INPUT,59, F,-; -AMIGA_BUS_DATA_DIR = OUTPUT,48, E,-; A_16_ = INPUT,96, A,-; -AMIGA_BUS_ENABLE_LOW = OUTPUT,20, C,-; -CIIN = OUTPUT,47, E,-; +BGACK_000 = INPUT,28, D,-; +CLK_030 = INPUT,64,-,-; +CLK_000 = INPUT,11,-,-; +CLK_OSZI = INPUT,61,-,-; +CLK_DIV_OUT = OUTPUT,65, G,-; +AVEC = OUTPUT,92, A,-; +AVEC_EXP = OUTPUT,22, C,-; +VPA = INPUT,36,-,-; +RST = INPUT,86,-,-; +RW = INPUT,71, G,-; A_0_ = INPUT,69, G,-; +AMIGA_BUS_DATA_DIR = OUTPUT,48, E,-; +AMIGA_BUS_ENABLE_LOW = OUTPUT,20, C,-; IPL_1_ = INPUT,56, F,-; +CIIN = OUTPUT,47, E,-; IPL_0_ = INPUT,67, G,-; DSACK_0_ = OUTPUT,80, H,-; FC_0_ = INPUT,57, F,-; @@ -190,28 +190,29 @@ RESET = OUTPUT,3, B,-; AMIGA_BUS_ENABLE = OUTPUT,34, D,-; IPL_030_1_ = OUTPUT,7, B,-; IPL_030_0_ = OUTPUT,8, B,-; -cpu_est_0_ = NODE,6, D,-; -cpu_est_1_ = NODE,9, D,-; -inst_AS_030_000_SYNC = NODE,2, H,-; -inst_DTACK_SYNC = NODE,0, A,-; -inst_VPA_D = NODE,1, G,-; -inst_VPA_SYNC = NODE,0, F,-; +inst_AS_030_000_SYNC = NODE,6, H,-; +inst_DTACK_SYNC = NODE,9, G,-; +inst_VPA_D = NODE,2, H,-; +inst_VPA_SYNC = NODE,5, G,-; inst_CLK_000_D0 = NODE,8, G,-; -inst_CLK_000_D1 = NODE,12, G,-; -inst_CLK_000_D2 = NODE,6, G,-; +inst_CLK_000_D1 = NODE,9, D,-; +inst_CLK_000_D2 = NODE,3, D,-; inst_CLK_000_D5 = NODE,13, H,-; -inst_CLK_OUT_PRE = NODE,9, G,-; -SM_AMIGA_6_ = NODE,5, H,-; SM_AMIGA_5_ = NODE,14, D,-; -cpu_est_2_ = NODE,2, D,-; -CLK_REF_1_ = NODE,14, H,-; -SM_AMIGA_7_ = NODE,1, H,-; -inst_CLK_000_D3 = NODE,10, H,-; +SM_AMIGA_6_ = NODE,5, H,-; +inst_CLK_000_D3 = NODE,14, H,-; SM_AMIGA_4_ = NODE,10, D,-; inst_CLK_000_D4 = NODE,9, H,-; -CLK_CNT_0_ = NODE,2, G,-; -CLK_CNT_1_ = NODE,13, G,-; -SM_AMIGA_3_ = NODE,5, B,-; -SM_AMIGA_1_ = NODE,9, B,-; -SM_AMIGA_2_ = NODE,5, G,-; -SM_AMIGA_0_ = NODE,6, H,-; +SM_AMIGA_7_ = NODE,1, H,-; +SM_AMIGA_3_ = NODE,9, B,-; +SM_AMIGA_1_ = NODE,5, B,-; +CLK_CNT_N_0_ = NODE,13, B,-; +CLK_CNT_N_1_ = NODE,13, G,-; +CLK_CNT_P_0_ = NODE,2, G,-; +CLK_CNT_P_1_ = NODE,6, G,-; +SM_AMIGA_2_ = NODE,2, B,-; +SM_AMIGA_0_ = NODE,10, H,-; +inst_CLK_OUT_PRE = NODE,1, G,-; +cpu_est_0_ = NODE,6, D,-; +cpu_est_1_ = NODE,12, G,-; +cpu_est_2_ = NODE,2, D,-; diff --git a/Logic/68030_tk.xrf b/Logic/68030_tk.xrf index 50b701b..9514321 100644 --- a/Logic/68030_tk.xrf +++ b/Logic/68030_tk.xrf @@ -2,7 +2,7 @@ Signal Name Cross Reference File ispLEVER Classic 1.7.00.05.28.13 -Design '68030_tk' created Sat May 24 11:44:09 2014 +Design '68030_tk' created Sat May 24 15:48:50 2014 LEGEND: '>' Functional Block Port Separator diff --git a/Logic/BUS68030.bl0 b/Logic/BUS68030.bl0 index 040abe3..6435d15 100644 --- a/Logic/BUS68030.bl0 +++ b/Logic/BUS68030.bl0 @@ -1,138 +1,134 @@ -#$ DATE Sat May 24 11:44:09 2014 +#$ DATE Sat May 24 15:48:50 2014 #$ TOOL EDIF2BLIF version IspLever 1.0 #$ MODULE bus68030 -#$ PINS 74 SIZE_1_ A_31_ IPL_030_2_ IPL_2_ DSACK_1_ FC_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 SIZE_0_ CLK_OSZI A_30_ CLK_DIV_OUT A_29_ CLK_EXP A_28_ FPU_CS A_27_ DTACK A_26_ AVEC A_25_ AVEC_EXP A_24_ E A_23_ VPA A_22_ VMA A_21_ RST A_20_ RESET A_19_ RW A_18_ AMIGA_BUS_ENABLE A_17_ AMIGA_BUS_DATA_DIR A_16_ AMIGA_BUS_ENABLE_LOW A_15_ CIIN A_14_ A_13_ A_12_ A_11_ A_10_ A_9_ A_8_ A_7_ A_6_ A_5_ A_4_ A_3_ A_2_ A_1_ A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ IPL_0_ DSACK_0_ FC_0_ -#$ NODES 376 BGACK_000_c CLK_030_c inst_BGACK_030_INTreg inst_FPU_CS_INTreg CLK_OSZI_c cpu_est_3_reg inst_VMA_INTreg cpu_est_0_ CLK_OUT_INTreg cpu_est_1_ \ -# inst_AS_000_INTreg inst_AS_030_000_SYNC IPL_030DFFSH_0_reg inst_DTACK_SYNC inst_VPA_D IPL_030DFFSH_1_reg inst_VPA_SYNC inst_CLK_000_D0 IPL_030DFFSH_2_reg inst_CLK_000_D1 \ -# inst_CLK_000_D2 ipl_c_0__n inst_CLK_000_D5 inst_CLK_OUT_PRE ipl_c_1__n SM_AMIGA_6_ SM_AMIGA_5_ ipl_c_2__n vcc_n_n gnd_n_n \ -# cpu_est_2_ dsack_c_1__n CLK_REF_1_ inst_UDS_000_INTreg DTACK_c inst_LDS_000_INTreg DSACK_INT_1_ SM_AMIGA_7_ AS_000_INT_1_sqmuxa state_machine_un8_clk_000_d2_n \ -# inst_CLK_000_D3 SM_AMIGA_4_ state_machine_un23_clk_000_d0_n RST_c state_machine_un6_clk_000_d4_n inst_CLK_000_D4 RESETDFFreg inst_DTACK_DMA clk_clk_cnt_n RW_c \ -# CLK_CNT_0_ CLK_CNT_1_ fc_c_0__n state_machine_un6_bgack_000_n SM_AMIGA_3_ fc_c_1__n SM_AMIGA_1_ SM_AMIGA_2_ AMIGA_BUS_ENABLEDFFreg SM_AMIGA_0_ \ -# state_machine_un7_as_000_int_n state_machine_un15_clk_000_d0_n clk_cpu_est_11_0_1__n state_machine_lds_000_int_5_n N_124_i state_machine_uds_000_int_5_n N_146_i un1_AMIGA_BUS_ENABLE_1_sqmuxa_2 N_121_i N_122_i \ -# N_66_0 N_65_0 N_145_i un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 DS_030_c_i N_63_i N_62_i state_machine_un6_clk_000_d4_i_n N_61_i CLK_OUT_PRE_0 \ -# N_60_i N_59_i N_58_i N_57_i CLK_000_D1_i N_56_i N_55_i N_52_i N_141_i N_142_i \ -# N_14_0 N_85_i N_139_i clk_cpu_est_11_1__n N_140_i clk_cpu_est_11_3__n sm_amiga_ns_0_0__n G_92 N_125_i G_96 \ -# N_138_i N_162 N_178_i N_163 clk_cpu_est_11_0_3__n N_164 N_119_i N_165 N_43_i N_30 \ -# N_117_i N_118_i N_51 N_123_i N_52 N_115_i N_55 N_116_i N_56 sm_amiga_ns_0_7__n \ -# N_57 N_98_i N_58 N_114_i N_59 N_39_0 N_60 N_94_i N_61 N_97_i \ -# N_62 sm_amiga_ns_0_5__n N_63 N_89_i N_65 N_90_i N_66 N_69 N_88_i N_72 \ -# N_73 N_86_i N_74 N_75 N_83_i N_76 N_77 N_81_i N_79 state_machine_lds_000_int_5_0_n \ -# N_81 state_machine_uds_000_int_5_0_n N_83 N_79_i N_85 N_30_0 N_86 N_165_0 N_88 N_76_i \ -# N_89 N_164_0 N_90 N_163_0 N_94 N_72_i N_97 N_73_i N_98 state_machine_un15_clk_000_d0_0_n \ -# N_114 N_162_0 N_115 state_machine_un6_bgack_000_0_n N_116 state_machine_un23_clk_000_d0_i_n N_117 N_188_1 N_118 N_188_2 \ -# N_119 N_188_3 N_120 N_188_4 N_121 N_188_5 N_122 N_188_6 N_124 N_191_1 \ -# N_125 N_191_2 N_178 state_machine_un8_clk_000_d2_1_n N_138 N_57_i_1 N_139 N_57_i_2 N_140 N_57_i_3 \ -# N_141 N_57_i_4 N_142 N_57_i_5 N_145 clk_cpu_est_11_0_1_1__n N_146 clk_cpu_est_11_0_2_1__n N_77_1 N_120_1 \ -# N_188 N_120_2 N_191 N_79_1 RW_i N_79_2 VPA_D_i N_77_1_0 CLK_000_D0_i N_75_1 \ -# cpu_est_i_0__n N_75_2 cpu_est_i_3__n N_75_3 VMA_INT_i N_75_4 cpu_est_i_1__n N_75_5 DTACK_i N_73_1 \ -# BG_030_i N_73_2 nEXP_SPACE_i N_72_1 sm_amiga_i_3__n N_72_2 AS_000_INT_i sm_amiga_ns_0_1_0__n sm_amiga_i_6__n clk_cpu_est_11_0_1_3__n \ -# cpu_est_i_2__n N_138_1 AMIGA_BUS_ENABLE_i N_119_1 AS_030_i N_118_1 sm_amiga_i_4__n N_117_1 sm_amiga_i_5__n N_97_1 \ -# state_machine_un8_clk_000_d2_i_n N_81_1 sm_amiga_i_7__n state_machine_uds_000_int_5_0_m2_un3_n a_i_0__n state_machine_uds_000_int_5_0_m2_un1_n size_i_1__n state_machine_uds_000_int_5_0_m2_un0_n dsack_i_1__n vpa_sync_0_un3_n \ -# clk_clk_cnt_i_n vpa_sync_0_un1_n clk_cnt_i_0__n vpa_sync_0_un0_n CLK_000_D2_i amiga_bus_enable_0_un3_n AS_030_000_SYNC_i amiga_bus_enable_0_un1_n a_i_30__n amiga_bus_enable_0_un0_n \ -# a_i_31__n uds_000_int_0_un3_n a_i_28__n uds_000_int_0_un1_n a_i_29__n uds_000_int_0_un0_n a_i_26__n lds_000_int_0_un3_n a_i_27__n lds_000_int_0_un1_n \ -# a_i_24__n lds_000_int_0_un0_n a_i_25__n vma_int_0_un3_n a_i_19__n vma_int_0_un1_n a_i_16__n vma_int_0_un0_n a_i_18__n bg_000_0_un3_n \ -# N_137_i bg_000_0_un1_n bg_000_0_un0_n RST_i bgack_030_int_0_un3_n N_120_i bgack_030_int_0_un1_n N_75_i bgack_030_int_0_un0_n N_74_i \ -# as_000_int_0_un3_n N_77_i as_000_int_0_un1_n FPU_CS_INT_i as_000_int_0_un0_n BGACK_030_INT_i cpu_est_0_1__un3_n CLK_000_D5_i cpu_est_0_1__un1_n AS_030_c \ -# cpu_est_0_1__un0_n cpu_est_0_2__un3_n cpu_est_0_2__un1_n DS_030_c cpu_est_0_2__un0_n cpu_est_0_3__un3_n cpu_est_0_3__un1_n cpu_est_0_3__un0_n size_c_0__n ipl_030_0_0__un3_n \ -# ipl_030_0_0__un1_n size_c_1__n ipl_030_0_0__un0_n ipl_030_0_1__un3_n a_c_0__n ipl_030_0_1__un1_n ipl_030_0_1__un0_n ipl_030_0_2__un3_n ipl_030_0_2__un1_n ipl_030_0_2__un0_n \ -# as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n dtack_sync_0_un3_n dtack_sync_0_un1_n dtack_sync_0_un0_n fpu_cs_int_0_un3_n fpu_cs_int_0_un1_n fpu_cs_int_0_un0_n dsack_int_0_1__un3_n \ -# dsack_int_0_1__un1_n dsack_int_0_1__un0_n a_c_16__n a_15__n a_c_17__n a_14__n a_c_18__n a_13__n a_c_19__n a_12__n \ -# a_c_20__n a_11__n a_c_21__n a_10__n a_c_22__n a_9__n a_c_23__n a_8__n a_c_24__n a_7__n \ -# a_c_25__n a_6__n a_c_26__n a_5__n a_c_27__n a_4__n a_c_28__n a_3__n a_c_29__n a_2__n \ -# a_c_30__n a_1__n a_c_31__n nEXP_SPACE_c BG_030_c BG_000DFFSHreg +#$ PINS 74 SIZE_1_ A_31_ IPL_030_2_ SIZE_0_ IPL_2_ A_30_ A_29_ DSACK_1_ A_28_ A_27_ FC_1_ A_26_ AS_030 A_25_ AS_000 A_24_ DS_030 A_23_ UDS_000 A_22_ LDS_000 A_21_ nEXP_SPACE A_20_ BERR A_19_ BG_030 A_18_ BG_000 A_17_ BGACK_030 A_16_ BGACK_000 A_15_ CLK_030 A_14_ CLK_000 A_13_ CLK_OSZI A_12_ CLK_DIV_OUT A_11_ CLK_EXP A_10_ FPU_CS A_9_ DTACK A_8_ AVEC A_7_ AVEC_EXP A_6_ E A_5_ VPA A_4_ VMA A_3_ RST A_2_ RESET A_1_ RW A_0_ AMIGA_BUS_ENABLE IPL_030_1_ AMIGA_BUS_DATA_DIR IPL_030_0_ AMIGA_BUS_ENABLE_LOW IPL_1_ CIIN IPL_0_ DSACK_0_ FC_0_ +#$ NODES 357 CLK_OSZI_c CLK_OUT_INTreg IPL_030DFFSH_0_reg inst_BGACK_030_INTreg inst_FPU_CS_INTreg IPL_030DFFSH_1_reg inst_VMA_INTreg inst_AS_000_INTreg IPL_030DFFSH_2_reg inst_AS_030_000_SYNC \ +# inst_DTACK_SYNC ipl_c_0__n inst_VPA_D inst_VPA_SYNC ipl_c_1__n inst_CLK_000_D0 inst_CLK_000_D1 ipl_c_2__n inst_CLK_000_D2 inst_CLK_000_D5 \ +# SM_AMIGA_5_ dsack_c_1__n SM_AMIGA_6_ vcc_n_n DTACK_c gnd_n_n inst_UDS_000_INTreg inst_LDS_000_INTreg DSACK_INT_1_ AS_000_INT_1_sqmuxa \ +# state_machine_un8_clk_000_d2_n inst_CLK_000_D3 SM_AMIGA_4_ RST_c state_machine_un23_clk_000_d0_n state_machine_un6_clk_000_d4_n RESETDFFRHreg inst_CLK_000_D4 inst_DTACK_DMA RW_c \ +# state_machine_un10_bg_030_n SM_AMIGA_7_ fc_c_0__n SM_AMIGA_3_ state_machine_un6_bgack_000_n fc_c_1__n SM_AMIGA_1_ G_102 AMIGA_BUS_ENABLEDFFreg CLK_CNT_N_0_ \ +# CLK_CNT_N_1_ G_108 CLK_CNT_P_0_ CLK_CNT_P_1_ cpu_est_ns_0_1__n SM_AMIGA_2_ N_126_i SM_AMIGA_0_ N_128_i state_machine_un7_as_000_int_n \ +# N_216_i state_machine_un15_clk_000_d0_n N_217_i state_machine_lds_000_int_5_n N_61_0 state_machine_uds_000_int_5_n N_60_0 un1_AMIGA_BUS_ENABLE_1_sqmuxa_2 N_129_i inst_CLK_OUT_PRE \ +# un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 DS_030_c_i N_58_i N_57_i N_55_i N_54_i N_53_i N_50_i CLK_000_D1_i N_49_i \ +# N_48_i N_122_i N_123_i cpu_est_ns_e_0_0__n N_79_i N_226_i N_227_i sm_amiga_ns_0_0__n cpu_est_0_ N_222_i \ +# cpu_est_1_ N_223_i cpu_est_2_ N_225_i cpu_est_3_reg cpu_est_ns_0_2__n N_221_i N_41_i N_127_i N_220_i \ +# cpu_est_ns_1__n N_157_i cpu_est_ns_2__n N_214_i N_203 N_215_i N_204 sm_amiga_ns_0_7__n N_205 N_93_i \ +# N_23 N_94_i N_27 N_47 N_85_i N_48 N_86_i N_49 sm_amiga_ns_0_5__n N_50 \ +# N_84_i N_53 N_130_i N_54 N_55 N_82_i N_57 N_58 N_81_i N_60 \ +# N_61 N_77_i N_68 N_69 N_75_i N_70 state_machine_lds_000_int_5_0_n N_71 state_machine_uds_000_int_5_0_n N_72 \ +# N_73_i N_73 N_27_0 N_75 N_23_0 N_77 N_71_i N_79 N_205_0 N_81 \ +# N_204_0 N_82 N_68_i N_84 N_69_i N_85 state_machine_un15_clk_000_d0_0_n N_86 N_203_0 N_93 \ +# state_machine_un6_bgack_000_0_n N_94 N_214 state_machine_un23_clk_000_d0_0_n N_215 N_238_1 N_216 N_238_2 N_217 N_238_3 \ +# N_220 N_238_4 N_221 N_238_5 N_222 N_238_6 N_223 N_241_1 N_225 N_241_2 \ +# N_226 state_machine_un8_clk_000_d2_1_n N_227 N_53_i_1 N_122 N_53_i_2 N_123 N_53_i_3 N_126 N_53_i_4 \ +# N_127 N_53_i_5 N_128 cpu_est_ns_0_1_1__n N_129 cpu_est_ns_0_2_1__n N_130 state_machine_un10_bg_030_1_n N_238 state_machine_un10_bg_030_2_n \ +# N_241 state_machine_un10_bg_030_3_n RW_i N_73_1 VMA_INT_i N_73_2 VPA_D_i N_72_1 DTACK_i N_72_2 \ +# BG_030_i N_70_1 nEXP_SPACE_i N_70_2 CLK_000_D0_i N_70_3 sm_amiga_i_4__n sm_amiga_ns_0_1_0__n cpu_est_i_3__n cpu_est_ns_0_1_2__n \ +# sm_amiga_i_1__n N_221_1 state_machine_un6_clk_000_d4_i_n N_215_1 sm_amiga_i_6__n N_75_1 AS_000_INT_i N_69_1 cpu_est_i_1__n N_68_1 \ +# cpu_est_i_0__n state_machine_uds_000_int_5_0_m2_un3_n AMIGA_BUS_ENABLE_i state_machine_uds_000_int_5_0_m2_un1_n AS_030_i state_machine_uds_000_int_5_0_m2_un0_n cpu_est_i_2__n lds_000_int_0_un3_n sm_amiga_i_2__n lds_000_int_0_un1_n \ +# sm_amiga_i_3__n lds_000_int_0_un0_n sm_amiga_i_5__n vpa_sync_0_un3_n state_machine_un8_clk_000_d2_i_n vpa_sync_0_un1_n sm_amiga_i_7__n vpa_sync_0_un0_n a_i_0__n vma_int_0_un3_n \ +# size_i_1__n vma_int_0_un1_n dsack_i_1__n vma_int_0_un0_n CLK_000_D2_i bgack_030_int_0_un3_n AS_030_000_SYNC_i bgack_030_int_0_un1_n a_i_30__n bgack_030_int_0_un0_n \ +# a_i_31__n as_000_int_0_un3_n a_i_28__n as_000_int_0_un1_n a_i_29__n as_000_int_0_un0_n a_i_26__n ipl_030_0_0__un3_n a_i_27__n ipl_030_0_0__un1_n \ +# a_i_24__n ipl_030_0_0__un0_n a_i_25__n ipl_030_0_1__un3_n a_i_19__n ipl_030_0_1__un1_n a_i_16__n ipl_030_0_1__un0_n a_i_18__n ipl_030_0_2__un3_n \ +# RST_i ipl_030_0_2__un1_n ipl_030_0_2__un0_n cpu_estse_0_un3_n cpu_estse_0_un1_n CLK_OSZI_i cpu_estse_0_un0_n cpu_estse_1_un3_n N_70_i cpu_estse_1_un1_n \ +# N_72_i cpu_estse_1_un0_n FPU_CS_INT_i cpu_estse_2_un3_n BGACK_030_INT_i cpu_estse_2_un1_n CLK_000_D5_i cpu_estse_2_un0_n AS_030_c as_030_000_sync_0_un3_n \ +# as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n DS_030_c dtack_sync_0_un3_n dtack_sync_0_un1_n dtack_sync_0_un0_n fpu_cs_int_0_un3_n size_c_0__n fpu_cs_int_0_un1_n fpu_cs_int_0_un0_n \ +# size_c_1__n dsack_int_0_1__un3_n dsack_int_0_1__un1_n a_c_0__n dsack_int_0_1__un0_n amiga_bus_enable_0_un3_n amiga_bus_enable_0_un1_n amiga_bus_enable_0_un0_n uds_000_int_0_un3_n uds_000_int_0_un1_n \ +# uds_000_int_0_un0_n a_15__n a_14__n a_13__n a_12__n a_11__n a_c_16__n a_10__n a_c_17__n a_9__n \ +# a_c_18__n a_8__n a_c_19__n a_7__n a_c_20__n a_6__n a_c_21__n a_5__n a_c_22__n a_4__n \ +# a_c_23__n a_3__n a_c_24__n a_2__n a_c_25__n a_1__n a_c_26__n a_c_27__n a_c_28__n a_c_29__n \ +# a_c_30__n a_c_31__n nEXP_SPACE_c BG_030_c BG_000DFFSHreg BGACK_000_c CLK_030_c .model bus68030 .inputs SIZE_1_.BLIF A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF AS_030.BLIF DS_030.BLIF nEXP_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF \ CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF VPA.BLIF RST.BLIF RW.BLIF SIZE_0_.BLIF A_30_.BLIF A_29_.BLIF \ A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF \ A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF A_15_.BLIF A_14_.BLIF A_13_.BLIF A_12_.BLIF A_11_.BLIF \ A_10_.BLIF A_9_.BLIF A_8_.BLIF A_7_.BLIF A_6_.BLIF A_5_.BLIF A_4_.BLIF A_3_.BLIF A_2_.BLIF \ - A_1_.BLIF A_0_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF DSACK_1_.BLIF DTACK.BLIF DSACK_0_.BLIF BGACK_000_c.BLIF CLK_030_c.BLIF inst_BGACK_030_INTreg.BLIF inst_FPU_CS_INTreg.BLIF \ - CLK_OSZI_c.BLIF cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF CLK_OUT_INTreg.BLIF cpu_est_1_.BLIF inst_AS_000_INTreg.BLIF inst_AS_030_000_SYNC.BLIF IPL_030DFFSH_0_reg.BLIF \ - inst_DTACK_SYNC.BLIF inst_VPA_D.BLIF IPL_030DFFSH_1_reg.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D0.BLIF IPL_030DFFSH_2_reg.BLIF inst_CLK_000_D1.BLIF inst_CLK_000_D2.BLIF ipl_c_0__n.BLIF \ - inst_CLK_000_D5.BLIF inst_CLK_OUT_PRE.BLIF ipl_c_1__n.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_5_.BLIF ipl_c_2__n.BLIF vcc_n_n.BLIF gnd_n_n.BLIF cpu_est_2_.BLIF \ - dsack_c_1__n.BLIF CLK_REF_1_.BLIF inst_UDS_000_INTreg.BLIF DTACK_c.BLIF inst_LDS_000_INTreg.BLIF DSACK_INT_1_.BLIF SM_AMIGA_7_.BLIF AS_000_INT_1_sqmuxa.BLIF state_machine_un8_clk_000_d2_n.BLIF \ - inst_CLK_000_D3.BLIF SM_AMIGA_4_.BLIF state_machine_un23_clk_000_d0_n.BLIF RST_c.BLIF state_machine_un6_clk_000_d4_n.BLIF inst_CLK_000_D4.BLIF RESETDFFreg.BLIF inst_DTACK_DMA.BLIF clk_clk_cnt_n.BLIF \ - RW_c.BLIF CLK_CNT_0_.BLIF CLK_CNT_1_.BLIF fc_c_0__n.BLIF state_machine_un6_bgack_000_n.BLIF SM_AMIGA_3_.BLIF fc_c_1__n.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_2_.BLIF \ - AMIGA_BUS_ENABLEDFFreg.BLIF SM_AMIGA_0_.BLIF state_machine_un7_as_000_int_n.BLIF state_machine_un15_clk_000_d0_n.BLIF clk_cpu_est_11_0_1__n.BLIF state_machine_lds_000_int_5_n.BLIF N_124_i.BLIF state_machine_uds_000_int_5_n.BLIF N_146_i.BLIF \ - un1_AMIGA_BUS_ENABLE_1_sqmuxa_2.BLIF N_121_i.BLIF N_122_i.BLIF N_66_0.BLIF N_65_0.BLIF N_145_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0.BLIF DS_030_c_i.BLIF N_63_i.BLIF \ - N_62_i.BLIF state_machine_un6_clk_000_d4_i_n.BLIF N_61_i.BLIF CLK_OUT_PRE_0.BLIF N_60_i.BLIF N_59_i.BLIF N_58_i.BLIF N_57_i.BLIF CLK_000_D1_i.BLIF \ - N_56_i.BLIF N_55_i.BLIF N_52_i.BLIF N_141_i.BLIF N_142_i.BLIF N_14_0.BLIF N_85_i.BLIF N_139_i.BLIF clk_cpu_est_11_1__n.BLIF \ - N_140_i.BLIF clk_cpu_est_11_3__n.BLIF sm_amiga_ns_0_0__n.BLIF G_92.BLIF N_125_i.BLIF G_96.BLIF N_138_i.BLIF N_162.BLIF N_178_i.BLIF \ - N_163.BLIF clk_cpu_est_11_0_3__n.BLIF N_164.BLIF N_119_i.BLIF N_165.BLIF N_43_i.BLIF N_30.BLIF N_117_i.BLIF N_118_i.BLIF \ - N_51.BLIF N_123_i.BLIF N_52.BLIF N_115_i.BLIF N_55.BLIF N_116_i.BLIF N_56.BLIF sm_amiga_ns_0_7__n.BLIF N_57.BLIF \ - N_98_i.BLIF N_58.BLIF N_114_i.BLIF N_59.BLIF N_39_0.BLIF N_60.BLIF N_94_i.BLIF N_61.BLIF N_97_i.BLIF \ - N_62.BLIF sm_amiga_ns_0_5__n.BLIF N_63.BLIF N_89_i.BLIF N_65.BLIF N_90_i.BLIF N_66.BLIF N_69.BLIF N_88_i.BLIF \ - N_72.BLIF N_73.BLIF N_86_i.BLIF N_74.BLIF N_75.BLIF N_83_i.BLIF N_76.BLIF N_77.BLIF N_81_i.BLIF \ - N_79.BLIF state_machine_lds_000_int_5_0_n.BLIF N_81.BLIF state_machine_uds_000_int_5_0_n.BLIF N_83.BLIF N_79_i.BLIF N_85.BLIF N_30_0.BLIF N_86.BLIF \ - N_165_0.BLIF N_88.BLIF N_76_i.BLIF N_89.BLIF N_164_0.BLIF N_90.BLIF N_163_0.BLIF N_94.BLIF N_72_i.BLIF \ - N_97.BLIF N_73_i.BLIF N_98.BLIF state_machine_un15_clk_000_d0_0_n.BLIF N_114.BLIF N_162_0.BLIF N_115.BLIF state_machine_un6_bgack_000_0_n.BLIF N_116.BLIF \ - state_machine_un23_clk_000_d0_i_n.BLIF N_117.BLIF N_188_1.BLIF N_118.BLIF N_188_2.BLIF N_119.BLIF N_188_3.BLIF N_120.BLIF N_188_4.BLIF \ - N_121.BLIF N_188_5.BLIF N_122.BLIF N_188_6.BLIF N_124.BLIF N_191_1.BLIF N_125.BLIF N_191_2.BLIF N_178.BLIF \ - state_machine_un8_clk_000_d2_1_n.BLIF N_138.BLIF N_57_i_1.BLIF N_139.BLIF N_57_i_2.BLIF N_140.BLIF N_57_i_3.BLIF N_141.BLIF N_57_i_4.BLIF \ - N_142.BLIF N_57_i_5.BLIF N_145.BLIF clk_cpu_est_11_0_1_1__n.BLIF N_146.BLIF clk_cpu_est_11_0_2_1__n.BLIF N_77_1.BLIF N_120_1.BLIF N_188.BLIF \ - N_120_2.BLIF N_191.BLIF N_79_1.BLIF RW_i.BLIF N_79_2.BLIF VPA_D_i.BLIF N_77_1_0.BLIF CLK_000_D0_i.BLIF N_75_1.BLIF \ - cpu_est_i_0__n.BLIF N_75_2.BLIF cpu_est_i_3__n.BLIF N_75_3.BLIF VMA_INT_i.BLIF N_75_4.BLIF cpu_est_i_1__n.BLIF N_75_5.BLIF DTACK_i.BLIF \ - N_73_1.BLIF BG_030_i.BLIF N_73_2.BLIF nEXP_SPACE_i.BLIF N_72_1.BLIF sm_amiga_i_3__n.BLIF N_72_2.BLIF AS_000_INT_i.BLIF sm_amiga_ns_0_1_0__n.BLIF \ - sm_amiga_i_6__n.BLIF clk_cpu_est_11_0_1_3__n.BLIF cpu_est_i_2__n.BLIF N_138_1.BLIF AMIGA_BUS_ENABLE_i.BLIF N_119_1.BLIF AS_030_i.BLIF N_118_1.BLIF sm_amiga_i_4__n.BLIF \ - N_117_1.BLIF sm_amiga_i_5__n.BLIF N_97_1.BLIF state_machine_un8_clk_000_d2_i_n.BLIF N_81_1.BLIF sm_amiga_i_7__n.BLIF state_machine_uds_000_int_5_0_m2_un3_n.BLIF a_i_0__n.BLIF state_machine_uds_000_int_5_0_m2_un1_n.BLIF \ - size_i_1__n.BLIF state_machine_uds_000_int_5_0_m2_un0_n.BLIF dsack_i_1__n.BLIF vpa_sync_0_un3_n.BLIF clk_clk_cnt_i_n.BLIF vpa_sync_0_un1_n.BLIF clk_cnt_i_0__n.BLIF vpa_sync_0_un0_n.BLIF CLK_000_D2_i.BLIF \ - amiga_bus_enable_0_un3_n.BLIF AS_030_000_SYNC_i.BLIF amiga_bus_enable_0_un1_n.BLIF a_i_30__n.BLIF amiga_bus_enable_0_un0_n.BLIF a_i_31__n.BLIF uds_000_int_0_un3_n.BLIF a_i_28__n.BLIF uds_000_int_0_un1_n.BLIF \ - a_i_29__n.BLIF uds_000_int_0_un0_n.BLIF a_i_26__n.BLIF lds_000_int_0_un3_n.BLIF a_i_27__n.BLIF lds_000_int_0_un1_n.BLIF a_i_24__n.BLIF lds_000_int_0_un0_n.BLIF a_i_25__n.BLIF \ - vma_int_0_un3_n.BLIF a_i_19__n.BLIF vma_int_0_un1_n.BLIF a_i_16__n.BLIF vma_int_0_un0_n.BLIF a_i_18__n.BLIF bg_000_0_un3_n.BLIF N_137_i.BLIF bg_000_0_un1_n.BLIF \ - bg_000_0_un0_n.BLIF RST_i.BLIF bgack_030_int_0_un3_n.BLIF N_120_i.BLIF bgack_030_int_0_un1_n.BLIF N_75_i.BLIF bgack_030_int_0_un0_n.BLIF N_74_i.BLIF as_000_int_0_un3_n.BLIF \ - N_77_i.BLIF as_000_int_0_un1_n.BLIF FPU_CS_INT_i.BLIF as_000_int_0_un0_n.BLIF BGACK_030_INT_i.BLIF cpu_est_0_1__un3_n.BLIF CLK_000_D5_i.BLIF cpu_est_0_1__un1_n.BLIF AS_030_c.BLIF \ - cpu_est_0_1__un0_n.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un1_n.BLIF DS_030_c.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF size_c_0__n.BLIF \ - ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un1_n.BLIF size_c_1__n.BLIF ipl_030_0_0__un0_n.BLIF ipl_030_0_1__un3_n.BLIF a_c_0__n.BLIF ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF ipl_030_0_2__un3_n.BLIF \ - ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF dtack_sync_0_un3_n.BLIF dtack_sync_0_un1_n.BLIF dtack_sync_0_un0_n.BLIF fpu_cs_int_0_un3_n.BLIF \ - fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF a_c_16__n.BLIF a_15__n.BLIF a_c_17__n.BLIF a_14__n.BLIF \ - a_c_18__n.BLIF a_13__n.BLIF a_c_19__n.BLIF a_12__n.BLIF a_c_20__n.BLIF a_11__n.BLIF a_c_21__n.BLIF a_10__n.BLIF a_c_22__n.BLIF \ - a_9__n.BLIF a_c_23__n.BLIF a_8__n.BLIF a_c_24__n.BLIF a_7__n.BLIF a_c_25__n.BLIF a_6__n.BLIF a_c_26__n.BLIF a_5__n.BLIF \ - a_c_27__n.BLIF a_4__n.BLIF a_c_28__n.BLIF a_3__n.BLIF a_c_29__n.BLIF a_2__n.BLIF a_c_30__n.BLIF a_1__n.BLIF a_c_31__n.BLIF \ - nEXP_SPACE_c.BLIF BG_030_c.BLIF BG_000DFFSHreg.BLIF DSACK_1_.PIN DTACK.PIN + A_1_.BLIF A_0_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF DSACK_1_.BLIF DTACK.BLIF DSACK_0_.BLIF CLK_OSZI_c.BLIF CLK_OUT_INTreg.BLIF IPL_030DFFSH_0_reg.BLIF inst_BGACK_030_INTreg.BLIF \ + inst_FPU_CS_INTreg.BLIF IPL_030DFFSH_1_reg.BLIF inst_VMA_INTreg.BLIF inst_AS_000_INTreg.BLIF IPL_030DFFSH_2_reg.BLIF inst_AS_030_000_SYNC.BLIF inst_DTACK_SYNC.BLIF ipl_c_0__n.BLIF inst_VPA_D.BLIF \ + inst_VPA_SYNC.BLIF ipl_c_1__n.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF ipl_c_2__n.BLIF inst_CLK_000_D2.BLIF inst_CLK_000_D5.BLIF SM_AMIGA_5_.BLIF dsack_c_1__n.BLIF \ + SM_AMIGA_6_.BLIF vcc_n_n.BLIF DTACK_c.BLIF gnd_n_n.BLIF inst_UDS_000_INTreg.BLIF inst_LDS_000_INTreg.BLIF DSACK_INT_1_.BLIF AS_000_INT_1_sqmuxa.BLIF state_machine_un8_clk_000_d2_n.BLIF \ + inst_CLK_000_D3.BLIF SM_AMIGA_4_.BLIF RST_c.BLIF state_machine_un23_clk_000_d0_n.BLIF state_machine_un6_clk_000_d4_n.BLIF RESETDFFRHreg.BLIF inst_CLK_000_D4.BLIF inst_DTACK_DMA.BLIF RW_c.BLIF \ + state_machine_un10_bg_030_n.BLIF SM_AMIGA_7_.BLIF fc_c_0__n.BLIF SM_AMIGA_3_.BLIF state_machine_un6_bgack_000_n.BLIF fc_c_1__n.BLIF SM_AMIGA_1_.BLIF G_102.BLIF AMIGA_BUS_ENABLEDFFreg.BLIF \ + CLK_CNT_N_0_.BLIF CLK_CNT_N_1_.BLIF G_108.BLIF CLK_CNT_P_0_.BLIF CLK_CNT_P_1_.BLIF cpu_est_ns_0_1__n.BLIF SM_AMIGA_2_.BLIF N_126_i.BLIF SM_AMIGA_0_.BLIF \ + N_128_i.BLIF state_machine_un7_as_000_int_n.BLIF N_216_i.BLIF state_machine_un15_clk_000_d0_n.BLIF N_217_i.BLIF state_machine_lds_000_int_5_n.BLIF N_61_0.BLIF state_machine_uds_000_int_5_n.BLIF N_60_0.BLIF \ + un1_AMIGA_BUS_ENABLE_1_sqmuxa_2.BLIF N_129_i.BLIF inst_CLK_OUT_PRE.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0.BLIF DS_030_c_i.BLIF N_58_i.BLIF N_57_i.BLIF N_55_i.BLIF N_54_i.BLIF \ + N_53_i.BLIF N_50_i.BLIF CLK_000_D1_i.BLIF N_49_i.BLIF N_48_i.BLIF N_122_i.BLIF N_123_i.BLIF cpu_est_ns_e_0_0__n.BLIF N_79_i.BLIF \ + N_226_i.BLIF N_227_i.BLIF sm_amiga_ns_0_0__n.BLIF cpu_est_0_.BLIF N_222_i.BLIF cpu_est_1_.BLIF N_223_i.BLIF cpu_est_2_.BLIF N_225_i.BLIF \ + cpu_est_3_reg.BLIF cpu_est_ns_0_2__n.BLIF N_221_i.BLIF N_41_i.BLIF N_127_i.BLIF N_220_i.BLIF cpu_est_ns_1__n.BLIF N_157_i.BLIF cpu_est_ns_2__n.BLIF \ + N_214_i.BLIF N_203.BLIF N_215_i.BLIF N_204.BLIF sm_amiga_ns_0_7__n.BLIF N_205.BLIF N_93_i.BLIF N_23.BLIF N_94_i.BLIF \ + N_27.BLIF N_47.BLIF N_85_i.BLIF N_48.BLIF N_86_i.BLIF N_49.BLIF sm_amiga_ns_0_5__n.BLIF N_50.BLIF N_84_i.BLIF \ + N_53.BLIF N_130_i.BLIF N_54.BLIF N_55.BLIF N_82_i.BLIF N_57.BLIF N_58.BLIF N_81_i.BLIF N_60.BLIF \ + N_61.BLIF N_77_i.BLIF N_68.BLIF N_69.BLIF N_75_i.BLIF N_70.BLIF state_machine_lds_000_int_5_0_n.BLIF N_71.BLIF state_machine_uds_000_int_5_0_n.BLIF \ + N_72.BLIF N_73_i.BLIF N_73.BLIF N_27_0.BLIF N_75.BLIF N_23_0.BLIF N_77.BLIF N_71_i.BLIF N_79.BLIF \ + N_205_0.BLIF N_81.BLIF N_204_0.BLIF N_82.BLIF N_68_i.BLIF N_84.BLIF N_69_i.BLIF N_85.BLIF state_machine_un15_clk_000_d0_0_n.BLIF \ + N_86.BLIF N_203_0.BLIF N_93.BLIF state_machine_un6_bgack_000_0_n.BLIF N_94.BLIF N_214.BLIF state_machine_un23_clk_000_d0_0_n.BLIF N_215.BLIF N_238_1.BLIF \ + N_216.BLIF N_238_2.BLIF N_217.BLIF N_238_3.BLIF N_220.BLIF N_238_4.BLIF N_221.BLIF N_238_5.BLIF N_222.BLIF \ + N_238_6.BLIF N_223.BLIF N_241_1.BLIF N_225.BLIF N_241_2.BLIF N_226.BLIF state_machine_un8_clk_000_d2_1_n.BLIF N_227.BLIF N_53_i_1.BLIF \ + N_122.BLIF N_53_i_2.BLIF N_123.BLIF N_53_i_3.BLIF N_126.BLIF N_53_i_4.BLIF N_127.BLIF N_53_i_5.BLIF N_128.BLIF \ + cpu_est_ns_0_1_1__n.BLIF N_129.BLIF cpu_est_ns_0_2_1__n.BLIF N_130.BLIF state_machine_un10_bg_030_1_n.BLIF N_238.BLIF state_machine_un10_bg_030_2_n.BLIF N_241.BLIF state_machine_un10_bg_030_3_n.BLIF \ + RW_i.BLIF N_73_1.BLIF VMA_INT_i.BLIF N_73_2.BLIF VPA_D_i.BLIF N_72_1.BLIF DTACK_i.BLIF N_72_2.BLIF BG_030_i.BLIF \ + N_70_1.BLIF nEXP_SPACE_i.BLIF N_70_2.BLIF CLK_000_D0_i.BLIF N_70_3.BLIF sm_amiga_i_4__n.BLIF sm_amiga_ns_0_1_0__n.BLIF cpu_est_i_3__n.BLIF cpu_est_ns_0_1_2__n.BLIF \ + sm_amiga_i_1__n.BLIF N_221_1.BLIF state_machine_un6_clk_000_d4_i_n.BLIF N_215_1.BLIF sm_amiga_i_6__n.BLIF N_75_1.BLIF AS_000_INT_i.BLIF N_69_1.BLIF cpu_est_i_1__n.BLIF \ + N_68_1.BLIF cpu_est_i_0__n.BLIF state_machine_uds_000_int_5_0_m2_un3_n.BLIF AMIGA_BUS_ENABLE_i.BLIF state_machine_uds_000_int_5_0_m2_un1_n.BLIF AS_030_i.BLIF state_machine_uds_000_int_5_0_m2_un0_n.BLIF cpu_est_i_2__n.BLIF lds_000_int_0_un3_n.BLIF \ + sm_amiga_i_2__n.BLIF lds_000_int_0_un1_n.BLIF sm_amiga_i_3__n.BLIF lds_000_int_0_un0_n.BLIF sm_amiga_i_5__n.BLIF vpa_sync_0_un3_n.BLIF state_machine_un8_clk_000_d2_i_n.BLIF vpa_sync_0_un1_n.BLIF sm_amiga_i_7__n.BLIF \ + vpa_sync_0_un0_n.BLIF a_i_0__n.BLIF vma_int_0_un3_n.BLIF size_i_1__n.BLIF vma_int_0_un1_n.BLIF dsack_i_1__n.BLIF vma_int_0_un0_n.BLIF CLK_000_D2_i.BLIF bgack_030_int_0_un3_n.BLIF \ + AS_030_000_SYNC_i.BLIF bgack_030_int_0_un1_n.BLIF a_i_30__n.BLIF bgack_030_int_0_un0_n.BLIF a_i_31__n.BLIF as_000_int_0_un3_n.BLIF a_i_28__n.BLIF as_000_int_0_un1_n.BLIF a_i_29__n.BLIF \ + as_000_int_0_un0_n.BLIF a_i_26__n.BLIF ipl_030_0_0__un3_n.BLIF a_i_27__n.BLIF ipl_030_0_0__un1_n.BLIF a_i_24__n.BLIF ipl_030_0_0__un0_n.BLIF a_i_25__n.BLIF ipl_030_0_1__un3_n.BLIF \ + a_i_19__n.BLIF ipl_030_0_1__un1_n.BLIF a_i_16__n.BLIF ipl_030_0_1__un0_n.BLIF a_i_18__n.BLIF ipl_030_0_2__un3_n.BLIF RST_i.BLIF ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF \ + cpu_estse_0_un3_n.BLIF cpu_estse_0_un1_n.BLIF CLK_OSZI_i.BLIF cpu_estse_0_un0_n.BLIF cpu_estse_1_un3_n.BLIF N_70_i.BLIF cpu_estse_1_un1_n.BLIF N_72_i.BLIF cpu_estse_1_un0_n.BLIF \ + FPU_CS_INT_i.BLIF cpu_estse_2_un3_n.BLIF BGACK_030_INT_i.BLIF cpu_estse_2_un1_n.BLIF CLK_000_D5_i.BLIF cpu_estse_2_un0_n.BLIF AS_030_c.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un1_n.BLIF \ + as_030_000_sync_0_un0_n.BLIF DS_030_c.BLIF dtack_sync_0_un3_n.BLIF dtack_sync_0_un1_n.BLIF dtack_sync_0_un0_n.BLIF fpu_cs_int_0_un3_n.BLIF size_c_0__n.BLIF fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF \ + size_c_1__n.BLIF dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un1_n.BLIF a_c_0__n.BLIF dsack_int_0_1__un0_n.BLIF amiga_bus_enable_0_un3_n.BLIF amiga_bus_enable_0_un1_n.BLIF amiga_bus_enable_0_un0_n.BLIF uds_000_int_0_un3_n.BLIF \ + uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF a_15__n.BLIF a_14__n.BLIF a_13__n.BLIF a_12__n.BLIF a_11__n.BLIF a_c_16__n.BLIF a_10__n.BLIF \ + a_c_17__n.BLIF a_9__n.BLIF a_c_18__n.BLIF a_8__n.BLIF a_c_19__n.BLIF a_7__n.BLIF a_c_20__n.BLIF a_6__n.BLIF a_c_21__n.BLIF \ + a_5__n.BLIF a_c_22__n.BLIF a_4__n.BLIF a_c_23__n.BLIF a_3__n.BLIF a_c_24__n.BLIF a_2__n.BLIF a_c_25__n.BLIF a_1__n.BLIF \ + a_c_26__n.BLIF a_c_27__n.BLIF a_c_28__n.BLIF a_c_29__n.BLIF a_c_30__n.BLIF a_c_31__n.BLIF nEXP_SPACE_c.BLIF BG_030_c.BLIF BG_000DFFSHreg.BLIF \ + BGACK_000_c.BLIF CLK_030_c.BLIF DSACK_1_.PIN DTACK.PIN .outputs IPL_030_2_ AS_000 UDS_000 LDS_000 BERR BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS AVEC \ - AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ IPL_030DFFSH_0_reg.D \ - IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP IPL_030DFFSH_1_reg.D IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D SM_AMIGA_7_.C SM_AMIGA_7_.AP \ - SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C \ - SM_AMIGA_3_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR CLK_CNT_0_.D \ - CLK_CNT_0_.C CLK_CNT_1_.D CLK_CNT_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_reg.D cpu_est_3_reg.C \ - inst_UDS_000_INTreg.D inst_UDS_000_INTreg.C inst_UDS_000_INTreg.AP inst_LDS_000_INTreg.D inst_LDS_000_INTreg.C inst_LDS_000_INTreg.AP inst_VMA_INTreg.D inst_VMA_INTreg.C inst_VMA_INTreg.AP BG_000DFFSHreg.D BG_000DFFSHreg.C \ - BG_000DFFSHreg.AP inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP inst_AS_000_INTreg.D inst_AS_000_INTreg.C inst_AS_000_INTreg.AP inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \ - inst_AS_030_000_SYNC.AP inst_DTACK_SYNC.D inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_FPU_CS_INTreg.D inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP DSACK_INT_1_.D DSACK_INT_1_.C DSACK_INT_1_.AP inst_VPA_SYNC.D \ - inst_VPA_SYNC.C inst_VPA_SYNC.AP AMIGA_BUS_ENABLEDFFreg.D AMIGA_BUS_ENABLEDFFreg.C inst_CLK_000_D5.D inst_CLK_000_D5.C inst_DTACK_DMA.D inst_DTACK_DMA.C inst_DTACK_DMA.AP CLK_OUT_INTreg.D CLK_OUT_INTreg.C \ - inst_CLK_000_D4.D inst_CLK_000_D4.C inst_CLK_000_D2.D inst_CLK_000_D2.C inst_CLK_000_D3.D inst_CLK_000_D3.C inst_VPA_D.D inst_VPA_D.C inst_CLK_000_D0.D inst_CLK_000_D0.C RESETDFFreg.D \ - RESETDFFreg.C inst_CLK_000_D1.D inst_CLK_000_D1.C CLK_REF_1_.D CLK_REF_1_.LH CLK_REF_1_.AR CLK_OUT_PRE_0.X1 CLK_OUT_PRE_0.X2 G_96.X1 G_96.X2 G_92.X1 \ - G_92.X2 DSACK_1_ DTACK DSACK_0_ BGACK_000_c CLK_030_c CLK_OSZI_c ipl_c_0__n ipl_c_1__n ipl_c_2__n vcc_n_n gnd_n_n dsack_c_1__n DTACK_c \ - AS_000_INT_1_sqmuxa state_machine_un8_clk_000_d2_n state_machine_un23_clk_000_d0_n RST_c state_machine_un6_clk_000_d4_n clk_clk_cnt_n RW_c fc_c_0__n state_machine_un6_bgack_000_n fc_c_1__n state_machine_un7_as_000_int_n \ - state_machine_un15_clk_000_d0_n clk_cpu_est_11_0_1__n state_machine_lds_000_int_5_n N_124_i state_machine_uds_000_int_5_n N_146_i un1_AMIGA_BUS_ENABLE_1_sqmuxa_2 N_121_i N_122_i N_66_0 N_65_0 \ - N_145_i un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 DS_030_c_i N_63_i N_62_i state_machine_un6_clk_000_d4_i_n N_61_i N_60_i N_59_i N_58_i N_57_i \ - CLK_000_D1_i N_56_i N_55_i N_52_i N_141_i N_142_i N_14_0 N_85_i N_139_i clk_cpu_est_11_1__n N_140_i \ - clk_cpu_est_11_3__n sm_amiga_ns_0_0__n N_125_i N_138_i N_162 N_178_i N_163 clk_cpu_est_11_0_3__n N_164 N_119_i N_165 \ - N_43_i N_30 N_117_i N_118_i N_51 N_123_i N_52 N_115_i N_55 N_116_i N_56 \ - sm_amiga_ns_0_7__n N_57 N_98_i N_58 N_114_i N_59 N_39_0 N_60 N_94_i N_61 N_97_i \ - N_62 sm_amiga_ns_0_5__n N_63 N_89_i N_65 N_90_i N_66 N_69 N_88_i N_72 N_73 \ - N_86_i N_74 N_75 N_83_i N_76 N_77 N_81_i N_79 state_machine_lds_000_int_5_0_n N_81 state_machine_uds_000_int_5_0_n \ - N_83 N_79_i N_85 N_30_0 N_86 N_165_0 N_88 N_76_i N_89 N_164_0 N_90 \ - N_163_0 N_94 N_72_i N_97 N_73_i N_98 state_machine_un15_clk_000_d0_0_n N_114 N_162_0 N_115 state_machine_un6_bgack_000_0_n \ - N_116 state_machine_un23_clk_000_d0_i_n N_117 N_188_1 N_118 N_188_2 N_119 N_188_3 N_120 N_188_4 N_121 \ - N_188_5 N_122 N_188_6 N_124 N_191_1 N_125 N_191_2 N_178 state_machine_un8_clk_000_d2_1_n N_138 N_57_i_1 \ - N_139 N_57_i_2 N_140 N_57_i_3 N_141 N_57_i_4 N_142 N_57_i_5 N_145 clk_cpu_est_11_0_1_1__n N_146 \ - clk_cpu_est_11_0_2_1__n N_77_1 N_120_1 N_188 N_120_2 N_191 N_79_1 RW_i N_79_2 VPA_D_i N_77_1_0 \ - CLK_000_D0_i N_75_1 cpu_est_i_0__n N_75_2 cpu_est_i_3__n N_75_3 VMA_INT_i N_75_4 cpu_est_i_1__n N_75_5 DTACK_i \ - N_73_1 BG_030_i N_73_2 nEXP_SPACE_i N_72_1 sm_amiga_i_3__n N_72_2 AS_000_INT_i sm_amiga_ns_0_1_0__n sm_amiga_i_6__n clk_cpu_est_11_0_1_3__n \ - cpu_est_i_2__n N_138_1 AMIGA_BUS_ENABLE_i N_119_1 AS_030_i N_118_1 sm_amiga_i_4__n N_117_1 sm_amiga_i_5__n N_97_1 state_machine_un8_clk_000_d2_i_n \ - N_81_1 sm_amiga_i_7__n state_machine_uds_000_int_5_0_m2_un3_n a_i_0__n state_machine_uds_000_int_5_0_m2_un1_n size_i_1__n state_machine_uds_000_int_5_0_m2_un0_n dsack_i_1__n vpa_sync_0_un3_n clk_clk_cnt_i_n vpa_sync_0_un1_n \ - clk_cnt_i_0__n vpa_sync_0_un0_n CLK_000_D2_i amiga_bus_enable_0_un3_n AS_030_000_SYNC_i amiga_bus_enable_0_un1_n a_i_30__n amiga_bus_enable_0_un0_n a_i_31__n uds_000_int_0_un3_n a_i_28__n \ - uds_000_int_0_un1_n a_i_29__n uds_000_int_0_un0_n a_i_26__n lds_000_int_0_un3_n a_i_27__n lds_000_int_0_un1_n a_i_24__n lds_000_int_0_un0_n a_i_25__n vma_int_0_un3_n \ - a_i_19__n vma_int_0_un1_n a_i_16__n vma_int_0_un0_n a_i_18__n bg_000_0_un3_n N_137_i bg_000_0_un1_n bg_000_0_un0_n RST_i bgack_030_int_0_un3_n \ - N_120_i bgack_030_int_0_un1_n N_75_i bgack_030_int_0_un0_n N_74_i as_000_int_0_un3_n N_77_i as_000_int_0_un1_n FPU_CS_INT_i as_000_int_0_un0_n BGACK_030_INT_i \ - cpu_est_0_1__un3_n CLK_000_D5_i cpu_est_0_1__un1_n AS_030_c cpu_est_0_1__un0_n cpu_est_0_2__un3_n cpu_est_0_2__un1_n DS_030_c cpu_est_0_2__un0_n cpu_est_0_3__un3_n cpu_est_0_3__un1_n \ - cpu_est_0_3__un0_n size_c_0__n ipl_030_0_0__un3_n ipl_030_0_0__un1_n size_c_1__n ipl_030_0_0__un0_n ipl_030_0_1__un3_n a_c_0__n ipl_030_0_1__un1_n ipl_030_0_1__un0_n ipl_030_0_2__un3_n \ - ipl_030_0_2__un1_n ipl_030_0_2__un0_n as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n dtack_sync_0_un3_n dtack_sync_0_un1_n dtack_sync_0_un0_n fpu_cs_int_0_un3_n fpu_cs_int_0_un1_n fpu_cs_int_0_un0_n \ - dsack_int_0_1__un3_n dsack_int_0_1__un1_n dsack_int_0_1__un0_n a_c_16__n a_15__n a_c_17__n a_14__n a_c_18__n a_13__n a_c_19__n a_12__n \ - a_c_20__n a_11__n a_c_21__n a_10__n a_c_22__n a_9__n a_c_23__n a_8__n a_c_24__n a_7__n a_c_25__n \ - a_6__n a_c_26__n a_5__n a_c_27__n a_4__n a_c_28__n a_3__n a_c_29__n a_2__n a_c_30__n a_1__n \ - a_c_31__n nEXP_SPACE_c BG_030_c DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE BERR.OE \ - DSACK_0_.OE AVEC_EXP.OE CIIN.OE + AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ cpu_est_2_.D \ + cpu_est_2_.C cpu_est_2_.AR cpu_est_3_reg.D cpu_est_3_reg.C cpu_est_3_reg.AR cpu_est_0_.D cpu_est_0_.C cpu_est_0_.AR cpu_est_1_.D cpu_est_1_.C cpu_est_1_.AR \ + SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C \ + SM_AMIGA_0_.AR CLK_CNT_N_0_.D CLK_CNT_N_0_.C CLK_CNT_N_0_.AR CLK_CNT_N_1_.D CLK_CNT_N_1_.C CLK_CNT_N_1_.AR CLK_CNT_P_0_.D CLK_CNT_P_0_.C CLK_CNT_P_0_.AR CLK_CNT_P_1_.D \ + CLK_CNT_P_1_.C CLK_CNT_P_1_.AR IPL_030DFFSH_0_reg.D IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP IPL_030DFFSH_1_reg.D IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP \ + SM_AMIGA_7_.D SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C \ + SM_AMIGA_4_.AR inst_UDS_000_INTreg.D inst_UDS_000_INTreg.C inst_UDS_000_INTreg.AP inst_LDS_000_INTreg.D inst_LDS_000_INTreg.C inst_LDS_000_INTreg.AP inst_VPA_SYNC.D inst_VPA_SYNC.C inst_VPA_SYNC.AP inst_VMA_INTreg.D \ + inst_VMA_INTreg.C inst_VMA_INTreg.AP inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP inst_AS_000_INTreg.D inst_AS_000_INTreg.C inst_AS_000_INTreg.AP inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C inst_CLK_OUT_PRE.AR \ + CLK_OUT_INTreg.D CLK_OUT_INTreg.C CLK_OUT_INTreg.AR inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_DTACK_SYNC.D inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_FPU_CS_INTreg.D inst_FPU_CS_INTreg.C \ + inst_FPU_CS_INTreg.AP DSACK_INT_1_.D DSACK_INT_1_.C DSACK_INT_1_.AP AMIGA_BUS_ENABLEDFFreg.D AMIGA_BUS_ENABLEDFFreg.C inst_DTACK_DMA.D inst_DTACK_DMA.C inst_DTACK_DMA.AP inst_CLK_000_D5.D inst_CLK_000_D5.C \ + inst_CLK_000_D5.AP BG_000DFFSHreg.D BG_000DFFSHreg.C BG_000DFFSHreg.AP inst_CLK_000_D4.D inst_CLK_000_D4.C inst_CLK_000_D4.AP inst_CLK_000_D2.D inst_CLK_000_D2.C inst_CLK_000_D2.AP inst_CLK_000_D3.D \ + inst_CLK_000_D3.C inst_CLK_000_D3.AP inst_VPA_D.D inst_VPA_D.C inst_VPA_D.AP inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_D0.AP RESETDFFRHreg.D RESETDFFRHreg.C RESETDFFRHreg.AR \ + inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_D1.AP G_102.X1 G_102.X2 G_108.X1 G_108.X2 DSACK_1_ DTACK DSACK_0_ CLK_OSZI_c ipl_c_0__n ipl_c_1__n ipl_c_2__n \ + dsack_c_1__n vcc_n_n DTACK_c gnd_n_n AS_000_INT_1_sqmuxa state_machine_un8_clk_000_d2_n RST_c state_machine_un23_clk_000_d0_n state_machine_un6_clk_000_d4_n RW_c state_machine_un10_bg_030_n \ + fc_c_0__n state_machine_un6_bgack_000_n fc_c_1__n cpu_est_ns_0_1__n N_126_i N_128_i state_machine_un7_as_000_int_n N_216_i state_machine_un15_clk_000_d0_n N_217_i state_machine_lds_000_int_5_n \ + N_61_0 state_machine_uds_000_int_5_n N_60_0 un1_AMIGA_BUS_ENABLE_1_sqmuxa_2 N_129_i un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 DS_030_c_i N_58_i N_57_i N_55_i N_54_i \ + N_53_i N_50_i CLK_000_D1_i N_49_i N_48_i N_122_i N_123_i cpu_est_ns_e_0_0__n N_79_i N_226_i N_227_i \ + sm_amiga_ns_0_0__n N_222_i N_223_i N_225_i cpu_est_ns_0_2__n N_221_i N_41_i N_127_i N_220_i cpu_est_ns_1__n N_157_i \ + cpu_est_ns_2__n N_214_i N_203 N_215_i N_204 sm_amiga_ns_0_7__n N_205 N_93_i N_23 N_94_i N_27 \ + N_47 N_85_i N_48 N_86_i N_49 sm_amiga_ns_0_5__n N_50 N_84_i N_53 N_130_i N_54 \ + N_55 N_82_i N_57 N_58 N_81_i N_60 N_61 N_77_i N_68 N_69 N_75_i \ + N_70 state_machine_lds_000_int_5_0_n N_71 state_machine_uds_000_int_5_0_n N_72 N_73_i N_73 N_27_0 N_75 N_23_0 N_77 \ + N_71_i N_79 N_205_0 N_81 N_204_0 N_82 N_68_i N_84 N_69_i N_85 state_machine_un15_clk_000_d0_0_n \ + N_86 N_203_0 N_93 state_machine_un6_bgack_000_0_n N_94 N_214 state_machine_un23_clk_000_d0_0_n N_215 N_238_1 N_216 N_238_2 \ + N_217 N_238_3 N_220 N_238_4 N_221 N_238_5 N_222 N_238_6 N_223 N_241_1 N_225 \ + N_241_2 N_226 state_machine_un8_clk_000_d2_1_n N_227 N_53_i_1 N_122 N_53_i_2 N_123 N_53_i_3 N_126 N_53_i_4 \ + N_127 N_53_i_5 N_128 cpu_est_ns_0_1_1__n N_129 cpu_est_ns_0_2_1__n N_130 state_machine_un10_bg_030_1_n N_238 state_machine_un10_bg_030_2_n N_241 \ + state_machine_un10_bg_030_3_n RW_i N_73_1 VMA_INT_i N_73_2 VPA_D_i N_72_1 DTACK_i N_72_2 BG_030_i N_70_1 \ + nEXP_SPACE_i N_70_2 CLK_000_D0_i N_70_3 sm_amiga_i_4__n sm_amiga_ns_0_1_0__n cpu_est_i_3__n cpu_est_ns_0_1_2__n sm_amiga_i_1__n N_221_1 state_machine_un6_clk_000_d4_i_n \ + N_215_1 sm_amiga_i_6__n N_75_1 AS_000_INT_i N_69_1 cpu_est_i_1__n N_68_1 cpu_est_i_0__n state_machine_uds_000_int_5_0_m2_un3_n AMIGA_BUS_ENABLE_i state_machine_uds_000_int_5_0_m2_un1_n \ + AS_030_i state_machine_uds_000_int_5_0_m2_un0_n cpu_est_i_2__n lds_000_int_0_un3_n sm_amiga_i_2__n lds_000_int_0_un1_n sm_amiga_i_3__n lds_000_int_0_un0_n sm_amiga_i_5__n vpa_sync_0_un3_n state_machine_un8_clk_000_d2_i_n \ + vpa_sync_0_un1_n sm_amiga_i_7__n vpa_sync_0_un0_n a_i_0__n vma_int_0_un3_n size_i_1__n vma_int_0_un1_n dsack_i_1__n vma_int_0_un0_n CLK_000_D2_i bgack_030_int_0_un3_n \ + AS_030_000_SYNC_i bgack_030_int_0_un1_n a_i_30__n bgack_030_int_0_un0_n a_i_31__n as_000_int_0_un3_n a_i_28__n as_000_int_0_un1_n a_i_29__n as_000_int_0_un0_n a_i_26__n \ + ipl_030_0_0__un3_n a_i_27__n ipl_030_0_0__un1_n a_i_24__n ipl_030_0_0__un0_n a_i_25__n ipl_030_0_1__un3_n a_i_19__n ipl_030_0_1__un1_n a_i_16__n ipl_030_0_1__un0_n \ + a_i_18__n ipl_030_0_2__un3_n RST_i ipl_030_0_2__un1_n ipl_030_0_2__un0_n cpu_estse_0_un3_n cpu_estse_0_un1_n CLK_OSZI_i cpu_estse_0_un0_n cpu_estse_1_un3_n N_70_i \ + cpu_estse_1_un1_n N_72_i cpu_estse_1_un0_n FPU_CS_INT_i cpu_estse_2_un3_n BGACK_030_INT_i cpu_estse_2_un1_n CLK_000_D5_i cpu_estse_2_un0_n AS_030_c as_030_000_sync_0_un3_n \ + as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n DS_030_c dtack_sync_0_un3_n dtack_sync_0_un1_n dtack_sync_0_un0_n fpu_cs_int_0_un3_n size_c_0__n fpu_cs_int_0_un1_n fpu_cs_int_0_un0_n size_c_1__n \ + dsack_int_0_1__un3_n dsack_int_0_1__un1_n a_c_0__n dsack_int_0_1__un0_n amiga_bus_enable_0_un3_n amiga_bus_enable_0_un1_n amiga_bus_enable_0_un0_n uds_000_int_0_un3_n uds_000_int_0_un1_n uds_000_int_0_un0_n a_15__n \ + a_14__n a_13__n a_12__n a_11__n a_c_16__n a_10__n a_c_17__n a_9__n a_c_18__n a_8__n a_c_19__n \ + a_7__n a_c_20__n a_6__n a_c_21__n a_5__n a_c_22__n a_4__n a_c_23__n a_3__n a_c_24__n a_2__n \ + a_c_25__n a_1__n a_c_26__n a_c_27__n a_c_28__n a_c_29__n a_c_30__n a_c_31__n nEXP_SPACE_c BG_030_c BGACK_000_c \ + CLK_030_c DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE \ + CIIN.OE .names DSACK_INT_1_.BLIF DSACK_1_ 1 1 .names DSACK_1_.PIN dsack_c_1__n @@ -169,831 +165,752 @@ 1 1 .names FPU_CS_INT_i.BLIF AVEC_EXP.OE 1 1 -.names N_191.BLIF CIIN +.names N_241.BLIF CIIN 1 1 -.names N_188.BLIF CIIN.OE +.names N_238.BLIF CIIN.OE 1 1 -.names N_61_i.BLIF N_61 +.names inst_CLK_000_D0.BLIF CLK_000_D0_i 0 1 -.names CLK_OSZI_c.BLIF IPL_030DFFSH_0_reg.C +.names CLK_OSZI_c.BLIF cpu_est_1_.C 1 1 -.names N_60_i.BLIF N_60 +.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n 0 1 -.names N_59_i.BLIF N_59 -0 1 -.names RST_i.BLIF IPL_030DFFSH_0_reg.AP -1 1 -.names N_58_i.BLIF N_58 -0 1 -.names N_57_i.BLIF N_57 -0 1 -.names clk_cpu_est_11_0_1__n.BLIF clk_cpu_est_11_1__n -0 1 -.names N_124.BLIF N_124_i -0 1 -.names CLK_OSZI_c.BLIF IPL_030DFFSH_1_reg.C -1 1 -.names N_146.BLIF N_146_i -0 1 -.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n -0 1 -.names RST_i.BLIF IPL_030DFFSH_1_reg.AP -1 1 -.names SM_AMIGA_3_.BLIF state_machine_un23_clk_000_d0_i_n.BLIF N_66_0 +.names inst_CLK_000_D0.BLIF SM_AMIGA_4_.BLIF N_61_0 11 1 -.names BG_030_c.BLIF BG_030_i -0 1 +.names RST_i.BLIF cpu_est_1_.AR +1 1 .names nEXP_SPACE_c.BLIF nEXP_SPACE_i 0 1 +.names BG_030_c.BLIF BG_030_i +0 1 .names DTACK_c.BLIF DTACK_i 0 1 -.names CLK_OSZI_c.BLIF IPL_030DFFSH_2_reg.C -1 1 -.names cpu_est_1_.BLIF cpu_est_i_1__n +.names inst_VPA_D.BLIF VPA_D_i 0 1 -.names inst_CLK_000_D0.BLIF SM_AMIGA_3_.BLIF N_77_1 -11 1 -.names RST_i.BLIF IPL_030DFFSH_2_reg.AP +.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C 1 1 .names inst_VMA_INTreg.BLIF VMA_INT_i 0 1 -.names cpu_est_0_.BLIF cpu_est_i_0__n -0 1 -.names cpu_est_3_reg.BLIF cpu_est_i_3__n -0 1 -.names inst_CLK_000_D0.BLIF CLK_000_D0_i -0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_7_.C -1 1 -.names inst_VPA_D.BLIF VPA_D_i -0 1 .names RW_c.BLIF RW_i 0 1 -.names RST_i.BLIF SM_AMIGA_7_.AP +.names RST_i.BLIF SM_AMIGA_3_.AR 1 1 +.names N_54.BLIF N_221_i.BLIF N_41_i +11 1 +.names N_122_i.BLIF N_123_i.BLIF cpu_est_ns_e_0_0__n +11 1 .names RW_c.BLIF state_machine_uds_000_int_5_0_m2_un3_n 0 1 .names SM_AMIGA_5_.BLIF RW_c.BLIF state_machine_uds_000_int_5_0_m2_un1_n 11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C +1 1 .names SM_AMIGA_4_.BLIF state_machine_uds_000_int_5_0_m2_un3_n.BLIF state_machine_uds_000_int_5_0_m2_un0_n 11 1 -.names state_machine_uds_000_int_5_0_m2_un1_n.BLIF state_machine_uds_000_int_5_0_m2_un0_n.BLIF N_51 +.names state_machine_uds_000_int_5_0_m2_un1_n.BLIF state_machine_uds_000_int_5_0_m2_un0_n.BLIF N_47 1- 1 -1 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C -1 1 -.names AS_030_i.BLIF N_74_i.BLIF N_52_i -11 1 -.names cpu_est_2_.BLIF cpu_est_i_2__n -0 1 -.names RST_i.BLIF SM_AMIGA_6_.AR -1 1 -.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_55_i -11 1 -.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF N_56_i -11 1 -.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n -0 1 -.names SM_AMIGA_6_.BLIF nEXP_SPACE_c.BLIF N_58_i -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C +.names RST_i.BLIF SM_AMIGA_2_.AR 1 1 .names inst_AS_000_INTreg.BLIF AS_000_INT_i 0 1 -.names inst_AS_000_INTreg.BLIF inst_CLK_000_D0.BLIF N_59_i +.names inst_AS_000_INTreg.BLIF inst_CLK_000_D0.BLIF N_48_i 11 1 -.names RST_i.BLIF SM_AMIGA_5_.AR -1 1 -.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF N_60_i +.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF N_49_i 11 1 -.names CLK_000_D0_i.BLIF state_machine_un6_clk_000_d4_i_n.BLIF N_61_i -11 1 -.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_62_i -11 1 -.names DS_030_c_i.BLIF N_51.BLIF N_63_i -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C -1 1 -.names N_52_i.BLIF N_145_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 -11 1 -.names CLK_000_D0_i.BLIF N_58_i.BLIF N_65_0 -11 1 -.names RST_i.BLIF SM_AMIGA_4_.AR -1 1 -.names AS_030_i.BLIF N_76_i.BLIF N_164_0 -11 1 -.names AS_030_i.BLIF N_77_i.BLIF N_165_0 -11 1 -.names N_79_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0.BLIF N_30_0 -11 1 -.names a_i_0__n.BLIF N_63_i.BLIF state_machine_uds_000_int_5_0_n -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C -1 1 -.names N_63_i.BLIF N_81_i.BLIF state_machine_lds_000_int_5_0_n -11 1 -.names N_83_i.BLIF N_85_i.BLIF SM_AMIGA_6_.D -11 1 -.names RST_i.BLIF SM_AMIGA_3_.AR -1 1 -.names inst_CLK_000_D0.BLIF N_86_i.BLIF SM_AMIGA_5_.D -11 1 -.names CLK_000_D0_i.BLIF N_88_i.BLIF SM_AMIGA_4_.D -11 1 -.names N_89_i.BLIF N_90_i.BLIF SM_AMIGA_3_.D -11 1 -.names N_94_i.BLIF N_97_i.BLIF sm_amiga_ns_0_5__n -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C -1 1 -.names N_98_i.BLIF N_114_i.BLIF N_39_0 -11 1 -.names N_115_i.BLIF N_116_i.BLIF sm_amiga_ns_0_7__n -11 1 -.names RST_i.BLIF SM_AMIGA_2_.AR -1 1 -.names N_117_i.BLIF N_118_i.BLIF N_123_i -11 1 -.names N_58.BLIF N_119_i.BLIF N_43_i -11 1 -.names N_141_i.BLIF N_142_i.BLIF N_14_0 -11 1 -.names N_60.BLIF cpu_est_i_0__n.BLIF N_121 +.names AS_030_i.BLIF N_55.BLIF N_50_i 11 1 .names CLK_OSZI_c.BLIF SM_AMIGA_1_.C 1 1 -.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_122 -11 1 -.names N_55_i.BLIF cpu_est_3_reg.BLIF N_124 +.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n +0 1 +.names SM_AMIGA_6_.BLIF nEXP_SPACE_c.BLIF N_54_i 11 1 .names RST_i.BLIF SM_AMIGA_1_.AR 1 1 -.names N_62.BLIF cpu_est_3_reg.BLIF N_125 -11 1 -.names N_62_i.BLIF cpu_est_i_2__n.BLIF N_178 -11 1 -.names CLK_000_D0_i.BLIF N_145.BLIF N_139 -11 1 -.names N_59_i.BLIF SM_AMIGA_0_.BLIF N_140 +.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n +0 1 +.names state_machine_un6_clk_000_d4_n.BLIF state_machine_un6_clk_000_d4_i_n +0 1 +.names SM_AMIGA_1_.BLIF state_machine_un6_clk_000_d4_n.BLIF N_55_i 11 1 +.names cpu_est_3_reg.BLIF cpu_est_i_3__n +0 1 .names CLK_OSZI_c.BLIF SM_AMIGA_0_.C 1 1 -.names N_56.BLIF cpu_est_0_.BLIF N_141 +.names cpu_est_3_reg.BLIF cpu_est_i_1__n.BLIF N_57_i 11 1 -.names N_56_i.BLIF cpu_est_i_0__n.BLIF N_142 +.names DS_030_c_i.BLIF N_47.BLIF N_58_i 11 1 .names RST_i.BLIF SM_AMIGA_0_.AR 1 1 -.names SM_AMIGA_6_.BLIF nEXP_SPACE_i.BLIF N_145 +.names N_68_i.BLIF N_69_i.BLIF state_machine_un15_clk_000_d0_0_n 11 1 -.names N_60_i.BLIF cpu_est_0_.BLIF N_146 +.names AS_030_i.BLIF N_70_i.BLIF N_204_0 11 1 -.names BGACK_000_c.BLIF N_56.BLIF state_machine_un6_bgack_000_0_n +.names AS_030_i.BLIF N_71_i.BLIF N_205_0 11 1 -.names AS_030_i.BLIF N_63.BLIF N_162_0 +.names AS_030_i.BLIF N_72_i.BLIF N_23_0 11 1 -.names CLK_OSZI_c.BLIF CLK_CNT_0_.C +.names CLK_OSZI_i.BLIF CLK_CNT_N_0_.C 1 1 -.names N_72_i.BLIF N_73_i.BLIF state_machine_un15_clk_000_d0_0_n +.names N_73_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0.BLIF N_27_0 11 1 -.names AS_030_i.BLIF N_75_i.BLIF N_163_0 +.names a_i_0__n.BLIF N_58_i.BLIF state_machine_uds_000_int_5_0_n 11 1 -.names state_machine_un8_clk_000_d2_n.BLIF state_machine_un8_clk_000_d2_i_n +.names RST_i.BLIF CLK_CNT_N_0_.AR +1 1 +.names N_58_i.BLIF N_75_i.BLIF state_machine_lds_000_int_5_0_n +11 1 +.names N_77_i.BLIF N_79_i.BLIF SM_AMIGA_6_.D +11 1 +.names inst_CLK_000_D0.BLIF N_81_i.BLIF SM_AMIGA_5_.D +11 1 +.names CLK_CNT_N_0_.BLIF CLK_CNT_N_1_.D +1 1 +.names CLK_000_D0_i.BLIF N_82_i.BLIF SM_AMIGA_4_.D +11 1 +.names N_84_i.BLIF N_130_i.BLIF SM_AMIGA_3_.D +11 1 +.names CLK_OSZI_i.BLIF CLK_CNT_N_1_.C +1 1 +.names N_85_i.BLIF N_86_i.BLIF sm_amiga_ns_0_5__n +11 1 +.names N_93_i.BLIF N_94_i.BLIF SM_AMIGA_1_.D +11 1 +.names RST_i.BLIF CLK_CNT_N_1_.AR +1 1 +.names N_214_i.BLIF N_215_i.BLIF sm_amiga_ns_0_7__n +11 1 +.names N_127_i.BLIF N_220_i.BLIF N_157_i +11 1 +.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_223 +11 1 +.names cpu_est_0_.BLIF cpu_est_3_reg.BLIF N_225 +11 1 +.names CLK_OSZI_c.BLIF CLK_CNT_P_0_.C +1 1 +.names CLK_000_D0_i.BLIF N_129.BLIF N_226 +11 1 +.names N_48_i.BLIF SM_AMIGA_0_.BLIF N_227 +11 1 +.names RST_i.BLIF CLK_CNT_P_0_.AR +1 1 +.names N_49.BLIF cpu_est_0_.BLIF N_122 +11 1 +.names N_49_i.BLIF cpu_est_i_0__n.BLIF N_123 +11 1 +.names cpu_est_0_.BLIF cpu_est_i_0__n 0 1 -.names SM_AMIGA_7_.BLIF state_machine_un8_clk_000_d2_i_n.BLIF N_85 -11 1 -.names CLK_OSZI_c.BLIF CLK_CNT_1_.C +.names CLK_CNT_P_0_.BLIF CLK_CNT_P_1_.D 1 1 -.names sm_amiga_i_5__n.BLIF sm_amiga_i_6__n.BLIF N_86 +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_126 11 1 -.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +.names N_126.BLIF cpu_est_i_3__n.BLIF N_127 +11 1 +.names CLK_OSZI_c.BLIF CLK_CNT_P_1_.C +1 1 +.names cpu_est_1_.BLIF cpu_est_i_1__n 0 1 -.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_88 +.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_128 11 1 -.names CLK_000_D0_i.BLIF N_66.BLIF N_89 -11 1 -.names CLK_OSZI_c.BLIF cpu_est_0_.C +.names RST_i.BLIF CLK_CNT_P_1_.AR 1 1 -.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n +.names SM_AMIGA_6_.BLIF nEXP_SPACE_i.BLIF N_129 +11 1 +.names CLK_000_D0_i.BLIF state_machine_un23_clk_000_d0_n.BLIF N_130 +11 1 +.names BGACK_000_c.BLIF N_49.BLIF state_machine_un6_bgack_000_0_n +11 1 +.names AS_030_i.BLIF N_58.BLIF N_203_0 +11 1 +.names CLK_OSZI_c.BLIF IPL_030DFFSH_0_reg.C +1 1 +.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n 0 1 -.names sm_amiga_i_3__n.BLIF sm_amiga_i_4__n.BLIF N_90 +.names N_61.BLIF sm_amiga_i_3__n.BLIF N_84 11 1 -.names CLK_000_D0_i.BLIF SM_AMIGA_2_.BLIF N_94 -11 1 -.names N_61.BLIF SM_AMIGA_1_.BLIF N_98 -11 1 -.names CLK_OSZI_c.BLIF cpu_est_1_.C +.names RST_i.BLIF IPL_030DFFSH_0_reg.AP 1 1 -.names inst_CLK_000_D0.BLIF SM_AMIGA_2_.BLIF N_114 +.names CLK_000_D0_i.BLIF SM_AMIGA_2_.BLIF N_85 11 1 -.names N_59.BLIF SM_AMIGA_0_.BLIF N_115 +.names N_130.BLIF SM_AMIGA_3_.BLIF N_86 11 1 -.names N_61_i.BLIF SM_AMIGA_1_.BLIF N_116 +.names CLK_000_D0_i.BLIF N_55.BLIF N_93 11 1 +.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n +0 1 +.names CLK_OSZI_c.BLIF IPL_030DFFSH_1_reg.C +1 1 +.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_94 +11 1 +.names N_48.BLIF SM_AMIGA_0_.BLIF N_214 +11 1 +.names RST_i.BLIF IPL_030DFFSH_1_reg.AP +1 1 +.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF N_216 +11 1 +.names cpu_est_2_.BLIF cpu_est_i_2__n +0 1 +.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_217 +11 1 +.names N_57.BLIF cpu_est_2_.BLIF N_220 +11 1 +.names CLK_OSZI_c.BLIF IPL_030DFFSH_2_reg.C +1 1 .names AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLE_i 0 1 -.names CLK_OSZI_c.BLIF cpu_est_2_.C -1 1 -.names AS_030.BLIF AS_030_c -1 1 .names AS_030_c.BLIF AS_030_i 0 1 -.names clk_clk_cnt_n.BLIF clk_clk_cnt_i_n -0 1 -.names DS_030.BLIF DS_030_c +.names RST_i.BLIF IPL_030DFFSH_2_reg.AP 1 1 -.names clk_clk_cnt_i_n.BLIF G_96.BLIF CLK_CNT_1_.D +.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_222 11 1 -.names CLK_OSZI_c.BLIF cpu_est_3_reg.C -1 1 -.names SIZE_0_.BLIF size_c_0__n -1 1 -.names SIZE_1_.BLIF size_c_1__n -1 1 -.names BG_030_i.BLIF CLK_030_c.BLIF N_69 -11 1 -.names A_0_.BLIF a_c_0__n -1 1 .names AS_030_i.BLIF sm_amiga_i_5__n.BLIF AS_000_INT_1_sqmuxa 11 1 -.names CLK_OSZI_c.BLIF inst_UDS_000_INTreg.C -1 1 -.names A_16_.BLIF a_c_16__n +.names CLK_OSZI_c.BLIF SM_AMIGA_7_.C 1 1 .names dsack_c_1__n.BLIF dsack_i_1__n 0 1 -.names A_17_.BLIF a_c_17__n -1 1 .names AS_000_INT_i.BLIF dsack_i_1__n.BLIF state_machine_un7_as_000_int_n 11 1 -.names RST_i.BLIF inst_UDS_000_INTreg.AP +.names RST_i.BLIF SM_AMIGA_7_.AP 1 1 -.names A_18_.BLIF a_c_18__n -1 1 -.names SM_AMIGA_1_.BLIF state_machine_un6_clk_000_d4_n.BLIF N_74 +.names CLK_030_c.BLIF N_53_i.BLIF N_71 11 1 -.names A_19_.BLIF a_c_19__n -1 1 -.names CLK_030_c.BLIF N_57_i.BLIF N_76 -11 1 -.names A_20_.BLIF a_c_20__n -1 1 .names a_c_0__n.BLIF a_i_0__n 0 1 -.names A_21_.BLIF a_c_21__n -1 1 .names size_c_1__n.BLIF size_i_1__n 0 1 -.names CLK_OSZI_c.BLIF inst_LDS_000_INTreg.C -1 1 -.names A_22_.BLIF a_c_22__n -1 1 .names SM_AMIGA_7_.BLIF sm_amiga_i_7__n 0 1 -.names A_23_.BLIF a_c_23__n +.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C 1 1 -.names N_65.BLIF sm_amiga_i_7__n.BLIF N_83 +.names N_60.BLIF sm_amiga_i_7__n.BLIF N_77 11 1 -.names RST_i.BLIF inst_LDS_000_INTreg.AP -1 1 -.names A_24_.BLIF a_c_24__n -1 1 -.names a_c_16__n.BLIF a_i_16__n +.names state_machine_un8_clk_000_d2_n.BLIF state_machine_un8_clk_000_d2_i_n 0 1 -.names A_25_.BLIF a_c_25__n +.names RST_i.BLIF SM_AMIGA_6_.AR 1 1 -.names a_c_18__n.BLIF a_i_18__n -0 1 -.names A_26_.BLIF a_c_26__n -1 1 -.names a_c_19__n.BLIF a_i_19__n -0 1 -.names A_27_.BLIF a_c_27__n -1 1 -.names a_c_24__n.BLIF a_i_24__n -0 1 -.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C -1 1 -.names A_28_.BLIF a_c_28__n -1 1 -.names a_c_25__n.BLIF a_i_25__n -0 1 -.names A_29_.BLIF a_c_29__n -1 1 -.names a_c_26__n.BLIF a_i_26__n -0 1 -.names RST_i.BLIF inst_VMA_INTreg.AP -1 1 -.names A_30_.BLIF a_c_30__n -1 1 -.names a_c_27__n.BLIF a_i_27__n -0 1 -.names A_31_.BLIF a_c_31__n -1 1 -.names a_c_28__n.BLIF a_i_28__n -0 1 -.names nEXP_SPACE.BLIF nEXP_SPACE_c -1 1 -.names a_c_29__n.BLIF a_i_29__n -0 1 -.names a_c_30__n.BLIF a_i_30__n -0 1 -.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C -1 1 -.names BG_030.BLIF BG_030_c -1 1 -.names a_c_31__n.BLIF a_i_31__n -0 1 -.names BG_000DFFSHreg.BLIF BG_000 -1 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i -0 1 -.names RST_i.BLIF BG_000DFFSHreg.AP -1 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030 -1 1 -.names inst_CLK_000_D2.BLIF CLK_000_D2_i -0 1 -.names BGACK_000.BLIF BGACK_000_c -1 1 -.names CLK_CNT_0_.BLIF clk_cnt_i_0__n -0 1 -.names CLK_030.BLIF CLK_030_c -1 1 -.names clk_cnt_i_0__n.BLIF clk_clk_cnt_i_n.BLIF CLK_CNT_0_.D +.names SM_AMIGA_7_.BLIF state_machine_un8_clk_000_d2_i_n.BLIF N_79 11 1 -.names CLK_000.BLIF inst_CLK_000_D0.D +.names sm_amiga_i_5__n.BLIF sm_amiga_i_6__n.BLIF N_81 +11 1 +.names AS_030.BLIF AS_030_c 1 1 -.names state_machine_un7_as_000_int_n.BLIF inst_DTACK_DMA.D +.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n 0 1 -.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE.C +.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_82 +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C 1 1 -.names CLK_OSZI.BLIF CLK_OSZI_c +.names DS_030.BLIF DS_030_c 1 1 .names RST_c.BLIF RST_i 0 1 -.names CLK_OUT_INTreg.BLIF CLK_DIV_OUT -1 1 -.names G_92.BLIF N_137_i +.names a_c_16__n.BLIF a_i_16__n 0 1 -.names CLK_OUT_INTreg.BLIF CLK_EXP +.names RST_i.BLIF SM_AMIGA_5_.AR 1 1 -.names clk_cnt_i_0__n.BLIF N_137_i.BLIF clk_clk_cnt_n -11 1 -.names inst_FPU_CS_INTreg.BLIF FPU_CS -1 1 -.names N_163.BLIF vpa_sync_0_un3_n +.names a_c_18__n.BLIF a_i_18__n 0 1 -.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C +.names SIZE_0_.BLIF size_c_0__n 1 1 -.names IPL_030DFFSH_0_reg.BLIF IPL_030_0_ -1 1 -.names N_75_i.BLIF N_163.BLIF vpa_sync_0_un1_n -11 1 -.names IPL_030DFFSH_1_reg.BLIF IPL_030_1_ -1 1 -.names inst_VPA_SYNC.BLIF vpa_sync_0_un3_n.BLIF vpa_sync_0_un0_n -11 1 -.names RST_i.BLIF inst_BGACK_030_INTreg.AP -1 1 -.names IPL_030DFFSH_2_reg.BLIF IPL_030_2_ -1 1 -.names vpa_sync_0_un1_n.BLIF vpa_sync_0_un0_n.BLIF inst_VPA_SYNC.D -1- 1 --1 1 -.names IPL_0_.BLIF ipl_c_0__n -1 1 -.names RST_c.BLIF amiga_bus_enable_0_un3_n +.names a_c_19__n.BLIF a_i_19__n 0 1 -.names IPL_1_.BLIF ipl_c_1__n +.names SIZE_1_.BLIF size_c_1__n 1 1 -.names N_43_i.BLIF RST_c.BLIF amiga_bus_enable_0_un1_n -11 1 -.names IPL_2_.BLIF ipl_c_2__n -1 1 -.names AMIGA_BUS_ENABLEDFFreg.BLIF amiga_bus_enable_0_un3_n.BLIF amiga_bus_enable_0_un0_n -11 1 -.names CLK_OSZI_c.BLIF inst_AS_000_INTreg.C -1 1 -.names amiga_bus_enable_0_un1_n.BLIF amiga_bus_enable_0_un0_n.BLIF AMIGA_BUS_ENABLEDFFreg.D -1- 1 --1 1 -.names N_162.BLIF uds_000_int_0_un3_n +.names a_c_24__n.BLIF a_i_24__n 0 1 -.names RST_i.BLIF inst_AS_000_INTreg.AP +.names A_0_.BLIF a_c_0__n 1 1 -.names state_machine_uds_000_int_5_n.BLIF N_162.BLIF uds_000_int_0_un1_n -11 1 -.names vcc_n_n.BLIF AVEC -1 1 -.names inst_UDS_000_INTreg.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n -11 1 -.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INTreg.D -1- 1 --1 1 -.names cpu_est_3_reg.BLIF E -1 1 -.names N_162.BLIF lds_000_int_0_un3_n +.names a_c_25__n.BLIF a_i_25__n 0 1 -.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C +.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C 1 1 -.names VPA.BLIF inst_VPA_D.D +.names A_16_.BLIF a_c_16__n 1 1 -.names state_machine_lds_000_int_5_n.BLIF N_162.BLIF lds_000_int_0_un1_n +.names a_c_26__n.BLIF a_i_26__n +0 1 +.names A_17_.BLIF a_c_17__n +1 1 +.names a_c_27__n.BLIF a_i_27__n +0 1 +.names RST_i.BLIF SM_AMIGA_4_.AR +1 1 +.names A_18_.BLIF a_c_18__n +1 1 +.names a_c_28__n.BLIF a_i_28__n +0 1 +.names A_19_.BLIF a_c_19__n +1 1 +.names a_c_29__n.BLIF a_i_29__n +0 1 +.names A_20_.BLIF a_c_20__n +1 1 +.names a_c_30__n.BLIF a_i_30__n +0 1 +.names A_21_.BLIF a_c_21__n +1 1 +.names a_c_31__n.BLIF a_i_31__n +0 1 +.names CLK_OSZI_c.BLIF inst_UDS_000_INTreg.C +1 1 +.names A_22_.BLIF a_c_22__n +1 1 +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +0 1 +.names A_23_.BLIF a_c_23__n +1 1 +.names inst_CLK_000_D2.BLIF CLK_000_D2_i +0 1 +.names RST_i.BLIF inst_UDS_000_INTreg.AP +1 1 +.names A_24_.BLIF a_c_24__n +1 1 +.names state_machine_un7_as_000_int_n.BLIF inst_DTACK_DMA.D +0 1 +.names A_25_.BLIF a_c_25__n +1 1 +.names state_machine_un10_bg_030_n.BLIF BG_000DFFSHreg.D +0 1 +.names A_26_.BLIF a_c_26__n +1 1 +.names G_102.BLIF CLK_CNT_N_0_.D +0 1 +.names A_27_.BLIF a_c_27__n +1 1 +.names CLK_OSZI_c.BLIF CLK_OSZI_i +0 1 +.names CLK_OSZI_c.BLIF inst_LDS_000_INTreg.C +1 1 +.names A_28_.BLIF a_c_28__n +1 1 +.names G_108.BLIF CLK_CNT_P_0_.D +0 1 +.names A_29_.BLIF a_c_29__n +1 1 +.names N_203.BLIF lds_000_int_0_un3_n +0 1 +.names RST_i.BLIF inst_LDS_000_INTreg.AP +1 1 +.names A_30_.BLIF a_c_30__n +1 1 +.names state_machine_lds_000_int_5_n.BLIF N_203.BLIF lds_000_int_0_un1_n 11 1 -.names inst_VMA_INTreg.BLIF VMA +.names A_31_.BLIF a_c_31__n 1 1 .names inst_LDS_000_INTreg.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n 11 1 -.names RST_i.BLIF inst_AS_030_000_SYNC.AP -1 1 -.names RST.BLIF RST_c +.names nEXP_SPACE.BLIF nEXP_SPACE_c 1 1 .names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF inst_LDS_000_INTreg.D 1- 1 -1 1 -.names RESETDFFreg.BLIF RESET +.names N_70.BLIF N_70_i +0 1 +.names CLK_OSZI_c.BLIF inst_VPA_SYNC.C +1 1 +.names BG_030.BLIF BG_030_c +1 1 +.names N_204.BLIF vpa_sync_0_un3_n +0 1 +.names BG_000DFFSHreg.BLIF BG_000 +1 1 +.names N_70_i.BLIF N_204.BLIF vpa_sync_0_un1_n +11 1 +.names RST_i.BLIF inst_VPA_SYNC.AP +1 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030 +1 1 +.names inst_VPA_SYNC.BLIF vpa_sync_0_un3_n.BLIF vpa_sync_0_un0_n +11 1 +.names BGACK_000.BLIF BGACK_000_c +1 1 +.names vpa_sync_0_un1_n.BLIF vpa_sync_0_un0_n.BLIF inst_VPA_SYNC.D +1- 1 +-1 1 +.names CLK_030.BLIF CLK_030_c 1 1 .names state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un3_n 0 1 -.names RW.BLIF RW_c +.names CLK_000.BLIF inst_CLK_000_D0.D 1 1 -.names cpu_est_1_.BLIF state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un1_n +.names N_48_i.BLIF state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un1_n 11 1 -.names FC_0_.BLIF fc_c_0__n +.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C +1 1 +.names CLK_OSZI.BLIF CLK_OSZI_c 1 1 .names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n 11 1 -.names CLK_OSZI_c.BLIF inst_DTACK_SYNC.C -1 1 -.names FC_1_.BLIF fc_c_1__n +.names CLK_OUT_INTreg.BLIF CLK_DIV_OUT 1 1 .names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D 1- 1 -1 1 -.names AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLE +.names RST_i.BLIF inst_VMA_INTreg.AP 1 1 -.names N_120.BLIF N_120_i -0 1 -.names RST_i.BLIF inst_DTACK_SYNC.AP +.names CLK_OUT_INTreg.BLIF CLK_EXP 1 1 -.names RW_i.BLIF AMIGA_BUS_DATA_DIR -1 1 -.names N_69.BLIF bg_000_0_un3_n -0 1 -.names vcc_n_n.BLIF AMIGA_BUS_ENABLE_LOW -1 1 -.names BG_000DFFSHreg.BLIF N_69.BLIF bg_000_0_un1_n -11 1 -.names N_120_i.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n -11 1 -.names N_178_i.BLIF N_125_i.BLIF clk_cpu_est_11_0_1_3__n -11 1 -.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF BG_000DFFSHreg.D -1- 1 --1 1 -.names CLK_OSZI_c.BLIF inst_FPU_CS_INTreg.C -1 1 -.names clk_cpu_est_11_0_1_3__n.BLIF N_138_i.BLIF clk_cpu_est_11_0_3__n -11 1 .names state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n 0 1 -.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_138_1 -11 1 +.names inst_FPU_CS_INTreg.BLIF FPU_CS +1 1 .names BGACK_000_c.BLIF state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n 11 1 -.names RST_i.BLIF inst_FPU_CS_INTreg.AP +.names IPL_030DFFSH_0_reg.BLIF IPL_030_0_ 1 1 -.names N_138_1.BLIF cpu_est_i_2__n.BLIF N_138 -11 1 .names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un0_n 11 1 -.names AMIGA_BUS_ENABLE_i.BLIF AS_030_i.BLIF N_119_1 -11 1 +.names IPL_030DFFSH_1_reg.BLIF IPL_030_1_ +1 1 .names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF inst_BGACK_030_INTreg.D 1- 1 -1 1 -.names N_119_1.BLIF sm_amiga_i_6__n.BLIF N_119 -11 1 +.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C +1 1 +.names IPL_030DFFSH_2_reg.BLIF IPL_030_2_ +1 1 .names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n 0 1 -.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_118_1 -11 1 +.names IPL_0_.BLIF ipl_c_0__n +1 1 .names inst_AS_000_INTreg.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n 11 1 -.names CLK_OSZI_c.BLIF DSACK_INT_1_.C +.names RST_i.BLIF inst_BGACK_030_INTreg.AP +1 1 +.names IPL_1_.BLIF ipl_c_1__n 1 1 -.names N_118_1.BLIF cpu_est_i_2__n.BLIF N_118 -11 1 .names sm_amiga_i_5__n.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n 11 1 -.names N_55.BLIF cpu_est_0_.BLIF N_117_1 -11 1 +.names IPL_2_.BLIF ipl_c_2__n +1 1 .names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF inst_AS_000_INTreg.D 1- 1 -1 1 -.names RST_i.BLIF DSACK_INT_1_.AP -1 1 -.names N_117_1.BLIF cpu_est_i_3__n.BLIF N_117 -11 1 -.names N_56.BLIF cpu_est_0_1__un3_n +.names N_49.BLIF ipl_030_0_0__un3_n 0 1 -.names CLK_000_D0_i.BLIF SM_AMIGA_3_.BLIF N_97_1 +.names IPL_030DFFSH_0_reg.BLIF N_49.BLIF ipl_030_0_0__un1_n 11 1 -.names cpu_est_1_.BLIF N_56.BLIF cpu_est_0_1__un1_n -11 1 -.names N_97_1.BLIF state_machine_un23_clk_000_d0_n.BLIF N_97 -11 1 -.names clk_cpu_est_11_1__n.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n -11 1 -.names a_i_0__n.BLIF size_c_0__n.BLIF N_81_1 -11 1 -.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D -1- 1 --1 1 -.names CLK_OSZI_c.BLIF inst_VPA_SYNC.C +.names CLK_OSZI_c.BLIF inst_AS_000_INTreg.C 1 1 -.names N_81_1.BLIF size_i_1__n.BLIF N_81 -11 1 -.names N_56.BLIF cpu_est_0_2__un3_n -0 1 -.names N_77_1_0.BLIF inst_VPA_D.BLIF N_77 -11 1 -.names cpu_est_2_.BLIF N_56.BLIF cpu_est_0_2__un1_n -11 1 -.names RST_i.BLIF inst_VPA_SYNC.AP -1 1 -.names N_77_1.BLIF VMA_INT_i.BLIF N_75_1 -11 1 -.names N_123_i.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n -11 1 -.names VPA_D_i.BLIF cpu_est_2_.BLIF N_75_2 -11 1 -.names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D -1- 1 --1 1 -.names cpu_est_3_reg.BLIF cpu_est_i_0__n.BLIF N_75_3 -11 1 -.names N_56.BLIF cpu_est_0_3__un3_n -0 1 -.names N_75_1.BLIF N_75_2.BLIF N_75_4 -11 1 -.names cpu_est_3_reg.BLIF N_56.BLIF cpu_est_0_3__un1_n -11 1 -.names CLK_OSZI_c.BLIF AMIGA_BUS_ENABLEDFFreg.C -1 1 -.names N_75_3.BLIF cpu_est_i_1__n.BLIF N_75_5 -11 1 -.names clk_cpu_est_11_3__n.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n -11 1 -.names N_75_4.BLIF N_75_5.BLIF N_75 -11 1 -.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_reg.D -1- 1 --1 1 -.names N_55_i.BLIF N_59_i.BLIF N_73_1 -11 1 -.names N_56.BLIF ipl_030_0_0__un3_n -0 1 -.names inst_CLK_000_D4.BLIF inst_CLK_000_D5.D -1 1 -.names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF N_73_2 -11 1 -.names IPL_030DFFSH_0_reg.BLIF N_56.BLIF ipl_030_0_0__un1_n -11 1 -.names N_73_1.BLIF N_73_2.BLIF N_73 -11 1 .names ipl_c_0__n.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n 11 1 -.names CLK_OSZI_c.BLIF inst_CLK_000_D5.C +.names vcc_n_n.BLIF AVEC 1 1 -.names CLK_000_D0_i.BLIF N_146.BLIF N_72_1 -11 1 .names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF IPL_030DFFSH_0_reg.D 1- 1 -1 1 -.names VPA_D_i.BLIF cpu_est_2_.BLIF N_72_2 -11 1 -.names N_56.BLIF ipl_030_0_1__un3_n +.names RST_i.BLIF inst_AS_000_INTreg.AP +1 1 +.names N_49.BLIF ipl_030_0_1__un3_n 0 1 -.names N_72_1.BLIF N_72_2.BLIF N_72 -11 1 -.names IPL_030DFFSH_1_reg.BLIF N_56.BLIF ipl_030_0_1__un1_n -11 1 -.names N_140_i.BLIF N_85_i.BLIF sm_amiga_ns_0_1_0__n +.names cpu_est_3_reg.BLIF E +1 1 +.names IPL_030DFFSH_1_reg.BLIF N_49.BLIF ipl_030_0_1__un1_n 11 1 +.names VPA.BLIF inst_VPA_D.D +1 1 .names ipl_c_1__n.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n 11 1 -.names CLK_OSZI_c.BLIF inst_DTACK_DMA.C +.names inst_VMA_INTreg.BLIF VMA 1 1 -.names sm_amiga_ns_0_1_0__n.BLIF N_139_i.BLIF sm_amiga_ns_0_0__n -11 1 .names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF IPL_030DFFSH_1_reg.D 1- 1 -1 1 -.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_57_i_2 -11 1 -.names N_56.BLIF ipl_030_0_2__un3_n -0 1 -.names RST_i.BLIF inst_DTACK_DMA.AP +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE.C 1 1 -.names a_i_19__n.BLIF a_i_16__n.BLIF N_57_i_3 -11 1 -.names IPL_030DFFSH_2_reg.BLIF N_56.BLIF ipl_030_0_2__un1_n -11 1 -.names N_57_i_1.BLIF N_57_i_2.BLIF N_57_i_4 +.names RST.BLIF RST_c +1 1 +.names N_49.BLIF ipl_030_0_2__un3_n +0 1 +.names RESETDFFRHreg.BLIF RESET +1 1 +.names IPL_030DFFSH_2_reg.BLIF N_49.BLIF ipl_030_0_2__un1_n 11 1 +.names RST_i.BLIF inst_CLK_OUT_PRE.AR +1 1 +.names RW.BLIF RW_c +1 1 .names ipl_c_2__n.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n 11 1 -.names N_57_i_3.BLIF a_i_18__n.BLIF N_57_i_5 -11 1 +.names FC_0_.BLIF fc_c_0__n +1 1 .names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF IPL_030DFFSH_2_reg.D 1- 1 -1 1 -.names inst_CLK_OUT_PRE.BLIF CLK_OUT_INTreg.D +.names FC_1_.BLIF fc_c_1__n 1 1 -.names N_57_i_4.BLIF N_57_i_5.BLIF N_57_i -11 1 -.names N_121_i.BLIF N_122_i.BLIF clk_cpu_est_11_0_1_1__n -11 1 -.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF state_machine_un23_clk_000_d0_i_n +.names N_49.BLIF cpu_estse_0_un3_n +0 1 +.names AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLE +1 1 +.names cpu_est_1_.BLIF N_49.BLIF cpu_estse_0_un1_n 11 1 .names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C 1 1 -.names N_124_i.BLIF N_146_i.BLIF clk_cpu_est_11_0_2_1__n +.names RW_i.BLIF AMIGA_BUS_DATA_DIR +1 1 +.names cpu_est_ns_1__n.BLIF cpu_estse_0_un3_n.BLIF cpu_estse_0_un0_n +11 1 +.names vcc_n_n.BLIF AMIGA_BUS_ENABLE_LOW +1 1 +.names cpu_estse_0_un1_n.BLIF cpu_estse_0_un0_n.BLIF cpu_est_1_.D +1- 1 +-1 1 +.names RST_i.BLIF CLK_OUT_INTreg.AR +1 1 +.names N_49.BLIF cpu_estse_1_un3_n +0 1 +.names N_70_3.BLIF VPA_D_i.BLIF N_70 +11 1 +.names cpu_est_2_.BLIF N_49.BLIF cpu_estse_1_un1_n +11 1 +.names N_227_i.BLIF N_79_i.BLIF sm_amiga_ns_0_1_0__n +11 1 +.names cpu_est_ns_2__n.BLIF cpu_estse_1_un3_n.BLIF cpu_estse_1_un0_n +11 1 +.names sm_amiga_ns_0_1_0__n.BLIF N_226_i.BLIF sm_amiga_ns_0_0__n +11 1 +.names cpu_estse_1_un1_n.BLIF cpu_estse_1_un0_n.BLIF cpu_est_2_.D +1- 1 +-1 1 +.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C +1 1 +.names N_225_i.BLIF N_222_i.BLIF cpu_est_ns_0_1_2__n +11 1 +.names N_49.BLIF cpu_estse_2_un3_n +0 1 +.names cpu_est_ns_0_1_2__n.BLIF N_223_i.BLIF cpu_est_ns_0_2__n +11 1 +.names cpu_est_3_reg.BLIF N_49.BLIF cpu_estse_2_un1_n +11 1 +.names RST_i.BLIF inst_AS_030_000_SYNC.AP +1 1 +.names AMIGA_BUS_ENABLE_i.BLIF AS_030_i.BLIF N_221_1 +11 1 +.names N_157_i.BLIF cpu_estse_2_un3_n.BLIF cpu_estse_2_un0_n +11 1 +.names N_221_1.BLIF sm_amiga_i_6__n.BLIF N_221 +11 1 +.names cpu_estse_2_un1_n.BLIF cpu_estse_2_un0_n.BLIF cpu_est_3_reg.D +1- 1 +-1 1 +.names CLK_000_D0_i.BLIF SM_AMIGA_1_.BLIF N_215_1 +11 1 +.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF state_machine_un23_clk_000_d0_0_n +11 1 +.names N_215_1.BLIF state_machine_un6_clk_000_d4_i_n.BLIF N_215 11 1 .names inst_CLK_000_D5.BLIF CLK_000_D5_i 0 1 -.names clk_cpu_est_11_0_1_1__n.BLIF clk_cpu_est_11_0_2_1__n.BLIF clk_cpu_est_11_0_1__n +.names CLK_OSZI_c.BLIF inst_DTACK_SYNC.C +1 1 +.names a_i_0__n.BLIF size_c_0__n.BLIF N_75_1 11 1 .names inst_CLK_000_D4.BLIF CLK_000_D5_i.BLIF state_machine_un6_clk_000_d4_n 11 1 -.names AS_030_c.BLIF BG_030_i.BLIF N_120_1 +.names N_75_1.BLIF size_i_1__n.BLIF N_75 11 1 .names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i 0 1 -.names inst_CLK_000_D3.BLIF inst_CLK_000_D4.D +.names RST_i.BLIF inst_DTACK_SYNC.AP 1 1 -.names SM_AMIGA_7_.BLIF nEXP_SPACE_i.BLIF N_120_2 +.names N_48_i.BLIF N_127.BLIF N_69_1 11 1 .names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i 0 1 -.names N_120_1.BLIF N_120_2.BLIF N_120 +.names N_69_1.BLIF cpu_est_2_.BLIF N_69 11 1 -.names N_30.BLIF as_030_000_sync_0_un3_n +.names G_108.BLIF G_102.BLIF inst_CLK_OUT_PRE.D +11 1 +.names CLK_000_D0_i.BLIF N_128.BLIF N_68_1 +11 1 +.names N_27.BLIF as_030_000_sync_0_un3_n 0 1 -.names CLK_OSZI_c.BLIF inst_CLK_000_D4.C +.names N_68_1.BLIF VPA_D_i.BLIF N_68 +11 1 +.names un1_AMIGA_BUS_ENABLE_1_sqmuxa_2.BLIF N_27.BLIF as_030_000_sync_0_un1_n +11 1 +.names CLK_OSZI_c.BLIF inst_FPU_CS_INTreg.C 1 1 -.names CLK_030_c.BLIF N_57.BLIF N_79_1 -11 1 -.names un1_AMIGA_BUS_ENABLE_1_sqmuxa_2.BLIF N_30.BLIF as_030_000_sync_0_un1_n -11 1 -.names SM_AMIGA_7_.BLIF nEXP_SPACE_c.BLIF N_79_2 +.names N_216_i.BLIF N_217_i.BLIF cpu_est_ns_0_2_1__n 11 1 .names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n 11 1 -.names N_79_1.BLIF N_79_2.BLIF N_79 +.names cpu_est_ns_0_1_1__n.BLIF cpu_est_ns_0_2_1__n.BLIF cpu_est_ns_0_1__n 11 1 .names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF inst_AS_030_000_SYNC.D 1- 1 -1 1 -.names inst_CLK_000_D1.BLIF inst_CLK_000_D2.D +.names RST_i.BLIF inst_FPU_CS_INTreg.AP 1 1 -.names DTACK_i.BLIF N_77_1.BLIF N_77_1_0 +.names nEXP_SPACE_i.BLIF AS_030_c.BLIF state_machine_un10_bg_030_1_n 11 1 -.names N_77.BLIF N_77_i +.names N_72.BLIF N_72_i 0 1 -.names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n -0 1 -.names N_165.BLIF dtack_sync_0_un3_n -0 1 -.names CLK_OSZI_c.BLIF inst_CLK_000_D2.C -1 1 -.names state_machine_un23_clk_000_d0_i_n.BLIF state_machine_un23_clk_000_d0_n -0 1 -.names N_77_i.BLIF N_165.BLIF dtack_sync_0_un1_n +.names BG_030_i.BLIF N_49_i.BLIF state_machine_un10_bg_030_2_n 11 1 -.names a_i_24__n.BLIF a_i_25__n.BLIF N_188_1 +.names N_23.BLIF dtack_sync_0_un3_n +0 1 +.names state_machine_un10_bg_030_1_n.BLIF state_machine_un10_bg_030_2_n.BLIF state_machine_un10_bg_030_3_n +11 1 +.names N_72_i.BLIF N_23.BLIF dtack_sync_0_un1_n +11 1 +.names state_machine_un10_bg_030_3_n.BLIF SM_AMIGA_7_.BLIF state_machine_un10_bg_030_n 11 1 .names inst_DTACK_SYNC.BLIF dtack_sync_0_un3_n.BLIF dtack_sync_0_un0_n 11 1 -.names a_i_26__n.BLIF a_i_27__n.BLIF N_188_2 +.names CLK_OSZI_c.BLIF DSACK_INT_1_.C +1 1 +.names CLK_030_c.BLIF N_53.BLIF N_73_1 11 1 .names dtack_sync_0_un1_n.BLIF dtack_sync_0_un0_n.BLIF inst_DTACK_SYNC.D 1- 1 -1 1 -.names inst_CLK_000_D2.BLIF inst_CLK_000_D3.D -1 1 -.names a_i_28__n.BLIF a_i_29__n.BLIF N_188_3 +.names SM_AMIGA_7_.BLIF nEXP_SPACE_c.BLIF N_73_2 11 1 -.names N_164.BLIF fpu_cs_int_0_un3_n +.names N_205.BLIF fpu_cs_int_0_un3_n 0 1 -.names a_i_30__n.BLIF a_i_31__n.BLIF N_188_4 -11 1 -.names AS_030_c.BLIF N_164.BLIF fpu_cs_int_0_un1_n -11 1 -.names CLK_OSZI_c.BLIF inst_CLK_000_D3.C +.names RST_i.BLIF DSACK_INT_1_.AP 1 1 -.names N_188_1.BLIF N_188_2.BLIF N_188_5 +.names N_73_1.BLIF N_73_2.BLIF N_73 +11 1 +.names AS_030_c.BLIF N_205.BLIF fpu_cs_int_0_un1_n +11 1 +.names inst_CLK_000_D0.BLIF DTACK_i.BLIF N_72_1 11 1 .names inst_FPU_CS_INTreg.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un0_n 11 1 -.names N_188_3.BLIF N_188_4.BLIF N_188_6 +.names SM_AMIGA_3_.BLIF inst_VPA_D.BLIF N_72_2 11 1 .names fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF inst_FPU_CS_INTreg.D 1- 1 -1 1 -.names N_188_5.BLIF N_188_6.BLIF N_188 +.names N_72_1.BLIF N_72_2.BLIF N_72 11 1 -.names N_74.BLIF N_74_i +.names N_50.BLIF dsack_int_0_1__un3_n 0 1 -.names a_c_20__n.BLIF a_c_21__n.BLIF N_191_1 -11 1 -.names N_52.BLIF dsack_int_0_1__un3_n -0 1 -.names CLK_OSZI_c.BLIF inst_VPA_D.C +.names CLK_OSZI_c.BLIF AMIGA_BUS_ENABLEDFFreg.C 1 1 -.names a_c_22__n.BLIF a_c_23__n.BLIF N_191_2 +.names inst_CLK_000_D0.BLIF N_57_i.BLIF N_70_1 11 1 -.names N_74_i.BLIF N_52.BLIF dsack_int_0_1__un1_n +.names N_55.BLIF N_50.BLIF dsack_int_0_1__un1_n 11 1 -.names N_191_1.BLIF N_191_2.BLIF N_191 +.names SM_AMIGA_3_.BLIF VMA_INT_i.BLIF N_70_2 11 1 .names DSACK_INT_1_.BLIF dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un0_n 11 1 -.names inst_CLK_000_D3.BLIF AS_030_000_SYNC_i.BLIF state_machine_un8_clk_000_d2_1_n +.names N_70_1.BLIF N_70_2.BLIF N_70_3 11 1 .names dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF DSACK_INT_1_.D 1- 1 -1 1 +.names N_238_1.BLIF N_238_2.BLIF N_238_5 +11 1 +.names RST_c.BLIF amiga_bus_enable_0_un3_n +0 1 +.names CLK_OSZI_c.BLIF inst_DTACK_DMA.C +1 1 +.names N_238_3.BLIF N_238_4.BLIF N_238_6 +11 1 +.names N_41_i.BLIF RST_c.BLIF amiga_bus_enable_0_un1_n +11 1 +.names N_238_5.BLIF N_238_6.BLIF N_238 +11 1 +.names AMIGA_BUS_ENABLEDFFreg.BLIF amiga_bus_enable_0_un3_n.BLIF amiga_bus_enable_0_un0_n +11 1 +.names RST_i.BLIF inst_DTACK_DMA.AP +1 1 +.names a_c_20__n.BLIF a_c_21__n.BLIF N_241_1 +11 1 +.names amiga_bus_enable_0_un1_n.BLIF amiga_bus_enable_0_un0_n.BLIF AMIGA_BUS_ENABLEDFFreg.D +1- 1 +-1 1 +.names a_c_22__n.BLIF a_c_23__n.BLIF N_241_2 +11 1 +.names N_203.BLIF uds_000_int_0_un3_n +0 1 +.names N_241_1.BLIF N_241_2.BLIF N_241 +11 1 +.names state_machine_uds_000_int_5_n.BLIF N_203.BLIF uds_000_int_0_un1_n +11 1 +.names inst_CLK_000_D4.BLIF inst_CLK_000_D5.D +1 1 +.names inst_CLK_000_D3.BLIF AS_030_000_SYNC_i.BLIF state_machine_un8_clk_000_d2_1_n +11 1 +.names inst_UDS_000_INTreg.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n +11 1 .names state_machine_un8_clk_000_d2_1_n.BLIF CLK_000_D2_i.BLIF state_machine_un8_clk_000_d2_n 11 1 -.names N_75.BLIF N_75_i -0 1 -.names CLK_OSZI_c.BLIF inst_CLK_000_D0.C +.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INTreg.D +1- 1 +-1 1 +.names CLK_OSZI_c.BLIF inst_CLK_000_D5.C 1 1 -.names a_c_17__n.BLIF BGACK_000_c.BLIF N_57_i_1 +.names a_c_17__n.BLIF BGACK_000_c.BLIF N_53_i_1 11 1 .names vcc_n_n 1 -.names N_86.BLIF N_86_i -0 1 +.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_53_i_2 +11 1 .names gnd_n_n -.names N_83.BLIF N_83_i -0 1 +.names RST_i.BLIF inst_CLK_000_D5.AP +1 1 +.names a_i_19__n.BLIF a_i_16__n.BLIF N_53_i_3 +11 1 .names A_15_.BLIF a_15__n 1 1 -.names RST_c.BLIF RESETDFFreg.D -1 1 -.names N_81.BLIF N_81_i -0 1 +.names N_53_i_1.BLIF N_53_i_2.BLIF N_53_i_4 +11 1 .names A_14_.BLIF a_14__n 1 1 -.names state_machine_lds_000_int_5_0_n.BLIF state_machine_lds_000_int_5_n -0 1 +.names N_53_i_3.BLIF a_i_18__n.BLIF N_53_i_5 +11 1 .names A_13_.BLIF a_13__n 1 1 -.names CLK_OSZI_c.BLIF RESETDFFreg.C -1 1 -.names state_machine_uds_000_int_5_0_n.BLIF state_machine_uds_000_int_5_n -0 1 +.names N_53_i_4.BLIF N_53_i_5.BLIF N_53_i +11 1 .names A_12_.BLIF a_12__n 1 1 -.names N_79.BLIF N_79_i -0 1 +.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C +1 1 +.names N_126_i.BLIF N_128_i.BLIF cpu_est_ns_0_1_1__n +11 1 .names A_11_.BLIF a_11__n 1 1 -.names N_30_0.BLIF N_30 +.names N_27_0.BLIF N_27 0 1 .names A_10_.BLIF a_10__n 1 1 -.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D +.names RST_i.BLIF BG_000DFFSHreg.AP 1 1 -.names N_165_0.BLIF N_165 +.names N_23_0.BLIF N_23 0 1 .names A_9_.BLIF a_9__n 1 1 -.names N_76.BLIF N_76_i +.names N_71.BLIF N_71_i 0 1 .names A_8_.BLIF a_8__n 1 1 -.names CLK_OSZI_c.BLIF inst_CLK_000_D1.C -1 1 -.names N_164_0.BLIF N_164 +.names N_205_0.BLIF N_205 0 1 .names A_7_.BLIF a_7__n 1 1 -.names N_163_0.BLIF N_163 +.names inst_CLK_000_D3.BLIF inst_CLK_000_D4.D +1 1 +.names N_204_0.BLIF N_204 0 1 .names A_6_.BLIF a_6__n 1 1 -.names N_72.BLIF N_72_i +.names N_68.BLIF N_68_i 0 1 .names A_5_.BLIF a_5__n 1 1 -.names gnd_n_n.BLIF CLK_REF_1_.D +.names CLK_OSZI_c.BLIF inst_CLK_000_D4.C 1 1 -.names N_73.BLIF N_73_i +.names N_69.BLIF N_69_i 0 1 .names A_4_.BLIF a_4__n 1 1 @@ -1001,108 +918,182 @@ 0 1 .names A_3_.BLIF a_3__n 1 1 -.names gnd_n_n.BLIF CLK_REF_1_.LH +.names RST_i.BLIF inst_CLK_000_D4.AP 1 1 -.names N_162_0.BLIF N_162 +.names N_203_0.BLIF N_203 0 1 .names A_2_.BLIF a_2__n 1 1 -.names N_119.BLIF N_119_i +.names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n 0 1 .names A_1_.BLIF a_1__n 1 1 -.names RST_i.BLIF CLK_REF_1_.AR +.names state_machine_un23_clk_000_d0_0_n.BLIF state_machine_un23_clk_000_d0_n +0 1 +.names inst_CLK_000_D1.BLIF inst_CLK_000_D2.D 1 1 -.names N_117.BLIF N_117_i -0 1 -.names N_118.BLIF N_118_i -0 1 -.names N_115.BLIF N_115_i -0 1 -.names inst_CLK_OUT_PRE.BLIF CLK_OUT_PRE_0.X1 +.names a_i_24__n.BLIF a_i_25__n.BLIF N_238_1 +11 1 +.names a_i_26__n.BLIF a_i_27__n.BLIF N_238_2 +11 1 +.names CLK_OSZI_c.BLIF inst_CLK_000_D2.C +1 1 +.names a_i_28__n.BLIF a_i_29__n.BLIF N_238_3 +11 1 +.names a_i_30__n.BLIF a_i_31__n.BLIF N_238_4 +11 1 +.names RST_i.BLIF inst_CLK_000_D2.AP 1 1 -.names N_116.BLIF N_116_i -0 1 .names sm_amiga_ns_0_7__n.BLIF SM_AMIGA_0_.D 0 1 -.names clk_clk_cnt_n.BLIF CLK_OUT_PRE_0.X2 -1 1 -.names N_98.BLIF N_98_i +.names N_93.BLIF N_93_i 0 1 -.names N_114.BLIF N_114_i -0 1 -.names N_39_0.BLIF SM_AMIGA_1_.D -0 1 -.names CLK_CNT_0_.BLIF G_96.X1 -1 1 .names N_94.BLIF N_94_i 0 1 -.names N_97.BLIF N_97_i +.names inst_CLK_000_D2.BLIF inst_CLK_000_D3.D +1 1 +.names N_85.BLIF N_85_i 0 1 -.names CLK_CNT_1_.BLIF G_96.X2 +.names N_86.BLIF N_86_i +0 1 +.names CLK_OSZI_c.BLIF inst_CLK_000_D3.C 1 1 .names sm_amiga_ns_0_5__n.BLIF SM_AMIGA_2_.D 0 1 -.names N_89.BLIF N_89_i +.names N_84.BLIF N_84_i 0 1 -.names N_90.BLIF N_90_i -0 1 -.names CLK_CNT_1_.BLIF G_92.X1 +.names RST_i.BLIF inst_CLK_000_D3.AP 1 1 -.names N_88.BLIF N_88_i +.names N_130.BLIF N_130_i 0 1 -.names inst_CLK_000_D1.BLIF CLK_000_D1_i +.names N_82.BLIF N_82_i 0 1 -.names CLK_REF_1_.BLIF G_92.X2 +.names N_81.BLIF N_81_i +0 1 +.names N_77.BLIF N_77_i +0 1 +.names CLK_OSZI_c.BLIF inst_VPA_D.C 1 1 -.names N_56_i.BLIF N_56 +.names N_75.BLIF N_75_i 0 1 -.names N_55_i.BLIF N_55 +.names state_machine_lds_000_int_5_0_n.BLIF state_machine_lds_000_int_5_n 0 1 -.names N_52_i.BLIF N_52 -0 1 -.names CLK_OUT_PRE_0.BLIF inst_CLK_OUT_PRE.D +.names RST_i.BLIF inst_VPA_D.AP 1 1 -.names N_141.BLIF N_141_i +.names state_machine_uds_000_int_5_0_n.BLIF state_machine_uds_000_int_5_n 0 1 -.names N_142.BLIF N_142_i +.names N_73.BLIF N_73_i 0 1 -.names N_14_0.BLIF cpu_est_0_.D +.names N_123.BLIF N_123_i 0 1 -.names N_85.BLIF N_85_i +.names cpu_est_ns_e_0_0__n.BLIF cpu_est_0_.D 0 1 -.names N_139.BLIF N_139_i +.names CLK_OSZI_c.BLIF inst_CLK_000_D0.C +1 1 +.names N_79.BLIF N_79_i 0 1 -.names N_140.BLIF N_140_i +.names N_226.BLIF N_226_i +0 1 +.names RST_i.BLIF inst_CLK_000_D0.AP +1 1 +.names N_227.BLIF N_227_i 0 1 .names sm_amiga_ns_0_0__n.BLIF SM_AMIGA_7_.D 0 1 -.names N_125.BLIF N_125_i +.names N_222.BLIF N_222_i 0 1 -.names N_138.BLIF N_138_i +.names vcc_n_n.BLIF RESETDFFRHreg.D +1 1 +.names N_223.BLIF N_223_i 0 1 -.names N_178.BLIF N_178_i +.names N_225.BLIF N_225_i 0 1 -.names clk_cpu_est_11_0_3__n.BLIF clk_cpu_est_11_3__n +.names CLK_OSZI_c.BLIF RESETDFFRHreg.C +1 1 +.names cpu_est_ns_0_2__n.BLIF cpu_est_ns_2__n 0 1 -.names N_121.BLIF N_121_i +.names N_221.BLIF N_221_i 0 1 -.names N_122.BLIF N_122_i +.names RST_i.BLIF RESETDFFRHreg.AR +1 1 +.names N_127.BLIF N_127_i 0 1 -.names N_66_0.BLIF N_66 +.names N_220.BLIF N_220_i 0 1 -.names N_65_0.BLIF N_65 +.names N_214.BLIF N_214_i 0 1 -.names N_145.BLIF N_145_i +.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D +1 1 +.names N_215.BLIF N_215_i 0 1 +.names N_61_0.BLIF N_61 +0 1 +.names CLK_OSZI_c.BLIF inst_CLK_000_D1.C +1 1 +.names N_60_0.BLIF N_60 +0 1 +.names N_129.BLIF N_129_i +0 1 +.names RST_i.BLIF inst_CLK_000_D1.AP +1 1 .names un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2 0 1 .names DS_030_c.BLIF DS_030_c_i 0 1 -.names N_63_i.BLIF N_63 +.names CLK_OSZI_c.BLIF cpu_est_2_.C +1 1 +.names N_58_i.BLIF N_58 0 1 -.names N_62_i.BLIF N_62 +.names CLK_CNT_N_0_.BLIF G_102.X1 +1 1 +.names N_57_i.BLIF N_57 0 1 -.names state_machine_un6_clk_000_d4_n.BLIF state_machine_un6_clk_000_d4_i_n +.names RST_i.BLIF cpu_est_2_.AR +1 1 +.names N_55_i.BLIF N_55 0 1 +.names CLK_CNT_N_1_.BLIF G_102.X2 +1 1 +.names N_54_i.BLIF N_54 +0 1 +.names N_53_i.BLIF N_53 +0 1 +.names N_50_i.BLIF N_50 +0 1 +.names CLK_OSZI_c.BLIF cpu_est_3_reg.C +1 1 +.names CLK_CNT_P_0_.BLIF G_108.X1 +1 1 +.names inst_CLK_000_D1.BLIF CLK_000_D1_i +0 1 +.names N_49_i.BLIF N_49 +0 1 +.names RST_i.BLIF cpu_est_3_reg.AR +1 1 +.names CLK_CNT_P_1_.BLIF G_108.X2 +1 1 +.names N_48_i.BLIF N_48 +0 1 +.names N_122.BLIF N_122_i +0 1 +.names cpu_est_ns_0_1__n.BLIF cpu_est_ns_1__n +0 1 +.names inst_CLK_OUT_PRE.BLIF CLK_OUT_INTreg.D +1 1 +.names N_126.BLIF N_126_i +0 1 +.names CLK_OSZI_c.BLIF cpu_est_0_.C +1 1 +.names N_128.BLIF N_128_i +0 1 +.names N_216.BLIF N_216_i +0 1 +.names RST_i.BLIF cpu_est_0_.AR +1 1 +.names N_217.BLIF N_217_i +0 1 +.names N_50_i.BLIF N_129_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 +11 1 +.names CLK_000_D0_i.BLIF N_54_i.BLIF N_60_0 +11 1 .end diff --git a/Logic/BUS68030.bl1 b/Logic/BUS68030.bl1 index 884c224..6efa5d3 100644 --- a/Logic/BUS68030.bl1 +++ b/Logic/BUS68030.bl1 @@ -1,75 +1,74 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Sat May 24 11:44:09 2014 +#$ DATE Sat May 24 15:48:50 2014 #$ MODULE bus68030 -#$ PINS 74 SIZE_1_ A_31_ IPL_030_2_ IPL_2_ DSACK_1_ FC_1_ AS_030 AS_000 DS_030 UDS_000 \ -# LDS_000 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 SIZE_0_ \ -# CLK_OSZI A_30_ CLK_DIV_OUT A_29_ CLK_EXP A_28_ FPU_CS A_27_ DTACK A_26_ AVEC A_25_ \ -# AVEC_EXP A_24_ E A_23_ VPA A_22_ VMA A_21_ RST A_20_ RESET A_19_ RW A_18_ AMIGA_BUS_ENABLE \ -# A_17_ AMIGA_BUS_DATA_DIR A_16_ AMIGA_BUS_ENABLE_LOW A_15_ CIIN A_14_ A_13_ A_12_ A_11_ \ -# A_10_ A_9_ A_8_ A_7_ A_6_ A_5_ A_4_ A_3_ A_2_ A_1_ A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ IPL_0_ \ +#$ PINS 74 SIZE_1_ A_31_ IPL_030_2_ SIZE_0_ IPL_2_ A_30_ A_29_ DSACK_1_ A_28_ A_27_ \ +# FC_1_ A_26_ AS_030 A_25_ AS_000 A_24_ DS_030 A_23_ UDS_000 A_22_ LDS_000 A_21_ nEXP_SPACE \ +# A_20_ BERR A_19_ BG_030 A_18_ BG_000 A_17_ BGACK_030 A_16_ BGACK_000 A_15_ CLK_030 A_14_ \ +# CLK_000 A_13_ CLK_OSZI A_12_ CLK_DIV_OUT A_11_ CLK_EXP A_10_ FPU_CS A_9_ DTACK A_8_ AVEC \ +# A_7_ AVEC_EXP A_6_ E A_5_ VPA A_4_ VMA A_3_ RST A_2_ RESET A_1_ RW A_0_ AMIGA_BUS_ENABLE \ +# IPL_030_1_ AMIGA_BUS_DATA_DIR IPL_030_0_ AMIGA_BUS_ENABLE_LOW IPL_1_ CIIN IPL_0_ \ # DSACK_0_ FC_0_ -#$ NODES 376 BGACK_000_c CLK_030_c inst_BGACK_030_INTreg inst_FPU_CS_INTreg \ -# CLK_OSZI_c cpu_est_3_reg inst_VMA_INTreg cpu_est_0_ CLK_OUT_INTreg cpu_est_1_ \ -# inst_AS_000_INTreg inst_AS_030_000_SYNC IPL_030DFFSH_0_reg inst_DTACK_SYNC \ -# inst_VPA_D IPL_030DFFSH_1_reg inst_VPA_SYNC inst_CLK_000_D0 IPL_030DFFSH_2_reg \ -# inst_CLK_000_D1 inst_CLK_000_D2 ipl_c_0__n inst_CLK_000_D5 inst_CLK_OUT_PRE \ -# ipl_c_1__n SM_AMIGA_6_ SM_AMIGA_5_ ipl_c_2__n vcc_n_n gnd_n_n cpu_est_2_ dsack_c_1__n \ -# CLK_REF_1_ inst_UDS_000_INTreg DTACK_c inst_LDS_000_INTreg DSACK_INT_1_ SM_AMIGA_7_ \ -# AS_000_INT_1_sqmuxa state_machine_un8_clk_000_d2_n inst_CLK_000_D3 SM_AMIGA_4_ \ -# state_machine_un23_clk_000_d0_n RST_c state_machine_un6_clk_000_d4_n \ -# inst_CLK_000_D4 RESETDFFreg inst_DTACK_DMA clk_clk_cnt_n RW_c CLK_CNT_0_ CLK_CNT_1_ \ -# fc_c_0__n state_machine_un6_bgack_000_n SM_AMIGA_3_ fc_c_1__n SM_AMIGA_1_ \ -# SM_AMIGA_2_ AMIGA_BUS_ENABLEDFFreg SM_AMIGA_0_ state_machine_un7_as_000_int_n \ -# state_machine_un15_clk_000_d0_n clk_cpu_est_11_0_1__n \ -# state_machine_lds_000_int_5_n N_124_i state_machine_uds_000_int_5_n N_146_i \ -# un1_AMIGA_BUS_ENABLE_1_sqmuxa_2 N_121_i N_122_i N_66_0 N_65_0 N_145_i \ -# un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 DS_030_c_i N_63_i N_62_i \ -# state_machine_un6_clk_000_d4_i_n N_61_i CLK_OUT_PRE_0 N_60_i N_59_i N_58_i N_57_i \ -# CLK_000_D1_i N_56_i N_55_i N_52_i N_141_i N_142_i N_14_0 N_85_i N_139_i \ -# clk_cpu_est_11_1__n N_140_i clk_cpu_est_11_3__n sm_amiga_ns_0_0__n G_92 N_125_i G_96 \ -# N_138_i N_162 N_178_i N_163 clk_cpu_est_11_0_3__n N_164 N_119_i N_165 N_43_i N_30 \ -# N_117_i N_118_i N_51 N_123_i N_52 N_115_i N_55 N_116_i N_56 sm_amiga_ns_0_7__n N_57 \ -# N_98_i N_58 N_114_i N_59 N_39_0 N_60 N_94_i N_61 N_97_i N_62 sm_amiga_ns_0_5__n N_63 \ -# N_89_i N_65 N_90_i N_66 N_69 N_88_i N_72 N_73 N_86_i N_74 N_75 N_83_i N_76 N_77 N_81_i N_79 \ -# state_machine_lds_000_int_5_0_n N_81 state_machine_uds_000_int_5_0_n N_83 N_79_i \ -# N_85 N_30_0 N_86 N_165_0 N_88 N_76_i N_89 N_164_0 N_90 N_163_0 N_94 N_72_i N_97 N_73_i N_98 \ -# state_machine_un15_clk_000_d0_0_n N_114 N_162_0 N_115 \ -# state_machine_un6_bgack_000_0_n N_116 state_machine_un23_clk_000_d0_i_n N_117 \ -# N_188_1 N_118 N_188_2 N_119 N_188_3 N_120 N_188_4 N_121 N_188_5 N_122 N_188_6 N_124 \ -# N_191_1 N_125 N_191_2 N_178 state_machine_un8_clk_000_d2_1_n N_138 N_57_i_1 N_139 \ -# N_57_i_2 N_140 N_57_i_3 N_141 N_57_i_4 N_142 N_57_i_5 N_145 clk_cpu_est_11_0_1_1__n \ -# N_146 clk_cpu_est_11_0_2_1__n N_77_1 N_120_1 N_188 N_120_2 N_191 N_79_1 RW_i N_79_2 \ -# VPA_D_i N_77_1_0 CLK_000_D0_i N_75_1 cpu_est_i_0__n N_75_2 cpu_est_i_3__n N_75_3 \ -# VMA_INT_i N_75_4 cpu_est_i_1__n N_75_5 DTACK_i N_73_1 BG_030_i N_73_2 nEXP_SPACE_i \ -# N_72_1 sm_amiga_i_3__n N_72_2 AS_000_INT_i sm_amiga_ns_0_1_0__n sm_amiga_i_6__n \ -# clk_cpu_est_11_0_1_3__n cpu_est_i_2__n N_138_1 AMIGA_BUS_ENABLE_i N_119_1 AS_030_i \ -# N_118_1 sm_amiga_i_4__n N_117_1 sm_amiga_i_5__n N_97_1 \ -# state_machine_un8_clk_000_d2_i_n N_81_1 sm_amiga_i_7__n \ -# state_machine_uds_000_int_5_0_m2_un3_n a_i_0__n \ -# state_machine_uds_000_int_5_0_m2_un1_n size_i_1__n \ -# state_machine_uds_000_int_5_0_m2_un0_n dsack_i_1__n vpa_sync_0_un3_n \ -# clk_clk_cnt_i_n vpa_sync_0_un1_n clk_cnt_i_0__n vpa_sync_0_un0_n CLK_000_D2_i \ -# amiga_bus_enable_0_un3_n AS_030_000_SYNC_i amiga_bus_enable_0_un1_n a_i_30__n \ -# amiga_bus_enable_0_un0_n a_i_31__n uds_000_int_0_un3_n a_i_28__n \ -# uds_000_int_0_un1_n a_i_29__n uds_000_int_0_un0_n a_i_26__n lds_000_int_0_un3_n \ -# a_i_27__n lds_000_int_0_un1_n a_i_24__n lds_000_int_0_un0_n a_i_25__n \ -# vma_int_0_un3_n a_i_19__n vma_int_0_un1_n a_i_16__n vma_int_0_un0_n a_i_18__n \ -# bg_000_0_un3_n N_137_i bg_000_0_un1_n bg_000_0_un0_n RST_i bgack_030_int_0_un3_n \ -# N_120_i bgack_030_int_0_un1_n N_75_i bgack_030_int_0_un0_n N_74_i \ -# as_000_int_0_un3_n N_77_i as_000_int_0_un1_n FPU_CS_INT_i as_000_int_0_un0_n \ -# BGACK_030_INT_i cpu_est_0_1__un3_n CLK_000_D5_i cpu_est_0_1__un1_n AS_030_c \ -# cpu_est_0_1__un0_n cpu_est_0_2__un3_n cpu_est_0_2__un1_n DS_030_c \ -# cpu_est_0_2__un0_n cpu_est_0_3__un3_n cpu_est_0_3__un1_n cpu_est_0_3__un0_n \ -# size_c_0__n ipl_030_0_0__un3_n ipl_030_0_0__un1_n size_c_1__n ipl_030_0_0__un0_n \ -# ipl_030_0_1__un3_n a_c_0__n ipl_030_0_1__un1_n ipl_030_0_1__un0_n \ -# ipl_030_0_2__un3_n ipl_030_0_2__un1_n ipl_030_0_2__un0_n as_030_000_sync_0_un3_n \ -# as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n dtack_sync_0_un3_n \ -# dtack_sync_0_un1_n dtack_sync_0_un0_n fpu_cs_int_0_un3_n fpu_cs_int_0_un1_n \ -# fpu_cs_int_0_un0_n dsack_int_0_1__un3_n dsack_int_0_1__un1_n dsack_int_0_1__un0_n \ -# a_c_16__n a_15__n a_c_17__n a_14__n a_c_18__n a_13__n a_c_19__n a_12__n a_c_20__n \ -# a_11__n a_c_21__n a_10__n a_c_22__n a_9__n a_c_23__n a_8__n a_c_24__n a_7__n a_c_25__n \ -# a_6__n a_c_26__n a_5__n a_c_27__n a_4__n a_c_28__n a_3__n a_c_29__n a_2__n a_c_30__n \ -# a_1__n a_c_31__n nEXP_SPACE_c BG_030_c BG_000DFFSHreg +#$ NODES 357 CLK_OSZI_c CLK_OUT_INTreg IPL_030DFFSH_0_reg inst_BGACK_030_INTreg \ +# inst_FPU_CS_INTreg IPL_030DFFSH_1_reg inst_VMA_INTreg inst_AS_000_INTreg \ +# IPL_030DFFSH_2_reg inst_AS_030_000_SYNC inst_DTACK_SYNC ipl_c_0__n inst_VPA_D \ +# inst_VPA_SYNC ipl_c_1__n inst_CLK_000_D0 inst_CLK_000_D1 ipl_c_2__n inst_CLK_000_D2 \ +# inst_CLK_000_D5 SM_AMIGA_5_ dsack_c_1__n SM_AMIGA_6_ vcc_n_n DTACK_c gnd_n_n \ +# inst_UDS_000_INTreg inst_LDS_000_INTreg DSACK_INT_1_ AS_000_INT_1_sqmuxa \ +# state_machine_un8_clk_000_d2_n inst_CLK_000_D3 SM_AMIGA_4_ RST_c \ +# state_machine_un23_clk_000_d0_n state_machine_un6_clk_000_d4_n RESETDFFRHreg \ +# inst_CLK_000_D4 inst_DTACK_DMA RW_c state_machine_un10_bg_030_n SM_AMIGA_7_ \ +# fc_c_0__n SM_AMIGA_3_ state_machine_un6_bgack_000_n fc_c_1__n SM_AMIGA_1_ G_102 \ +# AMIGA_BUS_ENABLEDFFreg CLK_CNT_N_0_ CLK_CNT_N_1_ G_108 CLK_CNT_P_0_ CLK_CNT_P_1_ \ +# cpu_est_ns_0_1__n SM_AMIGA_2_ N_126_i SM_AMIGA_0_ N_128_i \ +# state_machine_un7_as_000_int_n N_216_i state_machine_un15_clk_000_d0_n N_217_i \ +# state_machine_lds_000_int_5_n N_61_0 state_machine_uds_000_int_5_n N_60_0 \ +# un1_AMIGA_BUS_ENABLE_1_sqmuxa_2 N_129_i inst_CLK_OUT_PRE \ +# un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 DS_030_c_i N_58_i N_57_i N_55_i N_54_i N_53_i \ +# N_50_i CLK_000_D1_i N_49_i N_48_i N_122_i N_123_i cpu_est_ns_e_0_0__n N_79_i N_226_i \ +# N_227_i sm_amiga_ns_0_0__n cpu_est_0_ N_222_i cpu_est_1_ N_223_i cpu_est_2_ N_225_i \ +# cpu_est_3_reg cpu_est_ns_0_2__n N_221_i N_41_i N_127_i N_220_i cpu_est_ns_1__n \ +# N_157_i cpu_est_ns_2__n N_214_i N_203 N_215_i N_204 sm_amiga_ns_0_7__n N_205 N_93_i \ +# N_23 N_94_i N_27 N_47 N_85_i N_48 N_86_i N_49 sm_amiga_ns_0_5__n N_50 N_84_i N_53 N_130_i \ +# N_54 N_55 N_82_i N_57 N_58 N_81_i N_60 N_61 N_77_i N_68 N_69 N_75_i N_70 \ +# state_machine_lds_000_int_5_0_n N_71 state_machine_uds_000_int_5_0_n N_72 N_73_i \ +# N_73 N_27_0 N_75 N_23_0 N_77 N_71_i N_79 N_205_0 N_81 N_204_0 N_82 N_68_i N_84 N_69_i N_85 \ +# state_machine_un15_clk_000_d0_0_n N_86 N_203_0 N_93 \ +# state_machine_un6_bgack_000_0_n N_94 N_214 state_machine_un23_clk_000_d0_0_n N_215 \ +# N_238_1 N_216 N_238_2 N_217 N_238_3 N_220 N_238_4 N_221 N_238_5 N_222 N_238_6 N_223 \ +# N_241_1 N_225 N_241_2 N_226 state_machine_un8_clk_000_d2_1_n N_227 N_53_i_1 N_122 \ +# N_53_i_2 N_123 N_53_i_3 N_126 N_53_i_4 N_127 N_53_i_5 N_128 cpu_est_ns_0_1_1__n N_129 \ +# cpu_est_ns_0_2_1__n N_130 state_machine_un10_bg_030_1_n N_238 \ +# state_machine_un10_bg_030_2_n N_241 state_machine_un10_bg_030_3_n RW_i N_73_1 \ +# VMA_INT_i N_73_2 VPA_D_i N_72_1 DTACK_i N_72_2 BG_030_i N_70_1 nEXP_SPACE_i N_70_2 \ +# CLK_000_D0_i N_70_3 sm_amiga_i_4__n sm_amiga_ns_0_1_0__n cpu_est_i_3__n \ +# cpu_est_ns_0_1_2__n sm_amiga_i_1__n N_221_1 state_machine_un6_clk_000_d4_i_n \ +# N_215_1 sm_amiga_i_6__n N_75_1 AS_000_INT_i N_69_1 cpu_est_i_1__n N_68_1 \ +# cpu_est_i_0__n state_machine_uds_000_int_5_0_m2_un3_n AMIGA_BUS_ENABLE_i \ +# state_machine_uds_000_int_5_0_m2_un1_n AS_030_i \ +# state_machine_uds_000_int_5_0_m2_un0_n cpu_est_i_2__n lds_000_int_0_un3_n \ +# sm_amiga_i_2__n lds_000_int_0_un1_n sm_amiga_i_3__n lds_000_int_0_un0_n \ +# sm_amiga_i_5__n vpa_sync_0_un3_n state_machine_un8_clk_000_d2_i_n \ +# vpa_sync_0_un1_n sm_amiga_i_7__n vpa_sync_0_un0_n a_i_0__n vma_int_0_un3_n \ +# size_i_1__n vma_int_0_un1_n dsack_i_1__n vma_int_0_un0_n CLK_000_D2_i \ +# bgack_030_int_0_un3_n AS_030_000_SYNC_i bgack_030_int_0_un1_n a_i_30__n \ +# bgack_030_int_0_un0_n a_i_31__n as_000_int_0_un3_n a_i_28__n as_000_int_0_un1_n \ +# a_i_29__n as_000_int_0_un0_n a_i_26__n ipl_030_0_0__un3_n a_i_27__n \ +# ipl_030_0_0__un1_n a_i_24__n ipl_030_0_0__un0_n a_i_25__n ipl_030_0_1__un3_n \ +# a_i_19__n ipl_030_0_1__un1_n a_i_16__n ipl_030_0_1__un0_n a_i_18__n \ +# ipl_030_0_2__un3_n RST_i ipl_030_0_2__un1_n ipl_030_0_2__un0_n cpu_estse_0_un3_n \ +# cpu_estse_0_un1_n CLK_OSZI_i cpu_estse_0_un0_n cpu_estse_1_un3_n N_70_i \ +# cpu_estse_1_un1_n N_72_i cpu_estse_1_un0_n FPU_CS_INT_i cpu_estse_2_un3_n \ +# BGACK_030_INT_i cpu_estse_2_un1_n CLK_000_D5_i cpu_estse_2_un0_n AS_030_c \ +# as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n DS_030_c \ +# dtack_sync_0_un3_n dtack_sync_0_un1_n dtack_sync_0_un0_n fpu_cs_int_0_un3_n \ +# size_c_0__n fpu_cs_int_0_un1_n fpu_cs_int_0_un0_n size_c_1__n dsack_int_0_1__un3_n \ +# dsack_int_0_1__un1_n a_c_0__n dsack_int_0_1__un0_n amiga_bus_enable_0_un3_n \ +# amiga_bus_enable_0_un1_n amiga_bus_enable_0_un0_n uds_000_int_0_un3_n \ +# uds_000_int_0_un1_n uds_000_int_0_un0_n a_15__n a_14__n a_13__n a_12__n a_11__n \ +# a_c_16__n a_10__n a_c_17__n a_9__n a_c_18__n a_8__n a_c_19__n a_7__n a_c_20__n a_6__n \ +# a_c_21__n a_5__n a_c_22__n a_4__n a_c_23__n a_3__n a_c_24__n a_2__n a_c_25__n a_1__n \ +# a_c_26__n a_c_27__n a_c_28__n a_c_29__n a_c_30__n a_c_31__n nEXP_SPACE_c BG_030_c \ +# BG_000DFFSHreg BGACK_000_c CLK_030_c .model bus68030 .inputs SIZE_1_.BLIF A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF AS_030.BLIF DS_030.BLIF \ nEXP_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF \ @@ -79,192 +78,214 @@ A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF A_15_.BLIF \ A_14_.BLIF A_13_.BLIF A_12_.BLIF A_11_.BLIF A_10_.BLIF A_9_.BLIF A_8_.BLIF \ A_7_.BLIF A_6_.BLIF A_5_.BLIF A_4_.BLIF A_3_.BLIF A_2_.BLIF A_1_.BLIF \ A_0_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF DSACK_1_.BLIF DTACK.BLIF \ -DSACK_0_.BLIF BGACK_000_c.BLIF CLK_030_c.BLIF inst_BGACK_030_INTreg.BLIF \ -inst_FPU_CS_INTreg.BLIF CLK_OSZI_c.BLIF cpu_est_3_reg.BLIF \ -inst_VMA_INTreg.BLIF cpu_est_0_.BLIF CLK_OUT_INTreg.BLIF cpu_est_1_.BLIF \ -inst_AS_000_INTreg.BLIF inst_AS_030_000_SYNC.BLIF IPL_030DFFSH_0_reg.BLIF \ -inst_DTACK_SYNC.BLIF inst_VPA_D.BLIF IPL_030DFFSH_1_reg.BLIF \ -inst_VPA_SYNC.BLIF inst_CLK_000_D0.BLIF IPL_030DFFSH_2_reg.BLIF \ -inst_CLK_000_D1.BLIF inst_CLK_000_D2.BLIF ipl_c_0__n.BLIF inst_CLK_000_D5.BLIF \ -inst_CLK_OUT_PRE.BLIF ipl_c_1__n.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_5_.BLIF \ -ipl_c_2__n.BLIF vcc_n_n.BLIF gnd_n_n.BLIF cpu_est_2_.BLIF dsack_c_1__n.BLIF \ -CLK_REF_1_.BLIF inst_UDS_000_INTreg.BLIF DTACK_c.BLIF inst_LDS_000_INTreg.BLIF \ -DSACK_INT_1_.BLIF SM_AMIGA_7_.BLIF AS_000_INT_1_sqmuxa.BLIF \ -state_machine_un8_clk_000_d2_n.BLIF inst_CLK_000_D3.BLIF SM_AMIGA_4_.BLIF \ -state_machine_un23_clk_000_d0_n.BLIF RST_c.BLIF \ -state_machine_un6_clk_000_d4_n.BLIF inst_CLK_000_D4.BLIF RESETDFFreg.BLIF \ -inst_DTACK_DMA.BLIF clk_clk_cnt_n.BLIF RW_c.BLIF CLK_CNT_0_.BLIF \ -CLK_CNT_1_.BLIF fc_c_0__n.BLIF state_machine_un6_bgack_000_n.BLIF \ -SM_AMIGA_3_.BLIF fc_c_1__n.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_2_.BLIF \ -AMIGA_BUS_ENABLEDFFreg.BLIF SM_AMIGA_0_.BLIF \ -state_machine_un7_as_000_int_n.BLIF state_machine_un15_clk_000_d0_n.BLIF \ -clk_cpu_est_11_0_1__n.BLIF state_machine_lds_000_int_5_n.BLIF N_124_i.BLIF \ -state_machine_uds_000_int_5_n.BLIF N_146_i.BLIF \ -un1_AMIGA_BUS_ENABLE_1_sqmuxa_2.BLIF N_121_i.BLIF N_122_i.BLIF N_66_0.BLIF \ -N_65_0.BLIF N_145_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0.BLIF \ -DS_030_c_i.BLIF N_63_i.BLIF N_62_i.BLIF state_machine_un6_clk_000_d4_i_n.BLIF \ -N_61_i.BLIF CLK_OUT_PRE_0.BLIF N_60_i.BLIF N_59_i.BLIF N_58_i.BLIF N_57_i.BLIF \ -CLK_000_D1_i.BLIF N_56_i.BLIF N_55_i.BLIF N_52_i.BLIF N_141_i.BLIF \ -N_142_i.BLIF N_14_0.BLIF N_85_i.BLIF N_139_i.BLIF clk_cpu_est_11_1__n.BLIF \ -N_140_i.BLIF clk_cpu_est_11_3__n.BLIF sm_amiga_ns_0_0__n.BLIF G_92.BLIF \ -N_125_i.BLIF G_96.BLIF N_138_i.BLIF N_162.BLIF N_178_i.BLIF N_163.BLIF \ -clk_cpu_est_11_0_3__n.BLIF N_164.BLIF N_119_i.BLIF N_165.BLIF N_43_i.BLIF \ -N_30.BLIF N_117_i.BLIF N_118_i.BLIF N_51.BLIF N_123_i.BLIF N_52.BLIF \ -N_115_i.BLIF N_55.BLIF N_116_i.BLIF N_56.BLIF sm_amiga_ns_0_7__n.BLIF \ -N_57.BLIF N_98_i.BLIF N_58.BLIF N_114_i.BLIF N_59.BLIF N_39_0.BLIF N_60.BLIF \ -N_94_i.BLIF N_61.BLIF N_97_i.BLIF N_62.BLIF sm_amiga_ns_0_5__n.BLIF N_63.BLIF \ -N_89_i.BLIF N_65.BLIF N_90_i.BLIF N_66.BLIF N_69.BLIF N_88_i.BLIF N_72.BLIF \ -N_73.BLIF N_86_i.BLIF N_74.BLIF N_75.BLIF N_83_i.BLIF N_76.BLIF N_77.BLIF \ -N_81_i.BLIF N_79.BLIF state_machine_lds_000_int_5_0_n.BLIF N_81.BLIF \ -state_machine_uds_000_int_5_0_n.BLIF N_83.BLIF N_79_i.BLIF N_85.BLIF \ -N_30_0.BLIF N_86.BLIF N_165_0.BLIF N_88.BLIF N_76_i.BLIF N_89.BLIF \ -N_164_0.BLIF N_90.BLIF N_163_0.BLIF N_94.BLIF N_72_i.BLIF N_97.BLIF \ -N_73_i.BLIF N_98.BLIF state_machine_un15_clk_000_d0_0_n.BLIF N_114.BLIF \ -N_162_0.BLIF N_115.BLIF state_machine_un6_bgack_000_0_n.BLIF N_116.BLIF \ -state_machine_un23_clk_000_d0_i_n.BLIF N_117.BLIF N_188_1.BLIF N_118.BLIF \ -N_188_2.BLIF N_119.BLIF N_188_3.BLIF N_120.BLIF N_188_4.BLIF N_121.BLIF \ -N_188_5.BLIF N_122.BLIF N_188_6.BLIF N_124.BLIF N_191_1.BLIF N_125.BLIF \ -N_191_2.BLIF N_178.BLIF state_machine_un8_clk_000_d2_1_n.BLIF N_138.BLIF \ -N_57_i_1.BLIF N_139.BLIF N_57_i_2.BLIF N_140.BLIF N_57_i_3.BLIF N_141.BLIF \ -N_57_i_4.BLIF N_142.BLIF N_57_i_5.BLIF N_145.BLIF clk_cpu_est_11_0_1_1__n.BLIF \ -N_146.BLIF clk_cpu_est_11_0_2_1__n.BLIF N_77_1.BLIF N_120_1.BLIF N_188.BLIF \ -N_120_2.BLIF N_191.BLIF N_79_1.BLIF RW_i.BLIF N_79_2.BLIF VPA_D_i.BLIF \ -N_77_1_0.BLIF CLK_000_D0_i.BLIF N_75_1.BLIF cpu_est_i_0__n.BLIF N_75_2.BLIF \ -cpu_est_i_3__n.BLIF N_75_3.BLIF VMA_INT_i.BLIF N_75_4.BLIF cpu_est_i_1__n.BLIF \ -N_75_5.BLIF DTACK_i.BLIF N_73_1.BLIF BG_030_i.BLIF N_73_2.BLIF \ -nEXP_SPACE_i.BLIF N_72_1.BLIF sm_amiga_i_3__n.BLIF N_72_2.BLIF \ -AS_000_INT_i.BLIF sm_amiga_ns_0_1_0__n.BLIF sm_amiga_i_6__n.BLIF \ -clk_cpu_est_11_0_1_3__n.BLIF cpu_est_i_2__n.BLIF N_138_1.BLIF \ -AMIGA_BUS_ENABLE_i.BLIF N_119_1.BLIF AS_030_i.BLIF N_118_1.BLIF \ -sm_amiga_i_4__n.BLIF N_117_1.BLIF sm_amiga_i_5__n.BLIF N_97_1.BLIF \ -state_machine_un8_clk_000_d2_i_n.BLIF N_81_1.BLIF sm_amiga_i_7__n.BLIF \ -state_machine_uds_000_int_5_0_m2_un3_n.BLIF a_i_0__n.BLIF \ -state_machine_uds_000_int_5_0_m2_un1_n.BLIF size_i_1__n.BLIF \ -state_machine_uds_000_int_5_0_m2_un0_n.BLIF dsack_i_1__n.BLIF \ -vpa_sync_0_un3_n.BLIF clk_clk_cnt_i_n.BLIF vpa_sync_0_un1_n.BLIF \ -clk_cnt_i_0__n.BLIF vpa_sync_0_un0_n.BLIF CLK_000_D2_i.BLIF \ -amiga_bus_enable_0_un3_n.BLIF AS_030_000_SYNC_i.BLIF \ -amiga_bus_enable_0_un1_n.BLIF a_i_30__n.BLIF amiga_bus_enable_0_un0_n.BLIF \ -a_i_31__n.BLIF uds_000_int_0_un3_n.BLIF a_i_28__n.BLIF \ -uds_000_int_0_un1_n.BLIF a_i_29__n.BLIF uds_000_int_0_un0_n.BLIF \ -a_i_26__n.BLIF lds_000_int_0_un3_n.BLIF a_i_27__n.BLIF \ -lds_000_int_0_un1_n.BLIF a_i_24__n.BLIF lds_000_int_0_un0_n.BLIF \ -a_i_25__n.BLIF vma_int_0_un3_n.BLIF a_i_19__n.BLIF vma_int_0_un1_n.BLIF \ -a_i_16__n.BLIF vma_int_0_un0_n.BLIF a_i_18__n.BLIF bg_000_0_un3_n.BLIF \ -N_137_i.BLIF bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF RST_i.BLIF \ -bgack_030_int_0_un3_n.BLIF N_120_i.BLIF bgack_030_int_0_un1_n.BLIF N_75_i.BLIF \ -bgack_030_int_0_un0_n.BLIF N_74_i.BLIF as_000_int_0_un3_n.BLIF N_77_i.BLIF \ -as_000_int_0_un1_n.BLIF FPU_CS_INT_i.BLIF as_000_int_0_un0_n.BLIF \ -BGACK_030_INT_i.BLIF cpu_est_0_1__un3_n.BLIF CLK_000_D5_i.BLIF \ -cpu_est_0_1__un1_n.BLIF AS_030_c.BLIF cpu_est_0_1__un0_n.BLIF \ -cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un1_n.BLIF DS_030_c.BLIF \ -cpu_est_0_2__un0_n.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un1_n.BLIF \ -cpu_est_0_3__un0_n.BLIF size_c_0__n.BLIF ipl_030_0_0__un3_n.BLIF \ -ipl_030_0_0__un1_n.BLIF size_c_1__n.BLIF ipl_030_0_0__un0_n.BLIF \ -ipl_030_0_1__un3_n.BLIF a_c_0__n.BLIF ipl_030_0_1__un1_n.BLIF \ -ipl_030_0_1__un0_n.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un1_n.BLIF \ -ipl_030_0_2__un0_n.BLIF as_030_000_sync_0_un3_n.BLIF \ -as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF \ -dtack_sync_0_un3_n.BLIF dtack_sync_0_un1_n.BLIF dtack_sync_0_un0_n.BLIF \ -fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF \ -dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF \ -a_c_16__n.BLIF a_15__n.BLIF a_c_17__n.BLIF a_14__n.BLIF a_c_18__n.BLIF \ -a_13__n.BLIF a_c_19__n.BLIF a_12__n.BLIF a_c_20__n.BLIF a_11__n.BLIF \ -a_c_21__n.BLIF a_10__n.BLIF a_c_22__n.BLIF a_9__n.BLIF a_c_23__n.BLIF \ -a_8__n.BLIF a_c_24__n.BLIF a_7__n.BLIF a_c_25__n.BLIF a_6__n.BLIF \ -a_c_26__n.BLIF a_5__n.BLIF a_c_27__n.BLIF a_4__n.BLIF a_c_28__n.BLIF \ -a_3__n.BLIF a_c_29__n.BLIF a_2__n.BLIF a_c_30__n.BLIF a_1__n.BLIF \ +DSACK_0_.BLIF CLK_OSZI_c.BLIF CLK_OUT_INTreg.BLIF IPL_030DFFSH_0_reg.BLIF \ +inst_BGACK_030_INTreg.BLIF inst_FPU_CS_INTreg.BLIF IPL_030DFFSH_1_reg.BLIF \ +inst_VMA_INTreg.BLIF inst_AS_000_INTreg.BLIF IPL_030DFFSH_2_reg.BLIF \ +inst_AS_030_000_SYNC.BLIF inst_DTACK_SYNC.BLIF ipl_c_0__n.BLIF inst_VPA_D.BLIF \ +inst_VPA_SYNC.BLIF ipl_c_1__n.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF \ +ipl_c_2__n.BLIF inst_CLK_000_D2.BLIF inst_CLK_000_D5.BLIF SM_AMIGA_5_.BLIF \ +dsack_c_1__n.BLIF SM_AMIGA_6_.BLIF vcc_n_n.BLIF DTACK_c.BLIF gnd_n_n.BLIF \ +inst_UDS_000_INTreg.BLIF inst_LDS_000_INTreg.BLIF DSACK_INT_1_.BLIF \ +AS_000_INT_1_sqmuxa.BLIF state_machine_un8_clk_000_d2_n.BLIF \ +inst_CLK_000_D3.BLIF SM_AMIGA_4_.BLIF RST_c.BLIF \ +state_machine_un23_clk_000_d0_n.BLIF state_machine_un6_clk_000_d4_n.BLIF \ +RESETDFFRHreg.BLIF inst_CLK_000_D4.BLIF inst_DTACK_DMA.BLIF RW_c.BLIF \ +state_machine_un10_bg_030_n.BLIF SM_AMIGA_7_.BLIF fc_c_0__n.BLIF \ +SM_AMIGA_3_.BLIF state_machine_un6_bgack_000_n.BLIF fc_c_1__n.BLIF \ +SM_AMIGA_1_.BLIF G_102.BLIF AMIGA_BUS_ENABLEDFFreg.BLIF CLK_CNT_N_0_.BLIF \ +CLK_CNT_N_1_.BLIF G_108.BLIF CLK_CNT_P_0_.BLIF CLK_CNT_P_1_.BLIF \ +cpu_est_ns_0_1__n.BLIF SM_AMIGA_2_.BLIF N_126_i.BLIF SM_AMIGA_0_.BLIF \ +N_128_i.BLIF state_machine_un7_as_000_int_n.BLIF N_216_i.BLIF \ +state_machine_un15_clk_000_d0_n.BLIF N_217_i.BLIF \ +state_machine_lds_000_int_5_n.BLIF N_61_0.BLIF \ +state_machine_uds_000_int_5_n.BLIF N_60_0.BLIF \ +un1_AMIGA_BUS_ENABLE_1_sqmuxa_2.BLIF N_129_i.BLIF inst_CLK_OUT_PRE.BLIF \ +un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0.BLIF DS_030_c_i.BLIF N_58_i.BLIF N_57_i.BLIF \ +N_55_i.BLIF N_54_i.BLIF N_53_i.BLIF N_50_i.BLIF CLK_000_D1_i.BLIF N_49_i.BLIF \ +N_48_i.BLIF N_122_i.BLIF N_123_i.BLIF cpu_est_ns_e_0_0__n.BLIF N_79_i.BLIF \ +N_226_i.BLIF N_227_i.BLIF sm_amiga_ns_0_0__n.BLIF cpu_est_0_.BLIF N_222_i.BLIF \ +cpu_est_1_.BLIF N_223_i.BLIF cpu_est_2_.BLIF N_225_i.BLIF cpu_est_3_reg.BLIF \ +cpu_est_ns_0_2__n.BLIF N_221_i.BLIF N_41_i.BLIF N_127_i.BLIF N_220_i.BLIF \ +cpu_est_ns_1__n.BLIF N_157_i.BLIF cpu_est_ns_2__n.BLIF N_214_i.BLIF N_203.BLIF \ +N_215_i.BLIF N_204.BLIF sm_amiga_ns_0_7__n.BLIF N_205.BLIF N_93_i.BLIF \ +N_23.BLIF N_94_i.BLIF N_27.BLIF N_47.BLIF N_85_i.BLIF N_48.BLIF N_86_i.BLIF \ +N_49.BLIF sm_amiga_ns_0_5__n.BLIF N_50.BLIF N_84_i.BLIF N_53.BLIF N_130_i.BLIF \ +N_54.BLIF N_55.BLIF N_82_i.BLIF N_57.BLIF N_58.BLIF N_81_i.BLIF N_60.BLIF \ +N_61.BLIF N_77_i.BLIF N_68.BLIF N_69.BLIF N_75_i.BLIF N_70.BLIF \ +state_machine_lds_000_int_5_0_n.BLIF N_71.BLIF \ +state_machine_uds_000_int_5_0_n.BLIF N_72.BLIF N_73_i.BLIF N_73.BLIF \ +N_27_0.BLIF N_75.BLIF N_23_0.BLIF N_77.BLIF N_71_i.BLIF N_79.BLIF N_205_0.BLIF \ +N_81.BLIF N_204_0.BLIF N_82.BLIF N_68_i.BLIF N_84.BLIF N_69_i.BLIF N_85.BLIF \ +state_machine_un15_clk_000_d0_0_n.BLIF N_86.BLIF N_203_0.BLIF N_93.BLIF \ +state_machine_un6_bgack_000_0_n.BLIF N_94.BLIF N_214.BLIF \ +state_machine_un23_clk_000_d0_0_n.BLIF N_215.BLIF N_238_1.BLIF N_216.BLIF \ +N_238_2.BLIF N_217.BLIF N_238_3.BLIF N_220.BLIF N_238_4.BLIF N_221.BLIF \ +N_238_5.BLIF N_222.BLIF N_238_6.BLIF N_223.BLIF N_241_1.BLIF N_225.BLIF \ +N_241_2.BLIF N_226.BLIF state_machine_un8_clk_000_d2_1_n.BLIF N_227.BLIF \ +N_53_i_1.BLIF N_122.BLIF N_53_i_2.BLIF N_123.BLIF N_53_i_3.BLIF N_126.BLIF \ +N_53_i_4.BLIF N_127.BLIF N_53_i_5.BLIF N_128.BLIF cpu_est_ns_0_1_1__n.BLIF \ +N_129.BLIF cpu_est_ns_0_2_1__n.BLIF N_130.BLIF \ +state_machine_un10_bg_030_1_n.BLIF N_238.BLIF \ +state_machine_un10_bg_030_2_n.BLIF N_241.BLIF \ +state_machine_un10_bg_030_3_n.BLIF RW_i.BLIF N_73_1.BLIF VMA_INT_i.BLIF \ +N_73_2.BLIF VPA_D_i.BLIF N_72_1.BLIF DTACK_i.BLIF N_72_2.BLIF BG_030_i.BLIF \ +N_70_1.BLIF nEXP_SPACE_i.BLIF N_70_2.BLIF CLK_000_D0_i.BLIF N_70_3.BLIF \ +sm_amiga_i_4__n.BLIF sm_amiga_ns_0_1_0__n.BLIF cpu_est_i_3__n.BLIF \ +cpu_est_ns_0_1_2__n.BLIF sm_amiga_i_1__n.BLIF N_221_1.BLIF \ +state_machine_un6_clk_000_d4_i_n.BLIF N_215_1.BLIF sm_amiga_i_6__n.BLIF \ +N_75_1.BLIF AS_000_INT_i.BLIF N_69_1.BLIF cpu_est_i_1__n.BLIF N_68_1.BLIF \ +cpu_est_i_0__n.BLIF state_machine_uds_000_int_5_0_m2_un3_n.BLIF \ +AMIGA_BUS_ENABLE_i.BLIF state_machine_uds_000_int_5_0_m2_un1_n.BLIF \ +AS_030_i.BLIF state_machine_uds_000_int_5_0_m2_un0_n.BLIF cpu_est_i_2__n.BLIF \ +lds_000_int_0_un3_n.BLIF sm_amiga_i_2__n.BLIF lds_000_int_0_un1_n.BLIF \ +sm_amiga_i_3__n.BLIF lds_000_int_0_un0_n.BLIF sm_amiga_i_5__n.BLIF \ +vpa_sync_0_un3_n.BLIF state_machine_un8_clk_000_d2_i_n.BLIF \ +vpa_sync_0_un1_n.BLIF sm_amiga_i_7__n.BLIF vpa_sync_0_un0_n.BLIF a_i_0__n.BLIF \ +vma_int_0_un3_n.BLIF size_i_1__n.BLIF vma_int_0_un1_n.BLIF dsack_i_1__n.BLIF \ +vma_int_0_un0_n.BLIF CLK_000_D2_i.BLIF bgack_030_int_0_un3_n.BLIF \ +AS_030_000_SYNC_i.BLIF bgack_030_int_0_un1_n.BLIF a_i_30__n.BLIF \ +bgack_030_int_0_un0_n.BLIF a_i_31__n.BLIF as_000_int_0_un3_n.BLIF \ +a_i_28__n.BLIF as_000_int_0_un1_n.BLIF a_i_29__n.BLIF as_000_int_0_un0_n.BLIF \ +a_i_26__n.BLIF ipl_030_0_0__un3_n.BLIF a_i_27__n.BLIF ipl_030_0_0__un1_n.BLIF \ +a_i_24__n.BLIF ipl_030_0_0__un0_n.BLIF a_i_25__n.BLIF ipl_030_0_1__un3_n.BLIF \ +a_i_19__n.BLIF ipl_030_0_1__un1_n.BLIF a_i_16__n.BLIF ipl_030_0_1__un0_n.BLIF \ +a_i_18__n.BLIF ipl_030_0_2__un3_n.BLIF RST_i.BLIF ipl_030_0_2__un1_n.BLIF \ +ipl_030_0_2__un0_n.BLIF cpu_estse_0_un3_n.BLIF cpu_estse_0_un1_n.BLIF \ +CLK_OSZI_i.BLIF cpu_estse_0_un0_n.BLIF cpu_estse_1_un3_n.BLIF N_70_i.BLIF \ +cpu_estse_1_un1_n.BLIF N_72_i.BLIF cpu_estse_1_un0_n.BLIF FPU_CS_INT_i.BLIF \ +cpu_estse_2_un3_n.BLIF BGACK_030_INT_i.BLIF cpu_estse_2_un1_n.BLIF \ +CLK_000_D5_i.BLIF cpu_estse_2_un0_n.BLIF AS_030_c.BLIF \ +as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un1_n.BLIF \ +as_030_000_sync_0_un0_n.BLIF DS_030_c.BLIF dtack_sync_0_un3_n.BLIF \ +dtack_sync_0_un1_n.BLIF dtack_sync_0_un0_n.BLIF fpu_cs_int_0_un3_n.BLIF \ +size_c_0__n.BLIF fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF \ +size_c_1__n.BLIF dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un1_n.BLIF \ +a_c_0__n.BLIF dsack_int_0_1__un0_n.BLIF amiga_bus_enable_0_un3_n.BLIF \ +amiga_bus_enable_0_un1_n.BLIF amiga_bus_enable_0_un0_n.BLIF \ +uds_000_int_0_un3_n.BLIF uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF \ +a_15__n.BLIF a_14__n.BLIF a_13__n.BLIF a_12__n.BLIF a_11__n.BLIF \ +a_c_16__n.BLIF a_10__n.BLIF a_c_17__n.BLIF a_9__n.BLIF a_c_18__n.BLIF \ +a_8__n.BLIF a_c_19__n.BLIF a_7__n.BLIF a_c_20__n.BLIF a_6__n.BLIF \ +a_c_21__n.BLIF a_5__n.BLIF a_c_22__n.BLIF a_4__n.BLIF a_c_23__n.BLIF \ +a_3__n.BLIF a_c_24__n.BLIF a_2__n.BLIF a_c_25__n.BLIF a_1__n.BLIF \ +a_c_26__n.BLIF a_c_27__n.BLIF a_c_28__n.BLIF a_c_29__n.BLIF a_c_30__n.BLIF \ a_c_31__n.BLIF nEXP_SPACE_c.BLIF BG_030_c.BLIF BG_000DFFSHreg.BLIF \ -DSACK_1_.PIN.BLIF DTACK.PIN.BLIF +BGACK_000_c.BLIF CLK_030_c.BLIF DSACK_1_.PIN.BLIF DTACK.PIN.BLIF .outputs IPL_030_2_ AS_000 UDS_000 LDS_000 BERR BG_000 BGACK_030 CLK_DIV_OUT \ CLK_EXP FPU_CS AVEC AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR \ -AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ IPL_030DFFSH_0_reg.D \ -IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP IPL_030DFFSH_1_reg.D \ -IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D \ -IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D SM_AMIGA_7_.C \ -SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.D \ -SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_4_.AR \ +AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ cpu_est_2_.D cpu_est_2_.C \ +cpu_est_2_.AR cpu_est_3_reg.D cpu_est_3_reg.C cpu_est_3_reg.AR cpu_est_0_.D \ +cpu_est_0_.C cpu_est_0_.AR cpu_est_1_.D cpu_est_1_.C cpu_est_1_.AR \ SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C \ SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.D \ -SM_AMIGA_0_.C SM_AMIGA_0_.AR CLK_CNT_0_.D CLK_CNT_0_.C CLK_CNT_1_.D \ -CLK_CNT_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D \ -cpu_est_2_.C cpu_est_3_reg.D cpu_est_3_reg.C inst_UDS_000_INTreg.D \ -inst_UDS_000_INTreg.C inst_UDS_000_INTreg.AP inst_LDS_000_INTreg.D \ -inst_LDS_000_INTreg.C inst_LDS_000_INTreg.AP inst_VMA_INTreg.D \ -inst_VMA_INTreg.C inst_VMA_INTreg.AP BG_000DFFSHreg.D BG_000DFFSHreg.C \ -BG_000DFFSHreg.AP inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C \ -inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP \ -inst_AS_000_INTreg.D inst_AS_000_INTreg.C inst_AS_000_INTreg.AP \ -inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP \ -inst_DTACK_SYNC.D inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_FPU_CS_INTreg.D \ -inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP DSACK_INT_1_.D DSACK_INT_1_.C \ -DSACK_INT_1_.AP inst_VPA_SYNC.D inst_VPA_SYNC.C inst_VPA_SYNC.AP \ -AMIGA_BUS_ENABLEDFFreg.D AMIGA_BUS_ENABLEDFFreg.C inst_CLK_000_D5.D \ -inst_CLK_000_D5.C inst_DTACK_DMA.D inst_DTACK_DMA.C inst_DTACK_DMA.AP \ -CLK_OUT_INTreg.D CLK_OUT_INTreg.C inst_CLK_000_D4.D inst_CLK_000_D4.C \ -inst_CLK_000_D2.D inst_CLK_000_D2.C inst_CLK_000_D3.D inst_CLK_000_D3.C \ -inst_VPA_D.D inst_VPA_D.C inst_CLK_000_D0.D inst_CLK_000_D0.C RESETDFFreg.D \ -RESETDFFreg.C inst_CLK_000_D1.D inst_CLK_000_D1.C CLK_REF_1_.D CLK_REF_1_.LH \ -CLK_REF_1_.AR DSACK_1_ DTACK DSACK_0_ BGACK_000_c CLK_030_c CLK_OSZI_c \ -ipl_c_0__n ipl_c_1__n ipl_c_2__n vcc_n_n gnd_n_n dsack_c_1__n DTACK_c \ -AS_000_INT_1_sqmuxa state_machine_un8_clk_000_d2_n \ -state_machine_un23_clk_000_d0_n RST_c state_machine_un6_clk_000_d4_n \ -clk_clk_cnt_n RW_c fc_c_0__n state_machine_un6_bgack_000_n fc_c_1__n \ -state_machine_un7_as_000_int_n state_machine_un15_clk_000_d0_n \ -clk_cpu_est_11_0_1__n state_machine_lds_000_int_5_n N_124_i \ -state_machine_uds_000_int_5_n N_146_i un1_AMIGA_BUS_ENABLE_1_sqmuxa_2 N_121_i \ -N_122_i N_66_0 N_65_0 N_145_i un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 DS_030_c_i \ -N_63_i N_62_i state_machine_un6_clk_000_d4_i_n N_61_i N_60_i N_59_i N_58_i \ -N_57_i CLK_000_D1_i N_56_i N_55_i N_52_i N_141_i N_142_i N_14_0 N_85_i N_139_i \ -clk_cpu_est_11_1__n N_140_i clk_cpu_est_11_3__n sm_amiga_ns_0_0__n N_125_i \ -N_138_i N_162 N_178_i N_163 clk_cpu_est_11_0_3__n N_164 N_119_i N_165 N_43_i \ -N_30 N_117_i N_118_i N_51 N_123_i N_52 N_115_i N_55 N_116_i N_56 \ -sm_amiga_ns_0_7__n N_57 N_98_i N_58 N_114_i N_59 N_39_0 N_60 N_94_i N_61 \ -N_97_i N_62 sm_amiga_ns_0_5__n N_63 N_89_i N_65 N_90_i N_66 N_69 N_88_i N_72 \ -N_73 N_86_i N_74 N_75 N_83_i N_76 N_77 N_81_i N_79 \ -state_machine_lds_000_int_5_0_n N_81 state_machine_uds_000_int_5_0_n N_83 \ -N_79_i N_85 N_30_0 N_86 N_165_0 N_88 N_76_i N_89 N_164_0 N_90 N_163_0 N_94 \ -N_72_i N_97 N_73_i N_98 state_machine_un15_clk_000_d0_0_n N_114 N_162_0 N_115 \ -state_machine_un6_bgack_000_0_n N_116 state_machine_un23_clk_000_d0_i_n N_117 \ -N_188_1 N_118 N_188_2 N_119 N_188_3 N_120 N_188_4 N_121 N_188_5 N_122 N_188_6 \ -N_124 N_191_1 N_125 N_191_2 N_178 state_machine_un8_clk_000_d2_1_n N_138 \ -N_57_i_1 N_139 N_57_i_2 N_140 N_57_i_3 N_141 N_57_i_4 N_142 N_57_i_5 N_145 \ -clk_cpu_est_11_0_1_1__n N_146 clk_cpu_est_11_0_2_1__n N_77_1 N_120_1 N_188 \ -N_120_2 N_191 N_79_1 RW_i N_79_2 VPA_D_i N_77_1_0 CLK_000_D0_i N_75_1 \ -cpu_est_i_0__n N_75_2 cpu_est_i_3__n N_75_3 VMA_INT_i N_75_4 cpu_est_i_1__n \ -N_75_5 DTACK_i N_73_1 BG_030_i N_73_2 nEXP_SPACE_i N_72_1 sm_amiga_i_3__n \ -N_72_2 AS_000_INT_i sm_amiga_ns_0_1_0__n sm_amiga_i_6__n \ -clk_cpu_est_11_0_1_3__n cpu_est_i_2__n N_138_1 AMIGA_BUS_ENABLE_i N_119_1 \ -AS_030_i N_118_1 sm_amiga_i_4__n N_117_1 sm_amiga_i_5__n N_97_1 \ -state_machine_un8_clk_000_d2_i_n N_81_1 sm_amiga_i_7__n \ -state_machine_uds_000_int_5_0_m2_un3_n a_i_0__n \ -state_machine_uds_000_int_5_0_m2_un1_n size_i_1__n \ -state_machine_uds_000_int_5_0_m2_un0_n dsack_i_1__n vpa_sync_0_un3_n \ -clk_clk_cnt_i_n vpa_sync_0_un1_n clk_cnt_i_0__n vpa_sync_0_un0_n CLK_000_D2_i \ -amiga_bus_enable_0_un3_n AS_030_000_SYNC_i amiga_bus_enable_0_un1_n a_i_30__n \ -amiga_bus_enable_0_un0_n a_i_31__n uds_000_int_0_un3_n a_i_28__n \ -uds_000_int_0_un1_n a_i_29__n uds_000_int_0_un0_n a_i_26__n \ -lds_000_int_0_un3_n a_i_27__n lds_000_int_0_un1_n a_i_24__n \ -lds_000_int_0_un0_n a_i_25__n vma_int_0_un3_n a_i_19__n vma_int_0_un1_n \ -a_i_16__n vma_int_0_un0_n a_i_18__n bg_000_0_un3_n N_137_i bg_000_0_un1_n \ -bg_000_0_un0_n RST_i bgack_030_int_0_un3_n N_120_i bgack_030_int_0_un1_n \ -N_75_i bgack_030_int_0_un0_n N_74_i as_000_int_0_un3_n N_77_i \ -as_000_int_0_un1_n FPU_CS_INT_i as_000_int_0_un0_n BGACK_030_INT_i \ -cpu_est_0_1__un3_n CLK_000_D5_i cpu_est_0_1__un1_n AS_030_c cpu_est_0_1__un0_n \ -cpu_est_0_2__un3_n cpu_est_0_2__un1_n DS_030_c cpu_est_0_2__un0_n \ -cpu_est_0_3__un3_n cpu_est_0_3__un1_n cpu_est_0_3__un0_n size_c_0__n \ -ipl_030_0_0__un3_n ipl_030_0_0__un1_n size_c_1__n ipl_030_0_0__un0_n \ -ipl_030_0_1__un3_n a_c_0__n ipl_030_0_1__un1_n ipl_030_0_1__un0_n \ -ipl_030_0_2__un3_n ipl_030_0_2__un1_n ipl_030_0_2__un0_n \ -as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n \ -dtack_sync_0_un3_n dtack_sync_0_un1_n dtack_sync_0_un0_n fpu_cs_int_0_un3_n \ -fpu_cs_int_0_un1_n fpu_cs_int_0_un0_n dsack_int_0_1__un3_n \ -dsack_int_0_1__un1_n dsack_int_0_1__un0_n a_c_16__n a_15__n a_c_17__n a_14__n \ -a_c_18__n a_13__n a_c_19__n a_12__n a_c_20__n a_11__n a_c_21__n a_10__n \ -a_c_22__n a_9__n a_c_23__n a_8__n a_c_24__n a_7__n a_c_25__n a_6__n a_c_26__n \ -a_5__n a_c_27__n a_4__n a_c_28__n a_3__n a_c_29__n a_2__n a_c_30__n a_1__n \ -a_c_31__n nEXP_SPACE_c BG_030_c DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE \ -LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_OUT_PRE_0 G_92 G_96 +SM_AMIGA_0_.C SM_AMIGA_0_.AR CLK_CNT_N_0_.D CLK_CNT_N_0_.C CLK_CNT_N_0_.AR \ +CLK_CNT_N_1_.D CLK_CNT_N_1_.C CLK_CNT_N_1_.AR CLK_CNT_P_0_.D CLK_CNT_P_0_.C \ +CLK_CNT_P_0_.AR CLK_CNT_P_1_.D CLK_CNT_P_1_.C CLK_CNT_P_1_.AR \ +IPL_030DFFSH_0_reg.D IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP \ +IPL_030DFFSH_1_reg.D IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP \ +IPL_030DFFSH_2_reg.D IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D \ +SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR \ +SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C \ +SM_AMIGA_4_.AR inst_UDS_000_INTreg.D inst_UDS_000_INTreg.C \ +inst_UDS_000_INTreg.AP inst_LDS_000_INTreg.D inst_LDS_000_INTreg.C \ +inst_LDS_000_INTreg.AP inst_VPA_SYNC.D inst_VPA_SYNC.C inst_VPA_SYNC.AP \ +inst_VMA_INTreg.D inst_VMA_INTreg.C inst_VMA_INTreg.AP inst_BGACK_030_INTreg.D \ +inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP inst_AS_000_INTreg.D \ +inst_AS_000_INTreg.C inst_AS_000_INTreg.AP inst_CLK_OUT_PRE.D \ +inst_CLK_OUT_PRE.C inst_CLK_OUT_PRE.AR CLK_OUT_INTreg.D CLK_OUT_INTreg.C \ +CLK_OUT_INTreg.AR inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \ +inst_AS_030_000_SYNC.AP inst_DTACK_SYNC.D inst_DTACK_SYNC.C inst_DTACK_SYNC.AP \ +inst_FPU_CS_INTreg.D inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP DSACK_INT_1_.D \ +DSACK_INT_1_.C DSACK_INT_1_.AP AMIGA_BUS_ENABLEDFFreg.D \ +AMIGA_BUS_ENABLEDFFreg.C inst_DTACK_DMA.D inst_DTACK_DMA.C inst_DTACK_DMA.AP \ +inst_CLK_000_D5.D inst_CLK_000_D5.C inst_CLK_000_D5.AP BG_000DFFSHreg.D \ +BG_000DFFSHreg.C BG_000DFFSHreg.AP inst_CLK_000_D4.D inst_CLK_000_D4.C \ +inst_CLK_000_D4.AP inst_CLK_000_D2.D inst_CLK_000_D2.C inst_CLK_000_D2.AP \ +inst_CLK_000_D3.D inst_CLK_000_D3.C inst_CLK_000_D3.AP inst_VPA_D.D \ +inst_VPA_D.C inst_VPA_D.AP inst_CLK_000_D0.D inst_CLK_000_D0.C \ +inst_CLK_000_D0.AP RESETDFFRHreg.D RESETDFFRHreg.C RESETDFFRHreg.AR \ +inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_D1.AP DSACK_1_ DTACK DSACK_0_ \ +CLK_OSZI_c ipl_c_0__n ipl_c_1__n ipl_c_2__n dsack_c_1__n vcc_n_n DTACK_c \ +gnd_n_n AS_000_INT_1_sqmuxa state_machine_un8_clk_000_d2_n RST_c \ +state_machine_un23_clk_000_d0_n state_machine_un6_clk_000_d4_n RW_c \ +state_machine_un10_bg_030_n fc_c_0__n state_machine_un6_bgack_000_n fc_c_1__n \ +cpu_est_ns_0_1__n N_126_i N_128_i state_machine_un7_as_000_int_n N_216_i \ +state_machine_un15_clk_000_d0_n N_217_i state_machine_lds_000_int_5_n N_61_0 \ +state_machine_uds_000_int_5_n N_60_0 un1_AMIGA_BUS_ENABLE_1_sqmuxa_2 N_129_i \ +un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 DS_030_c_i N_58_i N_57_i N_55_i N_54_i \ +N_53_i N_50_i CLK_000_D1_i N_49_i N_48_i N_122_i N_123_i cpu_est_ns_e_0_0__n \ +N_79_i N_226_i N_227_i sm_amiga_ns_0_0__n N_222_i N_223_i N_225_i \ +cpu_est_ns_0_2__n N_221_i N_41_i N_127_i N_220_i cpu_est_ns_1__n N_157_i \ +cpu_est_ns_2__n N_214_i N_203 N_215_i N_204 sm_amiga_ns_0_7__n N_205 N_93_i \ +N_23 N_94_i N_27 N_47 N_85_i N_48 N_86_i N_49 sm_amiga_ns_0_5__n N_50 N_84_i \ +N_53 N_130_i N_54 N_55 N_82_i N_57 N_58 N_81_i N_60 N_61 N_77_i N_68 N_69 \ +N_75_i N_70 state_machine_lds_000_int_5_0_n N_71 \ +state_machine_uds_000_int_5_0_n N_72 N_73_i N_73 N_27_0 N_75 N_23_0 N_77 \ +N_71_i N_79 N_205_0 N_81 N_204_0 N_82 N_68_i N_84 N_69_i N_85 \ +state_machine_un15_clk_000_d0_0_n N_86 N_203_0 N_93 \ +state_machine_un6_bgack_000_0_n N_94 N_214 state_machine_un23_clk_000_d0_0_n \ +N_215 N_238_1 N_216 N_238_2 N_217 N_238_3 N_220 N_238_4 N_221 N_238_5 N_222 \ +N_238_6 N_223 N_241_1 N_225 N_241_2 N_226 state_machine_un8_clk_000_d2_1_n \ +N_227 N_53_i_1 N_122 N_53_i_2 N_123 N_53_i_3 N_126 N_53_i_4 N_127 N_53_i_5 \ +N_128 cpu_est_ns_0_1_1__n N_129 cpu_est_ns_0_2_1__n N_130 \ +state_machine_un10_bg_030_1_n N_238 state_machine_un10_bg_030_2_n N_241 \ +state_machine_un10_bg_030_3_n RW_i N_73_1 VMA_INT_i N_73_2 VPA_D_i N_72_1 \ +DTACK_i N_72_2 BG_030_i N_70_1 nEXP_SPACE_i N_70_2 CLK_000_D0_i N_70_3 \ +sm_amiga_i_4__n sm_amiga_ns_0_1_0__n cpu_est_i_3__n cpu_est_ns_0_1_2__n \ +sm_amiga_i_1__n N_221_1 state_machine_un6_clk_000_d4_i_n N_215_1 \ +sm_amiga_i_6__n N_75_1 AS_000_INT_i N_69_1 cpu_est_i_1__n N_68_1 \ +cpu_est_i_0__n state_machine_uds_000_int_5_0_m2_un3_n AMIGA_BUS_ENABLE_i \ +state_machine_uds_000_int_5_0_m2_un1_n AS_030_i \ +state_machine_uds_000_int_5_0_m2_un0_n cpu_est_i_2__n lds_000_int_0_un3_n \ +sm_amiga_i_2__n lds_000_int_0_un1_n sm_amiga_i_3__n lds_000_int_0_un0_n \ +sm_amiga_i_5__n vpa_sync_0_un3_n state_machine_un8_clk_000_d2_i_n \ +vpa_sync_0_un1_n sm_amiga_i_7__n vpa_sync_0_un0_n a_i_0__n vma_int_0_un3_n \ +size_i_1__n vma_int_0_un1_n dsack_i_1__n vma_int_0_un0_n CLK_000_D2_i \ +bgack_030_int_0_un3_n AS_030_000_SYNC_i bgack_030_int_0_un1_n a_i_30__n \ +bgack_030_int_0_un0_n a_i_31__n as_000_int_0_un3_n a_i_28__n \ +as_000_int_0_un1_n a_i_29__n as_000_int_0_un0_n a_i_26__n ipl_030_0_0__un3_n \ +a_i_27__n ipl_030_0_0__un1_n a_i_24__n ipl_030_0_0__un0_n a_i_25__n \ +ipl_030_0_1__un3_n a_i_19__n ipl_030_0_1__un1_n a_i_16__n ipl_030_0_1__un0_n \ +a_i_18__n ipl_030_0_2__un3_n RST_i ipl_030_0_2__un1_n ipl_030_0_2__un0_n \ +cpu_estse_0_un3_n cpu_estse_0_un1_n CLK_OSZI_i cpu_estse_0_un0_n \ +cpu_estse_1_un3_n N_70_i cpu_estse_1_un1_n N_72_i cpu_estse_1_un0_n \ +FPU_CS_INT_i cpu_estse_2_un3_n BGACK_030_INT_i cpu_estse_2_un1_n CLK_000_D5_i \ +cpu_estse_2_un0_n AS_030_c as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n \ +as_030_000_sync_0_un0_n DS_030_c dtack_sync_0_un3_n dtack_sync_0_un1_n \ +dtack_sync_0_un0_n fpu_cs_int_0_un3_n size_c_0__n fpu_cs_int_0_un1_n \ +fpu_cs_int_0_un0_n size_c_1__n dsack_int_0_1__un3_n dsack_int_0_1__un1_n \ +a_c_0__n dsack_int_0_1__un0_n amiga_bus_enable_0_un3_n \ +amiga_bus_enable_0_un1_n amiga_bus_enable_0_un0_n uds_000_int_0_un3_n \ +uds_000_int_0_un1_n uds_000_int_0_un0_n a_15__n a_14__n a_13__n a_12__n \ +a_11__n a_c_16__n a_10__n a_c_17__n a_9__n a_c_18__n a_8__n a_c_19__n a_7__n \ +a_c_20__n a_6__n a_c_21__n a_5__n a_c_22__n a_4__n a_c_23__n a_3__n a_c_24__n \ +a_2__n a_c_25__n a_1__n a_c_26__n a_c_27__n a_c_28__n a_c_29__n a_c_30__n \ +a_c_31__n nEXP_SPACE_c BG_030_c BGACK_000_c CLK_030_c DSACK_1_.OE DTACK.OE \ +AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE G_102 \ +G_108 +.names cpu_estse_1_un1_n.BLIF cpu_estse_1_un0_n.BLIF cpu_est_2_.D +1- 1 +-1 1 +.names cpu_estse_2_un1_n.BLIF cpu_estse_2_un0_n.BLIF cpu_est_3_reg.D +1- 1 +-1 1 +.names cpu_est_ns_e_0_0__n.BLIF cpu_est_0_.D +0 1 +.names cpu_estse_0_un1_n.BLIF cpu_estse_0_un0_n.BLIF cpu_est_1_.D +1- 1 +-1 1 +.names N_84_i.BLIF N_130_i.BLIF SM_AMIGA_3_.D +11 1 +.names sm_amiga_ns_0_5__n.BLIF SM_AMIGA_2_.D +0 1 +.names N_93_i.BLIF N_94_i.BLIF SM_AMIGA_1_.D +11 1 +.names sm_amiga_ns_0_7__n.BLIF SM_AMIGA_0_.D +0 1 +.names G_102.BLIF CLK_CNT_N_0_.D +0 1 +.names G_108.BLIF CLK_CNT_P_0_.D +0 1 .names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF IPL_030DFFSH_0_reg.D 1- 1 -1 1 @@ -276,45 +297,22 @@ LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_OUT_PRE_0 G_92 G_96 -1 1 .names sm_amiga_ns_0_0__n.BLIF SM_AMIGA_7_.D 0 1 -.names N_83_i.BLIF N_85_i.BLIF SM_AMIGA_6_.D +.names N_77_i.BLIF N_79_i.BLIF SM_AMIGA_6_.D 11 1 -.names inst_CLK_000_D0.BLIF N_86_i.BLIF SM_AMIGA_5_.D +.names inst_CLK_000_D0.BLIF N_81_i.BLIF SM_AMIGA_5_.D 11 1 -.names CLK_000_D0_i.BLIF N_88_i.BLIF SM_AMIGA_4_.D +.names CLK_000_D0_i.BLIF N_82_i.BLIF SM_AMIGA_4_.D 11 1 -.names N_89_i.BLIF N_90_i.BLIF SM_AMIGA_3_.D -11 1 -.names sm_amiga_ns_0_5__n.BLIF SM_AMIGA_2_.D -0 1 -.names N_39_0.BLIF SM_AMIGA_1_.D -0 1 -.names sm_amiga_ns_0_7__n.BLIF SM_AMIGA_0_.D -0 1 -.names clk_cnt_i_0__n.BLIF clk_clk_cnt_i_n.BLIF CLK_CNT_0_.D -11 1 -.names clk_clk_cnt_i_n.BLIF G_96.BLIF CLK_CNT_1_.D -11 1 -.names N_14_0.BLIF cpu_est_0_.D -0 1 -.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D -1- 1 --1 1 -.names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D -1- 1 --1 1 -.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_reg.D -1- 1 --1 1 .names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INTreg.D 1- 1 -1 1 .names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF inst_LDS_000_INTreg.D 1- 1 -1 1 -.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D +.names vpa_sync_0_un1_n.BLIF vpa_sync_0_un0_n.BLIF inst_VPA_SYNC.D 1- 1 -1 1 -.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF BG_000DFFSHreg.D +.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D 1- 1 -1 1 .names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF \ @@ -324,6 +322,8 @@ inst_BGACK_030_INTreg.D .names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF inst_AS_000_INTreg.D 1- 1 -1 1 +.names G_108.BLIF G_102.BLIF inst_CLK_OUT_PRE.D +11 1 .names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF \ inst_AS_030_000_SYNC.D 1- 1 @@ -337,15 +337,14 @@ inst_AS_030_000_SYNC.D .names dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF DSACK_INT_1_.D 1- 1 -1 1 -.names vpa_sync_0_un1_n.BLIF vpa_sync_0_un0_n.BLIF inst_VPA_SYNC.D -1- 1 --1 1 .names amiga_bus_enable_0_un1_n.BLIF amiga_bus_enable_0_un0_n.BLIF \ AMIGA_BUS_ENABLEDFFreg.D 1- 1 -1 1 .names state_machine_un7_as_000_int_n.BLIF inst_DTACK_DMA.D 0 1 +.names state_machine_un10_bg_030_n.BLIF BG_000DFFSHreg.D +0 1 .names vcc_n_n 1 .names gnd_n_n @@ -354,572 +353,535 @@ AMIGA_BUS_ENABLEDFFreg.D .names state_machine_un8_clk_000_d2_1_n.BLIF CLK_000_D2_i.BLIF \ state_machine_un8_clk_000_d2_n 11 1 -.names state_machine_un23_clk_000_d0_i_n.BLIF state_machine_un23_clk_000_d0_n +.names state_machine_un23_clk_000_d0_0_n.BLIF state_machine_un23_clk_000_d0_n 0 1 .names inst_CLK_000_D4.BLIF CLK_000_D5_i.BLIF state_machine_un6_clk_000_d4_n 11 1 -.names clk_cnt_i_0__n.BLIF N_137_i.BLIF clk_clk_cnt_n +.names state_machine_un10_bg_030_3_n.BLIF SM_AMIGA_7_.BLIF \ +state_machine_un10_bg_030_n 11 1 .names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n 0 1 +.names cpu_est_ns_0_1_1__n.BLIF cpu_est_ns_0_2_1__n.BLIF cpu_est_ns_0_1__n +11 1 +.names N_126.BLIF N_126_i +0 1 +.names N_128.BLIF N_128_i +0 1 .names AS_000_INT_i.BLIF dsack_i_1__n.BLIF state_machine_un7_as_000_int_n 11 1 +.names N_216.BLIF N_216_i +0 1 .names state_machine_un15_clk_000_d0_0_n.BLIF state_machine_un15_clk_000_d0_n 0 1 -.names clk_cpu_est_11_0_1_1__n.BLIF clk_cpu_est_11_0_2_1__n.BLIF \ -clk_cpu_est_11_0_1__n -11 1 +.names N_217.BLIF N_217_i +0 1 .names state_machine_lds_000_int_5_0_n.BLIF state_machine_lds_000_int_5_n 0 1 -.names N_124.BLIF N_124_i -0 1 +.names inst_CLK_000_D0.BLIF SM_AMIGA_4_.BLIF N_61_0 +11 1 .names state_machine_uds_000_int_5_0_n.BLIF state_machine_uds_000_int_5_n 0 1 -.names N_146.BLIF N_146_i -0 1 +.names CLK_000_D0_i.BLIF N_54_i.BLIF N_60_0 +11 1 .names un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2 0 1 -.names N_121.BLIF N_121_i +.names N_129.BLIF N_129_i 0 1 -.names N_122.BLIF N_122_i -0 1 -.names SM_AMIGA_3_.BLIF state_machine_un23_clk_000_d0_i_n.BLIF N_66_0 -11 1 -.names CLK_000_D0_i.BLIF N_58_i.BLIF N_65_0 -11 1 -.names N_145.BLIF N_145_i -0 1 -.names N_52_i.BLIF N_145_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 +.names N_50_i.BLIF N_129_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 11 1 .names DS_030_c.BLIF DS_030_c_i 0 1 -.names DS_030_c_i.BLIF N_51.BLIF N_63_i +.names DS_030_c_i.BLIF N_47.BLIF N_58_i 11 1 -.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_62_i +.names cpu_est_3_reg.BLIF cpu_est_i_1__n.BLIF N_57_i 11 1 -.names state_machine_un6_clk_000_d4_n.BLIF state_machine_un6_clk_000_d4_i_n -0 1 -.names CLK_000_D0_i.BLIF state_machine_un6_clk_000_d4_i_n.BLIF N_61_i +.names SM_AMIGA_1_.BLIF state_machine_un6_clk_000_d4_n.BLIF N_55_i 11 1 -.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF N_60_i +.names SM_AMIGA_6_.BLIF nEXP_SPACE_c.BLIF N_54_i 11 1 -.names inst_AS_000_INTreg.BLIF inst_CLK_000_D0.BLIF N_59_i +.names N_53_i_4.BLIF N_53_i_5.BLIF N_53_i 11 1 -.names SM_AMIGA_6_.BLIF nEXP_SPACE_c.BLIF N_58_i -11 1 -.names N_57_i_4.BLIF N_57_i_5.BLIF N_57_i +.names AS_030_i.BLIF N_55.BLIF N_50_i 11 1 .names inst_CLK_000_D1.BLIF CLK_000_D1_i 0 1 -.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF N_56_i +.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF N_49_i 11 1 -.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_55_i +.names inst_AS_000_INTreg.BLIF inst_CLK_000_D0.BLIF N_48_i 11 1 -.names AS_030_i.BLIF N_74_i.BLIF N_52_i -11 1 -.names N_141.BLIF N_141_i +.names N_122.BLIF N_122_i 0 1 -.names N_142.BLIF N_142_i +.names N_123.BLIF N_123_i 0 1 -.names N_141_i.BLIF N_142_i.BLIF N_14_0 -11 1 -.names N_85.BLIF N_85_i -0 1 -.names N_139.BLIF N_139_i -0 1 -.names clk_cpu_est_11_0_1__n.BLIF clk_cpu_est_11_1__n -0 1 -.names N_140.BLIF N_140_i -0 1 -.names clk_cpu_est_11_0_3__n.BLIF clk_cpu_est_11_3__n -0 1 -.names sm_amiga_ns_0_1_0__n.BLIF N_139_i.BLIF sm_amiga_ns_0_0__n -11 1 -.names N_125.BLIF N_125_i -0 1 -.names N_138.BLIF N_138_i -0 1 -.names N_162_0.BLIF N_162 -0 1 -.names N_178.BLIF N_178_i -0 1 -.names N_163_0.BLIF N_163 -0 1 -.names clk_cpu_est_11_0_1_3__n.BLIF N_138_i.BLIF clk_cpu_est_11_0_3__n -11 1 -.names N_164_0.BLIF N_164 -0 1 -.names N_119.BLIF N_119_i -0 1 -.names N_165_0.BLIF N_165 -0 1 -.names N_58.BLIF N_119_i.BLIF N_43_i -11 1 -.names N_30_0.BLIF N_30 -0 1 -.names N_117.BLIF N_117_i -0 1 -.names N_118.BLIF N_118_i -0 1 -.names state_machine_uds_000_int_5_0_m2_un1_n.BLIF \ -state_machine_uds_000_int_5_0_m2_un0_n.BLIF N_51 -1- 1 --1 1 -.names N_117_i.BLIF N_118_i.BLIF N_123_i -11 1 -.names N_52_i.BLIF N_52 -0 1 -.names N_115.BLIF N_115_i -0 1 -.names N_55_i.BLIF N_55 -0 1 -.names N_116.BLIF N_116_i -0 1 -.names N_56_i.BLIF N_56 -0 1 -.names N_115_i.BLIF N_116_i.BLIF sm_amiga_ns_0_7__n -11 1 -.names N_57_i.BLIF N_57 -0 1 -.names N_98.BLIF N_98_i -0 1 -.names N_58_i.BLIF N_58 -0 1 -.names N_114.BLIF N_114_i -0 1 -.names N_59_i.BLIF N_59 -0 1 -.names N_98_i.BLIF N_114_i.BLIF N_39_0 -11 1 -.names N_60_i.BLIF N_60 -0 1 -.names N_94.BLIF N_94_i -0 1 -.names N_61_i.BLIF N_61 -0 1 -.names N_97.BLIF N_97_i -0 1 -.names N_62_i.BLIF N_62 -0 1 -.names N_94_i.BLIF N_97_i.BLIF sm_amiga_ns_0_5__n -11 1 -.names N_63_i.BLIF N_63 -0 1 -.names N_89.BLIF N_89_i -0 1 -.names N_65_0.BLIF N_65 -0 1 -.names N_90.BLIF N_90_i -0 1 -.names N_66_0.BLIF N_66 -0 1 -.names BG_030_i.BLIF CLK_030_c.BLIF N_69 -11 1 -.names N_88.BLIF N_88_i -0 1 -.names N_72_1.BLIF N_72_2.BLIF N_72 -11 1 -.names N_73_1.BLIF N_73_2.BLIF N_73 -11 1 -.names N_86.BLIF N_86_i -0 1 -.names SM_AMIGA_1_.BLIF state_machine_un6_clk_000_d4_n.BLIF N_74 -11 1 -.names N_75_4.BLIF N_75_5.BLIF N_75 -11 1 -.names N_83.BLIF N_83_i -0 1 -.names CLK_030_c.BLIF N_57_i.BLIF N_76 -11 1 -.names N_77_1_0.BLIF inst_VPA_D.BLIF N_77 -11 1 -.names N_81.BLIF N_81_i -0 1 -.names N_79_1.BLIF N_79_2.BLIF N_79 -11 1 -.names N_63_i.BLIF N_81_i.BLIF state_machine_lds_000_int_5_0_n -11 1 -.names N_81_1.BLIF size_i_1__n.BLIF N_81 -11 1 -.names a_i_0__n.BLIF N_63_i.BLIF state_machine_uds_000_int_5_0_n -11 1 -.names N_65.BLIF sm_amiga_i_7__n.BLIF N_83 +.names N_122_i.BLIF N_123_i.BLIF cpu_est_ns_e_0_0__n 11 1 .names N_79.BLIF N_79_i 0 1 -.names SM_AMIGA_7_.BLIF state_machine_un8_clk_000_d2_i_n.BLIF N_85 -11 1 -.names N_79_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0.BLIF N_30_0 -11 1 -.names sm_amiga_i_5__n.BLIF sm_amiga_i_6__n.BLIF N_86 -11 1 -.names AS_030_i.BLIF N_77_i.BLIF N_165_0 -11 1 -.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_88 -11 1 -.names N_76.BLIF N_76_i +.names N_226.BLIF N_226_i 0 1 -.names CLK_000_D0_i.BLIF N_66.BLIF N_89 -11 1 -.names AS_030_i.BLIF N_76_i.BLIF N_164_0 -11 1 -.names sm_amiga_i_3__n.BLIF sm_amiga_i_4__n.BLIF N_90 -11 1 -.names AS_030_i.BLIF N_75_i.BLIF N_163_0 -11 1 -.names CLK_000_D0_i.BLIF SM_AMIGA_2_.BLIF N_94 -11 1 -.names N_72.BLIF N_72_i +.names N_227.BLIF N_227_i 0 1 -.names N_97_1.BLIF state_machine_un23_clk_000_d0_n.BLIF N_97 +.names sm_amiga_ns_0_1_0__n.BLIF N_226_i.BLIF sm_amiga_ns_0_0__n +11 1 +.names N_222.BLIF N_222_i +0 1 +.names N_223.BLIF N_223_i +0 1 +.names N_225.BLIF N_225_i +0 1 +.names cpu_est_ns_0_1_2__n.BLIF N_223_i.BLIF cpu_est_ns_0_2__n +11 1 +.names N_221.BLIF N_221_i +0 1 +.names N_54.BLIF N_221_i.BLIF N_41_i +11 1 +.names N_127.BLIF N_127_i +0 1 +.names N_220.BLIF N_220_i +0 1 +.names cpu_est_ns_0_1__n.BLIF cpu_est_ns_1__n +0 1 +.names N_127_i.BLIF N_220_i.BLIF N_157_i +11 1 +.names cpu_est_ns_0_2__n.BLIF cpu_est_ns_2__n +0 1 +.names N_214.BLIF N_214_i +0 1 +.names N_203_0.BLIF N_203 +0 1 +.names N_215.BLIF N_215_i +0 1 +.names N_204_0.BLIF N_204 +0 1 +.names N_214_i.BLIF N_215_i.BLIF sm_amiga_ns_0_7__n +11 1 +.names N_205_0.BLIF N_205 +0 1 +.names N_93.BLIF N_93_i +0 1 +.names N_23_0.BLIF N_23 +0 1 +.names N_94.BLIF N_94_i +0 1 +.names N_27_0.BLIF N_27 +0 1 +.names state_machine_uds_000_int_5_0_m2_un1_n.BLIF \ +state_machine_uds_000_int_5_0_m2_un0_n.BLIF N_47 +1- 1 +-1 1 +.names N_85.BLIF N_85_i +0 1 +.names N_48_i.BLIF N_48 +0 1 +.names N_86.BLIF N_86_i +0 1 +.names N_49_i.BLIF N_49 +0 1 +.names N_85_i.BLIF N_86_i.BLIF sm_amiga_ns_0_5__n +11 1 +.names N_50_i.BLIF N_50 +0 1 +.names N_84.BLIF N_84_i +0 1 +.names N_53_i.BLIF N_53 +0 1 +.names N_130.BLIF N_130_i +0 1 +.names N_54_i.BLIF N_54 +0 1 +.names N_55_i.BLIF N_55 +0 1 +.names N_82.BLIF N_82_i +0 1 +.names N_57_i.BLIF N_57 +0 1 +.names N_58_i.BLIF N_58 +0 1 +.names N_81.BLIF N_81_i +0 1 +.names N_60_0.BLIF N_60 +0 1 +.names N_61_0.BLIF N_61 +0 1 +.names N_77.BLIF N_77_i +0 1 +.names N_68_1.BLIF VPA_D_i.BLIF N_68 +11 1 +.names N_69_1.BLIF cpu_est_2_.BLIF N_69 +11 1 +.names N_75.BLIF N_75_i +0 1 +.names N_70_3.BLIF VPA_D_i.BLIF N_70 +11 1 +.names N_58_i.BLIF N_75_i.BLIF state_machine_lds_000_int_5_0_n +11 1 +.names CLK_030_c.BLIF N_53_i.BLIF N_71 +11 1 +.names a_i_0__n.BLIF N_58_i.BLIF state_machine_uds_000_int_5_0_n +11 1 +.names N_72_1.BLIF N_72_2.BLIF N_72 11 1 .names N_73.BLIF N_73_i 0 1 -.names N_61.BLIF SM_AMIGA_1_.BLIF N_98 +.names N_73_1.BLIF N_73_2.BLIF N_73 11 1 -.names N_72_i.BLIF N_73_i.BLIF state_machine_un15_clk_000_d0_0_n +.names N_73_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0.BLIF N_27_0 11 1 -.names inst_CLK_000_D0.BLIF SM_AMIGA_2_.BLIF N_114 +.names N_75_1.BLIF size_i_1__n.BLIF N_75 11 1 -.names AS_030_i.BLIF N_63.BLIF N_162_0 +.names AS_030_i.BLIF N_72_i.BLIF N_23_0 11 1 -.names N_59.BLIF SM_AMIGA_0_.BLIF N_115 +.names N_60.BLIF sm_amiga_i_7__n.BLIF N_77 11 1 -.names BGACK_000_c.BLIF N_56.BLIF state_machine_un6_bgack_000_0_n +.names N_71.BLIF N_71_i +0 1 +.names SM_AMIGA_7_.BLIF state_machine_un8_clk_000_d2_i_n.BLIF N_79 11 1 -.names N_61_i.BLIF SM_AMIGA_1_.BLIF N_116 +.names AS_030_i.BLIF N_71_i.BLIF N_205_0 +11 1 +.names sm_amiga_i_5__n.BLIF sm_amiga_i_6__n.BLIF N_81 +11 1 +.names AS_030_i.BLIF N_70_i.BLIF N_204_0 +11 1 +.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_82 +11 1 +.names N_68.BLIF N_68_i +0 1 +.names N_61.BLIF sm_amiga_i_3__n.BLIF N_84 +11 1 +.names N_69.BLIF N_69_i +0 1 +.names CLK_000_D0_i.BLIF SM_AMIGA_2_.BLIF N_85 +11 1 +.names N_68_i.BLIF N_69_i.BLIF state_machine_un15_clk_000_d0_0_n +11 1 +.names N_130.BLIF SM_AMIGA_3_.BLIF N_86 +11 1 +.names AS_030_i.BLIF N_58.BLIF N_203_0 +11 1 +.names CLK_000_D0_i.BLIF N_55.BLIF N_93 +11 1 +.names BGACK_000_c.BLIF N_49.BLIF state_machine_un6_bgack_000_0_n +11 1 +.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_94 +11 1 +.names N_48.BLIF SM_AMIGA_0_.BLIF N_214 11 1 .names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF \ -state_machine_un23_clk_000_d0_i_n +state_machine_un23_clk_000_d0_0_n 11 1 -.names N_117_1.BLIF cpu_est_i_3__n.BLIF N_117 +.names N_215_1.BLIF state_machine_un6_clk_000_d4_i_n.BLIF N_215 11 1 -.names a_i_24__n.BLIF a_i_25__n.BLIF N_188_1 +.names a_i_24__n.BLIF a_i_25__n.BLIF N_238_1 11 1 -.names N_118_1.BLIF cpu_est_i_2__n.BLIF N_118 +.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF N_216 11 1 -.names a_i_26__n.BLIF a_i_27__n.BLIF N_188_2 +.names a_i_26__n.BLIF a_i_27__n.BLIF N_238_2 11 1 -.names N_119_1.BLIF sm_amiga_i_6__n.BLIF N_119 +.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_217 11 1 -.names a_i_28__n.BLIF a_i_29__n.BLIF N_188_3 +.names a_i_28__n.BLIF a_i_29__n.BLIF N_238_3 11 1 -.names N_120_1.BLIF N_120_2.BLIF N_120 +.names N_57.BLIF cpu_est_2_.BLIF N_220 11 1 -.names a_i_30__n.BLIF a_i_31__n.BLIF N_188_4 +.names a_i_30__n.BLIF a_i_31__n.BLIF N_238_4 11 1 -.names N_60.BLIF cpu_est_i_0__n.BLIF N_121 +.names N_221_1.BLIF sm_amiga_i_6__n.BLIF N_221 11 1 -.names N_188_1.BLIF N_188_2.BLIF N_188_5 +.names N_238_1.BLIF N_238_2.BLIF N_238_5 11 1 -.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_122 +.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_222 11 1 -.names N_188_3.BLIF N_188_4.BLIF N_188_6 +.names N_238_3.BLIF N_238_4.BLIF N_238_6 11 1 -.names N_55_i.BLIF cpu_est_3_reg.BLIF N_124 +.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_223 11 1 -.names a_c_20__n.BLIF a_c_21__n.BLIF N_191_1 +.names a_c_20__n.BLIF a_c_21__n.BLIF N_241_1 11 1 -.names N_62.BLIF cpu_est_3_reg.BLIF N_125 +.names cpu_est_0_.BLIF cpu_est_3_reg.BLIF N_225 11 1 -.names a_c_22__n.BLIF a_c_23__n.BLIF N_191_2 +.names a_c_22__n.BLIF a_c_23__n.BLIF N_241_2 11 1 -.names N_62_i.BLIF cpu_est_i_2__n.BLIF N_178 +.names CLK_000_D0_i.BLIF N_129.BLIF N_226 11 1 .names inst_CLK_000_D3.BLIF AS_030_000_SYNC_i.BLIF \ state_machine_un8_clk_000_d2_1_n 11 1 -.names N_138_1.BLIF cpu_est_i_2__n.BLIF N_138 +.names N_48_i.BLIF SM_AMIGA_0_.BLIF N_227 11 1 -.names a_c_17__n.BLIF BGACK_000_c.BLIF N_57_i_1 +.names a_c_17__n.BLIF BGACK_000_c.BLIF N_53_i_1 11 1 -.names CLK_000_D0_i.BLIF N_145.BLIF N_139 +.names N_49.BLIF cpu_est_0_.BLIF N_122 11 1 -.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_57_i_2 +.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_53_i_2 11 1 -.names N_59_i.BLIF SM_AMIGA_0_.BLIF N_140 +.names N_49_i.BLIF cpu_est_i_0__n.BLIF N_123 11 1 -.names a_i_19__n.BLIF a_i_16__n.BLIF N_57_i_3 +.names a_i_19__n.BLIF a_i_16__n.BLIF N_53_i_3 11 1 -.names N_56.BLIF cpu_est_0_.BLIF N_141 +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_126 11 1 -.names N_57_i_1.BLIF N_57_i_2.BLIF N_57_i_4 +.names N_53_i_1.BLIF N_53_i_2.BLIF N_53_i_4 11 1 -.names N_56_i.BLIF cpu_est_i_0__n.BLIF N_142 +.names N_126.BLIF cpu_est_i_3__n.BLIF N_127 11 1 -.names N_57_i_3.BLIF a_i_18__n.BLIF N_57_i_5 +.names N_53_i_3.BLIF a_i_18__n.BLIF N_53_i_5 11 1 -.names SM_AMIGA_6_.BLIF nEXP_SPACE_i.BLIF N_145 +.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_128 11 1 -.names N_121_i.BLIF N_122_i.BLIF clk_cpu_est_11_0_1_1__n +.names N_126_i.BLIF N_128_i.BLIF cpu_est_ns_0_1_1__n 11 1 -.names N_60_i.BLIF cpu_est_0_.BLIF N_146 +.names SM_AMIGA_6_.BLIF nEXP_SPACE_i.BLIF N_129 11 1 -.names N_124_i.BLIF N_146_i.BLIF clk_cpu_est_11_0_2_1__n +.names N_216_i.BLIF N_217_i.BLIF cpu_est_ns_0_2_1__n 11 1 -.names inst_CLK_000_D0.BLIF SM_AMIGA_3_.BLIF N_77_1 +.names CLK_000_D0_i.BLIF state_machine_un23_clk_000_d0_n.BLIF N_130 11 1 -.names AS_030_c.BLIF BG_030_i.BLIF N_120_1 +.names nEXP_SPACE_i.BLIF AS_030_c.BLIF state_machine_un10_bg_030_1_n 11 1 -.names N_188_5.BLIF N_188_6.BLIF N_188 +.names N_238_5.BLIF N_238_6.BLIF N_238 11 1 -.names SM_AMIGA_7_.BLIF nEXP_SPACE_i.BLIF N_120_2 +.names BG_030_i.BLIF N_49_i.BLIF state_machine_un10_bg_030_2_n 11 1 -.names N_191_1.BLIF N_191_2.BLIF N_191 +.names N_241_1.BLIF N_241_2.BLIF N_241 11 1 -.names CLK_030_c.BLIF N_57.BLIF N_79_1 +.names state_machine_un10_bg_030_1_n.BLIF state_machine_un10_bg_030_2_n.BLIF \ +state_machine_un10_bg_030_3_n 11 1 .names RW_c.BLIF RW_i 0 1 -.names SM_AMIGA_7_.BLIF nEXP_SPACE_c.BLIF N_79_2 -11 1 -.names inst_VPA_D.BLIF VPA_D_i -0 1 -.names DTACK_i.BLIF N_77_1.BLIF N_77_1_0 -11 1 -.names inst_CLK_000_D0.BLIF CLK_000_D0_i -0 1 -.names N_77_1.BLIF VMA_INT_i.BLIF N_75_1 -11 1 -.names cpu_est_0_.BLIF cpu_est_i_0__n -0 1 -.names VPA_D_i.BLIF cpu_est_2_.BLIF N_75_2 -11 1 -.names cpu_est_3_reg.BLIF cpu_est_i_3__n -0 1 -.names cpu_est_3_reg.BLIF cpu_est_i_0__n.BLIF N_75_3 +.names CLK_030_c.BLIF N_53.BLIF N_73_1 11 1 .names inst_VMA_INTreg.BLIF VMA_INT_i 0 1 -.names N_75_1.BLIF N_75_2.BLIF N_75_4 +.names SM_AMIGA_7_.BLIF nEXP_SPACE_c.BLIF N_73_2 11 1 -.names cpu_est_1_.BLIF cpu_est_i_1__n +.names inst_VPA_D.BLIF VPA_D_i 0 1 -.names N_75_3.BLIF cpu_est_i_1__n.BLIF N_75_5 +.names inst_CLK_000_D0.BLIF DTACK_i.BLIF N_72_1 11 1 .names DTACK_c.BLIF DTACK_i 0 1 -.names N_55_i.BLIF N_59_i.BLIF N_73_1 +.names SM_AMIGA_3_.BLIF inst_VPA_D.BLIF N_72_2 11 1 .names BG_030_c.BLIF BG_030_i 0 1 -.names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF N_73_2 +.names inst_CLK_000_D0.BLIF N_57_i.BLIF N_70_1 11 1 .names nEXP_SPACE_c.BLIF nEXP_SPACE_i 0 1 -.names CLK_000_D0_i.BLIF N_146.BLIF N_72_1 +.names SM_AMIGA_3_.BLIF VMA_INT_i.BLIF N_70_2 11 1 -.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n +.names inst_CLK_000_D0.BLIF CLK_000_D0_i 0 1 -.names VPA_D_i.BLIF cpu_est_2_.BLIF N_72_2 -11 1 -.names inst_AS_000_INTreg.BLIF AS_000_INT_i -0 1 -.names N_140_i.BLIF N_85_i.BLIF sm_amiga_ns_0_1_0__n -11 1 -.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n -0 1 -.names N_178_i.BLIF N_125_i.BLIF clk_cpu_est_11_0_1_3__n -11 1 -.names cpu_est_2_.BLIF cpu_est_i_2__n -0 1 -.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_138_1 -11 1 -.names AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLE_i -0 1 -.names AMIGA_BUS_ENABLE_i.BLIF AS_030_i.BLIF N_119_1 -11 1 -.names AS_030_c.BLIF AS_030_i -0 1 -.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_118_1 +.names N_70_1.BLIF N_70_2.BLIF N_70_3 11 1 .names SM_AMIGA_4_.BLIF sm_amiga_i_4__n 0 1 -.names N_55.BLIF cpu_est_0_.BLIF N_117_1 +.names N_227_i.BLIF N_79_i.BLIF sm_amiga_ns_0_1_0__n 11 1 -.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +.names cpu_est_3_reg.BLIF cpu_est_i_3__n 0 1 -.names CLK_000_D0_i.BLIF SM_AMIGA_3_.BLIF N_97_1 +.names N_225_i.BLIF N_222_i.BLIF cpu_est_ns_0_1_2__n 11 1 -.names state_machine_un8_clk_000_d2_n.BLIF state_machine_un8_clk_000_d2_i_n +.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n 0 1 -.names a_i_0__n.BLIF size_c_0__n.BLIF N_81_1 +.names AMIGA_BUS_ENABLE_i.BLIF AS_030_i.BLIF N_221_1 11 1 -.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n +.names state_machine_un6_clk_000_d4_n.BLIF state_machine_un6_clk_000_d4_i_n +0 1 +.names CLK_000_D0_i.BLIF SM_AMIGA_1_.BLIF N_215_1 +11 1 +.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n +0 1 +.names a_i_0__n.BLIF size_c_0__n.BLIF N_75_1 +11 1 +.names inst_AS_000_INTreg.BLIF AS_000_INT_i +0 1 +.names N_48_i.BLIF N_127.BLIF N_69_1 +11 1 +.names cpu_est_1_.BLIF cpu_est_i_1__n +0 1 +.names CLK_000_D0_i.BLIF N_128.BLIF N_68_1 +11 1 +.names cpu_est_0_.BLIF cpu_est_i_0__n 0 1 .names RW_c.BLIF state_machine_uds_000_int_5_0_m2_un3_n 0 1 -.names a_c_0__n.BLIF a_i_0__n +.names AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLE_i 0 1 .names SM_AMIGA_5_.BLIF RW_c.BLIF state_machine_uds_000_int_5_0_m2_un1_n 11 1 -.names size_c_1__n.BLIF size_i_1__n +.names AS_030_c.BLIF AS_030_i 0 1 .names SM_AMIGA_4_.BLIF state_machine_uds_000_int_5_0_m2_un3_n.BLIF \ state_machine_uds_000_int_5_0_m2_un0_n 11 1 -.names dsack_c_1__n.BLIF dsack_i_1__n +.names cpu_est_2_.BLIF cpu_est_i_2__n 0 1 -.names N_163.BLIF vpa_sync_0_un3_n +.names N_203.BLIF lds_000_int_0_un3_n 0 1 -.names clk_clk_cnt_n.BLIF clk_clk_cnt_i_n +.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n 0 1 -.names N_75_i.BLIF N_163.BLIF vpa_sync_0_un1_n +.names state_machine_lds_000_int_5_n.BLIF N_203.BLIF lds_000_int_0_un1_n 11 1 -.names CLK_CNT_0_.BLIF clk_cnt_i_0__n -0 1 -.names inst_VPA_SYNC.BLIF vpa_sync_0_un3_n.BLIF vpa_sync_0_un0_n -11 1 -.names inst_CLK_000_D2.BLIF CLK_000_D2_i -0 1 -.names RST_c.BLIF amiga_bus_enable_0_un3_n -0 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i -0 1 -.names N_43_i.BLIF RST_c.BLIF amiga_bus_enable_0_un1_n -11 1 -.names a_c_30__n.BLIF a_i_30__n -0 1 -.names AMIGA_BUS_ENABLEDFFreg.BLIF amiga_bus_enable_0_un3_n.BLIF \ -amiga_bus_enable_0_un0_n -11 1 -.names a_c_31__n.BLIF a_i_31__n -0 1 -.names N_162.BLIF uds_000_int_0_un3_n -0 1 -.names a_c_28__n.BLIF a_i_28__n -0 1 -.names state_machine_uds_000_int_5_n.BLIF N_162.BLIF uds_000_int_0_un1_n -11 1 -.names a_c_29__n.BLIF a_i_29__n -0 1 -.names inst_UDS_000_INTreg.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n -11 1 -.names a_c_26__n.BLIF a_i_26__n -0 1 -.names N_162.BLIF lds_000_int_0_un3_n -0 1 -.names a_c_27__n.BLIF a_i_27__n -0 1 -.names state_machine_lds_000_int_5_n.BLIF N_162.BLIF lds_000_int_0_un1_n -11 1 -.names a_c_24__n.BLIF a_i_24__n +.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n 0 1 .names inst_LDS_000_INTreg.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n 11 1 -.names a_c_25__n.BLIF a_i_25__n +.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +0 1 +.names N_204.BLIF vpa_sync_0_un3_n +0 1 +.names state_machine_un8_clk_000_d2_n.BLIF state_machine_un8_clk_000_d2_i_n +0 1 +.names N_70_i.BLIF N_204.BLIF vpa_sync_0_un1_n +11 1 +.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n +0 1 +.names inst_VPA_SYNC.BLIF vpa_sync_0_un3_n.BLIF vpa_sync_0_un0_n +11 1 +.names a_c_0__n.BLIF a_i_0__n 0 1 .names state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un3_n 0 1 -.names a_c_19__n.BLIF a_i_19__n +.names size_c_1__n.BLIF size_i_1__n 0 1 -.names cpu_est_1_.BLIF state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un1_n +.names N_48_i.BLIF state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un1_n 11 1 -.names a_c_16__n.BLIF a_i_16__n +.names dsack_c_1__n.BLIF dsack_i_1__n 0 1 .names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n 11 1 -.names a_c_18__n.BLIF a_i_18__n -0 1 -.names N_69.BLIF bg_000_0_un3_n -0 1 -.names G_92.BLIF N_137_i -0 1 -.names BG_000DFFSHreg.BLIF N_69.BLIF bg_000_0_un1_n -11 1 -.names N_120_i.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n -11 1 -.names RST_c.BLIF RST_i +.names inst_CLK_000_D2.BLIF CLK_000_D2_i 0 1 .names state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n 0 1 -.names N_120.BLIF N_120_i +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i 0 1 .names BGACK_000_c.BLIF state_machine_un6_bgack_000_n.BLIF \ bgack_030_int_0_un1_n 11 1 -.names N_75.BLIF N_75_i +.names a_c_30__n.BLIF a_i_30__n 0 1 .names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \ bgack_030_int_0_un0_n 11 1 -.names N_74.BLIF N_74_i +.names a_c_31__n.BLIF a_i_31__n 0 1 .names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n 0 1 -.names N_77.BLIF N_77_i +.names a_c_28__n.BLIF a_i_28__n 0 1 .names inst_AS_000_INTreg.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n 11 1 -.names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i +.names a_c_29__n.BLIF a_i_29__n 0 1 .names sm_amiga_i_5__n.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n 11 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i +.names a_c_26__n.BLIF a_i_26__n 0 1 -.names N_56.BLIF cpu_est_0_1__un3_n +.names N_49.BLIF ipl_030_0_0__un3_n 0 1 -.names inst_CLK_000_D5.BLIF CLK_000_D5_i +.names a_c_27__n.BLIF a_i_27__n 0 1 -.names cpu_est_1_.BLIF N_56.BLIF cpu_est_0_1__un1_n +.names IPL_030DFFSH_0_reg.BLIF N_49.BLIF ipl_030_0_0__un1_n 11 1 -.names clk_cpu_est_11_1__n.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n -11 1 -.names N_56.BLIF cpu_est_0_2__un3_n +.names a_c_24__n.BLIF a_i_24__n 0 1 -.names cpu_est_2_.BLIF N_56.BLIF cpu_est_0_2__un1_n -11 1 -.names N_123_i.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n -11 1 -.names N_56.BLIF cpu_est_0_3__un3_n -0 1 -.names cpu_est_3_reg.BLIF N_56.BLIF cpu_est_0_3__un1_n -11 1 -.names clk_cpu_est_11_3__n.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n -11 1 -.names N_56.BLIF ipl_030_0_0__un3_n -0 1 -.names IPL_030DFFSH_0_reg.BLIF N_56.BLIF ipl_030_0_0__un1_n -11 1 .names ipl_c_0__n.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n 11 1 -.names N_56.BLIF ipl_030_0_1__un3_n +.names a_c_25__n.BLIF a_i_25__n 0 1 -.names IPL_030DFFSH_1_reg.BLIF N_56.BLIF ipl_030_0_1__un1_n +.names N_49.BLIF ipl_030_0_1__un3_n +0 1 +.names a_c_19__n.BLIF a_i_19__n +0 1 +.names IPL_030DFFSH_1_reg.BLIF N_49.BLIF ipl_030_0_1__un1_n 11 1 +.names a_c_16__n.BLIF a_i_16__n +0 1 .names ipl_c_1__n.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n 11 1 -.names N_56.BLIF ipl_030_0_2__un3_n +.names a_c_18__n.BLIF a_i_18__n 0 1 -.names IPL_030DFFSH_2_reg.BLIF N_56.BLIF ipl_030_0_2__un1_n +.names N_49.BLIF ipl_030_0_2__un3_n +0 1 +.names RST_c.BLIF RST_i +0 1 +.names IPL_030DFFSH_2_reg.BLIF N_49.BLIF ipl_030_0_2__un1_n 11 1 .names ipl_c_2__n.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n 11 1 -.names N_30.BLIF as_030_000_sync_0_un3_n +.names N_49.BLIF cpu_estse_0_un3_n 0 1 -.names un1_AMIGA_BUS_ENABLE_1_sqmuxa_2.BLIF N_30.BLIF as_030_000_sync_0_un1_n +.names cpu_est_1_.BLIF N_49.BLIF cpu_estse_0_un1_n +11 1 +.names CLK_OSZI_c.BLIF CLK_OSZI_i +0 1 +.names cpu_est_ns_1__n.BLIF cpu_estse_0_un3_n.BLIF cpu_estse_0_un0_n +11 1 +.names N_49.BLIF cpu_estse_1_un3_n +0 1 +.names N_70.BLIF N_70_i +0 1 +.names cpu_est_2_.BLIF N_49.BLIF cpu_estse_1_un1_n +11 1 +.names N_72.BLIF N_72_i +0 1 +.names cpu_est_ns_2__n.BLIF cpu_estse_1_un3_n.BLIF cpu_estse_1_un0_n +11 1 +.names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i +0 1 +.names N_49.BLIF cpu_estse_2_un3_n +0 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i +0 1 +.names cpu_est_3_reg.BLIF N_49.BLIF cpu_estse_2_un1_n +11 1 +.names inst_CLK_000_D5.BLIF CLK_000_D5_i +0 1 +.names N_157_i.BLIF cpu_estse_2_un3_n.BLIF cpu_estse_2_un0_n +11 1 +.names N_27.BLIF as_030_000_sync_0_un3_n +0 1 +.names un1_AMIGA_BUS_ENABLE_1_sqmuxa_2.BLIF N_27.BLIF as_030_000_sync_0_un1_n 11 1 .names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF \ as_030_000_sync_0_un0_n 11 1 -.names N_165.BLIF dtack_sync_0_un3_n +.names N_23.BLIF dtack_sync_0_un3_n 0 1 -.names N_77_i.BLIF N_165.BLIF dtack_sync_0_un1_n +.names N_72_i.BLIF N_23.BLIF dtack_sync_0_un1_n 11 1 .names inst_DTACK_SYNC.BLIF dtack_sync_0_un3_n.BLIF dtack_sync_0_un0_n 11 1 -.names N_164.BLIF fpu_cs_int_0_un3_n +.names N_205.BLIF fpu_cs_int_0_un3_n 0 1 -.names AS_030_c.BLIF N_164.BLIF fpu_cs_int_0_un1_n +.names AS_030_c.BLIF N_205.BLIF fpu_cs_int_0_un1_n 11 1 .names inst_FPU_CS_INTreg.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un0_n 11 1 -.names N_52.BLIF dsack_int_0_1__un3_n +.names N_50.BLIF dsack_int_0_1__un3_n 0 1 -.names N_74_i.BLIF N_52.BLIF dsack_int_0_1__un1_n +.names N_55.BLIF N_50.BLIF dsack_int_0_1__un1_n 11 1 .names DSACK_INT_1_.BLIF dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un0_n 11 1 +.names RST_c.BLIF amiga_bus_enable_0_un3_n +0 1 +.names N_41_i.BLIF RST_c.BLIF amiga_bus_enable_0_un1_n +11 1 +.names AMIGA_BUS_ENABLEDFFreg.BLIF amiga_bus_enable_0_un3_n.BLIF \ +amiga_bus_enable_0_un0_n +11 1 +.names N_203.BLIF uds_000_int_0_un3_n +0 1 +.names state_machine_uds_000_int_5_n.BLIF N_203.BLIF uds_000_int_0_un1_n +11 1 +.names inst_UDS_000_INTreg.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n +11 1 .names IPL_030DFFSH_2_reg.BLIF IPL_030_2_ 1 1 0 0 @@ -962,7 +924,7 @@ as_030_000_sync_0_un0_n .names inst_VMA_INTreg.BLIF VMA 1 1 0 0 -.names RESETDFFreg.BLIF RESET +.names RESETDFFRHreg.BLIF RESET 1 1 0 0 .names AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLE @@ -974,7 +936,7 @@ as_030_000_sync_0_un0_n .names vcc_n_n.BLIF AMIGA_BUS_ENABLE_LOW 1 1 0 0 -.names N_191.BLIF CIIN +.names N_241.BLIF CIIN 1 1 0 0 .names IPL_030DFFSH_1_reg.BLIF IPL_030_1_ @@ -983,6 +945,84 @@ as_030_000_sync_0_un0_n .names IPL_030DFFSH_0_reg.BLIF IPL_030_0_ 1 1 0 0 +.names CLK_OSZI_c.BLIF cpu_est_2_.C +1 1 +0 0 +.names RST_i.BLIF cpu_est_2_.AR +1 1 +0 0 +.names CLK_OSZI_c.BLIF cpu_est_3_reg.C +1 1 +0 0 +.names RST_i.BLIF cpu_est_3_reg.AR +1 1 +0 0 +.names CLK_OSZI_c.BLIF cpu_est_0_.C +1 1 +0 0 +.names RST_i.BLIF cpu_est_0_.AR +1 1 +0 0 +.names CLK_OSZI_c.BLIF cpu_est_1_.C +1 1 +0 0 +.names RST_i.BLIF cpu_est_1_.AR +1 1 +0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C +1 1 +0 0 +.names RST_i.BLIF SM_AMIGA_3_.AR +1 1 +0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C +1 1 +0 0 +.names RST_i.BLIF SM_AMIGA_2_.AR +1 1 +0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C +1 1 +0 0 +.names RST_i.BLIF SM_AMIGA_1_.AR +1 1 +0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C +1 1 +0 0 +.names RST_i.BLIF SM_AMIGA_0_.AR +1 1 +0 0 +.names CLK_OSZI_i.BLIF CLK_CNT_N_0_.C +1 1 +0 0 +.names RST_i.BLIF CLK_CNT_N_0_.AR +1 1 +0 0 +.names CLK_CNT_N_0_.BLIF CLK_CNT_N_1_.D +1 1 +0 0 +.names CLK_OSZI_i.BLIF CLK_CNT_N_1_.C +1 1 +0 0 +.names RST_i.BLIF CLK_CNT_N_1_.AR +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_CNT_P_0_.C +1 1 +0 0 +.names RST_i.BLIF CLK_CNT_P_0_.AR +1 1 +0 0 +.names CLK_CNT_P_0_.BLIF CLK_CNT_P_1_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_CNT_P_1_.C +1 1 +0 0 +.names RST_i.BLIF CLK_CNT_P_1_.AR +1 1 +0 0 .names CLK_OSZI_c.BLIF IPL_030DFFSH_0_reg.C 1 1 0 0 @@ -1025,48 +1065,6 @@ as_030_000_sync_0_un0_n .names RST_i.BLIF SM_AMIGA_4_.AR 1 1 0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C -1 1 -0 0 -.names RST_i.BLIF SM_AMIGA_3_.AR -1 1 -0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C -1 1 -0 0 -.names RST_i.BLIF SM_AMIGA_2_.AR -1 1 -0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C -1 1 -0 0 -.names RST_i.BLIF SM_AMIGA_1_.AR -1 1 -0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C -1 1 -0 0 -.names RST_i.BLIF SM_AMIGA_0_.AR -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_CNT_0_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_CNT_1_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF cpu_est_0_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF cpu_est_1_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF cpu_est_2_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF cpu_est_3_reg.C -1 1 -0 0 .names CLK_OSZI_c.BLIF inst_UDS_000_INTreg.C 1 1 0 0 @@ -1079,24 +1077,18 @@ as_030_000_sync_0_un0_n .names RST_i.BLIF inst_LDS_000_INTreg.AP 1 1 0 0 +.names CLK_OSZI_c.BLIF inst_VPA_SYNC.C +1 1 +0 0 +.names RST_i.BLIF inst_VPA_SYNC.AP +1 1 +0 0 .names CLK_OSZI_c.BLIF inst_VMA_INTreg.C 1 1 0 0 .names RST_i.BLIF inst_VMA_INTreg.AP 1 1 0 0 -.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C -1 1 -0 0 -.names RST_i.BLIF BG_000DFFSHreg.AP -1 1 -0 0 -.names CLK_OUT_PRE_0.BLIF inst_CLK_OUT_PRE.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE.C -1 1 -0 0 .names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C 1 1 0 0 @@ -1109,6 +1101,21 @@ as_030_000_sync_0_un0_n .names RST_i.BLIF inst_AS_000_INTreg.AP 1 1 0 0 +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE.C +1 1 +0 0 +.names RST_i.BLIF inst_CLK_OUT_PRE.AR +1 1 +0 0 +.names inst_CLK_OUT_PRE.BLIF CLK_OUT_INTreg.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C +1 1 +0 0 +.names RST_i.BLIF CLK_OUT_INTreg.AR +1 1 +0 0 .names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C 1 1 0 0 @@ -1133,31 +1140,28 @@ as_030_000_sync_0_un0_n .names RST_i.BLIF DSACK_INT_1_.AP 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_VPA_SYNC.C -1 1 -0 0 -.names RST_i.BLIF inst_VPA_SYNC.AP -1 1 -0 0 .names CLK_OSZI_c.BLIF AMIGA_BUS_ENABLEDFFreg.C 1 1 0 0 -.names inst_CLK_000_D4.BLIF inst_CLK_000_D5.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_CLK_000_D5.C -1 1 -0 0 .names CLK_OSZI_c.BLIF inst_DTACK_DMA.C 1 1 0 0 .names RST_i.BLIF inst_DTACK_DMA.AP 1 1 0 0 -.names inst_CLK_OUT_PRE.BLIF CLK_OUT_INTreg.D +.names inst_CLK_000_D4.BLIF inst_CLK_000_D5.D 1 1 0 0 -.names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C +.names CLK_OSZI_c.BLIF inst_CLK_000_D5.C +1 1 +0 0 +.names RST_i.BLIF inst_CLK_000_D5.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C +1 1 +0 0 +.names RST_i.BLIF BG_000DFFSHreg.AP 1 1 0 0 .names inst_CLK_000_D3.BLIF inst_CLK_000_D4.D @@ -1166,34 +1170,52 @@ as_030_000_sync_0_un0_n .names CLK_OSZI_c.BLIF inst_CLK_000_D4.C 1 1 0 0 +.names RST_i.BLIF inst_CLK_000_D4.AP +1 1 +0 0 .names inst_CLK_000_D1.BLIF inst_CLK_000_D2.D 1 1 0 0 .names CLK_OSZI_c.BLIF inst_CLK_000_D2.C 1 1 0 0 +.names RST_i.BLIF inst_CLK_000_D2.AP +1 1 +0 0 .names inst_CLK_000_D2.BLIF inst_CLK_000_D3.D 1 1 0 0 .names CLK_OSZI_c.BLIF inst_CLK_000_D3.C 1 1 0 0 +.names RST_i.BLIF inst_CLK_000_D3.AP +1 1 +0 0 .names VPA.BLIF inst_VPA_D.D 1 1 0 0 .names CLK_OSZI_c.BLIF inst_VPA_D.C 1 1 0 0 +.names RST_i.BLIF inst_VPA_D.AP +1 1 +0 0 .names CLK_000.BLIF inst_CLK_000_D0.D 1 1 0 0 .names CLK_OSZI_c.BLIF inst_CLK_000_D0.C 1 1 0 0 -.names RST_c.BLIF RESETDFFreg.D +.names RST_i.BLIF inst_CLK_000_D0.AP 1 1 0 0 -.names CLK_OSZI_c.BLIF RESETDFFreg.C +.names vcc_n_n.BLIF RESETDFFRHreg.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF RESETDFFRHreg.C +1 1 +0 0 +.names RST_i.BLIF RESETDFFRHreg.AR 1 1 0 0 .names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D @@ -1202,13 +1224,7 @@ as_030_000_sync_0_un0_n .names CLK_OSZI_c.BLIF inst_CLK_000_D1.C 1 1 0 0 -.names gnd_n_n.BLIF CLK_REF_1_.D -1 1 -0 0 -.names gnd_n_n.BLIF CLK_REF_1_.LH -1 1 -0 0 -.names RST_i.BLIF CLK_REF_1_.AR +.names RST_i.BLIF inst_CLK_000_D1.AP 1 1 0 0 .names DSACK_INT_1_.BLIF DSACK_1_ @@ -1220,12 +1236,6 @@ as_030_000_sync_0_un0_n .names vcc_n_n.BLIF DSACK_0_ 1 1 0 0 -.names BGACK_000.BLIF BGACK_000_c -1 1 -0 0 -.names CLK_030.BLIF CLK_030_c -1 1 -0 0 .names CLK_OSZI.BLIF CLK_OSZI_c 1 1 0 0 @@ -1271,96 +1281,96 @@ as_030_000_sync_0_un0_n .names A_0_.BLIF a_c_0__n 1 1 0 0 -.names A_16_.BLIF a_c_16__n -1 1 -0 0 .names A_15_.BLIF a_15__n 1 1 0 0 -.names A_17_.BLIF a_c_17__n -1 1 -0 0 .names A_14_.BLIF a_14__n 1 1 0 0 -.names A_18_.BLIF a_c_18__n -1 1 -0 0 .names A_13_.BLIF a_13__n 1 1 0 0 -.names A_19_.BLIF a_c_19__n -1 1 -0 0 .names A_12_.BLIF a_12__n 1 1 0 0 -.names A_20_.BLIF a_c_20__n -1 1 -0 0 .names A_11_.BLIF a_11__n 1 1 0 0 -.names A_21_.BLIF a_c_21__n +.names A_16_.BLIF a_c_16__n 1 1 0 0 .names A_10_.BLIF a_10__n 1 1 0 0 -.names A_22_.BLIF a_c_22__n +.names A_17_.BLIF a_c_17__n 1 1 0 0 .names A_9_.BLIF a_9__n 1 1 0 0 -.names A_23_.BLIF a_c_23__n +.names A_18_.BLIF a_c_18__n 1 1 0 0 .names A_8_.BLIF a_8__n 1 1 0 0 -.names A_24_.BLIF a_c_24__n +.names A_19_.BLIF a_c_19__n 1 1 0 0 .names A_7_.BLIF a_7__n 1 1 0 0 -.names A_25_.BLIF a_c_25__n +.names A_20_.BLIF a_c_20__n 1 1 0 0 .names A_6_.BLIF a_6__n 1 1 0 0 -.names A_26_.BLIF a_c_26__n +.names A_21_.BLIF a_c_21__n 1 1 0 0 .names A_5_.BLIF a_5__n 1 1 0 0 -.names A_27_.BLIF a_c_27__n +.names A_22_.BLIF a_c_22__n 1 1 0 0 .names A_4_.BLIF a_4__n 1 1 0 0 -.names A_28_.BLIF a_c_28__n +.names A_23_.BLIF a_c_23__n 1 1 0 0 .names A_3_.BLIF a_3__n 1 1 0 0 -.names A_29_.BLIF a_c_29__n +.names A_24_.BLIF a_c_24__n 1 1 0 0 .names A_2_.BLIF a_2__n 1 1 0 0 -.names A_30_.BLIF a_c_30__n +.names A_25_.BLIF a_c_25__n 1 1 0 0 .names A_1_.BLIF a_1__n 1 1 0 0 +.names A_26_.BLIF a_c_26__n +1 1 +0 0 +.names A_27_.BLIF a_c_27__n +1 1 +0 0 +.names A_28_.BLIF a_c_28__n +1 1 +0 0 +.names A_29_.BLIF a_c_29__n +1 1 +0 0 +.names A_30_.BLIF a_c_30__n +1 1 +0 0 .names A_31_.BLIF a_c_31__n 1 1 0 0 @@ -1370,6 +1380,12 @@ as_030_000_sync_0_un0_n .names BG_030.BLIF BG_030_c 1 1 0 0 +.names BGACK_000.BLIF BGACK_000_c +1 1 +0 0 +.names CLK_030.BLIF CLK_030_c +1 1 +0 0 .names nEXP_SPACE_c.BLIF DSACK_1_.OE 1 1 0 0 @@ -1394,20 +1410,15 @@ as_030_000_sync_0_un0_n .names FPU_CS_INT_i.BLIF AVEC_EXP.OE 1 1 0 0 -.names N_188.BLIF CIIN.OE +.names N_238.BLIF CIIN.OE 1 1 0 0 -.names inst_CLK_OUT_PRE.BLIF clk_clk_cnt_n.BLIF CLK_OUT_PRE_0 +.names CLK_CNT_N_0_.BLIF CLK_CNT_N_1_.BLIF G_102 01 1 10 1 11 0 00 0 -.names CLK_REF_1_.BLIF CLK_CNT_1_.BLIF G_92 -01 1 -10 1 -11 0 -00 0 -.names CLK_CNT_0_.BLIF CLK_CNT_1_.BLIF G_96 +.names CLK_CNT_P_0_.BLIF CLK_CNT_P_1_.BLIF G_108 01 1 10 1 11 0 diff --git a/Logic/BUS68030.cmd b/Logic/BUS68030.cmd deleted file mode 100644 index e7c37a0..0000000 --- a/Logic/BUS68030.cmd +++ /dev/null @@ -1,8 +0,0 @@ -STYFILENAME: 68030_tk.sty -PROJECT: BUS68030 -WORKING_PATH: "c:/users/matze/documents/github/68030tk/logic" -MODULE: BUS68030 -VHDL_FILE_LIST: 68030-68000-bus.vhd -OUTPUT_FILE_NAME: BUS68030 -SUFFIX_NAME: edi -PART: M4A5-128/64-10VC diff --git a/Logic/BUS68030.edi b/Logic/BUS68030.edi index 6f58570..07eda7c 100644 --- a/Logic/BUS68030.edi +++ b/Logic/BUS68030.edi @@ -4,7 +4,7 @@ (keywordMap (keywordLevel 0)) (status (written - (timeStamp 2014 5 24 11 44 4) + (timeStamp 2014 5 24 15 48 45) (author "Synopsys, Inc.") (program "Synplify Pro" (version "G-2012.09LC-SP1 , mapper maplat, Build 621R")) ) @@ -69,16 +69,6 @@ ) ) ) - (cell DLATRH (cellType GENERIC) - (view prim (viewType NETLIST) - (interface - (port Q (direction OUTPUT)) - (port D (direction INPUT)) - (port LAT (direction INPUT)) - (port R (direction INPUT)) - ) - ) - ) (cell IBUF (cellType GENERIC) (view prim (viewType NETLIST) (interface @@ -166,6 +156,30 @@ (port CIIN (direction OUTPUT)) ) (contents + (instance (rename cpu_est_2 "cpu_est[2]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename cpu_est_3 "cpu_est[3]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename cpu_est_0 "cpu_est[0]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename cpu_est_1 "cpu_est[1]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename SM_AMIGA_3 "SM_AMIGA[3]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename SM_AMIGA_2 "SM_AMIGA[2]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename SM_AMIGA_1 "SM_AMIGA[1]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename SM_AMIGA_0 "SM_AMIGA[0]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename CLK_CNT_N_0 "CLK_CNT_N[0]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename CLK_CNT_N_1 "CLK_CNT_N[1]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename CLK_CNT_P_0 "CLK_CNT_P[0]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename CLK_CNT_P_1 "CLK_CNT_P[1]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) (instance (rename IPL_030DFFSH_0 "IPL_030DFFSH[0]") (viewRef prim (cellRef DFFSH (libraryRef mach))) ) (instance (rename IPL_030DFFSH_1 "IPL_030DFFSH[1]") (viewRef prim (cellRef DFFSH (libraryRef mach))) @@ -180,40 +194,22 @@ ) (instance (rename SM_AMIGA_4 "SM_AMIGA[4]") (viewRef prim (cellRef DFFRH (libraryRef mach))) ) - (instance (rename SM_AMIGA_3 "SM_AMIGA[3]") (viewRef prim (cellRef DFFRH (libraryRef mach))) - ) - (instance (rename SM_AMIGA_2 "SM_AMIGA[2]") (viewRef prim (cellRef DFFRH (libraryRef mach))) - ) - (instance (rename SM_AMIGA_1 "SM_AMIGA[1]") (viewRef prim (cellRef DFFRH (libraryRef mach))) - ) - (instance (rename SM_AMIGA_0 "SM_AMIGA[0]") (viewRef prim (cellRef DFFRH (libraryRef mach))) - ) - (instance (rename CLK_CNT_0 "CLK_CNT[0]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename CLK_CNT_1 "CLK_CNT[1]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename cpu_est_0 "cpu_est[0]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename cpu_est_1 "cpu_est[1]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename cpu_est_2 "cpu_est[2]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename cpu_est_3 "cpu_est[3]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) (instance UDS_000_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) ) (instance LDS_000_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) ) + (instance VPA_SYNC (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) (instance VMA_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) ) - (instance BG_000DFFSH (viewRef prim (cellRef DFFSH (libraryRef mach))) - ) - (instance CLK_OUT_PRE (viewRef prim (cellRef DFF (libraryRef mach))) - ) (instance BGACK_030_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) ) (instance AS_000_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) ) + (instance CLK_OUT_PRE (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance CLK_OUT_INT (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) (instance AS_030_000_SYNC (viewRef prim (cellRef DFFSH (libraryRef mach))) ) (instance DTACK_SYNC (viewRef prim (cellRef DFFSH (libraryRef mach))) @@ -222,29 +218,27 @@ ) (instance (rename DSACK_INT_1 "DSACK_INT[1]") (viewRef prim (cellRef DFFSH (libraryRef mach))) ) - (instance VPA_SYNC (viewRef prim (cellRef DFFSH (libraryRef mach))) - ) (instance AMIGA_BUS_ENABLEDFF (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance CLK_000_D5 (viewRef prim (cellRef DFF (libraryRef mach))) - ) (instance DTACK_DMA (viewRef prim (cellRef DFFSH (libraryRef mach))) ) - (instance CLK_OUT_INT (viewRef prim (cellRef DFF (libraryRef mach))) + (instance CLK_000_D5 (viewRef prim (cellRef DFFSH (libraryRef mach))) ) - (instance CLK_000_D4 (viewRef prim (cellRef DFF (libraryRef mach))) + (instance BG_000DFFSH (viewRef prim (cellRef DFFSH (libraryRef mach))) ) - (instance CLK_000_D2 (viewRef prim (cellRef DFF (libraryRef mach))) + (instance CLK_000_D4 (viewRef prim (cellRef DFFSH (libraryRef mach))) ) - (instance CLK_000_D3 (viewRef prim (cellRef DFF (libraryRef mach))) + (instance CLK_000_D2 (viewRef prim (cellRef DFFSH (libraryRef mach))) ) - (instance VPA_D (viewRef prim (cellRef DFF (libraryRef mach))) + (instance CLK_000_D3 (viewRef prim (cellRef DFFSH (libraryRef mach))) ) - (instance CLK_000_D0 (viewRef prim (cellRef DFF (libraryRef mach))) + (instance VPA_D (viewRef prim (cellRef DFFSH (libraryRef mach))) ) - (instance RESETDFF (viewRef prim (cellRef DFF (libraryRef mach))) + (instance CLK_000_D0 (viewRef prim (cellRef DFFSH (libraryRef mach))) ) - (instance CLK_000_D1 (viewRef prim (cellRef DFF (libraryRef mach))) + (instance RESETDFFRH (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance CLK_000_D1 (viewRef prim (cellRef DFFSH (libraryRef mach))) ) (instance AS_030 (viewRef prim (cellRef IBUF (libraryRef mach))) ) (instance AS_000 (viewRef prim (cellRef BUFTH (libraryRef mach))) ) @@ -305,56 +299,36 @@ (instance AMIGA_BUS_DATA_DIR (viewRef prim (cellRef OBUF (libraryRef mach))) ) (instance AMIGA_BUS_ENABLE_LOW (viewRef prim (cellRef OBUF (libraryRef mach))) ) (instance CIIN (viewRef prim (cellRef BUFTH (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_0_1_3 "clk.cpu_est_11_0_0_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_0_3 "clk.cpu_est_11_0_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_0_a3_1_1_3 "clk.cpu_est_11_0_0_a3_1_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_0_a3_1_3 "clk.cpu_est_11_0_0_a3_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_AMIGA_BUS_ENABLE_3_f0_i_a3_1 "state_machine.AMIGA_BUS_ENABLE_3_f0_i_a3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_AMIGA_BUS_ENABLE_3_f0_i_a3 "state_machine.AMIGA_BUS_ENABLE_3_f0_i_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_i_0_a3_0_1_2 "clk.cpu_est_11_i_0_a3_0_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_i_0_a3_0_2 "clk.cpu_est_11_i_0_a3_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_i_0_a3_1_2 "clk.cpu_est_11_i_0_a3_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_i_0_a3_2 "clk.cpu_est_11_i_0_a3[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_0_a3_0_1_5 "SM_AMIGA_ns_0_a3_0_1[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_0_a3_0_5 "SM_AMIGA_ns_0_a3_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_LDS_000_INT_5_0_a3_1 "state_machine.LDS_000_INT_5_0_a3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_LDS_000_INT_5_0_a3 "state_machine.LDS_000_INT_5_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DTACK_SYNC_1_sqmuxa_1_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_SYNC_1_sqmuxa_1_i_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_SYNC_1_sqmuxa_1_i_a3_2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_SYNC_1_sqmuxa_1_i_a3_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_SYNC_1_sqmuxa_1_i_a3_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_SYNC_1_sqmuxa_1_i_a3_5 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance VPA_SYNC_1_sqmuxa_1_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un15_clk_000_d0_0_a3_0_1 "state_machine.un15_clk_000_d0_0_a3_0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un15_clk_000_d0_0_a3_0_2 "state_machine.un15_clk_000_d0_0_a3_0_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un15_clk_000_d0_0_a3_0 "state_machine.un15_clk_000_d0_0_a3_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un15_clk_000_d0_0_a3_1 "state_machine.un15_clk_000_d0_0_a3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un15_clk_000_d0_0_a3_2 "state_machine.un15_clk_000_d0_0_a3_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un15_clk_000_d0_0_a3 "state_machine.un15_clk_000_d0_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_ns_0_1_0 "SM_AMIGA_ns_0_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_ns_0_0 "SM_AMIGA_ns_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_000_SYNC_1_sqmuxa_i_o2_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_000_SYNC_1_sqmuxa_i_o2_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_000_SYNC_1_sqmuxa_i_o2_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_000_SYNC_1_sqmuxa_i_o2_5 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_000_SYNC_1_sqmuxa_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_0_1_1 "clk.cpu_est_11_0_0_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_0_2_1 "clk.cpu_est_11_0_0_2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_0_1 "clk.cpu_est_11_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_bg_030_i_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_bg_030_i_a3_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_bg_030_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_0_1_2 "cpu_est_ns_0_0_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_0_2 "cpu_est_ns_0_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_AMIGA_BUS_ENABLE_3_f0_i_a3_1 "state_machine.AMIGA_BUS_ENABLE_3_f0_i_a3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_AMIGA_BUS_ENABLE_3_f0_i_a3 "state_machine.AMIGA_BUS_ENABLE_3_f0_i_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_a3_0_1_7 "SM_AMIGA_ns_0_a3_0_1[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_a3_0_7 "SM_AMIGA_ns_0_a3_0[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_LDS_000_INT_5_0_a3_1 "state_machine.LDS_000_INT_5_0_a3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_LDS_000_INT_5_0_a3 "state_machine.LDS_000_INT_5_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un15_clk_000_d0_0_a3_0_1 "state_machine.un15_clk_000_d0_0_a3_0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un15_clk_000_d0_0_a3_0 "state_machine.un15_clk_000_d0_0_a3_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un15_clk_000_d0_0_a3_1 "state_machine.un15_clk_000_d0_0_a3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un15_clk_000_d0_0_a3 "state_machine.un15_clk_000_d0_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_0_2_1 "cpu_est_ns_0_0_2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_0_1 "cpu_est_ns_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un10_bg_030_0_a3_1 "state_machine.un10_bg_030_0_a3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un10_bg_030_0_a3_2 "state_machine.un10_bg_030_0_a3_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un10_bg_030_0_a3_3 "state_machine.un10_bg_030_0_a3_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un10_bg_030_0_a3 "state_machine.un10_bg_030_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance AS_030_000_SYNC_1_sqmuxa_i_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance AS_030_000_SYNC_1_sqmuxa_i_a3_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance AS_030_000_SYNC_1_sqmuxa_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance DTACK_SYNC_1_sqmuxa_1_i_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un6_bgack_000_0_i "state_machine.un6_bgack_000_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un23_clk_000_d0_i_0 "state_machine.un23_clk_000_d0_i_0") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un8_ciin_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un8_ciin_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un8_ciin_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un8_ciin_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DTACK_SYNC_1_sqmuxa_1_i_a3_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DTACK_SYNC_1_sqmuxa_1_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VPA_SYNC_1_sqmuxa_1_i_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VPA_SYNC_1_sqmuxa_1_i_a3_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VPA_SYNC_1_sqmuxa_1_i_a3_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un8_ciin_5 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un8_ciin_6 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un8_ciin (viewRef prim (cellRef AND2 (libraryRef mach))) ) @@ -364,100 +338,108 @@ (instance (rename state_machine_un8_clk_000_d2_1 "state_machine.un8_clk_000_d2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename state_machine_un8_clk_000_d2 "state_machine.un8_clk_000_d2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance AS_030_000_SYNC_1_sqmuxa_i_o2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance N_86_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_83_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_81_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_LDS_000_INT_5_0_i "state_machine.LDS_000_INT_5_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_UDS_000_INT_5_0_i "state_machine.UDS_000_INT_5_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_79_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_030_000_SYNC_1_sqmuxa_i_o2_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_000_SYNC_1_sqmuxa_i_o2_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_000_SYNC_1_sqmuxa_i_o2_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_000_SYNC_1_sqmuxa_i_o2_5 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_000_SYNC_1_sqmuxa_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_0_1_1 "cpu_est_ns_0_0_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance AS_030_000_SYNC_1_sqmuxa_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance DTACK_SYNC_1_sqmuxa_1_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_76_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_71_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance un1_as_030_000_sync8_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance VPA_SYNC_1_sqmuxa_1_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_72_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_73_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_68_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_69_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename state_machine_un15_clk_000_d0_0_i "state_machine.un15_clk_000_d0_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance un1_as_030_3_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_119_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_117_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_118_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_115_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_116_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un6_bgack_000_0_i "state_machine.un6_bgack_000_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un23_clk_000_d0_i "state_machine.un23_clk_000_d0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un8_ciin_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un8_ciin_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un8_ciin_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un8_ciin_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_ns_0_i_7 "SM_AMIGA_ns_0_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_98_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_114_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_i_i_6 "SM_AMIGA_ns_i_i_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_93_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_94_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_97_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_0_i_5 "SM_AMIGA_ns_0_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_89_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_90_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_88_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance CLK_000_D1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename clk_un4_clk_000_d1_0_o2_i "clk.un4_clk_000_d1_0_o2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_i_0_o2_i_2 "clk.cpu_est_11_i_0_o2_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DSACK_INT_1_sqmuxa_i_o3_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_141_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_142_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_0_0_i_0 "cpu_est_0_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_85_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_139_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_140_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_86_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_i_5 "SM_AMIGA_ns_0_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_84_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_130_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_82_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_81_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_77_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_75_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_LDS_000_INT_5_0_i "state_machine.LDS_000_INT_5_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_UDS_000_INT_5_0_i "state_machine.UDS_000_INT_5_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_73_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_123_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance cpu_estse_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_79_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_226_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_227_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename SM_AMIGA_ns_0_i_0 "SM_AMIGA_ns_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_125_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_138_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_178_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_0_i_3 "clk.cpu_est_11_0_0_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_121_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_122_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_222_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_223_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_225_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_0_i_2 "cpu_est_ns_0_0_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_221_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_127_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_220_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_214_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_215_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename SM_AMIGA_ns_i_0_o2_i_4 "SM_AMIGA_ns_i_0_o2_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename SM_AMIGA_ns_i_0_o2_i_1 "SM_AMIGA_ns_i_0_o2_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_145_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_129_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0_o3_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance DS_030_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename state_machine_UDS_000_INT_5_0_o3_i "state_machine.UDS_000_INT_5_0_o3_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_0_o2_i_3 "clk.cpu_est_11_0_0_o2_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un6_clk_000_d4_i "state_machine.un6_clk_000_d4_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_i_o2_i_6 "SM_AMIGA_ns_i_i_o2_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_0_o2_i_1 "clk.cpu_est_11_0_0_o2_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_0_o2_i_7 "SM_AMIGA_ns_0_o2_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_ns_i_0_o2_i_3 "cpu_est_ns_i_0_o2_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_DSACK_INT_0_sqmuxa_i_o2_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename state_machine_AMIGA_BUS_ENABLE_3_f0_i_o2_i "state_machine.AMIGA_BUS_ENABLE_3_f0_i_o2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance AS_030_000_SYNC_1_sqmuxa_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_0_i_1 "clk.cpu_est_11_0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_124_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_146_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_0_o2_4 "SM_AMIGA_ns_i_0_o2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance BG_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance nEXP_SPACE_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_114 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_i_1 "cpu_est_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance VPA_SYNC_1_sqmuxa_1_i_a3_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VMA_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_i_0 "cpu_est_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_i_3 "cpu_est_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DSACK_INT_1_sqmuxa_i_o3_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_000_D1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename clk_un3_clk_000_d1_0_o2_i "clk.un3_clk_000_d1_0_o2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_88_i_0_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_122_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_0_i_1 "cpu_est_ns_0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_126_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_128_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_216_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_217_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0_o3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_0_o2_1 "SM_AMIGA_ns_i_0_o2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance CLK_000_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_0_o2_4 "SM_AMIGA_ns_i_0_o2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance nEXP_SPACE_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance BG_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_127 (viewRef prim (cellRef INV (libraryRef mach))) ) (instance VPA_D_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance VMA_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance RW_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_AMIGA_BUS_ENABLE_3_f0_i "state_machine.AMIGA_BUS_ENABLE_3_f0_i") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance cpu_estse_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename state_machine_UDS_000_INT_5_0_m2_r "state_machine.UDS_000_INT_5_0_m2.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename state_machine_UDS_000_INT_5_0_m2_m "state_machine.UDS_000_INT_5_0_m2.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename state_machine_UDS_000_INT_5_0_m2_n "state_machine.UDS_000_INT_5_0_m2.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename state_machine_UDS_000_INT_5_0_m2_p "state_machine.UDS_000_INT_5_0_m2.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance AS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_88_i_0_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_un3_clk_000_d1_0_o2 "clk.un3_clk_000_d1_0_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance DSACK_INT_1_sqmuxa_i_o3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_i_2 "cpu_est_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_i_0_o2_2 "clk.cpu_est_11_i_0_o2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_un4_clk_000_d1_0_o2 "clk.un4_clk_000_d1_0_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename state_machine_AMIGA_BUS_ENABLE_3_f0_i_o2 "state_machine.AMIGA_BUS_ENABLE_3_f0_i_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_0_o2_7 "SM_AMIGA_ns_0_o2[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_0_o2_1 "clk.cpu_est_11_0_0_o2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_i_o2_6 "SM_AMIGA_ns_i_i_o2[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_0_o2_3 "clk.cpu_est_11_0_0_o2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un6_clk_000_d4_i "state_machine.un6_clk_000_d4_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_DSACK_INT_0_sqmuxa_i_o2_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_i_3 "cpu_est_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_ns_i_0_o2_3 "cpu_est_ns_i_0_o2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename state_machine_UDS_000_INT_5_0_o3 "state_machine.UDS_000_INT_5_0_o3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0_o3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_0_o2_1 "SM_AMIGA_ns_i_0_o2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un15_clk_000_d0_0 "state_machine.un15_clk_000_d0_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VPA_SYNC_1_sqmuxa_1_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un1_as_030_000_sync8_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance DTACK_SYNC_1_sqmuxa_1_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance AS_030_000_SYNC_1_sqmuxa_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) @@ -468,56 +450,55 @@ (instance (rename SM_AMIGA_ns_i_0_3 "SM_AMIGA_ns_i_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_ns_i_0_4 "SM_AMIGA_ns_i_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_ns_0_5 "SM_AMIGA_ns_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_i_6 "SM_AMIGA_ns_i_i[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_0_6 "SM_AMIGA_ns_i_0[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_ns_0_7 "SM_AMIGA_ns_0[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_i_0_2 "clk.cpu_est_11_i_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_AMIGA_BUS_ENABLE_3_f0_i "state_machine.AMIGA_BUS_ENABLE_3_f0_i") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_0_0 "cpu_est_0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_0_a3_1 "clk.cpu_est_11_0_0_a3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_0_a3_0_1 "clk.cpu_est_11_0_0_a3_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_0_a3_1_1 "clk.cpu_est_11_0_0_a3_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_0_a3_3 "clk.cpu_est_11_0_0_a3[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_0_a3_0_3 "clk.cpu_est_11_0_0_a3_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_i_0_3 "cpu_est_ns_i_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_0_a3_0_2 "cpu_est_ns_0_0_a3_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_0_a3_1_2 "cpu_est_ns_0_0_a3_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_ns_0_a3_0 "SM_AMIGA_ns_0_a3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_ns_0_a3_0_0 "SM_AMIGA_ns_0_a3_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_0_a3_0 "cpu_est_0_0_a3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_0_a3_0_0 "cpu_est_0_0_a3_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance cpu_estse_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance cpu_estse_0_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_i_0 "cpu_est_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_0_a2_1 "cpu_est_ns_0_0_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_i_0_a2_3 "cpu_est_ns_i_0_a2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_i_1 "cpu_est_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_0_a2_0_1 "cpu_est_ns_0_0_a2_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_ns_0_a2_0 "SM_AMIGA_ns_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_0_a2_1 "clk.cpu_est_11_0_0_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_0_a2_4 "SM_AMIGA_ns_i_0_a2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename state_machine_un6_bgack_000_0 "state_machine.un6_bgack_000_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un1_as_030_3_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un15_clk_000_d0_0 "state_machine.un15_clk_000_d0_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_SYNC_1_sqmuxa_1_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un8_clk_000_d2_i "state_machine.un8_clk_000_d2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_0_a3_0_1 "SM_AMIGA_ns_i_0_a3_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_0_a3_2 "SM_AMIGA_ns_i_0_a3[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_0_a3_3 "SM_AMIGA_ns_i_0_a3[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename SM_AMIGA_ns_i_0_a3_4 "SM_AMIGA_ns_i_0_a3[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_0_a3_0_4 "SM_AMIGA_ns_i_0_a3_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_ns_0_a3_5 "SM_AMIGA_ns_0_a3[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_i_a3_6 "SM_AMIGA_ns_i_i_a3[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_i_a3_0_6 "SM_AMIGA_ns_i_i_a3_0[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_a3_0_5 "SM_AMIGA_ns_0_a3_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_0_a3_6 "SM_AMIGA_ns_i_0_a3[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_0_a3_0_6 "SM_AMIGA_ns_i_0_a3_0[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_ns_0_a3_7 "SM_AMIGA_ns_0_a3[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_0_a3_0_7 "SM_AMIGA_ns_0_a3_0[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_0_a3_1 "cpu_est_ns_0_0_a3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_i_2 "cpu_est_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_0_a3_0_1 "cpu_est_ns_0_0_a3_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_i_0_a3_3 "cpu_est_ns_i_0_a3[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance AMIGA_BUS_ENABLE_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance AS_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename clk_clk_cnt_i "clk.clk_cnt_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename clk_CLK_CNT_3_1 "clk.CLK_CNT_3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_OUT_PRE_0 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance G_96 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance G_92 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance (rename state_machine_un1_clk_030_i_a3 "state_machine.un1_clk_030_i_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_0_a3_2 "cpu_est_ns_0_0_a3[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance G_102 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance G_108 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) (instance AS_000_INT_1_sqmuxa_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance I_115 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_128 (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename state_machine_un7_as_000_int_0_a3 "state_machine.un7_as_000_int_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_DSACK_INT_0_sqmuxa_i_o2_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un1_as_030_000_sync8_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename A_i_0 "A_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename SIZE_i_1 "SIZE_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename SM_AMIGA_ns_i_0_a3_1 "SM_AMIGA_ns_i_0_a3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un8_clk_000_d2_i "state_machine.un8_clk_000_d2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_0_a3_0_1 "SM_AMIGA_ns_i_0_a3_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_0_a3_2 "SM_AMIGA_ns_i_0_a3[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_0_a3_3 "SM_AMIGA_ns_i_0_a3[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename A_i_16 "A_i[16]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename A_i_18 "A_i[18]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename A_i_19 "A_i[19]") (viewRef prim (cellRef INV (libraryRef mach))) ) @@ -531,37 +512,24 @@ (instance (rename A_i_31 "A_i[31]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance AS_030_000_SYNC_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance CLK_000_D2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename CLK_CNT_i_0 "CLK_CNT_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename clk_CLK_CNT_3_0 "clk.CLK_CNT_3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename state_machine_un7_as_000_int_i "state_machine.un7_as_000_int_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RST_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_137_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance G_93 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename VPA_SYNC_0_r "VPA_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename VPA_SYNC_0_m "VPA_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename VPA_SYNC_0_n "VPA_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename VPA_SYNC_0_p "VPA_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_0_r "AMIGA_BUS_ENABLE_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_0_m "AMIGA_BUS_ENABLE_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_0_n "AMIGA_BUS_ENABLE_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_0_p "AMIGA_BUS_ENABLE_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename UDS_000_INT_0_r "UDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename UDS_000_INT_0_m "UDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename UDS_000_INT_0_n "UDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename UDS_000_INT_0_p "UDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename state_machine_un10_bg_030_i "state_machine.un10_bg_030_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename un4_clk_cnt_n_i_1 "un4_clk_cnt_n_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_OSZI_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename un2_clk_cnt_p_i_1 "un2_clk_cnt_p_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename LDS_000_INT_0_r "LDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename LDS_000_INT_0_m "LDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename LDS_000_INT_0_n "LDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename LDS_000_INT_0_p "LDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance N_70_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename VPA_SYNC_0_r "VPA_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename VPA_SYNC_0_m "VPA_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename VPA_SYNC_0_n "VPA_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename VPA_SYNC_0_p "VPA_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (instance (rename VMA_INT_0_r "VMA_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename VMA_INT_0_m "VMA_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename VMA_INT_0_n "VMA_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename VMA_INT_0_p "VMA_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance N_120_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename BG_000_0_r "BG_000_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename BG_000_0_m "BG_000_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename BG_000_0_n "BG_000_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename BG_000_0_p "BG_000_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (instance (rename BGACK_030_INT_0_r "BGACK_030_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename BGACK_030_INT_0_m "BGACK_030_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename BGACK_030_INT_0_n "BGACK_030_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) @@ -570,18 +538,6 @@ (instance (rename AS_000_INT_0_m "AS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename AS_000_INT_0_n "AS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename AS_000_INT_0_p "AS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename cpu_est_0_1__r "cpu_est_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_0_1__m "cpu_est_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_1__n "cpu_est_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_1__p "cpu_est_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename cpu_est_0_2__r "cpu_est_0_2_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_0_2__m "cpu_est_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_2__n "cpu_est_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_2__p "cpu_est_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename cpu_est_0_3__r "cpu_est_0_3_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_0_3__m "cpu_est_0_3_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_3__n "cpu_est_0_3_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_3__p "cpu_est_0_3_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (instance (rename IPL_030_0_0__r "IPL_030_0_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename IPL_030_0_0__m "IPL_030_0_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename IPL_030_0_0__n "IPL_030_0_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) @@ -594,17 +550,29 @@ (instance (rename IPL_030_0_2__m "IPL_030_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename IPL_030_0_2__n "IPL_030_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename IPL_030_0_2__p "IPL_030_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename CLK_REF_1 "CLK_REF[1]") (viewRef prim (cellRef DLATRH (libraryRef mach))) ) + (instance (rename cpu_estse_0_r "cpu_estse_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_estse_0_m "cpu_estse_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_estse_0_n "cpu_estse_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_estse_0_p "cpu_estse_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename cpu_estse_1_r "cpu_estse_1.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_estse_1_m "cpu_estse_1.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_estse_1_n "cpu_estse_1.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_estse_1_p "cpu_estse_1.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename cpu_estse_2_r "cpu_estse_2.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_estse_2_m "cpu_estse_2.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_estse_2_n "cpu_estse_2.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_estse_2_p "cpu_estse_2.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (instance (rename state_machine_un23_clk_000_d0 "state_machine.un23_clk_000_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance CLK_000_D5_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename state_machine_un6_clk_000_d4 "state_machine.un6_clk_000_d4") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance BGACK_030_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance FPU_CS_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename clk_un12_clk_cnt_p "clk.un12_clk_cnt_p") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename AS_030_000_SYNC_0_r "AS_030_000_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename AS_030_000_SYNC_0_m "AS_030_000_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename AS_030_000_SYNC_0_n "AS_030_000_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename AS_030_000_SYNC_0_p "AS_030_000_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance N_77_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_72_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename DTACK_SYNC_0_r "DTACK_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename DTACK_SYNC_0_m "DTACK_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename DTACK_SYNC_0_n "DTACK_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) @@ -613,12 +581,18 @@ (instance (rename FPU_CS_INT_0_m "FPU_CS_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename FPU_CS_INT_0_n "FPU_CS_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename FPU_CS_INT_0_p "FPU_CS_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance N_74_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename DSACK_INT_0_1__r "DSACK_INT_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename DSACK_INT_0_1__m "DSACK_INT_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename DSACK_INT_0_1__n "DSACK_INT_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename DSACK_INT_0_1__p "DSACK_INT_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance N_75_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_0_r "AMIGA_BUS_ENABLE_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_0_m "AMIGA_BUS_ENABLE_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_0_n "AMIGA_BUS_ENABLE_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_0_p "AMIGA_BUS_ENABLE_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_r "UDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_m "UDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_n "UDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_p "UDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (net BGACK_030_INT (joined (portRef Q (instanceRef BGACK_030_INT)) (portRef I0 (instanceRef BGACK_030_INT_i)) @@ -634,42 +608,16 @@ (portRef I0 (instanceRef FPU_CS_INT_i)) (portRef I0 (instanceRef FPU_CS)) )) - (net (rename cpu_est_3 "cpu_est[3]") (joined - (portRef Q (instanceRef cpu_est_3)) - (portRef I0 (instanceRef cpu_est_0_3__m)) - (portRef I1 (instanceRef clk_cpu_est_11_0_0_a3_3)) - (portRef I1 (instanceRef clk_cpu_est_11_0_0_a3_1_1)) - (portRef I0 (instanceRef cpu_est_i_3)) - (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_3)) - (portRef I0 (instanceRef E)) - )) (net VMA_INT (joined (portRef Q (instanceRef VMA_INT)) (portRef I0 (instanceRef VMA_INT_0_n)) (portRef I0 (instanceRef VMA_INT_i)) (portRef I0 (instanceRef VMA)) )) - (net (rename cpu_est_0 "cpu_est[0]") (joined - (portRef Q (instanceRef cpu_est_0)) - (portRef I1 (instanceRef clk_cpu_est_11_0_0_a2_1)) - (portRef I1 (instanceRef cpu_est_0_0_a3_0)) - (portRef I0 (instanceRef clk_cpu_est_11_0_0_o2_3)) - (portRef I0 (instanceRef cpu_est_i_0)) - (portRef I1 (instanceRef clk_cpu_est_11_i_0_a3_1_2)) - )) - (net (rename cpu_est_1 "cpu_est[1]") (joined - (portRef Q (instanceRef cpu_est_1)) - (portRef I0 (instanceRef cpu_est_0_1__m)) - (portRef I0 (instanceRef VMA_INT_0_m)) - (portRef I1 (instanceRef clk_cpu_est_11_0_0_o2_3)) - (portRef I0 (instanceRef clk_cpu_est_11_i_0_o2_2)) - (portRef I0 (instanceRef cpu_est_i_1)) - (portRef I0 (instanceRef clk_cpu_est_11_i_0_a3_0_1_2)) - )) (net AS_000_INT (joined (portRef Q (instanceRef AS_000_INT)) (portRef I0 (instanceRef AS_000_INT_0_m)) - (portRef I0 (instanceRef SM_AMIGA_ns_0_o2_7)) + (portRef I0 (instanceRef N_88_i_0_o2)) (portRef I0 (instanceRef AS_000_INT_i)) (portRef I0 (instanceRef AS_000)) )) @@ -686,7 +634,7 @@ (net VPA_D (joined (portRef Q (instanceRef VPA_D)) (portRef I0 (instanceRef VPA_D_i)) - (portRef I1 (instanceRef DTACK_SYNC_1_sqmuxa_1_i_a3)) + (portRef I1 (instanceRef DTACK_SYNC_1_sqmuxa_1_i_a3_2)) )) (net VPA_SYNC (joined (portRef Q (instanceRef VPA_SYNC)) @@ -695,12 +643,13 @@ )) (net CLK_000_D0 (joined (portRef Q (instanceRef CLK_000_D0)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_i_a3_0_6)) (portRef I0 (instanceRef SM_AMIGA_ns_i_0_2)) - (portRef I1 (instanceRef SM_AMIGA_ns_0_o2_7)) - (portRef I0 (instanceRef clk_un4_clk_000_d1_0_o2)) + (portRef I0 (instanceRef clk_un3_clk_000_d1_0_o2)) + (portRef I1 (instanceRef N_88_i_0_o2)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_0_o2_4)) (portRef I0 (instanceRef CLK_000_D0_i)) - (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_2)) + (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_1)) + (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa_1_i_a3_1)) (portRef D (instanceRef CLK_000_D1)) )) (net CLK_000_D1 (joined @@ -717,10 +666,10 @@ (portRef Q (instanceRef CLK_000_D5)) (portRef I0 (instanceRef CLK_000_D5_i)) )) - (net CLK_OUT_PRE (joined - (portRef Q (instanceRef CLK_OUT_PRE)) - (portRef I0 (instanceRef CLK_OUT_PRE_0)) - (portRef D (instanceRef CLK_OUT_INT)) + (net (rename SM_AMIGA_5 "SM_AMIGA[5]") (joined + (portRef Q (instanceRef SM_AMIGA_5)) + (portRef I0 (instanceRef SM_AMIGA_i_5)) + (portRef I0 (instanceRef state_machine_UDS_000_INT_5_0_m2_m)) )) (net (rename SM_AMIGA_6 "SM_AMIGA[6]") (joined (portRef Q (instanceRef SM_AMIGA_6)) @@ -728,34 +677,16 @@ (portRef I0 (instanceRef state_machine_AMIGA_BUS_ENABLE_3_f0_i_o2)) (portRef I0 (instanceRef SM_AMIGA_i_6)) )) - (net (rename SM_AMIGA_5 "SM_AMIGA[5]") (joined - (portRef Q (instanceRef SM_AMIGA_5)) - (portRef I0 (instanceRef SM_AMIGA_i_5)) - (portRef I0 (instanceRef state_machine_UDS_000_INT_5_0_m2_m)) - )) (net VCC (joined (portRef I0 (instanceRef AMIGA_BUS_ENABLE_LOW)) (portRef I0 (instanceRef AVEC)) (portRef I0 (instanceRef DSACK_0)) + (portRef D (instanceRef RESETDFFRH)) )) (net GND (joined - (portRef LAT (instanceRef CLK_REF_1)) - (portRef D (instanceRef CLK_REF_1)) (portRef I0 (instanceRef AVEC_EXP)) (portRef I0 (instanceRef BERR)) )) - (net (rename cpu_est_2 "cpu_est[2]") (joined - (portRef Q (instanceRef cpu_est_2)) - (portRef I0 (instanceRef cpu_est_0_2__m)) - (portRef I1 (instanceRef clk_cpu_est_11_i_0_o2_2)) - (portRef I0 (instanceRef cpu_est_i_2)) - (portRef I1 (instanceRef state_machine_un15_clk_000_d0_0_a3_2)) - (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_2_0)) - )) - (net (rename CLK_REF_1 "CLK_REF[1]") (joined - (portRef Q (instanceRef CLK_REF_1)) - (portRef I1 (instanceRef G_92)) - )) (net UDS_000_INT (joined (portRef Q (instanceRef UDS_000_INT)) (portRef I0 (instanceRef UDS_000_INT_0_n)) @@ -771,13 +702,6 @@ (portRef I0 (instanceRef DSACK_INT_0_1__n)) (portRef I0 (instanceRef DSACK_1)) )) - (net (rename SM_AMIGA_7 "SM_AMIGA[7]") (joined - (portRef Q (instanceRef SM_AMIGA_7)) - (portRef I0 (instanceRef SM_AMIGA_i_7)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_0_a3_0_1)) - (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a3_2)) - (portRef I0 (instanceRef un1_bg_030_i_a3_2)) - )) (net AS_000_INT_1_sqmuxa (joined (portRef O (instanceRef AS_000_INT_1_sqmuxa_0_a3)) (portRef I1 (instanceRef AS_000_INT_0_m)) @@ -794,16 +718,17 @@ )) (net (rename SM_AMIGA_4 "SM_AMIGA[4]") (joined (portRef Q (instanceRef SM_AMIGA_4)) - (portRef I0 (instanceRef SM_AMIGA_i_4)) (portRef I0 (instanceRef state_machine_UDS_000_INT_5_0_m2_n)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_0_o2_4)) + (portRef I0 (instanceRef SM_AMIGA_i_4)) )) (net (rename state_machine_un23_clk_000_d0 "state_machine.un23_clk_000_d0") (joined - (portRef O (instanceRef state_machine_un23_clk_000_d0_i_0)) - (portRef I1 (instanceRef SM_AMIGA_ns_0_a3_0_5)) + (portRef O (instanceRef state_machine_un23_clk_000_d0_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_0_a2_4)) )) (net (rename state_machine_un6_clk_000_d4 "state_machine.un6_clk_000_d4") (joined (portRef O (instanceRef state_machine_un6_clk_000_d4)) - (portRef I1 (instanceRef un1_DSACK_INT_0_sqmuxa_i_o2_i_a3)) + (portRef I1 (instanceRef un1_DSACK_INT_0_sqmuxa_i_o2_i_o2)) (portRef I0 (instanceRef state_machine_un6_clk_000_d4_i)) )) (net CLK_000_D4 (joined @@ -815,42 +740,66 @@ (portRef Q (instanceRef DTACK_DMA)) (portRef I0 (instanceRef DTACK)) )) - (net (rename clk_clk_cnt "clk.clk_cnt") (joined - (portRef O (instanceRef G_93)) - (portRef I1 (instanceRef CLK_OUT_PRE_0)) - (portRef I0 (instanceRef clk_clk_cnt_i)) + (net (rename state_machine_un10_bg_030 "state_machine.un10_bg_030") (joined + (portRef O (instanceRef state_machine_un10_bg_030_0_a3)) + (portRef I0 (instanceRef state_machine_un10_bg_030_i)) )) - (net (rename CLK_CNT_0 "CLK_CNT[0]") (joined - (portRef Q (instanceRef CLK_CNT_0)) - (portRef I0 (instanceRef CLK_CNT_i_0)) - (portRef I0 (instanceRef G_96)) + (net (rename SM_AMIGA_7 "SM_AMIGA[7]") (joined + (portRef Q (instanceRef SM_AMIGA_7)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_0_a3_0_1)) + (portRef I0 (instanceRef SM_AMIGA_i_7)) + (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a3_2)) + (portRef I1 (instanceRef state_machine_un10_bg_030_0_a3)) )) - (net (rename CLK_CNT_1 "CLK_CNT[1]") (joined - (portRef Q (instanceRef CLK_CNT_1)) - (portRef I0 (instanceRef G_92)) - (portRef I1 (instanceRef G_96)) + (net (rename SM_AMIGA_3 "SM_AMIGA[3]") (joined + (portRef Q (instanceRef SM_AMIGA_3)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_a3_0_5)) + (portRef I0 (instanceRef SM_AMIGA_i_3)) + (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_2)) + (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa_1_i_a3_2)) )) (net (rename state_machine_un6_bgack_000 "state_machine.un6_bgack_000") (joined (portRef O (instanceRef state_machine_un6_bgack_000_0_i)) (portRef I1 (instanceRef BGACK_030_INT_0_m)) (portRef I0 (instanceRef BGACK_030_INT_0_r)) )) - (net (rename SM_AMIGA_3 "SM_AMIGA[3]") (joined - (portRef Q (instanceRef SM_AMIGA_3)) - (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_2)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_0_o2_4)) - (portRef I0 (instanceRef SM_AMIGA_i_3)) - (portRef I1 (instanceRef SM_AMIGA_ns_0_a3_0_1_5)) - )) (net (rename SM_AMIGA_1 "SM_AMIGA[1]") (joined (portRef Q (instanceRef SM_AMIGA_1)) - (portRef I0 (instanceRef un1_DSACK_INT_0_sqmuxa_i_o2_i_a3)) - (portRef I1 (instanceRef SM_AMIGA_ns_0_a3_0_7)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_i_a3_6)) + (portRef I0 (instanceRef un1_DSACK_INT_0_sqmuxa_i_o2_i_o2)) + (portRef I0 (instanceRef SM_AMIGA_i_1)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_a3_0_1_7)) + )) + (net (rename un4_clk_cnt_n_1 "un4_clk_cnt_n[1]") (joined + (portRef O (instanceRef G_102)) + (portRef I1 (instanceRef clk_un12_clk_cnt_p)) + (portRef I0 (instanceRef un4_clk_cnt_n_i_1)) + )) + (net (rename CLK_CNT_N_0 "CLK_CNT_N[0]") (joined + (portRef Q (instanceRef CLK_CNT_N_0)) + (portRef I0 (instanceRef G_102)) + (portRef D (instanceRef CLK_CNT_N_1)) + )) + (net (rename CLK_CNT_N_1 "CLK_CNT_N[1]") (joined + (portRef Q (instanceRef CLK_CNT_N_1)) + (portRef I1 (instanceRef G_102)) + )) + (net (rename un2_clk_cnt_p_1 "un2_clk_cnt_p[1]") (joined + (portRef O (instanceRef G_108)) + (portRef I0 (instanceRef clk_un12_clk_cnt_p)) + (portRef I0 (instanceRef un2_clk_cnt_p_i_1)) + )) + (net (rename CLK_CNT_P_0 "CLK_CNT_P[0]") (joined + (portRef Q (instanceRef CLK_CNT_P_0)) + (portRef I0 (instanceRef G_108)) + (portRef D (instanceRef CLK_CNT_P_1)) + )) + (net (rename CLK_CNT_P_1 "CLK_CNT_P[1]") (joined + (portRef Q (instanceRef CLK_CNT_P_1)) + (portRef I1 (instanceRef G_108)) )) (net (rename SM_AMIGA_2 "SM_AMIGA[2]") (joined (portRef Q (instanceRef SM_AMIGA_2)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_i_a3_0_6)) + (portRef I0 (instanceRef SM_AMIGA_i_2)) (portRef I1 (instanceRef SM_AMIGA_ns_0_a3_5)) )) (net (rename SM_AMIGA_0 "SM_AMIGA[0]") (joined @@ -867,14 +816,6 @@ (portRef I1 (instanceRef VMA_INT_0_m)) (portRef I0 (instanceRef VMA_INT_0_r)) )) - (net (rename clk_CLK_CNT_3_0 "clk.CLK_CNT_3[0]") (joined - (portRef O (instanceRef clk_CLK_CNT_3_0)) - (portRef D (instanceRef CLK_CNT_0)) - )) - (net (rename clk_CLK_CNT_3_1 "clk.CLK_CNT_3[1]") (joined - (portRef O (instanceRef clk_CLK_CNT_3_1)) - (portRef D (instanceRef CLK_CNT_1)) - )) (net (rename state_machine_LDS_000_INT_5 "state_machine.LDS_000_INT_5") (joined (portRef O (instanceRef state_machine_LDS_000_INT_5_0_i)) (portRef I0 (instanceRef LDS_000_INT_0_m)) @@ -887,6 +828,10 @@ (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0_o3_i)) (portRef I0 (instanceRef AS_030_000_SYNC_0_m)) )) + (net CLK_OUT_PRE (joined + (portRef Q (instanceRef CLK_OUT_PRE)) + (portRef D (instanceRef CLK_OUT_INT)) + )) (net N_1 (joined (portRef O (instanceRef AS_030_000_SYNC_0_p)) (portRef D (instanceRef AS_030_000_SYNC)) @@ -904,66 +849,42 @@ (portRef D (instanceRef DSACK_INT_1)) )) (net N_5 (joined - (portRef O (instanceRef VPA_SYNC_0_p)) - (portRef D (instanceRef VPA_SYNC)) - )) - (net N_6 (joined (portRef O (instanceRef AMIGA_BUS_ENABLE_0_p)) (portRef D (instanceRef AMIGA_BUS_ENABLEDFF)) )) - (net N_7 (joined + (net N_6 (joined (portRef O (instanceRef UDS_000_INT_0_p)) (portRef D (instanceRef UDS_000_INT)) )) - (net N_8 (joined + (net N_7 (joined (portRef O (instanceRef LDS_000_INT_0_p)) (portRef D (instanceRef LDS_000_INT)) )) + (net N_8 (joined + (portRef O (instanceRef VPA_SYNC_0_p)) + (portRef D (instanceRef VPA_SYNC)) + )) (net N_9 (joined (portRef O (instanceRef VMA_INT_0_p)) (portRef D (instanceRef VMA_INT)) )) (net N_10 (joined - (portRef O (instanceRef BG_000_0_p)) - (portRef D (instanceRef BG_000DFFSH)) - )) - (net N_11 (joined - (portRef O (instanceRef CLK_OUT_PRE_0)) - (portRef D (instanceRef CLK_OUT_PRE)) - )) - (net N_12 (joined (portRef O (instanceRef BGACK_030_INT_0_p)) (portRef D (instanceRef BGACK_030_INT)) )) - (net N_13 (joined + (net N_11 (joined (portRef O (instanceRef AS_000_INT_0_p)) (portRef D (instanceRef AS_000_INT)) )) - (net N_14 (joined - (portRef O (instanceRef cpu_est_0_0_i_0)) - (portRef D (instanceRef cpu_est_0)) - )) - (net N_15 (joined - (portRef O (instanceRef cpu_est_0_1__p)) - (portRef D (instanceRef cpu_est_1)) - )) - (net N_16 (joined - (portRef O (instanceRef cpu_est_0_2__p)) - (portRef D (instanceRef cpu_est_2)) - )) - (net N_17 (joined - (portRef O (instanceRef cpu_est_0_3__p)) - (portRef D (instanceRef cpu_est_3)) - )) - (net N_18 (joined + (net N_12 (joined (portRef O (instanceRef IPL_030_0_0__p)) (portRef D (instanceRef IPL_030DFFSH_0)) )) - (net N_19 (joined + (net N_13 (joined (portRef O (instanceRef IPL_030_0_1__p)) (portRef D (instanceRef IPL_030DFFSH_1)) )) - (net N_20 (joined + (net N_14 (joined (portRef O (instanceRef IPL_030_0_2__p)) (portRef D (instanceRef IPL_030DFFSH_2)) )) @@ -979,280 +900,295 @@ (portRef O (instanceRef SM_AMIGA_ns_0_i_7)) (portRef D (instanceRef SM_AMIGA_0)) )) - (net (rename clk_cpu_est_11_1 "clk.cpu_est_11[1]") (joined - (portRef O (instanceRef clk_cpu_est_11_0_0_i_1)) - (portRef I0 (instanceRef cpu_est_0_1__n)) + (net (rename cpu_est_0 "cpu_est[0]") (joined + (portRef Q (instanceRef cpu_est_0)) + (portRef I0 (instanceRef cpu_est_ns_0_0_a2_0_1)) + (portRef I0 (instanceRef cpu_est_i_0)) + (portRef I1 (instanceRef cpu_estse_0_a3)) + (portRef I0 (instanceRef cpu_est_ns_0_0_a3_1_2)) )) - (net (rename clk_cpu_est_11_3 "clk.cpu_est_11[3]") (joined - (portRef O (instanceRef clk_cpu_est_11_0_0_i_3)) - (portRef I0 (instanceRef cpu_est_0_3__n)) + (net (rename cpu_est_1 "cpu_est[1]") (joined + (portRef Q (instanceRef cpu_est_1)) + (portRef I0 (instanceRef cpu_estse_0_m)) + (portRef I0 (instanceRef cpu_est_ns_0_0_a3_2)) + (portRef I0 (instanceRef cpu_est_i_1)) + (portRef I0 (instanceRef cpu_est_ns_0_0_a2_1)) )) - (net N_137 (joined - (portRef O (instanceRef G_92)) - (portRef I0 (instanceRef N_137_i)) + (net (rename cpu_est_2 "cpu_est[2]") (joined + (portRef Q (instanceRef cpu_est_2)) + (portRef I0 (instanceRef cpu_estse_1_m)) + (portRef I1 (instanceRef cpu_est_ns_0_0_a3_2)) + (portRef I1 (instanceRef cpu_est_ns_i_0_a3_3)) + (portRef I0 (instanceRef cpu_est_i_2)) + (portRef I0 (instanceRef cpu_est_ns_0_0_a3_1)) + (portRef I1 (instanceRef state_machine_un15_clk_000_d0_0_a3_0)) )) - (net (rename un3_clk_cnt_1 "un3_clk_cnt[1]") (joined - (portRef O (instanceRef G_96)) - (portRef I1 (instanceRef clk_CLK_CNT_3_1)) + (net (rename cpu_est_3 "cpu_est[3]") (joined + (portRef Q (instanceRef cpu_est_3)) + (portRef I0 (instanceRef cpu_estse_2_m)) + (portRef I1 (instanceRef cpu_est_ns_0_0_a3_1)) + (portRef I1 (instanceRef cpu_est_ns_0_0_a3_1_2)) + (portRef I0 (instanceRef cpu_est_ns_i_0_o2_3)) + (portRef I0 (instanceRef cpu_est_i_3)) + (portRef I0 (instanceRef E)) )) - (net N_162 (joined + (net (rename cpu_est_ns_e_0 "cpu_est_ns_e[0]") (joined + (portRef O (instanceRef cpu_estse_0_0_i)) + (portRef D (instanceRef cpu_est_0)) + )) + (net (rename cpu_est_ns_e_1 "cpu_est_ns_e[1]") (joined + (portRef O (instanceRef cpu_estse_0_p)) + (portRef D (instanceRef cpu_est_1)) + )) + (net (rename cpu_est_ns_e_2 "cpu_est_ns_e[2]") (joined + (portRef O (instanceRef cpu_estse_1_p)) + (portRef D (instanceRef cpu_est_2)) + )) + (net (rename cpu_est_ns_e_3 "cpu_est_ns_e[3]") (joined + (portRef O (instanceRef cpu_estse_2_p)) + (portRef D (instanceRef cpu_est_3)) + )) + (net (rename cpu_est_ns_1 "cpu_est_ns[1]") (joined + (portRef O (instanceRef cpu_est_ns_0_0_i_1)) + (portRef I0 (instanceRef cpu_estse_0_n)) + )) + (net (rename cpu_est_ns_2 "cpu_est_ns[2]") (joined + (portRef O (instanceRef cpu_est_ns_0_0_i_2)) + (portRef I0 (instanceRef cpu_estse_1_n)) + )) + (net N_203 (joined (portRef O (instanceRef un1_as_030_3_i_i)) - (portRef I1 (instanceRef LDS_000_INT_0_m)) - (portRef I0 (instanceRef LDS_000_INT_0_r)) (portRef I1 (instanceRef UDS_000_INT_0_m)) (portRef I0 (instanceRef UDS_000_INT_0_r)) + (portRef I1 (instanceRef LDS_000_INT_0_m)) + (portRef I0 (instanceRef LDS_000_INT_0_r)) )) - (net N_163 (joined + (net N_204 (joined (portRef O (instanceRef VPA_SYNC_1_sqmuxa_1_i_i)) (portRef I1 (instanceRef VPA_SYNC_0_m)) (portRef I0 (instanceRef VPA_SYNC_0_r)) )) - (net N_164 (joined + (net N_205 (joined (portRef O (instanceRef un1_as_030_000_sync8_i_i)) (portRef I1 (instanceRef FPU_CS_INT_0_m)) (portRef I0 (instanceRef FPU_CS_INT_0_r)) )) - (net N_165 (joined + (net N_23 (joined (portRef O (instanceRef DTACK_SYNC_1_sqmuxa_1_i_i)) (portRef I1 (instanceRef DTACK_SYNC_0_m)) (portRef I0 (instanceRef DTACK_SYNC_0_r)) )) - (net N_30 (joined + (net N_27 (joined (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_i)) (portRef I1 (instanceRef AS_030_000_SYNC_0_m)) (portRef I0 (instanceRef AS_030_000_SYNC_0_r)) )) - (net N_39 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_i_i_6)) - (portRef D (instanceRef SM_AMIGA_1)) - )) - (net N_51 (joined + (net N_47 (joined (portRef O (instanceRef state_machine_UDS_000_INT_5_0_m2_p)) (portRef I1 (instanceRef state_machine_UDS_000_INT_5_0_o3)) )) - (net N_52 (joined - (portRef O (instanceRef DSACK_INT_1_sqmuxa_i_o3_i)) - (portRef I1 (instanceRef DSACK_INT_0_1__m)) - (portRef I0 (instanceRef DSACK_INT_0_1__r)) + (net N_48 (joined + (portRef O (instanceRef N_88_i_0_o2_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_a3_7)) )) - (net N_55 (joined - (portRef O (instanceRef clk_cpu_est_11_i_0_o2_i_2)) - (portRef I0 (instanceRef clk_cpu_est_11_i_0_a3_1_2)) - )) - (net N_56 (joined - (portRef O (instanceRef clk_un4_clk_000_d1_0_o2_i)) + (net N_49 (joined + (portRef O (instanceRef clk_un3_clk_000_d1_0_o2_i)) + (portRef I1 (instanceRef cpu_estse_2_m)) + (portRef I0 (instanceRef cpu_estse_2_r)) + (portRef I1 (instanceRef cpu_estse_1_m)) + (portRef I0 (instanceRef cpu_estse_1_r)) + (portRef I1 (instanceRef cpu_estse_0_m)) + (portRef I0 (instanceRef cpu_estse_0_r)) (portRef I1 (instanceRef IPL_030_0_2__m)) (portRef I0 (instanceRef IPL_030_0_2__r)) (portRef I1 (instanceRef IPL_030_0_1__m)) (portRef I0 (instanceRef IPL_030_0_1__r)) (portRef I1 (instanceRef IPL_030_0_0__m)) (portRef I0 (instanceRef IPL_030_0_0__r)) - (portRef I1 (instanceRef cpu_est_0_3__m)) - (portRef I0 (instanceRef cpu_est_0_3__r)) - (portRef I1 (instanceRef cpu_est_0_2__m)) - (portRef I0 (instanceRef cpu_est_0_2__r)) - (portRef I1 (instanceRef cpu_est_0_1__m)) - (portRef I0 (instanceRef cpu_est_0_1__r)) (portRef I1 (instanceRef state_machine_un6_bgack_000_0)) - (portRef I0 (instanceRef cpu_est_0_0_a3_0)) + (portRef I0 (instanceRef cpu_estse_0_a3)) )) - (net N_57 (joined + (net N_50 (joined + (portRef O (instanceRef DSACK_INT_1_sqmuxa_i_o3_i)) + (portRef I1 (instanceRef DSACK_INT_0_1__m)) + (portRef I0 (instanceRef DSACK_INT_0_1__r)) + )) + (net N_53 (joined (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_i)) (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a3_1)) )) - (net N_58 (joined + (net N_54 (joined (portRef O (instanceRef state_machine_AMIGA_BUS_ENABLE_3_f0_i_o2_i)) (portRef I0 (instanceRef state_machine_AMIGA_BUS_ENABLE_3_f0_i)) )) - (net N_59 (joined - (portRef O (instanceRef SM_AMIGA_ns_0_o2_i_7)) - (portRef I0 (instanceRef SM_AMIGA_ns_0_a3_7)) + (net N_55 (joined + (portRef O (instanceRef un1_DSACK_INT_0_sqmuxa_i_o2_i_o2_i)) + (portRef I0 (instanceRef DSACK_INT_0_1__m)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_0_a3_6)) + (portRef I1 (instanceRef DSACK_INT_1_sqmuxa_i_o3)) )) - (net N_60 (joined - (portRef O (instanceRef clk_cpu_est_11_0_0_o2_i_1)) - (portRef I0 (instanceRef clk_cpu_est_11_0_0_a3_1)) + (net N_57 (joined + (portRef O (instanceRef cpu_est_ns_i_0_o2_i_3)) + (portRef I0 (instanceRef cpu_est_ns_i_0_a3_3)) )) - (net N_61 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_i_o2_i_6)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_i_a3_6)) - )) - (net N_62 (joined - (portRef O (instanceRef clk_cpu_est_11_0_0_o2_i_3)) - (portRef I0 (instanceRef clk_cpu_est_11_0_0_a3_3)) - )) - (net N_63 (joined + (net N_58 (joined (portRef O (instanceRef state_machine_UDS_000_INT_5_0_o3_i)) (portRef I1 (instanceRef un1_as_030_3_i)) )) - (net N_65 (joined + (net N_60 (joined (portRef O (instanceRef SM_AMIGA_ns_i_0_o2_i_1)) (portRef I0 (instanceRef SM_AMIGA_ns_i_0_a3_1)) )) - (net N_66 (joined + (net N_61 (joined (portRef O (instanceRef SM_AMIGA_ns_i_0_o2_i_4)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_0_a3_4)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_0_a3_4)) + )) + (net N_68 (joined + (portRef O (instanceRef state_machine_un15_clk_000_d0_0_a3)) + (portRef I0 (instanceRef N_68_i)) )) (net N_69 (joined - (portRef O (instanceRef state_machine_un1_clk_030_i_a3)) - (portRef I1 (instanceRef BG_000_0_m)) - (portRef I0 (instanceRef BG_000_0_r)) + (portRef O (instanceRef state_machine_un15_clk_000_d0_0_a3_0)) + (portRef I0 (instanceRef N_69_i)) + )) + (net N_70 (joined + (portRef O (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3)) + (portRef I0 (instanceRef N_70_i)) + )) + (net N_71 (joined + (portRef O (instanceRef un1_as_030_000_sync8_i_a3)) + (portRef I0 (instanceRef N_71_i)) )) (net N_72 (joined - (portRef O (instanceRef state_machine_un15_clk_000_d0_0_a3)) + (portRef O (instanceRef DTACK_SYNC_1_sqmuxa_1_i_a3)) (portRef I0 (instanceRef N_72_i)) )) (net N_73 (joined - (portRef O (instanceRef state_machine_un15_clk_000_d0_0_a3_0)) + (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a3)) (portRef I0 (instanceRef N_73_i)) )) - (net N_74 (joined - (portRef O (instanceRef un1_DSACK_INT_0_sqmuxa_i_o2_i_a3)) - (portRef I0 (instanceRef N_74_i)) - )) (net N_75 (joined - (portRef O (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3)) + (portRef O (instanceRef state_machine_LDS_000_INT_5_0_a3)) (portRef I0 (instanceRef N_75_i)) )) - (net N_76 (joined - (portRef O (instanceRef un1_as_030_000_sync8_i_a3)) - (portRef I0 (instanceRef N_76_i)) - )) (net N_77 (joined - (portRef O (instanceRef DTACK_SYNC_1_sqmuxa_1_i_a3)) + (portRef O (instanceRef SM_AMIGA_ns_i_0_a3_1)) (portRef I0 (instanceRef N_77_i)) )) (net N_79 (joined - (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a3)) + (portRef O (instanceRef SM_AMIGA_ns_i_0_a3_0_1)) (portRef I0 (instanceRef N_79_i)) )) (net N_81 (joined - (portRef O (instanceRef state_machine_LDS_000_INT_5_0_a3)) + (portRef O (instanceRef SM_AMIGA_ns_i_0_a3_2)) (portRef I0 (instanceRef N_81_i)) )) - (net N_83 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_0_a3_1)) - (portRef I0 (instanceRef N_83_i)) + (net N_82 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_0_a3_3)) + (portRef I0 (instanceRef N_82_i)) + )) + (net N_84 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_0_a3_4)) + (portRef I0 (instanceRef N_84_i)) )) (net N_85 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_0_a3_0_1)) + (portRef O (instanceRef SM_AMIGA_ns_0_a3_5)) (portRef I0 (instanceRef N_85_i)) )) (net N_86 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_0_a3_2)) + (portRef O (instanceRef SM_AMIGA_ns_0_a3_0_5)) (portRef I0 (instanceRef N_86_i)) )) - (net N_88 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_0_a3_3)) - (portRef I0 (instanceRef N_88_i)) - )) - (net N_89 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_0_a3_4)) - (portRef I0 (instanceRef N_89_i)) - )) - (net N_90 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_0_a3_0_4)) - (portRef I0 (instanceRef N_90_i)) + (net N_93 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_0_a3_6)) + (portRef I0 (instanceRef N_93_i)) )) (net N_94 (joined - (portRef O (instanceRef SM_AMIGA_ns_0_a3_5)) + (portRef O (instanceRef SM_AMIGA_ns_i_0_a3_0_6)) (portRef I0 (instanceRef N_94_i)) )) - (net N_97 (joined - (portRef O (instanceRef SM_AMIGA_ns_0_a3_0_5)) - (portRef I0 (instanceRef N_97_i)) - )) - (net N_98 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_i_a3_6)) - (portRef I0 (instanceRef N_98_i)) - )) - (net N_114 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_i_a3_0_6)) - (portRef I0 (instanceRef N_114_i)) - )) - (net N_115 (joined + (net N_214 (joined (portRef O (instanceRef SM_AMIGA_ns_0_a3_7)) - (portRef I0 (instanceRef N_115_i)) + (portRef I0 (instanceRef N_214_i)) )) - (net N_116 (joined + (net N_215 (joined (portRef O (instanceRef SM_AMIGA_ns_0_a3_0_7)) - (portRef I0 (instanceRef N_116_i)) + (portRef I0 (instanceRef N_215_i)) )) - (net N_117 (joined - (portRef O (instanceRef clk_cpu_est_11_i_0_a3_2)) - (portRef I0 (instanceRef N_117_i)) + (net N_216 (joined + (portRef O (instanceRef cpu_est_ns_0_0_a3_1)) + (portRef I0 (instanceRef N_216_i)) )) - (net N_118 (joined - (portRef O (instanceRef clk_cpu_est_11_i_0_a3_0_2)) - (portRef I0 (instanceRef N_118_i)) + (net N_217 (joined + (portRef O (instanceRef cpu_est_ns_0_0_a3_0_1)) + (portRef I0 (instanceRef N_217_i)) )) - (net N_119 (joined + (net N_220 (joined + (portRef O (instanceRef cpu_est_ns_i_0_a3_3)) + (portRef I0 (instanceRef N_220_i)) + )) + (net N_221 (joined (portRef O (instanceRef state_machine_AMIGA_BUS_ENABLE_3_f0_i_a3)) - (portRef I0 (instanceRef N_119_i)) + (portRef I0 (instanceRef N_221_i)) )) - (net N_120 (joined - (portRef O (instanceRef un1_bg_030_i_a3)) - (portRef I0 (instanceRef N_120_i)) + (net N_222 (joined + (portRef O (instanceRef cpu_est_ns_0_0_a3_2)) + (portRef I0 (instanceRef N_222_i)) )) - (net N_121 (joined - (portRef O (instanceRef clk_cpu_est_11_0_0_a3_1)) - (portRef I0 (instanceRef N_121_i)) + (net N_223 (joined + (portRef O (instanceRef cpu_est_ns_0_0_a3_0_2)) + (portRef I0 (instanceRef N_223_i)) + )) + (net N_225 (joined + (portRef O (instanceRef cpu_est_ns_0_0_a3_1_2)) + (portRef I0 (instanceRef N_225_i)) + )) + (net N_226 (joined + (portRef O (instanceRef SM_AMIGA_ns_0_a3_0)) + (portRef I0 (instanceRef N_226_i)) + )) + (net N_227 (joined + (portRef O (instanceRef SM_AMIGA_ns_0_a3_0_0)) + (portRef I0 (instanceRef N_227_i)) )) (net N_122 (joined - (portRef O (instanceRef clk_cpu_est_11_0_0_a3_0_1)) + (portRef O (instanceRef cpu_estse_0_a3)) (portRef I0 (instanceRef N_122_i)) )) - (net N_124 (joined - (portRef O (instanceRef clk_cpu_est_11_0_0_a3_1_1)) - (portRef I0 (instanceRef N_124_i)) + (net N_123 (joined + (portRef O (instanceRef cpu_estse_0_a3_0)) + (portRef I0 (instanceRef N_123_i)) )) - (net N_125 (joined - (portRef O (instanceRef clk_cpu_est_11_0_0_a3_3)) - (portRef I0 (instanceRef N_125_i)) + (net N_126 (joined + (portRef O (instanceRef cpu_est_ns_0_0_a2_1)) + (portRef I0 (instanceRef cpu_est_ns_i_0_a2_3)) + (portRef I0 (instanceRef N_126_i)) )) - (net N_178 (joined - (portRef O (instanceRef clk_cpu_est_11_0_0_a3_0_3)) - (portRef I0 (instanceRef N_178_i)) + (net N_127 (joined + (portRef O (instanceRef cpu_est_ns_i_0_a2_3)) + (portRef I0 (instanceRef N_127_i)) + (portRef I1 (instanceRef state_machine_un15_clk_000_d0_0_a3_0_1)) )) - (net N_138 (joined - (portRef O (instanceRef clk_cpu_est_11_0_0_a3_1_3)) - (portRef I0 (instanceRef N_138_i)) - )) - (net N_139 (joined - (portRef O (instanceRef SM_AMIGA_ns_0_a3_0)) - (portRef I0 (instanceRef N_139_i)) - )) - (net N_140 (joined - (portRef O (instanceRef SM_AMIGA_ns_0_a3_0_0)) - (portRef I0 (instanceRef N_140_i)) - )) - (net N_141 (joined - (portRef O (instanceRef cpu_est_0_0_a3_0)) - (portRef I0 (instanceRef N_141_i)) - )) - (net N_142 (joined - (portRef O (instanceRef cpu_est_0_0_a3_0_0)) - (portRef I0 (instanceRef N_142_i)) - )) - (net N_145 (joined - (portRef O (instanceRef SM_AMIGA_ns_0_a2_0)) - (portRef I1 (instanceRef SM_AMIGA_ns_0_a3_0)) - (portRef I0 (instanceRef N_145_i)) - )) - (net N_146 (joined - (portRef O (instanceRef clk_cpu_est_11_0_0_a2_1)) - (portRef I0 (instanceRef N_146_i)) + (net N_128 (joined + (portRef O (instanceRef cpu_est_ns_0_0_a2_0_1)) + (portRef I0 (instanceRef N_128_i)) (portRef I1 (instanceRef state_machine_un15_clk_000_d0_0_a3_1)) )) - (net N_77_1 (joined - (portRef O (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_2)) - (portRef I1 (instanceRef DTACK_SYNC_1_sqmuxa_1_i_a3_1)) - (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_1)) + (net N_129 (joined + (portRef O (instanceRef SM_AMIGA_ns_0_a2_0)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_a3_0)) + (portRef I0 (instanceRef N_129_i)) )) - (net N_188 (joined + (net N_130 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_0_a2_4)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_a3_0_5)) + (portRef I0 (instanceRef N_130_i)) + )) + (net N_238 (joined (portRef O (instanceRef un8_ciin)) (portRef OE (instanceRef CIIN)) )) - (net N_191 (joined + (net N_241 (joined (portRef O (instanceRef un4_ciin)) (portRef I0 (instanceRef CIIN)) )) @@ -1260,81 +1196,76 @@ (portRef O (instanceRef RW_i)) (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR)) )) - (net VPA_D_i (joined - (portRef O (instanceRef VPA_D_i)) - (portRef I0 (instanceRef state_machine_un15_clk_000_d0_0_a3_2)) - (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_2_0)) - )) - (net CLK_000_D0_i (joined - (portRef O (instanceRef CLK_000_D0_i)) - (portRef I0 (instanceRef SM_AMIGA_ns_0_a3_5)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_0_a3_4)) - (portRef I0 (instanceRef SM_AMIGA_ns_0_a3_0)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_0_3)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_0_o2_1)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_i_o2_6)) - (portRef I0 (instanceRef state_machine_un15_clk_000_d0_0_a3_1)) - (portRef I0 (instanceRef SM_AMIGA_ns_0_a3_0_1_5)) - )) - (net (rename cpu_est_i_0 "cpu_est_i[0]") (joined - (portRef O (instanceRef cpu_est_i_0)) - (portRef I1 (instanceRef cpu_est_0_0_a3_0_0)) - (portRef I1 (instanceRef clk_cpu_est_11_0_0_a3_1)) - (portRef I0 (instanceRef state_machine_un15_clk_000_d0_0_a3_0_2)) - (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_3)) - (portRef I1 (instanceRef clk_cpu_est_11_i_0_a3_0_1_2)) - (portRef I0 (instanceRef clk_cpu_est_11_0_0_a3_1_1_3)) - )) - (net (rename cpu_est_i_3 "cpu_est_i[3]") (joined - (portRef O (instanceRef cpu_est_i_3)) - (portRef I1 (instanceRef clk_cpu_est_11_0_0_a3_0_1)) - (portRef I1 (instanceRef clk_cpu_est_11_0_0_o2_1)) - (portRef I1 (instanceRef state_machine_un15_clk_000_d0_0_a3_0_2)) - (portRef I1 (instanceRef clk_cpu_est_11_i_0_a3_2)) - )) (net VMA_INT_i (joined (portRef O (instanceRef VMA_INT_i)) - (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_1)) + (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_2)) )) - (net (rename cpu_est_i_1 "cpu_est_i[1]") (joined - (portRef O (instanceRef cpu_est_i_1)) - (portRef I0 (instanceRef clk_cpu_est_11_0_0_o2_1)) - (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_5)) - (portRef I1 (instanceRef clk_cpu_est_11_0_0_a3_1_1_3)) + (net VPA_D_i (joined + (portRef O (instanceRef VPA_D_i)) + (portRef I1 (instanceRef state_machine_un15_clk_000_d0_0_a3)) + (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3)) )) (net DTACK_i (joined - (portRef O (instanceRef I_114)) - (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa_1_i_a3_1)) + (portRef O (instanceRef I_127)) + (portRef I1 (instanceRef DTACK_SYNC_1_sqmuxa_1_i_a3_1)) )) (net BG_030_i (joined (portRef O (instanceRef BG_030_i)) - (portRef I0 (instanceRef state_machine_un1_clk_030_i_a3)) - (portRef I1 (instanceRef un1_bg_030_i_a3_1)) + (portRef I0 (instanceRef state_machine_un10_bg_030_0_a3_2)) )) (net nEXP_SPACE_i (joined (portRef O (instanceRef nEXP_SPACE_i)) (portRef I1 (instanceRef SM_AMIGA_ns_0_a2_0)) - (portRef I1 (instanceRef un1_bg_030_i_a3_2)) + (portRef I0 (instanceRef state_machine_un10_bg_030_0_a3_1)) )) - (net (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (joined - (portRef O (instanceRef SM_AMIGA_i_3)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_0_a3_0_4)) + (net CLK_000_D0_i (joined + (portRef O (instanceRef CLK_000_D0_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_0_a3_6)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_a3_5)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_0_a2_4)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_a3_0)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_0_3)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_0_o2_1)) + (portRef I0 (instanceRef state_machine_un15_clk_000_d0_0_a3_1)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_a3_0_1_7)) )) - (net AS_000_INT_i (joined - (portRef O (instanceRef AS_000_INT_i)) - (portRef I0 (instanceRef state_machine_un7_as_000_int_0_a3)) + (net (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (joined + (portRef O (instanceRef SM_AMIGA_i_4)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_0_a3_3)) + )) + (net (rename cpu_est_i_3 "cpu_est_i[3]") (joined + (portRef O (instanceRef cpu_est_i_3)) + (portRef I1 (instanceRef cpu_est_ns_0_0_a3_0_1)) + (portRef I1 (instanceRef cpu_est_ns_i_0_a2_3)) + )) + (net (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (joined + (portRef O (instanceRef SM_AMIGA_i_1)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_0_a3_0_6)) + )) + (net (rename state_machine_un6_clk_000_d4_i "state_machine.un6_clk_000_d4_i") (joined + (portRef O (instanceRef state_machine_un6_clk_000_d4_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_a3_0_7)) )) (net (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (joined (portRef O (instanceRef SM_AMIGA_i_6)) (portRef I1 (instanceRef SM_AMIGA_ns_i_0_a3_2)) (portRef I1 (instanceRef state_machine_AMIGA_BUS_ENABLE_3_f0_i_a3)) )) - (net (rename cpu_est_i_2 "cpu_est_i[2]") (joined - (portRef O (instanceRef cpu_est_i_2)) - (portRef I1 (instanceRef clk_cpu_est_11_0_0_a3_0_3)) - (portRef I0 (instanceRef clk_cpu_est_11_0_0_a3_0_1)) - (portRef I1 (instanceRef clk_cpu_est_11_i_0_a3_0_2)) - (portRef I1 (instanceRef clk_cpu_est_11_0_0_a3_1_3)) + (net AS_000_INT_i (joined + (portRef O (instanceRef AS_000_INT_i)) + (portRef I0 (instanceRef state_machine_un7_as_000_int_0_a3)) + )) + (net (rename cpu_est_i_1 "cpu_est_i[1]") (joined + (portRef O (instanceRef cpu_est_i_1)) + (portRef I1 (instanceRef cpu_est_ns_0_0_a2_0_1)) + (portRef I1 (instanceRef cpu_est_ns_0_0_a3_0_2)) + (portRef I1 (instanceRef cpu_est_ns_i_0_o2_3)) + )) + (net (rename cpu_est_i_0 "cpu_est_i[0]") (joined + (portRef O (instanceRef cpu_est_i_0)) + (portRef I1 (instanceRef cpu_est_ns_0_0_a2_1)) + (portRef I1 (instanceRef cpu_estse_0_a3_0)) + (portRef I0 (instanceRef cpu_est_ns_0_0_a3_0_2)) )) (net AMIGA_BUS_ENABLE_i (joined (portRef O (instanceRef AMIGA_BUS_ENABLE_i)) @@ -1343,24 +1274,31 @@ (net AS_030_i (joined (portRef O (instanceRef AS_030_i)) (portRef I0 (instanceRef AS_000_INT_1_sqmuxa_0_a3)) - (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1_i)) (portRef I0 (instanceRef un1_as_030_3_i)) (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa_1_i)) (portRef I0 (instanceRef un1_as_030_000_sync8_i)) + (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1_i)) (portRef I0 (instanceRef DSACK_INT_1_sqmuxa_i_o3)) (portRef I1 (instanceRef state_machine_AMIGA_BUS_ENABLE_3_f0_i_a3_1)) )) - (net (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (joined - (portRef O (instanceRef SM_AMIGA_i_4)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_0_a3_0_4)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_0_a3_3)) + (net (rename cpu_est_i_2 "cpu_est_i[2]") (joined + (portRef O (instanceRef cpu_est_i_2)) + (portRef I0 (instanceRef cpu_est_ns_0_0_a3_0_1)) + )) + (net (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (joined + (portRef O (instanceRef SM_AMIGA_i_2)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_0_a3_0_6)) + )) + (net (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (joined + (portRef O (instanceRef SM_AMIGA_i_3)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_0_a3_4)) )) (net (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (joined (portRef O (instanceRef SM_AMIGA_i_5)) (portRef I0 (instanceRef AS_000_INT_0_n)) - (portRef I1 (instanceRef AS_000_INT_1_sqmuxa_0_a3)) (portRef I1 (instanceRef SM_AMIGA_ns_i_0_a3_3)) (portRef I0 (instanceRef SM_AMIGA_ns_i_0_a3_2)) + (portRef I1 (instanceRef AS_000_INT_1_sqmuxa_0_a3)) )) (net (rename state_machine_un8_clk_000_d2_i "state_machine.un8_clk_000_d2_i") (joined (portRef O (instanceRef state_machine_un8_clk_000_d2_i)) @@ -1380,19 +1318,9 @@ (portRef I1 (instanceRef state_machine_LDS_000_INT_5_0_a3)) )) (net (rename DSACK_i_1 "DSACK_i[1]") (joined - (portRef O (instanceRef I_115)) + (portRef O (instanceRef I_128)) (portRef I1 (instanceRef state_machine_un7_as_000_int_0_a3)) )) - (net (rename clk_clk_cnt_i "clk.clk_cnt_i") (joined - (portRef O (instanceRef clk_clk_cnt_i)) - (portRef I1 (instanceRef clk_CLK_CNT_3_0)) - (portRef I0 (instanceRef clk_CLK_CNT_3_1)) - )) - (net (rename CLK_CNT_i_0 "CLK_CNT_i[0]") (joined - (portRef O (instanceRef CLK_CNT_i_0)) - (portRef I0 (instanceRef G_93)) - (portRef I0 (instanceRef clk_CLK_CNT_3_0)) - )) (net CLK_000_D2_i (joined (portRef O (instanceRef CLK_000_D2_i)) (portRef I1 (instanceRef state_machine_un8_clk_000_d2)) @@ -1445,21 +1373,24 @@ (portRef O (instanceRef A_i_18)) (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_5)) )) - (net N_137_i (joined - (portRef O (instanceRef N_137_i)) - (portRef I1 (instanceRef G_93)) - )) - (net (rename state_machine_un7_as_000_int_i "state_machine.un7_as_000_int_i") (joined - (portRef O (instanceRef state_machine_un7_as_000_int_i)) - (portRef D (instanceRef DTACK_DMA)) - )) (net RST_i (joined (portRef O (instanceRef RST_i)) - (portRef R (instanceRef CLK_REF_1)) (portRef S (instanceRef AS_000_INT)) (portRef S (instanceRef AS_030_000_SYNC)) (portRef S (instanceRef BGACK_030_INT)) (portRef S (instanceRef BG_000DFFSH)) + (portRef S (instanceRef CLK_000_D0)) + (portRef S (instanceRef CLK_000_D1)) + (portRef S (instanceRef CLK_000_D2)) + (portRef S (instanceRef CLK_000_D3)) + (portRef S (instanceRef CLK_000_D4)) + (portRef S (instanceRef CLK_000_D5)) + (portRef R (instanceRef CLK_CNT_N_0)) + (portRef R (instanceRef CLK_CNT_N_1)) + (portRef R (instanceRef CLK_CNT_P_0)) + (portRef R (instanceRef CLK_CNT_P_1)) + (portRef R (instanceRef CLK_OUT_INT)) + (portRef R (instanceRef CLK_OUT_PRE)) (portRef S (instanceRef DSACK_INT_1)) (portRef S (instanceRef DTACK_DMA)) (portRef S (instanceRef DTACK_SYNC)) @@ -1468,6 +1399,7 @@ (portRef S (instanceRef IPL_030DFFSH_1)) (portRef S (instanceRef IPL_030DFFSH_2)) (portRef S (instanceRef LDS_000_INT)) + (portRef R (instanceRef RESETDFFRH)) (portRef R (instanceRef SM_AMIGA_0)) (portRef R (instanceRef SM_AMIGA_1)) (portRef R (instanceRef SM_AMIGA_2)) @@ -1478,24 +1410,41 @@ (portRef S (instanceRef SM_AMIGA_7)) (portRef S (instanceRef UDS_000_INT)) (portRef S (instanceRef VMA_INT)) + (portRef S (instanceRef VPA_D)) (portRef S (instanceRef VPA_SYNC)) + (portRef R (instanceRef cpu_est_0)) + (portRef R (instanceRef cpu_est_1)) + (portRef R (instanceRef cpu_est_2)) + (portRef R (instanceRef cpu_est_3)) )) - (net N_120_i (joined - (portRef O (instanceRef N_120_i)) - (portRef I0 (instanceRef BG_000_0_n)) + (net (rename state_machine_un10_bg_030_i "state_machine.un10_bg_030_i") (joined + (portRef O (instanceRef state_machine_un10_bg_030_i)) + (portRef D (instanceRef BG_000DFFSH)) )) - (net N_75_i (joined - (portRef O (instanceRef N_75_i)) + (net (rename state_machine_un7_as_000_int_i "state_machine.un7_as_000_int_i") (joined + (portRef O (instanceRef state_machine_un7_as_000_int_i)) + (portRef D (instanceRef DTACK_DMA)) + )) + (net (rename un2_clk_cnt_p_i_1 "un2_clk_cnt_p_i[1]") (joined + (portRef O (instanceRef un2_clk_cnt_p_i_1)) + (portRef D (instanceRef CLK_CNT_P_0)) + )) + (net CLK_OSZI_i (joined + (portRef O (instanceRef CLK_OSZI_i)) + (portRef CLK (instanceRef CLK_CNT_N_0)) + (portRef CLK (instanceRef CLK_CNT_N_1)) + )) + (net (rename un4_clk_cnt_n_i_1 "un4_clk_cnt_n_i[1]") (joined + (portRef O (instanceRef un4_clk_cnt_n_i_1)) + (portRef D (instanceRef CLK_CNT_N_0)) + )) + (net N_70_i (joined + (portRef O (instanceRef N_70_i)) (portRef I0 (instanceRef VPA_SYNC_0_m)) (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_1_i)) )) - (net N_74_i (joined - (portRef O (instanceRef N_74_i)) - (portRef I0 (instanceRef DSACK_INT_0_1__m)) - (portRef I1 (instanceRef DSACK_INT_1_sqmuxa_i_o3)) - )) - (net N_77_i (joined - (portRef O (instanceRef N_77_i)) + (net N_72_i (joined + (portRef O (instanceRef N_72_i)) (portRef I0 (instanceRef DTACK_SYNC_0_m)) (portRef I1 (instanceRef DTACK_SYNC_1_sqmuxa_1_i)) )) @@ -1516,7 +1465,7 @@ (portRef O (instanceRef AS_030)) (portRef I0 (instanceRef FPU_CS_INT_0_m)) (portRef I0 (instanceRef AS_030_i)) - (portRef I0 (instanceRef un1_bg_030_i_a3_1)) + (portRef I1 (instanceRef state_machine_un10_bg_030_0_a3_1)) )) (net AS_030 (joined (portRef AS_030) @@ -1765,7 +1714,6 @@ )) (net BG_000_c (joined (portRef Q (instanceRef BG_000DFFSH)) - (portRef I0 (instanceRef BG_000_0_m)) (portRef I0 (instanceRef BG_000)) )) (net BG_000 (joined @@ -1789,7 +1737,6 @@ (net CLK_030_c (joined (portRef O (instanceRef CLK_030)) (portRef I0 (instanceRef un1_as_030_000_sync8_i_a3)) - (portRef I1 (instanceRef state_machine_un1_clk_030_i_a3)) (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a3_1)) )) (net CLK_030 (joined @@ -1806,6 +1753,7 @@ )) (net CLK_OSZI_c (joined (portRef O (instanceRef CLK_OSZI)) + (portRef I0 (instanceRef CLK_OSZI_i)) (portRef CLK (instanceRef AMIGA_BUS_ENABLEDFF)) (portRef CLK (instanceRef AS_000_INT)) (portRef CLK (instanceRef AS_030_000_SYNC)) @@ -1817,8 +1765,8 @@ (portRef CLK (instanceRef CLK_000_D3)) (portRef CLK (instanceRef CLK_000_D4)) (portRef CLK (instanceRef CLK_000_D5)) - (portRef CLK (instanceRef CLK_CNT_0)) - (portRef CLK (instanceRef CLK_CNT_1)) + (portRef CLK (instanceRef CLK_CNT_P_0)) + (portRef CLK (instanceRef CLK_CNT_P_1)) (portRef CLK (instanceRef CLK_OUT_INT)) (portRef CLK (instanceRef CLK_OUT_PRE)) (portRef CLK (instanceRef DSACK_INT_1)) @@ -1829,7 +1777,7 @@ (portRef CLK (instanceRef IPL_030DFFSH_1)) (portRef CLK (instanceRef IPL_030DFFSH_2)) (portRef CLK (instanceRef LDS_000_INT)) - (portRef CLK (instanceRef RESETDFF)) + (portRef CLK (instanceRef RESETDFFRH)) (portRef CLK (instanceRef SM_AMIGA_0)) (portRef CLK (instanceRef SM_AMIGA_1)) (portRef CLK (instanceRef SM_AMIGA_2)) @@ -1925,7 +1873,7 @@ )) (net (rename DSACK_c_1 "DSACK_c[1]") (joined (portRef O (instanceRef DSACK_1)) - (portRef I0 (instanceRef I_115)) + (portRef I0 (instanceRef I_128)) )) (net (rename DSACK_1 "DSACK[1]") (joined (portRef (member dsack 0)) @@ -1933,7 +1881,7 @@ )) (net DTACK_c (joined (portRef O (instanceRef DTACK)) - (portRef I0 (instanceRef I_114)) + (portRef I0 (instanceRef I_127)) )) (net DTACK (joined (portRef IO (instanceRef DTACK)) @@ -1968,14 +1916,13 @@ (portRef I1 (instanceRef AMIGA_BUS_ENABLE_0_m)) (portRef I0 (instanceRef AMIGA_BUS_ENABLE_0_r)) (portRef I0 (instanceRef RST_i)) - (portRef D (instanceRef RESETDFF)) )) (net RST (joined (portRef RST) (portRef I0 (instanceRef RST)) )) (net RESET_c (joined - (portRef Q (instanceRef RESETDFF)) + (portRef Q (instanceRef RESETDFFRH)) (portRef I0 (instanceRef RESET)) )) (net RESET (joined @@ -2030,36 +1977,36 @@ (portRef O (instanceRef CIIN)) (portRef CIIN) )) - (net (rename clk_cpu_est_11_0_1 "clk.cpu_est_11_0[1]") (joined - (portRef O (instanceRef clk_cpu_est_11_0_0_1)) - (portRef I0 (instanceRef clk_cpu_est_11_0_0_i_1)) + (net (rename cpu_est_ns_0_1 "cpu_est_ns_0[1]") (joined + (portRef O (instanceRef cpu_est_ns_0_0_1)) + (portRef I0 (instanceRef cpu_est_ns_0_0_i_1)) )) - (net N_124_i (joined - (portRef O (instanceRef N_124_i)) - (portRef I0 (instanceRef clk_cpu_est_11_0_0_2_1)) + (net N_126_i (joined + (portRef O (instanceRef N_126_i)) + (portRef I0 (instanceRef cpu_est_ns_0_0_1_1)) )) - (net N_146_i (joined - (portRef O (instanceRef N_146_i)) - (portRef I1 (instanceRef clk_cpu_est_11_0_0_2_1)) + (net N_128_i (joined + (portRef O (instanceRef N_128_i)) + (portRef I1 (instanceRef cpu_est_ns_0_0_1_1)) )) - (net N_121_i (joined - (portRef O (instanceRef N_121_i)) - (portRef I0 (instanceRef clk_cpu_est_11_0_0_1_1)) + (net N_216_i (joined + (portRef O (instanceRef N_216_i)) + (portRef I0 (instanceRef cpu_est_ns_0_0_2_1)) )) - (net N_122_i (joined - (portRef O (instanceRef N_122_i)) - (portRef I1 (instanceRef clk_cpu_est_11_0_0_1_1)) + (net N_217_i (joined + (portRef O (instanceRef N_217_i)) + (portRef I1 (instanceRef cpu_est_ns_0_0_2_1)) )) - (net N_66_0 (joined + (net N_61_0 (joined (portRef O (instanceRef SM_AMIGA_ns_i_0_o2_4)) (portRef I0 (instanceRef SM_AMIGA_ns_i_0_o2_i_4)) )) - (net N_65_0 (joined + (net N_60_0 (joined (portRef O (instanceRef SM_AMIGA_ns_i_0_o2_1)) (portRef I0 (instanceRef SM_AMIGA_ns_i_0_o2_i_1)) )) - (net N_145_i (joined - (portRef O (instanceRef N_145_i)) + (net N_129_i (joined + (portRef O (instanceRef N_129_i)) (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0_o3)) )) (net un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 (joined @@ -2071,206 +2018,192 @@ (portRef O (instanceRef DS_030_c_i)) (portRef I0 (instanceRef state_machine_UDS_000_INT_5_0_o3)) )) - (net N_63_i (joined + (net N_58_i (joined (portRef O (instanceRef state_machine_UDS_000_INT_5_0_o3)) (portRef I0 (instanceRef state_machine_LDS_000_INT_5_0)) (portRef I1 (instanceRef state_machine_UDS_000_INT_5_0)) (portRef I0 (instanceRef state_machine_UDS_000_INT_5_0_o3_i)) )) - (net N_62_i (joined - (portRef O (instanceRef clk_cpu_est_11_0_0_o2_3)) - (portRef I0 (instanceRef clk_cpu_est_11_0_0_a3_0_3)) - (portRef I0 (instanceRef clk_cpu_est_11_0_0_o2_i_3)) + (net N_57_i (joined + (portRef O (instanceRef cpu_est_ns_i_0_o2_3)) + (portRef I0 (instanceRef cpu_est_ns_i_0_o2_i_3)) + (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_1)) )) - (net (rename state_machine_un6_clk_000_d4_i "state_machine.un6_clk_000_d4_i") (joined - (portRef O (instanceRef state_machine_un6_clk_000_d4_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_i_o2_6)) + (net N_55_i (joined + (portRef O (instanceRef un1_DSACK_INT_0_sqmuxa_i_o2_i_o2)) + (portRef I0 (instanceRef un1_DSACK_INT_0_sqmuxa_i_o2_i_o2_i)) )) - (net N_61_i (joined - (portRef O (instanceRef SM_AMIGA_ns_i_i_o2_6)) - (portRef I0 (instanceRef SM_AMIGA_ns_0_a3_0_7)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_i_o2_i_6)) - )) - (net N_60_i (joined - (portRef O (instanceRef clk_cpu_est_11_0_0_o2_1)) - (portRef I0 (instanceRef clk_cpu_est_11_0_0_a2_1)) - (portRef I0 (instanceRef clk_cpu_est_11_0_0_o2_i_1)) - )) - (net N_59_i (joined - (portRef O (instanceRef SM_AMIGA_ns_0_o2_7)) - (portRef I0 (instanceRef SM_AMIGA_ns_0_a3_0_0)) - (portRef I0 (instanceRef SM_AMIGA_ns_0_o2_i_7)) - (portRef I1 (instanceRef state_machine_un15_clk_000_d0_0_a3_0_1)) - )) - (net N_58_i (joined + (net N_54_i (joined (portRef O (instanceRef state_machine_AMIGA_BUS_ENABLE_3_f0_i_o2)) (portRef I1 (instanceRef SM_AMIGA_ns_i_0_o2_1)) (portRef I0 (instanceRef state_machine_AMIGA_BUS_ENABLE_3_f0_i_o2_i)) )) - (net N_57_i (joined + (net N_53_i (joined (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2)) (portRef I1 (instanceRef un1_as_030_000_sync8_i_a3)) (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_i)) )) - (net CLK_000_D1_i (joined - (portRef O (instanceRef CLK_000_D1_i)) - (portRef I1 (instanceRef clk_un4_clk_000_d1_0_o2)) - )) - (net N_56_i (joined - (portRef O (instanceRef clk_un4_clk_000_d1_0_o2)) - (portRef I0 (instanceRef cpu_est_0_0_a3_0_0)) - (portRef I0 (instanceRef clk_un4_clk_000_d1_0_o2_i)) - )) - (net N_55_i (joined - (portRef O (instanceRef clk_cpu_est_11_i_0_o2_2)) - (portRef I0 (instanceRef clk_cpu_est_11_0_0_a3_1_1)) - (portRef I0 (instanceRef clk_cpu_est_11_i_0_o2_i_2)) - (portRef I0 (instanceRef state_machine_un15_clk_000_d0_0_a3_0_1)) - )) - (net N_52_i (joined + (net N_50_i (joined (portRef O (instanceRef DSACK_INT_1_sqmuxa_i_o3)) (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0_o3)) (portRef I0 (instanceRef DSACK_INT_1_sqmuxa_i_o3_i)) )) - (net N_141_i (joined - (portRef O (instanceRef N_141_i)) - (portRef I0 (instanceRef cpu_est_0_0_0)) + (net CLK_000_D1_i (joined + (portRef O (instanceRef CLK_000_D1_i)) + (portRef I1 (instanceRef clk_un3_clk_000_d1_0_o2)) )) - (net N_142_i (joined - (portRef O (instanceRef N_142_i)) - (portRef I1 (instanceRef cpu_est_0_0_0)) + (net N_49_i (joined + (portRef O (instanceRef clk_un3_clk_000_d1_0_o2)) + (portRef I0 (instanceRef cpu_estse_0_a3_0)) + (portRef I0 (instanceRef clk_un3_clk_000_d1_0_o2_i)) + (portRef I1 (instanceRef state_machine_un10_bg_030_0_a3_2)) )) - (net N_14_0 (joined - (portRef O (instanceRef cpu_est_0_0_0)) - (portRef I0 (instanceRef cpu_est_0_0_i_0)) + (net N_48_i (joined + (portRef O (instanceRef N_88_i_0_o2)) + (portRef I0 (instanceRef VMA_INT_0_m)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_a3_0_0)) + (portRef I0 (instanceRef N_88_i_0_o2_i)) + (portRef I0 (instanceRef state_machine_un15_clk_000_d0_0_a3_0_1)) )) - (net N_85_i (joined - (portRef O (instanceRef N_85_i)) + (net N_122_i (joined + (portRef O (instanceRef N_122_i)) + (portRef I0 (instanceRef cpu_estse_0_0)) + )) + (net N_123_i (joined + (portRef O (instanceRef N_123_i)) + (portRef I1 (instanceRef cpu_estse_0_0)) + )) + (net (rename cpu_est_ns_e_0_0 "cpu_est_ns_e_0[0]") (joined + (portRef O (instanceRef cpu_estse_0_0)) + (portRef I0 (instanceRef cpu_estse_0_0_i)) + )) + (net N_79_i (joined + (portRef O (instanceRef N_79_i)) (portRef I1 (instanceRef SM_AMIGA_ns_i_0_1)) (portRef I1 (instanceRef SM_AMIGA_ns_0_1_0)) )) - (net N_139_i (joined - (portRef O (instanceRef N_139_i)) + (net N_226_i (joined + (portRef O (instanceRef N_226_i)) (portRef I1 (instanceRef SM_AMIGA_ns_0_0)) )) - (net N_140_i (joined - (portRef O (instanceRef N_140_i)) + (net N_227_i (joined + (portRef O (instanceRef N_227_i)) (portRef I0 (instanceRef SM_AMIGA_ns_0_1_0)) )) (net (rename SM_AMIGA_ns_0_0 "SM_AMIGA_ns_0[0]") (joined (portRef O (instanceRef SM_AMIGA_ns_0_0)) (portRef I0 (instanceRef SM_AMIGA_ns_0_i_0)) )) - (net N_125_i (joined - (portRef O (instanceRef N_125_i)) - (portRef I1 (instanceRef clk_cpu_est_11_0_0_1_3)) + (net N_222_i (joined + (portRef O (instanceRef N_222_i)) + (portRef I1 (instanceRef cpu_est_ns_0_0_1_2)) )) - (net N_138_i (joined - (portRef O (instanceRef N_138_i)) - (portRef I1 (instanceRef clk_cpu_est_11_0_0_3)) + (net N_223_i (joined + (portRef O (instanceRef N_223_i)) + (portRef I1 (instanceRef cpu_est_ns_0_0_2)) )) - (net N_178_i (joined - (portRef O (instanceRef N_178_i)) - (portRef I0 (instanceRef clk_cpu_est_11_0_0_1_3)) + (net N_225_i (joined + (portRef O (instanceRef N_225_i)) + (portRef I0 (instanceRef cpu_est_ns_0_0_1_2)) )) - (net (rename clk_cpu_est_11_0_3 "clk.cpu_est_11_0[3]") (joined - (portRef O (instanceRef clk_cpu_est_11_0_0_3)) - (portRef I0 (instanceRef clk_cpu_est_11_0_0_i_3)) + (net (rename cpu_est_ns_0_2 "cpu_est_ns_0[2]") (joined + (portRef O (instanceRef cpu_est_ns_0_0_2)) + (portRef I0 (instanceRef cpu_est_ns_0_0_i_2)) )) - (net N_119_i (joined - (portRef O (instanceRef N_119_i)) + (net N_221_i (joined + (portRef O (instanceRef N_221_i)) (portRef I1 (instanceRef state_machine_AMIGA_BUS_ENABLE_3_f0_i)) )) - (net N_43_i (joined + (net N_41_i (joined (portRef O (instanceRef state_machine_AMIGA_BUS_ENABLE_3_f0_i)) (portRef I0 (instanceRef AMIGA_BUS_ENABLE_0_m)) )) - (net N_117_i (joined - (portRef O (instanceRef N_117_i)) - (portRef I0 (instanceRef clk_cpu_est_11_i_0_2)) + (net N_127_i (joined + (portRef O (instanceRef N_127_i)) + (portRef I0 (instanceRef cpu_est_ns_i_0_3)) )) - (net N_118_i (joined - (portRef O (instanceRef N_118_i)) - (portRef I1 (instanceRef clk_cpu_est_11_i_0_2)) + (net N_220_i (joined + (portRef O (instanceRef N_220_i)) + (portRef I1 (instanceRef cpu_est_ns_i_0_3)) )) - (net N_123_i (joined - (portRef O (instanceRef clk_cpu_est_11_i_0_2)) - (portRef I0 (instanceRef cpu_est_0_2__n)) + (net N_157_i (joined + (portRef O (instanceRef cpu_est_ns_i_0_3)) + (portRef I0 (instanceRef cpu_estse_2_n)) )) - (net N_115_i (joined - (portRef O (instanceRef N_115_i)) + (net N_214_i (joined + (portRef O (instanceRef N_214_i)) (portRef I0 (instanceRef SM_AMIGA_ns_0_7)) )) - (net N_116_i (joined - (portRef O (instanceRef N_116_i)) + (net N_215_i (joined + (portRef O (instanceRef N_215_i)) (portRef I1 (instanceRef SM_AMIGA_ns_0_7)) )) (net (rename SM_AMIGA_ns_0_7 "SM_AMIGA_ns_0[7]") (joined (portRef O (instanceRef SM_AMIGA_ns_0_7)) (portRef I0 (instanceRef SM_AMIGA_ns_0_i_7)) )) - (net N_98_i (joined - (portRef O (instanceRef N_98_i)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_i_6)) - )) - (net N_114_i (joined - (portRef O (instanceRef N_114_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_i_6)) - )) - (net N_39_0 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_i_6)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_i_i_6)) + (net N_93_i (joined + (portRef O (instanceRef N_93_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_0_6)) )) (net N_94_i (joined (portRef O (instanceRef N_94_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_0_6)) + )) + (net N_83_i (joined + (portRef O (instanceRef SM_AMIGA_ns_i_0_6)) + (portRef D (instanceRef SM_AMIGA_1)) + )) + (net N_85_i (joined + (portRef O (instanceRef N_85_i)) (portRef I0 (instanceRef SM_AMIGA_ns_0_5)) )) - (net N_97_i (joined - (portRef O (instanceRef N_97_i)) + (net N_86_i (joined + (portRef O (instanceRef N_86_i)) (portRef I1 (instanceRef SM_AMIGA_ns_0_5)) )) (net (rename SM_AMIGA_ns_0_5 "SM_AMIGA_ns_0[5]") (joined (portRef O (instanceRef SM_AMIGA_ns_0_5)) (portRef I0 (instanceRef SM_AMIGA_ns_0_i_5)) )) - (net N_89_i (joined - (portRef O (instanceRef N_89_i)) + (net N_84_i (joined + (portRef O (instanceRef N_84_i)) (portRef I0 (instanceRef SM_AMIGA_ns_i_0_4)) )) - (net N_90_i (joined - (portRef O (instanceRef N_90_i)) + (net N_130_i (joined + (portRef O (instanceRef N_130_i)) (portRef I1 (instanceRef SM_AMIGA_ns_i_0_4)) )) - (net N_84_i (joined + (net N_80_i (joined (portRef O (instanceRef SM_AMIGA_ns_i_0_4)) (portRef D (instanceRef SM_AMIGA_3)) )) - (net N_88_i (joined - (portRef O (instanceRef N_88_i)) + (net N_82_i (joined + (portRef O (instanceRef N_82_i)) (portRef I1 (instanceRef SM_AMIGA_ns_i_0_3)) )) - (net N_82_i (joined + (net N_78_i (joined (portRef O (instanceRef SM_AMIGA_ns_i_0_3)) (portRef D (instanceRef SM_AMIGA_4)) )) - (net N_86_i (joined - (portRef O (instanceRef N_86_i)) + (net N_81_i (joined + (portRef O (instanceRef N_81_i)) (portRef I1 (instanceRef SM_AMIGA_ns_i_0_2)) )) - (net N_80_i (joined + (net N_76_i (joined (portRef O (instanceRef SM_AMIGA_ns_i_0_2)) (portRef D (instanceRef SM_AMIGA_5)) )) - (net N_83_i (joined - (portRef O (instanceRef N_83_i)) + (net N_77_i (joined + (portRef O (instanceRef N_77_i)) (portRef I0 (instanceRef SM_AMIGA_ns_i_0_1)) )) - (net N_78_i (joined + (net N_74_i (joined (portRef O (instanceRef SM_AMIGA_ns_i_0_1)) (portRef D (instanceRef SM_AMIGA_6)) )) - (net N_81_i (joined - (portRef O (instanceRef N_81_i)) + (net N_75_i (joined + (portRef O (instanceRef N_75_i)) (portRef I1 (instanceRef state_machine_LDS_000_INT_5_0)) )) (net (rename state_machine_LDS_000_INT_5_0 "state_machine.LDS_000_INT_5_0") (joined @@ -2281,43 +2214,43 @@ (portRef O (instanceRef state_machine_UDS_000_INT_5_0)) (portRef I0 (instanceRef state_machine_UDS_000_INT_5_0_i)) )) - (net N_79_i (joined - (portRef O (instanceRef N_79_i)) + (net N_73_i (joined + (portRef O (instanceRef N_73_i)) (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i)) )) - (net N_30_0 (joined + (net N_27_0 (joined (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i)) (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_i)) )) - (net N_165_0 (joined + (net N_23_0 (joined (portRef O (instanceRef DTACK_SYNC_1_sqmuxa_1_i)) (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa_1_i_i)) )) - (net N_76_i (joined - (portRef O (instanceRef N_76_i)) + (net N_71_i (joined + (portRef O (instanceRef N_71_i)) (portRef I1 (instanceRef un1_as_030_000_sync8_i)) )) - (net N_164_0 (joined + (net N_205_0 (joined (portRef O (instanceRef un1_as_030_000_sync8_i)) (portRef I0 (instanceRef un1_as_030_000_sync8_i_i)) )) - (net N_163_0 (joined + (net N_204_0 (joined (portRef O (instanceRef VPA_SYNC_1_sqmuxa_1_i)) (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1_i_i)) )) - (net N_72_i (joined - (portRef O (instanceRef N_72_i)) + (net N_68_i (joined + (portRef O (instanceRef N_68_i)) (portRef I0 (instanceRef state_machine_un15_clk_000_d0_0)) )) - (net N_73_i (joined - (portRef O (instanceRef N_73_i)) + (net N_69_i (joined + (portRef O (instanceRef N_69_i)) (portRef I1 (instanceRef state_machine_un15_clk_000_d0_0)) )) (net (rename state_machine_un15_clk_000_d0_0 "state_machine.un15_clk_000_d0_0") (joined (portRef O (instanceRef state_machine_un15_clk_000_d0_0)) (portRef I0 (instanceRef state_machine_un15_clk_000_d0_0_i)) )) - (net N_162_0 (joined + (net N_203_0 (joined (portRef O (instanceRef un1_as_030_3_i)) (portRef I0 (instanceRef un1_as_030_3_i_i)) )) @@ -2325,40 +2258,43 @@ (portRef O (instanceRef state_machine_un6_bgack_000_0)) (portRef I0 (instanceRef state_machine_un6_bgack_000_0_i)) )) - (net (rename state_machine_un23_clk_000_d0_i "state_machine.un23_clk_000_d0_i") (joined - (portRef O (instanceRef state_machine_un23_clk_000_d0)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_0_o2_4)) - (portRef I0 (instanceRef state_machine_un23_clk_000_d0_i_0)) + (net (rename clk_un12_clk_cnt_p_i "clk.un12_clk_cnt_p_i") (joined + (portRef O (instanceRef clk_un12_clk_cnt_p)) + (portRef D (instanceRef CLK_OUT_PRE)) )) - (net N_188_1 (joined + (net (rename state_machine_un23_clk_000_d0_0 "state_machine.un23_clk_000_d0_0") (joined + (portRef O (instanceRef state_machine_un23_clk_000_d0)) + (portRef I0 (instanceRef state_machine_un23_clk_000_d0_i)) + )) + (net N_238_1 (joined (portRef O (instanceRef un8_ciin_1)) (portRef I0 (instanceRef un8_ciin_5)) )) - (net N_188_2 (joined + (net N_238_2 (joined (portRef O (instanceRef un8_ciin_2)) (portRef I1 (instanceRef un8_ciin_5)) )) - (net N_188_3 (joined + (net N_238_3 (joined (portRef O (instanceRef un8_ciin_3)) (portRef I0 (instanceRef un8_ciin_6)) )) - (net N_188_4 (joined + (net N_238_4 (joined (portRef O (instanceRef un8_ciin_4)) (portRef I1 (instanceRef un8_ciin_6)) )) - (net N_188_5 (joined + (net N_238_5 (joined (portRef O (instanceRef un8_ciin_5)) (portRef I0 (instanceRef un8_ciin)) )) - (net N_188_6 (joined + (net N_238_6 (joined (portRef O (instanceRef un8_ciin_6)) (portRef I1 (instanceRef un8_ciin)) )) - (net N_191_1 (joined + (net N_241_1 (joined (portRef O (instanceRef un4_ciin_1)) (portRef I0 (instanceRef un4_ciin)) )) - (net N_191_2 (joined + (net N_241_2 (joined (portRef O (instanceRef un4_ciin_2)) (portRef I1 (instanceRef un4_ciin)) )) @@ -2366,122 +2302,102 @@ (portRef O (instanceRef state_machine_un8_clk_000_d2_1)) (portRef I0 (instanceRef state_machine_un8_clk_000_d2)) )) - (net N_57_i_1 (joined + (net N_53_i_1 (joined (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_1)) (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_4)) )) - (net N_57_i_2 (joined + (net N_53_i_2 (joined (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_2)) (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_4)) )) - (net N_57_i_3 (joined + (net N_53_i_3 (joined (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_3)) (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_5)) )) - (net N_57_i_4 (joined + (net N_53_i_4 (joined (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_4)) (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2)) )) - (net N_57_i_5 (joined + (net N_53_i_5 (joined (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_5)) (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2)) )) - (net (rename clk_cpu_est_11_0_1_1 "clk.cpu_est_11_0_1[1]") (joined - (portRef O (instanceRef clk_cpu_est_11_0_0_1_1)) - (portRef I0 (instanceRef clk_cpu_est_11_0_0_1)) + (net (rename cpu_est_ns_0_1_1 "cpu_est_ns_0_1[1]") (joined + (portRef O (instanceRef cpu_est_ns_0_0_1_1)) + (portRef I0 (instanceRef cpu_est_ns_0_0_1)) )) - (net (rename clk_cpu_est_11_0_2_1 "clk.cpu_est_11_0_2[1]") (joined - (portRef O (instanceRef clk_cpu_est_11_0_0_2_1)) - (portRef I1 (instanceRef clk_cpu_est_11_0_0_1)) + (net (rename cpu_est_ns_0_2_1 "cpu_est_ns_0_2[1]") (joined + (portRef O (instanceRef cpu_est_ns_0_0_2_1)) + (portRef I1 (instanceRef cpu_est_ns_0_0_1)) )) - (net N_120_1 (joined - (portRef O (instanceRef un1_bg_030_i_a3_1)) - (portRef I0 (instanceRef un1_bg_030_i_a3)) + (net (rename state_machine_un10_bg_030_1 "state_machine.un10_bg_030_1") (joined + (portRef O (instanceRef state_machine_un10_bg_030_0_a3_1)) + (portRef I0 (instanceRef state_machine_un10_bg_030_0_a3_3)) )) - (net N_120_2 (joined - (portRef O (instanceRef un1_bg_030_i_a3_2)) - (portRef I1 (instanceRef un1_bg_030_i_a3)) + (net (rename state_machine_un10_bg_030_2 "state_machine.un10_bg_030_2") (joined + (portRef O (instanceRef state_machine_un10_bg_030_0_a3_2)) + (portRef I1 (instanceRef state_machine_un10_bg_030_0_a3_3)) )) - (net N_79_1 (joined + (net (rename state_machine_un10_bg_030_3 "state_machine.un10_bg_030_3") (joined + (portRef O (instanceRef state_machine_un10_bg_030_0_a3_3)) + (portRef I0 (instanceRef state_machine_un10_bg_030_0_a3)) + )) + (net N_73_1 (joined (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a3_1)) (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a3)) )) - (net N_79_2 (joined + (net N_73_2 (joined (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a3_2)) (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a3)) )) - (net N_77_1_0 (joined + (net N_72_1 (joined (portRef O (instanceRef DTACK_SYNC_1_sqmuxa_1_i_a3_1)) (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa_1_i_a3)) )) - (net N_75_1 (joined - (portRef O (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_1)) - (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_4)) - )) - (net N_75_2 (joined - (portRef O (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_2_0)) - (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_4)) - )) - (net N_75_3 (joined - (portRef O (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_3)) - (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_5)) - )) - (net N_75_4 (joined - (portRef O (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_4)) - (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3)) - )) - (net N_75_5 (joined - (portRef O (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_5)) - (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3)) - )) - (net N_73_1 (joined - (portRef O (instanceRef state_machine_un15_clk_000_d0_0_a3_0_1)) - (portRef I0 (instanceRef state_machine_un15_clk_000_d0_0_a3_0)) - )) - (net N_73_2 (joined - (portRef O (instanceRef state_machine_un15_clk_000_d0_0_a3_0_2)) - (portRef I1 (instanceRef state_machine_un15_clk_000_d0_0_a3_0)) - )) - (net N_72_1 (joined - (portRef O (instanceRef state_machine_un15_clk_000_d0_0_a3_1)) - (portRef I0 (instanceRef state_machine_un15_clk_000_d0_0_a3)) - )) (net N_72_2 (joined - (portRef O (instanceRef state_machine_un15_clk_000_d0_0_a3_2)) - (portRef I1 (instanceRef state_machine_un15_clk_000_d0_0_a3)) + (portRef O (instanceRef DTACK_SYNC_1_sqmuxa_1_i_a3_2)) + (portRef I1 (instanceRef DTACK_SYNC_1_sqmuxa_1_i_a3)) + )) + (net N_70_1 (joined + (portRef O (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_1)) + (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_3)) + )) + (net N_70_2 (joined + (portRef O (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_2)) + (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_3)) + )) + (net N_70_3 (joined + (portRef O (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_3)) + (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3)) )) (net (rename SM_AMIGA_ns_0_1_0 "SM_AMIGA_ns_0_1[0]") (joined (portRef O (instanceRef SM_AMIGA_ns_0_1_0)) (portRef I0 (instanceRef SM_AMIGA_ns_0_0)) )) - (net (rename clk_cpu_est_11_0_1_3 "clk.cpu_est_11_0_1[3]") (joined - (portRef O (instanceRef clk_cpu_est_11_0_0_1_3)) - (portRef I0 (instanceRef clk_cpu_est_11_0_0_3)) + (net (rename cpu_est_ns_0_1_2 "cpu_est_ns_0_1[2]") (joined + (portRef O (instanceRef cpu_est_ns_0_0_1_2)) + (portRef I0 (instanceRef cpu_est_ns_0_0_2)) )) - (net N_138_1 (joined - (portRef O (instanceRef clk_cpu_est_11_0_0_a3_1_1_3)) - (portRef I0 (instanceRef clk_cpu_est_11_0_0_a3_1_3)) - )) - (net N_119_1 (joined + (net N_221_1 (joined (portRef O (instanceRef state_machine_AMIGA_BUS_ENABLE_3_f0_i_a3_1)) (portRef I0 (instanceRef state_machine_AMIGA_BUS_ENABLE_3_f0_i_a3)) )) - (net N_118_1 (joined - (portRef O (instanceRef clk_cpu_est_11_i_0_a3_0_1_2)) - (portRef I0 (instanceRef clk_cpu_est_11_i_0_a3_0_2)) + (net N_215_1 (joined + (portRef O (instanceRef SM_AMIGA_ns_0_a3_0_1_7)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_a3_0_7)) )) - (net N_117_1 (joined - (portRef O (instanceRef clk_cpu_est_11_i_0_a3_1_2)) - (portRef I0 (instanceRef clk_cpu_est_11_i_0_a3_2)) - )) - (net N_97_1 (joined - (portRef O (instanceRef SM_AMIGA_ns_0_a3_0_1_5)) - (portRef I0 (instanceRef SM_AMIGA_ns_0_a3_0_5)) - )) - (net N_81_1 (joined + (net N_75_1 (joined (portRef O (instanceRef state_machine_LDS_000_INT_5_0_a3_1)) (portRef I0 (instanceRef state_machine_LDS_000_INT_5_0_a3)) )) + (net N_69_1 (joined + (portRef O (instanceRef state_machine_un15_clk_000_d0_0_a3_0_1)) + (portRef I0 (instanceRef state_machine_un15_clk_000_d0_0_a3_0)) + )) + (net N_68_1 (joined + (portRef O (instanceRef state_machine_un15_clk_000_d0_0_a3_1)) + (portRef I0 (instanceRef state_machine_un15_clk_000_d0_0_a3)) + )) (net (rename state_machine_UDS_000_INT_5_0_m2_un3 "state_machine.UDS_000_INT_5_0_m2.un3") (joined (portRef O (instanceRef state_machine_UDS_000_INT_5_0_m2_r)) (portRef I1 (instanceRef state_machine_UDS_000_INT_5_0_m2_n)) @@ -2494,42 +2410,6 @@ (portRef O (instanceRef state_machine_UDS_000_INT_5_0_m2_n)) (portRef I1 (instanceRef state_machine_UDS_000_INT_5_0_m2_p)) )) - (net (rename VPA_SYNC_0_un3 "VPA_SYNC_0.un3") (joined - (portRef O (instanceRef VPA_SYNC_0_r)) - (portRef I1 (instanceRef VPA_SYNC_0_n)) - )) - (net (rename VPA_SYNC_0_un1 "VPA_SYNC_0.un1") (joined - (portRef O (instanceRef VPA_SYNC_0_m)) - (portRef I0 (instanceRef VPA_SYNC_0_p)) - )) - (net (rename VPA_SYNC_0_un0 "VPA_SYNC_0.un0") (joined - (portRef O (instanceRef VPA_SYNC_0_n)) - (portRef I1 (instanceRef VPA_SYNC_0_p)) - )) - (net (rename AMIGA_BUS_ENABLE_0_un3 "AMIGA_BUS_ENABLE_0.un3") (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_0_r)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_0_n)) - )) - (net (rename AMIGA_BUS_ENABLE_0_un1 "AMIGA_BUS_ENABLE_0.un1") (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_0_m)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_0_p)) - )) - (net (rename AMIGA_BUS_ENABLE_0_un0 "AMIGA_BUS_ENABLE_0.un0") (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_0_n)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_0_p)) - )) - (net (rename UDS_000_INT_0_un3 "UDS_000_INT_0.un3") (joined - (portRef O (instanceRef UDS_000_INT_0_r)) - (portRef I1 (instanceRef UDS_000_INT_0_n)) - )) - (net (rename UDS_000_INT_0_un1 "UDS_000_INT_0.un1") (joined - (portRef O (instanceRef UDS_000_INT_0_m)) - (portRef I0 (instanceRef UDS_000_INT_0_p)) - )) - (net (rename UDS_000_INT_0_un0 "UDS_000_INT_0.un0") (joined - (portRef O (instanceRef UDS_000_INT_0_n)) - (portRef I1 (instanceRef UDS_000_INT_0_p)) - )) (net (rename LDS_000_INT_0_un3 "LDS_000_INT_0.un3") (joined (portRef O (instanceRef LDS_000_INT_0_r)) (portRef I1 (instanceRef LDS_000_INT_0_n)) @@ -2542,6 +2422,18 @@ (portRef O (instanceRef LDS_000_INT_0_n)) (portRef I1 (instanceRef LDS_000_INT_0_p)) )) + (net (rename VPA_SYNC_0_un3 "VPA_SYNC_0.un3") (joined + (portRef O (instanceRef VPA_SYNC_0_r)) + (portRef I1 (instanceRef VPA_SYNC_0_n)) + )) + (net (rename VPA_SYNC_0_un1 "VPA_SYNC_0.un1") (joined + (portRef O (instanceRef VPA_SYNC_0_m)) + (portRef I0 (instanceRef VPA_SYNC_0_p)) + )) + (net (rename VPA_SYNC_0_un0 "VPA_SYNC_0.un0") (joined + (portRef O (instanceRef VPA_SYNC_0_n)) + (portRef I1 (instanceRef VPA_SYNC_0_p)) + )) (net (rename VMA_INT_0_un3 "VMA_INT_0.un3") (joined (portRef O (instanceRef VMA_INT_0_r)) (portRef I1 (instanceRef VMA_INT_0_n)) @@ -2554,18 +2446,6 @@ (portRef O (instanceRef VMA_INT_0_n)) (portRef I1 (instanceRef VMA_INT_0_p)) )) - (net (rename BG_000_0_un3 "BG_000_0.un3") (joined - (portRef O (instanceRef BG_000_0_r)) - (portRef I1 (instanceRef BG_000_0_n)) - )) - (net (rename BG_000_0_un1 "BG_000_0.un1") (joined - (portRef O (instanceRef BG_000_0_m)) - (portRef I0 (instanceRef BG_000_0_p)) - )) - (net (rename BG_000_0_un0 "BG_000_0.un0") (joined - (portRef O (instanceRef BG_000_0_n)) - (portRef I1 (instanceRef BG_000_0_p)) - )) (net (rename BGACK_030_INT_0_un3 "BGACK_030_INT_0.un3") (joined (portRef O (instanceRef BGACK_030_INT_0_r)) (portRef I1 (instanceRef BGACK_030_INT_0_n)) @@ -2590,42 +2470,6 @@ (portRef O (instanceRef AS_000_INT_0_n)) (portRef I1 (instanceRef AS_000_INT_0_p)) )) - (net (rename cpu_est_0_1__un3 "cpu_est_0_1_.un3") (joined - (portRef O (instanceRef cpu_est_0_1__r)) - (portRef I1 (instanceRef cpu_est_0_1__n)) - )) - (net (rename cpu_est_0_1__un1 "cpu_est_0_1_.un1") (joined - (portRef O (instanceRef cpu_est_0_1__m)) - (portRef I0 (instanceRef cpu_est_0_1__p)) - )) - (net (rename cpu_est_0_1__un0 "cpu_est_0_1_.un0") (joined - (portRef O (instanceRef cpu_est_0_1__n)) - (portRef I1 (instanceRef cpu_est_0_1__p)) - )) - (net (rename cpu_est_0_2__un3 "cpu_est_0_2_.un3") (joined - (portRef O (instanceRef cpu_est_0_2__r)) - (portRef I1 (instanceRef cpu_est_0_2__n)) - )) - (net (rename cpu_est_0_2__un1 "cpu_est_0_2_.un1") (joined - (portRef O (instanceRef cpu_est_0_2__m)) - (portRef I0 (instanceRef cpu_est_0_2__p)) - )) - (net (rename cpu_est_0_2__un0 "cpu_est_0_2_.un0") (joined - (portRef O (instanceRef cpu_est_0_2__n)) - (portRef I1 (instanceRef cpu_est_0_2__p)) - )) - (net (rename cpu_est_0_3__un3 "cpu_est_0_3_.un3") (joined - (portRef O (instanceRef cpu_est_0_3__r)) - (portRef I1 (instanceRef cpu_est_0_3__n)) - )) - (net (rename cpu_est_0_3__un1 "cpu_est_0_3_.un1") (joined - (portRef O (instanceRef cpu_est_0_3__m)) - (portRef I0 (instanceRef cpu_est_0_3__p)) - )) - (net (rename cpu_est_0_3__un0 "cpu_est_0_3_.un0") (joined - (portRef O (instanceRef cpu_est_0_3__n)) - (portRef I1 (instanceRef cpu_est_0_3__p)) - )) (net (rename IPL_030_0_0__un3 "IPL_030_0_0_.un3") (joined (portRef O (instanceRef IPL_030_0_0__r)) (portRef I1 (instanceRef IPL_030_0_0__n)) @@ -2662,6 +2506,42 @@ (portRef O (instanceRef IPL_030_0_2__n)) (portRef I1 (instanceRef IPL_030_0_2__p)) )) + (net (rename cpu_estse_0_un3 "cpu_estse_0.un3") (joined + (portRef O (instanceRef cpu_estse_0_r)) + (portRef I1 (instanceRef cpu_estse_0_n)) + )) + (net (rename cpu_estse_0_un1 "cpu_estse_0.un1") (joined + (portRef O (instanceRef cpu_estse_0_m)) + (portRef I0 (instanceRef cpu_estse_0_p)) + )) + (net (rename cpu_estse_0_un0 "cpu_estse_0.un0") (joined + (portRef O (instanceRef cpu_estse_0_n)) + (portRef I1 (instanceRef cpu_estse_0_p)) + )) + (net (rename cpu_estse_1_un3 "cpu_estse_1.un3") (joined + (portRef O (instanceRef cpu_estse_1_r)) + (portRef I1 (instanceRef cpu_estse_1_n)) + )) + (net (rename cpu_estse_1_un1 "cpu_estse_1.un1") (joined + (portRef O (instanceRef cpu_estse_1_m)) + (portRef I0 (instanceRef cpu_estse_1_p)) + )) + (net (rename cpu_estse_1_un0 "cpu_estse_1.un0") (joined + (portRef O (instanceRef cpu_estse_1_n)) + (portRef I1 (instanceRef cpu_estse_1_p)) + )) + (net (rename cpu_estse_2_un3 "cpu_estse_2.un3") (joined + (portRef O (instanceRef cpu_estse_2_r)) + (portRef I1 (instanceRef cpu_estse_2_n)) + )) + (net (rename cpu_estse_2_un1 "cpu_estse_2.un1") (joined + (portRef O (instanceRef cpu_estse_2_m)) + (portRef I0 (instanceRef cpu_estse_2_p)) + )) + (net (rename cpu_estse_2_un0 "cpu_estse_2.un0") (joined + (portRef O (instanceRef cpu_estse_2_n)) + (portRef I1 (instanceRef cpu_estse_2_p)) + )) (net (rename AS_030_000_SYNC_0_un3 "AS_030_000_SYNC_0.un3") (joined (portRef O (instanceRef AS_030_000_SYNC_0_r)) (portRef I1 (instanceRef AS_030_000_SYNC_0_n)) @@ -2710,6 +2590,30 @@ (portRef O (instanceRef DSACK_INT_0_1__n)) (portRef I1 (instanceRef DSACK_INT_0_1__p)) )) + (net (rename AMIGA_BUS_ENABLE_0_un3 "AMIGA_BUS_ENABLE_0.un3") (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_0_r)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_0_n)) + )) + (net (rename AMIGA_BUS_ENABLE_0_un1 "AMIGA_BUS_ENABLE_0.un1") (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_0_m)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_0_p)) + )) + (net (rename AMIGA_BUS_ENABLE_0_un0 "AMIGA_BUS_ENABLE_0.un0") (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_0_n)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_0_p)) + )) + (net (rename UDS_000_INT_0_un3 "UDS_000_INT_0.un3") (joined + (portRef O (instanceRef UDS_000_INT_0_r)) + (portRef I1 (instanceRef UDS_000_INT_0_n)) + )) + (net (rename UDS_000_INT_0_un1 "UDS_000_INT_0.un1") (joined + (portRef O (instanceRef UDS_000_INT_0_m)) + (portRef I0 (instanceRef UDS_000_INT_0_p)) + )) + (net (rename UDS_000_INT_0_un0 "UDS_000_INT_0.un0") (joined + (portRef O (instanceRef UDS_000_INT_0_n)) + (portRef I1 (instanceRef UDS_000_INT_0_p)) + )) ) (property orig_inst_of (string "BUS68030")) ) diff --git a/Logic/BUS68030.fse b/Logic/BUS68030.fse index 98498ff..e25682f 100644 --- a/Logic/BUS68030.fse +++ b/Logic/BUS68030.fse @@ -1,20 +1,46 @@ -fsm_encoding {718521851} onehot +fsm_encoding {722122211} onehot -fsm_state_encoding {718521851} idle_p {00000001} +fsm_state_encoding {722122211} idle_p {00000001} -fsm_state_encoding {718521851} idle_n {00000010} +fsm_state_encoding {722122211} idle_n {00000010} -fsm_state_encoding {718521851} as_set_p {00000100} +fsm_state_encoding {722122211} as_set_p {00000100} -fsm_state_encoding {718521851} as_set_n {00001000} +fsm_state_encoding {722122211} as_set_n {00001000} -fsm_state_encoding {718521851} sample_dtack_p {00010000} +fsm_state_encoding {722122211} sample_dtack_p {00010000} -fsm_state_encoding {718521851} data_fetch_n {00100000} +fsm_state_encoding {722122211} data_fetch_n {00100000} -fsm_state_encoding {718521851} data_fetch_p {01000000} +fsm_state_encoding {722122211} data_fetch_p {01000000} -fsm_state_encoding {718521851} end_cycle_n {10000000} +fsm_state_encoding {722122211} end_cycle_n {10000000} -fsm_registers {718521851} {SM_AMIGA[0]} {SM_AMIGA[1]} {SM_AMIGA[2]} {SM_AMIGA[3]} {SM_AMIGA[4]} {SM_AMIGA[5]} {SM_AMIGA[6]} {SM_AMIGA[7]} +fsm_registers {722122211} {SM_AMIGA[0]} {SM_AMIGA[1]} {SM_AMIGA[2]} {SM_AMIGA[3]} {SM_AMIGA[4]} {SM_AMIGA[5]} {SM_AMIGA[6]} {SM_AMIGA[7]} + +fsm_encoding {7112311122} original + +fsm_state_encoding {7112311122} e20 {0000} + +fsm_state_encoding {7112311122} e5 {0010} + +fsm_state_encoding {7112311122} e6 {0011} + +fsm_state_encoding {7112311122} e3 {0100} + +fsm_state_encoding {7112311122} e4 {0101} + +fsm_state_encoding {7112311122} e1 {0110} + +fsm_state_encoding {7112311122} e2 {0111} + +fsm_state_encoding {7112311122} e7 {1010} + +fsm_state_encoding {7112311122} e8 {1011} + +fsm_state_encoding {7112311122} e9 {1100} + +fsm_state_encoding {7112311122} e10 {1111} + +fsm_registers {7112311122} {cpu_est[3]} {cpu_est[2]} {cpu_est[1]} {cpu_est[0]} diff --git a/Logic/BUS68030.prj b/Logic/BUS68030.prj index 16f102d..35ddabb 100644 --- a/Logic/BUS68030.prj +++ b/Logic/BUS68030.prj @@ -1,6 +1,6 @@ #-- Lattice Semiconductor Corporation Ltd. #-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj -#-- Written on Sat May 24 11:44:02 2014 +#-- Written on Sat May 24 15:48:43 2014 #device options diff --git a/Logic/BUS68030.srm b/Logic/BUS68030.srm index 51c64d4..3a14dfd 100644 --- a/Logic/BUS68030.srm +++ b/Logic/BUS68030.srm @@ -33,8 +33,8 @@ af .is_vhdl 1; af .child_list "-1"; af .parent_list "-1"; VNAME 'mach.MACH_DFF.prim'; # view id 0 -VNAME 'mach.DFFSH.prim'; # view id 1 -VNAME 'mach.DFFRH.prim'; # view id 2 +VNAME 'mach.DFFRH.prim'; # view id 1 +VNAME 'mach.DFFSH.prim'; # view id 2 VNAME 'mach.DFF.prim'; # view id 3 VNAME 'mach.IBUF.prim'; # view id 4 VNAME 'mach.BUFTH.prim'; # view id 5 @@ -44,9 +44,7 @@ VNAME 'mach.AND2.prim'; # view id 8 VNAME 'mach.INV.prim'; # view id 9 VNAME 'mach.OR2.prim'; # view id 10 VNAME 'mach.XOR2.prim'; # view id 11 -VNAME 'mach.MACH_LATCH.prim'; # view id 12 -VNAME 'mach.DLATRH.prim'; # view id 13 -VNAME 'work.BUS68030.behavioral'; # view id 14 +VNAME 'work.BUS68030.behavioral'; # view id 12 @ERMRlENORBvq]w_7wsRbH l;N3ORCV8HMCF8V;R4 RNP3#8H#PFDCRlC4N; @@ -67,44 +65,44 @@ bfjj:RPHMR4kMR4kMR );bjRf:0jRsRkC0CskRBeB;R bfjj:RDVN#VCRNCD#R7th;R bfjj:RV8VsT#RR7TRRiBpR4kMRjkM;R -MROlNEwR7wR1]blsH;P +MROlNEwR7wR)]blsH;P NR#3HblsHR 4;FRRTk;Mj 7HR;R HB;pi -1HR;M +)HR;M oRjkM;M NRN3#PMC_CV0_D#No46R.no; MMRk4N; M#R3N_PCM_C0VoDN#.4R6 -n;sjRf:ljRNROEv]qB_w7wRHbslhRQ1S6 +n;sjRf:ljRNROEv]qB_w7wRHbslhRQ1S4 TM=kj7 S=S7 B=piB -piSe)=BSB -1M=k4h +piSk)=MS4 +1B=eBh SmwaQQ= )t;h7 -fbRjR:jHRMPkRM4kRM41b; +fbRjR:jHRMPkRM4kRM4)b; R:fjjsR0k0CRsRkCe;BB fbRjR:jV#NDCNRVDR#Ct;h7 -RMRlENORw7w)b]Rs;Hl +RMRlENORw7w1b]Rs;Hl RNP3bH#sRHl4F; RkTRM j;H;R7 BHRp -i;H;R) +i;H;R1 RoMk;Mj RNM3P#NCC_M0D_VN4o#Rn.6;M oR4kM;M NRN3#PMC_CV0_D#No46R.ns; -R:fjjNRlOvERq_B]7RwwblsHR1Qh4T +R:fjjNRlOvERq_B]7RwwblsHR1Qh6T S=jkM =S77B SpBi=pSi -)M=k41 -S=BeB +)B=eB1 +S=4kM mShaQQw t)=h -7;bjRf:HjRMkPRMk4RM)4R;R +7;bjRf:HjRMkPRMk4RM14R;R bfjj:Rk0sCsR0keCRB B;bjRf:VjRNCD#RDVN#tCRh 7;MlRRNROE7RwwblsH;P @@ -193,51 +191,8 @@ QHRjH; R;Q4 fbRjR:j0CskRk0sCBReBb; R:fjjNRVDR#CV#NDChRt7b; -R:fjjFRGsmPRRQmRj4RQ;R -MROlNEqRvBp]_q]aBRHbslN; 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+B;b@R@4::44::4..+4:DVN#fCRjR:jV#NDCNRVDR#Ct;h7 +@bR@.U:..4::4..:4d+.v:1_Qqvtjqr:R(9fjj:RFoE#10Rvv_qQrtqj9:(R4h_6_,h4hn,_,4(hU_4,4h_g_,h.hj,_,.4h._.;H NR03sD0C_F;R4 -RNH#_$MV_#lH"8R(64U.64U4 +RNH#_$MV_#lH"8R(4...4..4 ";N3HRs_0DFosHMCNlRv"1_Qqvt;q" RNH3lV#_FVslR#0"_1vqtvQq"Rd;H NR#3VlF_0#"0R1qv_vqQtR;U" @@ -559,62 +538,84 @@ RNH3lV#_L0ND0C#Rj"jjjR4jjjjjjjsjj4R4jjjjsjjjR4jjjj4jjjjs4j4Rjjj4jjjjjs4jjRjjjj4j RNH3lV#_HFsolMNC1R"vv_qQ"tq;H NR#3Vl0_#Ns0CC4oR;H NR03#N_0ClbNbHRMo"RRRjjjjj4jjRR->jjjjj4jj\RMRRjjjj4jjj>R-Rjjjj4jjjR\MRjRjj4jjj-jR>jRjj4jjjMj\RjRRj4jjjRjj-j>Rj4jjj\jjMRRRj4jjjjjjRR->j4jjjjjj\RMRR4jjjjjjj>R-R4jjjjjjjR\MR4Rjjjjjj-jR>4RjjjjjjMj\R4RRjjjjjRjj-4>Rjjjjj\jjM -";s@R@Uj:4g.:6:g4j:+664Qc:ujp_d.jr:Rj9fjj:ROlNEwR7wR1]blsHRpQu_jjd71ww]9rj -=STQ_upj_djO9rj -=S7hU_4 -pSBip=Bi1_mZOQ_ -=S1)_1aHN; -HsR30FD_sMHoNRlC"pQu_jjd"N; -HkR3MNVsOM_H8RCGjs; -RU@@:g4j::6.4:jg646+cu:Qpd_jj:r.jf9RjR:jlENORw7w1b]RsRHlQ_upj7djw]w1r -49SQT=ujp_dOj_r -49Sh7=_ -4gSiBp=iBp_Zm1Q -_OS)1=1Ha_;H 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-4;N3HRFosHH0M#MCNlRv'1_Qqvtjqr:'(9;R -s@:@U.:UjcU:.jj:.+:4c1qv_vqQtr(j:9jRf:ljRNROE7)ww]sRbH1lRvv_qQrtq6S9 -Tv=1_Qqvt6qr97 +4;N3HRFosHH0M#MCNlRb'Ok#_C0:rj4'j9;R +s@:@Ud:6jc6:djc:.+:4.1qv_vqQtr(j:9jRf:ljRNROE7)ww]sRbH1lRvv_qQrtqdS9 +Tv=1_Qqvtdqr97 S=Uh_j _HSiBp=iBp_Zm1Q _OS))=1Ha_;H NR03sD0C_F;R4 -RNH#_$MV_#lH"8R(64U.64U4 +RNH#_$MV_#lH"8R(4...4..4 ";N3HRs_0DFosHMCNlRv"1_Qqvt;q" RNH3lV#_FVslR#0"_1vqtvQq"Rd;H NR#3VlF_0#"0R1qv_vqQtR;U" @@ -622,41 +623,13 @@ RNH3lV#_L0ND0C#Rj"jjjR4jjjjjjjsjj4R4jjjjsjjjR4jjjj4jjjjs4j4Rjjj4jjjjjs4jjRjjjj4j RNH3lV#_HFsolMNC1R"vv_qQ"tq;H NR#3Vl0_#Ns0CC4oR;H NRs3FHMoH#N0Ml'CR1qv_vqQtr(j:9 -';s@R@Ug:.g::c.:gg.4j+cv:1_Qqvtjqr:R(9fjj:ROlNEwR7wR)]blsHR_1vqtvQq9rc -=ST1qv_vqQtr -c9Sh7=__U.HB -SpBi=pmi_1_ZQO) -S=a)1_ -H;N3HRsC0D_R0F4N; -H$R#M#_Vl8_HR4"(U46.U"64;H -NR03sDs_FHNoMl"CR1qv_vqQt"N; -HVR3#Vl_s#Fl01R"vv_qQRtqd -";N3HRV_#l00F#Rv"1_QqvtUqR"N; -HVR3#0l_NCLD#"0RjRjj4jjjjjjjs4jjRjj4jjjjj4sjjjRj4jjjjjjs4j4Rjjj4jsjj4Rjjjjjj4jjjs44jRjjjjjj4j4s4jjRjjjjj44js4j4Rjjjjjsj4"N; -HVR3#Fl_sMHoNRlC"_1vqtvQq -";N3HRV_#l#00NCosCR -4;N3HRFosHH0M#MCNlRv'1_Qqvtjqr:'(9;R -s@:@Ud:46c4:d6c:.+:4c1qv_vqQtr(j:9jRf:ljRNROE7)ww]sRbH1lRvv_qQrtqdS9 -Tv=1_Qqvtdqr97 -S=Uh_c -_HSiBp=iBp_Zm1Q -_OS))=1Ha_;H -NR03sD0C_F;R4 -RNH#_$MV_#lH"8R(64U.64U4 -";N3HRs_0DFosHMCNlRv"1_Qqvt;q" -RNH3lV#_FVslR#0"_1vqtvQq"Rd;H -NR#3VlF_0#"0R1qv_vqQtR;U" -RNH3lV#_L0ND0C#Rj"jjjR4jjjjjjjsjj4R4jjjjsjjjR4jjjj4jjjjs4j4Rjjj4jjjjjs4jjRjjjj4j4jsjj4Rjjjj4sjj4R4jjjjjjjj4s444Rjjjjjjj4;s" -RNH3lV#_HFsolMNC1R"vv_qQ"tq;H -NR#3Vl0_#Ns0CC4oR;H -NRs3FHMoH#N0Ml'CR1qv_vqQtr(j:9 -';s@R@U.:d(::cd:.(.4.+cv:1_Qqvtjqr:R(9fjj:ROlNEwR7wR)]blsHR_1vqtvQq9r. +';s@R@Un:d.::cd:n..4.+.v:1_Qqvtjqr:R(9fjj:ROlNEwR7wR)]blsHR_1vqtvQq9r. =ST1qv_vqQtr .9S17=vv_qQ_tqM6#r9B SpBi=pmi_1_ZQO) S=a)1_ H;N3HRsC0D_R0F4N; -H$R#M#_Vl8_HR4"(U46.U"64;H +H$R#M#_Vl8_HR."(..4.."44;H NR03sDs_FHNoMl"CR1qv_vqQt"N; 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+3lSwm=uBz_1h_Qa3_jk +M4S=Qjqj1_dOj_ +4SQ=.h_j +6;sjRf:ljRNROEq.h7RHbsluRwz1_B_aQh_Mj3 +=Smw_uzBQ1_hja_3jkM +jSQ=zwu__B1Q +haS=Q4w_uzBQ1_hja_3dkM;R +sfjj:ROlNE)Rm.sRbHwlRuBz_1h_Qa3_jbm +S=dh_ +jSQ=zwu__B1Q_hajM3k4Q +S4u=wz1_B_aQh_kj3M +j;sjRf:ljRNROEQRheblsHRq71BQi_hja__34_sm S=q71BQi_hja__34_k -MjS=Qj7B1qih_Qa9r4 -4SQ=q71BQi_hja__34_k;Md -fsRjR:jlENOR.m)RHbsl1R7q_BiQ_haj__43Sb -m_=hcQ -Sj1=7q_BiQ_haj__434kM -4SQ=q71BQi_hja__34_k;Mj -fsRjR:jlENOReQhRHbsl_Rh(H6_ -=Smh6_(_SH -Qhj=_;(6 +MdS=Qjhj_6;R +sfjj:ROlNEhRq7b.RsRHl7B1qih_Qa__j4l_3 +=Sm7B1qih_Qa__j4k_3MS4 +Qhj=_ +66S=Q4hj_6;R +sfjj:ROlNEhRq7b.RsRHl7B1qih_Qa__j4M_3 +=Sm7B1qih_Qa__j4k_3MSj +Q7j=1iqB_aQhr +49S=Q47B1qih_Qa__j4k_3M +d;sjRf:ljRNROEmR).blsHRq71BQi_hja__34_bm +S=ch_ +jSQ=q71BQi_hja__34_k +M4S=Q47B1qih_Qa__j4k_3M +j;sjRf:ljRNROEQRheblsHRQqvtAq_z 1_hpqA 3_jsm +S=QqvtAq_z 1_hpqA 3_jk +MdS=Qj)_1aOs; +R:fjjNRlOqERhR7.blsHRQqvtAq_z 1_hpqA 3_jlm +S=QqvtAq_z 1_hpqA 3_jk +M4S=Qjh4_c_SH +Q)4=1Oa_;R +sfjj:ROlNEhRq7b.RsRHlqtvQqz_A1h_ q Ap_Mj3 +=SmqtvQqz_A1h_ q Ap_kj3MSj +Qqj=vqQt_1Az_q hA_p OQ +S4v=qQ_tqA_z1 Ahqpj _3dkM;R +sfjj:ROlNE)Rm.sRbHqlRvqQt_1Az_q hA_p j +3bShm=_S6 +Qqj=vqQt_1Az_q hA_p jM3k4Q +S4v=qQ_tqA_z1 Ahqpj _3jkM;R +sfjj:ROlNEhRQesRbHzlR7j1_jQj_hja_3Ss +m7=z1j_jjh_Qa3_jk +MdS=Qjhj_.ds; +R:fjjNRlOqERhR7.blsHR1z7_jjj_aQh_lj3 +=Smz_71j_jjQ_hajM3k4Q +Sj0=#N_0ClENOH\MC31z7_jjj_aQh_S6 +Qh4=_d.j;R +sfjj:ROlNEhRq7b.RsRHlz_71j_jjQ_haj +3MSzm=7j1_jQj_hja_3jkM +jSQ=1z7_jjj_aQh +4SQ=1z7_jjj_aQh_kj3M +d;sjRf:ljRNROEmR).blsHR1z7_jjj_aQh_bj3 +=Smh +_nS=Qjz_71j_jjQ_hajM3k4Q +S47=z1j_jjh_Qa3_jk;Mj diff --git a/Logic/BUS68030.srr b/Logic/BUS68030.srr index 1adcd7f..360cf59 100644 --- a/Logic/BUS68030.srr +++ b/Logic/BUS68030.srr @@ -6,7 +6,7 @@ #Implementation: logic $ Start of Compile -#Sat May 24 11:44:03 2014 +#Sat May 24 15:48:43 2014 Synopsys VHDL Compiler, version comp201209rcp1, Build 283R, built Mar 19 2013 @N|Running in 64-bit mode @@ -18,17 +18,15 @@ File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - VHDL syntax check successful! File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling @N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral -@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":112:7:112:15|Signal clk_030_d is undriven +@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":113:7:113:15|Signal clk_030_d is undriven Post processing for work.bus68030.behavioral -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":119:32:119:34|Pruning register cpu_est_d(3 downto 0) -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":118:32:118:34|Pruning register CLK_000_D6 -@A: CL282 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:52:109:55|Feedback mux created for signal AMIGA_BUS_ENABLE -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. -@W: CL111 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":185:2:185:3|All reachable assignments to CLK_REF(0) assign '0'; register removed by optimization -@W: CL117 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":185:2:185:3|Latch generated from process for signal CLK_REF(1 downto 0); possible missing assignment in an if or case statement. -@W: CL190 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:52:109:55|Optimizing register bit DSACK_INT(0) to a constant 1 -@W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:52:109:55|Pruning register bit 0 of DSACK_INT(1 downto 0) -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":119:32:119:34|Trying to extract state machine for register cpu_est -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":185:2:185:3|Trying to extract state machine for register SM_AMIGA +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":221:2:221:3|Pruning register CLK_REF(1 downto 0) +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":119:32:119:34|Pruning register CLK_000_D6 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":112:31:112:33|Pruning register cpu_est_d(3 downto 0) +@A: CL282 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":110:52:110:55|Feedback mux created for signal AMIGA_BUS_ENABLE -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. +@W: CL190 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":110:52:110:55|Optimizing register bit DSACK_INT(0) to a constant 1 +@W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":110:52:110:55|Pruning register bit 0 of DSACK_INT(1 downto 0) +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":221:2:221:3|Trying to extract state machine for register SM_AMIGA Extracted state machine for register SM_AMIGA State machine has 8 reachable states with original encodings of: 000 @@ -39,10 +37,25 @@ State machine has 8 reachable states with original encodings of: 101 110 111 -@W: CL249 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":185:2:185:3|Initial value is not supported on state machine SM_AMIGA +@W: CL249 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":221:2:221:3|Initial value is not supported on state machine SM_AMIGA +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":112:31:112:33|Trying to extract state machine for register cpu_est +Extracted state machine for register cpu_est +State machine has 11 reachable states with original encodings of: + 0000 + 0010 + 0011 + 0100 + 0101 + 0110 + 0111 + 1010 + 1011 + 1100 + 1111 +@W: CL249 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":112:31:112:33|Initial value is not supported on state machine cpu_est @END Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Sat May 24 11:44:03 2014 +# Sat May 24 15:48:43 2014 ###########################################################] Map & Optimize Report @@ -61,23 +74,34 @@ original code -> new code 101 -> 00100000 110 -> 01000000 111 -> 10000000 -@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":154:4:154:7|Found ROM, 'clk\.cpu_est_11[3:0]', 16 words by 4 bits +Encoding state machine cpu_est[0:10] (view:work.BUS68030(behavioral)) +original code -> new code + 0000 -> 0000 + 0010 -> 0010 + 0011 -> 0011 + 0100 -> 0100 + 0101 -> 0101 + 0110 -> 0110 + 0111 -> 0111 + 1010 -> 1010 + 1011 -> 1011 + 1100 -> 1100 + 1111 -> 1111 --------------------------------------- Resource Usage Report Simple gate primitives: -DFFSH 16 uses -DFFRH 7 uses -DFF 17 uses +DFFRH 18 uses +DFFSH 23 uses +DFF 1 use IBUF 35 uses BUFTH 7 uses OBUF 15 uses BI_DIR 2 uses -AND2 159 uses -INV 132 uses -OR2 19 uses -XOR2 3 uses -DLATRH 1 use +AND2 145 uses +INV 129 uses +OR2 18 uses +XOR2 2 uses @N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis. @@ -87,6 +111,6 @@ Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 95MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Sat May 24 11:44:04 2014 +# Sat May 24 15:48:45 2014 ###########################################################] diff --git a/Logic/BUS68030.srs b/Logic/BUS68030.srs index 36d245e..e773b47 100644 Binary files a/Logic/BUS68030.srs and b/Logic/BUS68030.srs differ diff --git a/Logic/bus68030.exf b/Logic/bus68030.exf index 4f19ff2..ba32118 100644 --- a/Logic/bus68030.exf +++ b/Logic/bus68030.exf @@ -55,240 +55,214 @@ Section Member Rename Array-Notation Array Number Port FC_0_ FC[0] 4 1 End Section Cross Reference File -Design 'BUS68030' created Sat May 24 11:44:09 2014 +Design 'BUS68030' created Sat May 24 15:48:50 2014 Type New Name Original Name // ---------------------------------------------------------------------- - Inst i_z2K2K AS_000 - Inst i_z2M2M UDS_000 - Inst i_z2N2N LDS_000 - Inst i_z3C3C BERR - Inst i_z3V3V DTACK - Inst i_z4141 AVEC_EXP - Inst i_z4D4D CIIN - Inst SM_AMIGA_ns_i_i_o2_i_6_ SM_AMIGA_ns_i_i_o2_i[6] - Inst clk_cpu_est_11_0_0_o2_i_1_ clk.cpu_est_11_0_0_o2_i[1] - Inst SM_AMIGA_ns_0_o2_i_7_ SM_AMIGA_ns_0_o2_i[7] - Inst state_machine_AMIGA_BUS_ENABLE_3_f0_i_o2_i state_machine.AMIGA_BUS_ENABLE_3_f0_i_o2_i - Inst clk_cpu_est_11_0_0_i_1_ clk.cpu_est_11_0_0_i[1] - Inst SM_AMIGA_i_3_ SM_AMIGA_i[3] + Inst i_z2M2M AS_000 + Inst i_z2O2O UDS_000 + Inst i_z2P2P LDS_000 + Inst i_z3E3E BERR + Inst i_z4141 DTACK + Inst i_z4343 AVEC_EXP + Inst i_z4F4F CIIN + Inst SM_AMIGA_i_4_ SM_AMIGA_i[4] Inst SM_AMIGA_ns_i_0_o2_4_ SM_AMIGA_ns_i_0_o2[4] - Inst cpu_est_i_1_ cpu_est_i[1] - Inst cpu_est_i_0_ cpu_est_i[0] - Inst cpu_est_i_3_ cpu_est_i[3] + Inst state_machine_AMIGA_BUS_ENABLE_3_f0_i state_machine.AMIGA_BUS_ENABLE_3_f0_i Inst state_machine_UDS_000_INT_5_0_m2_r state_machine.UDS_000_INT_5_0_m2.r Inst state_machine_UDS_000_INT_5_0_m2_m state_machine.UDS_000_INT_5_0_m2.m Inst state_machine_UDS_000_INT_5_0_m2_n state_machine.UDS_000_INT_5_0_m2.n Inst state_machine_UDS_000_INT_5_0_m2_p state_machine.UDS_000_INT_5_0_m2.p - Inst cpu_est_i_2_ cpu_est_i[2] - Inst clk_cpu_est_11_i_0_o2_2_ clk.cpu_est_11_i_0_o2[2] - Inst clk_un4_clk_000_d1_0_o2 clk.un4_clk_000_d1_0_o2 + Inst clk_un3_clk_000_d1_0_o2 clk.un3_clk_000_d1_0_o2 Inst SM_AMIGA_i_6_ SM_AMIGA_i[6] Inst state_machine_AMIGA_BUS_ENABLE_3_f0_i_o2 state_machine.AMIGA_BUS_ENABLE_3_f0_i_o2 - Inst SM_AMIGA_ns_0_o2_7_ SM_AMIGA_ns_0_o2[7] - Inst clk_cpu_est_11_0_0_o2_1_ clk.cpu_est_11_0_0_o2[1] - Inst SM_AMIGA_ns_i_i_o2_6_ SM_AMIGA_ns_i_i_o2[6] - Inst clk_cpu_est_11_0_0_o2_3_ clk.cpu_est_11_0_0_o2[3] + Inst SM_AMIGA_i_1_ SM_AMIGA_i[1] + Inst state_machine_un6_clk_000_d4_i state_machine.un6_clk_000_d4_i + Inst cpu_est_i_3_ cpu_est_i[3] + Inst cpu_est_ns_i_0_o2_3_ cpu_est_ns_i_0_o2[3] Inst state_machine_UDS_000_INT_5_0_o3 state_machine.UDS_000_INT_5_0_o3 - Inst SM_AMIGA_ns_i_0_o2_1_ SM_AMIGA_ns_i_0_o2[1] + Inst state_machine_un15_clk_000_d0_0 state_machine.un15_clk_000_d0_0 Inst state_machine_UDS_000_INT_5_0 state_machine.UDS_000_INT_5_0 - Inst IPL_030DFFSH_0_ IPL_030DFFSH[0] Inst state_machine_LDS_000_INT_5_0 state_machine.LDS_000_INT_5_0 - Inst IPL_030DFFSH_1_ IPL_030DFFSH[1] Inst SM_AMIGA_ns_i_0_1_ SM_AMIGA_ns_i_0[1] - Inst IPL_030DFFSH_2_ IPL_030DFFSH[2] Inst SM_AMIGA_ns_i_0_2_ SM_AMIGA_ns_i_0[2] - Inst SM_AMIGA_7_ SM_AMIGA[7] Inst SM_AMIGA_ns_i_0_3_ SM_AMIGA_ns_i_0[3] - Inst SM_AMIGA_6_ SM_AMIGA[6] Inst SM_AMIGA_ns_i_0_4_ SM_AMIGA_ns_i_0[4] - Inst SM_AMIGA_5_ SM_AMIGA[5] Inst SM_AMIGA_ns_0_5_ SM_AMIGA_ns_0[5] - Inst SM_AMIGA_4_ SM_AMIGA[4] - Inst SM_AMIGA_ns_i_i_6_ SM_AMIGA_ns_i_i[6] - Inst SM_AMIGA_3_ SM_AMIGA[3] + Inst SM_AMIGA_ns_i_0_6_ SM_AMIGA_ns_i_0[6] Inst SM_AMIGA_ns_0_7_ SM_AMIGA_ns_0[7] - Inst SM_AMIGA_2_ SM_AMIGA[2] - Inst clk_cpu_est_11_i_0_2_ clk.cpu_est_11_i_0[2] - Inst SM_AMIGA_1_ SM_AMIGA[1] - Inst state_machine_AMIGA_BUS_ENABLE_3_f0_i state_machine.AMIGA_BUS_ENABLE_3_f0_i - Inst SM_AMIGA_0_ SM_AMIGA[0] - Inst cpu_est_0_0_0_ cpu_est_0_0[0] - Inst CLK_CNT_0_ CLK_CNT[0] - Inst clk_cpu_est_11_0_0_a3_1_ clk.cpu_est_11_0_0_a3[1] - Inst CLK_CNT_1_ CLK_CNT[1] - Inst clk_cpu_est_11_0_0_a3_0_1_ clk.cpu_est_11_0_0_a3_0[1] - Inst cpu_est_0_ cpu_est[0] - Inst clk_cpu_est_11_0_0_a3_1_1_ clk.cpu_est_11_0_0_a3_1[1] - Inst cpu_est_1_ cpu_est[1] - Inst clk_cpu_est_11_0_0_a3_3_ clk.cpu_est_11_0_0_a3[3] + Inst cpu_est_ns_i_0_3_ cpu_est_ns_i_0[3] + Inst cpu_est_ns_0_0_a3_0_2_ cpu_est_ns_0_0_a3_0[2] Inst cpu_est_2_ cpu_est[2] - Inst clk_cpu_est_11_0_0_a3_0_3_ clk.cpu_est_11_0_0_a3_0[3] + Inst cpu_est_ns_0_0_a3_1_2_ cpu_est_ns_0_0_a3_1[2] Inst cpu_est_3_ cpu_est[3] Inst SM_AMIGA_ns_0_a3_0_ SM_AMIGA_ns_0_a3[0] + Inst cpu_est_0_ cpu_est[0] Inst SM_AMIGA_ns_0_a3_0_0_ SM_AMIGA_ns_0_a3_0[0] - Inst cpu_est_0_0_a3_0_ cpu_est_0_0_a3[0] - Inst cpu_est_0_0_a3_0_0_ cpu_est_0_0_a3_0[0] + Inst cpu_est_1_ cpu_est[1] + Inst SM_AMIGA_3_ SM_AMIGA[3] + Inst SM_AMIGA_2_ SM_AMIGA[2] + Inst cpu_est_i_0_ cpu_est_i[0] + Inst SM_AMIGA_1_ SM_AMIGA[1] + Inst cpu_est_ns_0_0_a2_1_ cpu_est_ns_0_0_a2[1] + Inst SM_AMIGA_0_ SM_AMIGA[0] + Inst cpu_est_ns_i_0_a2_3_ cpu_est_ns_i_0_a2[3] + Inst CLK_CNT_N_0_ CLK_CNT_N[0] + Inst cpu_est_i_1_ cpu_est_i[1] + Inst CLK_CNT_N_1_ CLK_CNT_N[1] + Inst cpu_est_ns_0_0_a2_0_1_ cpu_est_ns_0_0_a2_0[1] + Inst CLK_CNT_P_0_ CLK_CNT_P[0] Inst SM_AMIGA_ns_0_a2_0_ SM_AMIGA_ns_0_a2[0] - Inst clk_cpu_est_11_0_0_a2_1_ clk.cpu_est_11_0_0_a2[1] + Inst CLK_CNT_P_1_ CLK_CNT_P[1] + Inst SM_AMIGA_ns_i_0_a2_4_ SM_AMIGA_ns_i_0_a2[4] + Inst IPL_030DFFSH_0_ IPL_030DFFSH[0] Inst state_machine_un6_bgack_000_0 state_machine.un6_bgack_000_0 - Inst state_machine_un15_clk_000_d0_0 state_machine.un15_clk_000_d0_0 - Inst state_machine_un8_clk_000_d2_i state_machine.un8_clk_000_d2_i + Inst IPL_030DFFSH_1_ IPL_030DFFSH[1] + Inst IPL_030DFFSH_2_ IPL_030DFFSH[2] + Inst SM_AMIGA_i_3_ SM_AMIGA_i[3] + Inst SM_AMIGA_7_ SM_AMIGA[7] + Inst SM_AMIGA_ns_i_0_a3_4_ SM_AMIGA_ns_i_0_a3[4] + Inst SM_AMIGA_6_ SM_AMIGA[6] + Inst SM_AMIGA_ns_0_a3_5_ SM_AMIGA_ns_0_a3[5] + Inst SM_AMIGA_5_ SM_AMIGA[5] + Inst SM_AMIGA_ns_0_a3_0_5_ SM_AMIGA_ns_0_a3_0[5] + Inst SM_AMIGA_4_ SM_AMIGA[4] + Inst SM_AMIGA_ns_i_0_a3_6_ SM_AMIGA_ns_i_0_a3[6] + Inst SM_AMIGA_i_2_ SM_AMIGA_i[2] + Inst SM_AMIGA_ns_i_0_a3_0_6_ SM_AMIGA_ns_i_0_a3_0[6] + Inst SM_AMIGA_ns_0_a3_7_ SM_AMIGA_ns_0_a3[7] + Inst cpu_est_ns_0_0_a3_1_ cpu_est_ns_0_0_a3[1] + Inst cpu_est_i_2_ cpu_est_i[2] + Inst cpu_est_ns_0_0_a3_0_1_ cpu_est_ns_0_0_a3_0[1] + Inst cpu_est_ns_i_0_a3_3_ cpu_est_ns_i_0_a3[3] + Inst cpu_est_ns_0_0_a3_2_ cpu_est_ns_0_0_a3[2] Inst DSACK_INT_1_ DSACK_INT[1] + Inst state_machine_un7_as_000_int_0_a3 state_machine.un7_as_000_int_0_a3 + Inst A_i_0_ A_i[0] + Inst SIZE_i_1_ SIZE_i[1] + Inst SM_AMIGA_i_7_ SM_AMIGA_i[7] + Inst SM_AMIGA_ns_i_0_a3_1_ SM_AMIGA_ns_i_0_a3[1] + Inst state_machine_un8_clk_000_d2_i state_machine.un8_clk_000_d2_i Inst SM_AMIGA_ns_i_0_a3_0_1_ SM_AMIGA_ns_i_0_a3_0[1] Inst SM_AMIGA_ns_i_0_a3_2_ SM_AMIGA_ns_i_0_a3[2] Inst SM_AMIGA_i_5_ SM_AMIGA_i[5] Inst SM_AMIGA_ns_i_0_a3_3_ SM_AMIGA_ns_i_0_a3[3] - Inst SM_AMIGA_ns_i_0_a3_4_ SM_AMIGA_ns_i_0_a3[4] - Inst SM_AMIGA_i_4_ SM_AMIGA_i[4] - Inst SM_AMIGA_ns_i_0_a3_0_4_ SM_AMIGA_ns_i_0_a3_0[4] - Inst SM_AMIGA_ns_0_a3_5_ SM_AMIGA_ns_0_a3[5] - Inst SM_AMIGA_ns_i_i_a3_6_ SM_AMIGA_ns_i_i_a3[6] - Inst SM_AMIGA_ns_i_i_a3_0_6_ SM_AMIGA_ns_i_i_a3_0[6] - Inst SM_AMIGA_ns_0_a3_7_ SM_AMIGA_ns_0_a3[7] - Inst SM_AMIGA_ns_0_a3_0_7_ SM_AMIGA_ns_0_a3_0[7] - Inst clk_clk_cnt_i clk.clk_cnt_i - Inst clk_CLK_CNT_3_1_ clk.CLK_CNT_3[1] - Inst SIZE_0_ SIZE[0] - Inst SIZE_1_ SIZE[1] - Inst state_machine_un1_clk_030_i_a3 state_machine.un1_clk_030_i_a3 - Inst A_0_ A[0] - Inst A_16_ A[16] - Inst A_17_ A[17] - Inst state_machine_un7_as_000_int_0_a3 state_machine.un7_as_000_int_0_a3 - Inst A_18_ A[18] - Inst A_19_ A[19] - Inst A_20_ A[20] - Inst A_i_0_ A_i[0] - Inst A_21_ A[21] - Inst SIZE_i_1_ SIZE_i[1] - Inst A_22_ A[22] - Inst SM_AMIGA_i_7_ SM_AMIGA_i[7] - Inst A_23_ A[23] - Inst SM_AMIGA_ns_i_0_a3_1_ SM_AMIGA_ns_i_0_a3[1] - Inst A_24_ A[24] Inst A_i_16_ A_i[16] - Inst A_25_ A[25] Inst A_i_18_ A_i[18] - Inst A_26_ A[26] + Inst SIZE_0_ SIZE[0] Inst A_i_19_ A_i[19] - Inst A_27_ A[27] + Inst SIZE_1_ SIZE[1] Inst A_i_24_ A_i[24] - Inst A_28_ A[28] + Inst A_0_ A[0] Inst A_i_25_ A_i[25] - Inst A_29_ A[29] + Inst A_16_ A[16] Inst A_i_26_ A_i[26] - Inst A_30_ A[30] + Inst A_17_ A[17] Inst A_i_27_ A_i[27] - Inst A_31_ A[31] + Inst A_18_ A[18] Inst A_i_28_ A_i[28] + Inst A_19_ A[19] Inst A_i_29_ A_i[29] + Inst A_20_ A[20] Inst A_i_30_ A_i[30] + Inst A_21_ A[21] Inst A_i_31_ A_i[31] - Inst CLK_CNT_i_0_ CLK_CNT_i[0] - Inst clk_CLK_CNT_3_0_ clk.CLK_CNT_3[0] + Inst A_22_ A[22] + Inst A_23_ A[23] + Inst A_24_ A[24] Inst state_machine_un7_as_000_int_i state_machine.un7_as_000_int_i - Inst VPA_SYNC_0_r VPA_SYNC_0.r - Inst IPL_030_0_ IPL_030[0] - Inst VPA_SYNC_0_m VPA_SYNC_0.m - Inst IPL_030_1_ IPL_030[1] - Inst VPA_SYNC_0_n VPA_SYNC_0.n - Inst IPL_030_2_ IPL_030[2] - Inst VPA_SYNC_0_p VPA_SYNC_0.p - Inst IPL_0_ IPL[0] - Inst AMIGA_BUS_ENABLE_0_r AMIGA_BUS_ENABLE_0.r - Inst IPL_1_ IPL[1] - Inst AMIGA_BUS_ENABLE_0_m AMIGA_BUS_ENABLE_0.m - Inst IPL_2_ IPL[2] - Inst AMIGA_BUS_ENABLE_0_n AMIGA_BUS_ENABLE_0.n - Inst DSACK_0_ DSACK[0] - Inst AMIGA_BUS_ENABLE_0_p AMIGA_BUS_ENABLE_0.p - Inst DSACK_1_ DSACK[1] - Inst UDS_000_INT_0_r UDS_000_INT_0.r - Inst UDS_000_INT_0_m UDS_000_INT_0.m - Inst UDS_000_INT_0_n UDS_000_INT_0.n - Inst UDS_000_INT_0_p UDS_000_INT_0.p + Inst A_25_ A[25] + Inst state_machine_un10_bg_030_i state_machine.un10_bg_030_i + Inst A_26_ A[26] + Inst un4_clk_cnt_n_i_1_ un4_clk_cnt_n_i[1] + Inst A_27_ A[27] + Inst A_28_ A[28] + Inst un2_clk_cnt_p_i_1_ un2_clk_cnt_p_i[1] + Inst A_29_ A[29] Inst LDS_000_INT_0_r LDS_000_INT_0.r + Inst A_30_ A[30] Inst LDS_000_INT_0_m LDS_000_INT_0.m + Inst A_31_ A[31] Inst LDS_000_INT_0_n LDS_000_INT_0.n Inst LDS_000_INT_0_p LDS_000_INT_0.p + Inst VPA_SYNC_0_r VPA_SYNC_0.r + Inst VPA_SYNC_0_m VPA_SYNC_0.m + Inst VPA_SYNC_0_n VPA_SYNC_0.n + Inst VPA_SYNC_0_p VPA_SYNC_0.p Inst VMA_INT_0_r VMA_INT_0.r Inst VMA_INT_0_m VMA_INT_0.m - Inst FC_0_ FC[0] Inst VMA_INT_0_n VMA_INT_0.n - Inst FC_1_ FC[1] Inst VMA_INT_0_p VMA_INT_0.p - Inst BG_000_0_r BG_000_0.r - Inst BG_000_0_m BG_000_0.m - Inst BG_000_0_n BG_000_0.n - Inst clk_cpu_est_11_0_0_1_3_ clk.cpu_est_11_0_0_1[3] - Inst BG_000_0_p BG_000_0.p - Inst clk_cpu_est_11_0_0_3_ clk.cpu_est_11_0_0[3] Inst BGACK_030_INT_0_r BGACK_030_INT_0.r - Inst clk_cpu_est_11_0_0_a3_1_1_3_ clk.cpu_est_11_0_0_a3_1_1[3] Inst BGACK_030_INT_0_m BGACK_030_INT_0.m - Inst clk_cpu_est_11_0_0_a3_1_3_ clk.cpu_est_11_0_0_a3_1[3] + Inst IPL_030_0_ IPL_030[0] Inst BGACK_030_INT_0_n BGACK_030_INT_0.n - Inst state_machine_AMIGA_BUS_ENABLE_3_f0_i_a3_1 state_machine.AMIGA_BUS_ENABLE_3_f0_i_a3_1 + Inst IPL_030_1_ IPL_030[1] Inst BGACK_030_INT_0_p BGACK_030_INT_0.p - Inst state_machine_AMIGA_BUS_ENABLE_3_f0_i_a3 state_machine.AMIGA_BUS_ENABLE_3_f0_i_a3 + Inst IPL_030_2_ IPL_030[2] Inst AS_000_INT_0_r AS_000_INT_0.r - Inst clk_cpu_est_11_i_0_a3_0_1_2_ clk.cpu_est_11_i_0_a3_0_1[2] + Inst IPL_0_ IPL[0] Inst AS_000_INT_0_m AS_000_INT_0.m - Inst clk_cpu_est_11_i_0_a3_0_2_ clk.cpu_est_11_i_0_a3_0[2] + Inst IPL_1_ IPL[1] Inst AS_000_INT_0_n AS_000_INT_0.n - Inst clk_cpu_est_11_i_0_a3_1_2_ clk.cpu_est_11_i_0_a3_1[2] + Inst IPL_2_ IPL[2] Inst AS_000_INT_0_p AS_000_INT_0.p - Inst clk_cpu_est_11_i_0_a3_2_ clk.cpu_est_11_i_0_a3[2] - Inst cpu_est_0_1__r cpu_est_0_1_.r - Inst SM_AMIGA_ns_0_a3_0_1_5_ SM_AMIGA_ns_0_a3_0_1[5] - Inst cpu_est_0_1__m cpu_est_0_1_.m - Inst SM_AMIGA_ns_0_a3_0_5_ SM_AMIGA_ns_0_a3_0[5] - Inst cpu_est_0_1__n cpu_est_0_1_.n - Inst state_machine_LDS_000_INT_5_0_a3_1 state_machine.LDS_000_INT_5_0_a3_1 - Inst cpu_est_0_1__p cpu_est_0_1_.p - Inst state_machine_LDS_000_INT_5_0_a3 state_machine.LDS_000_INT_5_0_a3 - Inst cpu_est_0_2__r cpu_est_0_2_.r - Inst cpu_est_0_2__m cpu_est_0_2_.m - Inst cpu_est_0_2__n cpu_est_0_2_.n - Inst cpu_est_0_2__p cpu_est_0_2_.p - Inst cpu_est_0_3__r cpu_est_0_3_.r - Inst cpu_est_0_3__m cpu_est_0_3_.m - Inst cpu_est_0_3__n cpu_est_0_3_.n - Inst cpu_est_0_3__p cpu_est_0_3_.p - Inst state_machine_un15_clk_000_d0_0_a3_0_1 state_machine.un15_clk_000_d0_0_a3_0_1 + Inst DSACK_0_ DSACK[0] Inst IPL_030_0_0__r IPL_030_0_0_.r - Inst state_machine_un15_clk_000_d0_0_a3_0_2 state_machine.un15_clk_000_d0_0_a3_0_2 + Inst DSACK_1_ DSACK[1] Inst IPL_030_0_0__m IPL_030_0_0_.m - Inst state_machine_un15_clk_000_d0_0_a3_0 state_machine.un15_clk_000_d0_0_a3_0 Inst IPL_030_0_0__n IPL_030_0_0_.n - Inst state_machine_un15_clk_000_d0_0_a3_1 state_machine.un15_clk_000_d0_0_a3_1 Inst IPL_030_0_0__p IPL_030_0_0_.p - Inst state_machine_un15_clk_000_d0_0_a3_2 state_machine.un15_clk_000_d0_0_a3_2 Inst IPL_030_0_1__r IPL_030_0_1_.r - Inst state_machine_un15_clk_000_d0_0_a3 state_machine.un15_clk_000_d0_0_a3 Inst IPL_030_0_1__m IPL_030_0_1_.m - Inst SM_AMIGA_ns_0_1_0_ SM_AMIGA_ns_0_1[0] Inst IPL_030_0_1__n IPL_030_0_1_.n - Inst SM_AMIGA_ns_0_0_ SM_AMIGA_ns_0[0] Inst IPL_030_0_1__p IPL_030_0_1_.p Inst IPL_030_0_2__r IPL_030_0_2_.r Inst IPL_030_0_2__m IPL_030_0_2_.m Inst IPL_030_0_2__n IPL_030_0_2_.n + Inst FC_0_ FC[0] Inst IPL_030_0_2__p IPL_030_0_2_.p - Inst CLK_REF_1_ CLK_REF[1] - Inst clk_cpu_est_11_0_0_1_1_ clk.cpu_est_11_0_0_1[1] + Inst FC_1_ FC[1] + Inst cpu_estse_0_r cpu_estse_0.r + Inst cpu_estse_0_m cpu_estse_0.m + Inst cpu_estse_0_n cpu_estse_0.n + Inst cpu_estse_0_p cpu_estse_0.p + Inst cpu_estse_1_r cpu_estse_1.r + Inst cpu_estse_1_m cpu_estse_1.m + Inst SM_AMIGA_ns_0_1_0_ SM_AMIGA_ns_0_1[0] + Inst cpu_estse_1_n cpu_estse_1.n + Inst SM_AMIGA_ns_0_0_ SM_AMIGA_ns_0[0] + Inst cpu_estse_1_p cpu_estse_1.p + Inst cpu_est_ns_0_0_1_2_ cpu_est_ns_0_0_1[2] + Inst cpu_estse_2_r cpu_estse_2.r + Inst cpu_est_ns_0_0_2_ cpu_est_ns_0_0[2] + Inst cpu_estse_2_m cpu_estse_2.m + Inst state_machine_AMIGA_BUS_ENABLE_3_f0_i_a3_1 state_machine.AMIGA_BUS_ENABLE_3_f0_i_a3_1 + Inst cpu_estse_2_n cpu_estse_2.n + Inst state_machine_AMIGA_BUS_ENABLE_3_f0_i_a3 state_machine.AMIGA_BUS_ENABLE_3_f0_i_a3 + Inst cpu_estse_2_p cpu_estse_2.p + Inst SM_AMIGA_ns_0_a3_0_1_7_ SM_AMIGA_ns_0_a3_0_1[7] Inst state_machine_un23_clk_000_d0 state_machine.un23_clk_000_d0 - Inst clk_cpu_est_11_0_0_2_1_ clk.cpu_est_11_0_0_2[1] - Inst clk_cpu_est_11_0_0_1_ clk.cpu_est_11_0_0[1] + Inst SM_AMIGA_ns_0_a3_0_7_ SM_AMIGA_ns_0_a3_0[7] + Inst state_machine_LDS_000_INT_5_0_a3_1 state_machine.LDS_000_INT_5_0_a3_1 Inst state_machine_un6_clk_000_d4 state_machine.un6_clk_000_d4 + Inst state_machine_LDS_000_INT_5_0_a3 state_machine.LDS_000_INT_5_0_a3 + Inst state_machine_un15_clk_000_d0_0_a3_0_1 state_machine.un15_clk_000_d0_0_a3_0_1 + Inst state_machine_un15_clk_000_d0_0_a3_0 state_machine.un15_clk_000_d0_0_a3_0 + Inst clk_un12_clk_cnt_p clk.un12_clk_cnt_p + Inst state_machine_un15_clk_000_d0_0_a3_1 state_machine.un15_clk_000_d0_0_a3_1 Inst AS_030_000_SYNC_0_r AS_030_000_SYNC_0.r + Inst state_machine_un15_clk_000_d0_0_a3 state_machine.un15_clk_000_d0_0_a3 Inst AS_030_000_SYNC_0_m AS_030_000_SYNC_0.m + Inst cpu_est_ns_0_0_2_1_ cpu_est_ns_0_0_2[1] Inst AS_030_000_SYNC_0_n AS_030_000_SYNC_0.n + Inst cpu_est_ns_0_0_1_ cpu_est_ns_0_0[1] Inst AS_030_000_SYNC_0_p AS_030_000_SYNC_0.p - Inst state_machine_un6_bgack_000_0_i state_machine.un6_bgack_000_0_i + Inst state_machine_un10_bg_030_0_a3_1 state_machine.un10_bg_030_0_a3_1 + Inst state_machine_un10_bg_030_0_a3_2 state_machine.un10_bg_030_0_a3_2 Inst DTACK_SYNC_0_r DTACK_SYNC_0.r - Inst state_machine_un23_clk_000_d0_i_0 state_machine.un23_clk_000_d0_i_0 + Inst state_machine_un10_bg_030_0_a3_3 state_machine.un10_bg_030_0_a3_3 Inst DTACK_SYNC_0_m DTACK_SYNC_0.m + Inst state_machine_un10_bg_030_0_a3 state_machine.un10_bg_030_0_a3 Inst DTACK_SYNC_0_n DTACK_SYNC_0.n Inst DTACK_SYNC_0_p DTACK_SYNC_0.p Inst FPU_CS_INT_0_r FPU_CS_INT_0.r @@ -298,28 +272,35 @@ Design 'BUS68030' created Sat May 24 11:44:09 2014 Inst DSACK_INT_0_1__r DSACK_INT_0_1_.r Inst DSACK_INT_0_1__m DSACK_INT_0_1_.m Inst DSACK_INT_0_1__n DSACK_INT_0_1_.n - Inst state_machine_un8_clk_000_d2_1 state_machine.un8_clk_000_d2_1 Inst DSACK_INT_0_1__p DSACK_INT_0_1_.p + Inst AMIGA_BUS_ENABLE_0_r AMIGA_BUS_ENABLE_0.r + Inst AMIGA_BUS_ENABLE_0_m AMIGA_BUS_ENABLE_0.m + Inst AMIGA_BUS_ENABLE_0_n AMIGA_BUS_ENABLE_0.n + Inst AMIGA_BUS_ENABLE_0_p AMIGA_BUS_ENABLE_0.p + Inst UDS_000_INT_0_r UDS_000_INT_0.r + Inst UDS_000_INT_0_m UDS_000_INT_0.m + Inst state_machine_un8_clk_000_d2_1 state_machine.un8_clk_000_d2_1 + Inst UDS_000_INT_0_n UDS_000_INT_0.n Inst state_machine_un8_clk_000_d2 state_machine.un8_clk_000_d2 + Inst UDS_000_INT_0_p UDS_000_INT_0.p + Inst cpu_est_ns_0_0_1_1_ cpu_est_ns_0_0_1[1] + Inst state_machine_un15_clk_000_d0_0_i state_machine.un15_clk_000_d0_0_i + Inst state_machine_un6_bgack_000_0_i state_machine.un6_bgack_000_0_i + Inst state_machine_un23_clk_000_d0_i state_machine.un23_clk_000_d0_i + Inst SM_AMIGA_ns_0_i_7_ SM_AMIGA_ns_0_i[7] + Inst SM_AMIGA_ns_0_i_5_ SM_AMIGA_ns_0_i[5] Inst state_machine_LDS_000_INT_5_0_i state_machine.LDS_000_INT_5_0_i Inst state_machine_UDS_000_INT_5_0_i state_machine.UDS_000_INT_5_0_i - Inst state_machine_un15_clk_000_d0_0_i state_machine.un15_clk_000_d0_0_i - Inst SM_AMIGA_ns_0_i_7_ SM_AMIGA_ns_0_i[7] - Inst SM_AMIGA_ns_i_i_i_6_ SM_AMIGA_ns_i_i_i[6] - Inst SM_AMIGA_ns_0_i_5_ SM_AMIGA_ns_0_i[5] - Inst clk_un4_clk_000_d1_0_o2_i clk.un4_clk_000_d1_0_o2_i - Inst clk_cpu_est_11_i_0_o2_i_2_ clk.cpu_est_11_i_0_o2_i[2] - Inst cpu_est_0_0_i_0_ cpu_est_0_0_i[0] Inst SM_AMIGA_ns_0_i_0_ SM_AMIGA_ns_0_i[0] - Inst clk_cpu_est_11_0_0_i_3_ clk.cpu_est_11_0_0_i[3] + Inst cpu_est_ns_0_0_i_2_ cpu_est_ns_0_0_i[2] Inst SM_AMIGA_ns_i_0_o2_i_4_ SM_AMIGA_ns_i_0_o2_i[4] Inst SM_AMIGA_ns_i_0_o2_i_1_ SM_AMIGA_ns_i_0_o2_i[1] Inst state_machine_UDS_000_INT_5_0_o3_i state_machine.UDS_000_INT_5_0_o3_i - Inst clk_cpu_est_11_0_0_o2_i_3_ clk.cpu_est_11_0_0_o2_i[3] - Inst state_machine_un6_clk_000_d4_i state_machine.un6_clk_000_d4_i - Net cpu_est_3__n cpu_est[3] - Net cpu_est_0__n cpu_est[0] - Net cpu_est_1__n cpu_est[1] + Inst cpu_est_ns_i_0_o2_i_3_ cpu_est_ns_i_0_o2_i[3] + Inst state_machine_AMIGA_BUS_ENABLE_3_f0_i_o2_i state_machine.AMIGA_BUS_ENABLE_3_f0_i_o2_i + Inst clk_un3_clk_000_d1_0_o2_i clk.un3_clk_000_d1_0_o2_i + Inst cpu_est_ns_0_0_i_1_ cpu_est_ns_0_0_i[1] + Inst SM_AMIGA_ns_i_0_o2_1_ SM_AMIGA_ns_i_0_o2[1] Net ipl_030_c_0__n IPL_030_c[0] Net ipl_030_0__n IPL_030[0] Net ipl_030_c_1__n IPL_030_c[1] @@ -328,138 +309,139 @@ Design 'BUS68030' created Sat May 24 11:44:09 2014 Net ipl_c_0__n IPL_c[0] Net ipl_0__n IPL[0] Net ipl_c_1__n IPL_c[1] - Net sm_amiga_6__n SM_AMIGA[6] Net ipl_1__n IPL[1] - Net sm_amiga_5__n SM_AMIGA[5] Net ipl_c_2__n IPL_c[2] + Net dsack_0__n DSACK[0] + Net sm_amiga_5__n SM_AMIGA[5] + Net dsack_c_1__n DSACK_c[1] + Net sm_amiga_6__n SM_AMIGA[6] Net vcc_n_n VCC Net gnd_n_n GND - Net dsack_0__n DSACK[0] - Net cpu_est_2__n cpu_est[2] - Net dsack_c_1__n DSACK_c[1] - Net clk_ref_1__n CLK_REF[1] Net dsack_int_1__n DSACK_INT[1] - Net sm_amiga_7__n SM_AMIGA[7] Net state_machine_un8_clk_000_d2_n state_machine.un8_clk_000_d2 Net sm_amiga_4__n SM_AMIGA[4] Net state_machine_un23_clk_000_d0_n state_machine.un23_clk_000_d0 Net state_machine_un6_clk_000_d4_n state_machine.un6_clk_000_d4 - Net clk_clk_cnt_n clk.clk_cnt - Net clk_cnt_0__n CLK_CNT[0] - Net clk_cnt_1__n CLK_CNT[1] + Net state_machine_un10_bg_030_n state_machine.un10_bg_030 + Net sm_amiga_7__n SM_AMIGA[7] Net fc_c_0__n FC_c[0] - Net state_machine_un6_bgack_000_n state_machine.un6_bgack_000 - Net fc_0__n FC[0] Net sm_amiga_3__n SM_AMIGA[3] + Net fc_0__n FC[0] + Net state_machine_un6_bgack_000_n state_machine.un6_bgack_000 Net fc_c_1__n FC_c[1] Net sm_amiga_1__n SM_AMIGA[1] + Net un4_clk_cnt_n_1__n un4_clk_cnt_n[1] + Net clk_cnt_n_0__n CLK_CNT_N[0] + Net clk_cnt_n_1__n CLK_CNT_N[1] + Net un2_clk_cnt_p_1__n un2_clk_cnt_p[1] + Net clk_cnt_p_0__n CLK_CNT_P[0] + Net clk_cnt_p_1__n CLK_CNT_P[1] + Net cpu_est_ns_0_1__n cpu_est_ns_0[1] Net sm_amiga_2__n SM_AMIGA[2] Net sm_amiga_0__n SM_AMIGA[0] Net state_machine_un7_as_000_int_n state_machine.un7_as_000_int Net state_machine_un15_clk_000_d0_n state_machine.un15_clk_000_d0 - Net clk_clk_cnt_3_0__n clk.CLK_CNT_3[0] - Net clk_clk_cnt_3_1__n clk.CLK_CNT_3[1] - Net clk_cpu_est_11_0_1__n clk.cpu_est_11_0[1] Net state_machine_lds_000_int_5_n state_machine.LDS_000_INT_5 Net state_machine_uds_000_int_5_n state_machine.UDS_000_INT_5 - Net state_machine_un6_clk_000_d4_i_n state_machine.un6_clk_000_d4_i + Net cpu_est_ns_e_0_0__n cpu_est_ns_e_0[0] Net sm_amiga_ns_0__n SM_AMIGA_ns[0] Net sm_amiga_ns_5__n SM_AMIGA_ns[5] Net sm_amiga_ns_7__n SM_AMIGA_ns[7] - Net clk_cpu_est_11_1__n clk.cpu_est_11[1] - Net clk_cpu_est_11_3__n clk.cpu_est_11[3] Net sm_amiga_ns_0_0__n SM_AMIGA_ns_0[0] - Net un3_clk_cnt_1__n un3_clk_cnt[1] - Net clk_cpu_est_11_0_3__n clk.cpu_est_11_0[3] + Net cpu_est_0__n cpu_est[0] + Net cpu_est_1__n cpu_est[1] + Net cpu_est_2__n cpu_est[2] + Net cpu_est_3__n cpu_est[3] + Net cpu_est_ns_0_2__n cpu_est_ns_0[2] + Net cpu_est_ns_e_0__n cpu_est_ns_e[0] + Net cpu_est_ns_e_1__n cpu_est_ns_e[1] + Net cpu_est_ns_e_2__n cpu_est_ns_e[2] + Net cpu_est_ns_e_3__n cpu_est_ns_e[3] + Net cpu_est_ns_1__n cpu_est_ns[1] + Net cpu_est_ns_2__n cpu_est_ns[2] Net sm_amiga_ns_0_7__n SM_AMIGA_ns_0[7] Net sm_amiga_ns_0_5__n SM_AMIGA_ns_0[5] Net state_machine_lds_000_int_5_0_n state_machine.LDS_000_INT_5_0 Net state_machine_uds_000_int_5_0_n state_machine.UDS_000_INT_5_0 Net state_machine_un15_clk_000_d0_0_n state_machine.un15_clk_000_d0_0 Net state_machine_un6_bgack_000_0_n state_machine.un6_bgack_000_0 - Net state_machine_un23_clk_000_d0_i_n state_machine.un23_clk_000_d0_i + Net clk_un12_clk_cnt_p_i_n clk.un12_clk_cnt_p_i + Net state_machine_un23_clk_000_d0_0_n state_machine.un23_clk_000_d0_0 Net state_machine_un8_clk_000_d2_1_n state_machine.un8_clk_000_d2_1 - Net clk_cpu_est_11_0_1_1__n clk.cpu_est_11_0_1[1] - Net clk_cpu_est_11_0_2_1__n clk.cpu_est_11_0_2[1] - Net cpu_est_i_0__n cpu_est_i[0] - Net cpu_est_i_3__n cpu_est_i[3] - Net cpu_est_i_1__n cpu_est_i[1] - Net sm_amiga_i_3__n SM_AMIGA_i[3] - Net sm_amiga_ns_0_1_0__n SM_AMIGA_ns_0_1[0] - Net sm_amiga_i_6__n SM_AMIGA_i[6] - Net clk_cpu_est_11_0_1_3__n clk.cpu_est_11_0_1[3] - Net cpu_est_i_2__n cpu_est_i[2] + Net cpu_est_ns_0_1_1__n cpu_est_ns_0_1[1] + Net cpu_est_ns_0_2_1__n cpu_est_ns_0_2[1] + Net state_machine_un10_bg_030_1_n state_machine.un10_bg_030_1 + Net state_machine_un10_bg_030_2_n state_machine.un10_bg_030_2 + Net state_machine_un10_bg_030_3_n state_machine.un10_bg_030_3 Net sm_amiga_i_4__n SM_AMIGA_i[4] - Net sm_amiga_i_5__n SM_AMIGA_i[5] - Net state_machine_un8_clk_000_d2_i_n state_machine.un8_clk_000_d2_i - Net sm_amiga_i_7__n SM_AMIGA_i[7] + Net sm_amiga_ns_0_1_0__n SM_AMIGA_ns_0_1[0] + Net cpu_est_i_3__n cpu_est_i[3] + Net cpu_est_ns_0_1_2__n cpu_est_ns_0_1[2] + Net sm_amiga_i_1__n SM_AMIGA_i[1] + Net state_machine_un6_clk_000_d4_i_n state_machine.un6_clk_000_d4_i + Net sm_amiga_i_6__n SM_AMIGA_i[6] + Net cpu_est_i_1__n cpu_est_i[1] + Net cpu_est_i_0__n cpu_est_i[0] Net state_machine_uds_000_int_5_0_m2_un3_n state_machine.UDS_000_INT_5_0_m2.un3 - Net a_i_0__n A_i[0] Net state_machine_uds_000_int_5_0_m2_un1_n state_machine.UDS_000_INT_5_0_m2.un1 - Net size_i_1__n SIZE_i[1] Net state_machine_uds_000_int_5_0_m2_un0_n state_machine.UDS_000_INT_5_0_m2.un0 - Net dsack_i_1__n DSACK_i[1] - Net vpa_sync_0_un3_n VPA_SYNC_0.un3 - Net clk_clk_cnt_i_n clk.clk_cnt_i - Net vpa_sync_0_un1_n VPA_SYNC_0.un1 - Net clk_cnt_i_0__n CLK_CNT_i[0] - Net vpa_sync_0_un0_n VPA_SYNC_0.un0 - Net amiga_bus_enable_0_un3_n AMIGA_BUS_ENABLE_0.un3 - Net amiga_bus_enable_0_un1_n AMIGA_BUS_ENABLE_0.un1 - Net a_i_30__n A_i[30] - Net amiga_bus_enable_0_un0_n AMIGA_BUS_ENABLE_0.un0 - Net a_i_31__n A_i[31] - Net uds_000_int_0_un3_n UDS_000_INT_0.un3 - Net a_i_28__n A_i[28] - Net uds_000_int_0_un1_n UDS_000_INT_0.un1 - Net a_i_29__n A_i[29] - Net uds_000_int_0_un0_n UDS_000_INT_0.un0 - Net a_i_26__n A_i[26] + Net cpu_est_i_2__n cpu_est_i[2] Net lds_000_int_0_un3_n LDS_000_INT_0.un3 - Net a_i_27__n A_i[27] + Net sm_amiga_i_2__n SM_AMIGA_i[2] Net lds_000_int_0_un1_n LDS_000_INT_0.un1 - Net a_i_24__n A_i[24] + Net sm_amiga_i_3__n SM_AMIGA_i[3] Net lds_000_int_0_un0_n LDS_000_INT_0.un0 - Net a_i_25__n A_i[25] + Net sm_amiga_i_5__n SM_AMIGA_i[5] + Net vpa_sync_0_un3_n VPA_SYNC_0.un3 + Net state_machine_un8_clk_000_d2_i_n state_machine.un8_clk_000_d2_i + Net vpa_sync_0_un1_n VPA_SYNC_0.un1 + Net sm_amiga_i_7__n SM_AMIGA_i[7] + Net vpa_sync_0_un0_n VPA_SYNC_0.un0 + Net a_i_0__n A_i[0] Net vma_int_0_un3_n VMA_INT_0.un3 - Net a_i_19__n A_i[19] + Net size_i_1__n SIZE_i[1] Net vma_int_0_un1_n VMA_INT_0.un1 - Net a_i_16__n A_i[16] + Net dsack_i_1__n DSACK_i[1] Net vma_int_0_un0_n VMA_INT_0.un0 - Net a_i_18__n A_i[18] - Net bg_000_0_un3_n BG_000_0.un3 - Net bg_000_0_un1_n BG_000_0.un1 - Net state_machine_un7_as_000_int_i_n state_machine.un7_as_000_int_i - Net bg_000_0_un0_n BG_000_0.un0 Net bgack_030_int_0_un3_n BGACK_030_INT_0.un3 Net bgack_030_int_0_un1_n BGACK_030_INT_0.un1 + Net a_i_30__n A_i[30] Net bgack_030_int_0_un0_n BGACK_030_INT_0.un0 + Net a_i_31__n A_i[31] Net as_000_int_0_un3_n AS_000_INT_0.un3 + Net a_i_28__n A_i[28] Net as_000_int_0_un1_n AS_000_INT_0.un1 + Net a_i_29__n A_i[29] Net as_000_int_0_un0_n AS_000_INT_0.un0 - Net cpu_est_0_1__un3_n cpu_est_0_1_.un3 - Net cpu_est_0_1__un1_n cpu_est_0_1_.un1 - Net cpu_est_0_1__un0_n cpu_est_0_1_.un0 - Net cpu_est_0_2__un3_n cpu_est_0_2_.un3 - Net cpu_est_0_2__un1_n cpu_est_0_2_.un1 - Net cpu_est_0_2__un0_n cpu_est_0_2_.un0 - Net cpu_est_0_3__un3_n cpu_est_0_3_.un3 - Net cpu_est_0_3__un1_n cpu_est_0_3_.un1 - Net cpu_est_0_3__un0_n cpu_est_0_3_.un0 - Net size_c_0__n SIZE_c[0] + Net a_i_26__n A_i[26] Net ipl_030_0_0__un3_n IPL_030_0_0_.un3 - Net size_0__n SIZE[0] + Net a_i_27__n A_i[27] Net ipl_030_0_0__un1_n IPL_030_0_0_.un1 - Net size_c_1__n SIZE_c[1] + Net a_i_24__n A_i[24] Net ipl_030_0_0__un0_n IPL_030_0_0_.un0 + Net a_i_25__n A_i[25] Net ipl_030_0_1__un3_n IPL_030_0_1_.un3 - Net a_c_0__n A_c[0] + Net a_i_19__n A_i[19] Net ipl_030_0_1__un1_n IPL_030_0_1_.un1 - Net a_0__n A[0] + Net a_i_16__n A_i[16] Net ipl_030_0_1__un0_n IPL_030_0_1_.un0 + Net a_i_18__n A_i[18] Net ipl_030_0_2__un3_n IPL_030_0_2_.un3 Net ipl_030_0_2__un1_n IPL_030_0_2_.un1 + Net state_machine_un10_bg_030_i_n state_machine.un10_bg_030_i Net ipl_030_0_2__un0_n IPL_030_0_2_.un0 + Net state_machine_un7_as_000_int_i_n state_machine.un7_as_000_int_i + Net cpu_estse_0_un3_n cpu_estse_0.un3 + Net un2_clk_cnt_p_i_1__n un2_clk_cnt_p_i[1] + Net cpu_estse_0_un1_n cpu_estse_0.un1 + Net cpu_estse_0_un0_n cpu_estse_0.un0 + Net un4_clk_cnt_n_i_1__n un4_clk_cnt_n_i[1] + Net cpu_estse_1_un3_n cpu_estse_1.un3 + Net cpu_estse_1_un1_n cpu_estse_1.un1 + Net cpu_estse_1_un0_n cpu_estse_1.un0 + Net cpu_estse_2_un3_n cpu_estse_2.un3 + Net cpu_estse_2_un1_n cpu_estse_2.un1 + Net cpu_estse_2_un0_n cpu_estse_2.un0 Net as_030_000_sync_0_un3_n AS_030_000_SYNC_0.un3 Net as_030_000_sync_0_un1_n AS_030_000_SYNC_0.un1 Net as_030_000_sync_0_un0_n AS_030_000_SYNC_0.un0 @@ -467,55 +449,66 @@ Design 'BUS68030' created Sat May 24 11:44:09 2014 Net dtack_sync_0_un1_n DTACK_SYNC_0.un1 Net dtack_sync_0_un0_n DTACK_SYNC_0.un0 Net fpu_cs_int_0_un3_n FPU_CS_INT_0.un3 + Net size_c_0__n SIZE_c[0] Net fpu_cs_int_0_un1_n FPU_CS_INT_0.un1 + Net size_0__n SIZE[0] Net fpu_cs_int_0_un0_n FPU_CS_INT_0.un0 + Net size_c_1__n SIZE_c[1] Net dsack_int_0_1__un3_n DSACK_INT_0_1_.un3 Net dsack_int_0_1__un1_n DSACK_INT_0_1_.un1 + Net a_c_0__n A_c[0] Net dsack_int_0_1__un0_n DSACK_INT_0_1_.un0 - Net a_c_16__n A_c[16] + Net a_0__n A[0] + Net amiga_bus_enable_0_un3_n AMIGA_BUS_ENABLE_0.un3 + Net amiga_bus_enable_0_un1_n AMIGA_BUS_ENABLE_0.un1 + Net amiga_bus_enable_0_un0_n AMIGA_BUS_ENABLE_0.un0 + Net uds_000_int_0_un3_n UDS_000_INT_0.un3 + Net uds_000_int_0_un1_n UDS_000_INT_0.un1 + Net uds_000_int_0_un0_n UDS_000_INT_0.un0 Net a_15__n A[15] + Net a_14__n A[14] + Net a_13__n A[13] + Net a_12__n A[12] + Net a_11__n A[11] + Net a_c_16__n A_c[16] + Net a_10__n A[10] Net a_16__n A[16] Net a_c_17__n A_c[17] - Net a_14__n A[14] + Net a_9__n A[9] Net a_17__n A[17] Net a_c_18__n A_c[18] - Net a_13__n A[13] + Net a_8__n A[8] Net a_18__n A[18] Net a_c_19__n A_c[19] - Net a_12__n A[12] + Net a_7__n A[7] Net a_19__n A[19] Net a_c_20__n A_c[20] - Net a_11__n A[11] + Net a_6__n A[6] Net a_20__n A[20] Net a_c_21__n A_c[21] - Net a_10__n A[10] + Net a_5__n A[5] Net a_21__n A[21] Net a_c_22__n A_c[22] - Net a_9__n A[9] + Net a_4__n A[4] Net a_22__n A[22] Net a_c_23__n A_c[23] - Net a_8__n A[8] + Net a_3__n A[3] Net a_23__n A[23] Net a_c_24__n A_c[24] - Net a_7__n A[7] + Net a_2__n A[2] Net a_24__n A[24] Net a_c_25__n A_c[25] - Net a_6__n A[6] + Net a_1__n A[1] Net a_25__n A[25] Net a_c_26__n A_c[26] - Net a_5__n A[5] Net a_26__n A[26] Net a_c_27__n A_c[27] - Net a_4__n A[4] Net a_27__n A[27] Net a_c_28__n A_c[28] - Net a_3__n A[3] Net a_28__n A[28] Net a_c_29__n A_c[29] - Net a_2__n A[2] Net a_29__n A[29] Net a_c_30__n A_c[30] - Net a_1__n A[1] Net a_30__n A[30] Net a_c_31__n A_c[31] End diff --git a/Logic/bus68030.srf b/Logic/bus68030.srf index 1adcd7f..360cf59 100644 --- a/Logic/bus68030.srf +++ b/Logic/bus68030.srf @@ -6,7 +6,7 @@ #Implementation: logic $ Start of Compile -#Sat May 24 11:44:03 2014 +#Sat May 24 15:48:43 2014 Synopsys VHDL Compiler, version comp201209rcp1, Build 283R, built Mar 19 2013 @N|Running in 64-bit mode @@ -18,17 +18,15 @@ File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - VHDL syntax check successful! File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling @N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral -@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":112:7:112:15|Signal clk_030_d is undriven +@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":113:7:113:15|Signal clk_030_d is undriven Post processing for work.bus68030.behavioral -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":119:32:119:34|Pruning register cpu_est_d(3 downto 0) -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":118:32:118:34|Pruning register CLK_000_D6 -@A: CL282 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:52:109:55|Feedback mux created for signal AMIGA_BUS_ENABLE -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. -@W: CL111 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":185:2:185:3|All reachable assignments to CLK_REF(0) assign '0'; register removed by optimization -@W: CL117 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":185:2:185:3|Latch generated from process for signal CLK_REF(1 downto 0); possible missing assignment in an if or case statement. -@W: CL190 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:52:109:55|Optimizing register bit DSACK_INT(0) to a constant 1 -@W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:52:109:55|Pruning register bit 0 of DSACK_INT(1 downto 0) -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":119:32:119:34|Trying to extract state machine for register cpu_est -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":185:2:185:3|Trying to extract state machine for register SM_AMIGA +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":221:2:221:3|Pruning register CLK_REF(1 downto 0) +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":119:32:119:34|Pruning register CLK_000_D6 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":112:31:112:33|Pruning register cpu_est_d(3 downto 0) +@A: CL282 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":110:52:110:55|Feedback mux created for signal AMIGA_BUS_ENABLE -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. +@W: CL190 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":110:52:110:55|Optimizing register bit DSACK_INT(0) to a constant 1 +@W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":110:52:110:55|Pruning register bit 0 of DSACK_INT(1 downto 0) +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":221:2:221:3|Trying to extract state machine for register SM_AMIGA Extracted state machine for register SM_AMIGA State machine has 8 reachable states with original encodings of: 000 @@ -39,10 +37,25 @@ State machine has 8 reachable states with original encodings of: 101 110 111 -@W: CL249 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":185:2:185:3|Initial value is not supported on state machine SM_AMIGA +@W: CL249 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":221:2:221:3|Initial value is not supported on state machine SM_AMIGA +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":112:31:112:33|Trying to extract state machine for register cpu_est +Extracted state machine for register cpu_est +State machine has 11 reachable states with original encodings of: + 0000 + 0010 + 0011 + 0100 + 0101 + 0110 + 0111 + 1010 + 1011 + 1100 + 1111 +@W: CL249 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":112:31:112:33|Initial value is not supported on state machine cpu_est @END Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Sat May 24 11:44:03 2014 +# Sat May 24 15:48:43 2014 ###########################################################] Map & Optimize Report @@ -61,23 +74,34 @@ original code -> new code 101 -> 00100000 110 -> 01000000 111 -> 10000000 -@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":154:4:154:7|Found ROM, 'clk\.cpu_est_11[3:0]', 16 words by 4 bits +Encoding state machine cpu_est[0:10] (view:work.BUS68030(behavioral)) +original code -> new code + 0000 -> 0000 + 0010 -> 0010 + 0011 -> 0011 + 0100 -> 0100 + 0101 -> 0101 + 0110 -> 0110 + 0111 -> 0111 + 1010 -> 1010 + 1011 -> 1011 + 1100 -> 1100 + 1111 -> 1111 --------------------------------------- Resource Usage Report Simple gate primitives: -DFFSH 16 uses -DFFRH 7 uses -DFF 17 uses +DFFRH 18 uses +DFFSH 23 uses +DFF 1 use IBUF 35 uses BUFTH 7 uses OBUF 15 uses BI_DIR 2 uses -AND2 159 uses -INV 132 uses -OR2 19 uses -XOR2 3 uses -DLATRH 1 use +AND2 145 uses +INV 129 uses +OR2 18 uses +XOR2 2 uses @N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis. @@ -87,6 +111,6 @@ Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 95MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Sat May 24 11:44:04 2014 +# Sat May 24 15:48:45 2014 ###########################################################] diff --git a/Logic/dm/BUS68030_compiler.xdm b/Logic/dm/BUS68030_compiler.xdm index 6cb1414..446166e 100644 --- a/Logic/dm/BUS68030_compiler.xdm +++ b/Logic/dm/BUS68030_compiler.xdm @@ -26,10 +26,10 @@ S7RCVMI="F3s Anz1Ujjd3ELCNFPHs"NDR"D=PDE8"S> SRSqS SRSqS"/ -S -S +/>SqSSqS"/ + + /S<7>CV ]sC diff --git a/Logic/run_options.txt b/Logic/run_options.txt index 58f511e..6440f68 100644 --- a/Logic/run_options.txt +++ b/Logic/run_options.txt @@ -1,7 +1,7 @@ #-- Synopsys, Inc. #-- Version G-2012.09LC-SP1 #-- Project file C:\users\matze\documents\github\68030tk\logic\run_options.txt -#-- Written on Sat May 24 11:44:03 2014 +#-- Written on Sat May 24 15:48:43 2014 #project files diff --git a/Logic/synlog/bus68030_fpga_mapper.srr b/Logic/synlog/bus68030_fpga_mapper.srr index d49a658..fb814f0 100644 --- a/Logic/synlog/bus68030_fpga_mapper.srr +++ b/Logic/synlog/bus68030_fpga_mapper.srr @@ -12,23 +12,34 @@ original code -> new code 101 -> 00100000 110 -> 01000000 111 -> 10000000 -@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":154:4:154:7|Found ROM, 'clk\.cpu_est_11[3:0]', 16 words by 4 bits +Encoding state machine cpu_est[0:10] (view:work.BUS68030(behavioral)) +original code -> new code + 0000 -> 0000 + 0010 -> 0010 + 0011 -> 0011 + 0100 -> 0100 + 0101 -> 0101 + 0110 -> 0110 + 0111 -> 0111 + 1010 -> 1010 + 1011 -> 1011 + 1100 -> 1100 + 1111 -> 1111 --------------------------------------- Resource Usage Report Simple gate primitives: -DFFSH 16 uses -DFFRH 7 uses -DFF 17 uses +DFFRH 18 uses +DFFSH 23 uses +DFF 1 use IBUF 35 uses BUFTH 7 uses OBUF 15 uses BI_DIR 2 uses -AND2 159 uses -INV 132 uses -OR2 19 uses -XOR2 3 uses -DLATRH 1 use +AND2 145 uses +INV 129 uses +OR2 18 uses +XOR2 2 uses @N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis. @@ -38,6 +49,6 @@ Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 95MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Sat May 24 11:44:04 2014 +# Sat May 24 15:48:45 2014 ###########################################################] diff --git a/Logic/synlog/report/BUS68030_compiler_errors.txt b/Logic/synlog/report/BUS68030_compiler_errors.txt index 7b271c5..42beacf 100644 --- a/Logic/synlog/report/BUS68030_compiler_errors.txt +++ b/Logic/synlog/report/BUS68030_compiler_errors.txt @@ -1,3 +1,3 @@ -@E: CG119 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":272:31:272:40|Expecting closing ) +@E: CD415 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":391:6:391:7|Expecting keyword process @E|Parse errors encountered - exiting diff --git a/Logic/synlog/report/BUS68030_compiler_notes.txt b/Logic/synlog/report/BUS68030_compiler_notes.txt index 947b038..4145143 100644 --- a/Logic/synlog/report/BUS68030_compiler_notes.txt +++ b/Logic/synlog/report/BUS68030_compiler_notes.txt @@ -2,6 +2,6 @@ @N: CD720 :"C:\Program Files (x86)\ispLever\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns @N:"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Top entity is set to BUS68030. @N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":119:32:119:34|Trying to extract state machine for register cpu_est -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":185:2:185:3|Trying to extract state machine for register SM_AMIGA +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":221:2:221:3|Trying to extract state machine for register SM_AMIGA +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":112:31:112:33|Trying to extract state machine for register cpu_est diff --git a/Logic/synlog/report/BUS68030_compiler_runstatus.xml b/Logic/synlog/report/BUS68030_compiler_runstatus.xml index 07e6671..ad5a740 100644 --- a/Logic/synlog/report/BUS68030_compiler_runstatus.xml +++ b/Logic/synlog/report/BUS68030_compiler_runstatus.xml @@ -29,13 +29,13 @@ The file contains the job information from compiler to be displayed as part of t - - 0h:00m:00s + 0h:00m:01s - - 1400924643 + 1400939323 \ No newline at end of file diff --git a/Logic/synlog/report/BUS68030_compiler_warnings.txt b/Logic/synlog/report/BUS68030_compiler_warnings.txt index 561fb4f..62cf801 100644 --- a/Logic/synlog/report/BUS68030_compiler_warnings.txt +++ b/Logic/synlog/report/BUS68030_compiler_warnings.txt @@ -1,9 +1,9 @@ -@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":112:7:112:15|Signal clk_030_d is undriven -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":119:32:119:34|Pruning register cpu_est_d(3 downto 0) -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":118:32:118:34|Pruning register CLK_000_D6 -@W: CL111 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":185:2:185:3|All reachable assignments to CLK_REF(0) assign '0'; register removed by optimization -@W: CL117 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":185:2:185:3|Latch generated from process for signal CLK_REF(1 downto 0); possible missing assignment in an if or case statement. -@W: CL190 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:52:109:55|Optimizing register bit DSACK_INT(0) to a constant 1 -@W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:52:109:55|Pruning register bit 0 of DSACK_INT(1 downto 0) -@W: CL249 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":185:2:185:3|Initial value is not supported on state machine SM_AMIGA +@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":113:7:113:15|Signal clk_030_d is undriven +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":221:2:221:3|Pruning register CLK_REF(1 downto 0) +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":119:32:119:34|Pruning register CLK_000_D6 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":112:31:112:33|Pruning register cpu_est_d(3 downto 0) +@W: CL190 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":110:52:110:55|Optimizing register bit DSACK_INT(0) to a constant 1 +@W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":110:52:110:55|Pruning register bit 0 of DSACK_INT(1 downto 0) +@W: CL249 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":221:2:221:3|Initial value is not supported on state machine SM_AMIGA +@W: CL249 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":112:31:112:33|Initial value is not supported on state machine cpu_est diff --git a/Logic/synlog/report/BUS68030_fpga_mapper_notes.txt b/Logic/synlog/report/BUS68030_fpga_mapper_notes.txt index 78363a8..9330d5e 100644 --- a/Logic/synlog/report/BUS68030_fpga_mapper_notes.txt +++ b/Logic/synlog/report/BUS68030_fpga_mapper_notes.txt @@ -1,3 +1,2 @@ @N: MF248 |Running in 64-bit mode. -@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":154:4:154:7|Found ROM, 'clk\.cpu_est_11[3:0]', 16 words by 4 bits @N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis. diff --git a/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml b/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml index bbb5cf9..12a0416 100644 --- a/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml +++ b/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml @@ -12,7 +12,7 @@ The file contains the job information from mapper to be displayed as part of the -3 +2 C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_fpga_mapper_notes.txt @@ -39,7 +39,7 @@ The file contains the job information from mapper to be displayed as part of the 95MB -1400924644 +1400939325 diff --git a/Logic/syntmp/run_option.xml b/Logic/syntmp/run_option.xml index ee999c5..d887180 100644 --- a/Logic/syntmp/run_option.xml +++ b/Logic/syntmp/run_option.xml @@ -3,7 +3,7 @@ Synopsys, Inc. Version G-2012.09LC-SP1 Project file C:\users\matze\documents\github\68030tk\logic\syntmp\run_option.xml - Written on Sat May 24 11:44:03 2014 + Written on Sat May 24 15:48:43 2014 --> diff --git a/Logic/synwork/BUS68030_compiler.fdep b/Logic/synwork/BUS68030_compiler.fdep index c474942..f654fe7 100644 --- a/Logic/synwork/BUS68030_compiler.fdep +++ b/Logic/synwork/BUS68030_compiler.fdep @@ -10,7 +10,7 @@ #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328 -#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1400924608 +#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1400939316 0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl # Dependency Lists (Uses list) diff --git a/Logic/synwork/BUS68030_compiler.fdeporig b/Logic/synwork/BUS68030_compiler.fdeporig index 5e3e626..8a2b35c 100644 --- a/Logic/synwork/BUS68030_compiler.fdeporig +++ b/Logic/synwork/BUS68030_compiler.fdeporig @@ -10,7 +10,7 @@ #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328 -#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1400924608 +#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1400939316 0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl # Dependency Lists (Uses list) diff --git a/Logic/synwork/BUS68030_compiler.srs b/Logic/synwork/BUS68030_compiler.srs index 36d245e..e773b47 100644 Binary files a/Logic/synwork/BUS68030_compiler.srs and b/Logic/synwork/BUS68030_compiler.srs differ diff --git a/Logic/synwork/BUS68030_compiler.tlg b/Logic/synwork/BUS68030_compiler.tlg index 8dc0c66..ec82448 100644 --- a/Logic/synwork/BUS68030_compiler.tlg +++ b/Logic/synwork/BUS68030_compiler.tlg @@ -1,15 +1,13 @@ @N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral -@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":112:7:112:15|Signal clk_030_d is undriven +@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":113:7:113:15|Signal clk_030_d is undriven Post processing for work.bus68030.behavioral -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":119:32:119:34|Pruning register cpu_est_d(3 downto 0) -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":118:32:118:34|Pruning register CLK_000_D6 -@A: CL282 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:52:109:55|Feedback mux created for signal AMIGA_BUS_ENABLE -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. -@W: CL111 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":185:2:185:3|All reachable assignments to CLK_REF(0) assign '0'; register removed by optimization -@W: CL117 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":185:2:185:3|Latch generated from process for signal CLK_REF(1 downto 0); possible missing assignment in an if or case statement. -@W: CL190 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:52:109:55|Optimizing register bit DSACK_INT(0) to a constant 1 -@W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:52:109:55|Pruning register bit 0 of DSACK_INT(1 downto 0) -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":119:32:119:34|Trying to extract state machine for register cpu_est -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":185:2:185:3|Trying to extract state machine for register SM_AMIGA +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":221:2:221:3|Pruning register CLK_REF(1 downto 0) +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":119:32:119:34|Pruning register CLK_000_D6 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":112:31:112:33|Pruning register cpu_est_d(3 downto 0) +@A: CL282 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":110:52:110:55|Feedback mux created for signal AMIGA_BUS_ENABLE -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. +@W: CL190 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":110:52:110:55|Optimizing register bit DSACK_INT(0) to a constant 1 +@W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":110:52:110:55|Pruning register bit 0 of DSACK_INT(1 downto 0) +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":221:2:221:3|Trying to extract state machine for register SM_AMIGA Extracted state machine for register SM_AMIGA State machine has 8 reachable states with original encodings of: 000 @@ -20,4 +18,19 @@ State machine has 8 reachable states with original encodings of: 101 110 111 -@W: CL249 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":185:2:185:3|Initial value is not supported on state machine SM_AMIGA +@W: CL249 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":221:2:221:3|Initial value is not supported on state machine SM_AMIGA +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":112:31:112:33|Trying to extract state machine for register cpu_est +Extracted state machine for register cpu_est +State machine has 11 reachable states with original encodings of: + 0000 + 0010 + 0011 + 0100 + 0101 + 0110 + 0111 + 1010 + 1011 + 1100 + 1111 +@W: CL249 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":112:31:112:33|Initial value is not supported on state machine cpu_est