From d39a0451d54073b581286de5c47d0081138e9909 Mon Sep 17 00:00:00 2001
From: MHeinrichs <matthias_heinrichs@yahoo.com>
Date: Sun, 10 Aug 2014 00:06:49 +0200
Subject: [PATCH] Stable! (up to now ;) )

---
 Logic/68030-68000-bus-diff.vhd                |  582 +++++++
 Logic/68030-68000-bus.vhd                     |   19 +-
 Logic/68030_TK.tcl                            | 1464 +++++++++++++++++
 Logic/68030_tk.crf                            |    2 +-
 Logic/68030_tk.ipr                            |    3 +-
 Logic/BUS68030.fse                            |   46 +-
 Logic/BUS68030.prj                            |    2 +-
 Logic/bus68030.srf                            |   40 +-
 Logic/run_options.txt                         |    2 +-
 Logic/synlog/bus68030_fpga_mapper.srr         |   11 +-
 .../synlog/report/BUS68030_compiler_notes.txt |    4 +-
 .../report/BUS68030_compiler_runstatus.xml    |    2 +-
 .../report/BUS68030_compiler_warnings.txt     |   20 +-
 .../report/BUS68030_fpga_mapper_runstatus.xml |    2 +-
 Logic/syntmp/run_option.xml                   |    2 +-
 Logic/synwork/BUS68030_compiler.fdep          |    2 +-
 Logic/synwork/BUS68030_compiler.fdeporig      |    2 +-
 Logic/synwork/BUS68030_compiler.srs           |  Bin 11220 -> 11308 bytes
 Logic/synwork/BUS68030_compiler.tlg           |   25 +-
 19 files changed, 2138 insertions(+), 92 deletions(-)
 create mode 100644 Logic/68030-68000-bus-diff.vhd

diff --git a/Logic/68030-68000-bus-diff.vhd b/Logic/68030-68000-bus-diff.vhd
new file mode 100644
index 0000000..adff212
--- /dev/null
+++ b/Logic/68030-68000-bus-diff.vhd
@@ -0,0 +1,582 @@
+-- Copyright: Matthias Heinrichs 2014
+-- Free for non-comercial use
+-- No warranty just for fun
+-- If you want to earn money with this code, ask me first!
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+entity BUS68030 is
+
+port( 
+	AS_030: inout std_logic ;
+	AS_000: inout std_logic ;
+	RW_000: inout std_logic ;
+	DS_030: inout std_logic ;
+	UDS_000: inout std_logic;
+	LDS_000: inout std_logic;
+	SIZE: inout std_logic_vector ( 1 downto 0 );
+	A: in std_logic_vector ( 31 downto 16 );
+	A0: inout std_logic;
+	nEXP_SPACE: in std_logic ;
+	BERR: inout std_logic ;
+	BG_030: in std_logic ;
+	BG_000: out std_logic ;
+	BGACK_030: out std_logic ;
+	BGACK_000: in std_logic ;
+	CLK_030: in std_logic ;
+	CLK_000: in std_logic ;
+	CLK_OSZI: in std_logic ;
+	CLK_DIV_OUT: out std_logic ;
+	CLK_EXP: out std_logic	; 
+	FPU_CS: out std_logic ;
+	IPL_030: out std_logic_vector ( 2 downto 0 );
+	IPL: in std_logic_vector ( 2 downto 0 );
+	DSACK1: inout std_logic;
+	DTACK: inout std_logic ;
+	AVEC: out std_logic ;
+	AVEC_EXP: inout std_logic ; --this is a "free pin"
+	E: out std_logic ;
+	VPA: in std_logic ;
+	VMA: out std_logic ;
+	RST: in std_logic ;
+	RESET: out std_logic ;
+	RW: inout std_logic ;
+--	D: inout std_logic_vector ( 31 downto 28 );
+	FC: in std_logic_vector ( 1 downto 0 );
+	AMIGA_BUS_ENABLE: out std_logic ;
+	AMIGA_BUS_DATA_DIR: out std_logic ;
+	AMIGA_BUS_ENABLE_LOW: out std_logic;
+	CIIN: out std_logic
+	);
+end BUS68030;
+
+architecture Behavioral of BUS68030 is
+
+
+subtype ESTATE is std_logic_vector(3 downto 0);
+  
+constant E1  : ESTATE := "0110";
+constant E2  : ESTATE := "0111";  
+constant E3  : ESTATE := "0100";  
+constant E4  : ESTATE := "0101";  
+constant E5  : ESTATE := "0010";  
+constant E6  : ESTATE := "0011";  
+constant E7  : ESTATE := "1010";  
+constant E8  : ESTATE := "1011";  
+constant E9  : ESTATE := "1100";  
+constant E10 : ESTATE := "1111";
+-- Illegal states  
+constant E20 : ESTATE := "0000";  
+constant E4a : ESTATE := "0001";  
+constant E21 : ESTATE := "1000";  
+constant E22 : ESTATE := "1001";  
+constant E23 : ESTATE := "1101";  
+constant E24 : ESTATE := "1110";  
+
+signal cpu_est : ESTATE;
+
+subtype AMIGA_STATE is std_logic_vector(2 downto 0);
+  
+constant IDLE_P		 : AMIGA_STATE := "000";
+constant IDLE_N		 : AMIGA_STATE := "001";
+constant AS_SET_P	 : AMIGA_STATE := "010";  
+constant AS_SET_N	 : AMIGA_STATE := "011";  
+constant SAMPLE_DTACK_P: AMIGA_STATE := "100";  
+constant DATA_FETCH_N: AMIGA_STATE := "101";  
+constant DATA_FETCH_P : AMIGA_STATE := "110";  
+constant END_CYCLE_N : AMIGA_STATE := "111";  
+
+signal SM_AMIGA : AMIGA_STATE;
+  
+--signal	Dout:STD_LOGIC_VECTOR(3 downto 0) := "0000";
+signal	AS_000_INT:STD_LOGIC		:= '1';
+signal	RW_000_INT:STD_LOGIC		:= '1';
+signal	AMIGA_BUS_ENABLE_INT:STD_LOGIC		:= '1';
+signal	AS_030_000_SYNC:STD_LOGIC	:= '1';
+signal	BGACK_030_INT:STD_LOGIC		:= '1';
+signal	BGACK_030_INT_D:STD_LOGIC	:= '1';
+signal	AS_000_DMA:STD_LOGIC		:= '1';
+signal	DS_000_DMA:STD_LOGIC		:= '1';
+signal	RW_000_DMA:STD_LOGIC		:= '1';
+signal  SIZE_DMA: STD_LOGIC_VECTOR ( 1 downto 0 ) 	:= "11";
+signal	A0_DMA: STD_LOGIC			:= '1';
+signal	FPU_CS_INT:STD_LOGIC		:= '1';
+signal	VMA_INT: STD_LOGIC			:= '1';
+signal	VPA_D: STD_LOGIC			:= '1';
+signal	UDS_000_INT: STD_LOGIC		:= '1';
+signal	LDS_000_INT: STD_LOGIC		:= '1';
+signal	DS_000_ENABLE: STD_LOGIC	:= '0';
+signal  DSACK1_INT: STD_LOGIC		:= '1';
+signal	CLK_CNT_P: STD_LOGIC_VECTOR ( 1 downto 0 ) 	:= "00";
+signal	CLK_CNT_N: STD_LOGIC_VECTOR ( 1 downto 0 ) 	:= "00";
+signal	CLK_REF: STD_LOGIC_VECTOR ( 1 downto 0 ) 	:= "10";
+signal	CLK_OUT_PRE_50: STD_LOGIC	:= '1';
+signal	CLK_OUT_PRE_50_D: STD_LOGIC	:= '1';
+signal	CLK_OUT_PRE_25: STD_LOGIC	:= '1';
+signal	CLK_OUT_PRE_33: STD_LOGIC	:= '1';
+signal  CLK_PRE_66:STD_LOGIC		:= '0';
+signal	CLK_OUT_PRE: STD_LOGIC		:= '1';
+signal	CLK_OUT_PRE_D: STD_LOGIC	:= '1';
+signal	CLK_OUT_NE: STD_LOGIC		:= '1';
+signal	CLK_OUT_INT: STD_LOGIC		:= '1';
+signal	CLK_030_H: STD_LOGIC		:= '1';
+signal	CLK_000_D0: STD_LOGIC 		:= '1';
+signal	CLK_000_D1: STD_LOGIC 		:= '1';
+signal	CLK_000_D2: STD_LOGIC 		:= '1';
+signal	CLK_000_D3: STD_LOGIC 		:= '1';
+signal	CLK_000_D4: STD_LOGIC 		:= '1';
+signal	CLK_000_P_SYNC: STD_LOGIC_VECTOR ( 12 downto 0 ) 	:= "0000000000000";
+signal	CLK_000_N_SYNC: STD_LOGIC_VECTOR ( 12 downto 0 ) 	:= "0000000000000";
+signal	CLK_000_PE: STD_LOGIC 		:= '0';
+signal	CLK_000_NE: STD_LOGIC 		:= '0';
+signal	CLK_000_NE_D: STD_LOGIC 	:= '0';
+signal	DTACK_D0: STD_LOGIC 		:= '1';
+begin
+
+
+	--the clocks
+	neg_clk: process(RST, CLK_OSZI)
+	begin
+		if(RST = '0' ) then
+			CLK_CNT_N	<= "10";	
+		elsif(falling_edge(CLK_OSZI)) then
+			if(CLK_CNT_N = "10") then
+				CLK_CNT_N	<= "00";	
+			else
+				CLK_CNT_N	<= CLK_CNT_N+1;					
+			end if;
+		end if;
+	end process neg_clk;
+	--the state machine
+	state_machine: process(RST, CLK_OSZI)
+	begin
+		if(RST = '0' ) then
+			CLK_CNT_P		<= "00";	
+			RESET 			<= '0';
+			CLK_OUT_PRE_50 	<= '0';
+			CLK_OUT_PRE_50_D <= '0';
+			--CLK_OUT_PRE_33 	<= '0';
+			CLK_OUT_PRE_25 	<= '0';
+			CLK_OUT_PRE 	<= '0';
+			CLK_OUT_PRE_D 	<= '0';
+			CLK_OUT_NE		<= '0';
+			CLK_OUT_INT		<= '0';
+			cpu_est			<= E20;
+			CLK_000_D0		<= '1';
+			CLK_000_D1		<= '1';
+			CLK_000_D2		<= '1';
+			CLK_000_D3		<= '1';
+			CLK_000_D4		<= '1';
+			VPA_D			<= '1';
+			DTACK_D0		<= '1';
+			SM_AMIGA		<= IDLE_P;
+			AS_000_INT 		<= '1';
+			RW_000_INT		<= '1';
+			RW_000_DMA		<= '1';
+			AS_030_000_SYNC <= '1';
+			UDS_000_INT		<= '1';
+			LDS_000_INT		<= '1';
+			DS_000_ENABLE	<= '0';
+			CLK_REF			<= "00";
+			VMA_INT			<= '1';
+			FPU_CS_INT		<= '1';
+			BG_000			<= '1';
+			BGACK_030_INT	<= '1';
+			BGACK_030_INT_D <= '1';
+			DSACK1_INT		<= '1';
+			IPL_030			<= "111";
+			CLK_000_P_SYNC	<= "0000000000000";
+			CLK_000_N_SYNC	<= "0000000000000";
+			CLK_000_PE		<= '0';
+			CLK_000_NE		<= '0';
+			CLK_000_NE_D	<= '0';
+			AS_000_DMA		<= '1';
+			DS_000_DMA		<= '1';
+			SIZE_DMA		<= "11";
+			A0_DMA			<= '1';
+			AMIGA_BUS_ENABLE_INT <= '1';
+		elsif(rising_edge(CLK_OSZI)) then
+			--reset buffer
+			RESET <= '1';
+
+			--clk generation :
+
+		    CLK_OUT_PRE_50	<=	not CLK_OUT_PRE_50;
+		    CLK_OUT_PRE_50_D<=	CLK_OUT_PRE_50;		    
+			if(CLK_CNT_P = "10") then				
+				CLK_CNT_P	<= "00";	
+			else
+				CLK_CNT_P	<= CLK_CNT_P+1;					
+			end if;
+			
+			--if(CLK_CNT_P ="00" or CLK_CNT_N ="00")then --33MHz Clock
+			--	CLK_OUT_PRE_33 <= '0'; 
+			--else 
+			--	CLK_OUT_PRE_33 <= '1';
+			--end if;
+			
+			if(CLK_OUT_PRE_50='1' and CLK_OUT_PRE_50_D='0')then
+				CLK_OUT_PRE_25	<=	not CLK_OUT_PRE_25;
+			end if;
+			
+			--here the clock is selected
+			CLK_OUT_PRE 	<= CLK_OUT_PRE_25;
+			CLK_OUT_PRE_D 	<= CLK_OUT_PRE;
+			
+			--a negative edge is comming next cycle
+			if(CLK_OUT_PRE_D='1' and CLK_OUT_PRE='0' )then
+				CLK_OUT_NE <= '1';
+			else
+				CLK_OUT_NE <= '0';
+			end if;
+			-- the external clock to the processor is generated here
+			CLK_OUT_INT	<= CLK_OUT_PRE_D; --this way we know the clock of the next state: Its like looking in the future, cool!
+			--delayed Clocks and signals for edge detection
+			CLK_000_D0 	<= CLK_000;
+			CLK_000_D1 	<= CLK_000_D0;
+			CLK_000_D2 	<= CLK_000_D1;
+			CLK_000_D3 	<= CLK_000_D2;
+			CLK_000_D4 	<= CLK_000_D3;
+
+			--shift registers for edge detection
+			CLK_000_P_SYNC( 12 downto 1 ) 	<= CLK_000_P_SYNC( 11 downto 0 );
+			CLK_000_P_SYNC(0)				<= CLK_000_D0 AND NOT CLK_000_D1 AND NOT CLK_000_D2 AND NOT CLK_000_D3;
+			CLK_000_N_SYNC( 12 downto 1 ) 	<= CLK_000_N_SYNC( 11 downto 0 );
+			CLK_000_N_SYNC(0)				<= NOT CLK_000_D0 AND CLK_000_D1 AND CLK_000_D2 AND CLK_000_D3;
+			
+			-- values are determined empiracally for 7.09 MHz Clock
+			-- since the clock is not symmetrically these values differ!
+			CLK_000_PE <= CLK_000_P_SYNC(9);
+			CLK_000_NE <= CLK_000_N_SYNC(11);
+			CLK_000_NE_D <= CLK_000_NE;
+			DTACK_D0	<= DTACK;
+			VPA_D 		<= VPA;
+
+			--now: 68000 state machine and signals
+			
+			-- e-clock
+			if(CLK_000_PE = '1') then
+			--if(CLK_000_D1 = '0' and CLK_000_D0 = '1') then
+				case (cpu_est) is
+					when E1 => cpu_est <= E2 ; 
+					when E2 => cpu_est <= E3 ;
+					when E3 => cpu_est <= E4;
+					when E4  => cpu_est <= E5 ;
+					when E5  => cpu_est <= E6 ;
+					when E6  => cpu_est <= E7 ;
+					when E7  => cpu_est <= E8 ;
+					when E8  => cpu_est <= E9 ;
+					when E9  => cpu_est <= E10;
+					when E10 => cpu_est <= E1 ;
+					-- Illegal states
+					when E4a => cpu_est <= E5 ;
+					when E20 => cpu_est <= E10;
+					when E21 => cpu_est <= E10;
+					when E22 => cpu_est <= E9 ;
+					when E23 => cpu_est <= E9 ;
+					when E24 => cpu_est <= E10;
+					when others =>
+						null;
+				end case;
+			end if;
+
+
+
+
+			--bgack is simple: assert as soon as Amiga asserts but hold bg_ack for one amiga-clock 
+			if(BGACK_000='0') then
+				BGACK_030_INT	<= '0';
+			elsif (	BGACK_000='1' 
+					AND CLK_000_PE='1'
+					--AND CLK_000_D1='0' and CLK_000_D0='1'
+					) then -- BGACK_000 is high here!
+				BGACK_030_INT 	<= '1'; --hold this signal high until 7m clock goes high
+			end if;
+			BGACK_030_INT_D <= BGACK_030_INT;
+
+			--bus grant only in idle state
+			if(BG_030= '1')then
+				BG_000	<= '1';
+			elsif(	BG_030= '0' --AND (SM_AMIGA 	= IDLE_P)
+					and nEXP_SPACE = '1' and AS_030='1'
+					and CLK_000='1' 
+					--and CLK_000_D0='1' AND CLK_000_D1='0'  
+					) then --bus granted no local access and no AS_030 running!
+					BG_000 	<= '0';
+			end if;
+
+		
+			--interrupt buffering to avoid ghost interrupts
+			if(CLK_000_PE='1')then
+			--if(CLK_000_D1='0' and CLK_000_D0='1')then
+				IPL_030<=IPL;			
+			end if;
+		
+			-- as030-sampling and FPU-Select
+
+			
+			if(AS_030 ='1' or BERR='0') then -- "async" reset of various signals
+				AS_030_000_SYNC <= '1';
+				FPU_CS_INT		<= '1';
+				DSACK1_INT		<= '1';
+				AS_000_INT  	<= '1';
+				DS_000_ENABLE	<= '0';
+			elsif(	--CLK_030  		= '1'  AND --68030 has a valid AS on high clocks					
+					AS_030 			= '0') then
+				if(FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0' AND BGACK_000='1') then
+					FPU_CS_INT	<= '0';
+				else 
+					if(	nEXP_SPACE ='1' and --not an expansion space cycle
+						SM_AMIGA = IDLE_P AND --last amiga cycle terminated
+						BGACK_030_INT	= '1'  --no dma -cycle
+						)then
+						AS_030_000_SYNC <= '0';					
+					end if;					
+				end if;
+			end if;
+			
+
+			-- VMA generation
+			if(CLK_000_NE='1' AND VPA_D='0' AND cpu_est = E4)then --assert
+				VMA_INT <= '0';
+			elsif(CLK_000_PE='1' AND AS_000_INT='1' AND cpu_est=E1)then --deassert
+				VMA_INT <= '1';
+			end if;
+			
+			--uds/lds precalculation
+			if (DS_030 = '0') then --DS: set udl/lds 	
+				if(A0='0') then
+					UDS_000_INT <= '0';
+				else
+					UDS_000_INT <= '1';
+				end if;
+				if((A0='1' OR SIZE(0)='0' OR SIZE(1)='1')) then
+					LDS_000_INT <= '0';
+				else
+					LDS_000_INT <= '1';
+				end if;
+			end if;
+
+
+			--Amiga statemachine
+
+			if(BERR='0')then --"async" reset on errors
+				SM_AMIGA<=IDLE_P;
+			end if;
+
+			case (SM_AMIGA) is
+				when IDLE_P 	 => --68000:S0 wait for a falling edge
+					AMIGA_BUS_ENABLE_INT <= '1';
+					RW_000_INT		<= '1';					
+					if( CLK_000_D0='0' and CLK_000_D1= '1' and AS_030_000_SYNC = '0')then						
+						if(nEXP_SPACE ='1')then -- if this a delayed expansion space detection, do not start an amiga cycle!
+							AMIGA_BUS_ENABLE_INT <= '0' ;--for now: allways on for amiga
+							SM_AMIGA<=IDLE_N;  --go to s1
+						end if;
+					end if;
+				when IDLE_N 	 => --68000:S1 place Adress on bus and wait for rising edge, on a rising CLK_000 look for a amiga adressrobe
+					if(CLK_000_PE='1')then --go to s2
+					--if(CLK_000_D0='1')then --go to s2
+						SM_AMIGA <= AS_SET_P; --as for amiga set! 
+						AS_000_INT <= '0';
+						RW_000_INT <= RW;						
+						if (RW='1' ) then --read: set udl/lds 	
+							DS_000_ENABLE	<= '1';
+						end if;
+					end if;
+				when AS_SET_P	 => --68000:S2 Amiga cycle starts here: since AS is asserted during transition to this state we simply wait here
+					if(CLK_000_NE='1')then --go to s3
+					--if(CLK_000_D0='0')then --go to s3
+						SM_AMIGA<=AS_SET_N; 
+					end if;
+				when AS_SET_N	 => --68000:S3: nothing happens here; on a transition to s4: assert uds/lds on write 
+					
+					if(CLK_000_PE='1')then --go to s4
+					--if(CLK_000_D0='1')then --go to s4
+						DS_000_ENABLE	<= '1';--write: set udl/lds earlier than in the specs. this does not seem to harm anything and is saver, than sampling uds/lds too late 				 
+						-- set DS-Enable without respect to rw: this simplifies the life for the syntesizer
+						SM_AMIGA <= SAMPLE_DTACK_P; 
+					end if;
+				when SAMPLE_DTACK_P=> --68000:S4 wait for dtack or VMA
+					if(	CLK_000_NE='1' and --falling edge
+					--if(	CLK_000_D0 = '0' and CLK_000_D1='1' and --falling edge
+						((VPA = '1' AND DTACK='0') OR --DTACK end cycle
+						(VPA='0' AND cpu_est=E9 AND VMA_INT='0')) --VPA end cycle
+						)then --go to s5
+						SM_AMIGA<=DATA_FETCH_N;
+					end if;
+				when DATA_FETCH_N=> --68000:S5 nothing happens here just wait for positive clock
+					if(CLK_000_PE = '1')then --go to s6
+					--if(CLK_000_D0='1')then --go to s6
+						SM_AMIGA<=DATA_FETCH_P;
+					end if;
+				when DATA_FETCH_P => --68000:S6: READ: here comes the data on the bus!
+					if( CLK_000_N_SYNC(6)='1') then --go to s7 next 030-clock is not a falling edge: dsack is sampled at the falling edge
+						DSACK1_INT <='0'; 
+					end if;
+					--if( CLK_000_D3 ='1' AND CLK_000_D4 = '0' ) then --go to s7 next 030-clock is high: dsack is sampled at the falling edge
+					--	DSACK1_INT <='0'; 
+					--end if;
+					if( CLK_000_NE ='1') then --go to s7 next 030-clock is high: dsack is sampled at the falling edge
+					--if( CLK_000_D0 ='0') then --go to s7 next 030-clock is high: dsack is sampled at the falling edge
+						SM_AMIGA<=END_CYCLE_N;
+						if(AS_030 ='1') then
+							AMIGA_BUS_ENABLE_INT <= '1';
+						end if;
+					end if;
+				when END_CYCLE_N =>--68000:S7: Latch/Store data. Wait here for new cycle and go to IDLE on high clock
+					if(AS_030 ='1') then
+						AMIGA_BUS_ENABLE_INT <= '1';
+					end if;
+
+					if(CLK_000_PE='1')then --go to s0	
+					--if(CLK_000_D0='1')then --go to s0																	
+						SM_AMIGA<=IDLE_P;						
+					end if;
+			end case;
+
+			if(BGACK_030_INT='0')then			
+				--switch amiga bus on for DMA-Cycles
+				AMIGA_BUS_ENABLE_INT <= '0' ;
+			elsif(BGACK_030_INT_D='0' and BGACK_030_INT='1')then			
+				AMIGA_BUS_ENABLE_INT <= '1' ;
+			end if;
+			
+			--dma stuff
+			--as can only be done if we know the uds/lds!
+			if(BGACK_030_INT='0' and AS_000='0' and (UDS_000='0' or LDS_000='0'))then 
+
+				--set AS_000
+				if( CLK_030='1') then 
+					AS_000_DMA 	<= '0'; --sampled on rising edges!
+					RW_000_DMA	<= RW_000;
+				elsif(AS_000_DMA = '0' and CLK_030='0')then
+					CLK_030_H		<= '1';
+				end if;
+				
+				if(RW_000='1') then
+					DS_000_DMA	<=AS_000_DMA;
+				elsif(RW_000='0' and CLK_030_H = '1' and CLK_030='1')then
+					DS_000_DMA	<=AS_000_DMA; -- write: one clock delayed!
+				end if;
+				-- now determine the size: if both uds and lds is set its 16 bit else 8 bit!
+				if(UDS_000='0' and LDS_000='0') then
+					SIZE_DMA		<= "10"; --16bit
+				else
+					SIZE_DMA		<= "01"; --8 bit
+				end if;
+					
+				--now calculate the offset: 
+				--if uds is set low, a0 is so too.
+				--if only lds is set a1 is high
+				--therefore a1 = uds 
+				--great! life is simple here!
+				A0_DMA <= UDS_000;		
+					
+				--A1 is set by the amiga side													
+			else
+				AS_000_DMA		<= '1';
+				DS_000_DMA		<= '1';
+				SIZE_DMA		<= "11";
+				A0_DMA			<= '0';	
+				RW_000_DMA		<= '1';	
+				CLK_030_H		<= '0';						
+			end if;
+		end if;		
+	end process	state_machine;
+
+	CLK_PRE_66 <= (not CLK_CNT_N(0) and CLK_CNT_P(0)) or
+            (CLK_CNT_N(1) and CLK_CNT_P(1));
+
+    process_33_clk:process(RST, CLK_PRE_66)
+	begin
+		if(RST = '0' ) then
+			CLK_OUT_PRE_33	<= '0';	
+		elsif(rising_edge(CLK_PRE_66)) then
+			CLK_OUT_PRE_33 <= not CLK_OUT_PRE_33;
+		end if;
+	end process process_33_clk; 
+	AMIGA_BUS_ENABLE_LOW <= CLK_OUT_PRE_33;
+
+	
+
+	--output clock assignment
+	CLK_DIV_OUT	<= CLK_OUT_INT;
+	CLK_EXP		<= CLK_OUT_INT;
+	--CLK_DIV_OUT	<= CLK_OUT_PRE_33;
+	--CLK_EXP		<= CLK_OUT_PRE_33;
+	AVEC_EXP	<= CLK_000_PE;
+	AMIGA_BUS_ENABLE <= AMIGA_BUS_ENABLE_INT;
+	--dma stuff
+	DTACK	<= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' OR AS_000_DMA ='1' else
+					DSACK1;
+	AS_030	<= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' OR AS_000_DMA ='1' else
+					AS_000_DMA;
+	DS_030	<= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' OR AS_000_DMA ='1' else
+					DS_000_DMA;
+	A0		<= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' OR AS_000_DMA ='1' else
+					A0_DMA;
+	SIZE	<= "ZZ" when BGACK_030_INT ='1' OR nEXP_SPACE = '1' OR AS_000_DMA ='1' else
+					SIZE_DMA;
+	
+	--fpu
+	FPU_CS		<=	'0' when AS_030 ='0' and FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0' AND BGACK_000='1'
+					else '1';
+	
+	--if no copro is installed:
+	--BERR		<=	'0' when AS_030 ='0' and FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0' AND BGACK_000='1'
+	--				else 'Z';
+	BERR		<=	'Z';
+
+
+
+	--cache inhibit: For now: disable
+	CIIN <= '1' WHEN A(31 downto 20) = x"00F" and AS_030 ='0' ELSE
+			--'1' WHEN A(31 downto 20) = x"002" ELSE
+			--'1' WHEN A(31 downto 20) = x"004" ELSE
+			'Z' WHEN (not(A(31 downto 24) = x"00") and AS_030 ='0') OR nEXP_SPACE = '0' ELSE
+			'0';
+
+	--bus buffers
+	AMIGA_BUS_DATA_DIR 	 <= '1' WHEN (RW='0' AND BGACK_030_INT ='1') ELSE --Amiga WRITE
+							'0' WHEN (RW='1' AND BGACK_030_INT ='1') ELSE --Amiga READ
+							'1' WHEN (RW='1' AND BGACK_030_INT ='0' AND nEXP_SPACE = '0' AND AS_000 = '0') ELSE --DMA READ to expansion space
+							'0' WHEN (RW='0' AND BGACK_030_INT ='0' AND nEXP_SPACE = '0' AND AS_000 = '0') ELSE --DMA WRITE to expansion space
+							'0'; --Point towarts TK
+	--AMIGA_BUS_ENABLE_LOW <= CLK_OUT_NE; --for now: allways off
+		
+	--e and VMA		
+	E		<= cpu_est(3);
+	VMA		<= VMA_INT;
+	
+	
+	--AVEC
+	AVEC <=	'1';
+		
+	--as and uds/lds
+	AS_000	<= 'Z' when BGACK_030_INT ='0' else
+					AS_000_INT;
+	RW_000	<= 'Z' when BGACK_030_INT ='0' else
+					RW_000_INT;
+
+	UDS_000	<= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle
+			   '1' when DS_000_ENABLE ='0' else -- datastrobe not ready jet
+					UDS_000_INT;
+	LDS_000	<= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle
+			   '1' when DS_000_ENABLE ='0' else -- datastrobe not ready jet
+					LDS_000_INT;
+
+	--dsack
+	DSACK1	<= 'Z' when nEXP_SPACE = '0' else -- output on amiga cycle
+			DSACK1_INT;
+	--rw
+	RW		<= 'Z' when BGACK_030_INT ='1' else
+					RW_000_DMA;
+	
+	BGACK_030	<= BGACK_030_INT;	
+end Behavioral;
\ No newline at end of file
diff --git a/Logic/68030-68000-bus.vhd b/Logic/68030-68000-bus.vhd
index 3fcba92..ea76b86 100644
--- a/Logic/68030-68000-bus.vhd
+++ b/Logic/68030-68000-bus.vhd
@@ -109,7 +109,6 @@ signal	RW_000_DMA:STD_LOGIC		:= '1';
 signal  SIZE_DMA: STD_LOGIC_VECTOR ( 1 downto 0 ) 	:= "11";
 signal	A0_DMA: STD_LOGIC			:= '1';
 signal	VMA_INT: STD_LOGIC			:= '1';
-signal	VMA_INT_D: STD_LOGIC			:= '1';
 signal	VPA_D: STD_LOGIC			:= '1';
 signal	UDS_000_INT: STD_LOGIC		:= '1';
 signal	LDS_000_INT: STD_LOGIC		:= '1';
@@ -188,7 +187,6 @@ begin
 			DS_000_ENABLE	<= '0';
 			CLK_REF			<= "00";
 			VMA_INT			<= '1';
-			VMA_INT_D		<= '1';
 			BG_000			<= '1';
 			BGACK_030_INT	<= '1';
 			BGACK_030_INT_D <= '1';
@@ -206,8 +204,6 @@ begin
 			AMIGA_BUS_ENABLE_INT <= '1';
 			AS_030_D0		<= '1';
 			DS_030_D0		<= '1';
-			IPL_030			<= "000";
-			CLK_030_H		<= '0';
 		elsif(rising_edge(CLK_OSZI)) then
 			--reset buffer
 			RESET <= '1';
@@ -264,7 +260,7 @@ begin
 			CLK_000_E_ADVANCE <= CLK_000_NE; 
 			DTACK_D0	<= DTACK;
 			VPA_D 		<= VPA;
-			VMA_INT_D	<= VMA_INT;
+
 			--now: 68000 state machine and signals
 			
 			-- e-clock is changed on the FALLING edge!
@@ -336,7 +332,7 @@ begin
 				DSACK1_INT		<= '1';
 				AS_000_INT  	<= '1';
 				DS_000_ENABLE	<= '0';
-				AMIGA_BUS_ENABLE_INT <= '1';								
+				AMIGA_BUS_ENABLE_INT <= '1';
 			elsif(	--CLK_030  		= '1'  AND --68030 has a valid AS on high clocks					
 					AS_030_D0			= '0'  AND --as set
 					BGACK_000='1' AND --no dma -cycle
@@ -378,7 +374,7 @@ begin
 
 			case (SM_AMIGA) is
 				when IDLE_P 	 => --68000:S0 wait for a falling edge
-												
+					RW_000_INT		<= '1';							
 					if( CLK_000_D0='0' and CLK_000_D1= '1' and AS_030_000_SYNC = '0')then						
 						if(nEXP_SPACE ='1')then -- if this a delayed expansion space detection, do not start an amiga cycle!
 							AMIGA_BUS_ENABLE_INT <= '0' ;--for now: allways on for amiga
@@ -386,8 +382,8 @@ begin
 						end if;
 					end if;
 				when IDLE_N 	 => --68000:S1 place Adress on bus and wait for rising edge, on a rising CLK_000 look for a amiga adressrobe
-					--if(CLK_000_PE='1')then --go to s2
-					if(CLK_000_D0='1')then --go to s2
+					if(CLK_000_PE='1')then --go to s2
+					--if(CLK_000_D0='1')then --go to s2
 						SM_AMIGA <= AS_SET_P; --as for amiga set! 
 						AS_000_INT <= '0';
 						RW_000_INT <= RW;						
@@ -436,8 +432,7 @@ begin
 					end if;
 				when END_CYCLE_N =>--68000:S7: Latch/Store data. Wait here for new cycle and go to IDLE on high clock
 					if(CLK_000_PE='1')then --go to s0	
-					--if(CLK_000_D0='1')then --go to s0	
-						RW_000_INT 		<= '1';																		
+					--if(CLK_000_D0='1')then --go to s0																	
 						SM_AMIGA<=IDLE_P;	
 						VMA_INT <= '1';					
 					end if;
@@ -553,7 +548,7 @@ begin
 		
 	--e and VMA		
 	E		<= cpu_est(3);
-	VMA		<= '1' WHEN VMA_INT = '1' AND VMA_INT_D ='1' ELSE '0';
+	VMA		<= VMA_INT;
 	
 	
 	--AVEC
diff --git a/Logic/68030_TK.tcl b/Logic/68030_TK.tcl
index 10452a4..d94a8c0 100644
--- a/Logic/68030_TK.tcl
+++ b/Logic/68030_TK.tcl
@@ -251399,3 +251399,1467 @@ if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 6
 
 ########## Tcl recorder end at 08/09/14 22:39:51 ###########
 
+
+########## Tcl recorder starts at 08/09/14 23:12:26 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 08/09/14 23:12:26 ###########
+
+
+########## Tcl recorder starts at 08/09/14 23:12:27 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 08/09/14 23:12:27 ###########
+
+
+########## Tcl recorder starts at 08/09/14 23:14:37 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 08/09/14 23:14:37 ###########
+
+
+########## Tcl recorder starts at 08/09/14 23:14:37 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 08/09/14 23:14:37 ###########
+
+
+########## Tcl recorder starts at 08/09/14 23:22:39 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 08/09/14 23:22:39 ###########
+
+
+########## Tcl recorder starts at 08/09/14 23:22:39 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 08/09/14 23:22:39 ###########
+
+
+########## Tcl recorder starts at 08/09/14 23:25:40 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 08/09/14 23:25:40 ###########
+
+
+########## Tcl recorder starts at 08/09/14 23:25:40 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 08/09/14 23:25:40 ###########
+
+
+########## Tcl recorder starts at 08/09/14 23:30:02 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 08/09/14 23:30:02 ###########
+
+
+########## Tcl recorder starts at 08/09/14 23:30:03 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 08/09/14 23:30:03 ###########
+
+
+########## Tcl recorder starts at 08/09/14 23:40:47 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 08/09/14 23:40:47 ###########
+
+
+########## Tcl recorder starts at 08/09/14 23:40:47 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 08/09/14 23:40:47 ###########
+
+
+########## Tcl recorder starts at 08/09/14 23:44:15 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 08/09/14 23:44:15 ###########
+
+
+########## Tcl recorder starts at 08/09/14 23:44:15 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 08/09/14 23:44:15 ###########
+
+
+########## Tcl recorder starts at 08/09/14 23:50:19 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 08/09/14 23:50:19 ###########
+
+
+########## Tcl recorder starts at 08/09/14 23:50:19 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 08/09/14 23:50:19 ###########
+
diff --git a/Logic/68030_tk.crf b/Logic/68030_tk.crf
index 2927d95..6c4256d 100644
--- a/Logic/68030_tk.crf
+++ b/Logic/68030_tk.crf
@@ -1,7 +1,7 @@
 // Signal Name Cross Reference File
 // ispLEVER Classic 1.7.00.05.28.13
 
-// Design '68030_tk' created Sat Aug 09 22:39:58 2014
+// Design '68030_tk' created Sat Aug 09 23:50:26 2014
 
 
 // LEGEND:  '>'  Functional Block Port Separator
diff --git a/Logic/68030_tk.ipr b/Logic/68030_tk.ipr
index 4214774..cf94d26 100644
--- a/Logic/68030_tk.ipr
+++ b/Logic/68030_tk.ipr
@@ -1 +1,2 @@
-<LATTICE_ENCRYPTED_BLIF>8855531@:_}c
\ No newline at end of file
+<LATTICE_ENCRYPTED_BLIF>6322631O
+GG?K
\ No newline at end of file
diff --git a/Logic/BUS68030.fse b/Logic/BUS68030.fse
index 39959f7..86ea831 100644
--- a/Logic/BUS68030.fse
+++ b/Logic/BUS68030.fse
@@ -1,46 +1,46 @@
 
-fsm_encoding {7141321411} onehot
+fsm_encoding {7140321401} onehot
 
-fsm_state_encoding {7141321411} idle_p {00000001}
+fsm_state_encoding {7140321401} idle_p {00000001}
 
-fsm_state_encoding {7141321411} idle_n {00000010}
+fsm_state_encoding {7140321401} idle_n {00000010}
 
-fsm_state_encoding {7141321411} as_set_p {00000100}
+fsm_state_encoding {7140321401} as_set_p {00000100}
 
-fsm_state_encoding {7141321411} as_set_n {00001000}
+fsm_state_encoding {7140321401} as_set_n {00001000}
 
-fsm_state_encoding {7141321411} sample_dtack_p {00010000}
+fsm_state_encoding {7140321401} sample_dtack_p {00010000}
 
-fsm_state_encoding {7141321411} data_fetch_n {00100000}
+fsm_state_encoding {7140321401} data_fetch_n {00100000}
 
-fsm_state_encoding {7141321411} data_fetch_p {01000000}
+fsm_state_encoding {7140321401} data_fetch_p {01000000}
 
-fsm_state_encoding {7141321411} end_cycle_n {10000000}
+fsm_state_encoding {7140321401} end_cycle_n {10000000}
 
-fsm_registers {7141321411} {SM_AMIGA[0]}  {SM_AMIGA[1]}  {SM_AMIGA[2]}  {SM_AMIGA[3]}  {SM_AMIGA[4]}  {SM_AMIGA[5]}  {SM_AMIGA[6]}  {SM_AMIGA[7]} 
+fsm_registers {7140321401} {SM_AMIGA[0]}  {SM_AMIGA[1]}  {SM_AMIGA[2]}  {SM_AMIGA[3]}  {SM_AMIGA[4]}  {SM_AMIGA[5]}  {SM_AMIGA[6]}  {SM_AMIGA[7]} 
 
-fsm_encoding {7129341292} original
+fsm_encoding {7128341282} original
 
-fsm_state_encoding {7129341292} e20 {0000}
+fsm_state_encoding {7128341282} e20 {0000}
 
-fsm_state_encoding {7129341292} e5 {0010}
+fsm_state_encoding {7128341282} e5 {0010}
 
-fsm_state_encoding {7129341292} e6 {0011}
+fsm_state_encoding {7128341282} e6 {0011}
 
-fsm_state_encoding {7129341292} e3 {0100}
+fsm_state_encoding {7128341282} e3 {0100}
 
-fsm_state_encoding {7129341292} e4 {0101}
+fsm_state_encoding {7128341282} e4 {0101}
 
-fsm_state_encoding {7129341292} e1 {0110}
+fsm_state_encoding {7128341282} e1 {0110}
 
-fsm_state_encoding {7129341292} e2 {0111}
+fsm_state_encoding {7128341282} e2 {0111}
 
-fsm_state_encoding {7129341292} e7 {1010}
+fsm_state_encoding {7128341282} e7 {1010}
 
-fsm_state_encoding {7129341292} e8 {1011}
+fsm_state_encoding {7128341282} e8 {1011}
 
-fsm_state_encoding {7129341292} e9 {1100}
+fsm_state_encoding {7128341282} e9 {1100}
 
-fsm_state_encoding {7129341292} e10 {1111}
+fsm_state_encoding {7128341282} e10 {1111}
 
-fsm_registers {7129341292} {cpu_est[3]}  {cpu_est[2]}  {cpu_est[1]}  {cpu_est[0]} 
+fsm_registers {7128341282} {cpu_est[3]}  {cpu_est[2]}  {cpu_est[1]}  {cpu_est[0]} 
diff --git a/Logic/BUS68030.prj b/Logic/BUS68030.prj
index 388a8cb..8571966 100644
--- a/Logic/BUS68030.prj
+++ b/Logic/BUS68030.prj
@@ -1,6 +1,6 @@
 #-- Lattice Semiconductor Corporation Ltd.
 #-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj
-#-- Written on Sat Aug 09 22:39:51 2014
+#-- Written on Sat Aug 09 23:50:19 2014
 
 
 #device options
diff --git a/Logic/bus68030.srf b/Logic/bus68030.srf
index 308d560..b2a0869 100644
--- a/Logic/bus68030.srf
+++ b/Logic/bus68030.srf
@@ -6,7 +6,7 @@
 #Implementation: logic
 
 $ Start of Compile
-#Sat Aug 09 22:39:52 2014
+#Sat Aug 09 23:50:20 2014
 
 Synopsys VHDL Compiler, version comp201209rcp1, Build 283R, built Mar 19 2013
 @N|Running in 64-bit mode
@@ -19,18 +19,19 @@ VHDL syntax check successful!
 File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
 @N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral 
 Post processing for work.bus68030.behavioral
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":501:2:501:3|Pruning register CLK_OUT_PRE_33  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":141:32:141:34|Pruning register CLK_REF(1 downto 0)  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":113:29:113:31|Pruning register DTACK_D0  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:34:134:36|Pruning register CLK_000_D4  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Pruning register CLK_000_D3  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_000_D2  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:35:127:37|Pruning register CLK_OUT_NE  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":162:2:162:3|Pruning register CLK_CNT_P(1 downto 0)  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":149:2:149:3|Pruning register CLK_CNT_N(1 downto 0)  
-@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":136:61:136:75|Pruning bit 12 of CLK_000_N_SYNC(12 downto 0) -- not in use ... 
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":496:2:496:3|Pruning register CLK_OUT_PRE_33  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":140:32:140:34|Pruning register CLK_REF(1 downto 0)  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":112:29:112:31|Pruning register DTACK_D0  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Pruning register CLK_000_D4  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_000_D3  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_000_D2  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:35:126:37|Pruning register CLK_OUT_NE  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":161:2:161:3|Pruning register CLK_CNT_P(1 downto 0)  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":148:2:148:3|Pruning register CLK_CNT_N(1 downto 0)  
+@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":135:61:135:75|Pruning bit 12 of CLK_000_N_SYNC(12 downto 0) -- not in use ... 
 @W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":105:36:105:38|Pruning bits 12 to 10 of CLK_000_P_SYNC(12 downto 0) -- not in use ... 
-@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":141:32:141:34|Trying to extract state machine for register SM_AMIGA
+@A: CL282 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":102:32:102:34|Feedback mux created for signal CLK_030_H -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
+@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":140:32:140:34|Trying to extract state machine for register SM_AMIGA
 Extracted state machine for register SM_AMIGA
 State machine has 8 reachable states with original encodings of:
    000
@@ -41,7 +42,7 @@ State machine has 8 reachable states with original encodings of:
    101
    110
    111
-@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:34:129:36|Trying to extract state machine for register cpu_est
+@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":128:34:128:36|Trying to extract state machine for register cpu_est
 Extracted state machine for register cpu_est
 State machine has 11 reachable states with original encodings of:
    0000
@@ -57,7 +58,7 @@ State machine has 11 reachable states with original encodings of:
    1111
 @END
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Sat Aug 09 22:39:52 2014
+# Sat Aug 09 23:50:20 2014
 
 ###########################################################]
 Map & Optimize Report
@@ -93,14 +94,15 @@ original code -> new code
 Resource Usage Report
 
 Simple gate primitives:
-DFFRH           48 uses
-DFFSH           24 uses
+DFFRH           44 uses
+DFFSH           26 uses
+DFF             1 use
 BI_DIR          13 uses
 IBUF            30 uses
 OBUF            16 uses
 BUFTH           1 use
-AND2            205 uses
-INV             162 uses
+AND2            201 uses
+INV             164 uses
 OR2             21 uses
 XOR2            2 uses
 
@@ -112,6 +114,6 @@ Mapper successful!
 At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 96MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Sat Aug 09 22:39:53 2014
+# Sat Aug 09 23:50:21 2014
 
 ###########################################################]
diff --git a/Logic/run_options.txt b/Logic/run_options.txt
index a3c8357..c9c6063 100644
--- a/Logic/run_options.txt
+++ b/Logic/run_options.txt
@@ -1,7 +1,7 @@
 #--  Synopsys, Inc.
 #--  Version G-2012.09LC-SP1 
 #--  Project file C:\users\matze\documents\github\68030tk\logic\run_options.txt
-#--  Written on Sat Aug 09 22:39:52 2014
+#--  Written on Sat Aug 09 23:50:20 2014
 
 
 #project files
diff --git a/Logic/synlog/bus68030_fpga_mapper.srr b/Logic/synlog/bus68030_fpga_mapper.srr
index 5a8aeb9..6f04a5b 100644
--- a/Logic/synlog/bus68030_fpga_mapper.srr
+++ b/Logic/synlog/bus68030_fpga_mapper.srr
@@ -29,14 +29,15 @@ original code -> new code
 Resource Usage Report
 
 Simple gate primitives:
-DFFRH           48 uses
-DFFSH           24 uses
+DFFRH           44 uses
+DFFSH           26 uses
+DFF             1 use
 BI_DIR          13 uses
 IBUF            30 uses
 OBUF            16 uses
 BUFTH           1 use
-AND2            205 uses
-INV             162 uses
+AND2            201 uses
+INV             164 uses
 OR2             21 uses
 XOR2            2 uses
 
@@ -48,6 +49,6 @@ Mapper successful!
 At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 96MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Sat Aug 09 22:39:53 2014
+# Sat Aug 09 23:50:21 2014
 
 ###########################################################]
diff --git a/Logic/synlog/report/BUS68030_compiler_notes.txt b/Logic/synlog/report/BUS68030_compiler_notes.txt
index 79da026..76c6e2a 100644
--- a/Logic/synlog/report/BUS68030_compiler_notes.txt
+++ b/Logic/synlog/report/BUS68030_compiler_notes.txt
@@ -2,6 +2,6 @@
 @N: CD720 :"C:\Program Files (x86)\ispLever\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
 @N:"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Top entity is set to BUS68030.
 @N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral 
-@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":141:32:141:34|Trying to extract state machine for register SM_AMIGA
-@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:34:129:36|Trying to extract state machine for register cpu_est
+@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":140:32:140:34|Trying to extract state machine for register SM_AMIGA
+@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":128:34:128:36|Trying to extract state machine for register cpu_est
 
diff --git a/Logic/synlog/report/BUS68030_compiler_runstatus.xml b/Logic/synlog/report/BUS68030_compiler_runstatus.xml
index c798f13..8776831 100644
--- a/Logic/synlog/report/BUS68030_compiler_runstatus.xml
+++ b/Logic/synlog/report/BUS68030_compiler_runstatus.xml
@@ -35,7 +35,7 @@ The file contains the job information from compiler to be displayed as part of t
   <data>-</data>
   </info>
 			<info name="Date &amp;Time">
-  <data type="timestamp">1407616792</data>
+  <data type="timestamp">1407621020</data>
   </info>
 			</job_info>
 </job_run_status>
\ No newline at end of file
diff --git a/Logic/synlog/report/BUS68030_compiler_warnings.txt b/Logic/synlog/report/BUS68030_compiler_warnings.txt
index dcae6f0..d0120f2 100644
--- a/Logic/synlog/report/BUS68030_compiler_warnings.txt
+++ b/Logic/synlog/report/BUS68030_compiler_warnings.txt
@@ -1,12 +1,12 @@
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":501:2:501:3|Pruning register CLK_OUT_PRE_33  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":141:32:141:34|Pruning register CLK_REF(1 downto 0)  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":113:29:113:31|Pruning register DTACK_D0  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:34:134:36|Pruning register CLK_000_D4  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Pruning register CLK_000_D3  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_000_D2  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:35:127:37|Pruning register CLK_OUT_NE  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":162:2:162:3|Pruning register CLK_CNT_P(1 downto 0)  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":149:2:149:3|Pruning register CLK_CNT_N(1 downto 0)  
-@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":136:61:136:75|Pruning bit 12 of CLK_000_N_SYNC(12 downto 0) -- not in use ... 
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":496:2:496:3|Pruning register CLK_OUT_PRE_33  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":140:32:140:34|Pruning register CLK_REF(1 downto 0)  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":112:29:112:31|Pruning register DTACK_D0  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Pruning register CLK_000_D4  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_000_D3  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_000_D2  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:35:126:37|Pruning register CLK_OUT_NE  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":161:2:161:3|Pruning register CLK_CNT_P(1 downto 0)  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":148:2:148:3|Pruning register CLK_CNT_N(1 downto 0)  
+@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":135:61:135:75|Pruning bit 12 of CLK_000_N_SYNC(12 downto 0) -- not in use ... 
 @W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":105:36:105:38|Pruning bits 12 to 10 of CLK_000_P_SYNC(12 downto 0) -- not in use ... 
 
diff --git a/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml b/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml
index 1c64237..acb453a 100644
--- a/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml
+++ b/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml
@@ -39,7 +39,7 @@ The file contains the job information from mapper to be displayed as part of the
 <data>96MB</data>
 </info>
 <info name="Date &amp; Time">
-<data type="timestamp">1407616793</data>
+<data type="timestamp">1407621021</data>
 </info>
 </job_info>
 </job_run_status>
diff --git a/Logic/syntmp/run_option.xml b/Logic/syntmp/run_option.xml
index 8ca52cb..316827c 100644
--- a/Logic/syntmp/run_option.xml
+++ b/Logic/syntmp/run_option.xml
@@ -3,7 +3,7 @@
   Synopsys, Inc.
   Version G-2012.09LC-SP1 
   Project file C:\users\matze\documents\github\68030tk\logic\syntmp\run_option.xml
-  Written on Sat Aug 09 22:39:52 2014
+  Written on Sat Aug 09 23:50:20 2014
 
 
 --> 
diff --git a/Logic/synwork/BUS68030_compiler.fdep b/Logic/synwork/BUS68030_compiler.fdep
index bd5fdd1..b842349 100644
--- a/Logic/synwork/BUS68030_compiler.fdep
+++ b/Logic/synwork/BUS68030_compiler.fdep
@@ -10,7 +10,7 @@
 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328
 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328
 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328
-#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1407616783
+#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1407621014
 0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
 
 # Dependency Lists (Uses list)
diff --git a/Logic/synwork/BUS68030_compiler.fdeporig b/Logic/synwork/BUS68030_compiler.fdeporig
index e69944a..f43c939 100644
--- a/Logic/synwork/BUS68030_compiler.fdeporig
+++ b/Logic/synwork/BUS68030_compiler.fdeporig
@@ -10,7 +10,7 @@
 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328
 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328
 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328
-#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1407616783
+#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1407621014
 0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
 
 # Dependency Lists (Uses list)
diff --git a/Logic/synwork/BUS68030_compiler.srs b/Logic/synwork/BUS68030_compiler.srs
index 579eb09b0a3780a1d57d0b431bce386b6772de66..3a757a886e5b084c3b64e255cc635c0c28ae2ad8 100644
GIT binary patch
delta 8308
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diff --git a/Logic/synwork/BUS68030_compiler.tlg b/Logic/synwork/BUS68030_compiler.tlg
index 2174b4b..fff237c 100644
--- a/Logic/synwork/BUS68030_compiler.tlg
+++ b/Logic/synwork/BUS68030_compiler.tlg
@@ -1,17 +1,18 @@
 @N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral 
 Post processing for work.bus68030.behavioral
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":501:2:501:3|Pruning register CLK_OUT_PRE_33  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":141:32:141:34|Pruning register CLK_REF(1 downto 0)  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":113:29:113:31|Pruning register DTACK_D0  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:34:134:36|Pruning register CLK_000_D4  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Pruning register CLK_000_D3  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_000_D2  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:35:127:37|Pruning register CLK_OUT_NE  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":162:2:162:3|Pruning register CLK_CNT_P(1 downto 0)  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":149:2:149:3|Pruning register CLK_CNT_N(1 downto 0)  
-@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":136:61:136:75|Pruning bit 12 of CLK_000_N_SYNC(12 downto 0) -- not in use ... 
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":496:2:496:3|Pruning register CLK_OUT_PRE_33  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":140:32:140:34|Pruning register CLK_REF(1 downto 0)  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":112:29:112:31|Pruning register DTACK_D0  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Pruning register CLK_000_D4  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_000_D3  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_000_D2  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:35:126:37|Pruning register CLK_OUT_NE  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":161:2:161:3|Pruning register CLK_CNT_P(1 downto 0)  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":148:2:148:3|Pruning register CLK_CNT_N(1 downto 0)  
+@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":135:61:135:75|Pruning bit 12 of CLK_000_N_SYNC(12 downto 0) -- not in use ... 
 @W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":105:36:105:38|Pruning bits 12 to 10 of CLK_000_P_SYNC(12 downto 0) -- not in use ... 
-@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":141:32:141:34|Trying to extract state machine for register SM_AMIGA
+@A: CL282 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":102:32:102:34|Feedback mux created for signal CLK_030_H -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
+@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":140:32:140:34|Trying to extract state machine for register SM_AMIGA
 Extracted state machine for register SM_AMIGA
 State machine has 8 reachable states with original encodings of:
    000
@@ -22,7 +23,7 @@ State machine has 8 reachable states with original encodings of:
    101
    110
    111
-@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:34:129:36|Trying to extract state machine for register cpu_est
+@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":128:34:128:36|Trying to extract state machine for register cpu_est
 Extracted state machine for register cpu_est
 State machine has 11 reachable states with original encodings of:
    0000