diff --git a/Logic/68030-68000-bus.vhd b/Logic/68030-68000-bus.vhd index 6744b5b..3e1fd0a 100644 --- a/Logic/68030-68000-bus.vhd +++ b/Logic/68030-68000-bus.vhd @@ -296,12 +296,12 @@ begin -- VMA generation --assert - if(CLK_000_D='0' AND VPA_SYNC='0')then + if(CLK_000_D='0' AND VPA_D='0' AND cpu_est = E4)then VMA_INT <= '0'; end if; --deassert - if(CLK_000_D='1' AND AS_000_INT='1')then + if(CLK_000_D='1' AND AS_000_INT='1' AND cpu_est_d=E1)then VMA_INT <= '1'; end if; @@ -314,7 +314,7 @@ begin end if; when IDLE_N => --68000:S1 wait for rising edge, on a rising CLK_000 look for a amiga adressrobe --AS_000_START <='0'; - if(CLK_000_D='1' )then --sample AS only at the rising edge! + if(CLK_000_D='1' and CLK_000_DD = '0')then --sample AS only at the rising edge! if( AS_030_000_SYNC = '0' )then AS_000_INT <= '0'; if (RW='1' and DS_030 = '0') then --read: set udl/lds @@ -333,18 +333,6 @@ begin end if; end if; when AS_SET_P => --68000:S2 Amiga cycle starts here: since AS is asserted during transition to this state we simply wait here - if (RW='1' and DS_030 = '0') then --read: set udl/lds if ds was not ready - if(A(0)='0') then - UDS_000_INT <= '0'; - else - UDS_000_INT <= '1'; - end if; - if((A(0)='1' OR SIZE(0)='0' OR SIZE(1)='1')) then - LDS_000_INT <= '0'; - else - LDS_000_INT <= '1'; - end if; - end if; if(CLK_000_D='0')then SM_AMIGA<=AS_SET_N; end if; @@ -374,39 +362,34 @@ begin else -- high clock: sample DTACK if(VPA_D = '1' AND DTACK='0') then DTACK_SYNC <= '0'; - elsif(VPA_D='0' AND cpu_est=E4) then --vpa/vma cycle: sync VPA on E3 + elsif(VPA_D='0' AND cpu_est=E9 AND VMA_INT='0') then --vpa/vma cycle: sync VPA on E9: one 7M-clock to latch! VPA_SYNC <= '0'; end if; end if; when DATA_FETCH_N=> --68000:S5 nothing happens here just wait for positive clock - if(CLK_000_D='1')then SM_AMIGA<=DATA_FETCH_P; end if; when DATA_FETCH_P => --68000:S6: READ: here comes the data on the bus! - - if( CLK_000 ='0')then - if( DTACK_SYNC ='0' OR - (VPA_SYNC ='0' and cpu_est=E10 ) )then - SM_AMIGA<=END_CYCLE_N; - --elsif(VPA_SYNC ='0')then - -- SM_AMIGA<=DATA_FETCH_N; --wait for right moment to end vpa-cyclus - end if; + if( CLK_000_D ='0' AND CLK_OUT_PRE='1' + ) then + DSACK_INT<="01"; + SM_AMIGA<=END_CYCLE_N; end if; when END_CYCLE_N =>--68000:S7: Latch/Store data and go to IDLE on high clock if(CLK_000_D='1' and AS_000_INT='1' )then SM_AMIGA<=IDLE_P; - elsif( CLK_000_D='0' AND CLK_OUT_PRE='1' --assert here (next 68030-Clock will be high)! - and AS_030_000_SYNC ='0' -- if the cycle somehow aboarded do not send a dsack! - ) then --timing is everything! - if( (VPA_SYNC ='0' AND CLK_000_CNT > x"0" and RW='0') OR - (VPA_SYNC ='0' AND CLK_000_CNT > x"0" and RW='1') OR - (DTACK_SYNC='0' AND CLK_000_CNT > x"0" and RW='0') OR - (DTACK_SYNC='0' AND CLK_000_CNT > x"0" and RW='1') - )then - DSACK_INT<="01"; - end if; + --elsif( CLK_OUT_PRE='1' --assert here (next 68030-Clock will be high)! + -- and AS_030_000_SYNC ='0' -- if the cycle somehow aboarded do not send a dsack! + -- ) then --timing is everything! + --if( (VPA_SYNC ='0' AND CLK_000_CNT > x"0" and RW='0') OR + -- (VPA_SYNC ='0' AND CLK_000_CNT > x"0" and RW='1') OR + -- (DTACK_SYNC='0' AND CLK_000_CNT > x"0" and RW='0') OR + -- (DTACK_SYNC='0' AND CLK_000_CNT > x"0" and RW='1') + --)then + -- DSACK_INT<="01"; + --end if; end if; end case; diff --git a/Logic/68030_TK.STY b/Logic/68030_TK.STY index 6d689ed..f74ee1f 100644 --- a/Logic/68030_TK.STY +++ b/Logic/68030_TK.STY @@ -1,6 +1,6 @@ -[synthesis-type] -tool=Synplify [STRATEGY-LIST] Normal=True, 1385910337 [TOUCHED-REPORT] Design.tt4File=1400149811 +[synthesis-type] +tool=Synplify diff --git a/Logic/68030_TK.tcl b/Logic/68030_TK.tcl index d75a148..34ea719 100644 --- a/Logic/68030_TK.tcl +++ b/Logic/68030_TK.tcl @@ -115104,3 +115104,4036 @@ if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 6 ########## Tcl recorder end at 05/15/14 19:20:46 ########### + +########## Tcl recorder starts at 05/15/14 21:18:29 ########## + +set version "1.7" +set proj_dir "C:/Users/Matze/Documents/GitHub/68030tk/Logic" +cd $proj_dir + +# Get directory paths +set pver $version +regsub -all {\.} $pver {_} pver +set lscfile "lsc_" +append lscfile $pver ".ini" +set lsvini_dir [lindex [array get env LSC_INI_PATH] 1] +set lsvini_path [file join $lsvini_dir $lscfile] +if {[catch {set fid [open $lsvini_path]} msg]} { + puts "File Open Error: $lsvini_path" + return false +} else {set data [read $fid]; close $fid } +foreach line [split $data '\n'] { + set lline [string tolower $line] + set lline [string trim $lline] + if {[string compare $lline "\[paths\]"] == 0} { set path 1; continue} + if {$path && [regexp {^\[} $lline]} {set path 0; break} + if {$path && [regexp {^bin} $lline]} {set cpld_bin $line; continue} + if {$path && [regexp {^fpgapath} $lline]} {set fpga_dir $line; continue} + if {$path && [regexp {^fpgabinpath} $lline]} {set fpga_bin $line}} + +set cpld_bin [string range $cpld_bin [expr [string first "=" $cpld_bin]+1] end] +regsub -all "\"" $cpld_bin "" cpld_bin +set cpld_bin [file join $cpld_bin] +set install_dir [string range $cpld_bin 0 [expr [string first "ispcpld" $cpld_bin]-2]] +regsub -all "\"" $install_dir "" install_dir +set install_dir [file join $install_dir] +set fpga_dir [string range $fpga_dir [expr [string first "=" $fpga_dir]+1] end] +regsub -all "\"" $fpga_dir "" fpga_dir +set fpga_dir [file join $fpga_dir] +set fpga_bin [string range $fpga_bin [expr [string first "=" $fpga_bin]+1] end] +regsub -all "\"" $fpga_bin "" fpga_bin +set fpga_bin [file join $fpga_bin] + +if {[string match "*$fpga_bin;*" $env(PATH)] == 0 } { + set env(PATH) "$fpga_bin;$env(PATH)" } + +if {[string match "*$cpld_bin;*" $env(PATH)] == 0 } { + set env(PATH) "$cpld_bin;$env(PATH)" } + +lappend auto_path [file join $install_dir "ispcpld" "tcltk" "lib" "ispwidget" "runproc"] +package require runcmd + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 21:18:29 ########### + + +########## Tcl recorder starts at 05/15/14 21:19:32 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 21:19:32 ########### + + +########## Tcl recorder starts at 05/15/14 21:21:04 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 21:21:04 ########### + + +########## Tcl recorder starts at 05/15/14 21:21:32 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 21:21:32 ########### + + +########## Tcl recorder starts at 05/15/14 21:21:36 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 21:21:36 ########### + + +########## Tcl recorder starts at 05/15/14 21:26:46 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 21:26:46 ########### + + +########## Tcl recorder starts at 05/15/14 21:27:02 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 21:27:02 ########### + + +########## Tcl recorder starts at 05/15/14 21:27:06 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 21:27:06 ########### + + +########## Tcl recorder starts at 05/15/14 21:28:18 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 21:28:18 ########### + + +########## Tcl recorder starts at 05/15/14 21:28:29 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 21:28:29 ########### + + +########## Tcl recorder starts at 05/15/14 21:32:45 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 21:32:45 ########### + + +########## Tcl recorder starts at 05/15/14 21:32:59 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 21:32:59 ########### + + +########## Tcl recorder starts at 05/15/14 21:34:04 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 21:34:04 ########### + + +########## Tcl recorder starts at 05/15/14 21:34:09 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 21:34:09 ########### + + +########## Tcl recorder starts at 05/15/14 21:35:23 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 21:35:23 ########### + + +########## Tcl recorder starts at 05/15/14 21:35:26 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 21:35:26 ########### + + +########## Tcl recorder starts at 05/15/14 21:35:47 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 21:35:47 ########### + + +########## Tcl recorder starts at 05/15/14 21:35:49 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 21:35:49 ########### + + +########## Tcl recorder starts at 05/15/14 21:36:10 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 21:36:10 ########### + + +########## Tcl recorder starts at 05/15/14 21:36:46 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 21:36:46 ########### + + +########## Tcl recorder starts at 05/15/14 21:39:06 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 21:39:06 ########### + + +########## Tcl recorder starts at 05/15/14 21:39:13 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 21:39:13 ########### + + +########## Tcl recorder starts at 05/15/14 21:39:20 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 21:39:20 ########### + + +########## Tcl recorder starts at 05/15/14 21:40:40 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 21:40:40 ########### + + +########## Tcl recorder starts at 05/15/14 21:40:47 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 21:40:47 ########### + + +########## Tcl recorder starts at 05/15/14 21:42:07 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 21:42:07 ########### + + +########## Tcl recorder starts at 05/15/14 21:42:21 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 21:42:21 ########### + + +########## Tcl recorder starts at 05/15/14 21:46:42 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 21:46:42 ########### + + +########## Tcl recorder starts at 05/15/14 21:47:09 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 21:47:09 ########### + + +########## Tcl recorder starts at 05/15/14 21:47:49 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 21:47:49 ########### + + +########## Tcl recorder starts at 05/15/14 21:47:55 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 21:47:55 ########### + + +########## Tcl recorder starts at 05/15/14 21:48:11 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 21:48:11 ########### + + +########## Tcl recorder starts at 05/15/14 21:48:15 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 21:48:15 ########### + + +########## Tcl recorder starts at 05/15/14 21:49:47 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 21:49:47 ########### + + +########## Tcl recorder starts at 05/15/14 21:49:55 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 21:49:55 ########### + + +########## Tcl recorder starts at 05/15/14 21:56:26 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 21:56:26 ########### + + +########## Tcl recorder starts at 05/15/14 21:56:37 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 21:56:37 ########### + + +########## Tcl recorder starts at 05/15/14 21:57:43 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 21:57:43 ########### + + +########## Tcl recorder starts at 05/15/14 21:57:54 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 21:57:54 ########### + + +########## Tcl recorder starts at 05/15/14 22:01:09 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 22:01:09 ########### + + +########## Tcl recorder starts at 05/15/14 22:03:13 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 22:03:13 ########### + + +########## Tcl recorder starts at 05/15/14 22:03:17 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 22:03:17 ########### + + +########## Tcl recorder starts at 05/15/14 22:03:25 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 22:03:25 ########### + + +########## Tcl recorder starts at 05/15/14 22:06:12 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 22:06:12 ########### + + +########## Tcl recorder starts at 05/15/14 22:06:16 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 22:06:16 ########### + + +########## Tcl recorder starts at 05/15/14 22:16:15 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 22:16:15 ########### + + +########## Tcl recorder starts at 05/15/14 22:16:20 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 22:16:20 ########### + + +########## Tcl recorder starts at 05/15/14 22:16:30 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 22:16:30 ########### + + +########## Tcl recorder starts at 05/15/14 22:16:31 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 22:16:31 ########### + + +########## Tcl recorder starts at 05/15/14 22:17:09 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 22:17:09 ########### + + +########## Tcl recorder starts at 05/15/14 22:17:20 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/15/14 22:17:20 ########### + diff --git a/Logic/68030_tk.bl2 b/Logic/68030_tk.bl2 index 70fff39..3d5473a 100644 --- a/Logic/68030_tk.bl2 +++ b/Logic/68030_tk.bl2 @@ -1,95 +1,91 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Thu May 15 19:20:52 2014 +#$ DATE Thu May 15 22:17:27 2014 #$ MODULE 68030_tk -#$ PINS 74 A_30_ A_29_ SIZE_1_ A_28_ A_27_ A_31_ A_26_ A_25_ IPL_030_2_ A_24_ A_23_ \ -# IPL_2_ A_22_ A_21_ DSACK_1_ A_20_ A_19_ FC_1_ A_18_ AS_030 A_17_ AS_000 A_16_ DS_030 A_15_ \ -# UDS_000 A_14_ LDS_000 A_13_ CPU_SPACE A_12_ BERR A_11_ BG_030 A_10_ BG_000 A_9_ BGACK_030 \ -# A_8_ BGACK_000 A_7_ CLK_030 A_6_ CLK_000 A_5_ CLK_OSZI A_4_ CLK_DIV_OUT A_3_ CLK_EXP A_2_ \ -# FPU_CS A_1_ DTACK A_0_ AVEC IPL_030_1_ AVEC_EXP IPL_030_0_ E IPL_1_ VPA IPL_0_ VMA DSACK_0_ \ -# RST FC_0_ RESET RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN \ -# SIZE_0_ -#$ NODES 414 a_15__n a_c_22__n a_14__n a_c_23__n a_13__n a_c_24__n a_12__n \ -# inst_BGACK_030_INTreg a_c_25__n inst_CLK_OUT_INTreg a_11__n inst_FPU_CS_INTreg \ -# a_c_26__n cpu_est_3_reg a_10__n inst_VMA_INTreg a_c_27__n gnd_n_n a_9__n cpu_est_1_ \ -# a_c_28__n inst_AS_000_INTreg a_8__n inst_AS_030_000_SYNC a_c_29__n inst_DTACK_SYNC \ -# a_7__n inst_VPA_D a_c_30__n inst_VPA_SYNC a_6__n inst_CLK_000_D a_c_31__n \ -# inst_CLK_000_DD a_5__n inst_CLK_OUT_PRE CPU_SPACE_c vcc_n_n a_4__n cpu_est_0_ \ -# cpu_est_2_ BG_030_c a_3__n CLK_CNT_0_ SM_AMIGA_6_ BG_000DFFSHreg a_2__n SM_AMIGA_7_ \ -# inst_UDS_000_INTreg a_1__n inst_LDS_000_INTreg BGACK_000_c inst_RISING_CLK_AMIGA \ -# DSACK_INT_1_ CLK_030_c inst_DTACK_DMA SM_AMIGA_4_ CLK_000_c SM_AMIGA_3_ SM_AMIGA_5_ \ -# CLK_OSZI_c un1_clk_000_cnt_3__n CLK_000_CNT_0_ CLK_000_CNT_1_ CLK_000_CNT_2_ \ -# CLK_000_CNT_3_ IPL_030DFFSH_0_reg state_machine_un14_as_000_int_n SM_AMIGA_2_ \ -# IPL_030DFFSH_1_reg SM_AMIGA_1_ SM_AMIGA_0_ IPL_030DFFSH_2_reg SM_AMIGA_D_0_ \ -# SM_AMIGA_D_1_ ipl_c_0__n SM_AMIGA_D_2_ clk_exp ipl_c_1__n G_128 G_130 ipl_c_2__n G_132 \ -# dsack_c_1__n DTACK_c RST_c RESETDFFreg RW_c cpu_est_0_0_ fc_c_0__n fc_c_1__n \ -# CLK_OUT_PRE_0 N_123 N_148_i clk_rising_clk_amiga_1_n N_147_i G_122 \ -# VMA_INT_1_sqmuxa_0 G_123 N_170_i G_124 N_171_i DSACK_INT_1_sqmuxa N_161_i N_120 \ -# N_164_i N_144_1 N_165_i N_251 N_168_i N_254 N_166_i N_186 N_167_i un1_clk_000_cnt_0__n \ -# N_169_i N_184 clk_cpu_est_11_0_1__n un1_clk_000_cnt_1__n N_173_i \ -# un1_clk_000_cnt_2__n N_172_i state_machine_un69_clk_000_d_n N_174_i \ -# state_machine_un78_clk_000_d_n clk_cpu_est_11_0_3__n N_149 N_121_i N_119 N_126_0 \ -# N_135 N_123_0 state_machine_un67_clk_000_d_n N_122_0 \ -# state_machine_un80_clk_000_d_n N_142_i N_132 N_143_i N_131 sm_amiga_ns_0_5__n \ -# state_machine_un25_clk_000_d_n N_141_i N_150 N_140_i N_151 sm_amiga_ns_0_4__n N_144 \ -# N_146 LDS_000_INT_1_sqmuxa_i N_143 un1_UDS_000_INT_0_sqmuxa_2_0 N_145 \ -# UDS_000_INT_0_sqmuxa_i state_machine_lds_000_int_8_n un1_UDS_000_INT_0_sqmuxa_i \ -# un1_UDS_000_INT_0_sqmuxa_2 N_124_0 state_machine_uds_000_int_8_n N_136_i \ -# LDS_000_INT_0_sqmuxa state_machine_un42_clk_030_n RISING_CLK_AMIGA_i un1_bg_030 \ -# state_machine_un4_bgack_000_0_n N_133 BG_030_c_i \ -# state_machine_as_030_000_sync_3_n state_machine_un1_clk_030_0_n N_125 \ -# state_machine_un17_clk_030_0_n N_137 un1_as_030_2_0 N_138 N_137_i \ -# DSACK_INT_1_sqmuxa_1 N_138_i un1_as_030_2 state_machine_un17_clk_030_n N_120_i \ -# state_machine_un1_clk_030_n N_125_0 state_machine_un4_bgack_000_n \ -# state_machine_as_030_000_sync_3_2_n VPA_SYNC_1_sqmuxa N_133_i VPA_SYNC_1_sqmuxa_1 \ -# un1_bg_030_0 N_122 a_c_i_0__n AS_000_INT_1_sqmuxa state_machine_uds_000_int_8_0_n \ -# N_136 state_machine_lds_000_int_8_0_n N_124 N_151_i N_130 \ -# state_machine_un15_clk_000_d_n N_146_i un1_UDS_000_INT_0_sqmuxa N_145_i \ -# UDS_000_INT_0_sqmuxa sm_amiga_ns_0_7__n LDS_000_INT_1_sqmuxa N_144_i N_139 N_150_i \ -# N_140 N_126 size_c_i_1__n N_141 state_machine_un25_clk_000_d_i_n N_121 \ -# state_machine_un80_clk_000_d_i_n N_142 state_machine_un67_clk_000_d_i_n \ -# VPA_SYNC_1_sqmuxa_1_0 state_machine_un78_clk_000_d_0_n DTACK_SYNC_1_sqmuxa \ -# clk_rising_clk_amiga_1_i_n DTACK_SYNC_1_sqmuxa_1 N_135_i N_149_2 N_104_i \ -# clk_un3_clk_000_dd_n N_149_i N_164 N_119_0 N_171 clk_000_cnt_i_1__n N_170 \ -# clk_000_cnt_i_0__n clk_cpu_est_11_3__n clk_000_cnt_i_3__n N_174 clk_000_cnt_i_2__n \ -# N_172 state_machine_un69_clk_000_d_0_n N_173 state_machine_un69_clk_000_d_0_1_n \ -# clk_cpu_est_11_1__n state_machine_un69_clk_000_d_0_2_n N_169 \ -# state_machine_un25_clk_000_d_i_1_n N_167 N_116_i_1 N_166 un1_bg_030_0_1 N_168 \ -# un1_bg_030_0_2 N_165 state_machine_as_030_000_sync_3_2_1_n VMA_INT_1_sqmuxa \ -# un1_UDS_000_INT_0_sqmuxa_i_1 N_147 clk_cpu_est_11_0_1_3__n N_148 \ -# clk_cpu_est_11_0_1_1__n RW_i clk_cpu_est_11_0_2_1__n clk_exp_i N_251_1 CLK_000_DD_i \ -# N_251_2 CLK_000_D_i N_251_3 AS_000_INT_i N_251_4 cpu_est_i_0__n N_251_5 \ -# cpu_est_i_2__n N_251_6 cpu_est_i_3__n N_254_1 cpu_est_i_1__n N_254_2 N_149_2_i \ -# DSACK_INT_1_sqmuxa_1_0 VPA_D_i DSACK_INT_1_sqmuxa_2 DTACK_i DSACK_INT_1_sqmuxa_3 \ -# VPA_SYNC_i N_149_1 DTACK_SYNC_i N_149_2_0 AS_030_i N_132_1 DTACK_SYNC_1_sqmuxa_i \ -# N_131_1 DS_030_i state_machine_un42_clk_030_1_n sm_amiga_i_4__n \ -# state_machine_un42_clk_030_2_n sm_amiga_i_6__n state_machine_un42_clk_030_3_n \ -# sm_amiga_i_5__n state_machine_un42_clk_030_4_n N_139_i \ -# state_machine_un42_clk_030_5_n state_machine_un15_clk_000_d_i_n N_142_1 N_130_i \ -# N_130_1 sm_amiga_i_0__n N_130_2 sm_amiga_i_7__n UDS_000_INT_0_sqmuxa_1 \ -# VPA_SYNC_1_sqmuxa_i UDS_000_INT_0_sqmuxa_2 dsack_i_1__n DTACK_SYNC_1_sqmuxa_1_0 \ -# DSACK_INT_1_sqmuxa_i VPA_SYNC_1_sqmuxa_1_1 a_i_18__n VPA_SYNC_1_sqmuxa_2 a_i_16__n \ -# VPA_SYNC_1_sqmuxa_3 a_i_19__n N_171_1 CLK_030_i N_170_1 \ -# state_machine_un42_clk_030_i_n N_174_1 AS_030_000_SYNC_i clk_exp_1 N_131_i \ -# cpu_est_0_1__un3_n N_132_i cpu_est_0_1__un1_n sm_amiga_i_2__n cpu_est_0_1__un0_n \ -# sm_amiga_i_1__n vma_int_0_un3_n sm_amiga_i_3__n vma_int_0_un1_n CLK_000_i \ -# vma_int_0_un0_n a_i_30__n cpu_est_0_3__un3_n a_i_31__n cpu_est_0_3__un1_n a_i_28__n \ -# cpu_est_0_3__un0_n a_i_29__n cpu_est_0_2__un3_n a_i_26__n cpu_est_0_2__un1_n \ -# a_i_27__n cpu_est_0_2__un0_n a_i_24__n dtack_sync_0_un3_n a_i_25__n \ -# dtack_sync_0_un1_n dtack_sync_0_un0_n sm_amiga_d_0_0__un3_n RST_i \ -# sm_amiga_d_0_0__un1_n sm_amiga_d_0_0__un0_n FPU_CS_INT_i bgack_030_int_0_un3_n \ -# CPU_SPACE_i bgack_030_int_0_un1_n BGACK_030_INT_i bgack_030_int_0_un0_n AS_030_c \ -# bg_000_0_un3_n bg_000_0_un1_n bg_000_0_un0_n DS_030_c as_030_000_sync_0_un3_n \ -# as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n fpu_cs_int_0_un3_n size_c_0__n \ -# fpu_cs_int_0_un1_n fpu_cs_int_0_un0_n size_c_1__n dsack_int_0_1__un3_n \ -# dsack_int_0_1__un1_n a_c_0__n dsack_int_0_1__un0_n vpa_sync_0_un3_n \ -# vpa_sync_0_un1_n vpa_sync_0_un0_n as_000_int_0_un3_n as_000_int_0_un1_n \ -# as_000_int_0_un0_n ipl_030_0_2__un3_n ipl_030_0_2__un1_n ipl_030_0_2__un0_n \ -# ipl_030_0_1__un3_n ipl_030_0_1__un1_n ipl_030_0_1__un0_n ipl_030_0_0__un3_n \ -# ipl_030_0_0__un1_n ipl_030_0_0__un0_n sm_amiga_d_0_2__un3_n a_c_16__n \ -# sm_amiga_d_0_2__un1_n sm_amiga_d_0_2__un0_n a_c_17__n sm_amiga_d_0_1__un3_n \ -# sm_amiga_d_0_1__un1_n a_c_18__n sm_amiga_d_0_1__un0_n lds_000_int_0_un3_n \ -# a_c_19__n lds_000_int_0_un1_n lds_000_int_0_un0_n a_c_20__n uds_000_int_0_un3_n \ -# uds_000_int_0_un1_n a_c_21__n uds_000_int_0_un0_n +#$ PINS 74 FC_0_ SIZE_1_ A_31_ IPL_030_2_ IPL_2_ DSACK_1_ FC_1_ AS_030 AS_000 DS_030 \ +# UDS_000 LDS_000 CPU_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 \ +# CLK_OSZI CLK_DIV_OUT SIZE_0_ CLK_EXP A_30_ FPU_CS A_29_ DTACK A_28_ AVEC A_27_ AVEC_EXP \ +# A_26_ E A_25_ VPA A_24_ VMA A_23_ RST A_22_ RESET A_21_ RW A_20_ AMIGA_BUS_ENABLE A_19_ \ +# AMIGA_BUS_DATA_DIR A_18_ AMIGA_BUS_ENABLE_LOW A_17_ CIIN A_16_ A_15_ A_14_ A_13_ A_12_ \ +# A_11_ A_10_ A_9_ A_8_ A_7_ A_6_ A_5_ A_4_ A_3_ A_2_ A_1_ A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ \ +# IPL_0_ DSACK_0_ +#$ NODES 378 a_c_30__n a_c_31__n CPU_SPACE_c inst_BGACK_030_INTreg BG_030_c \ +# inst_CLK_OUT_INTreg inst_FPU_CS_INTreg BG_000DFFSHreg cpu_est_3_reg \ +# inst_VMA_INTreg gnd_n_n BGACK_000_c cpu_est_0_ cpu_est_1_ CLK_030_c cpu_est_d_0_ \ +# cpu_est_d_3_ CLK_000_c inst_AS_000_INTreg inst_AS_030_000_SYNC CLK_OSZI_c \ +# inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D inst_CLK_000_DD \ +# IPL_030DFFSH_0_reg inst_CLK_OUT_PRE vcc_n_n IPL_030DFFSH_1_reg cpu_est_d_1_ \ +# cpu_est_d_2_ IPL_030DFFSH_2_reg cpu_est_2_ CLK_CNT_0_ ipl_c_0__n SM_AMIGA_6_ \ +# SM_AMIGA_7_ ipl_c_1__n inst_UDS_000_INTreg inst_LDS_000_INTreg ipl_c_2__n \ +# inst_RISING_CLK_AMIGA state_machine_un57_clk_000_d_n dsack_c_1__n SM_AMIGA_1_ \ +# DSACK_INT_1_ DTACK_c inst_DTACK_DMA SM_AMIGA_4_ SM_AMIGA_3_ \ +# state_machine_un13_as_000_int_n SM_AMIGA_5_ SM_AMIGA_2_ SM_AMIGA_0_ SM_AMIGA_D_0_ \ +# RST_c SM_AMIGA_D_1_ SM_AMIGA_D_2_ RESETDFFreg clk_exp RW_c fc_c_0__n fc_c_1__n \ +# state_machine_un57_clk_000_d_0_n N_161_i a_c_i_0__n \ +# state_machine_uds_000_int_8_0_n state_machine_lds_000_int_8_0_n N_113_i \ +# cpu_est_0_0_ sm_amiga_ns_0_2__n N_118_i N_117_i sm_amiga_ns_0_5__n N_123_i \ +# CLK_OUT_PRE_0 N_119_i N_120_i sm_amiga_ns_0_7__n CLK_OUT_PRE_i N_106 N_102_0 N_107 \ +# size_c_i_1__n clk_un3_clk_000_dd_n state_machine_un31_clk_000_d_i_n \ +# clk_cpu_est_11_1__n RISING_CLK_AMIGA_i clk_cpu_est_11_3__n \ +# state_machine_un4_bgack_000_0_n G_98 BG_030_c_i G_99 state_machine_un1_clk_030_0_n \ +# G_100 state_machine_un17_clk_030_0_n N_161 un1_as_030_2_0 N_114 \ +# state_machine_as_030_000_sync_3_2_n N_109 N_109_i N_111 un1_bg_030_0 N_112 N_111_i \ +# N_122 N_122_i N_115 N_101 N_147_i N_116 clk_cpu_est_11_0_3__n N_124 N_145_i N_139 \ +# N_146_i N_137 N_142_i N_140 clk_cpu_est_11_0_1__n N_141 N_140_i N_136 N_139_i N_142 \ +# N_141_i N_145 N_138_i N_138 N_137_i N_146 N_136_i N_143 N_143_i N_144 N_144_i \ +# UDS_000_INT_0_sqmuxa N_134_i UDS_000_INT_0_sqmuxa_1 N_101_0 N_147 N_115_i N_147_1 \ +# N_116_i state_machine_un13_clk_000_d_1_n N_186 N_124_i N_189 \ +# state_machine_un42_clk_030_n N_112_i un1_bg_030 sm_amiga_ns_0_0__n \ +# state_machine_as_030_000_sync_3_n N_86_i_1 un1_as_030_2 un1_bg_030_0_1 \ +# state_machine_un17_clk_030_n un1_bg_030_0_2 state_machine_un1_clk_030_n \ +# state_machine_as_030_000_sync_3_2_1_n state_machine_un4_bgack_000_n \ +# state_machine_un31_clk_000_d_i_1_n N_108 N_186_1 state_machine_un31_clk_000_d_n \ +# N_186_2 state_machine_un13_clk_000_d_n N_186_3 state_machine_un13_clk_000_d_4_n \ +# N_186_4 state_machine_un8_clk_000_d_n N_186_5 DTACK_SYNC_1_sqmuxa N_186_6 \ +# VPA_SYNC_1_sqmuxa_1_0 N_189_1 VPA_SYNC_1_sqmuxa N_189_2 N_123 \ +# clk_cpu_est_11_0_1_1__n N_118 clk_cpu_est_11_0_2_1__n N_110 \ +# clk_cpu_est_11_0_1_3__n N_102 N_143_1 N_120 N_144_1 N_119 N_106_1 N_117 N_106_2 N_113 \ +# N_107_1 state_machine_lds_000_int_8_n UDS_000_INT_0_sqmuxa_1_1 \ +# state_machine_uds_000_int_8_n UDS_000_INT_0_sqmuxa_1_2 DTACK_SYNC_1_sqmuxa_1 \ +# UDS_000_INT_0_sqmuxa_1_3 un2_clk_030_1 UDS_000_INT_0_sqmuxa_1_0 \ +# VPA_SYNC_1_sqmuxa_1 UDS_000_INT_0_sqmuxa_2 AS_000_INT_1_sqmuxa \ +# state_machine_un42_clk_030_1_n VMA_INT_1_sqmuxa state_machine_un42_clk_030_2_n \ +# DSACK_INT_1_sqmuxa state_machine_un42_clk_030_3_n RW_i \ +# state_machine_un42_clk_030_4_n clk_exp_i state_machine_un42_clk_030_5_n \ +# DTACK_SYNC_1_sqmuxa_i state_machine_un13_clk_000_d_1_0_n N_114_i \ +# state_machine_un13_clk_000_d_4_1_n VPA_SYNC_1_sqmuxa_i \ +# state_machine_un8_clk_000_d_1_n N_110_i state_machine_un8_clk_000_d_2_n N_108_i \ +# state_machine_un8_clk_000_d_3_n cpu_est_d_i_3__n state_machine_un8_clk_000_d_4_n \ +# cpu_est_d_i_0__n DTACK_SYNC_1_sqmuxa_1_0 CLK_000_D_i VPA_SYNC_1_sqmuxa_1_1 \ +# AS_030_i VPA_SYNC_1_sqmuxa_2 AS_000_INT_i VPA_SYNC_1_sqmuxa_3 dsack_i_1__n \ +# VPA_SYNC_1_sqmuxa_4 state_machine_un13_clk_000_d_i_n N_108_1 \ +# state_machine_un8_clk_000_d_i_n N_118_1 state_machine_un13_clk_000_d_1_i_n \ +# N_110_1 sm_amiga_i_1__n clk_exp_1 sm_amiga_i_2__n sm_amiga_d_0_2__un3_n \ +# sm_amiga_i_0__n sm_amiga_d_0_2__un1_n sm_amiga_i_3__n sm_amiga_d_0_2__un0_n \ +# VPA_D_i dsack_int_0_1__un3_n VMA_INT_i dsack_int_0_1__un1_n DTACK_i \ +# dsack_int_0_1__un0_n cpu_est_i_3__n vma_int_0_un3_n a_i_18__n vma_int_0_un1_n \ +# a_i_16__n vma_int_0_un0_n a_i_19__n vpa_sync_0_un3_n CLK_030_i vpa_sync_0_un1_n \ +# state_machine_un42_clk_030_i_n vpa_sync_0_un0_n DS_030_i as_000_int_0_un3_n \ +# cpu_est_i_1__n as_000_int_0_un1_n AS_030_000_SYNC_i as_000_int_0_un0_n \ +# cpu_est_i_0__n dtack_sync_0_un3_n sm_amiga_i_4__n dtack_sync_0_un1_n \ +# sm_amiga_i_6__n dtack_sync_0_un0_n cpu_est_i_2__n lds_000_int_0_un3_n \ +# UDS_000_INT_0_sqmuxa_1_i lds_000_int_0_un1_n UDS_000_INT_0_sqmuxa_i \ +# lds_000_int_0_un0_n sm_amiga_i_5__n uds_000_int_0_un3_n CLK_000_DD_i \ +# uds_000_int_0_un1_n sm_amiga_i_7__n uds_000_int_0_un0_n a_i_30__n bg_000_0_un3_n \ +# a_i_31__n bg_000_0_un1_n a_i_28__n bg_000_0_un0_n a_i_29__n as_030_000_sync_0_un3_n \ +# a_i_26__n as_030_000_sync_0_un1_n a_i_27__n as_030_000_sync_0_un0_n a_i_24__n \ +# fpu_cs_int_0_un3_n a_i_25__n fpu_cs_int_0_un1_n fpu_cs_int_0_un0_n \ +# ipl_030_0_2__un3_n RST_i ipl_030_0_2__un1_n N_107_i ipl_030_0_2__un0_n N_106_i \ +# ipl_030_0_1__un3_n FPU_CS_INT_i ipl_030_0_1__un1_n CPU_SPACE_i ipl_030_0_1__un0_n \ +# BGACK_030_INT_i ipl_030_0_0__un3_n AS_030_c ipl_030_0_0__un1_n ipl_030_0_0__un0_n \ +# bgack_030_int_0_un3_n DS_030_c bgack_030_int_0_un1_n bgack_030_int_0_un0_n \ +# sm_amiga_d_0_0__un3_n sm_amiga_d_0_0__un1_n size_c_0__n sm_amiga_d_0_0__un0_n \ +# sm_amiga_d_0_1__un3_n size_c_1__n sm_amiga_d_0_1__un1_n sm_amiga_d_0_1__un0_n \ +# a_c_0__n cpu_est_0_1__un3_n cpu_est_0_1__un1_n cpu_est_0_1__un0_n \ +# cpu_est_0_2__un3_n cpu_est_0_2__un1_n cpu_est_0_2__un0_n cpu_est_0_3__un3_n \ +# cpu_est_0_3__un1_n cpu_est_0_3__un0_n a_15__n a_14__n a_13__n a_12__n a_c_16__n \ +# a_11__n a_c_17__n a_10__n a_c_18__n a_9__n a_c_19__n a_8__n a_c_20__n a_7__n a_c_21__n \ +# a_6__n a_c_22__n a_5__n a_c_23__n a_4__n a_c_24__n a_3__n a_c_25__n a_2__n a_c_26__n \ +# a_1__n a_c_27__n a_c_28__n a_c_29__n .model bus68030 .inputs SIZE_1_.BLIF A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF AS_030.BLIF DS_030.BLIF \ CPU_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF \ @@ -99,244 +95,246 @@ A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF A_15_.BLIF \ A_14_.BLIF A_13_.BLIF A_12_.BLIF A_11_.BLIF A_10_.BLIF A_9_.BLIF A_8_.BLIF \ A_7_.BLIF A_6_.BLIF A_5_.BLIF A_4_.BLIF A_3_.BLIF A_2_.BLIF A_1_.BLIF \ A_0_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF DSACK_1_.BLIF DTACK.BLIF \ -DSACK_0_.BLIF a_15__n.BLIF a_c_22__n.BLIF a_14__n.BLIF a_c_23__n.BLIF \ -a_13__n.BLIF a_c_24__n.BLIF a_12__n.BLIF inst_BGACK_030_INTreg.BLIF \ -a_c_25__n.BLIF inst_CLK_OUT_INTreg.BLIF a_11__n.BLIF inst_FPU_CS_INTreg.BLIF \ -a_c_26__n.BLIF cpu_est_3_reg.BLIF a_10__n.BLIF inst_VMA_INTreg.BLIF \ -a_c_27__n.BLIF gnd_n_n.BLIF a_9__n.BLIF cpu_est_1_.BLIF a_c_28__n.BLIF \ -inst_AS_000_INTreg.BLIF a_8__n.BLIF inst_AS_030_000_SYNC.BLIF a_c_29__n.BLIF \ -inst_DTACK_SYNC.BLIF a_7__n.BLIF inst_VPA_D.BLIF a_c_30__n.BLIF \ -inst_VPA_SYNC.BLIF a_6__n.BLIF inst_CLK_000_D.BLIF a_c_31__n.BLIF \ -inst_CLK_000_DD.BLIF a_5__n.BLIF inst_CLK_OUT_PRE.BLIF CPU_SPACE_c.BLIF \ -vcc_n_n.BLIF a_4__n.BLIF cpu_est_0_.BLIF cpu_est_2_.BLIF BG_030_c.BLIF \ -a_3__n.BLIF CLK_CNT_0_.BLIF SM_AMIGA_6_.BLIF BG_000DFFSHreg.BLIF a_2__n.BLIF \ -SM_AMIGA_7_.BLIF inst_UDS_000_INTreg.BLIF a_1__n.BLIF inst_LDS_000_INTreg.BLIF \ -BGACK_000_c.BLIF inst_RISING_CLK_AMIGA.BLIF DSACK_INT_1_.BLIF CLK_030_c.BLIF \ -inst_DTACK_DMA.BLIF SM_AMIGA_4_.BLIF CLK_000_c.BLIF SM_AMIGA_3_.BLIF \ -SM_AMIGA_5_.BLIF CLK_OSZI_c.BLIF un1_clk_000_cnt_3__n.BLIF CLK_000_CNT_0_.BLIF \ -CLK_000_CNT_1_.BLIF CLK_000_CNT_2_.BLIF CLK_000_CNT_3_.BLIF \ -IPL_030DFFSH_0_reg.BLIF state_machine_un14_as_000_int_n.BLIF SM_AMIGA_2_.BLIF \ -IPL_030DFFSH_1_reg.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_0_.BLIF \ -IPL_030DFFSH_2_reg.BLIF SM_AMIGA_D_0_.BLIF SM_AMIGA_D_1_.BLIF ipl_c_0__n.BLIF \ -SM_AMIGA_D_2_.BLIF clk_exp.BLIF ipl_c_1__n.BLIF G_128.BLIF G_130.BLIF \ -ipl_c_2__n.BLIF G_132.BLIF dsack_c_1__n.BLIF DTACK_c.BLIF RST_c.BLIF \ -RESETDFFreg.BLIF RW_c.BLIF cpu_est_0_0_.BLIF fc_c_0__n.BLIF fc_c_1__n.BLIF \ -CLK_OUT_PRE_0.BLIF N_123.BLIF N_148_i.BLIF clk_rising_clk_amiga_1_n.BLIF \ -N_147_i.BLIF G_122.BLIF VMA_INT_1_sqmuxa_0.BLIF G_123.BLIF N_170_i.BLIF \ -G_124.BLIF N_171_i.BLIF DSACK_INT_1_sqmuxa.BLIF N_161_i.BLIF N_120.BLIF \ -N_164_i.BLIF N_144_1.BLIF N_165_i.BLIF N_251.BLIF N_168_i.BLIF N_254.BLIF \ -N_166_i.BLIF N_186.BLIF N_167_i.BLIF un1_clk_000_cnt_0__n.BLIF N_169_i.BLIF \ -N_184.BLIF clk_cpu_est_11_0_1__n.BLIF un1_clk_000_cnt_1__n.BLIF N_173_i.BLIF \ -un1_clk_000_cnt_2__n.BLIF N_172_i.BLIF state_machine_un69_clk_000_d_n.BLIF \ -N_174_i.BLIF state_machine_un78_clk_000_d_n.BLIF clk_cpu_est_11_0_3__n.BLIF \ -N_149.BLIF N_121_i.BLIF N_119.BLIF N_126_0.BLIF N_135.BLIF N_123_0.BLIF \ -state_machine_un67_clk_000_d_n.BLIF N_122_0.BLIF \ -state_machine_un80_clk_000_d_n.BLIF N_142_i.BLIF N_132.BLIF N_143_i.BLIF \ -N_131.BLIF sm_amiga_ns_0_5__n.BLIF state_machine_un25_clk_000_d_n.BLIF \ -N_141_i.BLIF N_150.BLIF N_140_i.BLIF N_151.BLIF sm_amiga_ns_0_4__n.BLIF \ -N_144.BLIF N_146.BLIF LDS_000_INT_1_sqmuxa_i.BLIF N_143.BLIF \ -un1_UDS_000_INT_0_sqmuxa_2_0.BLIF N_145.BLIF UDS_000_INT_0_sqmuxa_i.BLIF \ -state_machine_lds_000_int_8_n.BLIF un1_UDS_000_INT_0_sqmuxa_i.BLIF \ -un1_UDS_000_INT_0_sqmuxa_2.BLIF N_124_0.BLIF \ -state_machine_uds_000_int_8_n.BLIF N_136_i.BLIF LDS_000_INT_0_sqmuxa.BLIF \ -state_machine_un42_clk_030_n.BLIF RISING_CLK_AMIGA_i.BLIF un1_bg_030.BLIF \ -state_machine_un4_bgack_000_0_n.BLIF N_133.BLIF BG_030_c_i.BLIF \ -state_machine_as_030_000_sync_3_n.BLIF state_machine_un1_clk_030_0_n.BLIF \ -N_125.BLIF state_machine_un17_clk_030_0_n.BLIF N_137.BLIF un1_as_030_2_0.BLIF \ -N_138.BLIF N_137_i.BLIF DSACK_INT_1_sqmuxa_1.BLIF N_138_i.BLIF \ -un1_as_030_2.BLIF state_machine_un17_clk_030_n.BLIF N_120_i.BLIF \ -state_machine_un1_clk_030_n.BLIF N_125_0.BLIF \ -state_machine_un4_bgack_000_n.BLIF state_machine_as_030_000_sync_3_2_n.BLIF \ -VPA_SYNC_1_sqmuxa.BLIF N_133_i.BLIF VPA_SYNC_1_sqmuxa_1.BLIF un1_bg_030_0.BLIF \ -N_122.BLIF a_c_i_0__n.BLIF AS_000_INT_1_sqmuxa.BLIF \ -state_machine_uds_000_int_8_0_n.BLIF N_136.BLIF \ -state_machine_lds_000_int_8_0_n.BLIF N_124.BLIF N_151_i.BLIF N_130.BLIF \ -state_machine_un15_clk_000_d_n.BLIF N_146_i.BLIF un1_UDS_000_INT_0_sqmuxa.BLIF \ -N_145_i.BLIF UDS_000_INT_0_sqmuxa.BLIF sm_amiga_ns_0_7__n.BLIF \ -LDS_000_INT_1_sqmuxa.BLIF N_144_i.BLIF N_139.BLIF N_150_i.BLIF N_140.BLIF \ -N_126.BLIF size_c_i_1__n.BLIF N_141.BLIF state_machine_un25_clk_000_d_i_n.BLIF \ -N_121.BLIF state_machine_un80_clk_000_d_i_n.BLIF N_142.BLIF \ -state_machine_un67_clk_000_d_i_n.BLIF VPA_SYNC_1_sqmuxa_1_0.BLIF \ -state_machine_un78_clk_000_d_0_n.BLIF DTACK_SYNC_1_sqmuxa.BLIF \ -clk_rising_clk_amiga_1_i_n.BLIF DTACK_SYNC_1_sqmuxa_1.BLIF N_135_i.BLIF \ -N_149_2.BLIF N_104_i.BLIF clk_un3_clk_000_dd_n.BLIF N_149_i.BLIF N_164.BLIF \ -N_119_0.BLIF N_171.BLIF clk_000_cnt_i_1__n.BLIF N_170.BLIF \ -clk_000_cnt_i_0__n.BLIF clk_cpu_est_11_3__n.BLIF clk_000_cnt_i_3__n.BLIF \ -N_174.BLIF clk_000_cnt_i_2__n.BLIF N_172.BLIF \ -state_machine_un69_clk_000_d_0_n.BLIF N_173.BLIF \ -state_machine_un69_clk_000_d_0_1_n.BLIF clk_cpu_est_11_1__n.BLIF \ -state_machine_un69_clk_000_d_0_2_n.BLIF N_169.BLIF \ -state_machine_un25_clk_000_d_i_1_n.BLIF N_167.BLIF N_116_i_1.BLIF N_166.BLIF \ -un1_bg_030_0_1.BLIF N_168.BLIF un1_bg_030_0_2.BLIF N_165.BLIF \ -state_machine_as_030_000_sync_3_2_1_n.BLIF VMA_INT_1_sqmuxa.BLIF \ -un1_UDS_000_INT_0_sqmuxa_i_1.BLIF N_147.BLIF clk_cpu_est_11_0_1_3__n.BLIF \ -N_148.BLIF clk_cpu_est_11_0_1_1__n.BLIF RW_i.BLIF clk_cpu_est_11_0_2_1__n.BLIF \ -clk_exp_i.BLIF N_251_1.BLIF CLK_000_DD_i.BLIF N_251_2.BLIF CLK_000_D_i.BLIF \ -N_251_3.BLIF AS_000_INT_i.BLIF N_251_4.BLIF cpu_est_i_0__n.BLIF N_251_5.BLIF \ -cpu_est_i_2__n.BLIF N_251_6.BLIF cpu_est_i_3__n.BLIF N_254_1.BLIF \ -cpu_est_i_1__n.BLIF N_254_2.BLIF N_149_2_i.BLIF DSACK_INT_1_sqmuxa_1_0.BLIF \ -VPA_D_i.BLIF DSACK_INT_1_sqmuxa_2.BLIF DTACK_i.BLIF DSACK_INT_1_sqmuxa_3.BLIF \ -VPA_SYNC_i.BLIF N_149_1.BLIF DTACK_SYNC_i.BLIF N_149_2_0.BLIF AS_030_i.BLIF \ -N_132_1.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF N_131_1.BLIF DS_030_i.BLIF \ -state_machine_un42_clk_030_1_n.BLIF sm_amiga_i_4__n.BLIF \ -state_machine_un42_clk_030_2_n.BLIF sm_amiga_i_6__n.BLIF \ -state_machine_un42_clk_030_3_n.BLIF sm_amiga_i_5__n.BLIF \ -state_machine_un42_clk_030_4_n.BLIF N_139_i.BLIF \ -state_machine_un42_clk_030_5_n.BLIF state_machine_un15_clk_000_d_i_n.BLIF \ -N_142_1.BLIF N_130_i.BLIF N_130_1.BLIF sm_amiga_i_0__n.BLIF N_130_2.BLIF \ -sm_amiga_i_7__n.BLIF UDS_000_INT_0_sqmuxa_1.BLIF VPA_SYNC_1_sqmuxa_i.BLIF \ -UDS_000_INT_0_sqmuxa_2.BLIF dsack_i_1__n.BLIF DTACK_SYNC_1_sqmuxa_1_0.BLIF \ -DSACK_INT_1_sqmuxa_i.BLIF VPA_SYNC_1_sqmuxa_1_1.BLIF a_i_18__n.BLIF \ -VPA_SYNC_1_sqmuxa_2.BLIF a_i_16__n.BLIF VPA_SYNC_1_sqmuxa_3.BLIF \ -a_i_19__n.BLIF N_171_1.BLIF CLK_030_i.BLIF N_170_1.BLIF \ -state_machine_un42_clk_030_i_n.BLIF N_174_1.BLIF AS_030_000_SYNC_i.BLIF \ -clk_exp_1.BLIF N_131_i.BLIF cpu_est_0_1__un3_n.BLIF N_132_i.BLIF \ -cpu_est_0_1__un1_n.BLIF sm_amiga_i_2__n.BLIF cpu_est_0_1__un0_n.BLIF \ -sm_amiga_i_1__n.BLIF vma_int_0_un3_n.BLIF sm_amiga_i_3__n.BLIF \ -vma_int_0_un1_n.BLIF CLK_000_i.BLIF vma_int_0_un0_n.BLIF a_i_30__n.BLIF \ -cpu_est_0_3__un3_n.BLIF a_i_31__n.BLIF cpu_est_0_3__un1_n.BLIF a_i_28__n.BLIF \ -cpu_est_0_3__un0_n.BLIF a_i_29__n.BLIF cpu_est_0_2__un3_n.BLIF a_i_26__n.BLIF \ -cpu_est_0_2__un1_n.BLIF a_i_27__n.BLIF cpu_est_0_2__un0_n.BLIF a_i_24__n.BLIF \ -dtack_sync_0_un3_n.BLIF a_i_25__n.BLIF dtack_sync_0_un1_n.BLIF \ -dtack_sync_0_un0_n.BLIF sm_amiga_d_0_0__un3_n.BLIF RST_i.BLIF \ -sm_amiga_d_0_0__un1_n.BLIF sm_amiga_d_0_0__un0_n.BLIF FPU_CS_INT_i.BLIF \ -bgack_030_int_0_un3_n.BLIF CPU_SPACE_i.BLIF bgack_030_int_0_un1_n.BLIF \ -BGACK_030_INT_i.BLIF bgack_030_int_0_un0_n.BLIF AS_030_c.BLIF \ -bg_000_0_un3_n.BLIF bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF DS_030_c.BLIF \ -as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un1_n.BLIF \ -as_030_000_sync_0_un0_n.BLIF fpu_cs_int_0_un3_n.BLIF size_c_0__n.BLIF \ -fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF size_c_1__n.BLIF \ -dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un1_n.BLIF a_c_0__n.BLIF \ -dsack_int_0_1__un0_n.BLIF vpa_sync_0_un3_n.BLIF vpa_sync_0_un1_n.BLIF \ -vpa_sync_0_un0_n.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un1_n.BLIF \ -as_000_int_0_un0_n.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un1_n.BLIF \ -ipl_030_0_2__un0_n.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un1_n.BLIF \ -ipl_030_0_1__un0_n.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un1_n.BLIF \ -ipl_030_0_0__un0_n.BLIF sm_amiga_d_0_2__un3_n.BLIF a_c_16__n.BLIF \ -sm_amiga_d_0_2__un1_n.BLIF sm_amiga_d_0_2__un0_n.BLIF a_c_17__n.BLIF \ -sm_amiga_d_0_1__un3_n.BLIF sm_amiga_d_0_1__un1_n.BLIF a_c_18__n.BLIF \ -sm_amiga_d_0_1__un0_n.BLIF lds_000_int_0_un3_n.BLIF a_c_19__n.BLIF \ -lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF a_c_20__n.BLIF \ -uds_000_int_0_un3_n.BLIF uds_000_int_0_un1_n.BLIF a_c_21__n.BLIF \ -uds_000_int_0_un0_n.BLIF DSACK_1_.PIN.BLIF DTACK.PIN.BLIF +DSACK_0_.BLIF a_c_30__n.BLIF a_c_31__n.BLIF CPU_SPACE_c.BLIF \ +inst_BGACK_030_INTreg.BLIF BG_030_c.BLIF inst_CLK_OUT_INTreg.BLIF \ +inst_FPU_CS_INTreg.BLIF BG_000DFFSHreg.BLIF cpu_est_3_reg.BLIF \ +inst_VMA_INTreg.BLIF gnd_n_n.BLIF BGACK_000_c.BLIF cpu_est_0_.BLIF \ +cpu_est_1_.BLIF CLK_030_c.BLIF cpu_est_d_0_.BLIF cpu_est_d_3_.BLIF \ +CLK_000_c.BLIF inst_AS_000_INTreg.BLIF inst_AS_030_000_SYNC.BLIF \ +CLK_OSZI_c.BLIF inst_DTACK_SYNC.BLIF inst_VPA_D.BLIF inst_VPA_SYNC.BLIF \ +inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF IPL_030DFFSH_0_reg.BLIF \ +inst_CLK_OUT_PRE.BLIF vcc_n_n.BLIF IPL_030DFFSH_1_reg.BLIF cpu_est_d_1_.BLIF \ +cpu_est_d_2_.BLIF IPL_030DFFSH_2_reg.BLIF cpu_est_2_.BLIF CLK_CNT_0_.BLIF \ +ipl_c_0__n.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_7_.BLIF ipl_c_1__n.BLIF \ +inst_UDS_000_INTreg.BLIF inst_LDS_000_INTreg.BLIF ipl_c_2__n.BLIF \ +inst_RISING_CLK_AMIGA.BLIF state_machine_un57_clk_000_d_n.BLIF \ +dsack_c_1__n.BLIF SM_AMIGA_1_.BLIF DSACK_INT_1_.BLIF DTACK_c.BLIF \ +inst_DTACK_DMA.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_3_.BLIF \ +state_machine_un13_as_000_int_n.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_2_.BLIF \ +SM_AMIGA_0_.BLIF SM_AMIGA_D_0_.BLIF RST_c.BLIF SM_AMIGA_D_1_.BLIF \ +SM_AMIGA_D_2_.BLIF RESETDFFreg.BLIF clk_exp.BLIF RW_c.BLIF fc_c_0__n.BLIF \ +fc_c_1__n.BLIF state_machine_un57_clk_000_d_0_n.BLIF N_161_i.BLIF \ +a_c_i_0__n.BLIF state_machine_uds_000_int_8_0_n.BLIF \ +state_machine_lds_000_int_8_0_n.BLIF N_113_i.BLIF cpu_est_0_0_.BLIF \ +sm_amiga_ns_0_2__n.BLIF N_118_i.BLIF N_117_i.BLIF sm_amiga_ns_0_5__n.BLIF \ +N_123_i.BLIF CLK_OUT_PRE_0.BLIF N_119_i.BLIF N_120_i.BLIF \ +sm_amiga_ns_0_7__n.BLIF CLK_OUT_PRE_i.BLIF N_106.BLIF N_102_0.BLIF N_107.BLIF \ +size_c_i_1__n.BLIF clk_un3_clk_000_dd_n.BLIF \ +state_machine_un31_clk_000_d_i_n.BLIF clk_cpu_est_11_1__n.BLIF \ +RISING_CLK_AMIGA_i.BLIF clk_cpu_est_11_3__n.BLIF \ +state_machine_un4_bgack_000_0_n.BLIF G_98.BLIF BG_030_c_i.BLIF G_99.BLIF \ +state_machine_un1_clk_030_0_n.BLIF G_100.BLIF \ +state_machine_un17_clk_030_0_n.BLIF N_161.BLIF un1_as_030_2_0.BLIF N_114.BLIF \ +state_machine_as_030_000_sync_3_2_n.BLIF N_109.BLIF N_109_i.BLIF N_111.BLIF \ +un1_bg_030_0.BLIF N_112.BLIF N_111_i.BLIF N_122.BLIF N_122_i.BLIF N_115.BLIF \ +N_101.BLIF N_147_i.BLIF N_116.BLIF clk_cpu_est_11_0_3__n.BLIF N_124.BLIF \ +N_145_i.BLIF N_139.BLIF N_146_i.BLIF N_137.BLIF N_142_i.BLIF N_140.BLIF \ +clk_cpu_est_11_0_1__n.BLIF N_141.BLIF N_140_i.BLIF N_136.BLIF N_139_i.BLIF \ +N_142.BLIF N_141_i.BLIF N_145.BLIF N_138_i.BLIF N_138.BLIF N_137_i.BLIF \ +N_146.BLIF N_136_i.BLIF N_143.BLIF N_143_i.BLIF N_144.BLIF N_144_i.BLIF \ +UDS_000_INT_0_sqmuxa.BLIF N_134_i.BLIF UDS_000_INT_0_sqmuxa_1.BLIF \ +N_101_0.BLIF N_147.BLIF N_115_i.BLIF N_147_1.BLIF N_116_i.BLIF \ +state_machine_un13_clk_000_d_1_n.BLIF N_186.BLIF N_124_i.BLIF N_189.BLIF \ +state_machine_un42_clk_030_n.BLIF N_112_i.BLIF un1_bg_030.BLIF \ +sm_amiga_ns_0_0__n.BLIF state_machine_as_030_000_sync_3_n.BLIF N_86_i_1.BLIF \ +un1_as_030_2.BLIF un1_bg_030_0_1.BLIF state_machine_un17_clk_030_n.BLIF \ +un1_bg_030_0_2.BLIF state_machine_un1_clk_030_n.BLIF \ +state_machine_as_030_000_sync_3_2_1_n.BLIF state_machine_un4_bgack_000_n.BLIF \ +state_machine_un31_clk_000_d_i_1_n.BLIF N_108.BLIF N_186_1.BLIF \ +state_machine_un31_clk_000_d_n.BLIF N_186_2.BLIF \ +state_machine_un13_clk_000_d_n.BLIF N_186_3.BLIF \ +state_machine_un13_clk_000_d_4_n.BLIF N_186_4.BLIF \ +state_machine_un8_clk_000_d_n.BLIF N_186_5.BLIF DTACK_SYNC_1_sqmuxa.BLIF \ +N_186_6.BLIF VPA_SYNC_1_sqmuxa_1_0.BLIF N_189_1.BLIF VPA_SYNC_1_sqmuxa.BLIF \ +N_189_2.BLIF N_123.BLIF clk_cpu_est_11_0_1_1__n.BLIF N_118.BLIF \ +clk_cpu_est_11_0_2_1__n.BLIF N_110.BLIF clk_cpu_est_11_0_1_3__n.BLIF \ +N_102.BLIF N_143_1.BLIF N_120.BLIF N_144_1.BLIF N_119.BLIF N_106_1.BLIF \ +N_117.BLIF N_106_2.BLIF N_113.BLIF N_107_1.BLIF \ +state_machine_lds_000_int_8_n.BLIF UDS_000_INT_0_sqmuxa_1_1.BLIF \ +state_machine_uds_000_int_8_n.BLIF UDS_000_INT_0_sqmuxa_1_2.BLIF \ +DTACK_SYNC_1_sqmuxa_1.BLIF UDS_000_INT_0_sqmuxa_1_3.BLIF un2_clk_030_1.BLIF \ +UDS_000_INT_0_sqmuxa_1_0.BLIF VPA_SYNC_1_sqmuxa_1.BLIF \ +UDS_000_INT_0_sqmuxa_2.BLIF AS_000_INT_1_sqmuxa.BLIF \ +state_machine_un42_clk_030_1_n.BLIF VMA_INT_1_sqmuxa.BLIF \ +state_machine_un42_clk_030_2_n.BLIF DSACK_INT_1_sqmuxa.BLIF \ +state_machine_un42_clk_030_3_n.BLIF RW_i.BLIF \ +state_machine_un42_clk_030_4_n.BLIF clk_exp_i.BLIF \ +state_machine_un42_clk_030_5_n.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF \ +state_machine_un13_clk_000_d_1_0_n.BLIF N_114_i.BLIF \ +state_machine_un13_clk_000_d_4_1_n.BLIF VPA_SYNC_1_sqmuxa_i.BLIF \ +state_machine_un8_clk_000_d_1_n.BLIF N_110_i.BLIF \ +state_machine_un8_clk_000_d_2_n.BLIF N_108_i.BLIF \ +state_machine_un8_clk_000_d_3_n.BLIF cpu_est_d_i_3__n.BLIF \ +state_machine_un8_clk_000_d_4_n.BLIF cpu_est_d_i_0__n.BLIF \ +DTACK_SYNC_1_sqmuxa_1_0.BLIF CLK_000_D_i.BLIF VPA_SYNC_1_sqmuxa_1_1.BLIF \ +AS_030_i.BLIF VPA_SYNC_1_sqmuxa_2.BLIF AS_000_INT_i.BLIF \ +VPA_SYNC_1_sqmuxa_3.BLIF dsack_i_1__n.BLIF VPA_SYNC_1_sqmuxa_4.BLIF \ +state_machine_un13_clk_000_d_i_n.BLIF N_108_1.BLIF \ +state_machine_un8_clk_000_d_i_n.BLIF N_118_1.BLIF \ +state_machine_un13_clk_000_d_1_i_n.BLIF N_110_1.BLIF sm_amiga_i_1__n.BLIF \ +clk_exp_1.BLIF sm_amiga_i_2__n.BLIF sm_amiga_d_0_2__un3_n.BLIF \ +sm_amiga_i_0__n.BLIF sm_amiga_d_0_2__un1_n.BLIF sm_amiga_i_3__n.BLIF \ +sm_amiga_d_0_2__un0_n.BLIF VPA_D_i.BLIF dsack_int_0_1__un3_n.BLIF \ +VMA_INT_i.BLIF dsack_int_0_1__un1_n.BLIF DTACK_i.BLIF \ +dsack_int_0_1__un0_n.BLIF cpu_est_i_3__n.BLIF vma_int_0_un3_n.BLIF \ +a_i_18__n.BLIF vma_int_0_un1_n.BLIF a_i_16__n.BLIF vma_int_0_un0_n.BLIF \ +a_i_19__n.BLIF vpa_sync_0_un3_n.BLIF CLK_030_i.BLIF vpa_sync_0_un1_n.BLIF \ +state_machine_un42_clk_030_i_n.BLIF vpa_sync_0_un0_n.BLIF DS_030_i.BLIF \ +as_000_int_0_un3_n.BLIF cpu_est_i_1__n.BLIF as_000_int_0_un1_n.BLIF \ +AS_030_000_SYNC_i.BLIF as_000_int_0_un0_n.BLIF cpu_est_i_0__n.BLIF \ +dtack_sync_0_un3_n.BLIF sm_amiga_i_4__n.BLIF dtack_sync_0_un1_n.BLIF \ +sm_amiga_i_6__n.BLIF dtack_sync_0_un0_n.BLIF cpu_est_i_2__n.BLIF \ +lds_000_int_0_un3_n.BLIF UDS_000_INT_0_sqmuxa_1_i.BLIF \ +lds_000_int_0_un1_n.BLIF UDS_000_INT_0_sqmuxa_i.BLIF lds_000_int_0_un0_n.BLIF \ +sm_amiga_i_5__n.BLIF uds_000_int_0_un3_n.BLIF CLK_000_DD_i.BLIF \ +uds_000_int_0_un1_n.BLIF sm_amiga_i_7__n.BLIF uds_000_int_0_un0_n.BLIF \ +a_i_30__n.BLIF bg_000_0_un3_n.BLIF a_i_31__n.BLIF bg_000_0_un1_n.BLIF \ +a_i_28__n.BLIF bg_000_0_un0_n.BLIF a_i_29__n.BLIF as_030_000_sync_0_un3_n.BLIF \ +a_i_26__n.BLIF as_030_000_sync_0_un1_n.BLIF a_i_27__n.BLIF \ +as_030_000_sync_0_un0_n.BLIF a_i_24__n.BLIF fpu_cs_int_0_un3_n.BLIF \ +a_i_25__n.BLIF fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF \ +ipl_030_0_2__un3_n.BLIF RST_i.BLIF ipl_030_0_2__un1_n.BLIF N_107_i.BLIF \ +ipl_030_0_2__un0_n.BLIF N_106_i.BLIF ipl_030_0_1__un3_n.BLIF FPU_CS_INT_i.BLIF \ +ipl_030_0_1__un1_n.BLIF CPU_SPACE_i.BLIF ipl_030_0_1__un0_n.BLIF \ +BGACK_030_INT_i.BLIF ipl_030_0_0__un3_n.BLIF AS_030_c.BLIF \ +ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF bgack_030_int_0_un3_n.BLIF \ +DS_030_c.BLIF bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF \ +sm_amiga_d_0_0__un3_n.BLIF sm_amiga_d_0_0__un1_n.BLIF size_c_0__n.BLIF \ +sm_amiga_d_0_0__un0_n.BLIF sm_amiga_d_0_1__un3_n.BLIF size_c_1__n.BLIF \ +sm_amiga_d_0_1__un1_n.BLIF sm_amiga_d_0_1__un0_n.BLIF a_c_0__n.BLIF \ +cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF \ +cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF \ +cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF \ +a_15__n.BLIF a_14__n.BLIF a_13__n.BLIF a_12__n.BLIF a_c_16__n.BLIF \ +a_11__n.BLIF a_c_17__n.BLIF a_10__n.BLIF a_c_18__n.BLIF a_9__n.BLIF \ +a_c_19__n.BLIF a_8__n.BLIF a_c_20__n.BLIF a_7__n.BLIF a_c_21__n.BLIF \ +a_6__n.BLIF a_c_22__n.BLIF a_5__n.BLIF a_c_23__n.BLIF a_4__n.BLIF \ +a_c_24__n.BLIF a_3__n.BLIF a_c_25__n.BLIF a_2__n.BLIF a_c_26__n.BLIF \ +a_1__n.BLIF a_c_27__n.BLIF a_c_28__n.BLIF a_c_29__n.BLIF DSACK_1_.PIN.BLIF \ +DTACK.PIN.BLIF .outputs IPL_030_2_ AS_000 UDS_000 LDS_000 BERR BG_000 BGACK_030 CLK_DIV_OUT \ CLK_EXP FPU_CS AVEC AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR \ -AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_4_.D SM_AMIGA_4_.C \ -SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D \ -SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR \ -SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR cpu_est_0_.D cpu_est_0_.C \ +AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_6_.D SM_AMIGA_6_.C \ +SM_AMIGA_6_.AR SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D \ +SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR \ +SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C \ +SM_AMIGA_1_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR IPL_030DFFSH_1_reg.D \ +IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D \ +IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP cpu_est_0_.D cpu_est_0_.C \ cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_reg.D \ -cpu_est_3_reg.C SM_AMIGA_7_.D SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.D \ -SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR \ -CLK_000_CNT_0_.D CLK_000_CNT_0_.C CLK_000_CNT_1_.D CLK_000_CNT_1_.C \ -CLK_000_CNT_2_.D CLK_000_CNT_2_.C CLK_000_CNT_3_.D CLK_000_CNT_3_.C \ -SM_AMIGA_D_0_.D SM_AMIGA_D_0_.C SM_AMIGA_D_1_.D SM_AMIGA_D_1_.C \ -SM_AMIGA_D_2_.D SM_AMIGA_D_2_.C IPL_030DFFSH_0_reg.D IPL_030DFFSH_0_reg.C \ -IPL_030DFFSH_0_reg.AP IPL_030DFFSH_1_reg.D IPL_030DFFSH_1_reg.C \ -IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D IPL_030DFFSH_2_reg.C \ -IPL_030DFFSH_2_reg.AP inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \ -inst_AS_030_000_SYNC.AP inst_VPA_SYNC.D inst_VPA_SYNC.C inst_VPA_SYNC.AP \ -BG_000DFFSHreg.D BG_000DFFSHreg.C BG_000DFFSHreg.AP inst_AS_000_INTreg.D \ -inst_AS_000_INTreg.C inst_AS_000_INTreg.AP inst_VMA_INTreg.D inst_VMA_INTreg.C \ -inst_VMA_INTreg.AP inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C \ -inst_BGACK_030_INTreg.AP inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C DSACK_INT_1_.D \ -DSACK_INT_1_.C DSACK_INT_1_.AP inst_UDS_000_INTreg.D inst_UDS_000_INTreg.C \ -inst_UDS_000_INTreg.AP inst_LDS_000_INTreg.D inst_LDS_000_INTreg.C \ -inst_LDS_000_INTreg.AP inst_DTACK_SYNC.D inst_DTACK_SYNC.C inst_DTACK_SYNC.AP \ -inst_FPU_CS_INTreg.D inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP \ -inst_DTACK_DMA.D inst_DTACK_DMA.C inst_DTACK_DMA.AP CLK_CNT_0_.D CLK_CNT_0_.C \ -inst_RISING_CLK_AMIGA.D inst_RISING_CLK_AMIGA.C inst_VPA_D.D inst_VPA_D.C \ -inst_CLK_000_D.D inst_CLK_000_D.C RESETDFFreg.D RESETDFFreg.C \ -inst_CLK_000_DD.D inst_CLK_000_DD.C inst_CLK_OUT_INTreg.D \ -inst_CLK_OUT_INTreg.C DSACK_1_ DTACK DSACK_0_ a_15__n a_c_22__n a_14__n \ -a_c_23__n a_13__n a_c_24__n a_12__n a_c_25__n a_11__n a_c_26__n a_10__n \ -a_c_27__n gnd_n_n a_9__n a_c_28__n a_8__n a_c_29__n a_7__n a_c_30__n a_6__n \ -a_c_31__n a_5__n CPU_SPACE_c vcc_n_n a_4__n BG_030_c a_3__n a_2__n a_1__n \ -BGACK_000_c CLK_030_c CLK_000_c CLK_OSZI_c un1_clk_000_cnt_3__n \ -state_machine_un14_as_000_int_n ipl_c_0__n clk_exp ipl_c_1__n ipl_c_2__n \ -dsack_c_1__n DTACK_c RST_c RW_c fc_c_0__n fc_c_1__n N_123 N_148_i \ -clk_rising_clk_amiga_1_n N_147_i VMA_INT_1_sqmuxa_0 N_170_i N_171_i \ -DSACK_INT_1_sqmuxa N_161_i N_120 N_164_i N_144_1 N_165_i N_251 N_168_i N_254 \ -N_166_i N_186 N_167_i un1_clk_000_cnt_0__n N_169_i N_184 clk_cpu_est_11_0_1__n \ -un1_clk_000_cnt_1__n N_173_i un1_clk_000_cnt_2__n N_172_i \ -state_machine_un69_clk_000_d_n N_174_i state_machine_un78_clk_000_d_n \ -clk_cpu_est_11_0_3__n N_149 N_121_i N_119 N_126_0 N_135 N_123_0 \ -state_machine_un67_clk_000_d_n N_122_0 state_machine_un80_clk_000_d_n N_142_i \ -N_132 N_143_i N_131 sm_amiga_ns_0_5__n state_machine_un25_clk_000_d_n N_141_i \ -N_150 N_140_i N_151 sm_amiga_ns_0_4__n N_144 N_146 LDS_000_INT_1_sqmuxa_i \ -N_143 un1_UDS_000_INT_0_sqmuxa_2_0 N_145 UDS_000_INT_0_sqmuxa_i \ -state_machine_lds_000_int_8_n un1_UDS_000_INT_0_sqmuxa_i \ -un1_UDS_000_INT_0_sqmuxa_2 N_124_0 state_machine_uds_000_int_8_n N_136_i \ -LDS_000_INT_0_sqmuxa state_machine_un42_clk_030_n RISING_CLK_AMIGA_i \ -un1_bg_030 state_machine_un4_bgack_000_0_n N_133 BG_030_c_i \ -state_machine_as_030_000_sync_3_n state_machine_un1_clk_030_0_n N_125 \ -state_machine_un17_clk_030_0_n N_137 un1_as_030_2_0 N_138 N_137_i \ -DSACK_INT_1_sqmuxa_1 N_138_i un1_as_030_2 state_machine_un17_clk_030_n N_120_i \ -state_machine_un1_clk_030_n N_125_0 state_machine_un4_bgack_000_n \ -state_machine_as_030_000_sync_3_2_n VPA_SYNC_1_sqmuxa N_133_i \ -VPA_SYNC_1_sqmuxa_1 un1_bg_030_0 N_122 a_c_i_0__n AS_000_INT_1_sqmuxa \ -state_machine_uds_000_int_8_0_n N_136 state_machine_lds_000_int_8_0_n N_124 \ -N_151_i N_130 state_machine_un15_clk_000_d_n N_146_i un1_UDS_000_INT_0_sqmuxa \ -N_145_i UDS_000_INT_0_sqmuxa sm_amiga_ns_0_7__n LDS_000_INT_1_sqmuxa N_144_i \ -N_139 N_150_i N_140 N_126 size_c_i_1__n N_141 state_machine_un25_clk_000_d_i_n \ -N_121 state_machine_un80_clk_000_d_i_n N_142 state_machine_un67_clk_000_d_i_n \ -VPA_SYNC_1_sqmuxa_1_0 state_machine_un78_clk_000_d_0_n DTACK_SYNC_1_sqmuxa \ -clk_rising_clk_amiga_1_i_n DTACK_SYNC_1_sqmuxa_1 N_135_i N_149_2 N_104_i \ -clk_un3_clk_000_dd_n N_149_i N_164 N_119_0 N_171 clk_000_cnt_i_1__n N_170 \ -clk_000_cnt_i_0__n clk_cpu_est_11_3__n clk_000_cnt_i_3__n N_174 \ -clk_000_cnt_i_2__n N_172 state_machine_un69_clk_000_d_0_n N_173 \ -state_machine_un69_clk_000_d_0_1_n clk_cpu_est_11_1__n \ -state_machine_un69_clk_000_d_0_2_n N_169 state_machine_un25_clk_000_d_i_1_n \ -N_167 N_116_i_1 N_166 un1_bg_030_0_1 N_168 un1_bg_030_0_2 N_165 \ -state_machine_as_030_000_sync_3_2_1_n VMA_INT_1_sqmuxa \ -un1_UDS_000_INT_0_sqmuxa_i_1 N_147 clk_cpu_est_11_0_1_3__n N_148 \ -clk_cpu_est_11_0_1_1__n RW_i clk_cpu_est_11_0_2_1__n clk_exp_i N_251_1 \ -CLK_000_DD_i N_251_2 CLK_000_D_i N_251_3 AS_000_INT_i N_251_4 cpu_est_i_0__n \ -N_251_5 cpu_est_i_2__n N_251_6 cpu_est_i_3__n N_254_1 cpu_est_i_1__n N_254_2 \ -N_149_2_i DSACK_INT_1_sqmuxa_1_0 VPA_D_i DSACK_INT_1_sqmuxa_2 DTACK_i \ -DSACK_INT_1_sqmuxa_3 VPA_SYNC_i N_149_1 DTACK_SYNC_i N_149_2_0 AS_030_i \ -N_132_1 DTACK_SYNC_1_sqmuxa_i N_131_1 DS_030_i state_machine_un42_clk_030_1_n \ -sm_amiga_i_4__n state_machine_un42_clk_030_2_n sm_amiga_i_6__n \ -state_machine_un42_clk_030_3_n sm_amiga_i_5__n state_machine_un42_clk_030_4_n \ -N_139_i state_machine_un42_clk_030_5_n state_machine_un15_clk_000_d_i_n \ -N_142_1 N_130_i N_130_1 sm_amiga_i_0__n N_130_2 sm_amiga_i_7__n \ -UDS_000_INT_0_sqmuxa_1 VPA_SYNC_1_sqmuxa_i UDS_000_INT_0_sqmuxa_2 dsack_i_1__n \ -DTACK_SYNC_1_sqmuxa_1_0 DSACK_INT_1_sqmuxa_i VPA_SYNC_1_sqmuxa_1_1 a_i_18__n \ -VPA_SYNC_1_sqmuxa_2 a_i_16__n VPA_SYNC_1_sqmuxa_3 a_i_19__n N_171_1 CLK_030_i \ -N_170_1 state_machine_un42_clk_030_i_n N_174_1 AS_030_000_SYNC_i clk_exp_1 \ -N_131_i cpu_est_0_1__un3_n N_132_i cpu_est_0_1__un1_n sm_amiga_i_2__n \ -cpu_est_0_1__un0_n sm_amiga_i_1__n vma_int_0_un3_n sm_amiga_i_3__n \ -vma_int_0_un1_n CLK_000_i vma_int_0_un0_n a_i_30__n cpu_est_0_3__un3_n \ -a_i_31__n cpu_est_0_3__un1_n a_i_28__n cpu_est_0_3__un0_n a_i_29__n \ -cpu_est_0_2__un3_n a_i_26__n cpu_est_0_2__un1_n a_i_27__n cpu_est_0_2__un0_n \ -a_i_24__n dtack_sync_0_un3_n a_i_25__n dtack_sync_0_un1_n dtack_sync_0_un0_n \ -sm_amiga_d_0_0__un3_n RST_i sm_amiga_d_0_0__un1_n sm_amiga_d_0_0__un0_n \ -FPU_CS_INT_i bgack_030_int_0_un3_n CPU_SPACE_i bgack_030_int_0_un1_n \ -BGACK_030_INT_i bgack_030_int_0_un0_n AS_030_c bg_000_0_un3_n bg_000_0_un1_n \ -bg_000_0_un0_n DS_030_c as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n \ -as_030_000_sync_0_un0_n fpu_cs_int_0_un3_n size_c_0__n fpu_cs_int_0_un1_n \ -fpu_cs_int_0_un0_n size_c_1__n dsack_int_0_1__un3_n dsack_int_0_1__un1_n \ -a_c_0__n dsack_int_0_1__un0_n vpa_sync_0_un3_n vpa_sync_0_un1_n \ -vpa_sync_0_un0_n as_000_int_0_un3_n as_000_int_0_un1_n as_000_int_0_un0_n \ -ipl_030_0_2__un3_n ipl_030_0_2__un1_n ipl_030_0_2__un0_n ipl_030_0_1__un3_n \ -ipl_030_0_1__un1_n ipl_030_0_1__un0_n ipl_030_0_0__un3_n ipl_030_0_0__un1_n \ -ipl_030_0_0__un0_n sm_amiga_d_0_2__un3_n a_c_16__n sm_amiga_d_0_2__un1_n \ -sm_amiga_d_0_2__un0_n a_c_17__n sm_amiga_d_0_1__un3_n sm_amiga_d_0_1__un1_n \ -a_c_18__n sm_amiga_d_0_1__un0_n lds_000_int_0_un3_n a_c_19__n \ -lds_000_int_0_un1_n lds_000_int_0_un0_n a_c_20__n uds_000_int_0_un3_n \ -uds_000_int_0_un1_n a_c_21__n uds_000_int_0_un0_n DSACK_1_.OE DTACK.OE \ -AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE G_128 \ -G_130 G_132 cpu_est_0_0_ CLK_OUT_PRE_0 G_122 G_123 G_124 -.names CLK_000_D_i.BLIF N_151_i.BLIF SM_AMIGA_4_.D +cpu_est_3_reg.C SM_AMIGA_7_.D SM_AMIGA_7_.C SM_AMIGA_7_.AP cpu_est_d_0_.D \ +cpu_est_d_0_.C cpu_est_d_1_.D cpu_est_d_1_.C cpu_est_d_2_.D cpu_est_d_2_.C \ +cpu_est_d_3_.D cpu_est_d_3_.C SM_AMIGA_D_0_.D SM_AMIGA_D_0_.C SM_AMIGA_D_1_.D \ +SM_AMIGA_D_1_.C SM_AMIGA_D_2_.D SM_AMIGA_D_2_.C IPL_030DFFSH_0_reg.D \ +IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP inst_AS_000_INTreg.D \ +inst_AS_000_INTreg.C inst_AS_000_INTreg.AP inst_VPA_SYNC.D inst_VPA_SYNC.C \ +inst_VPA_SYNC.AP inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \ +inst_AS_030_000_SYNC.AP inst_VMA_INTreg.D inst_VMA_INTreg.C inst_VMA_INTreg.AP \ +BG_000DFFSHreg.D BG_000DFFSHreg.C BG_000DFFSHreg.AP DSACK_INT_1_.D \ +DSACK_INT_1_.C DSACK_INT_1_.AP inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C \ +inst_BGACK_030_INTreg.AP inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C \ +inst_UDS_000_INTreg.D inst_UDS_000_INTreg.C inst_UDS_000_INTreg.AP \ +inst_LDS_000_INTreg.D inst_LDS_000_INTreg.C inst_LDS_000_INTreg.AP \ +inst_DTACK_SYNC.D inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_FPU_CS_INTreg.D \ +inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP inst_DTACK_DMA.D inst_DTACK_DMA.C \ +inst_DTACK_DMA.AP inst_RISING_CLK_AMIGA.D inst_RISING_CLK_AMIGA.C CLK_CNT_0_.D \ +CLK_CNT_0_.C inst_VPA_D.D inst_VPA_D.C inst_CLK_000_D.D inst_CLK_000_D.C \ +RESETDFFreg.D RESETDFFreg.C inst_CLK_000_DD.D inst_CLK_000_DD.C \ +inst_CLK_OUT_INTreg.D inst_CLK_OUT_INTreg.C DSACK_1_ DTACK DSACK_0_ a_c_30__n \ +a_c_31__n CPU_SPACE_c BG_030_c gnd_n_n BGACK_000_c CLK_030_c CLK_000_c \ +CLK_OSZI_c vcc_n_n ipl_c_0__n ipl_c_1__n ipl_c_2__n \ +state_machine_un57_clk_000_d_n dsack_c_1__n DTACK_c \ +state_machine_un13_as_000_int_n RST_c clk_exp RW_c fc_c_0__n fc_c_1__n \ +state_machine_un57_clk_000_d_0_n N_161_i a_c_i_0__n \ +state_machine_uds_000_int_8_0_n state_machine_lds_000_int_8_0_n N_113_i \ +sm_amiga_ns_0_2__n N_118_i N_117_i sm_amiga_ns_0_5__n N_123_i N_119_i N_120_i \ +sm_amiga_ns_0_7__n CLK_OUT_PRE_i N_106 N_102_0 N_107 size_c_i_1__n \ +clk_un3_clk_000_dd_n state_machine_un31_clk_000_d_i_n clk_cpu_est_11_1__n \ +RISING_CLK_AMIGA_i clk_cpu_est_11_3__n state_machine_un4_bgack_000_0_n \ +BG_030_c_i state_machine_un1_clk_030_0_n state_machine_un17_clk_030_0_n N_161 \ +un1_as_030_2_0 N_114 state_machine_as_030_000_sync_3_2_n N_109 N_109_i N_111 \ +un1_bg_030_0 N_112 N_111_i N_122 N_122_i N_115 N_101 N_147_i N_116 \ +clk_cpu_est_11_0_3__n N_124 N_145_i N_139 N_146_i N_137 N_142_i N_140 \ +clk_cpu_est_11_0_1__n N_141 N_140_i N_136 N_139_i N_142 N_141_i N_145 N_138_i \ +N_138 N_137_i N_146 N_136_i N_143 N_143_i N_144 N_144_i UDS_000_INT_0_sqmuxa \ +N_134_i UDS_000_INT_0_sqmuxa_1 N_101_0 N_147 N_115_i N_147_1 N_116_i \ +state_machine_un13_clk_000_d_1_n N_186 N_124_i N_189 \ +state_machine_un42_clk_030_n N_112_i un1_bg_030 sm_amiga_ns_0_0__n \ +state_machine_as_030_000_sync_3_n N_86_i_1 un1_as_030_2 un1_bg_030_0_1 \ +state_machine_un17_clk_030_n un1_bg_030_0_2 state_machine_un1_clk_030_n \ +state_machine_as_030_000_sync_3_2_1_n state_machine_un4_bgack_000_n \ +state_machine_un31_clk_000_d_i_1_n N_108 N_186_1 \ +state_machine_un31_clk_000_d_n N_186_2 state_machine_un13_clk_000_d_n N_186_3 \ +state_machine_un13_clk_000_d_4_n N_186_4 state_machine_un8_clk_000_d_n N_186_5 \ +DTACK_SYNC_1_sqmuxa N_186_6 VPA_SYNC_1_sqmuxa_1_0 N_189_1 VPA_SYNC_1_sqmuxa \ +N_189_2 N_123 clk_cpu_est_11_0_1_1__n N_118 clk_cpu_est_11_0_2_1__n N_110 \ +clk_cpu_est_11_0_1_3__n N_102 N_143_1 N_120 N_144_1 N_119 N_106_1 N_117 \ +N_106_2 N_113 N_107_1 state_machine_lds_000_int_8_n UDS_000_INT_0_sqmuxa_1_1 \ +state_machine_uds_000_int_8_n UDS_000_INT_0_sqmuxa_1_2 DTACK_SYNC_1_sqmuxa_1 \ +UDS_000_INT_0_sqmuxa_1_3 un2_clk_030_1 UDS_000_INT_0_sqmuxa_1_0 \ +VPA_SYNC_1_sqmuxa_1 UDS_000_INT_0_sqmuxa_2 AS_000_INT_1_sqmuxa \ +state_machine_un42_clk_030_1_n VMA_INT_1_sqmuxa state_machine_un42_clk_030_2_n \ +DSACK_INT_1_sqmuxa state_machine_un42_clk_030_3_n RW_i \ +state_machine_un42_clk_030_4_n clk_exp_i state_machine_un42_clk_030_5_n \ +DTACK_SYNC_1_sqmuxa_i state_machine_un13_clk_000_d_1_0_n N_114_i \ +state_machine_un13_clk_000_d_4_1_n VPA_SYNC_1_sqmuxa_i \ +state_machine_un8_clk_000_d_1_n N_110_i state_machine_un8_clk_000_d_2_n \ +N_108_i state_machine_un8_clk_000_d_3_n cpu_est_d_i_3__n \ +state_machine_un8_clk_000_d_4_n cpu_est_d_i_0__n DTACK_SYNC_1_sqmuxa_1_0 \ +CLK_000_D_i VPA_SYNC_1_sqmuxa_1_1 AS_030_i VPA_SYNC_1_sqmuxa_2 AS_000_INT_i \ +VPA_SYNC_1_sqmuxa_3 dsack_i_1__n VPA_SYNC_1_sqmuxa_4 \ +state_machine_un13_clk_000_d_i_n N_108_1 state_machine_un8_clk_000_d_i_n \ +N_118_1 state_machine_un13_clk_000_d_1_i_n N_110_1 sm_amiga_i_1__n clk_exp_1 \ +sm_amiga_i_2__n sm_amiga_d_0_2__un3_n sm_amiga_i_0__n sm_amiga_d_0_2__un1_n \ +sm_amiga_i_3__n sm_amiga_d_0_2__un0_n VPA_D_i dsack_int_0_1__un3_n VMA_INT_i \ +dsack_int_0_1__un1_n DTACK_i dsack_int_0_1__un0_n cpu_est_i_3__n \ +vma_int_0_un3_n a_i_18__n vma_int_0_un1_n a_i_16__n vma_int_0_un0_n a_i_19__n \ +vpa_sync_0_un3_n CLK_030_i vpa_sync_0_un1_n state_machine_un42_clk_030_i_n \ +vpa_sync_0_un0_n DS_030_i as_000_int_0_un3_n cpu_est_i_1__n as_000_int_0_un1_n \ +AS_030_000_SYNC_i as_000_int_0_un0_n cpu_est_i_0__n dtack_sync_0_un3_n \ +sm_amiga_i_4__n dtack_sync_0_un1_n sm_amiga_i_6__n dtack_sync_0_un0_n \ +cpu_est_i_2__n lds_000_int_0_un3_n UDS_000_INT_0_sqmuxa_1_i \ +lds_000_int_0_un1_n UDS_000_INT_0_sqmuxa_i lds_000_int_0_un0_n sm_amiga_i_5__n \ +uds_000_int_0_un3_n CLK_000_DD_i uds_000_int_0_un1_n sm_amiga_i_7__n \ +uds_000_int_0_un0_n a_i_30__n bg_000_0_un3_n a_i_31__n bg_000_0_un1_n \ +a_i_28__n bg_000_0_un0_n a_i_29__n as_030_000_sync_0_un3_n a_i_26__n \ +as_030_000_sync_0_un1_n a_i_27__n as_030_000_sync_0_un0_n a_i_24__n \ +fpu_cs_int_0_un3_n a_i_25__n fpu_cs_int_0_un1_n fpu_cs_int_0_un0_n \ +ipl_030_0_2__un3_n RST_i ipl_030_0_2__un1_n N_107_i ipl_030_0_2__un0_n N_106_i \ +ipl_030_0_1__un3_n FPU_CS_INT_i ipl_030_0_1__un1_n CPU_SPACE_i \ +ipl_030_0_1__un0_n BGACK_030_INT_i ipl_030_0_0__un3_n AS_030_c \ +ipl_030_0_0__un1_n ipl_030_0_0__un0_n bgack_030_int_0_un3_n DS_030_c \ +bgack_030_int_0_un1_n bgack_030_int_0_un0_n sm_amiga_d_0_0__un3_n \ +sm_amiga_d_0_0__un1_n size_c_0__n sm_amiga_d_0_0__un0_n sm_amiga_d_0_1__un3_n \ +size_c_1__n sm_amiga_d_0_1__un1_n sm_amiga_d_0_1__un0_n a_c_0__n \ +cpu_est_0_1__un3_n cpu_est_0_1__un1_n cpu_est_0_1__un0_n cpu_est_0_2__un3_n \ +cpu_est_0_2__un1_n cpu_est_0_2__un0_n cpu_est_0_3__un3_n cpu_est_0_3__un1_n \ +cpu_est_0_3__un0_n a_15__n a_14__n a_13__n a_12__n a_c_16__n a_11__n a_c_17__n \ +a_10__n a_c_18__n a_9__n a_c_19__n a_8__n a_c_20__n a_7__n a_c_21__n a_6__n \ +a_c_22__n a_5__n a_c_23__n a_4__n a_c_24__n a_3__n a_c_25__n a_2__n a_c_26__n \ +a_1__n a_c_27__n a_c_28__n a_c_29__n DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE \ +LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE cpu_est_0_0_ CLK_OUT_PRE_0 \ +G_98 G_99 G_100 +.names N_86_i_1.BLIF N_122_i.BLIF SM_AMIGA_6_.D 11 1 -.names sm_amiga_ns_0_4__n.BLIF SM_AMIGA_3_.D +.names sm_amiga_ns_0_2__n.BLIF SM_AMIGA_5_.D 0 1 +.names CLK_000_D_i.BLIF N_124_i.BLIF SM_AMIGA_4_.D +11 1 +.names N_115_i.BLIF N_116_i.BLIF SM_AMIGA_3_.D +11 1 .names sm_amiga_ns_0_5__n.BLIF SM_AMIGA_2_.D 0 1 -.names N_116_i_1.BLIF N_150_i.BLIF SM_AMIGA_1_.D +.names N_119_i.BLIF N_123_i.BLIF SM_AMIGA_1_.D 11 1 .names sm_amiga_ns_0_7__n.BLIF SM_AMIGA_0_.D 0 1 +.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF IPL_030DFFSH_1_reg.D +1- 1 +-1 1 +.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF IPL_030DFFSH_2_reg.D +1- 1 +-1 1 .names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D 1- 1 -1 1 @@ -346,13 +344,7 @@ G_130 G_132 cpu_est_0_0_ CLK_OUT_PRE_0 G_122 G_123 G_124 .names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_reg.D 1- 1 -1 1 -.names inst_CLK_000_D.BLIF N_136_i.BLIF SM_AMIGA_7_.D -11 1 -.names N_137_i.BLIF N_138_i.BLIF SM_AMIGA_6_.D -11 1 -.names inst_CLK_000_D.BLIF N_139_i.BLIF SM_AMIGA_5_.D -11 1 -.names un1_clk_000_cnt_3__n.BLIF CLK_000_CNT_0_.D +.names sm_amiga_ns_0_0__n.BLIF SM_AMIGA_7_.D 0 1 .names sm_amiga_d_0_0__un1_n.BLIF sm_amiga_d_0_0__un0_n.BLIF SM_AMIGA_D_0_.D 1- 1 @@ -366,35 +358,29 @@ G_130 G_132 cpu_est_0_0_ CLK_OUT_PRE_0 G_122 G_123 G_124 .names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF IPL_030DFFSH_0_reg.D 1- 1 -1 1 -.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF IPL_030DFFSH_1_reg.D +.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF inst_AS_000_INTreg.D 1- 1 -1 1 -.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF IPL_030DFFSH_2_reg.D +.names vpa_sync_0_un1_n.BLIF vpa_sync_0_un0_n.BLIF inst_VPA_SYNC.D 1- 1 -1 1 .names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF \ inst_AS_030_000_SYNC.D 1- 1 -1 1 -.names vpa_sync_0_un1_n.BLIF vpa_sync_0_un0_n.BLIF inst_VPA_SYNC.D +.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D 1- 1 -1 1 .names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF BG_000DFFSHreg.D 1- 1 -1 1 -.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF inst_AS_000_INTreg.D -1- 1 --1 1 -.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D +.names dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF DSACK_INT_1_.D 1- 1 -1 1 .names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF \ inst_BGACK_030_INTreg.D 1- 1 -1 1 -.names dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF DSACK_INT_1_.D -1- 1 --1 1 .names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INTreg.D 1- 1 -1 1 @@ -407,679 +393,601 @@ inst_BGACK_030_INTreg.D .names fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF inst_FPU_CS_INTreg.D 1- 1 -1 1 -.names state_machine_un14_as_000_int_n.BLIF inst_DTACK_DMA.D +.names state_machine_un13_as_000_int_n.BLIF inst_DTACK_DMA.D 0 1 +.names CLK_000_D_i.BLIF CLK_000_c.BLIF inst_RISING_CLK_AMIGA.D +11 1 .names CLK_CNT_0_.BLIF CLK_CNT_0_.D 0 1 .names gnd_n_n .names vcc_n_n 1 -.names CLK_000_CNT_0_.BLIF N_104_i.BLIF un1_clk_000_cnt_3__n -11 1 -.names AS_000_INT_i.BLIF dsack_i_1__n.BLIF state_machine_un14_as_000_int_n -11 1 -.names clk_exp_1.BLIF G_123.BLIF clk_exp -11 1 -.names N_123_0.BLIF N_123 +.names state_machine_un57_clk_000_d_0_n.BLIF state_machine_un57_clk_000_d_n 0 1 -.names N_148.BLIF N_148_i +.names AS_000_INT_i.BLIF dsack_i_1__n.BLIF state_machine_un13_as_000_int_n +11 1 +.names clk_exp_1.BLIF G_99.BLIF clk_exp +11 1 +.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF \ +state_machine_un57_clk_000_d_0_n +11 1 +.names N_161.BLIF N_161_i 0 1 -.names CLK_000_D_i.BLIF CLK_000_c.BLIF clk_rising_clk_amiga_1_n -11 1 -.names N_147.BLIF N_147_i +.names a_c_0__n.BLIF a_c_i_0__n 0 1 -.names N_147_i.BLIF N_148_i.BLIF VMA_INT_1_sqmuxa_0 +.names a_c_i_0__n.BLIF N_161_i.BLIF state_machine_uds_000_int_8_0_n 11 1 -.names N_170.BLIF N_170_i +.names N_161_i.BLIF state_machine_un31_clk_000_d_n.BLIF \ +state_machine_lds_000_int_8_0_n +11 1 +.names N_113.BLIF N_113_i 0 1 -.names N_171.BLIF N_171_i +.names N_113_i.BLIF N_114_i.BLIF sm_amiga_ns_0_2__n +11 1 +.names N_118.BLIF N_118_i 0 1 -.names DSACK_INT_1_sqmuxa_3.BLIF state_machine_un78_clk_000_d_n.BLIF \ -DSACK_INT_1_sqmuxa -11 1 -.names N_170_i.BLIF N_171_i.BLIF N_161_i -11 1 -.names N_120_i.BLIF N_120 +.names N_117.BLIF N_117_i 0 1 -.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF N_164_i +.names N_117_i.BLIF N_118_i.BLIF sm_amiga_ns_0_5__n 11 1 -.names CLK_000_i.BLIF N_119.BLIF N_144_1 -11 1 -.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_165_i -11 1 -.names N_251_5.BLIF N_251_6.BLIF N_251 -11 1 -.names N_168.BLIF N_168_i +.names N_123.BLIF N_123_i 0 1 -.names N_254_1.BLIF N_254_2.BLIF N_254 -11 1 -.names N_166.BLIF N_166_i +.names N_119.BLIF N_119_i 0 1 -.names CLK_000_CNT_2_.BLIF N_184.BLIF N_186 -11 1 -.names N_167.BLIF N_167_i +.names N_120.BLIF N_120_i 0 1 -.names CLK_000_CNT_3_.BLIF N_104_i.BLIF un1_clk_000_cnt_0__n +.names N_110_i.BLIF N_120_i.BLIF sm_amiga_ns_0_7__n 11 1 -.names N_169.BLIF N_169_i +.names inst_CLK_OUT_PRE.BLIF CLK_OUT_PRE_i 0 1 -.names CLK_000_CNT_1_.BLIF un1_clk_000_cnt_3__n.BLIF N_184 +.names N_106_1.BLIF N_106_2.BLIF N_106 11 1 -.names clk_cpu_est_11_0_1_1__n.BLIF clk_cpu_est_11_0_2_1__n.BLIF \ -clk_cpu_est_11_0_1__n +.names CLK_OUT_PRE_i.BLIF SM_AMIGA_1_.BLIF N_102_0 11 1 -.names CLK_000_CNT_2_.BLIF N_104_i.BLIF un1_clk_000_cnt_1__n +.names N_107_1.BLIF sm_amiga_i_1__n.BLIF N_107 11 1 -.names N_173.BLIF N_173_i +.names size_c_1__n.BLIF size_c_i_1__n 0 1 -.names CLK_000_CNT_1_.BLIF N_104_i.BLIF un1_clk_000_cnt_2__n +.names inst_CLK_000_D.BLIF CLK_000_DD_i.BLIF clk_un3_clk_000_dd_n 11 1 -.names N_172.BLIF N_172_i +.names state_machine_un31_clk_000_d_i_1_n.BLIF size_c_i_1__n.BLIF \ +state_machine_un31_clk_000_d_i_n +11 1 +.names clk_cpu_est_11_0_1__n.BLIF clk_cpu_est_11_1__n 0 1 -.names state_machine_un69_clk_000_d_0_n.BLIF state_machine_un69_clk_000_d_n -0 1 -.names N_174.BLIF N_174_i -0 1 -.names state_machine_un78_clk_000_d_0_n.BLIF state_machine_un78_clk_000_d_n -0 1 -.names clk_cpu_est_11_0_1_3__n.BLIF N_173_i.BLIF clk_cpu_est_11_0_3__n -11 1 -.names N_149_1.BLIF N_149_2_0.BLIF N_149 -11 1 -.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF N_121_i -11 1 -.names N_119_0.BLIF N_119 -0 1 -.names sm_amiga_i_3__n.BLIF sm_amiga_i_4__n.BLIF N_126_0 -11 1 -.names inst_CLK_000_D.BLIF CLK_000_i.BLIF N_135 -11 1 -.names inst_AS_000_INTreg.BLIF inst_CLK_000_D.BLIF N_123_0 -11 1 -.names DTACK_SYNC_i.BLIF state_machine_un69_clk_000_d_n.BLIF \ -state_machine_un67_clk_000_d_n -11 1 -.names inst_CLK_000_D.BLIF N_120_i.BLIF N_122_0 -11 1 -.names VPA_SYNC_i.BLIF state_machine_un69_clk_000_d_n.BLIF \ -state_machine_un80_clk_000_d_n -11 1 -.names N_142.BLIF N_142_i -0 1 -.names N_132_1.BLIF sm_amiga_i_3__n.BLIF N_132 -11 1 -.names N_143.BLIF N_143_i -0 1 -.names N_131_1.BLIF sm_amiga_i_1__n.BLIF N_131 -11 1 -.names N_142_i.BLIF N_143_i.BLIF sm_amiga_ns_0_5__n -11 1 -.names state_machine_un25_clk_000_d_i_n.BLIF state_machine_un25_clk_000_d_n -0 1 -.names N_141.BLIF N_141_i -0 1 -.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_150 -11 1 -.names N_140.BLIF N_140_i -0 1 -.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_151 -11 1 -.names N_140_i.BLIF N_141_i.BLIF sm_amiga_ns_0_4__n -11 1 -.names N_144_1.BLIF sm_amiga_i_2__n.BLIF N_144 -11 1 -.names N_144_1.BLIF SM_AMIGA_1_.BLIF N_146 -11 1 -.names LDS_000_INT_1_sqmuxa.BLIF LDS_000_INT_1_sqmuxa_i -0 1 -.names CLK_000_D_i.BLIF SM_AMIGA_2_.BLIF N_143 -11 1 -.names LDS_000_INT_1_sqmuxa_i.BLIF un1_UDS_000_INT_0_sqmuxa.BLIF \ -un1_UDS_000_INT_0_sqmuxa_2_0 -11 1 -.names N_123.BLIF SM_AMIGA_0_.BLIF N_145 -11 1 -.names UDS_000_INT_0_sqmuxa.BLIF UDS_000_INT_0_sqmuxa_i -0 1 -.names state_machine_lds_000_int_8_0_n.BLIF state_machine_lds_000_int_8_n -0 1 -.names un1_UDS_000_INT_0_sqmuxa_i_1.BLIF UDS_000_INT_0_sqmuxa_i.BLIF \ -un1_UDS_000_INT_0_sqmuxa_i -11 1 -.names un1_UDS_000_INT_0_sqmuxa_2_0.BLIF un1_UDS_000_INT_0_sqmuxa_2 -0 1 -.names inst_AS_000_INTreg.BLIF SM_AMIGA_0_.BLIF N_124_0 -11 1 -.names state_machine_uds_000_int_8_0_n.BLIF state_machine_uds_000_int_8_n -0 1 -.names N_136.BLIF N_136_i -0 1 -.names AS_030_i.BLIF un1_UDS_000_INT_0_sqmuxa_2.BLIF LDS_000_INT_0_sqmuxa -11 1 -.names state_machine_un42_clk_030_4_n.BLIF state_machine_un42_clk_030_5_n.BLIF \ -state_machine_un42_clk_030_n -11 1 .names inst_RISING_CLK_AMIGA.BLIF RISING_CLK_AMIGA_i 0 1 -.names un1_bg_030_0.BLIF un1_bg_030 +.names clk_cpu_est_11_0_3__n.BLIF clk_cpu_est_11_3__n 0 1 .names BGACK_000_c.BLIF RISING_CLK_AMIGA_i.BLIF \ state_machine_un4_bgack_000_0_n 11 1 -.names sm_amiga_i_6__n.BLIF sm_amiga_i_7__n.BLIF N_133 -11 1 .names BG_030_c.BLIF BG_030_c_i 0 1 -.names state_machine_as_030_000_sync_3_2_n.BLIF \ -state_machine_as_030_000_sync_3_n -0 1 .names BG_030_c_i.BLIF CLK_030_c.BLIF state_machine_un1_clk_030_0_n 11 1 -.names N_125_0.BLIF N_125 -0 1 .names AS_030_i.BLIF CLK_030_i.BLIF state_machine_un17_clk_030_0_n 11 1 -.names N_125.BLIF sm_amiga_i_6__n.BLIF N_137 +.names UDS_000_INT_0_sqmuxa_1_i.BLIF UDS_000_INT_0_sqmuxa_i.BLIF N_161 11 1 .names AS_030_i.BLIF state_machine_un42_clk_030_n.BLIF un1_as_030_2_0 11 1 -.names AS_030_000_SYNC_i.BLIF inst_CLK_000_D.BLIF N_138 +.names N_122.BLIF SM_AMIGA_6_.BLIF N_114 11 1 -.names N_137.BLIF N_137_i -0 1 -.names AS_030_i.BLIF DSACK_INT_1_sqmuxa_i.BLIF DSACK_INT_1_sqmuxa_1 -11 1 -.names N_138.BLIF N_138_i -0 1 -.names un1_as_030_2_0.BLIF un1_as_030_2 -0 1 -.names state_machine_un17_clk_030_0_n.BLIF state_machine_un17_clk_030_n -0 1 -.names AS_030_000_SYNC_i.BLIF SM_AMIGA_6_.BLIF N_120_i -11 1 -.names state_machine_un1_clk_030_0_n.BLIF state_machine_un1_clk_030_n -0 1 -.names CLK_000_D_i.BLIF SM_AMIGA_7_.BLIF N_125_0 -11 1 -.names state_machine_un4_bgack_000_0_n.BLIF state_machine_un4_bgack_000_n -0 1 .names state_machine_as_030_000_sync_3_2_1_n.BLIF \ state_machine_un42_clk_030_i_n.BLIF state_machine_as_030_000_sync_3_2_n 11 1 -.names VPA_SYNC_1_sqmuxa_3.BLIF cpu_est_2_.BLIF VPA_SYNC_1_sqmuxa +.names sm_amiga_i_6__n.BLIF sm_amiga_i_7__n.BLIF N_109 11 1 -.names N_133.BLIF N_133_i +.names N_109.BLIF N_109_i 0 1 -.names AS_030_i.BLIF VPA_SYNC_1_sqmuxa_i.BLIF VPA_SYNC_1_sqmuxa_1 +.names inst_CLK_000_D.BLIF SM_AMIGA_7_.BLIF N_111 11 1 .names un1_bg_030_0_1.BLIF un1_bg_030_0_2.BLIF un1_bg_030_0 11 1 -.names N_122_0.BLIF N_122 +.names SM_AMIGA_0_.BLIF state_machine_un13_clk_000_d_1_n.BLIF N_112 +11 1 +.names N_111.BLIF N_111_i 0 1 -.names a_c_0__n.BLIF a_c_i_0__n +.names AS_030_000_SYNC_i.BLIF clk_un3_clk_000_dd_n.BLIF N_122 +11 1 +.names N_122.BLIF N_122_i 0 1 -.names AS_030_i.BLIF N_122.BLIF AS_000_INT_1_sqmuxa +.names CLK_000_D_i.BLIF N_101.BLIF N_115 11 1 -.names a_c_i_0__n.BLIF un1_UDS_000_INT_0_sqmuxa_2_0.BLIF \ -state_machine_uds_000_int_8_0_n -11 1 -.names N_124.BLIF sm_amiga_i_7__n.BLIF N_136 -11 1 -.names state_machine_un25_clk_000_d_n.BLIF un1_UDS_000_INT_0_sqmuxa_2_0.BLIF \ -state_machine_lds_000_int_8_0_n -11 1 -.names N_124_0.BLIF N_124 +.names N_101_0.BLIF N_101 0 1 -.names N_151.BLIF N_151_i +.names N_147.BLIF N_147_i 0 1 -.names N_130_1.BLIF N_130_2.BLIF N_130 +.names sm_amiga_i_3__n.BLIF sm_amiga_i_4__n.BLIF N_116 11 1 -.names DS_030_i.BLIF RW_c.BLIF state_machine_un15_clk_000_d_n +.names clk_cpu_est_11_0_1_3__n.BLIF N_146_i.BLIF clk_cpu_est_11_0_3__n +11 1 +.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_124 +11 1 +.names N_145.BLIF N_145_i +0 1 +.names N_137.BLIF cpu_est_i_0__n.BLIF N_139 11 1 .names N_146.BLIF N_146_i 0 1 -.names un1_UDS_000_INT_0_sqmuxa_i.BLIF un1_UDS_000_INT_0_sqmuxa +.names N_137_i.BLIF N_137 0 1 -.names N_145.BLIF N_145_i +.names N_142.BLIF N_142_i 0 1 -.names UDS_000_INT_0_sqmuxa_1.BLIF UDS_000_INT_0_sqmuxa_2.BLIF \ -UDS_000_INT_0_sqmuxa +.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_140 11 1 -.names N_145_i.BLIF N_146_i.BLIF sm_amiga_ns_0_7__n +.names clk_cpu_est_11_0_1_1__n.BLIF clk_cpu_est_11_0_2_1__n.BLIF \ +clk_cpu_est_11_0_1__n 11 1 -.names N_139_i.BLIF state_machine_un15_clk_000_d_i_n.BLIF LDS_000_INT_1_sqmuxa +.names N_137_i.BLIF cpu_est_0_.BLIF N_141 +11 1 +.names N_140.BLIF N_140_i +0 1 +.names N_136_i.BLIF N_136 +0 1 +.names N_139.BLIF N_139_i +0 1 +.names N_136_i.BLIF cpu_est_3_reg.BLIF N_142 +11 1 +.names N_141.BLIF N_141_i +0 1 +.names N_138.BLIF cpu_est_3_reg.BLIF N_145 +11 1 +.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_138_i +11 1 +.names N_138_i.BLIF N_138 +0 1 +.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF N_137_i +11 1 +.names N_138_i.BLIF cpu_est_i_2__n.BLIF N_146 +11 1 +.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_136_i +11 1 +.names N_143_1.BLIF cpu_est_i_3__n.BLIF N_143 +11 1 +.names N_143.BLIF N_143_i +0 1 +.names N_144_1.BLIF cpu_est_i_2__n.BLIF N_144 11 1 .names N_144.BLIF N_144_i 0 1 -.names N_120.BLIF sm_amiga_i_5__n.BLIF N_139 +.names UDS_000_INT_0_sqmuxa_1_0.BLIF UDS_000_INT_0_sqmuxa_2.BLIF \ +UDS_000_INT_0_sqmuxa 11 1 -.names N_150.BLIF N_150_i -0 1 -.names inst_CLK_000_D.BLIF N_126.BLIF N_140 +.names N_143_i.BLIF N_144_i.BLIF N_134_i 11 1 -.names N_126_0.BLIF N_126 -0 1 -.names size_c_1__n.BLIF size_c_i_1__n -0 1 -.names N_121_i.BLIF SM_AMIGA_3_.BLIF N_141 +.names UDS_000_INT_0_sqmuxa_1_3.BLIF clk_un3_clk_000_dd_n.BLIF \ +UDS_000_INT_0_sqmuxa_1 11 1 -.names state_machine_un25_clk_000_d_i_1_n.BLIF size_c_i_1__n.BLIF \ -state_machine_un25_clk_000_d_i_n +.names SM_AMIGA_3_.BLIF state_machine_un57_clk_000_d_0_n.BLIF N_101_0 11 1 -.names N_121_i.BLIF N_121 -0 1 -.names state_machine_un80_clk_000_d_n.BLIF state_machine_un80_clk_000_d_i_n -0 1 -.names N_142_1.BLIF SM_AMIGA_3_.BLIF N_142 +.names N_147_1.BLIF cpu_est_i_2__n.BLIF N_147 11 1 -.names state_machine_un67_clk_000_d_n.BLIF state_machine_un67_clk_000_d_i_n +.names N_115.BLIF N_115_i 0 1 -.names inst_CLK_000_D.BLIF SM_AMIGA_3_.BLIF VPA_SYNC_1_sqmuxa_1_0 +.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_147_1 11 1 -.names state_machine_un67_clk_000_d_i_n.BLIF \ -state_machine_un80_clk_000_d_i_n.BLIF state_machine_un78_clk_000_d_0_n +.names N_116.BLIF N_116_i +0 1 +.names inst_AS_000_INTreg.BLIF inst_CLK_000_D.BLIF \ +state_machine_un13_clk_000_d_1_n +11 1 +.names N_186_5.BLIF N_186_6.BLIF N_186 +11 1 +.names N_124.BLIF N_124_i +0 1 +.names N_189_1.BLIF N_189_2.BLIF N_189 +11 1 +.names state_machine_un42_clk_030_4_n.BLIF state_machine_un42_clk_030_5_n.BLIF \ +state_machine_un42_clk_030_n +11 1 +.names N_112.BLIF N_112_i +0 1 +.names un1_bg_030_0.BLIF un1_bg_030 +0 1 +.names N_111_i.BLIF N_112_i.BLIF sm_amiga_ns_0_0__n +11 1 +.names state_machine_as_030_000_sync_3_2_n.BLIF \ +state_machine_as_030_000_sync_3_n +0 1 +.names N_109_i.BLIF N_111_i.BLIF N_86_i_1 +11 1 +.names un1_as_030_2_0.BLIF un1_as_030_2 +0 1 +.names BG_030_c_i.BLIF CPU_SPACE_i.BLIF un1_bg_030_0_1 +11 1 +.names state_machine_un17_clk_030_0_n.BLIF state_machine_un17_clk_030_n +0 1 +.names AS_030_c.BLIF N_109_i.BLIF un1_bg_030_0_2 +11 1 +.names state_machine_un1_clk_030_0_n.BLIF state_machine_un1_clk_030_n +0 1 +.names AS_030_i.BLIF CPU_SPACE_i.BLIF state_machine_as_030_000_sync_3_2_1_n +11 1 +.names state_machine_un4_bgack_000_0_n.BLIF state_machine_un4_bgack_000_n +0 1 +.names size_c_0__n.BLIF a_c_i_0__n.BLIF state_machine_un31_clk_000_d_i_1_n +11 1 +.names N_108_1.BLIF sm_amiga_i_3__n.BLIF N_108 +11 1 +.names a_i_24__n.BLIF a_i_25__n.BLIF N_186_1 +11 1 +.names state_machine_un31_clk_000_d_i_n.BLIF state_machine_un31_clk_000_d_n +0 1 +.names a_i_26__n.BLIF a_i_27__n.BLIF N_186_2 +11 1 +.names state_machine_un13_clk_000_d_1_0_n.BLIF \ +state_machine_un13_clk_000_d_4_n.BLIF state_machine_un13_clk_000_d_n +11 1 +.names a_i_28__n.BLIF a_i_29__n.BLIF N_186_3 +11 1 +.names state_machine_un13_clk_000_d_4_1_n.BLIF cpu_est_d_2_.BLIF \ +state_machine_un13_clk_000_d_4_n +11 1 +.names a_i_30__n.BLIF a_i_31__n.BLIF N_186_4 +11 1 +.names state_machine_un8_clk_000_d_4_n.BLIF \ +state_machine_un8_clk_000_d_3_n.BLIF state_machine_un8_clk_000_d_n +11 1 +.names N_186_1.BLIF N_186_2.BLIF N_186_5 11 1 .names DTACK_SYNC_1_sqmuxa_1_0.BLIF VPA_SYNC_1_sqmuxa_1_0.BLIF \ DTACK_SYNC_1_sqmuxa 11 1 -.names clk_rising_clk_amiga_1_n.BLIF clk_rising_clk_amiga_1_i_n +.names N_186_3.BLIF N_186_4.BLIF N_186_6 +11 1 +.names inst_CLK_000_D.BLIF SM_AMIGA_3_.BLIF VPA_SYNC_1_sqmuxa_1_0 +11 1 +.names a_c_20__n.BLIF a_c_21__n.BLIF N_189_1 +11 1 +.names VPA_SYNC_1_sqmuxa_4.BLIF VPA_SYNC_1_sqmuxa_3.BLIF VPA_SYNC_1_sqmuxa +11 1 +.names a_c_22__n.BLIF a_c_23__n.BLIF N_189_2 +11 1 +.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_123 +11 1 +.names N_139_i.BLIF N_140_i.BLIF clk_cpu_est_11_0_1_1__n +11 1 +.names N_118_1.BLIF state_machine_un57_clk_000_d_n.BLIF N_118 +11 1 +.names N_141_i.BLIF N_142_i.BLIF clk_cpu_est_11_0_2_1__n +11 1 +.names N_110_1.BLIF SM_AMIGA_1_.BLIF N_110 +11 1 +.names N_147_i.BLIF N_145_i.BLIF clk_cpu_est_11_0_1_3__n +11 1 +.names N_102_0.BLIF N_102 0 1 +.names N_136.BLIF cpu_est_0_.BLIF N_143_1 +11 1 +.names SM_AMIGA_0_.BLIF state_machine_un13_clk_000_d_1_i_n.BLIF N_120 +11 1 +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_144_1 +11 1 +.names CLK_000_D_i.BLIF N_102.BLIF N_119 +11 1 +.names sm_amiga_i_0__n.BLIF sm_amiga_i_2__n.BLIF N_106_1 +11 1 +.names CLK_000_D_i.BLIF SM_AMIGA_2_.BLIF N_117 +11 1 +.names sm_amiga_i_4__n.BLIF sm_amiga_i_6__n.BLIF N_106_2 +11 1 +.names inst_CLK_000_D.BLIF SM_AMIGA_5_.BLIF N_113 +11 1 +.names N_124.BLIF sm_amiga_i_0__n.BLIF N_107_1 +11 1 +.names state_machine_lds_000_int_8_0_n.BLIF state_machine_lds_000_int_8_n +0 1 +.names AS_030_000_SYNC_i.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_1 +11 1 +.names state_machine_uds_000_int_8_0_n.BLIF state_machine_uds_000_int_8_n +0 1 +.names RW_c.BLIF SM_AMIGA_6_.BLIF UDS_000_INT_0_sqmuxa_1_2 +11 1 .names AS_030_i.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF DTACK_SYNC_1_sqmuxa_1 11 1 -.names N_135.BLIF N_135_i -0 1 -.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_149_2 +.names UDS_000_INT_0_sqmuxa_1_1.BLIF UDS_000_INT_0_sqmuxa_1_2.BLIF \ +UDS_000_INT_0_sqmuxa_1_3 11 1 -.names N_135_i.BLIF clk_rising_clk_amiga_1_i_n.BLIF N_104_i +.names AS_030_i.BLIF N_161.BLIF un2_clk_030_1 11 1 -.names inst_CLK_000_D.BLIF CLK_000_DD_i.BLIF clk_un3_clk_000_dd_n +.names inst_CLK_000_D.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_0 11 1 -.names N_149.BLIF N_149_i -0 1 -.names N_164_i.BLIF N_164 -0 1 -.names inst_DTACK_SYNC.BLIF N_149_i.BLIF N_119_0 +.names AS_030_i.BLIF VPA_SYNC_1_sqmuxa_i.BLIF VPA_SYNC_1_sqmuxa_1 11 1 -.names N_171_1.BLIF cpu_est_i_2__n.BLIF N_171 +.names RW_i.BLIF SM_AMIGA_4_.BLIF UDS_000_INT_0_sqmuxa_2 11 1 -.names CLK_000_CNT_1_.BLIF clk_000_cnt_i_1__n -0 1 -.names N_170_1.BLIF cpu_est_i_3__n.BLIF N_170 +.names AS_030_i.BLIF N_114_i.BLIF AS_000_INT_1_sqmuxa 11 1 -.names CLK_000_CNT_0_.BLIF clk_000_cnt_i_0__n -0 1 -.names clk_cpu_est_11_0_3__n.BLIF clk_cpu_est_11_3__n -0 1 -.names CLK_000_CNT_3_.BLIF clk_000_cnt_i_3__n -0 1 -.names N_174_1.BLIF cpu_est_i_2__n.BLIF N_174 -11 1 -.names CLK_000_CNT_2_.BLIF clk_000_cnt_i_2__n -0 1 -.names N_165.BLIF cpu_est_3_reg.BLIF N_172 -11 1 -.names state_machine_un69_clk_000_d_0_1_n.BLIF \ -state_machine_un69_clk_000_d_0_2_n.BLIF state_machine_un69_clk_000_d_0_n -11 1 -.names N_165_i.BLIF cpu_est_i_2__n.BLIF N_173 -11 1 -.names clk_000_cnt_i_0__n.BLIF clk_000_cnt_i_1__n.BLIF \ -state_machine_un69_clk_000_d_0_1_n -11 1 -.names clk_cpu_est_11_0_1__n.BLIF clk_cpu_est_11_1__n -0 1 -.names clk_000_cnt_i_2__n.BLIF clk_000_cnt_i_3__n.BLIF \ -state_machine_un69_clk_000_d_0_2_n -11 1 -.names N_149_2.BLIF cpu_est_3_reg.BLIF N_169 -11 1 -.names size_c_0__n.BLIF a_c_i_0__n.BLIF state_machine_un25_clk_000_d_i_1_n -11 1 -.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_167 -11 1 -.names N_143_i.BLIF N_144_i.BLIF N_116_i_1 -11 1 -.names N_164.BLIF cpu_est_i_0__n.BLIF N_166 -11 1 -.names BG_030_c_i.BLIF CPU_SPACE_i.BLIF un1_bg_030_0_1 -11 1 -.names N_164_i.BLIF cpu_est_0_.BLIF N_168 -11 1 -.names AS_030_c.BLIF N_133_i.BLIF un1_bg_030_0_2 -11 1 -.names N_165_i.BLIF N_165 -0 1 -.names AS_030_i.BLIF CPU_SPACE_i.BLIF state_machine_as_030_000_sync_3_2_1_n -11 1 -.names VMA_INT_1_sqmuxa_0.BLIF VMA_INT_1_sqmuxa -0 1 -.names N_122.BLIF sm_amiga_i_5__n.BLIF un1_UDS_000_INT_0_sqmuxa_i_1 -11 1 -.names CLK_000_D_i.BLIF inst_VPA_SYNC.BLIF N_147 -11 1 -.names N_174_i.BLIF N_172_i.BLIF clk_cpu_est_11_0_1_3__n -11 1 -.names AS_000_INT_i.BLIF inst_CLK_000_D.BLIF N_148 -11 1 -.names N_169_i.BLIF N_167_i.BLIF clk_cpu_est_11_0_1_1__n -11 1 -.names RW_c.BLIF RW_i -0 1 -.names N_166_i.BLIF N_168_i.BLIF clk_cpu_est_11_0_2_1__n -11 1 -.names clk_exp.BLIF clk_exp_i -0 1 -.names a_i_24__n.BLIF a_i_25__n.BLIF N_251_1 -11 1 -.names inst_CLK_000_DD.BLIF CLK_000_DD_i -0 1 -.names a_i_26__n.BLIF a_i_27__n.BLIF N_251_2 -11 1 -.names inst_CLK_000_D.BLIF CLK_000_D_i -0 1 -.names a_i_28__n.BLIF a_i_29__n.BLIF N_251_3 -11 1 -.names inst_AS_000_INTreg.BLIF AS_000_INT_i -0 1 -.names a_i_30__n.BLIF a_i_31__n.BLIF N_251_4 -11 1 -.names cpu_est_0_.BLIF cpu_est_i_0__n -0 1 -.names N_251_1.BLIF N_251_2.BLIF N_251_5 -11 1 -.names cpu_est_2_.BLIF cpu_est_i_2__n -0 1 -.names N_251_3.BLIF N_251_4.BLIF N_251_6 -11 1 -.names cpu_est_3_reg.BLIF cpu_est_i_3__n -0 1 -.names a_c_20__n.BLIF a_c_21__n.BLIF N_254_1 -11 1 -.names cpu_est_1_.BLIF cpu_est_i_1__n -0 1 -.names a_c_22__n.BLIF a_c_23__n.BLIF N_254_2 -11 1 -.names N_149_2.BLIF N_149_2_i -0 1 -.names AS_030_000_SYNC_i.BLIF CLK_000_D_i.BLIF DSACK_INT_1_sqmuxa_1_0 -11 1 -.names inst_VPA_D.BLIF VPA_D_i -0 1 -.names inst_CLK_OUT_PRE.BLIF SM_AMIGA_0_.BLIF DSACK_INT_1_sqmuxa_2 -11 1 -.names DTACK_c.BLIF DTACK_i -0 1 -.names DSACK_INT_1_sqmuxa_1_0.BLIF DSACK_INT_1_sqmuxa_2.BLIF \ -DSACK_INT_1_sqmuxa_3 -11 1 -.names inst_VPA_SYNC.BLIF VPA_SYNC_i -0 1 -.names N_149_2.BLIF VPA_SYNC_i.BLIF N_149_1 -11 1 -.names inst_DTACK_SYNC.BLIF DTACK_SYNC_i -0 1 -.names cpu_est_0_.BLIF cpu_est_3_reg.BLIF N_149_2_0 -11 1 -.names AS_030_c.BLIF AS_030_i -0 1 -.names N_150.BLIF sm_amiga_i_0__n.BLIF N_132_1 -11 1 -.names DTACK_SYNC_1_sqmuxa.BLIF DTACK_SYNC_1_sqmuxa_i -0 1 -.names N_151.BLIF sm_amiga_i_0__n.BLIF N_131_1 -11 1 -.names DS_030_c.BLIF DS_030_i -0 1 .names a_c_17__n.BLIF a_i_16__n.BLIF state_machine_un42_clk_030_1_n 11 1 -.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n -0 1 +.names state_machine_un8_clk_000_d_i_n.BLIF \ +state_machine_un13_clk_000_d_i_n.BLIF VMA_INT_1_sqmuxa +11 1 .names a_i_18__n.BLIF a_i_19__n.BLIF state_machine_un42_clk_030_2_n 11 1 -.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n -0 1 +.names AS_030_i.BLIF N_110_i.BLIF DSACK_INT_1_sqmuxa +11 1 .names fc_c_1__n.BLIF BGACK_000_c.BLIF state_machine_un42_clk_030_3_n 11 1 -.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +.names RW_c.BLIF RW_i 0 1 .names state_machine_un42_clk_030_1_n.BLIF state_machine_un42_clk_030_2_n.BLIF \ state_machine_un42_clk_030_4_n 11 1 -.names N_139.BLIF N_139_i +.names clk_exp.BLIF clk_exp_i 0 1 .names state_machine_un42_clk_030_3_n.BLIF fc_c_0__n.BLIF \ state_machine_un42_clk_030_5_n 11 1 -.names state_machine_un15_clk_000_d_n.BLIF state_machine_un15_clk_000_d_i_n +.names DTACK_SYNC_1_sqmuxa.BLIF DTACK_SYNC_1_sqmuxa_i 0 1 -.names CLK_000_D_i.BLIF N_121.BLIF N_142_1 +.names cpu_est_d_i_0__n.BLIF cpu_est_d_i_3__n.BLIF \ +state_machine_un13_clk_000_d_1_0_n 11 1 -.names N_130.BLIF N_130_i +.names N_114.BLIF N_114_i 0 1 -.names sm_amiga_i_0__n.BLIF sm_amiga_i_2__n.BLIF N_130_1 -11 1 -.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n -0 1 -.names sm_amiga_i_4__n.BLIF sm_amiga_i_6__n.BLIF N_130_2 -11 1 -.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n -0 1 -.names inst_CLK_000_D.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1 +.names state_machine_un13_clk_000_d_1_n.BLIF cpu_est_d_1_.BLIF \ +state_machine_un13_clk_000_d_4_1_n 11 1 .names VPA_SYNC_1_sqmuxa.BLIF VPA_SYNC_1_sqmuxa_i 0 1 -.names RW_i.BLIF SM_AMIGA_4_.BLIF UDS_000_INT_0_sqmuxa_2 +.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF state_machine_un8_clk_000_d_1_n 11 1 -.names dsack_c_1__n.BLIF dsack_i_1__n +.names N_110.BLIF N_110_i +0 1 +.names CLK_000_D_i.BLIF VPA_D_i.BLIF state_machine_un8_clk_000_d_2_n +11 1 +.names N_108.BLIF N_108_i +0 1 +.names cpu_est_0_.BLIF cpu_est_2_.BLIF state_machine_un8_clk_000_d_3_n +11 1 +.names cpu_est_d_3_.BLIF cpu_est_d_i_3__n +0 1 +.names state_machine_un8_clk_000_d_1_n.BLIF \ +state_machine_un8_clk_000_d_2_n.BLIF state_machine_un8_clk_000_d_4_n +11 1 +.names cpu_est_d_0_.BLIF cpu_est_d_i_0__n 0 1 .names DTACK_i.BLIF inst_VPA_D.BLIF DTACK_SYNC_1_sqmuxa_1_0 11 1 -.names DSACK_INT_1_sqmuxa.BLIF DSACK_INT_1_sqmuxa_i +.names inst_CLK_000_D.BLIF CLK_000_D_i 0 1 -.names N_164_i.BLIF VPA_D_i.BLIF VPA_SYNC_1_sqmuxa_1_1 +.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF VPA_SYNC_1_sqmuxa_1_1 11 1 -.names a_c_18__n.BLIF a_i_18__n +.names AS_030_c.BLIF AS_030_i 0 1 -.names VPA_SYNC_1_sqmuxa_1_0.BLIF cpu_est_0_.BLIF VPA_SYNC_1_sqmuxa_2 +.names N_147_1.BLIF VMA_INT_i.BLIF VPA_SYNC_1_sqmuxa_2 11 1 -.names a_c_16__n.BLIF a_i_16__n +.names inst_AS_000_INTreg.BLIF AS_000_INT_i 0 1 -.names VPA_SYNC_1_sqmuxa_1_1.BLIF VPA_SYNC_1_sqmuxa_2.BLIF VPA_SYNC_1_sqmuxa_3 +.names VPA_D_i.BLIF VPA_SYNC_1_sqmuxa_1_0.BLIF VPA_SYNC_1_sqmuxa_3 11 1 -.names a_c_19__n.BLIF a_i_19__n +.names dsack_c_1__n.BLIF dsack_i_1__n 0 1 -.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_171_1 +.names VPA_SYNC_1_sqmuxa_1_1.BLIF VPA_SYNC_1_sqmuxa_2.BLIF VPA_SYNC_1_sqmuxa_4 11 1 -.names CLK_030_c.BLIF CLK_030_i +.names state_machine_un13_clk_000_d_n.BLIF state_machine_un13_clk_000_d_i_n 0 1 -.names N_149_2_i.BLIF cpu_est_0_.BLIF N_170_1 +.names N_123.BLIF sm_amiga_i_0__n.BLIF N_108_1 11 1 -.names state_machine_un42_clk_030_n.BLIF state_machine_un42_clk_030_i_n +.names state_machine_un8_clk_000_d_n.BLIF state_machine_un8_clk_000_d_i_n 0 1 -.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_174_1 +.names CLK_000_D_i.BLIF SM_AMIGA_3_.BLIF N_118_1 11 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +.names state_machine_un13_clk_000_d_1_n.BLIF \ +state_machine_un13_clk_000_d_1_i_n 0 1 -.names G_124.BLIF G_122.BLIF clk_exp_1 -11 1 -.names N_131.BLIF N_131_i -0 1 -.names clk_un3_clk_000_dd_n.BLIF cpu_est_0_1__un3_n -0 1 -.names N_132.BLIF N_132_i -0 1 -.names clk_cpu_est_11_1__n.BLIF clk_un3_clk_000_dd_n.BLIF cpu_est_0_1__un1_n -11 1 -.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n -0 1 -.names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n +.names CLK_000_D_i.BLIF inst_CLK_OUT_PRE.BLIF N_110_1 11 1 .names SM_AMIGA_1_.BLIF sm_amiga_i_1__n 0 1 +.names G_100.BLIF G_98.BLIF clk_exp_1 +11 1 +.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n +0 1 +.names RST_c.BLIF sm_amiga_d_0_2__un3_n +0 1 +.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n +0 1 +.names N_108_i.BLIF RST_c.BLIF sm_amiga_d_0_2__un1_n +11 1 +.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n +0 1 +.names SM_AMIGA_D_2_.BLIF sm_amiga_d_0_2__un3_n.BLIF sm_amiga_d_0_2__un0_n +11 1 +.names inst_VPA_D.BLIF VPA_D_i +0 1 +.names DSACK_INT_1_sqmuxa.BLIF dsack_int_0_1__un3_n +0 1 +.names inst_VMA_INTreg.BLIF VMA_INT_i +0 1 +.names DSACK_INT_1_.BLIF DSACK_INT_1_sqmuxa.BLIF dsack_int_0_1__un1_n +11 1 +.names DTACK_c.BLIF DTACK_i +0 1 +.names N_110_i.BLIF dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un0_n +11 1 +.names cpu_est_3_reg.BLIF cpu_est_i_3__n +0 1 .names VMA_INT_1_sqmuxa.BLIF vma_int_0_un3_n 0 1 -.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n +.names a_c_18__n.BLIF a_i_18__n 0 1 .names inst_VMA_INTreg.BLIF VMA_INT_1_sqmuxa.BLIF vma_int_0_un1_n 11 1 -.names CLK_000_c.BLIF CLK_000_i +.names a_c_16__n.BLIF a_i_16__n 0 1 -.names inst_CLK_000_D.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n +.names state_machine_un13_clk_000_d_4_n.BLIF vma_int_0_un3_n.BLIF \ +vma_int_0_un0_n 11 1 -.names a_c_30__n.BLIF a_i_30__n +.names a_c_19__n.BLIF a_i_19__n 0 1 -.names clk_un3_clk_000_dd_n.BLIF cpu_est_0_3__un3_n +.names VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un3_n 0 1 -.names a_c_31__n.BLIF a_i_31__n +.names CLK_030_c.BLIF CLK_030_i 0 1 -.names clk_cpu_est_11_3__n.BLIF clk_un3_clk_000_dd_n.BLIF cpu_est_0_3__un1_n +.names inst_VPA_SYNC.BLIF VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un1_n 11 1 -.names a_c_28__n.BLIF a_i_28__n +.names state_machine_un42_clk_030_n.BLIF state_machine_un42_clk_030_i_n 0 1 -.names cpu_est_3_reg.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n +.names VPA_SYNC_1_sqmuxa_i.BLIF vpa_sync_0_un3_n.BLIF vpa_sync_0_un0_n 11 1 -.names a_c_29__n.BLIF a_i_29__n +.names DS_030_c.BLIF DS_030_i 0 1 -.names clk_un3_clk_000_dd_n.BLIF cpu_est_0_2__un3_n +.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n 0 1 -.names a_c_26__n.BLIF a_i_26__n +.names cpu_est_1_.BLIF cpu_est_i_1__n 0 1 -.names N_161_i.BLIF clk_un3_clk_000_dd_n.BLIF cpu_est_0_2__un1_n +.names inst_AS_000_INTreg.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n 11 1 -.names a_c_27__n.BLIF a_i_27__n +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i 0 1 -.names cpu_est_2_.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n +.names N_114_i.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n 11 1 -.names a_c_24__n.BLIF a_i_24__n +.names cpu_est_0_.BLIF cpu_est_i_0__n 0 1 .names DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un3_n 0 1 -.names a_c_25__n.BLIF a_i_25__n +.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n 0 1 .names inst_DTACK_SYNC.BLIF DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un1_n 11 1 +.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n +0 1 .names DTACK_SYNC_1_sqmuxa_i.BLIF dtack_sync_0_un3_n.BLIF dtack_sync_0_un0_n 11 1 -.names RST_c.BLIF sm_amiga_d_0_0__un3_n +.names cpu_est_2_.BLIF cpu_est_i_2__n 0 1 -.names RST_c.BLIF RST_i +.names un2_clk_030_1.BLIF lds_000_int_0_un3_n 0 1 -.names N_130_i.BLIF RST_c.BLIF sm_amiga_d_0_0__un1_n +.names UDS_000_INT_0_sqmuxa_1.BLIF UDS_000_INT_0_sqmuxa_1_i +0 1 +.names inst_LDS_000_INTreg.BLIF un2_clk_030_1.BLIF lds_000_int_0_un1_n 11 1 -.names SM_AMIGA_D_0_.BLIF sm_amiga_d_0_0__un3_n.BLIF sm_amiga_d_0_0__un0_n +.names UDS_000_INT_0_sqmuxa.BLIF UDS_000_INT_0_sqmuxa_i +0 1 +.names state_machine_lds_000_int_8_n.BLIF lds_000_int_0_un3_n.BLIF \ +lds_000_int_0_un0_n 11 1 -.names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i +.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n 0 1 -.names state_machine_un4_bgack_000_n.BLIF bgack_030_int_0_un3_n +.names un2_clk_030_1.BLIF uds_000_int_0_un3_n 0 1 -.names CPU_SPACE_c.BLIF CPU_SPACE_i +.names inst_CLK_000_DD.BLIF CLK_000_DD_i 0 1 -.names BGACK_000_c.BLIF state_machine_un4_bgack_000_n.BLIF \ -bgack_030_int_0_un1_n +.names inst_UDS_000_INTreg.BLIF un2_clk_030_1.BLIF uds_000_int_0_un1_n 11 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i +.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n 0 1 -.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \ -bgack_030_int_0_un0_n +.names state_machine_uds_000_int_8_n.BLIF uds_000_int_0_un3_n.BLIF \ +uds_000_int_0_un0_n 11 1 +.names a_c_30__n.BLIF a_i_30__n +0 1 .names state_machine_un1_clk_030_n.BLIF bg_000_0_un3_n 0 1 +.names a_c_31__n.BLIF a_i_31__n +0 1 .names un1_bg_030.BLIF state_machine_un1_clk_030_n.BLIF bg_000_0_un1_n 11 1 +.names a_c_28__n.BLIF a_i_28__n +0 1 .names BG_000DFFSHreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n 11 1 +.names a_c_29__n.BLIF a_i_29__n +0 1 .names state_machine_un17_clk_030_n.BLIF as_030_000_sync_0_un3_n 0 1 +.names a_c_26__n.BLIF a_i_26__n +0 1 .names state_machine_as_030_000_sync_3_n.BLIF \ state_machine_un17_clk_030_n.BLIF as_030_000_sync_0_un1_n 11 1 +.names a_c_27__n.BLIF a_i_27__n +0 1 .names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF \ as_030_000_sync_0_un0_n 11 1 +.names a_c_24__n.BLIF a_i_24__n +0 1 .names state_machine_un17_clk_030_n.BLIF fpu_cs_int_0_un3_n 0 1 +.names a_c_25__n.BLIF a_i_25__n +0 1 .names un1_as_030_2.BLIF state_machine_un17_clk_030_n.BLIF fpu_cs_int_0_un1_n 11 1 .names inst_FPU_CS_INTreg.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un0_n 11 1 -.names DSACK_INT_1_sqmuxa_1.BLIF dsack_int_0_1__un3_n -0 1 -.names DSACK_INT_1_.BLIF DSACK_INT_1_sqmuxa_1.BLIF dsack_int_0_1__un1_n -11 1 -.names DSACK_INT_1_sqmuxa_i.BLIF dsack_int_0_1__un3_n.BLIF \ -dsack_int_0_1__un0_n -11 1 -.names VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un3_n -0 1 -.names inst_VPA_SYNC.BLIF VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un1_n -11 1 -.names VPA_SYNC_1_sqmuxa_i.BLIF vpa_sync_0_un3_n.BLIF vpa_sync_0_un0_n -11 1 -.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n -0 1 -.names inst_AS_000_INTreg.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n -11 1 -.names N_122.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n -11 1 .names inst_RISING_CLK_AMIGA.BLIF ipl_030_0_2__un3_n 0 1 +.names RST_c.BLIF RST_i +0 1 .names ipl_c_2__n.BLIF inst_RISING_CLK_AMIGA.BLIF ipl_030_0_2__un1_n 11 1 +.names N_107.BLIF N_107_i +0 1 .names IPL_030DFFSH_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n 11 1 +.names N_106.BLIF N_106_i +0 1 .names inst_RISING_CLK_AMIGA.BLIF ipl_030_0_1__un3_n 0 1 +.names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i +0 1 .names ipl_c_1__n.BLIF inst_RISING_CLK_AMIGA.BLIF ipl_030_0_1__un1_n 11 1 +.names CPU_SPACE_c.BLIF CPU_SPACE_i +0 1 .names IPL_030DFFSH_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n 11 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i +0 1 .names inst_RISING_CLK_AMIGA.BLIF ipl_030_0_0__un3_n 0 1 .names ipl_c_0__n.BLIF inst_RISING_CLK_AMIGA.BLIF ipl_030_0_0__un1_n 11 1 .names IPL_030DFFSH_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n 11 1 -.names RST_c.BLIF sm_amiga_d_0_2__un3_n +.names state_machine_un4_bgack_000_n.BLIF bgack_030_int_0_un3_n 0 1 -.names N_132_i.BLIF RST_c.BLIF sm_amiga_d_0_2__un1_n +.names BGACK_000_c.BLIF state_machine_un4_bgack_000_n.BLIF \ +bgack_030_int_0_un1_n 11 1 -.names SM_AMIGA_D_2_.BLIF sm_amiga_d_0_2__un3_n.BLIF sm_amiga_d_0_2__un0_n +.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \ +bgack_030_int_0_un0_n +11 1 +.names RST_c.BLIF sm_amiga_d_0_0__un3_n +0 1 +.names N_106_i.BLIF RST_c.BLIF sm_amiga_d_0_0__un1_n +11 1 +.names SM_AMIGA_D_0_.BLIF sm_amiga_d_0_0__un3_n.BLIF sm_amiga_d_0_0__un0_n 11 1 .names RST_c.BLIF sm_amiga_d_0_1__un3_n 0 1 -.names N_131_i.BLIF RST_c.BLIF sm_amiga_d_0_1__un1_n +.names N_107_i.BLIF RST_c.BLIF sm_amiga_d_0_1__un1_n 11 1 .names SM_AMIGA_D_1_.BLIF sm_amiga_d_0_1__un3_n.BLIF sm_amiga_d_0_1__un0_n 11 1 -.names LDS_000_INT_0_sqmuxa.BLIF lds_000_int_0_un3_n +.names clk_un3_clk_000_dd_n.BLIF cpu_est_0_1__un3_n 0 1 -.names inst_LDS_000_INTreg.BLIF LDS_000_INT_0_sqmuxa.BLIF lds_000_int_0_un1_n +.names clk_cpu_est_11_1__n.BLIF clk_un3_clk_000_dd_n.BLIF cpu_est_0_1__un1_n 11 1 -.names state_machine_lds_000_int_8_n.BLIF lds_000_int_0_un3_n.BLIF \ -lds_000_int_0_un0_n +.names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n 11 1 -.names LDS_000_INT_0_sqmuxa.BLIF uds_000_int_0_un3_n +.names clk_un3_clk_000_dd_n.BLIF cpu_est_0_2__un3_n 0 1 -.names inst_UDS_000_INTreg.BLIF LDS_000_INT_0_sqmuxa.BLIF uds_000_int_0_un1_n +.names N_134_i.BLIF clk_un3_clk_000_dd_n.BLIF cpu_est_0_2__un1_n 11 1 -.names state_machine_uds_000_int_8_n.BLIF uds_000_int_0_un3_n.BLIF \ -uds_000_int_0_un0_n +.names cpu_est_2_.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n +11 1 +.names clk_un3_clk_000_dd_n.BLIF cpu_est_0_3__un3_n +0 1 +.names clk_cpu_est_11_3__n.BLIF clk_un3_clk_000_dd_n.BLIF cpu_est_0_3__un1_n +11 1 +.names cpu_est_3_reg.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n 11 1 -.names un1_clk_000_cnt_3__n.BLIF un1_clk_000_cnt_2__n.BLIF G_128 -01 1 -10 1 -11 0 -00 0 -.names N_184.BLIF un1_clk_000_cnt_1__n.BLIF G_130 -01 1 -10 1 -11 0 -00 0 -.names N_186.BLIF un1_clk_000_cnt_0__n.BLIF G_132 -01 1 -10 1 -11 0 -00 0 .names cpu_est_0_.BLIF clk_un3_clk_000_dd_n.BLIF cpu_est_0_0_ 01 1 10 1 @@ -1090,17 +998,17 @@ uds_000_int_0_un0_n 10 1 11 0 00 0 -.names SM_AMIGA_D_0_.BLIF N_130.BLIF G_122 +.names SM_AMIGA_D_0_.BLIF N_106.BLIF G_98 01 1 10 1 11 0 00 0 -.names SM_AMIGA_D_1_.BLIF N_131.BLIF G_123 +.names SM_AMIGA_D_1_.BLIF N_107.BLIF G_99 01 1 10 1 11 0 00 0 -.names SM_AMIGA_D_2_.BLIF N_132.BLIF G_124 +.names SM_AMIGA_D_2_.BLIF N_108.BLIF G_100 01 1 10 1 11 0 @@ -1159,7 +1067,7 @@ uds_000_int_0_un0_n .names vcc_n_n.BLIF AMIGA_BUS_ENABLE_LOW 1 1 0 0 -.names N_254.BLIF CIIN +.names N_189.BLIF CIIN 1 1 0 0 .names IPL_030DFFSH_1_reg.BLIF IPL_030_1_ @@ -1168,6 +1076,18 @@ uds_000_int_0_un0_n .names IPL_030DFFSH_0_reg.BLIF IPL_030_0_ 1 1 0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C +1 1 +0 0 +.names RST_i.BLIF SM_AMIGA_6_.AR +1 1 +0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C +1 1 +0 0 +.names RST_i.BLIF SM_AMIGA_5_.AR +1 1 +0 0 .names CLK_OSZI_c.BLIF SM_AMIGA_4_.C 1 1 0 0 @@ -1198,6 +1118,18 @@ uds_000_int_0_un0_n .names RST_i.BLIF SM_AMIGA_0_.AR 1 1 0 0 +.names CLK_OSZI_c.BLIF IPL_030DFFSH_1_reg.C +1 1 +0 0 +.names RST_i.BLIF IPL_030DFFSH_1_reg.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF IPL_030DFFSH_2_reg.C +1 1 +0 0 +.names RST_i.BLIF IPL_030DFFSH_2_reg.AP +1 1 +0 0 .names cpu_est_0_0_.BLIF cpu_est_0_.D 1 1 0 0 @@ -1219,37 +1151,28 @@ uds_000_int_0_un0_n .names RST_i.BLIF SM_AMIGA_7_.AP 1 1 0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C +.names cpu_est_0_.BLIF cpu_est_d_0_.D 1 1 0 0 -.names RST_i.BLIF SM_AMIGA_6_.AR +.names CLK_OSZI_c.BLIF cpu_est_d_0_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C +.names cpu_est_1_.BLIF cpu_est_d_1_.D 1 1 0 0 -.names RST_i.BLIF SM_AMIGA_5_.AR +.names CLK_OSZI_c.BLIF cpu_est_d_1_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF CLK_000_CNT_0_.C +.names cpu_est_2_.BLIF cpu_est_d_2_.D 1 1 0 0 -.names G_128.BLIF CLK_000_CNT_1_.D +.names CLK_OSZI_c.BLIF cpu_est_d_2_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF CLK_000_CNT_1_.C +.names cpu_est_3_reg.BLIF cpu_est_d_3_.D 1 1 0 0 -.names G_130.BLIF CLK_000_CNT_2_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_CNT_2_.C -1 1 -0 0 -.names G_132.BLIF CLK_000_CNT_3_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_CNT_3_.C +.names CLK_OSZI_c.BLIF cpu_est_d_3_.C 1 1 0 0 .names CLK_OSZI_c.BLIF SM_AMIGA_D_0_.C @@ -1267,22 +1190,10 @@ uds_000_int_0_un0_n .names RST_i.BLIF IPL_030DFFSH_0_reg.AP 1 1 0 0 -.names CLK_OSZI_c.BLIF IPL_030DFFSH_1_reg.C +.names CLK_OSZI_c.BLIF inst_AS_000_INTreg.C 1 1 0 0 -.names RST_i.BLIF IPL_030DFFSH_1_reg.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF IPL_030DFFSH_2_reg.C -1 1 -0 0 -.names RST_i.BLIF IPL_030DFFSH_2_reg.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C -1 1 -0 0 -.names RST_i.BLIF inst_AS_030_000_SYNC.AP +.names RST_i.BLIF inst_AS_000_INTreg.AP 1 1 0 0 .names CLK_OSZI_c.BLIF inst_VPA_SYNC.C @@ -1291,16 +1202,10 @@ uds_000_int_0_un0_n .names RST_i.BLIF inst_VPA_SYNC.AP 1 1 0 0 -.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C +.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C 1 1 0 0 -.names RST_i.BLIF BG_000DFFSHreg.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_AS_000_INTreg.C -1 1 -0 0 -.names RST_i.BLIF inst_AS_000_INTreg.AP +.names RST_i.BLIF inst_AS_030_000_SYNC.AP 1 1 0 0 .names CLK_OSZI_c.BLIF inst_VMA_INTreg.C @@ -1309,6 +1214,18 @@ uds_000_int_0_un0_n .names RST_i.BLIF inst_VMA_INTreg.AP 1 1 0 0 +.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C +1 1 +0 0 +.names RST_i.BLIF BG_000DFFSHreg.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF DSACK_INT_1_.C +1 1 +0 0 +.names RST_i.BLIF DSACK_INT_1_.AP +1 1 +0 0 .names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C 1 1 0 0 @@ -1321,12 +1238,6 @@ uds_000_int_0_un0_n .names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE.C 1 1 0 0 -.names CLK_OSZI_c.BLIF DSACK_INT_1_.C -1 1 -0 0 -.names RST_i.BLIF DSACK_INT_1_.AP -1 1 -0 0 .names CLK_OSZI_c.BLIF inst_UDS_000_INTreg.C 1 1 0 0 @@ -1357,15 +1268,12 @@ uds_000_int_0_un0_n .names RST_i.BLIF inst_DTACK_DMA.AP 1 1 0 0 -.names CLK_OSZI_c.BLIF CLK_CNT_0_.C -1 1 -0 0 -.names clk_rising_clk_amiga_1_n.BLIF inst_RISING_CLK_AMIGA.D -1 1 -0 0 .names CLK_OSZI_c.BLIF inst_RISING_CLK_AMIGA.C 1 1 0 0 +.names CLK_OSZI_c.BLIF CLK_CNT_0_.C +1 1 +0 0 .names VPA.BLIF inst_VPA_D.D 1 1 0 0 @@ -1405,87 +1313,18 @@ uds_000_int_0_un0_n .names vcc_n_n.BLIF DSACK_0_ 1 1 0 0 -.names A_15_.BLIF a_15__n -1 1 -0 0 -.names A_22_.BLIF a_c_22__n -1 1 -0 0 -.names A_14_.BLIF a_14__n -1 1 -0 0 -.names A_23_.BLIF a_c_23__n -1 1 -0 0 -.names A_13_.BLIF a_13__n -1 1 -0 0 -.names A_24_.BLIF a_c_24__n -1 1 -0 0 -.names A_12_.BLIF a_12__n -1 1 -0 0 -.names A_25_.BLIF a_c_25__n -1 1 -0 0 -.names A_11_.BLIF a_11__n -1 1 -0 0 -.names A_26_.BLIF a_c_26__n -1 1 -0 0 -.names A_10_.BLIF a_10__n -1 1 -0 0 -.names A_27_.BLIF a_c_27__n -1 1 -0 0 -.names A_9_.BLIF a_9__n -1 1 -0 0 -.names A_28_.BLIF a_c_28__n -1 1 -0 0 -.names A_8_.BLIF a_8__n -1 1 -0 0 -.names A_29_.BLIF a_c_29__n -1 1 -0 0 -.names A_7_.BLIF a_7__n -1 1 -0 0 .names A_30_.BLIF a_c_30__n 1 1 0 0 -.names A_6_.BLIF a_6__n -1 1 -0 0 .names A_31_.BLIF a_c_31__n 1 1 0 0 -.names A_5_.BLIF a_5__n -1 1 -0 0 .names CPU_SPACE.BLIF CPU_SPACE_c 1 1 0 0 -.names A_4_.BLIF a_4__n -1 1 -0 0 .names BG_030.BLIF BG_030_c 1 1 0 0 -.names A_3_.BLIF a_3__n -1 1 -0 0 -.names A_2_.BLIF a_2__n -1 1 -0 0 -.names A_1_.BLIF a_1__n -1 1 -0 0 .names BGACK_000.BLIF BGACK_000_c 1 1 0 0 @@ -1540,24 +1379,93 @@ uds_000_int_0_un0_n .names A_0_.BLIF a_c_0__n 1 1 0 0 +.names A_15_.BLIF a_15__n +1 1 +0 0 +.names A_14_.BLIF a_14__n +1 1 +0 0 +.names A_13_.BLIF a_13__n +1 1 +0 0 +.names A_12_.BLIF a_12__n +1 1 +0 0 .names A_16_.BLIF a_c_16__n 1 1 0 0 +.names A_11_.BLIF a_11__n +1 1 +0 0 .names A_17_.BLIF a_c_17__n 1 1 0 0 +.names A_10_.BLIF a_10__n +1 1 +0 0 .names A_18_.BLIF a_c_18__n 1 1 0 0 +.names A_9_.BLIF a_9__n +1 1 +0 0 .names A_19_.BLIF a_c_19__n 1 1 0 0 +.names A_8_.BLIF a_8__n +1 1 +0 0 .names A_20_.BLIF a_c_20__n 1 1 0 0 +.names A_7_.BLIF a_7__n +1 1 +0 0 .names A_21_.BLIF a_c_21__n 1 1 0 0 +.names A_6_.BLIF a_6__n +1 1 +0 0 +.names A_22_.BLIF a_c_22__n +1 1 +0 0 +.names A_5_.BLIF a_5__n +1 1 +0 0 +.names A_23_.BLIF a_c_23__n +1 1 +0 0 +.names A_4_.BLIF a_4__n +1 1 +0 0 +.names A_24_.BLIF a_c_24__n +1 1 +0 0 +.names A_3_.BLIF a_3__n +1 1 +0 0 +.names A_25_.BLIF a_c_25__n +1 1 +0 0 +.names A_2_.BLIF a_2__n +1 1 +0 0 +.names A_26_.BLIF a_c_26__n +1 1 +0 0 +.names A_1_.BLIF a_1__n +1 1 +0 0 +.names A_27_.BLIF a_c_27__n +1 1 +0 0 +.names A_28_.BLIF a_c_28__n +1 1 +0 0 +.names A_29_.BLIF a_c_29__n +1 1 +0 0 .names CPU_SPACE_i.BLIF DSACK_1_.OE 1 1 0 0 @@ -1582,7 +1490,7 @@ uds_000_int_0_un0_n .names FPU_CS_INT_i.BLIF AVEC_EXP.OE 1 1 0 0 -.names N_251.BLIF CIIN.OE +.names N_186.BLIF CIIN.OE 1 1 0 0 .end diff --git a/Logic/68030_tk.bl3 b/Logic/68030_tk.bl3 index e27675d..0999ae7 100644 --- a/Logic/68030_tk.bl3 +++ b/Logic/68030_tk.bl3 @@ -1,21 +1,21 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Thu May 15 19:20:52 2014 +#$ DATE Thu May 15 22:17:27 2014 #$ MODULE 68030_tk -#$ PINS 59 A_30_ A_29_ SIZE_1_ A_28_ A_27_ A_31_ A_26_ A_25_ IPL_030_2_ A_24_ A_23_ \ -# IPL_2_ A_22_ A_21_ DSACK_1_ A_20_ A_19_ FC_1_ A_18_ AS_030 A_17_ AS_000 A_16_ DS_030 \ +#$ PINS 59 FC_0_ SIZE_1_ A_31_ IPL_030_2_ IPL_2_ DSACK_1_ FC_1_ AS_030 AS_000 DS_030 \ # UDS_000 LDS_000 CPU_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 \ -# CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS DTACK A_0_ AVEC IPL_030_1_ AVEC_EXP IPL_030_0_ E \ -# IPL_1_ VPA IPL_0_ VMA DSACK_0_ RST FC_0_ RESET RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR \ -# AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ -#$ NODES 43 inst_BGACK_030_INTreg inst_CLK_OUT_INTreg inst_FPU_CS_INTreg \ -# cpu_est_3_reg inst_VMA_INTreg cpu_est_1_ inst_AS_000_INTreg inst_AS_030_000_SYNC \ -# inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D inst_CLK_000_DD \ -# inst_CLK_OUT_PRE cpu_est_0_ cpu_est_2_ CLK_CNT_0_ SM_AMIGA_6_ BG_000DFFSHreg \ -# SM_AMIGA_7_ inst_UDS_000_INTreg inst_LDS_000_INTreg inst_RISING_CLK_AMIGA \ -# DSACK_INT_1_ inst_DTACK_DMA SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_5_ CLK_000_CNT_0_ \ -# CLK_000_CNT_1_ CLK_000_CNT_2_ CLK_000_CNT_3_ IPL_030DFFSH_0_reg SM_AMIGA_2_ \ -# IPL_030DFFSH_1_reg SM_AMIGA_1_ SM_AMIGA_0_ IPL_030DFFSH_2_reg SM_AMIGA_D_0_ \ -# SM_AMIGA_D_1_ SM_AMIGA_D_2_ RESETDFFreg un1_UDS_000_INT_0_sqmuxa_2_0 +# CLK_OSZI CLK_DIV_OUT SIZE_0_ CLK_EXP A_30_ FPU_CS A_29_ DTACK A_28_ AVEC A_27_ AVEC_EXP \ +# A_26_ E A_25_ VPA A_24_ VMA A_23_ RST A_22_ RESET A_21_ RW A_20_ AMIGA_BUS_ENABLE A_19_ \ +# AMIGA_BUS_DATA_DIR A_18_ AMIGA_BUS_ENABLE_LOW A_17_ CIIN A_16_ A_0_ IPL_030_1_ \ +# IPL_030_0_ IPL_1_ IPL_0_ DSACK_0_ +#$ NODES 42 inst_BGACK_030_INTreg inst_CLK_OUT_INTreg inst_FPU_CS_INTreg \ +# BG_000DFFSHreg cpu_est_3_reg inst_VMA_INTreg cpu_est_0_ cpu_est_1_ cpu_est_d_0_ \ +# cpu_est_d_3_ inst_AS_000_INTreg inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D \ +# inst_VPA_SYNC inst_CLK_000_D inst_CLK_000_DD IPL_030DFFSH_0_reg inst_CLK_OUT_PRE \ +# IPL_030DFFSH_1_reg cpu_est_d_1_ cpu_est_d_2_ IPL_030DFFSH_2_reg cpu_est_2_ \ +# CLK_CNT_0_ SM_AMIGA_6_ SM_AMIGA_7_ inst_UDS_000_INTreg inst_LDS_000_INTreg \ +# inst_RISING_CLK_AMIGA SM_AMIGA_1_ DSACK_INT_1_ inst_DTACK_DMA SM_AMIGA_4_ \ +# SM_AMIGA_3_ SM_AMIGA_5_ SM_AMIGA_2_ SM_AMIGA_0_ SM_AMIGA_D_0_ SM_AMIGA_D_1_ \ +# SM_AMIGA_D_2_ RESETDFFreg .model bus68030 .inputs SIZE_1_.BLIF A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF AS_030.BLIF DS_030.BLIF \ CPU_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF \ @@ -23,53 +23,68 @@ CLK_OSZI.BLIF VPA.BLIF RST.BLIF RW.BLIF SIZE_0_.BLIF A_30_.BLIF A_29_.BLIF \ A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF \ A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF A_0_.BLIF \ IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF inst_BGACK_030_INTreg.BLIF \ -inst_CLK_OUT_INTreg.BLIF inst_FPU_CS_INTreg.BLIF cpu_est_3_reg.BLIF \ -inst_VMA_INTreg.BLIF cpu_est_1_.BLIF inst_AS_000_INTreg.BLIF \ +inst_CLK_OUT_INTreg.BLIF inst_FPU_CS_INTreg.BLIF BG_000DFFSHreg.BLIF \ +cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \ +cpu_est_d_0_.BLIF cpu_est_d_3_.BLIF inst_AS_000_INTreg.BLIF \ inst_AS_030_000_SYNC.BLIF inst_DTACK_SYNC.BLIF inst_VPA_D.BLIF \ inst_VPA_SYNC.BLIF inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF \ -inst_CLK_OUT_PRE.BLIF cpu_est_0_.BLIF cpu_est_2_.BLIF CLK_CNT_0_.BLIF \ -SM_AMIGA_6_.BLIF BG_000DFFSHreg.BLIF SM_AMIGA_7_.BLIF inst_UDS_000_INTreg.BLIF \ -inst_LDS_000_INTreg.BLIF inst_RISING_CLK_AMIGA.BLIF DSACK_INT_1_.BLIF \ -inst_DTACK_DMA.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_5_.BLIF \ -CLK_000_CNT_0_.BLIF CLK_000_CNT_1_.BLIF CLK_000_CNT_2_.BLIF \ -CLK_000_CNT_3_.BLIF IPL_030DFFSH_0_reg.BLIF SM_AMIGA_2_.BLIF \ -IPL_030DFFSH_1_reg.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_0_.BLIF \ -IPL_030DFFSH_2_reg.BLIF SM_AMIGA_D_0_.BLIF SM_AMIGA_D_1_.BLIF \ -SM_AMIGA_D_2_.BLIF RESETDFFreg.BLIF un1_UDS_000_INT_0_sqmuxa_2_0.BLIF \ -DSACK_1_.PIN.BLIF DTACK.PIN.BLIF +IPL_030DFFSH_0_reg.BLIF inst_CLK_OUT_PRE.BLIF IPL_030DFFSH_1_reg.BLIF \ +cpu_est_d_1_.BLIF cpu_est_d_2_.BLIF IPL_030DFFSH_2_reg.BLIF cpu_est_2_.BLIF \ +CLK_CNT_0_.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_7_.BLIF inst_UDS_000_INTreg.BLIF \ +inst_LDS_000_INTreg.BLIF inst_RISING_CLK_AMIGA.BLIF SM_AMIGA_1_.BLIF \ +DSACK_INT_1_.BLIF inst_DTACK_DMA.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_3_.BLIF \ +SM_AMIGA_5_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_D_0_.BLIF \ +SM_AMIGA_D_1_.BLIF SM_AMIGA_D_2_.BLIF RESETDFFreg.BLIF DSACK_1_.PIN.BLIF \ +DTACK.PIN.BLIF .outputs IPL_030_2_ AS_000 UDS_000 LDS_000 BERR BG_000 BGACK_030 CLK_DIV_OUT \ FPU_CS AVEC AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR \ -AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_4_.D SM_AMIGA_4_.C \ -SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D \ -SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR \ -SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR cpu_est_0_.D cpu_est_0_.C \ +AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_6_.D SM_AMIGA_6_.C \ +SM_AMIGA_6_.AR SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D \ +SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR \ +SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C \ +SM_AMIGA_1_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR IPL_030DFFSH_1_reg.D \ +IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D \ +IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP cpu_est_0_.D cpu_est_0_.C \ cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_reg.C \ -SM_AMIGA_7_.D SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C \ -SM_AMIGA_6_.AR SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR CLK_000_CNT_0_.D \ -CLK_000_CNT_0_.C CLK_000_CNT_1_.D CLK_000_CNT_1_.C CLK_000_CNT_2_.D \ -CLK_000_CNT_2_.C CLK_000_CNT_3_.D CLK_000_CNT_3_.C SM_AMIGA_D_0_.D \ -SM_AMIGA_D_0_.C SM_AMIGA_D_1_.D SM_AMIGA_D_1_.C SM_AMIGA_D_2_.D \ -SM_AMIGA_D_2_.C IPL_030DFFSH_0_reg.D IPL_030DFFSH_0_reg.C \ -IPL_030DFFSH_0_reg.AP IPL_030DFFSH_1_reg.D IPL_030DFFSH_1_reg.C \ -IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D IPL_030DFFSH_2_reg.C \ -IPL_030DFFSH_2_reg.AP inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \ -inst_AS_030_000_SYNC.AP inst_VPA_SYNC.D inst_VPA_SYNC.C inst_VPA_SYNC.AP \ -BG_000DFFSHreg.D BG_000DFFSHreg.C BG_000DFFSHreg.AP inst_AS_000_INTreg.D \ -inst_AS_000_INTreg.C inst_AS_000_INTreg.AP inst_VMA_INTreg.D inst_VMA_INTreg.C \ -inst_VMA_INTreg.AP inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C \ -inst_BGACK_030_INTreg.AP inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C DSACK_INT_1_.C \ -DSACK_INT_1_.AP inst_UDS_000_INTreg.D inst_UDS_000_INTreg.C \ -inst_UDS_000_INTreg.AP inst_LDS_000_INTreg.D inst_LDS_000_INTreg.C \ -inst_LDS_000_INTreg.AP inst_DTACK_SYNC.D inst_DTACK_SYNC.C inst_DTACK_SYNC.AP \ -inst_FPU_CS_INTreg.D inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP \ -inst_DTACK_DMA.D inst_DTACK_DMA.C inst_DTACK_DMA.AP CLK_CNT_0_.D CLK_CNT_0_.C \ -inst_RISING_CLK_AMIGA.D inst_RISING_CLK_AMIGA.C inst_VPA_D.D inst_VPA_D.C \ -inst_CLK_000_D.D inst_CLK_000_D.C RESETDFFreg.D RESETDFFreg.C \ -inst_CLK_000_DD.D inst_CLK_000_DD.C inst_CLK_OUT_INTreg.D \ -inst_CLK_OUT_INTreg.C DSACK_1_ DTACK DSACK_0_ un1_UDS_000_INT_0_sqmuxa_2_0 \ -DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE \ -AVEC_EXP.OE CIIN.OE CLK_EXP.X1 CLK_EXP.X2 cpu_est_3_reg.D.X1 \ -cpu_est_3_reg.D.X2 DSACK_INT_1_.D.X1 DSACK_INT_1_.D.X2 +SM_AMIGA_7_.D SM_AMIGA_7_.C SM_AMIGA_7_.AP cpu_est_d_0_.D cpu_est_d_0_.C \ +cpu_est_d_1_.D cpu_est_d_1_.C cpu_est_d_2_.D cpu_est_d_2_.C cpu_est_d_3_.D \ +cpu_est_d_3_.C SM_AMIGA_D_0_.D SM_AMIGA_D_0_.C SM_AMIGA_D_1_.D SM_AMIGA_D_1_.C \ +SM_AMIGA_D_2_.D SM_AMIGA_D_2_.C IPL_030DFFSH_0_reg.D IPL_030DFFSH_0_reg.C \ +IPL_030DFFSH_0_reg.AP inst_AS_000_INTreg.D inst_AS_000_INTreg.C \ +inst_AS_000_INTreg.AP inst_VPA_SYNC.D inst_VPA_SYNC.C inst_VPA_SYNC.AP \ +inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP \ +inst_VMA_INTreg.C inst_VMA_INTreg.AP BG_000DFFSHreg.D BG_000DFFSHreg.C \ +BG_000DFFSHreg.AP DSACK_INT_1_.D DSACK_INT_1_.C DSACK_INT_1_.AP \ +inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP \ +inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C inst_UDS_000_INTreg.D \ +inst_UDS_000_INTreg.C inst_UDS_000_INTreg.AP inst_LDS_000_INTreg.D \ +inst_LDS_000_INTreg.C inst_LDS_000_INTreg.AP inst_DTACK_SYNC.D \ +inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_FPU_CS_INTreg.D inst_FPU_CS_INTreg.C \ +inst_FPU_CS_INTreg.AP inst_DTACK_DMA.D inst_DTACK_DMA.C inst_DTACK_DMA.AP \ +inst_RISING_CLK_AMIGA.D inst_RISING_CLK_AMIGA.C CLK_CNT_0_.D CLK_CNT_0_.C \ +inst_VPA_D.D inst_VPA_D.C inst_CLK_000_D.D inst_CLK_000_D.C RESETDFFreg.D \ +RESETDFFreg.C inst_CLK_000_DD.D inst_CLK_000_DD.C inst_CLK_OUT_INTreg.D \ +inst_CLK_OUT_INTreg.C DSACK_1_ DTACK DSACK_0_ DSACK_1_.OE DTACK.OE AS_000.OE \ +UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_EXP.X1 \ +CLK_EXP.X2 cpu_est_3_reg.D.X1 cpu_est_3_reg.D.X2 inst_VMA_INTreg.D.X1 \ +inst_VMA_INTreg.D.X2 +.names inst_AS_030_000_SYNC.BLIF inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF \ +SM_AMIGA_6_.BLIF SM_AMIGA_7_.BLIF SM_AMIGA_6_.D +--110 1 +1--10 1 +-0--1 1 +-0-1- 1 +010-- 0 +---00 0 +-1--1 0 +.names inst_AS_030_000_SYNC.BLIF inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF \ +SM_AMIGA_6_.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_5_.D +0101- 1 +-1--1 1 +-0--- 0 +---00 0 +--1-0 0 +1---0 0 .names inst_CLK_000_D.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_4_.D 01- 1 0-1 1 @@ -92,68 +107,62 @@ SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_2_.D 11--0 0 --1-- 0 ---00 0 -.names CLK_000.BLIF cpu_est_3_reg.BLIF cpu_est_1_.BLIF inst_DTACK_SYNC.BLIF \ -inst_VPA_SYNC.BLIF inst_CLK_000_D.BLIF cpu_est_0_.BLIF cpu_est_2_.BLIF \ -SM_AMIGA_2_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_1_.D ------1--1- 1 ----1---001 1 ----1--0-01 1 ----11---01 1 ---01----01 1 --0-1----01 1 -1-------01 1 -011-0-110- 0 -0--0----0- 0 ------0--1- 0 ---------00 0 -.names CLK_000.BLIF cpu_est_3_reg.BLIF cpu_est_1_.BLIF inst_AS_000_INTreg.BLIF \ -inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D.BLIF cpu_est_0_.BLIF \ -cpu_est_2_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_0_.D -011--0-111- 1 -0---0----1- 1 -------0---1 1 ----0------1 1 ----11-1-0-- 0 ----11-10--- 0 ----1111---- 0 ---011-1---- 0 --0-11-1---- 0 ----1--1--0- 0 -1--1--1---- 0 -----1---0-0 0 -----1--0--0 0 -----11----0 0 ---0-1-----0 0 --0--1-----0 0 ----------00 0 -1---------0 0 -.names cpu_est_3_reg.BLIF cpu_est_1_.BLIF inst_CLK_000_D.BLIF \ -inst_CLK_000_DD.BLIF cpu_est_0_.BLIF cpu_est_2_.BLIF cpu_est_1_.D -0-10-0 1 -00101- 1 -1-100- 1 --1--0- 1 -11---1 1 --1-1-- 1 --10--- 1 -011011 0 -1-1010 0 -00--01 0 -10--1- 0 --0-1-- 0 --00--- 0 -.names cpu_est_3_reg.BLIF cpu_est_1_.BLIF inst_CLK_000_D.BLIF \ -inst_CLK_000_DD.BLIF cpu_est_0_.BLIF cpu_est_2_.BLIF cpu_est_2_.D --0100- 1 -1-101- 1 --1---1 1 ----1-1 1 ---0--1 1 -0---10 0 -00101- 0 --1--00 0 ----1-0 0 ---0--0 0 +.names inst_CLK_000_D.BLIF inst_CLK_OUT_PRE.BLIF SM_AMIGA_1_.BLIF \ +SM_AMIGA_2_.BLIF SM_AMIGA_1_.D +-01- 1 +1-1- 1 +1--1 1 +01-- 0 +0-0- 0 +--00 0 +.names inst_AS_000_INTreg.BLIF inst_CLK_000_D.BLIF inst_CLK_OUT_PRE.BLIF \ +SM_AMIGA_1_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_0_.D +-011- 1 +0---1 1 +-0--1 1 +11--- 0 +---00 0 +--0-0 0 +-1--0 0 +.names IPL_1_.BLIF IPL_030DFFSH_1_reg.BLIF inst_RISING_CLK_AMIGA.BLIF \ +IPL_030DFFSH_1_reg.D +-10 1 +1-1 1 +-00 0 +0-1 0 +.names IPL_2_.BLIF IPL_030DFFSH_2_reg.BLIF inst_RISING_CLK_AMIGA.BLIF \ +IPL_030DFFSH_2_reg.D +-10 1 +1-1 1 +-00 0 +0-1 0 +.names cpu_est_3_reg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_CLK_000_D.BLIF \ +inst_CLK_000_DD.BLIF cpu_est_2_.BLIF cpu_est_1_.D +0--100 1 +01010- 1 +10-10- 1 +-01--- 1 +1-1--1 1 +--1-1- 1 +--10-- 1 +011101 0 +11-100 0 +000--1 0 +110--- 0 +--0-1- 0 +--00-- 0 +.names cpu_est_3_reg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_CLK_000_D.BLIF \ +inst_CLK_000_DD.BLIF cpu_est_2_.BLIF cpu_est_2_.D +-0010- 1 +11-10- 1 +--1--1 1 +----11 1 +---0-1 1 +0-1--0 0 +01010- 0 +-01--0 0 +----10 0 +---0-0 0 .names inst_AS_000_INTreg.BLIF inst_CLK_000_D.BLIF SM_AMIGA_7_.BLIF \ SM_AMIGA_0_.BLIF SM_AMIGA_7_.D -11- 1 @@ -161,27 +170,6 @@ SM_AMIGA_0_.BLIF SM_AMIGA_7_.D 0-0- 0 --00 0 -0-- 0 -.names inst_AS_030_000_SYNC.BLIF inst_CLK_000_D.BLIF SM_AMIGA_6_.BLIF \ -SM_AMIGA_7_.BLIF SM_AMIGA_6_.D --01- 1 -1-1- 1 --0-1 1 -01-- 0 --10- 0 ---00 0 -.names inst_AS_030_000_SYNC.BLIF inst_CLK_000_D.BLIF SM_AMIGA_6_.BLIF \ -SM_AMIGA_5_.BLIF SM_AMIGA_5_.D -011- 1 --1-1 1 --0-- 0 ---00 0 -1--0 0 -.names CLK_000.BLIF inst_CLK_000_D.BLIF CLK_000_CNT_0_.BLIF CLK_000_CNT_0_.D -10- 1 -01- 1 ---0 1 -001 0 -111 0 .names RST.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_2_.BLIF \ SM_AMIGA_0_.BLIF SM_AMIGA_D_0_.BLIF SM_AMIGA_D_0_.D 1---1- 1 @@ -191,7 +179,7 @@ SM_AMIGA_0_.BLIF SM_AMIGA_D_0_.BLIF SM_AMIGA_D_0_.D 0----1 1 10000- 0 0----0 0 -.names RST.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_1_.BLIF \ +.names RST.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_5_.BLIF \ SM_AMIGA_0_.BLIF SM_AMIGA_D_1_.BLIF SM_AMIGA_D_1_.D 1---1- 1 1--1-- 1 @@ -200,7 +188,7 @@ SM_AMIGA_0_.BLIF SM_AMIGA_D_1_.BLIF SM_AMIGA_D_1_.D 0----1 1 10000- 0 0----0 0 -.names RST.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_1_.BLIF \ +.names RST.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF \ SM_AMIGA_0_.BLIF SM_AMIGA_D_2_.BLIF SM_AMIGA_D_2_.D 1---1- 1 1--1-- 1 @@ -209,24 +197,45 @@ SM_AMIGA_0_.BLIF SM_AMIGA_D_2_.BLIF SM_AMIGA_D_2_.D 0----1 1 10000- 0 0----0 0 -.names IPL_0_.BLIF inst_RISING_CLK_AMIGA.BLIF IPL_030DFFSH_0_reg.BLIF \ +.names IPL_0_.BLIF IPL_030DFFSH_0_reg.BLIF inst_RISING_CLK_AMIGA.BLIF \ IPL_030DFFSH_0_reg.D -11- 1 --01 1 -01- 0 --00 0 -.names IPL_1_.BLIF inst_RISING_CLK_AMIGA.BLIF IPL_030DFFSH_1_reg.BLIF \ -IPL_030DFFSH_1_reg.D -11- 1 --01 1 -01- 0 --00 0 -.names IPL_2_.BLIF inst_RISING_CLK_AMIGA.BLIF IPL_030DFFSH_2_reg.BLIF \ -IPL_030DFFSH_2_reg.D -11- 1 --01 1 -01- 0 +-10 1 +1-1 1 -00 0 +0-1 0 +.names AS_030.BLIF inst_AS_000_INTreg.BLIF inst_AS_030_000_SYNC.BLIF \ +inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF SM_AMIGA_6_.BLIF inst_AS_000_INTreg.D +-1--1- 1 +-1-0-- 1 +-11--- 1 +-1---0 1 +1---1- 1 +1--0-- 1 +1-1--- 1 +1----0 1 +--0101 0 +00---- 0 +.names AS_030.BLIF cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF \ +cpu_est_1_.BLIF inst_VPA_D.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D.BLIF \ +cpu_est_2_.BLIF SM_AMIGA_3_.BLIF inst_VPA_SYNC.D +------1-0- 1 +------10-- 1 +-----11--- 1 +----1-1--- 1 +---1--1--- 1 +--1---1--- 1 +-0----1--- 1 +------1--0 1 +1-------0- 1 +1------0-- 1 +1----1---- 1 +1---1----- 1 +1--1------ 1 +1-1------- 1 +10-------- 1 +1--------0 1 +-10000-111 0 +0-----0--- 0 .names FC_1_.BLIF AS_030.BLIF CPU_SPACE.BLIF BGACK_000.BLIF CLK_030.BLIF \ A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF FC_0_.BLIF \ inst_AS_030_000_SYNC.BLIF inst_AS_030_000_SYNC.D @@ -242,53 +251,26 @@ inst_AS_030_000_SYNC.BLIF inst_AS_030_000_SYNC.D -0001------ 0 000-1------ 0 -0--0-----0 0 -.names AS_030.BLIF cpu_est_3_reg.BLIF cpu_est_1_.BLIF inst_VPA_D.BLIF \ -inst_VPA_SYNC.BLIF inst_CLK_000_D.BLIF cpu_est_0_.BLIF cpu_est_2_.BLIF \ -SM_AMIGA_3_.BLIF inst_VPA_SYNC.D -----1--0- 1 -----1-0-- 1 -----10--- 1 ----11---- 1 ---1-1---- 1 --1--1---- 1 -----1---0 1 -1------0- 1 -1-----0-- 1 -1----0--- 1 -1--1----- 1 -1-1------ 1 -11------- 1 -1-------0 1 --000-1111 0 -0---0---- 0 -.names AS_030.BLIF CPU_SPACE.BLIF BG_030.BLIF CLK_030.BLIF SM_AMIGA_6_.BLIF \ -BG_000DFFSHreg.BLIF SM_AMIGA_7_.BLIF BG_000DFFSHreg.D ----1-1- 1 ----00-0 1 +.names AS_030.BLIF CPU_SPACE.BLIF BG_030.BLIF CLK_030.BLIF BG_000DFFSHreg.BLIF \ +SM_AMIGA_6_.BLIF SM_AMIGA_7_.BLIF BG_000DFFSHreg.D +---11-- 1 +---0-00 1 -1-0--- 1 0--0--- 1 --1---- 1 -10001-- 0 +1000-1- 0 1000--1 0 ---01-0- 0 -.names AS_030.BLIF inst_AS_000_INTreg.BLIF inst_AS_030_000_SYNC.BLIF \ -inst_CLK_000_D.BLIF SM_AMIGA_6_.BLIF inst_AS_000_INTreg.D --1-0- 1 --11-- 1 --1--0 1 +--010-- 0 +.names AS_030.BLIF inst_CLK_000_D.BLIF inst_CLK_OUT_PRE.BLIF SM_AMIGA_1_.BLIF \ +DSACK_INT_1_.BLIF DSACK_INT_1_.D 1--0- 1 -1-1-- 1 -1---0 1 ---011 0 -00--- 0 -.names inst_VMA_INTreg.BLIF inst_AS_000_INTreg.BLIF inst_VPA_SYNC.BLIF \ -inst_CLK_000_D.BLIF inst_VMA_INTreg.D -1-1- 1 -1--1 1 --1-1 1 -00-- 0 ---00 0 -0--0 0 +1-0-- 1 +11--- 1 +---01 1 +--0-1 1 +-1--1 1 +-011- 0 +0---0 0 .names BGACK_000.BLIF inst_BGACK_030_INTreg.BLIF inst_RISING_CLK_AMIGA.BLIF \ inst_BGACK_030_INTreg.D 11- 1 @@ -296,47 +278,60 @@ inst_BGACK_030_INTreg.D -00 0 0-- 0 .names AS_030.BLIF DS_030.BLIF RW.BLIF A_0_.BLIF inst_AS_030_000_SYNC.BLIF \ -inst_CLK_000_D.BLIF SM_AMIGA_6_.BLIF inst_UDS_000_INTreg.BLIF SM_AMIGA_4_.BLIF \ -SM_AMIGA_5_.BLIF inst_UDS_000_INTreg.D -1-0-----0- 1 ---0----10- 1 --011011--- 1 --001-10-10 1 --00111--10 1 ---0-0-11-- 1 -1-0-0-1--- 1 --011-----1 1 ---1---01-0 1 ---1-1--1-0 1 -1-1---0--0 1 -1-1-1----0 1 --1-----1-- 1 +inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF SM_AMIGA_6_.BLIF \ +inst_UDS_000_INTreg.BLIF SM_AMIGA_4_.BLIF inst_UDS_000_INTreg.D +-0110101-- 1 +-001-1---1 1 +--1----01- 1 +--1---1-1- 1 +--1-1---1- 1 +1-1----0-- 1 +1-1---1--- 1 +1-1-1----- 1 +--0-----10 1 +-----0--1- 1 +-1------1- 1 +1-0------0 1 +1----0---- 1 11-------- 1 ---0----1-1 1 -1-0------1 1 ------0-1-0 1 -1----0---0 1 -0-0----00- 0 --010011--- 0 --000-10-10 0 --00011--10 0 -0-0-0-10-- 0 --010-----1 0 -0-1---00-0 0 -0-1-1--0-0 0 -01-----0-- 0 -0-0----0-1 0 -0----0-0-0 0 -.names SIZE_1_.BLIF AS_030.BLIF SIZE_0_.BLIF A_0_.BLIF \ -inst_LDS_000_INTreg.BLIF un1_UDS_000_INT_0_sqmuxa_2_0.BLIF \ +-0100101-- 0 +-000-1---1 0 +0-1----00- 0 +0-1---1-0- 0 +0-1-1---0- 0 +0----0--0- 0 +0-0-----00 0 +01------0- 0 +.names SIZE_1_.BLIF AS_030.BLIF DS_030.BLIF RW.BLIF SIZE_0_.BLIF A_0_.BLIF \ +inst_AS_030_000_SYNC.BLIF inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF \ +SM_AMIGA_6_.BLIF inst_LDS_000_INTreg.BLIF SM_AMIGA_4_.BLIF \ inst_LDS_000_INTreg.D -0-10-1 1 -----10 1 --1---0 1 --0--00 0 ----1-1 0 ---0--1 0 -1----1 0 +0-01100101-- 1 +0-0010-1---1 1 +---1-----01- 1 +---1----1-1- 1 +---1--1---1- 1 +-1-1-----0-- 1 +-1-1----1--- 1 +-1-1--1----- 1 +---0------10 1 +-1-0-------0 1 +-------0--1- 1 +--1-------1- 1 +-1-----0---- 1 +-11--------- 1 +--01-10101-- 0 +--010-0101-- 0 +1-01--0101-- 0 +--00-1-1---1 0 +--000--1---1 0 +1-00---1---1 0 +-0-1-----00- 0 +-0-1----1-0- 0 +-0-1--1---0- 0 +-0-----0--0- 0 +-01-------0- 0 +-0-0------00 0 .names AS_030.BLIF inst_DTACK_SYNC.BLIF inst_VPA_D.BLIF inst_CLK_000_D.BLIF \ SM_AMIGA_3_.BLIF DTACK.PIN.BLIF inst_DTACK_SYNC.D -1--0- 1 @@ -367,23 +362,13 @@ inst_FPU_CS_INTreg.D 1- 1 -1 1 00 0 +.names CLK_000.BLIF inst_CLK_000_D.BLIF inst_RISING_CLK_AMIGA.D +10 1 +0- 0 +-1 0 .names CLK_CNT_0_.BLIF CLK_CNT_0_.D 0 1 1 0 -.names DS_030.BLIF RW.BLIF inst_AS_030_000_SYNC.BLIF inst_CLK_000_D.BLIF \ -SM_AMIGA_6_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_5_.BLIF \ -un1_UDS_000_INT_0_sqmuxa_2_0 -01011-- 1 -00-1010 1 -0011-10 1 -01----1 1 --0---0- 0 --00-1-- 0 --1--0-0 0 --11---0 0 -1------ 0 --0----1 0 ----0--0 0 .names IPL_030DFFSH_2_reg.BLIF IPL_030_2_ 1 1 0 0 @@ -442,6 +427,18 @@ un1_UDS_000_INT_0_sqmuxa_2_0 .names IPL_030DFFSH_0_reg.BLIF IPL_030_0_ 1 1 0 0 +.names CLK_OSZI.BLIF SM_AMIGA_6_.C +1 1 +0 0 +.names RST.BLIF SM_AMIGA_6_.AR +0 1 +1 0 +.names CLK_OSZI.BLIF SM_AMIGA_5_.C +1 1 +0 0 +.names RST.BLIF SM_AMIGA_5_.AR +0 1 +1 0 .names CLK_OSZI.BLIF SM_AMIGA_4_.C 1 1 0 0 @@ -472,13 +469,25 @@ un1_UDS_000_INT_0_sqmuxa_2_0 .names RST.BLIF SM_AMIGA_0_.AR 0 1 1 0 -.names inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF cpu_est_0_.BLIF cpu_est_0_.D -100 1 --11 1 -0-1 1 -101 0 --10 0 -0-0 0 +.names CLK_OSZI.BLIF IPL_030DFFSH_1_reg.C +1 1 +0 0 +.names RST.BLIF IPL_030DFFSH_1_reg.AP +0 1 +1 0 +.names CLK_OSZI.BLIF IPL_030DFFSH_2_reg.C +1 1 +0 0 +.names RST.BLIF IPL_030DFFSH_2_reg.AP +0 1 +1 0 +.names cpu_est_0_.BLIF inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF cpu_est_0_.D +010 1 +10- 1 +1-1 1 +110 0 +00- 0 +0-1 0 .names CLK_OSZI.BLIF cpu_est_0_.C 1 1 0 0 @@ -497,67 +506,28 @@ un1_UDS_000_INT_0_sqmuxa_2_0 .names RST.BLIF SM_AMIGA_7_.AP 0 1 1 0 -.names CLK_OSZI.BLIF SM_AMIGA_6_.C +.names cpu_est_0_.BLIF cpu_est_d_0_.D 1 1 0 0 -.names RST.BLIF SM_AMIGA_6_.AR -0 1 -1 0 -.names CLK_OSZI.BLIF SM_AMIGA_5_.C +.names CLK_OSZI.BLIF cpu_est_d_0_.C 1 1 0 0 -.names RST.BLIF SM_AMIGA_5_.AR -0 1 -1 0 -.names CLK_OSZI.BLIF CLK_000_CNT_0_.C +.names cpu_est_1_.BLIF cpu_est_d_1_.D 1 1 0 0 -.names CLK_000.BLIF inst_CLK_000_D.BLIF CLK_000_CNT_0_.BLIF \ -CLK_000_CNT_1_.BLIF CLK_000_CNT_1_.D -0010 1 -1110 1 -0001 1 -1101 1 -10-- 0 -01-- 0 ---00 0 ---11 0 -.names CLK_OSZI.BLIF CLK_000_CNT_1_.C +.names CLK_OSZI.BLIF cpu_est_d_1_.C 1 1 0 0 -.names CLK_000.BLIF inst_CLK_000_D.BLIF CLK_000_CNT_0_.BLIF \ -CLK_000_CNT_1_.BLIF CLK_000_CNT_2_.BLIF CLK_000_CNT_2_.D -00110 1 -11110 1 -00-01 1 -11-01 1 -000-1 1 -110-1 1 ---111 0 -10--- 0 -01--- 0 ----00 0 ---0-0 0 -.names CLK_OSZI.BLIF CLK_000_CNT_2_.C +.names cpu_est_2_.BLIF cpu_est_d_2_.D 1 1 0 0 -.names CLK_000.BLIF inst_CLK_000_D.BLIF CLK_000_CNT_0_.BLIF \ -CLK_000_CNT_1_.BLIF CLK_000_CNT_2_.BLIF CLK_000_CNT_3_.BLIF CLK_000_CNT_3_.D -001110 1 -111110 1 -00--01 1 -11--01 1 -00-0-1 1 -11-0-1 1 -000--1 1 -110--1 1 ---1111 0 -10---- 0 -01---- 0 -----00 0 ----0-0 0 ---0--0 0 -.names CLK_OSZI.BLIF CLK_000_CNT_3_.C +.names CLK_OSZI.BLIF cpu_est_d_2_.C +1 1 +0 0 +.names cpu_est_3_reg.BLIF cpu_est_d_3_.D +1 1 +0 0 +.names CLK_OSZI.BLIF cpu_est_d_3_.C 1 1 0 0 .names CLK_OSZI.BLIF SM_AMIGA_D_0_.C @@ -575,22 +545,10 @@ CLK_000_CNT_1_.BLIF CLK_000_CNT_2_.BLIF CLK_000_CNT_3_.BLIF CLK_000_CNT_3_.D .names RST.BLIF IPL_030DFFSH_0_reg.AP 0 1 1 0 -.names CLK_OSZI.BLIF IPL_030DFFSH_1_reg.C +.names CLK_OSZI.BLIF inst_AS_000_INTreg.C 1 1 0 0 -.names RST.BLIF IPL_030DFFSH_1_reg.AP -0 1 -1 0 -.names CLK_OSZI.BLIF IPL_030DFFSH_2_reg.C -1 1 -0 0 -.names RST.BLIF IPL_030DFFSH_2_reg.AP -0 1 -1 0 -.names CLK_OSZI.BLIF inst_AS_030_000_SYNC.C -1 1 -0 0 -.names RST.BLIF inst_AS_030_000_SYNC.AP +.names RST.BLIF inst_AS_000_INTreg.AP 0 1 1 0 .names CLK_OSZI.BLIF inst_VPA_SYNC.C @@ -599,16 +557,10 @@ CLK_000_CNT_1_.BLIF CLK_000_CNT_2_.BLIF CLK_000_CNT_3_.BLIF CLK_000_CNT_3_.D .names RST.BLIF inst_VPA_SYNC.AP 0 1 1 0 -.names CLK_OSZI.BLIF BG_000DFFSHreg.C +.names CLK_OSZI.BLIF inst_AS_030_000_SYNC.C 1 1 0 0 -.names RST.BLIF BG_000DFFSHreg.AP -0 1 -1 0 -.names CLK_OSZI.BLIF inst_AS_000_INTreg.C -1 1 -0 0 -.names RST.BLIF inst_AS_000_INTreg.AP +.names RST.BLIF inst_AS_030_000_SYNC.AP 0 1 1 0 .names CLK_OSZI.BLIF inst_VMA_INTreg.C @@ -617,6 +569,18 @@ CLK_000_CNT_1_.BLIF CLK_000_CNT_2_.BLIF CLK_000_CNT_3_.BLIF CLK_000_CNT_3_.D .names RST.BLIF inst_VMA_INTreg.AP 0 1 1 0 +.names CLK_OSZI.BLIF BG_000DFFSHreg.C +1 1 +0 0 +.names RST.BLIF BG_000DFFSHreg.AP +0 1 +1 0 +.names CLK_OSZI.BLIF DSACK_INT_1_.C +1 1 +0 0 +.names RST.BLIF DSACK_INT_1_.AP +0 1 +1 0 .names CLK_OSZI.BLIF inst_BGACK_030_INTreg.C 1 1 0 0 @@ -631,12 +595,6 @@ CLK_000_CNT_1_.BLIF CLK_000_CNT_2_.BLIF CLK_000_CNT_3_.BLIF CLK_000_CNT_3_.D .names CLK_OSZI.BLIF inst_CLK_OUT_PRE.C 1 1 0 0 -.names CLK_OSZI.BLIF DSACK_INT_1_.C -1 1 -0 0 -.names RST.BLIF DSACK_INT_1_.AP -0 1 -1 0 .names CLK_OSZI.BLIF inst_UDS_000_INTreg.C 1 1 0 0 @@ -667,14 +625,10 @@ CLK_000_CNT_1_.BLIF CLK_000_CNT_2_.BLIF CLK_000_CNT_3_.BLIF CLK_000_CNT_3_.D .names RST.BLIF inst_DTACK_DMA.AP 0 1 1 0 -.names CLK_OSZI.BLIF CLK_CNT_0_.C +.names CLK_OSZI.BLIF inst_RISING_CLK_AMIGA.C 1 1 0 0 -.names CLK_000.BLIF inst_CLK_000_D.BLIF inst_RISING_CLK_AMIGA.D -10 1 -0- 0 --1 0 -.names CLK_OSZI.BLIF inst_RISING_CLK_AMIGA.C +.names CLK_OSZI.BLIF CLK_CNT_0_.C 1 1 0 0 .names VPA.BLIF inst_VPA_D.D @@ -757,86 +711,77 @@ SM_AMIGA_D_2_.BLIF CLK_EXP.X1 -0-- 0 --0- 0 ---0 0 -.names SM_AMIGA_6_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_5_.BLIF \ -SM_AMIGA_2_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_D_0_.BLIF \ +.names SM_AMIGA_6_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_3_.BLIF \ +SM_AMIGA_5_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_D_0_.BLIF \ SM_AMIGA_D_1_.BLIF SM_AMIGA_D_2_.BLIF CLK_EXP.X2 -00--0--1-- 1 --0-0-0--1- 1 ---0-00---1 1 ----1----0- 1 ---1------0 1 +0-0--0-1-- 1 +-00-0---1- 1 +-0-0-0---1 1 +----1---0- 1 +---1-----0 1 1------0-- 1 ------1--0- 1 +-----1-0-- 1 -----1---0 1 -----1--0-- 1 -----1----0 1 --1-----0-- 1 +--1----0-- 1 +--1-----0- 1 -1------0- 1 +-1-------0 1 ------1--- 1 +11----0111 0 -11---0111 0 --1--1-0111 0 ----11-0111 0 -1----10111 0 +--11--0111 0 -1---10111 0 +--1--10111 0 ----110111 0 -1-11--0111 0 -00--010011 0 --0-0100101 0 --10-000110 0 -00110-0011 0 -1010-00101 0 -1-01000110 0 -0010000001 0 -0001000010 0 +1--11-0111 0 +010--00011 0 +-00-010101 0 +-010-00110 0 +0-01100011 0 +10010-0101 0 +10-0100110 0 +0001000001 0 +0000100010 0 1000000100 0 0000000000 0 -.names cpu_est_3_reg.BLIF cpu_est_1_.BLIF cpu_est_3_reg.D.X1 +.names cpu_est_3_reg.BLIF cpu_est_0_.BLIF cpu_est_3_reg.D.X1 11 1 0- 0 -0 0 -.names cpu_est_3_reg.BLIF cpu_est_1_.BLIF inst_CLK_000_D.BLIF \ -inst_CLK_000_DD.BLIF cpu_est_0_.BLIF cpu_est_2_.BLIF cpu_est_3_reg.D.X2 +.names cpu_est_3_reg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_CLK_000_D.BLIF \ +inst_CLK_000_DD.BLIF cpu_est_2_.BLIF cpu_est_3_reg.D.X2 10---- 1 --01000 1 -011010 1 -1-1011 1 -0-0--- 0 +-00100 1 +011100 1 +1-1101 1 -10--- 0 -0--1-- 0 --1-1-- 0 --1--0- 0 +0--0-- 0 +-1-0-- 0 +0---1- 0 +-1--1- 0 0----1 0 -00--1- 0 +001--- 0 11---0 0 -.names AS_030.BLIF DSACK_INT_1_.BLIF DSACK_INT_1_.D.X1 -00 1 -1- 0 +.names inst_VMA_INTreg.BLIF inst_CLK_000_D.BLIF inst_VMA_INTreg.D.X1 +10 1 +0- 0 -1 0 -.names AS_030.BLIF inst_AS_030_000_SYNC.BLIF inst_DTACK_SYNC.BLIF \ -inst_VPA_SYNC.BLIF inst_CLK_000_D.BLIF inst_CLK_OUT_PRE.BLIF DSACK_INT_1_.BLIF \ -CLK_000_CNT_0_.BLIF CLK_000_CNT_1_.BLIF CLK_000_CNT_2_.BLIF \ -CLK_000_CNT_3_.BLIF SM_AMIGA_0_.BLIF DSACK_INT_1_.D.X2 -0-----0----- 1 --1---------- 1 -----1------- 1 ------0------ 1 ------------0 1 ---11-------- 1 --------0000- 1 -100-01-1---1 0 -10-001-1---1 0 --00-0111---1 0 --0-00111---1 0 -100-01--1--1 0 -10-001--1--1 0 --00-011-1--1 0 --0-0011-1--1 0 -100-01---1-1 0 -10-001---1-1 0 --00-011--1-1 0 --0-0011--1-1 0 -100-01----11 0 -10-001----11 0 --00-011---11 0 --0-0011---11 0 +.names cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \ +cpu_est_d_0_.BLIF cpu_est_d_3_.BLIF inst_AS_000_INTreg.BLIF inst_VPA_D.BLIF \ +inst_CLK_000_D.BLIF cpu_est_d_1_.BLIF cpu_est_d_2_.BLIF cpu_est_2_.BLIF \ +inst_VMA_INTreg.D.X2 +0110---0---1 1 +-1------1--- 1 +----001-111- 1 +-0--1------- 0 +-0---1------ 0 +-0----0----- 0 +1-------0--- 0 +-0------0--- 0 +--0-----0--- 0 +---1----0--- 0 +-------10--- 0 +-0-------0-- 0 +-0--------0- 0 +--------0--0 0 .end diff --git a/Logic/68030_tk.crf b/Logic/68030_tk.crf index 968feaf..08f099e 100644 --- a/Logic/68030_tk.crf +++ b/Logic/68030_tk.crf @@ -1,7 +1,7 @@ // Signal Name Cross Reference File // ispLEVER Classic 1.7.00.05.28.13 -// Design '68030_tk' created Thu May 15 19:20:52 2014 +// Design '68030_tk' created Thu May 15 22:17:27 2014 // LEGEND: '>' Functional Block Port Separator diff --git a/Logic/68030_tk.eq3 b/Logic/68030_tk.eq3 index b05f7c2..3164363 100644 --- a/Logic/68030_tk.eq3 +++ b/Logic/68030_tk.eq3 @@ -2,7 +2,7 @@ Copyright(C), 1992-2013, Lattice Semiconductor Corp. All Rights Reserved. -Design bus68030 created Thu May 15 19:20:52 2014 +Design bus68030 created Thu May 15 22:17:27 2014 P-Terms Fan-in Fan-out Type Name (attributes) @@ -14,30 +14,30 @@ Design bus68030 created Thu May 15 19:20:52 2014 1 0 1 Pin AVEC 0 0 1 Pin AVEC_EXP 1 1 1 Pin AVEC_EXP.OE - 1 0 1 Pin DSACK_0_ - 1 1 1 Pin DSACK_0_.OE 0 0 1 Pin AMIGA_BUS_ENABLE 1 1 1 Pin AMIGA_BUS_DATA_DIR 1 0 1 Pin AMIGA_BUS_ENABLE_LOW 1 4 1 Pin CIIN 1 8 1 Pin CIIN.OE + 1 0 1 Pin DSACK_0_ + 1 1 1 Pin DSACK_0_.OE 2 3 1 Pin IPL_030_2_.D 1 1 1 Pin IPL_030_2_.AP 1 1 1 Pin IPL_030_2_.C 1 1 1 Pin DSACK_1_.OE - 9 12 1 Pin DSACK_1_.D- + 2 5 1 Pin DSACK_1_.D- 1 1 1 Pin DSACK_1_.AP 1 1 1 Pin DSACK_1_.C 1 1 1 Pin AS_000.OE - 2 5 1 Pin AS_000.D- + 2 6 1 Pin AS_000.D- 1 1 1 Pin AS_000.AP 1 1 1 Pin AS_000.C 1 1 1 Pin UDS_000.OE - 11 10 1 Pin UDS_000.D- + 8 10 1 Pin UDS_000.D- 1 1 1 Pin UDS_000.AP 1 1 1 Pin UDS_000.C 1 1 1 Pin LDS_000.OE - 3 6 1 Pin LDS_000.D + 12 12 1 Pin LDS_000.D- 1 1 1 Pin LDS_000.AP 1 1 1 Pin LDS_000.C 3 7 1 Pin BG_000.D- @@ -55,21 +55,27 @@ Design bus68030 created Thu May 15 19:20:52 2014 1 2 1 Pin DTACK.D- 1 1 1 Pin DTACK.AP 1 1 1 Pin DTACK.C + 3 6 1 Pin E.T + 1 1 1 Pin E.C + 1 1 1 Pin VMA.AP + 2 12 1 Pin VMA.T + 1 1 1 Pin VMA.C + 1 1 1 Pin RESET.D + 1 1 1 Pin RESET.C 2 3 1 Pin IPL_030_1_.D 1 1 1 Pin IPL_030_1_.AP 1 1 1 Pin IPL_030_1_.C 2 3 1 Pin IPL_030_0_.D 1 1 1 Pin IPL_030_0_.AP 1 1 1 Pin IPL_030_0_.C - 3 6 1 Pin E.T - 1 1 1 Pin E.C - 3 4 1 Pin VMA.D - 1 1 1 Pin VMA.AP - 1 1 1 Pin VMA.C - 1 1 1 Pin RESET.D - 1 1 1 Pin RESET.C + 3 3 1 Node cpu_est_0_.D + 1 1 1 Node cpu_est_0_.C 4 6 1 Node cpu_est_1_.T 1 1 1 Node cpu_est_1_.C + 1 1 1 Node cpu_est_d_0_.D + 1 1 1 Node cpu_est_d_0_.C + 1 1 1 Node cpu_est_d_3_.D + 1 1 1 Node cpu_est_d_3_.C 4 11 1 Node inst_AS_030_000_SYNC.D 1 1 1 Node inst_AS_030_000_SYNC.AP 1 1 1 Node inst_AS_030_000_SYNC.C @@ -78,7 +84,7 @@ Design bus68030 created Thu May 15 19:20:52 2014 1 1 1 Node inst_DTACK_SYNC.C 1 1 1 Node inst_VPA_D.D 1 1 1 Node inst_VPA_D.C - 2 9 1 Node inst_VPA_SYNC.D- + 2 10 1 Node inst_VPA_SYNC.D- 1 1 1 Node inst_VPA_SYNC.AP 1 1 1 Node inst_VPA_SYNC.C 1 1 1 Node inst_CLK_000_D.D @@ -87,21 +93,26 @@ Design bus68030 created Thu May 15 19:20:52 2014 1 1 1 Node inst_CLK_000_DD.C 2 2 1 Node inst_CLK_OUT_PRE.D 1 1 1 Node inst_CLK_OUT_PRE.C - 3 3 1 Node cpu_est_0_.D - 1 1 1 Node cpu_est_0_.C + 1 1 1 Node cpu_est_d_1_.D + 1 1 1 Node cpu_est_d_1_.C + 1 1 1 Node cpu_est_d_2_.D + 1 1 1 Node cpu_est_d_2_.C 3 6 1 NodeX1 cpu_est_2_.D.X1 1 1 1 NodeX2 cpu_est_2_.D.X2 1 1 1 Node cpu_est_2_.C 1 1 1 Node CLK_CNT_0_.D 1 1 1 Node CLK_CNT_0_.C 1 1 1 Node SM_AMIGA_6_.AR - 3 4 1 Node SM_AMIGA_6_.D + 3 5 1 Node SM_AMIGA_6_.D- 1 1 1 Node SM_AMIGA_6_.C 2 4 1 Node SM_AMIGA_7_.D 1 1 1 Node SM_AMIGA_7_.AP 1 1 1 Node SM_AMIGA_7_.C 1 2 1 Node inst_RISING_CLK_AMIGA.D 1 1 1 Node inst_RISING_CLK_AMIGA.C + 1 1 1 Node SM_AMIGA_1_.AR + 3 4 1 Node SM_AMIGA_1_.D + 1 1 1 Node SM_AMIGA_1_.C 1 1 1 Node SM_AMIGA_4_.AR 2 3 1 Node SM_AMIGA_4_.D 1 1 1 Node SM_AMIGA_4_.C @@ -109,24 +120,13 @@ Design bus68030 created Thu May 15 19:20:52 2014 3 5 1 Node SM_AMIGA_3_.D 1 1 1 Node SM_AMIGA_3_.C 1 1 1 Node SM_AMIGA_5_.AR - 2 4 1 Node SM_AMIGA_5_.D + 2 5 1 Node SM_AMIGA_5_.D 1 1 1 Node SM_AMIGA_5_.C - 2 3 1 Node CLK_000_CNT_0_.D- - 1 1 1 Node CLK_000_CNT_0_.C - 4 4 1 Node CLK_000_CNT_1_.D - 1 1 1 Node CLK_000_CNT_1_.C - 5 5 1 Node CLK_000_CNT_2_.D- - 1 1 1 Node CLK_000_CNT_2_.C - 4 6 1 Node CLK_000_CNT_3_.T - 1 1 1 Node CLK_000_CNT_3_.C 1 1 1 Node SM_AMIGA_2_.AR 3 5 1 Node SM_AMIGA_2_.D 1 1 1 Node SM_AMIGA_2_.C - 1 1 1 Node SM_AMIGA_1_.AR - 4 10 1 Node SM_AMIGA_1_.D- - 1 1 1 Node SM_AMIGA_1_.C 1 1 1 Node SM_AMIGA_0_.AR - 4 11 1 Node SM_AMIGA_0_.D + 3 5 1 Node SM_AMIGA_0_.D 1 1 1 Node SM_AMIGA_0_.C 2 6 1 Node SM_AMIGA_D_0_.D- 1 1 1 Node SM_AMIGA_D_0_.C @@ -134,11 +134,10 @@ Design bus68030 created Thu May 15 19:20:52 2014 1 1 1 Node SM_AMIGA_D_1_.C 2 6 1 Node SM_AMIGA_D_2_.D- 1 1 1 Node SM_AMIGA_D_2_.C - 4 7 1 Node un1_UDS_000_INT_0_sqmuxa_2_0 ========= - 214 P-Term Total: 214 + 195 P-Term Total: 195 Total Pins: 59 - Total Nodes: 28 + Total Nodes: 27 Average P-Term/Output: 2 @@ -152,15 +151,15 @@ CLK_EXP.X1 = (SM_AMIGA_0_.Q # SM_AMIGA_6_.Q & !SM_AMIGA_D_0_.Q # SM_AMIGA_4_.Q & !SM_AMIGA_D_0_.Q # SM_AMIGA_2_.Q & !SM_AMIGA_D_0_.Q + # SM_AMIGA_1_.Q & !SM_AMIGA_D_1_.Q # SM_AMIGA_4_.Q & !SM_AMIGA_D_1_.Q # SM_AMIGA_5_.Q & !SM_AMIGA_D_1_.Q - # SM_AMIGA_1_.Q & !SM_AMIGA_D_1_.Q + # SM_AMIGA_1_.Q & !SM_AMIGA_D_2_.Q # SM_AMIGA_3_.Q & !SM_AMIGA_D_2_.Q # SM_AMIGA_2_.Q & !SM_AMIGA_D_2_.Q - # SM_AMIGA_1_.Q & !SM_AMIGA_D_2_.Q # !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q & SM_AMIGA_D_0_.Q - # !SM_AMIGA_4_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_1_.Q & SM_AMIGA_D_1_.Q - # !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & !SM_AMIGA_1_.Q & SM_AMIGA_D_2_.Q); + # !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_5_.Q & SM_AMIGA_D_1_.Q + # !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & SM_AMIGA_D_2_.Q); CLK_EXP.X2 = (SM_AMIGA_0_.Q & SM_AMIGA_D_0_.Q & SM_AMIGA_D_1_.Q & SM_AMIGA_D_2_.Q); @@ -170,10 +169,6 @@ AVEC_EXP = (0); AVEC_EXP.OE = (!FPU_CS.Q); -DSACK_0_ = (1); - -DSACK_0_.OE = (!CPU_SPACE); - AMIGA_BUS_ENABLE = (0); AMIGA_BUS_DATA_DIR = (!RW); @@ -184,8 +179,12 @@ CIIN = (A_23_ & A_22_ & A_21_ & A_20_); CIIN.OE = (!A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_); +DSACK_0_ = (1); + +DSACK_0_.OE = (!CPU_SPACE); + IPL_030_2_.D = (IPL_2_ & inst_RISING_CLK_AMIGA.Q - # !inst_RISING_CLK_AMIGA.Q & IPL_030_2_.Q); + # IPL_030_2_.Q & !inst_RISING_CLK_AMIGA.Q); IPL_030_2_.AP = (!RST); @@ -194,14 +193,7 @@ IPL_030_2_.C = (CLK_OSZI); DSACK_1_.OE = (!CPU_SPACE); !DSACK_1_.D = (!AS_030 & !DSACK_1_.Q - # !inst_AS_030_000_SYNC.Q & !inst_DTACK_SYNC.Q & !inst_CLK_000_D.Q & inst_CLK_OUT_PRE.Q & CLK_000_CNT_0_.Q & SM_AMIGA_0_.Q - # !inst_AS_030_000_SYNC.Q & !inst_VPA_SYNC.Q & !inst_CLK_000_D.Q & inst_CLK_OUT_PRE.Q & CLK_000_CNT_0_.Q & SM_AMIGA_0_.Q - # !inst_AS_030_000_SYNC.Q & !inst_DTACK_SYNC.Q & !inst_CLK_000_D.Q & inst_CLK_OUT_PRE.Q & CLK_000_CNT_1_.Q & SM_AMIGA_0_.Q - # !inst_AS_030_000_SYNC.Q & !inst_VPA_SYNC.Q & !inst_CLK_000_D.Q & inst_CLK_OUT_PRE.Q & CLK_000_CNT_1_.Q & SM_AMIGA_0_.Q - # !inst_AS_030_000_SYNC.Q & !inst_DTACK_SYNC.Q & !inst_CLK_000_D.Q & inst_CLK_OUT_PRE.Q & CLK_000_CNT_2_.Q & SM_AMIGA_0_.Q - # !inst_AS_030_000_SYNC.Q & !inst_VPA_SYNC.Q & !inst_CLK_000_D.Q & inst_CLK_OUT_PRE.Q & CLK_000_CNT_2_.Q & SM_AMIGA_0_.Q - # !inst_AS_030_000_SYNC.Q & !inst_DTACK_SYNC.Q & !inst_CLK_000_D.Q & inst_CLK_OUT_PRE.Q & CLK_000_CNT_3_.Q & SM_AMIGA_0_.Q - # !inst_AS_030_000_SYNC.Q & !inst_VPA_SYNC.Q & !inst_CLK_000_D.Q & inst_CLK_OUT_PRE.Q & CLK_000_CNT_3_.Q & SM_AMIGA_0_.Q); + # !inst_CLK_000_D.Q & inst_CLK_OUT_PRE.Q & SM_AMIGA_1_.Q); DSACK_1_.AP = (!RST); @@ -210,7 +202,7 @@ DSACK_1_.C = (CLK_OSZI); AS_000.OE = (BGACK_030.Q); !AS_000.D = (!AS_030 & !AS_000.Q - # !inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & SM_AMIGA_6_.Q); + # !inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & SM_AMIGA_6_.Q); AS_000.AP = (!RST); @@ -219,16 +211,13 @@ AS_000.C = (CLK_OSZI); UDS_000.OE = (BGACK_030.Q); !UDS_000.D = (!AS_030 & DS_030 & !UDS_000.Q + # !AS_030 & !inst_CLK_000_D.Q & !UDS_000.Q + # !AS_030 & RW & inst_AS_030_000_SYNC.Q & !UDS_000.Q + # !AS_030 & RW & inst_CLK_000_DD.Q & !UDS_000.Q + # !AS_030 & RW & !SM_AMIGA_6_.Q & !UDS_000.Q # !AS_030 & !RW & !UDS_000.Q & !SM_AMIGA_4_.Q - # !DS_030 & RW & !A_0_ & SM_AMIGA_5_.Q - # !AS_030 & !RW & !UDS_000.Q & SM_AMIGA_5_.Q - # !AS_030 & !inst_CLK_000_D.Q & !UDS_000.Q & !SM_AMIGA_5_.Q - # !AS_030 & !RW & !inst_AS_030_000_SYNC.Q & SM_AMIGA_6_.Q & !UDS_000.Q - # !AS_030 & RW & inst_AS_030_000_SYNC.Q & !UDS_000.Q & !SM_AMIGA_5_.Q - # !AS_030 & RW & !SM_AMIGA_6_.Q & !UDS_000.Q & !SM_AMIGA_5_.Q - # !DS_030 & RW & !A_0_ & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & SM_AMIGA_6_.Q - # !DS_030 & !RW & !A_0_ & inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & SM_AMIGA_4_.Q & !SM_AMIGA_5_.Q - # !DS_030 & !RW & !A_0_ & inst_CLK_000_D.Q & !SM_AMIGA_6_.Q & SM_AMIGA_4_.Q & !SM_AMIGA_5_.Q); + # !DS_030 & !RW & !A_0_ & inst_CLK_000_D.Q & SM_AMIGA_4_.Q + # !DS_030 & RW & !A_0_ & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & SM_AMIGA_6_.Q); UDS_000.AP = (!RST); @@ -236,9 +225,18 @@ UDS_000.C = (CLK_OSZI); LDS_000.OE = (BGACK_030.Q); -LDS_000.D = (AS_030 & !un1_UDS_000_INT_0_sqmuxa_2_0 - # LDS_000.Q & !un1_UDS_000_INT_0_sqmuxa_2_0 - # !SIZE_1_ & SIZE_0_ & !A_0_ & un1_UDS_000_INT_0_sqmuxa_2_0); +!LDS_000.D = (!AS_030 & DS_030 & !LDS_000.Q + # !AS_030 & !inst_CLK_000_D.Q & !LDS_000.Q + # !AS_030 & RW & inst_AS_030_000_SYNC.Q & !LDS_000.Q + # !AS_030 & RW & inst_CLK_000_DD.Q & !LDS_000.Q + # !AS_030 & RW & !SM_AMIGA_6_.Q & !LDS_000.Q + # !AS_030 & !RW & !LDS_000.Q & !SM_AMIGA_4_.Q + # SIZE_1_ & !DS_030 & !RW & inst_CLK_000_D.Q & SM_AMIGA_4_.Q + # !DS_030 & !RW & !SIZE_0_ & inst_CLK_000_D.Q & SM_AMIGA_4_.Q + # !DS_030 & !RW & A_0_ & inst_CLK_000_D.Q & SM_AMIGA_4_.Q + # SIZE_1_ & !DS_030 & RW & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & SM_AMIGA_6_.Q + # !DS_030 & RW & !SIZE_0_ & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & SM_AMIGA_6_.Q + # !DS_030 & RW & A_0_ & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & SM_AMIGA_6_.Q); LDS_000.AP = (!RST); @@ -278,45 +276,58 @@ DTACK.AP = (!RST); DTACK.C = (CLK_OSZI); -IPL_030_1_.D = (IPL_1_ & inst_RISING_CLK_AMIGA.Q - # !inst_RISING_CLK_AMIGA.Q & IPL_030_1_.Q); - -IPL_030_1_.AP = (!RST); - -IPL_030_1_.C = (CLK_OSZI); - -IPL_030_0_.D = (IPL_0_ & inst_RISING_CLK_AMIGA.Q - # !inst_RISING_CLK_AMIGA.Q & IPL_030_0_.Q); - -IPL_030_0_.AP = (!RST); - -IPL_030_0_.C = (CLK_OSZI); - -E.T = (E.Q & cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & cpu_est_0_.Q & cpu_est_2_.Q - # !E.Q & cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & cpu_est_0_.Q & !cpu_est_2_.Q - # !E.Q & !cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & !cpu_est_0_.Q & !cpu_est_2_.Q); +E.T = (E.Q & cpu_est_0_.Q & cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & cpu_est_2_.Q + # !E.Q & cpu_est_0_.Q & cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & !cpu_est_2_.Q + # !E.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & !cpu_est_2_.Q); E.C = (CLK_OSZI); -VMA.D = (VMA.Q & inst_VPA_SYNC.Q - # VMA.Q & inst_CLK_000_D.Q - # AS_000.Q & inst_CLK_000_D.Q); - VMA.AP = (!RST); +VMA.T = (!VMA.Q & !cpu_est_d_0_.Q & !cpu_est_d_3_.Q & AS_000.Q & inst_CLK_000_D.Q & cpu_est_d_1_.Q & cpu_est_d_2_.Q + # !E.Q & VMA.Q & cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & !inst_CLK_000_D.Q & cpu_est_2_.Q); + VMA.C = (CLK_OSZI); RESET.D = (RST); RESET.C = (CLK_OSZI); -cpu_est_1_.T = (E.Q & !cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & !cpu_est_0_.Q - # !E.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & cpu_est_0_.Q & cpu_est_2_.Q +IPL_030_1_.D = (IPL_1_ & inst_RISING_CLK_AMIGA.Q + # IPL_030_1_.Q & !inst_RISING_CLK_AMIGA.Q); + +IPL_030_1_.AP = (!RST); + +IPL_030_1_.C = (CLK_OSZI); + +IPL_030_0_.D = (IPL_0_ & inst_RISING_CLK_AMIGA.Q + # IPL_030_0_.Q & !inst_RISING_CLK_AMIGA.Q); + +IPL_030_0_.AP = (!RST); + +IPL_030_0_.C = (CLK_OSZI); + +cpu_est_0_.D = (cpu_est_0_.Q & !inst_CLK_000_D.Q + # cpu_est_0_.Q & inst_CLK_000_DD.Q + # !cpu_est_0_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q); + +cpu_est_0_.C = (CLK_OSZI); + +cpu_est_1_.T = (E.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q + # !E.Q & cpu_est_0_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & cpu_est_2_.Q # !E.Q & !cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & !cpu_est_2_.Q - # E.Q & cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & cpu_est_0_.Q & !cpu_est_2_.Q); + # E.Q & cpu_est_0_.Q & cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & !cpu_est_2_.Q); cpu_est_1_.C = (CLK_OSZI); +cpu_est_d_0_.D = (cpu_est_0_.Q); + +cpu_est_d_0_.C = (CLK_OSZI); + +cpu_est_d_3_.D = (E.Q); + +cpu_est_d_3_.C = (CLK_OSZI); + inst_AS_030_000_SYNC.D = (AS_030 # CPU_SPACE & CLK_030 # !CLK_030 & inst_AS_030_000_SYNC.Q @@ -338,7 +349,7 @@ inst_VPA_D.D = (VPA); inst_VPA_D.C = (CLK_OSZI); !inst_VPA_SYNC.D = (!AS_030 & !inst_VPA_SYNC.Q - # !E.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_D.Q & cpu_est_0_.Q & cpu_est_2_.Q & SM_AMIGA_3_.Q); + # E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_D.Q & cpu_est_2_.Q & SM_AMIGA_3_.Q); inst_VPA_SYNC.AP = (!RST); @@ -357,15 +368,17 @@ inst_CLK_OUT_PRE.D = (!inst_CLK_OUT_PRE.Q & CLK_CNT_0_.Q inst_CLK_OUT_PRE.C = (CLK_OSZI); -cpu_est_0_.D = (!inst_CLK_000_D.Q & cpu_est_0_.Q - # inst_CLK_000_DD.Q & cpu_est_0_.Q - # inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & !cpu_est_0_.Q); +cpu_est_d_1_.D = (cpu_est_1_.Q); -cpu_est_0_.C = (CLK_OSZI); +cpu_est_d_1_.C = (CLK_OSZI); -cpu_est_2_.D.X1 = (E.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & cpu_est_0_.Q & !cpu_est_2_.Q - # !cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & !cpu_est_0_.Q & !cpu_est_2_.Q - # !E.Q & !cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & cpu_est_0_.Q & cpu_est_2_.Q); +cpu_est_d_2_.D = (cpu_est_2_.Q); + +cpu_est_d_2_.C = (CLK_OSZI); + +cpu_est_2_.D.X1 = (E.Q & cpu_est_0_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & !cpu_est_2_.Q + # !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & !cpu_est_2_.Q + # !E.Q & cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & cpu_est_2_.Q); cpu_est_2_.D.X2 = (cpu_est_2_.Q); @@ -377,9 +390,9 @@ CLK_CNT_0_.C = (CLK_OSZI); SM_AMIGA_6_.AR = (!RST); -SM_AMIGA_6_.D = (inst_AS_030_000_SYNC.Q & SM_AMIGA_6_.Q - # !inst_CLK_000_D.Q & SM_AMIGA_6_.Q - # !inst_CLK_000_D.Q & SM_AMIGA_7_.Q); +!SM_AMIGA_6_.D = (inst_CLK_000_D.Q & SM_AMIGA_7_.Q + # !SM_AMIGA_6_.Q & !SM_AMIGA_7_.Q + # !inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q); SM_AMIGA_6_.C = (CLK_OSZI); @@ -394,6 +407,14 @@ inst_RISING_CLK_AMIGA.D = (CLK_000 & !inst_CLK_000_D.Q); inst_RISING_CLK_AMIGA.C = (CLK_OSZI); +SM_AMIGA_1_.AR = (!RST); + +SM_AMIGA_1_.D = (inst_CLK_000_D.Q & SM_AMIGA_1_.Q + # !inst_CLK_OUT_PRE.Q & SM_AMIGA_1_.Q + # inst_CLK_000_D.Q & SM_AMIGA_2_.Q); + +SM_AMIGA_1_.C = (CLK_OSZI); + SM_AMIGA_4_.AR = (!RST); SM_AMIGA_4_.D = (!inst_CLK_000_D.Q & SM_AMIGA_4_.Q @@ -412,37 +433,10 @@ SM_AMIGA_3_.C = (CLK_OSZI); SM_AMIGA_5_.AR = (!RST); SM_AMIGA_5_.D = (inst_CLK_000_D.Q & SM_AMIGA_5_.Q - # !inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & SM_AMIGA_6_.Q); + # !inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & SM_AMIGA_6_.Q); SM_AMIGA_5_.C = (CLK_OSZI); -!CLK_000_CNT_0_.D = (CLK_000 & inst_CLK_000_D.Q & CLK_000_CNT_0_.Q - # !CLK_000 & !inst_CLK_000_D.Q & CLK_000_CNT_0_.Q); - -CLK_000_CNT_0_.C = (CLK_OSZI); - -CLK_000_CNT_1_.D = (CLK_000 & inst_CLK_000_D.Q & !CLK_000_CNT_0_.Q & CLK_000_CNT_1_.Q - # !CLK_000 & !inst_CLK_000_D.Q & !CLK_000_CNT_0_.Q & CLK_000_CNT_1_.Q - # CLK_000 & inst_CLK_000_D.Q & CLK_000_CNT_0_.Q & !CLK_000_CNT_1_.Q - # !CLK_000 & !inst_CLK_000_D.Q & CLK_000_CNT_0_.Q & !CLK_000_CNT_1_.Q); - -CLK_000_CNT_1_.C = (CLK_OSZI); - -!CLK_000_CNT_2_.D = (!CLK_000 & inst_CLK_000_D.Q - # CLK_000 & !inst_CLK_000_D.Q - # !CLK_000_CNT_0_.Q & !CLK_000_CNT_2_.Q - # !CLK_000_CNT_1_.Q & !CLK_000_CNT_2_.Q - # CLK_000_CNT_0_.Q & CLK_000_CNT_1_.Q & CLK_000_CNT_2_.Q); - -CLK_000_CNT_2_.C = (CLK_OSZI); - -CLK_000_CNT_3_.T = (!CLK_000 & inst_CLK_000_D.Q & CLK_000_CNT_3_.Q - # CLK_000 & !inst_CLK_000_D.Q & CLK_000_CNT_3_.Q - # CLK_000 & inst_CLK_000_D.Q & CLK_000_CNT_0_.Q & CLK_000_CNT_1_.Q & CLK_000_CNT_2_.Q - # !CLK_000 & !inst_CLK_000_D.Q & CLK_000_CNT_0_.Q & CLK_000_CNT_1_.Q & CLK_000_CNT_2_.Q); - -CLK_000_CNT_3_.C = (CLK_OSZI); - SM_AMIGA_2_.AR = (!RST); SM_AMIGA_2_.D = (!inst_CLK_000_D.Q & SM_AMIGA_2_.Q @@ -451,21 +445,11 @@ SM_AMIGA_2_.D = (!inst_CLK_000_D.Q & SM_AMIGA_2_.Q SM_AMIGA_2_.C = (CLK_OSZI); -SM_AMIGA_1_.AR = (!RST); - -!SM_AMIGA_1_.D = (!inst_CLK_000_D.Q & SM_AMIGA_2_.Q - # !SM_AMIGA_2_.Q & !SM_AMIGA_1_.Q - # !CLK_000 & !inst_DTACK_SYNC.Q & !SM_AMIGA_2_.Q - # !CLK_000 & E.Q & cpu_est_1_.Q & !inst_VPA_SYNC.Q & cpu_est_0_.Q & cpu_est_2_.Q & !SM_AMIGA_2_.Q); - -SM_AMIGA_1_.C = (CLK_OSZI); - SM_AMIGA_0_.AR = (!RST); SM_AMIGA_0_.D = (!AS_000.Q & SM_AMIGA_0_.Q # !inst_CLK_000_D.Q & SM_AMIGA_0_.Q - # !CLK_000 & !inst_DTACK_SYNC.Q & SM_AMIGA_1_.Q - # !CLK_000 & E.Q & cpu_est_1_.Q & !inst_VPA_SYNC.Q & cpu_est_0_.Q & cpu_est_2_.Q & SM_AMIGA_1_.Q); + # !inst_CLK_000_D.Q & inst_CLK_OUT_PRE.Q & SM_AMIGA_1_.Q); SM_AMIGA_0_.C = (CLK_OSZI); @@ -475,20 +459,15 @@ SM_AMIGA_0_.C = (CLK_OSZI); SM_AMIGA_D_0_.C = (CLK_OSZI); !SM_AMIGA_D_1_.D = (!RST & !SM_AMIGA_D_1_.Q - # RST & !SM_AMIGA_4_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q); + # RST & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q); SM_AMIGA_D_1_.C = (CLK_OSZI); !SM_AMIGA_D_2_.D = (!RST & !SM_AMIGA_D_2_.Q - # RST & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q); + # RST & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & !SM_AMIGA_0_.Q); SM_AMIGA_D_2_.C = (CLK_OSZI); -un1_UDS_000_INT_0_sqmuxa_2_0 = (!DS_030 & RW & SM_AMIGA_5_.Q - # !DS_030 & RW & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & SM_AMIGA_6_.Q - # !DS_030 & !RW & inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & SM_AMIGA_4_.Q & !SM_AMIGA_5_.Q - # !DS_030 & !RW & inst_CLK_000_D.Q & !SM_AMIGA_6_.Q & SM_AMIGA_4_.Q & !SM_AMIGA_5_.Q); - Reverse-Polarity Equations: diff --git a/Logic/68030_tk.fti b/Logic/68030_tk.fti index 18fe8f7..a568afd 100644 --- a/Logic/68030_tk.fti +++ b/Logic/68030_tk.fti @@ -34,12 +34,8 @@ DATA LOCATION BG_000:D_1_29 // IO {RN_BG_000} DATA LOCATION BG_030:C_*_21 // INP DATA LOCATION CIIN:E_12_47 // OUT DATA LOCATION CLK_000:*_*_11 // INP -DATA LOCATION CLK_000_CNT_0_:H_5 // NOD -DATA LOCATION CLK_000_CNT_1_:G_5 // NOD -DATA LOCATION CLK_000_CNT_2_:H_13 // NOD -DATA LOCATION CLK_000_CNT_3_:H_2 // NOD DATA LOCATION CLK_030:*_*_64 // INP -DATA LOCATION CLK_CNT_0_:G_15 // NOD +DATA LOCATION CLK_CNT_0_:G_14 // NOD DATA LOCATION CLK_DIV_OUT:G_0_65 // OUT DATA LOCATION CLK_EXP:B_0_10 // OUT DATA LOCATION CLK_OSZI:*_*_61 // Cin @@ -58,7 +54,7 @@ DATA LOCATION IPL_030_2_:B_4_9 // IO {RN_IPL_030_2_} DATA LOCATION IPL_0_:G_*_67 // INP DATA LOCATION IPL_1_:F_*_56 // INP DATA LOCATION IPL_2_:G_*_68 // INP -DATA LOCATION LDS_000:D_12_31 // IO {RN_LDS_000} +DATA LOCATION LDS_000:D_8_31 // IO {RN_LDS_000} DATA LOCATION RESET:B_5_3 // OUT DATA LOCATION RN_AS_000:D_5 // NOD {AS_000} DATA LOCATION RN_BGACK_030:H_4 // NOD {BGACK_030} @@ -69,39 +65,42 @@ DATA LOCATION RN_FPU_CS:H_0 // NOD {FPU_CS} DATA LOCATION RN_IPL_030_0_:B_8 // NOD {IPL_030_0_} DATA LOCATION RN_IPL_030_1_:B_12 // NOD {IPL_030_1_} DATA LOCATION RN_IPL_030_2_:B_4 // NOD {IPL_030_2_} -DATA LOCATION RN_LDS_000:D_12 // NOD {LDS_000} -DATA LOCATION RN_UDS_000:D_8 // NOD {UDS_000} +DATA LOCATION RN_LDS_000:D_8 // NOD {LDS_000} +DATA LOCATION RN_UDS_000:D_12 // NOD {UDS_000} DATA LOCATION RN_VMA:D_4 // NOD {VMA} DATA LOCATION RST:*_*_86 // INP DATA LOCATION RW:G_*_71 // INP DATA LOCATION SIZE_0_:G_*_70 // INP DATA LOCATION SIZE_1_:H_*_79 // INP -DATA LOCATION SM_AMIGA_0_:G_8 // NOD -DATA LOCATION SM_AMIGA_1_:G_1 // NOD -DATA LOCATION SM_AMIGA_2_:G_9 // NOD -DATA LOCATION SM_AMIGA_3_:G_13 // NOD +DATA LOCATION SM_AMIGA_0_:G_9 // NOD +DATA LOCATION SM_AMIGA_1_:G_12 // NOD +DATA LOCATION SM_AMIGA_2_:G_13 // NOD +DATA LOCATION SM_AMIGA_3_:G_8 // NOD DATA LOCATION SM_AMIGA_4_:D_13 // NOD DATA LOCATION SM_AMIGA_5_:D_6 // NOD DATA LOCATION SM_AMIGA_6_:D_2 // NOD DATA LOCATION SM_AMIGA_7_:G_6 // NOD -DATA LOCATION SM_AMIGA_D_0_:B_13 // NOD -DATA LOCATION SM_AMIGA_D_1_:B_9 // NOD -DATA LOCATION SM_AMIGA_D_2_:G_2 // NOD -DATA LOCATION UDS_000:D_8_32 // IO {RN_UDS_000} +DATA LOCATION SM_AMIGA_D_0_:B_6 // NOD +DATA LOCATION SM_AMIGA_D_1_:B_13 // NOD +DATA LOCATION SM_AMIGA_D_2_:B_9 // NOD +DATA LOCATION UDS_000:D_12_32 // IO {RN_UDS_000} DATA LOCATION VMA:D_4_35 // IO {RN_VMA} DATA LOCATION VPA:*_*_36 // INP -DATA LOCATION cpu_est_0_:G_11 // NOD -DATA LOCATION cpu_est_1_:G_3 // NOD -DATA LOCATION cpu_est_2_:G_7 // NOD -DATA LOCATION inst_AS_030_000_SYNC:H_1 // NOD -DATA LOCATION inst_CLK_000_D:A_0 // NOD -DATA LOCATION inst_CLK_000_DD:D_14 // NOD +DATA LOCATION cpu_est_0_:G_5 // NOD +DATA LOCATION cpu_est_1_:G_2 // NOD +DATA LOCATION cpu_est_2_:G_1 // NOD +DATA LOCATION cpu_est_d_0_:G_15 // NOD +DATA LOCATION cpu_est_d_1_:G_7 // NOD +DATA LOCATION cpu_est_d_2_:G_3 // NOD +DATA LOCATION cpu_est_d_3_:G_11 // NOD +DATA LOCATION inst_AS_030_000_SYNC:H_5 // NOD +DATA LOCATION inst_CLK_000_D:H_1 // NOD +DATA LOCATION inst_CLK_000_DD:H_13 // NOD DATA LOCATION inst_CLK_OUT_PRE:G_10 // NOD -DATA LOCATION inst_DTACK_SYNC:G_14 // NOD +DATA LOCATION inst_DTACK_SYNC:A_8 // NOD DATA LOCATION inst_RISING_CLK_AMIGA:H_9 // NOD -DATA LOCATION inst_VPA_D:B_6 // NOD -DATA LOCATION inst_VPA_SYNC:G_12 // NOD -DATA LOCATION un1_UDS_000_INT_0_sqmuxa_2_0:D_10 // NOD +DATA LOCATION inst_VPA_D:A_0 // NOD +DATA LOCATION inst_VPA_SYNC:F_0 // NOD DATA IO_DIR AMIGA_BUS_DATA_DIR:OUT DATA IO_DIR AMIGA_BUS_ENABLE:OUT DATA IO_DIR AMIGA_BUS_ENABLE_LOW:OUT @@ -162,46 +161,18 @@ DATA IO_DIR UDS_000:OUT DATA IO_DIR VMA:OUT DATA IO_DIR VPA:IN DATA GLB_CLOCK CLK_OSZI -DATA PW_LEVEL A_30_:0 -DATA SLEW A_30_:0 -DATA PW_LEVEL A_29_:0 -DATA SLEW A_29_:0 +DATA PW_LEVEL FC_0_:0 +DATA SLEW FC_0_:0 DATA PW_LEVEL SIZE_1_:0 DATA SLEW SIZE_1_:0 -DATA PW_LEVEL A_28_:0 -DATA SLEW A_28_:0 -DATA PW_LEVEL A_27_:0 -DATA SLEW A_27_:0 DATA PW_LEVEL A_31_:0 DATA SLEW A_31_:0 -DATA PW_LEVEL A_26_:0 -DATA SLEW A_26_:0 -DATA PW_LEVEL A_25_:0 -DATA SLEW A_25_:0 -DATA PW_LEVEL A_24_:0 -DATA SLEW A_24_:0 -DATA PW_LEVEL A_23_:0 -DATA SLEW A_23_:0 DATA PW_LEVEL IPL_2_:0 DATA SLEW IPL_2_:0 -DATA PW_LEVEL A_22_:0 -DATA SLEW A_22_:0 -DATA PW_LEVEL A_21_:0 -DATA SLEW A_21_:0 -DATA PW_LEVEL A_20_:0 -DATA SLEW A_20_:0 -DATA PW_LEVEL A_19_:0 -DATA SLEW A_19_:0 DATA PW_LEVEL FC_1_:0 DATA SLEW FC_1_:0 -DATA PW_LEVEL A_18_:0 -DATA SLEW A_18_:0 DATA PW_LEVEL AS_030:0 DATA SLEW AS_030:0 -DATA PW_LEVEL A_17_:0 -DATA SLEW A_17_:0 -DATA PW_LEVEL A_16_:0 -DATA SLEW A_16_:0 DATA PW_LEVEL DS_030:0 DATA SLEW DS_030:0 DATA SLEW CPU_SPACE:0 @@ -214,36 +185,64 @@ DATA SLEW BGACK_000:0 DATA SLEW CLK_030:0 DATA SLEW CLK_000:0 DATA SLEW CLK_OSZI:0 +DATA PW_LEVEL SIZE_0_:0 +DATA SLEW SIZE_0_:0 DATA PW_LEVEL CLK_EXP:0 DATA SLEW CLK_EXP:0 -DATA PW_LEVEL A_0_:0 -DATA SLEW A_0_:0 +DATA PW_LEVEL A_30_:0 +DATA SLEW A_30_:0 +DATA PW_LEVEL A_29_:0 +DATA SLEW A_29_:0 +DATA PW_LEVEL A_28_:0 +DATA SLEW A_28_:0 DATA PW_LEVEL AVEC:0 DATA SLEW AVEC:0 +DATA PW_LEVEL A_27_:0 +DATA SLEW A_27_:0 DATA PW_LEVEL AVEC_EXP:0 DATA SLEW AVEC_EXP:0 +DATA PW_LEVEL A_26_:0 +DATA SLEW A_26_:0 +DATA PW_LEVEL A_25_:0 +DATA SLEW A_25_:0 +DATA SLEW VPA:0 +DATA PW_LEVEL A_24_:0 +DATA SLEW A_24_:0 +DATA PW_LEVEL A_23_:0 +DATA SLEW A_23_:0 +DATA SLEW RST:0 +DATA PW_LEVEL A_22_:0 +DATA SLEW A_22_:0 +DATA PW_LEVEL A_21_:0 +DATA SLEW A_21_:0 +DATA PW_LEVEL RW:0 +DATA SLEW RW:0 +DATA PW_LEVEL A_20_:0 +DATA SLEW A_20_:0 +DATA PW_LEVEL AMIGA_BUS_ENABLE:0 +DATA SLEW AMIGA_BUS_ENABLE:0 +DATA PW_LEVEL A_19_:0 +DATA SLEW A_19_:0 +DATA PW_LEVEL AMIGA_BUS_DATA_DIR:0 +DATA SLEW AMIGA_BUS_DATA_DIR:0 +DATA PW_LEVEL A_18_:0 +DATA SLEW A_18_:0 +DATA PW_LEVEL AMIGA_BUS_ENABLE_LOW:0 +DATA SLEW AMIGA_BUS_ENABLE_LOW:0 +DATA PW_LEVEL A_17_:0 +DATA SLEW A_17_:0 +DATA PW_LEVEL CIIN:0 +DATA SLEW CIIN:0 +DATA PW_LEVEL A_16_:0 +DATA SLEW A_16_:0 +DATA PW_LEVEL A_0_:0 +DATA SLEW A_0_:0 DATA PW_LEVEL IPL_1_:0 DATA SLEW IPL_1_:0 -DATA SLEW VPA:0 DATA PW_LEVEL IPL_0_:0 DATA SLEW IPL_0_:0 DATA PW_LEVEL DSACK_0_:0 DATA SLEW DSACK_0_:0 -DATA SLEW RST:0 -DATA PW_LEVEL FC_0_:0 -DATA SLEW FC_0_:0 -DATA PW_LEVEL RW:0 -DATA SLEW RW:0 -DATA PW_LEVEL AMIGA_BUS_ENABLE:0 -DATA SLEW AMIGA_BUS_ENABLE:0 -DATA PW_LEVEL AMIGA_BUS_DATA_DIR:0 -DATA SLEW AMIGA_BUS_DATA_DIR:0 -DATA PW_LEVEL AMIGA_BUS_ENABLE_LOW:0 -DATA SLEW AMIGA_BUS_ENABLE_LOW:0 -DATA PW_LEVEL CIIN:0 -DATA SLEW CIIN:0 -DATA PW_LEVEL SIZE_0_:0 -DATA SLEW SIZE_0_:0 DATA PW_LEVEL IPL_030_2_:0 DATA SLEW IPL_030_2_:0 DATA PW_LEVEL DSACK_1_:0 @@ -264,18 +263,24 @@ DATA PW_LEVEL FPU_CS:0 DATA SLEW FPU_CS:0 DATA PW_LEVEL DTACK:0 DATA SLEW DTACK:0 -DATA PW_LEVEL IPL_030_1_:0 -DATA SLEW IPL_030_1_:0 -DATA PW_LEVEL IPL_030_0_:0 -DATA SLEW IPL_030_0_:0 DATA PW_LEVEL E:0 DATA SLEW E:0 DATA PW_LEVEL VMA:0 DATA SLEW VMA:0 DATA PW_LEVEL RESET:0 DATA SLEW RESET:0 +DATA PW_LEVEL IPL_030_1_:0 +DATA SLEW IPL_030_1_:0 +DATA PW_LEVEL IPL_030_0_:0 +DATA SLEW IPL_030_0_:0 +DATA PW_LEVEL cpu_est_0_:0 +DATA SLEW cpu_est_0_:0 DATA PW_LEVEL cpu_est_1_:0 DATA SLEW cpu_est_1_:0 +DATA PW_LEVEL cpu_est_d_0_:0 +DATA SLEW cpu_est_d_0_:0 +DATA PW_LEVEL cpu_est_d_3_:0 +DATA SLEW cpu_est_d_3_:0 DATA PW_LEVEL inst_AS_030_000_SYNC:0 DATA SLEW inst_AS_030_000_SYNC:0 DATA PW_LEVEL inst_DTACK_SYNC:0 @@ -290,8 +295,10 @@ DATA PW_LEVEL inst_CLK_000_DD:0 DATA SLEW inst_CLK_000_DD:0 DATA PW_LEVEL inst_CLK_OUT_PRE:0 DATA SLEW inst_CLK_OUT_PRE:0 -DATA PW_LEVEL cpu_est_0_:0 -DATA SLEW cpu_est_0_:0 +DATA PW_LEVEL cpu_est_d_1_:0 +DATA SLEW cpu_est_d_1_:0 +DATA PW_LEVEL cpu_est_d_2_:0 +DATA SLEW cpu_est_d_2_:0 DATA PW_LEVEL cpu_est_2_:0 DATA SLEW cpu_est_2_:0 DATA PW_LEVEL CLK_CNT_0_:0 @@ -302,24 +309,16 @@ DATA PW_LEVEL SM_AMIGA_7_:0 DATA SLEW SM_AMIGA_7_:0 DATA PW_LEVEL inst_RISING_CLK_AMIGA:0 DATA SLEW inst_RISING_CLK_AMIGA:0 +DATA PW_LEVEL SM_AMIGA_1_:0 +DATA SLEW SM_AMIGA_1_:0 DATA PW_LEVEL SM_AMIGA_4_:0 DATA SLEW SM_AMIGA_4_:0 DATA PW_LEVEL SM_AMIGA_3_:0 DATA SLEW SM_AMIGA_3_:0 DATA PW_LEVEL SM_AMIGA_5_:0 DATA SLEW SM_AMIGA_5_:0 -DATA PW_LEVEL CLK_000_CNT_0_:0 -DATA SLEW CLK_000_CNT_0_:0 -DATA PW_LEVEL CLK_000_CNT_1_:0 -DATA SLEW CLK_000_CNT_1_:0 -DATA PW_LEVEL CLK_000_CNT_2_:0 -DATA SLEW CLK_000_CNT_2_:0 -DATA PW_LEVEL CLK_000_CNT_3_:0 -DATA SLEW CLK_000_CNT_3_:0 DATA PW_LEVEL SM_AMIGA_2_:0 DATA SLEW SM_AMIGA_2_:0 -DATA PW_LEVEL SM_AMIGA_1_:0 -DATA SLEW SM_AMIGA_1_:0 DATA PW_LEVEL SM_AMIGA_0_:0 DATA SLEW SM_AMIGA_0_:0 DATA PW_LEVEL SM_AMIGA_D_0_:0 @@ -328,8 +327,6 @@ DATA PW_LEVEL SM_AMIGA_D_1_:0 DATA SLEW SM_AMIGA_D_1_:0 DATA PW_LEVEL SM_AMIGA_D_2_:0 DATA SLEW SM_AMIGA_D_2_:0 -DATA PW_LEVEL un1_UDS_000_INT_0_sqmuxa_2_0:0 -DATA SLEW un1_UDS_000_INT_0_sqmuxa_2_0:0 DATA PW_LEVEL RN_IPL_030_2_:0 DATA PW_LEVEL RN_DSACK_1_:0 DATA PW_LEVEL RN_AS_000:0 @@ -338,8 +335,8 @@ DATA PW_LEVEL RN_LDS_000:0 DATA PW_LEVEL RN_BG_000:0 DATA PW_LEVEL RN_BGACK_030:0 DATA PW_LEVEL RN_FPU_CS:0 -DATA PW_LEVEL RN_IPL_030_1_:0 -DATA PW_LEVEL RN_IPL_030_0_:0 DATA PW_LEVEL RN_E:0 DATA PW_LEVEL RN_VMA:0 +DATA PW_LEVEL RN_IPL_030_1_:0 +DATA PW_LEVEL RN_IPL_030_0_:0 END diff --git a/Logic/68030_tk.grp b/Logic/68030_tk.grp index 1845f1a..5197407 100644 --- a/Logic/68030_tk.grp +++ b/Logic/68030_tk.grp @@ -1,16 +1,16 @@ -GROUP MACH_SEG_A inst_CLK_000_D AVEC -GROUP MACH_SEG_B SM_AMIGA_D_1_ SM_AMIGA_D_0_ IPL_030_1_ RN_IPL_030_1_ IPL_030_0_ - RN_IPL_030_0_ IPL_030_2_ RN_IPL_030_2_ inst_VPA_D RESET CLK_EXP +GROUP MACH_SEG_A inst_DTACK_SYNC inst_VPA_D AVEC +GROUP MACH_SEG_B SM_AMIGA_D_1_ SM_AMIGA_D_2_ SM_AMIGA_D_0_ IPL_030_1_ RN_IPL_030_1_ + IPL_030_0_ RN_IPL_030_0_ IPL_030_2_ RN_IPL_030_2_ RESET CLK_EXP GROUP MACH_SEG_C AVEC_EXP AMIGA_BUS_ENABLE_LOW -GROUP MACH_SEG_D UDS_000 RN_UDS_000 LDS_000 RN_LDS_000 BG_000 RN_BG_000 - AS_000 RN_AS_000 VMA RN_VMA SM_AMIGA_6_ SM_AMIGA_5_ SM_AMIGA_4_ DTACK - inst_CLK_000_DD un1_UDS_000_INT_0_sqmuxa_2_0 AMIGA_BUS_ENABLE +GROUP MACH_SEG_D LDS_000 RN_LDS_000 VMA RN_VMA UDS_000 RN_UDS_000 BG_000 + RN_BG_000 AS_000 RN_AS_000 SM_AMIGA_6_ SM_AMIGA_5_ SM_AMIGA_4_ DTACK + AMIGA_BUS_ENABLE GROUP MACH_SEG_E CIIN BERR AMIGA_BUS_DATA_DIR -GROUP MACH_SEG_G SM_AMIGA_0_ SM_AMIGA_1_ inst_VPA_SYNC inst_DTACK_SYNC - SM_AMIGA_D_2_ E RN_E cpu_est_1_ cpu_est_2_ SM_AMIGA_2_ SM_AMIGA_3_ - SM_AMIGA_7_ CLK_000_CNT_1_ cpu_est_0_ inst_CLK_OUT_PRE CLK_CNT_0_ - CLK_DIV_OUT -GROUP MACH_SEG_H DSACK_1_ RN_DSACK_1_ inst_AS_030_000_SYNC FPU_CS RN_FPU_CS - CLK_000_CNT_3_ CLK_000_CNT_2_ BGACK_030 RN_BGACK_030 CLK_000_CNT_0_ - inst_RISING_CLK_AMIGA DSACK_0_ \ No newline at end of file +GROUP MACH_SEG_F inst_VPA_SYNC +GROUP MACH_SEG_G E RN_E cpu_est_1_ cpu_est_2_ SM_AMIGA_2_ SM_AMIGA_3_ SM_AMIGA_0_ + SM_AMIGA_7_ SM_AMIGA_1_ cpu_est_0_ inst_CLK_OUT_PRE CLK_CNT_0_ CLK_DIV_OUT + cpu_est_d_3_ cpu_est_d_1_ cpu_est_d_2_ cpu_est_d_0_ +GROUP MACH_SEG_H inst_AS_030_000_SYNC FPU_CS RN_FPU_CS DSACK_1_ RN_DSACK_1_ + BGACK_030 RN_BGACK_030 inst_RISING_CLK_AMIGA inst_CLK_000_D inst_CLK_000_DD + DSACK_0_ \ No newline at end of file diff --git a/Logic/68030_tk.ipr b/Logic/68030_tk.ipr index a3b1a89..2b14e0d 100644 --- a/Logic/68030_tk.ipr +++ b/Logic/68030_tk.ipr @@ -1 +1 @@ -3467346{D`00n \ No newline at end of file +7526<46^3ðt( \ No newline at end of file diff --git a/Logic/68030_tk.jed b/Logic/68030_tk.jed index e53b249..12ba74d 100644 --- a/Logic/68030_tk.jed +++ b/Logic/68030_tk.jed @@ -10,7 +10,7 @@ AUTHOR: PATTERN: COMPANY: REVISION: -DATE: Thu May 15 19:20:57 2014 +DATE: Thu May 15 22:17:31 2014 ABEL mach447a * @@ -31,49 +31,48 @@ NOTE Spread Placement? Y * NOTE Run Time Upper Bound in 15 minutes 0 * NOTE Zero Hold Time For Input Registers? Y * NOTE Table of pin names and numbers* -NOTE PINS A_30_:5 A_29_:6 SIZE_1_:79 A_28_:15 A_27_:16 A_31_:4* -NOTE PINS A_26_:17 A_25_:18 A_24_:19 A_23_:84 IPL_2_:68 A_22_:85* -NOTE PINS A_21_:94 A_20_:93 A_19_:97 FC_1_:58 A_18_:95 AS_030:82* -NOTE PINS A_17_:59 A_16_:96 DS_030:98 CPU_SPACE:14 BERR:41* -NOTE PINS BG_030:21 BGACK_000:28 CLK_030:64 CLK_000:11 CLK_OSZI:61* -NOTE PINS CLK_EXP:10 A_0_:69 AVEC:92 AVEC_EXP:22 IPL_1_:56* -NOTE PINS VPA:36 IPL_0_:67 DSACK_0_:80 RST:86 FC_0_:57 RW:71* -NOTE PINS AMIGA_BUS_ENABLE:34 AMIGA_BUS_DATA_DIR:48 AMIGA_BUS_ENABLE_LOW:20* -NOTE PINS CIIN:47 SIZE_0_:70 IPL_030_2_:9 DSACK_1_:81 AS_000:33* -NOTE PINS UDS_000:32 LDS_000:31 BG_000:29 BGACK_030:83 CLK_DIV_OUT:65* -NOTE PINS FPU_CS:78 DTACK:30 IPL_030_1_:7 IPL_030_0_:8 E:66* -NOTE PINS VMA:35 RESET:3 * +NOTE PINS FC_0_:57 SIZE_1_:79 A_31_:4 IPL_2_:68 FC_1_:58* +NOTE PINS AS_030:82 DS_030:98 CPU_SPACE:14 BERR:41 BG_030:21* +NOTE PINS BGACK_000:28 CLK_030:64 CLK_000:11 CLK_OSZI:61* +NOTE PINS SIZE_0_:70 CLK_EXP:10 A_30_:5 A_29_:6 A_28_:15* +NOTE PINS AVEC:92 A_27_:16 AVEC_EXP:22 A_26_:17 A_25_:18* +NOTE PINS VPA:36 A_24_:19 A_23_:84 RST:86 A_22_:85 A_21_:94* +NOTE PINS RW:71 A_20_:93 AMIGA_BUS_ENABLE:34 A_19_:97 AMIGA_BUS_DATA_DIR:48* +NOTE PINS A_18_:95 AMIGA_BUS_ENABLE_LOW:20 A_17_:59 CIIN:47* +NOTE PINS A_16_:96 A_0_:69 IPL_1_:56 IPL_0_:67 DSACK_0_:80* +NOTE PINS IPL_030_2_:9 DSACK_1_:81 AS_000:33 UDS_000:32 LDS_000:31* +NOTE PINS BG_000:29 BGACK_030:83 CLK_DIV_OUT:65 FPU_CS:78* +NOTE PINS DTACK:30 E:66 VMA:35 RESET:3 IPL_030_1_:7 IPL_030_0_:8* NOTE Table of node names and numbers* NOTE NODES RN_IPL_030_2_:131 RN_DSACK_1_:281 RN_AS_000:181 * -NOTE NODES RN_UDS_000:185 RN_LDS_000:191 RN_BG_000:175 RN_BGACK_030:275 * -NOTE NODES RN_FPU_CS:269 RN_DTACK:173 RN_IPL_030_1_:143 * -NOTE NODES RN_IPL_030_0_:137 RN_E:251 RN_VMA:179 cpu_est_1_:250 * -NOTE NODES inst_AS_030_000_SYNC:271 inst_DTACK_SYNC:266 * -NOTE NODES inst_VPA_D:134 inst_VPA_SYNC:263 inst_CLK_000_D:101 * -NOTE NODES inst_CLK_000_DD:194 inst_CLK_OUT_PRE:260 cpu_est_0_:262 * -NOTE NODES cpu_est_2_:256 CLK_CNT_0_:268 SM_AMIGA_6_:176 * -NOTE NODES SM_AMIGA_7_:254 inst_RISING_CLK_AMIGA:283 SM_AMIGA_4_:193 * -NOTE NODES SM_AMIGA_3_:265 SM_AMIGA_5_:182 CLK_000_CNT_0_:277 * -NOTE NODES CLK_000_CNT_1_:253 CLK_000_CNT_2_:289 CLK_000_CNT_3_:272 * -NOTE NODES SM_AMIGA_2_:259 SM_AMIGA_1_:247 SM_AMIGA_0_:257 * -NOTE NODES SM_AMIGA_D_0_:145 SM_AMIGA_D_1_:139 SM_AMIGA_D_2_:248 * -NOTE NODES un1_UDS_000_INT_0_sqmuxa_2_0:188 * +NOTE NODES RN_UDS_000:191 RN_LDS_000:185 RN_BG_000:175 RN_BGACK_030:275 * +NOTE NODES RN_FPU_CS:269 RN_DTACK:173 RN_E:251 RN_VMA:179 * +NOTE NODES RN_IPL_030_1_:143 RN_IPL_030_0_:137 cpu_est_0_:253 * +NOTE NODES cpu_est_1_:248 cpu_est_d_0_:268 cpu_est_d_3_:262 * +NOTE NODES inst_AS_030_000_SYNC:277 inst_DTACK_SYNC:113 * +NOTE NODES inst_VPA_D:101 inst_VPA_SYNC:221 inst_CLK_000_D:271 * +NOTE NODES inst_CLK_000_DD:289 inst_CLK_OUT_PRE:260 cpu_est_d_1_:256 * +NOTE NODES cpu_est_d_2_:250 cpu_est_2_:247 CLK_CNT_0_:266 * +NOTE NODES SM_AMIGA_6_:176 SM_AMIGA_7_:254 inst_RISING_CLK_AMIGA:283 * +NOTE NODES SM_AMIGA_1_:263 SM_AMIGA_4_:193 SM_AMIGA_3_:257 * +NOTE NODES SM_AMIGA_5_:182 SM_AMIGA_2_:265 SM_AMIGA_0_:259 * +NOTE NODES SM_AMIGA_D_0_:134 SM_AMIGA_D_1_:145 SM_AMIGA_D_2_:139 * NOTE BLOCK 0 * L000000 - 111111011111111111111111111111111111111111111111111111111111111111 + 111111111111111111111111111111111111111111111111111111111111111111 111111111011111111111111111111111111111111111111111111111111111111 + 111111111111111111111111111011111111111111111111111111111111111111 111111111111111111111111111111111111111111111111111111111111111111 111111111111111111111111111111111111111111111111111111111111111111 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111* + 111111011111111111111111111101111111111111111111111111111111111111 + 111111111111111111101111111111111111111111111111111111111111111111 + 101111111111111111110111101111011111111111111111111111111111111111* L000594 000000000000000000000000000000000000000000000000000000000000000000* -L000660 111111011111111111111111111111111111111111111111111111111111111111* -L000726 111111111111111111111111111111111111111111111111111111111111111111* -L000792 111111111111111111111111111111111111111111111111111111111111111111* +L000660 111111111111111111110111111111111111111111111111111111111111111111* +L000726 111111110111111111111111111111111111111111111111111111111111111111* +L000792 000000000000000000000000000000000000000000000000000000000000000000* L000858 111111111111111111111111111111111111111111111111111111111111111111* L000924 111111111111111111111111111111111111111111111111111111111111111111* L000990 111111111111111111111111111111111111111111111111111111111111111111* @@ -119,11 +118,11 @@ L003366 111111111111111111111111111111111111111111111111111111111111111111* L003432 111111111111111111111111111111111111111111111111111111111111111111* L003498 000000000000000000000000000000000000000000000000000000000000000000* -L003564 111111111111111111111111111111111111111111111111111111111111111111* -L003630 111111111111111111111111111111111111111111111111111111111111111111* -L003696 111111111111111111111111111111111111111111111111111111111111111111* -L003762 111111111111111111111111111111111111111111111111111111111111111111* -L003828 111111111111111111111111111111111111111111111111111111111111111111* +L003564 111111101111111111101111111111111111111111111111111111111111111111* +L003630 111111111111111111111111010110011111111111111111111111111111111111* +L003696 000000000000000000000000000000000000000000000000000000000000000000* +L003762 000000000000000000000000000000000000000000000000000000000000000000* +L003828 000000000000000000000000000000000000000000000000000000000000000000* L003894 111111111111111111111111111111111111111111111111111111111111111111* L003960 111111111111111111111111111111111111111111111111111111111111111111* L004026 111111111111111111111111111111111111111111111111111111111111111111* @@ -167,9 +166,9 @@ L006270 111111111111111111111111111111111111111111111111111111111111111111* L006336 111111111111111111111111111111111111111111111111111111111111111111* L006402 000000000000000000000000000000000000000000000000000000000000000000 - 000000000000000000000000000000000000000000000000000000000000000000* + 101111111111111111111111111111111111111111111111111111111111111111* L006534 0010* -L006538 00010110010000* +L006538 00011110000000* L006552 11011011111110* L006566 11110011110101* L006580 11110111111111* @@ -177,43 +176,43 @@ L006594 00110011111000* L006608 11000111110011* L006622 11110011110001* L006636 11110111110011* -L006650 11110011110000* -L006664 11111011110011* -L006678 11110111110001* -L006692 11111111110011* -L006706 11110011110000* -L006720 11111011110011* -L006734 11110111110001* -L006748 11111111110011* +L006650 11100110010000* +L006664 11000011110011* +L006678 11111011110001* +L006692 11110111110011* +L006706 11111111110000* +L006720 11110011110011* +L006734 11111011110001* +L006748 11110111110011* NOTE BLOCK 1 * L006762 - 111111111111111111101111011111111111111111011111111111111111111111 + 111111111111111011101111011111111111111111011111111111111111111111 111111111111011111111011111111111111111111111111111111111110111111 - 111111101111111101111111111111111111111111111011111111111011111111 - 101111111111111111111111111111111111111111111110111111011111111111 - 111111111011111111111111111111111111111111111111111111111111111111 + 111101101111111101111111111011111111111111111011111111111111111111 + 111111111111111111111111111111111011111111111111111111011111111111 + 111111111111111111111111111111111111111111111111111111111111111111 110111111111111111111111111111111111111111111111111111111111111111 111111111110111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111011111 - 111111111111111111111111110111110111111111111111101111111111111111* + 111111110111111111111111111111111111111111111111111111111111111111 + 101111111111111111111111111111111111111111111111111111110111111111* L007356 111111111111111111111111111111111111111111111111111111111111111111* -L007422 111111111111011111111111111111111111111111011101111111110111111111* -L007488 111111111111111111111111111111111111111111111111111111110111111111* -L007554 111011111111111111111011111111111011111111011111111111111111111111* -L007620 111111111111111111111111111111110111111111101111111111111111111111* -L007686 110111111111111111111111111111111111111111101111111111111111111111* -L007752 111111111111111111110111111111111111111111101111111111111111111111* -L007818 111011111011011111111111111111111111111111111111111111111111101111* -L007884 110111111111101111111111111111111111111111111111111111111111111111* -L007950 111111111111101111111111111111111111111111111111111111111111011111* -L008016 111111110111101111111111111111111111111111111111111111111111111111* +L007422 111101111111011111110111111111111111111111011111111111111111111111* +L007488 111111111111111111110111111111111111111111111111111111111111111111* +L007554 111001111111111111101111111111111111111111111111111111111011111111* +L007620 111110111111111111111111111111111111111111111111111111110111111111* +L007686 110110111111111111111111111111111111111111111111111111111111111111* +L007752 111110111111111111011111111111111111111111111111111111111111111111* +L007818 111011111011111011111111111111111111111111011111111111111111111111* +L007884 111111111111110111111111111111111111111111101111111111111111111111* +L007950 110111111111111111111111111111111111111111101111111111111111111111* +L008016 111111110111111111111111111111111111111111101111111111111111111111* L008082 111111111111111111111111111111111111111111111111111111111111111111* -L008148 111111111011111111101011111111111111111111111101111111111111111111* -L008214 111111111111111111011111111111111111111111111110111111111111111111* -L008280 111111111111111111110111111111111111111111111110111111111111111111* -L008346 111111110111111111111111111111111111111111111110111111111111111111* +L008148 111111111111011011101111111011111111111111111111111111111111111111* +L008214 111111111111100111111111111111111111111111111111111111111111111111* +L008280 111111111111101111111111110111111111111111111111111111111111111111* +L008346 111111111111101111011111111111111111111111111111111111111111111111* L008412 000000000000000000000000000000000000000000000000000000000000000000* L008478 111111111111111111111111111111111111111111111111111111111111111111* L008544 111111111111111111111111111111111111111111111111111111111111111111* @@ -227,18 +226,18 @@ L008940 111111111110111111111111111111111111111111111111111111011111111111* L009006 000000000000000000000000000000000000000000000000000000000000000000* L009072 000000000000000000000000000000000000000000000000000000000000000000* L009138 000000000000000000000000000000000000000000000000000000000000000000* -L009204 111111111111111111111111111111111111111111111111011111111111111111* +L009204 011111111111111111111111111111111111111111111111111111111111111111* L009270 111111111111111111111111111111111111111111111111111111111101111111* L009336 000000000000000000000000000000000000000000000000000000000000000000* L009402 111111111111111111111111111111111111111111111111111111111111111111* L009468 111111111111111111111111111111111111111111111111111111111111111111* L009534 111111111111111111111111111111111111111111111111111111111111111111* -L009600 111111111111111111111111110111111111111111111111111111111111111111* +L009600 011011111111111111101011111111111111111111111111111111111011111111* L009666 111111111111111111111111111111111111111111111111111111111101111111* L009732 000000000000000000000000000000000000000000000000000000000000000000* -L009798 111111111111111111111111111111111111111111111111111111111111111111* -L009864 111111111111111111111111111111111111111111111111111111111111111111* +L009798 101110111111111111111111111111111111111111111111111111111111111111* +L009864 000000000000000000000000000000000000000000000000000000000000000000* L009930 111111111111111111111111111111111111111111111111111111111111111111* L009996 111111111111111111111111111111111111111111111111111111111111111111* L010062 111111111111111111111111111111111111111111111111111111111111111111* @@ -246,15 +245,15 @@ L010128 111111111111111111111111111111111111111111111111111111111111111111* L010194 111111111111111111111111111111111111111111111111111111111111111111* L010260 000000000000000000000000000000000000000000000000000000000000000000* -L010326 011111111101111111111111111111111111111111111111111111111111111111* +L010326 111111111101111111111111111111110111111111111111111111111111111111* L010392 111111111110111101111111111111111111111111111111111111111111111111* L010458 000000000000000000000000000000000000000000000000000000000000000000* L010524 000000000000000000000000000000000000000000000000000000000000000000* L010590 000000000000000000000000000000000000000000000000000000000000000000* -L010656 111011111011111111111111111111111111111111111111011111111011101111* +L010656 011111111111111011101011111011111111111111111111111111111111111111* L010722 111111111111111111111111111111111111111111111111111111111101111111* L010788 000000000000000000000000000000000000000000000000000000000000000000* -L010854 111111111111101111111111111111111111111111111111101111111111111111* +L010854 101111111111101111111111111111111111111111111111111111111111111111* L010920 000000000000000000000000000000000000000000000000000000000000000000* L010986 000000000000000000000000000000000000000000000000000000000000000000* @@ -275,10 +274,10 @@ L011844 111111111110111111111111011111111111111111111111111111111111111111* L011910 000000000000000000000000000000000000000000000000000000000000000000* L011976 000000000000000000000000000000000000000000000000000000000000000000* L012042 000000000000000000000000000000000000000000000000000000000000000000* -L012108 111011111111111111111011111111111011111111111111011111111011111111* +L012108 011011111011111011111011111111111111111111111111111111111111111111* L012174 111111111111111111111111111111111111111111111111111111111101111111* L012240 000000000000000000000000000000000000000000000000000000000000000000* -L012306 111111111111111111111111111111111111111111101111101111111111111111* +L012306 101111111111111111111111111111111111111111101111111111111111111111* L012372 000000000000000000000000000000000000000000000000000000000000000000* L012438 111111111111111111111111111111111111111111111111111111111111111111* @@ -294,7 +293,7 @@ L013032 111111111111111111111111111111111111111111111111111111111111111111* L013098 111111111111111111111111111111111111111111111111111111111111111111* L013164 000000000000000000000000000000000000000000000000000000000000000000 - 111111111111111111111111111111111111111111111111101111111111111111* + 101111111111111111111111111111111111111111111111111111111111111111* L013296 0010* L013300 00100011110000* L013314 11111111111111* @@ -302,7 +301,7 @@ L013328 11001011110100* L013342 11110011111110* L013356 10100110010011* L013370 00001110001111* -L013384 00011110000110* +L013384 11101110000110* L013398 11100111111111* L013412 10100110011001* L013426 11101110000011* @@ -441,32 +440,32 @@ L020258 11110111110101* L020272 11111111111111* NOTE BLOCK 3 * L020286 - 111111111111111011111111111111111111111111111111111111111011111111 - 111111111111111110111111111110111111111111010111111111111110111111 - 101111111111111111111111111111111111111111111110111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111011111111111111111111111111111 - 110111111101101111111111111111111111111111111111111111111111011111 - 111111111111111111111111111111110110111111111111111111111111111111 - 111111110111111111100101111111111111111110111111111111111111111111 - 111101011111111111111111101111011111111111111111101111111111111111* + 111111111111111111111111111111111111101110111111111111111111111111 + 111111110101111111111111111111111110111111111111111010111111111111 + 111111111111111110111111111111101111111111111110111111111111111111 + 111110111111111111111111111111111111111111111011101111111111111011 + 111111111111111111111111011111111111111111111111111111111111111110 + 110111111111101111111101111111111111111111111111111111111011111111 + 111111111111111111111011111111110111111111111111111111111111111111 + 101111111111110111101111111001111111111111111111111111111111011111 + 111111011111111111111111111111111111111011101111111111011101111111* L020880 111111111111111111111111111111111111111111111111111111111111111111* -L020946 111111111111111111111110111111111110111111111111111111111111111111* +L020946 111111111111111011111011111111111111111111111111111111111111111111* L021012 000000000000000000000000000000000000000000000000000000000000000000* L021078 000000000000000000000000000000000000000000000000000000000000000000* L021144 000000000000000000000000000000000000000000000000000000000000000000* L021210 000000000000000000000000000000000000000000000000000000000000000000* -L021276 111111011111111111011111111111111111111111101011111111111011111111* -L021342 111110111111111111111111111111111111111111111011111111110111111111* -L021408 111111111111111111011111111111111111111111101001111111111011111111* +L021276 111111111011111111111111111111111111111101111111111111101111111111* +L021342 111111011010111111011111111111111111111110111111111111111111111111* +L021408 111111111010111111011111111111111111111110111101111111111111111111* L021474 000000000000000000000000000000000000000000000000000000000000000000* L021540 000000000000000000000000000000000000000000000000000000000000000000* L021606 111111111111111111111111111111111111111111111111111111111111111111* -L021672 111111011111111111111111011111111111111111111111111111111111111111* -L021738 111111011111111111111111111111101111111111111111111111111111111111* -L021804 111111111111111111111111111111101111111111111101111111111111111111* +L021672 111111111111111111111111111011111111110111111111111111111011111111* +L021738 111111111111111111111111111111111111110111111101111111111111111111* +L021804 111111101111111111111111111111111111111111111110111111111111111111* L021870 000000000000000000000000000000000000000000000000000000000000000000* L021936 000000000000000000000000000000000000000000000000000000000000000000* L022002 111111111111111111111111111111111111111111111111111111111111111111* @@ -475,47 +474,47 @@ L022134 111111111111111111111111111111111111111111111111111111111111111111* L022200 111111111111111111111111111111111111111111111111111111111111111111* L022266 111111111111111111111111111111111111111111111111111111111111111111* L022332 - 111111111111111111111111111111111111111101111111111111111111111111* -L022398 111111111111110111110111111111111111111111111111111111111111111111* -L022464 111111111111111111110111111111011111111111111111111111111111111111* -L022530 111111111111111111111101111111011111111111111111111111111111111111* + 011111111111111111111111111111111111111111111111111111111111111111* +L022398 111111111111110101111111111110111111100111111111011110111111111111* +L022464 111110111111111111111111111101111111111011110111111111111110111001* +L022530 000000000000000000000000000000000000000000000000000000000000000000* L022596 000000000000000000000000000000000000000000000000000000000000000000* L022662 000000000000000000000000000000000000000000000000000000000000000000* -L022728 111111111111111111101110111111111111111111111111111111111111111111* -L022794 111111011111111111111111101111011111111111111111111111111111111111* +L022728 111111111111111011101111111111111111111111111111111111111111111111* +L022794 111111011111111111111111111011111111110111111111111111111011111111* L022860 000000000000000000000000000000000000000000000000000000000000000000* L022926 000000000000000000000000000000000000000000000000000000000000000000* L022992 000000000000000000000000000000000000000000000000000000000000000000* L023058 - 111111111111111111111111111111111111111101111111111111111111111111* -L023124 111111011111111111111111101111011111111111111111111111111111111111* -L023190 111111110111111111111111111111011111111111111111111111111111111111* + 011111111111111111111111111111111111111111111111111111111111111111* +L023124 111111011111111111111111111011111111110111111111111111111011111111* +L023190 111111111111111111111111111111111111110111111111111111111111011111* L023256 000000000000000000000000000000000000000000000000000000000000000000* L023322 000000000000000000000000000000000000000000000000000000000000000000* L023388 000000000000000000000000000000000000000000000000000000000000000000* -L023454 101111011111111101111111101111011111101111111111111111111111111111* -L023520 111111111111111111101111111111111011011111111111111111111111111111* -L023586 111111011111111110101111101111111011111111111111111111111111111111* -L023652 111011111111111110101111111111111011111111111111111111111111111111* -L023718 101111110111111101111111111111111111101111111111111111111111111111* +L023454 111111111111111111111111111111111111111111111111111111111111111111* +L023520 111111111111111111111111111111111111111111111111111111111111111111* +L023586 111111111111111111111111111111111111111111111111111111111111111111* +L023652 111111111111111111111111111111111111111111111111111111111111111111* +L023718 111111111111111111111111111111111111111111111111111111111111111111* L023784 - 111111111111111111111111111111111111111101111111111111111111111111* -L023850 111111110111111110101111111111111011111111111111111111111111111111* -L023916 111111111011111101101111011111111011111111111111111111111111111111* -L023982 111111111011111111101111111111101011111111111111111111111111111111* -L024048 111111101011111101101111111111111011111111111111111111111111111111* -L024114 100111111011111110111111011111011111101111111111111111111111111111* + 011111111111111111111111111111111111111111111111111111111111111111* +L023850 111111011111011111111111101011111111110111111111110111111011111111* +L023916 111111011111111111111111101011111110110111111111110111111011111111* +L023982 111111011111111111111111101011011111110111111111110111111011111111* +L024048 111111111111111111101111011111111011111111111111111111111111111111* +L024114 111111111111111111101111110111111011111111111111110111111111111111* L024180 000000000000000000000000000000000000000000000000000000000000000000* -L024246 100111101011111110111111111111011111101111111111111111111111111111* -L024312 000000000000000000000000000000000000000000000000000000000000000000* -L024378 000000000000000000000000000000000000000000000000000000000000000000* -L024444 000000000000000000000000000000000000000000000000000000000000000000* +L024246 111111111111111111101111111111111011111011111111111111111111111111* +L024312 111111111111111111101111111111111011111111111111110111110111111111* +L024378 111111101111111111101111111111111011111111111111110111111111111111* +L024444 110111111111011111111111101111111111110111111111111011111111111111* L024510 - 111111111111111111111111111111111111111110111111111111111111111111* -L024576 111111011111111101111111101111011111101111111111111111111111111111* -L024642 111111110111111101111111111111111111101111111111111111111111111111* -L024708 110111111011111110111111011111011111101111111111111111111111111111* -L024774 110111101011111110111111111111011111101111111111111111111111111111* + 101111111111111111111111111111111111111111111111111111111111111111* +L024576 110111111111111111111111101111111110110111111111111011111111111111* +L024642 110111111111111111111111101111011111110111111111111011111111111111* +L024708 111011111111111111101111111111111011111111111111111011111111111111* +L024774 000000000000000000000000000000000000000000000000000000000000000000* L024840 000000000000000000000000000000000000000000000000000000000000000000* L024906 111111111111111111111111111111111111111111111111111111111111111111* L024972 111111111111111111111111111111111111111111111111111111111111111111* @@ -524,23 +523,23 @@ L025104 111111111111111111111111111111111111111111111111111111111111111111* L025170 111111111111111111111111111111111111111111111111111111111111111111* L025236 111111111111111111111111111111111111111111111111111111111111111111* -L025302 101111111111101111111111111101111111111111111111111111111111011111* -L025368 111111111111111111011111111111111111111111111111111111111111101111* -L025434 111111111101111111111111111111111111111111111111111111111111101111* -L025500 000000000000000000000000000000000000000000000000000000000000000000* -L025566 000000000000000000000000000000000000000000000000000000000000000000* -L025632 110111111111111111111111111111101111111111111111111111111111111111* -L025698 111111110111111111111111111111101111111111111111111111111111111111* +L025302 111111011111111111111111101011101111110111111111110111111011111111* +L025368 111111111111111111101110011111111111111111111111111111111111111111* +L025434 111111111111111111101110110111111111111111111111110111111111111111* +L025500 111111111111111111101110111111111111111011111111111111111111111111* +L025566 111111111111111111101110111111111111111111111111110111110111111111* +L025632 110111111111111111111111111111111111111011111111111111111111111111* +L025698 111111111111111111111111111111111111111011111111111111111111011111* L025764 000000000000000000000000000000000000000000000000000000000000000000* L025830 000000000000000000000000000000000000000000000000000000000000000000* L025896 000000000000000000000000000000000000000000000000000000000000000000* L025962 000000000000000000000000000000000000000000000000000000000000000000* -L026028 111111111111111111111111111111011111111111111111111111111111111111* -L026094 111111111111111111111111111111111111111111111111111111111101111111* -L026160 000000000000000000000000000000000000000000000000000000000000000000* -L026226 111111111111111111111111111111111111111111111111111111111111111111* -L026292 111111111111111111111111111111111111111111111111111111111111111111* +L026028 111111101111111111101110111111111111111111111111110111111111111111* +L026094 110111111111111111111111101111101111110111111111111011111111111111* +L026160 111011111111111111101110111111111111111111111111111011111111111111* +L026226 000000000000000000000000000000000000000000000000000000000000000000* +L026292 000000000000000000000000000000000000000000000000000000000000000000* L026358 111111111111111111111111111111111111111111111111111111111111111111* L026424 111111111111111111111111111111111111111111111111111111111111111111* L026490 111111111111111111111111111111111111111111111111111111111111111111* @@ -548,24 +547,24 @@ L026556 111111111111111111111111111111111111111111111111111111111111111111* L026622 111111111111111111111111111111111111111111111111111111111111111111* L026688 000000000000000000000000000000000000000000000000000000000000000000 - 111111111111111111111111111111111111111111111111101111111111111111* + 111111111111111111111111111111111111111111101111111111111111111111* L026820 0010* L026824 01100110010010* L026838 11100110011110* -L026852 10100100011110* +L026852 11100100011110* L026866 11100011111111* -L026880 10100110011001* +L026880 10100111011001* L026894 11100110011111* -L026908 10100100010100* -L026922 11011111111111* -L026936 11100110010011* +L026908 10100100010110* +L026922 11101111111111* +L026936 11100110010001* L026950 00111011111111* -L026964 10101111110110* -L026978 11100011110010* -L026992 10100110011010* +L026964 11001111110110* +L026978 11110011110010* +L026992 11100110011010* L027006 10100100011111* -L027020 00011110000000* -L027034 11101011110010* +L027020 11001011110000* +L027034 11111111110010* NOTE BLOCK 4 * L027048 111111111111111111111111111111111111111111111111111111111111111111 @@ -696,21 +695,21 @@ L033796 11111111111111* NOTE BLOCK 5 * L033810 111111111111111111111111111111111111111111111111111111111111111111 + 111111111011111111111111111111111111111111111111111111111111111111 + 111111111111111111111111111011111111111111111111111111111111111111 + 111110101111111111111111111111111111111111111110111111111111111111 + 111111111110111111111111111111111111111111111111101111111111111111 111111111111111111111111111111111111111111111111111111111111111111 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111* + 111111111111111111100111111111111111111111111111111111111111111111 + 101111111111111111111111101111011111111111111111111111111111111111* L034404 000000000000000000000000000000000000000000000000000000000000000000* -L034470 111111111111111111111111111111111111111111111111111111111111111111* -L034536 111111111111111111111111111111111111111111111111111111111111111111* -L034602 111111111111111111111111111111111111111111111111111111111111111111* -L034668 111111111111111111111111111111111111111111111111111111111111111111* -L034734 111111111111111111111111111111111111111111111111111111111111111111* +L034470 111111111110111111101111111111111111111111111111111111111111111111* +L034536 111101101111111111111011010111101111111111111110011111111111111111* +L034602 000000000000000000000000000000000000000000000000000000000000000000* +L034668 000000000000000000000000000000000000000000000000000000000000000000* +L034734 000000000000000000000000000000000000000000000000000000000000000000* L034800 111111111111111111111111111111111111111111111111111111111111111111* L034866 111111111111111111111111111111111111111111111111111111111111111111* L034932 111111111111111111111111111111111111111111111111111111111111111111* @@ -802,10 +801,10 @@ L040080 111111111111111111111111111111111111111111111111111111111111111111* L040146 111111111111111111111111111111111111111111111111111111111111111111* L040212 000000000000000000000000000000000000000000000000000000000000000000 - 000000000000000000000000000000000000000000000000000000000000000000* -L040344 0000* -L040348 11010011111110* -L040362 11110111111111* + 101111111111111111111111111111111111111111111111111111111111111111* +L040344 0010* +L040348 11100110011110* +L040362 11011011111110* L040376 11110011111111* L040390 11110111110011* L040404 11110011111110* @@ -822,107 +821,107 @@ L040544 11110111111111* L040558 11111111111111* NOTE BLOCK 6 * L040572 - 111111011111111111111111101110111111101111111111111110111111111111 - 111111111011111111111011111011111111111111111011111111111111111111 - 111101111111111110111111111111111111111111111110111111111011111111 - 111111111110111111111110111111111111111111111111111111111111111010 - 111111111111111111111111111111111101111111111111101111111111111111 - 110111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111011111111111111111111111111111111111111111111111 - 111111111111110111111111111111111111111011111111111111101111111111 - 101111111111111111111111111111011111111111111111111111111111111111* + 111111111111111111101011111110111111111111111111111111111111111111 + 111111111011111111111111101111111111111111111011111111111111111111 + 111111111111111111111111111011111111111111111110111111111111111111 + 111110111111111111111111111111111111111111111111111111111111111010 + 111111111110111111111111111111111111111111111111101111111111111111 + 110111111111111011111111111111111111111111111111111111111111111111 + 111111011111111111111111111111111111111111111111111111111111111111 + 111111111111111111111101111111111111111111111111111111111111111111 + 101111111111111111111111111111111111111011111111111111111111111111* L041166 111111111111111111111111111111111111111111111111111111111111111111* L041232 111111111111111111111111111111111111111111110111111111111111111111* -L041298 111111111111111111110111111111101111111111111111111111111111111111* -L041364 111111101111111111111011111111111111111111111111111110111111111111* -L041430 111111101101111101111001110110111111111111111111111111111111111111* -L041496 111111111111111111111011111111111111111111111111101111111111111111* -L041562 000000000000000000000000000000000000000000000000000000000000000000* -L041628 111111110111111111111111111111111111111111111111111111111111111111* -L041694 101111111111111111111111111111111111111111111111111111111111111111* -L041760 000000000000000000000000000000000000000000000000000000000000000000* +L041298 000000000000000000000000000000000000000000000000000000000000000000* +L041364 000000000000000000000000000000000000000000000000000000000000000000* +L041430 000000000000000000000000000000000000000000000000000000000000000000* +L041496 000000000000000000000000000000000000000000000000000000000000000000* +L041562 111111111111111111111111111111111111111111111111011111111111111111* +L041628 111101111111111011111111111111111111110111111111101111111111111101* +L041694 111111111111111011111111111111111111110111111111101111111111111010* +L041760 111110111111111011111111111111111111110111111111011111111111111001* L041826 000000000000000000000000000000000000000000000000000000000000000000* L041892 111111111111111111111111111111111111111111111111111111111111111111* -L041958 011111111111111111111011101111111111111111111111101111111011111111* -L042024 101111111111111111111111111111111111111111111111111111111111111011* -L042090 000000000000000000000000000000000000000000000000000000000000000000* -L042156 000000000000000000000000000000000000000000000000000000000000000000* +L041958 111101111111111011111111111111111111110111111111111111111111111010* +L042024 111110111111111011111111111111111111110111111111011111111111111101* +L042090 111101111111111011111111111111111111110111111111101111111111110101* +L042156 111110111111111011111111111111111111110111111111101111111111111011* L042222 000000000000000000000000000000000000000000000000000000000000000000* -L042288 111111111110111111111101111011011110111111111111111111111111111111* -L042354 111111111111111101111110110111011110111111111111111111111111111111* -L042420 111111111110111110111110111111011110111111111111111111111111111111* -L042486 111111111101111110111101110111011110111111111111111111111111111111* +L042288 111111111111111111111111111111111111111111111111011111111111111111* +L042354 000000000000000000000000000000000000000000000000000000000000000000* +L042420 000000000000000000000000000000000000000000000000000000000000000000* +L042486 000000000000000000000000000000000000000000000000000000000000000000* L042552 000000000000000000000000000000000000000000000000000000000000000000* L042618 000000000000000000000000000000000000000000000000000000000000000000* -L042684 111111111101111101111101110111011110111111111111111111111111111111* -L042750 111111111101111110111110110111011110111111111111111111111111111111* -L042816 111111111110111110111110111011011110111111111111111111111111111111* +L042684 111101111111111011111111111111111111110111111111011111111111110101* +L042750 111110111111111011111111111111111111110111111111101111111111110101* +L042816 111110111111111011111111111111111111110111111111101111111111111010* L042882 000000000000000000000000000000000000000000000000000000000000000000* L042948 000000000000000000000000000000000000000000000000000000000000000000* -L043014 111111011111111111111111111111011111111111111111111111101111111101* -L043080 111111101111111111111111111111101111111111111111111111101111111101* -L043146 111111011111111111111111111111011111111111111111111111011111111110* -L043212 111111101111111111111111111111101111111111111111111111011111111110* +L043014 111111111111111111111111111111111111111011111111111111111111111101* +L043080 111111111111110111111111111111111111111111111111111111111111111101* +L043146 111111111111111011111111111111111111110111111111111111111111111110* +L043212 000000000000000000000000000000000000000000000000000000000000000000* L043278 000000000000000000000000000000000000000000000000000000000000000000* L043344 000000000000000000000000000000000000000000000000000000000000000000* -L043410 111111111111111111111111111111011111111111111101111111111111111111* +L043410 111111111111111111111111111111111111110111111101111111111111111111* L043476 111111110111111111111111111111111111111111111111111111111111111111* L043542 101111111111111111111111111111111111111111111111111111111111111111* -L043608 111111111111110111111111111111011111111111111111111111110111111111* +L043608 111111111111111111111101011111111111110111111111111111111111111111* L043674 000000000000000000000000000000000000000000000000000000000000000000* -L043740 111111111111111101111111111111111111111111111111111111111111111111* -L043806 111111111111111110111101110111011110111111111111111111111111111111* -L043872 111111111110111110111111111011011110111111111111111111111111111111* -L043938 111111111110111101111110110111011110111111111111111111111111111111* +L043740 111111111111111111111111111111111111111111111111111111111111110111* +L043806 000000000000000000000000000000000000000000000000000000000000000000* +L043872 000000000000000000000000000000000000000000000000000000000000000000* +L043938 000000000000000000000000000000000000000000000000000000000000000000* L044004 000000000000000000000000000000000000000000000000000000000000000000* L044070 000000000000000000000000000000000000000000000000000000000000000000* -L044136 111111111111111111111111011111101111111111111111111110111111111111* +L044136 110111111111111111111111111111111111110111111111111111111111111111* L044202 111111110111111111111111111111111111111111111111111111111111111111* L044268 101111111111111111111111111111111111111111111111111111111111111111* -L044334 111111111111111111111111011110101111111111111111111111111111111111* -L044400 111111111111111111110111111111101111111111111111111111111111111111* -L044466 111111111111111111111111111111111111011111111011111111111111111111* +L044334 111111011101111111111111110111111111111111111111111111111111111111* +L044400 111111111111111111111111110111111111110111111111111111111111111111* +L044466 111111111111111111111111111101111111111011110111111111111111111111* L044532 111111110111111111111111111111111111111111111111111111111111111111* L044598 101111111111111111111111111111111111111111111111111111111111111111* -L044664 111111111111111111111111111111111111101111110111111111111111111111* -L044730 000000000000000000000000000000000000000000000000000000000000000000* +L044664 111111111111111111111110011111111111111111111111111111111111111111* +L044730 111111111111111111111111011111111111111011111111111111111111111111* L044796 000000000000000000000000000000000000000000000000000000000000000000* -L044862 111111101111111111111111111111111111111111111111011110111111111111* -L044928 111111101101111101111101110110111111111111111111011111111111111111* -L044994 111111111111111011111111111111111111111111111111111111110111111111* -L045060 111111111111111111111111111111101111111111111111111111110111111111* +L044862 111111111111111111110111111111111111111111111011111111111111111111* +L044928 111111111111111111111011111111111111111111110111111111111111111111* +L044994 000000000000000000000000000000000000000000000000000000000000000000* +L045060 000000000000000000000000000000000000000000000000000000000000000000* L045126 000000000000000000000000000000000000000000000000000000000000000000* -L045192 111111111111111111111111110111101111111111111111111111111111111111* -L045258 111111111111111111111111110111111101111111111111111111111111111111* -L045324 111111111111111111111111111011011110111111111111111111111111111111* +L045192 111101111111111111111111111111111111111111111111111111111111111111* +L045258 000000000000000000000000000000000000000000000000000000000000000000* +L045324 000000000000000000000000000000000000000000000000000000000000000000* L045390 000000000000000000000000000000000000000000000000000000000000000000* L045456 000000000000000000000000000000000000000000000000000000000000000000* L045522 000000000000000000000000000000000000000000000000000000000000000000* -L045588 111111111111111111111111111110111111111011111111111111111111111111* +L045588 111111111111111111111111111101111111110111111111111111111111111111* L045654 111111110111111111111111111111111111111111111111111111111111111111* L045720 101111111111111111111111111111111111111111111111111111111111111111* -L045786 111110111110111101111110010111011111111111111111111111111111111111* -L045852 000000000000000000000000000000000000000000000000000000000000000000* -L045918 110111111111111111111111111111011111111111111111111111111111111111* +L045786 111111111111111111111111111101111111111111111011111111111111111111* +L045852 111111111111111111011111111111111111110111111111111111111111111111* +L045918 111111101111111111111111110111111111111011111111111111111111111111* L045984 111111110111111111111111111111111111111111111111111111111111111111* L046050 101111111111111111111111111111111111111111111111111111111111111111* -L046116 111111111111111111111111011101111111111111111111111101111111111111* -L046182 111111111111111111111111011111011111111111111111111111111111111111* +L046116 111111111110111111111111110111111111111011111111111111111111111111* +L046182 111111111111111111011111111111111111111011111111111111111111111111* L046248 000000000000000000000000000000000000000000000000000000000000000000* -L046314 111111111111111111111111111111111111111011111111111110111111111111* -L046380 111111110111111111111111111111111111111111111111111111111111111111* -L046446 101111111111111111111111111111111111111111111111111111111111111111* -L046512 111101111111111111101111011111011111111111111111111111111111111111* +L046314 111111111111111111111011111111111111111111111111111111111111111111* +L046380 000000000000000000000000000000000000000000000000000000000000000000* +L046446 000000000000000000000000000000000000000000000000000000000000000000* +L046512 000000000000000000000000000000000000000000000000000000000000000000* L046578 000000000000000000000000000000000000000000000000000000000000000000* -L046644 111111111111111111111111111111111111101111111111111111111111111111* +L046644 111111111111111111111111111111111111111111111111111111111111111101* L046710 000000000000000000000000000000000000000000000000000000000000000000* L046776 000000000000000000000000000000000000000000000000000000000000000000* L046842 000000000000000000000000000000000000000000000000000000000000000000* @@ -931,100 +930,100 @@ L046974 000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000* L047106 0010* -L047110 00010110010000* -L047124 11101110001110* -L047138 11100110010100* -L047152 10100111011111* +L047110 00100110010000* +L047124 00100110011110* +L047138 10100111010100* +L047152 00100110011111* L047166 10100111011001* L047180 10100110010011* L047194 10101100000000* L047208 00100110010010* -L047222 10011110000000* -L047236 10011110000011* -L047250 10000110010001* -L047264 10100110010011* -L047278 11101100000000* +L047222 10101110000000* +L047236 10101110000011* +L047250 10100110010001* +L047264 00100110010011* +L047278 10101110000000* L047292 10101110000010* -L047306 11101100000000* +L047306 00100110010000* L047320 00100110011111* NOTE BLOCK 7 * L047334 - 111111111111111011111110111111111111111110111111011111111111111111 + 111111011111111011111111111111111111111110111111111111111111111111 111111111101111111111111111111111111111111101011111111111111111111 - 111111111111111111111111111111111110111111111111111111111011111111 - 111011111111111110111111111111111111111111111111111111111111111110 + 111111111111101111111111111111111111111111111111111111111111111111 + 111011111111111110111111111111111111111111111111111111111111111111 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111011111111111011011111111111111111111111111 - 111111100111011111111111111111111111111111111111111111101111111111 - 111111111111111111101111111011111111111111111110111111111111111111 - 101111111111111111111011111110011111111111111111111111111111101111* + 111111111111111111111111011111111111011111111111111111111111111111 + 111111111111111111111101111011111101111111111111111111101111111111 + 111111111011111111101111111111111111111111111110111111111111111111 + 101111111111111111111011111111111111111111111111111111111111101111* L047928 000000000000000000000000000000000000000000000000000000000000000000* -L047994 110111111011101101101111101111111101011101111111111111111111111111* +L047994 110111111111011101101110101111111110011101111111111111111111111111* L048060 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000000000000000000000000000000000000000000000000000000000000000000* -L052878 111111111111111111111111111111011111111111111111101111111111111111* -L052944 111111111111111111111111110111111111110111111111111111111111111101* +L052878 111111111111111111111111111111111111111111111111111111111111111111* +L052944 111111111111111111111111111111111111111111111111111111111111111111* L053010 111111111111111111111111111111111111111111111111111111111111111111* L053076 111111111111111111111111111111111111111111111111111111111111111111* @@ -1049,31 +1048,31 @@ L053142 111111111111111111111111111111111111111111111111111111111111111111* L053208 111111111111111111111111111111111111111111111111111111111111111111* L053274 111111111111111111111111111111111111111111111111111111111111111111* L053340 111111111111111111111111111111111111111111111111111111111111111111* -L053406 111111111111111111111111111011111111111011111111111111111111111111* -L053472 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11111011110000* -L053970 11010011110011* -L053984 11110110010001* -L053998 00111110000011* -L054012 11001111110100* -L054026 11110011111110* -L054040 00111011111001* -L054054 11101110000011* -L054068 11010111110100* -L054082 11001111111111* +L053886 00011110000010* +L053900 11011111110000* +L053914 11111011110011* +L053928 10100110010000* +L053942 10100110011110* +L053956 11011111110001* +L053970 11111011110011* +L053984 11100110010000* +L053998 00001110000010* +L054012 11010011110100* +L054026 11111011111111* +L054040 00110111111000* +L054054 00001110000010* +L054068 11011111110101* +L054082 11110011111111* E1 0 00000000 @@ -1093,6 +1092,6 @@ E1 00000000 1 * -C1D70* +CEB62* U00000000000000000000000000000000* -DC63 +CFEF diff --git a/Logic/68030_tk.jid b/Logic/68030_tk.jid index 4d6ed37..7e63140 100644 --- a/Logic/68030_tk.jid +++ b/Logic/68030_tk.jid @@ -1 +1 @@ -. BUS68030 68030-68000-bus.vhd c:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd +. BUS68030 68030-68000-bus.vhd c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd diff --git a/Logic/68030_tk.lco b/Logic/68030_tk.lco index ddddb01..74b2228 100644 --- a/Logic/68030_tk.lco +++ b/Logic/68030_tk.lco @@ -17,7 +17,7 @@ Parent = m4a5.lci; SDS_File = m4a5.sds; Design = 68030_tk.tt4; DATE = 5/15/14; -TIME = 19:20:57; +TIME = 22:17:31; Source_Format = Pure_VHDL; Type = TT2; Pre_Fit_Time = 1; @@ -76,26 +76,12 @@ Usercode_Format = Hex; [LOCATION ASSIGNMENTS] Layer = OFF; -A_30_ = pin,5,-,B,-; -A_29_ = pin,6,-,B,-; +FC_0_ = pin,57,-,F,-; SIZE_1_ = pin,79,-,H,-; -A_28_ = pin,15,-,C,-; -A_27_ = pin,16,-,C,-; A_31_ = pin,4,-,B,-; -A_26_ = pin,17,-,C,-; -A_25_ = pin,18,-,C,-; -A_24_ = pin,19,-,C,-; -A_23_ = pin,84,-,H,-; IPL_2_ = pin,68,-,G,-; -A_22_ = pin,85,-,H,-; -A_21_ = pin,94,-,A,-; -A_20_ = pin,93,-,A,-; -A_19_ = pin,97,-,A,-; FC_1_ = pin,58,-,F,-; -A_18_ = pin,95,-,A,-; AS_030 = pin,82,-,H,-; -A_17_ = pin,59,-,F,-; -A_16_ = pin,96,-,A,-; DS_030 = pin,98,-,A,-; CPU_SPACE = pin,14,-,-,-; BERR = pin,41,-,E,-; @@ -104,22 +90,36 @@ BGACK_000 = pin,28,-,D,-; CLK_030 = pin,64,-,-,-; CLK_000 = pin,11,-,-,-; CLK_OSZI = pin,61,-,-,-; +SIZE_0_ = pin,70,-,G,-; CLK_EXP = pin,10,-,B,-; -A_0_ = pin,69,-,G,-; +A_30_ = pin,5,-,B,-; +A_29_ = pin,6,-,B,-; +A_28_ = pin,15,-,C,-; AVEC = pin,92,-,A,-; +A_27_ = pin,16,-,C,-; AVEC_EXP = pin,22,-,C,-; -IPL_1_ = pin,56,-,F,-; +A_26_ = pin,17,-,C,-; +A_25_ = pin,18,-,C,-; VPA = pin,36,-,-,-; +A_24_ = pin,19,-,C,-; +A_23_ = pin,84,-,H,-; +RST = pin,86,-,-,-; +A_22_ = pin,85,-,H,-; +A_21_ = pin,94,-,A,-; +RW = pin,71,-,G,-; +A_20_ = pin,93,-,A,-; +AMIGA_BUS_ENABLE = pin,34,-,D,-; +A_19_ = pin,97,-,A,-; +AMIGA_BUS_DATA_DIR = pin,48,-,E,-; +A_18_ = pin,95,-,A,-; +AMIGA_BUS_ENABLE_LOW = pin,20,-,C,-; +A_17_ = pin,59,-,F,-; +CIIN = pin,47,-,E,-; +A_16_ = pin,96,-,A,-; +A_0_ = pin,69,-,G,-; +IPL_1_ = pin,56,-,F,-; IPL_0_ = pin,67,-,G,-; DSACK_0_ = pin,80,-,H,-; -RST = pin,86,-,-,-; -FC_0_ = pin,57,-,F,-; -RW = pin,71,-,G,-; -AMIGA_BUS_ENABLE = pin,34,-,D,-; -AMIGA_BUS_DATA_DIR = pin,48,-,E,-; -AMIGA_BUS_ENABLE_LOW = pin,20,-,C,-; -CIIN = pin,47,-,E,-; -SIZE_0_ = pin,70,-,G,-; IPL_030_2_ = pin,9,-,B,-; DSACK_1_ = pin,81,-,H,-; AS_000 = pin,33,-,D,-; @@ -130,39 +130,38 @@ BGACK_030 = pin,83,-,H,-; CLK_DIV_OUT = pin,65,-,G,-; FPU_CS = pin,78,-,H,-; DTACK = pin,30,-,D,-; -IPL_030_1_ = pin,7,-,B,-; -IPL_030_0_ = pin,8,-,B,-; E = pin,66,-,G,-; VMA = pin,35,-,D,-; RESET = pin,3,-,B,-; -cpu_est_1_ = node,-,-,G,3; -inst_AS_030_000_SYNC = node,-,-,H,1; -inst_DTACK_SYNC = node,-,-,G,14; -inst_VPA_D = node,-,-,B,6; -inst_VPA_SYNC = node,-,-,G,12; -inst_CLK_000_D = node,-,-,A,0; -inst_CLK_000_DD = node,-,-,D,14; +IPL_030_1_ = pin,7,-,B,-; +IPL_030_0_ = pin,8,-,B,-; +cpu_est_0_ = node,-,-,G,5; +cpu_est_1_ = node,-,-,G,2; +cpu_est_d_0_ = node,-,-,G,15; +cpu_est_d_3_ = node,-,-,G,11; +inst_AS_030_000_SYNC = node,-,-,H,5; +inst_DTACK_SYNC = node,-,-,A,8; +inst_VPA_D = node,-,-,A,0; +inst_VPA_SYNC = node,-,-,F,0; +inst_CLK_000_D = node,-,-,H,1; +inst_CLK_000_DD = node,-,-,H,13; inst_CLK_OUT_PRE = node,-,-,G,10; -cpu_est_0_ = node,-,-,G,11; -cpu_est_2_ = node,-,-,G,7; -CLK_CNT_0_ = node,-,-,G,15; +cpu_est_d_1_ = node,-,-,G,7; +cpu_est_d_2_ = node,-,-,G,3; +cpu_est_2_ = node,-,-,G,1; +CLK_CNT_0_ = node,-,-,G,14; SM_AMIGA_6_ = node,-,-,D,2; SM_AMIGA_7_ = node,-,-,G,6; inst_RISING_CLK_AMIGA = node,-,-,H,9; +SM_AMIGA_1_ = node,-,-,G,12; SM_AMIGA_4_ = node,-,-,D,13; -SM_AMIGA_3_ = node,-,-,G,13; +SM_AMIGA_3_ = node,-,-,G,8; SM_AMIGA_5_ = node,-,-,D,6; -CLK_000_CNT_0_ = node,-,-,H,5; -CLK_000_CNT_1_ = node,-,-,G,5; -CLK_000_CNT_2_ = node,-,-,H,13; -CLK_000_CNT_3_ = node,-,-,H,2; -SM_AMIGA_2_ = node,-,-,G,9; -SM_AMIGA_1_ = node,-,-,G,1; -SM_AMIGA_0_ = node,-,-,G,8; -SM_AMIGA_D_0_ = node,-,-,B,13; -SM_AMIGA_D_1_ = node,-,-,B,9; -SM_AMIGA_D_2_ = node,-,-,G,2; -un1_UDS_000_INT_0_sqmuxa_2_0 = node,-,-,D,10; +SM_AMIGA_2_ = node,-,-,G,13; +SM_AMIGA_0_ = node,-,-,G,9; +SM_AMIGA_D_0_ = node,-,-,B,6; +SM_AMIGA_D_1_ = node,-,-,B,13; +SM_AMIGA_D_2_ = node,-,-,B,9; [GROUP ASSIGNMENTS] Layer = OFF; diff --git a/Logic/68030_tk.out b/Logic/68030_tk.out index fcb9096..a4175e0 100644 --- a/Logic/68030_tk.out +++ b/Logic/68030_tk.out @@ -47221,6 +47221,1821 @@ 16 A_26_ 1 -1 -1 1 4 16 -1 15 A_27_ 1 -1 -1 1 4 15 -1 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +105 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 328 7 1 3 80 -1 8 0 21 + 29 DTACK 5 -1 3 1 5 29 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 13 1 21 + 31 UDS_000 5 330 3 0 31 -1 11 0 21 + 65 E 5 335 6 0 65 -1 3 0 21 + 34 VMA 5 336 3 0 34 -1 3 0 21 + 30 LDS_000 5 331 3 0 30 -1 3 0 21 + 28 BG_000 5 332 3 0 28 -1 3 0 21 + 82 BGACK_030 5 333 7 0 82 -1 2 0 21 + 77 FPU_CS 5 334 7 0 77 -1 2 0 21 + 32 AS_000 5 329 3 0 32 -1 2 0 21 + 8 IPL_030_2_ 5 327 1 0 8 -1 2 0 21 + 7 IPL_030_0_ 5 338 1 0 7 -1 2 0 21 + 6 IPL_030_1_ 5 337 1 0 6 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 20 + 299 inst_VPA_SYNC 3 -1 6 7 0 1 2 3 5 6 7 -1 -1 2 0 20 + 297 inst_DTACK_SYNC 3 -1 5 6 0 1 2 5 6 7 -1 -1 2 0 21 + 302 inst_CLK_000_D 3 -1 3 6 0 1 2 3 5 6 -1 -1 1 0 20 + 321 SM_AMIGA_0_ 3 -1 5 4 0 1 3 5 -1 -1 4 0 21 + 320 SM_AMIGA_1_ 3 -1 2 4 1 2 5 7 -1 -1 4 0 21 + 293 cpu_est_1_ 3 -1 6 4 2 5 6 7 -1 -1 4 0 21 + 335 RN_E 3 65 6 4 2 5 6 7 65 -1 3 0 21 + 308 cpu_est_2_ 3 -1 6 4 2 5 6 7 -1 -1 3 1 21 + 307 cpu_est_0_ 3 -1 6 4 2 5 6 7 -1 -1 3 0 21 + 317 CLK_000_CNT_2_ 3 -1 6 3 0 6 7 -1 -1 5 0 21 + 318 CLK_000_CNT_3_ 3 -1 6 3 0 6 7 -1 -1 4 0 21 + 316 CLK_000_CNT_1_ 3 -1 6 3 0 6 7 -1 -1 4 0 21 + 313 SM_AMIGA_3_ 3 -1 6 3 1 5 6 -1 -1 3 0 20 + 334 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 329 RN_AS_000 3 32 3 3 0 3 5 32 -1 2 0 21 + 315 CLK_000_CNT_0_ 3 -1 6 3 0 6 7 -1 -1 2 0 21 + 312 SM_AMIGA_4_ 3 -1 3 3 1 3 6 -1 -1 2 0 21 + 296 inst_AS_030_000_SYNC 3 -1 0 2 0 3 -1 -1 4 0 21 + 319 SM_AMIGA_2_ 3 -1 1 2 1 2 -1 -1 3 0 21 + 309 SM_AMIGA_6_ 3 -1 3 2 1 3 -1 -1 3 0 21 + 304 inst_CLK_OUT_PRE 3 -1 6 2 0 6 -1 -1 3 0 21 + 333 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 314 SM_AMIGA_5_ 3 -1 3 2 1 3 -1 -1 2 0 21 + 311 inst_RISING_CLK_AMIGA 3 -1 3 2 1 7 -1 -1 1 0 20 + 298 inst_VPA_D 3 -1 6 2 5 6 -1 -1 1 0 21 + 330 RN_UDS_000 3 31 3 1 3 31 -1 11 0 21 + 328 RN_DSACK_1_ 3 80 7 1 7 80 -1 8 0 21 + 326 DSACK_INT_1_sqmuxa 3 -1 0 1 7 -1 -1 4 1 21 + 325 un1_UDS_000_INT_0_sqmuxa_2_0 3 -1 3 1 3 -1 -1 4 0 21 + 336 RN_VMA 3 34 3 1 3 34 -1 3 0 21 + 332 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 331 RN_LDS_000 3 30 3 1 3 30 -1 3 0 21 + 338 RN_IPL_030_0_ 3 7 1 1 1 7 -1 2 0 21 + 337 RN_IPL_030_1_ 3 6 1 1 1 6 -1 2 0 21 + 327 RN_IPL_030_2_ 3 8 1 1 1 8 -1 2 0 21 + 324 SM_AMIGA_D_2_ 3 -1 1 1 1 -1 -1 2 0 20 + 323 SM_AMIGA_D_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 322 SM_AMIGA_D_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 310 SM_AMIGA_7_ 3 -1 3 1 3 -1 -1 2 0 21 + 301 CLK_CNT_1_ 3 -1 6 1 6 -1 -1 2 0 21 + 306 cpu_est_d_2_ 3 -1 7 1 3 -1 -1 1 0 20 + 305 cpu_est_d_1_ 3 -1 7 1 3 -1 -1 1 0 20 + 303 inst_CLK_000_DD 3 -1 3 1 6 -1 -1 1 0 20 + 300 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 1 0 21 + 295 cpu_est_d_3_ 3 -1 6 1 3 -1 -1 1 0 21 + 294 cpu_est_d_0_ 3 -1 7 1 3 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 6 1 2 3 5 6 7 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 81 AS_030 1 -1 -1 5 0 3 5 6 7 81 -1 + 10 CLK_000 1 -1 -1 4 2 3 5 6 10 -1 + 63 CLK_030 1 -1 -1 3 0 3 7 63 -1 + 13 CPU_SPACE 1 -1 -1 3 0 3 7 13 -1 + 96 A_19_ 1 -1 -1 2 0 7 96 -1 + 95 A_16_ 1 -1 -1 2 0 7 95 -1 + 94 A_18_ 1 -1 -1 2 0 7 94 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 58 A_17_ 1 -1 -1 2 0 7 58 -1 + 57 FC_1_ 1 -1 -1 2 0 7 57 -1 + 56 FC_0_ 1 -1 -1 2 0 7 56 -1 + 27 BGACK_000 1 -1 -1 2 0 7 27 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +105 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 328 7 1 3 80 -1 5 0 21 + 29 DTACK 5 -1 3 1 4 29 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 13 1 21 + 31 UDS_000 5 330 3 0 31 -1 11 0 21 + 65 E 5 335 6 0 65 -1 3 0 21 + 34 VMA 5 336 3 0 34 -1 3 0 21 + 30 LDS_000 5 331 3 0 30 -1 3 0 21 + 28 BG_000 5 332 3 0 28 -1 3 0 21 + 82 BGACK_030 5 333 7 0 82 -1 2 0 21 + 77 FPU_CS 5 334 7 0 77 -1 2 0 21 + 32 AS_000 5 329 3 0 32 -1 2 0 21 + 8 IPL_030_2_ 5 327 1 0 8 -1 2 0 21 + 7 IPL_030_0_ 5 338 1 0 7 -1 2 0 21 + 6 IPL_030_1_ 5 337 1 0 6 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 20 + 302 inst_CLK_000_D 3 -1 1 7 0 1 3 4 5 6 7 -1 -1 1 0 20 + 299 inst_VPA_SYNC 3 -1 6 5 0 3 5 6 7 -1 -1 2 0 20 + 297 inst_DTACK_SYNC 3 -1 4 5 0 4 5 6 7 -1 -1 2 0 21 + 320 SM_AMIGA_1_ 3 -1 0 4 0 1 5 7 -1 -1 4 0 21 + 293 cpu_est_1_ 3 -1 6 4 0 5 6 7 -1 -1 4 0 21 + 335 RN_E 3 65 6 4 0 5 6 7 65 -1 3 0 21 + 314 SM_AMIGA_3_ 3 -1 0 4 0 1 4 6 -1 -1 3 0 21 + 308 cpu_est_2_ 3 -1 6 4 0 5 6 7 -1 -1 3 1 21 + 307 cpu_est_0_ 3 -1 6 4 0 5 6 7 -1 -1 3 0 21 + 329 RN_AS_000 3 32 3 4 1 3 5 7 32 -1 2 0 21 + 321 SM_AMIGA_0_ 3 -1 5 3 1 5 7 -1 -1 4 0 21 + 319 SM_AMIGA_2_ 3 -1 6 3 0 1 6 -1 -1 3 0 20 + 334 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 313 SM_AMIGA_4_ 3 -1 3 3 0 1 3 -1 -1 2 0 21 + 312 CLK_000_CNT_3_ 3 -1 6 2 6 7 -1 -1 4 0 21 + 296 inst_AS_030_000_SYNC 3 -1 7 2 3 7 -1 -1 4 0 21 + 309 SM_AMIGA_6_ 3 -1 3 2 1 3 -1 -1 3 0 21 + 304 inst_CLK_OUT_PRE 3 -1 6 2 6 7 -1 -1 3 0 21 + 333 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 316 CLK_000_CNT_0_ 3 -1 1 2 1 6 -1 -1 2 0 20 + 315 SM_AMIGA_5_ 3 -1 3 2 1 3 -1 -1 2 0 21 + 310 SM_AMIGA_7_ 3 -1 1 2 1 3 -1 -1 2 0 21 + 311 inst_RISING_CLK_AMIGA 3 -1 6 2 1 7 -1 -1 1 0 21 + 298 inst_VPA_D 3 -1 3 2 4 6 -1 -1 1 0 20 + 330 RN_UDS_000 3 31 3 1 3 31 -1 11 0 21 + 328 RN_DSACK_1_ 3 80 7 1 7 80 -1 5 0 21 + 318 CLK_000_CNT_2_ 3 -1 6 1 6 -1 -1 5 0 21 + 326 un1_UDS_000_INT_0_sqmuxa_2_0 3 -1 3 1 3 -1 -1 4 0 21 + 317 CLK_000_CNT_1_ 3 -1 6 1 6 -1 -1 4 0 21 + 336 RN_VMA 3 34 3 1 3 34 -1 3 0 21 + 332 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 331 RN_LDS_000 3 30 3 1 3 30 -1 3 0 21 + 325 state_machine_un27_clk_out_pre_0_n 3 -1 6 1 7 -1 -1 3 0 21 + 338 RN_IPL_030_0_ 3 7 1 1 1 7 -1 2 0 21 + 337 RN_IPL_030_1_ 3 6 1 1 1 6 -1 2 0 21 + 327 RN_IPL_030_2_ 3 8 1 1 1 8 -1 2 0 21 + 324 SM_AMIGA_D_2_ 3 -1 1 1 1 -1 -1 2 0 20 + 323 SM_AMIGA_D_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 322 SM_AMIGA_D_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 301 CLK_CNT_1_ 3 -1 6 1 6 -1 -1 2 0 21 + 306 cpu_est_d_2_ 3 -1 6 1 3 -1 -1 1 0 21 + 305 cpu_est_d_1_ 3 -1 7 1 3 -1 -1 1 0 20 + 303 inst_CLK_000_DD 3 -1 7 1 6 -1 -1 1 0 20 + 300 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 1 0 21 + 295 cpu_est_d_3_ 3 -1 7 1 3 -1 -1 1 0 20 + 294 cpu_est_d_0_ 3 -1 7 1 3 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 7 0 1 3 4 5 6 7 60 -1 + 85 RST 1 -1 -1 7 0 1 3 4 5 6 7 85 -1 + 81 AS_030 1 -1 -1 4 3 4 6 7 81 -1 + 10 CLK_000 1 -1 -1 4 0 1 5 6 10 -1 + 70 RW 1 -1 -1 3 3 4 6 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 13 CPU_SPACE 1 -1 -1 2 3 7 13 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 3 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +100 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 324 7 1 3 80 -1 3 0 21 + 29 DTACK 5 -1 3 1 0 29 -1 1 0 21 + 30 LDS_000 5 328 3 0 30 -1 13 0 21 + 9 CLK_EXP 0 1 0 9 -1 13 1 21 + 31 UDS_000 5 327 3 0 31 -1 11 0 21 + 65 E 5 332 6 0 65 -1 3 0 21 + 34 VMA 5 333 3 0 34 -1 3 0 21 + 28 BG_000 5 329 3 0 28 -1 3 0 21 + 82 BGACK_030 5 330 7 0 82 -1 2 0 21 + 77 FPU_CS 5 331 7 0 77 -1 2 0 21 + 32 AS_000 5 326 3 0 32 -1 2 0 21 + 8 IPL_030_2_ 5 322 1 0 8 -1 2 0 21 + 7 IPL_030_0_ 5 325 1 0 7 -1 2 0 21 + 6 IPL_030_1_ 5 323 1 0 6 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 20 + 301 inst_CLK_000_D 3 -1 6 6 0 2 3 5 6 7 -1 -1 1 0 21 + 298 inst_VPA_SYNC 3 -1 2 5 0 2 3 5 6 -1 -1 2 0 21 + 314 SM_AMIGA_0_ 3 -1 5 4 1 5 6 7 -1 -1 4 0 21 + 312 SM_AMIGA_3_ 3 -1 0 4 0 1 2 6 -1 -1 3 0 21 + 326 RN_AS_000 3 32 3 4 3 5 6 7 32 -1 2 0 21 + 293 cpu_est_1_ 3 -1 6 3 2 5 6 -1 -1 4 0 21 + 332 RN_E 3 65 6 3 2 5 6 65 -1 3 0 21 + 315 SM_AMIGA_2_ 3 -1 6 3 1 5 6 -1 -1 3 0 20 + 307 cpu_est_2_ 3 -1 6 3 2 5 6 -1 -1 3 1 21 + 306 cpu_est_0_ 3 -1 6 3 2 5 6 -1 -1 3 0 21 + 331 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 320 inst_DTACK_SYNC 3 -1 0 3 0 5 6 -1 -1 2 0 21 + 311 SM_AMIGA_4_ 3 -1 3 3 0 1 3 -1 -1 2 0 21 + 316 SM_AMIGA_1_ 3 -1 5 2 1 5 -1 -1 4 0 21 + 296 inst_AS_030_000_SYNC 3 -1 7 2 3 7 -1 -1 4 0 21 + 308 SM_AMIGA_6_ 3 -1 3 2 1 3 -1 -1 3 0 21 + 303 inst_CLK_OUT_PRE 3 -1 6 2 6 7 -1 -1 3 0 21 + 330 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 313 SM_AMIGA_5_ 3 -1 3 2 1 3 -1 -1 2 0 21 + 309 SM_AMIGA_7_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 310 inst_RISING_CLK_AMIGA 3 -1 6 2 1 7 -1 -1 1 0 21 + 297 inst_VPA_D 3 -1 7 2 0 2 -1 -1 1 0 20 + 328 RN_LDS_000 3 30 3 1 3 30 -1 13 0 21 + 327 RN_UDS_000 3 31 3 1 3 31 -1 11 0 21 + 333 RN_VMA 3 34 3 1 3 34 -1 3 0 21 + 329 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 324 RN_DSACK_1_ 3 80 7 1 7 80 -1 3 0 21 + 321 un1_UDS_000_INT_0_sqmuxa_i 3 -1 3 1 3 -1 -1 3 0 21 + 325 RN_IPL_030_0_ 3 7 1 1 1 7 -1 2 0 21 + 323 RN_IPL_030_1_ 3 6 1 1 1 6 -1 2 0 21 + 322 RN_IPL_030_2_ 3 8 1 1 1 8 -1 2 0 21 + 319 SM_AMIGA_D_2_ 3 -1 1 1 1 -1 -1 2 0 20 + 318 SM_AMIGA_D_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 317 SM_AMIGA_D_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 300 CLK_CNT_1_ 3 -1 6 1 6 -1 -1 2 0 21 + 305 cpu_est_d_2_ 3 -1 6 1 3 -1 -1 1 0 21 + 304 cpu_est_d_1_ 3 -1 6 1 3 -1 -1 1 0 21 + 302 inst_CLK_000_DD 3 -1 7 1 6 -1 -1 1 0 20 + 299 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 1 0 21 + 295 cpu_est_d_3_ 3 -1 6 1 3 -1 -1 1 0 21 + 294 cpu_est_d_0_ 3 -1 6 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 6 0 1 2 5 6 7 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 2 3 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 13 CPU_SPACE 1 -1 -1 2 3 7 13 -1 + 10 CLK_000 1 -1 -1 2 5 6 10 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 7 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +101 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 324 7 1 3 80 -1 4 0 21 + 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 13 1 21 + 31 UDS_000 5 327 3 0 31 -1 11 0 21 + 30 LDS_000 5 329 3 0 30 -1 4 0 21 + 65 E 5 333 6 0 65 -1 3 0 21 + 34 VMA 5 334 3 0 34 -1 3 0 21 + 28 BG_000 5 330 3 0 28 -1 3 0 21 + 82 BGACK_030 5 331 7 0 82 -1 2 0 21 + 77 FPU_CS 5 332 7 0 77 -1 2 0 21 + 32 AS_000 5 325 3 0 32 -1 2 0 21 + 8 IPL_030_2_ 5 323 1 0 8 -1 2 0 21 + 7 IPL_030_0_ 5 328 1 0 7 -1 2 0 21 + 6 IPL_030_1_ 5 326 1 0 6 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 20 + 301 inst_CLK_000_D 3 -1 3 5 0 3 5 6 7 -1 -1 1 0 20 + 310 SM_AMIGA_1_ 3 -1 5 4 0 1 5 7 -1 -1 4 0 21 + 298 inst_VPA_SYNC 3 -1 6 4 0 3 5 6 -1 -1 2 0 20 + 311 SM_AMIGA_0_ 3 -1 0 3 0 1 7 -1 -1 4 0 21 + 296 inst_AS_030_000_SYNC 3 -1 7 3 3 6 7 -1 -1 4 0 21 + 293 cpu_est_1_ 3 -1 6 3 0 5 6 -1 -1 4 0 21 + 333 RN_E 3 65 6 3 0 5 6 65 -1 3 0 21 + 316 SM_AMIGA_2_ 3 -1 6 3 1 5 6 -1 -1 3 0 20 + 308 SM_AMIGA_6_ 3 -1 3 3 1 3 6 -1 -1 3 0 21 + 307 cpu_est_2_ 3 -1 6 3 0 5 6 -1 -1 3 1 21 + 306 cpu_est_0_ 3 -1 6 3 0 5 6 -1 -1 3 0 21 + 332 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 325 RN_AS_000 3 32 3 3 0 3 7 32 -1 2 0 21 + 320 inst_DTACK_SYNC 3 -1 6 3 0 5 6 -1 -1 2 0 20 + 315 SM_AMIGA_5_ 3 -1 6 3 1 3 6 -1 -1 2 0 20 + 313 SM_AMIGA_4_ 3 -1 3 3 1 3 6 -1 -1 2 0 21 + 329 RN_LDS_000 3 30 3 2 3 6 30 -1 4 0 21 + 321 un1_UDS_000_INT_0_sqmuxa_i 3 -1 6 2 3 6 -1 -1 3 0 21 + 314 SM_AMIGA_3_ 3 -1 6 2 1 6 -1 -1 3 0 20 + 303 inst_CLK_OUT_PRE 3 -1 7 2 6 7 -1 -1 3 0 20 + 331 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 309 SM_AMIGA_7_ 3 -1 7 2 3 7 -1 -1 2 0 21 + 312 inst_RISING_CLK_AMIGA 3 -1 3 2 1 7 -1 -1 1 0 20 + 327 RN_UDS_000 3 31 3 1 3 31 -1 11 0 21 + 322 LDS_000_0 3 -1 6 1 3 -1 -1 10 0 21 + 324 RN_DSACK_1_ 3 80 7 1 7 80 -1 4 0 21 + 334 RN_VMA 3 34 3 1 3 34 -1 3 0 21 + 330 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 328 RN_IPL_030_0_ 3 7 1 1 1 7 -1 2 0 21 + 326 RN_IPL_030_1_ 3 6 1 1 1 6 -1 2 0 21 + 323 RN_IPL_030_2_ 3 8 1 1 1 8 -1 2 0 21 + 319 SM_AMIGA_D_2_ 3 -1 1 1 1 -1 -1 2 0 20 + 318 SM_AMIGA_D_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 317 SM_AMIGA_D_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 300 CLK_CNT_1_ 3 -1 7 1 7 -1 -1 2 0 20 + 305 cpu_est_d_2_ 3 -1 6 1 3 -1 -1 1 0 21 + 304 cpu_est_d_1_ 3 -1 6 1 3 -1 -1 1 0 21 + 302 inst_CLK_000_DD 3 -1 3 1 6 -1 -1 1 0 20 + 299 CLK_CNT_0_ 3 -1 7 1 7 -1 -1 1 0 20 + 297 inst_VPA_D 3 -1 0 1 6 -1 -1 1 0 20 + 295 cpu_est_d_3_ 3 -1 6 1 3 -1 -1 1 0 21 + 294 cpu_est_d_0_ 3 -1 6 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 6 0 1 3 5 6 7 60 -1 + 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1 + 81 AS_030 1 -1 -1 3 3 6 7 81 -1 + 70 RW 1 -1 -1 3 3 4 6 70 -1 + 10 CLK_000 1 -1 -1 3 0 3 5 10 -1 + 97 DS_030 1 -1 -1 2 3 6 97 -1 + 68 A_0_ 1 -1 -1 2 3 6 68 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 13 CPU_SPACE 1 -1 -1 2 3 7 13 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 6 78 -1 + 69 SIZE_0_ 1 -1 -1 1 6 69 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +104 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 327 7 1 3 80 -1 4 0 21 + 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 + 30 LDS_000 5 330 3 0 30 -1 13 0 21 + 9 CLK_EXP 0 1 0 9 -1 13 1 21 + 31 UDS_000 5 329 3 0 31 -1 11 0 21 + 65 E 5 335 6 0 65 -1 3 0 21 + 34 VMA 5 337 3 0 34 -1 3 0 21 + 28 BG_000 5 331 3 0 28 -1 3 0 21 + 82 BGACK_030 5 332 7 0 82 -1 2 0 21 + 77 FPU_CS 5 333 7 0 77 -1 2 0 21 + 32 AS_000 5 328 3 0 32 -1 2 0 21 + 8 IPL_030_2_ 5 326 1 0 8 -1 2 0 21 + 7 IPL_030_0_ 5 336 1 0 7 -1 2 0 21 + 6 IPL_030_1_ 5 334 1 0 6 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 20 + 301 inst_CLK_000_D 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 20 + 319 SM_AMIGA_0_ 3 -1 5 4 0 1 5 7 -1 -1 4 0 21 + 310 SM_AMIGA_1_ 3 -1 6 4 1 5 6 7 -1 -1 4 0 20 + 328 RN_AS_000 3 32 3 4 0 3 5 7 32 -1 2 0 21 + 316 CLK_000_CNT_0_ 3 -1 6 4 0 2 5 6 -1 -1 2 0 21 + 298 inst_VPA_SYNC 3 -1 6 4 0 3 5 6 -1 -1 2 0 20 + 317 CLK_000_CNT_1_ 3 -1 5 3 0 2 5 -1 -1 4 0 20 + 314 SM_AMIGA_3_ 3 -1 0 3 0 1 6 -1 -1 3 0 21 + 333 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 324 inst_DTACK_SYNC 3 -1 6 3 0 5 6 -1 -1 2 0 20 + 313 SM_AMIGA_4_ 3 -1 3 3 0 1 3 -1 -1 2 0 21 + 318 CLK_000_CNT_2_ 3 -1 0 2 0 2 -1 -1 5 0 20 + 311 CLK_000_CNT_3_ 3 -1 2 2 2 7 -1 -1 4 0 21 + 296 inst_AS_030_000_SYNC 3 -1 7 2 3 7 -1 -1 4 0 21 + 293 cpu_est_1_ 3 -1 6 2 5 6 -1 -1 4 0 21 + 335 RN_E 3 65 6 2 5 6 65 -1 3 0 21 + 320 SM_AMIGA_2_ 3 -1 6 2 1 6 -1 -1 3 0 20 + 308 SM_AMIGA_6_ 3 -1 3 2 1 3 -1 -1 3 0 21 + 307 cpu_est_2_ 3 -1 6 2 5 6 -1 -1 3 1 21 + 306 cpu_est_0_ 3 -1 6 2 5 6 -1 -1 3 0 21 + 303 inst_CLK_OUT_PRE 3 -1 7 2 6 7 -1 -1 3 0 20 + 332 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 315 SM_AMIGA_5_ 3 -1 3 2 1 3 -1 -1 2 0 21 + 309 SM_AMIGA_7_ 3 -1 0 2 0 3 -1 -1 2 0 21 + 300 CLK_CNT_1_ 3 -1 7 2 6 7 -1 -1 2 0 20 + 312 inst_RISING_CLK_AMIGA 3 -1 7 2 1 7 -1 -1 1 0 20 + 299 CLK_CNT_0_ 3 -1 6 2 6 7 -1 -1 1 0 21 + 330 RN_LDS_000 3 30 3 1 3 30 -1 13 0 21 + 329 RN_UDS_000 3 31 3 1 3 31 -1 11 0 21 + 327 RN_DSACK_1_ 3 80 7 1 7 80 -1 4 0 21 + 337 RN_VMA 3 34 3 1 3 34 -1 3 0 21 + 331 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 325 un1_UDS_000_INT_0_sqmuxa_i 3 -1 3 1 3 -1 -1 3 0 21 + 336 RN_IPL_030_0_ 3 7 1 1 1 7 -1 2 0 21 + 334 RN_IPL_030_1_ 3 6 1 1 1 6 -1 2 0 21 + 326 RN_IPL_030_2_ 3 8 1 1 1 8 -1 2 0 21 + 323 SM_AMIGA_D_2_ 3 -1 1 1 1 -1 -1 2 0 20 + 322 SM_AMIGA_D_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 321 SM_AMIGA_D_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 305 cpu_est_d_2_ 3 -1 6 1 3 -1 -1 1 0 21 + 304 cpu_est_d_1_ 3 -1 6 1 3 -1 -1 1 0 21 + 302 inst_CLK_000_DD 3 -1 7 1 6 -1 -1 1 0 20 + 297 inst_VPA_D 3 -1 6 1 6 -1 -1 1 0 21 + 295 cpu_est_d_3_ 3 -1 6 1 3 -1 -1 1 0 21 + 294 cpu_est_d_0_ 3 -1 6 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 6 0 1 2 5 6 7 60 -1 + 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1 + 10 CLK_000 1 -1 -1 5 0 2 5 6 7 10 -1 + 81 AS_030 1 -1 -1 3 3 6 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 13 CPU_SPACE 1 -1 -1 2 3 7 13 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +105 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 328 7 1 3 80 -1 5 0 21 + 29 DTACK 5 -1 3 1 0 29 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 13 1 21 + 31 UDS_000 5 330 3 0 31 -1 11 0 21 + 30 LDS_000 5 331 3 0 30 -1 11 0 21 + 65 E 5 335 6 0 65 -1 3 0 21 + 34 VMA 5 338 3 0 34 -1 3 0 21 + 28 BG_000 5 332 3 0 28 -1 3 0 21 + 82 BGACK_030 5 333 7 0 82 -1 2 0 21 + 77 FPU_CS 5 334 7 0 77 -1 2 0 21 + 32 AS_000 5 329 3 0 32 -1 2 0 21 + 8 IPL_030_2_ 5 327 1 0 8 -1 2 0 21 + 7 IPL_030_0_ 5 337 1 0 7 -1 2 0 21 + 6 IPL_030_1_ 5 336 1 0 6 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 20 + 302 inst_CLK_000_D 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 20 + 313 SM_AMIGA_3_ 3 -1 5 5 0 1 2 5 6 -1 -1 3 0 21 + 299 inst_VPA_SYNC 3 -1 2 5 2 3 5 6 7 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 0 4 0 5 6 7 -1 -1 2 0 21 + 321 SM_AMIGA_1_ 3 -1 6 3 1 6 7 -1 -1 4 0 20 + 319 SM_AMIGA_0_ 3 -1 7 3 1 3 7 -1 -1 4 0 21 + 293 cpu_est_1_ 3 -1 6 3 2 6 7 -1 -1 4 0 21 + 335 RN_E 3 65 6 3 2 6 7 65 -1 3 0 21 + 308 cpu_est_2_ 3 -1 6 3 2 6 7 -1 -1 3 1 21 + 307 cpu_est_0_ 3 -1 6 3 2 6 7 -1 -1 3 0 21 + 334 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 312 SM_AMIGA_4_ 3 -1 3 3 1 3 5 -1 -1 2 0 21 + 318 CLK_000_CNT_3_ 3 -1 6 2 6 7 -1 -1 4 0 21 + 296 inst_AS_030_000_SYNC 3 -1 7 2 3 7 -1 -1 4 0 21 + 320 SM_AMIGA_2_ 3 -1 6 2 1 6 -1 -1 3 0 20 + 309 SM_AMIGA_6_ 3 -1 3 2 1 3 -1 -1 3 0 21 + 304 inst_CLK_OUT_PRE 3 -1 6 2 6 7 -1 -1 3 0 21 + 333 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 329 RN_AS_000 3 32 3 2 3 7 32 -1 2 0 21 + 314 SM_AMIGA_5_ 3 -1 3 2 1 3 -1 -1 2 0 21 + 311 inst_RISING_CLK_AMIGA 3 -1 6 2 1 7 -1 -1 1 0 21 + 298 inst_VPA_D 3 -1 0 2 0 2 -1 -1 1 0 20 + 331 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21 + 330 RN_UDS_000 3 31 3 1 3 31 -1 11 0 21 + 328 RN_DSACK_1_ 3 80 7 1 7 80 -1 5 0 21 + 317 CLK_000_CNT_2_ 3 -1 6 1 6 -1 -1 5 0 21 + 316 CLK_000_CNT_1_ 3 -1 6 1 6 -1 -1 4 0 21 + 338 RN_VMA 3 34 3 1 3 34 -1 3 0 21 + 332 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 326 LDS_000_INT_1_sqmuxa 3 -1 3 1 3 -1 -1 3 0 21 + 337 RN_IPL_030_0_ 3 7 1 1 1 7 -1 2 0 21 + 336 RN_IPL_030_1_ 3 6 1 1 1 6 -1 2 0 21 + 327 RN_IPL_030_2_ 3 8 1 1 1 8 -1 2 0 21 + 324 SM_AMIGA_D_2_ 3 -1 1 1 1 -1 -1 2 0 20 + 323 SM_AMIGA_D_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 322 SM_AMIGA_D_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 315 CLK_000_CNT_0_ 3 -1 6 1 6 -1 -1 2 0 21 + 310 SM_AMIGA_7_ 3 -1 3 1 3 -1 -1 2 0 21 + 301 CLK_CNT_1_ 3 -1 6 1 6 -1 -1 2 0 21 + 325 UDS_000_INT_0_sqmuxa 3 -1 3 1 3 -1 -1 1 0 21 + 306 cpu_est_d_2_ 3 -1 7 1 3 -1 -1 1 0 20 + 305 cpu_est_d_1_ 3 -1 7 1 3 -1 -1 1 0 20 + 303 inst_CLK_000_DD 3 -1 3 1 6 -1 -1 1 0 20 + 300 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 1 0 21 + 295 cpu_est_d_3_ 3 -1 6 1 3 -1 -1 1 0 21 + 294 cpu_est_d_0_ 3 -1 7 1 3 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 7 0 1 2 3 5 6 7 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 2 3 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 13 CPU_SPACE 1 -1 -1 2 3 7 13 -1 + 10 CLK_000 1 -1 -1 2 6 7 10 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +101 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 324 7 1 3 80 -1 5 0 21 + 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 + 30 LDS_000 5 327 3 0 30 -1 13 0 21 + 9 CLK_EXP 0 1 0 9 -1 13 1 21 + 31 UDS_000 5 326 3 0 31 -1 11 0 21 + 65 E 5 333 6 0 65 -1 3 0 21 + 34 VMA 5 334 3 0 34 -1 3 0 21 + 28 BG_000 5 328 3 0 28 -1 3 0 21 + 82 BGACK_030 5 330 7 0 82 -1 2 0 21 + 77 FPU_CS 5 332 7 0 77 -1 2 0 21 + 32 AS_000 5 325 3 0 32 -1 2 0 21 + 8 IPL_030_2_ 5 323 1 0 8 -1 2 0 21 + 7 IPL_030_0_ 5 331 1 0 7 -1 2 0 21 + 6 IPL_030_1_ 5 329 1 0 6 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D 3 -1 1 5 0 1 3 6 7 -1 -1 1 0 20 + 318 SM_AMIGA_1_ 3 -1 6 4 0 1 6 7 -1 -1 4 0 20 + 325 RN_AS_000 3 32 3 4 0 1 3 7 32 -1 2 0 21 + 299 inst_VPA_SYNC 3 -1 6 4 0 3 6 7 -1 -1 2 0 20 + 316 SM_AMIGA_0_ 3 -1 0 3 0 1 7 -1 -1 4 0 21 + 293 cpu_est_1_ 3 -1 6 3 0 6 7 -1 -1 4 0 21 + 333 RN_E 3 65 6 3 0 6 7 65 -1 3 0 21 + 306 cpu_est_2_ 3 -1 6 3 0 6 7 -1 -1 3 1 21 + 305 cpu_est_0_ 3 -1 6 3 0 6 7 -1 -1 3 0 21 + 332 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 311 SM_AMIGA_4_ 3 -1 3 3 1 3 6 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 6 3 0 6 7 -1 -1 2 0 20 + 315 CLK_000_CNT_1_ 3 -1 6 2 6 7 -1 -1 4 0 21 + 296 inst_AS_030_000_SYNC 3 -1 7 2 3 7 -1 -1 4 0 21 + 317 SM_AMIGA_2_ 3 -1 6 2 1 6 -1 -1 3 0 20 + 312 SM_AMIGA_3_ 3 -1 6 2 1 6 -1 -1 3 0 20 + 308 SM_AMIGA_6_ 3 -1 3 2 1 3 -1 -1 3 0 21 + 330 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 314 CLK_000_CNT_0_ 3 -1 6 2 6 7 -1 -1 2 0 21 + 313 SM_AMIGA_5_ 3 -1 3 2 1 3 -1 -1 2 0 21 + 309 SM_AMIGA_7_ 3 -1 1 2 1 3 -1 -1 2 0 21 + 302 inst_CLK_OUT_PRE 3 -1 6 2 6 7 -1 -1 2 0 21 + 310 inst_RISING_CLK_AMIGA 3 -1 6 2 1 7 -1 -1 1 0 21 + 327 RN_LDS_000 3 30 3 1 3 30 -1 13 0 21 + 326 RN_UDS_000 3 31 3 1 3 31 -1 11 0 21 + 324 RN_DSACK_1_ 3 80 7 1 7 80 -1 5 0 21 + 334 RN_VMA 3 34 3 1 3 34 -1 3 0 21 + 328 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 322 un1_UDS_000_INT_0_sqmuxa_i 3 -1 3 1 3 -1 -1 3 0 21 + 331 RN_IPL_030_0_ 3 7 1 1 1 7 -1 2 0 21 + 329 RN_IPL_030_1_ 3 6 1 1 1 6 -1 2 0 21 + 323 RN_IPL_030_2_ 3 8 1 1 1 8 -1 2 0 21 + 321 SM_AMIGA_D_2_ 3 -1 1 1 1 -1 -1 2 0 20 + 320 SM_AMIGA_D_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 319 SM_AMIGA_D_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 307 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 1 0 21 + 304 cpu_est_d_2_ 3 -1 7 1 3 -1 -1 1 0 20 + 303 cpu_est_d_1_ 3 -1 7 1 3 -1 -1 1 0 20 + 301 inst_CLK_000_DD 3 -1 3 1 6 -1 -1 1 0 20 + 298 inst_VPA_D 3 -1 6 1 6 -1 -1 1 0 21 + 295 cpu_est_d_3_ 3 -1 7 1 3 -1 -1 1 0 20 + 294 cpu_est_d_0_ 3 -1 7 1 3 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 5 0 1 3 6 7 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 3 3 6 7 81 -1 + 10 CLK_000 1 -1 -1 3 0 1 6 10 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 13 CPU_SPACE 1 -1 -1 2 3 7 13 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +102 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 325 7 1 3 80 -1 5 0 21 + 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 13 1 21 + 31 UDS_000 5 327 3 0 31 -1 11 0 21 + 65 E 5 334 6 0 65 -1 3 0 21 + 34 VMA 5 335 3 0 34 -1 3 0 21 + 30 LDS_000 5 328 3 0 30 -1 3 0 21 + 28 BG_000 5 329 3 0 28 -1 3 0 21 + 82 BGACK_030 5 330 7 0 82 -1 2 0 21 + 77 FPU_CS 5 333 7 0 77 -1 2 0 21 + 32 AS_000 5 326 3 0 32 -1 2 0 21 + 8 IPL_030_2_ 5 324 1 0 8 -1 2 0 21 + 7 IPL_030_0_ 5 332 1 0 7 -1 2 0 21 + 6 IPL_030_1_ 5 331 1 0 6 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 20 + 299 inst_VPA_SYNC 3 -1 6 4 0 3 6 7 -1 -1 2 0 20 + 300 inst_CLK_000_D 3 -1 7 4 0 3 6 7 -1 -1 1 0 20 + 319 SM_AMIGA_1_ 3 -1 6 3 1 6 7 -1 -1 4 0 20 + 317 SM_AMIGA_0_ 3 -1 7 3 1 6 7 -1 -1 4 0 21 + 312 SM_AMIGA_3_ 3 -1 0 3 0 1 6 -1 -1 3 0 21 + 333 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 326 RN_AS_000 3 32 3 3 3 6 7 32 -1 2 0 21 + 311 SM_AMIGA_4_ 3 -1 3 3 0 1 3 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 6 3 0 6 7 -1 -1 2 0 20 + 316 CLK_000_CNT_2_ 3 -1 6 2 6 7 -1 -1 5 0 21 + 296 inst_AS_030_000_SYNC 3 -1 7 2 3 7 -1 -1 4 0 21 + 293 cpu_est_1_ 3 -1 6 2 6 7 -1 -1 4 0 21 + 334 RN_E 3 65 6 2 6 7 65 -1 3 0 21 + 318 SM_AMIGA_2_ 3 -1 6 2 1 6 -1 -1 3 0 20 + 308 SM_AMIGA_6_ 3 -1 3 2 1 3 -1 -1 3 0 21 + 306 cpu_est_2_ 3 -1 6 2 6 7 -1 -1 3 1 21 + 305 cpu_est_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 330 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 313 SM_AMIGA_5_ 3 -1 3 2 1 3 -1 -1 2 0 21 + 309 SM_AMIGA_7_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 302 inst_CLK_OUT_PRE 3 -1 6 2 6 7 -1 -1 2 0 21 + 310 inst_RISING_CLK_AMIGA 3 -1 3 2 1 7 -1 -1 1 0 20 + 307 CLK_CNT_0_ 3 -1 3 2 3 6 -1 -1 1 0 20 + 327 RN_UDS_000 3 31 3 1 3 31 -1 11 0 21 + 325 RN_DSACK_1_ 3 80 7 1 7 80 -1 5 0 21 + 323 un1_UDS_000_INT_0_sqmuxa_2_0 3 -1 3 1 3 -1 -1 4 0 21 + 315 CLK_000_CNT_1_ 3 -1 6 1 6 -1 -1 4 0 21 + 335 RN_VMA 3 34 3 1 3 34 -1 3 0 21 + 329 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 328 RN_LDS_000 3 30 3 1 3 30 -1 3 0 21 + 332 RN_IPL_030_0_ 3 7 1 1 1 7 -1 2 0 21 + 331 RN_IPL_030_1_ 3 6 1 1 1 6 -1 2 0 21 + 324 RN_IPL_030_2_ 3 8 1 1 1 8 -1 2 0 21 + 322 SM_AMIGA_D_2_ 3 -1 1 1 1 -1 -1 2 0 20 + 321 SM_AMIGA_D_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 320 SM_AMIGA_D_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 314 CLK_000_CNT_0_ 3 -1 6 1 6 -1 -1 2 0 21 + 304 cpu_est_d_2_ 3 -1 7 1 3 -1 -1 1 0 20 + 303 cpu_est_d_1_ 3 -1 7 1 3 -1 -1 1 0 20 + 301 inst_CLK_000_DD 3 -1 3 1 6 -1 -1 1 0 20 + 298 inst_VPA_D 3 -1 6 1 6 -1 -1 1 0 21 + 295 cpu_est_d_3_ 3 -1 6 1 3 -1 -1 1 0 21 + 294 cpu_est_d_0_ 3 -1 7 1 3 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 5 0 1 3 6 7 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 3 3 6 7 81 -1 + 10 CLK_000 1 -1 -1 3 3 6 7 10 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 13 CPU_SPACE 1 -1 -1 2 3 7 13 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +99 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 324 7 1 3 80 -1 5 0 21 + 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 + 30 LDS_000 5 327 3 0 30 -1 13 0 21 + 9 CLK_EXP 0 1 0 9 -1 13 1 21 + 31 UDS_000 5 326 3 0 31 -1 11 0 21 + 65 E 5 331 6 0 65 -1 3 0 21 + 34 VMA 5 332 3 0 34 -1 3 0 21 + 28 BG_000 5 328 3 0 28 -1 3 0 21 + 82 BGACK_030 5 329 7 0 82 -1 2 0 21 + 77 FPU_CS 5 330 7 0 77 -1 2 0 21 + 32 AS_000 5 325 3 0 32 -1 2 0 21 + 8 IPL_030_2_ 5 321 1 0 8 -1 2 0 21 + 7 IPL_030_0_ 5 323 1 0 7 -1 2 0 21 + 6 IPL_030_1_ 5 322 1 0 6 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 20 + 299 inst_VPA_SYNC 3 -1 6 4 0 3 6 7 -1 -1 2 0 20 + 300 inst_CLK_000_D 3 -1 6 4 0 3 6 7 -1 -1 1 0 21 + 316 SM_AMIGA_1_ 3 -1 6 3 1 6 7 -1 -1 4 0 20 + 314 SM_AMIGA_0_ 3 -1 6 3 1 6 7 -1 -1 4 0 20 + 312 SM_AMIGA_3_ 3 -1 0 3 0 1 6 -1 -1 3 0 21 + 330 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 325 RN_AS_000 3 32 3 3 3 6 7 32 -1 2 0 21 + 311 SM_AMIGA_4_ 3 -1 3 3 0 1 3 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 6 3 0 6 7 -1 -1 2 0 20 + 296 inst_AS_030_000_SYNC 3 -1 7 2 3 7 -1 -1 4 0 21 + 293 cpu_est_1_ 3 -1 6 2 6 7 -1 -1 4 0 21 + 331 RN_E 3 65 6 2 6 7 65 -1 3 0 21 + 315 SM_AMIGA_2_ 3 -1 6 2 1 6 -1 -1 3 0 20 + 308 SM_AMIGA_6_ 3 -1 3 2 1 3 -1 -1 3 0 21 + 306 cpu_est_2_ 3 -1 6 2 6 7 -1 -1 3 1 21 + 305 cpu_est_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 329 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 313 SM_AMIGA_5_ 3 -1 3 2 1 3 -1 -1 2 0 21 + 309 SM_AMIGA_7_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 302 inst_CLK_OUT_PRE 3 -1 7 2 6 7 -1 -1 2 0 20 + 310 inst_RISING_CLK_AMIGA 3 -1 6 2 1 7 -1 -1 1 0 21 + 327 RN_LDS_000 3 30 3 1 3 30 -1 13 0 21 + 326 RN_UDS_000 3 31 3 1 3 31 -1 11 0 21 + 324 RN_DSACK_1_ 3 80 7 1 7 80 -1 5 0 21 + 332 RN_VMA 3 34 3 1 3 34 -1 3 0 21 + 328 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 320 un1_UDS_000_INT_0_sqmuxa_i 3 -1 3 1 3 -1 -1 3 0 21 + 323 RN_IPL_030_0_ 3 7 1 1 1 7 -1 2 0 21 + 322 RN_IPL_030_1_ 3 6 1 1 1 6 -1 2 0 21 + 321 RN_IPL_030_2_ 3 8 1 1 1 8 -1 2 0 21 + 319 SM_AMIGA_D_2_ 3 -1 1 1 1 -1 -1 2 0 20 + 318 SM_AMIGA_D_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 317 SM_AMIGA_D_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 307 CLK_CNT_0_ 3 -1 7 1 7 -1 -1 1 0 20 + 304 cpu_est_d_2_ 3 -1 7 1 3 -1 -1 1 0 20 + 303 cpu_est_d_1_ 3 -1 7 1 3 -1 -1 1 0 20 + 301 inst_CLK_000_DD 3 -1 3 1 6 -1 -1 1 0 20 + 298 inst_VPA_D 3 -1 6 1 6 -1 -1 1 0 21 + 295 cpu_est_d_3_ 3 -1 7 1 3 -1 -1 1 0 20 + 294 cpu_est_d_0_ 3 -1 7 1 3 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 5 0 1 3 6 7 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 3 3 6 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 13 CPU_SPACE 1 -1 -1 2 3 7 13 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 6 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +99 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 324 7 1 3 80 -1 4 0 21 + 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 13 1 21 + 31 UDS_000 5 326 3 0 31 -1 11 0 21 + 65 E 5 331 6 0 65 -1 3 0 21 + 30 LDS_000 5 327 3 0 30 -1 3 0 21 + 28 BG_000 5 328 3 0 28 -1 3 0 21 + 82 BGACK_030 5 329 7 0 82 -1 2 0 21 + 77 FPU_CS 5 330 7 0 77 -1 2 0 21 + 34 VMA 5 332 3 0 34 -1 2 0 21 + 32 AS_000 5 325 3 0 32 -1 2 0 21 + 8 IPL_030_2_ 5 321 1 0 8 -1 2 0 21 + 7 IPL_030_0_ 5 323 1 0 7 -1 2 0 21 + 6 IPL_030_1_ 5 322 1 0 6 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 20 + 316 SM_AMIGA_2_ 3 -1 6 3 1 6 7 -1 -1 3 0 20 + 311 SM_AMIGA_0_ 3 -1 7 3 1 6 7 -1 -1 3 0 21 + 330 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 325 RN_AS_000 3 32 3 3 3 6 7 32 -1 2 0 21 + 313 SM_AMIGA_4_ 3 -1 3 3 1 3 6 -1 -1 2 0 21 + 301 inst_CLK_000_D 3 -1 7 3 3 6 7 -1 -1 1 0 20 + 297 inst_AS_030_000_SYNC 3 -1 7 2 3 7 -1 -1 4 0 21 + 294 cpu_est_1_ 3 -1 6 2 3 6 -1 -1 4 0 21 + 331 RN_E 3 65 6 2 3 6 65 -1 3 0 21 + 315 SM_AMIGA_3_ 3 -1 6 2 1 6 -1 -1 3 0 20 + 308 SM_AMIGA_6_ 3 -1 3 2 1 3 -1 -1 3 0 21 + 306 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21 + 293 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 3 0 21 + 332 RN_VMA 3 34 3 2 3 6 34 -1 2 0 21 + 329 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 314 SM_AMIGA_5_ 3 -1 3 2 1 3 -1 -1 2 0 21 + 310 SM_AMIGA_1_ 3 -1 7 2 1 7 -1 -1 2 0 21 + 309 SM_AMIGA_7_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 303 inst_CLK_OUT_PRE 3 -1 6 2 6 7 -1 -1 2 0 21 + 312 inst_RISING_CLK_AMIGA 3 -1 7 2 1 7 -1 -1 1 0 20 + 307 CLK_CNT_0_ 3 -1 0 2 0 6 -1 -1 1 0 21 + 299 inst_VPA_D 3 -1 6 2 3 6 -1 -1 1 0 21 + 326 RN_UDS_000 3 31 3 1 3 31 -1 11 0 21 + 324 RN_DSACK_1_ 3 80 7 1 7 80 -1 4 0 21 + 320 un1_UDS_000_INT_0_sqmuxa_3_i 3 -1 3 1 3 -1 -1 4 0 21 + 328 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 327 RN_LDS_000 3 30 3 1 3 30 -1 3 0 21 + 323 RN_IPL_030_0_ 3 7 1 1 1 7 -1 2 0 21 + 322 RN_IPL_030_1_ 3 6 1 1 1 6 -1 2 0 21 + 321 RN_IPL_030_2_ 3 8 1 1 1 8 -1 2 0 21 + 319 SM_AMIGA_D_2_ 3 -1 1 1 1 -1 -1 2 0 20 + 318 SM_AMIGA_D_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 317 SM_AMIGA_D_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 300 inst_VPA_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 298 inst_DTACK_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 305 cpu_est_d_2_ 3 -1 6 1 3 -1 -1 1 0 21 + 304 cpu_est_d_1_ 3 -1 6 1 3 -1 -1 1 0 21 + 302 inst_CLK_000_DD 3 -1 7 1 6 -1 -1 1 0 20 + 296 cpu_est_d_3_ 3 -1 6 1 3 -1 -1 1 0 21 + 295 cpu_est_d_0_ 3 -1 6 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 4 0 1 6 7 60 -1 + 85 RST 1 -1 -1 4 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 3 3 6 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 13 CPU_SPACE 1 -1 -1 2 3 7 13 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 7 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +99 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 324 7 1 3 80 -1 4 0 21 + 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 13 1 21 + 31 UDS_000 5 326 3 0 31 -1 11 0 21 + 65 E 5 331 6 0 65 -1 3 0 21 + 30 LDS_000 5 327 3 0 30 -1 3 0 21 + 28 BG_000 5 328 3 0 28 -1 3 0 21 + 82 BGACK_030 5 329 7 0 82 -1 2 0 21 + 77 FPU_CS 5 330 7 0 77 -1 2 0 21 + 34 VMA 5 332 3 0 34 -1 2 0 21 + 32 AS_000 5 325 3 0 32 -1 2 0 21 + 8 IPL_030_2_ 5 321 1 0 8 -1 2 0 21 + 7 IPL_030_0_ 5 323 1 0 7 -1 2 0 21 + 6 IPL_030_1_ 5 322 1 0 6 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 20 + 316 SM_AMIGA_2_ 3 -1 6 3 1 6 7 -1 -1 3 0 20 + 315 SM_AMIGA_0_ 3 -1 7 3 1 6 7 -1 -1 3 0 21 + 330 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 325 RN_AS_000 3 32 3 3 3 6 7 32 -1 2 0 21 + 311 SM_AMIGA_4_ 3 -1 3 3 1 3 6 -1 -1 2 0 21 + 301 inst_CLK_000_D 3 -1 7 3 3 6 7 -1 -1 1 0 20 + 297 inst_AS_030_000_SYNC 3 -1 7 2 3 7 -1 -1 4 0 21 + 294 cpu_est_1_ 3 -1 6 2 3 6 -1 -1 4 0 21 + 331 RN_E 3 65 6 2 3 6 65 -1 3 0 21 + 313 SM_AMIGA_3_ 3 -1 6 2 1 6 -1 -1 3 0 20 + 308 SM_AMIGA_6_ 3 -1 3 2 1 3 -1 -1 3 0 21 + 306 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21 + 293 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 3 0 21 + 332 RN_VMA 3 34 3 2 3 6 34 -1 2 0 21 + 329 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 314 SM_AMIGA_1_ 3 -1 7 2 1 7 -1 -1 2 0 21 + 312 SM_AMIGA_5_ 3 -1 3 2 1 3 -1 -1 2 0 21 + 309 SM_AMIGA_7_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 303 inst_CLK_OUT_PRE 3 -1 6 2 6 7 -1 -1 2 0 21 + 310 inst_RISING_CLK_AMIGA 3 -1 7 2 1 7 -1 -1 1 0 20 + 307 CLK_CNT_0_ 3 -1 0 2 0 6 -1 -1 1 0 21 + 299 inst_VPA_D 3 -1 6 2 3 6 -1 -1 1 0 21 + 326 RN_UDS_000 3 31 3 1 3 31 -1 11 0 21 + 324 RN_DSACK_1_ 3 80 7 1 7 80 -1 4 0 21 + 320 un1_UDS_000_INT_0_sqmuxa_3_0 3 -1 3 1 3 -1 -1 4 0 21 + 328 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 327 RN_LDS_000 3 30 3 1 3 30 -1 3 0 21 + 323 RN_IPL_030_0_ 3 7 1 1 1 7 -1 2 0 21 + 322 RN_IPL_030_1_ 3 6 1 1 1 6 -1 2 0 21 + 321 RN_IPL_030_2_ 3 8 1 1 1 8 -1 2 0 21 + 319 SM_AMIGA_D_2_ 3 -1 1 1 1 -1 -1 2 0 20 + 318 SM_AMIGA_D_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 317 SM_AMIGA_D_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 300 inst_VPA_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 298 inst_DTACK_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 305 cpu_est_d_2_ 3 -1 6 1 3 -1 -1 1 0 21 + 304 cpu_est_d_1_ 3 -1 6 1 3 -1 -1 1 0 21 + 302 inst_CLK_000_DD 3 -1 7 1 6 -1 -1 1 0 20 + 296 cpu_est_d_3_ 3 -1 6 1 3 -1 -1 1 0 21 + 295 cpu_est_d_0_ 3 -1 6 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 4 0 1 6 7 60 -1 + 85 RST 1 -1 -1 4 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 3 3 6 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 13 CPU_SPACE 1 -1 -1 2 3 7 13 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 7 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +99 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 324 7 1 3 80 -1 4 0 21 + 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 13 1 21 + 31 UDS_000 5 326 3 0 31 -1 11 0 21 + 65 E 5 331 6 0 65 -1 3 0 21 + 30 LDS_000 5 327 3 0 30 -1 3 0 21 + 28 BG_000 5 328 3 0 28 -1 3 0 21 + 82 BGACK_030 5 329 7 0 82 -1 2 0 21 + 77 FPU_CS 5 330 7 0 77 -1 2 0 21 + 34 VMA 5 332 3 0 34 -1 2 0 21 + 32 AS_000 5 325 3 0 32 -1 2 0 21 + 8 IPL_030_2_ 5 322 1 0 8 -1 2 0 21 + 7 IPL_030_0_ 5 323 1 0 7 -1 2 0 21 + 6 IPL_030_1_ 5 321 1 0 6 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 20 + 316 SM_AMIGA_2_ 3 -1 6 3 1 6 7 -1 -1 3 0 20 + 315 SM_AMIGA_0_ 3 -1 7 3 1 6 7 -1 -1 3 0 21 + 330 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 325 RN_AS_000 3 32 3 3 3 6 7 32 -1 2 0 21 + 311 SM_AMIGA_4_ 3 -1 3 3 1 3 6 -1 -1 2 0 21 + 303 inst_CLK_OUT_PRE 3 -1 0 3 0 6 7 -1 -1 2 0 21 + 301 inst_CLK_000_D 3 -1 7 3 3 6 7 -1 -1 1 0 20 + 314 SM_AMIGA_1_ 3 -1 7 2 1 7 -1 -1 4 0 21 + 297 inst_AS_030_000_SYNC 3 -1 7 2 3 7 -1 -1 4 0 21 + 294 cpu_est_1_ 3 -1 6 2 3 6 -1 -1 4 0 21 + 331 RN_E 3 65 6 2 3 6 65 -1 3 0 21 + 313 SM_AMIGA_3_ 3 -1 6 2 1 6 -1 -1 3 0 20 + 308 SM_AMIGA_6_ 3 -1 3 2 1 3 -1 -1 3 0 21 + 306 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21 + 293 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 3 0 21 + 332 RN_VMA 3 34 3 2 3 6 34 -1 2 0 21 + 329 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 312 SM_AMIGA_5_ 3 -1 3 2 1 3 -1 -1 2 0 21 + 309 SM_AMIGA_7_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 310 inst_RISING_CLK_AMIGA 3 -1 7 2 1 7 -1 -1 1 0 20 + 307 CLK_CNT_0_ 3 -1 6 2 0 6 -1 -1 1 0 21 + 299 inst_VPA_D 3 -1 6 2 3 6 -1 -1 1 0 21 + 326 RN_UDS_000 3 31 3 1 3 31 -1 11 0 21 + 324 RN_DSACK_1_ 3 80 7 1 7 80 -1 4 0 21 + 320 un1_UDS_000_INT_0_sqmuxa_3_i 3 -1 3 1 3 -1 -1 4 0 21 + 328 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 327 RN_LDS_000 3 30 3 1 3 30 -1 3 0 21 + 323 RN_IPL_030_0_ 3 7 1 1 1 7 -1 2 0 21 + 322 RN_IPL_030_2_ 3 8 1 1 1 8 -1 2 0 21 + 321 RN_IPL_030_1_ 3 6 1 1 1 6 -1 2 0 21 + 319 SM_AMIGA_D_2_ 3 -1 1 1 1 -1 -1 2 0 20 + 318 SM_AMIGA_D_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 317 SM_AMIGA_D_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 300 inst_VPA_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 298 inst_DTACK_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 305 cpu_est_d_2_ 3 -1 6 1 3 -1 -1 1 0 21 + 304 cpu_est_d_1_ 3 -1 6 1 3 -1 -1 1 0 21 + 302 inst_CLK_000_DD 3 -1 7 1 6 -1 -1 1 0 20 + 296 cpu_est_d_3_ 3 -1 6 1 3 -1 -1 1 0 21 + 295 cpu_est_d_0_ 3 -1 6 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 4 0 1 6 7 60 -1 + 85 RST 1 -1 -1 4 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 3 3 6 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 13 CPU_SPACE 1 -1 -1 2 3 7 13 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 7 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +99 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 324 7 1 3 80 -1 4 0 21 + 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 + 30 LDS_000 5 327 3 0 30 -1 13 0 21 + 9 CLK_EXP 0 1 0 9 -1 13 1 21 + 31 UDS_000 5 326 3 0 31 -1 11 0 21 + 65 E 5 331 6 0 65 -1 3 0 21 + 28 BG_000 5 328 3 0 28 -1 3 0 21 + 82 BGACK_030 5 329 7 0 82 -1 2 0 21 + 77 FPU_CS 5 330 7 0 77 -1 2 0 21 + 34 VMA 5 332 3 0 34 -1 2 0 21 + 32 AS_000 5 325 3 0 32 -1 2 0 21 + 8 IPL_030_2_ 5 323 1 0 8 -1 2 0 21 + 7 IPL_030_0_ 5 322 1 0 7 -1 2 0 21 + 6 IPL_030_1_ 5 321 1 0 6 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 20 + 316 SM_AMIGA_2_ 3 -1 6 3 1 6 7 -1 -1 3 0 20 + 315 SM_AMIGA_0_ 3 -1 7 3 1 6 7 -1 -1 3 0 21 + 330 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 325 RN_AS_000 3 32 3 3 3 6 7 32 -1 2 0 21 + 312 SM_AMIGA_4_ 3 -1 3 3 1 3 6 -1 -1 2 0 21 + 301 inst_CLK_000_D 3 -1 7 3 3 6 7 -1 -1 1 0 20 + 297 inst_AS_030_000_SYNC 3 -1 7 2 3 7 -1 -1 4 0 21 + 294 cpu_est_1_ 3 -1 6 2 3 6 -1 -1 4 0 21 + 331 RN_E 3 65 6 2 3 6 65 -1 3 0 21 + 314 SM_AMIGA_3_ 3 -1 6 2 1 6 -1 -1 3 0 20 + 308 SM_AMIGA_6_ 3 -1 3 2 1 3 -1 -1 3 0 21 + 306 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21 + 293 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 3 0 21 + 332 RN_VMA 3 34 3 2 3 6 34 -1 2 0 21 + 329 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 313 SM_AMIGA_5_ 3 -1 3 2 1 3 -1 -1 2 0 21 + 311 SM_AMIGA_1_ 3 -1 7 2 1 7 -1 -1 2 0 21 + 309 SM_AMIGA_7_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 303 inst_CLK_OUT_PRE 3 -1 6 2 6 7 -1 -1 2 0 21 + 310 inst_RISING_CLK_AMIGA 3 -1 7 2 1 7 -1 -1 1 0 20 + 307 CLK_CNT_0_ 3 -1 0 2 0 6 -1 -1 1 0 21 + 299 inst_VPA_D 3 -1 6 2 3 6 -1 -1 1 0 21 + 327 RN_LDS_000 3 30 3 1 3 30 -1 13 0 21 + 326 RN_UDS_000 3 31 3 1 3 31 -1 11 0 21 + 324 RN_DSACK_1_ 3 80 7 1 7 80 -1 4 0 21 + 328 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 320 un1_UDS_000_INT_0_sqmuxa_1_i 3 -1 3 1 3 -1 -1 3 0 21 + 323 RN_IPL_030_2_ 3 8 1 1 1 8 -1 2 0 21 + 322 RN_IPL_030_0_ 3 7 1 1 1 7 -1 2 0 21 + 321 RN_IPL_030_1_ 3 6 1 1 1 6 -1 2 0 21 + 319 SM_AMIGA_D_2_ 3 -1 1 1 1 -1 -1 2 0 20 + 318 SM_AMIGA_D_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 317 SM_AMIGA_D_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 300 inst_VPA_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 298 inst_DTACK_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 305 cpu_est_d_2_ 3 -1 6 1 3 -1 -1 1 0 21 + 304 cpu_est_d_1_ 3 -1 6 1 3 -1 -1 1 0 21 + 302 inst_CLK_000_DD 3 -1 7 1 6 -1 -1 1 0 20 + 296 cpu_est_d_3_ 3 -1 6 1 3 -1 -1 1 0 21 + 295 cpu_est_d_0_ 3 -1 6 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 4 0 1 6 7 60 -1 + 85 RST 1 -1 -1 4 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 3 3 6 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 13 CPU_SPACE 1 -1 -1 2 3 7 13 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 7 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +99 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 322 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 0 29 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 13 1 21 + 31 UDS_000 5 324 3 0 31 -1 11 0 21 + 65 E 5 329 6 0 65 -1 3 0 21 + 30 LDS_000 5 325 3 0 30 -1 3 0 21 + 28 BG_000 5 326 3 0 28 -1 3 0 21 + 82 BGACK_030 5 327 7 0 82 -1 2 0 21 + 77 FPU_CS 5 328 7 0 77 -1 2 0 21 + 34 VMA 5 330 3 0 34 -1 2 0 21 + 32 AS_000 5 323 3 0 32 -1 2 0 21 + 8 IPL_030_2_ 5 321 1 0 8 -1 2 0 21 + 7 IPL_030_0_ 5 332 1 0 7 -1 2 0 21 + 6 IPL_030_1_ 5 331 1 0 6 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 20 + 301 inst_CLK_000_D 3 -1 7 5 0 3 5 6 7 -1 -1 1 0 20 + 314 SM_AMIGA_3_ 3 -1 6 4 0 1 5 6 -1 -1 3 0 20 + 294 cpu_est_1_ 3 -1 6 3 3 5 6 -1 -1 4 0 21 + 329 RN_E 3 65 6 3 3 5 6 65 -1 3 0 21 + 316 SM_AMIGA_0_ 3 -1 6 3 0 1 6 -1 -1 3 0 20 + 306 cpu_est_2_ 3 -1 6 3 3 5 6 -1 -1 3 1 21 + 293 cpu_est_0_ 3 -1 6 3 3 5 6 -1 -1 3 0 21 + 328 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 323 RN_AS_000 3 32 3 3 0 3 6 32 -1 2 0 21 + 312 SM_AMIGA_4_ 3 -1 3 3 1 3 6 -1 -1 2 0 21 + 311 SM_AMIGA_1_ 3 -1 6 3 1 6 7 -1 -1 2 0 20 + 299 inst_VPA_D 3 -1 6 3 0 3 5 -1 -1 1 0 21 + 297 inst_AS_030_000_SYNC 3 -1 7 2 3 7 -1 -1 4 0 21 + 315 SM_AMIGA_2_ 3 -1 6 2 1 6 -1 -1 3 0 20 + 308 SM_AMIGA_6_ 3 -1 3 2 1 3 -1 -1 3 0 21 + 330 RN_VMA 3 34 3 2 3 5 34 -1 2 0 21 + 327 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 313 SM_AMIGA_5_ 3 -1 3 2 1 3 -1 -1 2 0 21 + 309 SM_AMIGA_7_ 3 -1 0 2 0 3 -1 -1 2 0 21 + 300 inst_VPA_SYNC 3 -1 5 2 5 6 -1 -1 2 0 21 + 298 inst_DTACK_SYNC 3 -1 0 2 0 6 -1 -1 2 0 21 + 310 inst_RISING_CLK_AMIGA 3 -1 7 2 1 7 -1 -1 1 0 20 + 324 RN_UDS_000 3 31 3 1 3 31 -1 11 0 21 + 320 un1_UDS_000_INT_0_sqmuxa_3_0 3 -1 3 1 3 -1 -1 4 0 21 + 326 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 325 RN_LDS_000 3 30 3 1 3 30 -1 3 0 21 + 332 RN_IPL_030_0_ 3 7 1 1 1 7 -1 2 0 21 + 331 RN_IPL_030_1_ 3 6 1 1 1 6 -1 2 0 21 + 322 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 321 RN_IPL_030_2_ 3 8 1 1 1 8 -1 2 0 21 + 319 SM_AMIGA_D_2_ 3 -1 1 1 1 -1 -1 2 0 20 + 318 SM_AMIGA_D_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 317 SM_AMIGA_D_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 303 inst_CLK_OUT_PRE 3 -1 6 1 6 -1 -1 2 0 21 + 307 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 1 0 21 + 305 cpu_est_d_2_ 3 -1 6 1 3 -1 -1 1 0 21 + 304 cpu_est_d_1_ 3 -1 6 1 3 -1 -1 1 0 21 + 302 inst_CLK_000_DD 3 -1 7 1 6 -1 -1 1 0 20 + 296 cpu_est_d_3_ 3 -1 6 1 3 -1 -1 1 0 21 + 295 cpu_est_d_0_ 3 -1 6 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 5 0 1 5 6 7 60 -1 + 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 3 5 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 13 CPU_SPACE 1 -1 -1 2 3 7 13 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 7 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +99 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 323 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 0 29 -1 1 0 21 + 30 LDS_000 5 326 3 0 30 -1 13 0 21 + 9 CLK_EXP 0 1 0 9 -1 13 1 21 + 31 UDS_000 5 325 3 0 31 -1 11 0 21 + 65 E 5 330 6 0 65 -1 3 0 21 + 28 BG_000 5 327 3 0 28 -1 3 0 21 + 82 BGACK_030 5 328 7 0 82 -1 2 0 21 + 77 FPU_CS 5 329 7 0 77 -1 2 0 21 + 34 VMA 5 331 3 0 34 -1 2 0 21 + 32 AS_000 5 324 3 0 32 -1 2 0 21 + 8 IPL_030_2_ 5 322 1 0 8 -1 2 0 21 + 7 IPL_030_0_ 5 321 1 0 7 -1 2 0 21 + 6 IPL_030_1_ 5 332 1 0 6 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 20 + 301 inst_CLK_000_D 3 -1 7 5 0 3 5 6 7 -1 -1 1 0 20 + 314 SM_AMIGA_3_ 3 -1 0 4 0 1 5 6 -1 -1 3 0 21 + 294 cpu_est_1_ 3 -1 6 3 3 5 6 -1 -1 4 0 21 + 330 RN_E 3 65 6 3 3 5 6 65 -1 3 0 21 + 311 SM_AMIGA_1_ 3 -1 6 3 1 6 7 -1 -1 3 0 20 + 306 cpu_est_2_ 3 -1 6 3 3 5 6 -1 -1 3 1 21 + 293 cpu_est_0_ 3 -1 6 3 3 5 6 -1 -1 3 0 21 + 329 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 312 SM_AMIGA_4_ 3 -1 3 3 0 1 3 -1 -1 2 0 21 + 300 inst_VPA_SYNC 3 -1 5 3 0 5 6 -1 -1 2 0 21 + 299 inst_VPA_D 3 -1 6 3 0 3 5 -1 -1 1 0 21 + 297 inst_AS_030_000_SYNC 3 -1 7 2 3 7 -1 -1 4 0 21 + 316 SM_AMIGA_0_ 3 -1 6 2 1 6 -1 -1 3 0 20 + 315 SM_AMIGA_2_ 3 -1 6 2 1 6 -1 -1 3 0 20 + 308 SM_AMIGA_6_ 3 -1 3 2 1 3 -1 -1 3 0 21 + 331 RN_VMA 3 34 3 2 3 5 34 -1 2 0 21 + 328 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 324 RN_AS_000 3 32 3 2 3 6 32 -1 2 0 21 + 313 SM_AMIGA_5_ 3 -1 3 2 1 3 -1 -1 2 0 21 + 309 SM_AMIGA_7_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 303 inst_CLK_OUT_PRE 3 -1 6 2 6 7 -1 -1 2 0 21 + 298 inst_DTACK_SYNC 3 -1 0 2 0 6 -1 -1 2 0 21 + 310 inst_RISING_CLK_AMIGA 3 -1 7 2 1 7 -1 -1 1 0 20 + 326 RN_LDS_000 3 30 3 1 3 30 -1 13 0 21 + 325 RN_UDS_000 3 31 3 1 3 31 -1 11 0 21 + 327 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 320 un1_UDS_000_INT_0_sqmuxa_1_i 3 -1 3 1 3 -1 -1 3 0 21 + 332 RN_IPL_030_1_ 3 6 1 1 1 6 -1 2 0 21 + 323 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 322 RN_IPL_030_2_ 3 8 1 1 1 8 -1 2 0 21 + 321 RN_IPL_030_0_ 3 7 1 1 1 7 -1 2 0 21 + 319 SM_AMIGA_D_2_ 3 -1 1 1 1 -1 -1 2 0 20 + 318 SM_AMIGA_D_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 317 SM_AMIGA_D_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 307 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 1 0 21 + 305 cpu_est_d_2_ 3 -1 6 1 3 -1 -1 1 0 21 + 304 cpu_est_d_1_ 3 -1 6 1 3 -1 -1 1 0 21 + 302 inst_CLK_000_DD 3 -1 7 1 6 -1 -1 1 0 20 + 296 cpu_est_d_3_ 3 -1 6 1 3 -1 -1 1 0 21 + 295 cpu_est_d_0_ 3 -1 6 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 5 0 1 5 6 7 60 -1 + 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 3 5 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 13 CPU_SPACE 1 -1 -1 2 3 7 13 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 7 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +99 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 31 UDS_000 0 3 0 31 -1 13 0 21 + 9 CLK_EXP 0 -1 0 9 -1 13 1 21 + 65 E 0 6 0 65 -1 3 0 21 + 30 LDS_000 0 3 0 30 -1 3 0 21 + 28 BG_000 0 3 0 28 -1 3 0 21 + 82 BGACK_030 0 7 0 82 -1 2 0 21 + 80 DSACK_1_ 5 322 7 0 80 -1 2 0 21 + 77 FPU_CS 0 7 0 77 -1 2 0 21 + 34 VMA 0 3 0 34 -1 2 0 21 + 32 AS_000 0 3 0 32 -1 2 0 21 + 8 IPL_030_2_ 0 1 0 8 -1 2 0 21 + 7 IPL_030_0_ 0 1 0 7 -1 2 0 21 + 6 IPL_030_1_ 0 1 0 6 -1 2 0 21 + 91 AVEC 0 -1 0 91 -1 1 0 21 + 79 DSACK_0_ 0 -1 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 -1 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 -1 0 47 -1 1 0 21 + 46 CIIN 0 -1 0 46 -1 1 0 21 + 40 BERR 0 -1 0 40 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 -1 0 33 -1 1 0 21 + 29 DTACK 0 -1 0 29 -1 1 0 21 + 21 AVEC_EXP 0 -1 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 -1 0 19 -1 1 0 21 + 2 RESET 0 -1 0 2 -1 1 0 21 + 301 inst_CLK_000_D 3 -1 -1 3 3 6 7 -1 -1 1 0 21 + 294 cpu_est_1_ 3 -1 -1 2 3 6 -1 -1 4 0 21 + 329 RN_E 3 65 6 2 3 6 65 -1 3 0 21 + 306 cpu_est_2_ 3 -1 -1 2 3 6 -1 -1 3 1 21 + 293 cpu_est_0_ 3 -1 -1 2 3 6 -1 -1 3 0 21 + 327 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 310 inst_RISING_CLK_AMIGA 3 -1 -1 2 1 7 -1 -1 1 0 21 + 302 inst_CLK_000_DD 3 -1 -1 2 3 6 -1 -1 1 0 21 + 324 RN_UDS_000 3 31 3 1 3 31 -1 13 0 21 + 297 inst_AS_030_000_SYNC 3 -1 -1 1 3 -1 -1 4 0 21 + 326 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 325 RN_LDS_000 3 30 3 1 3 30 -1 3 0 21 + 320 un1_UDS_000_INT_0_sqmuxa_3_0 3 -1 -1 1 3 -1 -1 3 1 21 + 311 SM_AMIGA_1_ 3 -1 -1 1 7 -1 -1 3 0 21 + 308 SM_AMIGA_6_ 3 -1 -1 1 3 -1 -1 3 0 21 + 332 RN_IPL_030_0_ 3 7 1 1 1 7 -1 2 0 21 + 331 RN_IPL_030_1_ 3 6 1 1 1 6 -1 2 0 21 + 330 RN_VMA 3 34 3 1 3 34 -1 2 0 21 + 328 RN_FPU_CS 3 77 7 1 7 77 -1 2 0 21 + 323 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 322 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 321 RN_IPL_030_2_ 3 8 1 1 1 8 -1 2 0 21 + 314 SM_AMIGA_5_ 3 -1 -1 1 3 -1 -1 2 0 21 + 312 SM_AMIGA_4_ 3 -1 -1 1 3 -1 -1 2 0 21 + 309 SM_AMIGA_7_ 3 -1 -1 1 3 -1 -1 2 0 21 + 303 inst_CLK_OUT_PRE 3 -1 -1 1 7 -1 -1 2 0 21 + 305 cpu_est_d_2_ 3 -1 -1 1 3 -1 -1 1 0 21 + 304 cpu_est_d_1_ 3 -1 -1 1 3 -1 -1 1 0 21 + 299 inst_VPA_D 3 -1 -1 1 3 -1 -1 1 0 21 + 296 cpu_est_d_3_ 3 -1 -1 1 3 -1 -1 1 0 21 + 295 cpu_est_d_0_ 3 -1 -1 1 3 -1 -1 1 0 21 + 316 SM_AMIGA_0_ 3 -1 -1 0 -1 -1 3 0 21 + 315 SM_AMIGA_2_ 3 -1 -1 0 -1 -1 3 0 21 + 313 SM_AMIGA_3_ 3 -1 -1 0 -1 -1 3 0 21 + 319 SM_AMIGA_D_2_ 3 -1 -1 0 -1 -1 2 0 21 + 318 SM_AMIGA_D_1_ 3 -1 -1 0 -1 -1 2 0 21 + 317 SM_AMIGA_D_0_ 3 -1 -1 0 -1 -1 2 0 21 + 300 inst_VPA_SYNC 3 -1 -1 0 -1 -1 2 0 21 + 298 inst_DTACK_SYNC 3 -1 -1 0 -1 -1 2 0 21 + 307 CLK_CNT_0_ 3 -1 -1 0 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 3 1 3 7 85 -1 + 81 AS_030 1 -1 -1 2 3 7 81 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 13 CPU_SPACE 1 -1 -1 2 3 7 13 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 70 RW 1 -1 -1 1 3 70 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 93 A_21_ 1 -1 -1 0 93 -1 + 92 A_20_ 1 -1 -1 0 92 -1 + 84 A_22_ 1 -1 -1 0 84 -1 + 83 A_23_ 1 -1 -1 0 83 -1 + 35 VPA 1 -1 -1 0 35 -1 + 18 A_24_ 1 -1 -1 0 18 -1 + 17 A_25_ 1 -1 -1 0 17 -1 + 16 A_26_ 1 -1 -1 0 16 -1 + 15 A_27_ 1 -1 -1 0 15 -1 + 14 A_28_ 1 -1 -1 0 14 -1 + 10 CLK_000 1 -1 -1 0 10 -1 + 5 A_29_ 1 -1 -1 0 5 -1 + 4 A_30_ 1 -1 -1 0 4 -1 + 3 A_31_ 1 -1 -1 0 3 -1 +98 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 321 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 0 29 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 13 1 21 + 30 LDS_000 5 324 3 0 30 -1 12 0 21 + 31 UDS_000 5 323 3 0 31 -1 8 0 21 + 65 E 5 328 6 0 65 -1 3 0 21 + 28 BG_000 5 325 3 0 28 -1 3 0 21 + 82 BGACK_030 5 326 7 0 82 -1 2 0 21 + 77 FPU_CS 5 327 7 0 77 -1 2 0 21 + 34 VMA 5 329 3 0 34 -1 2 0 21 + 32 AS_000 5 322 3 0 32 -1 2 0 21 + 8 IPL_030_2_ 5 320 1 0 8 -1 2 0 21 + 7 IPL_030_0_ 5 331 1 0 7 -1 2 0 21 + 6 IPL_030_1_ 5 330 1 0 6 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 20 + 301 inst_CLK_000_D 3 -1 7 5 0 3 5 6 7 -1 -1 1 0 20 + 313 SM_AMIGA_3_ 3 -1 6 4 0 1 5 6 -1 -1 3 0 20 + 294 cpu_est_1_ 3 -1 6 3 3 5 6 -1 -1 4 0 21 + 328 RN_E 3 65 6 3 3 5 6 65 -1 3 0 21 + 311 SM_AMIGA_1_ 3 -1 6 3 1 6 7 -1 -1 3 0 20 + 306 cpu_est_2_ 3 -1 6 3 3 5 6 -1 -1 3 1 21 + 293 cpu_est_0_ 3 -1 6 3 3 5 6 -1 -1 3 0 21 + 327 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 312 SM_AMIGA_4_ 3 -1 3 3 1 3 6 -1 -1 2 0 21 + 299 inst_VPA_D 3 -1 0 3 0 3 5 -1 -1 1 0 20 + 297 inst_AS_030_000_SYNC 3 -1 7 2 3 7 -1 -1 4 0 21 + 316 SM_AMIGA_0_ 3 -1 6 2 1 6 -1 -1 3 0 20 + 315 SM_AMIGA_2_ 3 -1 6 2 1 6 -1 -1 3 0 20 + 308 SM_AMIGA_6_ 3 -1 3 2 1 3 -1 -1 3 0 21 + 329 RN_VMA 3 34 3 2 3 5 34 -1 2 0 21 + 326 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 322 RN_AS_000 3 32 3 2 3 6 32 -1 2 0 21 + 314 SM_AMIGA_5_ 3 -1 3 2 1 3 -1 -1 2 0 21 + 309 SM_AMIGA_7_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 303 inst_CLK_OUT_PRE 3 -1 6 2 6 7 -1 -1 2 0 21 + 300 inst_VPA_SYNC 3 -1 5 2 5 6 -1 -1 2 0 21 + 298 inst_DTACK_SYNC 3 -1 0 2 0 6 -1 -1 2 0 21 + 310 inst_RISING_CLK_AMIGA 3 -1 7 2 1 7 -1 -1 1 0 20 + 302 inst_CLK_000_DD 3 -1 7 2 3 6 -1 -1 1 0 20 + 324 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 323 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 325 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 331 RN_IPL_030_0_ 3 7 1 1 1 7 -1 2 0 21 + 330 RN_IPL_030_1_ 3 6 1 1 1 6 -1 2 0 21 + 321 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 320 RN_IPL_030_2_ 3 8 1 1 1 8 -1 2 0 21 + 319 SM_AMIGA_D_2_ 3 -1 1 1 1 -1 -1 2 0 20 + 318 SM_AMIGA_D_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 317 SM_AMIGA_D_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 307 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 1 0 21 + 305 cpu_est_d_2_ 3 -1 6 1 3 -1 -1 1 0 21 + 304 cpu_est_d_1_ 3 -1 6 1 3 -1 -1 1 0 21 + 296 cpu_est_d_3_ 3 -1 6 1 3 -1 -1 1 0 21 + 295 cpu_est_d_0_ 3 -1 6 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 5 0 1 5 6 7 60 -1 + 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 3 5 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 13 CPU_SPACE 1 -1 -1 2 3 7 13 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 7 10 -1 5 A_29_ 1 -1 -1 1 4 5 -1 4 A_30_ 1 -1 -1 1 4 4 -1 3 A_31_ 1 -1 -1 1 4 3 -1 \ No newline at end of file diff --git a/Logic/68030_tk.plc b/Logic/68030_tk.plc index dd6b838..ee64943 100644 --- a/Logic/68030_tk.plc +++ b/Logic/68030_tk.plc @@ -8,29 +8,15 @@ ; Source file 68030_tk.tt4 ; FITTER-generated Placements. ; DEVICE mach447a -; DATE Thu May 15 19:20:57 2014 +; DATE Thu May 15 22:17:31 2014 -Pin 5 A_30_ -Pin 6 A_29_ +Pin 57 FC_0_ Pin 79 SIZE_1_ -Pin 15 A_28_ -Pin 16 A_27_ Pin 4 A_31_ -Pin 17 A_26_ -Pin 18 A_25_ -Pin 19 A_24_ -Pin 84 A_23_ Pin 68 IPL_2_ -Pin 85 A_22_ -Pin 94 A_21_ -Pin 93 A_20_ -Pin 97 A_19_ Pin 58 FC_1_ -Pin 95 A_18_ Pin 82 AS_030 -Pin 59 A_17_ -Pin 96 A_16_ Pin 98 DS_030 Pin 14 CPU_SPACE Pin 41 BERR Comb ; S6=1 S9=1 Pair 203 @@ -39,77 +25,90 @@ Pin 28 BGACK_000 Pin 64 CLK_030 Pin 11 CLK_000 Pin 61 CLK_OSZI +Pin 70 SIZE_0_ Pin 10 CLK_EXP Comb ; S6=1 S9=1 Pair 125 -Pin 69 A_0_ +Pin 5 A_30_ +Pin 6 A_29_ +Pin 15 A_28_ Pin 92 AVEC Comb ; S6=1 S9=1 Pair 107 +Pin 16 A_27_ Pin 22 AVEC_EXP Comb ; S6=1 S9=1 Pair 149 -Pin 56 IPL_1_ +Pin 17 A_26_ +Pin 18 A_25_ Pin 36 VPA +Pin 19 A_24_ +Pin 84 A_23_ +Pin 86 RST +Pin 85 A_22_ +Pin 94 A_21_ +Pin 71 RW +Pin 93 A_20_ +Pin 34 AMIGA_BUS_ENABLE Comb ; S6=1 S9=1 Pair 187 +Pin 97 A_19_ +Pin 48 AMIGA_BUS_DATA_DIR Comb ; S6=1 S9=1 Pair 197 +Pin 95 A_18_ +Pin 20 AMIGA_BUS_ENABLE_LOW Comb ; S6=1 S9=1 Pair 167 +Pin 59 A_17_ +Pin 47 CIIN Comb ; S6=1 S9=1 Pair 215 +Pin 96 A_16_ +Pin 69 A_0_ +Pin 56 IPL_1_ Pin 67 IPL_0_ Pin 80 DSACK_0_ Comb ; S6=1 S9=1 Pair 287 -Pin 86 RST -Pin 57 FC_0_ -Pin 71 RW -Pin 34 AMIGA_BUS_ENABLE Comb ; S6=1 S9=1 Pair 187 -Pin 48 AMIGA_BUS_DATA_DIR Comb ; S6=1 S9=1 Pair 197 -Pin 20 AMIGA_BUS_ENABLE_LOW Comb ; S6=1 S9=1 Pair 167 -Pin 47 CIIN Comb ; S6=1 S9=1 Pair 215 -Pin 70 SIZE_0_ Pin 9 IPL_030_2_ Reg ; S6=1 S9=1 Pair 131 Pin 81 DSACK_1_ Reg ; S6=1 S9=1 Pair 281 Pin 33 AS_000 Reg ; S6=1 S9=1 Pair 181 -Pin 32 UDS_000 Reg ; S6=1 S9=1 Pair 185 -Pin 31 LDS_000 Reg ; S6=1 S9=1 Pair 191 +Pin 32 UDS_000 Reg ; S6=1 S9=1 Pair 191 +Pin 31 LDS_000 Reg ; S6=1 S9=1 Pair 185 Pin 29 BG_000 Reg ; S6=1 S9=1 Pair 175 Pin 83 BGACK_030 Reg ; S6=1 S9=1 Pair 275 Pin 65 CLK_DIV_OUT Reg ; S6=1 S9=1 Pair 245 Pin 78 FPU_CS Reg ; S6=1 S9=1 Pair 269 Pin 30 DTACK Reg ; S6=1 S9=1 Pair 173 -Pin 7 IPL_030_1_ Reg ; S6=1 S9=1 Pair 143 -Pin 8 IPL_030_0_ Reg ; S6=1 S9=1 Pair 137 Pin 66 E Reg ; S6=1 S9=1 Pair 251 Pin 35 VMA Reg ; S6=1 S9=1 Pair 179 Pin 3 RESET Reg ; S6=1 S9=0 Pair 133 +Pin 7 IPL_030_1_ Reg ; S6=1 S9=1 Pair 143 +Pin 8 IPL_030_0_ Reg ; S6=1 S9=1 Pair 137 Node 131 RN_IPL_030_2_ Reg ; S6=1 S9=1 Node 281 RN_DSACK_1_ Reg ; S6=1 S9=1 Node 181 RN_AS_000 Reg ; S6=1 S9=1 -Node 185 RN_UDS_000 Reg ; S6=1 S9=1 -Node 191 RN_LDS_000 Reg ; S6=1 S9=1 +Node 191 RN_UDS_000 Reg ; S6=1 S9=1 +Node 185 RN_LDS_000 Reg ; S6=1 S9=1 Node 175 RN_BG_000 Reg ; S6=1 S9=1 Node 275 RN_BGACK_030 Reg ; S6=1 S9=1 Node 269 RN_FPU_CS Reg ; S6=1 S9=1 Node 173 RN_DTACK Reg ; S6=1 S9=1 -Node 143 RN_IPL_030_1_ Reg ; S6=1 S9=1 -Node 137 RN_IPL_030_0_ Reg ; S6=1 S9=1 Node 251 RN_E Reg ; S6=1 S9=1 Node 179 RN_VMA Reg ; S6=1 S9=1 -Node 250 cpu_est_1_ Reg ; S6=1 S9=1 -Node 271 inst_AS_030_000_SYNC Reg ; S6=1 S9=1 -Node 266 inst_DTACK_SYNC Reg ; S6=0 S9=0 -Node 134 inst_VPA_D Reg ; S6=1 S9=0 -Node 263 inst_VPA_SYNC Reg ; S6=0 S9=0 -Node 101 inst_CLK_000_D Reg ; S6=1 S9=1 -Node 194 inst_CLK_000_DD Reg ; S6=1 S9=0 +Node 143 RN_IPL_030_1_ Reg ; S6=1 S9=1 +Node 137 RN_IPL_030_0_ Reg ; S6=1 S9=1 +Node 253 cpu_est_0_ Reg ; S6=1 S9=1 +Node 248 cpu_est_1_ Reg ; S6=1 S9=1 +Node 268 cpu_est_d_0_ Reg ; S6=1 S9=1 +Node 262 cpu_est_d_3_ Reg ; S6=1 S9=1 +Node 277 inst_AS_030_000_SYNC Reg ; S6=1 S9=1 +Node 113 inst_DTACK_SYNC Reg ; S6=1 S9=1 +Node 101 inst_VPA_D Reg ; S6=1 S9=0 +Node 221 inst_VPA_SYNC Reg ; S6=1 S9=1 +Node 271 inst_CLK_000_D Reg ; S6=1 S9=0 +Node 289 inst_CLK_000_DD Reg ; S6=1 S9=0 Node 260 inst_CLK_OUT_PRE Reg ; S6=1 S9=1 -Node 262 cpu_est_0_ Reg ; S6=1 S9=1 -Node 256 cpu_est_2_ Reg ; S6=1 S9=1 -Node 268 CLK_CNT_0_ Reg ; S6=1 S9=1 +Node 256 cpu_est_d_1_ Reg ; S6=1 S9=1 +Node 250 cpu_est_d_2_ Reg ; S6=1 S9=1 +Node 247 cpu_est_2_ Reg ; S6=1 S9=1 +Node 266 CLK_CNT_0_ Reg ; S6=1 S9=1 Node 176 SM_AMIGA_6_ Reg ; S6=0 S9=1 Node 254 SM_AMIGA_7_ Reg ; S6=0 S9=0 Node 283 inst_RISING_CLK_AMIGA Reg ; S6=1 S9=0 +Node 263 SM_AMIGA_1_ Reg ; S6=1 S9=0 Node 193 SM_AMIGA_4_ Reg ; S6=0 S9=1 -Node 265 SM_AMIGA_3_ Reg ; S6=1 S9=0 +Node 257 SM_AMIGA_3_ Reg ; S6=1 S9=0 Node 182 SM_AMIGA_5_ Reg ; S6=0 S9=1 -Node 277 CLK_000_CNT_0_ Reg ; S6=1 S9=0 -Node 253 CLK_000_CNT_1_ Reg ; S6=1 S9=1 -Node 289 CLK_000_CNT_2_ Reg ; S6=1 S9=0 -Node 272 CLK_000_CNT_3_ Reg ; S6=1 S9=0 -Node 259 SM_AMIGA_2_ Reg ; S6=1 S9=0 -Node 247 SM_AMIGA_1_ Reg ; S6=1 S9=0 -Node 257 SM_AMIGA_0_ Reg ; S6=1 S9=0 -Node 145 SM_AMIGA_D_0_ Reg ; S6=1 S9=0 -Node 139 SM_AMIGA_D_1_ Reg ; S6=1 S9=0 -Node 248 SM_AMIGA_D_2_ Reg ; S6=1 S9=1 -Node 188 un1_UDS_000_INT_0_sqmuxa_2_0 Comb ; S6=1 S9=1 +Node 265 SM_AMIGA_2_ Reg ; S6=1 S9=0 +Node 259 SM_AMIGA_0_ Reg ; S6=1 S9=0 +Node 134 SM_AMIGA_D_0_ Reg ; S6=1 S9=0 +Node 145 SM_AMIGA_D_1_ Reg ; S6=1 S9=0 +Node 139 SM_AMIGA_D_2_ Reg ; S6=1 S9=0 ; Unused Pins & Nodes ; -> None Found. diff --git a/Logic/68030_tk.prd b/Logic/68030_tk.prd index 1a4470f..9ee789b 100644 --- a/Logic/68030_tk.prd +++ b/Logic/68030_tk.prd @@ -5,8 +5,8 @@ |--------------------------------------------| -Start: Thu May 15 19:20:57 2014 -End : Thu May 15 19:20:57 2014 $$$ Elapsed time: 00:00:00 +Start: Thu May 15 22:17:31 2014 +End : Thu May 15 22:17:31 2014 $$$ Elapsed time: 00:00:00 =========================================================================== Part [C:/Program Files (x86)/ispLever/ispcpld/dat/mach4a/mach447a] Design [68030_tk.tt4] @@ -21,16 +21,16 @@ Part [C:/Program Files (x86)/ispLever/ispcpld/dat/mach4a/mach447a] Design [68030 | | +- Signals to Place | | +----- Logic Array Inputs | | | +- Placed | | | +- Array Inputs Used _|____|____|____|_______________|____|_____________|___|________________ - 0 | 16 | 2 | 2 => 100% | 8 | 7 => 87% | 33 | 2 => 6% - 1 | 16 | 8 | 8 => 100% | 8 | 8 => 100% | 33 | 20 => 60% + 0 | 16 | 3 | 3 => 100% | 8 | 7 => 87% | 33 | 9 => 27% + 1 | 16 | 8 | 8 => 100% | 8 | 8 => 100% | 33 | 19 => 57% 2 | 16 | 2 | 2 => 100% | 8 | 8 => 100% | 33 | 1 => 3% - 3 | 16 | 12 | 12 => 100% | 8 | 8 => 100% | 33 | 26 => 78% + 3 | 16 | 10 | 10 => 100% | 8 | 8 => 100% | 33 | 33 => 100% 4 | 16 | 3 | 3 => 100% | 8 | 3 => 37% | 33 | 14 => 42% - 5 | 16 | 0 | 0 => n/a | 8 | 4 => 50% | 33 | 0 => 0% - 6 | 16 | 16 | 16 => 100% | 8 | 7 => 87% | 33 | 26 => 78% - 7 | 16 | 9 | 9 => 100% | 8 | 8 => 100% | 33 | 27 => 81% + 5 | 16 | 1 | 1 => 100% | 8 | 4 => 50% | 33 | 12 => 36% + 6 | 16 | 16 | 16 => 100% | 8 | 7 => 87% | 33 | 19 => 57% + 7 | 16 | 8 | 8 => 100% | 8 | 8 => 100% | 33 | 21 => 63% ---|----|----|------------|-------|------------|-----|------------------ - | Avg number of array inputs in used blocks : 16.57 => 50% + | Avg number of array inputs in used blocks : 16.00 => 48% * Input/Clock Signal count: 35 -> placed: 35 = 100% @@ -40,14 +40,14 @@ _|____|____|____|_______________|____|_____________|___|________________ I/O Pins : 64 53 => 82% Clock Only Pins : 0 0 => 0% Clock/Input Pins : 4 4 => 100% - Logic Blocks : 8 7 => 87% - Macrocells : 128 52 => 40% - PT Clusters : 128 45 => 35% - - Single PT Clusters : 128 16 => 12% + Logic Blocks : 8 8 => 100% + Macrocells : 128 51 => 39% + PT Clusters : 128 36 => 28% + - Single PT Clusters : 128 20 => 15% Input Registers : 0 * Routing Completion: 100% -* Attempts: Place [ 99] Route [ 0] +* Attempts: Place [ 170] Route [ 0] =========================================================================== Signal Fanout Table =========================================================================== @@ -62,7 +62,7 @@ ___|__|__|____|____________________________________________________________ 3| 2|OUT| 20|=> ....|....| AMIGA_BUS_ENABLE_LOW 4| 3| IO| 33|=> ....|....| AS_000 |=> Paired w/: RN_AS_000 - 5| 7|INP| 82|=> ...3|..67| AS_030 + 5| 7|INP| 82|=> 0..3|.5.7| AS_030 6| 0|OUT| 92|=> ....|....| AVEC 7| 2|OUT| 22|=> ....|....| AVEC_EXP 8| 6|INP| 69|=> ...3|....| A_0_ @@ -90,96 +90,95 @@ ___|__|__|____|____________________________________________________________ |=> Paired w/: RN_BG_000 29| 2|INP| 21|=> ...3|....| BG_030 30| 4|OUT| 47|=> ....|....| CIIN - 31| +|INP| 11|=> 0...|..67| CLK_000 - 32| 7|NOD| . |=> ....|..67| CLK_000_CNT_0_ - 33| 6|NOD| . |=> ....|..67| CLK_000_CNT_1_ - 34| 7|NOD| . |=> ....|...7| CLK_000_CNT_2_ - 35| 7|NOD| . |=> ....|...7| CLK_000_CNT_3_ - 36| +|INP| 64|=> ...3|...7| CLK_030 - 37| 6|NOD| . |=> ....|..6.| CLK_CNT_0_ - 38| 6|OUT| 65|=> ....|....| CLK_DIV_OUT - 39| 1|OUT| 10|=> ....|....| CLK_EXP - 40| +|Cin| 61|=> 01.3|..67| CLK_OSZI - 41| +|INP| 14|=> ...3|...7| CPU_SPACE - 42| 7|OUT| 80|=> ....|....| DSACK_0_ - 43| 7| IO| 81|=> ...3|....| DSACK_1_ + 31| +|INP| 11|=> ....|...7| CLK_000 + 32| +|INP| 64|=> ...3|...7| CLK_030 + 33| 6|NOD| . |=> ....|..6.| CLK_CNT_0_ + 34| 6|OUT| 65|=> ....|....| CLK_DIV_OUT + 35| 1|OUT| 10|=> ....|....| CLK_EXP + 36| +|Cin| 61|=> 01..|.567| CLK_OSZI + 37| +|INP| 14|=> ...3|...7| CPU_SPACE + 38| 7|OUT| 80|=> ....|....| DSACK_0_ + 39| 7| IO| 81|=> ...3|....| DSACK_1_ |=> Paired w/: RN_DSACK_1_ - 44| 0|INP| 98|=> ...3|....| DS_030 - 45| 3| IO| 30|=> ....|..6.| DTACK - 46| 6| IO| 66|=> ....|....| E + 40| 0|INP| 98|=> ...3|....| DS_030 + 41| 3| IO| 30|=> 0...|....| DTACK + 42| 6| IO| 66|=> ....|....| E |=> Paired w/: RN_E - 47| 5|INP| 57|=> ....|...7| FC_0_ - 48| 5|INP| 58|=> ....|...7| FC_1_ - 49| 7| IO| 78|=> ....|....| FPU_CS + 43| 5|INP| 57|=> ....|...7| FC_0_ + 44| 5|INP| 58|=> ....|...7| FC_1_ + 45| 7| IO| 78|=> ....|....| FPU_CS |=> Paired w/: RN_FPU_CS - 50| 1| IO| 8|=> ....|....| IPL_030_0_ + 46| 1| IO| 8|=> ....|....| IPL_030_0_ |=> Paired w/: RN_IPL_030_0_ - 51| 1| IO| 7|=> ....|....| IPL_030_1_ + 47| 1| IO| 7|=> ....|....| IPL_030_1_ |=> Paired w/: RN_IPL_030_1_ - 52| 1| IO| 9|=> ....|....| IPL_030_2_ + 48| 1| IO| 9|=> ....|....| IPL_030_2_ |=> Paired w/: RN_IPL_030_2_ - 53| 6|INP| 67|=> .1..|....| IPL_0_ - 54| 5|INP| 56|=> .1..|....| IPL_1_ - 55| 6|INP| 68|=> .1..|....| IPL_2_ - 56| 3| IO| 31|=> ....|....| LDS_000 + 49| 6|INP| 67|=> .1..|....| IPL_0_ + 50| 5|INP| 56|=> .1..|....| IPL_1_ + 51| 6|INP| 68|=> .1..|....| IPL_2_ + 52| 3| IO| 31|=> ....|....| LDS_000 |=> Paired w/: RN_LDS_000 - 57| 1|OUT| 3|=> ....|....| RESET - 58| 3|NOD| . |=> ...3|..6.| RN_AS_000 + 53| 1|OUT| 3|=> ....|....| RESET + 54| 3|NOD| . |=> ...3|..6.| RN_AS_000 |=> Paired w/: AS_000 - 59| 7|NOD| . |=> ...3|...7| RN_BGACK_030 + 55| 7|NOD| . |=> ...3|...7| RN_BGACK_030 |=> Paired w/: BGACK_030 - 60| 3|NOD| . |=> ...3|....| RN_BG_000 + 56| 3|NOD| . |=> ...3|....| RN_BG_000 |=> Paired w/: BG_000 - 61| 7|NOD| . |=> ....|...7| RN_DSACK_1_ + 57| 7|NOD| . |=> ....|...7| RN_DSACK_1_ |=> Paired w/: DSACK_1_ - 62| 6|NOD| . |=> ....|..6.| RN_E + 58| 6|NOD| . |=> ...3|.56.| RN_E |=> Paired w/: E - 63| 7|NOD| . |=> ..2.|4..7| RN_FPU_CS + 59| 7|NOD| . |=> ..2.|4..7| RN_FPU_CS |=> Paired w/: FPU_CS - 64| 1|NOD| . |=> .1..|....| RN_IPL_030_0_ + 60| 1|NOD| . |=> .1..|....| RN_IPL_030_0_ |=> Paired w/: IPL_030_0_ - 65| 1|NOD| . |=> .1..|....| RN_IPL_030_1_ + 61| 1|NOD| . |=> .1..|....| RN_IPL_030_1_ |=> Paired w/: IPL_030_1_ - 66| 1|NOD| . |=> .1..|....| RN_IPL_030_2_ + 62| 1|NOD| . |=> .1..|....| RN_IPL_030_2_ |=> Paired w/: IPL_030_2_ - 67| 3|NOD| . |=> ...3|....| RN_LDS_000 + 63| 3|NOD| . |=> ...3|....| RN_LDS_000 |=> Paired w/: LDS_000 - 68| 3|NOD| . |=> ...3|....| RN_UDS_000 + 64| 3|NOD| . |=> ...3|....| RN_UDS_000 |=> Paired w/: UDS_000 - 69| 3|NOD| . |=> ...3|....| RN_VMA + 65| 3|NOD| . |=> ...3|.5..| RN_VMA |=> Paired w/: VMA - 70| +|INP| 86|=> .1.3|..67| RST - 71| 6|INP| 71|=> ...3|4...| RW - 72| 6|INP| 70|=> ...3|....| SIZE_0_ - 73| 7|INP| 79|=> ...3|....| SIZE_1_ - 74| 6|NOD| . |=> .1..|..67| SM_AMIGA_0_ - 75| 6|NOD| . |=> .1..|..6.| SM_AMIGA_1_ - 76| 6|NOD| . |=> .1..|..6.| SM_AMIGA_2_ - 77| 6|NOD| . |=> .1..|..6.| SM_AMIGA_3_ - 78| 3|NOD| . |=> .1.3|..6.| SM_AMIGA_4_ - 79| 3|NOD| . |=> .1.3|....| SM_AMIGA_5_ - 80| 3|NOD| . |=> .1.3|....| SM_AMIGA_6_ - 81| 6|NOD| . |=> ...3|..6.| SM_AMIGA_7_ - 82| 1|NOD| . |=> .1..|....| SM_AMIGA_D_0_ - 83| 1|NOD| . |=> .1..|....| SM_AMIGA_D_1_ - 84| 6|NOD| . |=> .1..|..6.| SM_AMIGA_D_2_ - 85| 3| IO| 32|=> ....|....| UDS_000 + 66| +|INP| 86|=> 01.3|.567| RST + 67| 6|INP| 71|=> ...3|4...| RW + 68| 6|INP| 70|=> ...3|....| SIZE_0_ + 69| 7|INP| 79|=> ...3|....| SIZE_1_ + 70| 6|NOD| . |=> .1..|..6.| SM_AMIGA_0_ + 71| 6|NOD| . |=> .1..|..67| SM_AMIGA_1_ + 72| 6|NOD| . |=> .1..|..6.| SM_AMIGA_2_ + 73| 6|NOD| . |=> 01..|.56.| SM_AMIGA_3_ + 74| 3|NOD| . |=> .1.3|..6.| SM_AMIGA_4_ + 75| 3|NOD| . |=> .1.3|....| SM_AMIGA_5_ + 76| 3|NOD| . |=> .1.3|....| SM_AMIGA_6_ + 77| 6|NOD| . |=> ...3|..6.| SM_AMIGA_7_ + 78| 1|NOD| . |=> .1..|....| SM_AMIGA_D_0_ + 79| 1|NOD| . |=> .1..|....| SM_AMIGA_D_1_ + 80| 1|NOD| . |=> .1..|....| SM_AMIGA_D_2_ + 81| 3| IO| 32|=> ....|....| UDS_000 |=> Paired w/: RN_UDS_000 - 86| 3| IO| 35|=> ....|....| VMA + 82| 3| IO| 35|=> ....|....| VMA |=> Paired w/: RN_VMA - 87| +|INP| 36|=> .1..|....| VPA - 88| 6|NOD| . |=> ....|..6.| cpu_est_0_ - 89| 6|NOD| . |=> ....|..6.| cpu_est_1_ - 90| 6|NOD| . |=> ....|..6.| cpu_est_2_ + 83| +|INP| 36|=> 0...|....| VPA + 84| 6|NOD| . |=> ...3|.56.| cpu_est_0_ + 85| 6|NOD| . |=> ...3|.56.| cpu_est_1_ + 86| 6|NOD| . |=> ...3|.56.| cpu_est_2_ + 87| 6|NOD| . |=> ...3|....| cpu_est_d_0_ + 88| 6|NOD| . |=> ...3|....| cpu_est_d_1_ + 89| 6|NOD| . |=> ...3|....| cpu_est_d_2_ + 90| 6|NOD| . |=> ...3|....| cpu_est_d_3_ 91| 7|NOD| . |=> ...3|...7| inst_AS_030_000_SYNC - 92| 0|NOD| . |=> ...3|..67| inst_CLK_000_D - 93| 3|NOD| . |=> ....|..6.| inst_CLK_000_DD + 92| 7|NOD| . |=> 0..3|.567| inst_CLK_000_D + 93| 7|NOD| . |=> ...3|..6.| inst_CLK_000_DD 94| 6|NOD| . |=> ....|..67| inst_CLK_OUT_PRE - 95| 6|NOD| . |=> ....|..67| inst_DTACK_SYNC + 95| 0|NOD| . |=> 0...|..6.| inst_DTACK_SYNC 96| 7|NOD| . |=> .1..|...7| inst_RISING_CLK_AMIGA - 97| 1|NOD| . |=> ....|..6.| inst_VPA_D - 98| 6|NOD| . |=> ...3|..67| inst_VPA_SYNC - 99| 3|NOD| . |=> ...3|....| un1_UDS_000_INT_0_sqmuxa_2_0 + 97| 0|NOD| . |=> 0..3|.5..| inst_VPA_D + 98| 5|NOD| . |=> ....|.56.| inst_VPA_SYNC --------------------------------------------------------------------------- =========================================================================== < C:/Program Files (x86)/ispLever/ispcpld/dat/mach4a/mach447a Device Pin Assignments > @@ -299,7 +298,7 @@ ____|_____|_________|______________________________________________________ | Sig Type-+ | | | | | | | XOR to Mcell Assignment | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ - 0|inst_CLK_000_D|NOD| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig + 0| inst_VPA_D|NOD| | A | 1 | 2 free | 1 XOR to [ 0] for 1 PT sig 1| | ? | | S | | 4 free | 1 XOR free 2| | ? | | S | | 4 free | 1 XOR free 3| | ? | | S | | 4 free | 1 XOR free @@ -307,7 +306,7 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ 5| | ? | | S | | 4 free | 1 XOR free 6| | ? | | S | | 4 free | 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free - 8| | ? | | S | | 4 free | 1 XOR free + 8|inst_DTACK_SYNC|NOD| | S | 2 | 4 to [ 8]| 1 XOR free 9| | ? | | S | | 4 free | 1 XOR free 10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free @@ -326,16 +325,16 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0|inst_CLK_000_D|NOD| | S | 1 |=> can support up to [ 15] logic PT(s) - 1| | ? | | S | |=> can support up to [ 19] logic PT(s) + 0| inst_VPA_D|NOD| | A | 1 |=> can support up to [ 13] logic PT(s) + 1| | ? | | S | |=> can support up to [ 17] logic PT(s) 2| | ? | | S | |=> can support up to [ 19] logic PT(s) 3| | ? | | S | |=> can support up to [ 19] logic PT(s) 4| AVEC|OUT| | S | 1 |=> can support up to [ 20] logic PT(s) 5| | ? | | S | |=> can support up to [ 19] logic PT(s) - 6| | ? | | S | |=> can support up to [ 20] logic PT(s) - 7| | ? | | S | |=> can support up to [ 20] logic PT(s) - 8| | ? | | S | |=> can support up to [ 20] logic PT(s) - 9| | ? | | S | |=> can support up to [ 20] logic PT(s) + 6| | ? | | S | |=> can support up to [ 15] logic PT(s) + 7| | ? | | S | |=> can support up to [ 15] logic PT(s) + 8|inst_DTACK_SYNC|NOD| | S | 2 |=> can support up to [ 20] logic PT(s) + 9| | ? | | S | |=> can support up to [ 15] logic PT(s) 10| | ? | | S | |=> can support up to [ 20] logic PT(s) 11| | ? | | S | |=> can support up to [ 20] logic PT(s) 12| | ? | | S | |=> can support up to [ 20] logic PT(s) @@ -351,7 +350,7 @@ _|_________________|__|__|___|_____|_______________________________________ | Sig Type---+ | to | Block [ 0] IO Pin | Device Pin | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ - 0|inst_CLK_000_D|NOD| | => | 5 6 7 0 | 96 97 98 91 + 0| inst_VPA_D|NOD| | => | 5 6 7 0 | 96 97 98 91 1| | | | => | 5 6 7 0 | 96 97 98 91 2| | | | => | 6 7 0 1 | 97 98 91 92 3| | | | => | 6 7 0 1 | 97 98 91 92 @@ -359,7 +358,7 @@ _|_________________|__|_____|____________________|________________________ 5| | | | => | 7 0 1 2 | 98 91 92 93 6| | | | => | 0 1 2 3 | 91 92 93 94 7| | | | => | 0 1 2 3 | 91 92 93 94 - 8| | | | => | 1 2 3 4 | 92 93 94 95 + 8|inst_DTACK_SYNC|NOD| | => | 1 2 3 4 | 92 93 94 95 9| | | | => | 1 2 3 4 | 92 93 94 95 10| | | | => | 2 3 4 5 | 93 94 95 96 11| | | | => | 2 3 4 5 | 93 94 95 96 @@ -415,7 +414,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number ---|-------|----|---|---|----------|------|-|------------------------------ 0 [IOpin 0 | 91| -| | ] [RegIn 0 |102| -| | ] - [MCell 0 |101|NOD inst_CLK_000_D| |*] + [MCell 0 |101|NOD inst_VPA_D| |*] [MCell 1 |103| -| | ] 1 [IOpin 1 | 92|OUT AVEC|*| ] @@ -435,7 +434,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 4 [IOpin 4 | 95|INP A_18_|*|*] [RegIn 4 |114| -| | ] - [MCell 8 |113| -| | ] + [MCell 8 |113|NOD inst_DTACK_SYNC| |*] [MCell 9 |115| -| | ] 5 [IOpin 5 | 96|INP A_16_|*|*] @@ -459,22 +458,22 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| ... | ... +Mux00| Input Pin ( 86)| RST Mux01| ... | ... Mux02| ... | ... -Mux03| Input Pin ( 11)| CLK_000 +Mux03| Mcel 0 8 ( 113)| inst_DTACK_SYNC Mux04| Input Pin ( 61)| CLK_OSZI Mux05| ... | ... Mux06| ... | ... Mux07| ... | ... Mux08| ... | ... -Mux09| ... | ... -Mux10| ... | ... +Mux09| IOPin 7 3 ( 82)| AS_030 +Mux10| Input Pin ( 36)| VPA Mux11| ... | ... -Mux12| ... | ... -Mux13| ... | ... -Mux14| ... | ... -Mux15| ... | ... +Mux12| Mcel 7 1 ( 271)| inst_CLK_000_D +Mux13| Mcel 6 8 ( 257)| SM_AMIGA_3_ +Mux14| IOPin 3 5 ( 30)| DTACK +Mux15| Mcel 0 0 ( 101)| inst_VPA_D Mux16| ... | ... Mux17| ... | ... Mux18| ... | ... @@ -509,14 +508,14 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ 3| | ? | | S | | 4 free | 1 XOR free 4| IPL_030_2_| IO| | S | 2 | 4 to [ 4]| 1 XOR free 5| RESET|OUT| | A | 1 | 2 free | 1 XOR to [ 5] for 1 PT sig - 6| inst_VPA_D|NOD| | A | 1 | 2 free | 1 XOR to [ 6] for 1 PT sig + 6| SM_AMIGA_D_0_|NOD| | A | 2 | 2 to [ 6]| 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free 8| IPL_030_0_| IO| | S | 2 | 4 to [ 8]| 1 XOR free - 9| SM_AMIGA_D_1_|NOD| | A | 2 | 2 to [ 9]| 1 XOR free + 9| SM_AMIGA_D_2_|NOD| | A | 2 | 2 to [ 9]| 1 XOR free 10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free 12| IPL_030_1_| IO| | S | 2 | 4 to [12]| 1 XOR free -13| SM_AMIGA_D_0_|NOD| | A | 2 | 2 to [13]| 1 XOR free +13| SM_AMIGA_D_1_|NOD| | A | 2 | 2 to [13]| 1 XOR free 14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- @@ -534,16 +533,16 @@ _|_________________|__|__|___|_____|_______________________________________ 1| | ? | | S | |=> can support up to [ 5] logic PT(s) 2| | ? | | S | |=> can support up to [ 6] logic PT(s) 3| | ? | | S | |=> can support up to [ 7] logic PT(s) - 4| IPL_030_2_| IO| | S | 2 |=> can support up to [ 14] logic PT(s) - 5| RESET|OUT| | A | 1 |=> can support up to [ 10] logic PT(s) - 6| inst_VPA_D|NOD| | A | 1 |=> can support up to [ 10] logic PT(s) - 7| | ? | | S | |=> can support up to [ 7] logic PT(s) + 4| IPL_030_2_| IO| | S | 2 |=> can support up to [ 12] logic PT(s) + 5| RESET|OUT| | A | 1 |=> can support up to [ 8] logic PT(s) + 6| SM_AMIGA_D_0_|NOD| | A | 2 |=> can support up to [ 10] logic PT(s) + 7| | ? | | S | |=> can support up to [ 5] logic PT(s) 8| IPL_030_0_| IO| | S | 2 |=> can support up to [ 15] logic PT(s) - 9| SM_AMIGA_D_1_|NOD| | A | 2 |=> can support up to [ 13] logic PT(s) + 9| SM_AMIGA_D_2_|NOD| | A | 2 |=> can support up to [ 13] logic PT(s) 10| | ? | | S | |=> can support up to [ 10] logic PT(s) 11| | ? | | S | |=> can support up to [ 10] logic PT(s) 12| IPL_030_1_| IO| | S | 2 |=> can support up to [ 15] logic PT(s) -13| SM_AMIGA_D_0_|NOD| | A | 2 |=> can support up to [ 13] logic PT(s) +13| SM_AMIGA_D_1_|NOD| | A | 2 |=> can support up to [ 13] logic PT(s) 14| | ? | | S | |=> can support up to [ 10] logic PT(s) 15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- @@ -561,14 +560,14 @@ _|_________________|__|_____|____________________|________________________ 3| | | | => | 6 7 0 1 | 4 3 10 9 4| IPL_030_2_| IO| | => | 7 0 ( 1) 2 | 3 10 ( 9) 8 5| RESET|OUT| | => |( 7) 0 1 2 |( 3) 10 9 8 - 6| inst_VPA_D|NOD| | => | 0 1 2 3 | 10 9 8 7 + 6| SM_AMIGA_D_0_|NOD| | => | 0 1 2 3 | 10 9 8 7 7| | | | => | 0 1 2 3 | 10 9 8 7 8| IPL_030_0_| IO| | => | 1 ( 2) 3 4 | 9 ( 8) 7 6 - 9| SM_AMIGA_D_1_|NOD| | => | 1 2 3 4 | 9 8 7 6 + 9| SM_AMIGA_D_2_|NOD| | => | 1 2 3 4 | 9 8 7 6 10| | | | => | 2 3 4 5 | 8 7 6 5 11| | | | => | 2 3 4 5 | 8 7 6 5 12| IPL_030_1_| IO| | => |( 3) 4 5 6 |( 7) 6 5 4 -13| SM_AMIGA_D_0_|NOD| | => | 3 4 5 6 | 7 6 5 4 +13| SM_AMIGA_D_1_|NOD| | => | 3 4 5 6 | 7 6 5 4 14| | | | => | 4 5 6 7 | 6 5 4 3 15| | | | => | 4 5 6 7 | 6 5 4 3 --------------------------------------------------------------------------- @@ -637,13 +636,13 @@ IMX No. | +---- Block IO Pin or Macrocell Number 3 [IOpin 3 | 7| IO IPL_030_1_|*| ] paired w/[ RN_IPL_030_1_] [RegIn 3 |135| -| | ] - [MCell 6 |134|NOD inst_VPA_D| |*] + [MCell 6 |134|NOD SM_AMIGA_D_0_| |*] [MCell 7 |136| -| | ] 4 [IOpin 4 | 6|INP A_29_|*|*] [RegIn 4 |138| -| | ] [MCell 8 |137|NOD RN_IPL_030_0_| |*] paired w/[ IPL_030_0_] - [MCell 9 |139|NOD SM_AMIGA_D_1_| |*] + [MCell 9 |139|NOD SM_AMIGA_D_2_| |*] 5 [IOpin 5 | 5|INP A_30_|*|*] [RegIn 5 |141| -| | ] @@ -653,7 +652,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 6 [IOpin 6 | 4|INP A_31_|*|*] [RegIn 6 |144| -| | ] [MCell 12 |143|NOD RN_IPL_030_1_| |*] paired w/[ IPL_030_1_] - [MCell 13 |145|NOD SM_AMIGA_D_0_| |*] + [MCell 13 |145|NOD SM_AMIGA_D_1_| |*] 7 [IOpin 7 | 3|OUT RESET|*| ] [RegIn 7 |147| -| | ] @@ -666,37 +665,37 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| IOPin 6 2 ( 67)| IPL_0_ +Mux00| Input Pin ( 86)| RST Mux01| Mcel 3 13 ( 193)| SM_AMIGA_4_ -Mux02| ... | ... +Mux02| Mcel 1 6 ( 134)| SM_AMIGA_D_0_ Mux03| IOPin 5 4 ( 56)| IPL_1_ -Mux04| Mcel 6 1 ( 247)| SM_AMIGA_1_ +Mux04| Mcel 3 6 ( 182)| SM_AMIGA_5_ Mux05| Mcel 7 9 ( 283)| inst_RISING_CLK_AMIGA -Mux06| Mcel 1 9 ( 139)| SM_AMIGA_D_1_ -Mux07| ... | ... +Mux06| Mcel 1 9 ( 139)| SM_AMIGA_D_2_ +Mux07| Mcel 6 12 ( 263)| SM_AMIGA_1_ Mux08| Mcel 1 8 ( 137)| RN_IPL_030_0_ -Mux09| Mcel 6 13 ( 265)| SM_AMIGA_3_ -Mux10| Mcel 6 9 ( 259)| SM_AMIGA_2_ +Mux09| Mcel 6 13 ( 265)| SM_AMIGA_2_ +Mux10| Mcel 6 9 ( 259)| SM_AMIGA_0_ Mux11| ... | ... Mux12| Mcel 1 12 ( 143)| RN_IPL_030_1_ -Mux13| Input Pin ( 36)| VPA +Mux13| Mcel 6 8 ( 257)| SM_AMIGA_3_ Mux14| ... | ... Mux15| ... | ... -Mux16| Mcel 3 2 ( 176)| SM_AMIGA_6_ +Mux16| IOPin 6 2 ( 67)| IPL_0_ Mux17| ... | ... Mux18| ... | ... Mux19| ... | ... Mux20| ... | ... -Mux21| Mcel 1 13 ( 145)| SM_AMIGA_D_0_ +Mux21| Mcel 1 13 ( 145)| SM_AMIGA_D_1_ Mux22| IOPin 6 3 ( 68)| IPL_2_ -Mux23| Mcel 6 2 ( 248)| SM_AMIGA_D_2_ -Mux24| Input Pin ( 86)| RST +Mux23| ... | ... +Mux24| ... | ... Mux25| ... | ... Mux26| ... | ... Mux27| Mcel 1 4 ( 131)| RN_IPL_030_2_ -Mux28| Mcel 6 8 ( 257)| SM_AMIGA_0_ +Mux28| Mcel 3 2 ( 176)| SM_AMIGA_6_ Mux29| Input Pin ( 61)| CLK_OSZI -Mux30| Mcel 3 6 ( 182)| SM_AMIGA_5_ +Mux30| ... | ... Mux31| ... | ... Mux32| ... | ... --------------------------------------------------------------------------- @@ -918,17 +917,17 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ 1| BG_000| IO| | S | 3 | 4 to [ 1]| 1 XOR free 2| SM_AMIGA_6_|NOD| | S | 3 | 4 to [ 2]| 1 XOR free 3| | ? | | S | | 4 free | 1 XOR free - 4| VMA| IO| | S | 3 | 4 to [ 4]| 1 XOR free + 4| VMA| IO| | S | 2 | 4 to [ 4]| 1 XOR free 5| AS_000| IO| | S | 2 | 4 to [ 5]| 1 XOR free 6| SM_AMIGA_5_|NOD| | S | 2 | 4 to [ 6]| 1 XOR free - 7| | ? | | S | | 4 to [ 8]| 1 XOR free - 8| UDS_000| IO| | S |11 | 4 to [ 8]| 1 XOR to [ 8] as logic PT + 7| | ? | | S | | 4 free | 1 XOR free + 8| LDS_000| IO| | S |12 | 4 to [ 8]| 1 XOR to [ 8] as logic PT 9|AMIGA_BUS_ENABLE|OUT| | S | 1 | 4 to [ 8]| 1 XOR to [ 9] for 1 PT sig -10|un1_UDS_000_INT_0_sqmuxa_2_0|NOD| | S | 4 | 4 to [10]| 1 XOR free +10| | ? | | S | | 4 to [ 8]| 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free -12| LDS_000| IO| | S | 3 | 4 to [12]| 1 XOR free +12| UDS_000| IO| | S | 8 | 4 to [12]| 1 XOR to [12] as logic PT 13| SM_AMIGA_4_|NOD| | S | 2 | 4 to [13]| 1 XOR free -14|inst_CLK_000_DD|NOD| | A | 1 | 2 free | 1 XOR to [14] for 1 PT sig +14| | ? | | S | | 4 to [12]| 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== @@ -945,18 +944,18 @@ _|_________________|__|__|___|_____|_______________________________________ 1| BG_000| IO| | S | 3 |=> can support up to [ 14] logic PT(s) 2| SM_AMIGA_6_|NOD| | S | 3 |=> can support up to [ 10] logic PT(s) 3| | ? | | S | |=> can support up to [ 5] logic PT(s) - 4| VMA| IO| | S | 3 |=> can support up to [ 10] logic PT(s) - 5| AS_000| IO| | S | 2 |=> can support up to [ 5] logic PT(s) - 6| SM_AMIGA_5_|NOD| | S | 2 |=> can support up to [ 5] logic PT(s) - 7| | ? | | S | |=> can support up to [ 1] logic PT(s) - 8| UDS_000| IO| | S |11 |=> can support up to [ 14] logic PT(s) + 4| VMA| IO| | S | 2 |=> can support up to [ 10] logic PT(s) + 5| AS_000| IO| | S | 2 |=> can support up to [ 10] logic PT(s) + 6| SM_AMIGA_5_|NOD| | S | 2 |=> can support up to [ 10] logic PT(s) + 7| | ? | | S | |=> can support up to [ 5] logic PT(s) + 8| LDS_000| IO| | S |12 |=> can support up to [ 19] logic PT(s) 9|AMIGA_BUS_ENABLE|OUT| | S | 1 |=> can support up to [ 6] logic PT(s) -10|un1_UDS_000_INT_0_sqmuxa_2_0|NOD| | S | 4 |=> can support up to [ 10] logic PT(s) +10| | ? | | S | |=> can support up to [ 6] logic PT(s) 11| | ? | | S | |=> can support up to [ 5] logic PT(s) -12| LDS_000| IO| | S | 3 |=> can support up to [ 12] logic PT(s) -13| SM_AMIGA_4_|NOD| | S | 2 |=> can support up to [ 12] logic PT(s) -14|inst_CLK_000_DD|NOD| | A | 1 |=> can support up to [ 8] logic PT(s) -15| | ? | | S | |=> can support up to [ 7] logic PT(s) +12| UDS_000| IO| | S | 8 |=> can support up to [ 15] logic PT(s) +13| SM_AMIGA_4_|NOD| | S | 2 |=> can support up to [ 10] logic PT(s) +14| | ? | | S | |=> can support up to [ 6] logic PT(s) +15| | ? | | S | |=> can support up to [ 5] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 3] > Node-Pin Assignments @@ -974,13 +973,13 @@ _|_________________|__|_____|____________________|________________________ 5| AS_000| IO| | => | 7 0 1 ( 2)| 28 35 34 ( 33) 6| SM_AMIGA_5_|NOD| | => | 0 1 2 3 | 35 34 33 32 7| | | | => | 0 1 2 3 | 35 34 33 32 - 8| UDS_000| IO| | => | 1 2 ( 3) 4 | 34 33 ( 32) 31 + 8| LDS_000| IO| | => | 1 2 3 ( 4)| 34 33 32 ( 31) 9|AMIGA_BUS_ENABLE|OUT| | => |( 1) 2 3 4 |( 34) 33 32 31 -10|un1_UDS_000_INT_0_sqmuxa_2_0|NOD| | => | 2 3 4 5 | 33 32 31 30 +10| | | | => | 2 3 4 5 | 33 32 31 30 11| | | | => | 2 3 4 5 | 33 32 31 30 -12| LDS_000| IO| | => | 3 ( 4) 5 6 | 32 ( 31) 30 29 +12| UDS_000| IO| | => |( 3) 4 5 6 |( 32) 31 30 29 13| SM_AMIGA_4_|NOD| | => | 3 4 5 6 | 32 31 30 29 -14|inst_CLK_000_DD|NOD| | => | 4 5 6 7 | 31 30 29 28 +14| | | | => | 4 5 6 7 | 31 30 29 28 15| | | | => | 4 5 6 7 | 31 30 29 28 --------------------------------------------------------------------------- =========================================================================== @@ -995,8 +994,8 @@ _|_________________|__|___|_____|___________________________________________ 0| VMA| IO|*| 35| => | 0 1 2 3 ( 4) 5 6 7 1|AMIGA_BUS_ENABLE|OUT|*| 34| => | 2 3 4 5 6 7 8 ( 9) 2| AS_000| IO|*| 33| => | 4 ( 5) 6 7 8 9 10 11 - 3| UDS_000| IO|*| 32| => | 6 7 ( 8) 9 10 11 12 13 - 4| LDS_000| IO|*| 31| => | 8 9 10 11 (12) 13 14 15 + 3| UDS_000| IO|*| 32| => | 6 7 8 9 10 11 (12) 13 + 4| LDS_000| IO|*| 31| => | ( 8) 9 10 11 12 13 14 15 5| DTACK| IO|*| 30| => | 10 11 12 13 14 15 ( 0) 1 6| BG_000| IO|*| 29| => | 12 13 14 15 0 ( 1) 2 3 7| BGACK_000|INP|*| 28| => | 14 15 0 1 2 3 4 5 @@ -1055,22 +1054,22 @@ IMX No. | +---- Block IO Pin or Macrocell Number 4 [IOpin 4 | 31| IO LDS_000|*| ] paired w/[ RN_LDS_000] [RegIn 4 |186| -| | ] - [MCell 8 |185|NOD RN_UDS_000| |*] paired w/[ UDS_000] + [MCell 8 |185|NOD RN_LDS_000| |*] paired w/[ LDS_000] [MCell 9 |187|OUT AMIGA_BUS_ENABLE| | ] 5 [IOpin 5 | 30| IO DTACK|*|*] [RegIn 5 |189| -| | ] - [MCell 10 |188|NOD un1_UDS_000_INT_0_sqmuxa_2_0| |*] + [MCell 10 |188| -| | ] [MCell 11 |190| -| | ] 6 [IOpin 6 | 29| IO BG_000|*| ] paired w/[ RN_BG_000] [RegIn 6 |192| -| | ] - [MCell 12 |191|NOD RN_LDS_000| |*] paired w/[ LDS_000] + [MCell 12 |191|NOD RN_UDS_000| |*] paired w/[ UDS_000] [MCell 13 |193|NOD SM_AMIGA_4_| |*] 7 [IOpin 7 | 28|INP BGACK_000|*|*] [RegIn 7 |195| -| | ] - [MCell 14 |194|NOD inst_CLK_000_DD| |*] + [MCell 14 |194| -| | ] [MCell 15 |196| -| | ] --------------------------------------------------------------------------- =========================================================================== @@ -1079,39 +1078,39 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| IOPin 6 4 ( 69)| A_0_ +Mux00| Mcel 7 4 ( 275)| RN_BGACK_030 Mux01| Mcel 3 13 ( 193)| SM_AMIGA_4_ -Mux02| Mcel 3 1 ( 175)| RN_BG_000 +Mux02| Mcel 6 4 ( 251)| RN_E Mux03| Mcel 3 2 ( 176)| SM_AMIGA_6_ -Mux04| Mcel 3 6 ( 182)| SM_AMIGA_5_ -Mux05| Mcel 3 12 ( 191)| RN_LDS_000 +Mux04| IOPin 2 6 ( 21)| BG_030 +Mux05| Input Pin ( 14)| CPU_SPACE Mux06| IOPin 7 6 ( 79)| SIZE_1_ -Mux07| Mcel 6 12 ( 263)| inst_VPA_SYNC -Mux08| IOPin 6 6 ( 71)| RW +Mux07| Mcel 3 5 ( 181)| RN_AS_000 +Mux08| Mcel 6 7 ( 256)| cpu_est_d_1_ Mux09| IOPin 7 3 ( 82)| AS_030 -Mux10| Mcel 3 4 ( 179)| RN_VMA -Mux11| Mcel 3 5 ( 181)| RN_AS_000 -Mux12| Mcel 7 1 ( 271)| inst_AS_030_000_SYNC -Mux13| ... | ... -Mux14| IOPin 6 5 ( 70)| SIZE_0_ -Mux15| Mcel 0 0 ( 101)| inst_CLK_000_D -Mux16| Mcel 3 8 ( 185)| RN_UDS_000 -Mux17| IOPin 7 4 ( 81)| DSACK_1_ -Mux18| IOPin 0 7 ( 98)| DS_030 -Mux19| ... | ... -Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux21| Input Pin ( 14)| CPU_SPACE -Mux22| IOPin 2 6 ( 21)| BG_030 +Mux10| IOPin 7 4 ( 81)| DSACK_1_ +Mux11| Mcel 3 12 ( 191)| RN_UDS_000 +Mux12| IOPin 0 7 ( 98)| DS_030 +Mux13| Mcel 7 5 ( 277)| inst_AS_030_000_SYNC +Mux14| Mcel 3 4 ( 179)| RN_VMA +Mux15| IOPin 6 4 ( 69)| A_0_ +Mux16| Mcel 3 8 ( 185)| RN_LDS_000 +Mux17| IOPin 6 5 ( 70)| SIZE_0_ +Mux18| Mcel 6 15 ( 268)| cpu_est_d_0_ +Mux19| Mcel 7 1 ( 271)| inst_CLK_000_D +Mux20| Input Pin ( 64)| CLK_030 +Mux21| Input Pin ( 86)| RST +Mux22| Mcel 6 5 ( 253)| cpu_est_0_ Mux23| Mcel 6 6 ( 254)| SM_AMIGA_7_ -Mux24| Input Pin ( 86)| RST -Mux25| ... | ... -Mux26| ... | ... -Mux27| ... | ... -Mux28| Input Pin ( 64)| CLK_030 -Mux29| Input Pin ( 61)| CLK_OSZI -Mux30| Mcel 3 10 ( 188)| un1_UDS_000_INT_0_sqmuxa_2_0 -Mux31| ... | ... -Mux32| ... | ... +Mux24| Mcel 6 3 ( 250)| cpu_est_d_2_ +Mux25| IOPin 6 6 ( 71)| RW +Mux26| Mcel 6 11 ( 262)| cpu_est_d_3_ +Mux27| Mcel 3 1 ( 175)| RN_BG_000 +Mux28| Mcel 7 13 ( 289)| inst_CLK_000_DD +Mux29| Mcel 0 0 ( 101)| inst_VPA_D +Mux30| Mcel 3 6 ( 182)| SM_AMIGA_5_ +Mux31| Mcel 6 2 ( 248)| cpu_est_1_ +Mux32| Mcel 6 1 ( 247)| cpu_est_2_ --------------------------------------------------------------------------- =========================================================================== < Block [ 4] > Macrocell (MCell) Cluster Assignments @@ -1317,6 +1316,85 @@ Mux30| ... | ... Mux31| ... | ... Mux32| ... | ... --------------------------------------------------------------------------- +=========================================================================== + < Block [ 5] > Macrocell (MCell) Cluster Assignments +=========================================================================== + + Macrocell Number + | PT Requirements------ Logic XOR+ +--- Macrocell PT Cluster Size + | Sync/Async-------+ | | | Cluster to Mcell Assignment + | Node Fixed(*)----+ | | | | | +- XOR PT Size + | Sig Type-+ | | | | | | | XOR to Mcell Assignment + | Signal Name | | | | | | | | | +_|_________________|__|__|___|_____|__|______|___|__________|______________ + 0| inst_VPA_SYNC|NOD| | S | 2 | 4 to [ 0]| 1 XOR free + 1| | ? | | S | | 4 free | 1 XOR free + 2| | ? | | S | | 4 free | 1 XOR free + 3| | ? | | S | | 4 free | 1 XOR free + 4| | ? | | S | | 4 free | 1 XOR free + 5| | ? | | S | | 4 free | 1 XOR free + 6| | ? | | S | | 4 free | 1 XOR free + 7| | ? | | S | | 4 free | 1 XOR free + 8| | ? | | S | | 4 free | 1 XOR free + 9| | ? | | S | | 4 free | 1 XOR free +10| | ? | | S | | 4 free | 1 XOR free +11| | ? | | S | | 4 free | 1 XOR free +12| | ? | | S | | 4 free | 1 XOR free +13| | ? | | S | | 4 free | 1 XOR free +14| | ? | | S | | 4 free | 1 XOR free +15| | ? | | S | | 4 free | 1 XOR free +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 5] > Maximum PT Capacity +=========================================================================== + + Macrocell Number + | PT Requirements------ Logic XOR+ + | Sync/Async-------+ | | + | Node Fixed(*)----+ | | | + | Sig Type-+ | | | | + | Signal Name | | | | | Maximum PT Capacity +_|_________________|__|__|___|_____|_______________________________________ + 0| inst_VPA_SYNC|NOD| | S | 2 |=> can support up to [ 15] logic PT(s) + 1| | ? | | S | |=> can support up to [ 15] logic PT(s) + 2| | ? | | S | |=> can support up to [ 20] logic PT(s) + 3| | ? | | S | |=> can support up to [ 20] logic PT(s) + 4| | ? | | S | |=> can support up to [ 20] logic PT(s) + 5| | ? | | S | |=> can support up to [ 20] logic PT(s) + 6| | ? | | S | |=> can support up to [ 20] logic PT(s) + 7| | ? | | S | |=> can support up to [ 20] logic PT(s) + 8| | ? | | S | |=> can support up to [ 20] logic PT(s) + 9| | ? | | S | |=> can support up to [ 20] logic PT(s) +10| | ? | | S | |=> can support up to [ 20] logic PT(s) +11| | ? | | S | |=> can support up to [ 20] logic PT(s) +12| | ? | | S | |=> can support up to [ 20] logic PT(s) +13| | ? | | S | |=> can support up to [ 20] logic PT(s) +14| | ? | | S | |=> can support up to [ 15] logic PT(s) +15| | ? | | S | |=> can support up to [ 10] logic PT(s) +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 5] > Node-Pin Assignments +=========================================================================== + + Macrocell Number + | Node Fixed(*)------+ + | Sig Type---+ | to | Block [ 5] IO Pin | Device Pin + | Signal Name | | pin | Numbers | Numbers +_|_________________|__|_____|____________________|________________________ + 0| inst_VPA_SYNC|NOD| | => | 5 6 7 0 | 55 54 53 60 + 1| | | | => | 5 6 7 0 | 55 54 53 60 + 2| | | | => | 6 7 0 1 | 54 53 60 59 + 3| | | | => | 6 7 0 1 | 54 53 60 59 + 4| | | | => | 7 0 1 2 | 53 60 59 58 + 5| | | | => | 7 0 1 2 | 53 60 59 58 + 6| | | | => | 0 1 2 3 | 60 59 58 57 + 7| | | | => | 0 1 2 3 | 60 59 58 57 + 8| | | | => | 1 2 3 4 | 59 58 57 56 + 9| | | | => | 1 2 3 4 | 59 58 57 56 +10| | | | => | 2 3 4 5 | 58 57 56 55 +11| | | | => | 2 3 4 5 | 58 57 56 55 +12| | | | => | 3 4 5 6 | 57 56 55 54 +13| | | | => | 3 4 5 6 | 57 56 55 54 +14| | | | => | 4 5 6 7 | 56 55 54 53 +15| | | | => | 4 5 6 7 | 56 55 54 53 +--------------------------------------------------------------------------- =========================================================================== < Block [ 5] > IO-to-Node Pin Mapping =========================================================================== @@ -1364,7 +1442,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number ---|-------|----|---|---|----------|------|-|------------------------------ 0 [IOpin 0 | 60| -| | ] [RegIn 0 |222| -| | ] - [MCell 0 |221| -| | ] + [MCell 0 |221|NOD inst_VPA_SYNC| |*] [MCell 1 |223| -| | ] 1 [IOpin 1 | 59|INP A_17_|*|*] @@ -1402,6 +1480,46 @@ IMX No. | +---- Block IO Pin or Macrocell Number [MCell 14 |242| -| | ] [MCell 15 |244| -| | ] --------------------------------------------------------------------------- +=========================================================================== + < Block [ 5] > Logic Array Fan-in +=========================================================================== + +- Central Switch Matrix No. + | Src (ABEL Node/Pin#) Signal +--|--|--------------------|--------------------------------------------------- +Mux00| Input Pin ( 86)| RST +Mux01| ... | ... +Mux02| Mcel 6 4 ( 251)| RN_E +Mux03| Mcel 6 5 ( 253)| cpu_est_0_ +Mux04| Input Pin ( 61)| CLK_OSZI +Mux05| Mcel 5 0 ( 221)| inst_VPA_SYNC +Mux06| ... | ... +Mux07| ... | ... +Mux08| ... | ... +Mux09| IOPin 7 3 ( 82)| AS_030 +Mux10| Mcel 3 4 ( 179)| RN_VMA +Mux11| ... | ... +Mux12| Mcel 7 1 ( 271)| inst_CLK_000_D +Mux13| Mcel 6 8 ( 257)| SM_AMIGA_3_ +Mux14| ... | ... +Mux15| Mcel 0 0 ( 101)| inst_VPA_D +Mux16| ... | ... +Mux17| ... | ... +Mux18| ... | ... +Mux19| ... | ... +Mux20| ... | ... +Mux21| ... | ... +Mux22| ... | ... +Mux23| Mcel 6 2 ( 248)| cpu_est_1_ +Mux24| Mcel 6 1 ( 247)| cpu_est_2_ +Mux25| ... | ... +Mux26| ... | ... +Mux27| ... | ... +Mux28| ... | ... +Mux29| ... | ... +Mux30| ... | ... +Mux31| ... | ... +Mux32| ... | ... +--------------------------------------------------------------------------- =========================================================================== < Block [ 6] > Macrocell (MCell) Cluster Assignments =========================================================================== @@ -1412,22 +1530,22 @@ IMX No. | +---- Block IO Pin or Macrocell Number | Sig Type-+ | | | | | | | XOR to Mcell Assignment | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ - 0| CLK_DIV_OUT|OUT| | S | 1 | 4 to [ 1]| 1 XOR to [ 0] for 1 PT sig - 1| SM_AMIGA_1_|NOD| | A | 4 | 2 to [ 1]| 1 XOR to [ 1] as logic PT - 2| SM_AMIGA_D_2_|NOD| | S | 2 | 4 to [ 2]| 1 XOR free - 3| cpu_est_1_|NOD| | S | 4 | 4 to [ 3]| 1 XOR free + 0| CLK_DIV_OUT|OUT| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig + 1| cpu_est_2_|NOD| | S | 3 :+: 1| 4 to [ 1]| 1 XOR to [ 1] + 2| cpu_est_1_|NOD| | S | 4 | 4 to [ 2]| 1 XOR free + 3| cpu_est_d_2_|NOD| | S | 1 | 4 free | 1 XOR to [ 3] for 1 PT sig 4| E| IO| | S | 3 | 4 to [ 4]| 1 XOR free - 5|CLK_000_CNT_1_|NOD| | S | 4 | 4 to [ 5]| 1 XOR free + 5| cpu_est_0_|NOD| | S | 3 | 4 to [ 5]| 1 XOR free 6| SM_AMIGA_7_|NOD| | A | 2 | 2 to [ 6]| 1 XOR free - 7| cpu_est_2_|NOD| | S | 3 :+: 1| 4 to [ 7]| 1 XOR to [ 7] - 8| SM_AMIGA_0_|NOD| | A | 4 | 2 to [ 9]| 1 XOR to [ 9] as logic PT - 9| SM_AMIGA_2_|NOD| | A | 3 | 2 to [10]| 1 XOR free -10|inst_CLK_OUT_PRE|NOD| | S | 2 | 4 to [ 8]| 1 XOR free -11| cpu_est_0_|NOD| | S | 3 | 4 to [11]| 1 XOR free -12| inst_VPA_SYNC|NOD| | A | 2 | 2 to [12]| 1 XOR free -13| SM_AMIGA_3_|NOD| | A | 3 | 2 to [13]| 1 XOR to [13] as logic PT -14|inst_DTACK_SYNC|NOD| | A | 2 | 2 to [14]| 1 XOR free -15| CLK_CNT_0_|NOD| | S | 1 | 4 free | 1 XOR to [15] for 1 PT sig + 7| cpu_est_d_1_|NOD| | S | 1 | 4 free | 1 XOR to [ 7] for 1 PT sig + 8| SM_AMIGA_3_|NOD| | A | 3 | 2 to [ 8]| 1 XOR to [ 8] as logic PT + 9| SM_AMIGA_0_|NOD| | A | 3 | 2 to [ 9]| 1 XOR to [ 9] as logic PT +10|inst_CLK_OUT_PRE|NOD| | S | 2 | 4 to [10]| 1 XOR free +11| cpu_est_d_3_|NOD| | S | 1 | 4 free | 1 XOR to [11] for 1 PT sig +12| SM_AMIGA_1_|NOD| | A | 3 | 2 to [12]| 1 XOR to [12] as logic PT +13| SM_AMIGA_2_|NOD| | A | 3 | 2 to [13]| 1 XOR to [13] as logic PT +14| CLK_CNT_0_|NOD| | S | 1 | 4 free | 1 XOR to [14] for 1 PT sig +15| cpu_est_d_0_|NOD| | S | 1 | 4 free | 1 XOR to [15] for 1 PT sig --------------------------------------------------------------------------- =========================================================================== < Block [ 6] > Maximum PT Capacity @@ -1439,22 +1557,22 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| CLK_DIV_OUT|OUT| | S | 1 |=> can support up to [ 1] logic PT(s) - 1| SM_AMIGA_1_|NOD| | A | 4 |=> can support up to [ 7] logic PT(s) - 2| SM_AMIGA_D_2_|NOD| | S | 2 |=> can support up to [ 5] logic PT(s) - 3| cpu_est_1_|NOD| | S | 4 |=> can support up to [ 5] logic PT(s) - 4| E| IO| | S | 3 |=> can support up to [ 5] logic PT(s) - 5|CLK_000_CNT_1_|NOD| | S | 4 |=> can support up to [ 5] logic PT(s) - 6| SM_AMIGA_7_|NOD| | A | 2 |=> can support up to [ 3] logic PT(s) - 7| cpu_est_2_|NOD| | S | 3 :+: 1|=> can support up to [ 4] logic PT(s) - 8| SM_AMIGA_0_|NOD| | A | 4 |=> can support up to [ 5] logic PT(s) - 9| SM_AMIGA_2_|NOD| | A | 3 |=> can support up to [ 3] logic PT(s) -10|inst_CLK_OUT_PRE|NOD| | S | 2 |=> can support up to [ 3] logic PT(s) -11| cpu_est_0_|NOD| | S | 3 |=> can support up to [ 5] logic PT(s) -12| inst_VPA_SYNC|NOD| | A | 2 |=> can support up to [ 3] logic PT(s) -13| SM_AMIGA_3_|NOD| | A | 3 |=> can support up to [ 7] logic PT(s) -14|inst_DTACK_SYNC|NOD| | A | 2 |=> can support up to [ 7] logic PT(s) -15| CLK_CNT_0_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) + 0| CLK_DIV_OUT|OUT| | S | 1 |=> can support up to [ 5] logic PT(s) + 1| cpu_est_2_|NOD| | S | 3 :+: 1|=> can support up to [ 12] logic PT(s) + 2| cpu_est_1_|NOD| | S | 4 |=> can support up to [ 9] logic PT(s) + 3| cpu_est_d_2_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) + 4| E| IO| | S | 3 |=> can support up to [ 9] logic PT(s) + 5| cpu_est_0_|NOD| | S | 3 |=> can support up to [ 9] logic PT(s) + 6| SM_AMIGA_7_|NOD| | A | 2 |=> can support up to [ 7] logic PT(s) + 7| cpu_est_d_1_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) + 8| SM_AMIGA_3_|NOD| | A | 3 |=> can support up to [ 7] logic PT(s) + 9| SM_AMIGA_0_|NOD| | A | 3 |=> can support up to [ 7] logic PT(s) +10|inst_CLK_OUT_PRE|NOD| | S | 2 |=> can support up to [ 9] logic PT(s) +11| cpu_est_d_3_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) +12| SM_AMIGA_1_|NOD| | A | 3 |=> can support up to [ 11] logic PT(s) +13| SM_AMIGA_2_|NOD| | A | 3 |=> can support up to [ 11] logic PT(s) +14| CLK_CNT_0_|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) +15| cpu_est_d_0_|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 6] > Node-Pin Assignments @@ -1465,21 +1583,21 @@ _|_________________|__|__|___|_____|_______________________________________ | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ 0| CLK_DIV_OUT|OUT| | => | 5 6 7 ( 0)| 70 71 72 ( 65) - 1| SM_AMIGA_1_|NOD| | => | 5 6 7 0 | 70 71 72 65 - 2| SM_AMIGA_D_2_|NOD| | => | 6 7 0 1 | 71 72 65 66 - 3| cpu_est_1_|NOD| | => | 6 7 0 1 | 71 72 65 66 + 1| cpu_est_2_|NOD| | => | 5 6 7 0 | 70 71 72 65 + 2| cpu_est_1_|NOD| | => | 6 7 0 1 | 71 72 65 66 + 3| cpu_est_d_2_|NOD| | => | 6 7 0 1 | 71 72 65 66 4| E| IO| | => | 7 0 ( 1) 2 | 72 65 ( 66) 67 - 5|CLK_000_CNT_1_|NOD| | => | 7 0 1 2 | 72 65 66 67 + 5| cpu_est_0_|NOD| | => | 7 0 1 2 | 72 65 66 67 6| SM_AMIGA_7_|NOD| | => | 0 1 2 3 | 65 66 67 68 - 7| cpu_est_2_|NOD| | => | 0 1 2 3 | 65 66 67 68 - 8| SM_AMIGA_0_|NOD| | => | 1 2 3 4 | 66 67 68 69 - 9| SM_AMIGA_2_|NOD| | => | 1 2 3 4 | 66 67 68 69 + 7| cpu_est_d_1_|NOD| | => | 0 1 2 3 | 65 66 67 68 + 8| SM_AMIGA_3_|NOD| | => | 1 2 3 4 | 66 67 68 69 + 9| SM_AMIGA_0_|NOD| | => | 1 2 3 4 | 66 67 68 69 10|inst_CLK_OUT_PRE|NOD| | => | 2 3 4 5 | 67 68 69 70 -11| cpu_est_0_|NOD| | => | 2 3 4 5 | 67 68 69 70 -12| inst_VPA_SYNC|NOD| | => | 3 4 5 6 | 68 69 70 71 -13| SM_AMIGA_3_|NOD| | => | 3 4 5 6 | 68 69 70 71 -14|inst_DTACK_SYNC|NOD| | => | 4 5 6 7 | 69 70 71 72 -15| CLK_CNT_0_|NOD| | => | 4 5 6 7 | 69 70 71 72 +11| cpu_est_d_3_|NOD| | => | 2 3 4 5 | 67 68 69 70 +12| SM_AMIGA_1_|NOD| | => | 3 4 5 6 | 68 69 70 71 +13| SM_AMIGA_2_|NOD| | => | 3 4 5 6 | 68 69 70 71 +14| CLK_CNT_0_|NOD| | => | 4 5 6 7 | 69 70 71 72 +15| cpu_est_d_0_|NOD| | => | 4 5 6 7 | 69 70 71 72 --------------------------------------------------------------------------- =========================================================================== < Block [ 6] > IO-to-Node Pin Mapping @@ -1530,42 +1648,42 @@ IMX No. | +---- Block IO Pin or Macrocell Number 0 [IOpin 0 | 65|OUT CLK_DIV_OUT|*| ] [RegIn 0 |246| -| | ] [MCell 0 |245|OUT CLK_DIV_OUT| | ] - [MCell 1 |247|NOD SM_AMIGA_1_| |*] + [MCell 1 |247|NOD cpu_est_2_| |*] 1 [IOpin 1 | 66| IO E|*| ] paired w/[ RN_E] [RegIn 1 |249| -| | ] - [MCell 2 |248|NOD SM_AMIGA_D_2_| |*] - [MCell 3 |250|NOD cpu_est_1_| |*] + [MCell 2 |248|NOD cpu_est_1_| |*] + [MCell 3 |250|NOD cpu_est_d_2_| |*] 2 [IOpin 2 | 67|INP IPL_0_|*|*] [RegIn 2 |252| -| | ] [MCell 4 |251|NOD RN_E| |*] paired w/[ E] - [MCell 5 |253|NOD CLK_000_CNT_1_| |*] + [MCell 5 |253|NOD cpu_est_0_| |*] 3 [IOpin 3 | 68|INP IPL_2_|*|*] [RegIn 3 |255| -| | ] [MCell 6 |254|NOD SM_AMIGA_7_| |*] - [MCell 7 |256|NOD cpu_est_2_| |*] + [MCell 7 |256|NOD cpu_est_d_1_| |*] 4 [IOpin 4 | 69|INP A_0_|*|*] [RegIn 4 |258| -| | ] - [MCell 8 |257|NOD SM_AMIGA_0_| |*] - [MCell 9 |259|NOD SM_AMIGA_2_| |*] + [MCell 8 |257|NOD SM_AMIGA_3_| |*] + [MCell 9 |259|NOD SM_AMIGA_0_| |*] 5 [IOpin 5 | 70|INP SIZE_0_|*|*] [RegIn 5 |261| -| | ] [MCell 10 |260|NOD inst_CLK_OUT_PRE| |*] - [MCell 11 |262|NOD cpu_est_0_| |*] + [MCell 11 |262|NOD cpu_est_d_3_| |*] 6 [IOpin 6 | 71|INP RW|*|*] [RegIn 6 |264| -| | ] - [MCell 12 |263|NOD inst_VPA_SYNC| |*] - [MCell 13 |265|NOD SM_AMIGA_3_| |*] + [MCell 12 |263|NOD SM_AMIGA_1_| |*] + [MCell 13 |265|NOD SM_AMIGA_2_| |*] 7 [IOpin 7 | 72| -| | ] [RegIn 7 |267| -| | ] - [MCell 14 |266|NOD inst_DTACK_SYNC| |*] - [MCell 15 |268|NOD CLK_CNT_0_| |*] + [MCell 14 |266|NOD CLK_CNT_0_| |*] + [MCell 15 |268|NOD cpu_est_d_0_| |*] --------------------------------------------------------------------------- =========================================================================== < Block [ 6] > Logic Array Fan-in @@ -1575,37 +1693,37 @@ IMX No. | +---- Block IO Pin or Macrocell Number --|--|--------------------|--------------------------------------------------- Mux00| Input Pin ( 86)| RST Mux01| Mcel 3 13 ( 193)| SM_AMIGA_4_ -Mux02| Mcel 1 6 ( 134)| inst_VPA_D -Mux03| Input Pin ( 11)| CLK_000 +Mux02| Mcel 6 4 ( 251)| RN_E +Mux03| Mcel 0 8 ( 113)| inst_DTACK_SYNC Mux04| Input Pin ( 61)| CLK_OSZI -Mux05| Mcel 6 3 ( 250)| cpu_est_1_ +Mux05| Mcel 5 0 ( 221)| inst_VPA_SYNC Mux06| ... | ... -Mux07| Mcel 3 5 ( 181)| RN_AS_000 -Mux08| Mcel 6 7 ( 256)| cpu_est_2_ -Mux09| IOPin 3 5 ( 30)| DTACK -Mux10| Mcel 6 9 ( 259)| SM_AMIGA_2_ -Mux11| Mcel 6 4 ( 251)| RN_E -Mux12| Mcel 6 13 ( 265)| SM_AMIGA_3_ -Mux13| Mcel 6 11 ( 262)| cpu_est_0_ -Mux14| Mcel 6 12 ( 263)| inst_VPA_SYNC -Mux15| Mcel 0 0 ( 101)| inst_CLK_000_D +Mux07| Mcel 7 13 ( 289)| inst_CLK_000_DD +Mux08| ... | ... +Mux09| Mcel 6 13 ( 265)| SM_AMIGA_2_ +Mux10| Mcel 6 14 ( 266)| CLK_CNT_0_ +Mux11| Mcel 3 5 ( 181)| RN_AS_000 +Mux12| Mcel 6 9 ( 259)| SM_AMIGA_0_ +Mux13| Mcel 6 8 ( 257)| SM_AMIGA_3_ +Mux14| Mcel 6 12 ( 263)| SM_AMIGA_1_ +Mux15| ... | ... Mux16| ... | ... -Mux17| Mcel 3 14 ( 194)| inst_CLK_000_DD -Mux18| Mcel 6 15 ( 268)| CLK_CNT_0_ -Mux19| IOPin 7 3 ( 82)| AS_030 +Mux17| ... | ... +Mux18| ... | ... +Mux19| Mcel 7 1 ( 271)| inst_CLK_000_D Mux20| ... | ... Mux21| ... | ... Mux22| Mcel 6 10 ( 260)| inst_CLK_OUT_PRE Mux23| Mcel 6 6 ( 254)| SM_AMIGA_7_ -Mux24| Mcel 6 1 ( 247)| SM_AMIGA_1_ +Mux24| Mcel 6 1 ( 247)| cpu_est_2_ Mux25| ... | ... -Mux26| Mcel 6 14 ( 266)| inst_DTACK_SYNC -Mux27| Mcel 7 5 ( 277)| CLK_000_CNT_0_ -Mux28| Mcel 6 8 ( 257)| SM_AMIGA_0_ +Mux26| ... | ... +Mux27| ... | ... +Mux28| ... | ... Mux29| ... | ... Mux30| ... | ... -Mux31| Mcel 6 2 ( 248)| SM_AMIGA_D_2_ -Mux32| Mcel 6 5 ( 253)| CLK_000_CNT_1_ +Mux31| Mcel 6 2 ( 248)| cpu_est_1_ +Mux32| Mcel 6 5 ( 253)| cpu_est_0_ --------------------------------------------------------------------------- =========================================================================== < Block [ 7] > Macrocell (MCell) Cluster Assignments @@ -1618,21 +1736,21 @@ Mux32| Mcel 6 5 ( 253)| CLK_000_CNT_1_ | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| FPU_CS| IO| | S | 2 | 4 to [ 0]| 1 XOR free - 1|inst_AS_030_000_SYNC|NOD| | S | 4 | 4 to [ 1]| 1 XOR free - 2|CLK_000_CNT_3_|NOD| | A | 4 | 2 to [ 2]| 1 XOR to [ 2] as logic PT - 3| | ? | | S | | 4 to [ 2]| 1 XOR free - 4| BGACK_030| IO| | S | 2 | 4 free | 1 XOR free - 5|CLK_000_CNT_0_|NOD| | A | 2 | 2 to [ 4]| 1 XOR free - 6| | ? | | S | | 4 to [ 5]| 1 XOR free - 7| | ? | | S | | 4 to [ 8]| 1 XOR free - 8| DSACK_1_| IO| | S | 9 | 4 free | 1 XOR free - 9|inst_RISING_CLK_AMIGA|NOD| | A | 1 | 2 to [ 8]| 1 XOR to [ 9] for 1 PT sig -10| | ? | | S | | 4 to [ 8]| 1 XOR to [ 8] as logic PT + 1|inst_CLK_000_D|NOD| | A | 1 | 2 free | 1 XOR to [ 1] for 1 PT sig + 2| | ? | | S | | 4 free | 1 XOR free + 3| | ? | | S | | 4 free | 1 XOR free + 4| BGACK_030| IO| | S | 2 | 4 to [ 4]| 1 XOR free + 5|inst_AS_030_000_SYNC|NOD| | S | 4 | 4 to [ 5]| 1 XOR free + 6| | ? | | S | | 4 free | 1 XOR free + 7| | ? | | S | | 4 free | 1 XOR free + 8| DSACK_1_| IO| | S | 2 | 4 to [ 8]| 1 XOR free + 9|inst_RISING_CLK_AMIGA|NOD| | A | 1 | 2 free | 1 XOR to [ 9] for 1 PT sig +10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free 12| DSACK_0_|OUT| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig -13|CLK_000_CNT_2_|NOD| | A | 5 | 2 to [13]| 1 XOR to [13] as logic PT +13|inst_CLK_000_DD|NOD| | A | 1 | 2 free | 1 XOR to [13] for 1 PT sig 14| | ? | | S | | 4 free | 1 XOR free -15| | ? | | S | | 4 to [13]| 1 XOR free +15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== < Block [ 7] > Maximum PT Capacity @@ -1644,22 +1762,22 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| FPU_CS| IO| | S | 2 |=> can support up to [ 5] logic PT(s) - 1|inst_AS_030_000_SYNC|NOD| | S | 4 |=> can support up to [ 5] logic PT(s) - 2|CLK_000_CNT_3_|NOD| | A | 4 |=> can support up to [ 13] logic PT(s) - 3| | ? | | S | |=> can support up to [ 6] logic PT(s) - 4| BGACK_030| IO| | S | 2 |=> can support up to [ 8] logic PT(s) - 5|CLK_000_CNT_0_|NOD| | A | 2 |=> can support up to [ 10] logic PT(s) - 6| | ? | | S | |=> can support up to [ 6] logic PT(s) - 7| | ? | | S | |=> can support up to [ 6] logic PT(s) - 8| DSACK_1_| IO| | S | 9 |=> can support up to [ 17] logic PT(s) - 9|inst_RISING_CLK_AMIGA|NOD| | A | 1 |=> can support up to [ 11] logic PT(s) -10| | ? | | S | |=> can support up to [ 9] logic PT(s) -11| | ? | | S | |=> can support up to [ 9] logic PT(s) -12| DSACK_0_|OUT| | S | 1 |=> can support up to [ 15] logic PT(s) -13|CLK_000_CNT_2_|NOD| | A | 5 |=> can support up to [ 17] logic PT(s) -14| | ? | | S | |=> can support up to [ 5] logic PT(s) -15| | ? | | S | |=> can support up to [ 6] logic PT(s) + 0| FPU_CS| IO| | S | 2 |=> can support up to [ 12] logic PT(s) + 1|inst_CLK_000_D|NOD| | A | 1 |=> can support up to [ 13] logic PT(s) + 2| | ? | | S | |=> can support up to [ 12] logic PT(s) + 3| | ? | | S | |=> can support up to [ 10] logic PT(s) + 4| BGACK_030| IO| | S | 2 |=> can support up to [ 15] logic PT(s) + 5|inst_AS_030_000_SYNC|NOD| | S | 4 |=> can support up to [ 15] logic PT(s) + 6| | ? | | S | |=> can support up to [ 10] logic PT(s) + 7| | ? | | S | |=> can support up to [ 12] logic PT(s) + 8| DSACK_1_| IO| | S | 2 |=> can support up to [ 17] logic PT(s) + 9|inst_RISING_CLK_AMIGA|NOD| | A | 1 |=> can support up to [ 13] logic PT(s) +10| | ? | | S | |=> can support up to [ 16] logic PT(s) +11| | ? | | S | |=> can support up to [ 16] logic PT(s) +12| DSACK_0_|OUT| | S | 1 |=> can support up to [ 17] logic PT(s) +13|inst_CLK_000_DD|NOD| | A | 1 |=> can support up to [ 17] logic PT(s) +14| | ? | | S | |=> can support up to [ 12] logic PT(s) +15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 7] > Node-Pin Assignments @@ -1670,11 +1788,11 @@ _|_________________|__|__|___|_____|_______________________________________ | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ 0| FPU_CS| IO| | => | 5 6 ( 7) 0 | 80 79 ( 78) 85 - 1|inst_AS_030_000_SYNC|NOD| | => | 5 6 7 0 | 80 79 78 85 - 2|CLK_000_CNT_3_|NOD| | => | 6 7 0 1 | 79 78 85 84 + 1|inst_CLK_000_D|NOD| | => | 5 6 7 0 | 80 79 78 85 + 2| | | | => | 6 7 0 1 | 79 78 85 84 3| | | | => | 6 7 0 1 | 79 78 85 84 4| BGACK_030| IO| | => | 7 0 1 ( 2)| 78 85 84 ( 83) - 5|CLK_000_CNT_0_|NOD| | => | 7 0 1 2 | 78 85 84 83 + 5|inst_AS_030_000_SYNC|NOD| | => | 7 0 1 2 | 78 85 84 83 6| | | | => | 0 1 2 3 | 85 84 83 82 7| | | | => | 0 1 2 3 | 85 84 83 82 8| DSACK_1_| IO| | => | 1 2 3 ( 4)| 84 83 82 ( 81) @@ -1682,7 +1800,7 @@ _|_________________|__|_____|____________________|________________________ 10| | | | => | 2 3 4 5 | 83 82 81 80 11| | | | => | 2 3 4 5 | 83 82 81 80 12| DSACK_0_|OUT| | => | 3 4 ( 5) 6 | 82 81 ( 80) 79 -13|CLK_000_CNT_2_|NOD| | => | 3 4 5 6 | 82 81 80 79 +13|inst_CLK_000_DD|NOD| | => | 3 4 5 6 | 82 81 80 79 14| | | | => | 4 5 6 7 | 81 80 79 78 15| | | | => | 4 5 6 7 | 81 80 79 78 --------------------------------------------------------------------------- @@ -1737,17 +1855,17 @@ IMX No. | +---- Block IO Pin or Macrocell Number 0 [IOpin 0 | 85|INP A_22_|*|*] [RegIn 0 |270| -| | ] [MCell 0 |269|NOD RN_FPU_CS| |*] paired w/[ FPU_CS] - [MCell 1 |271|NOD inst_AS_030_000_SYNC| |*] + [MCell 1 |271|NOD inst_CLK_000_D| |*] 1 [IOpin 1 | 84|INP A_23_|*|*] [RegIn 1 |273| -| | ] - [MCell 2 |272|NOD CLK_000_CNT_3_| |*] + [MCell 2 |272| -| | ] [MCell 3 |274| -| | ] 2 [IOpin 2 | 83| IO BGACK_030|*| ] paired w/[ RN_BGACK_030] [RegIn 2 |276| -| | ] [MCell 4 |275|NOD RN_BGACK_030| |*] paired w/[ BGACK_030] - [MCell 5 |277|NOD CLK_000_CNT_0_| |*] + [MCell 5 |277|NOD inst_AS_030_000_SYNC| |*] 3 [IOpin 3 | 82|INP AS_030|*|*] [RegIn 3 |279| -| | ] @@ -1767,7 +1885,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 6 [IOpin 6 | 79|INP SIZE_1_|*|*] [RegIn 6 |288| -| | ] [MCell 12 |287|OUT DSACK_0_| | ] - [MCell 13 |289|NOD CLK_000_CNT_2_| |*] + [MCell 13 |289|NOD inst_CLK_000_DD| |*] 7 [IOpin 7 | 78| IO FPU_CS|*| ] paired w/[ RN_FPU_CS] [RegIn 7 |291| -| | ] @@ -1783,34 +1901,34 @@ IMX No. | +---- Block IO Pin or Macrocell Number Mux00| Input Pin ( 86)| RST Mux01| IOPin 5 2 ( 58)| FC_1_ Mux02| ... | ... -Mux03| Mcel 7 8 ( 281)| RN_DSACK_1_ -Mux04| IOPin 0 4 ( 95)| A_18_ +Mux03| Input Pin ( 11)| CLK_000 +Mux04| Mcel 7 5 ( 277)| inst_AS_030_000_SYNC Mux05| Input Pin ( 14)| CPU_SPACE -Mux06| IOPin 0 5 ( 96)| A_16_ -Mux07| Mcel 6 12 ( 263)| inst_VPA_SYNC +Mux06| IOPin 5 3 ( 57)| FC_0_ +Mux07| Mcel 6 12 ( 263)| SM_AMIGA_1_ Mux08| IOPin 5 1 ( 59)| A_17_ Mux09| IOPin 7 3 ( 82)| AS_030 -Mux10| Mcel 7 1 ( 271)| inst_AS_030_000_SYNC -Mux11| Mcel 6 14 ( 266)| inst_DTACK_SYNC +Mux10| Mcel 7 1 ( 271)| inst_CLK_000_D +Mux11| IOPin 0 5 ( 96)| A_16_ Mux12| IOPin 0 6 ( 97)| A_19_ -Mux13| Mcel 7 5 ( 277)| CLK_000_CNT_0_ -Mux14| Mcel 7 2 ( 272)| CLK_000_CNT_3_ -Mux15| Mcel 0 0 ( 101)| inst_CLK_000_D +Mux13| Mcel 7 8 ( 281)| RN_DSACK_1_ +Mux14| ... | ... +Mux15| ... | ... Mux16| ... | ... -Mux17| IOPin 5 3 ( 57)| FC_0_ +Mux17| IOPin 0 4 ( 95)| A_18_ Mux18| IOPin 3 7 ( 28)| BGACK_000 -Mux19| Mcel 7 13 ( 289)| CLK_000_CNT_2_ +Mux19| ... | ... Mux20| Input Pin ( 64)| CLK_030 Mux21| Input Pin ( 61)| CLK_OSZI Mux22| Mcel 6 10 ( 260)| inst_CLK_OUT_PRE Mux23| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux24| Input Pin ( 11)| CLK_000 +Mux24| ... | ... Mux25| ... | ... Mux26| ... | ... Mux27| Mcel 7 9 ( 283)| inst_RISING_CLK_AMIGA -Mux28| Mcel 6 8 ( 257)| SM_AMIGA_0_ +Mux28| ... | ... Mux29| ... | ... Mux30| Mcel 7 0 ( 269)| RN_FPU_CS Mux31| ... | ... -Mux32| Mcel 6 5 ( 253)| CLK_000_CNT_1_ +Mux32| ... | ... --------------------------------------------------------------------------- \ No newline at end of file diff --git a/Logic/68030_tk.rpt b/Logic/68030_tk.rpt index f32a840..e8861ff 100644 --- a/Logic/68030_tk.rpt +++ b/Logic/68030_tk.rpt @@ -11,8 +11,8 @@ Project_Summary ~~~~~~~~~~~~~~~ Project Name : 68030_tk -Project Path : C:\Users\Matze\Amiga\Hardwarehacks\68030-TK\Logic -Project Fitted on : Thu May 15 19:20:57 2014 +Project Path : C:\Users\Matze\Documents\GitHub\68030tk\Logic +Project Fitted on : Thu May 15 22:17:31 2014 Device : M4A5-128/64 Package : 100TQFP @@ -41,7 +41,7 @@ Design_Summary Total Output Pins : 22 Total Bidir I/O Pins : 2 Total Flip-Flops : 42 - Total Product Terms : 141 + Total Product Terms : 122 Total Reserved Pins : 0 Total Reserved Blocks : 0 @@ -54,13 +54,13 @@ Dedicated Pins Input-Only Pins 2 2 0 --> 100% Clock/Input Pins 4 4 0 --> 100% I/O Pins 64 53 11 --> 82% -Logic Macrocells 128 52 76 --> 40% +Logic Macrocells 128 51 77 --> 39% Input Registers 64 0 64 --> 0% Unusable Macrocells .. 0 .. -CSM Outputs/Total Block Inputs 264 116 148 --> 43% -Logical Product Terms 640 143 497 --> 22% -Product Term Clusters 128 48 80 --> 37% +CSM Outputs/Total Block Inputs 264 128 136 --> 48% +Logical Product Terms 640 124 516 --> 19% +Product Term Clusters 128 40 88 --> 31%  Blocks_Resource_Summary @@ -71,14 +71,14 @@ Blocks_Resource_Summary --------------------------------------------------------------------------------- Maximum 33 8 8 -- -- 16 80 16 - --------------------------------------------------------------------------------- -Block A 2 7 0 2 0 14 2 16 Hi -Block B 20 8 0 8 0 8 26 8 Hi +Block A 9 7 0 3 0 13 4 15 Hi +Block B 19 8 0 8 0 8 27 7 Hi Block C 1 8 0 2 0 14 2 16 Hi -Block D 26 8 0 12 0 4 36 5 Hi +Block D 33 8 0 10 0 6 36 5 Hi Block E 14 3 0 3 0 13 3 16 Hi -Block F 0 4 0 0 0 16 0 16 Hi -Block G 26 7 0 16 0 0 44 1 Hi -Block H 27 8 0 9 0 7 30 5 Hi +Block F 12 4 0 1 0 15 2 15 Hi +Block G 19 7 0 16 0 0 36 6 Hi +Block H 21 8 0 8 0 8 14 12 Hi --------------------------------------------------------------------------------- Four rightmost columns above reflect last status of the placement process. @@ -287,7 +287,7 @@ Input_Signal_List Pin r e O Input Pin Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- - 82 H . I/O ---D--GH Hi Fast AS_030 + 82 H . I/O A--D-F-H Hi Fast AS_030 69 G . I/O ---D---- Hi Fast A_0_ 96 A . I/O -------H Hi Fast A_16_ 59 F . I/O -------H Hi Fast A_17_ @@ -316,12 +316,12 @@ Pin Blk PTs Type e s E Fanout Pwr Slew Signal 71 G . I/O ---DE--- Hi Fast RW 70 G . I/O ---D---- Hi Fast SIZE_0_ 79 H . I/O ---D---- Hi Fast SIZE_1_ - 11 . . Ck/I A-----GH - Fast CLK_000 + 11 . . Ck/I -------H - Fast CLK_000 14 . . Ck/I ---D---H - Fast CPU_SPACE - 36 . . Ded -B------ - Fast VPA - 61 . . Ck/I AB-D--GH - Fast CLK_OSZI + 36 . . Ded A------- - Fast VPA + 61 . . Ck/I AB-D-FGH - Fast CLK_OSZI 64 . . Ck/I ---D---H - Fast CLK_030 - 86 . . Ded -B-D--GH - Fast RST + 86 . . Ded AB-D-FGH - Fast RST ---------------------------------------------------------------------- Power : Hi = High @@ -355,10 +355,10 @@ Pin Blk PTs Type e s E Fanout Pwr Slew Signal 8 B 2 DFF * * -------- Hi Fast IPL_030_0_ 7 B 2 DFF * * -------- Hi Fast IPL_030_1_ 9 B 2 DFF * * -------- Hi Fast IPL_030_2_ - 31 D 3 DFF * * -------- Hi Fast LDS_000 + 31 D 12 DFF * * -------- Hi Fast LDS_000 3 B 1 DFF * * -------- Hi Fast RESET - 32 D 11 DFF * * -------- Hi Fast UDS_000 - 35 D 3 DFF * * -------- Hi Fast VMA + 32 D 8 DFF * * -------- Hi Fast UDS_000 + 35 D 2 TFF * * -------- Hi Fast VMA ---------------------------------------------------------------------- Power : Hi = High @@ -374,8 +374,8 @@ Bidir_Signal_List Pin r e O Bidir Pin Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- - 81 H 9 DFF * * ---D---- Hi Fast DSACK_1_ - 30 D 1 DFF * * ------G- Hi Fast DTACK + 81 H 2 DFF * * ---D---- Hi Fast DSACK_1_ + 30 D 1 DFF * * A------- Hi Fast DTACK ---------------------------------------------------------------------- Power : Hi = High @@ -391,46 +391,45 @@ Buried_Signal_List Pin r e O Node #Mc Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- - H5 H 2 DFF * * ------GH Hi Fast CLK_000_CNT_0_ - G5 G 4 DFF * * ------GH Hi Fast CLK_000_CNT_1_ - H13 H 5 DFF * * -------H Hi Fast CLK_000_CNT_2_ - H2 H 4 TFF * * -------H Hi Fast CLK_000_CNT_3_ - G15 G 1 DFF * * ------G- Hi Fast CLK_CNT_0_ + G14 G 1 DFF * * ------G- Hi Fast CLK_CNT_0_ D5 D 2 DFF * * ---D--G- Hi - RN_AS_000 --> AS_000 H4 H 2 DFF * * ---D---H Hi - RN_BGACK_030 --> BGACK_030 D1 D 3 DFF * * ---D---- Hi - RN_BG_000 --> BG_000 - H8 H 9 DFF * * -------H Hi - RN_DSACK_1_ --> DSACK_1_ - G4 G 3 TFF * * ------G- Hi - RN_E --> E + H8 H 2 DFF * * -------H Hi - RN_DSACK_1_ --> DSACK_1_ + G4 G 3 TFF * * ---D-FG- Hi - RN_E --> E H0 H 2 DFF * * --C-E--H Hi - RN_FPU_CS --> FPU_CS B8 B 2 DFF * * -B------ Hi - RN_IPL_030_0_ --> IPL_030_0_ B12 B 2 DFF * * -B------ Hi - RN_IPL_030_1_ --> IPL_030_1_ B4 B 2 DFF * * -B------ Hi - RN_IPL_030_2_ --> IPL_030_2_ - D12 D 3 DFF * * ---D---- Hi - RN_LDS_000 --> LDS_000 - D8 D 11 DFF * * ---D---- Hi - RN_UDS_000 --> UDS_000 - D4 D 3 DFF * * ---D---- Hi - RN_VMA --> VMA - G8 G 4 DFF * * -B----GH Hi Fast SM_AMIGA_0_ - G1 G 4 DFF * * -B----G- Hi Fast SM_AMIGA_1_ - G9 G 3 DFF * * -B----G- Hi Fast SM_AMIGA_2_ - G13 G 3 DFF * * -B----G- Hi Fast SM_AMIGA_3_ + D8 D 12 DFF * * ---D---- Hi - RN_LDS_000 --> LDS_000 + D12 D 8 DFF * * ---D---- Hi - RN_UDS_000 --> UDS_000 + D4 D 2 TFF * * ---D-F-- Hi - RN_VMA --> VMA + G9 G 3 DFF * * -B----G- Hi Fast SM_AMIGA_0_ + G12 G 3 DFF * * -B----GH Hi Fast SM_AMIGA_1_ + G13 G 3 DFF * * -B----G- Hi Fast SM_AMIGA_2_ + G8 G 3 DFF * * AB---FG- Hi Fast SM_AMIGA_3_ D13 D 2 DFF * * -B-D--G- Hi Fast SM_AMIGA_4_ D6 D 2 DFF * * -B-D---- Hi Fast SM_AMIGA_5_ D2 D 3 DFF * * -B-D---- Hi Fast SM_AMIGA_6_ G6 G 2 DFF * * ---D--G- Hi Fast SM_AMIGA_7_ - B13 B 2 DFF * * -B------ Hi Fast SM_AMIGA_D_0_ - B9 B 2 DFF * * -B------ Hi Fast SM_AMIGA_D_1_ - G2 G 2 DFF * * -B----G- Hi Fast SM_AMIGA_D_2_ - G11 G 3 DFF * * ------G- Hi Fast cpu_est_0_ - G3 G 4 TFF * * ------G- Hi Fast cpu_est_1_ - G7 G 3 DFF * * ------G- Hi Fast cpu_est_2_ - H1 H 4 DFF * * ---D---H Hi Fast inst_AS_030_000_SYNC - A0 A 1 DFF * * ---D--GH Hi Fast inst_CLK_000_D - D14 D 1 DFF * * ------G- Hi Fast inst_CLK_000_DD + B6 B 2 DFF * * -B------ Hi Fast SM_AMIGA_D_0_ + B13 B 2 DFF * * -B------ Hi Fast SM_AMIGA_D_1_ + B9 B 2 DFF * * -B------ Hi Fast SM_AMIGA_D_2_ + G5 G 3 DFF * * ---D-FG- Hi Fast cpu_est_0_ + G2 G 4 TFF * * ---D-FG- Hi Fast cpu_est_1_ + G1 G 3 DFF * * ---D-FG- Hi Fast cpu_est_2_ + G15 G 1 DFF * * ---D---- Hi Fast cpu_est_d_0_ + G7 G 1 DFF * * ---D---- Hi Fast cpu_est_d_1_ + G3 G 1 DFF * * ---D---- Hi Fast cpu_est_d_2_ + G11 G 1 DFF * * ---D---- Hi Fast cpu_est_d_3_ + H5 H 4 DFF * * ---D---H Hi Fast inst_AS_030_000_SYNC + H1 H 1 DFF * * A--D-FGH Hi Fast inst_CLK_000_D + H13 H 1 DFF * * ---D--G- Hi Fast inst_CLK_000_DD G10 G 2 DFF * * ------GH Hi Fast inst_CLK_OUT_PRE - G14 G 2 DFF * * ------GH Hi Fast inst_DTACK_SYNC + A8 A 2 DFF * * A-----G- Hi Fast inst_DTACK_SYNC H9 H 1 DFF * * -B-----H Hi Fast inst_RISING_CLK_AMIGA - B6 B 1 DFF * * ------G- Hi Fast inst_VPA_D - G12 G 2 DFF * * ---D--GH Hi Fast inst_VPA_SYNC - D10 D 4 COM ---D---- Hi Fast un1_UDS_000_INT_0_sqmuxa_2_0 + A0 A 1 DFF * * A--D-F-- Hi Fast inst_VPA_D + F0 F 2 DFF * * -----FG- Hi Fast inst_VPA_SYNC ---------------------------------------------------------------------- Power : Hi = High @@ -445,53 +444,51 @@ Signals_Fanout_List ~~~~~~~~~~~~~~~~~~~ Signal Source : Fanout List ----------------------------------------------------------------------------- - A_30_{ C}: CIIN{ E} - A_29_{ C}: CIIN{ E} + FC_0_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} SIZE_1_{ I}: LDS_000{ D} - A_28_{ D}: CIIN{ E} - A_27_{ D}: CIIN{ E} A_31_{ C}: CIIN{ E} - A_26_{ D}: CIIN{ E} - A_25_{ D}: CIIN{ E} - A_24_{ D}: CIIN{ E} - A_23_{ I}: CIIN{ E} IPL_2_{ H}: IPL_030_2_{ B} - A_22_{ I}: CIIN{ E} - A_21_{ B}: CIIN{ E} - A_20_{ B}: CIIN{ E} - A_19_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} FC_1_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} - A_18_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} AS_030{ I}: DSACK_1_{ H} AS_000{ D} UDS_000{ D} : LDS_000{ D} BG_000{ D} FPU_CS{ H} - :inst_AS_030_000_SYNC{ H}inst_DTACK_SYNC{ G} inst_VPA_SYNC{ G} - A_17_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} - A_16_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} - DS_030{ B}: UDS_000{ D}un1_UDS_000_INT_0_sqmuxa_2_0{ D} + :inst_AS_030_000_SYNC{ H}inst_DTACK_SYNC{ A} inst_VPA_SYNC{ F} + DS_030{ B}: UDS_000{ D} LDS_000{ D} CPU_SPACE{. }: DSACK_0_{ H} DSACK_1_{ H} BG_000{ D} :inst_AS_030_000_SYNC{ H} BG_030{ D}: BG_000{ D} BGACK_000{ E}: BGACK_030{ H} FPU_CS{ H}inst_AS_030_000_SYNC{ H} CLK_030{. }: BG_000{ D} FPU_CS{ H}inst_AS_030_000_SYNC{ H} - CLK_000{. }: inst_CLK_000_D{ A}inst_RISING_CLK_AMIGA{ H} CLK_000_CNT_0_{ H} - : CLK_000_CNT_1_{ G} CLK_000_CNT_2_{ H} CLK_000_CNT_3_{ H} - : SM_AMIGA_1_{ G} SM_AMIGA_0_{ G} - A_0_{ H}: UDS_000{ D} LDS_000{ D} - IPL_1_{ G}: IPL_030_1_{ B} - VPA{. }: inst_VPA_D{ B} - IPL_0_{ H}: IPL_030_0_{ B} + CLK_000{. }: inst_CLK_000_D{ H}inst_RISING_CLK_AMIGA{ H} + SIZE_0_{ H}: LDS_000{ D} + A_30_{ C}: CIIN{ E} + A_29_{ C}: CIIN{ E} + A_28_{ D}: CIIN{ E} + A_27_{ D}: CIIN{ E} + A_26_{ D}: CIIN{ E} + A_25_{ D}: CIIN{ E} + VPA{. }: inst_VPA_D{ A} + A_24_{ D}: CIIN{ E} + A_23_{ I}: CIIN{ E} RST{. }: IPL_030_2_{ B} DSACK_1_{ H} AS_000{ D} : UDS_000{ D} LDS_000{ D} BG_000{ D} : BGACK_030{ H} FPU_CS{ H} DTACK{ D} - : IPL_030_1_{ B} IPL_030_0_{ B} VMA{ D} - : RESET{ B}inst_AS_030_000_SYNC{ H}inst_DTACK_SYNC{ G} - : inst_VPA_SYNC{ G} SM_AMIGA_6_{ D} SM_AMIGA_7_{ G} - : SM_AMIGA_4_{ D} SM_AMIGA_3_{ G} SM_AMIGA_5_{ D} - : SM_AMIGA_2_{ G} SM_AMIGA_1_{ G} SM_AMIGA_0_{ G} - : SM_AMIGA_D_0_{ B} SM_AMIGA_D_1_{ B} SM_AMIGA_D_2_{ G} - FC_0_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} - RW{ H}:AMIGA_BUS_DATA_DIR{ E} UDS_000{ D}un1_UDS_000_INT_0_sqmuxa_2_0{ D} - SIZE_0_{ H}: LDS_000{ D} + : VMA{ D} RESET{ B} IPL_030_1_{ B} + : IPL_030_0_{ B}inst_AS_030_000_SYNC{ H}inst_DTACK_SYNC{ A} + : inst_VPA_SYNC{ F} SM_AMIGA_6_{ D} SM_AMIGA_7_{ G} + : SM_AMIGA_1_{ G} SM_AMIGA_4_{ D} SM_AMIGA_3_{ G} + : SM_AMIGA_5_{ D} SM_AMIGA_2_{ G} SM_AMIGA_0_{ G} + : SM_AMIGA_D_0_{ B} SM_AMIGA_D_1_{ B} SM_AMIGA_D_2_{ B} + A_22_{ I}: CIIN{ E} + A_21_{ B}: CIIN{ E} + RW{ H}:AMIGA_BUS_DATA_DIR{ E} UDS_000{ D} LDS_000{ D} + A_20_{ B}: CIIN{ E} + A_19_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} + A_18_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} + A_17_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} + A_16_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} + A_0_{ H}: UDS_000{ D} LDS_000{ D} + IPL_1_{ G}: IPL_030_1_{ B} + IPL_0_{ H}: IPL_030_0_{ B} RN_IPL_030_2_{ C}: IPL_030_2_{ B} DSACK_1_{ I}: DTACK{ D} RN_DSACK_1_{ I}: DSACK_1_{ H} @@ -503,71 +500,63 @@ RN_DSACK_1_{ I}: DSACK_1_{ H} RN_BGACK_030{ I}: AS_000{ D} UDS_000{ D} LDS_000{ D} : BGACK_030{ H} DTACK{ D} RN_FPU_CS{ I}: BERR{ E} AVEC_EXP{ C} FPU_CS{ H} - DTACK{ E}:inst_DTACK_SYNC{ G} + DTACK{ E}:inst_DTACK_SYNC{ A} + RN_E{ H}: E{ G} VMA{ D} cpu_est_1_{ G} + : cpu_est_d_3_{ G} inst_VPA_SYNC{ F} cpu_est_2_{ G} + RN_VMA{ E}: VMA{ D} inst_VPA_SYNC{ F} RN_IPL_030_1_{ C}: IPL_030_1_{ B} RN_IPL_030_0_{ C}: IPL_030_0_{ B} - RN_E{ H}: E{ G} cpu_est_1_{ G} inst_VPA_SYNC{ G} - : cpu_est_2_{ G} SM_AMIGA_1_{ G} SM_AMIGA_0_{ G} - RN_VMA{ E}: VMA{ D} - cpu_est_1_{ H}: E{ G} cpu_est_1_{ G} inst_VPA_SYNC{ G} - : cpu_est_2_{ G} SM_AMIGA_1_{ G} SM_AMIGA_0_{ G} -inst_AS_030_000_SYNC{ I}: DSACK_1_{ H} AS_000{ D} UDS_000{ D} - :inst_AS_030_000_SYNC{ H} SM_AMIGA_6_{ D} SM_AMIGA_5_{ D} - :un1_UDS_000_INT_0_sqmuxa_2_0{ D} -inst_DTACK_SYNC{ H}: DSACK_1_{ H}inst_DTACK_SYNC{ G} SM_AMIGA_3_{ G} - : SM_AMIGA_2_{ G} SM_AMIGA_1_{ G} SM_AMIGA_0_{ G} - inst_VPA_D{ C}:inst_DTACK_SYNC{ G} inst_VPA_SYNC{ G} -inst_VPA_SYNC{ H}: DSACK_1_{ H} VMA{ D} inst_VPA_SYNC{ G} - : SM_AMIGA_3_{ G} SM_AMIGA_2_{ G} SM_AMIGA_1_{ G} - : SM_AMIGA_0_{ G} -inst_CLK_000_D{ B}: DSACK_1_{ H} AS_000{ D} UDS_000{ D} - : E{ G} VMA{ D} cpu_est_1_{ G} - :inst_DTACK_SYNC{ G} inst_VPA_SYNC{ G}inst_CLK_000_DD{ D} - : cpu_est_0_{ G} cpu_est_2_{ G} SM_AMIGA_6_{ D} - : SM_AMIGA_7_{ G}inst_RISING_CLK_AMIGA{ H} SM_AMIGA_4_{ D} - : SM_AMIGA_3_{ G} SM_AMIGA_5_{ D} CLK_000_CNT_0_{ H} - : CLK_000_CNT_1_{ G} CLK_000_CNT_2_{ H} CLK_000_CNT_3_{ H} - : SM_AMIGA_2_{ G} SM_AMIGA_1_{ G} SM_AMIGA_0_{ G} - :un1_UDS_000_INT_0_sqmuxa_2_0{ D} -inst_CLK_000_DD{ E}: E{ G} cpu_est_1_{ G} cpu_est_0_{ G} + cpu_est_0_{ H}: E{ G} VMA{ D} cpu_est_0_{ G} + : cpu_est_1_{ G} cpu_est_d_0_{ G} inst_VPA_SYNC{ F} : cpu_est_2_{ G} + cpu_est_1_{ H}: E{ G} VMA{ D} cpu_est_1_{ G} + : inst_VPA_SYNC{ F} cpu_est_d_1_{ G} cpu_est_2_{ G} +cpu_est_d_0_{ H}: VMA{ D} +cpu_est_d_3_{ H}: VMA{ D} +inst_AS_030_000_SYNC{ I}: AS_000{ D} UDS_000{ D} LDS_000{ D} + :inst_AS_030_000_SYNC{ H} SM_AMIGA_6_{ D} SM_AMIGA_5_{ D} +inst_DTACK_SYNC{ B}:inst_DTACK_SYNC{ A} SM_AMIGA_3_{ G} SM_AMIGA_2_{ G} + inst_VPA_D{ B}: VMA{ D}inst_DTACK_SYNC{ A} inst_VPA_SYNC{ F} +inst_VPA_SYNC{ G}: inst_VPA_SYNC{ F} SM_AMIGA_3_{ G} SM_AMIGA_2_{ G} +inst_CLK_000_D{ I}: DSACK_1_{ H} AS_000{ D} UDS_000{ D} + : LDS_000{ D} E{ G} VMA{ D} + : cpu_est_0_{ G} cpu_est_1_{ G}inst_DTACK_SYNC{ A} + : inst_VPA_SYNC{ F}inst_CLK_000_DD{ H} cpu_est_2_{ G} + : SM_AMIGA_6_{ D} SM_AMIGA_7_{ G}inst_RISING_CLK_AMIGA{ H} + : SM_AMIGA_1_{ G} SM_AMIGA_4_{ D} SM_AMIGA_3_{ G} + : SM_AMIGA_5_{ D} SM_AMIGA_2_{ G} SM_AMIGA_0_{ G} +inst_CLK_000_DD{ I}: AS_000{ D} UDS_000{ D} LDS_000{ D} + : E{ G} cpu_est_0_{ G} cpu_est_1_{ G} + : cpu_est_2_{ G} SM_AMIGA_6_{ D} SM_AMIGA_5_{ D} inst_CLK_OUT_PRE{ H}: DSACK_1_{ H} CLK_DIV_OUT{ G}inst_CLK_OUT_PRE{ G} - cpu_est_0_{ H}: E{ G} cpu_est_1_{ G} inst_VPA_SYNC{ G} - : cpu_est_0_{ G} cpu_est_2_{ G} SM_AMIGA_1_{ G} - : SM_AMIGA_0_{ G} - cpu_est_2_{ H}: E{ G} cpu_est_1_{ G} inst_VPA_SYNC{ G} - : cpu_est_2_{ G} SM_AMIGA_1_{ G} SM_AMIGA_0_{ G} + : SM_AMIGA_1_{ G} SM_AMIGA_0_{ G} +cpu_est_d_1_{ H}: VMA{ D} +cpu_est_d_2_{ H}: VMA{ D} + cpu_est_2_{ H}: E{ G} VMA{ D} cpu_est_1_{ G} + : inst_VPA_SYNC{ F} cpu_est_d_2_{ G} cpu_est_2_{ G} CLK_CNT_0_{ H}:inst_CLK_OUT_PRE{ G} CLK_CNT_0_{ G} SM_AMIGA_6_{ E}: CLK_EXP{ B} AS_000{ D} UDS_000{ D} - : BG_000{ D} SM_AMIGA_6_{ D} SM_AMIGA_5_{ D} - : SM_AMIGA_D_0_{ B}un1_UDS_000_INT_0_sqmuxa_2_0{ D} + : LDS_000{ D} BG_000{ D} SM_AMIGA_6_{ D} + : SM_AMIGA_5_{ D} SM_AMIGA_D_0_{ B} SM_AMIGA_7_{ H}: BG_000{ D} SM_AMIGA_6_{ D} SM_AMIGA_7_{ G} inst_RISING_CLK_AMIGA{ I}: IPL_030_2_{ B} BGACK_030{ H} IPL_030_1_{ B} : IPL_030_0_{ B} -SM_AMIGA_4_{ E}: CLK_EXP{ B} UDS_000{ D} SM_AMIGA_4_{ D} - : SM_AMIGA_3_{ G} SM_AMIGA_D_0_{ B} SM_AMIGA_D_1_{ B} - :un1_UDS_000_INT_0_sqmuxa_2_0{ D} -SM_AMIGA_3_{ H}: CLK_EXP{ B}inst_DTACK_SYNC{ G} inst_VPA_SYNC{ G} - : SM_AMIGA_3_{ G} SM_AMIGA_2_{ G} SM_AMIGA_D_2_{ G} -SM_AMIGA_5_{ E}: CLK_EXP{ B} UDS_000{ D} SM_AMIGA_4_{ D} - : SM_AMIGA_5_{ D} SM_AMIGA_D_1_{ B}un1_UDS_000_INT_0_sqmuxa_2_0{ D} -CLK_000_CNT_0_{ I}: DSACK_1_{ H} CLK_000_CNT_0_{ H} CLK_000_CNT_1_{ G} - : CLK_000_CNT_2_{ H} CLK_000_CNT_3_{ H} -CLK_000_CNT_1_{ H}: DSACK_1_{ H} CLK_000_CNT_1_{ G} CLK_000_CNT_2_{ H} - : CLK_000_CNT_3_{ H} -CLK_000_CNT_2_{ I}: DSACK_1_{ H} CLK_000_CNT_2_{ H} CLK_000_CNT_3_{ H} -CLK_000_CNT_3_{ I}: DSACK_1_{ H} CLK_000_CNT_3_{ H} -SM_AMIGA_2_{ H}: CLK_EXP{ B} SM_AMIGA_2_{ G} SM_AMIGA_1_{ G} - : SM_AMIGA_D_0_{ B} SM_AMIGA_D_2_{ G} -SM_AMIGA_1_{ H}: CLK_EXP{ B} SM_AMIGA_1_{ G} SM_AMIGA_0_{ G} - : SM_AMIGA_D_1_{ B} SM_AMIGA_D_2_{ G} -SM_AMIGA_0_{ H}: CLK_EXP{ B} DSACK_1_{ H} SM_AMIGA_7_{ G} - : SM_AMIGA_0_{ G} SM_AMIGA_D_0_{ B} SM_AMIGA_D_1_{ B} - : SM_AMIGA_D_2_{ G} +SM_AMIGA_1_{ H}: CLK_EXP{ B} DSACK_1_{ H} SM_AMIGA_1_{ G} + : SM_AMIGA_0_{ G} SM_AMIGA_D_1_{ B} SM_AMIGA_D_2_{ B} +SM_AMIGA_4_{ E}: CLK_EXP{ B} UDS_000{ D} LDS_000{ D} + : SM_AMIGA_4_{ D} SM_AMIGA_3_{ G} SM_AMIGA_D_0_{ B} + : SM_AMIGA_D_1_{ B} +SM_AMIGA_3_{ H}: CLK_EXP{ B}inst_DTACK_SYNC{ A} inst_VPA_SYNC{ F} + : SM_AMIGA_3_{ G} SM_AMIGA_2_{ G} SM_AMIGA_D_2_{ B} +SM_AMIGA_5_{ E}: CLK_EXP{ B} SM_AMIGA_4_{ D} SM_AMIGA_5_{ D} + : SM_AMIGA_D_1_{ B} +SM_AMIGA_2_{ H}: CLK_EXP{ B} SM_AMIGA_1_{ G} SM_AMIGA_2_{ G} + : SM_AMIGA_D_0_{ B} SM_AMIGA_D_2_{ B} +SM_AMIGA_0_{ H}: CLK_EXP{ B} SM_AMIGA_7_{ G} SM_AMIGA_0_{ G} + : SM_AMIGA_D_0_{ B} SM_AMIGA_D_1_{ B} SM_AMIGA_D_2_{ B} SM_AMIGA_D_0_{ C}: CLK_EXP{ B} SM_AMIGA_D_0_{ B} SM_AMIGA_D_1_{ C}: CLK_EXP{ B} SM_AMIGA_D_1_{ B} -SM_AMIGA_D_2_{ H}: CLK_EXP{ B} SM_AMIGA_D_2_{ G} -un1_UDS_000_INT_0_sqmuxa_2_0{ E}: LDS_000{ D} +SM_AMIGA_D_2_{ C}: CLK_EXP{ B} SM_AMIGA_D_2_{ B} ----------------------------------------------------------------------------- {.} : Indicates block location of signal @@ -577,14 +566,15 @@ Set_Reset_Summary ~~~~~~~~~~~~~~~~~ Block A -block level set pt : GND +block level set pt : !RST block level reset pt : GND Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ | | | | | AVEC -| * | S | BS | BR | inst_CLK_000_D +| * | A | | | inst_VPA_D +| * | S | BS | BR | inst_DTACK_SYNC | | | | | DS_030 | | | | | A_19_ | | | | | A_16_ @@ -608,9 +598,9 @@ Equations : | * | S | BS | BR | RN_IPL_030_0_ | * | S | BS | BR | RN_IPL_030_1_ | * | S | BS | BR | RN_IPL_030_2_ +| * | A | | | SM_AMIGA_D_2_ | * | A | | | SM_AMIGA_D_1_ | * | A | | | SM_AMIGA_D_0_ -| * | A | | | inst_VPA_D | | | | | A_29_ | | | | | A_30_ | | | | | A_31_ @@ -641,22 +631,20 @@ Equations : | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ | * | S | BS | BR | DTACK -| * | S | BS | BR | UDS_000 -| * | S | BS | BR | VMA | * | S | BS | BR | LDS_000 +| * | S | BS | BR | UDS_000 | * | S | BS | BR | BG_000 +| * | S | BS | BR | VMA | * | S | BS | BR | AS_000 | | | | | AMIGA_BUS_ENABLE | * | S | BR | BS | SM_AMIGA_4_ | * | S | BR | BS | SM_AMIGA_6_ +| * | S | BS | BR | RN_VMA | * | S | BS | BR | RN_AS_000 | * | S | BR | BS | SM_AMIGA_5_ -| * | S | BS | BR | RN_UDS_000 -| | | | | un1_UDS_000_INT_0_sqmuxa_2_0 -| * | S | BS | BR | RN_VMA -| * | S | BS | BR | RN_BG_000 | * | S | BS | BR | RN_LDS_000 -| * | A | | | inst_CLK_000_DD +| * | S | BS | BR | RN_UDS_000 +| * | S | BS | BR | RN_BG_000 | | | | | BGACK_000 @@ -673,12 +661,13 @@ Equations : Block F -block level set pt : -block level reset pt : +block level set pt : !RST +block level reset pt : GND Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ +| * | S | BS | BR | inst_VPA_SYNC | | | | | A_17_ | | | | | FC_1_ | | | | | FC_0_ @@ -694,21 +683,21 @@ Equations : +-----+-----+-----+-----+------------------------ | * | S | BS | BR | E | * | S | BS | BR | CLK_DIV_OUT -| * | A | | | SM_AMIGA_0_ -| * | A | | | inst_VPA_SYNC -| * | A | | | SM_AMIGA_1_ -| * | S | BS | BR | CLK_000_CNT_1_ -| * | A | | | SM_AMIGA_2_ | * | A | | | SM_AMIGA_3_ -| * | S | BS | BR | SM_AMIGA_D_2_ -| * | A | | | SM_AMIGA_7_ -| * | S | BS | BR | inst_CLK_OUT_PRE -| * | A | | | inst_DTACK_SYNC | * | S | BS | BR | cpu_est_1_ | * | S | BS | BR | RN_E +| * | A | | | SM_AMIGA_1_ | * | S | BS | BR | cpu_est_2_ | * | S | BS | BR | cpu_est_0_ +| * | A | | | SM_AMIGA_0_ +| * | A | | | SM_AMIGA_2_ +| * | A | | | SM_AMIGA_7_ +| * | S | BS | BR | inst_CLK_OUT_PRE | * | S | BS | BR | CLK_CNT_0_ +| * | S | BS | BR | cpu_est_d_2_ +| * | S | BS | BR | cpu_est_d_1_ +| * | S | BS | BR | cpu_est_d_3_ +| * | S | BS | BR | cpu_est_d_0_ | | | | | RW | | | | | SIZE_0_ | | | | | A_0_ @@ -727,14 +716,13 @@ Equations : | * | S | BS | BR | BGACK_030 | * | S | BS | BR | FPU_CS | | | | | DSACK_0_ +| * | A | | | inst_CLK_000_D | * | S | BS | BR | RN_FPU_CS | * | S | BS | BR | inst_AS_030_000_SYNC | * | S | BS | BR | RN_BGACK_030 -| * | A | | | CLK_000_CNT_0_ | * | A | | | inst_RISING_CLK_AMIGA +| * | A | | | inst_CLK_000_DD | * | S | BS | BR | RN_DSACK_1_ -| * | A | | | CLK_000_CNT_2_ -| * | A | | | CLK_000_CNT_3_ | | | | | AS_030 | | | | | A_22_ | | | | | A_23_ @@ -755,22 +743,22 @@ BLOCK_A_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx A0 ... ... mx A17 ... ... +mx A0 RST pin 86 mx A17 ... ... mx A1 ... ... mx A18 ... ... mx A2 ... ... mx A19 ... ... -mx A3 CLK_000 pin 11 mx A20 ... ... +mx A3 inst_DTACK_SYNC mcell A8 mx A20 ... ... mx A4 CLK_OSZI pin 61 mx A21 ... ... mx A5 ... ... mx A22 ... ... mx A6 ... ... mx A23 ... ... mx A7 ... ... mx A24 ... ... mx A8 ... ... mx A25 ... ... -mx A9 ... ... mx A26 ... ... -mx A10 ... ... mx A27 ... ... +mx A9 AS_030 pin 82 mx A26 ... ... +mx A10 VPA pin 36 mx A27 ... ... mx A11 ... ... mx A28 ... ... -mx A12 ... ... mx A29 ... ... -mx A13 ... ... mx A30 ... ... -mx A14 ... ... mx A31 ... ... -mx A15 ... ... mx A32 ... ... +mx A12 inst_CLK_000_D mcell H1 mx A29 ... ... +mx A13 SM_AMIGA_3_ mcell G8 mx A30 ... ... +mx A14 DTACK pin 30 mx A31 ... ... +mx A15 inst_VPA_D mcell A0 mx A32 ... ... mx A16 ... ... ---------------------------------------------------------------------------- @@ -779,23 +767,23 @@ BLOCK_B_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx B0 IPL_0_ pin 67 mx B17 ... ... +mx B0 RST pin 86 mx B17 ... ... mx B1 SM_AMIGA_4_ mcell D13 mx B18 ... ... -mx B2 ... ... mx B19 ... ... +mx B2 SM_AMIGA_D_0_ mcell B6 mx B19 ... ... mx B3 IPL_1_ pin 56 mx B20 ... ... -mx B4 SM_AMIGA_1_ mcell G1 mx B21 SM_AMIGA_D_0_ mcell B13 +mx B4 SM_AMIGA_5_ mcell D6 mx B21 SM_AMIGA_D_1_ mcell B13 mx B5inst_RISING_CLK_AMIGA mcell H9 mx B22 IPL_2_ pin 68 -mx B6 SM_AMIGA_D_1_ mcell B9 mx B23 SM_AMIGA_D_2_ mcell G2 -mx B7 ... ... mx B24 RST pin 86 +mx B6 SM_AMIGA_D_2_ mcell B9 mx B23 ... ... +mx B7 SM_AMIGA_1_ mcell G12 mx B24 ... ... mx B8 RN_IPL_030_0_ mcell B8 mx B25 ... ... -mx B9 SM_AMIGA_3_ mcell G13 mx B26 ... ... -mx B10 SM_AMIGA_2_ mcell G9 mx B27 RN_IPL_030_2_ mcell B4 -mx B11 ... ... mx B28 SM_AMIGA_0_ mcell G8 +mx B9 SM_AMIGA_2_ mcell G13 mx B26 ... ... +mx B10 SM_AMIGA_0_ mcell G9 mx B27 RN_IPL_030_2_ mcell B4 +mx B11 ... ... mx B28 SM_AMIGA_6_ mcell D2 mx B12 RN_IPL_030_1_ mcell B12 mx B29 CLK_OSZI pin 61 -mx B13 VPA pin 36 mx B30 SM_AMIGA_5_ mcell D6 +mx B13 SM_AMIGA_3_ mcell G8 mx B30 ... ... mx B14 ... ... mx B31 ... ... mx B15 ... ... mx B32 ... ... -mx B16 SM_AMIGA_6_ mcell D2 +mx B16 IPL_0_ pin 67 ---------------------------------------------------------------------------- @@ -827,23 +815,23 @@ BLOCK_D_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx D0 A_0_ pin 69 mx D17 DSACK_1_ pin 81 -mx D1 SM_AMIGA_4_ mcell D13 mx D18 DS_030 pin 98 -mx D2 RN_BG_000 mcell D1 mx D19 ... ... -mx D3 SM_AMIGA_6_ mcell D2 mx D20 RN_BGACK_030 mcell H4 -mx D4 SM_AMIGA_5_ mcell D6 mx D21 CPU_SPACE pin 14 -mx D5 RN_LDS_000 mcell D12 mx D22 BG_030 pin 21 +mx D0 RN_BGACK_030 mcell H4 mx D17 SIZE_0_ pin 70 +mx D1 SM_AMIGA_4_ mcell D13 mx D18 cpu_est_d_0_ mcell G15 +mx D2 RN_E mcell G4 mx D19 inst_CLK_000_D mcell H1 +mx D3 SM_AMIGA_6_ mcell D2 mx D20 CLK_030 pin 64 +mx D4 BG_030 pin 21 mx D21 RST pin 86 +mx D5 CPU_SPACE pin 14 mx D22 cpu_est_0_ mcell G5 mx D6 SIZE_1_ pin 79 mx D23 SM_AMIGA_7_ mcell G6 -mx D7 inst_VPA_SYNC mcell G12 mx D24 RST pin 86 -mx D8 RW pin 71 mx D25 ... ... -mx D9 AS_030 pin 82 mx D26 ... ... -mx D10 RN_VMA mcell D4 mx D27 ... ... -mx D11 RN_AS_000 mcell D5 mx D28 CLK_030 pin 64 -mx D12inst_AS_030_000_SYNC mcell H1 mx D29 CLK_OSZI pin 61 -mx D13 ... ... mx D30un1_UDS_000_INT_0_sqmuxa_2_0 mcell D10 -mx D14 SIZE_0_ pin 70 mx D31 ... ... -mx D15 inst_CLK_000_D mcell A0 mx D32 ... ... -mx D16 RN_UDS_000 mcell D8 +mx D7 RN_AS_000 mcell D5 mx D24 cpu_est_d_2_ mcell G3 +mx D8 cpu_est_d_1_ mcell G7 mx D25 RW pin 71 +mx D9 AS_030 pin 82 mx D26 cpu_est_d_3_ mcell G11 +mx D10 DSACK_1_ pin 81 mx D27 RN_BG_000 mcell D1 +mx D11 RN_UDS_000 mcell D12 mx D28 inst_CLK_000_DD mcell H13 +mx D12 DS_030 pin 98 mx D29 inst_VPA_D mcell A0 +mx D13inst_AS_030_000_SYNC mcell H5 mx D30 SM_AMIGA_5_ mcell D6 +mx D14 RN_VMA mcell D4 mx D31 cpu_est_1_ mcell G2 +mx D15 A_0_ pin 69 mx D32 cpu_est_2_ mcell G1 +mx D16 RN_LDS_000 mcell D8 ---------------------------------------------------------------------------- @@ -871,26 +859,50 @@ mx E16 ... ... ---------------------------------------------------------------------------- +BLOCK_F_LOGIC_ARRAY_FANIN +~~~~~~~~~~~~~~~~~~~~~~~~~ +CSM Signal Source CSM Signal Source +------------------------------------ ------------------------------------ +mx F0 RST pin 86 mx F17 ... ... +mx F1 ... ... mx F18 ... ... +mx F2 RN_E mcell G4 mx F19 ... ... +mx F3 cpu_est_0_ mcell G5 mx F20 ... ... +mx F4 CLK_OSZI pin 61 mx F21 ... ... +mx F5 inst_VPA_SYNC mcell F0 mx F22 ... ... +mx F6 ... ... mx F23 cpu_est_1_ mcell G2 +mx F7 ... ... mx F24 cpu_est_2_ mcell G1 +mx F8 ... ... mx F25 ... ... +mx F9 AS_030 pin 82 mx F26 ... ... +mx F10 RN_VMA mcell D4 mx F27 ... ... +mx F11 ... ... mx F28 ... ... +mx F12 inst_CLK_000_D mcell H1 mx F29 ... ... +mx F13 SM_AMIGA_3_ mcell G8 mx F30 ... ... +mx F14 ... ... mx F31 ... ... +mx F15 inst_VPA_D mcell A0 mx F32 ... ... +mx F16 ... ... +---------------------------------------------------------------------------- + + BLOCK_G_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx G0 RST pin 86 mx G17 inst_CLK_000_DD mcell D14 -mx G1 SM_AMIGA_4_ mcell D13 mx G18 CLK_CNT_0_ mcell G15 -mx G2 inst_VPA_D mcell B6 mx G19 AS_030 pin 82 -mx G3 CLK_000 pin 11 mx G20 ... ... +mx G0 RST pin 86 mx G17 ... ... +mx G1 SM_AMIGA_4_ mcell D13 mx G18 ... ... +mx G2 RN_E mcell G4 mx G19 inst_CLK_000_D mcell H1 +mx G3 inst_DTACK_SYNC mcell A8 mx G20 ... ... mx G4 CLK_OSZI pin 61 mx G21 ... ... -mx G5 cpu_est_1_ mcell G3 mx G22inst_CLK_OUT_PRE mcell G10 +mx G5 inst_VPA_SYNC mcell F0 mx G22inst_CLK_OUT_PRE mcell G10 mx G6 ... ... mx G23 SM_AMIGA_7_ mcell G6 -mx G7 RN_AS_000 mcell D5 mx G24 SM_AMIGA_1_ mcell G1 -mx G8 cpu_est_2_ mcell G7 mx G25 ... ... -mx G9 DTACK pin 30 mx G26 inst_DTACK_SYNC mcell G14 -mx G10 SM_AMIGA_2_ mcell G9 mx G27 CLK_000_CNT_0_ mcell H5 -mx G11 RN_E mcell G4 mx G28 SM_AMIGA_0_ mcell G8 -mx G12 SM_AMIGA_3_ mcell G13 mx G29 ... ... -mx G13 cpu_est_0_ mcell G11 mx G30 ... ... -mx G14 inst_VPA_SYNC mcell G12 mx G31 SM_AMIGA_D_2_ mcell G2 -mx G15 inst_CLK_000_D mcell A0 mx G32 CLK_000_CNT_1_ mcell G5 +mx G7 inst_CLK_000_DD mcell H13 mx G24 cpu_est_2_ mcell G1 +mx G8 ... ... mx G25 ... ... +mx G9 SM_AMIGA_2_ mcell G13 mx G26 ... ... +mx G10 CLK_CNT_0_ mcell G14 mx G27 ... ... +mx G11 RN_AS_000 mcell D5 mx G28 ... ... +mx G12 SM_AMIGA_0_ mcell G9 mx G29 ... ... +mx G13 SM_AMIGA_3_ mcell G8 mx G30 ... ... +mx G14 SM_AMIGA_1_ mcell G12 mx G31 cpu_est_1_ mcell G2 +mx G15 ... ... mx G32 cpu_est_0_ mcell G5 mx G16 ... ... ---------------------------------------------------------------------------- @@ -899,22 +911,22 @@ BLOCK_H_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx H0 RST pin 86 mx H17 FC_0_ pin 57 +mx H0 RST pin 86 mx H17 A_18_ pin 95 mx H1 FC_1_ pin 58 mx H18 BGACK_000 pin 28 -mx H2 ... ... mx H19 CLK_000_CNT_2_ mcell H13 -mx H3 RN_DSACK_1_ mcell H8 mx H20 CLK_030 pin 64 -mx H4 A_18_ pin 95 mx H21 CLK_OSZI pin 61 +mx H2 ... ... mx H19 ... ... +mx H3 CLK_000 pin 11 mx H20 CLK_030 pin 64 +mx H4inst_AS_030_000_SYNC mcell H5 mx H21 CLK_OSZI pin 61 mx H5 CPU_SPACE pin 14 mx H22inst_CLK_OUT_PRE mcell G10 -mx H6 A_16_ pin 96 mx H23 RN_BGACK_030 mcell H4 -mx H7 inst_VPA_SYNC mcell G12 mx H24 CLK_000 pin 11 +mx H6 FC_0_ pin 57 mx H23 RN_BGACK_030 mcell H4 +mx H7 SM_AMIGA_1_ mcell G12 mx H24 ... ... mx H8 A_17_ pin 59 mx H25 ... ... mx H9 AS_030 pin 82 mx H26 ... ... -mx H10inst_AS_030_000_SYNC mcell H1 mx H27inst_RISING_CLK_AMIGA mcell H9 -mx H11 inst_DTACK_SYNC mcell G14 mx H28 SM_AMIGA_0_ mcell G8 +mx H10 inst_CLK_000_D mcell H1 mx H27inst_RISING_CLK_AMIGA mcell H9 +mx H11 A_16_ pin 96 mx H28 ... ... mx H12 A_19_ pin 97 mx H29 ... ... -mx H13 CLK_000_CNT_0_ mcell H5 mx H30 RN_FPU_CS mcell H0 -mx H14 CLK_000_CNT_3_ mcell H2 mx H31 ... ... -mx H15 inst_CLK_000_D mcell A0 mx H32 CLK_000_CNT_1_ mcell G5 +mx H13 RN_DSACK_1_ mcell H8 mx H30 RN_FPU_CS mcell H0 +mx H14 ... ... mx H31 ... ... +mx H15 ... ... mx H32 ... ... mx H16 ... ... ---------------------------------------------------------------------------- @@ -937,30 +949,30 @@ PostFit_Equations 1 0 1 Pin AVEC 0 0 1 Pin AVEC_EXP 1 1 1 Pin AVEC_EXP.OE - 1 0 1 Pin DSACK_0_ - 1 1 1 Pin DSACK_0_.OE 0 0 1 Pin AMIGA_BUS_ENABLE 1 1 1 Pin AMIGA_BUS_DATA_DIR 1 0 1 Pin AMIGA_BUS_ENABLE_LOW 1 4 1 Pin CIIN 1 8 1 Pin CIIN.OE + 1 0 1 Pin DSACK_0_ + 1 1 1 Pin DSACK_0_.OE 2 3 1 Pin IPL_030_2_.D 1 1 1 Pin IPL_030_2_.AP 1 1 1 Pin IPL_030_2_.C 1 1 1 Pin DSACK_1_.OE - 9 12 1 Pin DSACK_1_.D- + 2 5 1 Pin DSACK_1_.D- 1 1 1 Pin DSACK_1_.AP 1 1 1 Pin DSACK_1_.C 1 1 1 Pin AS_000.OE - 2 5 1 Pin AS_000.D- + 2 6 1 Pin AS_000.D- 1 1 1 Pin AS_000.AP 1 1 1 Pin AS_000.C 1 1 1 Pin UDS_000.OE - 11 10 1 Pin UDS_000.D- + 8 10 1 Pin UDS_000.D- 1 1 1 Pin UDS_000.AP 1 1 1 Pin UDS_000.C 1 1 1 Pin LDS_000.OE - 3 6 1 Pin LDS_000.D + 12 12 1 Pin LDS_000.D- 1 1 1 Pin LDS_000.AP 1 1 1 Pin LDS_000.C 3 7 1 Pin BG_000.D- @@ -978,21 +990,27 @@ PostFit_Equations 1 2 1 Pin DTACK.D- 1 1 1 Pin DTACK.AP 1 1 1 Pin DTACK.C + 3 6 1 Pin E.T + 1 1 1 Pin E.C + 1 1 1 Pin VMA.AP + 2 12 1 Pin VMA.T + 1 1 1 Pin VMA.C + 1 1 1 Pin RESET.D + 1 1 1 Pin RESET.C 2 3 1 Pin IPL_030_1_.D 1 1 1 Pin IPL_030_1_.AP 1 1 1 Pin IPL_030_1_.C 2 3 1 Pin IPL_030_0_.D 1 1 1 Pin IPL_030_0_.AP 1 1 1 Pin IPL_030_0_.C - 3 6 1 Pin E.T - 1 1 1 Pin E.C - 3 4 1 Pin VMA.D - 1 1 1 Pin VMA.AP - 1 1 1 Pin VMA.C - 1 1 1 Pin RESET.D - 1 1 1 Pin RESET.C + 3 3 1 Node cpu_est_0_.D + 1 1 1 Node cpu_est_0_.C 4 6 1 Node cpu_est_1_.T 1 1 1 Node cpu_est_1_.C + 1 1 1 Node cpu_est_d_0_.D + 1 1 1 Node cpu_est_d_0_.C + 1 1 1 Node cpu_est_d_3_.D + 1 1 1 Node cpu_est_d_3_.C 4 11 1 Node inst_AS_030_000_SYNC.D 1 1 1 Node inst_AS_030_000_SYNC.AP 1 1 1 Node inst_AS_030_000_SYNC.C @@ -1001,7 +1019,7 @@ PostFit_Equations 1 1 1 Node inst_DTACK_SYNC.C 1 1 1 Node inst_VPA_D.D 1 1 1 Node inst_VPA_D.C - 2 9 1 Node inst_VPA_SYNC.D- + 2 10 1 Node inst_VPA_SYNC.D- 1 1 1 Node inst_VPA_SYNC.AP 1 1 1 Node inst_VPA_SYNC.C 1 1 1 Node inst_CLK_000_D.D @@ -1010,21 +1028,26 @@ PostFit_Equations 1 1 1 Node inst_CLK_000_DD.C 2 2 1 Node inst_CLK_OUT_PRE.D 1 1 1 Node inst_CLK_OUT_PRE.C - 3 3 1 Node cpu_est_0_.D - 1 1 1 Node cpu_est_0_.C + 1 1 1 Node cpu_est_d_1_.D + 1 1 1 Node cpu_est_d_1_.C + 1 1 1 Node cpu_est_d_2_.D + 1 1 1 Node cpu_est_d_2_.C 3 6 1 NodeX1 cpu_est_2_.D.X1 1 1 1 NodeX2 cpu_est_2_.D.X2 1 1 1 Node cpu_est_2_.C 1 1 1 Node CLK_CNT_0_.D 1 1 1 Node CLK_CNT_0_.C 1 1 1 Node SM_AMIGA_6_.AR - 3 4 1 Node SM_AMIGA_6_.D + 3 5 1 Node SM_AMIGA_6_.D- 1 1 1 Node SM_AMIGA_6_.C 2 4 1 Node SM_AMIGA_7_.D 1 1 1 Node SM_AMIGA_7_.AP 1 1 1 Node SM_AMIGA_7_.C 1 2 1 Node inst_RISING_CLK_AMIGA.D 1 1 1 Node inst_RISING_CLK_AMIGA.C + 1 1 1 Node SM_AMIGA_1_.AR + 3 4 1 Node SM_AMIGA_1_.D + 1 1 1 Node SM_AMIGA_1_.C 1 1 1 Node SM_AMIGA_4_.AR 2 3 1 Node SM_AMIGA_4_.D 1 1 1 Node SM_AMIGA_4_.C @@ -1032,24 +1055,13 @@ PostFit_Equations 3 5 1 Node SM_AMIGA_3_.D 1 1 1 Node SM_AMIGA_3_.C 1 1 1 Node SM_AMIGA_5_.AR - 2 4 1 Node SM_AMIGA_5_.D + 2 5 1 Node SM_AMIGA_5_.D 1 1 1 Node SM_AMIGA_5_.C - 2 3 1 Node CLK_000_CNT_0_.D- - 1 1 1 Node CLK_000_CNT_0_.C - 4 4 1 Node CLK_000_CNT_1_.D - 1 1 1 Node CLK_000_CNT_1_.C - 5 5 1 Node CLK_000_CNT_2_.D- - 1 1 1 Node CLK_000_CNT_2_.C - 4 6 1 Node CLK_000_CNT_3_.T - 1 1 1 Node CLK_000_CNT_3_.C 1 1 1 Node SM_AMIGA_2_.AR 3 5 1 Node SM_AMIGA_2_.D 1 1 1 Node SM_AMIGA_2_.C - 1 1 1 Node SM_AMIGA_1_.AR - 4 10 1 Node SM_AMIGA_1_.D- - 1 1 1 Node SM_AMIGA_1_.C 1 1 1 Node SM_AMIGA_0_.AR - 4 11 1 Node SM_AMIGA_0_.D + 3 5 1 Node SM_AMIGA_0_.D 1 1 1 Node SM_AMIGA_0_.C 2 6 1 Node SM_AMIGA_D_0_.D- 1 1 1 Node SM_AMIGA_D_0_.C @@ -1057,11 +1069,10 @@ PostFit_Equations 1 1 1 Node SM_AMIGA_D_1_.C 2 6 1 Node SM_AMIGA_D_2_.D- 1 1 1 Node SM_AMIGA_D_2_.C - 4 7 1 Node un1_UDS_000_INT_0_sqmuxa_2_0 ========= - 214 P-Term Total: 214 + 195 P-Term Total: 195 Total Pins: 59 - Total Nodes: 28 + Total Nodes: 27 Average P-Term/Output: 2 @@ -1075,15 +1086,15 @@ CLK_EXP.X1 = (SM_AMIGA_0_.Q # SM_AMIGA_6_.Q & !SM_AMIGA_D_0_.Q # SM_AMIGA_4_.Q & !SM_AMIGA_D_0_.Q # SM_AMIGA_2_.Q & !SM_AMIGA_D_0_.Q + # SM_AMIGA_1_.Q & !SM_AMIGA_D_1_.Q # SM_AMIGA_4_.Q & !SM_AMIGA_D_1_.Q # SM_AMIGA_5_.Q & !SM_AMIGA_D_1_.Q - # SM_AMIGA_1_.Q & !SM_AMIGA_D_1_.Q + # SM_AMIGA_1_.Q & !SM_AMIGA_D_2_.Q # SM_AMIGA_3_.Q & !SM_AMIGA_D_2_.Q # SM_AMIGA_2_.Q & !SM_AMIGA_D_2_.Q - # SM_AMIGA_1_.Q & !SM_AMIGA_D_2_.Q # !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q & SM_AMIGA_D_0_.Q - # !SM_AMIGA_4_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_1_.Q & SM_AMIGA_D_1_.Q - # !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & !SM_AMIGA_1_.Q & SM_AMIGA_D_2_.Q); + # !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_5_.Q & SM_AMIGA_D_1_.Q + # !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & SM_AMIGA_D_2_.Q); CLK_EXP.X2 = (SM_AMIGA_0_.Q & SM_AMIGA_D_0_.Q & SM_AMIGA_D_1_.Q & SM_AMIGA_D_2_.Q); @@ -1093,10 +1104,6 @@ AVEC_EXP = (0); AVEC_EXP.OE = (!FPU_CS.Q); -DSACK_0_ = (1); - -DSACK_0_.OE = (!CPU_SPACE); - AMIGA_BUS_ENABLE = (0); AMIGA_BUS_DATA_DIR = (!RW); @@ -1107,8 +1114,12 @@ CIIN = (A_23_ & A_22_ & A_21_ & A_20_); CIIN.OE = (!A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_); +DSACK_0_ = (1); + +DSACK_0_.OE = (!CPU_SPACE); + IPL_030_2_.D = (IPL_2_ & inst_RISING_CLK_AMIGA.Q - # !inst_RISING_CLK_AMIGA.Q & IPL_030_2_.Q); + # IPL_030_2_.Q & !inst_RISING_CLK_AMIGA.Q); IPL_030_2_.AP = (!RST); @@ -1117,14 +1128,7 @@ IPL_030_2_.C = (CLK_OSZI); DSACK_1_.OE = (!CPU_SPACE); !DSACK_1_.D = (!AS_030 & !DSACK_1_.Q - # !inst_AS_030_000_SYNC.Q & !inst_DTACK_SYNC.Q & !inst_CLK_000_D.Q & inst_CLK_OUT_PRE.Q & CLK_000_CNT_0_.Q & SM_AMIGA_0_.Q - # !inst_AS_030_000_SYNC.Q & !inst_VPA_SYNC.Q & !inst_CLK_000_D.Q & inst_CLK_OUT_PRE.Q & CLK_000_CNT_0_.Q & SM_AMIGA_0_.Q - # !inst_AS_030_000_SYNC.Q & !inst_DTACK_SYNC.Q & !inst_CLK_000_D.Q & inst_CLK_OUT_PRE.Q & CLK_000_CNT_1_.Q & SM_AMIGA_0_.Q - # !inst_AS_030_000_SYNC.Q & !inst_VPA_SYNC.Q & !inst_CLK_000_D.Q & inst_CLK_OUT_PRE.Q & CLK_000_CNT_1_.Q & SM_AMIGA_0_.Q - # !inst_AS_030_000_SYNC.Q & !inst_DTACK_SYNC.Q & !inst_CLK_000_D.Q & inst_CLK_OUT_PRE.Q & CLK_000_CNT_2_.Q & SM_AMIGA_0_.Q - # !inst_AS_030_000_SYNC.Q & !inst_VPA_SYNC.Q & !inst_CLK_000_D.Q & inst_CLK_OUT_PRE.Q & CLK_000_CNT_2_.Q & SM_AMIGA_0_.Q - # !inst_AS_030_000_SYNC.Q & !inst_DTACK_SYNC.Q & !inst_CLK_000_D.Q & inst_CLK_OUT_PRE.Q & CLK_000_CNT_3_.Q & SM_AMIGA_0_.Q - # !inst_AS_030_000_SYNC.Q & !inst_VPA_SYNC.Q & !inst_CLK_000_D.Q & inst_CLK_OUT_PRE.Q & CLK_000_CNT_3_.Q & SM_AMIGA_0_.Q); + # !inst_CLK_000_D.Q & inst_CLK_OUT_PRE.Q & SM_AMIGA_1_.Q); DSACK_1_.AP = (!RST); @@ -1133,7 +1137,7 @@ DSACK_1_.C = (CLK_OSZI); AS_000.OE = (BGACK_030.Q); !AS_000.D = (!AS_030 & !AS_000.Q - # !inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & SM_AMIGA_6_.Q); + # !inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & SM_AMIGA_6_.Q); AS_000.AP = (!RST); @@ -1142,16 +1146,13 @@ AS_000.C = (CLK_OSZI); UDS_000.OE = (BGACK_030.Q); !UDS_000.D = (!AS_030 & DS_030 & !UDS_000.Q + # !AS_030 & !inst_CLK_000_D.Q & !UDS_000.Q + # !AS_030 & RW & inst_AS_030_000_SYNC.Q & !UDS_000.Q + # !AS_030 & RW & inst_CLK_000_DD.Q & !UDS_000.Q + # !AS_030 & RW & !SM_AMIGA_6_.Q & !UDS_000.Q # !AS_030 & !RW & !UDS_000.Q & !SM_AMIGA_4_.Q - # !DS_030 & RW & !A_0_ & SM_AMIGA_5_.Q - # !AS_030 & !RW & !UDS_000.Q & SM_AMIGA_5_.Q - # !AS_030 & !inst_CLK_000_D.Q & !UDS_000.Q & !SM_AMIGA_5_.Q - # !AS_030 & !RW & !inst_AS_030_000_SYNC.Q & SM_AMIGA_6_.Q & !UDS_000.Q - # !AS_030 & RW & inst_AS_030_000_SYNC.Q & !UDS_000.Q & !SM_AMIGA_5_.Q - # !AS_030 & RW & !SM_AMIGA_6_.Q & !UDS_000.Q & !SM_AMIGA_5_.Q - # !DS_030 & RW & !A_0_ & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & SM_AMIGA_6_.Q - # !DS_030 & !RW & !A_0_ & inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & SM_AMIGA_4_.Q & !SM_AMIGA_5_.Q - # !DS_030 & !RW & !A_0_ & inst_CLK_000_D.Q & !SM_AMIGA_6_.Q & SM_AMIGA_4_.Q & !SM_AMIGA_5_.Q); + # !DS_030 & !RW & !A_0_ & inst_CLK_000_D.Q & SM_AMIGA_4_.Q + # !DS_030 & RW & !A_0_ & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & SM_AMIGA_6_.Q); UDS_000.AP = (!RST); @@ -1159,9 +1160,18 @@ UDS_000.C = (CLK_OSZI); LDS_000.OE = (BGACK_030.Q); -LDS_000.D = (AS_030 & !un1_UDS_000_INT_0_sqmuxa_2_0 - # LDS_000.Q & !un1_UDS_000_INT_0_sqmuxa_2_0 - # !SIZE_1_ & SIZE_0_ & !A_0_ & un1_UDS_000_INT_0_sqmuxa_2_0); +!LDS_000.D = (!AS_030 & DS_030 & !LDS_000.Q + # !AS_030 & !inst_CLK_000_D.Q & !LDS_000.Q + # !AS_030 & RW & inst_AS_030_000_SYNC.Q & !LDS_000.Q + # !AS_030 & RW & inst_CLK_000_DD.Q & !LDS_000.Q + # !AS_030 & RW & !SM_AMIGA_6_.Q & !LDS_000.Q + # !AS_030 & !RW & !LDS_000.Q & !SM_AMIGA_4_.Q + # SIZE_1_ & !DS_030 & !RW & inst_CLK_000_D.Q & SM_AMIGA_4_.Q + # !DS_030 & !RW & !SIZE_0_ & inst_CLK_000_D.Q & SM_AMIGA_4_.Q + # !DS_030 & !RW & A_0_ & inst_CLK_000_D.Q & SM_AMIGA_4_.Q + # SIZE_1_ & !DS_030 & RW & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & SM_AMIGA_6_.Q + # !DS_030 & RW & !SIZE_0_ & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & SM_AMIGA_6_.Q + # !DS_030 & RW & A_0_ & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & SM_AMIGA_6_.Q); LDS_000.AP = (!RST); @@ -1201,45 +1211,58 @@ DTACK.AP = (!RST); DTACK.C = (CLK_OSZI); -IPL_030_1_.D = (IPL_1_ & inst_RISING_CLK_AMIGA.Q - # !inst_RISING_CLK_AMIGA.Q & IPL_030_1_.Q); - -IPL_030_1_.AP = (!RST); - -IPL_030_1_.C = (CLK_OSZI); - -IPL_030_0_.D = (IPL_0_ & inst_RISING_CLK_AMIGA.Q - # !inst_RISING_CLK_AMIGA.Q & IPL_030_0_.Q); - -IPL_030_0_.AP = (!RST); - -IPL_030_0_.C = (CLK_OSZI); - -E.T = (E.Q & cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & cpu_est_0_.Q & cpu_est_2_.Q - # !E.Q & cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & cpu_est_0_.Q & !cpu_est_2_.Q - # !E.Q & !cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & !cpu_est_0_.Q & !cpu_est_2_.Q); +E.T = (E.Q & cpu_est_0_.Q & cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & cpu_est_2_.Q + # !E.Q & cpu_est_0_.Q & cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & !cpu_est_2_.Q + # !E.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & !cpu_est_2_.Q); E.C = (CLK_OSZI); -VMA.D = (VMA.Q & inst_VPA_SYNC.Q - # VMA.Q & inst_CLK_000_D.Q - # AS_000.Q & inst_CLK_000_D.Q); - VMA.AP = (!RST); +VMA.T = (!VMA.Q & !cpu_est_d_0_.Q & !cpu_est_d_3_.Q & AS_000.Q & inst_CLK_000_D.Q & cpu_est_d_1_.Q & cpu_est_d_2_.Q + # !E.Q & VMA.Q & cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & !inst_CLK_000_D.Q & cpu_est_2_.Q); + VMA.C = (CLK_OSZI); RESET.D = (RST); RESET.C = (CLK_OSZI); -cpu_est_1_.T = (E.Q & !cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & !cpu_est_0_.Q - # !E.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & cpu_est_0_.Q & cpu_est_2_.Q +IPL_030_1_.D = (IPL_1_ & inst_RISING_CLK_AMIGA.Q + # IPL_030_1_.Q & !inst_RISING_CLK_AMIGA.Q); + +IPL_030_1_.AP = (!RST); + +IPL_030_1_.C = (CLK_OSZI); + +IPL_030_0_.D = (IPL_0_ & inst_RISING_CLK_AMIGA.Q + # IPL_030_0_.Q & !inst_RISING_CLK_AMIGA.Q); + +IPL_030_0_.AP = (!RST); + +IPL_030_0_.C = (CLK_OSZI); + +cpu_est_0_.D = (cpu_est_0_.Q & !inst_CLK_000_D.Q + # cpu_est_0_.Q & inst_CLK_000_DD.Q + # !cpu_est_0_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q); + +cpu_est_0_.C = (CLK_OSZI); + +cpu_est_1_.T = (E.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q + # !E.Q & cpu_est_0_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & cpu_est_2_.Q # !E.Q & !cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & !cpu_est_2_.Q - # E.Q & cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & cpu_est_0_.Q & !cpu_est_2_.Q); + # E.Q & cpu_est_0_.Q & cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & !cpu_est_2_.Q); cpu_est_1_.C = (CLK_OSZI); +cpu_est_d_0_.D = (cpu_est_0_.Q); + +cpu_est_d_0_.C = (CLK_OSZI); + +cpu_est_d_3_.D = (E.Q); + +cpu_est_d_3_.C = (CLK_OSZI); + inst_AS_030_000_SYNC.D = (AS_030 # CPU_SPACE & CLK_030 # !CLK_030 & inst_AS_030_000_SYNC.Q @@ -1261,7 +1284,7 @@ inst_VPA_D.D = (VPA); inst_VPA_D.C = (CLK_OSZI); !inst_VPA_SYNC.D = (!AS_030 & !inst_VPA_SYNC.Q - # !E.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_D.Q & cpu_est_0_.Q & cpu_est_2_.Q & SM_AMIGA_3_.Q); + # E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_D.Q & cpu_est_2_.Q & SM_AMIGA_3_.Q); inst_VPA_SYNC.AP = (!RST); @@ -1280,15 +1303,17 @@ inst_CLK_OUT_PRE.D = (!inst_CLK_OUT_PRE.Q & CLK_CNT_0_.Q inst_CLK_OUT_PRE.C = (CLK_OSZI); -cpu_est_0_.D = (!inst_CLK_000_D.Q & cpu_est_0_.Q - # inst_CLK_000_DD.Q & cpu_est_0_.Q - # inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & !cpu_est_0_.Q); +cpu_est_d_1_.D = (cpu_est_1_.Q); -cpu_est_0_.C = (CLK_OSZI); +cpu_est_d_1_.C = (CLK_OSZI); -cpu_est_2_.D.X1 = (E.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & cpu_est_0_.Q & !cpu_est_2_.Q - # !cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & !cpu_est_0_.Q & !cpu_est_2_.Q - # !E.Q & !cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & cpu_est_0_.Q & cpu_est_2_.Q); +cpu_est_d_2_.D = (cpu_est_2_.Q); + +cpu_est_d_2_.C = (CLK_OSZI); + +cpu_est_2_.D.X1 = (E.Q & cpu_est_0_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & !cpu_est_2_.Q + # !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & !cpu_est_2_.Q + # !E.Q & cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & cpu_est_2_.Q); cpu_est_2_.D.X2 = (cpu_est_2_.Q); @@ -1300,9 +1325,9 @@ CLK_CNT_0_.C = (CLK_OSZI); SM_AMIGA_6_.AR = (!RST); -SM_AMIGA_6_.D = (inst_AS_030_000_SYNC.Q & SM_AMIGA_6_.Q - # !inst_CLK_000_D.Q & SM_AMIGA_6_.Q - # !inst_CLK_000_D.Q & SM_AMIGA_7_.Q); +!SM_AMIGA_6_.D = (inst_CLK_000_D.Q & SM_AMIGA_7_.Q + # !SM_AMIGA_6_.Q & !SM_AMIGA_7_.Q + # !inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q); SM_AMIGA_6_.C = (CLK_OSZI); @@ -1317,6 +1342,14 @@ inst_RISING_CLK_AMIGA.D = (CLK_000 & !inst_CLK_000_D.Q); inst_RISING_CLK_AMIGA.C = (CLK_OSZI); +SM_AMIGA_1_.AR = (!RST); + +SM_AMIGA_1_.D = (inst_CLK_000_D.Q & SM_AMIGA_1_.Q + # !inst_CLK_OUT_PRE.Q & SM_AMIGA_1_.Q + # inst_CLK_000_D.Q & SM_AMIGA_2_.Q); + +SM_AMIGA_1_.C = (CLK_OSZI); + SM_AMIGA_4_.AR = (!RST); SM_AMIGA_4_.D = (!inst_CLK_000_D.Q & SM_AMIGA_4_.Q @@ -1335,37 +1368,10 @@ SM_AMIGA_3_.C = (CLK_OSZI); SM_AMIGA_5_.AR = (!RST); SM_AMIGA_5_.D = (inst_CLK_000_D.Q & SM_AMIGA_5_.Q - # !inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & SM_AMIGA_6_.Q); + # !inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & SM_AMIGA_6_.Q); SM_AMIGA_5_.C = (CLK_OSZI); -!CLK_000_CNT_0_.D = (CLK_000 & inst_CLK_000_D.Q & CLK_000_CNT_0_.Q - # !CLK_000 & !inst_CLK_000_D.Q & CLK_000_CNT_0_.Q); - -CLK_000_CNT_0_.C = (CLK_OSZI); - -CLK_000_CNT_1_.D = (CLK_000 & inst_CLK_000_D.Q & !CLK_000_CNT_0_.Q & CLK_000_CNT_1_.Q - # !CLK_000 & !inst_CLK_000_D.Q & !CLK_000_CNT_0_.Q & CLK_000_CNT_1_.Q - # CLK_000 & inst_CLK_000_D.Q & CLK_000_CNT_0_.Q & !CLK_000_CNT_1_.Q - # !CLK_000 & !inst_CLK_000_D.Q & CLK_000_CNT_0_.Q & !CLK_000_CNT_1_.Q); - -CLK_000_CNT_1_.C = (CLK_OSZI); - -!CLK_000_CNT_2_.D = (!CLK_000 & inst_CLK_000_D.Q - # CLK_000 & !inst_CLK_000_D.Q - # !CLK_000_CNT_0_.Q & !CLK_000_CNT_2_.Q - # !CLK_000_CNT_1_.Q & !CLK_000_CNT_2_.Q - # CLK_000_CNT_0_.Q & CLK_000_CNT_1_.Q & CLK_000_CNT_2_.Q); - -CLK_000_CNT_2_.C = (CLK_OSZI); - -CLK_000_CNT_3_.T = (!CLK_000 & inst_CLK_000_D.Q & CLK_000_CNT_3_.Q - # CLK_000 & !inst_CLK_000_D.Q & CLK_000_CNT_3_.Q - # CLK_000 & inst_CLK_000_D.Q & CLK_000_CNT_0_.Q & CLK_000_CNT_1_.Q & CLK_000_CNT_2_.Q - # !CLK_000 & !inst_CLK_000_D.Q & CLK_000_CNT_0_.Q & CLK_000_CNT_1_.Q & CLK_000_CNT_2_.Q); - -CLK_000_CNT_3_.C = (CLK_OSZI); - SM_AMIGA_2_.AR = (!RST); SM_AMIGA_2_.D = (!inst_CLK_000_D.Q & SM_AMIGA_2_.Q @@ -1374,21 +1380,11 @@ SM_AMIGA_2_.D = (!inst_CLK_000_D.Q & SM_AMIGA_2_.Q SM_AMIGA_2_.C = (CLK_OSZI); -SM_AMIGA_1_.AR = (!RST); - -!SM_AMIGA_1_.D = (!inst_CLK_000_D.Q & SM_AMIGA_2_.Q - # !SM_AMIGA_2_.Q & !SM_AMIGA_1_.Q - # !CLK_000 & !inst_DTACK_SYNC.Q & !SM_AMIGA_2_.Q - # !CLK_000 & E.Q & cpu_est_1_.Q & !inst_VPA_SYNC.Q & cpu_est_0_.Q & cpu_est_2_.Q & !SM_AMIGA_2_.Q); - -SM_AMIGA_1_.C = (CLK_OSZI); - SM_AMIGA_0_.AR = (!RST); SM_AMIGA_0_.D = (!AS_000.Q & SM_AMIGA_0_.Q # !inst_CLK_000_D.Q & SM_AMIGA_0_.Q - # !CLK_000 & !inst_DTACK_SYNC.Q & SM_AMIGA_1_.Q - # !CLK_000 & E.Q & cpu_est_1_.Q & !inst_VPA_SYNC.Q & cpu_est_0_.Q & cpu_est_2_.Q & SM_AMIGA_1_.Q); + # !inst_CLK_000_D.Q & inst_CLK_OUT_PRE.Q & SM_AMIGA_1_.Q); SM_AMIGA_0_.C = (CLK_OSZI); @@ -1398,20 +1394,15 @@ SM_AMIGA_0_.C = (CLK_OSZI); SM_AMIGA_D_0_.C = (CLK_OSZI); !SM_AMIGA_D_1_.D = (!RST & !SM_AMIGA_D_1_.Q - # RST & !SM_AMIGA_4_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q); + # RST & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q); SM_AMIGA_D_1_.C = (CLK_OSZI); !SM_AMIGA_D_2_.D = (!RST & !SM_AMIGA_D_2_.Q - # RST & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q); + # RST & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & !SM_AMIGA_0_.Q); SM_AMIGA_D_2_.C = (CLK_OSZI); -un1_UDS_000_INT_0_sqmuxa_2_0 = (!DS_030 & RW & SM_AMIGA_5_.Q - # !DS_030 & RW & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & SM_AMIGA_6_.Q - # !DS_030 & !RW & inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & SM_AMIGA_4_.Q & !SM_AMIGA_5_.Q - # !DS_030 & !RW & inst_CLK_000_D.Q & !SM_AMIGA_6_.Q & SM_AMIGA_4_.Q & !SM_AMIGA_5_.Q); - Reverse-Polarity Equations: diff --git a/Logic/68030_tk.tal b/Logic/68030_tk.tal index c3b982d..3f37f9e 100644 --- a/Logic/68030_tk.tal +++ b/Logic/68030_tk.tal @@ -32,13 +32,6 @@ TCR, Clocked Output-to-Register Time, TSU TCO TPD TCR #passes #passes #passes #passes SIGNAL NAME min max min max min max min max - LDS_000 1 2 0 0 .. .. 1 1 - RN_LDS_000 1 2 0 0 .. .. 1 1 -inst_AS_030_000_SYNC 1 1 .. .. .. .. 1 2 - inst_CLK_000_D 1 1 .. .. .. .. 1 2 - SM_AMIGA_6_ .. .. 1 1 .. .. 1 2 - SM_AMIGA_4_ .. .. 1 1 .. .. 1 2 - SM_AMIGA_5_ .. .. 1 1 .. .. 1 2 AMIGA_BUS_DATA_DIR .. .. .. .. 1 1 .. .. CIIN .. .. .. .. 1 1 .. .. IPL_030_2_ 1 1 0 0 .. .. 1 1 @@ -49,6 +42,8 @@ AMIGA_BUS_DATA_DIR .. .. .. .. 1 1 .. .. RN_AS_000 1 1 0 0 .. .. 1 1 UDS_000 1 1 0 0 .. .. 1 1 RN_UDS_000 1 1 0 0 .. .. 1 1 + LDS_000 1 1 0 0 .. .. 1 1 + RN_LDS_000 1 1 0 0 .. .. 1 1 BG_000 1 1 0 0 .. .. 1 1 RN_BG_000 1 1 0 0 .. .. 1 1 BGACK_030 1 1 0 0 .. .. 1 1 @@ -56,35 +51,39 @@ AMIGA_BUS_DATA_DIR .. .. .. .. 1 1 .. .. FPU_CS 1 1 0 0 .. .. 1 1 RN_FPU_CS 1 1 0 0 .. .. 1 1 DTACK 1 1 0 0 .. .. .. .. - IPL_030_1_ 1 1 0 0 .. .. 1 1 - RN_IPL_030_1_ 1 1 0 0 .. .. 1 1 - IPL_030_0_ 1 1 0 0 .. .. 1 1 - RN_IPL_030_0_ 1 1 0 0 .. .. 1 1 E .. .. 0 0 .. .. 1 1 RN_E .. .. 0 0 .. .. 1 1 VMA .. .. 0 0 .. .. 1 1 RN_VMA .. .. 0 0 .. .. 1 1 RESET 1 1 0 0 .. .. .. .. + IPL_030_1_ 1 1 0 0 .. .. 1 1 + RN_IPL_030_1_ 1 1 0 0 .. .. 1 1 + IPL_030_0_ 1 1 0 0 .. .. 1 1 + RN_IPL_030_0_ 1 1 0 0 .. .. 1 1 + cpu_est_0_ .. .. .. .. .. .. 1 1 cpu_est_1_ .. .. .. .. .. .. 1 1 + cpu_est_d_0_ .. .. .. .. .. .. 1 1 + cpu_est_d_3_ .. .. .. .. .. .. 1 1 +inst_AS_030_000_SYNC 1 1 .. .. .. .. 1 1 inst_DTACK_SYNC 1 1 .. .. .. .. 1 1 inst_VPA_D 1 1 .. .. .. .. 1 1 inst_VPA_SYNC 1 1 .. .. .. .. 1 1 + inst_CLK_000_D 1 1 .. .. .. .. 1 1 inst_CLK_000_DD .. .. .. .. .. .. 1 1 inst_CLK_OUT_PRE .. .. .. .. .. .. 1 1 - cpu_est_0_ .. .. .. .. .. .. 1 1 + cpu_est_d_1_ .. .. .. .. .. .. 1 1 + cpu_est_d_2_ .. .. .. .. .. .. 1 1 cpu_est_2_ .. .. .. .. .. .. 1 1 CLK_CNT_0_ .. .. .. .. .. .. 1 1 + SM_AMIGA_6_ .. .. 1 1 .. .. 1 1 SM_AMIGA_7_ .. .. .. .. .. .. 1 1 inst_RISING_CLK_AMIGA 1 1 .. .. .. .. 1 1 + SM_AMIGA_1_ .. .. 1 1 .. .. 1 1 + SM_AMIGA_4_ .. .. 1 1 .. .. 1 1 SM_AMIGA_3_ .. .. 1 1 .. .. 1 1 - CLK_000_CNT_0_ 1 1 .. .. .. .. 1 1 - CLK_000_CNT_1_ 1 1 .. .. .. .. 1 1 - CLK_000_CNT_2_ 1 1 .. .. .. .. 1 1 - CLK_000_CNT_3_ 1 1 .. .. .. .. 1 1 + SM_AMIGA_5_ .. .. 1 1 .. .. 1 1 SM_AMIGA_2_ .. .. 1 1 .. .. 1 1 - SM_AMIGA_1_ 1 1 1 1 .. .. 1 1 - SM_AMIGA_0_ 1 1 1 1 .. .. 1 1 + SM_AMIGA_0_ .. .. 1 1 .. .. 1 1 SM_AMIGA_D_0_ 1 1 1 1 .. .. .. .. SM_AMIGA_D_1_ 1 1 1 1 .. .. .. .. - SM_AMIGA_D_2_ 1 1 1 1 .. .. .. .. -un1_UDS_000_INT_0_sqmuxa_2_0 .. .. .. .. 1 1 .. .. \ No newline at end of file + SM_AMIGA_D_2_ 1 1 1 1 .. .. .. .. \ No newline at end of file diff --git a/Logic/68030_tk.tt2 b/Logic/68030_tk.tt2 index 1ca82fc..0917fbf 100644 --- a/Logic/68030_tk.tt2 +++ b/Logic/68030_tk.tt2 @@ -1,387 +1,340 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Thu May 15 19:20:52 2014 +#$ DATE Thu May 15 22:17:27 2014 #$ MODULE 68030_tk -#$ PINS 59 A_30_ A_29_ SIZE_1_ A_28_ A_27_ A_31_ A_26_ A_25_ A_24_ A_23_ IPL_2_ A_22_ A_21_ A_20_ A_19_ FC_1_ A_18_ AS_030 A_17_ A_16_ DS_030 CPU_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_EXP A_0_ AVEC AVEC_EXP IPL_1_ VPA IPL_0_ DSACK_0_ RST FC_0_ RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 BG_000 BGACK_030 CLK_DIV_OUT FPU_CS DTACK IPL_030_1_ IPL_030_0_ E VMA RESET -#$ NODES 28 cpu_est_1_ inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D inst_CLK_000_DD inst_CLK_OUT_PRE cpu_est_0_ cpu_est_2_ CLK_CNT_0_ SM_AMIGA_6_ SM_AMIGA_7_ inst_RISING_CLK_AMIGA SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_5_ CLK_000_CNT_0_ CLK_000_CNT_1_ CLK_000_CNT_2_ CLK_000_CNT_3_ SM_AMIGA_2_ SM_AMIGA_1_ SM_AMIGA_0_ SM_AMIGA_D_0_ SM_AMIGA_D_1_ SM_AMIGA_D_2_ un1_UDS_000_INT_0_sqmuxa_2_0 +#$ PINS 59 FC_0_ SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 CPU_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI SIZE_0_ CLK_EXP A_30_ A_29_ A_28_ AVEC A_27_ AVEC_EXP A_26_ A_25_ VPA A_24_ A_23_ RST A_22_ A_21_ RW A_20_ AMIGA_BUS_ENABLE A_19_ AMIGA_BUS_DATA_DIR A_18_ AMIGA_BUS_ENABLE_LOW A_17_ CIIN A_16_ A_0_ IPL_1_ IPL_0_ DSACK_0_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 BG_000 BGACK_030 CLK_DIV_OUT FPU_CS DTACK E VMA RESET IPL_030_1_ IPL_030_0_ +#$ NODES 27 cpu_est_0_ cpu_est_1_ cpu_est_d_0_ cpu_est_d_3_ inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D inst_CLK_000_DD inst_CLK_OUT_PRE cpu_est_d_1_ cpu_est_d_2_ cpu_est_2_ CLK_CNT_0_ SM_AMIGA_6_ SM_AMIGA_7_ inst_RISING_CLK_AMIGA SM_AMIGA_1_ SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_5_ SM_AMIGA_2_ SM_AMIGA_0_ SM_AMIGA_D_0_ SM_AMIGA_D_1_ SM_AMIGA_D_2_ .type fr -.i 77 -.o 127 -.ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 CPU_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q FPU_CS.Q E.Q VMA.Q cpu_est_1_.Q AS_000.Q inst_AS_030_000_SYNC.Q inst_DTACK_SYNC.Q inst_VPA_D.Q inst_VPA_SYNC.Q inst_CLK_000_D.Q inst_CLK_000_DD.Q inst_CLK_OUT_PRE.Q cpu_est_0_.Q cpu_est_2_.Q CLK_CNT_0_.Q SM_AMIGA_6_.Q BG_000.Q SM_AMIGA_7_.Q UDS_000.Q LDS_000.Q inst_RISING_CLK_AMIGA.Q DSACK_1_.Q SM_AMIGA_4_.Q SM_AMIGA_3_.Q SM_AMIGA_5_.Q CLK_000_CNT_0_.Q CLK_000_CNT_1_.Q CLK_000_CNT_2_.Q CLK_000_CNT_3_.Q IPL_030_0_.Q SM_AMIGA_2_.Q IPL_030_1_.Q SM_AMIGA_1_.Q SM_AMIGA_0_.Q IPL_030_2_.Q SM_AMIGA_D_0_.Q SM_AMIGA_D_1_.Q SM_AMIGA_D_2_.Q un1_UDS_000_INT_0_sqmuxa_2_0 DSACK_1_.PIN DTACK.PIN -.ob BERR AVEC AVEC_EXP AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.C SM_AMIGA_0_.AR cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C E.C SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.C SM_AMIGA_5_.AR CLK_000_CNT_0_.C CLK_000_CNT_1_.C CLK_000_CNT_2_.C CLK_000_CNT_3_.C SM_AMIGA_D_0_.C SM_AMIGA_D_1_.C SM_AMIGA_D_2_.C IPL_030_0_.C IPL_030_0_.AP IPL_030_1_.C IPL_030_1_.AP IPL_030_2_.C IPL_030_2_.AP inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_VPA_SYNC.C inst_VPA_SYNC.AP BG_000.C BG_000.AP AS_000.C AS_000.AP VMA.C VMA.AP BGACK_030.C BGACK_030.AP inst_CLK_OUT_PRE.C DSACK_1_.C DSACK_1_.AP UDS_000.C UDS_000.AP LDS_000.C LDS_000.AP inst_DTACK_SYNC.C inst_DTACK_SYNC.AP FPU_CS.C FPU_CS.AP DTACK.C DTACK.AP CLK_CNT_0_.C inst_RISING_CLK_AMIGA.C inst_VPA_D.C inst_CLK_000_D.C RESET.C inst_CLK_000_DD.C CLK_DIV_OUT.C DSACK_0_ un1_UDS_000_INT_0_sqmuxa_2_0 DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_EXP.X1 CLK_EXP.X2 BGACK_030.D CLK_DIV_OUT.D FPU_CS.D E.T VMA.D cpu_est_1_.T AS_000.D inst_AS_030_000_SYNC.D inst_DTACK_SYNC.D inst_VPA_D.D inst_VPA_SYNC.D inst_CLK_000_D.D inst_CLK_000_DD.D inst_CLK_OUT_PRE.D cpu_est_0_.D cpu_est_2_.D CLK_CNT_0_.D SM_AMIGA_6_.D BG_000.D SM_AMIGA_7_.D UDS_000.D LDS_000.D inst_RISING_CLK_AMIGA.D DSACK_1_.D DTACK.D SM_AMIGA_4_.D SM_AMIGA_3_.D SM_AMIGA_5_.D CLK_000_CNT_0_.D CLK_000_CNT_1_.D CLK_000_CNT_2_.D CLK_000_CNT_3_.T IPL_030_0_.D SM_AMIGA_2_.D IPL_030_1_.D SM_AMIGA_1_.D SM_AMIGA_0_.D IPL_030_2_.D SM_AMIGA_D_0_.D SM_AMIGA_D_1_.D SM_AMIGA_D_2_.D RESET.D -.p 375 ------------------------------------------------------------------------------ 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ -----0---------0---------------------------------------0-----1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------1------------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ ---------------1--------------------------1------------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------0--------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------0--------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ ---------------1------------------------------------0--------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0---------1--------------------------1------------0-----0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ -----0----------------------------------------0--------0-----0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ -----0---------1------------------------------------0--0-----0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ ------0--------0----------------0---------1---1------------1-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ ------0--------0----------------0-------------1-----0------1-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------------------0-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ -----------1----------------------------------1---------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ -----------0----------------------------------0---------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ -----------1----------------------------------1---------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ -----------0----------------------------------0---------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ --------------------------------------------------------------11-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ -----------1----------------------------------1----------------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ -----------0----------------------------------0----------------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ --------------------------------------------------------------00-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ --------------------------------------------------------------111------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~ -----------1----------------------------------1-----------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ -----------0----------------------------------0-----------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ --------------------------------------------------------------0-0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~ ---------------------------------------------------------------00------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~ -----------0----------------------------------1------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ -----------1----------------------------------0------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ ---------------------------------------------------------0--------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~ ----------------------------------------------0--------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ -----------0-------------------------------0-----------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ -------------------------------------------1-1---------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~ -----------0--------------------------1-1----0---11----------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ ------------------------------------------------------------0------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~ ---------------------------------------------------------0----------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ -----------------------------------------1----1----------------------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ -------------------------------------------------------------------0-0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ ------------------------------------------00--0-1-------------1-------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ ------------------------------------------0--00-1-------------1-------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ ------------------------------------------00--0-1--------------1------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ ------------------------------------------0--00-1--------------1------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ ------------------------------------------00--0-1---------------1-----1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ ------------------------------------------0--00-1---------------1-----1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ ------------------------------------------00--0-1----------------1----1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ ------------------------------------------0--00-1----------------1----1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ ----------------------------------------------------------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------1----------------------------------------------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ --------------------------------------0----1--------------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ----------------------------------------0--1--------------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ -------------------------------------------1-1------------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ -------------------------------------------1-----0--------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ -------------------------------------------1------0-------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ------------------------------------------------------0---------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ --------------1-------------------------------------0------0-------0--0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ ---------------------------------------------------------------------00------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ --------------1--------------------------------------------0-0-------00------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ --------------1---------------------------------------------0------0-00------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ ---------------------------------------------------------0-------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ ------------------------------------------------------------------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------0---------------------------------------------------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ -------------------------------------------------------------------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------0----------------------------------------------------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ -----------------------------------------------------------11---------0-111--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------1-------11--------0-111--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------------------1-------1--0-111--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------------------1-----1--0-111--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------1----------------10-111--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------------------1---------10-111--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------------------------1-10-111--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------0------011-----0--0-011--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------0------0-------0-10-011--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------1------010-------00-101--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------------------0-0-----1-00-101--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------0------010-----0-00-001--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------------------------------------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------0-----------------------------------------------------------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ -----------------------------------------------------------10------0-00-110--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------1-------01-----0-00-110--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------0------001-----0-00-010--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------1------000-----0-00-100--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------0------000-----0-00-000--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -1-------------------------------------------------------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ ----------------0----------------------------------------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ --------------------------------1------------------------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ -----0--------------------------------------------------0------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ -----------------------------------------0----------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ --------------------------------------------1-1-------------1----------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +.i 76 +.o 126 +.ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 CPU_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q FPU_CS.Q BG_000.Q E.Q VMA.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_d_0_.Q cpu_est_d_3_.Q AS_000.Q inst_AS_030_000_SYNC.Q inst_DTACK_SYNC.Q inst_VPA_D.Q inst_VPA_SYNC.Q inst_CLK_000_D.Q inst_CLK_000_DD.Q IPL_030_0_.Q inst_CLK_OUT_PRE.Q IPL_030_1_.Q cpu_est_d_1_.Q cpu_est_d_2_.Q IPL_030_2_.Q cpu_est_2_.Q CLK_CNT_0_.Q SM_AMIGA_6_.Q SM_AMIGA_7_.Q UDS_000.Q LDS_000.Q inst_RISING_CLK_AMIGA.Q SM_AMIGA_1_.Q DSACK_1_.Q SM_AMIGA_4_.Q SM_AMIGA_3_.Q SM_AMIGA_5_.Q SM_AMIGA_2_.Q SM_AMIGA_0_.Q SM_AMIGA_D_0_.Q SM_AMIGA_D_1_.Q SM_AMIGA_D_2_.Q DSACK_1_.PIN DTACK.PIN +.ob BERR AVEC AVEC_EXP AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.C SM_AMIGA_0_.AR IPL_030_1_.C IPL_030_1_.AP IPL_030_2_.C IPL_030_2_.AP cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C E.C SM_AMIGA_7_.C SM_AMIGA_7_.AP cpu_est_d_0_.C cpu_est_d_1_.C cpu_est_d_2_.C cpu_est_d_3_.C SM_AMIGA_D_0_.C SM_AMIGA_D_1_.C SM_AMIGA_D_2_.C IPL_030_0_.C IPL_030_0_.AP AS_000.C AS_000.AP inst_VPA_SYNC.C inst_VPA_SYNC.AP inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP VMA.C VMA.AP BG_000.C BG_000.AP DSACK_1_.C DSACK_1_.AP BGACK_030.C BGACK_030.AP inst_CLK_OUT_PRE.C UDS_000.C UDS_000.AP LDS_000.C LDS_000.AP inst_DTACK_SYNC.C inst_DTACK_SYNC.AP FPU_CS.C FPU_CS.AP DTACK.C DTACK.AP inst_RISING_CLK_AMIGA.C CLK_CNT_0_.C inst_VPA_D.C inst_CLK_000_D.C RESET.C inst_CLK_000_DD.C CLK_DIV_OUT.C DSACK_0_ DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_EXP.X1 CLK_EXP.X2 BGACK_030.D CLK_DIV_OUT.D FPU_CS.D BG_000.D E.T VMA.T cpu_est_0_.D cpu_est_1_.T cpu_est_d_0_.D cpu_est_d_3_.D AS_000.D inst_AS_030_000_SYNC.D inst_DTACK_SYNC.D inst_VPA_D.D inst_VPA_SYNC.D inst_CLK_000_D.D inst_CLK_000_DD.D IPL_030_0_.D inst_CLK_OUT_PRE.D IPL_030_1_.D cpu_est_d_1_.D cpu_est_d_2_.D IPL_030_2_.D cpu_est_2_.D CLK_CNT_0_.D SM_AMIGA_6_.D SM_AMIGA_7_.D UDS_000.D LDS_000.D inst_RISING_CLK_AMIGA.D SM_AMIGA_1_.D DSACK_1_.D DTACK.D SM_AMIGA_4_.D SM_AMIGA_3_.D SM_AMIGA_5_.D SM_AMIGA_2_.D SM_AMIGA_0_.D SM_AMIGA_D_0_.D SM_AMIGA_D_1_.D SM_AMIGA_D_2_.D RESET.D +.p 328 +---------------------------------------------------------------------------- ~1~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1----------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----11---------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~ +------0--------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------1-------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---0-----1------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------1--1------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------01------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0----0------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------1--0------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------1----------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1---------------------------------------------------------------- ~~~~~~~1~1~1~1~1~1~1~1~1~11111~11111111~1~1~1~1~1~1~1~11~1~1~1~1~1111111~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------1--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +-------------0-------------------------------------------------------------- ~~~~~~~~1~1~1~1~1~1~1~1~1~~~~~1~~~~~~~~1~1~1~1~1~1~1~1~~1~1~1~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------0------------------------------------------------------------- ~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-0--------------0000000----------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------1111------------------------------------------------- ~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1-----------------1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1------------------1----------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1-------------------0---------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1--------------------1--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1----11-----------------0010---1----------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1------------------------0----------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------1---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~111~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------1--------------------------1---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------0---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------0--------------------------1--------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------0--------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1---------------------------1-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1---------------------------------0------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1----------------------------------1------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------1----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1-----------------------------------1----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------1---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +----1------------------------------------1---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~ +----1----------------------------------------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------0-----------------------------------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1---------1------------------------------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~ +--------------------------------------------11------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1------------------------------------------1---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1------------------------------------------0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------10---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0---------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------1--------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------1-------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------1------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------11--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +----1--------------------------------------------1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~ +----1--------------------------------------------0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~1~~~~~~~~~~~~11~~~~~~~~~~~~~ +----------1--------------------------------------0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +----------------------------------------1--------0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------1----0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------1--0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------10-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1---------------------------------------------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1---------1-----------------------------------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~ +----------------------------------------1---------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------1-----1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-1--------10------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ +----------------------------------------0--------10------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------00-------10------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ +--------------------------------------1-00-------10------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1-----------------------------------------------0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~ +---------------------------------------0--001----1----11-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------1---------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ +-------------------------------------------------0-------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ +--------------------------------------0110-----0-0-------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------1------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ +--------------------------------------0-1--------10------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-11-------10------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1----------------------------------------------------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------1--------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-11-------10------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0-11-------10------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0--0-------10------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0-00-------10------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------------0-----1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~ +----------------------------------------------------1-----0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ +-------------1---------------------------------------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ +-------------------------------------------------0---------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~ +---------------------------------------------0---10--------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ +-----0--------1----------------1-------------0---10--------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +0----0--------11---------------0-------------0---10--------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +----1------------------------------------------------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1---------1--------------------------------------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~ +--------------------------------------------1--------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------1----------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~ +-------------------------------------------------0----------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~ +---------------------------------------------1-------------10--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~ +--------------------------------------------------1--------10--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~ +---------0-------------------------------------------------00--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----1-------------------------------------------------------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +--------------1------------------------------1---------------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +-------------------------------------------------0-----------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +--------------1-----------------------------------1----------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +--------------1--------------------------------------------0-1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +-----1--------------------------------------------------------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +--------------1------------------------------1----------------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +-------------------------------------------------0------------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +--------------1-----------------------------------1-----------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +--------------1--------------------------------------------0--1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +--1------------------------------------------------------------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ +--------1------------------------------------------------------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------1------------------------------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------1-----------------------------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------1-----------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------1---------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------------1------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ +-------------1--------------------------------------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~ +-------------------------------------------------1--------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +-------------------------------------------------0--1-----------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ +----------------------------------------------------0-----------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +----1-----------------------------------------------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~ +-------------------------------------------------1---------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~ +----------------------------------------------------0------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~ +----------------------------------------------------------------01---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~ +-------------1----------------------------------------------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~ +-------------------------------------------------1----------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~ +-----0--------0----------------1-----------------1----------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +0----0--------01---------------0-----------------1----------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +-------------------------------------------------0----------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~ +----1---------0---------------------------------------------------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~ +--------------0----------------------------------------------1----0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +--------------0-----------------------------------------------1---0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +-------------1-----------------------------------------------------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +----------------------------------------------1-1------------------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~ +-------------------------------------------------1-----------------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~ +----------------------------------------------0--0-----------------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~ +------------------------------------------------00-----------------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~ +----1--------------------------------------------------------------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------1--------------------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------1------------------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1------------------------------------------------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +-------------------------------------------------1------------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ +-------------------------------------------------0------------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~ +-------------1-------------------------------------------------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~ +-------------------------------------------------1-------------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +-------------------------------------------------0-------------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~ +----------------------------------------------------------------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1--------------------------------------------------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~111~ +--------------------------------------------0-------------------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ +--------------------------------------------1----1--------------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~ +-------------------------------------------------0--------------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ +-------------0---------------------------------------------------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ +-----------------------------------------------------------0------0--0-1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------------1-----------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------------------------1----0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------------------------1-0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------0----------------------------------------------------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +----------------------------------------------------------------0-0-0---1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------------------------1-------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------------------------1-----0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------------------------1---0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------0-----------------------------------------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +----------------------------------------------------------------0--0-0---1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------------------------------1111-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------------------------1--------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------------------------1-----0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------------------------1---0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~ +----1----------------------------------------------------------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------1----------------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------------------------------- 0~00~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-1-------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------1--------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------0------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---00-0--1------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-0-01------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------0----------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~0~~~~~~~~~~~~ +-----------0---------------------------------------------------------------- ~~~~~~~0~0~0~0~0~0~0~0~0~00000~00000000~0~0~0~0~0~0~0~00~0~0~0~0~0000000~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------0--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1-------------------------------------------------------------- ~~~~~~~~0~0~0~0~0~0~0~0~0~~~~~0~~~~~~~~0~0~0~0~0~0~0~0~~0~0~0~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------0-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 +--------------1------------------------------------------------------------- ~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------1----------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------1---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------1--------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------1-------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------1------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------1------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------1----------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------0---------------------------------------------------- ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------0--------------------------------------------------- ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------0-------------------------------------------------- ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------0------------------------------------------------- ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-0--1-----------------1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-0--1------------------1----------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-0--1-------------------0---------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-0--1--------------------1--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---10---11-----------------0010---1----------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-0--1------------------------0----------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------1---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------0---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~000~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------1--------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0----0--------------------------0--------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------0-1---------------------------0-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------0----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------01---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------0---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------10---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-10---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0---------------------------------------0------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0----0-----------------------------------0------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-----------------------------------------0----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-------------------------------------------0--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~0~~0~~~~~ +---------------------------------------1---------1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------1------1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------1-----1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------1----1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +--------------------------------------------0----1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~0~~~~~~~~0~~~~~~~~~0~~~~~~~~0~~~~~~ +--------------------------------------1----------0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------0---------0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------0--------0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~00~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------1-------0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------0--0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ +-----------------------------------------------1-0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------00-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ +--------------------------------------------------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------0---------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------1--------10------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0-10-------10------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ +---------------------------------------------0---10------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ +-------------------------------------------------0--1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~ +----------------------------------------------------0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------1----0--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------1-----0-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------0----------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0-0----------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1--1---------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 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+-------------------------------------------------0--1-----------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ +-------------------------------------------------0--------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~ +----0------------------------------------------------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ +1----0--------0----------------------------------1----------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +-----0--------00---------------------------------1----------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +-----0--------0----------------1-----------------1----------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +-----0--------0----------------0-----------------1----------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ +----0---------0----------------------------------------------0----0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ +----0---------0-----------------------------------------------0---0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +--------------------------------------1000-----0-1-------1---------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------0-----------------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ +------------------------------------------------------------------00-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ +---------------------------------------------1----------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +--------------------------------------------------1-----------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +-----------------------------------------------------------0--------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +------------------------------------------------------------------0-0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~ +----------------------------------------------1-1--------------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +----------------------------------------------------------------0----0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~ 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ +----------------------------------------------------------------0-----0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +-------------1--------------------------------------------------0-0-0-0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ +-------------1---------------------------------------------0------0--00----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ +-------------1--------------------------------------------------0--0-00----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ +-----------------------------------------------------------------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------0---------------------------------------------------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ +------------------------------------------------------------------------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------0----------------------------------------------------------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ +-----------------------------------------------------------1----1-----0111-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------------------------1-1---0111-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------------------------11--0111-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------------1-------11-0111-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------------------------1----10111-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------------------------1--10111-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------------------------110111-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------------0----1-0--00011-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------------0------01100011-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------------1----0-010-0101-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------------------------0-0-010101-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------------0----0-01000001-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------------------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------0-----------------------------------------------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ +----------------------------------------------------------------0-10-00110-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------------1----0--0100110-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------------0----0-00100010-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------------1----0-00000100-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------------0----0-00000000-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------0-----------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~ +-----------------------------------------------1-1-----------------1-------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ .end diff --git a/Logic/68030_tk.tt3 b/Logic/68030_tk.tt3 index b2feb41..e63bcfc 100644 --- a/Logic/68030_tk.tt3 +++ b/Logic/68030_tk.tt3 @@ -1,387 +1,340 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Thu May 15 19:20:52 2014 +#$ DATE Thu May 15 22:17:27 2014 #$ MODULE 68030_tk -#$ PINS 59 A_30_ A_29_ SIZE_1_ A_28_ A_27_ A_31_ A_26_ A_25_ A_24_ A_23_ IPL_2_ A_22_ A_21_ A_20_ A_19_ FC_1_ A_18_ AS_030 A_17_ A_16_ DS_030 CPU_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_EXP A_0_ AVEC AVEC_EXP IPL_1_ VPA IPL_0_ DSACK_0_ RST FC_0_ RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 BG_000 BGACK_030 CLK_DIV_OUT FPU_CS DTACK IPL_030_1_ IPL_030_0_ E VMA RESET -#$ NODES 28 cpu_est_1_ inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D inst_CLK_000_DD inst_CLK_OUT_PRE cpu_est_0_ cpu_est_2_ CLK_CNT_0_ SM_AMIGA_6_ SM_AMIGA_7_ inst_RISING_CLK_AMIGA SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_5_ CLK_000_CNT_0_ CLK_000_CNT_1_ CLK_000_CNT_2_ CLK_000_CNT_3_ SM_AMIGA_2_ SM_AMIGA_1_ SM_AMIGA_0_ SM_AMIGA_D_0_ SM_AMIGA_D_1_ SM_AMIGA_D_2_ un1_UDS_000_INT_0_sqmuxa_2_0 +#$ PINS 59 FC_0_ SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 CPU_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI SIZE_0_ CLK_EXP A_30_ A_29_ A_28_ AVEC A_27_ AVEC_EXP A_26_ A_25_ VPA A_24_ A_23_ RST A_22_ A_21_ RW A_20_ AMIGA_BUS_ENABLE A_19_ AMIGA_BUS_DATA_DIR A_18_ AMIGA_BUS_ENABLE_LOW A_17_ CIIN A_16_ A_0_ IPL_1_ IPL_0_ DSACK_0_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 BG_000 BGACK_030 CLK_DIV_OUT FPU_CS DTACK E VMA RESET IPL_030_1_ IPL_030_0_ +#$ NODES 27 cpu_est_0_ cpu_est_1_ cpu_est_d_0_ cpu_est_d_3_ inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D inst_CLK_000_DD inst_CLK_OUT_PRE cpu_est_d_1_ cpu_est_d_2_ cpu_est_2_ CLK_CNT_0_ SM_AMIGA_6_ SM_AMIGA_7_ inst_RISING_CLK_AMIGA SM_AMIGA_1_ SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_5_ SM_AMIGA_2_ SM_AMIGA_0_ SM_AMIGA_D_0_ SM_AMIGA_D_1_ SM_AMIGA_D_2_ .type fr -.i 77 -.o 127 -.ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 CPU_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q FPU_CS.Q E.Q VMA.Q cpu_est_1_.Q AS_000.Q inst_AS_030_000_SYNC.Q inst_DTACK_SYNC.Q inst_VPA_D.Q inst_VPA_SYNC.Q inst_CLK_000_D.Q inst_CLK_000_DD.Q inst_CLK_OUT_PRE.Q cpu_est_0_.Q cpu_est_2_.Q CLK_CNT_0_.Q SM_AMIGA_6_.Q BG_000.Q SM_AMIGA_7_.Q UDS_000.Q LDS_000.Q inst_RISING_CLK_AMIGA.Q DSACK_1_.Q SM_AMIGA_4_.Q SM_AMIGA_3_.Q SM_AMIGA_5_.Q CLK_000_CNT_0_.Q CLK_000_CNT_1_.Q CLK_000_CNT_2_.Q CLK_000_CNT_3_.Q IPL_030_0_.Q SM_AMIGA_2_.Q IPL_030_1_.Q SM_AMIGA_1_.Q SM_AMIGA_0_.Q IPL_030_2_.Q SM_AMIGA_D_0_.Q SM_AMIGA_D_1_.Q SM_AMIGA_D_2_.Q un1_UDS_000_INT_0_sqmuxa_2_0 DSACK_1_.PIN DTACK.PIN -.ob BERR AVEC AVEC_EXP AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.C SM_AMIGA_0_.AR cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C E.C SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.C SM_AMIGA_5_.AR CLK_000_CNT_0_.C CLK_000_CNT_1_.C CLK_000_CNT_2_.C CLK_000_CNT_3_.C SM_AMIGA_D_0_.C SM_AMIGA_D_1_.C SM_AMIGA_D_2_.C IPL_030_0_.C IPL_030_0_.AP IPL_030_1_.C IPL_030_1_.AP IPL_030_2_.C IPL_030_2_.AP inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_VPA_SYNC.C inst_VPA_SYNC.AP BG_000.C BG_000.AP AS_000.C AS_000.AP VMA.C VMA.AP BGACK_030.C BGACK_030.AP inst_CLK_OUT_PRE.C DSACK_1_.C DSACK_1_.AP UDS_000.C UDS_000.AP LDS_000.C LDS_000.AP inst_DTACK_SYNC.C inst_DTACK_SYNC.AP FPU_CS.C FPU_CS.AP DTACK.C DTACK.AP CLK_CNT_0_.C inst_RISING_CLK_AMIGA.C inst_VPA_D.C inst_CLK_000_D.C RESET.C inst_CLK_000_DD.C CLK_DIV_OUT.C DSACK_0_ un1_UDS_000_INT_0_sqmuxa_2_0 DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_EXP.X1 CLK_EXP.X2 BGACK_030.D CLK_DIV_OUT.D FPU_CS.D E.T VMA.D cpu_est_1_.T AS_000.D inst_AS_030_000_SYNC.D inst_DTACK_SYNC.D inst_VPA_D.D inst_VPA_SYNC.D inst_CLK_000_D.D inst_CLK_000_DD.D inst_CLK_OUT_PRE.D cpu_est_0_.D cpu_est_2_.D CLK_CNT_0_.D SM_AMIGA_6_.D BG_000.D SM_AMIGA_7_.D UDS_000.D LDS_000.D inst_RISING_CLK_AMIGA.D DSACK_1_.D DTACK.D SM_AMIGA_4_.D SM_AMIGA_3_.D SM_AMIGA_5_.D CLK_000_CNT_0_.D CLK_000_CNT_1_.D CLK_000_CNT_2_.D CLK_000_CNT_3_.T IPL_030_0_.D SM_AMIGA_2_.D IPL_030_1_.D SM_AMIGA_1_.D SM_AMIGA_0_.D IPL_030_2_.D SM_AMIGA_D_0_.D SM_AMIGA_D_1_.D SM_AMIGA_D_2_.D RESET.D -.p 375 ------------------------------------------------------------------------------ ~1~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----1------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----11----------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ -------0---------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------1--------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ ----0-----1------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------1--1------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------01------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0----0------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ -------1--0------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ -----------1------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------1----------------------------------------------------------------- ~~~~~~~1~1~1~1~1~11111~1~1~11111111~1~1~1~1~1~1~1~1~11~1~1~1~1~1~1111111~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------1---------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------1--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 --------------0--------------------------------------------------------------- ~~~~~~~~1~1~1~1~1~~~~~1~1~1~~~~~~~~1~1~1~1~1~1~1~1~1~~1~1~1~1~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------0-------------------------------------------------------------- ~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --0--------------0000000------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------1111-------------------------------------------------- ~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------1-----------------1------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------1------------------1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------1-------------------0----------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------1--------------------1---------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----1----11-----------------0010---1------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------1------------------------0------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------1----------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~111~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------1--------------------------1----------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------0----------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------0--------------------------1---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------0---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----1--------------------------------1--------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----1----------------------------------1------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------1------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~ -----1------------------------------------1----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ ----------0-------------------------------1----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------11----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----1--------------------------------------1--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----1--------------------------------------0--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------10--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------1------1-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------1-----1-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------1----1-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----1-------------------------------------1-1-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ --------------------------------------------11-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----1----------------------------------------1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ -----------0----------------------------------1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ ---------------------------------------1------1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------1----1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----1----------------------------------------0------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------1----------------------------------0------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~1~~~~~~~~~~~~~ -----------------------------------------1----0------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------1--0------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------10------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------------1----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----1------------------------------------------0----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ ----------------------------------------------0--1---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------1-1---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------1-------10-1---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~ -----1-------------------------------------------0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------1---0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------10-0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------0-----10-0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------1-0-----10-0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------1---------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------0---1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------1--1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------0-------10-11--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------1-1-----10-11--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----1--------------------------------------------0--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------1----0--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------0-0-----10--0--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------1-1-----10-10--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------0-1-----10-10--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------0-0-----10-00--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------------0--1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------------1--0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------1-------------------------------------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ ------------------------------------------1---------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~ -----1---------0--------------------------0---------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------0---1-----1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ ------0--------1--------------------------0---1-----1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------0--------1----------------1---------0---1-----1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------0-----1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~ -----1----------------------------------------------0------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------1----------0------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------1------------------------------------------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------1-------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------0-------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~ ----------0-----------------------------------------0-0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ ------1------------------------------------------------1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ ---------------0--------------------------0---------1--1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ ---1-----------------------------------------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ ---------1-----------------------------------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------1-----------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~ ----------------------------------1----------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~ ------------------------------------------1---------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ -------------------------------------------1-1------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ ----------------------------------------------1-----------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ ------------------------------------------------0---------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ --------------1--------------------------------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~ ----------------------------------------------1------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~ ----------------------------------------------0------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~ -----1---------0-------------------------------------------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ ---------------0---------------------------------------1---0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ --------------1---------------------------------------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ -------------------------------------------1-1--------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~ ----------------------------------------------1-------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~ -------------------------------------------0--0-------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~ ---------------------------------------------00-------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~ -----1------------------------------------------------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------1----------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------1--------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------1----------------------------------------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ ------0--------1---------------------------------------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----1---------0---------------------------------------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ ------0--------1----------------1----------------------------1---------------- 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ ------0--------0--------------------------1---1------------1-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------0--------0----------------1---------1---1------------1-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ ------0--------0------------------------------1-----0------1-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------0--------0----------------1-------------1-----0------1-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------------------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ -----------1----------------------------------1---------------01-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ -----------0----------------------------------0---------------01-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ -----------1----------------------------------1---------------10-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ -----------0----------------------------------0---------------10-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ -----------1----------------------------------1---------------0-1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ -----------0----------------------------------0---------------0-1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ -----------1----------------------------------1---------------111------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~ -----------0----------------------------------0---------------111------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~ 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-----1----------------------------------------------------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ ----------------------------------------------------------1-----------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ ---------------------------------------------------------0-------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ --------------0---------------------------------------------------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ ----------------------------------------------------0------0-------0----1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------1-------------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------------------1------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------------------------1----0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------0----------------------------------------------------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ -----------------------------------------------------------0-0-------0---1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------------------1-------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------------------1-----------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------------------------1---0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------0-----------------------------------------------------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ ------------------------------------------------------------0------0-0----1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------------------------1-111--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------------------------1-------------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------------------------1------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------------------------1----0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -0--------------1---------------0------------------------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~ -----1---------------------------------------------------------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~ --------------------------------------------------------1------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~ -----1-----------------------------------------------------------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------1---------------------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------------------------------------------ 0~00~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --1--------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------1----------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------1---------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------0-------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----00-0--1------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-0-01------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------0------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ ------------0----------------------------------------------------------------- ~~~~~~~0~0~0~0~0~00000~0~0~00000000~0~0~0~0~0~0~0~0~00~0~0~0~0~0~0000000~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------0---------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------1--------------------------------------------------------------- ~~~~~~~~0~0~0~0~0~~~~~0~0~0~~~~~~~~0~0~0~0~0~0~0~0~0~~0~0~0~0~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------0--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 ---------------1-------------------------------------------------------------- ~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------1------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------1----------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------1---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------1--------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------1-------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------1------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------1------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------0----------------------------------------------------- ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------0---------------------------------------------------- ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------0--------------------------------------------------- ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------0-------------------------------------------------- ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-0--1-----------------1------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-0--1------------------1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-0--1-------------------0----------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-0--1--------------------1---------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----10---11-----------------0010---1------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-0--1------------------------0------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------1----------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------0----------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~000~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------1---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0----0--------------------------0---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-----------------------------------0------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------0-0------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0----0-------------------------------0----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-------------------------------------0---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0---------------------------------------0-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~0~~~~~~~0~~~~~~~~ -----------0----------------------------------1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~00~~~~~~~~~~~ -----------1-----------------------------1----1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ------------------------------------------0---1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------0--1-1--1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ----------------------------------------01-1--1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ -----------------------------------------1-1-11------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ----------------------------------------------0------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~~~~~0~~~~~~0~~~~~~~0~~~~~~~~~~~~~~ -----------1----------------------------------0------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~00~~~~~~~~~~~ ---------------------------------------0------0------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------0--0------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ ---------------------------------------------00------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ -----------------------------------------------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------------0----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------0--------1---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------1-0--------1---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------10-1---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------0-0-----10-1---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------1--------0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------1-1--1--0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ----------------------------------------------0--0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------1-0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------0-----------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------0---------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------1----------11--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------0----------01--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------1-----------0--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------0-1---------0--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------1-1--1---0--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ----------------------------------------------0---0--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------1--0--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------0----------10--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------1--------00--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------------1--1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------------0--0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----1-00-0-----------------------------------------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~ ---------------0--------------------------0---------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------0---1-----1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------0--------1----------------0---------0---1-----1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------1-----0------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~ --------0-1------------------------------------------0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~ -----1-00-0-------------------------------------------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------0------------0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------0-0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~ -----01------------------------------------------------0---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ -----0---------0--------------------------0---------1--0---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ ---0-----------------------------------------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ ---------------------------------0-----------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ ----------------------------------0----------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~ ------------------------------------0--------------------0-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0----------------------------------------------------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ ---------------0-------------------------------------------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0---------0---------------------------------------0---0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ --------------------------------------0-0---0-1--11---------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------0-------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ -----------------------------------------------------------00----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ ---------------0---------------------------------------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------0--------1----------------0----------------------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ -----0---------0---------------------------------------0-----1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------1------------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ ---------------1--------------------------1------------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------0--------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------0--------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ ---------------1------------------------------------0--------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0---------1--------------------------1------------0-----0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ -----0----------------------------------------0--------0-----0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ -----0---------1------------------------------------0--0-----0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ ------0--------0----------------0---------1---1------------1-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ ------0--------0----------------0-------------1-----0------1-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------------------0-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ -----------1----------------------------------1---------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ -----------0----------------------------------0---------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ -----------1----------------------------------1---------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ -----------0----------------------------------0---------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ --------------------------------------------------------------11-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ -----------1----------------------------------1----------------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ -----------0----------------------------------0----------------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ --------------------------------------------------------------00-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ --------------------------------------------------------------111------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~ -----------1----------------------------------1-----------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ -----------0----------------------------------0-----------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ --------------------------------------------------------------0-0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~ ---------------------------------------------------------------00------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~ -----------0----------------------------------1------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ -----------1----------------------------------0------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ ---------------------------------------------------------0--------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~ ----------------------------------------------0--------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ -----------0-------------------------------0-----------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ -------------------------------------------1-1---------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~ -----------0--------------------------1-1----0---11----------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ ------------------------------------------------------------0------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~ ---------------------------------------------------------0----------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ -----------------------------------------1----1----------------------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ -------------------------------------------------------------------0-0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ ------------------------------------------00--0-1-------------1-------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ ------------------------------------------0--00-1-------------1-------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ ------------------------------------------00--0-1--------------1------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ ------------------------------------------0--00-1--------------1------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ ------------------------------------------00--0-1---------------1-----1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ ------------------------------------------0--00-1---------------1-----1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ ------------------------------------------00--0-1----------------1----1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ ------------------------------------------0--00-1----------------1----1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ ----------------------------------------------------------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------1----------------------------------------------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ --------------------------------------0----1--------------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ----------------------------------------0--1--------------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ -------------------------------------------1-1------------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ -------------------------------------------1-----0--------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ -------------------------------------------1------0-------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ------------------------------------------------------0---------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ --------------1-------------------------------------0------0-------0--0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ ---------------------------------------------------------------------00------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ --------------1--------------------------------------------0-0-------00------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ --------------1---------------------------------------------0------0-00------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ ---------------------------------------------------------0-------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ ------------------------------------------------------------------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------0---------------------------------------------------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ -------------------------------------------------------------------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------0----------------------------------------------------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ -----------------------------------------------------------11---------0-111--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------1-------11--------0-111--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------------------1-------1--0-111--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------------------1-----1--0-111--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------1----------------10-111--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------------------1---------10-111--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------------------------1-10-111--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------0------011-----0--0-011--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------0------0-------0-10-011--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------1------010-------00-101--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------------------0-0-----1-00-101--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------0------010-----0-00-001--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------------------------------------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------0-----------------------------------------------------------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ -----------------------------------------------------------10------0-00-110--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------1-------01-----0-00-110--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------0------001-----0-00-010--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------1------000-----0-00-100--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------0------000-----0-00-000--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -1-------------------------------------------------------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ ----------------0----------------------------------------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ --------------------------------1------------------------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ -----0--------------------------------------------------0------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ -----------------------------------------0----------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ --------------------------------------------1-1-------------1----------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +.i 76 +.o 126 +.ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 CPU_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q FPU_CS.Q BG_000.Q E.Q VMA.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_d_0_.Q cpu_est_d_3_.Q AS_000.Q inst_AS_030_000_SYNC.Q inst_DTACK_SYNC.Q inst_VPA_D.Q inst_VPA_SYNC.Q inst_CLK_000_D.Q inst_CLK_000_DD.Q IPL_030_0_.Q inst_CLK_OUT_PRE.Q IPL_030_1_.Q cpu_est_d_1_.Q cpu_est_d_2_.Q IPL_030_2_.Q cpu_est_2_.Q CLK_CNT_0_.Q SM_AMIGA_6_.Q SM_AMIGA_7_.Q UDS_000.Q LDS_000.Q inst_RISING_CLK_AMIGA.Q SM_AMIGA_1_.Q DSACK_1_.Q SM_AMIGA_4_.Q SM_AMIGA_3_.Q SM_AMIGA_5_.Q SM_AMIGA_2_.Q SM_AMIGA_0_.Q SM_AMIGA_D_0_.Q SM_AMIGA_D_1_.Q SM_AMIGA_D_2_.Q DSACK_1_.PIN DTACK.PIN +.ob BERR AVEC AVEC_EXP AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.C SM_AMIGA_0_.AR IPL_030_1_.C IPL_030_1_.AP IPL_030_2_.C IPL_030_2_.AP cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C E.C SM_AMIGA_7_.C SM_AMIGA_7_.AP cpu_est_d_0_.C cpu_est_d_1_.C cpu_est_d_2_.C cpu_est_d_3_.C SM_AMIGA_D_0_.C SM_AMIGA_D_1_.C SM_AMIGA_D_2_.C IPL_030_0_.C IPL_030_0_.AP AS_000.C AS_000.AP inst_VPA_SYNC.C inst_VPA_SYNC.AP inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP VMA.C VMA.AP BG_000.C BG_000.AP DSACK_1_.C DSACK_1_.AP BGACK_030.C BGACK_030.AP inst_CLK_OUT_PRE.C UDS_000.C UDS_000.AP LDS_000.C LDS_000.AP inst_DTACK_SYNC.C inst_DTACK_SYNC.AP FPU_CS.C FPU_CS.AP DTACK.C DTACK.AP inst_RISING_CLK_AMIGA.C CLK_CNT_0_.C inst_VPA_D.C inst_CLK_000_D.C RESET.C inst_CLK_000_DD.C CLK_DIV_OUT.C DSACK_0_ DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_EXP.X1 CLK_EXP.X2 BGACK_030.D CLK_DIV_OUT.D FPU_CS.D BG_000.D E.T VMA.T cpu_est_0_.D cpu_est_1_.T cpu_est_d_0_.D cpu_est_d_3_.D AS_000.D inst_AS_030_000_SYNC.D inst_DTACK_SYNC.D inst_VPA_D.D inst_VPA_SYNC.D inst_CLK_000_D.D inst_CLK_000_DD.D IPL_030_0_.D inst_CLK_OUT_PRE.D IPL_030_1_.D cpu_est_d_1_.D cpu_est_d_2_.D IPL_030_2_.D cpu_est_2_.D CLK_CNT_0_.D SM_AMIGA_6_.D SM_AMIGA_7_.D UDS_000.D LDS_000.D inst_RISING_CLK_AMIGA.D SM_AMIGA_1_.D DSACK_1_.D DTACK.D SM_AMIGA_4_.D SM_AMIGA_3_.D SM_AMIGA_5_.D SM_AMIGA_2_.D SM_AMIGA_0_.D SM_AMIGA_D_0_.D SM_AMIGA_D_1_.D SM_AMIGA_D_2_.D RESET.D +.p 328 +---------------------------------------------------------------------------- ~1~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1----------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----11---------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~ +------0--------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------1-------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---0-----1------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------1--1------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------01------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0----0------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------1--0------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------1----------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1---------------------------------------------------------------- ~~~~~~~1~1~1~1~1~1~1~1~1~11111~11111111~1~1~1~1~1~1~1~11~1~1~1~1~1111111~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------1--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +-------------0-------------------------------------------------------------- ~~~~~~~~1~1~1~1~1~1~1~1~1~~~~~1~~~~~~~~1~1~1~1~1~1~1~1~~1~1~1~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------0------------------------------------------------------------- ~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-0--------------0000000----------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------1111------------------------------------------------- ~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1-----------------1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1------------------1----------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1-------------------0---------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1--------------------1--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1----11-----------------0010---1----------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1------------------------0----------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------1---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~111~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------1--------------------------1---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------0---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------0--------------------------1--------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------0--------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1---------------------------1-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1---------------------------------0------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1----------------------------------1------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------1----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1-----------------------------------1----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------1---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +----1------------------------------------1---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~ +----1----------------------------------------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------0-----------------------------------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1---------1------------------------------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~ +--------------------------------------------11------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1------------------------------------------1---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1------------------------------------------0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------10---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0---------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------1--------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------1-------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------1------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------11--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +----1--------------------------------------------1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~ +----1--------------------------------------------0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~1~~~~~~~~~~~~11~~~~~~~~~~~~~ +----------1--------------------------------------0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +----------------------------------------1--------0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------1----0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------1--0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------10-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1---------------------------------------------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1---------1-----------------------------------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~ +----------------------------------------1---------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------1-----1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-1--------10------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ +----------------------------------------0--------10------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------00-------10------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ +--------------------------------------1-00-------10------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1-----------------------------------------------0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~ +---------------------------------------0--001----1----11-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------1---------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ +-------------------------------------------------0-------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ +--------------------------------------0110-----0-0-------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------1------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ +--------------------------------------0-1--------10------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-11-------10------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1----------------------------------------------------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------1--------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-11-------10------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0-11-------10------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0--0-------10------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0-00-------10------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------------0-----1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~ +----------------------------------------------------1-----0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ +-------------1---------------------------------------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ +-------------------------------------------------0---------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~ +---------------------------------------------0---10--------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ +-----0--------1----------------1-------------0---10--------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +0----0--------11---------------0-------------0---10--------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +----1------------------------------------------------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1---------1--------------------------------------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~ +--------------------------------------------1--------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------1----------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~ +-------------------------------------------------0----------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~ +---------------------------------------------1-------------10--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~ +--------------------------------------------------1--------10--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~ +---------0-------------------------------------------------00--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----1-------------------------------------------------------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +--------------1------------------------------1---------------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +-------------------------------------------------0-----------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +--------------1-----------------------------------1----------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +--------------1--------------------------------------------0-1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +-----1--------------------------------------------------------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +--------------1------------------------------1----------------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +-------------------------------------------------0------------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +--------------1-----------------------------------1-----------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +--------------1--------------------------------------------0--1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +--1------------------------------------------------------------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ +--------1------------------------------------------------------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------1------------------------------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------1-----------------------------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------1-----------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------1---------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------------1------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ +-------------1--------------------------------------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~ +-------------------------------------------------1--------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +-------------------------------------------------0--1-----------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ +----------------------------------------------------0-----------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +----1-----------------------------------------------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~ +-------------------------------------------------1---------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~ +----------------------------------------------------0------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~ 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +-------------------------------------------------0----------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~ +----1---------0---------------------------------------------------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~ +--------------0----------------------------------------------1----0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +--------------0-----------------------------------------------1---0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~ +----1--------------------------------------------------------------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------1--------------------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------1------------------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1------------------------------------------------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------------------------1-0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------0----------------------------------------------------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +----------------------------------------------------------------0-0-0---1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------------------------1-------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------------------------1--------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------------------------1-----0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------------------------1---0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~ +----1----------------------------------------------------------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------1----------------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------------------------------- 0~00~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-1-------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------1--------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------0------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---00-0--1------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-0-01------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------0----------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~0~~~~~~~~~~~~ +-----------0---------------------------------------------------------------- ~~~~~~~0~0~0~0~0~0~0~0~0~00000~00000000~0~0~0~0~0~0~0~00~0~0~0~0~0000000~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------0--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1-------------------------------------------------------------- ~~~~~~~~0~0~0~0~0~0~0~0~0~~~~~0~~~~~~~~0~0~0~0~0~0~0~0~~0~0~0~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------0-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 +--------------1------------------------------------------------------------- ~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------1----------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------1---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------1--------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------1-------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------1------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------1------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------1----------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------0---------------------------------------------------- ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------0--------------------------------------------------- ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------0-------------------------------------------------- ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------0------------------------------------------------- ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-0--1-----------------1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-0--1------------------1----------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-0--1-------------------0---------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-0--1--------------------1--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---10---11-----------------0010---1----------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-0--1------------------------0----------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------1---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------0---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~000~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------1--------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0----0--------------------------0--------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------0-1---------------------------0-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------00-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ +--------------------------------------------------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------0---------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------1--------10------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +-----0--------1----------------1-------------0---10--------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +-----0--------1----------------0-------------0---10--------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ +----1-00-0--------------------------------------------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------1----------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +-----0--------00---------------------------------1----------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +-----0--------0----------------1-----------------1----------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +-----0--------0----------------0-----------------1----------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ +----0---------0----------------------------------------------0----0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ +----0---------0-----------------------------------------------0---0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +--------------------------------------1000-----0-1-------1---------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------0-----------------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ +------------------------------------------------------------------00-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ +---------------------------------------------1----------------------0------- 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +------------------------------------------------------------0---------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ +----------------------------------------------------------------0-----0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +-------------1--------------------------------------------------0-0-0-0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ +-------------1---------------------------------------------0------0--00----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ +-----------------------------------------------------------1----1-----0111-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------------------------1-1---0111-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------------------------11--0111-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------------1-------11-0111-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------------------------1----10111-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------------------------1--10111-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------------------------110111-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------------0----1-0--00011-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------------0------01100011-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------------1----0-010-0101-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------------------------0-0-010101-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------------0----0-01000001-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------------------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------0-----------------------------------------------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ +----------------------------------------------------------------0-10-00110-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------------1----0--0100110-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------------0----0-00100010-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------------1----0-00000100-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------------0----0-00000000-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------0-----------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~ +-----------------------------------------------1-1-----------------1-------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ .end diff --git a/Logic/68030_tk.tt4 b/Logic/68030_tk.tt4 index 3d6e4f2..38f32ff 100644 --- a/Logic/68030_tk.tt4 +++ b/Logic/68030_tk.tt4 @@ -1,199 +1,178 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Thu May 15 19:20:52 2014 +#$ DATE Thu May 15 22:17:27 2014 #$ MODULE BUS68030 -#$ PINS 59 A_30_ A_29_ SIZE_1_ A_28_ A_27_ A_31_ A_26_ A_25_ A_24_ A_23_ IPL_2_ - A_22_ A_21_ A_20_ A_19_ FC_1_ A_18_ AS_030 A_17_ A_16_ DS_030 CPU_SPACE BERR - BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_EXP A_0_ AVEC AVEC_EXP IPL_1_ VPA - IPL_0_ DSACK_0_ RST FC_0_ RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR - AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 - BG_000 BGACK_030 CLK_DIV_OUT FPU_CS DTACK IPL_030_1_ IPL_030_0_ E VMA RESET -#$ NODES 28 cpu_est_1_ inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D - inst_VPA_SYNC inst_CLK_000_D inst_CLK_000_DD inst_CLK_OUT_PRE cpu_est_0_ - cpu_est_2_ CLK_CNT_0_ SM_AMIGA_6_ SM_AMIGA_7_ inst_RISING_CLK_AMIGA SM_AMIGA_4_ - SM_AMIGA_3_ SM_AMIGA_5_ CLK_000_CNT_0_ CLK_000_CNT_1_ CLK_000_CNT_2_ - CLK_000_CNT_3_ SM_AMIGA_2_ SM_AMIGA_1_ SM_AMIGA_0_ SM_AMIGA_D_0_ SM_AMIGA_D_1_ - SM_AMIGA_D_2_ un1_UDS_000_INT_0_sqmuxa_2_0 +#$ PINS 59 FC_0_ SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 CPU_SPACE BERR BG_030 + BGACK_000 CLK_030 CLK_000 CLK_OSZI SIZE_0_ CLK_EXP A_30_ A_29_ A_28_ AVEC A_27_ + AVEC_EXP A_26_ A_25_ VPA A_24_ A_23_ RST A_22_ A_21_ RW A_20_ AMIGA_BUS_ENABLE + A_19_ AMIGA_BUS_DATA_DIR A_18_ AMIGA_BUS_ENABLE_LOW A_17_ CIIN A_16_ A_0_ IPL_1_ + IPL_0_ DSACK_0_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 BG_000 BGACK_030 + CLK_DIV_OUT FPU_CS DTACK E VMA RESET IPL_030_1_ IPL_030_0_ +#$ NODES 27 cpu_est_0_ cpu_est_1_ cpu_est_d_0_ cpu_est_d_3_ + inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D + inst_CLK_000_DD inst_CLK_OUT_PRE cpu_est_d_1_ cpu_est_d_2_ cpu_est_2_ CLK_CNT_0_ + SM_AMIGA_6_ SM_AMIGA_7_ inst_RISING_CLK_AMIGA SM_AMIGA_1_ SM_AMIGA_4_ + SM_AMIGA_3_ SM_AMIGA_5_ SM_AMIGA_2_ SM_AMIGA_0_ SM_AMIGA_D_0_ SM_AMIGA_D_1_ + SM_AMIGA_D_2_ .type f -.i 77 -.o 128 +.i 76 +.o 127 .ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 CPU_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_ - BGACK_030.Q FPU_CS.Q E.Q VMA.Q cpu_est_1_.Q AS_000.Q inst_AS_030_000_SYNC.Q - inst_DTACK_SYNC.Q inst_VPA_D.Q inst_VPA_SYNC.Q inst_CLK_000_D.Q - inst_CLK_000_DD.Q inst_CLK_OUT_PRE.Q cpu_est_0_.Q cpu_est_2_.Q CLK_CNT_0_.Q - SM_AMIGA_6_.Q BG_000.Q SM_AMIGA_7_.Q UDS_000.Q LDS_000.Q inst_RISING_CLK_AMIGA.Q - DSACK_1_.Q SM_AMIGA_4_.Q SM_AMIGA_3_.Q SM_AMIGA_5_.Q CLK_000_CNT_0_.Q - CLK_000_CNT_1_.Q CLK_000_CNT_2_.Q CLK_000_CNT_3_.Q IPL_030_0_.Q SM_AMIGA_2_.Q - IPL_030_1_.Q SM_AMIGA_1_.Q SM_AMIGA_0_.Q IPL_030_2_.Q SM_AMIGA_D_0_.Q - SM_AMIGA_D_1_.Q SM_AMIGA_D_2_.Q un1_UDS_000_INT_0_sqmuxa_2_0 DSACK_1_.PIN - DTACK.PIN -.ob BERR BERR.OE CLK_EXP.X1 CLK_EXP.X2 AVEC AVEC_EXP AVEC_EXP.OE DSACK_0_ - DSACK_0_.OE AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN - CIIN.OE IPL_030_2_.D IPL_030_2_.C IPL_030_2_.AP DSACK_1_.D% DSACK_1_.C + BGACK_030.Q FPU_CS.Q BG_000.Q E.Q VMA.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_d_0_.Q + cpu_est_d_3_.Q AS_000.Q inst_AS_030_000_SYNC.Q inst_DTACK_SYNC.Q inst_VPA_D.Q + inst_VPA_SYNC.Q inst_CLK_000_D.Q inst_CLK_000_DD.Q IPL_030_0_.Q + inst_CLK_OUT_PRE.Q IPL_030_1_.Q cpu_est_d_1_.Q cpu_est_d_2_.Q IPL_030_2_.Q + cpu_est_2_.Q CLK_CNT_0_.Q SM_AMIGA_6_.Q SM_AMIGA_7_.Q UDS_000.Q LDS_000.Q + inst_RISING_CLK_AMIGA.Q SM_AMIGA_1_.Q DSACK_1_.Q SM_AMIGA_4_.Q SM_AMIGA_3_.Q + SM_AMIGA_5_.Q SM_AMIGA_2_.Q SM_AMIGA_0_.Q SM_AMIGA_D_0_.Q SM_AMIGA_D_1_.Q + SM_AMIGA_D_2_.Q DSACK_1_.PIN DTACK.PIN +.ob BERR BERR.OE CLK_EXP.X1 CLK_EXP.X2 AVEC AVEC_EXP AVEC_EXP.OE + AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN CIIN.OE DSACK_0_ + DSACK_0_.OE IPL_030_2_.D IPL_030_2_.C IPL_030_2_.AP DSACK_1_.D% DSACK_1_.C DSACK_1_.AP DSACK_1_.OE AS_000.D% AS_000.C AS_000.AP AS_000.OE UDS_000.D% - UDS_000.C UDS_000.AP UDS_000.OE LDS_000.D LDS_000.C LDS_000.AP LDS_000.OE + UDS_000.C UDS_000.AP UDS_000.OE LDS_000.D% LDS_000.C LDS_000.AP LDS_000.OE BG_000.D% BG_000.C BG_000.AP BGACK_030.D BGACK_030.C BGACK_030.AP CLK_DIV_OUT.D CLK_DIV_OUT.C FPU_CS.D% FPU_CS.C FPU_CS.AP DTACK.D% DTACK.C DTACK.AP DTACK.OE - IPL_030_1_.D IPL_030_1_.C IPL_030_1_.AP IPL_030_0_.D IPL_030_0_.C IPL_030_0_.AP - E.T E.C VMA.D VMA.C VMA.AP RESET.D RESET.C cpu_est_1_.T cpu_est_1_.C - inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP - inst_DTACK_SYNC.D% inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_VPA_D.D - inst_VPA_D.C inst_VPA_SYNC.D% inst_VPA_SYNC.C inst_VPA_SYNC.AP inst_CLK_000_D.D - inst_CLK_000_D.C inst_CLK_000_DD.D inst_CLK_000_DD.C inst_CLK_OUT_PRE.D - inst_CLK_OUT_PRE.C cpu_est_0_.D cpu_est_0_.C cpu_est_2_.D.X1 cpu_est_2_.D.X2 - cpu_est_2_.C CLK_CNT_0_.D CLK_CNT_0_.C SM_AMIGA_6_.D SM_AMIGA_6_.C - SM_AMIGA_6_.AR SM_AMIGA_7_.D SM_AMIGA_7_.C SM_AMIGA_7_.AP - inst_RISING_CLK_AMIGA.D inst_RISING_CLK_AMIGA.C SM_AMIGA_4_.D SM_AMIGA_4_.C - SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_5_.D - SM_AMIGA_5_.C SM_AMIGA_5_.AR CLK_000_CNT_0_.D% CLK_000_CNT_0_.C CLK_000_CNT_1_.D - CLK_000_CNT_1_.C CLK_000_CNT_2_.D% CLK_000_CNT_2_.C CLK_000_CNT_3_.T - CLK_000_CNT_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D% - SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR - SM_AMIGA_D_0_.D% SM_AMIGA_D_0_.C SM_AMIGA_D_1_.D% SM_AMIGA_D_1_.C - SM_AMIGA_D_2_.D% SM_AMIGA_D_2_.C un1_UDS_000_INT_0_sqmuxa_2_0 -.phase 11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 -.p 142 ------------------------------------------------------------------------------ 00001001000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -------------------------------------0---------------------------------------- 01000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ----------------------------------------------------------------------1------- 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0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000 +-------------1---------------------------------------------0------0--00----- 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000 +-------------0---------------------------------------------------------0---- 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000 +-------------1--------------------------------------------------0-0-0-0----- 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000 +-------------0----------------------------------------------------------0--- 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000 +-------------1--------------------------------------------------0--0-00----- 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 +-------------0-----------------------------------------------------------0-- 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 .end diff --git a/Logic/68030_tk.tte b/Logic/68030_tk.tte index be16a28..cd40279 100644 --- a/Logic/68030_tk.tte +++ b/Logic/68030_tk.tte @@ -1,199 +1,178 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Thu May 15 19:20:52 2014 +#$ DATE Thu May 15 22:17:27 2014 #$ MODULE BUS68030 -#$ PINS 59 A_30_ A_29_ SIZE_1_ A_28_ A_27_ A_31_ A_26_ A_25_ A_24_ A_23_ IPL_2_ - A_22_ A_21_ A_20_ A_19_ FC_1_ A_18_ AS_030 A_17_ A_16_ DS_030 CPU_SPACE BERR - BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_EXP A_0_ AVEC AVEC_EXP IPL_1_ VPA - IPL_0_ DSACK_0_ RST FC_0_ RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR - AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 - BG_000 BGACK_030 CLK_DIV_OUT FPU_CS DTACK IPL_030_1_ IPL_030_0_ E VMA RESET -#$ NODES 28 cpu_est_1_ inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D - inst_VPA_SYNC inst_CLK_000_D inst_CLK_000_DD inst_CLK_OUT_PRE cpu_est_0_ - cpu_est_2_ CLK_CNT_0_ SM_AMIGA_6_ SM_AMIGA_7_ inst_RISING_CLK_AMIGA SM_AMIGA_4_ - SM_AMIGA_3_ SM_AMIGA_5_ CLK_000_CNT_0_ CLK_000_CNT_1_ CLK_000_CNT_2_ - CLK_000_CNT_3_ SM_AMIGA_2_ SM_AMIGA_1_ SM_AMIGA_0_ SM_AMIGA_D_0_ SM_AMIGA_D_1_ - SM_AMIGA_D_2_ un1_UDS_000_INT_0_sqmuxa_2_0 +#$ PINS 59 FC_0_ SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 CPU_SPACE BERR BG_030 + BGACK_000 CLK_030 CLK_000 CLK_OSZI SIZE_0_ CLK_EXP A_30_ A_29_ A_28_ AVEC A_27_ + AVEC_EXP A_26_ A_25_ VPA A_24_ A_23_ RST A_22_ A_21_ RW A_20_ AMIGA_BUS_ENABLE + A_19_ AMIGA_BUS_DATA_DIR A_18_ AMIGA_BUS_ENABLE_LOW A_17_ CIIN A_16_ A_0_ IPL_1_ + IPL_0_ DSACK_0_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 BG_000 BGACK_030 + CLK_DIV_OUT FPU_CS DTACK E VMA RESET IPL_030_1_ IPL_030_0_ +#$ NODES 27 cpu_est_0_ cpu_est_1_ cpu_est_d_0_ cpu_est_d_3_ + inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D + inst_CLK_000_DD inst_CLK_OUT_PRE cpu_est_d_1_ cpu_est_d_2_ cpu_est_2_ CLK_CNT_0_ + SM_AMIGA_6_ SM_AMIGA_7_ inst_RISING_CLK_AMIGA SM_AMIGA_1_ SM_AMIGA_4_ + SM_AMIGA_3_ SM_AMIGA_5_ SM_AMIGA_2_ SM_AMIGA_0_ SM_AMIGA_D_0_ SM_AMIGA_D_1_ + SM_AMIGA_D_2_ .type f -.i 77 -.o 128 +.i 76 +.o 127 .ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 CPU_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_ - BGACK_030.Q FPU_CS.Q E.Q VMA.Q cpu_est_1_.Q AS_000.Q inst_AS_030_000_SYNC.Q - inst_DTACK_SYNC.Q inst_VPA_D.Q inst_VPA_SYNC.Q inst_CLK_000_D.Q - inst_CLK_000_DD.Q inst_CLK_OUT_PRE.Q cpu_est_0_.Q cpu_est_2_.Q CLK_CNT_0_.Q - SM_AMIGA_6_.Q BG_000.Q SM_AMIGA_7_.Q UDS_000.Q LDS_000.Q inst_RISING_CLK_AMIGA.Q - DSACK_1_.Q SM_AMIGA_4_.Q SM_AMIGA_3_.Q SM_AMIGA_5_.Q CLK_000_CNT_0_.Q - CLK_000_CNT_1_.Q CLK_000_CNT_2_.Q CLK_000_CNT_3_.Q IPL_030_0_.Q SM_AMIGA_2_.Q - IPL_030_1_.Q SM_AMIGA_1_.Q SM_AMIGA_0_.Q IPL_030_2_.Q SM_AMIGA_D_0_.Q - SM_AMIGA_D_1_.Q SM_AMIGA_D_2_.Q un1_UDS_000_INT_0_sqmuxa_2_0 DSACK_1_.PIN - DTACK.PIN -.ob BERR BERR.OE CLK_EXP.X1 CLK_EXP.X2 AVEC AVEC_EXP AVEC_EXP.OE DSACK_0_ - DSACK_0_.OE AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN - CIIN.OE IPL_030_2_.D IPL_030_2_.C IPL_030_2_.AP DSACK_1_.D- DSACK_1_.C + BGACK_030.Q FPU_CS.Q BG_000.Q E.Q VMA.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_d_0_.Q + cpu_est_d_3_.Q AS_000.Q inst_AS_030_000_SYNC.Q inst_DTACK_SYNC.Q inst_VPA_D.Q + inst_VPA_SYNC.Q inst_CLK_000_D.Q inst_CLK_000_DD.Q IPL_030_0_.Q + inst_CLK_OUT_PRE.Q IPL_030_1_.Q cpu_est_d_1_.Q cpu_est_d_2_.Q IPL_030_2_.Q + cpu_est_2_.Q CLK_CNT_0_.Q SM_AMIGA_6_.Q SM_AMIGA_7_.Q UDS_000.Q LDS_000.Q + inst_RISING_CLK_AMIGA.Q SM_AMIGA_1_.Q DSACK_1_.Q SM_AMIGA_4_.Q SM_AMIGA_3_.Q + SM_AMIGA_5_.Q SM_AMIGA_2_.Q SM_AMIGA_0_.Q SM_AMIGA_D_0_.Q SM_AMIGA_D_1_.Q + SM_AMIGA_D_2_.Q DSACK_1_.PIN DTACK.PIN +.ob BERR BERR.OE CLK_EXP.X1 CLK_EXP.X2 AVEC AVEC_EXP AVEC_EXP.OE + AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN CIIN.OE DSACK_0_ + DSACK_0_.OE IPL_030_2_.D IPL_030_2_.C IPL_030_2_.AP DSACK_1_.D- DSACK_1_.C DSACK_1_.AP DSACK_1_.OE AS_000.D- AS_000.C AS_000.AP AS_000.OE UDS_000.D- - UDS_000.C UDS_000.AP UDS_000.OE LDS_000.D LDS_000.C LDS_000.AP LDS_000.OE + UDS_000.C UDS_000.AP UDS_000.OE LDS_000.D- LDS_000.C LDS_000.AP LDS_000.OE BG_000.D- BG_000.C BG_000.AP BGACK_030.D BGACK_030.C BGACK_030.AP CLK_DIV_OUT.D CLK_DIV_OUT.C FPU_CS.D- FPU_CS.C FPU_CS.AP DTACK.D- DTACK.C DTACK.AP DTACK.OE - IPL_030_1_.D IPL_030_1_.C IPL_030_1_.AP IPL_030_0_.D IPL_030_0_.C IPL_030_0_.AP - E.T E.C VMA.D VMA.C VMA.AP RESET.D RESET.C cpu_est_1_.T cpu_est_1_.C - inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP - 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+-------------0-----------------------------------------------------------0-- 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 .end diff --git a/Logic/68030_tk.vcl b/Logic/68030_tk.vcl index 3cc9688..5fee938 100644 --- a/Logic/68030_tk.vcl +++ b/Logic/68030_tk.vcl @@ -18,7 +18,7 @@ SDS_file = m4a5.sds; Design = 68030_tk.tt4; Rev = 0.01; DATE = 5/15/14; -TIME = 19:20:57; +TIME = 22:17:31; Type = TT2; Pre_Fit_Time = 1; Source_Format = Pure_VHDL; @@ -134,13 +134,13 @@ Layer = OFF DSACK_1_ = BIDIR,81,7,-; DTACK = OUTPUT,30,3,-; CLK_EXP = OUTPUT,10,1,-; +LDS_000 = OUTPUT,31,3,-; UDS_000 = OUTPUT,32,3,-; E = OUTPUT,66,6,-; -VMA = OUTPUT,35,3,-; -LDS_000 = OUTPUT,31,3,-; BG_000 = OUTPUT,29,3,-; BGACK_030 = OUTPUT,83,7,-; FPU_CS = OUTPUT,78,7,-; +VMA = OUTPUT,35,3,-; AS_000 = OUTPUT,33,3,-; IPL_030_2_ = OUTPUT,9,1,-; IPL_030_0_ = OUTPUT,8,1,-; @@ -155,44 +155,43 @@ AMIGA_BUS_ENABLE = OUTPUT,34,3,-; AVEC_EXP = OUTPUT,22,2,-; AMIGA_BUS_ENABLE_LOW = OUTPUT,20,2,-; RESET = OUTPUT,3,1,-; -SM_AMIGA_0_ = NODE,*,6,-; +inst_CLK_000_D = NODE,*,7,-; +SM_AMIGA_3_ = NODE,*,6,-; +cpu_est_1_ = NODE,*,6,-; +RN_E = NODE,-1,6,-; +SM_AMIGA_1_ = NODE,*,6,-; +cpu_est_2_ = NODE,*,6,-; +cpu_est_0_ = NODE,*,6,-; RN_FPU_CS = NODE,-1,7,-; SM_AMIGA_4_ = NODE,*,3,-; -inst_VPA_SYNC = NODE,*,6,-; -inst_CLK_000_D = NODE,*,0,-; -SM_AMIGA_1_ = NODE,*,6,-; -CLK_000_CNT_1_ = NODE,*,6,-; +inst_VPA_D = NODE,*,0,-; inst_AS_030_000_SYNC = NODE,*,7,-; +SM_AMIGA_0_ = NODE,*,6,-; SM_AMIGA_2_ = NODE,*,6,-; -SM_AMIGA_3_ = NODE,*,6,-; SM_AMIGA_6_ = NODE,*,3,-; +RN_VMA = NODE,-1,3,-; RN_BGACK_030 = NODE,-1,7,-; RN_AS_000 = NODE,-1,3,-; -SM_AMIGA_D_2_ = NODE,*,6,-; -CLK_000_CNT_0_ = NODE,*,7,-; SM_AMIGA_5_ = NODE,*,3,-; SM_AMIGA_7_ = NODE,*,6,-; inst_CLK_OUT_PRE = NODE,*,6,-; -inst_DTACK_SYNC = NODE,*,6,-; +inst_VPA_SYNC = NODE,*,5,-; +inst_DTACK_SYNC = NODE,*,0,-; inst_RISING_CLK_AMIGA = NODE,*,7,-; -RN_UDS_000 = NODE,-1,3,-; -RN_DSACK_1_ = NODE,-1,7,-; -CLK_000_CNT_2_ = NODE,*,7,-; -un1_UDS_000_INT_0_sqmuxa_2_0 = NODE,*,3,-; -CLK_000_CNT_3_ = NODE,*,7,-; -cpu_est_1_ = NODE,*,6,-; -RN_VMA = NODE,-1,3,-; -RN_E = NODE,-1,6,-; -RN_BG_000 = NODE,-1,3,-; +inst_CLK_000_DD = NODE,*,7,-; RN_LDS_000 = NODE,-1,3,-; -cpu_est_2_ = NODE,*,6,-; -cpu_est_0_ = NODE,*,6,-; +RN_UDS_000 = NODE,-1,3,-; +RN_BG_000 = NODE,-1,3,-; RN_IPL_030_0_ = NODE,-1,1,-; RN_IPL_030_1_ = NODE,-1,1,-; +RN_DSACK_1_ = NODE,-1,7,-; RN_IPL_030_2_ = NODE,-1,1,-; +SM_AMIGA_D_2_ = NODE,*,1,-; SM_AMIGA_D_1_ = NODE,*,1,-; SM_AMIGA_D_0_ = NODE,*,1,-; CLK_CNT_0_ = NODE,*,6,-; -inst_CLK_000_DD = NODE,*,3,-; -inst_VPA_D = NODE,*,1,-; +cpu_est_d_2_ = NODE,*,6,-; +cpu_est_d_1_ = NODE,*,6,-; +cpu_est_d_3_ = NODE,*,6,-; +cpu_est_d_0_ = NODE,*,6,-; CLK_OSZI = INPUT,61,-,-; diff --git a/Logic/68030_tk.vco b/Logic/68030_tk.vco index 5aa1ea5..905b04e 100644 --- a/Logic/68030_tk.vco +++ b/Logic/68030_tk.vco @@ -18,7 +18,7 @@ SDS_file = m4a5.sds; Design = 68030_tk.tt4; Rev = 0.01; DATE = 5/15/14; -TIME = 19:20:57; +TIME = 22:17:31; Type = TT2; Pre_Fit_Time = 1; Source_Format = Pure_VHDL; @@ -131,26 +131,12 @@ Usercode_Format = Hex; [LOCATION ASSIGNMENT] Layer = OFF; -A_30_ = INPUT,5, B,-; -A_29_ = INPUT,6, B,-; +FC_0_ = INPUT,57, F,-; SIZE_1_ = INPUT,79, H,-; -A_28_ = INPUT,15, C,-; -A_27_ = INPUT,16, C,-; A_31_ = INPUT,4, B,-; -A_26_ = INPUT,17, C,-; -A_25_ = INPUT,18, C,-; -A_24_ = INPUT,19, C,-; -A_23_ = INPUT,84, H,-; IPL_2_ = INPUT,68, G,-; -A_22_ = INPUT,85, H,-; -A_21_ = INPUT,94, A,-; -A_20_ = INPUT,93, A,-; -A_19_ = INPUT,97, A,-; FC_1_ = INPUT,58, F,-; -A_18_ = INPUT,95, A,-; AS_030 = INPUT,82, H,-; -A_17_ = INPUT,59, F,-; -A_16_ = INPUT,96, A,-; DS_030 = INPUT,98, A,-; CPU_SPACE = INPUT,14,-,-; BERR = OUTPUT,41, E,-; @@ -159,22 +145,36 @@ BGACK_000 = INPUT,28, D,-; CLK_030 = INPUT,64,-,-; CLK_000 = INPUT,11,-,-; CLK_OSZI = INPUT,61,-,-; +SIZE_0_ = INPUT,70, G,-; CLK_EXP = OUTPUT,10, B,-; -A_0_ = INPUT,69, G,-; +A_30_ = INPUT,5, B,-; +A_29_ = INPUT,6, B,-; +A_28_ = INPUT,15, C,-; AVEC = OUTPUT,92, A,-; +A_27_ = INPUT,16, C,-; AVEC_EXP = OUTPUT,22, C,-; -IPL_1_ = INPUT,56, F,-; +A_26_ = INPUT,17, C,-; +A_25_ = INPUT,18, C,-; VPA = INPUT,36,-,-; +A_24_ = INPUT,19, C,-; +A_23_ = INPUT,84, H,-; +RST = INPUT,86,-,-; +A_22_ = INPUT,85, H,-; +A_21_ = INPUT,94, A,-; +RW = INPUT,71, G,-; +A_20_ = INPUT,93, A,-; +AMIGA_BUS_ENABLE = OUTPUT,34, D,-; +A_19_ = INPUT,97, A,-; +AMIGA_BUS_DATA_DIR = OUTPUT,48, E,-; +A_18_ = INPUT,95, A,-; +AMIGA_BUS_ENABLE_LOW = OUTPUT,20, C,-; +A_17_ = INPUT,59, F,-; +CIIN = OUTPUT,47, E,-; +A_16_ = INPUT,96, A,-; +A_0_ = INPUT,69, G,-; +IPL_1_ = INPUT,56, F,-; IPL_0_ = INPUT,67, G,-; DSACK_0_ = OUTPUT,80, H,-; -RST = INPUT,86,-,-; -FC_0_ = INPUT,57, F,-; -RW = INPUT,71, G,-; -AMIGA_BUS_ENABLE = OUTPUT,34, D,-; -AMIGA_BUS_DATA_DIR = OUTPUT,48, E,-; -AMIGA_BUS_ENABLE_LOW = OUTPUT,20, C,-; -CIIN = OUTPUT,47, E,-; -SIZE_0_ = INPUT,70, G,-; IPL_030_2_ = OUTPUT,9, B,-; DSACK_1_ = BIDIR,81, H,-; AS_000 = OUTPUT,33, D,-; @@ -185,36 +185,35 @@ BGACK_030 = OUTPUT,83, H,-; CLK_DIV_OUT = OUTPUT,65, G,-; FPU_CS = OUTPUT,78, H,-; DTACK = BIDIR,30, D,-; -IPL_030_1_ = OUTPUT,7, B,-; -IPL_030_0_ = OUTPUT,8, B,-; E = OUTPUT,66, G,-; VMA = OUTPUT,35, D,-; RESET = OUTPUT,3, B,-; -cpu_est_1_ = NODE,3, G,-; -inst_AS_030_000_SYNC = NODE,1, H,-; -inst_DTACK_SYNC = NODE,14, G,-; -inst_VPA_D = NODE,6, B,-; -inst_VPA_SYNC = NODE,12, G,-; -inst_CLK_000_D = NODE,0, A,-; -inst_CLK_000_DD = NODE,14, D,-; +IPL_030_1_ = OUTPUT,7, B,-; +IPL_030_0_ = OUTPUT,8, B,-; +cpu_est_0_ = NODE,5, G,-; +cpu_est_1_ = NODE,2, G,-; +cpu_est_d_0_ = NODE,15, G,-; +cpu_est_d_3_ = NODE,11, G,-; +inst_AS_030_000_SYNC = NODE,5, H,-; +inst_DTACK_SYNC = NODE,8, A,-; +inst_VPA_D = NODE,0, A,-; +inst_VPA_SYNC = NODE,0, F,-; +inst_CLK_000_D = NODE,1, H,-; +inst_CLK_000_DD = NODE,13, H,-; inst_CLK_OUT_PRE = NODE,10, G,-; -cpu_est_0_ = NODE,11, G,-; -cpu_est_2_ = NODE,7, G,-; -CLK_CNT_0_ = NODE,15, G,-; +cpu_est_d_1_ = NODE,7, G,-; +cpu_est_d_2_ = NODE,3, G,-; +cpu_est_2_ = NODE,1, G,-; +CLK_CNT_0_ = NODE,14, G,-; SM_AMIGA_6_ = NODE,2, D,-; SM_AMIGA_7_ = NODE,6, G,-; inst_RISING_CLK_AMIGA = NODE,9, H,-; +SM_AMIGA_1_ = NODE,12, G,-; SM_AMIGA_4_ = NODE,13, D,-; -SM_AMIGA_3_ = NODE,13, G,-; +SM_AMIGA_3_ = NODE,8, G,-; SM_AMIGA_5_ = NODE,6, D,-; -CLK_000_CNT_0_ = NODE,5, H,-; -CLK_000_CNT_1_ = NODE,5, G,-; -CLK_000_CNT_2_ = NODE,13, H,-; -CLK_000_CNT_3_ = NODE,2, H,-; -SM_AMIGA_2_ = NODE,9, G,-; -SM_AMIGA_1_ = NODE,1, G,-; -SM_AMIGA_0_ = NODE,8, G,-; -SM_AMIGA_D_0_ = NODE,13, B,-; -SM_AMIGA_D_1_ = NODE,9, B,-; -SM_AMIGA_D_2_ = NODE,2, G,-; -un1_UDS_000_INT_0_sqmuxa_2_0 = NODE,10, D,-; +SM_AMIGA_2_ = NODE,13, G,-; +SM_AMIGA_0_ = NODE,9, G,-; +SM_AMIGA_D_0_ = NODE,6, B,-; +SM_AMIGA_D_1_ = NODE,13, B,-; +SM_AMIGA_D_2_ = NODE,9, B,-; diff --git a/Logic/68030_tk.xrf b/Logic/68030_tk.xrf index 75952e4..d28f785 100644 --- a/Logic/68030_tk.xrf +++ b/Logic/68030_tk.xrf @@ -2,7 +2,7 @@ Signal Name Cross Reference File ispLEVER Classic 1.7.00.05.28.13 -Design '68030_tk' created Thu May 15 19:20:52 2014 +Design '68030_tk' created Thu May 15 22:17:27 2014 LEGEND: '>' Functional Block Port Separator diff --git a/Logic/BUS68030.bl0 b/Logic/BUS68030.bl0 index 0bd7084..51ee47f 100644 --- a/Logic/BUS68030.bl0 +++ b/Logic/BUS68030.bl0 @@ -1,150 +1,138 @@ -#$ DATE Thu May 15 19:20:52 2014 +#$ DATE Thu May 15 22:17:27 2014 #$ TOOL EDIF2BLIF version IspLever 1.0 #$ MODULE bus68030 -#$ PINS 74 A_30_ A_29_ SIZE_1_ A_28_ A_27_ A_31_ A_26_ A_25_ IPL_030_2_ A_24_ A_23_ IPL_2_ A_22_ A_21_ DSACK_1_ A_20_ A_19_ FC_1_ A_18_ AS_030 A_17_ AS_000 A_16_ DS_030 A_15_ UDS_000 A_14_ LDS_000 A_13_ CPU_SPACE A_12_ BERR A_11_ BG_030 A_10_ BG_000 A_9_ BGACK_030 A_8_ BGACK_000 A_7_ CLK_030 A_6_ CLK_000 A_5_ CLK_OSZI A_4_ CLK_DIV_OUT A_3_ CLK_EXP A_2_ FPU_CS A_1_ DTACK A_0_ AVEC IPL_030_1_ AVEC_EXP IPL_030_0_ E IPL_1_ VPA IPL_0_ VMA DSACK_0_ RST FC_0_ RESET RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ -#$ NODES 414 a_15__n a_c_22__n a_14__n a_c_23__n a_13__n a_c_24__n a_12__n inst_BGACK_030_INTreg a_c_25__n inst_CLK_OUT_INTreg \ -# a_11__n inst_FPU_CS_INTreg a_c_26__n cpu_est_3_reg a_10__n inst_VMA_INTreg a_c_27__n gnd_n_n a_9__n cpu_est_1_ \ -# a_c_28__n inst_AS_000_INTreg a_8__n inst_AS_030_000_SYNC a_c_29__n inst_DTACK_SYNC a_7__n inst_VPA_D a_c_30__n inst_VPA_SYNC \ -# a_6__n inst_CLK_000_D a_c_31__n inst_CLK_000_DD a_5__n inst_CLK_OUT_PRE CPU_SPACE_c vcc_n_n a_4__n cpu_est_0_ \ -# cpu_est_2_ BG_030_c a_3__n CLK_CNT_0_ SM_AMIGA_6_ BG_000DFFSHreg a_2__n SM_AMIGA_7_ inst_UDS_000_INTreg a_1__n \ -# inst_LDS_000_INTreg BGACK_000_c inst_RISING_CLK_AMIGA DSACK_INT_1_ CLK_030_c inst_DTACK_DMA SM_AMIGA_4_ CLK_000_c SM_AMIGA_3_ SM_AMIGA_5_ \ -# CLK_OSZI_c un1_clk_000_cnt_3__n CLK_000_CNT_0_ CLK_000_CNT_1_ CLK_000_CNT_2_ CLK_000_CNT_3_ IPL_030DFFSH_0_reg state_machine_un14_as_000_int_n SM_AMIGA_2_ IPL_030DFFSH_1_reg \ -# SM_AMIGA_1_ SM_AMIGA_0_ IPL_030DFFSH_2_reg SM_AMIGA_D_0_ SM_AMIGA_D_1_ ipl_c_0__n SM_AMIGA_D_2_ clk_exp ipl_c_1__n G_128 \ -# G_130 ipl_c_2__n G_132 dsack_c_1__n DTACK_c RST_c RESETDFFreg RW_c cpu_est_0_0_ fc_c_0__n \ -# fc_c_1__n CLK_OUT_PRE_0 N_123 N_148_i clk_rising_clk_amiga_1_n N_147_i G_122 VMA_INT_1_sqmuxa_0 G_123 N_170_i \ -# G_124 N_171_i DSACK_INT_1_sqmuxa N_161_i N_120 N_164_i N_144_1 N_165_i N_251 N_168_i \ -# N_254 N_166_i N_186 N_167_i un1_clk_000_cnt_0__n N_169_i N_184 clk_cpu_est_11_0_1__n un1_clk_000_cnt_1__n N_173_i \ -# un1_clk_000_cnt_2__n N_172_i state_machine_un69_clk_000_d_n N_174_i state_machine_un78_clk_000_d_n clk_cpu_est_11_0_3__n N_149 N_121_i N_119 N_126_0 \ -# N_135 N_123_0 state_machine_un67_clk_000_d_n N_122_0 state_machine_un80_clk_000_d_n N_142_i N_132 N_143_i N_131 sm_amiga_ns_0_5__n \ -# state_machine_un25_clk_000_d_n N_141_i N_150 N_140_i N_151 sm_amiga_ns_0_4__n N_144 N_146 LDS_000_INT_1_sqmuxa_i N_143 \ -# un1_UDS_000_INT_0_sqmuxa_2_0 N_145 UDS_000_INT_0_sqmuxa_i state_machine_lds_000_int_8_n un1_UDS_000_INT_0_sqmuxa_i un1_UDS_000_INT_0_sqmuxa_2 N_124_0 state_machine_uds_000_int_8_n N_136_i LDS_000_INT_0_sqmuxa \ -# state_machine_un42_clk_030_n RISING_CLK_AMIGA_i un1_bg_030 state_machine_un4_bgack_000_0_n N_133 BG_030_c_i state_machine_as_030_000_sync_3_n state_machine_un1_clk_030_0_n N_125 state_machine_un17_clk_030_0_n \ -# N_137 un1_as_030_2_0 N_138 N_137_i DSACK_INT_1_sqmuxa_1 N_138_i un1_as_030_2 state_machine_un17_clk_030_n N_120_i state_machine_un1_clk_030_n \ -# N_125_0 state_machine_un4_bgack_000_n state_machine_as_030_000_sync_3_2_n VPA_SYNC_1_sqmuxa N_133_i VPA_SYNC_1_sqmuxa_1 un1_bg_030_0 N_122 a_c_i_0__n AS_000_INT_1_sqmuxa \ -# state_machine_uds_000_int_8_0_n N_136 state_machine_lds_000_int_8_0_n N_124 N_151_i N_130 state_machine_un15_clk_000_d_n N_146_i un1_UDS_000_INT_0_sqmuxa N_145_i \ -# UDS_000_INT_0_sqmuxa sm_amiga_ns_0_7__n LDS_000_INT_1_sqmuxa N_144_i N_139 N_150_i N_140 N_126 size_c_i_1__n N_141 \ -# state_machine_un25_clk_000_d_i_n N_121 state_machine_un80_clk_000_d_i_n N_142 state_machine_un67_clk_000_d_i_n VPA_SYNC_1_sqmuxa_1_0 state_machine_un78_clk_000_d_0_n DTACK_SYNC_1_sqmuxa clk_rising_clk_amiga_1_i_n DTACK_SYNC_1_sqmuxa_1 \ -# N_135_i N_149_2 N_104_i clk_un3_clk_000_dd_n N_149_i N_164 N_119_0 N_171 clk_000_cnt_i_1__n N_170 \ -# clk_000_cnt_i_0__n clk_cpu_est_11_3__n clk_000_cnt_i_3__n N_174 clk_000_cnt_i_2__n N_172 state_machine_un69_clk_000_d_0_n N_173 state_machine_un69_clk_000_d_0_1_n clk_cpu_est_11_1__n \ -# state_machine_un69_clk_000_d_0_2_n N_169 state_machine_un25_clk_000_d_i_1_n N_167 N_116_i_1 N_166 un1_bg_030_0_1 N_168 un1_bg_030_0_2 N_165 \ -# state_machine_as_030_000_sync_3_2_1_n VMA_INT_1_sqmuxa un1_UDS_000_INT_0_sqmuxa_i_1 N_147 clk_cpu_est_11_0_1_3__n N_148 clk_cpu_est_11_0_1_1__n RW_i clk_cpu_est_11_0_2_1__n clk_exp_i \ -# N_251_1 CLK_000_DD_i N_251_2 CLK_000_D_i N_251_3 AS_000_INT_i N_251_4 cpu_est_i_0__n N_251_5 cpu_est_i_2__n \ -# N_251_6 cpu_est_i_3__n N_254_1 cpu_est_i_1__n N_254_2 N_149_2_i DSACK_INT_1_sqmuxa_1_0 VPA_D_i DSACK_INT_1_sqmuxa_2 DTACK_i \ -# DSACK_INT_1_sqmuxa_3 VPA_SYNC_i N_149_1 DTACK_SYNC_i N_149_2_0 AS_030_i N_132_1 DTACK_SYNC_1_sqmuxa_i N_131_1 DS_030_i \ -# state_machine_un42_clk_030_1_n sm_amiga_i_4__n state_machine_un42_clk_030_2_n sm_amiga_i_6__n state_machine_un42_clk_030_3_n sm_amiga_i_5__n state_machine_un42_clk_030_4_n N_139_i state_machine_un42_clk_030_5_n state_machine_un15_clk_000_d_i_n \ -# N_142_1 N_130_i N_130_1 sm_amiga_i_0__n N_130_2 sm_amiga_i_7__n UDS_000_INT_0_sqmuxa_1 VPA_SYNC_1_sqmuxa_i UDS_000_INT_0_sqmuxa_2 dsack_i_1__n \ -# DTACK_SYNC_1_sqmuxa_1_0 DSACK_INT_1_sqmuxa_i VPA_SYNC_1_sqmuxa_1_1 a_i_18__n VPA_SYNC_1_sqmuxa_2 a_i_16__n VPA_SYNC_1_sqmuxa_3 a_i_19__n N_171_1 CLK_030_i \ -# N_170_1 state_machine_un42_clk_030_i_n N_174_1 AS_030_000_SYNC_i clk_exp_1 N_131_i cpu_est_0_1__un3_n N_132_i cpu_est_0_1__un1_n sm_amiga_i_2__n \ -# cpu_est_0_1__un0_n sm_amiga_i_1__n vma_int_0_un3_n sm_amiga_i_3__n vma_int_0_un1_n CLK_000_i vma_int_0_un0_n a_i_30__n cpu_est_0_3__un3_n a_i_31__n \ -# cpu_est_0_3__un1_n a_i_28__n cpu_est_0_3__un0_n a_i_29__n cpu_est_0_2__un3_n a_i_26__n cpu_est_0_2__un1_n a_i_27__n cpu_est_0_2__un0_n a_i_24__n \ -# dtack_sync_0_un3_n a_i_25__n dtack_sync_0_un1_n dtack_sync_0_un0_n sm_amiga_d_0_0__un3_n RST_i sm_amiga_d_0_0__un1_n sm_amiga_d_0_0__un0_n FPU_CS_INT_i bgack_030_int_0_un3_n \ -# CPU_SPACE_i bgack_030_int_0_un1_n BGACK_030_INT_i bgack_030_int_0_un0_n AS_030_c bg_000_0_un3_n bg_000_0_un1_n bg_000_0_un0_n DS_030_c as_030_000_sync_0_un3_n \ -# as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n fpu_cs_int_0_un3_n size_c_0__n fpu_cs_int_0_un1_n fpu_cs_int_0_un0_n size_c_1__n dsack_int_0_1__un3_n dsack_int_0_1__un1_n a_c_0__n \ -# dsack_int_0_1__un0_n vpa_sync_0_un3_n vpa_sync_0_un1_n vpa_sync_0_un0_n as_000_int_0_un3_n as_000_int_0_un1_n as_000_int_0_un0_n ipl_030_0_2__un3_n ipl_030_0_2__un1_n ipl_030_0_2__un0_n \ -# ipl_030_0_1__un3_n ipl_030_0_1__un1_n ipl_030_0_1__un0_n ipl_030_0_0__un3_n ipl_030_0_0__un1_n ipl_030_0_0__un0_n sm_amiga_d_0_2__un3_n a_c_16__n sm_amiga_d_0_2__un1_n sm_amiga_d_0_2__un0_n \ -# a_c_17__n sm_amiga_d_0_1__un3_n sm_amiga_d_0_1__un1_n a_c_18__n sm_amiga_d_0_1__un0_n lds_000_int_0_un3_n a_c_19__n lds_000_int_0_un1_n lds_000_int_0_un0_n a_c_20__n \ -# uds_000_int_0_un3_n uds_000_int_0_un1_n a_c_21__n uds_000_int_0_un0_n +#$ PINS 74 FC_0_ SIZE_1_ A_31_ IPL_030_2_ IPL_2_ DSACK_1_ FC_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 CPU_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT SIZE_0_ CLK_EXP A_30_ FPU_CS A_29_ DTACK A_28_ AVEC A_27_ AVEC_EXP A_26_ E A_25_ VPA A_24_ VMA A_23_ RST A_22_ RESET A_21_ RW A_20_ AMIGA_BUS_ENABLE A_19_ AMIGA_BUS_DATA_DIR A_18_ AMIGA_BUS_ENABLE_LOW A_17_ CIIN A_16_ A_15_ A_14_ A_13_ A_12_ A_11_ A_10_ A_9_ A_8_ A_7_ A_6_ A_5_ A_4_ A_3_ A_2_ A_1_ A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ IPL_0_ DSACK_0_ +#$ NODES 378 a_c_30__n a_c_31__n CPU_SPACE_c inst_BGACK_030_INTreg BG_030_c inst_CLK_OUT_INTreg inst_FPU_CS_INTreg BG_000DFFSHreg cpu_est_3_reg inst_VMA_INTreg \ +# gnd_n_n BGACK_000_c cpu_est_0_ cpu_est_1_ CLK_030_c cpu_est_d_0_ cpu_est_d_3_ CLK_000_c inst_AS_000_INTreg inst_AS_030_000_SYNC \ +# CLK_OSZI_c inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D inst_CLK_000_DD IPL_030DFFSH_0_reg inst_CLK_OUT_PRE vcc_n_n IPL_030DFFSH_1_reg \ +# cpu_est_d_1_ cpu_est_d_2_ IPL_030DFFSH_2_reg cpu_est_2_ CLK_CNT_0_ ipl_c_0__n SM_AMIGA_6_ SM_AMIGA_7_ ipl_c_1__n inst_UDS_000_INTreg \ +# inst_LDS_000_INTreg ipl_c_2__n inst_RISING_CLK_AMIGA state_machine_un57_clk_000_d_n dsack_c_1__n SM_AMIGA_1_ DSACK_INT_1_ DTACK_c inst_DTACK_DMA SM_AMIGA_4_ \ +# SM_AMIGA_3_ state_machine_un13_as_000_int_n SM_AMIGA_5_ SM_AMIGA_2_ SM_AMIGA_0_ SM_AMIGA_D_0_ RST_c SM_AMIGA_D_1_ SM_AMIGA_D_2_ RESETDFFreg \ +# clk_exp RW_c fc_c_0__n fc_c_1__n state_machine_un57_clk_000_d_0_n N_161_i a_c_i_0__n state_machine_uds_000_int_8_0_n state_machine_lds_000_int_8_0_n N_113_i \ +# cpu_est_0_0_ sm_amiga_ns_0_2__n N_118_i N_117_i sm_amiga_ns_0_5__n N_123_i CLK_OUT_PRE_0 N_119_i N_120_i sm_amiga_ns_0_7__n \ +# CLK_OUT_PRE_i N_106 N_102_0 N_107 size_c_i_1__n clk_un3_clk_000_dd_n state_machine_un31_clk_000_d_i_n clk_cpu_est_11_1__n RISING_CLK_AMIGA_i clk_cpu_est_11_3__n \ +# state_machine_un4_bgack_000_0_n G_98 BG_030_c_i G_99 state_machine_un1_clk_030_0_n G_100 state_machine_un17_clk_030_0_n N_161 un1_as_030_2_0 N_114 \ +# state_machine_as_030_000_sync_3_2_n N_109 N_109_i N_111 un1_bg_030_0 N_112 N_111_i N_122 N_122_i N_115 \ +# N_101 N_147_i N_116 clk_cpu_est_11_0_3__n N_124 N_145_i N_139 N_146_i N_137 N_142_i \ +# N_140 clk_cpu_est_11_0_1__n N_141 N_140_i N_136 N_139_i N_142 N_141_i N_145 N_138_i \ +# N_138 N_137_i N_146 N_136_i N_143 N_143_i N_144 N_144_i UDS_000_INT_0_sqmuxa N_134_i \ +# UDS_000_INT_0_sqmuxa_1 N_101_0 N_147 N_115_i N_147_1 N_116_i state_machine_un13_clk_000_d_1_n N_186 N_124_i N_189 \ +# state_machine_un42_clk_030_n N_112_i un1_bg_030 sm_amiga_ns_0_0__n state_machine_as_030_000_sync_3_n N_86_i_1 un1_as_030_2 un1_bg_030_0_1 state_machine_un17_clk_030_n un1_bg_030_0_2 \ +# state_machine_un1_clk_030_n state_machine_as_030_000_sync_3_2_1_n state_machine_un4_bgack_000_n state_machine_un31_clk_000_d_i_1_n N_108 N_186_1 state_machine_un31_clk_000_d_n N_186_2 state_machine_un13_clk_000_d_n N_186_3 \ +# state_machine_un13_clk_000_d_4_n N_186_4 state_machine_un8_clk_000_d_n N_186_5 DTACK_SYNC_1_sqmuxa N_186_6 VPA_SYNC_1_sqmuxa_1_0 N_189_1 VPA_SYNC_1_sqmuxa N_189_2 \ +# N_123 clk_cpu_est_11_0_1_1__n N_118 clk_cpu_est_11_0_2_1__n N_110 clk_cpu_est_11_0_1_3__n N_102 N_143_1 N_120 N_144_1 \ +# N_119 N_106_1 N_117 N_106_2 N_113 N_107_1 state_machine_lds_000_int_8_n UDS_000_INT_0_sqmuxa_1_1 state_machine_uds_000_int_8_n UDS_000_INT_0_sqmuxa_1_2 \ +# DTACK_SYNC_1_sqmuxa_1 UDS_000_INT_0_sqmuxa_1_3 un2_clk_030_1 UDS_000_INT_0_sqmuxa_1_0 VPA_SYNC_1_sqmuxa_1 UDS_000_INT_0_sqmuxa_2 AS_000_INT_1_sqmuxa state_machine_un42_clk_030_1_n VMA_INT_1_sqmuxa state_machine_un42_clk_030_2_n \ +# DSACK_INT_1_sqmuxa state_machine_un42_clk_030_3_n RW_i state_machine_un42_clk_030_4_n clk_exp_i state_machine_un42_clk_030_5_n DTACK_SYNC_1_sqmuxa_i state_machine_un13_clk_000_d_1_0_n N_114_i state_machine_un13_clk_000_d_4_1_n \ +# VPA_SYNC_1_sqmuxa_i state_machine_un8_clk_000_d_1_n N_110_i state_machine_un8_clk_000_d_2_n N_108_i state_machine_un8_clk_000_d_3_n cpu_est_d_i_3__n state_machine_un8_clk_000_d_4_n cpu_est_d_i_0__n DTACK_SYNC_1_sqmuxa_1_0 \ +# CLK_000_D_i VPA_SYNC_1_sqmuxa_1_1 AS_030_i VPA_SYNC_1_sqmuxa_2 AS_000_INT_i VPA_SYNC_1_sqmuxa_3 dsack_i_1__n VPA_SYNC_1_sqmuxa_4 state_machine_un13_clk_000_d_i_n N_108_1 \ +# state_machine_un8_clk_000_d_i_n N_118_1 state_machine_un13_clk_000_d_1_i_n N_110_1 sm_amiga_i_1__n clk_exp_1 sm_amiga_i_2__n sm_amiga_d_0_2__un3_n sm_amiga_i_0__n sm_amiga_d_0_2__un1_n \ +# sm_amiga_i_3__n sm_amiga_d_0_2__un0_n VPA_D_i dsack_int_0_1__un3_n VMA_INT_i dsack_int_0_1__un1_n DTACK_i dsack_int_0_1__un0_n cpu_est_i_3__n vma_int_0_un3_n \ +# a_i_18__n vma_int_0_un1_n a_i_16__n vma_int_0_un0_n a_i_19__n vpa_sync_0_un3_n CLK_030_i vpa_sync_0_un1_n state_machine_un42_clk_030_i_n vpa_sync_0_un0_n \ +# DS_030_i as_000_int_0_un3_n cpu_est_i_1__n as_000_int_0_un1_n AS_030_000_SYNC_i as_000_int_0_un0_n cpu_est_i_0__n dtack_sync_0_un3_n sm_amiga_i_4__n dtack_sync_0_un1_n \ +# sm_amiga_i_6__n dtack_sync_0_un0_n cpu_est_i_2__n lds_000_int_0_un3_n UDS_000_INT_0_sqmuxa_1_i lds_000_int_0_un1_n UDS_000_INT_0_sqmuxa_i lds_000_int_0_un0_n sm_amiga_i_5__n uds_000_int_0_un3_n \ +# CLK_000_DD_i uds_000_int_0_un1_n sm_amiga_i_7__n uds_000_int_0_un0_n a_i_30__n bg_000_0_un3_n a_i_31__n bg_000_0_un1_n a_i_28__n bg_000_0_un0_n \ +# a_i_29__n as_030_000_sync_0_un3_n a_i_26__n as_030_000_sync_0_un1_n a_i_27__n as_030_000_sync_0_un0_n a_i_24__n fpu_cs_int_0_un3_n a_i_25__n fpu_cs_int_0_un1_n \ +# fpu_cs_int_0_un0_n ipl_030_0_2__un3_n RST_i ipl_030_0_2__un1_n N_107_i ipl_030_0_2__un0_n N_106_i ipl_030_0_1__un3_n FPU_CS_INT_i ipl_030_0_1__un1_n \ +# CPU_SPACE_i ipl_030_0_1__un0_n BGACK_030_INT_i ipl_030_0_0__un3_n AS_030_c ipl_030_0_0__un1_n ipl_030_0_0__un0_n bgack_030_int_0_un3_n DS_030_c bgack_030_int_0_un1_n \ +# bgack_030_int_0_un0_n sm_amiga_d_0_0__un3_n sm_amiga_d_0_0__un1_n size_c_0__n sm_amiga_d_0_0__un0_n sm_amiga_d_0_1__un3_n size_c_1__n sm_amiga_d_0_1__un1_n sm_amiga_d_0_1__un0_n a_c_0__n \ +# cpu_est_0_1__un3_n cpu_est_0_1__un1_n cpu_est_0_1__un0_n cpu_est_0_2__un3_n cpu_est_0_2__un1_n cpu_est_0_2__un0_n cpu_est_0_3__un3_n cpu_est_0_3__un1_n cpu_est_0_3__un0_n a_15__n \ +# a_14__n a_13__n a_12__n a_c_16__n a_11__n a_c_17__n a_10__n a_c_18__n a_9__n a_c_19__n \ +# a_8__n a_c_20__n a_7__n a_c_21__n a_6__n a_c_22__n a_5__n a_c_23__n a_4__n a_c_24__n \ +# a_3__n a_c_25__n a_2__n a_c_26__n a_1__n a_c_27__n a_c_28__n a_c_29__n .model bus68030 .inputs SIZE_1_.BLIF A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF AS_030.BLIF DS_030.BLIF CPU_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF \ CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF VPA.BLIF RST.BLIF RW.BLIF SIZE_0_.BLIF A_30_.BLIF A_29_.BLIF \ A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF \ A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF A_15_.BLIF A_14_.BLIF A_13_.BLIF A_12_.BLIF A_11_.BLIF \ A_10_.BLIF A_9_.BLIF A_8_.BLIF A_7_.BLIF A_6_.BLIF A_5_.BLIF A_4_.BLIF A_3_.BLIF A_2_.BLIF \ - A_1_.BLIF A_0_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF DSACK_1_.BLIF DTACK.BLIF DSACK_0_.BLIF a_15__n.BLIF a_c_22__n.BLIF a_14__n.BLIF a_c_23__n.BLIF \ - a_13__n.BLIF a_c_24__n.BLIF a_12__n.BLIF inst_BGACK_030_INTreg.BLIF a_c_25__n.BLIF inst_CLK_OUT_INTreg.BLIF a_11__n.BLIF inst_FPU_CS_INTreg.BLIF a_c_26__n.BLIF \ - cpu_est_3_reg.BLIF a_10__n.BLIF inst_VMA_INTreg.BLIF a_c_27__n.BLIF gnd_n_n.BLIF a_9__n.BLIF cpu_est_1_.BLIF a_c_28__n.BLIF inst_AS_000_INTreg.BLIF \ - a_8__n.BLIF inst_AS_030_000_SYNC.BLIF a_c_29__n.BLIF inst_DTACK_SYNC.BLIF a_7__n.BLIF inst_VPA_D.BLIF a_c_30__n.BLIF inst_VPA_SYNC.BLIF a_6__n.BLIF \ - inst_CLK_000_D.BLIF a_c_31__n.BLIF inst_CLK_000_DD.BLIF a_5__n.BLIF inst_CLK_OUT_PRE.BLIF CPU_SPACE_c.BLIF vcc_n_n.BLIF a_4__n.BLIF cpu_est_0_.BLIF \ - cpu_est_2_.BLIF BG_030_c.BLIF a_3__n.BLIF CLK_CNT_0_.BLIF SM_AMIGA_6_.BLIF BG_000DFFSHreg.BLIF a_2__n.BLIF SM_AMIGA_7_.BLIF inst_UDS_000_INTreg.BLIF \ - a_1__n.BLIF inst_LDS_000_INTreg.BLIF BGACK_000_c.BLIF inst_RISING_CLK_AMIGA.BLIF DSACK_INT_1_.BLIF CLK_030_c.BLIF inst_DTACK_DMA.BLIF SM_AMIGA_4_.BLIF CLK_000_c.BLIF \ - SM_AMIGA_3_.BLIF SM_AMIGA_5_.BLIF CLK_OSZI_c.BLIF un1_clk_000_cnt_3__n.BLIF CLK_000_CNT_0_.BLIF CLK_000_CNT_1_.BLIF CLK_000_CNT_2_.BLIF CLK_000_CNT_3_.BLIF IPL_030DFFSH_0_reg.BLIF \ - state_machine_un14_as_000_int_n.BLIF SM_AMIGA_2_.BLIF IPL_030DFFSH_1_reg.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_0_.BLIF IPL_030DFFSH_2_reg.BLIF SM_AMIGA_D_0_.BLIF SM_AMIGA_D_1_.BLIF ipl_c_0__n.BLIF \ - SM_AMIGA_D_2_.BLIF clk_exp.BLIF ipl_c_1__n.BLIF G_128.BLIF G_130.BLIF ipl_c_2__n.BLIF G_132.BLIF dsack_c_1__n.BLIF DTACK_c.BLIF \ - RST_c.BLIF RESETDFFreg.BLIF RW_c.BLIF cpu_est_0_0_.BLIF fc_c_0__n.BLIF fc_c_1__n.BLIF CLK_OUT_PRE_0.BLIF N_123.BLIF N_148_i.BLIF \ - clk_rising_clk_amiga_1_n.BLIF N_147_i.BLIF G_122.BLIF VMA_INT_1_sqmuxa_0.BLIF G_123.BLIF N_170_i.BLIF G_124.BLIF N_171_i.BLIF DSACK_INT_1_sqmuxa.BLIF \ - N_161_i.BLIF N_120.BLIF N_164_i.BLIF N_144_1.BLIF N_165_i.BLIF N_251.BLIF N_168_i.BLIF N_254.BLIF N_166_i.BLIF \ - N_186.BLIF N_167_i.BLIF un1_clk_000_cnt_0__n.BLIF N_169_i.BLIF N_184.BLIF clk_cpu_est_11_0_1__n.BLIF un1_clk_000_cnt_1__n.BLIF N_173_i.BLIF un1_clk_000_cnt_2__n.BLIF \ - N_172_i.BLIF state_machine_un69_clk_000_d_n.BLIF N_174_i.BLIF state_machine_un78_clk_000_d_n.BLIF clk_cpu_est_11_0_3__n.BLIF N_149.BLIF N_121_i.BLIF N_119.BLIF N_126_0.BLIF \ - N_135.BLIF N_123_0.BLIF state_machine_un67_clk_000_d_n.BLIF N_122_0.BLIF state_machine_un80_clk_000_d_n.BLIF N_142_i.BLIF N_132.BLIF N_143_i.BLIF N_131.BLIF \ - sm_amiga_ns_0_5__n.BLIF state_machine_un25_clk_000_d_n.BLIF N_141_i.BLIF N_150.BLIF N_140_i.BLIF N_151.BLIF sm_amiga_ns_0_4__n.BLIF N_144.BLIF N_146.BLIF \ - LDS_000_INT_1_sqmuxa_i.BLIF N_143.BLIF un1_UDS_000_INT_0_sqmuxa_2_0.BLIF N_145.BLIF UDS_000_INT_0_sqmuxa_i.BLIF state_machine_lds_000_int_8_n.BLIF un1_UDS_000_INT_0_sqmuxa_i.BLIF un1_UDS_000_INT_0_sqmuxa_2.BLIF N_124_0.BLIF \ - state_machine_uds_000_int_8_n.BLIF N_136_i.BLIF LDS_000_INT_0_sqmuxa.BLIF state_machine_un42_clk_030_n.BLIF RISING_CLK_AMIGA_i.BLIF un1_bg_030.BLIF state_machine_un4_bgack_000_0_n.BLIF N_133.BLIF BG_030_c_i.BLIF \ - state_machine_as_030_000_sync_3_n.BLIF state_machine_un1_clk_030_0_n.BLIF N_125.BLIF state_machine_un17_clk_030_0_n.BLIF N_137.BLIF un1_as_030_2_0.BLIF N_138.BLIF N_137_i.BLIF DSACK_INT_1_sqmuxa_1.BLIF \ - N_138_i.BLIF un1_as_030_2.BLIF state_machine_un17_clk_030_n.BLIF N_120_i.BLIF state_machine_un1_clk_030_n.BLIF N_125_0.BLIF state_machine_un4_bgack_000_n.BLIF state_machine_as_030_000_sync_3_2_n.BLIF VPA_SYNC_1_sqmuxa.BLIF \ - N_133_i.BLIF VPA_SYNC_1_sqmuxa_1.BLIF un1_bg_030_0.BLIF N_122.BLIF a_c_i_0__n.BLIF AS_000_INT_1_sqmuxa.BLIF state_machine_uds_000_int_8_0_n.BLIF N_136.BLIF state_machine_lds_000_int_8_0_n.BLIF \ - N_124.BLIF N_151_i.BLIF N_130.BLIF state_machine_un15_clk_000_d_n.BLIF N_146_i.BLIF un1_UDS_000_INT_0_sqmuxa.BLIF N_145_i.BLIF UDS_000_INT_0_sqmuxa.BLIF sm_amiga_ns_0_7__n.BLIF \ - LDS_000_INT_1_sqmuxa.BLIF N_144_i.BLIF N_139.BLIF N_150_i.BLIF N_140.BLIF N_126.BLIF size_c_i_1__n.BLIF N_141.BLIF state_machine_un25_clk_000_d_i_n.BLIF \ - N_121.BLIF state_machine_un80_clk_000_d_i_n.BLIF N_142.BLIF state_machine_un67_clk_000_d_i_n.BLIF VPA_SYNC_1_sqmuxa_1_0.BLIF state_machine_un78_clk_000_d_0_n.BLIF DTACK_SYNC_1_sqmuxa.BLIF clk_rising_clk_amiga_1_i_n.BLIF DTACK_SYNC_1_sqmuxa_1.BLIF \ - N_135_i.BLIF N_149_2.BLIF N_104_i.BLIF clk_un3_clk_000_dd_n.BLIF N_149_i.BLIF N_164.BLIF N_119_0.BLIF N_171.BLIF clk_000_cnt_i_1__n.BLIF \ - N_170.BLIF clk_000_cnt_i_0__n.BLIF clk_cpu_est_11_3__n.BLIF clk_000_cnt_i_3__n.BLIF N_174.BLIF clk_000_cnt_i_2__n.BLIF N_172.BLIF state_machine_un69_clk_000_d_0_n.BLIF N_173.BLIF \ - state_machine_un69_clk_000_d_0_1_n.BLIF clk_cpu_est_11_1__n.BLIF state_machine_un69_clk_000_d_0_2_n.BLIF N_169.BLIF state_machine_un25_clk_000_d_i_1_n.BLIF N_167.BLIF N_116_i_1.BLIF N_166.BLIF un1_bg_030_0_1.BLIF \ - N_168.BLIF un1_bg_030_0_2.BLIF N_165.BLIF state_machine_as_030_000_sync_3_2_1_n.BLIF VMA_INT_1_sqmuxa.BLIF un1_UDS_000_INT_0_sqmuxa_i_1.BLIF N_147.BLIF clk_cpu_est_11_0_1_3__n.BLIF N_148.BLIF \ - clk_cpu_est_11_0_1_1__n.BLIF RW_i.BLIF clk_cpu_est_11_0_2_1__n.BLIF clk_exp_i.BLIF N_251_1.BLIF CLK_000_DD_i.BLIF N_251_2.BLIF CLK_000_D_i.BLIF N_251_3.BLIF \ - AS_000_INT_i.BLIF N_251_4.BLIF cpu_est_i_0__n.BLIF N_251_5.BLIF cpu_est_i_2__n.BLIF N_251_6.BLIF cpu_est_i_3__n.BLIF N_254_1.BLIF cpu_est_i_1__n.BLIF \ - N_254_2.BLIF N_149_2_i.BLIF DSACK_INT_1_sqmuxa_1_0.BLIF VPA_D_i.BLIF DSACK_INT_1_sqmuxa_2.BLIF DTACK_i.BLIF DSACK_INT_1_sqmuxa_3.BLIF VPA_SYNC_i.BLIF N_149_1.BLIF \ - DTACK_SYNC_i.BLIF N_149_2_0.BLIF AS_030_i.BLIF N_132_1.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF N_131_1.BLIF DS_030_i.BLIF state_machine_un42_clk_030_1_n.BLIF sm_amiga_i_4__n.BLIF \ - state_machine_un42_clk_030_2_n.BLIF sm_amiga_i_6__n.BLIF state_machine_un42_clk_030_3_n.BLIF sm_amiga_i_5__n.BLIF state_machine_un42_clk_030_4_n.BLIF N_139_i.BLIF state_machine_un42_clk_030_5_n.BLIF state_machine_un15_clk_000_d_i_n.BLIF N_142_1.BLIF \ - N_130_i.BLIF N_130_1.BLIF sm_amiga_i_0__n.BLIF N_130_2.BLIF sm_amiga_i_7__n.BLIF UDS_000_INT_0_sqmuxa_1.BLIF VPA_SYNC_1_sqmuxa_i.BLIF UDS_000_INT_0_sqmuxa_2.BLIF dsack_i_1__n.BLIF \ - DTACK_SYNC_1_sqmuxa_1_0.BLIF DSACK_INT_1_sqmuxa_i.BLIF VPA_SYNC_1_sqmuxa_1_1.BLIF a_i_18__n.BLIF VPA_SYNC_1_sqmuxa_2.BLIF a_i_16__n.BLIF VPA_SYNC_1_sqmuxa_3.BLIF a_i_19__n.BLIF N_171_1.BLIF \ - CLK_030_i.BLIF N_170_1.BLIF state_machine_un42_clk_030_i_n.BLIF N_174_1.BLIF AS_030_000_SYNC_i.BLIF clk_exp_1.BLIF N_131_i.BLIF cpu_est_0_1__un3_n.BLIF N_132_i.BLIF \ - cpu_est_0_1__un1_n.BLIF sm_amiga_i_2__n.BLIF cpu_est_0_1__un0_n.BLIF sm_amiga_i_1__n.BLIF vma_int_0_un3_n.BLIF sm_amiga_i_3__n.BLIF vma_int_0_un1_n.BLIF CLK_000_i.BLIF vma_int_0_un0_n.BLIF \ - a_i_30__n.BLIF cpu_est_0_3__un3_n.BLIF a_i_31__n.BLIF cpu_est_0_3__un1_n.BLIF a_i_28__n.BLIF cpu_est_0_3__un0_n.BLIF a_i_29__n.BLIF cpu_est_0_2__un3_n.BLIF a_i_26__n.BLIF \ - cpu_est_0_2__un1_n.BLIF a_i_27__n.BLIF cpu_est_0_2__un0_n.BLIF a_i_24__n.BLIF dtack_sync_0_un3_n.BLIF a_i_25__n.BLIF dtack_sync_0_un1_n.BLIF dtack_sync_0_un0_n.BLIF sm_amiga_d_0_0__un3_n.BLIF \ - RST_i.BLIF sm_amiga_d_0_0__un1_n.BLIF sm_amiga_d_0_0__un0_n.BLIF FPU_CS_INT_i.BLIF bgack_030_int_0_un3_n.BLIF CPU_SPACE_i.BLIF bgack_030_int_0_un1_n.BLIF BGACK_030_INT_i.BLIF bgack_030_int_0_un0_n.BLIF \ - AS_030_c.BLIF bg_000_0_un3_n.BLIF bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF DS_030_c.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF fpu_cs_int_0_un3_n.BLIF \ - size_c_0__n.BLIF fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF size_c_1__n.BLIF dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un1_n.BLIF a_c_0__n.BLIF dsack_int_0_1__un0_n.BLIF vpa_sync_0_un3_n.BLIF \ - vpa_sync_0_un1_n.BLIF vpa_sync_0_un0_n.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF ipl_030_0_1__un3_n.BLIF \ - ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF sm_amiga_d_0_2__un3_n.BLIF a_c_16__n.BLIF sm_amiga_d_0_2__un1_n.BLIF sm_amiga_d_0_2__un0_n.BLIF \ - a_c_17__n.BLIF sm_amiga_d_0_1__un3_n.BLIF sm_amiga_d_0_1__un1_n.BLIF a_c_18__n.BLIF sm_amiga_d_0_1__un0_n.BLIF lds_000_int_0_un3_n.BLIF a_c_19__n.BLIF lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF \ - a_c_20__n.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un1_n.BLIF a_c_21__n.BLIF uds_000_int_0_un0_n.BLIF DSACK_1_.PIN DTACK.PIN + A_1_.BLIF A_0_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF DSACK_1_.BLIF DTACK.BLIF DSACK_0_.BLIF a_c_30__n.BLIF a_c_31__n.BLIF CPU_SPACE_c.BLIF inst_BGACK_030_INTreg.BLIF \ + BG_030_c.BLIF inst_CLK_OUT_INTreg.BLIF inst_FPU_CS_INTreg.BLIF BG_000DFFSHreg.BLIF cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF gnd_n_n.BLIF BGACK_000_c.BLIF cpu_est_0_.BLIF \ + cpu_est_1_.BLIF CLK_030_c.BLIF cpu_est_d_0_.BLIF cpu_est_d_3_.BLIF CLK_000_c.BLIF inst_AS_000_INTreg.BLIF inst_AS_030_000_SYNC.BLIF CLK_OSZI_c.BLIF inst_DTACK_SYNC.BLIF \ + inst_VPA_D.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF IPL_030DFFSH_0_reg.BLIF inst_CLK_OUT_PRE.BLIF vcc_n_n.BLIF IPL_030DFFSH_1_reg.BLIF cpu_est_d_1_.BLIF \ + cpu_est_d_2_.BLIF IPL_030DFFSH_2_reg.BLIF cpu_est_2_.BLIF CLK_CNT_0_.BLIF ipl_c_0__n.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_7_.BLIF ipl_c_1__n.BLIF inst_UDS_000_INTreg.BLIF \ + inst_LDS_000_INTreg.BLIF ipl_c_2__n.BLIF inst_RISING_CLK_AMIGA.BLIF state_machine_un57_clk_000_d_n.BLIF dsack_c_1__n.BLIF SM_AMIGA_1_.BLIF DSACK_INT_1_.BLIF DTACK_c.BLIF inst_DTACK_DMA.BLIF \ + SM_AMIGA_4_.BLIF SM_AMIGA_3_.BLIF state_machine_un13_as_000_int_n.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_D_0_.BLIF RST_c.BLIF SM_AMIGA_D_1_.BLIF \ + SM_AMIGA_D_2_.BLIF RESETDFFreg.BLIF clk_exp.BLIF RW_c.BLIF fc_c_0__n.BLIF fc_c_1__n.BLIF state_machine_un57_clk_000_d_0_n.BLIF N_161_i.BLIF a_c_i_0__n.BLIF \ + state_machine_uds_000_int_8_0_n.BLIF state_machine_lds_000_int_8_0_n.BLIF N_113_i.BLIF cpu_est_0_0_.BLIF sm_amiga_ns_0_2__n.BLIF N_118_i.BLIF N_117_i.BLIF sm_amiga_ns_0_5__n.BLIF N_123_i.BLIF \ + CLK_OUT_PRE_0.BLIF N_119_i.BLIF N_120_i.BLIF sm_amiga_ns_0_7__n.BLIF CLK_OUT_PRE_i.BLIF N_106.BLIF N_102_0.BLIF N_107.BLIF size_c_i_1__n.BLIF \ + clk_un3_clk_000_dd_n.BLIF state_machine_un31_clk_000_d_i_n.BLIF clk_cpu_est_11_1__n.BLIF RISING_CLK_AMIGA_i.BLIF clk_cpu_est_11_3__n.BLIF state_machine_un4_bgack_000_0_n.BLIF G_98.BLIF BG_030_c_i.BLIF G_99.BLIF \ + state_machine_un1_clk_030_0_n.BLIF G_100.BLIF state_machine_un17_clk_030_0_n.BLIF N_161.BLIF un1_as_030_2_0.BLIF N_114.BLIF state_machine_as_030_000_sync_3_2_n.BLIF N_109.BLIF N_109_i.BLIF \ + N_111.BLIF un1_bg_030_0.BLIF N_112.BLIF N_111_i.BLIF N_122.BLIF N_122_i.BLIF N_115.BLIF N_101.BLIF N_147_i.BLIF \ + N_116.BLIF clk_cpu_est_11_0_3__n.BLIF N_124.BLIF N_145_i.BLIF N_139.BLIF N_146_i.BLIF N_137.BLIF N_142_i.BLIF N_140.BLIF \ + clk_cpu_est_11_0_1__n.BLIF N_141.BLIF N_140_i.BLIF N_136.BLIF N_139_i.BLIF N_142.BLIF N_141_i.BLIF N_145.BLIF N_138_i.BLIF \ + N_138.BLIF N_137_i.BLIF N_146.BLIF N_136_i.BLIF N_143.BLIF N_143_i.BLIF N_144.BLIF N_144_i.BLIF UDS_000_INT_0_sqmuxa.BLIF \ + N_134_i.BLIF UDS_000_INT_0_sqmuxa_1.BLIF N_101_0.BLIF N_147.BLIF N_115_i.BLIF N_147_1.BLIF N_116_i.BLIF state_machine_un13_clk_000_d_1_n.BLIF N_186.BLIF \ + N_124_i.BLIF N_189.BLIF state_machine_un42_clk_030_n.BLIF N_112_i.BLIF un1_bg_030.BLIF sm_amiga_ns_0_0__n.BLIF state_machine_as_030_000_sync_3_n.BLIF N_86_i_1.BLIF un1_as_030_2.BLIF \ + un1_bg_030_0_1.BLIF state_machine_un17_clk_030_n.BLIF un1_bg_030_0_2.BLIF state_machine_un1_clk_030_n.BLIF state_machine_as_030_000_sync_3_2_1_n.BLIF state_machine_un4_bgack_000_n.BLIF state_machine_un31_clk_000_d_i_1_n.BLIF N_108.BLIF N_186_1.BLIF \ + state_machine_un31_clk_000_d_n.BLIF N_186_2.BLIF state_machine_un13_clk_000_d_n.BLIF N_186_3.BLIF state_machine_un13_clk_000_d_4_n.BLIF N_186_4.BLIF state_machine_un8_clk_000_d_n.BLIF N_186_5.BLIF DTACK_SYNC_1_sqmuxa.BLIF \ + N_186_6.BLIF VPA_SYNC_1_sqmuxa_1_0.BLIF N_189_1.BLIF VPA_SYNC_1_sqmuxa.BLIF N_189_2.BLIF N_123.BLIF clk_cpu_est_11_0_1_1__n.BLIF N_118.BLIF clk_cpu_est_11_0_2_1__n.BLIF \ + N_110.BLIF clk_cpu_est_11_0_1_3__n.BLIF N_102.BLIF N_143_1.BLIF N_120.BLIF N_144_1.BLIF N_119.BLIF N_106_1.BLIF N_117.BLIF \ + N_106_2.BLIF N_113.BLIF N_107_1.BLIF state_machine_lds_000_int_8_n.BLIF UDS_000_INT_0_sqmuxa_1_1.BLIF state_machine_uds_000_int_8_n.BLIF UDS_000_INT_0_sqmuxa_1_2.BLIF DTACK_SYNC_1_sqmuxa_1.BLIF UDS_000_INT_0_sqmuxa_1_3.BLIF \ + un2_clk_030_1.BLIF UDS_000_INT_0_sqmuxa_1_0.BLIF VPA_SYNC_1_sqmuxa_1.BLIF UDS_000_INT_0_sqmuxa_2.BLIF AS_000_INT_1_sqmuxa.BLIF state_machine_un42_clk_030_1_n.BLIF VMA_INT_1_sqmuxa.BLIF state_machine_un42_clk_030_2_n.BLIF DSACK_INT_1_sqmuxa.BLIF \ + state_machine_un42_clk_030_3_n.BLIF RW_i.BLIF state_machine_un42_clk_030_4_n.BLIF clk_exp_i.BLIF state_machine_un42_clk_030_5_n.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF state_machine_un13_clk_000_d_1_0_n.BLIF N_114_i.BLIF state_machine_un13_clk_000_d_4_1_n.BLIF \ + VPA_SYNC_1_sqmuxa_i.BLIF state_machine_un8_clk_000_d_1_n.BLIF N_110_i.BLIF state_machine_un8_clk_000_d_2_n.BLIF N_108_i.BLIF state_machine_un8_clk_000_d_3_n.BLIF cpu_est_d_i_3__n.BLIF state_machine_un8_clk_000_d_4_n.BLIF cpu_est_d_i_0__n.BLIF \ + DTACK_SYNC_1_sqmuxa_1_0.BLIF CLK_000_D_i.BLIF VPA_SYNC_1_sqmuxa_1_1.BLIF AS_030_i.BLIF VPA_SYNC_1_sqmuxa_2.BLIF AS_000_INT_i.BLIF VPA_SYNC_1_sqmuxa_3.BLIF dsack_i_1__n.BLIF VPA_SYNC_1_sqmuxa_4.BLIF \ + state_machine_un13_clk_000_d_i_n.BLIF N_108_1.BLIF state_machine_un8_clk_000_d_i_n.BLIF N_118_1.BLIF state_machine_un13_clk_000_d_1_i_n.BLIF N_110_1.BLIF sm_amiga_i_1__n.BLIF clk_exp_1.BLIF sm_amiga_i_2__n.BLIF \ + sm_amiga_d_0_2__un3_n.BLIF sm_amiga_i_0__n.BLIF sm_amiga_d_0_2__un1_n.BLIF sm_amiga_i_3__n.BLIF sm_amiga_d_0_2__un0_n.BLIF VPA_D_i.BLIF dsack_int_0_1__un3_n.BLIF VMA_INT_i.BLIF dsack_int_0_1__un1_n.BLIF \ + DTACK_i.BLIF dsack_int_0_1__un0_n.BLIF cpu_est_i_3__n.BLIF vma_int_0_un3_n.BLIF a_i_18__n.BLIF vma_int_0_un1_n.BLIF a_i_16__n.BLIF vma_int_0_un0_n.BLIF a_i_19__n.BLIF \ + vpa_sync_0_un3_n.BLIF CLK_030_i.BLIF vpa_sync_0_un1_n.BLIF state_machine_un42_clk_030_i_n.BLIF vpa_sync_0_un0_n.BLIF DS_030_i.BLIF as_000_int_0_un3_n.BLIF cpu_est_i_1__n.BLIF as_000_int_0_un1_n.BLIF \ + AS_030_000_SYNC_i.BLIF as_000_int_0_un0_n.BLIF cpu_est_i_0__n.BLIF dtack_sync_0_un3_n.BLIF sm_amiga_i_4__n.BLIF dtack_sync_0_un1_n.BLIF sm_amiga_i_6__n.BLIF dtack_sync_0_un0_n.BLIF cpu_est_i_2__n.BLIF \ + lds_000_int_0_un3_n.BLIF UDS_000_INT_0_sqmuxa_1_i.BLIF lds_000_int_0_un1_n.BLIF UDS_000_INT_0_sqmuxa_i.BLIF lds_000_int_0_un0_n.BLIF sm_amiga_i_5__n.BLIF uds_000_int_0_un3_n.BLIF CLK_000_DD_i.BLIF uds_000_int_0_un1_n.BLIF \ + sm_amiga_i_7__n.BLIF uds_000_int_0_un0_n.BLIF a_i_30__n.BLIF bg_000_0_un3_n.BLIF a_i_31__n.BLIF bg_000_0_un1_n.BLIF a_i_28__n.BLIF bg_000_0_un0_n.BLIF a_i_29__n.BLIF \ + as_030_000_sync_0_un3_n.BLIF a_i_26__n.BLIF as_030_000_sync_0_un1_n.BLIF a_i_27__n.BLIF as_030_000_sync_0_un0_n.BLIF a_i_24__n.BLIF fpu_cs_int_0_un3_n.BLIF a_i_25__n.BLIF fpu_cs_int_0_un1_n.BLIF \ + fpu_cs_int_0_un0_n.BLIF ipl_030_0_2__un3_n.BLIF RST_i.BLIF ipl_030_0_2__un1_n.BLIF N_107_i.BLIF ipl_030_0_2__un0_n.BLIF N_106_i.BLIF ipl_030_0_1__un3_n.BLIF FPU_CS_INT_i.BLIF \ + ipl_030_0_1__un1_n.BLIF CPU_SPACE_i.BLIF ipl_030_0_1__un0_n.BLIF BGACK_030_INT_i.BLIF ipl_030_0_0__un3_n.BLIF AS_030_c.BLIF ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF bgack_030_int_0_un3_n.BLIF \ + DS_030_c.BLIF bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF sm_amiga_d_0_0__un3_n.BLIF sm_amiga_d_0_0__un1_n.BLIF size_c_0__n.BLIF sm_amiga_d_0_0__un0_n.BLIF sm_amiga_d_0_1__un3_n.BLIF size_c_1__n.BLIF \ + sm_amiga_d_0_1__un1_n.BLIF sm_amiga_d_0_1__un0_n.BLIF a_c_0__n.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF \ + cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF a_15__n.BLIF a_14__n.BLIF a_13__n.BLIF a_12__n.BLIF a_c_16__n.BLIF a_11__n.BLIF \ + a_c_17__n.BLIF a_10__n.BLIF a_c_18__n.BLIF a_9__n.BLIF a_c_19__n.BLIF a_8__n.BLIF a_c_20__n.BLIF a_7__n.BLIF a_c_21__n.BLIF \ + a_6__n.BLIF a_c_22__n.BLIF a_5__n.BLIF a_c_23__n.BLIF a_4__n.BLIF a_c_24__n.BLIF a_3__n.BLIF a_c_25__n.BLIF a_2__n.BLIF \ + a_c_26__n.BLIF a_1__n.BLIF a_c_27__n.BLIF a_c_28__n.BLIF a_c_29__n.BLIF DSACK_1_.PIN DTACK.PIN .outputs IPL_030_2_ AS_000 UDS_000 LDS_000 BERR BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS AVEC \ - AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_4_.D \ - SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR \ - SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_reg.D cpu_est_3_reg.C \ - SM_AMIGA_7_.D SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR CLK_000_CNT_0_.D CLK_000_CNT_0_.C \ - CLK_000_CNT_1_.D CLK_000_CNT_1_.C CLK_000_CNT_2_.D CLK_000_CNT_2_.C CLK_000_CNT_3_.D CLK_000_CNT_3_.C SM_AMIGA_D_0_.D SM_AMIGA_D_0_.C SM_AMIGA_D_1_.D SM_AMIGA_D_1_.C SM_AMIGA_D_2_.D \ - SM_AMIGA_D_2_.C IPL_030DFFSH_0_reg.D IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP IPL_030DFFSH_1_reg.D IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP inst_AS_030_000_SYNC.D \ - inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_VPA_SYNC.D inst_VPA_SYNC.C inst_VPA_SYNC.AP BG_000DFFSHreg.D BG_000DFFSHreg.C BG_000DFFSHreg.AP inst_AS_000_INTreg.D inst_AS_000_INTreg.C inst_AS_000_INTreg.AP \ - inst_VMA_INTreg.D inst_VMA_INTreg.C inst_VMA_INTreg.AP inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C DSACK_INT_1_.D DSACK_INT_1_.C DSACK_INT_1_.AP \ + AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_6_.D \ + SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR \ + SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR IPL_030DFFSH_1_reg.D IPL_030DFFSH_1_reg.C \ + IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_reg.D \ + cpu_est_3_reg.C SM_AMIGA_7_.D SM_AMIGA_7_.C SM_AMIGA_7_.AP cpu_est_d_0_.D cpu_est_d_0_.C cpu_est_d_1_.D cpu_est_d_1_.C cpu_est_d_2_.D cpu_est_d_2_.C cpu_est_d_3_.D \ + cpu_est_d_3_.C SM_AMIGA_D_0_.D SM_AMIGA_D_0_.C SM_AMIGA_D_1_.D SM_AMIGA_D_1_.C SM_AMIGA_D_2_.D SM_AMIGA_D_2_.C IPL_030DFFSH_0_reg.D IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP inst_AS_000_INTreg.D \ + inst_AS_000_INTreg.C inst_AS_000_INTreg.AP inst_VPA_SYNC.D inst_VPA_SYNC.C inst_VPA_SYNC.AP inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_VMA_INTreg.D inst_VMA_INTreg.C inst_VMA_INTreg.AP \ + BG_000DFFSHreg.D BG_000DFFSHreg.C BG_000DFFSHreg.AP DSACK_INT_1_.D DSACK_INT_1_.C DSACK_INT_1_.AP inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C \ inst_UDS_000_INTreg.D inst_UDS_000_INTreg.C inst_UDS_000_INTreg.AP inst_LDS_000_INTreg.D inst_LDS_000_INTreg.C inst_LDS_000_INTreg.AP inst_DTACK_SYNC.D inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_FPU_CS_INTreg.D inst_FPU_CS_INTreg.C \ - inst_FPU_CS_INTreg.AP inst_DTACK_DMA.D inst_DTACK_DMA.C inst_DTACK_DMA.AP CLK_CNT_0_.D CLK_CNT_0_.C inst_RISING_CLK_AMIGA.D inst_RISING_CLK_AMIGA.C inst_VPA_D.D inst_VPA_D.C inst_CLK_000_D.D \ - inst_CLK_000_D.C RESETDFFreg.D RESETDFFreg.C inst_CLK_000_DD.D inst_CLK_000_DD.C inst_CLK_OUT_INTreg.D inst_CLK_OUT_INTreg.C cpu_est_0_0_.X1 cpu_est_0_0_.X2 G_122.X1 G_122.X2 \ - G_124.X1 G_124.X2 G_123.X1 G_123.X2 G_132.X1 G_132.X2 G_130.X1 G_130.X2 G_128.X1 G_128.X2 CLK_OUT_PRE_0.X1 \ - CLK_OUT_PRE_0.X2 DSACK_1_ DTACK DSACK_0_ a_15__n a_c_22__n a_14__n a_c_23__n a_13__n a_c_24__n a_12__n a_c_25__n a_11__n a_c_26__n \ - a_10__n a_c_27__n gnd_n_n a_9__n a_c_28__n a_8__n a_c_29__n a_7__n a_c_30__n a_6__n a_c_31__n \ - a_5__n CPU_SPACE_c vcc_n_n a_4__n BG_030_c a_3__n a_2__n a_1__n BGACK_000_c CLK_030_c CLK_000_c \ - CLK_OSZI_c un1_clk_000_cnt_3__n state_machine_un14_as_000_int_n ipl_c_0__n clk_exp ipl_c_1__n ipl_c_2__n dsack_c_1__n DTACK_c RST_c RW_c \ - fc_c_0__n fc_c_1__n N_123 N_148_i clk_rising_clk_amiga_1_n N_147_i VMA_INT_1_sqmuxa_0 N_170_i N_171_i DSACK_INT_1_sqmuxa N_161_i \ - N_120 N_164_i N_144_1 N_165_i N_251 N_168_i N_254 N_166_i N_186 N_167_i un1_clk_000_cnt_0__n \ - N_169_i N_184 clk_cpu_est_11_0_1__n un1_clk_000_cnt_1__n N_173_i un1_clk_000_cnt_2__n N_172_i state_machine_un69_clk_000_d_n N_174_i state_machine_un78_clk_000_d_n clk_cpu_est_11_0_3__n \ - N_149 N_121_i N_119 N_126_0 N_135 N_123_0 state_machine_un67_clk_000_d_n N_122_0 state_machine_un80_clk_000_d_n N_142_i N_132 \ - N_143_i N_131 sm_amiga_ns_0_5__n state_machine_un25_clk_000_d_n N_141_i N_150 N_140_i N_151 sm_amiga_ns_0_4__n N_144 N_146 \ - LDS_000_INT_1_sqmuxa_i N_143 un1_UDS_000_INT_0_sqmuxa_2_0 N_145 UDS_000_INT_0_sqmuxa_i state_machine_lds_000_int_8_n un1_UDS_000_INT_0_sqmuxa_i un1_UDS_000_INT_0_sqmuxa_2 N_124_0 state_machine_uds_000_int_8_n N_136_i \ - LDS_000_INT_0_sqmuxa state_machine_un42_clk_030_n RISING_CLK_AMIGA_i un1_bg_030 state_machine_un4_bgack_000_0_n N_133 BG_030_c_i state_machine_as_030_000_sync_3_n state_machine_un1_clk_030_0_n N_125 state_machine_un17_clk_030_0_n \ - N_137 un1_as_030_2_0 N_138 N_137_i DSACK_INT_1_sqmuxa_1 N_138_i un1_as_030_2 state_machine_un17_clk_030_n N_120_i state_machine_un1_clk_030_n N_125_0 \ - state_machine_un4_bgack_000_n state_machine_as_030_000_sync_3_2_n VPA_SYNC_1_sqmuxa N_133_i VPA_SYNC_1_sqmuxa_1 un1_bg_030_0 N_122 a_c_i_0__n AS_000_INT_1_sqmuxa state_machine_uds_000_int_8_0_n N_136 \ - state_machine_lds_000_int_8_0_n N_124 N_151_i N_130 state_machine_un15_clk_000_d_n N_146_i un1_UDS_000_INT_0_sqmuxa N_145_i UDS_000_INT_0_sqmuxa sm_amiga_ns_0_7__n LDS_000_INT_1_sqmuxa \ - N_144_i N_139 N_150_i N_140 N_126 size_c_i_1__n N_141 state_machine_un25_clk_000_d_i_n N_121 state_machine_un80_clk_000_d_i_n N_142 \ - state_machine_un67_clk_000_d_i_n VPA_SYNC_1_sqmuxa_1_0 state_machine_un78_clk_000_d_0_n DTACK_SYNC_1_sqmuxa clk_rising_clk_amiga_1_i_n DTACK_SYNC_1_sqmuxa_1 N_135_i N_149_2 N_104_i clk_un3_clk_000_dd_n N_149_i \ - N_164 N_119_0 N_171 clk_000_cnt_i_1__n N_170 clk_000_cnt_i_0__n clk_cpu_est_11_3__n clk_000_cnt_i_3__n N_174 clk_000_cnt_i_2__n N_172 \ - state_machine_un69_clk_000_d_0_n N_173 state_machine_un69_clk_000_d_0_1_n clk_cpu_est_11_1__n state_machine_un69_clk_000_d_0_2_n N_169 state_machine_un25_clk_000_d_i_1_n N_167 N_116_i_1 N_166 un1_bg_030_0_1 \ - N_168 un1_bg_030_0_2 N_165 state_machine_as_030_000_sync_3_2_1_n VMA_INT_1_sqmuxa un1_UDS_000_INT_0_sqmuxa_i_1 N_147 clk_cpu_est_11_0_1_3__n N_148 clk_cpu_est_11_0_1_1__n RW_i \ - clk_cpu_est_11_0_2_1__n clk_exp_i N_251_1 CLK_000_DD_i N_251_2 CLK_000_D_i N_251_3 AS_000_INT_i N_251_4 cpu_est_i_0__n N_251_5 \ - cpu_est_i_2__n N_251_6 cpu_est_i_3__n N_254_1 cpu_est_i_1__n N_254_2 N_149_2_i DSACK_INT_1_sqmuxa_1_0 VPA_D_i DSACK_INT_1_sqmuxa_2 DTACK_i \ - DSACK_INT_1_sqmuxa_3 VPA_SYNC_i N_149_1 DTACK_SYNC_i N_149_2_0 AS_030_i N_132_1 DTACK_SYNC_1_sqmuxa_i N_131_1 DS_030_i state_machine_un42_clk_030_1_n \ - sm_amiga_i_4__n state_machine_un42_clk_030_2_n sm_amiga_i_6__n state_machine_un42_clk_030_3_n sm_amiga_i_5__n state_machine_un42_clk_030_4_n N_139_i state_machine_un42_clk_030_5_n state_machine_un15_clk_000_d_i_n N_142_1 N_130_i \ - N_130_1 sm_amiga_i_0__n N_130_2 sm_amiga_i_7__n UDS_000_INT_0_sqmuxa_1 VPA_SYNC_1_sqmuxa_i UDS_000_INT_0_sqmuxa_2 dsack_i_1__n DTACK_SYNC_1_sqmuxa_1_0 DSACK_INT_1_sqmuxa_i VPA_SYNC_1_sqmuxa_1_1 \ - a_i_18__n VPA_SYNC_1_sqmuxa_2 a_i_16__n VPA_SYNC_1_sqmuxa_3 a_i_19__n N_171_1 CLK_030_i N_170_1 state_machine_un42_clk_030_i_n N_174_1 AS_030_000_SYNC_i \ - clk_exp_1 N_131_i cpu_est_0_1__un3_n N_132_i cpu_est_0_1__un1_n sm_amiga_i_2__n cpu_est_0_1__un0_n sm_amiga_i_1__n vma_int_0_un3_n sm_amiga_i_3__n vma_int_0_un1_n \ - CLK_000_i vma_int_0_un0_n a_i_30__n cpu_est_0_3__un3_n a_i_31__n cpu_est_0_3__un1_n a_i_28__n cpu_est_0_3__un0_n a_i_29__n cpu_est_0_2__un3_n a_i_26__n \ - cpu_est_0_2__un1_n a_i_27__n cpu_est_0_2__un0_n a_i_24__n dtack_sync_0_un3_n a_i_25__n dtack_sync_0_un1_n dtack_sync_0_un0_n sm_amiga_d_0_0__un3_n RST_i sm_amiga_d_0_0__un1_n \ - sm_amiga_d_0_0__un0_n FPU_CS_INT_i bgack_030_int_0_un3_n CPU_SPACE_i bgack_030_int_0_un1_n BGACK_030_INT_i bgack_030_int_0_un0_n AS_030_c bg_000_0_un3_n bg_000_0_un1_n bg_000_0_un0_n \ - DS_030_c as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n fpu_cs_int_0_un3_n size_c_0__n fpu_cs_int_0_un1_n fpu_cs_int_0_un0_n size_c_1__n dsack_int_0_1__un3_n dsack_int_0_1__un1_n \ - a_c_0__n dsack_int_0_1__un0_n vpa_sync_0_un3_n vpa_sync_0_un1_n vpa_sync_0_un0_n as_000_int_0_un3_n as_000_int_0_un1_n as_000_int_0_un0_n ipl_030_0_2__un3_n ipl_030_0_2__un1_n ipl_030_0_2__un0_n \ - ipl_030_0_1__un3_n ipl_030_0_1__un1_n ipl_030_0_1__un0_n ipl_030_0_0__un3_n ipl_030_0_0__un1_n ipl_030_0_0__un0_n sm_amiga_d_0_2__un3_n a_c_16__n sm_amiga_d_0_2__un1_n sm_amiga_d_0_2__un0_n a_c_17__n \ - sm_amiga_d_0_1__un3_n sm_amiga_d_0_1__un1_n a_c_18__n sm_amiga_d_0_1__un0_n lds_000_int_0_un3_n a_c_19__n lds_000_int_0_un1_n lds_000_int_0_un0_n a_c_20__n uds_000_int_0_un3_n uds_000_int_0_un1_n \ - a_c_21__n uds_000_int_0_un0_n DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE \ - AVEC_EXP.OE CIIN.OE + inst_FPU_CS_INTreg.AP inst_DTACK_DMA.D inst_DTACK_DMA.C inst_DTACK_DMA.AP inst_RISING_CLK_AMIGA.D inst_RISING_CLK_AMIGA.C CLK_CNT_0_.D CLK_CNT_0_.C inst_VPA_D.D inst_VPA_D.C inst_CLK_000_D.D \ + inst_CLK_000_D.C RESETDFFreg.D RESETDFFreg.C inst_CLK_000_DD.D inst_CLK_000_DD.C inst_CLK_OUT_INTreg.D inst_CLK_OUT_INTreg.C G_100.X1 G_100.X2 CLK_OUT_PRE_0.X1 CLK_OUT_PRE_0.X2 \ + G_98.X1 G_98.X2 G_99.X1 G_99.X2 cpu_est_0_0_.X1 cpu_est_0_0_.X2 DSACK_1_ DTACK DSACK_0_ a_c_30__n a_c_31__n CPU_SPACE_c BG_030_c gnd_n_n \ + BGACK_000_c CLK_030_c CLK_000_c CLK_OSZI_c vcc_n_n ipl_c_0__n ipl_c_1__n ipl_c_2__n state_machine_un57_clk_000_d_n dsack_c_1__n DTACK_c \ + state_machine_un13_as_000_int_n RST_c clk_exp RW_c fc_c_0__n fc_c_1__n state_machine_un57_clk_000_d_0_n N_161_i a_c_i_0__n state_machine_uds_000_int_8_0_n state_machine_lds_000_int_8_0_n \ + N_113_i sm_amiga_ns_0_2__n N_118_i N_117_i sm_amiga_ns_0_5__n N_123_i N_119_i N_120_i sm_amiga_ns_0_7__n CLK_OUT_PRE_i N_106 \ + N_102_0 N_107 size_c_i_1__n clk_un3_clk_000_dd_n state_machine_un31_clk_000_d_i_n clk_cpu_est_11_1__n RISING_CLK_AMIGA_i clk_cpu_est_11_3__n state_machine_un4_bgack_000_0_n BG_030_c_i state_machine_un1_clk_030_0_n \ + state_machine_un17_clk_030_0_n N_161 un1_as_030_2_0 N_114 state_machine_as_030_000_sync_3_2_n N_109 N_109_i N_111 un1_bg_030_0 N_112 N_111_i \ + N_122 N_122_i N_115 N_101 N_147_i N_116 clk_cpu_est_11_0_3__n N_124 N_145_i N_139 N_146_i \ + N_137 N_142_i N_140 clk_cpu_est_11_0_1__n N_141 N_140_i N_136 N_139_i N_142 N_141_i N_145 \ + N_138_i N_138 N_137_i N_146 N_136_i N_143 N_143_i N_144 N_144_i UDS_000_INT_0_sqmuxa N_134_i \ + UDS_000_INT_0_sqmuxa_1 N_101_0 N_147 N_115_i N_147_1 N_116_i state_machine_un13_clk_000_d_1_n N_186 N_124_i N_189 state_machine_un42_clk_030_n \ + N_112_i un1_bg_030 sm_amiga_ns_0_0__n state_machine_as_030_000_sync_3_n N_86_i_1 un1_as_030_2 un1_bg_030_0_1 state_machine_un17_clk_030_n un1_bg_030_0_2 state_machine_un1_clk_030_n state_machine_as_030_000_sync_3_2_1_n \ + state_machine_un4_bgack_000_n state_machine_un31_clk_000_d_i_1_n N_108 N_186_1 state_machine_un31_clk_000_d_n N_186_2 state_machine_un13_clk_000_d_n N_186_3 state_machine_un13_clk_000_d_4_n N_186_4 state_machine_un8_clk_000_d_n \ + N_186_5 DTACK_SYNC_1_sqmuxa N_186_6 VPA_SYNC_1_sqmuxa_1_0 N_189_1 VPA_SYNC_1_sqmuxa N_189_2 N_123 clk_cpu_est_11_0_1_1__n N_118 clk_cpu_est_11_0_2_1__n \ + N_110 clk_cpu_est_11_0_1_3__n N_102 N_143_1 N_120 N_144_1 N_119 N_106_1 N_117 N_106_2 N_113 \ + N_107_1 state_machine_lds_000_int_8_n UDS_000_INT_0_sqmuxa_1_1 state_machine_uds_000_int_8_n UDS_000_INT_0_sqmuxa_1_2 DTACK_SYNC_1_sqmuxa_1 UDS_000_INT_0_sqmuxa_1_3 un2_clk_030_1 UDS_000_INT_0_sqmuxa_1_0 VPA_SYNC_1_sqmuxa_1 UDS_000_INT_0_sqmuxa_2 \ + AS_000_INT_1_sqmuxa state_machine_un42_clk_030_1_n VMA_INT_1_sqmuxa state_machine_un42_clk_030_2_n DSACK_INT_1_sqmuxa state_machine_un42_clk_030_3_n RW_i state_machine_un42_clk_030_4_n clk_exp_i state_machine_un42_clk_030_5_n DTACK_SYNC_1_sqmuxa_i \ + state_machine_un13_clk_000_d_1_0_n N_114_i state_machine_un13_clk_000_d_4_1_n VPA_SYNC_1_sqmuxa_i state_machine_un8_clk_000_d_1_n N_110_i state_machine_un8_clk_000_d_2_n N_108_i state_machine_un8_clk_000_d_3_n cpu_est_d_i_3__n state_machine_un8_clk_000_d_4_n \ + cpu_est_d_i_0__n DTACK_SYNC_1_sqmuxa_1_0 CLK_000_D_i VPA_SYNC_1_sqmuxa_1_1 AS_030_i VPA_SYNC_1_sqmuxa_2 AS_000_INT_i VPA_SYNC_1_sqmuxa_3 dsack_i_1__n VPA_SYNC_1_sqmuxa_4 state_machine_un13_clk_000_d_i_n \ + N_108_1 state_machine_un8_clk_000_d_i_n N_118_1 state_machine_un13_clk_000_d_1_i_n N_110_1 sm_amiga_i_1__n clk_exp_1 sm_amiga_i_2__n sm_amiga_d_0_2__un3_n sm_amiga_i_0__n sm_amiga_d_0_2__un1_n \ + sm_amiga_i_3__n sm_amiga_d_0_2__un0_n VPA_D_i dsack_int_0_1__un3_n VMA_INT_i dsack_int_0_1__un1_n DTACK_i dsack_int_0_1__un0_n cpu_est_i_3__n vma_int_0_un3_n a_i_18__n \ + vma_int_0_un1_n a_i_16__n vma_int_0_un0_n a_i_19__n vpa_sync_0_un3_n CLK_030_i vpa_sync_0_un1_n state_machine_un42_clk_030_i_n vpa_sync_0_un0_n DS_030_i as_000_int_0_un3_n \ + cpu_est_i_1__n as_000_int_0_un1_n AS_030_000_SYNC_i as_000_int_0_un0_n cpu_est_i_0__n dtack_sync_0_un3_n sm_amiga_i_4__n dtack_sync_0_un1_n sm_amiga_i_6__n dtack_sync_0_un0_n cpu_est_i_2__n \ + lds_000_int_0_un3_n UDS_000_INT_0_sqmuxa_1_i lds_000_int_0_un1_n UDS_000_INT_0_sqmuxa_i lds_000_int_0_un0_n sm_amiga_i_5__n uds_000_int_0_un3_n CLK_000_DD_i uds_000_int_0_un1_n sm_amiga_i_7__n uds_000_int_0_un0_n \ + a_i_30__n bg_000_0_un3_n a_i_31__n bg_000_0_un1_n a_i_28__n bg_000_0_un0_n a_i_29__n as_030_000_sync_0_un3_n a_i_26__n as_030_000_sync_0_un1_n a_i_27__n \ + as_030_000_sync_0_un0_n a_i_24__n fpu_cs_int_0_un3_n a_i_25__n fpu_cs_int_0_un1_n fpu_cs_int_0_un0_n ipl_030_0_2__un3_n RST_i ipl_030_0_2__un1_n N_107_i ipl_030_0_2__un0_n \ + N_106_i ipl_030_0_1__un3_n FPU_CS_INT_i ipl_030_0_1__un1_n CPU_SPACE_i ipl_030_0_1__un0_n BGACK_030_INT_i ipl_030_0_0__un3_n AS_030_c ipl_030_0_0__un1_n ipl_030_0_0__un0_n \ + bgack_030_int_0_un3_n DS_030_c bgack_030_int_0_un1_n bgack_030_int_0_un0_n sm_amiga_d_0_0__un3_n sm_amiga_d_0_0__un1_n size_c_0__n sm_amiga_d_0_0__un0_n sm_amiga_d_0_1__un3_n size_c_1__n sm_amiga_d_0_1__un1_n \ + sm_amiga_d_0_1__un0_n a_c_0__n cpu_est_0_1__un3_n cpu_est_0_1__un1_n cpu_est_0_1__un0_n cpu_est_0_2__un3_n cpu_est_0_2__un1_n cpu_est_0_2__un0_n cpu_est_0_3__un3_n cpu_est_0_3__un1_n cpu_est_0_3__un0_n \ + a_15__n a_14__n a_13__n a_12__n a_c_16__n a_11__n a_c_17__n a_10__n a_c_18__n a_9__n a_c_19__n \ + a_8__n a_c_20__n a_7__n a_c_21__n a_6__n a_c_22__n a_5__n a_c_23__n a_4__n a_c_24__n a_3__n \ + a_c_25__n a_2__n a_c_26__n a_1__n a_c_27__n a_c_28__n a_c_29__n DSACK_1_.OE DTACK.OE \ + AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE .names DSACK_INT_1_.BLIF DSACK_1_ 1 1 .names DSACK_1_.PIN dsack_c_1__n @@ -181,1027 +169,949 @@ 1 1 .names FPU_CS_INT_i.BLIF AVEC_EXP.OE 1 1 -.names N_254.BLIF CIIN +.names N_189.BLIF CIIN 1 1 -.names N_251.BLIF CIIN.OE +.names N_186.BLIF CIIN.OE 1 1 -.names clk_cpu_est_11_0_3__n.BLIF clk_cpu_est_11_3__n +.names N_123.BLIF N_123_i 0 1 -.names clk_un3_clk_000_dd_n.BLIF cpu_est_0_0_.X1 -1 1 -.names N_121_i.BLIF N_121 +.names N_119.BLIF N_119_i 0 1 -.names N_126_0.BLIF N_126 +.names N_120.BLIF N_120_i 0 1 -.names cpu_est_0_.BLIF cpu_est_0_0_.X2 -1 1 -.names N_123_0.BLIF N_123 -0 1 -.names N_122_0.BLIF N_122 -0 1 -.names N_142.BLIF N_142_i -0 1 -.names N_130.BLIF G_122.X1 -1 1 -.names N_143.BLIF N_143_i -0 1 -.names sm_amiga_ns_0_5__n.BLIF SM_AMIGA_2_.D -0 1 -.names SM_AMIGA_D_0_.BLIF G_122.X2 -1 1 -.names N_141.BLIF N_141_i -0 1 -.names N_140.BLIF N_140_i -0 1 -.names sm_amiga_ns_0_4__n.BLIF SM_AMIGA_3_.D -0 1 -.names N_132.BLIF G_124.X1 -1 1 -.names LDS_000_INT_1_sqmuxa.BLIF LDS_000_INT_1_sqmuxa_i -0 1 -.names N_148.BLIF N_148_i -0 1 -.names SM_AMIGA_D_2_.BLIF G_124.X2 -1 1 -.names N_147.BLIF N_147_i -0 1 -.names VMA_INT_1_sqmuxa_0.BLIF VMA_INT_1_sqmuxa -0 1 -.names N_170.BLIF N_170_i -0 1 -.names N_131.BLIF G_123.X1 -1 1 -.names N_171.BLIF N_171_i -0 1 -.names N_164_i.BLIF N_164 -0 1 -.names SM_AMIGA_D_1_.BLIF G_123.X2 -1 1 -.names N_165_i.BLIF N_165 -0 1 -.names N_168.BLIF N_168_i -0 1 -.names N_166.BLIF N_166_i -0 1 -.names N_186.BLIF G_132.X1 -1 1 -.names N_167.BLIF N_167_i -0 1 -.names N_169.BLIF N_169_i -0 1 -.names un1_clk_000_cnt_0__n.BLIF G_132.X2 -1 1 -.names clk_cpu_est_11_0_1__n.BLIF clk_cpu_est_11_1__n -0 1 -.names clk_un3_clk_000_dd_n.BLIF cpu_est_0_1__un3_n -0 1 -.names clk_cpu_est_11_1__n.BLIF clk_un3_clk_000_dd_n.BLIF cpu_est_0_1__un1_n -11 1 -.names N_184.BLIF G_130.X1 -1 1 -.names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n -11 1 -.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D -1- 1 --1 1 -.names un1_clk_000_cnt_1__n.BLIF G_130.X2 -1 1 -.names VMA_INT_1_sqmuxa.BLIF vma_int_0_un3_n -0 1 -.names inst_VMA_INTreg.BLIF VMA_INT_1_sqmuxa.BLIF vma_int_0_un1_n -11 1 -.names inst_CLK_000_D.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n -11 1 -.names un1_clk_000_cnt_2__n.BLIF G_128.X1 -1 1 -.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D -1- 1 --1 1 -.names RW_c.BLIF RW_i -0 1 -.names un1_clk_000_cnt_3__n.BLIF G_128.X2 -1 1 -.names clk_exp.BLIF clk_exp_i -0 1 -.names N_164_i.BLIF cpu_est_0_.BLIF N_168 -11 1 -.names cpu_est_2_.BLIF cpu_est_i_2__n -0 1 -.names CLK_CNT_0_.BLIF CLK_OUT_PRE_0.X1 -1 1 -.names cpu_est_3_reg.BLIF cpu_est_i_3__n -0 1 -.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_167 -11 1 -.names inst_CLK_OUT_PRE.BLIF CLK_OUT_PRE_0.X2 -1 1 -.names cpu_est_0_.BLIF cpu_est_i_0__n -0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C -1 1 -.names N_164.BLIF cpu_est_i_0__n.BLIF N_166 -11 1 -.names N_147_i.BLIF N_148_i.BLIF VMA_INT_1_sqmuxa_0 -11 1 -.names RST_i.BLIF SM_AMIGA_4_.AR -1 1 -.names cpu_est_0_0_.BLIF cpu_est_0_.D -1 1 -.names inst_AS_000_INTreg.BLIF AS_000_INT_i -0 1 -.names G_128.BLIF CLK_000_CNT_1_.D -1 1 -.names AS_000_INT_i.BLIF inst_CLK_000_D.BLIF N_148 -11 1 -.names G_130.BLIF CLK_000_CNT_2_.D -1 1 -.names inst_CLK_000_D.BLIF CLK_000_D_i -0 1 -.names G_132.BLIF CLK_000_CNT_3_.D -1 1 -.names CLK_000_D_i.BLIF inst_VPA_SYNC.BLIF N_147 -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C -1 1 -.names CLK_OUT_PRE_0.BLIF inst_CLK_OUT_PRE.D -1 1 -.names inst_CLK_000_DD.BLIF CLK_000_DD_i -0 1 -.names inst_CLK_000_D.BLIF CLK_000_DD_i.BLIF clk_un3_clk_000_dd_n -11 1 -.names RST_i.BLIF SM_AMIGA_3_.AR -1 1 -.names clk_un3_clk_000_dd_n.BLIF cpu_est_0_3__un3_n -0 1 -.names clk_cpu_est_11_3__n.BLIF clk_un3_clk_000_dd_n.BLIF cpu_est_0_3__un1_n -11 1 -.names cpu_est_3_reg.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n -11 1 -.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_reg.D -1- 1 --1 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C -1 1 -.names clk_un3_clk_000_dd_n.BLIF cpu_est_0_2__un3_n -0 1 -.names N_161_i.BLIF clk_un3_clk_000_dd_n.BLIF cpu_est_0_2__un1_n -11 1 -.names RST_i.BLIF SM_AMIGA_2_.AR -1 1 -.names cpu_est_2_.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n -11 1 -.names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D -1- 1 --1 1 -.names inst_DTACK_SYNC.BLIF DTACK_SYNC_i -0 1 -.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF N_121_i -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C -1 1 -.names inst_VPA_SYNC.BLIF VPA_SYNC_i -0 1 -.names DTACK_c.BLIF DTACK_i -0 1 -.names RST_i.BLIF SM_AMIGA_1_.AR -1 1 -.names inst_VPA_D.BLIF VPA_D_i -0 1 -.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_149_2 -11 1 -.names N_149_2.BLIF N_149_2_i -0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C -1 1 -.names cpu_est_1_.BLIF cpu_est_i_1__n -0 1 -.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_165_i -11 1 -.names RST_i.BLIF SM_AMIGA_0_.AR -1 1 -.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF N_164_i -11 1 -.names N_170_i.BLIF N_171_i.BLIF N_161_i -11 1 -.names N_165_i.BLIF cpu_est_i_2__n.BLIF N_173 -11 1 -.names N_165.BLIF cpu_est_3_reg.BLIF N_172 -11 1 -.names CLK_OSZI_c.BLIF cpu_est_0_.C -1 1 -.names N_149_2.BLIF cpu_est_3_reg.BLIF N_169 -11 1 -.names inst_CLK_000_D.BLIF N_139_i.BLIF SM_AMIGA_5_.D -11 1 -.names N_140_i.BLIF N_141_i.BLIF sm_amiga_ns_0_4__n -11 1 -.names N_142_i.BLIF N_143_i.BLIF sm_amiga_ns_0_5__n -11 1 -.names CLK_OSZI_c.BLIF cpu_est_1_.C -1 1 -.names inst_CLK_000_D.BLIF N_120_i.BLIF N_122_0 -11 1 -.names inst_AS_000_INTreg.BLIF inst_CLK_000_D.BLIF N_123_0 -11 1 -.names sm_amiga_i_3__n.BLIF sm_amiga_i_4__n.BLIF N_126_0 -11 1 -.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n -0 1 -.names CLK_OSZI_c.BLIF cpu_est_2_.C -1 1 -.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n -0 1 -.names DS_030_c.BLIF DS_030_i -0 1 -.names inst_CLK_000_D.BLIF SM_AMIGA_3_.BLIF VPA_SYNC_1_sqmuxa_1_0 -11 1 -.names CLK_OSZI_c.BLIF cpu_est_3_reg.C -1 1 -.names DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un3_n -0 1 -.names inst_DTACK_SYNC.BLIF DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un1_n -11 1 -.names DTACK_SYNC_1_sqmuxa_i.BLIF dtack_sync_0_un3_n.BLIF dtack_sync_0_un0_n -11 1 -.names dtack_sync_0_un1_n.BLIF dtack_sync_0_un0_n.BLIF inst_DTACK_SYNC.D -1- 1 --1 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_7_.C -1 1 -.names AS_030.BLIF AS_030_c -1 1 -.names AS_030_c.BLIF AS_030_i -0 1 -.names DTACK_SYNC_1_sqmuxa.BLIF DTACK_SYNC_1_sqmuxa_i -0 1 -.names RST_i.BLIF SM_AMIGA_7_.AP -1 1 -.names DS_030.BLIF DS_030_c -1 1 -.names AS_030_i.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF DTACK_SYNC_1_sqmuxa_1 -11 1 -.names inst_CLK_000_D.BLIF N_136_i.BLIF SM_AMIGA_7_.D -11 1 -.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n -0 1 -.names SIZE_0_.BLIF size_c_0__n -1 1 -.names inst_AS_000_INTreg.BLIF SM_AMIGA_0_.BLIF N_124_0 -11 1 .names CLK_OSZI_c.BLIF SM_AMIGA_6_.C 1 1 -.names SIZE_1_.BLIF size_c_1__n -1 1 -.names N_130.BLIF N_130_i +.names sm_amiga_ns_0_7__n.BLIF SM_AMIGA_0_.D 0 1 -.names A_0_.BLIF a_c_0__n -1 1 -.names RST_c.BLIF sm_amiga_d_0_0__un3_n +.names inst_CLK_OUT_PRE.BLIF CLK_OUT_PRE_i 0 1 .names RST_i.BLIF SM_AMIGA_6_.AR 1 1 -.names A_16_.BLIF a_c_16__n -1 1 -.names N_130_i.BLIF RST_c.BLIF sm_amiga_d_0_0__un1_n -11 1 -.names A_17_.BLIF a_c_17__n -1 1 -.names SM_AMIGA_D_0_.BLIF sm_amiga_d_0_0__un3_n.BLIF sm_amiga_d_0_0__un0_n -11 1 -.names A_18_.BLIF a_c_18__n -1 1 -.names sm_amiga_d_0_0__un1_n.BLIF sm_amiga_d_0_0__un0_n.BLIF SM_AMIGA_D_0_.D -1- 1 --1 1 -.names A_19_.BLIF a_c_19__n -1 1 -.names DS_030_i.BLIF RW_c.BLIF state_machine_un15_clk_000_d_n +.names N_102_0.BLIF N_102 +0 1 +.names state_machine_un57_clk_000_d_0_n.BLIF state_machine_un57_clk_000_d_n +0 1 +.names RST_c.BLIF sm_amiga_d_0_2__un3_n +0 1 +.names N_108_i.BLIF RST_c.BLIF sm_amiga_d_0_2__un1_n 11 1 .names CLK_OSZI_c.BLIF SM_AMIGA_5_.C 1 1 -.names A_20_.BLIF a_c_20__n -1 1 -.names N_139.BLIF N_139_i -0 1 -.names A_21_.BLIF a_c_21__n -1 1 -.names state_machine_un15_clk_000_d_n.BLIF state_machine_un15_clk_000_d_i_n -0 1 +.names SM_AMIGA_D_2_.BLIF sm_amiga_d_0_2__un3_n.BLIF sm_amiga_d_0_2__un0_n +11 1 +.names sm_amiga_d_0_2__un1_n.BLIF sm_amiga_d_0_2__un0_n.BLIF SM_AMIGA_D_2_.D +1- 1 +-1 1 .names RST_i.BLIF SM_AMIGA_5_.AR 1 1 -.names A_22_.BLIF a_c_22__n -1 1 -.names N_139_i.BLIF state_machine_un15_clk_000_d_i_n.BLIF LDS_000_INT_1_sqmuxa -11 1 -.names A_23_.BLIF a_c_23__n -1 1 -.names LDS_000_INT_1_sqmuxa_i.BLIF un1_UDS_000_INT_0_sqmuxa.BLIF un1_UDS_000_INT_0_sqmuxa_2_0 -11 1 -.names A_24_.BLIF a_c_24__n -1 1 -.names N_120.BLIF sm_amiga_i_5__n.BLIF N_139 -11 1 -.names A_25_.BLIF a_c_25__n -1 1 -.names inst_CLK_000_D.BLIF N_126.BLIF N_140 -11 1 -.names CLK_OSZI_c.BLIF CLK_000_CNT_0_.C -1 1 -.names A_26_.BLIF a_c_26__n -1 1 -.names N_121_i.BLIF SM_AMIGA_3_.BLIF N_141 -11 1 -.names A_27_.BLIF a_c_27__n -1 1 -.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +.names N_110.BLIF N_110_i 0 1 -.names A_28_.BLIF a_c_28__n -1 1 -.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_151 -11 1 -.names A_29_.BLIF a_c_29__n -1 1 -.names state_machine_un4_bgack_000_n.BLIF bgack_030_int_0_un3_n +.names DSACK_INT_1_sqmuxa.BLIF dsack_int_0_1__un3_n 0 1 -.names CLK_OSZI_c.BLIF CLK_000_CNT_1_.C -1 1 -.names A_30_.BLIF a_c_30__n -1 1 -.names BGACK_000_c.BLIF state_machine_un4_bgack_000_n.BLIF bgack_030_int_0_un1_n +.names DSACK_INT_1_.BLIF DSACK_INT_1_sqmuxa.BLIF dsack_int_0_1__un1_n 11 1 -.names A_31_.BLIF a_c_31__n -1 1 -.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un0_n +.names N_110_i.BLIF dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un0_n 11 1 -.names CPU_SPACE.BLIF CPU_SPACE_c -1 1 -.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF inst_BGACK_030_INTreg.D -1- 1 --1 1 -.names state_machine_un1_clk_030_n.BLIF bg_000_0_un3_n -0 1 -.names CLK_OSZI_c.BLIF CLK_000_CNT_2_.C -1 1 -.names BG_030.BLIF BG_030_c -1 1 -.names un1_bg_030.BLIF state_machine_un1_clk_030_n.BLIF bg_000_0_un1_n -11 1 -.names BG_000DFFSHreg.BLIF BG_000 -1 1 -.names BG_000DFFSHreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n -11 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030 -1 1 -.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF BG_000DFFSHreg.D -1- 1 --1 1 -.names BGACK_000.BLIF BGACK_000_c -1 1 -.names state_machine_un17_clk_030_n.BLIF as_030_000_sync_0_un3_n -0 1 -.names CLK_OSZI_c.BLIF CLK_000_CNT_3_.C -1 1 -.names CLK_030.BLIF CLK_030_c -1 1 -.names state_machine_as_030_000_sync_3_n.BLIF state_machine_un17_clk_030_n.BLIF as_030_000_sync_0_un1_n -11 1 -.names CLK_000.BLIF CLK_000_c -1 1 -.names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n -11 1 -.names CLK_OSZI.BLIF CLK_OSZI_c -1 1 -.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF inst_AS_030_000_SYNC.D -1- 1 --1 1 -.names inst_CLK_OUT_INTreg.BLIF CLK_DIV_OUT -1 1 -.names state_machine_un17_clk_030_n.BLIF fpu_cs_int_0_un3_n -0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_D_0_.C -1 1 -.names clk_exp_i.BLIF CLK_EXP -1 1 -.names un1_as_030_2.BLIF state_machine_un17_clk_030_n.BLIF fpu_cs_int_0_un1_n -11 1 -.names inst_FPU_CS_INTreg.BLIF FPU_CS -1 1 -.names inst_FPU_CS_INTreg.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un0_n -11 1 -.names IPL_030DFFSH_0_reg.BLIF IPL_030_0_ -1 1 -.names fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF inst_FPU_CS_INTreg.D -1- 1 --1 1 -.names IPL_030DFFSH_1_reg.BLIF IPL_030_1_ -1 1 -.names DSACK_INT_1_sqmuxa.BLIF DSACK_INT_1_sqmuxa_i -0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_D_1_.C -1 1 -.names IPL_030DFFSH_2_reg.BLIF IPL_030_2_ -1 1 -.names DSACK_INT_1_sqmuxa_1.BLIF dsack_int_0_1__un3_n -0 1 -.names IPL_0_.BLIF ipl_c_0__n -1 1 -.names DSACK_INT_1_.BLIF DSACK_INT_1_sqmuxa_1.BLIF dsack_int_0_1__un1_n -11 1 -.names IPL_1_.BLIF ipl_c_1__n -1 1 -.names DSACK_INT_1_sqmuxa_i.BLIF dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un0_n -11 1 -.names IPL_2_.BLIF ipl_c_2__n +.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C 1 1 .names dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF DSACK_INT_1_.D 1- 1 -1 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_D_2_.C +.names VMA_INT_1_sqmuxa.BLIF vma_int_0_un3_n +0 1 +.names RST_i.BLIF SM_AMIGA_4_.AR +1 1 +.names inst_VMA_INTreg.BLIF VMA_INT_1_sqmuxa.BLIF vma_int_0_un1_n +11 1 +.names state_machine_un13_clk_000_d_4_n.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n +11 1 +.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D +1- 1 +-1 1 +.names VPA_SYNC_1_sqmuxa.BLIF VPA_SYNC_1_sqmuxa_i +0 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C 1 1 .names VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un3_n 0 1 .names inst_VPA_SYNC.BLIF VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un1_n 11 1 +.names RST_i.BLIF SM_AMIGA_3_.AR +1 1 .names VPA_SYNC_1_sqmuxa_i.BLIF vpa_sync_0_un3_n.BLIF vpa_sync_0_un0_n 11 1 -.names vcc_n_n.BLIF AVEC -1 1 .names vpa_sync_0_un1_n.BLIF vpa_sync_0_un0_n.BLIF inst_VPA_SYNC.D 1- 1 -1 1 -.names CLK_OSZI_c.BLIF IPL_030DFFSH_0_reg.C -1 1 +.names N_114.BLIF N_114_i +0 1 .names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n 0 1 -.names cpu_est_3_reg.BLIF E +.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C 1 1 .names inst_AS_000_INTreg.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n 11 1 -.names RST_i.BLIF IPL_030DFFSH_0_reg.AP -1 1 -.names VPA.BLIF inst_VPA_D.D -1 1 -.names N_122.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n +.names N_114_i.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n 11 1 -.names inst_VMA_INTreg.BLIF VMA +.names RST_i.BLIF SM_AMIGA_2_.AR 1 1 .names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF inst_AS_000_INTreg.D 1- 1 -1 1 -.names RST.BLIF RST_c -1 1 -.names AS_030_i.BLIF N_122.BLIF AS_000_INT_1_sqmuxa -11 1 -.names RESETDFFreg.BLIF RESET -1 1 -.names dsack_c_1__n.BLIF dsack_i_1__n +.names DTACK_SYNC_1_sqmuxa.BLIF DTACK_SYNC_1_sqmuxa_i 0 1 -.names CLK_OSZI_c.BLIF IPL_030DFFSH_1_reg.C -1 1 -.names RW.BLIF RW_c -1 1 -.names AS_000_INT_i.BLIF dsack_i_1__n.BLIF state_machine_un14_as_000_int_n -11 1 -.names FC_0_.BLIF fc_c_0__n -1 1 -.names VPA_SYNC_1_sqmuxa.BLIF VPA_SYNC_1_sqmuxa_i +.names DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un3_n 0 1 -.names RST_i.BLIF IPL_030DFFSH_1_reg.AP +.names inst_DTACK_SYNC.BLIF DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un1_n +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C 1 1 -.names FC_1_.BLIF fc_c_1__n -1 1 -.names AS_030_i.BLIF VPA_SYNC_1_sqmuxa_i.BLIF VPA_SYNC_1_sqmuxa_1 +.names DTACK_SYNC_1_sqmuxa_i.BLIF dtack_sync_0_un3_n.BLIF dtack_sync_0_un0_n 11 1 -.names gnd_n_n.BLIF AMIGA_BUS_ENABLE -1 1 -.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n -0 1 -.names RW_i.BLIF AMIGA_BUS_DATA_DIR -1 1 -.names N_124.BLIF sm_amiga_i_7__n.BLIF N_136 -11 1 -.names vcc_n_n.BLIF AMIGA_BUS_ENABLE_LOW -1 1 -.names N_125.BLIF sm_amiga_i_6__n.BLIF N_137 -11 1 -.names CLK_OSZI_c.BLIF IPL_030DFFSH_2_reg.C -1 1 -.names sm_amiga_i_6__n.BLIF sm_amiga_i_7__n.BLIF N_133 -11 1 -.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_174_1 -11 1 -.names AS_030_i.BLIF DSACK_INT_1_sqmuxa_i.BLIF DSACK_INT_1_sqmuxa_1 -11 1 -.names RST_i.BLIF IPL_030DFFSH_2_reg.AP -1 1 -.names N_174_1.BLIF cpu_est_i_2__n.BLIF N_174 -11 1 -.names state_machine_un42_clk_030_n.BLIF state_machine_un42_clk_030_i_n -0 1 -.names G_124.BLIF G_122.BLIF clk_exp_1 -11 1 -.names AS_030_i.BLIF state_machine_un42_clk_030_n.BLIF un1_as_030_2_0 -11 1 -.names clk_exp_1.BLIF G_123.BLIF clk_exp -11 1 -.names AS_030_i.BLIF CLK_030_i.BLIF state_machine_un17_clk_030_0_n -11 1 -.names sm_amiga_i_4__n.BLIF sm_amiga_i_6__n.BLIF N_130_2 -11 1 -.names CLK_030_c.BLIF CLK_030_i -0 1 -.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C -1 1 -.names N_130_1.BLIF N_130_2.BLIF N_130 -11 1 -.names BG_030_c_i.BLIF CLK_030_c.BLIF state_machine_un1_clk_030_0_n -11 1 -.names inst_CLK_000_D.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1 -11 1 -.names BGACK_000_c.BLIF RISING_CLK_AMIGA_i.BLIF state_machine_un4_bgack_000_0_n -11 1 -.names RST_i.BLIF inst_AS_030_000_SYNC.AP -1 1 -.names RW_i.BLIF SM_AMIGA_4_.BLIF UDS_000_INT_0_sqmuxa_2 -11 1 -.names a_c_19__n.BLIF a_i_19__n -0 1 -.names UDS_000_INT_0_sqmuxa_1.BLIF UDS_000_INT_0_sqmuxa_2.BLIF UDS_000_INT_0_sqmuxa -11 1 -.names a_c_18__n.BLIF a_i_18__n -0 1 -.names DTACK_i.BLIF inst_VPA_D.BLIF DTACK_SYNC_1_sqmuxa_1_0 -11 1 -.names a_c_16__n.BLIF a_i_16__n -0 1 -.names DTACK_SYNC_1_sqmuxa_1_0.BLIF VPA_SYNC_1_sqmuxa_1_0.BLIF DTACK_SYNC_1_sqmuxa -11 1 -.names inst_RISING_CLK_AMIGA.BLIF ipl_030_0_2__un3_n -0 1 -.names CLK_OSZI_c.BLIF inst_VPA_SYNC.C -1 1 -.names N_164_i.BLIF VPA_D_i.BLIF VPA_SYNC_1_sqmuxa_1_1 -11 1 -.names ipl_c_2__n.BLIF inst_RISING_CLK_AMIGA.BLIF ipl_030_0_2__un1_n -11 1 -.names VPA_SYNC_1_sqmuxa_1_0.BLIF cpu_est_0_.BLIF VPA_SYNC_1_sqmuxa_2 -11 1 -.names IPL_030DFFSH_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n -11 1 -.names RST_i.BLIF inst_VPA_SYNC.AP -1 1 -.names VPA_SYNC_1_sqmuxa_1_1.BLIF VPA_SYNC_1_sqmuxa_2.BLIF VPA_SYNC_1_sqmuxa_3 -11 1 -.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF IPL_030DFFSH_2_reg.D +.names dtack_sync_0_un1_n.BLIF dtack_sync_0_un0_n.BLIF inst_DTACK_SYNC.D 1- 1 -1 1 -.names VPA_SYNC_1_sqmuxa_3.BLIF cpu_est_2_.BLIF VPA_SYNC_1_sqmuxa -11 1 -.names inst_RISING_CLK_AMIGA.BLIF ipl_030_0_1__un3_n +.names RST_i.BLIF SM_AMIGA_1_.AR +1 1 +.names un2_clk_030_1.BLIF lds_000_int_0_un3_n 0 1 -.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_171_1 -11 1 -.names ipl_c_1__n.BLIF inst_RISING_CLK_AMIGA.BLIF ipl_030_0_1__un1_n -11 1 -.names N_171_1.BLIF cpu_est_i_2__n.BLIF N_171 -11 1 -.names IPL_030DFFSH_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n -11 1 -.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C -1 1 -.names N_149_2_i.BLIF cpu_est_0_.BLIF N_170_1 -11 1 -.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF IPL_030DFFSH_1_reg.D -1- 1 --1 1 -.names N_170_1.BLIF cpu_est_i_3__n.BLIF N_170 -11 1 -.names inst_RISING_CLK_AMIGA.BLIF ipl_030_0_0__un3_n -0 1 -.names RST_i.BLIF BG_000DFFSHreg.AP -1 1 -.names cpu_est_0_.BLIF cpu_est_3_reg.BLIF N_149_2_0 -11 1 -.names ipl_c_0__n.BLIF inst_RISING_CLK_AMIGA.BLIF ipl_030_0_0__un1_n -11 1 -.names N_149_1.BLIF N_149_2_0.BLIF N_149 -11 1 -.names IPL_030DFFSH_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n -11 1 -.names N_150.BLIF sm_amiga_i_0__n.BLIF N_132_1 -11 1 -.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF IPL_030DFFSH_0_reg.D -1- 1 --1 1 -.names N_132_1.BLIF sm_amiga_i_3__n.BLIF N_132 -11 1 -.names CLK_000_D_i.BLIF SM_AMIGA_2_.BLIF N_143 -11 1 -.names CLK_OSZI_c.BLIF inst_AS_000_INTreg.C -1 1 -.names N_151.BLIF sm_amiga_i_0__n.BLIF N_131_1 -11 1 -.names state_machine_un25_clk_000_d_n.BLIF un1_UDS_000_INT_0_sqmuxa_2_0.BLIF state_machine_lds_000_int_8_0_n -11 1 -.names N_131_1.BLIF sm_amiga_i_1__n.BLIF N_131 -11 1 -.names a_c_i_0__n.BLIF un1_UDS_000_INT_0_sqmuxa_2_0.BLIF state_machine_uds_000_int_8_0_n -11 1 -.names RST_i.BLIF inst_AS_000_INTreg.AP -1 1 -.names a_c_17__n.BLIF a_i_16__n.BLIF state_machine_un42_clk_030_1_n -11 1 -.names AS_030_i.BLIF un1_UDS_000_INT_0_sqmuxa_2.BLIF LDS_000_INT_0_sqmuxa -11 1 -.names a_i_18__n.BLIF a_i_19__n.BLIF state_machine_un42_clk_030_2_n -11 1 -.names N_132.BLIF N_132_i -0 1 -.names fc_c_1__n.BLIF BGACK_000_c.BLIF state_machine_un42_clk_030_3_n -11 1 -.names RST_c.BLIF sm_amiga_d_0_2__un3_n -0 1 -.names state_machine_un42_clk_030_1_n.BLIF state_machine_un42_clk_030_2_n.BLIF state_machine_un42_clk_030_4_n -11 1 -.names N_132_i.BLIF RST_c.BLIF sm_amiga_d_0_2__un1_n -11 1 -.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C -1 1 -.names state_machine_un42_clk_030_3_n.BLIF fc_c_0__n.BLIF state_machine_un42_clk_030_5_n -11 1 -.names SM_AMIGA_D_2_.BLIF sm_amiga_d_0_2__un3_n.BLIF sm_amiga_d_0_2__un0_n -11 1 -.names state_machine_un42_clk_030_4_n.BLIF state_machine_un42_clk_030_5_n.BLIF state_machine_un42_clk_030_n -11 1 -.names sm_amiga_d_0_2__un1_n.BLIF sm_amiga_d_0_2__un0_n.BLIF SM_AMIGA_D_2_.D -1- 1 --1 1 -.names RST_i.BLIF inst_VMA_INTreg.AP -1 1 -.names CLK_000_D_i.BLIF N_121.BLIF N_142_1 -11 1 -.names N_131.BLIF N_131_i -0 1 -.names N_142_1.BLIF SM_AMIGA_3_.BLIF N_142 -11 1 -.names RST_c.BLIF sm_amiga_d_0_1__un3_n -0 1 -.names sm_amiga_i_0__n.BLIF sm_amiga_i_2__n.BLIF N_130_1 -11 1 -.names N_131_i.BLIF RST_c.BLIF sm_amiga_d_0_1__un1_n -11 1 -.names a_i_24__n.BLIF a_i_25__n.BLIF N_251_1 -11 1 -.names SM_AMIGA_D_1_.BLIF sm_amiga_d_0_1__un3_n.BLIF sm_amiga_d_0_1__un0_n -11 1 -.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C -1 1 -.names a_i_26__n.BLIF a_i_27__n.BLIF N_251_2 -11 1 -.names sm_amiga_d_0_1__un1_n.BLIF sm_amiga_d_0_1__un0_n.BLIF SM_AMIGA_D_1_.D -1- 1 --1 1 -.names a_i_28__n.BLIF a_i_29__n.BLIF N_251_3 -11 1 -.names LDS_000_INT_0_sqmuxa.BLIF lds_000_int_0_un3_n -0 1 -.names RST_i.BLIF inst_BGACK_030_INTreg.AP -1 1 -.names a_i_30__n.BLIF a_i_31__n.BLIF N_251_4 -11 1 -.names inst_LDS_000_INTreg.BLIF LDS_000_INT_0_sqmuxa.BLIF lds_000_int_0_un1_n -11 1 -.names N_251_1.BLIF N_251_2.BLIF N_251_5 +.names inst_LDS_000_INTreg.BLIF un2_clk_030_1.BLIF lds_000_int_0_un1_n 11 1 .names state_machine_lds_000_int_8_n.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n 11 1 -.names N_251_3.BLIF N_251_4.BLIF N_251_6 -11 1 .names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF inst_LDS_000_INTreg.D 1- 1 -1 1 -.names N_251_5.BLIF N_251_6.BLIF N_251 -11 1 -.names LDS_000_INT_0_sqmuxa.BLIF uds_000_int_0_un3_n -0 1 -.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE.C +.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C 1 1 -.names a_c_20__n.BLIF a_c_21__n.BLIF N_254_1 -11 1 -.names inst_UDS_000_INTreg.BLIF LDS_000_INT_0_sqmuxa.BLIF uds_000_int_0_un1_n -11 1 -.names a_c_22__n.BLIF a_c_23__n.BLIF N_254_2 +.names un2_clk_030_1.BLIF uds_000_int_0_un3_n +0 1 +.names inst_UDS_000_INTreg.BLIF un2_clk_030_1.BLIF uds_000_int_0_un1_n 11 1 +.names RST_i.BLIF SM_AMIGA_0_.AR +1 1 .names state_machine_uds_000_int_8_n.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n 11 1 -.names N_254_1.BLIF N_254_2.BLIF N_254 -11 1 .names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INTreg.D 1- 1 -1 1 -.names AS_030_000_SYNC_i.BLIF CLK_000_D_i.BLIF DSACK_INT_1_sqmuxa_1_0 +.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF state_machine_un57_clk_000_d_0_n 11 1 -.names CLK_000_D_i.BLIF SM_AMIGA_7_.BLIF N_125_0 -11 1 -.names CLK_OSZI_c.BLIF DSACK_INT_1_.C -1 1 -.names inst_CLK_OUT_PRE.BLIF SM_AMIGA_0_.BLIF DSACK_INT_1_sqmuxa_2 -11 1 -.names AS_030_000_SYNC_i.BLIF SM_AMIGA_6_.BLIF N_120_i -11 1 -.names DSACK_INT_1_sqmuxa_1_0.BLIF DSACK_INT_1_sqmuxa_2.BLIF DSACK_INT_1_sqmuxa_3 -11 1 -.names N_137_i.BLIF N_138_i.BLIF SM_AMIGA_6_.D -11 1 -.names RST_i.BLIF DSACK_INT_1_.AP -1 1 -.names DSACK_INT_1_sqmuxa_3.BLIF state_machine_un78_clk_000_d_n.BLIF DSACK_INT_1_sqmuxa -11 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +.names RW_c.BLIF RW_i 0 1 -.names N_149_2.BLIF VPA_SYNC_i.BLIF N_149_1 -11 1 -.names AS_030_000_SYNC_i.BLIF inst_CLK_000_D.BLIF N_138 -11 1 -.names state_machine_un25_clk_000_d_i_1_n.BLIF size_c_i_1__n.BLIF state_machine_un25_clk_000_d_i_n -11 1 -.names DTACK_SYNC_i.BLIF state_machine_un69_clk_000_d_n.BLIF state_machine_un67_clk_000_d_n -11 1 -.names N_143_i.BLIF N_144_i.BLIF N_116_i_1 -11 1 -.names VPA_SYNC_i.BLIF state_machine_un69_clk_000_d_n.BLIF state_machine_un80_clk_000_d_n -11 1 -.names CLK_OSZI_c.BLIF inst_UDS_000_INTreg.C +.names CLK_OSZI_c.BLIF IPL_030DFFSH_1_reg.C 1 1 -.names N_116_i_1.BLIF N_150_i.BLIF SM_AMIGA_1_.D -11 1 -.names CLK_000_CNT_2_.BLIF N_184.BLIF N_186 -11 1 -.names BG_030_c_i.BLIF CPU_SPACE_i.BLIF un1_bg_030_0_1 -11 1 -.names CLK_000_CNT_1_.BLIF un1_clk_000_cnt_3__n.BLIF N_184 -11 1 -.names RST_i.BLIF inst_UDS_000_INTreg.AP -1 1 -.names AS_030_c.BLIF N_133_i.BLIF un1_bg_030_0_2 -11 1 -.names un1_bg_030_0_1.BLIF un1_bg_030_0_2.BLIF un1_bg_030_0 -11 1 -.names AS_030_i.BLIF CPU_SPACE_i.BLIF state_machine_as_030_000_sync_3_2_1_n -11 1 -.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n +.names clk_exp.BLIF clk_exp_i 0 1 -.names state_machine_as_030_000_sync_3_2_1_n.BLIF state_machine_un42_clk_030_i_n.BLIF state_machine_as_030_000_sync_3_2_n +.names AS_030_i.BLIF VPA_SYNC_1_sqmuxa_i.BLIF VPA_SYNC_1_sqmuxa_1 11 1 -.names N_144_1.BLIF sm_amiga_i_2__n.BLIF N_144 -11 1 -.names CLK_OSZI_c.BLIF inst_LDS_000_INTreg.C +.names RST_i.BLIF IPL_030DFFSH_1_reg.AP 1 1 -.names N_122.BLIF sm_amiga_i_5__n.BLIF un1_UDS_000_INT_0_sqmuxa_i_1 +.names AS_030_i.BLIF N_114_i.BLIF AS_000_INT_1_sqmuxa 11 1 -.names N_144_1.BLIF SM_AMIGA_1_.BLIF N_146 -11 1 -.names un1_UDS_000_INT_0_sqmuxa_i_1.BLIF UDS_000_INT_0_sqmuxa_i.BLIF un1_UDS_000_INT_0_sqmuxa_i -11 1 -.names N_145_i.BLIF N_146_i.BLIF sm_amiga_ns_0_7__n -11 1 -.names RST_i.BLIF inst_LDS_000_INTreg.AP -1 1 -.names N_174_i.BLIF N_172_i.BLIF clk_cpu_est_11_0_1_3__n -11 1 -.names CLK_000_D_i.BLIF N_151_i.BLIF SM_AMIGA_4_.D -11 1 -.names clk_cpu_est_11_0_1_3__n.BLIF N_173_i.BLIF clk_cpu_est_11_0_3__n -11 1 -.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n +.names state_machine_un13_clk_000_d_n.BLIF state_machine_un13_clk_000_d_i_n 0 1 -.names N_169_i.BLIF N_167_i.BLIF clk_cpu_est_11_0_1_1__n +.names state_machine_un8_clk_000_d_n.BLIF state_machine_un8_clk_000_d_i_n +0 1 +.names state_machine_un8_clk_000_d_i_n.BLIF state_machine_un13_clk_000_d_i_n.BLIF VMA_INT_1_sqmuxa +11 1 +.names CLK_OSZI_c.BLIF IPL_030DFFSH_2_reg.C +1 1 +.names inst_AS_000_INTreg.BLIF AS_000_INT_i +0 1 +.names dsack_c_1__n.BLIF dsack_i_1__n +0 1 +.names RST_i.BLIF IPL_030DFFSH_2_reg.AP +1 1 +.names AS_000_INT_i.BLIF dsack_i_1__n.BLIF state_machine_un13_as_000_int_n +11 1 +.names AS_030_c.BLIF AS_030_i +0 1 +.names AS_030_i.BLIF N_110_i.BLIF DSACK_INT_1_sqmuxa +11 1 +.names inst_CLK_000_D.BLIF CLK_000_D_i +0 1 +.names CLK_OSZI_c.BLIF cpu_est_0_.C +1 1 +.names CLK_000_D_i.BLIF CLK_000_c.BLIF inst_RISING_CLK_AMIGA.D +11 1 +.names cpu_est_d_3_.BLIF cpu_est_d_i_3__n +0 1 +.names cpu_est_d_0_.BLIF cpu_est_d_i_0__n +0 1 +.names N_108.BLIF N_108_i +0 1 +.names CLK_OSZI_c.BLIF cpu_est_1_.C +1 1 +.names N_119_i.BLIF N_123_i.BLIF SM_AMIGA_1_.D +11 1 +.names N_117_i.BLIF N_118_i.BLIF sm_amiga_ns_0_5__n +11 1 +.names N_113_i.BLIF N_114_i.BLIF sm_amiga_ns_0_2__n 11 1 .names SM_AMIGA_1_.BLIF sm_amiga_i_1__n 0 1 -.names N_166_i.BLIF N_168_i.BLIF clk_cpu_est_11_0_2_1__n -11 1 -.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_150 -11 1 -.names CLK_OSZI_c.BLIF inst_DTACK_SYNC.C +.names CLK_OSZI_c.BLIF cpu_est_2_.C 1 1 -.names clk_cpu_est_11_0_1_1__n.BLIF clk_cpu_est_11_0_2_1__n.BLIF clk_cpu_est_11_0_1__n -11 1 -.names N_123.BLIF SM_AMIGA_0_.BLIF N_145 -11 1 -.names state_machine_un67_clk_000_d_n.BLIF state_machine_un67_clk_000_d_i_n +.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n 0 1 -.names RST_i.BLIF inst_DTACK_SYNC.AP +.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_123 +11 1 +.names state_machine_un13_clk_000_d_1_n.BLIF state_machine_un13_clk_000_d_1_i_n +0 1 +.names SM_AMIGA_0_.BLIF state_machine_un13_clk_000_d_1_i_n.BLIF N_120 +11 1 +.names CLK_OSZI_c.BLIF cpu_est_3_reg.C 1 1 -.names state_machine_un78_clk_000_d_0_n.BLIF state_machine_un78_clk_000_d_n -0 1 -.names clk_rising_clk_amiga_1_n.BLIF clk_rising_clk_amiga_1_i_n -0 1 -.names N_135.BLIF N_135_i -0 1 -.names CLK_000_CNT_3_.BLIF N_104_i.BLIF un1_clk_000_cnt_0__n +.names CLK_000_D_i.BLIF N_102.BLIF N_119 11 1 -.names N_149.BLIF N_149_i -0 1 -.names CLK_000_CNT_2_.BLIF N_104_i.BLIF un1_clk_000_cnt_1__n +.names CLK_000_D_i.BLIF SM_AMIGA_2_.BLIF N_117 11 1 -.names CLK_OSZI_c.BLIF inst_FPU_CS_INTreg.C +.names inst_CLK_000_D.BLIF SM_AMIGA_5_.BLIF N_113 +11 1 +.names N_161_i.BLIF state_machine_un31_clk_000_d_n.BLIF state_machine_lds_000_int_8_0_n +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_7_.C 1 1 -.names N_119_0.BLIF N_119 -0 1 -.names CLK_000_CNT_1_.BLIF N_104_i.BLIF un1_clk_000_cnt_2__n +.names a_c_i_0__n.BLIF N_161_i.BLIF state_machine_uds_000_int_8_0_n 11 1 -.names CLK_000_CNT_1_.BLIF clk_000_cnt_i_1__n -0 1 -.names CLK_000_CNT_0_.BLIF N_104_i.BLIF un1_clk_000_cnt_3__n +.names AS_030_i.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF DTACK_SYNC_1_sqmuxa_1 11 1 -.names RST_i.BLIF inst_FPU_CS_INTreg.AP +.names RST_i.BLIF SM_AMIGA_7_.AP 1 1 -.names CLK_000_CNT_0_.BLIF clk_000_cnt_i_0__n -0 1 -.names CLK_000_CNT_3_.BLIF clk_000_cnt_i_3__n -0 1 -.names CLK_000_i.BLIF N_119.BLIF N_144_1 +.names AS_030_i.BLIF N_161.BLIF un2_clk_030_1 11 1 -.names CLK_000_CNT_2_.BLIF clk_000_cnt_i_2__n +.names state_machine_un1_clk_030_n.BLIF bg_000_0_un3_n 0 1 -.names inst_DTACK_SYNC.BLIF N_149_i.BLIF N_119_0 +.names un1_bg_030.BLIF state_machine_un1_clk_030_n.BLIF bg_000_0_un1_n 11 1 -.names state_machine_un69_clk_000_d_0_n.BLIF state_machine_un69_clk_000_d_n -0 1 -.names N_135_i.BLIF clk_rising_clk_amiga_1_i_n.BLIF N_104_i -11 1 -.names CLK_OSZI_c.BLIF inst_DTACK_DMA.C +.names cpu_est_0_.BLIF cpu_est_d_0_.D 1 1 -.names clk_000_cnt_i_0__n.BLIF clk_000_cnt_i_1__n.BLIF state_machine_un69_clk_000_d_0_1_n +.names BG_000DFFSHreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n 11 1 -.names CLK_000_c.BLIF CLK_000_i -0 1 -.names clk_000_cnt_i_2__n.BLIF clk_000_cnt_i_3__n.BLIF state_machine_un69_clk_000_d_0_2_n -11 1 -.names inst_CLK_000_D.BLIF CLK_000_i.BLIF N_135 -11 1 -.names RST_i.BLIF inst_DTACK_DMA.AP +.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF BG_000DFFSHreg.D +1- 1 +-1 1 +.names CLK_OSZI_c.BLIF cpu_est_d_0_.C 1 1 -.names state_machine_un69_clk_000_d_0_1_n.BLIF state_machine_un69_clk_000_d_0_2_n.BLIF state_machine_un69_clk_000_d_0_n +.names state_machine_un17_clk_030_n.BLIF as_030_000_sync_0_un3_n +0 1 +.names state_machine_as_030_000_sync_3_n.BLIF state_machine_un17_clk_030_n.BLIF as_030_000_sync_0_un1_n 11 1 -.names CLK_000_D_i.BLIF CLK_000_c.BLIF clk_rising_clk_amiga_1_n +.names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n 11 1 -.names size_c_0__n.BLIF a_c_i_0__n.BLIF state_machine_un25_clk_000_d_i_1_n +.names cpu_est_1_.BLIF cpu_est_d_1_.D +1 1 +.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF inst_AS_030_000_SYNC.D +1- 1 +-1 1 +.names state_machine_un17_clk_030_n.BLIF fpu_cs_int_0_un3_n +0 1 +.names CLK_OSZI_c.BLIF cpu_est_d_1_.C +1 1 +.names AS_030.BLIF AS_030_c +1 1 +.names un1_as_030_2.BLIF state_machine_un17_clk_030_n.BLIF fpu_cs_int_0_un1_n 11 1 -.names state_machine_un67_clk_000_d_i_n.BLIF state_machine_un80_clk_000_d_i_n.BLIF state_machine_un78_clk_000_d_0_n +.names inst_FPU_CS_INTreg.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un0_n 11 1 -.names state_machine_as_030_000_sync_3_2_n.BLIF state_machine_as_030_000_sync_3_n -0 1 -.names a_c_24__n.BLIF a_i_24__n -0 1 -.names N_133.BLIF N_133_i -0 1 -.names a_c_25__n.BLIF a_i_25__n -0 1 -.names CLK_OSZI_c.BLIF CLK_CNT_0_.C +.names DS_030.BLIF DS_030_c 1 1 -.names un1_bg_030_0.BLIF un1_bg_030 -0 1 -.names a_c_26__n.BLIF a_i_26__n -0 1 -.names a_c_0__n.BLIF a_c_i_0__n -0 1 -.names a_c_27__n.BLIF a_i_27__n -0 1 -.names state_machine_uds_000_int_8_0_n.BLIF state_machine_uds_000_int_8_n -0 1 -.names a_c_28__n.BLIF a_i_28__n -0 1 -.names clk_rising_clk_amiga_1_n.BLIF inst_RISING_CLK_AMIGA.D +.names fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF inst_FPU_CS_INTreg.D +1- 1 +-1 1 +.names cpu_est_2_.BLIF cpu_est_d_2_.D 1 1 -.names state_machine_lds_000_int_8_0_n.BLIF state_machine_lds_000_int_8_n -0 1 -.names a_c_29__n.BLIF a_i_29__n -0 1 -.names N_151.BLIF N_151_i -0 1 -.names a_c_30__n.BLIF a_i_30__n -0 1 -.names CLK_OSZI_c.BLIF inst_RISING_CLK_AMIGA.C +.names CLK_OSZI_c.BLIF cpu_est_d_2_.C 1 1 -.names N_146.BLIF N_146_i -0 1 -.names a_c_31__n.BLIF a_i_31__n -0 1 -.names N_145.BLIF N_145_i -0 1 -.names state_machine_un14_as_000_int_n.BLIF inst_DTACK_DMA.D -0 1 -.names sm_amiga_ns_0_7__n.BLIF SM_AMIGA_0_.D -0 1 -.names RST_c.BLIF RST_i -0 1 -.names N_144.BLIF N_144_i -0 1 -.names CLK_CNT_0_.BLIF CLK_CNT_0_.D -0 1 -.names CLK_OSZI_c.BLIF inst_VPA_D.C +.names SIZE_0_.BLIF size_c_0__n 1 1 -.names N_150.BLIF N_150_i -0 1 -.names un1_clk_000_cnt_3__n.BLIF CLK_000_CNT_0_.D -0 1 -.names size_c_1__n.BLIF size_c_i_1__n -0 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i -0 1 -.names state_machine_un25_clk_000_d_i_n.BLIF state_machine_un25_clk_000_d_n -0 1 -.names CPU_SPACE_c.BLIF CPU_SPACE_i -0 1 -.names CLK_000_c.BLIF inst_CLK_000_D.D +.names inst_AS_000_INTreg.BLIF inst_CLK_000_D.BLIF state_machine_un13_clk_000_d_1_n +11 1 +.names SIZE_1_.BLIF size_c_1__n 1 1 -.names state_machine_un80_clk_000_d_n.BLIF state_machine_un80_clk_000_d_i_n +.names cpu_est_3_reg.BLIF cpu_est_i_3__n 0 1 -.names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i +.names A_0_.BLIF a_c_0__n +1 1 +.names DTACK_c.BLIF DTACK_i 0 1 -.names un1_UDS_000_INT_0_sqmuxa_2_0.BLIF un1_UDS_000_INT_0_sqmuxa_2 +.names cpu_est_3_reg.BLIF cpu_est_d_3_.D +1 1 +.names A_16_.BLIF a_c_16__n +1 1 +.names inst_CLK_000_D.BLIF SM_AMIGA_3_.BLIF VPA_SYNC_1_sqmuxa_1_0 +11 1 +.names A_17_.BLIF a_c_17__n +1 1 +.names inst_VPA_D.BLIF VPA_D_i 0 1 -.names gnd_n_n -.names CLK_OSZI_c.BLIF inst_CLK_000_D.C +.names CLK_OSZI_c.BLIF cpu_est_d_3_.C +1 1 +.names A_18_.BLIF a_c_18__n +1 1 +.names inst_VMA_INTreg.BLIF VMA_INT_i +0 1 +.names A_19_.BLIF a_c_19__n +1 1 +.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n +0 1 +.names A_20_.BLIF a_c_20__n +1 1 +.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n +0 1 +.names A_21_.BLIF a_c_21__n +1 1 +.names CLK_OUT_PRE_i.BLIF SM_AMIGA_1_.BLIF N_102_0 +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_D_0_.C +1 1 +.names A_22_.BLIF a_c_22__n +1 1 +.names N_110_i.BLIF N_120_i.BLIF sm_amiga_ns_0_7__n +11 1 +.names A_23_.BLIF a_c_23__n +1 1 +.names A_24_.BLIF a_c_24__n +1 1 +.names A_25_.BLIF a_c_25__n +1 1 +.names state_machine_un42_clk_030_n.BLIF state_machine_un42_clk_030_i_n +0 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_D_1_.C +1 1 +.names A_26_.BLIF a_c_26__n +1 1 +.names AS_030_i.BLIF state_machine_un42_clk_030_n.BLIF un1_as_030_2_0 +11 1 +.names A_27_.BLIF a_c_27__n +1 1 +.names AS_030_i.BLIF CLK_030_i.BLIF state_machine_un17_clk_030_0_n +11 1 +.names A_28_.BLIF a_c_28__n +1 1 +.names CLK_030_c.BLIF CLK_030_i +0 1 +.names A_29_.BLIF a_c_29__n +1 1 +.names BG_030_c_i.BLIF CLK_030_c.BLIF state_machine_un1_clk_030_0_n +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_D_2_.C +1 1 +.names A_30_.BLIF a_c_30__n +1 1 +.names BGACK_000_c.BLIF RISING_CLK_AMIGA_i.BLIF state_machine_un4_bgack_000_0_n +11 1 +.names A_31_.BLIF a_c_31__n +1 1 +.names a_c_19__n.BLIF a_i_19__n +0 1 +.names CPU_SPACE.BLIF CPU_SPACE_c +1 1 +.names a_c_18__n.BLIF a_i_18__n +0 1 +.names a_c_16__n.BLIF a_i_16__n +0 1 +.names CLK_OSZI_c.BLIF IPL_030DFFSH_0_reg.C +1 1 +.names BG_030.BLIF BG_030_c +1 1 +.names inst_RISING_CLK_AMIGA.BLIF ipl_030_0_2__un3_n +0 1 +.names BG_000DFFSHreg.BLIF BG_000 +1 1 +.names ipl_c_2__n.BLIF inst_RISING_CLK_AMIGA.BLIF ipl_030_0_2__un1_n +11 1 +.names RST_i.BLIF IPL_030DFFSH_0_reg.AP +1 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030 +1 1 +.names IPL_030DFFSH_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n +11 1 +.names BGACK_000.BLIF BGACK_000_c +1 1 +.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF IPL_030DFFSH_2_reg.D +1- 1 +-1 1 +.names CLK_030.BLIF CLK_030_c +1 1 +.names inst_RISING_CLK_AMIGA.BLIF ipl_030_0_1__un3_n +0 1 +.names CLK_000.BLIF CLK_000_c +1 1 +.names ipl_c_1__n.BLIF inst_RISING_CLK_AMIGA.BLIF ipl_030_0_1__un1_n +11 1 +.names CLK_OSZI_c.BLIF inst_AS_000_INTreg.C +1 1 +.names CLK_OSZI.BLIF CLK_OSZI_c +1 1 +.names IPL_030DFFSH_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n +11 1 +.names inst_CLK_OUT_INTreg.BLIF CLK_DIV_OUT +1 1 +.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF IPL_030DFFSH_1_reg.D +1- 1 +-1 1 +.names RST_i.BLIF inst_AS_000_INTreg.AP +1 1 +.names clk_exp_i.BLIF CLK_EXP +1 1 +.names inst_RISING_CLK_AMIGA.BLIF ipl_030_0_0__un3_n +0 1 +.names inst_FPU_CS_INTreg.BLIF FPU_CS +1 1 +.names ipl_c_0__n.BLIF inst_RISING_CLK_AMIGA.BLIF ipl_030_0_0__un1_n +11 1 +.names IPL_030DFFSH_0_reg.BLIF IPL_030_0_ +1 1 +.names IPL_030DFFSH_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n +11 1 +.names IPL_030DFFSH_1_reg.BLIF IPL_030_1_ +1 1 +.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF IPL_030DFFSH_0_reg.D +1- 1 +-1 1 +.names CLK_OSZI_c.BLIF inst_VPA_SYNC.C +1 1 +.names IPL_030DFFSH_2_reg.BLIF IPL_030_2_ +1 1 +.names state_machine_un4_bgack_000_n.BLIF bgack_030_int_0_un3_n +0 1 +.names IPL_0_.BLIF ipl_c_0__n +1 1 +.names BGACK_000_c.BLIF state_machine_un4_bgack_000_n.BLIF bgack_030_int_0_un1_n +11 1 +.names RST_i.BLIF inst_VPA_SYNC.AP +1 1 +.names IPL_1_.BLIF ipl_c_1__n +1 1 +.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un0_n +11 1 +.names IPL_2_.BLIF ipl_c_2__n +1 1 +.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF inst_BGACK_030_INTreg.D +1- 1 +-1 1 +.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF N_137_i +11 1 +.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_138_i +11 1 +.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C +1 1 +.names UDS_000_INT_0_sqmuxa_1.BLIF UDS_000_INT_0_sqmuxa_1_i +0 1 +.names vcc_n_n.BLIF AVEC 1 1 .names UDS_000_INT_0_sqmuxa.BLIF UDS_000_INT_0_sqmuxa_i 0 1 +.names RST_i.BLIF inst_AS_030_000_SYNC.AP +1 1 +.names UDS_000_INT_0_sqmuxa_1_i.BLIF UDS_000_INT_0_sqmuxa_i.BLIF N_161 +11 1 +.names cpu_est_3_reg.BLIF E +1 1 +.names cpu_est_2_.BLIF cpu_est_i_2__n +0 1 +.names VPA.BLIF inst_VPA_D.D +1 1 +.names N_147_1.BLIF cpu_est_i_2__n.BLIF N_147 +11 1 +.names inst_VMA_INTreg.BLIF VMA +1 1 +.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n +0 1 +.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C +1 1 +.names RST.BLIF RST_c +1 1 +.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n +0 1 +.names RESETDFFreg.BLIF RESET +1 1 +.names cpu_est_0_.BLIF cpu_est_i_0__n +0 1 +.names RST_i.BLIF inst_VMA_INTreg.AP +1 1 +.names RW.BLIF RW_c +1 1 +.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_147_1 +11 1 +.names FC_0_.BLIF fc_c_0__n +1 1 +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +0 1 +.names FC_1_.BLIF fc_c_1__n +1 1 +.names cpu_est_1_.BLIF cpu_est_i_1__n +0 1 +.names gnd_n_n.BLIF AMIGA_BUS_ENABLE +1 1 +.names DS_030_c.BLIF DS_030_i +0 1 +.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C +1 1 +.names RW_i.BLIF AMIGA_BUS_DATA_DIR +1 1 +.names vcc_n_n.BLIF AMIGA_BUS_ENABLE_LOW +1 1 +.names AS_030_000_SYNC_i.BLIF clk_un3_clk_000_dd_n.BLIF N_122 +11 1 +.names RST_i.BLIF BG_000DFFSHreg.AP +1 1 +.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +0 1 +.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF VPA_SYNC_1_sqmuxa_1_1 +11 1 +.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_124 +11 1 +.names N_147_1.BLIF VMA_INT_i.BLIF VPA_SYNC_1_sqmuxa_2 +11 1 +.names N_111_i.BLIF N_112_i.BLIF sm_amiga_ns_0_0__n +11 1 +.names VPA_D_i.BLIF VPA_SYNC_1_sqmuxa_1_0.BLIF VPA_SYNC_1_sqmuxa_3 +11 1 +.names CLK_000_D_i.BLIF N_124_i.BLIF SM_AMIGA_4_.D +11 1 +.names CLK_OSZI_c.BLIF DSACK_INT_1_.C +1 1 +.names VPA_SYNC_1_sqmuxa_1_1.BLIF VPA_SYNC_1_sqmuxa_2.BLIF VPA_SYNC_1_sqmuxa_4 +11 1 +.names N_115_i.BLIF N_116_i.BLIF SM_AMIGA_3_.D +11 1 +.names VPA_SYNC_1_sqmuxa_4.BLIF VPA_SYNC_1_sqmuxa_3.BLIF VPA_SYNC_1_sqmuxa +11 1 +.names SM_AMIGA_3_.BLIF state_machine_un57_clk_000_d_0_n.BLIF N_101_0 +11 1 +.names RST_i.BLIF DSACK_INT_1_.AP +1 1 +.names N_123.BLIF sm_amiga_i_0__n.BLIF N_108_1 +11 1 +.names N_137.BLIF cpu_est_i_0__n.BLIF N_139 +11 1 +.names N_108_1.BLIF sm_amiga_i_3__n.BLIF N_108 +11 1 +.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_140 +11 1 +.names CLK_000_D_i.BLIF SM_AMIGA_3_.BLIF N_118_1 +11 1 +.names N_137_i.BLIF cpu_est_0_.BLIF N_141 +11 1 +.names N_118_1.BLIF state_machine_un57_clk_000_d_n.BLIF N_118 +11 1 +.names N_136_i.BLIF cpu_est_3_reg.BLIF N_142 +11 1 +.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C +1 1 +.names CLK_000_D_i.BLIF inst_CLK_OUT_PRE.BLIF N_110_1 +11 1 +.names N_138.BLIF cpu_est_3_reg.BLIF N_145 +11 1 +.names N_110_1.BLIF SM_AMIGA_1_.BLIF N_110 +11 1 +.names N_138_i.BLIF cpu_est_i_2__n.BLIF N_146 +11 1 +.names RST_i.BLIF inst_BGACK_030_INTreg.AP +1 1 +.names G_100.BLIF G_98.BLIF clk_exp_1 +11 1 +.names N_143_i.BLIF N_144_i.BLIF N_134_i +11 1 +.names clk_exp_1.BLIF G_99.BLIF clk_exp +11 1 +.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_136_i +11 1 +.names fc_c_1__n.BLIF BGACK_000_c.BLIF state_machine_un42_clk_030_3_n +11 1 +.names a_c_26__n.BLIF a_i_26__n +0 1 +.names state_machine_un42_clk_030_1_n.BLIF state_machine_un42_clk_030_2_n.BLIF state_machine_un42_clk_030_4_n +11 1 +.names a_c_27__n.BLIF a_i_27__n +0 1 +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE.C +1 1 +.names state_machine_un42_clk_030_3_n.BLIF fc_c_0__n.BLIF state_machine_un42_clk_030_5_n +11 1 +.names a_c_28__n.BLIF a_i_28__n +0 1 +.names state_machine_un42_clk_030_4_n.BLIF state_machine_un42_clk_030_5_n.BLIF state_machine_un42_clk_030_n +11 1 +.names a_c_29__n.BLIF a_i_29__n +0 1 +.names cpu_est_d_i_0__n.BLIF cpu_est_d_i_3__n.BLIF state_machine_un13_clk_000_d_1_0_n +11 1 +.names a_c_30__n.BLIF a_i_30__n +0 1 +.names state_machine_un13_clk_000_d_1_0_n.BLIF state_machine_un13_clk_000_d_4_n.BLIF state_machine_un13_clk_000_d_n +11 1 +.names a_c_31__n.BLIF a_i_31__n +0 1 +.names CLK_OSZI_c.BLIF inst_UDS_000_INTreg.C +1 1 +.names state_machine_un13_clk_000_d_1_n.BLIF cpu_est_d_1_.BLIF state_machine_un13_clk_000_d_4_1_n +11 1 +.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n +0 1 +.names state_machine_un13_clk_000_d_4_1_n.BLIF cpu_est_d_2_.BLIF state_machine_un13_clk_000_d_4_n +11 1 +.names sm_amiga_i_6__n.BLIF sm_amiga_i_7__n.BLIF N_109 +11 1 +.names RST_i.BLIF inst_UDS_000_INTreg.AP +1 1 +.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF state_machine_un8_clk_000_d_1_n +11 1 +.names inst_CLK_000_D.BLIF SM_AMIGA_7_.BLIF N_111 +11 1 +.names CLK_000_D_i.BLIF VPA_D_i.BLIF state_machine_un8_clk_000_d_2_n +11 1 +.names SM_AMIGA_0_.BLIF state_machine_un13_clk_000_d_1_n.BLIF N_112 +11 1 +.names cpu_est_0_.BLIF cpu_est_2_.BLIF state_machine_un8_clk_000_d_3_n +11 1 +.names N_122.BLIF SM_AMIGA_6_.BLIF N_114 +11 1 +.names state_machine_un8_clk_000_d_1_n.BLIF state_machine_un8_clk_000_d_2_n.BLIF state_machine_un8_clk_000_d_4_n +11 1 +.names CLK_000_D_i.BLIF N_101.BLIF N_115 +11 1 +.names CLK_OSZI_c.BLIF inst_LDS_000_INTreg.C +1 1 +.names state_machine_un8_clk_000_d_4_n.BLIF state_machine_un8_clk_000_d_3_n.BLIF state_machine_un8_clk_000_d_n +11 1 +.names sm_amiga_i_3__n.BLIF sm_amiga_i_4__n.BLIF N_116 +11 1 +.names DTACK_i.BLIF inst_VPA_D.BLIF DTACK_SYNC_1_sqmuxa_1_0 +11 1 +.names inst_CLK_000_DD.BLIF CLK_000_DD_i +0 1 +.names RST_i.BLIF inst_LDS_000_INTreg.AP +1 1 +.names DTACK_SYNC_1_sqmuxa_1_0.BLIF VPA_SYNC_1_sqmuxa_1_0.BLIF DTACK_SYNC_1_sqmuxa +11 1 +.names inst_CLK_000_D.BLIF CLK_000_DD_i.BLIF clk_un3_clk_000_dd_n +11 1 +.names N_144_1.BLIF cpu_est_i_2__n.BLIF N_144 +11 1 +.names state_machine_un13_as_000_int_n.BLIF inst_DTACK_DMA.D +0 1 +.names sm_amiga_i_0__n.BLIF sm_amiga_i_2__n.BLIF N_106_1 +11 1 +.names RST_c.BLIF RST_i +0 1 +.names sm_amiga_i_4__n.BLIF sm_amiga_i_6__n.BLIF N_106_2 +11 1 +.names CLK_CNT_0_.BLIF CLK_CNT_0_.D +0 1 +.names CLK_OSZI_c.BLIF inst_DTACK_SYNC.C +1 1 +.names N_106_1.BLIF N_106_2.BLIF N_106 +11 1 +.names a_c_24__n.BLIF a_i_24__n +0 1 +.names N_124.BLIF sm_amiga_i_0__n.BLIF N_107_1 +11 1 +.names a_c_25__n.BLIF a_i_25__n +0 1 +.names RST_i.BLIF inst_DTACK_SYNC.AP +1 1 +.names N_107_1.BLIF sm_amiga_i_1__n.BLIF N_107 +11 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i +0 1 +.names AS_030_000_SYNC_i.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_1 +11 1 +.names CPU_SPACE_c.BLIF CPU_SPACE_i +0 1 +.names RW_c.BLIF SM_AMIGA_6_.BLIF UDS_000_INT_0_sqmuxa_1_2 +11 1 +.names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i +0 1 +.names UDS_000_INT_0_sqmuxa_1_1.BLIF UDS_000_INT_0_sqmuxa_1_2.BLIF UDS_000_INT_0_sqmuxa_1_3 +11 1 +.names N_106.BLIF N_106_i +0 1 +.names CLK_OSZI_c.BLIF inst_FPU_CS_INTreg.C +1 1 +.names UDS_000_INT_0_sqmuxa_1_3.BLIF clk_un3_clk_000_dd_n.BLIF UDS_000_INT_0_sqmuxa_1 +11 1 +.names RST_c.BLIF sm_amiga_d_0_0__un3_n +0 1 +.names inst_CLK_000_D.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_0 +11 1 +.names N_106_i.BLIF RST_c.BLIF sm_amiga_d_0_0__un1_n +11 1 +.names RST_i.BLIF inst_FPU_CS_INTreg.AP +1 1 +.names RW_i.BLIF SM_AMIGA_4_.BLIF UDS_000_INT_0_sqmuxa_2 +11 1 +.names SM_AMIGA_D_0_.BLIF sm_amiga_d_0_0__un3_n.BLIF sm_amiga_d_0_0__un0_n +11 1 +.names UDS_000_INT_0_sqmuxa_1_0.BLIF UDS_000_INT_0_sqmuxa_2.BLIF UDS_000_INT_0_sqmuxa +11 1 +.names sm_amiga_d_0_0__un1_n.BLIF sm_amiga_d_0_0__un0_n.BLIF SM_AMIGA_D_0_.D +1- 1 +-1 1 +.names a_c_17__n.BLIF a_i_16__n.BLIF state_machine_un42_clk_030_1_n +11 1 +.names N_107.BLIF N_107_i +0 1 +.names a_i_18__n.BLIF a_i_19__n.BLIF state_machine_un42_clk_030_2_n +11 1 +.names RST_c.BLIF sm_amiga_d_0_1__un3_n +0 1 +.names CLK_OSZI_c.BLIF inst_DTACK_DMA.C +1 1 +.names a_i_30__n.BLIF a_i_31__n.BLIF N_186_4 +11 1 +.names N_107_i.BLIF RST_c.BLIF sm_amiga_d_0_1__un1_n +11 1 +.names N_186_1.BLIF N_186_2.BLIF N_186_5 +11 1 +.names SM_AMIGA_D_1_.BLIF sm_amiga_d_0_1__un3_n.BLIF sm_amiga_d_0_1__un0_n +11 1 +.names RST_i.BLIF inst_DTACK_DMA.AP +1 1 +.names N_186_3.BLIF N_186_4.BLIF N_186_6 +11 1 +.names sm_amiga_d_0_1__un1_n.BLIF sm_amiga_d_0_1__un0_n.BLIF SM_AMIGA_D_1_.D +1- 1 +-1 1 +.names N_186_5.BLIF N_186_6.BLIF N_186 +11 1 +.names clk_un3_clk_000_dd_n.BLIF cpu_est_0_1__un3_n +0 1 +.names a_c_20__n.BLIF a_c_21__n.BLIF N_189_1 +11 1 +.names clk_cpu_est_11_1__n.BLIF clk_un3_clk_000_dd_n.BLIF cpu_est_0_1__un1_n +11 1 +.names a_c_22__n.BLIF a_c_23__n.BLIF N_189_2 +11 1 +.names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n +11 1 +.names CLK_OSZI_c.BLIF inst_RISING_CLK_AMIGA.C +1 1 +.names N_189_1.BLIF N_189_2.BLIF N_189 +11 1 +.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D +1- 1 +-1 1 +.names N_139_i.BLIF N_140_i.BLIF clk_cpu_est_11_0_1_1__n +11 1 +.names clk_un3_clk_000_dd_n.BLIF cpu_est_0_2__un3_n +0 1 +.names N_141_i.BLIF N_142_i.BLIF clk_cpu_est_11_0_2_1__n +11 1 +.names N_134_i.BLIF clk_un3_clk_000_dd_n.BLIF cpu_est_0_2__un1_n +11 1 +.names clk_cpu_est_11_0_1_1__n.BLIF clk_cpu_est_11_0_2_1__n.BLIF clk_cpu_est_11_0_1__n +11 1 +.names cpu_est_2_.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n +11 1 +.names CLK_OSZI_c.BLIF CLK_CNT_0_.C +1 1 +.names N_147_i.BLIF N_145_i.BLIF clk_cpu_est_11_0_1_3__n +11 1 +.names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D +1- 1 +-1 1 +.names clk_cpu_est_11_0_1_3__n.BLIF N_146_i.BLIF clk_cpu_est_11_0_3__n +11 1 +.names clk_un3_clk_000_dd_n.BLIF cpu_est_0_3__un3_n +0 1 +.names N_136.BLIF cpu_est_0_.BLIF N_143_1 +11 1 +.names clk_cpu_est_11_3__n.BLIF clk_un3_clk_000_dd_n.BLIF cpu_est_0_3__un1_n +11 1 +.names N_143_1.BLIF cpu_est_i_3__n.BLIF N_143 +11 1 +.names cpu_est_3_reg.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n +11 1 +.names CLK_OSZI_c.BLIF inst_VPA_D.C +1 1 +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_144_1 +11 1 +.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_reg.D +1- 1 +-1 1 +.names N_124.BLIF N_124_i +0 1 +.names gnd_n_n +.names N_112.BLIF N_112_i +0 1 .names vcc_n_n 1 -.names un1_UDS_000_INT_0_sqmuxa_i.BLIF un1_UDS_000_INT_0_sqmuxa +.names CLK_000_c.BLIF inst_CLK_000_D.D +1 1 +.names sm_amiga_ns_0_0__n.BLIF SM_AMIGA_7_.D 0 1 .names A_15_.BLIF a_15__n 1 1 -.names N_124_0.BLIF N_124 -0 1 +.names N_109_i.BLIF N_111_i.BLIF N_86_i_1 +11 1 .names A_14_.BLIF a_14__n 1 1 +.names CLK_OSZI_c.BLIF inst_CLK_000_D.C +1 1 +.names N_86_i_1.BLIF N_122_i.BLIF SM_AMIGA_6_.D +11 1 +.names A_13_.BLIF a_13__n +1 1 +.names BG_030_c_i.BLIF CPU_SPACE_i.BLIF un1_bg_030_0_1 +11 1 +.names A_12_.BLIF a_12__n +1 1 +.names AS_030_c.BLIF N_109_i.BLIF un1_bg_030_0_2 +11 1 +.names A_11_.BLIF a_11__n +1 1 .names RST_c.BLIF RESETDFFreg.D 1 1 -.names N_136.BLIF N_136_i -0 1 -.names A_13_.BLIF a_13__n +.names un1_bg_030_0_1.BLIF un1_bg_030_0_2.BLIF un1_bg_030_0 +11 1 +.names A_10_.BLIF a_10__n 1 1 -.names inst_RISING_CLK_AMIGA.BLIF RISING_CLK_AMIGA_i -0 1 -.names A_12_.BLIF a_12__n +.names AS_030_i.BLIF CPU_SPACE_i.BLIF state_machine_as_030_000_sync_3_2_1_n +11 1 +.names A_9_.BLIF a_9__n 1 1 .names CLK_OSZI_c.BLIF RESETDFFreg.C 1 1 -.names state_machine_un4_bgack_000_0_n.BLIF state_machine_un4_bgack_000_n -0 1 -.names A_11_.BLIF a_11__n +.names state_machine_as_030_000_sync_3_2_1_n.BLIF state_machine_un42_clk_030_i_n.BLIF state_machine_as_030_000_sync_3_2_n +11 1 +.names A_8_.BLIF a_8__n 1 1 -.names BG_030_c.BLIF BG_030_c_i -0 1 -.names A_10_.BLIF a_10__n +.names size_c_0__n.BLIF a_c_i_0__n.BLIF state_machine_un31_clk_000_d_i_1_n +11 1 +.names A_7_.BLIF a_7__n 1 1 -.names state_machine_un1_clk_030_0_n.BLIF state_machine_un1_clk_030_n -0 1 -.names A_9_.BLIF a_9__n +.names state_machine_un31_clk_000_d_i_1_n.BLIF size_c_i_1__n.BLIF state_machine_un31_clk_000_d_i_n +11 1 +.names A_6_.BLIF a_6__n 1 1 .names inst_CLK_000_D.BLIF inst_CLK_000_DD.D 1 1 -.names state_machine_un17_clk_030_0_n.BLIF state_machine_un17_clk_030_n -0 1 -.names A_8_.BLIF a_8__n +.names a_i_24__n.BLIF a_i_25__n.BLIF N_186_1 +11 1 +.names A_5_.BLIF a_5__n 1 1 -.names un1_as_030_2_0.BLIF un1_as_030_2 -0 1 -.names A_7_.BLIF a_7__n +.names a_i_26__n.BLIF a_i_27__n.BLIF N_186_2 +11 1 +.names A_4_.BLIF a_4__n 1 1 .names CLK_OSZI_c.BLIF inst_CLK_000_DD.C 1 1 -.names N_137.BLIF N_137_i -0 1 -.names A_6_.BLIF a_6__n -1 1 -.names N_138.BLIF N_138_i -0 1 -.names A_5_.BLIF a_5__n -1 1 -.names N_120_i.BLIF N_120 -0 1 -.names A_4_.BLIF a_4__n -1 1 -.names inst_CLK_OUT_PRE.BLIF inst_CLK_OUT_INTreg.D -1 1 -.names N_125_0.BLIF N_125 -0 1 +.names a_i_28__n.BLIF a_i_29__n.BLIF N_186_3 +11 1 .names A_3_.BLIF a_3__n 1 1 -.names N_173.BLIF N_173_i +.names N_145.BLIF N_145_i 0 1 .names A_2_.BLIF a_2__n 1 1 -.names CLK_OSZI_c.BLIF inst_CLK_OUT_INTreg.C -1 1 -.names N_172.BLIF N_172_i +.names N_146.BLIF N_146_i 0 1 .names A_1_.BLIF a_1__n 1 1 -.names N_174.BLIF N_174_i +.names inst_CLK_OUT_PRE.BLIF inst_CLK_OUT_INTreg.D +1 1 +.names N_142.BLIF N_142_i +0 1 +.names clk_cpu_est_11_0_1__n.BLIF clk_cpu_est_11_1__n +0 1 +.names CLK_OSZI_c.BLIF inst_CLK_OUT_INTreg.C +1 1 +.names N_140.BLIF N_140_i +0 1 +.names N_139.BLIF N_139_i +0 1 +.names N_141.BLIF N_141_i +0 1 +.names N_108.BLIF G_100.X1 +1 1 +.names N_138_i.BLIF N_138 +0 1 +.names N_137_i.BLIF N_137 +0 1 +.names SM_AMIGA_D_2_.BLIF G_100.X2 +1 1 +.names N_136_i.BLIF N_136 +0 1 +.names N_143.BLIF N_143_i +0 1 +.names N_144.BLIF N_144_i +0 1 +.names CLK_CNT_0_.BLIF CLK_OUT_PRE_0.X1 +1 1 +.names N_101_0.BLIF N_101 +0 1 +.names N_115.BLIF N_115_i +0 1 +.names inst_CLK_OUT_PRE.BLIF CLK_OUT_PRE_0.X2 +1 1 +.names N_116.BLIF N_116_i +0 1 +.names size_c_1__n.BLIF size_c_i_1__n +0 1 +.names state_machine_un31_clk_000_d_i_n.BLIF state_machine_un31_clk_000_d_n +0 1 +.names N_106.BLIF G_98.X1 +1 1 +.names inst_RISING_CLK_AMIGA.BLIF RISING_CLK_AMIGA_i +0 1 +.names state_machine_un4_bgack_000_0_n.BLIF state_machine_un4_bgack_000_n +0 1 +.names SM_AMIGA_D_0_.BLIF G_98.X2 +1 1 +.names BG_030_c.BLIF BG_030_c_i +0 1 +.names state_machine_un1_clk_030_0_n.BLIF state_machine_un1_clk_030_n +0 1 +.names state_machine_un17_clk_030_0_n.BLIF state_machine_un17_clk_030_n +0 1 +.names N_107.BLIF G_99.X1 +1 1 +.names un1_as_030_2_0.BLIF un1_as_030_2 +0 1 +.names state_machine_as_030_000_sync_3_2_n.BLIF state_machine_as_030_000_sync_3_n +0 1 +.names SM_AMIGA_D_1_.BLIF G_99.X2 +1 1 +.names N_109.BLIF N_109_i +0 1 +.names un1_bg_030_0.BLIF un1_bg_030 +0 1 +.names N_111.BLIF N_111_i +0 1 +.names clk_un3_clk_000_dd_n.BLIF cpu_est_0_0_.X1 +1 1 +.names N_122.BLIF N_122_i +0 1 +.names N_147.BLIF N_147_i +0 1 +.names cpu_est_0_.BLIF cpu_est_0_0_.X2 +1 1 +.names clk_cpu_est_11_0_3__n.BLIF clk_cpu_est_11_3__n +0 1 +.names N_161.BLIF N_161_i +0 1 +.names a_c_0__n.BLIF a_c_i_0__n +0 1 +.names cpu_est_0_0_.BLIF cpu_est_0_.D +1 1 +.names state_machine_uds_000_int_8_0_n.BLIF state_machine_uds_000_int_8_n +0 1 +.names CLK_OUT_PRE_0.BLIF inst_CLK_OUT_PRE.D +1 1 +.names state_machine_lds_000_int_8_0_n.BLIF state_machine_lds_000_int_8_n +0 1 +.names N_113.BLIF N_113_i +0 1 +.names sm_amiga_ns_0_2__n.BLIF SM_AMIGA_5_.D +0 1 +.names N_118.BLIF N_118_i +0 1 +.names N_117.BLIF N_117_i +0 1 +.names sm_amiga_ns_0_5__n.BLIF SM_AMIGA_2_.D 0 1 .end diff --git a/Logic/BUS68030.bl1 b/Logic/BUS68030.bl1 index 7a9dc45..b90f347 100644 --- a/Logic/BUS68030.bl1 +++ b/Logic/BUS68030.bl1 @@ -1,95 +1,91 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Thu May 15 19:20:52 2014 +#$ DATE Thu May 15 22:17:27 2014 #$ MODULE bus68030 -#$ PINS 74 A_30_ A_29_ SIZE_1_ A_28_ A_27_ A_31_ A_26_ A_25_ IPL_030_2_ A_24_ A_23_ \ -# IPL_2_ A_22_ A_21_ DSACK_1_ A_20_ A_19_ FC_1_ A_18_ AS_030 A_17_ AS_000 A_16_ DS_030 A_15_ \ -# UDS_000 A_14_ LDS_000 A_13_ CPU_SPACE A_12_ BERR A_11_ BG_030 A_10_ BG_000 A_9_ BGACK_030 \ -# A_8_ BGACK_000 A_7_ CLK_030 A_6_ CLK_000 A_5_ CLK_OSZI A_4_ CLK_DIV_OUT A_3_ CLK_EXP A_2_ \ -# FPU_CS A_1_ DTACK A_0_ AVEC IPL_030_1_ AVEC_EXP IPL_030_0_ E IPL_1_ VPA IPL_0_ VMA DSACK_0_ \ -# RST FC_0_ RESET RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN \ -# SIZE_0_ -#$ NODES 414 a_15__n a_c_22__n a_14__n a_c_23__n a_13__n a_c_24__n a_12__n \ -# inst_BGACK_030_INTreg a_c_25__n inst_CLK_OUT_INTreg a_11__n inst_FPU_CS_INTreg \ -# a_c_26__n cpu_est_3_reg a_10__n inst_VMA_INTreg a_c_27__n gnd_n_n a_9__n cpu_est_1_ \ -# a_c_28__n inst_AS_000_INTreg a_8__n inst_AS_030_000_SYNC a_c_29__n inst_DTACK_SYNC \ -# a_7__n inst_VPA_D a_c_30__n inst_VPA_SYNC a_6__n inst_CLK_000_D a_c_31__n \ -# inst_CLK_000_DD a_5__n inst_CLK_OUT_PRE CPU_SPACE_c vcc_n_n a_4__n cpu_est_0_ \ -# cpu_est_2_ BG_030_c a_3__n CLK_CNT_0_ SM_AMIGA_6_ BG_000DFFSHreg a_2__n SM_AMIGA_7_ \ -# inst_UDS_000_INTreg a_1__n inst_LDS_000_INTreg BGACK_000_c inst_RISING_CLK_AMIGA \ -# DSACK_INT_1_ CLK_030_c inst_DTACK_DMA SM_AMIGA_4_ CLK_000_c SM_AMIGA_3_ SM_AMIGA_5_ \ -# CLK_OSZI_c un1_clk_000_cnt_3__n CLK_000_CNT_0_ CLK_000_CNT_1_ CLK_000_CNT_2_ \ -# CLK_000_CNT_3_ IPL_030DFFSH_0_reg state_machine_un14_as_000_int_n SM_AMIGA_2_ \ -# IPL_030DFFSH_1_reg SM_AMIGA_1_ SM_AMIGA_0_ IPL_030DFFSH_2_reg SM_AMIGA_D_0_ \ -# SM_AMIGA_D_1_ ipl_c_0__n SM_AMIGA_D_2_ clk_exp ipl_c_1__n G_128 G_130 ipl_c_2__n G_132 \ -# dsack_c_1__n DTACK_c RST_c RESETDFFreg RW_c cpu_est_0_0_ fc_c_0__n fc_c_1__n \ -# CLK_OUT_PRE_0 N_123 N_148_i clk_rising_clk_amiga_1_n N_147_i G_122 \ -# VMA_INT_1_sqmuxa_0 G_123 N_170_i G_124 N_171_i DSACK_INT_1_sqmuxa N_161_i N_120 \ -# N_164_i N_144_1 N_165_i N_251 N_168_i N_254 N_166_i N_186 N_167_i un1_clk_000_cnt_0__n \ -# N_169_i N_184 clk_cpu_est_11_0_1__n un1_clk_000_cnt_1__n N_173_i \ -# un1_clk_000_cnt_2__n N_172_i state_machine_un69_clk_000_d_n N_174_i \ -# state_machine_un78_clk_000_d_n clk_cpu_est_11_0_3__n N_149 N_121_i N_119 N_126_0 \ -# N_135 N_123_0 state_machine_un67_clk_000_d_n N_122_0 \ -# state_machine_un80_clk_000_d_n N_142_i N_132 N_143_i N_131 sm_amiga_ns_0_5__n \ -# state_machine_un25_clk_000_d_n N_141_i N_150 N_140_i N_151 sm_amiga_ns_0_4__n N_144 \ -# N_146 LDS_000_INT_1_sqmuxa_i N_143 un1_UDS_000_INT_0_sqmuxa_2_0 N_145 \ -# UDS_000_INT_0_sqmuxa_i state_machine_lds_000_int_8_n un1_UDS_000_INT_0_sqmuxa_i \ -# un1_UDS_000_INT_0_sqmuxa_2 N_124_0 state_machine_uds_000_int_8_n N_136_i \ -# LDS_000_INT_0_sqmuxa state_machine_un42_clk_030_n RISING_CLK_AMIGA_i un1_bg_030 \ -# state_machine_un4_bgack_000_0_n N_133 BG_030_c_i \ -# state_machine_as_030_000_sync_3_n state_machine_un1_clk_030_0_n N_125 \ -# state_machine_un17_clk_030_0_n N_137 un1_as_030_2_0 N_138 N_137_i \ -# DSACK_INT_1_sqmuxa_1 N_138_i un1_as_030_2 state_machine_un17_clk_030_n N_120_i \ -# state_machine_un1_clk_030_n N_125_0 state_machine_un4_bgack_000_n \ -# state_machine_as_030_000_sync_3_2_n VPA_SYNC_1_sqmuxa N_133_i VPA_SYNC_1_sqmuxa_1 \ -# un1_bg_030_0 N_122 a_c_i_0__n AS_000_INT_1_sqmuxa state_machine_uds_000_int_8_0_n \ -# N_136 state_machine_lds_000_int_8_0_n N_124 N_151_i N_130 \ -# state_machine_un15_clk_000_d_n N_146_i un1_UDS_000_INT_0_sqmuxa N_145_i \ -# UDS_000_INT_0_sqmuxa sm_amiga_ns_0_7__n LDS_000_INT_1_sqmuxa N_144_i N_139 N_150_i \ -# N_140 N_126 size_c_i_1__n N_141 state_machine_un25_clk_000_d_i_n N_121 \ -# state_machine_un80_clk_000_d_i_n N_142 state_machine_un67_clk_000_d_i_n \ -# VPA_SYNC_1_sqmuxa_1_0 state_machine_un78_clk_000_d_0_n DTACK_SYNC_1_sqmuxa \ -# clk_rising_clk_amiga_1_i_n DTACK_SYNC_1_sqmuxa_1 N_135_i N_149_2 N_104_i \ -# clk_un3_clk_000_dd_n N_149_i N_164 N_119_0 N_171 clk_000_cnt_i_1__n N_170 \ -# clk_000_cnt_i_0__n clk_cpu_est_11_3__n clk_000_cnt_i_3__n N_174 clk_000_cnt_i_2__n \ -# N_172 state_machine_un69_clk_000_d_0_n N_173 state_machine_un69_clk_000_d_0_1_n \ -# clk_cpu_est_11_1__n state_machine_un69_clk_000_d_0_2_n N_169 \ -# state_machine_un25_clk_000_d_i_1_n N_167 N_116_i_1 N_166 un1_bg_030_0_1 N_168 \ -# un1_bg_030_0_2 N_165 state_machine_as_030_000_sync_3_2_1_n VMA_INT_1_sqmuxa \ -# un1_UDS_000_INT_0_sqmuxa_i_1 N_147 clk_cpu_est_11_0_1_3__n N_148 \ -# clk_cpu_est_11_0_1_1__n RW_i clk_cpu_est_11_0_2_1__n clk_exp_i N_251_1 CLK_000_DD_i \ -# N_251_2 CLK_000_D_i N_251_3 AS_000_INT_i N_251_4 cpu_est_i_0__n N_251_5 \ -# cpu_est_i_2__n N_251_6 cpu_est_i_3__n N_254_1 cpu_est_i_1__n N_254_2 N_149_2_i \ -# DSACK_INT_1_sqmuxa_1_0 VPA_D_i DSACK_INT_1_sqmuxa_2 DTACK_i DSACK_INT_1_sqmuxa_3 \ -# VPA_SYNC_i N_149_1 DTACK_SYNC_i N_149_2_0 AS_030_i N_132_1 DTACK_SYNC_1_sqmuxa_i \ -# N_131_1 DS_030_i state_machine_un42_clk_030_1_n sm_amiga_i_4__n \ -# state_machine_un42_clk_030_2_n sm_amiga_i_6__n state_machine_un42_clk_030_3_n \ -# sm_amiga_i_5__n state_machine_un42_clk_030_4_n N_139_i \ -# state_machine_un42_clk_030_5_n state_machine_un15_clk_000_d_i_n N_142_1 N_130_i \ -# N_130_1 sm_amiga_i_0__n N_130_2 sm_amiga_i_7__n UDS_000_INT_0_sqmuxa_1 \ -# VPA_SYNC_1_sqmuxa_i UDS_000_INT_0_sqmuxa_2 dsack_i_1__n DTACK_SYNC_1_sqmuxa_1_0 \ -# DSACK_INT_1_sqmuxa_i VPA_SYNC_1_sqmuxa_1_1 a_i_18__n VPA_SYNC_1_sqmuxa_2 a_i_16__n \ -# VPA_SYNC_1_sqmuxa_3 a_i_19__n N_171_1 CLK_030_i N_170_1 \ -# state_machine_un42_clk_030_i_n N_174_1 AS_030_000_SYNC_i clk_exp_1 N_131_i \ -# cpu_est_0_1__un3_n N_132_i cpu_est_0_1__un1_n sm_amiga_i_2__n cpu_est_0_1__un0_n \ -# sm_amiga_i_1__n vma_int_0_un3_n sm_amiga_i_3__n vma_int_0_un1_n CLK_000_i \ -# vma_int_0_un0_n a_i_30__n cpu_est_0_3__un3_n a_i_31__n cpu_est_0_3__un1_n a_i_28__n \ -# cpu_est_0_3__un0_n a_i_29__n cpu_est_0_2__un3_n a_i_26__n cpu_est_0_2__un1_n \ -# a_i_27__n cpu_est_0_2__un0_n a_i_24__n dtack_sync_0_un3_n a_i_25__n \ -# dtack_sync_0_un1_n dtack_sync_0_un0_n sm_amiga_d_0_0__un3_n RST_i \ -# sm_amiga_d_0_0__un1_n sm_amiga_d_0_0__un0_n FPU_CS_INT_i bgack_030_int_0_un3_n \ -# CPU_SPACE_i bgack_030_int_0_un1_n BGACK_030_INT_i bgack_030_int_0_un0_n AS_030_c \ -# bg_000_0_un3_n bg_000_0_un1_n bg_000_0_un0_n DS_030_c as_030_000_sync_0_un3_n \ -# as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n fpu_cs_int_0_un3_n size_c_0__n \ -# fpu_cs_int_0_un1_n fpu_cs_int_0_un0_n size_c_1__n dsack_int_0_1__un3_n \ -# dsack_int_0_1__un1_n a_c_0__n dsack_int_0_1__un0_n vpa_sync_0_un3_n \ -# vpa_sync_0_un1_n vpa_sync_0_un0_n as_000_int_0_un3_n as_000_int_0_un1_n \ -# as_000_int_0_un0_n ipl_030_0_2__un3_n ipl_030_0_2__un1_n ipl_030_0_2__un0_n \ -# ipl_030_0_1__un3_n ipl_030_0_1__un1_n ipl_030_0_1__un0_n ipl_030_0_0__un3_n \ -# ipl_030_0_0__un1_n ipl_030_0_0__un0_n sm_amiga_d_0_2__un3_n a_c_16__n \ -# sm_amiga_d_0_2__un1_n sm_amiga_d_0_2__un0_n a_c_17__n sm_amiga_d_0_1__un3_n \ -# sm_amiga_d_0_1__un1_n a_c_18__n sm_amiga_d_0_1__un0_n lds_000_int_0_un3_n \ -# a_c_19__n lds_000_int_0_un1_n lds_000_int_0_un0_n a_c_20__n uds_000_int_0_un3_n \ -# uds_000_int_0_un1_n a_c_21__n uds_000_int_0_un0_n +#$ PINS 74 FC_0_ SIZE_1_ A_31_ IPL_030_2_ IPL_2_ DSACK_1_ FC_1_ AS_030 AS_000 DS_030 \ +# UDS_000 LDS_000 CPU_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 \ +# CLK_OSZI CLK_DIV_OUT SIZE_0_ CLK_EXP A_30_ FPU_CS A_29_ DTACK A_28_ AVEC A_27_ AVEC_EXP \ +# A_26_ E A_25_ VPA A_24_ VMA A_23_ RST A_22_ RESET A_21_ RW A_20_ AMIGA_BUS_ENABLE A_19_ \ +# AMIGA_BUS_DATA_DIR A_18_ AMIGA_BUS_ENABLE_LOW A_17_ CIIN A_16_ A_15_ A_14_ A_13_ A_12_ \ +# A_11_ A_10_ A_9_ A_8_ A_7_ A_6_ A_5_ A_4_ A_3_ A_2_ A_1_ A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ \ +# IPL_0_ DSACK_0_ +#$ NODES 378 a_c_30__n a_c_31__n CPU_SPACE_c inst_BGACK_030_INTreg BG_030_c \ +# inst_CLK_OUT_INTreg inst_FPU_CS_INTreg BG_000DFFSHreg cpu_est_3_reg \ +# inst_VMA_INTreg gnd_n_n BGACK_000_c cpu_est_0_ cpu_est_1_ CLK_030_c cpu_est_d_0_ \ +# cpu_est_d_3_ CLK_000_c inst_AS_000_INTreg inst_AS_030_000_SYNC CLK_OSZI_c \ +# inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D inst_CLK_000_DD \ +# IPL_030DFFSH_0_reg inst_CLK_OUT_PRE vcc_n_n IPL_030DFFSH_1_reg cpu_est_d_1_ \ +# cpu_est_d_2_ IPL_030DFFSH_2_reg cpu_est_2_ CLK_CNT_0_ ipl_c_0__n SM_AMIGA_6_ \ +# SM_AMIGA_7_ ipl_c_1__n inst_UDS_000_INTreg inst_LDS_000_INTreg ipl_c_2__n \ +# inst_RISING_CLK_AMIGA state_machine_un57_clk_000_d_n dsack_c_1__n SM_AMIGA_1_ \ +# DSACK_INT_1_ DTACK_c inst_DTACK_DMA SM_AMIGA_4_ SM_AMIGA_3_ \ +# state_machine_un13_as_000_int_n SM_AMIGA_5_ SM_AMIGA_2_ SM_AMIGA_0_ SM_AMIGA_D_0_ \ +# RST_c SM_AMIGA_D_1_ SM_AMIGA_D_2_ RESETDFFreg clk_exp RW_c fc_c_0__n fc_c_1__n \ +# state_machine_un57_clk_000_d_0_n N_161_i a_c_i_0__n \ +# state_machine_uds_000_int_8_0_n state_machine_lds_000_int_8_0_n N_113_i \ +# cpu_est_0_0_ sm_amiga_ns_0_2__n N_118_i N_117_i sm_amiga_ns_0_5__n N_123_i \ +# CLK_OUT_PRE_0 N_119_i N_120_i sm_amiga_ns_0_7__n CLK_OUT_PRE_i N_106 N_102_0 N_107 \ +# size_c_i_1__n clk_un3_clk_000_dd_n state_machine_un31_clk_000_d_i_n \ +# clk_cpu_est_11_1__n RISING_CLK_AMIGA_i clk_cpu_est_11_3__n \ +# state_machine_un4_bgack_000_0_n G_98 BG_030_c_i G_99 state_machine_un1_clk_030_0_n \ +# G_100 state_machine_un17_clk_030_0_n N_161 un1_as_030_2_0 N_114 \ +# state_machine_as_030_000_sync_3_2_n N_109 N_109_i N_111 un1_bg_030_0 N_112 N_111_i \ +# N_122 N_122_i N_115 N_101 N_147_i N_116 clk_cpu_est_11_0_3__n N_124 N_145_i N_139 \ +# N_146_i N_137 N_142_i N_140 clk_cpu_est_11_0_1__n N_141 N_140_i N_136 N_139_i N_142 \ +# N_141_i N_145 N_138_i N_138 N_137_i N_146 N_136_i N_143 N_143_i N_144 N_144_i \ +# UDS_000_INT_0_sqmuxa N_134_i UDS_000_INT_0_sqmuxa_1 N_101_0 N_147 N_115_i N_147_1 \ +# N_116_i state_machine_un13_clk_000_d_1_n N_186 N_124_i N_189 \ +# state_machine_un42_clk_030_n N_112_i un1_bg_030 sm_amiga_ns_0_0__n \ +# state_machine_as_030_000_sync_3_n N_86_i_1 un1_as_030_2 un1_bg_030_0_1 \ +# state_machine_un17_clk_030_n un1_bg_030_0_2 state_machine_un1_clk_030_n \ +# state_machine_as_030_000_sync_3_2_1_n state_machine_un4_bgack_000_n \ +# state_machine_un31_clk_000_d_i_1_n N_108 N_186_1 state_machine_un31_clk_000_d_n \ +# N_186_2 state_machine_un13_clk_000_d_n N_186_3 state_machine_un13_clk_000_d_4_n \ +# N_186_4 state_machine_un8_clk_000_d_n N_186_5 DTACK_SYNC_1_sqmuxa N_186_6 \ +# VPA_SYNC_1_sqmuxa_1_0 N_189_1 VPA_SYNC_1_sqmuxa N_189_2 N_123 \ +# clk_cpu_est_11_0_1_1__n N_118 clk_cpu_est_11_0_2_1__n N_110 \ +# clk_cpu_est_11_0_1_3__n N_102 N_143_1 N_120 N_144_1 N_119 N_106_1 N_117 N_106_2 N_113 \ +# N_107_1 state_machine_lds_000_int_8_n UDS_000_INT_0_sqmuxa_1_1 \ +# state_machine_uds_000_int_8_n UDS_000_INT_0_sqmuxa_1_2 DTACK_SYNC_1_sqmuxa_1 \ +# UDS_000_INT_0_sqmuxa_1_3 un2_clk_030_1 UDS_000_INT_0_sqmuxa_1_0 \ +# VPA_SYNC_1_sqmuxa_1 UDS_000_INT_0_sqmuxa_2 AS_000_INT_1_sqmuxa \ +# state_machine_un42_clk_030_1_n VMA_INT_1_sqmuxa state_machine_un42_clk_030_2_n \ +# DSACK_INT_1_sqmuxa state_machine_un42_clk_030_3_n RW_i \ +# state_machine_un42_clk_030_4_n clk_exp_i state_machine_un42_clk_030_5_n \ +# DTACK_SYNC_1_sqmuxa_i state_machine_un13_clk_000_d_1_0_n N_114_i \ +# state_machine_un13_clk_000_d_4_1_n VPA_SYNC_1_sqmuxa_i \ +# state_machine_un8_clk_000_d_1_n N_110_i state_machine_un8_clk_000_d_2_n N_108_i \ +# state_machine_un8_clk_000_d_3_n cpu_est_d_i_3__n state_machine_un8_clk_000_d_4_n \ +# cpu_est_d_i_0__n DTACK_SYNC_1_sqmuxa_1_0 CLK_000_D_i VPA_SYNC_1_sqmuxa_1_1 \ +# AS_030_i VPA_SYNC_1_sqmuxa_2 AS_000_INT_i VPA_SYNC_1_sqmuxa_3 dsack_i_1__n \ +# VPA_SYNC_1_sqmuxa_4 state_machine_un13_clk_000_d_i_n N_108_1 \ +# state_machine_un8_clk_000_d_i_n N_118_1 state_machine_un13_clk_000_d_1_i_n \ +# N_110_1 sm_amiga_i_1__n clk_exp_1 sm_amiga_i_2__n sm_amiga_d_0_2__un3_n \ +# sm_amiga_i_0__n sm_amiga_d_0_2__un1_n sm_amiga_i_3__n sm_amiga_d_0_2__un0_n \ +# VPA_D_i dsack_int_0_1__un3_n VMA_INT_i dsack_int_0_1__un1_n DTACK_i \ +# dsack_int_0_1__un0_n cpu_est_i_3__n vma_int_0_un3_n a_i_18__n vma_int_0_un1_n \ +# a_i_16__n vma_int_0_un0_n a_i_19__n vpa_sync_0_un3_n CLK_030_i vpa_sync_0_un1_n \ +# state_machine_un42_clk_030_i_n vpa_sync_0_un0_n DS_030_i as_000_int_0_un3_n \ +# cpu_est_i_1__n as_000_int_0_un1_n AS_030_000_SYNC_i as_000_int_0_un0_n \ +# cpu_est_i_0__n dtack_sync_0_un3_n sm_amiga_i_4__n dtack_sync_0_un1_n \ +# sm_amiga_i_6__n dtack_sync_0_un0_n cpu_est_i_2__n lds_000_int_0_un3_n \ +# UDS_000_INT_0_sqmuxa_1_i lds_000_int_0_un1_n UDS_000_INT_0_sqmuxa_i \ +# lds_000_int_0_un0_n sm_amiga_i_5__n uds_000_int_0_un3_n CLK_000_DD_i \ +# uds_000_int_0_un1_n sm_amiga_i_7__n uds_000_int_0_un0_n a_i_30__n bg_000_0_un3_n \ +# a_i_31__n bg_000_0_un1_n a_i_28__n bg_000_0_un0_n a_i_29__n as_030_000_sync_0_un3_n \ +# a_i_26__n as_030_000_sync_0_un1_n a_i_27__n as_030_000_sync_0_un0_n a_i_24__n \ +# fpu_cs_int_0_un3_n a_i_25__n fpu_cs_int_0_un1_n fpu_cs_int_0_un0_n \ +# ipl_030_0_2__un3_n RST_i ipl_030_0_2__un1_n N_107_i ipl_030_0_2__un0_n N_106_i \ +# ipl_030_0_1__un3_n FPU_CS_INT_i ipl_030_0_1__un1_n CPU_SPACE_i ipl_030_0_1__un0_n \ +# BGACK_030_INT_i ipl_030_0_0__un3_n AS_030_c ipl_030_0_0__un1_n ipl_030_0_0__un0_n \ +# bgack_030_int_0_un3_n DS_030_c bgack_030_int_0_un1_n bgack_030_int_0_un0_n \ +# sm_amiga_d_0_0__un3_n sm_amiga_d_0_0__un1_n size_c_0__n sm_amiga_d_0_0__un0_n \ +# sm_amiga_d_0_1__un3_n size_c_1__n sm_amiga_d_0_1__un1_n sm_amiga_d_0_1__un0_n \ +# a_c_0__n cpu_est_0_1__un3_n cpu_est_0_1__un1_n cpu_est_0_1__un0_n \ +# cpu_est_0_2__un3_n cpu_est_0_2__un1_n cpu_est_0_2__un0_n cpu_est_0_3__un3_n \ +# cpu_est_0_3__un1_n cpu_est_0_3__un0_n a_15__n a_14__n a_13__n a_12__n a_c_16__n \ +# a_11__n a_c_17__n a_10__n a_c_18__n a_9__n a_c_19__n a_8__n a_c_20__n a_7__n a_c_21__n \ +# a_6__n a_c_22__n a_5__n a_c_23__n a_4__n a_c_24__n a_3__n a_c_25__n a_2__n a_c_26__n \ +# a_1__n a_c_27__n a_c_28__n a_c_29__n .model bus68030 .inputs SIZE_1_.BLIF A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF AS_030.BLIF DS_030.BLIF \ CPU_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF \ @@ -99,244 +95,246 @@ A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF A_15_.BLIF \ A_14_.BLIF A_13_.BLIF A_12_.BLIF A_11_.BLIF A_10_.BLIF A_9_.BLIF A_8_.BLIF \ A_7_.BLIF A_6_.BLIF A_5_.BLIF A_4_.BLIF A_3_.BLIF A_2_.BLIF A_1_.BLIF \ A_0_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF DSACK_1_.BLIF DTACK.BLIF \ -DSACK_0_.BLIF a_15__n.BLIF a_c_22__n.BLIF a_14__n.BLIF a_c_23__n.BLIF \ -a_13__n.BLIF a_c_24__n.BLIF a_12__n.BLIF inst_BGACK_030_INTreg.BLIF \ -a_c_25__n.BLIF inst_CLK_OUT_INTreg.BLIF a_11__n.BLIF inst_FPU_CS_INTreg.BLIF \ -a_c_26__n.BLIF cpu_est_3_reg.BLIF a_10__n.BLIF inst_VMA_INTreg.BLIF \ -a_c_27__n.BLIF gnd_n_n.BLIF a_9__n.BLIF cpu_est_1_.BLIF a_c_28__n.BLIF \ -inst_AS_000_INTreg.BLIF a_8__n.BLIF inst_AS_030_000_SYNC.BLIF a_c_29__n.BLIF \ -inst_DTACK_SYNC.BLIF a_7__n.BLIF inst_VPA_D.BLIF a_c_30__n.BLIF \ -inst_VPA_SYNC.BLIF a_6__n.BLIF inst_CLK_000_D.BLIF a_c_31__n.BLIF \ -inst_CLK_000_DD.BLIF a_5__n.BLIF inst_CLK_OUT_PRE.BLIF CPU_SPACE_c.BLIF \ -vcc_n_n.BLIF a_4__n.BLIF cpu_est_0_.BLIF cpu_est_2_.BLIF BG_030_c.BLIF \ -a_3__n.BLIF CLK_CNT_0_.BLIF SM_AMIGA_6_.BLIF BG_000DFFSHreg.BLIF a_2__n.BLIF \ -SM_AMIGA_7_.BLIF inst_UDS_000_INTreg.BLIF a_1__n.BLIF inst_LDS_000_INTreg.BLIF \ -BGACK_000_c.BLIF inst_RISING_CLK_AMIGA.BLIF DSACK_INT_1_.BLIF CLK_030_c.BLIF \ -inst_DTACK_DMA.BLIF SM_AMIGA_4_.BLIF CLK_000_c.BLIF SM_AMIGA_3_.BLIF \ -SM_AMIGA_5_.BLIF CLK_OSZI_c.BLIF un1_clk_000_cnt_3__n.BLIF CLK_000_CNT_0_.BLIF \ -CLK_000_CNT_1_.BLIF CLK_000_CNT_2_.BLIF CLK_000_CNT_3_.BLIF \ -IPL_030DFFSH_0_reg.BLIF state_machine_un14_as_000_int_n.BLIF SM_AMIGA_2_.BLIF \ -IPL_030DFFSH_1_reg.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_0_.BLIF \ -IPL_030DFFSH_2_reg.BLIF SM_AMIGA_D_0_.BLIF SM_AMIGA_D_1_.BLIF ipl_c_0__n.BLIF \ -SM_AMIGA_D_2_.BLIF clk_exp.BLIF ipl_c_1__n.BLIF G_128.BLIF G_130.BLIF \ -ipl_c_2__n.BLIF G_132.BLIF dsack_c_1__n.BLIF DTACK_c.BLIF RST_c.BLIF \ -RESETDFFreg.BLIF RW_c.BLIF cpu_est_0_0_.BLIF fc_c_0__n.BLIF fc_c_1__n.BLIF \ -CLK_OUT_PRE_0.BLIF N_123.BLIF N_148_i.BLIF clk_rising_clk_amiga_1_n.BLIF \ -N_147_i.BLIF G_122.BLIF VMA_INT_1_sqmuxa_0.BLIF G_123.BLIF N_170_i.BLIF \ -G_124.BLIF N_171_i.BLIF DSACK_INT_1_sqmuxa.BLIF N_161_i.BLIF N_120.BLIF \ -N_164_i.BLIF N_144_1.BLIF N_165_i.BLIF N_251.BLIF N_168_i.BLIF N_254.BLIF \ -N_166_i.BLIF N_186.BLIF N_167_i.BLIF un1_clk_000_cnt_0__n.BLIF N_169_i.BLIF \ -N_184.BLIF clk_cpu_est_11_0_1__n.BLIF un1_clk_000_cnt_1__n.BLIF N_173_i.BLIF \ -un1_clk_000_cnt_2__n.BLIF N_172_i.BLIF state_machine_un69_clk_000_d_n.BLIF \ -N_174_i.BLIF state_machine_un78_clk_000_d_n.BLIF clk_cpu_est_11_0_3__n.BLIF \ -N_149.BLIF N_121_i.BLIF N_119.BLIF N_126_0.BLIF N_135.BLIF N_123_0.BLIF \ -state_machine_un67_clk_000_d_n.BLIF N_122_0.BLIF \ -state_machine_un80_clk_000_d_n.BLIF N_142_i.BLIF N_132.BLIF N_143_i.BLIF \ -N_131.BLIF sm_amiga_ns_0_5__n.BLIF state_machine_un25_clk_000_d_n.BLIF \ -N_141_i.BLIF N_150.BLIF N_140_i.BLIF N_151.BLIF sm_amiga_ns_0_4__n.BLIF \ -N_144.BLIF N_146.BLIF LDS_000_INT_1_sqmuxa_i.BLIF N_143.BLIF \ -un1_UDS_000_INT_0_sqmuxa_2_0.BLIF N_145.BLIF UDS_000_INT_0_sqmuxa_i.BLIF \ -state_machine_lds_000_int_8_n.BLIF un1_UDS_000_INT_0_sqmuxa_i.BLIF \ -un1_UDS_000_INT_0_sqmuxa_2.BLIF N_124_0.BLIF \ -state_machine_uds_000_int_8_n.BLIF N_136_i.BLIF LDS_000_INT_0_sqmuxa.BLIF \ -state_machine_un42_clk_030_n.BLIF RISING_CLK_AMIGA_i.BLIF un1_bg_030.BLIF \ -state_machine_un4_bgack_000_0_n.BLIF N_133.BLIF BG_030_c_i.BLIF \ -state_machine_as_030_000_sync_3_n.BLIF state_machine_un1_clk_030_0_n.BLIF \ -N_125.BLIF state_machine_un17_clk_030_0_n.BLIF N_137.BLIF un1_as_030_2_0.BLIF \ -N_138.BLIF N_137_i.BLIF DSACK_INT_1_sqmuxa_1.BLIF N_138_i.BLIF \ -un1_as_030_2.BLIF state_machine_un17_clk_030_n.BLIF N_120_i.BLIF \ -state_machine_un1_clk_030_n.BLIF N_125_0.BLIF \ -state_machine_un4_bgack_000_n.BLIF state_machine_as_030_000_sync_3_2_n.BLIF \ -VPA_SYNC_1_sqmuxa.BLIF N_133_i.BLIF VPA_SYNC_1_sqmuxa_1.BLIF un1_bg_030_0.BLIF \ -N_122.BLIF a_c_i_0__n.BLIF AS_000_INT_1_sqmuxa.BLIF \ -state_machine_uds_000_int_8_0_n.BLIF N_136.BLIF \ -state_machine_lds_000_int_8_0_n.BLIF N_124.BLIF N_151_i.BLIF N_130.BLIF \ -state_machine_un15_clk_000_d_n.BLIF N_146_i.BLIF un1_UDS_000_INT_0_sqmuxa.BLIF \ -N_145_i.BLIF UDS_000_INT_0_sqmuxa.BLIF sm_amiga_ns_0_7__n.BLIF \ -LDS_000_INT_1_sqmuxa.BLIF N_144_i.BLIF N_139.BLIF N_150_i.BLIF N_140.BLIF \ -N_126.BLIF size_c_i_1__n.BLIF N_141.BLIF state_machine_un25_clk_000_d_i_n.BLIF \ -N_121.BLIF state_machine_un80_clk_000_d_i_n.BLIF N_142.BLIF \ -state_machine_un67_clk_000_d_i_n.BLIF VPA_SYNC_1_sqmuxa_1_0.BLIF \ -state_machine_un78_clk_000_d_0_n.BLIF DTACK_SYNC_1_sqmuxa.BLIF \ -clk_rising_clk_amiga_1_i_n.BLIF DTACK_SYNC_1_sqmuxa_1.BLIF N_135_i.BLIF \ -N_149_2.BLIF N_104_i.BLIF clk_un3_clk_000_dd_n.BLIF N_149_i.BLIF N_164.BLIF \ -N_119_0.BLIF N_171.BLIF clk_000_cnt_i_1__n.BLIF N_170.BLIF \ -clk_000_cnt_i_0__n.BLIF clk_cpu_est_11_3__n.BLIF clk_000_cnt_i_3__n.BLIF \ -N_174.BLIF clk_000_cnt_i_2__n.BLIF N_172.BLIF \ -state_machine_un69_clk_000_d_0_n.BLIF N_173.BLIF \ -state_machine_un69_clk_000_d_0_1_n.BLIF clk_cpu_est_11_1__n.BLIF \ -state_machine_un69_clk_000_d_0_2_n.BLIF N_169.BLIF \ -state_machine_un25_clk_000_d_i_1_n.BLIF N_167.BLIF N_116_i_1.BLIF N_166.BLIF \ -un1_bg_030_0_1.BLIF N_168.BLIF un1_bg_030_0_2.BLIF N_165.BLIF \ -state_machine_as_030_000_sync_3_2_1_n.BLIF VMA_INT_1_sqmuxa.BLIF \ -un1_UDS_000_INT_0_sqmuxa_i_1.BLIF N_147.BLIF clk_cpu_est_11_0_1_3__n.BLIF \ -N_148.BLIF clk_cpu_est_11_0_1_1__n.BLIF RW_i.BLIF clk_cpu_est_11_0_2_1__n.BLIF \ -clk_exp_i.BLIF N_251_1.BLIF CLK_000_DD_i.BLIF N_251_2.BLIF CLK_000_D_i.BLIF \ -N_251_3.BLIF AS_000_INT_i.BLIF N_251_4.BLIF cpu_est_i_0__n.BLIF N_251_5.BLIF \ -cpu_est_i_2__n.BLIF N_251_6.BLIF cpu_est_i_3__n.BLIF N_254_1.BLIF \ -cpu_est_i_1__n.BLIF N_254_2.BLIF N_149_2_i.BLIF DSACK_INT_1_sqmuxa_1_0.BLIF \ -VPA_D_i.BLIF DSACK_INT_1_sqmuxa_2.BLIF DTACK_i.BLIF DSACK_INT_1_sqmuxa_3.BLIF \ -VPA_SYNC_i.BLIF N_149_1.BLIF DTACK_SYNC_i.BLIF N_149_2_0.BLIF AS_030_i.BLIF \ -N_132_1.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF N_131_1.BLIF DS_030_i.BLIF \ -state_machine_un42_clk_030_1_n.BLIF sm_amiga_i_4__n.BLIF \ -state_machine_un42_clk_030_2_n.BLIF sm_amiga_i_6__n.BLIF \ -state_machine_un42_clk_030_3_n.BLIF sm_amiga_i_5__n.BLIF \ -state_machine_un42_clk_030_4_n.BLIF N_139_i.BLIF \ -state_machine_un42_clk_030_5_n.BLIF state_machine_un15_clk_000_d_i_n.BLIF \ -N_142_1.BLIF N_130_i.BLIF N_130_1.BLIF sm_amiga_i_0__n.BLIF N_130_2.BLIF \ -sm_amiga_i_7__n.BLIF UDS_000_INT_0_sqmuxa_1.BLIF VPA_SYNC_1_sqmuxa_i.BLIF \ -UDS_000_INT_0_sqmuxa_2.BLIF dsack_i_1__n.BLIF DTACK_SYNC_1_sqmuxa_1_0.BLIF \ -DSACK_INT_1_sqmuxa_i.BLIF VPA_SYNC_1_sqmuxa_1_1.BLIF a_i_18__n.BLIF \ -VPA_SYNC_1_sqmuxa_2.BLIF a_i_16__n.BLIF VPA_SYNC_1_sqmuxa_3.BLIF \ -a_i_19__n.BLIF N_171_1.BLIF CLK_030_i.BLIF N_170_1.BLIF \ -state_machine_un42_clk_030_i_n.BLIF N_174_1.BLIF AS_030_000_SYNC_i.BLIF \ -clk_exp_1.BLIF N_131_i.BLIF cpu_est_0_1__un3_n.BLIF N_132_i.BLIF \ -cpu_est_0_1__un1_n.BLIF sm_amiga_i_2__n.BLIF cpu_est_0_1__un0_n.BLIF \ -sm_amiga_i_1__n.BLIF vma_int_0_un3_n.BLIF sm_amiga_i_3__n.BLIF \ -vma_int_0_un1_n.BLIF CLK_000_i.BLIF vma_int_0_un0_n.BLIF a_i_30__n.BLIF \ -cpu_est_0_3__un3_n.BLIF a_i_31__n.BLIF cpu_est_0_3__un1_n.BLIF a_i_28__n.BLIF \ -cpu_est_0_3__un0_n.BLIF a_i_29__n.BLIF cpu_est_0_2__un3_n.BLIF a_i_26__n.BLIF \ -cpu_est_0_2__un1_n.BLIF a_i_27__n.BLIF cpu_est_0_2__un0_n.BLIF a_i_24__n.BLIF \ -dtack_sync_0_un3_n.BLIF a_i_25__n.BLIF dtack_sync_0_un1_n.BLIF \ -dtack_sync_0_un0_n.BLIF sm_amiga_d_0_0__un3_n.BLIF RST_i.BLIF \ -sm_amiga_d_0_0__un1_n.BLIF sm_amiga_d_0_0__un0_n.BLIF FPU_CS_INT_i.BLIF \ -bgack_030_int_0_un3_n.BLIF CPU_SPACE_i.BLIF bgack_030_int_0_un1_n.BLIF \ -BGACK_030_INT_i.BLIF bgack_030_int_0_un0_n.BLIF AS_030_c.BLIF \ -bg_000_0_un3_n.BLIF bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF DS_030_c.BLIF \ -as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un1_n.BLIF \ -as_030_000_sync_0_un0_n.BLIF fpu_cs_int_0_un3_n.BLIF size_c_0__n.BLIF \ -fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF size_c_1__n.BLIF \ -dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un1_n.BLIF a_c_0__n.BLIF \ -dsack_int_0_1__un0_n.BLIF vpa_sync_0_un3_n.BLIF vpa_sync_0_un1_n.BLIF \ -vpa_sync_0_un0_n.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un1_n.BLIF \ -as_000_int_0_un0_n.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un1_n.BLIF \ -ipl_030_0_2__un0_n.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un1_n.BLIF \ -ipl_030_0_1__un0_n.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un1_n.BLIF \ -ipl_030_0_0__un0_n.BLIF sm_amiga_d_0_2__un3_n.BLIF a_c_16__n.BLIF \ -sm_amiga_d_0_2__un1_n.BLIF sm_amiga_d_0_2__un0_n.BLIF a_c_17__n.BLIF \ -sm_amiga_d_0_1__un3_n.BLIF sm_amiga_d_0_1__un1_n.BLIF a_c_18__n.BLIF \ -sm_amiga_d_0_1__un0_n.BLIF lds_000_int_0_un3_n.BLIF a_c_19__n.BLIF \ -lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF a_c_20__n.BLIF \ -uds_000_int_0_un3_n.BLIF uds_000_int_0_un1_n.BLIF a_c_21__n.BLIF \ -uds_000_int_0_un0_n.BLIF DSACK_1_.PIN.BLIF DTACK.PIN.BLIF +DSACK_0_.BLIF a_c_30__n.BLIF a_c_31__n.BLIF CPU_SPACE_c.BLIF \ +inst_BGACK_030_INTreg.BLIF BG_030_c.BLIF inst_CLK_OUT_INTreg.BLIF \ +inst_FPU_CS_INTreg.BLIF BG_000DFFSHreg.BLIF cpu_est_3_reg.BLIF \ +inst_VMA_INTreg.BLIF gnd_n_n.BLIF BGACK_000_c.BLIF cpu_est_0_.BLIF \ +cpu_est_1_.BLIF CLK_030_c.BLIF cpu_est_d_0_.BLIF cpu_est_d_3_.BLIF \ +CLK_000_c.BLIF inst_AS_000_INTreg.BLIF inst_AS_030_000_SYNC.BLIF \ +CLK_OSZI_c.BLIF inst_DTACK_SYNC.BLIF inst_VPA_D.BLIF inst_VPA_SYNC.BLIF \ +inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF IPL_030DFFSH_0_reg.BLIF \ +inst_CLK_OUT_PRE.BLIF vcc_n_n.BLIF IPL_030DFFSH_1_reg.BLIF cpu_est_d_1_.BLIF \ +cpu_est_d_2_.BLIF IPL_030DFFSH_2_reg.BLIF cpu_est_2_.BLIF CLK_CNT_0_.BLIF \ +ipl_c_0__n.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_7_.BLIF ipl_c_1__n.BLIF \ +inst_UDS_000_INTreg.BLIF inst_LDS_000_INTreg.BLIF ipl_c_2__n.BLIF \ +inst_RISING_CLK_AMIGA.BLIF state_machine_un57_clk_000_d_n.BLIF \ +dsack_c_1__n.BLIF SM_AMIGA_1_.BLIF DSACK_INT_1_.BLIF DTACK_c.BLIF \ +inst_DTACK_DMA.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_3_.BLIF \ +state_machine_un13_as_000_int_n.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_2_.BLIF \ +SM_AMIGA_0_.BLIF SM_AMIGA_D_0_.BLIF RST_c.BLIF SM_AMIGA_D_1_.BLIF \ +SM_AMIGA_D_2_.BLIF RESETDFFreg.BLIF clk_exp.BLIF RW_c.BLIF fc_c_0__n.BLIF \ +fc_c_1__n.BLIF state_machine_un57_clk_000_d_0_n.BLIF N_161_i.BLIF \ +a_c_i_0__n.BLIF state_machine_uds_000_int_8_0_n.BLIF \ +state_machine_lds_000_int_8_0_n.BLIF N_113_i.BLIF cpu_est_0_0_.BLIF \ +sm_amiga_ns_0_2__n.BLIF N_118_i.BLIF N_117_i.BLIF sm_amiga_ns_0_5__n.BLIF \ +N_123_i.BLIF CLK_OUT_PRE_0.BLIF N_119_i.BLIF N_120_i.BLIF \ +sm_amiga_ns_0_7__n.BLIF CLK_OUT_PRE_i.BLIF N_106.BLIF N_102_0.BLIF N_107.BLIF \ +size_c_i_1__n.BLIF clk_un3_clk_000_dd_n.BLIF \ +state_machine_un31_clk_000_d_i_n.BLIF clk_cpu_est_11_1__n.BLIF \ +RISING_CLK_AMIGA_i.BLIF clk_cpu_est_11_3__n.BLIF \ +state_machine_un4_bgack_000_0_n.BLIF G_98.BLIF BG_030_c_i.BLIF G_99.BLIF \ +state_machine_un1_clk_030_0_n.BLIF G_100.BLIF \ +state_machine_un17_clk_030_0_n.BLIF N_161.BLIF un1_as_030_2_0.BLIF N_114.BLIF \ +state_machine_as_030_000_sync_3_2_n.BLIF N_109.BLIF N_109_i.BLIF N_111.BLIF \ +un1_bg_030_0.BLIF N_112.BLIF N_111_i.BLIF N_122.BLIF N_122_i.BLIF N_115.BLIF \ +N_101.BLIF N_147_i.BLIF N_116.BLIF clk_cpu_est_11_0_3__n.BLIF N_124.BLIF \ +N_145_i.BLIF N_139.BLIF N_146_i.BLIF N_137.BLIF N_142_i.BLIF N_140.BLIF \ +clk_cpu_est_11_0_1__n.BLIF N_141.BLIF N_140_i.BLIF N_136.BLIF N_139_i.BLIF \ +N_142.BLIF N_141_i.BLIF N_145.BLIF N_138_i.BLIF N_138.BLIF N_137_i.BLIF \ +N_146.BLIF N_136_i.BLIF N_143.BLIF N_143_i.BLIF N_144.BLIF N_144_i.BLIF \ +UDS_000_INT_0_sqmuxa.BLIF N_134_i.BLIF UDS_000_INT_0_sqmuxa_1.BLIF \ +N_101_0.BLIF N_147.BLIF N_115_i.BLIF N_147_1.BLIF N_116_i.BLIF \ +state_machine_un13_clk_000_d_1_n.BLIF N_186.BLIF N_124_i.BLIF N_189.BLIF \ +state_machine_un42_clk_030_n.BLIF N_112_i.BLIF un1_bg_030.BLIF \ +sm_amiga_ns_0_0__n.BLIF state_machine_as_030_000_sync_3_n.BLIF N_86_i_1.BLIF \ +un1_as_030_2.BLIF un1_bg_030_0_1.BLIF state_machine_un17_clk_030_n.BLIF \ +un1_bg_030_0_2.BLIF state_machine_un1_clk_030_n.BLIF \ +state_machine_as_030_000_sync_3_2_1_n.BLIF state_machine_un4_bgack_000_n.BLIF \ +state_machine_un31_clk_000_d_i_1_n.BLIF N_108.BLIF N_186_1.BLIF \ +state_machine_un31_clk_000_d_n.BLIF N_186_2.BLIF \ +state_machine_un13_clk_000_d_n.BLIF N_186_3.BLIF \ +state_machine_un13_clk_000_d_4_n.BLIF N_186_4.BLIF \ +state_machine_un8_clk_000_d_n.BLIF N_186_5.BLIF DTACK_SYNC_1_sqmuxa.BLIF \ +N_186_6.BLIF VPA_SYNC_1_sqmuxa_1_0.BLIF N_189_1.BLIF VPA_SYNC_1_sqmuxa.BLIF \ +N_189_2.BLIF N_123.BLIF clk_cpu_est_11_0_1_1__n.BLIF N_118.BLIF \ +clk_cpu_est_11_0_2_1__n.BLIF N_110.BLIF clk_cpu_est_11_0_1_3__n.BLIF \ +N_102.BLIF N_143_1.BLIF N_120.BLIF N_144_1.BLIF N_119.BLIF N_106_1.BLIF \ +N_117.BLIF N_106_2.BLIF N_113.BLIF N_107_1.BLIF \ +state_machine_lds_000_int_8_n.BLIF UDS_000_INT_0_sqmuxa_1_1.BLIF \ +state_machine_uds_000_int_8_n.BLIF UDS_000_INT_0_sqmuxa_1_2.BLIF \ +DTACK_SYNC_1_sqmuxa_1.BLIF UDS_000_INT_0_sqmuxa_1_3.BLIF un2_clk_030_1.BLIF \ +UDS_000_INT_0_sqmuxa_1_0.BLIF VPA_SYNC_1_sqmuxa_1.BLIF \ +UDS_000_INT_0_sqmuxa_2.BLIF AS_000_INT_1_sqmuxa.BLIF \ +state_machine_un42_clk_030_1_n.BLIF VMA_INT_1_sqmuxa.BLIF \ +state_machine_un42_clk_030_2_n.BLIF DSACK_INT_1_sqmuxa.BLIF \ +state_machine_un42_clk_030_3_n.BLIF RW_i.BLIF \ +state_machine_un42_clk_030_4_n.BLIF clk_exp_i.BLIF \ +state_machine_un42_clk_030_5_n.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF \ +state_machine_un13_clk_000_d_1_0_n.BLIF N_114_i.BLIF \ +state_machine_un13_clk_000_d_4_1_n.BLIF VPA_SYNC_1_sqmuxa_i.BLIF \ +state_machine_un8_clk_000_d_1_n.BLIF N_110_i.BLIF \ +state_machine_un8_clk_000_d_2_n.BLIF N_108_i.BLIF \ +state_machine_un8_clk_000_d_3_n.BLIF cpu_est_d_i_3__n.BLIF \ +state_machine_un8_clk_000_d_4_n.BLIF cpu_est_d_i_0__n.BLIF \ +DTACK_SYNC_1_sqmuxa_1_0.BLIF CLK_000_D_i.BLIF VPA_SYNC_1_sqmuxa_1_1.BLIF \ +AS_030_i.BLIF VPA_SYNC_1_sqmuxa_2.BLIF AS_000_INT_i.BLIF \ +VPA_SYNC_1_sqmuxa_3.BLIF dsack_i_1__n.BLIF VPA_SYNC_1_sqmuxa_4.BLIF \ +state_machine_un13_clk_000_d_i_n.BLIF N_108_1.BLIF \ +state_machine_un8_clk_000_d_i_n.BLIF N_118_1.BLIF \ +state_machine_un13_clk_000_d_1_i_n.BLIF N_110_1.BLIF sm_amiga_i_1__n.BLIF \ +clk_exp_1.BLIF sm_amiga_i_2__n.BLIF sm_amiga_d_0_2__un3_n.BLIF \ +sm_amiga_i_0__n.BLIF sm_amiga_d_0_2__un1_n.BLIF sm_amiga_i_3__n.BLIF \ +sm_amiga_d_0_2__un0_n.BLIF VPA_D_i.BLIF dsack_int_0_1__un3_n.BLIF \ +VMA_INT_i.BLIF dsack_int_0_1__un1_n.BLIF DTACK_i.BLIF \ +dsack_int_0_1__un0_n.BLIF cpu_est_i_3__n.BLIF vma_int_0_un3_n.BLIF \ +a_i_18__n.BLIF vma_int_0_un1_n.BLIF a_i_16__n.BLIF vma_int_0_un0_n.BLIF \ +a_i_19__n.BLIF vpa_sync_0_un3_n.BLIF CLK_030_i.BLIF vpa_sync_0_un1_n.BLIF \ +state_machine_un42_clk_030_i_n.BLIF vpa_sync_0_un0_n.BLIF DS_030_i.BLIF \ +as_000_int_0_un3_n.BLIF cpu_est_i_1__n.BLIF as_000_int_0_un1_n.BLIF \ +AS_030_000_SYNC_i.BLIF as_000_int_0_un0_n.BLIF cpu_est_i_0__n.BLIF \ +dtack_sync_0_un3_n.BLIF sm_amiga_i_4__n.BLIF dtack_sync_0_un1_n.BLIF \ +sm_amiga_i_6__n.BLIF dtack_sync_0_un0_n.BLIF cpu_est_i_2__n.BLIF \ +lds_000_int_0_un3_n.BLIF UDS_000_INT_0_sqmuxa_1_i.BLIF \ +lds_000_int_0_un1_n.BLIF UDS_000_INT_0_sqmuxa_i.BLIF lds_000_int_0_un0_n.BLIF \ +sm_amiga_i_5__n.BLIF uds_000_int_0_un3_n.BLIF CLK_000_DD_i.BLIF \ +uds_000_int_0_un1_n.BLIF sm_amiga_i_7__n.BLIF uds_000_int_0_un0_n.BLIF \ +a_i_30__n.BLIF bg_000_0_un3_n.BLIF a_i_31__n.BLIF bg_000_0_un1_n.BLIF \ +a_i_28__n.BLIF bg_000_0_un0_n.BLIF a_i_29__n.BLIF as_030_000_sync_0_un3_n.BLIF \ +a_i_26__n.BLIF as_030_000_sync_0_un1_n.BLIF a_i_27__n.BLIF \ +as_030_000_sync_0_un0_n.BLIF a_i_24__n.BLIF fpu_cs_int_0_un3_n.BLIF \ +a_i_25__n.BLIF fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF \ +ipl_030_0_2__un3_n.BLIF RST_i.BLIF ipl_030_0_2__un1_n.BLIF N_107_i.BLIF \ +ipl_030_0_2__un0_n.BLIF N_106_i.BLIF ipl_030_0_1__un3_n.BLIF FPU_CS_INT_i.BLIF \ +ipl_030_0_1__un1_n.BLIF CPU_SPACE_i.BLIF ipl_030_0_1__un0_n.BLIF \ +BGACK_030_INT_i.BLIF ipl_030_0_0__un3_n.BLIF AS_030_c.BLIF \ +ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF bgack_030_int_0_un3_n.BLIF \ +DS_030_c.BLIF bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF \ +sm_amiga_d_0_0__un3_n.BLIF sm_amiga_d_0_0__un1_n.BLIF size_c_0__n.BLIF \ +sm_amiga_d_0_0__un0_n.BLIF sm_amiga_d_0_1__un3_n.BLIF size_c_1__n.BLIF \ +sm_amiga_d_0_1__un1_n.BLIF sm_amiga_d_0_1__un0_n.BLIF a_c_0__n.BLIF \ +cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF \ +cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF \ +cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF \ +a_15__n.BLIF a_14__n.BLIF a_13__n.BLIF a_12__n.BLIF a_c_16__n.BLIF \ +a_11__n.BLIF a_c_17__n.BLIF a_10__n.BLIF a_c_18__n.BLIF a_9__n.BLIF \ +a_c_19__n.BLIF a_8__n.BLIF a_c_20__n.BLIF a_7__n.BLIF a_c_21__n.BLIF \ +a_6__n.BLIF a_c_22__n.BLIF a_5__n.BLIF a_c_23__n.BLIF a_4__n.BLIF \ +a_c_24__n.BLIF a_3__n.BLIF a_c_25__n.BLIF a_2__n.BLIF a_c_26__n.BLIF \ +a_1__n.BLIF a_c_27__n.BLIF a_c_28__n.BLIF a_c_29__n.BLIF DSACK_1_.PIN.BLIF \ +DTACK.PIN.BLIF .outputs IPL_030_2_ AS_000 UDS_000 LDS_000 BERR BG_000 BGACK_030 CLK_DIV_OUT \ CLK_EXP FPU_CS AVEC AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR \ -AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_4_.D SM_AMIGA_4_.C \ -SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D \ -SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR \ -SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR cpu_est_0_.D cpu_est_0_.C \ +AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_6_.D SM_AMIGA_6_.C \ +SM_AMIGA_6_.AR SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D \ +SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR \ +SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C \ +SM_AMIGA_1_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR IPL_030DFFSH_1_reg.D \ +IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D \ +IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP cpu_est_0_.D cpu_est_0_.C \ cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_reg.D \ -cpu_est_3_reg.C SM_AMIGA_7_.D SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.D \ -SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR \ -CLK_000_CNT_0_.D CLK_000_CNT_0_.C CLK_000_CNT_1_.D CLK_000_CNT_1_.C \ -CLK_000_CNT_2_.D CLK_000_CNT_2_.C CLK_000_CNT_3_.D CLK_000_CNT_3_.C \ -SM_AMIGA_D_0_.D SM_AMIGA_D_0_.C SM_AMIGA_D_1_.D SM_AMIGA_D_1_.C \ -SM_AMIGA_D_2_.D SM_AMIGA_D_2_.C IPL_030DFFSH_0_reg.D IPL_030DFFSH_0_reg.C \ -IPL_030DFFSH_0_reg.AP IPL_030DFFSH_1_reg.D IPL_030DFFSH_1_reg.C \ -IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D IPL_030DFFSH_2_reg.C \ -IPL_030DFFSH_2_reg.AP inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \ -inst_AS_030_000_SYNC.AP inst_VPA_SYNC.D inst_VPA_SYNC.C inst_VPA_SYNC.AP \ -BG_000DFFSHreg.D BG_000DFFSHreg.C BG_000DFFSHreg.AP inst_AS_000_INTreg.D \ -inst_AS_000_INTreg.C inst_AS_000_INTreg.AP inst_VMA_INTreg.D inst_VMA_INTreg.C \ -inst_VMA_INTreg.AP inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C \ -inst_BGACK_030_INTreg.AP inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C DSACK_INT_1_.D \ -DSACK_INT_1_.C DSACK_INT_1_.AP inst_UDS_000_INTreg.D inst_UDS_000_INTreg.C \ -inst_UDS_000_INTreg.AP inst_LDS_000_INTreg.D inst_LDS_000_INTreg.C \ -inst_LDS_000_INTreg.AP inst_DTACK_SYNC.D inst_DTACK_SYNC.C inst_DTACK_SYNC.AP \ -inst_FPU_CS_INTreg.D inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP \ -inst_DTACK_DMA.D inst_DTACK_DMA.C inst_DTACK_DMA.AP CLK_CNT_0_.D CLK_CNT_0_.C \ -inst_RISING_CLK_AMIGA.D inst_RISING_CLK_AMIGA.C inst_VPA_D.D inst_VPA_D.C \ -inst_CLK_000_D.D inst_CLK_000_D.C RESETDFFreg.D RESETDFFreg.C \ -inst_CLK_000_DD.D inst_CLK_000_DD.C inst_CLK_OUT_INTreg.D \ -inst_CLK_OUT_INTreg.C DSACK_1_ DTACK DSACK_0_ a_15__n a_c_22__n a_14__n \ -a_c_23__n a_13__n a_c_24__n a_12__n a_c_25__n a_11__n a_c_26__n a_10__n \ -a_c_27__n gnd_n_n a_9__n a_c_28__n a_8__n a_c_29__n a_7__n a_c_30__n a_6__n \ -a_c_31__n a_5__n CPU_SPACE_c vcc_n_n a_4__n BG_030_c a_3__n a_2__n a_1__n \ -BGACK_000_c CLK_030_c CLK_000_c CLK_OSZI_c un1_clk_000_cnt_3__n \ -state_machine_un14_as_000_int_n ipl_c_0__n clk_exp ipl_c_1__n ipl_c_2__n \ -dsack_c_1__n DTACK_c RST_c RW_c fc_c_0__n fc_c_1__n N_123 N_148_i \ -clk_rising_clk_amiga_1_n N_147_i VMA_INT_1_sqmuxa_0 N_170_i N_171_i \ -DSACK_INT_1_sqmuxa N_161_i N_120 N_164_i N_144_1 N_165_i N_251 N_168_i N_254 \ -N_166_i N_186 N_167_i un1_clk_000_cnt_0__n N_169_i N_184 clk_cpu_est_11_0_1__n \ -un1_clk_000_cnt_1__n N_173_i un1_clk_000_cnt_2__n N_172_i \ -state_machine_un69_clk_000_d_n N_174_i state_machine_un78_clk_000_d_n \ -clk_cpu_est_11_0_3__n N_149 N_121_i N_119 N_126_0 N_135 N_123_0 \ -state_machine_un67_clk_000_d_n N_122_0 state_machine_un80_clk_000_d_n N_142_i \ -N_132 N_143_i N_131 sm_amiga_ns_0_5__n state_machine_un25_clk_000_d_n N_141_i \ -N_150 N_140_i N_151 sm_amiga_ns_0_4__n N_144 N_146 LDS_000_INT_1_sqmuxa_i \ -N_143 un1_UDS_000_INT_0_sqmuxa_2_0 N_145 UDS_000_INT_0_sqmuxa_i \ -state_machine_lds_000_int_8_n un1_UDS_000_INT_0_sqmuxa_i \ -un1_UDS_000_INT_0_sqmuxa_2 N_124_0 state_machine_uds_000_int_8_n N_136_i \ -LDS_000_INT_0_sqmuxa state_machine_un42_clk_030_n RISING_CLK_AMIGA_i \ -un1_bg_030 state_machine_un4_bgack_000_0_n N_133 BG_030_c_i \ -state_machine_as_030_000_sync_3_n state_machine_un1_clk_030_0_n N_125 \ -state_machine_un17_clk_030_0_n N_137 un1_as_030_2_0 N_138 N_137_i \ -DSACK_INT_1_sqmuxa_1 N_138_i un1_as_030_2 state_machine_un17_clk_030_n N_120_i \ -state_machine_un1_clk_030_n N_125_0 state_machine_un4_bgack_000_n \ -state_machine_as_030_000_sync_3_2_n VPA_SYNC_1_sqmuxa N_133_i \ -VPA_SYNC_1_sqmuxa_1 un1_bg_030_0 N_122 a_c_i_0__n AS_000_INT_1_sqmuxa \ -state_machine_uds_000_int_8_0_n N_136 state_machine_lds_000_int_8_0_n N_124 \ -N_151_i N_130 state_machine_un15_clk_000_d_n N_146_i un1_UDS_000_INT_0_sqmuxa \ -N_145_i UDS_000_INT_0_sqmuxa sm_amiga_ns_0_7__n LDS_000_INT_1_sqmuxa N_144_i \ -N_139 N_150_i N_140 N_126 size_c_i_1__n N_141 state_machine_un25_clk_000_d_i_n \ -N_121 state_machine_un80_clk_000_d_i_n N_142 state_machine_un67_clk_000_d_i_n \ -VPA_SYNC_1_sqmuxa_1_0 state_machine_un78_clk_000_d_0_n DTACK_SYNC_1_sqmuxa \ -clk_rising_clk_amiga_1_i_n DTACK_SYNC_1_sqmuxa_1 N_135_i N_149_2 N_104_i \ -clk_un3_clk_000_dd_n N_149_i N_164 N_119_0 N_171 clk_000_cnt_i_1__n N_170 \ -clk_000_cnt_i_0__n clk_cpu_est_11_3__n clk_000_cnt_i_3__n N_174 \ -clk_000_cnt_i_2__n N_172 state_machine_un69_clk_000_d_0_n N_173 \ -state_machine_un69_clk_000_d_0_1_n clk_cpu_est_11_1__n \ -state_machine_un69_clk_000_d_0_2_n N_169 state_machine_un25_clk_000_d_i_1_n \ -N_167 N_116_i_1 N_166 un1_bg_030_0_1 N_168 un1_bg_030_0_2 N_165 \ -state_machine_as_030_000_sync_3_2_1_n VMA_INT_1_sqmuxa \ -un1_UDS_000_INT_0_sqmuxa_i_1 N_147 clk_cpu_est_11_0_1_3__n N_148 \ -clk_cpu_est_11_0_1_1__n RW_i clk_cpu_est_11_0_2_1__n clk_exp_i N_251_1 \ -CLK_000_DD_i N_251_2 CLK_000_D_i N_251_3 AS_000_INT_i N_251_4 cpu_est_i_0__n \ -N_251_5 cpu_est_i_2__n N_251_6 cpu_est_i_3__n N_254_1 cpu_est_i_1__n N_254_2 \ -N_149_2_i DSACK_INT_1_sqmuxa_1_0 VPA_D_i DSACK_INT_1_sqmuxa_2 DTACK_i \ -DSACK_INT_1_sqmuxa_3 VPA_SYNC_i N_149_1 DTACK_SYNC_i N_149_2_0 AS_030_i \ -N_132_1 DTACK_SYNC_1_sqmuxa_i N_131_1 DS_030_i state_machine_un42_clk_030_1_n \ -sm_amiga_i_4__n state_machine_un42_clk_030_2_n sm_amiga_i_6__n \ -state_machine_un42_clk_030_3_n sm_amiga_i_5__n state_machine_un42_clk_030_4_n \ -N_139_i state_machine_un42_clk_030_5_n state_machine_un15_clk_000_d_i_n \ -N_142_1 N_130_i N_130_1 sm_amiga_i_0__n N_130_2 sm_amiga_i_7__n \ -UDS_000_INT_0_sqmuxa_1 VPA_SYNC_1_sqmuxa_i UDS_000_INT_0_sqmuxa_2 dsack_i_1__n \ -DTACK_SYNC_1_sqmuxa_1_0 DSACK_INT_1_sqmuxa_i VPA_SYNC_1_sqmuxa_1_1 a_i_18__n \ -VPA_SYNC_1_sqmuxa_2 a_i_16__n VPA_SYNC_1_sqmuxa_3 a_i_19__n N_171_1 CLK_030_i \ -N_170_1 state_machine_un42_clk_030_i_n N_174_1 AS_030_000_SYNC_i clk_exp_1 \ -N_131_i cpu_est_0_1__un3_n N_132_i cpu_est_0_1__un1_n sm_amiga_i_2__n \ -cpu_est_0_1__un0_n sm_amiga_i_1__n vma_int_0_un3_n sm_amiga_i_3__n \ -vma_int_0_un1_n CLK_000_i vma_int_0_un0_n a_i_30__n cpu_est_0_3__un3_n \ -a_i_31__n cpu_est_0_3__un1_n a_i_28__n cpu_est_0_3__un0_n a_i_29__n \ -cpu_est_0_2__un3_n a_i_26__n cpu_est_0_2__un1_n a_i_27__n cpu_est_0_2__un0_n \ -a_i_24__n dtack_sync_0_un3_n a_i_25__n dtack_sync_0_un1_n dtack_sync_0_un0_n \ -sm_amiga_d_0_0__un3_n RST_i sm_amiga_d_0_0__un1_n sm_amiga_d_0_0__un0_n \ -FPU_CS_INT_i bgack_030_int_0_un3_n CPU_SPACE_i bgack_030_int_0_un1_n \ -BGACK_030_INT_i bgack_030_int_0_un0_n AS_030_c bg_000_0_un3_n bg_000_0_un1_n \ -bg_000_0_un0_n DS_030_c as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n \ -as_030_000_sync_0_un0_n fpu_cs_int_0_un3_n size_c_0__n fpu_cs_int_0_un1_n \ -fpu_cs_int_0_un0_n size_c_1__n dsack_int_0_1__un3_n dsack_int_0_1__un1_n \ -a_c_0__n dsack_int_0_1__un0_n vpa_sync_0_un3_n vpa_sync_0_un1_n \ -vpa_sync_0_un0_n as_000_int_0_un3_n as_000_int_0_un1_n as_000_int_0_un0_n \ -ipl_030_0_2__un3_n ipl_030_0_2__un1_n ipl_030_0_2__un0_n ipl_030_0_1__un3_n \ -ipl_030_0_1__un1_n ipl_030_0_1__un0_n ipl_030_0_0__un3_n ipl_030_0_0__un1_n \ -ipl_030_0_0__un0_n sm_amiga_d_0_2__un3_n a_c_16__n sm_amiga_d_0_2__un1_n \ -sm_amiga_d_0_2__un0_n a_c_17__n sm_amiga_d_0_1__un3_n sm_amiga_d_0_1__un1_n \ -a_c_18__n sm_amiga_d_0_1__un0_n lds_000_int_0_un3_n a_c_19__n \ -lds_000_int_0_un1_n lds_000_int_0_un0_n a_c_20__n uds_000_int_0_un3_n \ -uds_000_int_0_un1_n a_c_21__n uds_000_int_0_un0_n DSACK_1_.OE DTACK.OE \ -AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE G_128 \ -G_130 G_132 cpu_est_0_0_ CLK_OUT_PRE_0 G_122 G_123 G_124 -.names CLK_000_D_i.BLIF N_151_i.BLIF SM_AMIGA_4_.D +cpu_est_3_reg.C SM_AMIGA_7_.D SM_AMIGA_7_.C SM_AMIGA_7_.AP cpu_est_d_0_.D \ +cpu_est_d_0_.C cpu_est_d_1_.D cpu_est_d_1_.C cpu_est_d_2_.D cpu_est_d_2_.C \ +cpu_est_d_3_.D cpu_est_d_3_.C SM_AMIGA_D_0_.D SM_AMIGA_D_0_.C SM_AMIGA_D_1_.D \ +SM_AMIGA_D_1_.C SM_AMIGA_D_2_.D SM_AMIGA_D_2_.C IPL_030DFFSH_0_reg.D \ +IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP inst_AS_000_INTreg.D \ +inst_AS_000_INTreg.C inst_AS_000_INTreg.AP inst_VPA_SYNC.D inst_VPA_SYNC.C \ +inst_VPA_SYNC.AP inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \ +inst_AS_030_000_SYNC.AP inst_VMA_INTreg.D inst_VMA_INTreg.C inst_VMA_INTreg.AP \ +BG_000DFFSHreg.D BG_000DFFSHreg.C BG_000DFFSHreg.AP DSACK_INT_1_.D \ +DSACK_INT_1_.C DSACK_INT_1_.AP inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C \ +inst_BGACK_030_INTreg.AP inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C \ +inst_UDS_000_INTreg.D inst_UDS_000_INTreg.C inst_UDS_000_INTreg.AP \ +inst_LDS_000_INTreg.D inst_LDS_000_INTreg.C inst_LDS_000_INTreg.AP \ +inst_DTACK_SYNC.D inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_FPU_CS_INTreg.D \ +inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP inst_DTACK_DMA.D inst_DTACK_DMA.C \ +inst_DTACK_DMA.AP inst_RISING_CLK_AMIGA.D inst_RISING_CLK_AMIGA.C CLK_CNT_0_.D \ +CLK_CNT_0_.C inst_VPA_D.D inst_VPA_D.C inst_CLK_000_D.D inst_CLK_000_D.C \ +RESETDFFreg.D RESETDFFreg.C inst_CLK_000_DD.D inst_CLK_000_DD.C \ +inst_CLK_OUT_INTreg.D inst_CLK_OUT_INTreg.C DSACK_1_ DTACK DSACK_0_ a_c_30__n \ +a_c_31__n CPU_SPACE_c BG_030_c gnd_n_n BGACK_000_c CLK_030_c CLK_000_c \ +CLK_OSZI_c vcc_n_n ipl_c_0__n ipl_c_1__n ipl_c_2__n \ +state_machine_un57_clk_000_d_n dsack_c_1__n DTACK_c \ +state_machine_un13_as_000_int_n RST_c clk_exp RW_c fc_c_0__n fc_c_1__n \ +state_machine_un57_clk_000_d_0_n N_161_i a_c_i_0__n \ +state_machine_uds_000_int_8_0_n state_machine_lds_000_int_8_0_n N_113_i \ +sm_amiga_ns_0_2__n N_118_i N_117_i sm_amiga_ns_0_5__n N_123_i N_119_i N_120_i \ +sm_amiga_ns_0_7__n CLK_OUT_PRE_i N_106 N_102_0 N_107 size_c_i_1__n \ +clk_un3_clk_000_dd_n state_machine_un31_clk_000_d_i_n clk_cpu_est_11_1__n \ +RISING_CLK_AMIGA_i clk_cpu_est_11_3__n state_machine_un4_bgack_000_0_n \ +BG_030_c_i state_machine_un1_clk_030_0_n state_machine_un17_clk_030_0_n N_161 \ +un1_as_030_2_0 N_114 state_machine_as_030_000_sync_3_2_n N_109 N_109_i N_111 \ +un1_bg_030_0 N_112 N_111_i N_122 N_122_i N_115 N_101 N_147_i N_116 \ +clk_cpu_est_11_0_3__n N_124 N_145_i N_139 N_146_i N_137 N_142_i N_140 \ +clk_cpu_est_11_0_1__n N_141 N_140_i N_136 N_139_i N_142 N_141_i N_145 N_138_i \ +N_138 N_137_i N_146 N_136_i N_143 N_143_i N_144 N_144_i UDS_000_INT_0_sqmuxa \ +N_134_i UDS_000_INT_0_sqmuxa_1 N_101_0 N_147 N_115_i N_147_1 N_116_i \ +state_machine_un13_clk_000_d_1_n N_186 N_124_i N_189 \ +state_machine_un42_clk_030_n N_112_i un1_bg_030 sm_amiga_ns_0_0__n \ +state_machine_as_030_000_sync_3_n N_86_i_1 un1_as_030_2 un1_bg_030_0_1 \ +state_machine_un17_clk_030_n un1_bg_030_0_2 state_machine_un1_clk_030_n \ +state_machine_as_030_000_sync_3_2_1_n state_machine_un4_bgack_000_n \ +state_machine_un31_clk_000_d_i_1_n N_108 N_186_1 \ +state_machine_un31_clk_000_d_n N_186_2 state_machine_un13_clk_000_d_n N_186_3 \ +state_machine_un13_clk_000_d_4_n N_186_4 state_machine_un8_clk_000_d_n N_186_5 \ +DTACK_SYNC_1_sqmuxa N_186_6 VPA_SYNC_1_sqmuxa_1_0 N_189_1 VPA_SYNC_1_sqmuxa \ +N_189_2 N_123 clk_cpu_est_11_0_1_1__n N_118 clk_cpu_est_11_0_2_1__n N_110 \ +clk_cpu_est_11_0_1_3__n N_102 N_143_1 N_120 N_144_1 N_119 N_106_1 N_117 \ +N_106_2 N_113 N_107_1 state_machine_lds_000_int_8_n UDS_000_INT_0_sqmuxa_1_1 \ +state_machine_uds_000_int_8_n UDS_000_INT_0_sqmuxa_1_2 DTACK_SYNC_1_sqmuxa_1 \ +UDS_000_INT_0_sqmuxa_1_3 un2_clk_030_1 UDS_000_INT_0_sqmuxa_1_0 \ +VPA_SYNC_1_sqmuxa_1 UDS_000_INT_0_sqmuxa_2 AS_000_INT_1_sqmuxa \ +state_machine_un42_clk_030_1_n VMA_INT_1_sqmuxa state_machine_un42_clk_030_2_n \ +DSACK_INT_1_sqmuxa state_machine_un42_clk_030_3_n RW_i \ +state_machine_un42_clk_030_4_n clk_exp_i state_machine_un42_clk_030_5_n \ +DTACK_SYNC_1_sqmuxa_i state_machine_un13_clk_000_d_1_0_n N_114_i \ +state_machine_un13_clk_000_d_4_1_n VPA_SYNC_1_sqmuxa_i \ +state_machine_un8_clk_000_d_1_n N_110_i state_machine_un8_clk_000_d_2_n \ +N_108_i state_machine_un8_clk_000_d_3_n cpu_est_d_i_3__n \ +state_machine_un8_clk_000_d_4_n cpu_est_d_i_0__n DTACK_SYNC_1_sqmuxa_1_0 \ +CLK_000_D_i VPA_SYNC_1_sqmuxa_1_1 AS_030_i VPA_SYNC_1_sqmuxa_2 AS_000_INT_i \ +VPA_SYNC_1_sqmuxa_3 dsack_i_1__n VPA_SYNC_1_sqmuxa_4 \ +state_machine_un13_clk_000_d_i_n N_108_1 state_machine_un8_clk_000_d_i_n \ +N_118_1 state_machine_un13_clk_000_d_1_i_n N_110_1 sm_amiga_i_1__n clk_exp_1 \ +sm_amiga_i_2__n sm_amiga_d_0_2__un3_n sm_amiga_i_0__n sm_amiga_d_0_2__un1_n \ +sm_amiga_i_3__n sm_amiga_d_0_2__un0_n VPA_D_i dsack_int_0_1__un3_n VMA_INT_i \ +dsack_int_0_1__un1_n DTACK_i dsack_int_0_1__un0_n cpu_est_i_3__n \ +vma_int_0_un3_n a_i_18__n vma_int_0_un1_n a_i_16__n vma_int_0_un0_n a_i_19__n \ +vpa_sync_0_un3_n CLK_030_i vpa_sync_0_un1_n state_machine_un42_clk_030_i_n \ +vpa_sync_0_un0_n DS_030_i as_000_int_0_un3_n cpu_est_i_1__n as_000_int_0_un1_n \ +AS_030_000_SYNC_i as_000_int_0_un0_n cpu_est_i_0__n dtack_sync_0_un3_n \ +sm_amiga_i_4__n dtack_sync_0_un1_n sm_amiga_i_6__n dtack_sync_0_un0_n \ +cpu_est_i_2__n lds_000_int_0_un3_n UDS_000_INT_0_sqmuxa_1_i \ +lds_000_int_0_un1_n UDS_000_INT_0_sqmuxa_i lds_000_int_0_un0_n sm_amiga_i_5__n \ +uds_000_int_0_un3_n CLK_000_DD_i uds_000_int_0_un1_n sm_amiga_i_7__n \ +uds_000_int_0_un0_n a_i_30__n bg_000_0_un3_n a_i_31__n bg_000_0_un1_n \ +a_i_28__n bg_000_0_un0_n a_i_29__n as_030_000_sync_0_un3_n a_i_26__n \ +as_030_000_sync_0_un1_n a_i_27__n as_030_000_sync_0_un0_n a_i_24__n \ +fpu_cs_int_0_un3_n a_i_25__n fpu_cs_int_0_un1_n fpu_cs_int_0_un0_n \ +ipl_030_0_2__un3_n RST_i ipl_030_0_2__un1_n N_107_i ipl_030_0_2__un0_n N_106_i \ +ipl_030_0_1__un3_n FPU_CS_INT_i ipl_030_0_1__un1_n CPU_SPACE_i \ +ipl_030_0_1__un0_n BGACK_030_INT_i ipl_030_0_0__un3_n AS_030_c \ +ipl_030_0_0__un1_n ipl_030_0_0__un0_n bgack_030_int_0_un3_n DS_030_c \ +bgack_030_int_0_un1_n bgack_030_int_0_un0_n sm_amiga_d_0_0__un3_n \ +sm_amiga_d_0_0__un1_n size_c_0__n sm_amiga_d_0_0__un0_n sm_amiga_d_0_1__un3_n \ +size_c_1__n sm_amiga_d_0_1__un1_n sm_amiga_d_0_1__un0_n a_c_0__n \ +cpu_est_0_1__un3_n cpu_est_0_1__un1_n cpu_est_0_1__un0_n cpu_est_0_2__un3_n \ +cpu_est_0_2__un1_n cpu_est_0_2__un0_n cpu_est_0_3__un3_n cpu_est_0_3__un1_n \ +cpu_est_0_3__un0_n a_15__n a_14__n a_13__n a_12__n a_c_16__n a_11__n a_c_17__n \ +a_10__n a_c_18__n a_9__n a_c_19__n a_8__n a_c_20__n a_7__n a_c_21__n a_6__n \ +a_c_22__n a_5__n a_c_23__n a_4__n a_c_24__n a_3__n a_c_25__n a_2__n a_c_26__n \ +a_1__n a_c_27__n a_c_28__n a_c_29__n DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE \ +LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE cpu_est_0_0_ CLK_OUT_PRE_0 \ +G_98 G_99 G_100 +.names N_86_i_1.BLIF N_122_i.BLIF SM_AMIGA_6_.D 11 1 -.names sm_amiga_ns_0_4__n.BLIF SM_AMIGA_3_.D +.names sm_amiga_ns_0_2__n.BLIF SM_AMIGA_5_.D 0 1 +.names CLK_000_D_i.BLIF N_124_i.BLIF SM_AMIGA_4_.D +11 1 +.names N_115_i.BLIF N_116_i.BLIF SM_AMIGA_3_.D +11 1 .names sm_amiga_ns_0_5__n.BLIF SM_AMIGA_2_.D 0 1 -.names N_116_i_1.BLIF N_150_i.BLIF SM_AMIGA_1_.D +.names N_119_i.BLIF N_123_i.BLIF SM_AMIGA_1_.D 11 1 .names sm_amiga_ns_0_7__n.BLIF SM_AMIGA_0_.D 0 1 +.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF IPL_030DFFSH_1_reg.D +1- 1 +-1 1 +.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF IPL_030DFFSH_2_reg.D +1- 1 +-1 1 .names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D 1- 1 -1 1 @@ -346,13 +344,7 @@ G_130 G_132 cpu_est_0_0_ CLK_OUT_PRE_0 G_122 G_123 G_124 .names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_reg.D 1- 1 -1 1 -.names inst_CLK_000_D.BLIF N_136_i.BLIF SM_AMIGA_7_.D -11 1 -.names N_137_i.BLIF N_138_i.BLIF SM_AMIGA_6_.D -11 1 -.names inst_CLK_000_D.BLIF N_139_i.BLIF SM_AMIGA_5_.D -11 1 -.names un1_clk_000_cnt_3__n.BLIF CLK_000_CNT_0_.D +.names sm_amiga_ns_0_0__n.BLIF SM_AMIGA_7_.D 0 1 .names sm_amiga_d_0_0__un1_n.BLIF sm_amiga_d_0_0__un0_n.BLIF SM_AMIGA_D_0_.D 1- 1 @@ -366,35 +358,29 @@ G_130 G_132 cpu_est_0_0_ CLK_OUT_PRE_0 G_122 G_123 G_124 .names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF IPL_030DFFSH_0_reg.D 1- 1 -1 1 -.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF IPL_030DFFSH_1_reg.D +.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF inst_AS_000_INTreg.D 1- 1 -1 1 -.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF IPL_030DFFSH_2_reg.D +.names vpa_sync_0_un1_n.BLIF vpa_sync_0_un0_n.BLIF inst_VPA_SYNC.D 1- 1 -1 1 .names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF \ inst_AS_030_000_SYNC.D 1- 1 -1 1 -.names vpa_sync_0_un1_n.BLIF vpa_sync_0_un0_n.BLIF inst_VPA_SYNC.D +.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D 1- 1 -1 1 .names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF BG_000DFFSHreg.D 1- 1 -1 1 -.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF inst_AS_000_INTreg.D -1- 1 --1 1 -.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D +.names dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF DSACK_INT_1_.D 1- 1 -1 1 .names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF \ inst_BGACK_030_INTreg.D 1- 1 -1 1 -.names dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF DSACK_INT_1_.D -1- 1 --1 1 .names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INTreg.D 1- 1 -1 1 @@ -407,663 +393,600 @@ inst_BGACK_030_INTreg.D .names fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF inst_FPU_CS_INTreg.D 1- 1 -1 1 -.names state_machine_un14_as_000_int_n.BLIF inst_DTACK_DMA.D +.names state_machine_un13_as_000_int_n.BLIF inst_DTACK_DMA.D 0 1 +.names CLK_000_D_i.BLIF CLK_000_c.BLIF inst_RISING_CLK_AMIGA.D +11 1 .names CLK_CNT_0_.BLIF CLK_CNT_0_.D 0 1 .names gnd_n_n .names vcc_n_n 1 -.names CLK_000_CNT_0_.BLIF N_104_i.BLIF un1_clk_000_cnt_3__n -11 1 -.names AS_000_INT_i.BLIF dsack_i_1__n.BLIF state_machine_un14_as_000_int_n -11 1 -.names clk_exp_1.BLIF G_123.BLIF clk_exp -11 1 -.names N_123_0.BLIF N_123 +.names state_machine_un57_clk_000_d_0_n.BLIF state_machine_un57_clk_000_d_n 0 1 -.names N_148.BLIF N_148_i +.names AS_000_INT_i.BLIF dsack_i_1__n.BLIF state_machine_un13_as_000_int_n +11 1 +.names clk_exp_1.BLIF G_99.BLIF clk_exp +11 1 +.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF \ +state_machine_un57_clk_000_d_0_n +11 1 +.names N_161.BLIF N_161_i 0 1 -.names CLK_000_D_i.BLIF CLK_000_c.BLIF clk_rising_clk_amiga_1_n -11 1 -.names N_147.BLIF N_147_i +.names a_c_0__n.BLIF a_c_i_0__n 0 1 -.names N_147_i.BLIF N_148_i.BLIF VMA_INT_1_sqmuxa_0 +.names a_c_i_0__n.BLIF N_161_i.BLIF state_machine_uds_000_int_8_0_n 11 1 -.names N_170.BLIF N_170_i +.names N_161_i.BLIF state_machine_un31_clk_000_d_n.BLIF \ +state_machine_lds_000_int_8_0_n +11 1 +.names N_113.BLIF N_113_i 0 1 -.names N_171.BLIF N_171_i +.names N_113_i.BLIF N_114_i.BLIF sm_amiga_ns_0_2__n +11 1 +.names N_118.BLIF N_118_i 0 1 -.names DSACK_INT_1_sqmuxa_3.BLIF state_machine_un78_clk_000_d_n.BLIF \ -DSACK_INT_1_sqmuxa -11 1 -.names N_170_i.BLIF N_171_i.BLIF N_161_i -11 1 -.names N_120_i.BLIF N_120 +.names N_117.BLIF N_117_i 0 1 -.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF N_164_i +.names N_117_i.BLIF N_118_i.BLIF sm_amiga_ns_0_5__n 11 1 -.names CLK_000_i.BLIF N_119.BLIF N_144_1 -11 1 -.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_165_i -11 1 -.names N_251_5.BLIF N_251_6.BLIF N_251 -11 1 -.names N_168.BLIF N_168_i +.names N_123.BLIF N_123_i 0 1 -.names N_254_1.BLIF N_254_2.BLIF N_254 -11 1 -.names N_166.BLIF N_166_i +.names N_119.BLIF N_119_i 0 1 -.names CLK_000_CNT_2_.BLIF N_184.BLIF N_186 -11 1 -.names N_167.BLIF N_167_i +.names N_120.BLIF N_120_i 0 1 -.names CLK_000_CNT_3_.BLIF N_104_i.BLIF un1_clk_000_cnt_0__n +.names N_110_i.BLIF N_120_i.BLIF sm_amiga_ns_0_7__n 11 1 -.names N_169.BLIF N_169_i +.names inst_CLK_OUT_PRE.BLIF CLK_OUT_PRE_i 0 1 -.names CLK_000_CNT_1_.BLIF un1_clk_000_cnt_3__n.BLIF N_184 +.names N_106_1.BLIF N_106_2.BLIF N_106 11 1 -.names clk_cpu_est_11_0_1_1__n.BLIF clk_cpu_est_11_0_2_1__n.BLIF \ -clk_cpu_est_11_0_1__n +.names CLK_OUT_PRE_i.BLIF SM_AMIGA_1_.BLIF N_102_0 11 1 -.names CLK_000_CNT_2_.BLIF N_104_i.BLIF un1_clk_000_cnt_1__n +.names N_107_1.BLIF sm_amiga_i_1__n.BLIF N_107 11 1 -.names N_173.BLIF N_173_i +.names size_c_1__n.BLIF size_c_i_1__n 0 1 -.names CLK_000_CNT_1_.BLIF N_104_i.BLIF un1_clk_000_cnt_2__n +.names inst_CLK_000_D.BLIF CLK_000_DD_i.BLIF clk_un3_clk_000_dd_n 11 1 -.names N_172.BLIF N_172_i +.names state_machine_un31_clk_000_d_i_1_n.BLIF size_c_i_1__n.BLIF \ +state_machine_un31_clk_000_d_i_n +11 1 +.names clk_cpu_est_11_0_1__n.BLIF clk_cpu_est_11_1__n 0 1 -.names state_machine_un69_clk_000_d_0_n.BLIF state_machine_un69_clk_000_d_n -0 1 -.names N_174.BLIF N_174_i -0 1 -.names state_machine_un78_clk_000_d_0_n.BLIF state_machine_un78_clk_000_d_n -0 1 -.names clk_cpu_est_11_0_1_3__n.BLIF N_173_i.BLIF clk_cpu_est_11_0_3__n -11 1 -.names N_149_1.BLIF N_149_2_0.BLIF N_149 -11 1 -.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF N_121_i -11 1 -.names N_119_0.BLIF N_119 -0 1 -.names sm_amiga_i_3__n.BLIF sm_amiga_i_4__n.BLIF N_126_0 -11 1 -.names inst_CLK_000_D.BLIF CLK_000_i.BLIF N_135 -11 1 -.names inst_AS_000_INTreg.BLIF inst_CLK_000_D.BLIF N_123_0 -11 1 -.names DTACK_SYNC_i.BLIF state_machine_un69_clk_000_d_n.BLIF \ -state_machine_un67_clk_000_d_n -11 1 -.names inst_CLK_000_D.BLIF N_120_i.BLIF N_122_0 -11 1 -.names VPA_SYNC_i.BLIF state_machine_un69_clk_000_d_n.BLIF \ -state_machine_un80_clk_000_d_n -11 1 -.names N_142.BLIF N_142_i -0 1 -.names N_132_1.BLIF sm_amiga_i_3__n.BLIF N_132 -11 1 -.names N_143.BLIF N_143_i -0 1 -.names N_131_1.BLIF sm_amiga_i_1__n.BLIF N_131 -11 1 -.names N_142_i.BLIF N_143_i.BLIF sm_amiga_ns_0_5__n -11 1 -.names state_machine_un25_clk_000_d_i_n.BLIF state_machine_un25_clk_000_d_n -0 1 -.names N_141.BLIF N_141_i -0 1 -.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_150 -11 1 -.names N_140.BLIF N_140_i -0 1 -.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_151 -11 1 -.names N_140_i.BLIF N_141_i.BLIF sm_amiga_ns_0_4__n -11 1 -.names N_144_1.BLIF sm_amiga_i_2__n.BLIF N_144 -11 1 -.names N_144_1.BLIF SM_AMIGA_1_.BLIF N_146 -11 1 -.names LDS_000_INT_1_sqmuxa.BLIF LDS_000_INT_1_sqmuxa_i -0 1 -.names CLK_000_D_i.BLIF SM_AMIGA_2_.BLIF N_143 -11 1 -.names LDS_000_INT_1_sqmuxa_i.BLIF un1_UDS_000_INT_0_sqmuxa.BLIF \ -un1_UDS_000_INT_0_sqmuxa_2_0 -11 1 -.names N_123.BLIF SM_AMIGA_0_.BLIF N_145 -11 1 -.names UDS_000_INT_0_sqmuxa.BLIF UDS_000_INT_0_sqmuxa_i -0 1 -.names state_machine_lds_000_int_8_0_n.BLIF state_machine_lds_000_int_8_n -0 1 -.names un1_UDS_000_INT_0_sqmuxa_i_1.BLIF UDS_000_INT_0_sqmuxa_i.BLIF \ -un1_UDS_000_INT_0_sqmuxa_i -11 1 -.names un1_UDS_000_INT_0_sqmuxa_2_0.BLIF un1_UDS_000_INT_0_sqmuxa_2 -0 1 -.names inst_AS_000_INTreg.BLIF SM_AMIGA_0_.BLIF N_124_0 -11 1 -.names state_machine_uds_000_int_8_0_n.BLIF state_machine_uds_000_int_8_n -0 1 -.names N_136.BLIF N_136_i -0 1 -.names AS_030_i.BLIF un1_UDS_000_INT_0_sqmuxa_2.BLIF LDS_000_INT_0_sqmuxa -11 1 -.names state_machine_un42_clk_030_4_n.BLIF state_machine_un42_clk_030_5_n.BLIF \ -state_machine_un42_clk_030_n -11 1 .names inst_RISING_CLK_AMIGA.BLIF RISING_CLK_AMIGA_i 0 1 -.names un1_bg_030_0.BLIF un1_bg_030 +.names clk_cpu_est_11_0_3__n.BLIF clk_cpu_est_11_3__n 0 1 .names BGACK_000_c.BLIF RISING_CLK_AMIGA_i.BLIF \ state_machine_un4_bgack_000_0_n 11 1 -.names sm_amiga_i_6__n.BLIF sm_amiga_i_7__n.BLIF N_133 -11 1 .names BG_030_c.BLIF BG_030_c_i 0 1 -.names state_machine_as_030_000_sync_3_2_n.BLIF \ -state_machine_as_030_000_sync_3_n -0 1 .names BG_030_c_i.BLIF CLK_030_c.BLIF state_machine_un1_clk_030_0_n 11 1 -.names N_125_0.BLIF N_125 -0 1 .names AS_030_i.BLIF CLK_030_i.BLIF state_machine_un17_clk_030_0_n 11 1 -.names N_125.BLIF sm_amiga_i_6__n.BLIF N_137 +.names UDS_000_INT_0_sqmuxa_1_i.BLIF UDS_000_INT_0_sqmuxa_i.BLIF N_161 11 1 .names AS_030_i.BLIF state_machine_un42_clk_030_n.BLIF un1_as_030_2_0 11 1 -.names AS_030_000_SYNC_i.BLIF inst_CLK_000_D.BLIF N_138 +.names N_122.BLIF SM_AMIGA_6_.BLIF N_114 11 1 -.names N_137.BLIF N_137_i -0 1 -.names AS_030_i.BLIF DSACK_INT_1_sqmuxa_i.BLIF DSACK_INT_1_sqmuxa_1 -11 1 -.names N_138.BLIF N_138_i -0 1 -.names un1_as_030_2_0.BLIF un1_as_030_2 -0 1 -.names state_machine_un17_clk_030_0_n.BLIF state_machine_un17_clk_030_n -0 1 -.names AS_030_000_SYNC_i.BLIF SM_AMIGA_6_.BLIF N_120_i -11 1 -.names state_machine_un1_clk_030_0_n.BLIF state_machine_un1_clk_030_n -0 1 -.names CLK_000_D_i.BLIF SM_AMIGA_7_.BLIF N_125_0 -11 1 -.names state_machine_un4_bgack_000_0_n.BLIF state_machine_un4_bgack_000_n -0 1 .names state_machine_as_030_000_sync_3_2_1_n.BLIF \ state_machine_un42_clk_030_i_n.BLIF state_machine_as_030_000_sync_3_2_n 11 1 -.names VPA_SYNC_1_sqmuxa_3.BLIF cpu_est_2_.BLIF VPA_SYNC_1_sqmuxa +.names sm_amiga_i_6__n.BLIF sm_amiga_i_7__n.BLIF N_109 11 1 -.names N_133.BLIF N_133_i +.names N_109.BLIF N_109_i 0 1 -.names AS_030_i.BLIF VPA_SYNC_1_sqmuxa_i.BLIF VPA_SYNC_1_sqmuxa_1 +.names inst_CLK_000_D.BLIF SM_AMIGA_7_.BLIF N_111 11 1 .names un1_bg_030_0_1.BLIF un1_bg_030_0_2.BLIF un1_bg_030_0 11 1 -.names N_122_0.BLIF N_122 +.names SM_AMIGA_0_.BLIF state_machine_un13_clk_000_d_1_n.BLIF N_112 +11 1 +.names N_111.BLIF N_111_i 0 1 -.names a_c_0__n.BLIF a_c_i_0__n +.names AS_030_000_SYNC_i.BLIF clk_un3_clk_000_dd_n.BLIF N_122 +11 1 +.names N_122.BLIF N_122_i 0 1 -.names AS_030_i.BLIF N_122.BLIF AS_000_INT_1_sqmuxa +.names CLK_000_D_i.BLIF N_101.BLIF N_115 11 1 -.names a_c_i_0__n.BLIF un1_UDS_000_INT_0_sqmuxa_2_0.BLIF \ -state_machine_uds_000_int_8_0_n -11 1 -.names N_124.BLIF sm_amiga_i_7__n.BLIF N_136 -11 1 -.names state_machine_un25_clk_000_d_n.BLIF un1_UDS_000_INT_0_sqmuxa_2_0.BLIF \ -state_machine_lds_000_int_8_0_n -11 1 -.names N_124_0.BLIF N_124 +.names N_101_0.BLIF N_101 0 1 -.names N_151.BLIF N_151_i +.names N_147.BLIF N_147_i 0 1 -.names N_130_1.BLIF N_130_2.BLIF N_130 +.names sm_amiga_i_3__n.BLIF sm_amiga_i_4__n.BLIF N_116 11 1 -.names DS_030_i.BLIF RW_c.BLIF state_machine_un15_clk_000_d_n +.names clk_cpu_est_11_0_1_3__n.BLIF N_146_i.BLIF clk_cpu_est_11_0_3__n +11 1 +.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_124 +11 1 +.names N_145.BLIF N_145_i +0 1 +.names N_137.BLIF cpu_est_i_0__n.BLIF N_139 11 1 .names N_146.BLIF N_146_i 0 1 -.names un1_UDS_000_INT_0_sqmuxa_i.BLIF un1_UDS_000_INT_0_sqmuxa +.names N_137_i.BLIF N_137 0 1 -.names N_145.BLIF N_145_i +.names N_142.BLIF N_142_i 0 1 -.names UDS_000_INT_0_sqmuxa_1.BLIF UDS_000_INT_0_sqmuxa_2.BLIF \ -UDS_000_INT_0_sqmuxa +.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_140 11 1 -.names N_145_i.BLIF N_146_i.BLIF sm_amiga_ns_0_7__n +.names clk_cpu_est_11_0_1_1__n.BLIF clk_cpu_est_11_0_2_1__n.BLIF \ +clk_cpu_est_11_0_1__n 11 1 -.names N_139_i.BLIF state_machine_un15_clk_000_d_i_n.BLIF LDS_000_INT_1_sqmuxa +.names N_137_i.BLIF cpu_est_0_.BLIF N_141 +11 1 +.names N_140.BLIF N_140_i +0 1 +.names N_136_i.BLIF N_136 +0 1 +.names N_139.BLIF N_139_i +0 1 +.names N_136_i.BLIF cpu_est_3_reg.BLIF N_142 +11 1 +.names N_141.BLIF N_141_i +0 1 +.names N_138.BLIF cpu_est_3_reg.BLIF N_145 +11 1 +.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_138_i +11 1 +.names N_138_i.BLIF N_138 +0 1 +.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF N_137_i +11 1 +.names N_138_i.BLIF cpu_est_i_2__n.BLIF N_146 +11 1 +.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_136_i +11 1 +.names N_143_1.BLIF cpu_est_i_3__n.BLIF N_143 +11 1 +.names N_143.BLIF N_143_i +0 1 +.names N_144_1.BLIF cpu_est_i_2__n.BLIF N_144 11 1 .names N_144.BLIF N_144_i 0 1 -.names N_120.BLIF sm_amiga_i_5__n.BLIF N_139 +.names UDS_000_INT_0_sqmuxa_1_0.BLIF UDS_000_INT_0_sqmuxa_2.BLIF \ +UDS_000_INT_0_sqmuxa 11 1 -.names N_150.BLIF N_150_i -0 1 -.names inst_CLK_000_D.BLIF N_126.BLIF N_140 +.names N_143_i.BLIF N_144_i.BLIF N_134_i 11 1 -.names N_126_0.BLIF N_126 -0 1 -.names size_c_1__n.BLIF size_c_i_1__n -0 1 -.names N_121_i.BLIF SM_AMIGA_3_.BLIF N_141 +.names UDS_000_INT_0_sqmuxa_1_3.BLIF clk_un3_clk_000_dd_n.BLIF \ +UDS_000_INT_0_sqmuxa_1 11 1 -.names state_machine_un25_clk_000_d_i_1_n.BLIF size_c_i_1__n.BLIF \ -state_machine_un25_clk_000_d_i_n +.names SM_AMIGA_3_.BLIF state_machine_un57_clk_000_d_0_n.BLIF N_101_0 11 1 -.names N_121_i.BLIF N_121 -0 1 -.names state_machine_un80_clk_000_d_n.BLIF state_machine_un80_clk_000_d_i_n -0 1 -.names N_142_1.BLIF SM_AMIGA_3_.BLIF N_142 +.names N_147_1.BLIF cpu_est_i_2__n.BLIF N_147 11 1 -.names state_machine_un67_clk_000_d_n.BLIF state_machine_un67_clk_000_d_i_n +.names N_115.BLIF N_115_i 0 1 -.names inst_CLK_000_D.BLIF SM_AMIGA_3_.BLIF VPA_SYNC_1_sqmuxa_1_0 +.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_147_1 11 1 -.names state_machine_un67_clk_000_d_i_n.BLIF \ -state_machine_un80_clk_000_d_i_n.BLIF state_machine_un78_clk_000_d_0_n +.names N_116.BLIF N_116_i +0 1 +.names inst_AS_000_INTreg.BLIF inst_CLK_000_D.BLIF \ +state_machine_un13_clk_000_d_1_n +11 1 +.names N_186_5.BLIF N_186_6.BLIF N_186 +11 1 +.names N_124.BLIF N_124_i +0 1 +.names N_189_1.BLIF N_189_2.BLIF N_189 +11 1 +.names state_machine_un42_clk_030_4_n.BLIF state_machine_un42_clk_030_5_n.BLIF \ +state_machine_un42_clk_030_n +11 1 +.names N_112.BLIF N_112_i +0 1 +.names un1_bg_030_0.BLIF un1_bg_030 +0 1 +.names N_111_i.BLIF N_112_i.BLIF sm_amiga_ns_0_0__n +11 1 +.names state_machine_as_030_000_sync_3_2_n.BLIF \ +state_machine_as_030_000_sync_3_n +0 1 +.names N_109_i.BLIF N_111_i.BLIF N_86_i_1 +11 1 +.names un1_as_030_2_0.BLIF un1_as_030_2 +0 1 +.names BG_030_c_i.BLIF CPU_SPACE_i.BLIF un1_bg_030_0_1 +11 1 +.names state_machine_un17_clk_030_0_n.BLIF state_machine_un17_clk_030_n +0 1 +.names AS_030_c.BLIF N_109_i.BLIF un1_bg_030_0_2 +11 1 +.names state_machine_un1_clk_030_0_n.BLIF state_machine_un1_clk_030_n +0 1 +.names AS_030_i.BLIF CPU_SPACE_i.BLIF state_machine_as_030_000_sync_3_2_1_n +11 1 +.names state_machine_un4_bgack_000_0_n.BLIF state_machine_un4_bgack_000_n +0 1 +.names size_c_0__n.BLIF a_c_i_0__n.BLIF state_machine_un31_clk_000_d_i_1_n +11 1 +.names N_108_1.BLIF sm_amiga_i_3__n.BLIF N_108 +11 1 +.names a_i_24__n.BLIF a_i_25__n.BLIF N_186_1 +11 1 +.names state_machine_un31_clk_000_d_i_n.BLIF state_machine_un31_clk_000_d_n +0 1 +.names a_i_26__n.BLIF a_i_27__n.BLIF N_186_2 +11 1 +.names state_machine_un13_clk_000_d_1_0_n.BLIF \ +state_machine_un13_clk_000_d_4_n.BLIF state_machine_un13_clk_000_d_n +11 1 +.names a_i_28__n.BLIF a_i_29__n.BLIF N_186_3 +11 1 +.names state_machine_un13_clk_000_d_4_1_n.BLIF cpu_est_d_2_.BLIF \ +state_machine_un13_clk_000_d_4_n +11 1 +.names a_i_30__n.BLIF a_i_31__n.BLIF N_186_4 +11 1 +.names state_machine_un8_clk_000_d_4_n.BLIF \ +state_machine_un8_clk_000_d_3_n.BLIF state_machine_un8_clk_000_d_n +11 1 +.names N_186_1.BLIF N_186_2.BLIF N_186_5 11 1 .names DTACK_SYNC_1_sqmuxa_1_0.BLIF VPA_SYNC_1_sqmuxa_1_0.BLIF \ DTACK_SYNC_1_sqmuxa 11 1 -.names clk_rising_clk_amiga_1_n.BLIF clk_rising_clk_amiga_1_i_n +.names N_186_3.BLIF N_186_4.BLIF N_186_6 +11 1 +.names inst_CLK_000_D.BLIF SM_AMIGA_3_.BLIF VPA_SYNC_1_sqmuxa_1_0 +11 1 +.names a_c_20__n.BLIF a_c_21__n.BLIF N_189_1 +11 1 +.names VPA_SYNC_1_sqmuxa_4.BLIF VPA_SYNC_1_sqmuxa_3.BLIF VPA_SYNC_1_sqmuxa +11 1 +.names a_c_22__n.BLIF a_c_23__n.BLIF N_189_2 +11 1 +.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_123 +11 1 +.names N_139_i.BLIF N_140_i.BLIF clk_cpu_est_11_0_1_1__n +11 1 +.names N_118_1.BLIF state_machine_un57_clk_000_d_n.BLIF N_118 +11 1 +.names N_141_i.BLIF N_142_i.BLIF clk_cpu_est_11_0_2_1__n +11 1 +.names N_110_1.BLIF SM_AMIGA_1_.BLIF N_110 +11 1 +.names N_147_i.BLIF N_145_i.BLIF clk_cpu_est_11_0_1_3__n +11 1 +.names N_102_0.BLIF N_102 0 1 +.names N_136.BLIF cpu_est_0_.BLIF N_143_1 +11 1 +.names SM_AMIGA_0_.BLIF state_machine_un13_clk_000_d_1_i_n.BLIF N_120 +11 1 +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_144_1 +11 1 +.names CLK_000_D_i.BLIF N_102.BLIF N_119 +11 1 +.names sm_amiga_i_0__n.BLIF sm_amiga_i_2__n.BLIF N_106_1 +11 1 +.names CLK_000_D_i.BLIF SM_AMIGA_2_.BLIF N_117 +11 1 +.names sm_amiga_i_4__n.BLIF sm_amiga_i_6__n.BLIF N_106_2 +11 1 +.names inst_CLK_000_D.BLIF SM_AMIGA_5_.BLIF N_113 +11 1 +.names N_124.BLIF sm_amiga_i_0__n.BLIF N_107_1 +11 1 +.names state_machine_lds_000_int_8_0_n.BLIF state_machine_lds_000_int_8_n +0 1 +.names AS_030_000_SYNC_i.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_1 +11 1 +.names state_machine_uds_000_int_8_0_n.BLIF state_machine_uds_000_int_8_n +0 1 +.names RW_c.BLIF SM_AMIGA_6_.BLIF UDS_000_INT_0_sqmuxa_1_2 +11 1 .names AS_030_i.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF DTACK_SYNC_1_sqmuxa_1 11 1 -.names N_135.BLIF N_135_i -0 1 -.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_149_2 +.names UDS_000_INT_0_sqmuxa_1_1.BLIF UDS_000_INT_0_sqmuxa_1_2.BLIF \ +UDS_000_INT_0_sqmuxa_1_3 11 1 -.names N_135_i.BLIF clk_rising_clk_amiga_1_i_n.BLIF N_104_i +.names AS_030_i.BLIF N_161.BLIF un2_clk_030_1 11 1 -.names inst_CLK_000_D.BLIF CLK_000_DD_i.BLIF clk_un3_clk_000_dd_n +.names inst_CLK_000_D.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_0 11 1 -.names N_149.BLIF N_149_i -0 1 -.names N_164_i.BLIF N_164 -0 1 -.names inst_DTACK_SYNC.BLIF N_149_i.BLIF N_119_0 +.names AS_030_i.BLIF VPA_SYNC_1_sqmuxa_i.BLIF VPA_SYNC_1_sqmuxa_1 11 1 -.names N_171_1.BLIF cpu_est_i_2__n.BLIF N_171 +.names RW_i.BLIF SM_AMIGA_4_.BLIF UDS_000_INT_0_sqmuxa_2 11 1 -.names CLK_000_CNT_1_.BLIF clk_000_cnt_i_1__n -0 1 -.names N_170_1.BLIF cpu_est_i_3__n.BLIF N_170 +.names AS_030_i.BLIF N_114_i.BLIF AS_000_INT_1_sqmuxa 11 1 -.names CLK_000_CNT_0_.BLIF clk_000_cnt_i_0__n -0 1 -.names clk_cpu_est_11_0_3__n.BLIF clk_cpu_est_11_3__n -0 1 -.names CLK_000_CNT_3_.BLIF clk_000_cnt_i_3__n -0 1 -.names N_174_1.BLIF cpu_est_i_2__n.BLIF N_174 -11 1 -.names CLK_000_CNT_2_.BLIF clk_000_cnt_i_2__n -0 1 -.names N_165.BLIF cpu_est_3_reg.BLIF N_172 -11 1 -.names state_machine_un69_clk_000_d_0_1_n.BLIF \ -state_machine_un69_clk_000_d_0_2_n.BLIF state_machine_un69_clk_000_d_0_n -11 1 -.names N_165_i.BLIF cpu_est_i_2__n.BLIF N_173 -11 1 -.names clk_000_cnt_i_0__n.BLIF clk_000_cnt_i_1__n.BLIF \ -state_machine_un69_clk_000_d_0_1_n -11 1 -.names clk_cpu_est_11_0_1__n.BLIF clk_cpu_est_11_1__n -0 1 -.names clk_000_cnt_i_2__n.BLIF clk_000_cnt_i_3__n.BLIF \ -state_machine_un69_clk_000_d_0_2_n -11 1 -.names N_149_2.BLIF cpu_est_3_reg.BLIF N_169 -11 1 -.names size_c_0__n.BLIF a_c_i_0__n.BLIF state_machine_un25_clk_000_d_i_1_n -11 1 -.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_167 -11 1 -.names N_143_i.BLIF N_144_i.BLIF N_116_i_1 -11 1 -.names N_164.BLIF cpu_est_i_0__n.BLIF N_166 -11 1 -.names BG_030_c_i.BLIF CPU_SPACE_i.BLIF un1_bg_030_0_1 -11 1 -.names N_164_i.BLIF cpu_est_0_.BLIF N_168 -11 1 -.names AS_030_c.BLIF N_133_i.BLIF un1_bg_030_0_2 -11 1 -.names N_165_i.BLIF N_165 -0 1 -.names AS_030_i.BLIF CPU_SPACE_i.BLIF state_machine_as_030_000_sync_3_2_1_n -11 1 -.names VMA_INT_1_sqmuxa_0.BLIF VMA_INT_1_sqmuxa -0 1 -.names N_122.BLIF sm_amiga_i_5__n.BLIF un1_UDS_000_INT_0_sqmuxa_i_1 -11 1 -.names CLK_000_D_i.BLIF inst_VPA_SYNC.BLIF N_147 -11 1 -.names N_174_i.BLIF N_172_i.BLIF clk_cpu_est_11_0_1_3__n -11 1 -.names AS_000_INT_i.BLIF inst_CLK_000_D.BLIF N_148 -11 1 -.names N_169_i.BLIF N_167_i.BLIF clk_cpu_est_11_0_1_1__n -11 1 -.names RW_c.BLIF RW_i -0 1 -.names N_166_i.BLIF N_168_i.BLIF clk_cpu_est_11_0_2_1__n -11 1 -.names clk_exp.BLIF clk_exp_i -0 1 -.names a_i_24__n.BLIF a_i_25__n.BLIF N_251_1 -11 1 -.names inst_CLK_000_DD.BLIF CLK_000_DD_i -0 1 -.names a_i_26__n.BLIF a_i_27__n.BLIF N_251_2 -11 1 -.names inst_CLK_000_D.BLIF CLK_000_D_i -0 1 -.names a_i_28__n.BLIF a_i_29__n.BLIF N_251_3 -11 1 -.names inst_AS_000_INTreg.BLIF AS_000_INT_i -0 1 -.names a_i_30__n.BLIF a_i_31__n.BLIF N_251_4 -11 1 -.names cpu_est_0_.BLIF cpu_est_i_0__n -0 1 -.names N_251_1.BLIF N_251_2.BLIF N_251_5 -11 1 -.names cpu_est_2_.BLIF cpu_est_i_2__n -0 1 -.names N_251_3.BLIF N_251_4.BLIF N_251_6 -11 1 -.names cpu_est_3_reg.BLIF cpu_est_i_3__n -0 1 -.names a_c_20__n.BLIF a_c_21__n.BLIF N_254_1 -11 1 -.names cpu_est_1_.BLIF cpu_est_i_1__n -0 1 -.names a_c_22__n.BLIF a_c_23__n.BLIF N_254_2 -11 1 -.names N_149_2.BLIF N_149_2_i -0 1 -.names AS_030_000_SYNC_i.BLIF CLK_000_D_i.BLIF DSACK_INT_1_sqmuxa_1_0 -11 1 -.names inst_VPA_D.BLIF VPA_D_i -0 1 -.names inst_CLK_OUT_PRE.BLIF SM_AMIGA_0_.BLIF DSACK_INT_1_sqmuxa_2 -11 1 -.names DTACK_c.BLIF DTACK_i -0 1 -.names DSACK_INT_1_sqmuxa_1_0.BLIF DSACK_INT_1_sqmuxa_2.BLIF \ -DSACK_INT_1_sqmuxa_3 -11 1 -.names inst_VPA_SYNC.BLIF VPA_SYNC_i -0 1 -.names N_149_2.BLIF VPA_SYNC_i.BLIF N_149_1 -11 1 -.names inst_DTACK_SYNC.BLIF DTACK_SYNC_i -0 1 -.names cpu_est_0_.BLIF cpu_est_3_reg.BLIF N_149_2_0 -11 1 -.names AS_030_c.BLIF AS_030_i -0 1 -.names N_150.BLIF sm_amiga_i_0__n.BLIF N_132_1 -11 1 -.names DTACK_SYNC_1_sqmuxa.BLIF DTACK_SYNC_1_sqmuxa_i -0 1 -.names N_151.BLIF sm_amiga_i_0__n.BLIF N_131_1 -11 1 -.names DS_030_c.BLIF DS_030_i -0 1 .names a_c_17__n.BLIF a_i_16__n.BLIF state_machine_un42_clk_030_1_n 11 1 -.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n -0 1 +.names state_machine_un8_clk_000_d_i_n.BLIF \ +state_machine_un13_clk_000_d_i_n.BLIF VMA_INT_1_sqmuxa +11 1 .names a_i_18__n.BLIF a_i_19__n.BLIF state_machine_un42_clk_030_2_n 11 1 -.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n -0 1 +.names AS_030_i.BLIF N_110_i.BLIF DSACK_INT_1_sqmuxa +11 1 .names fc_c_1__n.BLIF BGACK_000_c.BLIF state_machine_un42_clk_030_3_n 11 1 -.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +.names RW_c.BLIF RW_i 0 1 .names state_machine_un42_clk_030_1_n.BLIF state_machine_un42_clk_030_2_n.BLIF \ state_machine_un42_clk_030_4_n 11 1 -.names N_139.BLIF N_139_i +.names clk_exp.BLIF clk_exp_i 0 1 .names state_machine_un42_clk_030_3_n.BLIF fc_c_0__n.BLIF \ state_machine_un42_clk_030_5_n 11 1 -.names state_machine_un15_clk_000_d_n.BLIF state_machine_un15_clk_000_d_i_n +.names DTACK_SYNC_1_sqmuxa.BLIF DTACK_SYNC_1_sqmuxa_i 0 1 -.names CLK_000_D_i.BLIF N_121.BLIF N_142_1 +.names cpu_est_d_i_0__n.BLIF cpu_est_d_i_3__n.BLIF \ +state_machine_un13_clk_000_d_1_0_n 11 1 -.names N_130.BLIF N_130_i +.names N_114.BLIF N_114_i 0 1 -.names sm_amiga_i_0__n.BLIF sm_amiga_i_2__n.BLIF N_130_1 -11 1 -.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n -0 1 -.names sm_amiga_i_4__n.BLIF sm_amiga_i_6__n.BLIF N_130_2 -11 1 -.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n -0 1 -.names inst_CLK_000_D.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1 +.names state_machine_un13_clk_000_d_1_n.BLIF cpu_est_d_1_.BLIF \ +state_machine_un13_clk_000_d_4_1_n 11 1 .names VPA_SYNC_1_sqmuxa.BLIF VPA_SYNC_1_sqmuxa_i 0 1 -.names RW_i.BLIF SM_AMIGA_4_.BLIF UDS_000_INT_0_sqmuxa_2 +.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF state_machine_un8_clk_000_d_1_n 11 1 -.names dsack_c_1__n.BLIF dsack_i_1__n +.names N_110.BLIF N_110_i +0 1 +.names CLK_000_D_i.BLIF VPA_D_i.BLIF state_machine_un8_clk_000_d_2_n +11 1 +.names N_108.BLIF N_108_i +0 1 +.names cpu_est_0_.BLIF cpu_est_2_.BLIF state_machine_un8_clk_000_d_3_n +11 1 +.names cpu_est_d_3_.BLIF cpu_est_d_i_3__n +0 1 +.names state_machine_un8_clk_000_d_1_n.BLIF \ +state_machine_un8_clk_000_d_2_n.BLIF state_machine_un8_clk_000_d_4_n +11 1 +.names cpu_est_d_0_.BLIF cpu_est_d_i_0__n 0 1 .names DTACK_i.BLIF inst_VPA_D.BLIF DTACK_SYNC_1_sqmuxa_1_0 11 1 -.names DSACK_INT_1_sqmuxa.BLIF DSACK_INT_1_sqmuxa_i +.names inst_CLK_000_D.BLIF CLK_000_D_i 0 1 -.names N_164_i.BLIF VPA_D_i.BLIF VPA_SYNC_1_sqmuxa_1_1 +.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF VPA_SYNC_1_sqmuxa_1_1 11 1 -.names a_c_18__n.BLIF a_i_18__n +.names AS_030_c.BLIF AS_030_i 0 1 -.names VPA_SYNC_1_sqmuxa_1_0.BLIF cpu_est_0_.BLIF VPA_SYNC_1_sqmuxa_2 +.names N_147_1.BLIF VMA_INT_i.BLIF VPA_SYNC_1_sqmuxa_2 11 1 -.names a_c_16__n.BLIF a_i_16__n +.names inst_AS_000_INTreg.BLIF AS_000_INT_i 0 1 -.names VPA_SYNC_1_sqmuxa_1_1.BLIF VPA_SYNC_1_sqmuxa_2.BLIF VPA_SYNC_1_sqmuxa_3 +.names VPA_D_i.BLIF VPA_SYNC_1_sqmuxa_1_0.BLIF VPA_SYNC_1_sqmuxa_3 11 1 -.names a_c_19__n.BLIF a_i_19__n +.names dsack_c_1__n.BLIF dsack_i_1__n 0 1 -.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_171_1 +.names VPA_SYNC_1_sqmuxa_1_1.BLIF VPA_SYNC_1_sqmuxa_2.BLIF VPA_SYNC_1_sqmuxa_4 11 1 -.names CLK_030_c.BLIF CLK_030_i +.names state_machine_un13_clk_000_d_n.BLIF state_machine_un13_clk_000_d_i_n 0 1 -.names N_149_2_i.BLIF cpu_est_0_.BLIF N_170_1 +.names N_123.BLIF sm_amiga_i_0__n.BLIF N_108_1 11 1 -.names state_machine_un42_clk_030_n.BLIF state_machine_un42_clk_030_i_n +.names state_machine_un8_clk_000_d_n.BLIF state_machine_un8_clk_000_d_i_n 0 1 -.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_174_1 +.names CLK_000_D_i.BLIF SM_AMIGA_3_.BLIF N_118_1 11 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +.names state_machine_un13_clk_000_d_1_n.BLIF \ +state_machine_un13_clk_000_d_1_i_n 0 1 -.names G_124.BLIF G_122.BLIF clk_exp_1 -11 1 -.names N_131.BLIF N_131_i -0 1 -.names clk_un3_clk_000_dd_n.BLIF cpu_est_0_1__un3_n -0 1 -.names N_132.BLIF N_132_i -0 1 -.names clk_cpu_est_11_1__n.BLIF clk_un3_clk_000_dd_n.BLIF cpu_est_0_1__un1_n -11 1 -.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n -0 1 -.names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n +.names CLK_000_D_i.BLIF inst_CLK_OUT_PRE.BLIF N_110_1 11 1 .names SM_AMIGA_1_.BLIF sm_amiga_i_1__n 0 1 +.names G_100.BLIF G_98.BLIF clk_exp_1 +11 1 +.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n +0 1 +.names RST_c.BLIF sm_amiga_d_0_2__un3_n +0 1 +.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n +0 1 +.names N_108_i.BLIF RST_c.BLIF sm_amiga_d_0_2__un1_n +11 1 +.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n +0 1 +.names SM_AMIGA_D_2_.BLIF sm_amiga_d_0_2__un3_n.BLIF sm_amiga_d_0_2__un0_n +11 1 +.names inst_VPA_D.BLIF VPA_D_i +0 1 +.names DSACK_INT_1_sqmuxa.BLIF dsack_int_0_1__un3_n +0 1 +.names inst_VMA_INTreg.BLIF VMA_INT_i +0 1 +.names DSACK_INT_1_.BLIF DSACK_INT_1_sqmuxa.BLIF dsack_int_0_1__un1_n +11 1 +.names DTACK_c.BLIF DTACK_i +0 1 +.names N_110_i.BLIF dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un0_n +11 1 +.names cpu_est_3_reg.BLIF cpu_est_i_3__n +0 1 .names VMA_INT_1_sqmuxa.BLIF vma_int_0_un3_n 0 1 -.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n +.names a_c_18__n.BLIF a_i_18__n 0 1 .names inst_VMA_INTreg.BLIF VMA_INT_1_sqmuxa.BLIF vma_int_0_un1_n 11 1 -.names CLK_000_c.BLIF CLK_000_i +.names a_c_16__n.BLIF a_i_16__n 0 1 -.names inst_CLK_000_D.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n +.names state_machine_un13_clk_000_d_4_n.BLIF vma_int_0_un3_n.BLIF \ +vma_int_0_un0_n 11 1 -.names a_c_30__n.BLIF a_i_30__n +.names a_c_19__n.BLIF a_i_19__n 0 1 -.names clk_un3_clk_000_dd_n.BLIF cpu_est_0_3__un3_n +.names VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un3_n 0 1 -.names a_c_31__n.BLIF a_i_31__n +.names CLK_030_c.BLIF CLK_030_i 0 1 -.names clk_cpu_est_11_3__n.BLIF clk_un3_clk_000_dd_n.BLIF cpu_est_0_3__un1_n +.names inst_VPA_SYNC.BLIF VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un1_n 11 1 -.names a_c_28__n.BLIF a_i_28__n +.names state_machine_un42_clk_030_n.BLIF state_machine_un42_clk_030_i_n 0 1 -.names cpu_est_3_reg.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n +.names VPA_SYNC_1_sqmuxa_i.BLIF vpa_sync_0_un3_n.BLIF vpa_sync_0_un0_n 11 1 -.names a_c_29__n.BLIF a_i_29__n +.names DS_030_c.BLIF DS_030_i 0 1 -.names clk_un3_clk_000_dd_n.BLIF cpu_est_0_2__un3_n +.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n 0 1 -.names a_c_26__n.BLIF a_i_26__n +.names cpu_est_1_.BLIF cpu_est_i_1__n 0 1 -.names N_161_i.BLIF clk_un3_clk_000_dd_n.BLIF cpu_est_0_2__un1_n +.names inst_AS_000_INTreg.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n 11 1 -.names a_c_27__n.BLIF a_i_27__n +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i 0 1 -.names cpu_est_2_.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n +.names N_114_i.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n 11 1 -.names a_c_24__n.BLIF a_i_24__n +.names cpu_est_0_.BLIF cpu_est_i_0__n 0 1 .names DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un3_n 0 1 -.names a_c_25__n.BLIF a_i_25__n +.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n 0 1 .names inst_DTACK_SYNC.BLIF DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un1_n 11 1 +.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n +0 1 .names DTACK_SYNC_1_sqmuxa_i.BLIF dtack_sync_0_un3_n.BLIF dtack_sync_0_un0_n 11 1 -.names RST_c.BLIF sm_amiga_d_0_0__un3_n +.names cpu_est_2_.BLIF cpu_est_i_2__n 0 1 -.names RST_c.BLIF RST_i +.names un2_clk_030_1.BLIF lds_000_int_0_un3_n 0 1 -.names N_130_i.BLIF RST_c.BLIF sm_amiga_d_0_0__un1_n +.names UDS_000_INT_0_sqmuxa_1.BLIF UDS_000_INT_0_sqmuxa_1_i +0 1 +.names inst_LDS_000_INTreg.BLIF un2_clk_030_1.BLIF lds_000_int_0_un1_n 11 1 -.names SM_AMIGA_D_0_.BLIF sm_amiga_d_0_0__un3_n.BLIF sm_amiga_d_0_0__un0_n +.names UDS_000_INT_0_sqmuxa.BLIF UDS_000_INT_0_sqmuxa_i +0 1 +.names state_machine_lds_000_int_8_n.BLIF lds_000_int_0_un3_n.BLIF \ +lds_000_int_0_un0_n 11 1 -.names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i +.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n 0 1 -.names state_machine_un4_bgack_000_n.BLIF bgack_030_int_0_un3_n +.names un2_clk_030_1.BLIF uds_000_int_0_un3_n 0 1 -.names CPU_SPACE_c.BLIF CPU_SPACE_i +.names inst_CLK_000_DD.BLIF CLK_000_DD_i 0 1 -.names BGACK_000_c.BLIF state_machine_un4_bgack_000_n.BLIF \ -bgack_030_int_0_un1_n +.names inst_UDS_000_INTreg.BLIF un2_clk_030_1.BLIF uds_000_int_0_un1_n 11 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i +.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n 0 1 -.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \ -bgack_030_int_0_un0_n +.names state_machine_uds_000_int_8_n.BLIF uds_000_int_0_un3_n.BLIF \ +uds_000_int_0_un0_n 11 1 +.names a_c_30__n.BLIF a_i_30__n +0 1 .names state_machine_un1_clk_030_n.BLIF bg_000_0_un3_n 0 1 +.names a_c_31__n.BLIF a_i_31__n +0 1 .names un1_bg_030.BLIF state_machine_un1_clk_030_n.BLIF bg_000_0_un1_n 11 1 +.names a_c_28__n.BLIF a_i_28__n +0 1 .names BG_000DFFSHreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n 11 1 +.names a_c_29__n.BLIF a_i_29__n +0 1 .names state_machine_un17_clk_030_n.BLIF as_030_000_sync_0_un3_n 0 1 +.names a_c_26__n.BLIF a_i_26__n +0 1 .names state_machine_as_030_000_sync_3_n.BLIF \ state_machine_un17_clk_030_n.BLIF as_030_000_sync_0_un1_n 11 1 +.names a_c_27__n.BLIF a_i_27__n +0 1 .names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF \ as_030_000_sync_0_un0_n 11 1 +.names a_c_24__n.BLIF a_i_24__n +0 1 .names state_machine_un17_clk_030_n.BLIF fpu_cs_int_0_un3_n 0 1 +.names a_c_25__n.BLIF a_i_25__n +0 1 .names un1_as_030_2.BLIF state_machine_un17_clk_030_n.BLIF fpu_cs_int_0_un1_n 11 1 .names inst_FPU_CS_INTreg.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un0_n 11 1 -.names DSACK_INT_1_sqmuxa_1.BLIF dsack_int_0_1__un3_n -0 1 -.names DSACK_INT_1_.BLIF DSACK_INT_1_sqmuxa_1.BLIF dsack_int_0_1__un1_n -11 1 -.names DSACK_INT_1_sqmuxa_i.BLIF dsack_int_0_1__un3_n.BLIF \ -dsack_int_0_1__un0_n -11 1 -.names VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un3_n -0 1 -.names inst_VPA_SYNC.BLIF VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un1_n -11 1 -.names VPA_SYNC_1_sqmuxa_i.BLIF vpa_sync_0_un3_n.BLIF vpa_sync_0_un0_n -11 1 -.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n -0 1 -.names inst_AS_000_INTreg.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n -11 1 -.names N_122.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n -11 1 .names inst_RISING_CLK_AMIGA.BLIF ipl_030_0_2__un3_n 0 1 +.names RST_c.BLIF RST_i +0 1 .names ipl_c_2__n.BLIF inst_RISING_CLK_AMIGA.BLIF ipl_030_0_2__un1_n 11 1 +.names N_107.BLIF N_107_i +0 1 .names IPL_030DFFSH_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n 11 1 +.names N_106.BLIF N_106_i +0 1 .names inst_RISING_CLK_AMIGA.BLIF ipl_030_0_1__un3_n 0 1 +.names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i +0 1 .names ipl_c_1__n.BLIF inst_RISING_CLK_AMIGA.BLIF ipl_030_0_1__un1_n 11 1 +.names CPU_SPACE_c.BLIF CPU_SPACE_i +0 1 .names IPL_030DFFSH_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n 11 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i +0 1 .names inst_RISING_CLK_AMIGA.BLIF ipl_030_0_0__un3_n 0 1 .names ipl_c_0__n.BLIF inst_RISING_CLK_AMIGA.BLIF ipl_030_0_0__un1_n 11 1 .names IPL_030DFFSH_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n 11 1 -.names RST_c.BLIF sm_amiga_d_0_2__un3_n +.names state_machine_un4_bgack_000_n.BLIF bgack_030_int_0_un3_n 0 1 -.names N_132_i.BLIF RST_c.BLIF sm_amiga_d_0_2__un1_n +.names BGACK_000_c.BLIF state_machine_un4_bgack_000_n.BLIF \ +bgack_030_int_0_un1_n 11 1 -.names SM_AMIGA_D_2_.BLIF sm_amiga_d_0_2__un3_n.BLIF sm_amiga_d_0_2__un0_n +.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \ +bgack_030_int_0_un0_n +11 1 +.names RST_c.BLIF sm_amiga_d_0_0__un3_n +0 1 +.names N_106_i.BLIF RST_c.BLIF sm_amiga_d_0_0__un1_n +11 1 +.names SM_AMIGA_D_0_.BLIF sm_amiga_d_0_0__un3_n.BLIF sm_amiga_d_0_0__un0_n 11 1 .names RST_c.BLIF sm_amiga_d_0_1__un3_n 0 1 -.names N_131_i.BLIF RST_c.BLIF sm_amiga_d_0_1__un1_n +.names N_107_i.BLIF RST_c.BLIF sm_amiga_d_0_1__un1_n 11 1 .names SM_AMIGA_D_1_.BLIF sm_amiga_d_0_1__un3_n.BLIF sm_amiga_d_0_1__un0_n 11 1 -.names LDS_000_INT_0_sqmuxa.BLIF lds_000_int_0_un3_n +.names clk_un3_clk_000_dd_n.BLIF cpu_est_0_1__un3_n 0 1 -.names inst_LDS_000_INTreg.BLIF LDS_000_INT_0_sqmuxa.BLIF lds_000_int_0_un1_n +.names clk_cpu_est_11_1__n.BLIF clk_un3_clk_000_dd_n.BLIF cpu_est_0_1__un1_n 11 1 -.names state_machine_lds_000_int_8_n.BLIF lds_000_int_0_un3_n.BLIF \ -lds_000_int_0_un0_n +.names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n 11 1 -.names LDS_000_INT_0_sqmuxa.BLIF uds_000_int_0_un3_n +.names clk_un3_clk_000_dd_n.BLIF cpu_est_0_2__un3_n 0 1 -.names inst_UDS_000_INTreg.BLIF LDS_000_INT_0_sqmuxa.BLIF uds_000_int_0_un1_n +.names N_134_i.BLIF clk_un3_clk_000_dd_n.BLIF cpu_est_0_2__un1_n 11 1 -.names state_machine_uds_000_int_8_n.BLIF uds_000_int_0_un3_n.BLIF \ -uds_000_int_0_un0_n +.names cpu_est_2_.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n +11 1 +.names clk_un3_clk_000_dd_n.BLIF cpu_est_0_3__un3_n +0 1 +.names clk_cpu_est_11_3__n.BLIF clk_un3_clk_000_dd_n.BLIF cpu_est_0_3__un1_n +11 1 +.names cpu_est_3_reg.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n 11 1 .names IPL_030DFFSH_2_reg.BLIF IPL_030_2_ 1 1 @@ -1119,7 +1042,7 @@ uds_000_int_0_un0_n .names vcc_n_n.BLIF AMIGA_BUS_ENABLE_LOW 1 1 0 0 -.names N_254.BLIF CIIN +.names N_189.BLIF CIIN 1 1 0 0 .names IPL_030DFFSH_1_reg.BLIF IPL_030_1_ @@ -1128,6 +1051,18 @@ uds_000_int_0_un0_n .names IPL_030DFFSH_0_reg.BLIF IPL_030_0_ 1 1 0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C +1 1 +0 0 +.names RST_i.BLIF SM_AMIGA_6_.AR +1 1 +0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C +1 1 +0 0 +.names RST_i.BLIF SM_AMIGA_5_.AR +1 1 +0 0 .names CLK_OSZI_c.BLIF SM_AMIGA_4_.C 1 1 0 0 @@ -1158,6 +1093,18 @@ uds_000_int_0_un0_n .names RST_i.BLIF SM_AMIGA_0_.AR 1 1 0 0 +.names CLK_OSZI_c.BLIF IPL_030DFFSH_1_reg.C +1 1 +0 0 +.names RST_i.BLIF IPL_030DFFSH_1_reg.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF IPL_030DFFSH_2_reg.C +1 1 +0 0 +.names RST_i.BLIF IPL_030DFFSH_2_reg.AP +1 1 +0 0 .names cpu_est_0_0_.BLIF cpu_est_0_.D 1 1 0 0 @@ -1179,37 +1126,28 @@ uds_000_int_0_un0_n .names RST_i.BLIF SM_AMIGA_7_.AP 1 1 0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C +.names cpu_est_0_.BLIF cpu_est_d_0_.D 1 1 0 0 -.names RST_i.BLIF SM_AMIGA_6_.AR +.names CLK_OSZI_c.BLIF cpu_est_d_0_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C +.names cpu_est_1_.BLIF cpu_est_d_1_.D 1 1 0 0 -.names RST_i.BLIF SM_AMIGA_5_.AR +.names CLK_OSZI_c.BLIF cpu_est_d_1_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF CLK_000_CNT_0_.C +.names cpu_est_2_.BLIF cpu_est_d_2_.D 1 1 0 0 -.names G_128.BLIF CLK_000_CNT_1_.D +.names CLK_OSZI_c.BLIF cpu_est_d_2_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF CLK_000_CNT_1_.C +.names cpu_est_3_reg.BLIF cpu_est_d_3_.D 1 1 0 0 -.names G_130.BLIF CLK_000_CNT_2_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_CNT_2_.C -1 1 -0 0 -.names G_132.BLIF CLK_000_CNT_3_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_CNT_3_.C +.names CLK_OSZI_c.BLIF cpu_est_d_3_.C 1 1 0 0 .names CLK_OSZI_c.BLIF SM_AMIGA_D_0_.C @@ -1227,22 +1165,10 @@ uds_000_int_0_un0_n .names RST_i.BLIF IPL_030DFFSH_0_reg.AP 1 1 0 0 -.names CLK_OSZI_c.BLIF IPL_030DFFSH_1_reg.C +.names CLK_OSZI_c.BLIF inst_AS_000_INTreg.C 1 1 0 0 -.names RST_i.BLIF IPL_030DFFSH_1_reg.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF IPL_030DFFSH_2_reg.C -1 1 -0 0 -.names RST_i.BLIF IPL_030DFFSH_2_reg.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C -1 1 -0 0 -.names RST_i.BLIF inst_AS_030_000_SYNC.AP +.names RST_i.BLIF inst_AS_000_INTreg.AP 1 1 0 0 .names CLK_OSZI_c.BLIF inst_VPA_SYNC.C @@ -1251,16 +1177,10 @@ uds_000_int_0_un0_n .names RST_i.BLIF inst_VPA_SYNC.AP 1 1 0 0 -.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C +.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C 1 1 0 0 -.names RST_i.BLIF BG_000DFFSHreg.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_AS_000_INTreg.C -1 1 -0 0 -.names RST_i.BLIF inst_AS_000_INTreg.AP +.names RST_i.BLIF inst_AS_030_000_SYNC.AP 1 1 0 0 .names CLK_OSZI_c.BLIF inst_VMA_INTreg.C @@ -1269,6 +1189,18 @@ uds_000_int_0_un0_n .names RST_i.BLIF inst_VMA_INTreg.AP 1 1 0 0 +.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C +1 1 +0 0 +.names RST_i.BLIF BG_000DFFSHreg.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF DSACK_INT_1_.C +1 1 +0 0 +.names RST_i.BLIF DSACK_INT_1_.AP +1 1 +0 0 .names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C 1 1 0 0 @@ -1281,12 +1213,6 @@ uds_000_int_0_un0_n .names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE.C 1 1 0 0 -.names CLK_OSZI_c.BLIF DSACK_INT_1_.C -1 1 -0 0 -.names RST_i.BLIF DSACK_INT_1_.AP -1 1 -0 0 .names CLK_OSZI_c.BLIF inst_UDS_000_INTreg.C 1 1 0 0 @@ -1317,15 +1243,12 @@ uds_000_int_0_un0_n .names RST_i.BLIF inst_DTACK_DMA.AP 1 1 0 0 -.names CLK_OSZI_c.BLIF CLK_CNT_0_.C -1 1 -0 0 -.names clk_rising_clk_amiga_1_n.BLIF inst_RISING_CLK_AMIGA.D -1 1 -0 0 .names CLK_OSZI_c.BLIF inst_RISING_CLK_AMIGA.C 1 1 0 0 +.names CLK_OSZI_c.BLIF CLK_CNT_0_.C +1 1 +0 0 .names VPA.BLIF inst_VPA_D.D 1 1 0 0 @@ -1365,87 +1288,18 @@ uds_000_int_0_un0_n .names vcc_n_n.BLIF DSACK_0_ 1 1 0 0 -.names A_15_.BLIF a_15__n -1 1 -0 0 -.names A_22_.BLIF a_c_22__n -1 1 -0 0 -.names A_14_.BLIF a_14__n -1 1 -0 0 -.names A_23_.BLIF a_c_23__n -1 1 -0 0 -.names A_13_.BLIF a_13__n -1 1 -0 0 -.names A_24_.BLIF a_c_24__n -1 1 -0 0 -.names A_12_.BLIF a_12__n -1 1 -0 0 -.names A_25_.BLIF a_c_25__n -1 1 -0 0 -.names A_11_.BLIF a_11__n -1 1 -0 0 -.names A_26_.BLIF a_c_26__n -1 1 -0 0 -.names A_10_.BLIF a_10__n -1 1 -0 0 -.names A_27_.BLIF a_c_27__n -1 1 -0 0 -.names A_9_.BLIF a_9__n -1 1 -0 0 -.names A_28_.BLIF a_c_28__n -1 1 -0 0 -.names A_8_.BLIF a_8__n -1 1 -0 0 -.names A_29_.BLIF a_c_29__n -1 1 -0 0 -.names A_7_.BLIF a_7__n -1 1 -0 0 .names A_30_.BLIF a_c_30__n 1 1 0 0 -.names A_6_.BLIF a_6__n -1 1 -0 0 .names A_31_.BLIF a_c_31__n 1 1 0 0 -.names A_5_.BLIF a_5__n -1 1 -0 0 .names CPU_SPACE.BLIF CPU_SPACE_c 1 1 0 0 -.names A_4_.BLIF a_4__n -1 1 -0 0 .names BG_030.BLIF BG_030_c 1 1 0 0 -.names A_3_.BLIF a_3__n -1 1 -0 0 -.names A_2_.BLIF a_2__n -1 1 -0 0 -.names A_1_.BLIF a_1__n -1 1 -0 0 .names BGACK_000.BLIF BGACK_000_c 1 1 0 0 @@ -1500,24 +1354,93 @@ uds_000_int_0_un0_n .names A_0_.BLIF a_c_0__n 1 1 0 0 +.names A_15_.BLIF a_15__n +1 1 +0 0 +.names A_14_.BLIF a_14__n +1 1 +0 0 +.names A_13_.BLIF a_13__n +1 1 +0 0 +.names A_12_.BLIF a_12__n +1 1 +0 0 .names A_16_.BLIF a_c_16__n 1 1 0 0 +.names A_11_.BLIF a_11__n +1 1 +0 0 .names A_17_.BLIF a_c_17__n 1 1 0 0 +.names A_10_.BLIF a_10__n +1 1 +0 0 .names A_18_.BLIF a_c_18__n 1 1 0 0 +.names A_9_.BLIF a_9__n +1 1 +0 0 .names A_19_.BLIF a_c_19__n 1 1 0 0 +.names A_8_.BLIF a_8__n +1 1 +0 0 .names A_20_.BLIF a_c_20__n 1 1 0 0 +.names A_7_.BLIF a_7__n +1 1 +0 0 .names A_21_.BLIF a_c_21__n 1 1 0 0 +.names A_6_.BLIF a_6__n +1 1 +0 0 +.names A_22_.BLIF a_c_22__n +1 1 +0 0 +.names A_5_.BLIF a_5__n +1 1 +0 0 +.names A_23_.BLIF a_c_23__n +1 1 +0 0 +.names A_4_.BLIF a_4__n +1 1 +0 0 +.names A_24_.BLIF a_c_24__n +1 1 +0 0 +.names A_3_.BLIF a_3__n +1 1 +0 0 +.names A_25_.BLIF a_c_25__n +1 1 +0 0 +.names A_2_.BLIF a_2__n +1 1 +0 0 +.names A_26_.BLIF a_c_26__n +1 1 +0 0 +.names A_1_.BLIF a_1__n +1 1 +0 0 +.names A_27_.BLIF a_c_27__n +1 1 +0 0 +.names A_28_.BLIF a_c_28__n +1 1 +0 0 +.names A_29_.BLIF a_c_29__n +1 1 +0 0 .names CPU_SPACE_i.BLIF DSACK_1_.OE 1 1 0 0 @@ -1542,24 +1465,9 @@ uds_000_int_0_un0_n .names FPU_CS_INT_i.BLIF AVEC_EXP.OE 1 1 0 0 -.names N_251.BLIF CIIN.OE +.names N_186.BLIF CIIN.OE 1 1 0 0 -.names un1_clk_000_cnt_3__n.BLIF un1_clk_000_cnt_2__n.BLIF G_128 -01 1 -10 1 -11 0 -00 0 -.names N_184.BLIF un1_clk_000_cnt_1__n.BLIF G_130 -01 1 -10 1 -11 0 -00 0 -.names N_186.BLIF un1_clk_000_cnt_0__n.BLIF G_132 -01 1 -10 1 -11 0 -00 0 .names cpu_est_0_.BLIF clk_un3_clk_000_dd_n.BLIF cpu_est_0_0_ 01 1 10 1 @@ -1570,17 +1478,17 @@ uds_000_int_0_un0_n 10 1 11 0 00 0 -.names SM_AMIGA_D_0_.BLIF N_130.BLIF G_122 +.names SM_AMIGA_D_0_.BLIF N_106.BLIF G_98 01 1 10 1 11 0 00 0 -.names SM_AMIGA_D_1_.BLIF N_131.BLIF G_123 +.names SM_AMIGA_D_1_.BLIF N_107.BLIF G_99 01 1 10 1 11 0 00 0 -.names SM_AMIGA_D_2_.BLIF N_132.BLIF G_124 +.names SM_AMIGA_D_2_.BLIF N_108.BLIF G_100 01 1 10 1 11 0 diff --git a/Logic/BUS68030.cmd b/Logic/BUS68030.cmd new file mode 100644 index 0000000..e7c37a0 --- /dev/null +++ b/Logic/BUS68030.cmd @@ -0,0 +1,8 @@ +STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: "c:/users/matze/documents/github/68030tk/logic" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC diff --git a/Logic/BUS68030.edi b/Logic/BUS68030.edi index 0b534fb..e72b29e 100644 --- a/Logic/BUS68030.edi +++ b/Logic/BUS68030.edi @@ -4,7 +4,7 @@ (keywordMap (keywordLevel 0)) (status (written - (timeStamp 2014 5 15 19 20 48) + (timeStamp 2014 5 15 22 17 22) (author "Synopsys, Inc.") (program "Synplify Pro" (version "G-2012.09LC-SP1 , mapper maplat, Build 621R")) ) @@ -156,6 +156,10 @@ (port CIIN (direction OUTPUT)) ) (contents + (instance (rename SM_AMIGA_6 "SM_AMIGA[6]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename SM_AMIGA_5 "SM_AMIGA[5]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) (instance (rename SM_AMIGA_4 "SM_AMIGA[4]") (viewRef prim (cellRef DFFRH (libraryRef mach))) ) (instance (rename SM_AMIGA_3 "SM_AMIGA[3]") (viewRef prim (cellRef DFFRH (libraryRef mach))) @@ -166,6 +170,10 @@ ) (instance (rename SM_AMIGA_0 "SM_AMIGA[0]") (viewRef prim (cellRef DFFRH (libraryRef mach))) ) + (instance (rename IPL_030DFFSH_1 "IPL_030DFFSH[1]") (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance (rename IPL_030DFFSH_2 "IPL_030DFFSH[2]") (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) (instance (rename cpu_est_0 "cpu_est[0]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance (rename cpu_est_1 "cpu_est[1]") (viewRef prim (cellRef DFF (libraryRef mach))) @@ -176,17 +184,13 @@ ) (instance (rename SM_AMIGA_7 "SM_AMIGA[7]") (viewRef prim (cellRef DFFSH (libraryRef mach))) ) - (instance (rename SM_AMIGA_6 "SM_AMIGA[6]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + (instance (rename cpu_est_d_0 "cpu_est_d[0]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance (rename SM_AMIGA_5 "SM_AMIGA[5]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + (instance (rename cpu_est_d_1 "cpu_est_d[1]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance (rename CLK_000_CNT_0 "CLK_000_CNT[0]") (viewRef prim (cellRef DFF (libraryRef mach))) + (instance (rename cpu_est_d_2 "cpu_est_d[2]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance (rename CLK_000_CNT_1 "CLK_000_CNT[1]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename CLK_000_CNT_2 "CLK_000_CNT[2]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename CLK_000_CNT_3 "CLK_000_CNT[3]") (viewRef prim (cellRef DFF (libraryRef mach))) + (instance (rename cpu_est_d_3 "cpu_est_d[3]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance (rename SM_AMIGA_D_0 "SM_AMIGA_D[0]") (viewRef prim (cellRef DFF (libraryRef mach))) ) @@ -196,26 +200,22 @@ ) (instance (rename IPL_030DFFSH_0 "IPL_030DFFSH[0]") (viewRef prim (cellRef DFFSH (libraryRef mach))) ) - (instance (rename IPL_030DFFSH_1 "IPL_030DFFSH[1]") (viewRef prim (cellRef DFFSH (libraryRef mach))) - ) - (instance (rename IPL_030DFFSH_2 "IPL_030DFFSH[2]") (viewRef prim (cellRef DFFSH (libraryRef mach))) - ) - (instance AS_030_000_SYNC (viewRef prim (cellRef DFFSH (libraryRef mach))) + (instance AS_000_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) ) (instance VPA_SYNC (viewRef prim (cellRef DFFSH (libraryRef mach))) ) - (instance BG_000DFFSH (viewRef prim (cellRef DFFSH (libraryRef mach))) - ) - (instance AS_000_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) + (instance AS_030_000_SYNC (viewRef prim (cellRef DFFSH (libraryRef mach))) ) (instance VMA_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) ) + (instance BG_000DFFSH (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance (rename DSACK_INT_1 "DSACK_INT[1]") (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) (instance BGACK_030_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) ) (instance CLK_OUT_PRE (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance (rename DSACK_INT_1 "DSACK_INT[1]") (viewRef prim (cellRef DFFSH (libraryRef mach))) - ) (instance UDS_000_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) ) (instance LDS_000_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) @@ -226,10 +226,10 @@ ) (instance DTACK_DMA (viewRef prim (cellRef DFFSH (libraryRef mach))) ) - (instance (rename CLK_CNT_0 "CLK_CNT[0]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) (instance RISING_CLK_AMIGA (viewRef prim (cellRef DFF (libraryRef mach))) ) + (instance (rename CLK_CNT_0 "CLK_CNT[0]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) (instance VPA_D (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance CLK_000_D (viewRef prim (cellRef DFF (libraryRef mach))) @@ -299,43 +299,49 @@ (instance AMIGA_BUS_DATA_DIR (viewRef prim (cellRef OBUF (libraryRef mach))) ) (instance AMIGA_BUS_ENABLE_LOW (viewRef prim (cellRef OBUF (libraryRef mach))) ) (instance CIIN (viewRef prim (cellRef BUFTH (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_a4_1_1_3 "clk.cpu_est_11_0_a4_1_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_a4_1_3 "clk.cpu_est_11_0_a4_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance G_125_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance G_125 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename un9_i_a3_2_2 "un9_i_a3_2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename un9_i_a3_2 "un9_i_a3[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance UDS_000_INT_0_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance UDS_000_INT_0_sqmuxa_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance UDS_000_INT_0_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DTACK_SYNC_1_sqmuxa_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DTACK_SYNC_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_SYNC_1_sqmuxa_1_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VPA_SYNC_1_sqmuxa_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance VPA_SYNC_1_sqmuxa_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_SYNC_1_sqmuxa_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VPA_SYNC_1_sqmuxa_3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VPA_SYNC_1_sqmuxa_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance VPA_SYNC_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_i_a4_0_1_2 "clk.cpu_est_11_i_a4_0_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_i_a4_0_2 "clk.cpu_est_11_i_a4_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_i_a4_1_2 "clk.cpu_est_11_i_a4_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_i_a4_2 "clk.cpu_est_11_i_a4[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_a2_0_2_0_6 "SM_AMIGA_ns_i_a2_0_2_0[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_a2_0_6 "SM_AMIGA_ns_i_a2_0[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename un9_i_a3_1_0 "un9_i_a3_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename un9_i_a3_0 "un9_i_a3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename un9_i_a3_1_1 "un9_i_a3_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename un9_i_a3_1 "un9_i_a3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un42_clk_030_1 "state_machine.un42_clk_030_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un42_clk_030_2 "state_machine.un42_clk_030_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename un9_i_a2_1_0 "un9_i_a2_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename un9_i_a2_0 "un9_i_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_a2_0_1_5 "SM_AMIGA_ns_a2_0_1[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_a2_0_5 "SM_AMIGA_ns_a2_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_DSACK_INT_0_sqmuxa_i_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_DSACK_INT_0_sqmuxa_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance G_101_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance G_101 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename state_machine_un42_clk_030_3 "state_machine.un42_clk_030_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename state_machine_un42_clk_030_4 "state_machine.un42_clk_030_4") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename state_machine_un42_clk_030_5 "state_machine.un42_clk_030_5") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename state_machine_un42_clk_030 "state_machine.un42_clk_030") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_a3_1_5 "SM_AMIGA_ns_a3_1[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_a3_5 "SM_AMIGA_ns_a3[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename un9_i_a3_1_2 "un9_i_a3_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un8_ciin_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un8_ciin_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un8_ciin_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un13_clk_000_d_1_0 "state_machine.un13_clk_000_d_1_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un13_clk_000_d "state_machine.un13_clk_000_d") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un13_clk_000_d_4_1 "state_machine.un13_clk_000_d_4_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un13_clk_000_d_4 "state_machine.un13_clk_000_d_4") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un8_clk_000_d_1 "state_machine.un8_clk_000_d_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un8_clk_000_d_2 "state_machine.un8_clk_000_d_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un8_clk_000_d_3 "state_machine.un8_clk_000_d_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un8_clk_000_d_4 "state_machine.un8_clk_000_d_4") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un8_clk_000_d "state_machine.un8_clk_000_d") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DTACK_SYNC_1_sqmuxa_1_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DTACK_SYNC_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_i_a4_0_2 "clk.cpu_est_11_i_a4_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename un9_i_a2_1_2 "un9_i_a2_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename un9_i_a2_2_2 "un9_i_a2_2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename un9_i_a2_2 "un9_i_a2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename un9_i_a2_1_1 "un9_i_a2_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename un9_i_a2_1 "un9_i_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance UDS_000_INT_0_sqmuxa_1_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance UDS_000_INT_0_sqmuxa_1_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance UDS_000_INT_0_sqmuxa_1_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance UDS_000_INT_0_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance UDS_000_INT_0_sqmuxa_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance UDS_000_INT_0_sqmuxa_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance UDS_000_INT_0_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un42_clk_030_1 "state_machine.un42_clk_030_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un42_clk_030_2 "state_machine.un42_clk_030_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un8_ciin_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un8_ciin_5 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un8_ciin_6 (viewRef prim (cellRef AND2 (libraryRef mach))) ) @@ -343,184 +349,144 @@ (instance un4_ciin_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un4_ciin_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un4_ciin (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DSACK_INT_1_sqmuxa_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DSACK_INT_1_sqmuxa_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DSACK_INT_1_sqmuxa_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DSACK_INT_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_a2_0_1_6 "SM_AMIGA_ns_i_a2_0_1[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un25_clk_000_d "state_machine.un25_clk_000_d") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_1_6 "SM_AMIGA_ns_i_1[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_6 "SM_AMIGA_ns_i[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_1_1 "clk.cpu_est_11_0_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_2_1 "clk.cpu_est_11_0_2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_1 "clk.cpu_est_11_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_1_3 "clk.cpu_est_11_0_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_3 "clk.cpu_est_11_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_i_a4_1_2 "clk.cpu_est_11_i_a4_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_i_a4_2 "clk.cpu_est_11_i_a4[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_i_a4_0_1_2 "clk.cpu_est_11_i_a4_0_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance N_124_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_112_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_0 "SM_AMIGA_ns_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_1_1 "SM_AMIGA_ns_i_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_1 "SM_AMIGA_ns_i[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un1_bg_030_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un1_bg_030_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un1_bg_030 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename state_machine_AS_030_000_SYNC_3_1 "state_machine.AS_030_000_SYNC_3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename state_machine_AS_030_000_SYNC_3 "state_machine.AS_030_000_SYNC_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_UDS_000_INT_0_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_UDS_000_INT_0_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_1_3 "clk.cpu_est_11_0_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_3 "clk.cpu_est_11_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_1_1 "clk.cpu_est_11_0_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_2_1 "clk.cpu_est_11_0_2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_1 "clk.cpu_est_11_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un67_clk_000_d_i "state_machine.un67_clk_000_d_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un78_clk_000_d_i "state_machine.un78_clk_000_d_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename clk_RISING_CLK_AMIGA_1_i "clk.RISING_CLK_AMIGA_1_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_135_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_149_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_o2_i_6 "SM_AMIGA_ns_i_o2_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename CLK_000_CNT_i_1 "CLK_000_CNT_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename CLK_000_CNT_i_0 "CLK_000_CNT_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename CLK_000_CNT_i_3 "CLK_000_CNT_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename CLK_000_CNT_i_2 "CLK_000_CNT_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance G_150_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance G_150_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance G_150_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance G_150 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un25_clk_000_d_1 "state_machine.un25_clk_000_d_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_AS_030_000_SYNC_3_i "state_machine.AS_030_000_SYNC_3_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_133_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_bg_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_c_i_0 "A_c_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_UDS_000_INT_8_i "state_machine.UDS_000_INT_8_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_LDS_000_INT_8_i "state_machine.LDS_000_INT_8_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_151_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_146_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un31_clk_000_d_1 "state_machine.un31_clk_000_d_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un31_clk_000_d "state_machine.un31_clk_000_d") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un8_ciin_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un8_ciin_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un8_ciin_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance N_145_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_7 "SM_AMIGA_ns_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_146_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_142_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_i_1 "clk.cpu_est_11_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_140_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_139_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_141_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_o4_i_3 "clk.cpu_est_11_0_o4_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_o4_i_1 "clk.cpu_est_11_0_o4_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_i_o4_i_2 "clk.cpu_est_11_i_o4_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_143_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_144_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_150_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_o2_i_4 "SM_AMIGA_ns_i_o2_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_115_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_116_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename SIZE_c_i_1 "SIZE_c_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un25_clk_000_d_i_0 "state_machine.un25_clk_000_d_i_0") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un80_clk_000_d_i "state_machine.un80_clk_000_d_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_UDS_000_INT_0_sqmuxa_2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance UDS_000_INT_0_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_UDS_000_INT_0_sqmuxa_i_0 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_o2_i_0 "SM_AMIGA_ns_i_o2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_136_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un31_clk_000_d_i_0 "state_machine.un31_clk_000_d_i_0") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance RISING_CLK_AMIGA_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename state_machine_un4_bgack_000_i "state_machine.un4_bgack_000_i") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance BG_030_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename state_machine_un1_clk_030_i "state_machine.un1_clk_030_i") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename state_machine_un17_clk_030_i "state_machine.un17_clk_030_i") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance un1_as_030_2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_137_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_138_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_o2_i_2 "SM_AMIGA_ns_i_o2_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_o2_i_1 "SM_AMIGA_ns_i_o2_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_173_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_172_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_174_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_i_3 "clk.cpu_est_11_0_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_o2_i_5 "SM_AMIGA_ns_o2_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_o2_i_4 "SM_AMIGA_ns_o2_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un9_clk_000_d_i_o3_i "state_machine.un9_clk_000_d_i_o3_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_SM_AMIGA_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_142_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_143_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_5 "SM_AMIGA_ns_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_141_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_140_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_4 "SM_AMIGA_ns_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance LDS_000_INT_1_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_148_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_AS_030_000_SYNC_3_i "state_machine.AS_030_000_SYNC_3_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_109_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_bg_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_111_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_122_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_147_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance VMA_INT_1_sqmuxa_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_170_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_171_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_o4_i_1 "clk.cpu_est_11_0_o4_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_o4_i_3 "clk.cpu_est_11_0_o4_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_168_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_166_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_167_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_169_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_i_1 "clk.cpu_est_11_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_0_1__r "cpu_est_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_0_1__m "cpu_est_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_1__n "cpu_est_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_1__p "cpu_est_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_i_3 "clk.cpu_est_11_0_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_161_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_c_i_0 "A_c_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_UDS_000_INT_8_i "state_machine.UDS_000_INT_8_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_LDS_000_INT_8_i "state_machine.LDS_000_INT_8_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_113_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_2 "SM_AMIGA_ns_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_118_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_117_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_5 "SM_AMIGA_ns_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_123_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_119_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_120_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_7 "SM_AMIGA_ns_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_OUT_PRE_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_o2_i_6 "SM_AMIGA_ns_i_o2_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un57_clk_000_d_i "state_machine.un57_clk_000_d_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_D_0_2__r "SM_AMIGA_D_0_2_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_D_0_2__m "SM_AMIGA_D_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_D_0_2__n "SM_AMIGA_D_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_D_0_2__p "SM_AMIGA_D_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance N_110_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename DSACK_INT_0_1__r "DSACK_INT_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename DSACK_INT_0_1__m "DSACK_INT_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DSACK_INT_0_1__n "DSACK_INT_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DSACK_INT_0_1__p "DSACK_INT_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (instance (rename VMA_INT_0_r "VMA_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename VMA_INT_0_m "VMA_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename VMA_INT_0_n "VMA_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename VMA_INT_0_p "VMA_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance RW_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance clk_exp_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_a4_1_1 "clk.cpu_est_11_0_a4_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_i_2 "cpu_est_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_i_3 "cpu_est_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_a4_0_1 "clk.cpu_est_11_0_a4_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_i_0 "cpu_est_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_a4_1 "clk.cpu_est_11_0_a4[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VMA_INT_1_sqmuxa_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance VMA_INT_1_sqmuxa_0_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_000_D_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance VMA_INT_1_sqmuxa_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_000_DD_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename clk_un3_clk_000_dd "clk.un3_clk_000_dd") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_3__r "cpu_est_0_3_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_0_3__m "cpu_est_0_3_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_3__n "cpu_est_0_3_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_3__p "cpu_est_0_3_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename cpu_est_0_2__r "cpu_est_0_2_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_0_2__m "cpu_est_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_2__n "cpu_est_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_2__p "cpu_est_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance DTACK_SYNC_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_o2_5 "SM_AMIGA_ns_o2[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_SYNC_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_169 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_0_0 "cpu_est_0[0]") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance VPA_D_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_a2_0_2_6 "SM_AMIGA_ns_i_a2_0_2[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance N_149_2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_i_1 "cpu_est_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_o4_3 "clk.cpu_est_11_0_o4[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_o4_1 "clk.cpu_est_11_0_o4[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_i_2 "clk.cpu_est_11_i[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_a4_0_3 "clk.cpu_est_11_0_a4_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_a4_3 "clk.cpu_est_11_0_a4[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_a4_2_1 "clk.cpu_est_11_0_a4_2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_2 "SM_AMIGA_ns_i[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_4 "SM_AMIGA_ns[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_5 "SM_AMIGA_ns[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_SM_AMIGA_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un9_clk_000_d_i_o3 "state_machine.un9_clk_000_d_i_o3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_o2_4 "SM_AMIGA_ns_o2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DS_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance VPA_SYNC_1_sqmuxa_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance G_122 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance VPA_SYNC_1_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename VPA_SYNC_0_r "VPA_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename VPA_SYNC_0_m "VPA_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename VPA_SYNC_0_n "VPA_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename VPA_SYNC_0_p "VPA_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance N_114_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AS_000_INT_0_r "AS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AS_000_INT_0_m "AS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_000_INT_0_n "AS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_000_INT_0_p "AS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance DTACK_SYNC_1_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename DTACK_SYNC_0_r "DTACK_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename DTACK_SYNC_0_m "DTACK_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename DTACK_SYNC_0_n "DTACK_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename DTACK_SYNC_0_p "DTACK_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename LDS_000_INT_0_r "LDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename LDS_000_INT_0_m "LDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename LDS_000_INT_0_n "LDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename LDS_000_INT_0_p "LDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_r "UDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_m "UDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_n "UDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_p "UDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename state_machine_un57_clk_000_d "state_machine.un57_clk_000_d") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RW_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance clk_exp_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance VPA_SYNC_1_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_INT_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un13_clk_000_d_i "state_machine.un13_clk_000_d_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un8_clk_000_d_i "state_machine.un8_clk_000_d_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance VMA_INT_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_119 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un13_as_000_int "state_machine.un13_as_000_int") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance AS_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DTACK_SYNC_1_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DSACK_INT_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_000_D_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename clk_RISING_CLK_AMIGA_1 "clk.RISING_CLK_AMIGA_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_d_i_3 "cpu_est_d_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_d_i_0 "cpu_est_d_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_108_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_6 "SM_AMIGA_ns_i[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_5 "SM_AMIGA_ns[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_2 "SM_AMIGA_ns[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_a2_0_6 "SM_AMIGA_ns_i_a2_0[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un13_clk_000_d_1_i "state_machine.un13_clk_000_d_1_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_a2_7 "SM_AMIGA_ns_a2[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_a2_6 "SM_AMIGA_ns_i_a2[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_a2_5 "SM_AMIGA_ns_a2[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_a2_2 "SM_AMIGA_ns_a2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_LDS_000_INT_8 "state_machine.LDS_000_INT_8") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_UDS_000_INT_8 "state_machine.UDS_000_INT_8") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance DTACK_SYNC_1_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_0 "SM_AMIGA_ns_i[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_o2_0 "SM_AMIGA_ns_i_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance N_130_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_D_0_0__r "SM_AMIGA_D_0_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_D_0_0__m "SM_AMIGA_D_0_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_D_0_0__n "SM_AMIGA_D_0_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_D_0_0__p "SM_AMIGA_D_0_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename state_machine_un15_clk_000_d "state_machine.un15_clk_000_d") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance N_139_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un15_clk_000_d_i "state_machine.un15_clk_000_d_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance LDS_000_INT_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_UDS_000_INT_0_sqmuxa_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_a3_2 "SM_AMIGA_ns_i_a3[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_a3_4 "SM_AMIGA_ns_a3[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_a3_0_4 "SM_AMIGA_ns_a3_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_a2_3 "SM_AMIGA_ns_i_a2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename BGACK_030_INT_0_r "BGACK_030_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename BGACK_030_INT_0_m "BGACK_030_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename BGACK_030_INT_0_n "BGACK_030_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename BGACK_030_INT_0_p "BGACK_030_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance un2_clk_030_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename BG_000_0_r "BG_000_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename BG_000_0_m "BG_000_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename BG_000_0_n "BG_000_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) @@ -533,29 +499,20 @@ (instance (rename FPU_CS_INT_0_m "FPU_CS_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename FPU_CS_INT_0_n "FPU_CS_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename FPU_CS_INT_0_p "FPU_CS_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance DSACK_INT_1_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename DSACK_INT_0_1__r "DSACK_INT_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename DSACK_INT_0_1__m "DSACK_INT_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename DSACK_INT_0_1__n "DSACK_INT_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename DSACK_INT_0_1__p "DSACK_INT_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename VPA_SYNC_0_r "VPA_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename VPA_SYNC_0_m "VPA_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename VPA_SYNC_0_n "VPA_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename VPA_SYNC_0_p "VPA_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename AS_000_INT_0_r "AS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AS_000_INT_0_m "AS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AS_000_INT_0_n "AS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AS_000_INT_0_p "AS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance AS_000_INT_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance I_170 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un14_as_000_int "state_machine.un14_as_000_int") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_SYNC_1_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance VPA_SYNC_1_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_a3_0 "SM_AMIGA_ns_i_a3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_a3_1 "SM_AMIGA_ns_i_a3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un5_clk_030_i_a3 "state_machine.un5_clk_030_i_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DSACK_INT_1_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance G_100 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance CLK_OUT_PRE_0 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance (rename state_machine_un13_clk_000_d_1 "state_machine.un13_clk_000_d_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_i_3 "cpu_est_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_120 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DTACK_SYNC_1_sqmuxa_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VPA_D_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance VMA_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_o2_6 "SM_AMIGA_ns_i_o2[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_7 "SM_AMIGA_ns[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance G_98 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance G_99 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) (instance (rename state_machine_un42_clk_030_i "state_machine.un42_clk_030_i") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance un1_as_030_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename state_machine_un17_clk_030 "state_machine.un17_clk_030") (viewRef prim (cellRef AND2 (libraryRef mach))) ) @@ -577,78 +534,85 @@ (instance (rename IPL_030_0_0__m "IPL_030_0_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename IPL_030_0_0__n "IPL_030_0_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename IPL_030_0_0__p "IPL_030_0_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_a3_0_5 "SM_AMIGA_ns_a3_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_LDS_000_INT_8 "state_machine.LDS_000_INT_8") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_UDS_000_INT_8 "state_machine.UDS_000_INT_8") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance LDS_000_INT_0_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance N_132_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_D_0_2__r "SM_AMIGA_D_0_2_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_D_0_2__m "SM_AMIGA_D_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_D_0_2__n "SM_AMIGA_D_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_D_0_2__p "SM_AMIGA_D_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance N_131_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_D_0_1__r "SM_AMIGA_D_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_D_0_1__m "SM_AMIGA_D_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_D_0_1__n "SM_AMIGA_D_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_D_0_1__p "SM_AMIGA_D_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename LDS_000_INT_0_r "LDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename LDS_000_INT_0_m "LDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename LDS_000_INT_0_n "LDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename LDS_000_INT_0_p "LDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename UDS_000_INT_0_r "UDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename UDS_000_INT_0_m "UDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename UDS_000_INT_0_n "UDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename UDS_000_INT_0_p "UDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_o2_1 "SM_AMIGA_ns_i_o2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_o2_2 "SM_AMIGA_ns_i_o2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_1 "SM_AMIGA_ns_i[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BGACK_030_INT_0_r "BGACK_030_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename BGACK_030_INT_0_m "BGACK_030_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BGACK_030_INT_0_n "BGACK_030_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BGACK_030_INT_0_p "BGACK_030_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_o4_1 "clk.cpu_est_11_0_o4[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_o4_3 "clk.cpu_est_11_0_o4[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance UDS_000_INT_0_sqmuxa_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance UDS_000_INT_0_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un2_clk_030_1_106 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_i_2 "cpu_est_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_a4_1_3 "clk.cpu_est_11_0_a4_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_i_0 "cpu_est_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance VPA_SYNC_1_sqmuxa_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance AS_030_000_SYNC_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_a3_0_1 "SM_AMIGA_ns_i_a3_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un67_clk_000_d "state_machine.un67_clk_000_d") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un80_clk_000_d "state_machine.un80_clk_000_d") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance G_131 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance G_129 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance G_124 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance G_123 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_a3_6 "SM_AMIGA_ns_i_a3[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_a3_0_7 "SM_AMIGA_ns_a3_0[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_7 "SM_AMIGA_ns[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_i_1 "cpu_est_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DS_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_0_0 "cpu_est_0[0]") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_a2_1 "SM_AMIGA_ns_i_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_a2_3 "SM_AMIGA_ns_i_a2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0 "SM_AMIGA_ns[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_ns_i_3 "SM_AMIGA_ns_i[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_a2_6 "SM_AMIGA_ns_i_a2[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_a3_7 "SM_AMIGA_ns_a3[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance G_132 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance G_130 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance G_128 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance (rename un1_CLK_000_CNT_0 "un1_CLK_000_CNT[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename un1_CLK_000_CNT_1 "un1_CLK_000_CNT[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename un1_CLK_000_CNT_2 "un1_CLK_000_CNT[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename un1_CLK_000_CNT_3 "un1_CLK_000_CNT[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_OUT_PRE_0 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_a3_0_1_7 "SM_AMIGA_ns_a3_0_1[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_o2_6 "SM_AMIGA_ns_i_o2[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_un1_clk_000_i "clk.un1_clk_000_i") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_000_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename clk_un1_clk_000_i_a3 "clk.un1_clk_000_i_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_RISING_CLK_AMIGA_1_0_a3 "clk.RISING_CLK_AMIGA_1_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un78_clk_000_d "state_machine.un78_clk_000_d") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename A_i_24 "A_i[24]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_i_25 "A_i[25]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_4 "SM_AMIGA_ns_i[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_o2_4 "SM_AMIGA_ns_i_o2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_a4_1 "clk.cpu_est_11_0_a4[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_a4_0_1 "clk.cpu_est_11_0_a4_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_a4_1_1 "clk.cpu_est_11_0_a4_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_a4_2_1 "clk.cpu_est_11_0_a4_2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_a4_3 "clk.cpu_est_11_0_a4[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_a4_0_3 "clk.cpu_est_11_0_a4_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_i_2 "clk.cpu_est_11_i[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_i_o4_2 "clk.cpu_est_11_i_o4[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename A_i_26 "A_i[26]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename A_i_27 "A_i[27]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename A_i_28 "A_i[28]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename A_i_29 "A_i[29]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename A_i_30 "A_i[30]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename A_i_31 "A_i[31]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un14_as_000_int_i "state_machine.un14_as_000_int_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un5_clk_030_i_a2 "state_machine.un5_clk_030_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_a2_0 "SM_AMIGA_ns_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_a2_0_0 "SM_AMIGA_ns_a2_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_a2_0_2 "SM_AMIGA_ns_a2_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_a2_4 "SM_AMIGA_ns_i_a2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_a2_0_4 "SM_AMIGA_ns_i_a2_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_000_DD_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename clk_un3_clk_000_dd_0_a2 "clk.un3_clk_000_dd_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un13_as_000_int_i "state_machine.un13_as_000_int_i") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance RST_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename CLK_CNT_i_0 "CLK_CNT_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename un1_CLK_000_CNT_i_3 "un1_CLK_000_CNT_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_24 "A_i[24]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_25 "A_i[25]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance BGACK_030_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance CPU_SPACE_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance FPU_CS_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_106_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_D_0_0__r "SM_AMIGA_D_0_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_D_0_0__m "SM_AMIGA_D_0_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_D_0_0__n "SM_AMIGA_D_0_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_D_0_0__p "SM_AMIGA_D_0_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance N_107_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_D_0_1__r "SM_AMIGA_D_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_D_0_1__m "SM_AMIGA_D_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_D_0_1__n "SM_AMIGA_D_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_D_0_1__p "SM_AMIGA_D_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename cpu_est_0_1__r "cpu_est_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_0_1__m "cpu_est_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_1__n "cpu_est_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_1__p "cpu_est_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename cpu_est_0_2__r "cpu_est_0_2_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_0_2__m "cpu_est_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_2__n "cpu_est_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_2__p "cpu_est_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename cpu_est_0_3__r "cpu_est_0_3_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_0_3__m "cpu_est_0_3_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_3__n "cpu_est_0_3_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_3__p "cpu_est_0_3_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (net BGACK_030_INT (joined (portRef Q (instanceRef BGACK_030_INT)) (portRef I0 (instanceRef BGACK_030_INT_i)) @@ -670,15 +634,17 @@ )) (net (rename cpu_est_3 "cpu_est[3]") (joined (portRef Q (instanceRef cpu_est_3)) - (portRef I1 (instanceRef clk_cpu_est_11_0_a4_2_1)) - (portRef I1 (instanceRef clk_cpu_est_11_0_a4_3)) (portRef I0 (instanceRef cpu_est_0_3__n)) + (portRef I1 (instanceRef clk_cpu_est_11_0_a4_3)) + (portRef I1 (instanceRef clk_cpu_est_11_0_a4_2_1)) (portRef I0 (instanceRef cpu_est_i_3)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_0_2_0_6)) + (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_1_0)) (portRef I0 (instanceRef E)) + (portRef D (instanceRef cpu_est_d_3)) )) (net VMA_INT (joined (portRef Q (instanceRef VMA_INT)) + (portRef I0 (instanceRef VMA_INT_i)) (portRef I0 (instanceRef VMA_INT_0_m)) (portRef I0 (instanceRef VMA)) )) @@ -687,20 +653,38 @@ (portRef I0 (instanceRef AVEC_EXP)) (portRef I0 (instanceRef BERR)) )) + (net (rename cpu_est_0 "cpu_est[0]") (joined + (portRef Q (instanceRef cpu_est_0)) + (portRef I1 (instanceRef clk_cpu_est_11_0_a4_1_1)) + (portRef I1 (instanceRef cpu_est_0_0)) + (portRef I0 (instanceRef cpu_est_i_0)) + (portRef I0 (instanceRef clk_cpu_est_11_0_o4_3)) + (portRef I1 (instanceRef clk_cpu_est_11_i_a4_1_2)) + (portRef I0 (instanceRef state_machine_un8_clk_000_d_3)) + (portRef D (instanceRef cpu_est_d_0)) + )) (net (rename cpu_est_1 "cpu_est[1]") (joined (portRef Q (instanceRef cpu_est_1)) - (portRef I1 (instanceRef clk_cpu_est_11_0_o4_3)) - (portRef I0 (instanceRef cpu_est_i_1)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_0_2_6)) (portRef I0 (instanceRef cpu_est_0_1__n)) + (portRef I0 (instanceRef clk_cpu_est_11_i_o4_2)) + (portRef I0 (instanceRef cpu_est_i_1)) + (portRef I1 (instanceRef clk_cpu_est_11_0_o4_3)) (portRef I0 (instanceRef clk_cpu_est_11_i_a4_0_1_2)) + (portRef D (instanceRef cpu_est_d_1)) + )) + (net (rename cpu_est_d_0 "cpu_est_d[0]") (joined + (portRef Q (instanceRef cpu_est_d_0)) + (portRef I0 (instanceRef cpu_est_d_i_0)) + )) + (net (rename cpu_est_d_3 "cpu_est_d[3]") (joined + (portRef Q (instanceRef cpu_est_d_3)) + (portRef I0 (instanceRef cpu_est_d_i_3)) )) (net AS_000_INT (joined (portRef Q (instanceRef AS_000_INT)) - (portRef I0 (instanceRef AS_000_INT_0_m)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_0)) - (portRef I0 (instanceRef state_machine_un9_clk_000_d_i_o3)) + (portRef I0 (instanceRef state_machine_un13_clk_000_d_1)) (portRef I0 (instanceRef AS_000_INT_i)) + (portRef I0 (instanceRef AS_000_INT_0_m)) (portRef I0 (instanceRef AS_000)) )) (net AS_030_000_SYNC (joined @@ -710,38 +694,28 @@ )) (net DTACK_SYNC (joined (portRef Q (instanceRef DTACK_SYNC)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_6)) + (portRef I0 (instanceRef state_machine_un57_clk_000_d)) (portRef I0 (instanceRef DTACK_SYNC_0_m)) - (portRef I0 (instanceRef SM_AMIGA_ns_o2_5)) - (portRef I0 (instanceRef DTACK_SYNC_i)) )) (net VPA_D (joined (portRef Q (instanceRef VPA_D)) (portRef I0 (instanceRef VPA_D_i)) - (portRef I1 (instanceRef DTACK_SYNC_1_sqmuxa_1_0)) + (portRef I1 (instanceRef DTACK_SYNC_1_sqmuxa_1_1)) )) (net VPA_SYNC (joined (portRef Q (instanceRef VPA_SYNC)) + (portRef I1 (instanceRef state_machine_un57_clk_000_d)) (portRef I0 (instanceRef VPA_SYNC_0_m)) - (portRef I0 (instanceRef VPA_SYNC_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_o2_5)) - (portRef I1 (instanceRef VMA_INT_1_sqmuxa_0_a3)) )) (net CLK_000_D (joined (portRef Q (instanceRef CLK_000_D)) - (portRef I0 (instanceRef clk_un1_clk_000_i_a3)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_a3_0_1)) - (portRef I0 (instanceRef SM_AMIGA_ns_a3_4)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_0)) - (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1_0)) - (portRef I1 (instanceRef state_machine_un9_clk_000_d_i_o3)) - (portRef I0 (instanceRef un1_SM_AMIGA_i_o2)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_2)) - (portRef I0 (instanceRef clk_un3_clk_000_dd)) + (portRef I0 (instanceRef clk_un3_clk_000_dd_0_a2)) + (portRef I0 (instanceRef SM_AMIGA_ns_a2_0)) + (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa_1_0)) + (portRef I1 (instanceRef state_machine_un13_clk_000_d_1)) + (portRef I0 (instanceRef SM_AMIGA_ns_a2_2)) (portRef I0 (instanceRef CLK_000_D_i)) - (portRef I1 (instanceRef VMA_INT_1_sqmuxa_0_a3_0)) - (portRef I0 (instanceRef VMA_INT_0_n)) - (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_1)) + (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_1_0)) (portRef D (instanceRef CLK_000_DD)) )) (net CLK_000_DD (joined @@ -751,7 +725,8 @@ (net CLK_OUT_PRE (joined (portRef Q (instanceRef CLK_OUT_PRE)) (portRef I1 (instanceRef CLK_OUT_PRE_0)) - (portRef I0 (instanceRef DSACK_INT_1_sqmuxa_2)) + (portRef I0 (instanceRef CLK_OUT_PRE_i)) + (portRef I1 (instanceRef un1_DSACK_INT_0_sqmuxa_i_a2_1)) (portRef D (instanceRef CLK_OUT_INT)) )) (net VCC (joined @@ -759,22 +734,22 @@ (portRef I0 (instanceRef AVEC)) (portRef I0 (instanceRef DSACK_0)) )) - (net (rename cpu_est_0 "cpu_est[0]") (joined - (portRef Q (instanceRef cpu_est_0)) - (portRef I0 (instanceRef clk_cpu_est_11_0_o4_3)) - (portRef I1 (instanceRef cpu_est_0_0)) - (portRef I0 (instanceRef cpu_est_i_0)) - (portRef I1 (instanceRef clk_cpu_est_11_0_a4_1_1)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_0_2_0_6)) - (portRef I1 (instanceRef clk_cpu_est_11_i_a4_1_2)) - (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_2)) + (net (rename cpu_est_d_1 "cpu_est_d[1]") (joined + (portRef Q (instanceRef cpu_est_d_1)) + (portRef I1 (instanceRef state_machine_un13_clk_000_d_4_1)) + )) + (net (rename cpu_est_d_2 "cpu_est_d[2]") (joined + (portRef Q (instanceRef cpu_est_d_2)) + (portRef I1 (instanceRef state_machine_un13_clk_000_d_4)) )) (net (rename cpu_est_2 "cpu_est[2]") (joined (portRef Q (instanceRef cpu_est_2)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_0_2_6)) (portRef I0 (instanceRef cpu_est_0_2__n)) + (portRef I1 (instanceRef clk_cpu_est_11_i_o4_2)) (portRef I0 (instanceRef cpu_est_i_2)) - (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa)) + (portRef I1 (instanceRef state_machine_un8_clk_000_d_3)) + (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1_0)) + (portRef D (instanceRef cpu_est_d_2)) )) (net (rename CLK_CNT_0 "CLK_CNT[0]") (joined (portRef Q (instanceRef CLK_CNT_0)) @@ -783,12 +758,13 @@ )) (net (rename SM_AMIGA_6 "SM_AMIGA[6]") (joined (portRef Q (instanceRef SM_AMIGA_6)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_o2_2)) + (portRef I1 (instanceRef SM_AMIGA_ns_a2_0_2)) (portRef I0 (instanceRef SM_AMIGA_i_6)) + (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa_1_2)) )) (net (rename SM_AMIGA_7 "SM_AMIGA[7]") (joined (portRef Q (instanceRef SM_AMIGA_7)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_o2_1)) + (portRef I1 (instanceRef SM_AMIGA_ns_a2_0)) (portRef I0 (instanceRef SM_AMIGA_i_7)) )) (net UDS_000_INT (joined @@ -801,6 +777,10 @@ (portRef I0 (instanceRef LDS_000_INT_0_m)) (portRef I0 (instanceRef LDS_000)) )) + (net (rename clk_RISING_CLK_AMIGA_1 "clk.RISING_CLK_AMIGA_1") (joined + (portRef O (instanceRef clk_RISING_CLK_AMIGA_1)) + (portRef D (instanceRef RISING_CLK_AMIGA)) + )) (net RISING_CLK_AMIGA (joined (portRef Q (instanceRef RISING_CLK_AMIGA)) (portRef I1 (instanceRef IPL_030_0_0__m)) @@ -811,6 +791,16 @@ (portRef I0 (instanceRef IPL_030_0_2__r)) (portRef I0 (instanceRef RISING_CLK_AMIGA_i)) )) + (net (rename state_machine_un57_clk_000_d "state_machine.un57_clk_000_d") (joined + (portRef O (instanceRef state_machine_un57_clk_000_d_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_a2_0_5)) + )) + (net (rename SM_AMIGA_1 "SM_AMIGA[1]") (joined + (portRef Q (instanceRef SM_AMIGA_1)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_o2_6)) + (portRef I0 (instanceRef SM_AMIGA_i_1)) + (portRef I1 (instanceRef un1_DSACK_INT_0_sqmuxa_i_a2)) + )) (net (rename DSACK_INT_1 "DSACK_INT[1]") (joined (portRef Q (instanceRef DSACK_INT_1)) (portRef I0 (instanceRef DSACK_INT_0_1__m)) @@ -827,147 +817,102 @@ )) (net (rename SM_AMIGA_3 "SM_AMIGA[3]") (joined (portRef Q (instanceRef SM_AMIGA_3)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_4)) (portRef I0 (instanceRef SM_AMIGA_i_3)) - (portRef I1 (instanceRef SM_AMIGA_ns_a3_0_4)) - (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_1_0)) - (portRef I1 (instanceRef SM_AMIGA_ns_a3_5)) + (portRef I1 (instanceRef DTACK_SYNC_1_sqmuxa_1_0)) + (portRef I1 (instanceRef SM_AMIGA_ns_a2_0_1_5)) + )) + (net (rename state_machine_un13_as_000_int "state_machine.un13_as_000_int") (joined + (portRef O (instanceRef state_machine_un13_as_000_int)) + (portRef I0 (instanceRef state_machine_un13_as_000_int_i)) )) (net (rename SM_AMIGA_5 "SM_AMIGA[5]") (joined (portRef Q (instanceRef SM_AMIGA_5)) (portRef I0 (instanceRef SM_AMIGA_i_5)) - )) - (net (rename un1_CLK_000_CNT_3 "un1_CLK_000_CNT[3]") (joined - (portRef O (instanceRef un1_CLK_000_CNT_3)) - (portRef I0 (instanceRef un1_CLK_000_CNT_i_3)) - (portRef I1 (instanceRef G_128)) - (portRef I1 (instanceRef G_129)) - )) - (net (rename CLK_000_CNT_0 "CLK_000_CNT[0]") (joined - (portRef Q (instanceRef CLK_000_CNT_0)) - (portRef I0 (instanceRef un1_CLK_000_CNT_3)) - (portRef I0 (instanceRef CLK_000_CNT_i_0)) - )) - (net (rename CLK_000_CNT_1 "CLK_000_CNT[1]") (joined - (portRef Q (instanceRef CLK_000_CNT_1)) - (portRef I0 (instanceRef un1_CLK_000_CNT_2)) - (portRef I0 (instanceRef G_129)) - (portRef I0 (instanceRef CLK_000_CNT_i_1)) - )) - (net (rename CLK_000_CNT_2 "CLK_000_CNT[2]") (joined - (portRef Q (instanceRef CLK_000_CNT_2)) - (portRef I0 (instanceRef un1_CLK_000_CNT_1)) - (portRef I0 (instanceRef G_131)) - (portRef I0 (instanceRef CLK_000_CNT_i_2)) - )) - (net (rename CLK_000_CNT_3 "CLK_000_CNT[3]") (joined - (portRef Q (instanceRef CLK_000_CNT_3)) - (portRef I0 (instanceRef un1_CLK_000_CNT_0)) - (portRef I0 (instanceRef CLK_000_CNT_i_3)) - )) - (net (rename state_machine_un14_as_000_int "state_machine.un14_as_000_int") (joined - (portRef O (instanceRef state_machine_un14_as_000_int)) - (portRef I0 (instanceRef state_machine_un14_as_000_int_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_a2_2)) )) (net (rename SM_AMIGA_2 "SM_AMIGA[2]") (joined (portRef Q (instanceRef SM_AMIGA_2)) + (portRef I1 (instanceRef SM_AMIGA_ns_a2_5)) (portRef I0 (instanceRef SM_AMIGA_i_2)) - (portRef I1 (instanceRef SM_AMIGA_ns_a3_0_5)) - )) - (net (rename SM_AMIGA_1 "SM_AMIGA[1]") (joined - (portRef Q (instanceRef SM_AMIGA_1)) - (portRef I0 (instanceRef SM_AMIGA_i_1)) - (portRef I1 (instanceRef SM_AMIGA_ns_a3_0_7)) )) (net (rename SM_AMIGA_0 "SM_AMIGA[0]") (joined (portRef Q (instanceRef SM_AMIGA_0)) - (portRef I1 (instanceRef SM_AMIGA_ns_a3_7)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_o2_0)) + (portRef I0 (instanceRef SM_AMIGA_ns_a2_0_0)) (portRef I0 (instanceRef SM_AMIGA_i_0)) - (portRef I1 (instanceRef DSACK_INT_1_sqmuxa_2)) + (portRef I0 (instanceRef SM_AMIGA_ns_a2_7)) )) (net (rename SM_AMIGA_D_0 "SM_AMIGA_D[0]") (joined (portRef Q (instanceRef SM_AMIGA_D_0)) (portRef I0 (instanceRef SM_AMIGA_D_0_0__n)) - (portRef I1 (instanceRef G_122)) + (portRef I1 (instanceRef G_98)) )) (net (rename SM_AMIGA_D_1 "SM_AMIGA_D[1]") (joined (portRef Q (instanceRef SM_AMIGA_D_1)) - (portRef I1 (instanceRef G_123)) (portRef I0 (instanceRef SM_AMIGA_D_0_1__n)) + (portRef I1 (instanceRef G_99)) )) (net (rename SM_AMIGA_D_2 "SM_AMIGA_D[2]") (joined (portRef Q (instanceRef SM_AMIGA_D_2)) - (portRef I1 (instanceRef G_124)) + (portRef I1 (instanceRef G_100)) (portRef I0 (instanceRef SM_AMIGA_D_0_2__n)) )) (net (rename clk_expZ0 "clk_exp") (joined - (portRef O (instanceRef G_125)) + (portRef O (instanceRef G_101)) (portRef I0 (instanceRef clk_exp_i)) )) - (net (rename clk_CLK_000_CNT_3_1 "clk.CLK_000_CNT_3[1]") (joined - (portRef O (instanceRef G_128)) - (portRef D (instanceRef CLK_000_CNT_1)) - )) - (net (rename clk_CLK_000_CNT_3_2 "clk.CLK_000_CNT_3[2]") (joined - (portRef O (instanceRef G_130)) - (portRef D (instanceRef CLK_000_CNT_2)) - )) - (net (rename clk_CLK_000_CNT_3_3 "clk.CLK_000_CNT_3[3]") (joined - (portRef O (instanceRef G_132)) - (portRef D (instanceRef CLK_000_CNT_3)) - )) (net N_1 (joined - (portRef O (instanceRef DSACK_INT_0_1__p)) - (portRef D (instanceRef DSACK_INT_1)) - )) - (net N_2 (joined (portRef O (instanceRef UDS_000_INT_0_p)) (portRef D (instanceRef UDS_000_INT)) )) - (net N_3 (joined + (net N_2 (joined (portRef O (instanceRef LDS_000_INT_0_p)) (portRef D (instanceRef LDS_000_INT)) )) - (net N_4 (joined + (net N_3 (joined (portRef O (instanceRef DTACK_SYNC_0_p)) (portRef D (instanceRef DTACK_SYNC)) )) - (net N_5 (joined + (net N_4 (joined (portRef O (instanceRef FPU_CS_INT_0_p)) (portRef D (instanceRef FPU_CS_INT)) )) - (net N_6 (joined - (portRef O (instanceRef AS_030_000_SYNC_0_p)) - (portRef D (instanceRef AS_030_000_SYNC)) - )) - (net N_7 (joined - (portRef O (instanceRef SM_AMIGA_D_0_0__p)) - (portRef D (instanceRef SM_AMIGA_D_0)) - )) - (net N_8 (joined - (portRef O (instanceRef SM_AMIGA_D_0_1__p)) - (portRef D (instanceRef SM_AMIGA_D_1)) - )) - (net N_9 (joined - (portRef O (instanceRef SM_AMIGA_D_0_2__p)) - (portRef D (instanceRef SM_AMIGA_D_2)) - )) - (net N_10 (joined - (portRef O (instanceRef VPA_SYNC_0_p)) - (portRef D (instanceRef VPA_SYNC)) - )) - (net N_11 (joined - (portRef O (instanceRef BG_000_0_p)) - (portRef D (instanceRef BG_000DFFSH)) - )) - (net N_12 (joined + (net N_5 (joined (portRef O (instanceRef AS_000_INT_0_p)) (portRef D (instanceRef AS_000_INT)) )) - (net N_13 (joined + (net N_6 (joined + (portRef O (instanceRef VPA_SYNC_0_p)) + (portRef D (instanceRef VPA_SYNC)) + )) + (net N_7 (joined + (portRef O (instanceRef AS_030_000_SYNC_0_p)) + (portRef D (instanceRef AS_030_000_SYNC)) + )) + (net N_8 (joined + (portRef O (instanceRef SM_AMIGA_D_0_0__p)) + (portRef D (instanceRef SM_AMIGA_D_0)) + )) + (net N_9 (joined + (portRef O (instanceRef SM_AMIGA_D_0_1__p)) + (portRef D (instanceRef SM_AMIGA_D_1)) + )) + (net N_10 (joined + (portRef O (instanceRef SM_AMIGA_D_0_2__p)) + (portRef D (instanceRef SM_AMIGA_D_2)) + )) + (net N_11 (joined (portRef O (instanceRef VMA_INT_0_p)) (portRef D (instanceRef VMA_INT)) )) + (net N_12 (joined + (portRef O (instanceRef BG_000_0_p)) + (portRef D (instanceRef BG_000DFFSH)) + )) + (net N_13 (joined + (portRef O (instanceRef DSACK_INT_0_1__p)) + (portRef D (instanceRef DSACK_INT_1)) + )) (net N_14 (joined (portRef O (instanceRef IPL_030_0_0__p)) (portRef D (instanceRef IPL_030DFFSH_0)) @@ -1004,9 +949,13 @@ (portRef O (instanceRef CLK_OUT_PRE_0)) (portRef D (instanceRef CLK_OUT_PRE)) )) - (net (rename SM_AMIGA_ns_4 "SM_AMIGA_ns[4]") (joined - (portRef O (instanceRef SM_AMIGA_ns_i_4)) - (portRef D (instanceRef SM_AMIGA_3)) + (net (rename SM_AMIGA_ns_0 "SM_AMIGA_ns[0]") (joined + (portRef O (instanceRef SM_AMIGA_ns_i_0)) + (portRef D (instanceRef SM_AMIGA_7)) + )) + (net (rename SM_AMIGA_ns_2 "SM_AMIGA_ns[2]") (joined + (portRef O (instanceRef SM_AMIGA_ns_i_2)) + (portRef D (instanceRef SM_AMIGA_5)) )) (net (rename SM_AMIGA_ns_5 "SM_AMIGA_ns[5]") (joined (portRef O (instanceRef SM_AMIGA_ns_i_5)) @@ -1016,156 +965,165 @@ (portRef O (instanceRef SM_AMIGA_ns_i_7)) (portRef D (instanceRef SM_AMIGA_0)) )) - (net N_123 (joined - (portRef O (instanceRef state_machine_un9_clk_000_d_i_o3_i)) - (portRef I0 (instanceRef SM_AMIGA_ns_a3_7)) + (net N_106 (joined + (portRef O (instanceRef un9_i_a2_2)) + (portRef I0 (instanceRef N_106_i)) + (portRef I0 (instanceRef G_98)) )) - (net (rename clk_RISING_CLK_AMIGA_1 "clk.RISING_CLK_AMIGA_1") (joined - (portRef O (instanceRef clk_RISING_CLK_AMIGA_1_0_a3)) - (portRef I0 (instanceRef clk_RISING_CLK_AMIGA_1_i)) - (portRef D (instanceRef RISING_CLK_AMIGA)) + (net N_107 (joined + (portRef O (instanceRef un9_i_a2_1)) + (portRef I0 (instanceRef N_107_i)) + (portRef I0 (instanceRef G_99)) )) - (net N_213 (joined - (portRef O (instanceRef G_122)) - (portRef I1 (instanceRef G_125_1)) + (net (rename clk_un3_clk_000_dd "clk.un3_clk_000_dd") (joined + (portRef O (instanceRef clk_un3_clk_000_dd_0_a2)) + (portRef I1 (instanceRef cpu_est_0_3__m)) + (portRef I0 (instanceRef cpu_est_0_3__r)) + (portRef I1 (instanceRef cpu_est_0_2__m)) + (portRef I0 (instanceRef cpu_est_0_2__r)) + (portRef I1 (instanceRef cpu_est_0_1__m)) + (portRef I0 (instanceRef cpu_est_0_1__r)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_1)) + (portRef I0 (instanceRef cpu_est_0_0)) + (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa_1)) )) - (net N_214 (joined - (portRef O (instanceRef G_123)) - (portRef I1 (instanceRef G_125)) + (net (rename clk_cpu_est_11_1 "clk.cpu_est_11[1]") (joined + (portRef O (instanceRef clk_cpu_est_11_0_i_1)) + (portRef I0 (instanceRef cpu_est_0_1__m)) )) - (net N_215 (joined - (portRef O (instanceRef G_124)) - (portRef I0 (instanceRef G_125_1)) + (net (rename clk_cpu_est_11_3 "clk.cpu_est_11[3]") (joined + (portRef O (instanceRef clk_cpu_est_11_0_i_3)) + (portRef I0 (instanceRef cpu_est_0_3__m)) )) - (net DSACK_INT_1_sqmuxa (joined - (portRef O (instanceRef DSACK_INT_1_sqmuxa)) - (portRef I0 (instanceRef DSACK_INT_1_sqmuxa_i)) + (net N_162 (joined + (portRef O (instanceRef G_98)) + (portRef I1 (instanceRef G_101_1)) )) - (net N_120 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_o2_i_2)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_a3_2)) + (net N_163 (joined + (portRef O (instanceRef G_99)) + (portRef I1 (instanceRef G_101)) )) - (net N_144_1 (joined - (portRef O (instanceRef SM_AMIGA_ns_a3_0_1_7)) - (portRef I0 (instanceRef SM_AMIGA_ns_a3_0_7)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_a3_6)) + (net N_164 (joined + (portRef O (instanceRef G_100)) + (portRef I0 (instanceRef G_101_1)) )) - (net N_251 (joined - (portRef O (instanceRef un8_ciin)) - (portRef OE (instanceRef CIIN)) + (net N_161 (joined + (portRef O (instanceRef un2_clk_030_1_106)) + (portRef I1 (instanceRef un2_clk_030_1)) + (portRef I0 (instanceRef N_161_i)) )) - (net N_254 (joined - (portRef O (instanceRef un4_ciin)) - (portRef I0 (instanceRef CIIN)) + (net N_114 (joined + (portRef O (instanceRef SM_AMIGA_ns_a2_0_2)) + (portRef I0 (instanceRef N_114_i)) )) - (net N_186 (joined - (portRef O (instanceRef G_131)) - (portRef I0 (instanceRef G_132)) + (net N_109 (joined + (portRef O (instanceRef state_machine_un5_clk_030_i_a2)) + (portRef I0 (instanceRef N_109_i)) )) - (net (rename un1_CLK_000_CNT_0 "un1_CLK_000_CNT[0]") (joined - (portRef O (instanceRef un1_CLK_000_CNT_0)) - (portRef I1 (instanceRef G_132)) + (net N_111 (joined + (portRef O (instanceRef SM_AMIGA_ns_a2_0)) + (portRef I0 (instanceRef N_111_i)) )) - (net N_184 (joined - (portRef O (instanceRef G_129)) - (portRef I0 (instanceRef G_130)) - (portRef I1 (instanceRef G_131)) + (net N_112 (joined + (portRef O (instanceRef SM_AMIGA_ns_a2_0_0)) + (portRef I0 (instanceRef N_112_i)) )) - (net (rename un1_CLK_000_CNT_1 "un1_CLK_000_CNT[1]") (joined - (portRef O (instanceRef un1_CLK_000_CNT_1)) - (portRef I1 (instanceRef G_130)) + (net N_122 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_a2_1)) + (portRef I0 (instanceRef SM_AMIGA_ns_a2_0_2)) + (portRef I0 (instanceRef N_122_i)) )) - (net (rename un1_CLK_000_CNT_2 "un1_CLK_000_CNT[2]") (joined - (portRef O (instanceRef un1_CLK_000_CNT_2)) - (portRef I0 (instanceRef G_128)) + (net N_115 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_a2_4)) + (portRef I0 (instanceRef N_115_i)) )) - (net (rename state_machine_un69_clk_000_d "state_machine.un69_clk_000_d") (joined - (portRef O (instanceRef G_150_i)) - (portRef I1 (instanceRef state_machine_un80_clk_000_d)) - (portRef I1 (instanceRef state_machine_un67_clk_000_d)) + (net N_101 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_o2_i_4)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_4)) )) - (net (rename state_machine_un78_clk_000_d "state_machine.un78_clk_000_d") (joined - (portRef O (instanceRef state_machine_un78_clk_000_d_i)) - (portRef I1 (instanceRef DSACK_INT_1_sqmuxa)) + (net N_116 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_a2_0_4)) + (portRef I0 (instanceRef N_116_i)) )) - (net N_149 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_a2_0_6)) - (portRef I0 (instanceRef N_149_i)) - )) - (net N_119 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_o2_i_6)) - (portRef I1 (instanceRef SM_AMIGA_ns_a3_0_1_7)) - )) - (net N_135 (joined - (portRef O (instanceRef clk_un1_clk_000_i_a3)) - (portRef I0 (instanceRef N_135_i)) - )) - (net (rename state_machine_un67_clk_000_d "state_machine.un67_clk_000_d") (joined - (portRef O (instanceRef state_machine_un67_clk_000_d)) - (portRef I0 (instanceRef state_machine_un67_clk_000_d_i)) - )) - (net (rename state_machine_un80_clk_000_d "state_machine.un80_clk_000_d") (joined - (portRef O (instanceRef state_machine_un80_clk_000_d)) - (portRef I0 (instanceRef state_machine_un80_clk_000_d_i)) - )) - (net N_132 (joined - (portRef O (instanceRef un9_i_a3_0)) - (portRef I0 (instanceRef G_124)) - (portRef I0 (instanceRef N_132_i)) - )) - (net N_131 (joined - (portRef O (instanceRef un9_i_a3_1)) - (portRef I0 (instanceRef G_123)) - (portRef I0 (instanceRef N_131_i)) - )) - (net (rename state_machine_un25_clk_000_d "state_machine.un25_clk_000_d") (joined - (portRef O (instanceRef state_machine_un25_clk_000_d_i_0)) - (portRef I0 (instanceRef state_machine_LDS_000_INT_8)) - )) - (net N_150 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_a2_6)) - (portRef I0 (instanceRef N_150_i)) - (portRef I0 (instanceRef un9_i_a3_1_0)) - )) - (net N_151 (joined + (net N_124 (joined (portRef O (instanceRef SM_AMIGA_ns_i_a2_3)) - (portRef I0 (instanceRef N_151_i)) - (portRef I0 (instanceRef un9_i_a3_1_1)) + (portRef I0 (instanceRef N_124_i)) + (portRef I0 (instanceRef un9_i_a2_1_1)) )) - (net N_144 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_a3_6)) - (portRef I0 (instanceRef N_144_i)) + (net N_139 (joined + (portRef O (instanceRef clk_cpu_est_11_0_a4_1)) + (portRef I0 (instanceRef N_139_i)) + )) + (net N_137 (joined + (portRef O (instanceRef clk_cpu_est_11_0_o4_i_1)) + (portRef I0 (instanceRef clk_cpu_est_11_0_a4_1)) + )) + (net N_140 (joined + (portRef O (instanceRef clk_cpu_est_11_0_a4_0_1)) + (portRef I0 (instanceRef N_140_i)) + )) + (net N_141 (joined + (portRef O (instanceRef clk_cpu_est_11_0_a4_1_1)) + (portRef I0 (instanceRef N_141_i)) + )) + (net N_136 (joined + (portRef O (instanceRef clk_cpu_est_11_i_o4_i_2)) + (portRef I0 (instanceRef clk_cpu_est_11_i_a4_1_2)) + )) + (net N_142 (joined + (portRef O (instanceRef clk_cpu_est_11_0_a4_2_1)) + (portRef I0 (instanceRef N_142_i)) + )) + (net N_145 (joined + (portRef O (instanceRef clk_cpu_est_11_0_a4_3)) + (portRef I0 (instanceRef N_145_i)) + )) + (net N_138 (joined + (portRef O (instanceRef clk_cpu_est_11_0_o4_i_3)) + (portRef I0 (instanceRef clk_cpu_est_11_0_a4_3)) )) (net N_146 (joined - (portRef O (instanceRef SM_AMIGA_ns_a3_0_7)) + (portRef O (instanceRef clk_cpu_est_11_0_a4_0_3)) (portRef I0 (instanceRef N_146_i)) )) (net N_143 (joined - (portRef O (instanceRef SM_AMIGA_ns_a3_0_5)) + (portRef O (instanceRef clk_cpu_est_11_i_a4_2)) (portRef I0 (instanceRef N_143_i)) )) - (net N_145 (joined - (portRef O (instanceRef SM_AMIGA_ns_a3_7)) - (portRef I0 (instanceRef N_145_i)) + (net N_144 (joined + (portRef O (instanceRef clk_cpu_est_11_i_a4_0_2)) + (portRef I0 (instanceRef N_144_i)) )) - (net (rename state_machine_LDS_000_INT_8 "state_machine.LDS_000_INT_8") (joined - (portRef O (instanceRef state_machine_LDS_000_INT_8_i)) - (portRef I0 (instanceRef LDS_000_INT_0_n)) + (net UDS_000_INT_0_sqmuxa (joined + (portRef O (instanceRef UDS_000_INT_0_sqmuxa)) + (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_i)) )) - (net un1_UDS_000_INT_0_sqmuxa_2 (joined - (portRef O (instanceRef un1_UDS_000_INT_0_sqmuxa_2_i)) - (portRef I1 (instanceRef LDS_000_INT_0_sqmuxa)) + (net UDS_000_INT_0_sqmuxa_1 (joined + (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1)) + (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_1_i)) )) - (net (rename state_machine_UDS_000_INT_8 "state_machine.UDS_000_INT_8") (joined - (portRef O (instanceRef state_machine_UDS_000_INT_8_i)) - (portRef I0 (instanceRef UDS_000_INT_0_n)) + (net N_147 (joined + (portRef O (instanceRef clk_cpu_est_11_0_a4_1_3)) + (portRef I0 (instanceRef N_147_i)) )) - (net LDS_000_INT_0_sqmuxa (joined - (portRef O (instanceRef LDS_000_INT_0_sqmuxa)) - (portRef I1 (instanceRef UDS_000_INT_0_m)) - (portRef I0 (instanceRef UDS_000_INT_0_r)) - (portRef I1 (instanceRef LDS_000_INT_0_m)) - (portRef I0 (instanceRef LDS_000_INT_0_r)) + (net N_147_1 (joined + (portRef O (instanceRef VPA_SYNC_1_sqmuxa_3)) + (portRef I0 (instanceRef clk_cpu_est_11_0_a4_1_3)) + (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_2)) + )) + (net (rename state_machine_un13_clk_000_d_1 "state_machine.un13_clk_000_d_1") (joined + (portRef O (instanceRef state_machine_un13_clk_000_d_1)) + (portRef I1 (instanceRef SM_AMIGA_ns_a2_0_0)) + (portRef I0 (instanceRef state_machine_un13_clk_000_d_1_i)) + (portRef I0 (instanceRef state_machine_un13_clk_000_d_4_1)) + )) + (net N_186 (joined + (portRef O (instanceRef un8_ciin)) + (portRef OE (instanceRef CIIN)) + )) + (net N_189 (joined + (portRef O (instanceRef un4_ciin)) + (portRef I0 (instanceRef CIIN)) )) (net (rename state_machine_un42_clk_030 "state_machine.un42_clk_030") (joined (portRef O (instanceRef state_machine_un42_clk_030)) @@ -1176,31 +1134,10 @@ (portRef O (instanceRef un1_bg_030_i)) (portRef I0 (instanceRef BG_000_0_m)) )) - (net N_133 (joined - (portRef O (instanceRef state_machine_un5_clk_030_i_a3)) - (portRef I0 (instanceRef N_133_i)) - )) (net (rename state_machine_AS_030_000_SYNC_3 "state_machine.AS_030_000_SYNC_3") (joined (portRef O (instanceRef state_machine_AS_030_000_SYNC_3_i)) (portRef I0 (instanceRef AS_030_000_SYNC_0_m)) )) - (net N_125 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_o2_i_1)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_a3_1)) - )) - (net N_137 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_a3_1)) - (portRef I0 (instanceRef N_137_i)) - )) - (net N_138 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_a3_0_1)) - (portRef I0 (instanceRef N_138_i)) - )) - (net DSACK_INT_1_sqmuxa_1 (joined - (portRef O (instanceRef DSACK_INT_1_sqmuxa_1)) - (portRef I1 (instanceRef DSACK_INT_0_1__m)) - (portRef I0 (instanceRef DSACK_INT_0_1__r)) - )) (net un1_as_030_2 (joined (portRef O (instanceRef un1_as_030_2_i)) (portRef I0 (instanceRef FPU_CS_INT_0_m)) @@ -1222,173 +1159,113 @@ (portRef I1 (instanceRef BGACK_030_INT_0_m)) (portRef I0 (instanceRef BGACK_030_INT_0_r)) )) - (net VPA_SYNC_1_sqmuxa (joined - (portRef O (instanceRef VPA_SYNC_1_sqmuxa)) - (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_i)) + (net N_108 (joined + (portRef O (instanceRef un9_i_a2_0)) + (portRef I0 (instanceRef G_100)) + (portRef I0 (instanceRef N_108_i)) )) - (net VPA_SYNC_1_sqmuxa_1 (joined - (portRef O (instanceRef VPA_SYNC_1_sqmuxa_1)) - (portRef I1 (instanceRef VPA_SYNC_0_m)) - (portRef I0 (instanceRef VPA_SYNC_0_r)) + (net (rename state_machine_un31_clk_000_d "state_machine.un31_clk_000_d") (joined + (portRef O (instanceRef state_machine_un31_clk_000_d_i_0)) + (portRef I1 (instanceRef state_machine_LDS_000_INT_8)) )) - (net N_122 (joined - (portRef O (instanceRef un1_SM_AMIGA_i_o2_i)) - (portRef I1 (instanceRef AS_000_INT_1_sqmuxa)) - (portRef I0 (instanceRef AS_000_INT_0_n)) - (portRef I0 (instanceRef un1_UDS_000_INT_0_sqmuxa_1)) + (net (rename state_machine_un13_clk_000_d "state_machine.un13_clk_000_d") (joined + (portRef O (instanceRef state_machine_un13_clk_000_d)) + (portRef I0 (instanceRef state_machine_un13_clk_000_d_i)) )) - (net AS_000_INT_1_sqmuxa (joined - (portRef O (instanceRef AS_000_INT_1_sqmuxa)) - (portRef I1 (instanceRef AS_000_INT_0_m)) - (portRef I0 (instanceRef AS_000_INT_0_r)) + (net (rename state_machine_un13_clk_000_d_4 "state_machine.un13_clk_000_d_4") (joined + (portRef O (instanceRef state_machine_un13_clk_000_d_4)) + (portRef I0 (instanceRef VMA_INT_0_n)) + (portRef I1 (instanceRef state_machine_un13_clk_000_d)) )) - (net N_136 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_a3_0)) - (portRef I0 (instanceRef N_136_i)) - )) - (net N_124 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_o2_i_0)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_a3_0)) - )) - (net N_130 (joined - (portRef O (instanceRef un9_i_a3_2)) - (portRef I0 (instanceRef N_130_i)) - (portRef I0 (instanceRef G_122)) - )) - (net (rename state_machine_un15_clk_000_d "state_machine.un15_clk_000_d") (joined - (portRef O (instanceRef state_machine_un15_clk_000_d)) - (portRef I0 (instanceRef state_machine_un15_clk_000_d_i)) - )) - (net un1_UDS_000_INT_0_sqmuxa (joined - (portRef O (instanceRef un1_UDS_000_INT_0_sqmuxa_i_0)) - (portRef I1 (instanceRef un1_UDS_000_INT_0_sqmuxa_2)) - )) - (net UDS_000_INT_0_sqmuxa (joined - (portRef O (instanceRef UDS_000_INT_0_sqmuxa)) - (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_i)) - )) - (net LDS_000_INT_1_sqmuxa (joined - (portRef O (instanceRef LDS_000_INT_1_sqmuxa)) - (portRef I0 (instanceRef LDS_000_INT_1_sqmuxa_i)) - )) - (net N_139 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_a3_2)) - (portRef I0 (instanceRef N_139_i)) - )) - (net N_140 (joined - (portRef O (instanceRef SM_AMIGA_ns_a3_4)) - (portRef I0 (instanceRef N_140_i)) - )) - (net N_126 (joined - (portRef O (instanceRef SM_AMIGA_ns_o2_i_4)) - (portRef I1 (instanceRef SM_AMIGA_ns_a3_4)) - )) - (net N_141 (joined - (portRef O (instanceRef SM_AMIGA_ns_a3_0_4)) - (portRef I0 (instanceRef N_141_i)) - )) - (net N_121 (joined - (portRef O (instanceRef SM_AMIGA_ns_o2_i_5)) - (portRef I1 (instanceRef SM_AMIGA_ns_a3_1_5)) - )) - (net N_142 (joined - (portRef O (instanceRef SM_AMIGA_ns_a3_5)) - (portRef I0 (instanceRef N_142_i)) - )) - (net VPA_SYNC_1_sqmuxa_1_0 (joined - (portRef O (instanceRef VPA_SYNC_1_sqmuxa_1_0)) - (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_2)) - (portRef I1 (instanceRef DTACK_SYNC_1_sqmuxa)) + (net (rename state_machine_un8_clk_000_d "state_machine.un8_clk_000_d") (joined + (portRef O (instanceRef state_machine_un8_clk_000_d)) + (portRef I0 (instanceRef state_machine_un8_clk_000_d_i)) )) (net DTACK_SYNC_1_sqmuxa (joined (portRef O (instanceRef DTACK_SYNC_1_sqmuxa)) (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa_i)) )) + (net VPA_SYNC_1_sqmuxa_1_0 (joined + (portRef O (instanceRef DTACK_SYNC_1_sqmuxa_1_0)) + (portRef I1 (instanceRef DTACK_SYNC_1_sqmuxa)) + (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_3_0)) + )) + (net VPA_SYNC_1_sqmuxa (joined + (portRef O (instanceRef VPA_SYNC_1_sqmuxa)) + (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_i)) + )) + (net N_123 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_a2_0_6)) + (portRef I0 (instanceRef N_123_i)) + (portRef I0 (instanceRef un9_i_a2_1_0)) + )) + (net N_118 (joined + (portRef O (instanceRef SM_AMIGA_ns_a2_0_5)) + (portRef I0 (instanceRef N_118_i)) + )) + (net N_110 (joined + (portRef O (instanceRef un1_DSACK_INT_0_sqmuxa_i_a2)) + (portRef I0 (instanceRef N_110_i)) + )) + (net N_102 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_o2_i_6)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_6)) + )) + (net N_120 (joined + (portRef O (instanceRef SM_AMIGA_ns_a2_7)) + (portRef I0 (instanceRef N_120_i)) + )) + (net N_119 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_a2_6)) + (portRef I0 (instanceRef N_119_i)) + )) + (net N_117 (joined + (portRef O (instanceRef SM_AMIGA_ns_a2_5)) + (portRef I0 (instanceRef N_117_i)) + )) + (net N_113 (joined + (portRef O (instanceRef SM_AMIGA_ns_a2_2)) + (portRef I0 (instanceRef N_113_i)) + )) + (net (rename state_machine_LDS_000_INT_8 "state_machine.LDS_000_INT_8") (joined + (portRef O (instanceRef state_machine_LDS_000_INT_8_i)) + (portRef I0 (instanceRef LDS_000_INT_0_n)) + )) + (net (rename state_machine_UDS_000_INT_8 "state_machine.UDS_000_INT_8") (joined + (portRef O (instanceRef state_machine_UDS_000_INT_8_i)) + (portRef I0 (instanceRef UDS_000_INT_0_n)) + )) (net DTACK_SYNC_1_sqmuxa_1 (joined (portRef O (instanceRef DTACK_SYNC_1_sqmuxa_1)) (portRef I1 (instanceRef DTACK_SYNC_0_m)) (portRef I0 (instanceRef DTACK_SYNC_0_r)) )) - (net N_149_2 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_a2_0_2_6)) - (portRef I0 (instanceRef clk_cpu_est_11_0_a4_2_1)) - (portRef I0 (instanceRef N_149_2_i)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_0_1_6)) + (net un2_clk_030_1 (joined + (portRef O (instanceRef un2_clk_030_1)) + (portRef I1 (instanceRef UDS_000_INT_0_m)) + (portRef I0 (instanceRef UDS_000_INT_0_r)) + (portRef I1 (instanceRef LDS_000_INT_0_m)) + (portRef I0 (instanceRef LDS_000_INT_0_r)) )) - (net (rename clk_un3_clk_000_dd "clk.un3_clk_000_dd") (joined - (portRef O (instanceRef clk_un3_clk_000_dd)) - (portRef I0 (instanceRef cpu_est_0_0)) - (portRef I1 (instanceRef cpu_est_0_2__m)) - (portRef I0 (instanceRef cpu_est_0_2__r)) - (portRef I1 (instanceRef cpu_est_0_3__m)) - (portRef I0 (instanceRef cpu_est_0_3__r)) - (portRef I1 (instanceRef cpu_est_0_1__m)) - (portRef I0 (instanceRef cpu_est_0_1__r)) + (net VPA_SYNC_1_sqmuxa_1 (joined + (portRef O (instanceRef VPA_SYNC_1_sqmuxa_1)) + (portRef I1 (instanceRef VPA_SYNC_0_m)) + (portRef I0 (instanceRef VPA_SYNC_0_r)) )) - (net N_164 (joined - (portRef O (instanceRef clk_cpu_est_11_0_o4_i_1)) - (portRef I0 (instanceRef clk_cpu_est_11_0_a4_1)) - )) - (net N_171 (joined - (portRef O (instanceRef clk_cpu_est_11_i_a4_0_2)) - (portRef I0 (instanceRef N_171_i)) - )) - (net N_170 (joined - (portRef O (instanceRef clk_cpu_est_11_i_a4_2)) - (portRef I0 (instanceRef N_170_i)) - )) - (net (rename clk_cpu_est_11_3 "clk.cpu_est_11[3]") (joined - (portRef O (instanceRef clk_cpu_est_11_0_i_3)) - (portRef I0 (instanceRef cpu_est_0_3__m)) - )) - (net N_174 (joined - (portRef O (instanceRef clk_cpu_est_11_0_a4_1_3)) - (portRef I0 (instanceRef N_174_i)) - )) - (net N_172 (joined - (portRef O (instanceRef clk_cpu_est_11_0_a4_3)) - (portRef I0 (instanceRef N_172_i)) - )) - (net N_173 (joined - (portRef O (instanceRef clk_cpu_est_11_0_a4_0_3)) - (portRef I0 (instanceRef N_173_i)) - )) - (net (rename clk_cpu_est_11_1 "clk.cpu_est_11[1]") (joined - (portRef O (instanceRef clk_cpu_est_11_0_i_1)) - (portRef I0 (instanceRef cpu_est_0_1__m)) - )) - (net N_169 (joined - (portRef O (instanceRef clk_cpu_est_11_0_a4_2_1)) - (portRef I0 (instanceRef N_169_i)) - )) - (net N_167 (joined - (portRef O (instanceRef clk_cpu_est_11_0_a4_0_1)) - (portRef I0 (instanceRef N_167_i)) - )) - (net N_166 (joined - (portRef O (instanceRef clk_cpu_est_11_0_a4_1)) - (portRef I0 (instanceRef N_166_i)) - )) - (net N_168 (joined - (portRef O (instanceRef clk_cpu_est_11_0_a4_1_1)) - (portRef I0 (instanceRef N_168_i)) - )) - (net N_165 (joined - (portRef O (instanceRef clk_cpu_est_11_0_o4_i_3)) - (portRef I0 (instanceRef clk_cpu_est_11_0_a4_3)) + (net AS_000_INT_1_sqmuxa (joined + (portRef O (instanceRef AS_000_INT_1_sqmuxa)) + (portRef I1 (instanceRef AS_000_INT_0_m)) + (portRef I0 (instanceRef AS_000_INT_0_r)) )) (net VMA_INT_1_sqmuxa (joined - (portRef O (instanceRef VMA_INT_1_sqmuxa_0_i)) + (portRef O (instanceRef VMA_INT_1_sqmuxa)) (portRef I1 (instanceRef VMA_INT_0_m)) (portRef I0 (instanceRef VMA_INT_0_r)) )) - (net N_147 (joined - (portRef O (instanceRef VMA_INT_1_sqmuxa_0_a3)) - (portRef I0 (instanceRef N_147_i)) - )) - (net N_148 (joined - (portRef O (instanceRef VMA_INT_1_sqmuxa_0_a3_0)) - (portRef I0 (instanceRef N_148_i)) + (net DSACK_INT_1_sqmuxa (joined + (portRef O (instanceRef DSACK_INT_1_sqmuxa)) + (portRef I1 (instanceRef DSACK_INT_0_1__m)) + (portRef I0 (instanceRef DSACK_INT_0_1__r)) )) (net RW_i (joined (portRef O (instanceRef RW_i)) @@ -1399,147 +1276,123 @@ (portRef O (instanceRef clk_exp_i)) (portRef I0 (instanceRef CLK_EXP)) )) - (net CLK_000_DD_i (joined - (portRef O (instanceRef CLK_000_DD_i)) - (portRef I1 (instanceRef clk_un3_clk_000_dd)) - )) - (net CLK_000_D_i (joined - (portRef O (instanceRef CLK_000_D_i)) - (portRef I0 (instanceRef clk_RISING_CLK_AMIGA_1_0_a3)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_3)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_1)) - (portRef I0 (instanceRef SM_AMIGA_ns_a3_0_5)) - (portRef I0 (instanceRef VMA_INT_1_sqmuxa_0_a3)) - (portRef I1 (instanceRef DSACK_INT_1_sqmuxa_1_0)) - (portRef I0 (instanceRef SM_AMIGA_ns_a3_1_5)) - )) - (net AS_000_INT_i (joined - (portRef O (instanceRef AS_000_INT_i)) - (portRef I0 (instanceRef state_machine_un14_as_000_int)) - (portRef I0 (instanceRef VMA_INT_1_sqmuxa_0_a3_0)) - )) - (net (rename cpu_est_i_0 "cpu_est_i[0]") (joined - (portRef O (instanceRef cpu_est_i_0)) - (portRef I1 (instanceRef clk_cpu_est_11_0_a4_1)) - (portRef I1 (instanceRef clk_cpu_est_11_i_a4_0_1_2)) - (portRef I0 (instanceRef clk_cpu_est_11_0_a4_1_1_3)) - )) - (net (rename cpu_est_i_2 "cpu_est_i[2]") (joined - (portRef O (instanceRef cpu_est_i_2)) - (portRef I1 (instanceRef clk_cpu_est_11_0_a4_0_3)) - (portRef I0 (instanceRef clk_cpu_est_11_0_a4_0_1)) - (portRef I1 (instanceRef clk_cpu_est_11_i_a4_0_2)) - (portRef I1 (instanceRef clk_cpu_est_11_0_a4_1_3)) - )) - (net (rename cpu_est_i_3 "cpu_est_i[3]") (joined - (portRef O (instanceRef cpu_est_i_3)) - (portRef I1 (instanceRef clk_cpu_est_11_0_o4_1)) - (portRef I1 (instanceRef clk_cpu_est_11_0_a4_0_1)) - (portRef I1 (instanceRef clk_cpu_est_11_i_a4_2)) - )) - (net (rename cpu_est_i_1 "cpu_est_i[1]") (joined - (portRef O (instanceRef cpu_est_i_1)) - (portRef I0 (instanceRef clk_cpu_est_11_0_o4_1)) - (portRef I1 (instanceRef clk_cpu_est_11_0_a4_1_1_3)) - )) - (net N_149_2_i (joined - (portRef O (instanceRef N_149_2_i)) - (portRef I0 (instanceRef clk_cpu_est_11_i_a4_1_2)) - )) - (net VPA_D_i (joined - (portRef O (instanceRef VPA_D_i)) - (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_1_1)) - )) - (net DTACK_i (joined - (portRef O (instanceRef I_169)) - (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa_1_0)) - )) - (net VPA_SYNC_i (joined - (portRef O (instanceRef VPA_SYNC_i)) - (portRef I0 (instanceRef state_machine_un80_clk_000_d)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_0_1_6)) - )) - (net DTACK_SYNC_i (joined - (portRef O (instanceRef DTACK_SYNC_i)) - (portRef I0 (instanceRef state_machine_un67_clk_000_d)) - )) - (net AS_030_i (joined - (portRef O (instanceRef AS_030_i)) - (portRef I0 (instanceRef LDS_000_INT_0_sqmuxa)) - (portRef I0 (instanceRef state_machine_un17_clk_030)) - (portRef I0 (instanceRef un1_as_030_2)) - (portRef I0 (instanceRef DSACK_INT_1_sqmuxa_1)) - (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1)) - (portRef I0 (instanceRef AS_000_INT_1_sqmuxa)) - (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa_1)) - (portRef I0 (instanceRef state_machine_AS_030_000_SYNC_3_1)) - )) (net DTACK_SYNC_1_sqmuxa_i (joined (portRef O (instanceRef DTACK_SYNC_1_sqmuxa_i)) (portRef I1 (instanceRef DTACK_SYNC_1_sqmuxa_1)) (portRef I0 (instanceRef DTACK_SYNC_0_n)) )) - (net DS_030_i (joined - (portRef O (instanceRef DS_030_i)) - (portRef I0 (instanceRef state_machine_un15_clk_000_d)) - (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa_1)) - )) - (net (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (joined - (portRef O (instanceRef SM_AMIGA_i_4)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_3)) - (portRef I1 (instanceRef SM_AMIGA_ns_o2_4)) - (portRef I0 (instanceRef un9_i_a3_2_2)) - )) - (net (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (joined - (portRef O (instanceRef SM_AMIGA_i_6)) - (portRef I0 (instanceRef state_machine_un5_clk_030_i_a3)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_a3_1)) - (portRef I1 (instanceRef un9_i_a3_2_2)) - )) - (net (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (joined - (portRef O (instanceRef SM_AMIGA_i_5)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_3)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_a3_2)) - (portRef I1 (instanceRef un1_UDS_000_INT_0_sqmuxa_1)) - )) - (net N_139_i (joined - (portRef O (instanceRef N_139_i)) - (portRef I0 (instanceRef LDS_000_INT_1_sqmuxa)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_2)) - )) - (net (rename state_machine_un15_clk_000_d_i "state_machine.un15_clk_000_d_i") (joined - (portRef O (instanceRef state_machine_un15_clk_000_d_i)) - (portRef I1 (instanceRef LDS_000_INT_1_sqmuxa)) - )) - (net N_130_i (joined - (portRef O (instanceRef N_130_i)) - (portRef I0 (instanceRef SM_AMIGA_D_0_0__m)) - )) - (net (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (joined - (portRef O (instanceRef SM_AMIGA_i_0)) - (portRef I0 (instanceRef un9_i_a3_1_2)) - (portRef I1 (instanceRef un9_i_a3_1_1)) - (portRef I1 (instanceRef un9_i_a3_1_0)) - )) - (net (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (joined - (portRef O (instanceRef SM_AMIGA_i_7)) - (portRef I1 (instanceRef state_machine_un5_clk_030_i_a3)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_a3_0)) + (net N_114_i (joined + (portRef O (instanceRef N_114_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_2)) + (portRef I1 (instanceRef AS_000_INT_1_sqmuxa)) + (portRef I0 (instanceRef AS_000_INT_0_n)) )) (net VPA_SYNC_1_sqmuxa_i (joined (portRef O (instanceRef VPA_SYNC_1_sqmuxa_i)) (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_1)) (portRef I0 (instanceRef VPA_SYNC_0_n)) )) - (net (rename DSACK_i_1 "DSACK_i[1]") (joined - (portRef O (instanceRef I_170)) - (portRef I1 (instanceRef state_machine_un14_as_000_int)) - )) - (net DSACK_INT_1_sqmuxa_i (joined - (portRef O (instanceRef DSACK_INT_1_sqmuxa_i)) - (portRef I1 (instanceRef DSACK_INT_1_sqmuxa_1)) + (net N_110_i (joined + (portRef O (instanceRef N_110_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_7)) + (portRef I1 (instanceRef DSACK_INT_1_sqmuxa)) (portRef I0 (instanceRef DSACK_INT_0_1__n)) )) + (net N_108_i (joined + (portRef O (instanceRef N_108_i)) + (portRef I0 (instanceRef SM_AMIGA_D_0_2__m)) + )) + (net (rename cpu_est_d_i_3 "cpu_est_d_i[3]") (joined + (portRef O (instanceRef cpu_est_d_i_3)) + (portRef I1 (instanceRef state_machine_un13_clk_000_d_1_0)) + )) + (net (rename cpu_est_d_i_0 "cpu_est_d_i[0]") (joined + (portRef O (instanceRef cpu_est_d_i_0)) + (portRef I0 (instanceRef state_machine_un13_clk_000_d_1_0)) + )) + (net CLK_000_D_i (joined + (portRef O (instanceRef CLK_000_D_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_4)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_3)) + (portRef I0 (instanceRef SM_AMIGA_ns_a2_5)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_6)) + (portRef I0 (instanceRef clk_RISING_CLK_AMIGA_1)) + (portRef I0 (instanceRef state_machine_un8_clk_000_d_2)) + (portRef I0 (instanceRef un1_DSACK_INT_0_sqmuxa_i_a2_1)) + (portRef I0 (instanceRef SM_AMIGA_ns_a2_0_1_5)) + )) + (net AS_030_i (joined + (portRef O (instanceRef AS_030_i)) + (portRef I0 (instanceRef state_machine_un17_clk_030)) + (portRef I0 (instanceRef un1_as_030_2)) + (portRef I0 (instanceRef un2_clk_030_1)) + (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa_1)) + (portRef I0 (instanceRef DSACK_INT_1_sqmuxa)) + (portRef I0 (instanceRef AS_000_INT_1_sqmuxa)) + (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1)) + (portRef I0 (instanceRef state_machine_AS_030_000_SYNC_3_1)) + )) + (net AS_000_INT_i (joined + (portRef O (instanceRef AS_000_INT_i)) + (portRef I0 (instanceRef state_machine_un13_as_000_int)) + )) + (net (rename DSACK_i_1 "DSACK_i[1]") (joined + (portRef O (instanceRef I_119)) + (portRef I1 (instanceRef state_machine_un13_as_000_int)) + )) + (net (rename state_machine_un13_clk_000_d_i "state_machine.un13_clk_000_d_i") (joined + (portRef O (instanceRef state_machine_un13_clk_000_d_i)) + (portRef I1 (instanceRef VMA_INT_1_sqmuxa)) + )) + (net (rename state_machine_un8_clk_000_d_i "state_machine.un8_clk_000_d_i") (joined + (portRef O (instanceRef state_machine_un8_clk_000_d_i)) + (portRef I0 (instanceRef VMA_INT_1_sqmuxa)) + )) + (net (rename state_machine_un13_clk_000_d_1_i "state_machine.un13_clk_000_d_1_i") (joined + (portRef O (instanceRef state_machine_un13_clk_000_d_1_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_a2_7)) + )) + (net (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (joined + (portRef O (instanceRef SM_AMIGA_i_1)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_0_6)) + (portRef I1 (instanceRef un9_i_a2_1)) + )) + (net (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (joined + (portRef O (instanceRef SM_AMIGA_i_2)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_0_6)) + (portRef I1 (instanceRef un9_i_a2_1_2)) + )) + (net (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (joined + (portRef O (instanceRef SM_AMIGA_i_0)) + (portRef I1 (instanceRef un9_i_a2_1_1)) + (portRef I0 (instanceRef un9_i_a2_1_2)) + (portRef I1 (instanceRef un9_i_a2_1_0)) + )) + (net (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (joined + (portRef O (instanceRef SM_AMIGA_i_3)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_0_4)) + (portRef I1 (instanceRef un9_i_a2_0)) + )) + (net VPA_D_i (joined + (portRef O (instanceRef VPA_D_i)) + (portRef I1 (instanceRef state_machine_un8_clk_000_d_2)) + (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_3_0)) + )) + (net VMA_INT_i (joined + (portRef O (instanceRef VMA_INT_i)) + (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_2)) + )) + (net DTACK_i (joined + (portRef O (instanceRef I_120)) + (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa_1_1)) + )) + (net (rename cpu_est_i_3 "cpu_est_i[3]") (joined + (portRef O (instanceRef cpu_est_i_3)) + (portRef I1 (instanceRef clk_cpu_est_11_0_a4_0_1)) + (portRef I1 (instanceRef clk_cpu_est_11_0_o4_1)) + (portRef I1 (instanceRef clk_cpu_est_11_i_a4_2)) + (portRef I1 (instanceRef state_machine_un8_clk_000_d_1)) + )) (net (rename A_i_18 "A_i[18]") (joined (portRef O (instanceRef A_i_18)) (portRef I0 (instanceRef state_machine_un42_clk_030_2)) @@ -1560,40 +1413,65 @@ (portRef O (instanceRef state_machine_un42_clk_030_i)) (portRef I1 (instanceRef state_machine_AS_030_000_SYNC_3)) )) + (net DS_030_i (joined + (portRef O (instanceRef DS_030_i)) + (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa_1_0)) + (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa_1_1)) + )) + (net (rename cpu_est_i_1 "cpu_est_i[1]") (joined + (portRef O (instanceRef cpu_est_i_1)) + (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_3)) + (portRef I0 (instanceRef clk_cpu_est_11_0_o4_1)) + (portRef I0 (instanceRef state_machine_un8_clk_000_d_1)) + )) (net AS_030_000_SYNC_i (joined (portRef O (instanceRef AS_030_000_SYNC_i)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_a3_0_1)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_2)) - (portRef I0 (instanceRef DSACK_INT_1_sqmuxa_1_0)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_1)) + (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_1_1)) )) - (net N_131_i (joined - (portRef O (instanceRef N_131_i)) - (portRef I0 (instanceRef SM_AMIGA_D_0_1__m)) + (net (rename cpu_est_i_0 "cpu_est_i[0]") (joined + (portRef O (instanceRef cpu_est_i_0)) + (portRef I1 (instanceRef clk_cpu_est_11_0_a4_1)) + (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_3)) + (portRef I1 (instanceRef clk_cpu_est_11_i_a4_0_1_2)) )) - (net N_132_i (joined - (portRef O (instanceRef N_132_i)) - (portRef I0 (instanceRef SM_AMIGA_D_0_2__m)) + (net (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (joined + (portRef O (instanceRef SM_AMIGA_i_4)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_0_4)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_3)) + (portRef I0 (instanceRef un9_i_a2_2_2)) )) - (net (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (joined - (portRef O (instanceRef SM_AMIGA_i_2)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_6)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_a3_6)) - (portRef I1 (instanceRef un9_i_a3_1_2)) + (net (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (joined + (portRef O (instanceRef SM_AMIGA_i_6)) + (portRef I0 (instanceRef state_machine_un5_clk_030_i_a2)) + (portRef I1 (instanceRef un9_i_a2_2_2)) )) - (net (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (joined - (portRef O (instanceRef SM_AMIGA_i_1)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_6)) - (portRef I1 (instanceRef un9_i_a3_1)) + (net (rename cpu_est_i_2 "cpu_est_i[2]") (joined + (portRef O (instanceRef cpu_est_i_2)) + (portRef I1 (instanceRef clk_cpu_est_11_0_a4_0_3)) + (portRef I0 (instanceRef clk_cpu_est_11_0_a4_0_1)) + (portRef I1 (instanceRef clk_cpu_est_11_0_a4_1_3)) + (portRef I1 (instanceRef clk_cpu_est_11_i_a4_0_2)) )) - (net (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (joined - (portRef O (instanceRef SM_AMIGA_i_3)) - (portRef I0 (instanceRef SM_AMIGA_ns_o2_4)) - (portRef I1 (instanceRef un9_i_a3_0)) + (net UDS_000_INT_0_sqmuxa_1_i (joined + (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1_i)) + (portRef I0 (instanceRef un2_clk_030_1_106)) )) - (net CLK_000_i (joined - (portRef O (instanceRef CLK_000_i)) - (portRef I1 (instanceRef clk_un1_clk_000_i_a3)) - (portRef I0 (instanceRef SM_AMIGA_ns_a3_0_1_7)) + (net UDS_000_INT_0_sqmuxa_i (joined + (portRef O (instanceRef UDS_000_INT_0_sqmuxa_i)) + (portRef I1 (instanceRef un2_clk_030_1_106)) + )) + (net (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (joined + (portRef O (instanceRef SM_AMIGA_i_5)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_3)) + )) + (net CLK_000_DD_i (joined + (portRef O (instanceRef CLK_000_DD_i)) + (portRef I1 (instanceRef clk_un3_clk_000_dd_0_a2)) + )) + (net (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (joined + (portRef O (instanceRef SM_AMIGA_i_7)) + (portRef I1 (instanceRef state_machine_un5_clk_030_i_a2)) )) (net (rename A_i_30 "A_i[30]") (joined (portRef O (instanceRef A_i_30)) @@ -1631,8 +1509,8 @@ (portRef O (instanceRef CLK_CNT_i_0)) (portRef D (instanceRef CLK_CNT_0)) )) - (net (rename state_machine_un14_as_000_int_i "state_machine.un14_as_000_int_i") (joined - (portRef O (instanceRef state_machine_un14_as_000_int_i)) + (net (rename state_machine_un13_as_000_int_i "state_machine.un13_as_000_int_i") (joined + (portRef O (instanceRef state_machine_un13_as_000_int_i)) (portRef D (instanceRef DTACK_DMA)) )) (net RST_i (joined @@ -1661,9 +1539,13 @@ (portRef S (instanceRef VMA_INT)) (portRef S (instanceRef VPA_SYNC)) )) - (net (rename un1_CLK_000_CNT_i_3 "un1_CLK_000_CNT_i[3]") (joined - (portRef O (instanceRef un1_CLK_000_CNT_i_3)) - (portRef D (instanceRef CLK_000_CNT_0)) + (net N_107_i (joined + (portRef O (instanceRef N_107_i)) + (portRef I0 (instanceRef SM_AMIGA_D_0_1__m)) + )) + (net N_106_i (joined + (portRef O (instanceRef N_106_i)) + (portRef I0 (instanceRef SM_AMIGA_D_0_0__m)) )) (net FPU_CS_INT_i (joined (portRef O (instanceRef FPU_CS_INT_i)) @@ -1712,7 +1594,7 @@ )) (net (rename SIZE_c_0 "SIZE_c[0]") (joined (portRef O (instanceRef SIZE_0)) - (portRef I0 (instanceRef state_machine_un25_clk_000_d_1)) + (portRef I0 (instanceRef state_machine_un31_clk_000_d_1)) )) (net (rename SIZE_0 "SIZE[0]") (joined (portRef (member size 1)) @@ -1942,8 +1824,8 @@ )) (net BGACK_000_c (joined (portRef O (instanceRef BGACK_000)) - (portRef I0 (instanceRef state_machine_un4_bgack_000)) (portRef I0 (instanceRef BGACK_030_INT_0_m)) + (portRef I0 (instanceRef state_machine_un4_bgack_000)) (portRef I1 (instanceRef state_machine_un42_clk_030_3)) )) (net BGACK_000 (joined @@ -1961,8 +1843,7 @@ )) (net CLK_000_c (joined (portRef O (instanceRef CLK_000)) - (portRef I1 (instanceRef clk_RISING_CLK_AMIGA_1_0_a3)) - (portRef I0 (instanceRef CLK_000_i)) + (portRef I1 (instanceRef clk_RISING_CLK_AMIGA_1)) (portRef D (instanceRef CLK_000_D)) )) (net CLK_000 (joined @@ -1975,10 +1856,6 @@ (portRef CLK (instanceRef AS_030_000_SYNC)) (portRef CLK (instanceRef BGACK_030_INT)) (portRef CLK (instanceRef BG_000DFFSH)) - (portRef CLK (instanceRef CLK_000_CNT_0)) - (portRef CLK (instanceRef CLK_000_CNT_1)) - (portRef CLK (instanceRef CLK_000_CNT_2)) - (portRef CLK (instanceRef CLK_000_CNT_3)) (portRef CLK (instanceRef CLK_000_D)) (portRef CLK (instanceRef CLK_000_DD)) (portRef CLK (instanceRef CLK_CNT_0)) @@ -2013,6 +1890,10 @@ (portRef CLK (instanceRef cpu_est_1)) (portRef CLK (instanceRef cpu_est_2)) (portRef CLK (instanceRef cpu_est_3)) + (portRef CLK (instanceRef cpu_est_d_0)) + (portRef CLK (instanceRef cpu_est_d_1)) + (portRef CLK (instanceRef cpu_est_d_2)) + (portRef CLK (instanceRef cpu_est_d_3)) )) (net CLK_OSZI (joined (portRef CLK_OSZI) @@ -2087,7 +1968,7 @@ )) (net (rename DSACK_c_1 "DSACK_c[1]") (joined (portRef O (instanceRef DSACK_1)) - (portRef I0 (instanceRef I_170)) + (portRef I0 (instanceRef I_119)) )) (net (rename DSACK_1 "DSACK[1]") (joined (portRef (member dsack 0)) @@ -2095,7 +1976,7 @@ )) (net DTACK_c (joined (portRef O (instanceRef DTACK)) - (portRef I0 (instanceRef I_169)) + (portRef I0 (instanceRef I_120)) )) (net DTACK (joined (portRef IO (instanceRef DTACK)) @@ -2127,13 +2008,13 @@ )) (net RST_c (joined (portRef O (instanceRef RST)) - (portRef I0 (instanceRef RST_i)) (portRef I1 (instanceRef SM_AMIGA_D_0_1__m)) (portRef I0 (instanceRef SM_AMIGA_D_0_1__r)) - (portRef I1 (instanceRef SM_AMIGA_D_0_2__m)) - (portRef I0 (instanceRef SM_AMIGA_D_0_2__r)) (portRef I1 (instanceRef SM_AMIGA_D_0_0__m)) (portRef I0 (instanceRef SM_AMIGA_D_0_0__r)) + (portRef I0 (instanceRef RST_i)) + (portRef I1 (instanceRef SM_AMIGA_D_0_2__m)) + (portRef I0 (instanceRef SM_AMIGA_D_0_2__r)) (portRef D (instanceRef RESETDFF)) )) (net RST (joined @@ -2150,8 +2031,8 @@ )) (net RW_c (joined (portRef O (instanceRef RW)) - (portRef I1 (instanceRef state_machine_un15_clk_000_d)) (portRef I0 (instanceRef RW_i)) + (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_1_2)) )) (net RW (joined (portRef RW) @@ -2189,152 +2070,84 @@ (portRef O (instanceRef CIIN)) (portRef CIIN) )) - (net N_148_i (joined - (portRef O (instanceRef N_148_i)) - (portRef I1 (instanceRef VMA_INT_1_sqmuxa_0)) - )) - (net N_147_i (joined - (portRef O (instanceRef N_147_i)) - (portRef I0 (instanceRef VMA_INT_1_sqmuxa_0)) - )) - (net VMA_INT_1_sqmuxa_0 (joined - (portRef O (instanceRef VMA_INT_1_sqmuxa_0)) - (portRef I0 (instanceRef VMA_INT_1_sqmuxa_0_i)) - )) - (net N_170_i (joined - (portRef O (instanceRef N_170_i)) - (portRef I0 (instanceRef clk_cpu_est_11_i_2)) - )) - (net N_171_i (joined - (portRef O (instanceRef N_171_i)) - (portRef I1 (instanceRef clk_cpu_est_11_i_2)) + (net (rename state_machine_un57_clk_000_d_0 "state_machine.un57_clk_000_d_0") (joined + (portRef O (instanceRef state_machine_un57_clk_000_d)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_o2_4)) + (portRef I0 (instanceRef state_machine_un57_clk_000_d_i)) )) (net N_161_i (joined - (portRef O (instanceRef clk_cpu_est_11_i_2)) - (portRef I0 (instanceRef cpu_est_0_2__m)) + (portRef O (instanceRef N_161_i)) + (portRef I1 (instanceRef state_machine_UDS_000_INT_8)) + (portRef I0 (instanceRef state_machine_LDS_000_INT_8)) )) - (net N_164_i (joined - (portRef O (instanceRef clk_cpu_est_11_0_o4_1)) - (portRef I0 (instanceRef clk_cpu_est_11_0_a4_1_1)) - (portRef I0 (instanceRef clk_cpu_est_11_0_o4_i_1)) - (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1_1)) + (net (rename A_c_i_0 "A_c_i[0]") (joined + (portRef O (instanceRef A_c_i_0)) + (portRef I0 (instanceRef state_machine_UDS_000_INT_8)) + (portRef I1 (instanceRef state_machine_un31_clk_000_d_1)) )) - (net N_165_i (joined - (portRef O (instanceRef clk_cpu_est_11_0_o4_3)) - (portRef I0 (instanceRef clk_cpu_est_11_0_a4_0_3)) - (portRef I0 (instanceRef clk_cpu_est_11_0_o4_i_3)) + (net (rename state_machine_UDS_000_INT_8_0 "state_machine.UDS_000_INT_8_0") (joined + (portRef O (instanceRef state_machine_UDS_000_INT_8)) + (portRef I0 (instanceRef state_machine_UDS_000_INT_8_i)) )) - (net N_168_i (joined - (portRef O (instanceRef N_168_i)) - (portRef I1 (instanceRef clk_cpu_est_11_0_2_1)) + (net (rename state_machine_LDS_000_INT_8_0 "state_machine.LDS_000_INT_8_0") (joined + (portRef O (instanceRef state_machine_LDS_000_INT_8)) + (portRef I0 (instanceRef state_machine_LDS_000_INT_8_i)) )) - (net N_166_i (joined - (portRef O (instanceRef N_166_i)) - (portRef I0 (instanceRef clk_cpu_est_11_0_2_1)) + (net N_113_i (joined + (portRef O (instanceRef N_113_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_2)) )) - (net N_167_i (joined - (portRef O (instanceRef N_167_i)) - (portRef I1 (instanceRef clk_cpu_est_11_0_1_1)) + (net (rename SM_AMIGA_ns_0_2 "SM_AMIGA_ns_0[2]") (joined + (portRef O (instanceRef SM_AMIGA_ns_2)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_2)) )) - (net N_169_i (joined - (portRef O (instanceRef N_169_i)) - (portRef I0 (instanceRef clk_cpu_est_11_0_1_1)) - )) - (net (rename clk_cpu_est_11_0_1 "clk.cpu_est_11_0[1]") (joined - (portRef O (instanceRef clk_cpu_est_11_0_1)) - (portRef I0 (instanceRef clk_cpu_est_11_0_i_1)) - )) - (net N_173_i (joined - (portRef O (instanceRef N_173_i)) - (portRef I1 (instanceRef clk_cpu_est_11_0_3)) - )) - (net N_172_i (joined - (portRef O (instanceRef N_172_i)) - (portRef I1 (instanceRef clk_cpu_est_11_0_1_3)) - )) - (net N_174_i (joined - (portRef O (instanceRef N_174_i)) - (portRef I0 (instanceRef clk_cpu_est_11_0_1_3)) - )) - (net (rename clk_cpu_est_11_0_3 "clk.cpu_est_11_0[3]") (joined - (portRef O (instanceRef clk_cpu_est_11_0_3)) - (portRef I0 (instanceRef clk_cpu_est_11_0_i_3)) - )) - (net N_121_i (joined - (portRef O (instanceRef SM_AMIGA_ns_o2_5)) - (portRef I0 (instanceRef SM_AMIGA_ns_a3_0_4)) - (portRef I0 (instanceRef SM_AMIGA_ns_o2_i_5)) - )) - (net N_126_0 (joined - (portRef O (instanceRef SM_AMIGA_ns_o2_4)) - (portRef I0 (instanceRef SM_AMIGA_ns_o2_i_4)) - )) - (net N_123_0 (joined - (portRef O (instanceRef state_machine_un9_clk_000_d_i_o3)) - (portRef I0 (instanceRef state_machine_un9_clk_000_d_i_o3_i)) - )) - (net N_122_0 (joined - (portRef O (instanceRef un1_SM_AMIGA_i_o2)) - (portRef I0 (instanceRef un1_SM_AMIGA_i_o2_i)) - )) - (net N_142_i (joined - (portRef O (instanceRef N_142_i)) - (portRef I0 (instanceRef SM_AMIGA_ns_5)) - )) - (net N_143_i (joined - (portRef O (instanceRef N_143_i)) + (net N_118_i (joined + (portRef O (instanceRef N_118_i)) (portRef I1 (instanceRef SM_AMIGA_ns_5)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_1_6)) + )) + (net N_117_i (joined + (portRef O (instanceRef N_117_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_5)) )) (net (rename SM_AMIGA_ns_0_5 "SM_AMIGA_ns_0[5]") (joined (portRef O (instanceRef SM_AMIGA_ns_5)) (portRef I0 (instanceRef SM_AMIGA_ns_i_5)) )) - (net N_141_i (joined - (portRef O (instanceRef N_141_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_4)) + (net N_123_i (joined + (portRef O (instanceRef N_123_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_6)) )) - (net N_140_i (joined - (portRef O (instanceRef N_140_i)) - (portRef I0 (instanceRef SM_AMIGA_ns_4)) + (net N_119_i (joined + (portRef O (instanceRef N_119_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_6)) )) - (net (rename SM_AMIGA_ns_0_4 "SM_AMIGA_ns_0[4]") (joined - (portRef O (instanceRef SM_AMIGA_ns_4)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_4)) + (net N_94_i (joined + (portRef O (instanceRef SM_AMIGA_ns_i_6)) + (portRef D (instanceRef SM_AMIGA_1)) )) - (net N_110_i (joined - (portRef O (instanceRef SM_AMIGA_ns_i_2)) - (portRef D (instanceRef SM_AMIGA_5)) + (net N_120_i (joined + (portRef O (instanceRef N_120_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_7)) )) - (net LDS_000_INT_1_sqmuxa_i (joined - (portRef O (instanceRef LDS_000_INT_1_sqmuxa_i)) - (portRef I0 (instanceRef un1_UDS_000_INT_0_sqmuxa_2)) + (net (rename SM_AMIGA_ns_0_7 "SM_AMIGA_ns_0[7]") (joined + (portRef O (instanceRef SM_AMIGA_ns_7)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_7)) )) - (net un1_UDS_000_INT_0_sqmuxa_2_0 (joined - (portRef O (instanceRef un1_UDS_000_INT_0_sqmuxa_2)) - (portRef I1 (instanceRef state_machine_UDS_000_INT_8)) - (portRef I1 (instanceRef state_machine_LDS_000_INT_8)) - (portRef I0 (instanceRef un1_UDS_000_INT_0_sqmuxa_2_i)) + (net CLK_OUT_PRE_i (joined + (portRef O (instanceRef CLK_OUT_PRE_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_6)) )) - (net UDS_000_INT_0_sqmuxa_i (joined - (portRef O (instanceRef UDS_000_INT_0_sqmuxa_i)) - (portRef I1 (instanceRef un1_UDS_000_INT_0_sqmuxa)) + (net N_102_0 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_o2_6)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_i_6)) )) - (net un1_UDS_000_INT_0_sqmuxa_i (joined - (portRef O (instanceRef un1_UDS_000_INT_0_sqmuxa)) - (portRef I0 (instanceRef un1_UDS_000_INT_0_sqmuxa_i_0)) + (net (rename SIZE_c_i_1 "SIZE_c_i[1]") (joined + (portRef O (instanceRef SIZE_c_i_1)) + (portRef I1 (instanceRef state_machine_un31_clk_000_d)) )) - (net N_124_0 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_o2_0)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_i_0)) - )) - (net N_136_i (joined - (portRef O (instanceRef N_136_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_0)) - )) - (net N_106_i (joined - (portRef O (instanceRef SM_AMIGA_ns_i_0)) - (portRef D (instanceRef SM_AMIGA_7)) + (net (rename state_machine_un31_clk_000_d_i "state_machine.un31_clk_000_d_i") (joined + (portRef O (instanceRef state_machine_un31_clk_000_d)) + (portRef I0 (instanceRef state_machine_un31_clk_000_d_i_0)) )) (net RISING_CLK_AMIGA_i (joined (portRef O (instanceRef RISING_CLK_AMIGA_i)) @@ -2361,162 +2174,130 @@ (portRef O (instanceRef un1_as_030_2)) (portRef I0 (instanceRef un1_as_030_2_i)) )) - (net N_137_i (joined - (portRef O (instanceRef N_137_i)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_1)) - )) - (net N_138_i (joined - (portRef O (instanceRef N_138_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_1)) - )) - (net N_108_i (joined - (portRef O (instanceRef SM_AMIGA_ns_i_1)) - (portRef D (instanceRef SM_AMIGA_6)) - )) - (net N_120_i (joined - (portRef O (instanceRef SM_AMIGA_ns_i_o2_2)) - (portRef I1 (instanceRef un1_SM_AMIGA_i_o2)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_i_2)) - )) - (net N_125_0 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_o2_1)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_i_1)) - )) (net (rename state_machine_AS_030_000_SYNC_3_2 "state_machine.AS_030_000_SYNC_3_2") (joined (portRef O (instanceRef state_machine_AS_030_000_SYNC_3)) (portRef I0 (instanceRef state_machine_AS_030_000_SYNC_3_i)) )) - (net N_133_i (joined - (portRef O (instanceRef N_133_i)) + (net N_109_i (joined + (portRef O (instanceRef N_109_i)) (portRef I1 (instanceRef un1_bg_030_2)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_1_1)) )) (net un1_bg_030_0 (joined (portRef O (instanceRef un1_bg_030)) (portRef I0 (instanceRef un1_bg_030_i)) )) - (net (rename A_c_i_0 "A_c_i[0]") (joined - (portRef O (instanceRef A_c_i_0)) - (portRef I0 (instanceRef state_machine_UDS_000_INT_8)) - (portRef I1 (instanceRef state_machine_un25_clk_000_d_1)) + (net N_111_i (joined + (portRef O (instanceRef N_111_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_0)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_1_1)) )) - (net (rename state_machine_UDS_000_INT_8_0 "state_machine.UDS_000_INT_8_0") (joined - (portRef O (instanceRef state_machine_UDS_000_INT_8)) - (portRef I0 (instanceRef state_machine_UDS_000_INT_8_i)) + (net N_122_i (joined + (portRef O (instanceRef N_122_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_1)) )) - (net (rename state_machine_LDS_000_INT_8_0 "state_machine.LDS_000_INT_8_0") (joined - (portRef O (instanceRef state_machine_LDS_000_INT_8)) - (portRef I0 (instanceRef state_machine_LDS_000_INT_8_i)) + (net N_86_i (joined + (portRef O (instanceRef SM_AMIGA_ns_i_1)) + (portRef D (instanceRef SM_AMIGA_6)) )) - (net N_151_i (joined - (portRef O (instanceRef N_151_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_3)) + (net N_147_i (joined + (portRef O (instanceRef N_147_i)) + (portRef I0 (instanceRef clk_cpu_est_11_0_1_3)) )) - (net N_112_i (joined - (portRef O (instanceRef SM_AMIGA_ns_i_3)) - (portRef D (instanceRef SM_AMIGA_4)) - )) - (net N_146_i (joined - (portRef O (instanceRef N_146_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_7)) + (net (rename clk_cpu_est_11_0_3 "clk.cpu_est_11_0[3]") (joined + (portRef O (instanceRef clk_cpu_est_11_0_3)) + (portRef I0 (instanceRef clk_cpu_est_11_0_i_3)) )) (net N_145_i (joined (portRef O (instanceRef N_145_i)) - (portRef I0 (instanceRef SM_AMIGA_ns_7)) + (portRef I1 (instanceRef clk_cpu_est_11_0_1_3)) )) - (net (rename SM_AMIGA_ns_0_7 "SM_AMIGA_ns_0[7]") (joined - (portRef O (instanceRef SM_AMIGA_ns_7)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_7)) + (net N_146_i (joined + (portRef O (instanceRef N_146_i)) + (portRef I1 (instanceRef clk_cpu_est_11_0_3)) + )) + (net N_142_i (joined + (portRef O (instanceRef N_142_i)) + (portRef I1 (instanceRef clk_cpu_est_11_0_2_1)) + )) + (net (rename clk_cpu_est_11_0_1 "clk.cpu_est_11_0[1]") (joined + (portRef O (instanceRef clk_cpu_est_11_0_1)) + (portRef I0 (instanceRef clk_cpu_est_11_0_i_1)) + )) + (net N_140_i (joined + (portRef O (instanceRef N_140_i)) + (portRef I1 (instanceRef clk_cpu_est_11_0_1_1)) + )) + (net N_139_i (joined + (portRef O (instanceRef N_139_i)) + (portRef I0 (instanceRef clk_cpu_est_11_0_1_1)) + )) + (net N_141_i (joined + (portRef O (instanceRef N_141_i)) + (portRef I0 (instanceRef clk_cpu_est_11_0_2_1)) + )) + (net N_138_i (joined + (portRef O (instanceRef clk_cpu_est_11_0_o4_3)) + (portRef I0 (instanceRef clk_cpu_est_11_0_a4_0_3)) + (portRef I0 (instanceRef clk_cpu_est_11_0_o4_i_3)) + )) + (net N_137_i (joined + (portRef O (instanceRef clk_cpu_est_11_0_o4_1)) + (portRef I0 (instanceRef clk_cpu_est_11_0_a4_1_1)) + (portRef I0 (instanceRef clk_cpu_est_11_0_o4_i_1)) + )) + (net N_136_i (joined + (portRef O (instanceRef clk_cpu_est_11_i_o4_2)) + (portRef I0 (instanceRef clk_cpu_est_11_0_a4_2_1)) + (portRef I0 (instanceRef clk_cpu_est_11_i_o4_i_2)) + )) + (net N_143_i (joined + (portRef O (instanceRef N_143_i)) + (portRef I0 (instanceRef clk_cpu_est_11_i_2)) )) (net N_144_i (joined (portRef O (instanceRef N_144_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_1_6)) + (portRef I1 (instanceRef clk_cpu_est_11_i_2)) )) - (net N_150_i (joined - (portRef O (instanceRef N_150_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_6)) + (net N_134_i (joined + (portRef O (instanceRef clk_cpu_est_11_i_2)) + (portRef I0 (instanceRef cpu_est_0_2__m)) + )) + (net N_101_0 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_o2_4)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_i_4)) + )) + (net N_115_i (joined + (portRef O (instanceRef N_115_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_4)) )) (net N_116_i (joined - (portRef O (instanceRef SM_AMIGA_ns_i_6)) - (portRef D (instanceRef SM_AMIGA_1)) + (portRef O (instanceRef N_116_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_4)) )) - (net (rename SIZE_c_i_1 "SIZE_c_i[1]") (joined - (portRef O (instanceRef SIZE_c_i_1)) - (portRef I1 (instanceRef state_machine_un25_clk_000_d)) + (net N_91_i (joined + (portRef O (instanceRef SM_AMIGA_ns_i_4)) + (portRef D (instanceRef SM_AMIGA_3)) )) - (net (rename state_machine_un25_clk_000_d_i "state_machine.un25_clk_000_d_i") (joined - (portRef O (instanceRef state_machine_un25_clk_000_d)) - (portRef I0 (instanceRef state_machine_un25_clk_000_d_i_0)) + (net N_124_i (joined + (portRef O (instanceRef N_124_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_3)) )) - (net (rename state_machine_un80_clk_000_d_i "state_machine.un80_clk_000_d_i") (joined - (portRef O (instanceRef state_machine_un80_clk_000_d_i)) - (portRef I1 (instanceRef state_machine_un78_clk_000_d)) + (net N_89_i (joined + (portRef O (instanceRef SM_AMIGA_ns_i_3)) + (portRef D (instanceRef SM_AMIGA_4)) )) - (net (rename state_machine_un67_clk_000_d_i "state_machine.un67_clk_000_d_i") (joined - (portRef O (instanceRef state_machine_un67_clk_000_d_i)) - (portRef I0 (instanceRef state_machine_un78_clk_000_d)) + (net N_112_i (joined + (portRef O (instanceRef N_112_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_0)) )) - (net (rename state_machine_un78_clk_000_d_0 "state_machine.un78_clk_000_d_0") (joined - (portRef O (instanceRef state_machine_un78_clk_000_d)) - (portRef I0 (instanceRef state_machine_un78_clk_000_d_i)) + (net (rename SM_AMIGA_ns_0_0 "SM_AMIGA_ns_0[0]") (joined + (portRef O (instanceRef SM_AMIGA_ns_0)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_0)) )) - (net (rename clk_RISING_CLK_AMIGA_1_i "clk.RISING_CLK_AMIGA_1_i") (joined - (portRef O (instanceRef clk_RISING_CLK_AMIGA_1_i)) - (portRef I1 (instanceRef clk_un1_clk_000_i)) - )) - (net N_135_i (joined - (portRef O (instanceRef N_135_i)) - (portRef I0 (instanceRef clk_un1_clk_000_i)) - )) - (net N_104_i (joined - (portRef O (instanceRef clk_un1_clk_000_i)) - (portRef I1 (instanceRef un1_CLK_000_CNT_3)) - (portRef I1 (instanceRef un1_CLK_000_CNT_2)) - (portRef I1 (instanceRef un1_CLK_000_CNT_1)) - (portRef I1 (instanceRef un1_CLK_000_CNT_0)) - )) - (net N_149_i (joined - (portRef O (instanceRef N_149_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_o2_6)) - )) - (net N_119_0 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_o2_6)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_i_6)) - )) - (net (rename CLK_000_CNT_i_1 "CLK_000_CNT_i[1]") (joined - (portRef O (instanceRef CLK_000_CNT_i_1)) - (portRef I1 (instanceRef G_150_1)) - )) - (net (rename CLK_000_CNT_i_0 "CLK_000_CNT_i[0]") (joined - (portRef O (instanceRef CLK_000_CNT_i_0)) - (portRef I0 (instanceRef G_150_1)) - )) - (net (rename CLK_000_CNT_i_3 "CLK_000_CNT_i[3]") (joined - (portRef O (instanceRef CLK_000_CNT_i_3)) - (portRef I1 (instanceRef G_150_2)) - )) - (net (rename CLK_000_CNT_i_2 "CLK_000_CNT_i[2]") (joined - (portRef O (instanceRef CLK_000_CNT_i_2)) - (portRef I0 (instanceRef G_150_2)) - )) - (net (rename state_machine_un69_clk_000_d_0 "state_machine.un69_clk_000_d_0") (joined - (portRef O (instanceRef G_150)) - (portRef I0 (instanceRef G_150_i)) - )) - (net (rename state_machine_un69_clk_000_d_0_1 "state_machine.un69_clk_000_d_0_1") (joined - (portRef O (instanceRef G_150_1)) - (portRef I0 (instanceRef G_150)) - )) - (net (rename state_machine_un69_clk_000_d_0_2 "state_machine.un69_clk_000_d_0_2") (joined - (portRef O (instanceRef G_150_2)) - (portRef I1 (instanceRef G_150)) - )) - (net (rename state_machine_un25_clk_000_d_i_1 "state_machine.un25_clk_000_d_i_1") (joined - (portRef O (instanceRef state_machine_un25_clk_000_d_1)) - (portRef I0 (instanceRef state_machine_un25_clk_000_d)) - )) - (net N_116_i_1 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_1_6)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_6)) + (net N_86_i_1 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_1_1)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_1)) )) (net un1_bg_030_0_1 (joined (portRef O (instanceRef un1_bg_030_1)) @@ -2530,13 +2311,41 @@ (portRef O (instanceRef state_machine_AS_030_000_SYNC_3_1)) (portRef I0 (instanceRef state_machine_AS_030_000_SYNC_3)) )) - (net un1_UDS_000_INT_0_sqmuxa_i_1 (joined - (portRef O (instanceRef un1_UDS_000_INT_0_sqmuxa_1)) - (portRef I0 (instanceRef un1_UDS_000_INT_0_sqmuxa)) + (net (rename state_machine_un31_clk_000_d_i_1 "state_machine.un31_clk_000_d_i_1") (joined + (portRef O (instanceRef state_machine_un31_clk_000_d_1)) + (portRef I0 (instanceRef state_machine_un31_clk_000_d)) )) - (net (rename clk_cpu_est_11_0_1_3 "clk.cpu_est_11_0_1[3]") (joined - (portRef O (instanceRef clk_cpu_est_11_0_1_3)) - (portRef I0 (instanceRef clk_cpu_est_11_0_3)) + (net N_186_1 (joined + (portRef O (instanceRef un8_ciin_1)) + (portRef I0 (instanceRef un8_ciin_5)) + )) + (net N_186_2 (joined + (portRef O (instanceRef un8_ciin_2)) + (portRef I1 (instanceRef un8_ciin_5)) + )) + (net N_186_3 (joined + (portRef O (instanceRef un8_ciin_3)) + (portRef I0 (instanceRef un8_ciin_6)) + )) + (net N_186_4 (joined + (portRef O (instanceRef un8_ciin_4)) + (portRef I1 (instanceRef un8_ciin_6)) + )) + (net N_186_5 (joined + (portRef O (instanceRef un8_ciin_5)) + (portRef I0 (instanceRef un8_ciin)) + )) + (net N_186_6 (joined + (portRef O (instanceRef un8_ciin_6)) + (portRef I1 (instanceRef un8_ciin)) + )) + (net N_189_1 (joined + (portRef O (instanceRef un4_ciin_1)) + (portRef I0 (instanceRef un4_ciin)) + )) + (net N_189_2 (joined + (portRef O (instanceRef un4_ciin_2)) + (portRef I1 (instanceRef un4_ciin)) )) (net (rename clk_cpu_est_11_0_1_1 "clk.cpu_est_11_0_1[1]") (joined (portRef O (instanceRef clk_cpu_est_11_0_1_1)) @@ -2546,65 +2355,49 @@ (portRef O (instanceRef clk_cpu_est_11_0_2_1)) (portRef I1 (instanceRef clk_cpu_est_11_0_1)) )) - (net N_251_1 (joined - (portRef O (instanceRef un8_ciin_1)) - (portRef I0 (instanceRef un8_ciin_5)) + (net (rename clk_cpu_est_11_0_1_3 "clk.cpu_est_11_0_1[3]") (joined + (portRef O (instanceRef clk_cpu_est_11_0_1_3)) + (portRef I0 (instanceRef clk_cpu_est_11_0_3)) )) - (net N_251_2 (joined - (portRef O (instanceRef un8_ciin_2)) - (portRef I1 (instanceRef un8_ciin_5)) + (net N_143_1 (joined + (portRef O (instanceRef clk_cpu_est_11_i_a4_1_2)) + (portRef I0 (instanceRef clk_cpu_est_11_i_a4_2)) )) - (net N_251_3 (joined - (portRef O (instanceRef un8_ciin_3)) - (portRef I0 (instanceRef un8_ciin_6)) + (net N_144_1 (joined + (portRef O (instanceRef clk_cpu_est_11_i_a4_0_1_2)) + (portRef I0 (instanceRef clk_cpu_est_11_i_a4_0_2)) )) - (net N_251_4 (joined - (portRef O (instanceRef un8_ciin_4)) - (portRef I1 (instanceRef un8_ciin_6)) + (net N_106_1 (joined + (portRef O (instanceRef un9_i_a2_1_2)) + (portRef I0 (instanceRef un9_i_a2_2)) )) - (net N_251_5 (joined - (portRef O (instanceRef un8_ciin_5)) - (portRef I0 (instanceRef un8_ciin)) + (net N_106_2 (joined + (portRef O (instanceRef un9_i_a2_2_2)) + (portRef I1 (instanceRef un9_i_a2_2)) )) - (net N_251_6 (joined - (portRef O (instanceRef un8_ciin_6)) - (portRef I1 (instanceRef un8_ciin)) + (net N_107_1 (joined + (portRef O (instanceRef un9_i_a2_1_1)) + (portRef I0 (instanceRef un9_i_a2_1)) )) - (net N_254_1 (joined - (portRef O (instanceRef un4_ciin_1)) - (portRef I0 (instanceRef un4_ciin)) + (net UDS_000_INT_0_sqmuxa_1_1 (joined + (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1_1)) + (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_1_3)) )) - (net N_254_2 (joined - (portRef O (instanceRef un4_ciin_2)) - (portRef I1 (instanceRef un4_ciin)) + (net UDS_000_INT_0_sqmuxa_1_2 (joined + (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1_2)) + (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa_1_3)) )) - (net DSACK_INT_1_sqmuxa_1_0 (joined - (portRef O (instanceRef DSACK_INT_1_sqmuxa_1_0)) - (portRef I0 (instanceRef DSACK_INT_1_sqmuxa_3)) + (net UDS_000_INT_0_sqmuxa_1_3 (joined + (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1_3)) + (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_1)) )) - (net DSACK_INT_1_sqmuxa_2 (joined - (portRef O (instanceRef DSACK_INT_1_sqmuxa_2)) - (portRef I1 (instanceRef DSACK_INT_1_sqmuxa_3)) + (net UDS_000_INT_0_sqmuxa_1_0 (joined + (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1_0)) + (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa)) )) - (net DSACK_INT_1_sqmuxa_3 (joined - (portRef O (instanceRef DSACK_INT_1_sqmuxa_3)) - (portRef I0 (instanceRef DSACK_INT_1_sqmuxa)) - )) - (net N_149_1 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_a2_0_1_6)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_0_6)) - )) - (net N_149_2_0 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_a2_0_2_0_6)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_0_6)) - )) - (net N_132_1 (joined - (portRef O (instanceRef un9_i_a3_1_0)) - (portRef I0 (instanceRef un9_i_a3_0)) - )) - (net N_131_1 (joined - (portRef O (instanceRef un9_i_a3_1_1)) - (portRef I0 (instanceRef un9_i_a3_1)) + (net UDS_000_INT_0_sqmuxa_2 (joined + (portRef O (instanceRef UDS_000_INT_0_sqmuxa_2)) + (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa)) )) (net (rename state_machine_un42_clk_030_1 "state_machine.un42_clk_030_1") (joined (portRef O (instanceRef state_machine_un42_clk_030_1)) @@ -2626,69 +2419,89 @@ (portRef O (instanceRef state_machine_un42_clk_030_5)) (portRef I1 (instanceRef state_machine_un42_clk_030)) )) - (net N_142_1 (joined - (portRef O (instanceRef SM_AMIGA_ns_a3_1_5)) - (portRef I0 (instanceRef SM_AMIGA_ns_a3_5)) + (net (rename state_machine_un13_clk_000_d_1_0 "state_machine.un13_clk_000_d_1_0") (joined + (portRef O (instanceRef state_machine_un13_clk_000_d_1_0)) + (portRef I0 (instanceRef state_machine_un13_clk_000_d)) )) - (net N_130_1 (joined - (portRef O (instanceRef un9_i_a3_1_2)) - (portRef I0 (instanceRef un9_i_a3_2)) + (net (rename state_machine_un13_clk_000_d_4_1 "state_machine.un13_clk_000_d_4_1") (joined + (portRef O (instanceRef state_machine_un13_clk_000_d_4_1)) + (portRef I0 (instanceRef state_machine_un13_clk_000_d_4)) )) - (net N_130_2 (joined - (portRef O (instanceRef un9_i_a3_2_2)) - (portRef I1 (instanceRef un9_i_a3_2)) + (net (rename state_machine_un8_clk_000_d_1 "state_machine.un8_clk_000_d_1") (joined + (portRef O (instanceRef state_machine_un8_clk_000_d_1)) + (portRef I0 (instanceRef state_machine_un8_clk_000_d_4)) )) - (net UDS_000_INT_0_sqmuxa_1 (joined - (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1)) - (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa)) + (net (rename state_machine_un8_clk_000_d_2 "state_machine.un8_clk_000_d_2") (joined + (portRef O (instanceRef state_machine_un8_clk_000_d_2)) + (portRef I1 (instanceRef state_machine_un8_clk_000_d_4)) )) - (net UDS_000_INT_0_sqmuxa_2 (joined - (portRef O (instanceRef UDS_000_INT_0_sqmuxa_2)) - (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa)) + (net (rename state_machine_un8_clk_000_d_3 "state_machine.un8_clk_000_d_3") (joined + (portRef O (instanceRef state_machine_un8_clk_000_d_3)) + (portRef I1 (instanceRef state_machine_un8_clk_000_d)) + )) + (net (rename state_machine_un8_clk_000_d_4 "state_machine.un8_clk_000_d_4") (joined + (portRef O (instanceRef state_machine_un8_clk_000_d_4)) + (portRef I0 (instanceRef state_machine_un8_clk_000_d)) )) (net DTACK_SYNC_1_sqmuxa_1_0 (joined - (portRef O (instanceRef DTACK_SYNC_1_sqmuxa_1_0)) + (portRef O (instanceRef DTACK_SYNC_1_sqmuxa_1_1)) (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa)) )) (net VPA_SYNC_1_sqmuxa_1_1 (joined - (portRef O (instanceRef VPA_SYNC_1_sqmuxa_1_1)) - (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_3)) + (portRef O (instanceRef VPA_SYNC_1_sqmuxa_1_0)) + (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_4)) )) (net VPA_SYNC_1_sqmuxa_2 (joined (portRef O (instanceRef VPA_SYNC_1_sqmuxa_2)) - (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_3)) + (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_4)) )) (net VPA_SYNC_1_sqmuxa_3 (joined - (portRef O (instanceRef VPA_SYNC_1_sqmuxa_3)) + (portRef O (instanceRef VPA_SYNC_1_sqmuxa_3_0)) + (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa)) + )) + (net VPA_SYNC_1_sqmuxa_4 (joined + (portRef O (instanceRef VPA_SYNC_1_sqmuxa_4)) (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa)) )) - (net N_171_1 (joined - (portRef O (instanceRef clk_cpu_est_11_i_a4_0_1_2)) - (portRef I0 (instanceRef clk_cpu_est_11_i_a4_0_2)) + (net N_108_1 (joined + (portRef O (instanceRef un9_i_a2_1_0)) + (portRef I0 (instanceRef un9_i_a2_0)) )) - (net N_170_1 (joined - (portRef O (instanceRef clk_cpu_est_11_i_a4_1_2)) - (portRef I0 (instanceRef clk_cpu_est_11_i_a4_2)) + (net N_118_1 (joined + (portRef O (instanceRef SM_AMIGA_ns_a2_0_1_5)) + (portRef I0 (instanceRef SM_AMIGA_ns_a2_0_5)) )) - (net N_174_1 (joined - (portRef O (instanceRef clk_cpu_est_11_0_a4_1_1_3)) - (portRef I0 (instanceRef clk_cpu_est_11_0_a4_1_3)) + (net N_110_1 (joined + (portRef O (instanceRef un1_DSACK_INT_0_sqmuxa_i_a2_1)) + (portRef I0 (instanceRef un1_DSACK_INT_0_sqmuxa_i_a2)) )) (net clk_exp_1 (joined - (portRef O (instanceRef G_125_1)) - (portRef I0 (instanceRef G_125)) + (portRef O (instanceRef G_101_1)) + (portRef I0 (instanceRef G_101)) )) - (net (rename cpu_est_0_1__un3 "cpu_est_0_1_.un3") (joined - (portRef O (instanceRef cpu_est_0_1__r)) - (portRef I1 (instanceRef cpu_est_0_1__n)) + (net (rename SM_AMIGA_D_0_2__un3 "SM_AMIGA_D_0_2_.un3") (joined + (portRef O (instanceRef SM_AMIGA_D_0_2__r)) + (portRef I1 (instanceRef SM_AMIGA_D_0_2__n)) )) - (net (rename cpu_est_0_1__un1 "cpu_est_0_1_.un1") (joined - (portRef O (instanceRef cpu_est_0_1__m)) - (portRef I0 (instanceRef cpu_est_0_1__p)) + (net (rename SM_AMIGA_D_0_2__un1 "SM_AMIGA_D_0_2_.un1") (joined + (portRef O (instanceRef SM_AMIGA_D_0_2__m)) + (portRef I0 (instanceRef SM_AMIGA_D_0_2__p)) )) - (net (rename cpu_est_0_1__un0 "cpu_est_0_1_.un0") (joined - (portRef O (instanceRef cpu_est_0_1__n)) - (portRef I1 (instanceRef cpu_est_0_1__p)) + (net (rename SM_AMIGA_D_0_2__un0 "SM_AMIGA_D_0_2_.un0") (joined + (portRef O (instanceRef SM_AMIGA_D_0_2__n)) + (portRef I1 (instanceRef SM_AMIGA_D_0_2__p)) + )) + (net (rename DSACK_INT_0_1__un3 "DSACK_INT_0_1_.un3") (joined + (portRef O (instanceRef DSACK_INT_0_1__r)) + (portRef I1 (instanceRef DSACK_INT_0_1__n)) + )) + (net (rename DSACK_INT_0_1__un1 "DSACK_INT_0_1_.un1") (joined + (portRef O (instanceRef DSACK_INT_0_1__m)) + (portRef I0 (instanceRef DSACK_INT_0_1__p)) + )) + (net (rename DSACK_INT_0_1__un0 "DSACK_INT_0_1_.un0") (joined + (portRef O (instanceRef DSACK_INT_0_1__n)) + (portRef I1 (instanceRef DSACK_INT_0_1__p)) )) (net (rename VMA_INT_0_un3 "VMA_INT_0.un3") (joined (portRef O (instanceRef VMA_INT_0_r)) @@ -2702,29 +2515,29 @@ (portRef O (instanceRef VMA_INT_0_n)) (portRef I1 (instanceRef VMA_INT_0_p)) )) - (net (rename cpu_est_0_3__un3 "cpu_est_0_3_.un3") (joined - (portRef O (instanceRef cpu_est_0_3__r)) - (portRef I1 (instanceRef cpu_est_0_3__n)) + (net (rename VPA_SYNC_0_un3 "VPA_SYNC_0.un3") (joined + (portRef O (instanceRef VPA_SYNC_0_r)) + (portRef I1 (instanceRef VPA_SYNC_0_n)) )) - (net (rename cpu_est_0_3__un1 "cpu_est_0_3_.un1") (joined - (portRef O (instanceRef cpu_est_0_3__m)) - (portRef I0 (instanceRef cpu_est_0_3__p)) + (net (rename VPA_SYNC_0_un1 "VPA_SYNC_0.un1") (joined + (portRef O (instanceRef VPA_SYNC_0_m)) + (portRef I0 (instanceRef VPA_SYNC_0_p)) )) - (net (rename cpu_est_0_3__un0 "cpu_est_0_3_.un0") (joined - (portRef O (instanceRef cpu_est_0_3__n)) - (portRef I1 (instanceRef cpu_est_0_3__p)) + (net (rename VPA_SYNC_0_un0 "VPA_SYNC_0.un0") (joined + (portRef O (instanceRef VPA_SYNC_0_n)) + (portRef I1 (instanceRef VPA_SYNC_0_p)) )) - (net (rename cpu_est_0_2__un3 "cpu_est_0_2_.un3") (joined - (portRef O (instanceRef cpu_est_0_2__r)) - (portRef I1 (instanceRef cpu_est_0_2__n)) + (net (rename AS_000_INT_0_un3 "AS_000_INT_0.un3") (joined + (portRef O (instanceRef AS_000_INT_0_r)) + (portRef I1 (instanceRef AS_000_INT_0_n)) )) - (net (rename cpu_est_0_2__un1 "cpu_est_0_2_.un1") (joined - (portRef O (instanceRef cpu_est_0_2__m)) - (portRef I0 (instanceRef cpu_est_0_2__p)) + (net (rename AS_000_INT_0_un1 "AS_000_INT_0.un1") (joined + (portRef O (instanceRef AS_000_INT_0_m)) + (portRef I0 (instanceRef AS_000_INT_0_p)) )) - (net (rename cpu_est_0_2__un0 "cpu_est_0_2_.un0") (joined - (portRef O (instanceRef cpu_est_0_2__n)) - (portRef I1 (instanceRef cpu_est_0_2__p)) + (net (rename AS_000_INT_0_un0 "AS_000_INT_0.un0") (joined + (portRef O (instanceRef AS_000_INT_0_n)) + (portRef I1 (instanceRef AS_000_INT_0_p)) )) (net (rename DTACK_SYNC_0_un3 "DTACK_SYNC_0.un3") (joined (portRef O (instanceRef DTACK_SYNC_0_r)) @@ -2738,29 +2551,29 @@ (portRef O (instanceRef DTACK_SYNC_0_n)) (portRef I1 (instanceRef DTACK_SYNC_0_p)) )) - (net (rename SM_AMIGA_D_0_0__un3 "SM_AMIGA_D_0_0_.un3") (joined - (portRef O (instanceRef SM_AMIGA_D_0_0__r)) - (portRef I1 (instanceRef SM_AMIGA_D_0_0__n)) + (net (rename LDS_000_INT_0_un3 "LDS_000_INT_0.un3") (joined + (portRef O (instanceRef LDS_000_INT_0_r)) + (portRef I1 (instanceRef LDS_000_INT_0_n)) )) - (net (rename SM_AMIGA_D_0_0__un1 "SM_AMIGA_D_0_0_.un1") (joined - (portRef O (instanceRef SM_AMIGA_D_0_0__m)) - (portRef I0 (instanceRef SM_AMIGA_D_0_0__p)) + (net (rename LDS_000_INT_0_un1 "LDS_000_INT_0.un1") (joined + (portRef O (instanceRef LDS_000_INT_0_m)) + (portRef I0 (instanceRef LDS_000_INT_0_p)) )) - (net (rename SM_AMIGA_D_0_0__un0 "SM_AMIGA_D_0_0_.un0") (joined - (portRef O (instanceRef SM_AMIGA_D_0_0__n)) - (portRef I1 (instanceRef SM_AMIGA_D_0_0__p)) + (net (rename LDS_000_INT_0_un0 "LDS_000_INT_0.un0") (joined + (portRef O (instanceRef LDS_000_INT_0_n)) + (portRef I1 (instanceRef LDS_000_INT_0_p)) )) - (net (rename BGACK_030_INT_0_un3 "BGACK_030_INT_0.un3") (joined - (portRef O (instanceRef BGACK_030_INT_0_r)) - (portRef I1 (instanceRef BGACK_030_INT_0_n)) + (net (rename UDS_000_INT_0_un3 "UDS_000_INT_0.un3") (joined + (portRef O (instanceRef UDS_000_INT_0_r)) + (portRef I1 (instanceRef UDS_000_INT_0_n)) )) - (net (rename BGACK_030_INT_0_un1 "BGACK_030_INT_0.un1") (joined - (portRef O (instanceRef BGACK_030_INT_0_m)) - (portRef I0 (instanceRef BGACK_030_INT_0_p)) + (net (rename UDS_000_INT_0_un1 "UDS_000_INT_0.un1") (joined + (portRef O (instanceRef UDS_000_INT_0_m)) + (portRef I0 (instanceRef UDS_000_INT_0_p)) )) - (net (rename BGACK_030_INT_0_un0 "BGACK_030_INT_0.un0") (joined - (portRef O (instanceRef BGACK_030_INT_0_n)) - (portRef I1 (instanceRef BGACK_030_INT_0_p)) + (net (rename UDS_000_INT_0_un0 "UDS_000_INT_0.un0") (joined + (portRef O (instanceRef UDS_000_INT_0_n)) + (portRef I1 (instanceRef UDS_000_INT_0_p)) )) (net (rename BG_000_0_un3 "BG_000_0.un3") (joined (portRef O (instanceRef BG_000_0_r)) @@ -2798,42 +2611,6 @@ (portRef O (instanceRef FPU_CS_INT_0_n)) (portRef I1 (instanceRef FPU_CS_INT_0_p)) )) - (net (rename DSACK_INT_0_1__un3 "DSACK_INT_0_1_.un3") (joined - (portRef O (instanceRef DSACK_INT_0_1__r)) - (portRef I1 (instanceRef DSACK_INT_0_1__n)) - )) - (net (rename DSACK_INT_0_1__un1 "DSACK_INT_0_1_.un1") (joined - (portRef O (instanceRef DSACK_INT_0_1__m)) - (portRef I0 (instanceRef DSACK_INT_0_1__p)) - )) - (net (rename DSACK_INT_0_1__un0 "DSACK_INT_0_1_.un0") (joined - (portRef O (instanceRef DSACK_INT_0_1__n)) - (portRef I1 (instanceRef DSACK_INT_0_1__p)) - )) - (net (rename VPA_SYNC_0_un3 "VPA_SYNC_0.un3") (joined - (portRef O (instanceRef VPA_SYNC_0_r)) - (portRef I1 (instanceRef VPA_SYNC_0_n)) - )) - (net (rename VPA_SYNC_0_un1 "VPA_SYNC_0.un1") (joined - (portRef O (instanceRef VPA_SYNC_0_m)) - (portRef I0 (instanceRef VPA_SYNC_0_p)) - )) - (net (rename VPA_SYNC_0_un0 "VPA_SYNC_0.un0") (joined - (portRef O (instanceRef VPA_SYNC_0_n)) - (portRef I1 (instanceRef VPA_SYNC_0_p)) - )) - (net (rename AS_000_INT_0_un3 "AS_000_INT_0.un3") (joined - (portRef O (instanceRef AS_000_INT_0_r)) - (portRef I1 (instanceRef AS_000_INT_0_n)) - )) - (net (rename AS_000_INT_0_un1 "AS_000_INT_0.un1") (joined - (portRef O (instanceRef AS_000_INT_0_m)) - (portRef I0 (instanceRef AS_000_INT_0_p)) - )) - (net (rename AS_000_INT_0_un0 "AS_000_INT_0.un0") (joined - (portRef O (instanceRef AS_000_INT_0_n)) - (portRef I1 (instanceRef AS_000_INT_0_p)) - )) (net (rename IPL_030_0_2__un3 "IPL_030_0_2_.un3") (joined (portRef O (instanceRef IPL_030_0_2__r)) (portRef I1 (instanceRef IPL_030_0_2__n)) @@ -2870,17 +2647,29 @@ (portRef O (instanceRef IPL_030_0_0__n)) (portRef I1 (instanceRef IPL_030_0_0__p)) )) - (net (rename SM_AMIGA_D_0_2__un3 "SM_AMIGA_D_0_2_.un3") (joined - (portRef O (instanceRef SM_AMIGA_D_0_2__r)) - (portRef I1 (instanceRef SM_AMIGA_D_0_2__n)) + (net (rename BGACK_030_INT_0_un3 "BGACK_030_INT_0.un3") (joined + (portRef O (instanceRef BGACK_030_INT_0_r)) + (portRef I1 (instanceRef BGACK_030_INT_0_n)) )) - (net (rename SM_AMIGA_D_0_2__un1 "SM_AMIGA_D_0_2_.un1") (joined - (portRef O (instanceRef SM_AMIGA_D_0_2__m)) - (portRef I0 (instanceRef SM_AMIGA_D_0_2__p)) + (net (rename BGACK_030_INT_0_un1 "BGACK_030_INT_0.un1") (joined + (portRef O (instanceRef BGACK_030_INT_0_m)) + (portRef I0 (instanceRef BGACK_030_INT_0_p)) )) - (net (rename SM_AMIGA_D_0_2__un0 "SM_AMIGA_D_0_2_.un0") (joined - (portRef O (instanceRef SM_AMIGA_D_0_2__n)) - (portRef I1 (instanceRef SM_AMIGA_D_0_2__p)) + (net (rename BGACK_030_INT_0_un0 "BGACK_030_INT_0.un0") (joined + (portRef O (instanceRef BGACK_030_INT_0_n)) + (portRef I1 (instanceRef BGACK_030_INT_0_p)) + )) + (net (rename SM_AMIGA_D_0_0__un3 "SM_AMIGA_D_0_0_.un3") (joined + (portRef O (instanceRef SM_AMIGA_D_0_0__r)) + (portRef I1 (instanceRef SM_AMIGA_D_0_0__n)) + )) + (net (rename SM_AMIGA_D_0_0__un1 "SM_AMIGA_D_0_0_.un1") (joined + (portRef O (instanceRef SM_AMIGA_D_0_0__m)) + (portRef I0 (instanceRef SM_AMIGA_D_0_0__p)) + )) + (net (rename SM_AMIGA_D_0_0__un0 "SM_AMIGA_D_0_0_.un0") (joined + (portRef O (instanceRef SM_AMIGA_D_0_0__n)) + (portRef I1 (instanceRef SM_AMIGA_D_0_0__p)) )) (net (rename SM_AMIGA_D_0_1__un3 "SM_AMIGA_D_0_1_.un3") (joined (portRef O (instanceRef SM_AMIGA_D_0_1__r)) @@ -2894,29 +2683,41 @@ (portRef O (instanceRef SM_AMIGA_D_0_1__n)) (portRef I1 (instanceRef SM_AMIGA_D_0_1__p)) )) - (net (rename LDS_000_INT_0_un3 "LDS_000_INT_0.un3") (joined - (portRef O (instanceRef LDS_000_INT_0_r)) - (portRef I1 (instanceRef LDS_000_INT_0_n)) + (net (rename cpu_est_0_1__un3 "cpu_est_0_1_.un3") (joined + (portRef O (instanceRef cpu_est_0_1__r)) + (portRef I1 (instanceRef cpu_est_0_1__n)) )) - (net (rename LDS_000_INT_0_un1 "LDS_000_INT_0.un1") (joined - (portRef O (instanceRef LDS_000_INT_0_m)) - (portRef I0 (instanceRef LDS_000_INT_0_p)) + (net (rename cpu_est_0_1__un1 "cpu_est_0_1_.un1") (joined + (portRef O (instanceRef cpu_est_0_1__m)) + (portRef I0 (instanceRef cpu_est_0_1__p)) )) - (net (rename LDS_000_INT_0_un0 "LDS_000_INT_0.un0") (joined - (portRef O (instanceRef LDS_000_INT_0_n)) - (portRef I1 (instanceRef LDS_000_INT_0_p)) + (net (rename cpu_est_0_1__un0 "cpu_est_0_1_.un0") (joined + (portRef O (instanceRef cpu_est_0_1__n)) + (portRef I1 (instanceRef cpu_est_0_1__p)) )) - (net (rename UDS_000_INT_0_un3 "UDS_000_INT_0.un3") (joined - (portRef O (instanceRef UDS_000_INT_0_r)) - (portRef I1 (instanceRef UDS_000_INT_0_n)) + (net (rename cpu_est_0_2__un3 "cpu_est_0_2_.un3") (joined + (portRef O (instanceRef cpu_est_0_2__r)) + (portRef I1 (instanceRef cpu_est_0_2__n)) )) - (net (rename UDS_000_INT_0_un1 "UDS_000_INT_0.un1") (joined - (portRef O (instanceRef UDS_000_INT_0_m)) - (portRef I0 (instanceRef UDS_000_INT_0_p)) + (net (rename cpu_est_0_2__un1 "cpu_est_0_2_.un1") (joined + (portRef O (instanceRef cpu_est_0_2__m)) + (portRef I0 (instanceRef cpu_est_0_2__p)) )) - (net (rename UDS_000_INT_0_un0 "UDS_000_INT_0.un0") (joined - (portRef O (instanceRef UDS_000_INT_0_n)) - (portRef I1 (instanceRef UDS_000_INT_0_p)) + (net (rename cpu_est_0_2__un0 "cpu_est_0_2_.un0") (joined + (portRef O (instanceRef cpu_est_0_2__n)) + (portRef I1 (instanceRef cpu_est_0_2__p)) + )) + (net (rename cpu_est_0_3__un3 "cpu_est_0_3_.un3") (joined + (portRef O (instanceRef cpu_est_0_3__r)) + (portRef I1 (instanceRef cpu_est_0_3__n)) + )) + (net (rename cpu_est_0_3__un1 "cpu_est_0_3_.un1") (joined + (portRef O (instanceRef cpu_est_0_3__m)) + (portRef I0 (instanceRef cpu_est_0_3__p)) + )) + (net (rename cpu_est_0_3__un0 "cpu_est_0_3_.un0") (joined + (portRef O (instanceRef cpu_est_0_3__n)) + (portRef I1 (instanceRef cpu_est_0_3__p)) )) ) (property orig_inst_of (string "BUS68030")) diff --git a/Logic/BUS68030.prj b/Logic/BUS68030.prj index 97c35d3..9c21018 100644 --- a/Logic/BUS68030.prj +++ b/Logic/BUS68030.prj @@ -1,6 +1,6 @@ #-- Lattice Semiconductor Corporation Ltd. -#-- Synplify OEM project file c:/users/matze/amiga/hardwarehacks/68030-tk/logic\BUS68030.prj -#-- Written on Thu May 15 19:20:46 2014 +#-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj +#-- Written on Thu May 15 22:17:20 2014 #device options diff --git a/Logic/BUS68030.srm b/Logic/BUS68030.srm index d1a95e4..96b6227 100644 --- a/Logic/BUS68030.srm +++ b/Logic/BUS68030.srm @@ -28,14 +28,14 @@ f "c:\program files (x86)\isplever\synpbase\lib\vhd\unsigned.vhd"; #file 7 af .is_vhdl 1; af .child_list "-1"; af .parent_list "-1"; -f "c:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd"; #file 8 +f "c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd"; #file 8 af .is_vhdl 1; af .child_list "-1"; af .parent_list "-1"; VNAME 'mach.MACH_DFF.prim'; # view id 0 VNAME 'mach.DFFRH.prim'; # view id 1 -VNAME 'mach.DFF.prim'; # view id 2 -VNAME 'mach.DFFSH.prim'; # view id 3 +VNAME 'mach.DFFSH.prim'; # view id 2 +VNAME 'mach.DFF.prim'; # view id 3 VNAME 'mach.IBUF.prim'; # view id 4 VNAME 'mach.BUFTH.prim'; # view id 5 VNAME 'mach.OBUF.prim'; # view id 6 @@ -85,40 +85,40 @@ SmwaQQ= )t;h7 fbRjR:jHRMPkRM4kRM4)b; R:fjjsR0k0CRsRkCe;BB fbRjR:jV#NDCNRVDR#Ct;h7 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+oR_Atj_jjjM3k4N; M#R3N_PCM_C0VoDN#.4R6 -n;oqMR1d_jjj_jjY_1hjB_3dkM;M -NRN3#PMC_CV0_D#No46R.no; -M1Rq_jjd_jjj_h1YB3_jk;M4 +n;oAMRtj_jj3_jk;Mj RNM3P#NCC_M0D_VN4o#Rn.6;M oR_q1j_djj_jj1BYh_kj3M -j;N3MR#CNP_0MC_NVDoR#4.;6n -RoMw_uzBQ1_hja_3dkM;M +d;N3MR#CNP_0MC_NVDoR#4.;6n +RoMqj1_djj_j1j_Y_hBjM3k4N; +M#R3N_PCM_C0VoDN#.4R6 +n;oqMR1d_jjj_jjY_1hjB_3jkM;M NRN3#PMC_CV0_D#No46R.no; MuRwz1_B_aQh_kj3M -4;N3MR#CNP_0MC_NVDoR#4.;6n -RoMw_uzBQ1_hja_3jkM;M -NRN3#PMC_CV0_D#No46R.no; -M1R7q_BiQ_haj__43dkM;M -NRN3#PMC_CV0_D#No46R.no; -M1R7q_BiQ_haj__434kM;M -NRN3#PMC_CV0_D#No46R.no; -M1R7q_BiQ_haj__43jkM;M -NRN3#PMC_CV0_D#No46R.no; -MuReqY_1hjB_3dkM;M -NRN3#PMC_CV0_D#No46R.no; -MuReqY_1hjB_34kM;M -NRN3#PMC_CV0_D#No46R.no; -MuReqY_1hjB_3jkM;M -NRN3#PMC_CV0_D#No46R.no; -M1Rq_jjj_aQh_kj3M d;N3MR#CNP_0MC_NVDoR#4.;6n -RoMqj1_jQj_hja_34kM;M +RoMw_uzBQ1_hja_34kM;M NRN3#PMC_CV0_D#No46R.no; -M1Rq_jjj_aQh_kj3M +MuRwz1_B_aQh_kj3M j;N3MR#CNP_0MC_NVDoR#4.;6n RoMQ_upj_djj__.3dkM;M NRN3#PMC_CV0_D#No46R.no; @@ -484,47 +472,45 @@ MuRQpd_jj__jjk_3M 4;N3MR#CNP_0MC_NVDoR#4.;6n RoMQ_upj_djj__j3jkM;M NRN3#PMC_CV0_D#No46R.no; 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+R:fjjNRlOmER)b.RsRHlO_bkC_#0j__.3Sb +m_=h4Sg +QOj=bCk_#j0__3._k +M4S=Q4O_bkC_#0j__.3jkM;R +sfjj:ROlNEhRQesRbHOlRbCk_#j0__3d_sm +S=kOb_0C#_dj__M3kdQ +SjD=O k\3MOd_Dj _j8j_8s; +R:fjjNRlOqERhR7.blsHRkOb_0C#_dj__ +3lSOm=bCk_#j0__3d_k +M4S=QjO\D 3kOb_0C#_r44dS9 +QO4=D3 \k_MdO_D j_jj8 +8;sjRf:ljRNROEq.h7RHbslbROk#_C0__jdM_3 +=SmO_bkC_#0j__d3jkM +jSQ=kOb_0C#r +d9S=Q4O_bkC_#0j__d3dkM;R +sfjj:ROlNE)Rm.sRbHOlRbCk_#j0__3d_bm +S=.h_jQ +Sjb=Ok#_C0__jdk_3MS4 +QO4=bCk_#j0__3d_k;Mj diff --git a/Logic/BUS68030.srr b/Logic/BUS68030.srr index 15c1c83..b6c1b9f 100644 --- a/Logic/BUS68030.srr +++ b/Logic/BUS68030.srr @@ -6,32 +6,32 @@ #Implementation: logic $ Start of Compile -#Thu May 15 19:20:46 2014 +#Thu May 15 22:17:20 2014 Synopsys VHDL Compiler, version comp201209rcp1, Build 283R, built Mar 19 2013 @N|Running in 64-bit mode Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc. @N: CD720 :"C:\Program Files (x86)\ispLever\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns -@N:"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":6:7:6:14|Top entity is set to BUS68030. -File C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd changed - recompiling +@N:"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":6:7:6:14|Top entity is set to BUS68030. +File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling VHDL syntax check successful! -File C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd changed - recompiling -@N: CD630 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":6:7:6:14|Synthesizing work.bus68030.behavioral -@W: CD638 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":109:7:109:15|Signal clk_030_d is undriven +File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling +@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":6:7:6:14|Synthesizing work.bus68030.behavioral +@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:7:109:15|Signal clk_030_d is undriven Post processing for work.bus68030.behavioral -@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":105:52:105:55|Pruning register VMA_INT_D -@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":91:32:91:34|Pruning register CLK_REF(1 downto 0) -@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":220:2:220:3|Pruning register AS_000_START -@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":113:38:113:40|Pruning register cpu_est_d(3 downto 0) -@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":112:37:112:39|Pruning register FALLING_CLK_AMIGA -@A: CL282 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":100:29:100:31|Feedback mux created for signal SM_AMIGA_D[2:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. -@W: CL190 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":100:29:100:31|Optimizing register bit DSACK_INT(0) to a constant 1 -@W: CL260 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":100:29:100:31|Pruning register bit 0 of DSACK_INT(1 downto 0) -@W: CL189 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":124:2:124:3|Register bit CLK_CNT(1) is always 0, optimizing ... -@W: CL260 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":124:2:124:3|Pruning register bit 1 of CLK_CNT(1 downto 0) -@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":113:38:113:40|Trying to extract state machine for register cpu_est -@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":220:2:220:3|Trying to extract state machine for register SM_AMIGA +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":105:52:105:55|Pruning register VMA_INT_D +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":91:32:91:34|Pruning register CLK_REF(1 downto 0) +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":220:2:220:3|Pruning register AS_000_START +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":113:38:113:40|Pruning register CLK_000_CNT(3 downto 0) +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":112:37:112:39|Pruning register FALLING_CLK_AMIGA +@A: CL282 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":100:29:100:31|Feedback mux created for signal SM_AMIGA_D[2:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. +@W: CL190 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":100:29:100:31|Optimizing register bit DSACK_INT(0) to a constant 1 +@W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":100:29:100:31|Pruning register bit 0 of DSACK_INT(1 downto 0) +@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:2:124:3|Register bit CLK_CNT(1) is always 0, optimizing ... +@W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:2:124:3|Pruning register bit 1 of CLK_CNT(1 downto 0) +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":113:38:113:40|Trying to extract state machine for register cpu_est +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":220:2:220:3|Trying to extract state machine for register SM_AMIGA Extracted state machine for register SM_AMIGA State machine has 8 reachable states with original encodings of: 000 @@ -42,10 +42,10 @@ State machine has 8 reachable states with original encodings of: 101 110 111 -@W: CL249 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":220:2:220:3|Initial value is not supported on state machine SM_AMIGA +@W: CL249 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":220:2:220:3|Initial value is not supported on state machine SM_AMIGA @END Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Thu May 15 19:20:46 2014 +# Thu May 15 22:17:20 2014 ###########################################################] Map & Optimize Report @@ -64,22 +64,22 @@ original code -> new code 101 -> 00100000 110 -> 01000000 111 -> 10000000 -@N: MO106 :"c:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":160:4:160:7|Found ROM, 'clk\.cpu_est_11[3:0]', 16 words by 4 bits +@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":160:4:160:7|Found ROM, 'clk\.cpu_est_11[3:0]', 16 words by 4 bits --------------------------------------- Resource Usage Report Simple gate primitives: DFFRH 7 uses -DFF 19 uses DFFSH 16 uses +DFF 19 uses IBUF 35 uses BUFTH 7 uses OBUF 15 uses BI_DIR 2 uses -AND2 179 uses -INV 143 uses +AND2 163 uses +INV 126 uses OR2 20 uses -XOR2 8 uses +XOR2 5 uses @N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis. @@ -89,6 +89,6 @@ Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 95MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Thu May 15 19:20:48 2014 +# Thu May 15 22:17:22 2014 ###########################################################] diff --git a/Logic/BUS68030.srs b/Logic/BUS68030.srs index cf01d59..32e46a3 100644 Binary files a/Logic/BUS68030.srs and b/Logic/BUS68030.srs differ diff --git a/Logic/bus68030.exf b/Logic/bus68030.exf index 80597ca..122bd13 100644 --- a/Logic/bus68030.exf +++ b/Logic/bus68030.exf @@ -55,7 +55,7 @@ Section Member Rename Array-Notation Array Number Port FC_0_ FC[0] 4 1 End Section Cross Reference File -Design 'BUS68030' created Thu May 15 19:20:52 2014 +Design 'BUS68030' created Thu May 15 22:17:27 2014 Type New Name Original Name // ---------------------------------------------------------------------- Inst i_z2M2M AS_000 @@ -65,145 +65,22 @@ Design 'BUS68030' created Thu May 15 19:20:52 2014 Inst i_z4141 DTACK Inst i_z4343 AVEC_EXP Inst i_z4F4F CIIN - Inst clk_cpu_est_11_0_i_3_ clk.cpu_est_11_0_i[3] - Inst SM_AMIGA_ns_o2_i_5_ SM_AMIGA_ns_o2_i[5] - Inst SM_AMIGA_ns_o2_i_4_ SM_AMIGA_ns_o2_i[4] - Inst state_machine_un9_clk_000_d_i_o3_i state_machine.un9_clk_000_d_i_o3_i - Inst SM_AMIGA_ns_i_5_ SM_AMIGA_ns_i[5] - Inst SM_AMIGA_ns_i_4_ SM_AMIGA_ns_i[4] - Inst clk_cpu_est_11_0_o4_i_1_ clk.cpu_est_11_0_o4_i[1] - Inst clk_cpu_est_11_0_o4_i_3_ clk.cpu_est_11_0_o4_i[3] - Inst clk_cpu_est_11_0_i_1_ clk.cpu_est_11_0_i[1] - Inst cpu_est_0_1__r cpu_est_0_1_.r - Inst cpu_est_0_1__m cpu_est_0_1_.m - Inst cpu_est_0_1__n cpu_est_0_1_.n - Inst cpu_est_0_1__p cpu_est_0_1_.p + Inst SM_AMIGA_ns_i_7_ SM_AMIGA_ns_i[7] + Inst SM_AMIGA_ns_i_o2_i_6_ SM_AMIGA_ns_i_o2_i[6] + Inst state_machine_un57_clk_000_d_i state_machine.un57_clk_000_d_i + Inst SM_AMIGA_D_0_2__r SM_AMIGA_D_0_2_.r + Inst SM_AMIGA_D_0_2__m SM_AMIGA_D_0_2_.m + Inst SM_AMIGA_D_0_2__n SM_AMIGA_D_0_2_.n + Inst SM_AMIGA_D_0_2__p SM_AMIGA_D_0_2_.p + Inst DSACK_INT_0_1__r DSACK_INT_0_1_.r + Inst DSACK_INT_0_1__m DSACK_INT_0_1_.m + Inst DSACK_INT_0_1__n DSACK_INT_0_1_.n + Inst DSACK_INT_0_1__p DSACK_INT_0_1_.p Inst VMA_INT_0_r VMA_INT_0.r Inst VMA_INT_0_m VMA_INT_0.m Inst VMA_INT_0_n VMA_INT_0.n Inst VMA_INT_0_p VMA_INT_0.p - Inst clk_cpu_est_11_0_a4_1_1_ clk.cpu_est_11_0_a4_1[1] - Inst cpu_est_i_2_ cpu_est_i[2] - Inst cpu_est_i_3_ cpu_est_i[3] - Inst clk_cpu_est_11_0_a4_0_1_ clk.cpu_est_11_0_a4_0[1] - Inst cpu_est_i_0_ cpu_est_i[0] - Inst clk_cpu_est_11_0_a4_1_ clk.cpu_est_11_0_a4[1] - Inst SM_AMIGA_4_ SM_AMIGA[4] - Inst SM_AMIGA_3_ SM_AMIGA[3] - Inst SM_AMIGA_2_ SM_AMIGA[2] - Inst SM_AMIGA_1_ SM_AMIGA[1] - Inst clk_un3_clk_000_dd clk.un3_clk_000_dd - Inst SM_AMIGA_0_ SM_AMIGA[0] - Inst cpu_est_0_3__r cpu_est_0_3_.r - Inst cpu_est_0_ cpu_est[0] - Inst cpu_est_0_3__m cpu_est_0_3_.m - Inst cpu_est_1_ cpu_est[1] - Inst cpu_est_0_3__n cpu_est_0_3_.n - Inst cpu_est_2_ cpu_est[2] - Inst cpu_est_0_3__p cpu_est_0_3_.p - Inst cpu_est_3_ cpu_est[3] - Inst cpu_est_0_2__r cpu_est_0_2_.r - Inst SM_AMIGA_7_ SM_AMIGA[7] - Inst cpu_est_0_2__m cpu_est_0_2_.m - Inst SM_AMIGA_6_ SM_AMIGA[6] - Inst cpu_est_0_2__n cpu_est_0_2_.n - Inst SM_AMIGA_5_ SM_AMIGA[5] - Inst cpu_est_0_2__p cpu_est_0_2_.p - Inst CLK_000_CNT_0_ CLK_000_CNT[0] - Inst CLK_000_CNT_1_ CLK_000_CNT[1] - Inst SM_AMIGA_ns_o2_5_ SM_AMIGA_ns_o2[5] - Inst CLK_000_CNT_2_ CLK_000_CNT[2] - Inst CLK_000_CNT_3_ CLK_000_CNT[3] - Inst SM_AMIGA_D_0_ SM_AMIGA_D[0] - Inst cpu_est_0_0_ cpu_est_0[0] - Inst SM_AMIGA_D_1_ SM_AMIGA_D[1] - Inst SM_AMIGA_D_2_ SM_AMIGA_D[2] - Inst SM_AMIGA_ns_i_a2_0_2_6_ SM_AMIGA_ns_i_a2_0_2[6] - Inst IPL_030DFFSH_0_ IPL_030DFFSH[0] - Inst IPL_030DFFSH_1_ IPL_030DFFSH[1] - Inst cpu_est_i_1_ cpu_est_i[1] - Inst IPL_030DFFSH_2_ IPL_030DFFSH[2] - Inst clk_cpu_est_11_0_o4_3_ clk.cpu_est_11_0_o4[3] - Inst clk_cpu_est_11_0_o4_1_ clk.cpu_est_11_0_o4[1] - Inst clk_cpu_est_11_i_2_ clk.cpu_est_11_i[2] - Inst clk_cpu_est_11_0_a4_0_3_ clk.cpu_est_11_0_a4_0[3] - Inst clk_cpu_est_11_0_a4_3_ clk.cpu_est_11_0_a4[3] - Inst clk_cpu_est_11_0_a4_2_1_ clk.cpu_est_11_0_a4_2[1] - Inst SM_AMIGA_ns_i_2_ SM_AMIGA_ns_i[2] - Inst SM_AMIGA_ns_4_ SM_AMIGA_ns[4] - Inst DSACK_INT_1_ DSACK_INT[1] - Inst SM_AMIGA_ns_5_ SM_AMIGA_ns[5] - Inst state_machine_un9_clk_000_d_i_o3 state_machine.un9_clk_000_d_i_o3 - Inst SM_AMIGA_ns_o2_4_ SM_AMIGA_ns_o2[4] - Inst SM_AMIGA_i_4_ SM_AMIGA_i[4] - Inst SM_AMIGA_i_6_ SM_AMIGA_i[6] - Inst CLK_CNT_0_ CLK_CNT[0] - Inst DTACK_SYNC_0_r DTACK_SYNC_0.r - Inst DTACK_SYNC_0_m DTACK_SYNC_0.m - Inst DTACK_SYNC_0_n DTACK_SYNC_0.n - Inst DTACK_SYNC_0_p DTACK_SYNC_0.p - Inst SM_AMIGA_ns_i_0_ SM_AMIGA_ns_i[0] - Inst SM_AMIGA_i_0_ SM_AMIGA_i[0] - Inst SIZE_0_ SIZE[0] - Inst SM_AMIGA_ns_i_o2_0_ SM_AMIGA_ns_i_o2[0] - Inst SIZE_1_ SIZE[1] - Inst A_0_ A[0] - Inst SM_AMIGA_D_0_0__r SM_AMIGA_D_0_0_.r - Inst A_16_ A[16] - Inst SM_AMIGA_D_0_0__m SM_AMIGA_D_0_0_.m - Inst A_17_ A[17] - Inst SM_AMIGA_D_0_0__n SM_AMIGA_D_0_0_.n - Inst A_18_ A[18] - Inst SM_AMIGA_D_0_0__p SM_AMIGA_D_0_0_.p - Inst A_19_ A[19] - Inst state_machine_un15_clk_000_d state_machine.un15_clk_000_d - Inst A_20_ A[20] - Inst A_21_ A[21] - Inst state_machine_un15_clk_000_d_i state_machine.un15_clk_000_d_i - Inst A_22_ A[22] - Inst A_23_ A[23] - Inst A_24_ A[24] - Inst SM_AMIGA_ns_i_a3_2_ SM_AMIGA_ns_i_a3[2] - Inst A_25_ A[25] - Inst SM_AMIGA_ns_a3_4_ SM_AMIGA_ns_a3[4] - Inst A_26_ A[26] - Inst SM_AMIGA_ns_a3_0_4_ SM_AMIGA_ns_a3_0[4] - Inst A_27_ A[27] - Inst SM_AMIGA_i_5_ SM_AMIGA_i[5] - Inst A_28_ A[28] - Inst SM_AMIGA_ns_i_a2_3_ SM_AMIGA_ns_i_a2[3] - Inst A_29_ A[29] - Inst BGACK_030_INT_0_r BGACK_030_INT_0.r - Inst A_30_ A[30] - Inst BGACK_030_INT_0_m BGACK_030_INT_0.m - Inst A_31_ A[31] - Inst BGACK_030_INT_0_n BGACK_030_INT_0.n - Inst BGACK_030_INT_0_p BGACK_030_INT_0.p - Inst BG_000_0_r BG_000_0.r - Inst BG_000_0_m BG_000_0.m - Inst BG_000_0_n BG_000_0.n - Inst BG_000_0_p BG_000_0.p - Inst AS_030_000_SYNC_0_r AS_030_000_SYNC_0.r - Inst AS_030_000_SYNC_0_m AS_030_000_SYNC_0.m - Inst AS_030_000_SYNC_0_n AS_030_000_SYNC_0.n - Inst AS_030_000_SYNC_0_p AS_030_000_SYNC_0.p - Inst FPU_CS_INT_0_r FPU_CS_INT_0.r - Inst FPU_CS_INT_0_m FPU_CS_INT_0.m - Inst FPU_CS_INT_0_n FPU_CS_INT_0.n - Inst IPL_030_0_ IPL_030[0] - Inst FPU_CS_INT_0_p FPU_CS_INT_0.p - Inst IPL_030_1_ IPL_030[1] - Inst IPL_030_2_ IPL_030[2] - Inst DSACK_INT_0_1__r DSACK_INT_0_1_.r - Inst IPL_0_ IPL[0] - Inst DSACK_INT_0_1__m DSACK_INT_0_1_.m - Inst IPL_1_ IPL[1] - Inst DSACK_INT_0_1__n DSACK_INT_0_1_.n - Inst IPL_2_ IPL[2] - Inst DSACK_INT_0_1__p DSACK_INT_0_1_.p - Inst DSACK_0_ DSACK[0] Inst VPA_SYNC_0_r VPA_SYNC_0.r - Inst DSACK_1_ DSACK[1] Inst VPA_SYNC_0_m VPA_SYNC_0.m Inst VPA_SYNC_0_n VPA_SYNC_0.n Inst VPA_SYNC_0_p VPA_SYNC_0.p @@ -211,66 +88,10 @@ Design 'BUS68030' created Thu May 15 19:20:52 2014 Inst AS_000_INT_0_m AS_000_INT_0.m Inst AS_000_INT_0_n AS_000_INT_0.n Inst AS_000_INT_0_p AS_000_INT_0.p - Inst state_machine_un14_as_000_int state_machine.un14_as_000_int - Inst FC_0_ FC[0] - Inst FC_1_ FC[1] - Inst SM_AMIGA_i_7_ SM_AMIGA_i[7] - Inst SM_AMIGA_ns_i_a3_0_ SM_AMIGA_ns_i_a3[0] - Inst SM_AMIGA_ns_i_a3_1_ SM_AMIGA_ns_i_a3[1] - Inst state_machine_un5_clk_030_i_a3 state_machine.un5_clk_030_i_a3 - Inst clk_cpu_est_11_0_a4_1_1_3_ clk.cpu_est_11_0_a4_1_1[3] - Inst clk_cpu_est_11_0_a4_1_3_ clk.cpu_est_11_0_a4_1[3] - Inst state_machine_un42_clk_030_i state_machine.un42_clk_030_i - Inst state_machine_un17_clk_030 state_machine.un17_clk_030 - Inst un9_i_a3_2_2_ un9_i_a3_2[2] - Inst un9_i_a3_2_ un9_i_a3[2] - Inst state_machine_un1_clk_030 state_machine.un1_clk_030 - Inst state_machine_un4_bgack_000 state_machine.un4_bgack_000 - Inst A_i_19_ A_i[19] - Inst A_i_18_ A_i[18] - Inst A_i_16_ A_i[16] - Inst IPL_030_0_2__r IPL_030_0_2_.r - Inst IPL_030_0_2__m IPL_030_0_2_.m - Inst IPL_030_0_2__n IPL_030_0_2_.n - Inst IPL_030_0_2__p IPL_030_0_2_.p - Inst IPL_030_0_1__r IPL_030_0_1_.r - Inst clk_cpu_est_11_i_a4_0_1_2_ clk.cpu_est_11_i_a4_0_1[2] - Inst IPL_030_0_1__m IPL_030_0_1_.m - Inst clk_cpu_est_11_i_a4_0_2_ clk.cpu_est_11_i_a4_0[2] - Inst IPL_030_0_1__n IPL_030_0_1_.n - Inst clk_cpu_est_11_i_a4_1_2_ clk.cpu_est_11_i_a4_1[2] - Inst IPL_030_0_1__p IPL_030_0_1_.p - Inst clk_cpu_est_11_i_a4_2_ clk.cpu_est_11_i_a4[2] - Inst IPL_030_0_0__r IPL_030_0_0_.r - Inst SM_AMIGA_ns_i_a2_0_2_0_6_ SM_AMIGA_ns_i_a2_0_2_0[6] - Inst IPL_030_0_0__m IPL_030_0_0_.m - Inst SM_AMIGA_ns_i_a2_0_6_ SM_AMIGA_ns_i_a2_0[6] - Inst IPL_030_0_0__n IPL_030_0_0_.n - Inst un9_i_a3_1_0_ un9_i_a3_1[0] - Inst IPL_030_0_0__p IPL_030_0_0_.p - Inst un9_i_a3_0_ un9_i_a3[0] - Inst SM_AMIGA_ns_a3_0_5_ SM_AMIGA_ns_a3_0[5] - Inst un9_i_a3_1_1_ un9_i_a3_1[1] - Inst state_machine_LDS_000_INT_8 state_machine.LDS_000_INT_8 - Inst un9_i_a3_1_ un9_i_a3[1] - Inst state_machine_UDS_000_INT_8 state_machine.UDS_000_INT_8 - Inst state_machine_un42_clk_030_1 state_machine.un42_clk_030_1 - Inst state_machine_un42_clk_030_2 state_machine.un42_clk_030_2 - Inst state_machine_un42_clk_030_3 state_machine.un42_clk_030_3 - Inst SM_AMIGA_D_0_2__r SM_AMIGA_D_0_2_.r - Inst state_machine_un42_clk_030_4 state_machine.un42_clk_030_4 - Inst SM_AMIGA_D_0_2__m SM_AMIGA_D_0_2_.m - Inst state_machine_un42_clk_030_5 state_machine.un42_clk_030_5 - Inst SM_AMIGA_D_0_2__n SM_AMIGA_D_0_2_.n - Inst state_machine_un42_clk_030 state_machine.un42_clk_030 - Inst SM_AMIGA_D_0_2__p SM_AMIGA_D_0_2_.p - Inst SM_AMIGA_ns_a3_1_5_ SM_AMIGA_ns_a3_1[5] - Inst SM_AMIGA_ns_a3_5_ SM_AMIGA_ns_a3[5] - Inst SM_AMIGA_D_0_1__r SM_AMIGA_D_0_1_.r - Inst un9_i_a3_1_2_ un9_i_a3_1[2] - Inst SM_AMIGA_D_0_1__m SM_AMIGA_D_0_1_.m - Inst SM_AMIGA_D_0_1__n SM_AMIGA_D_0_1_.n - Inst SM_AMIGA_D_0_1__p SM_AMIGA_D_0_1_.p + Inst DTACK_SYNC_0_r DTACK_SYNC_0.r + Inst DTACK_SYNC_0_m DTACK_SYNC_0.m + Inst DTACK_SYNC_0_n DTACK_SYNC_0.n + Inst DTACK_SYNC_0_p DTACK_SYNC_0.p Inst LDS_000_INT_0_r LDS_000_INT_0.r Inst LDS_000_INT_0_m LDS_000_INT_0.m Inst LDS_000_INT_0_n LDS_000_INT_0.n @@ -279,285 +100,399 @@ Design 'BUS68030' created Thu May 15 19:20:52 2014 Inst UDS_000_INT_0_m UDS_000_INT_0.m Inst UDS_000_INT_0_n UDS_000_INT_0.n Inst UDS_000_INT_0_p UDS_000_INT_0.p - Inst SM_AMIGA_ns_i_o2_1_ SM_AMIGA_ns_i_o2[1] - Inst SM_AMIGA_ns_i_o2_2_ SM_AMIGA_ns_i_o2[2] - Inst SM_AMIGA_ns_i_1_ SM_AMIGA_ns_i[1] - Inst SM_AMIGA_ns_i_a2_0_1_6_ SM_AMIGA_ns_i_a2_0_1[6] - Inst SM_AMIGA_ns_i_a3_0_1_ SM_AMIGA_ns_i_a3_0[1] - Inst state_machine_un25_clk_000_d state_machine.un25_clk_000_d - Inst state_machine_un67_clk_000_d state_machine.un67_clk_000_d - Inst SM_AMIGA_ns_i_1_6_ SM_AMIGA_ns_i_1[6] - Inst state_machine_un80_clk_000_d state_machine.un80_clk_000_d + Inst SM_AMIGA_6_ SM_AMIGA[6] + Inst state_machine_un57_clk_000_d state_machine.un57_clk_000_d + Inst SM_AMIGA_5_ SM_AMIGA[5] + Inst SM_AMIGA_4_ SM_AMIGA[4] + Inst SM_AMIGA_3_ SM_AMIGA[3] + Inst SM_AMIGA_2_ SM_AMIGA[2] + Inst SM_AMIGA_1_ SM_AMIGA[1] + Inst state_machine_un13_clk_000_d_i state_machine.un13_clk_000_d_i + Inst SM_AMIGA_0_ SM_AMIGA[0] + Inst state_machine_un8_clk_000_d_i state_machine.un8_clk_000_d_i + Inst IPL_030DFFSH_1_ IPL_030DFFSH[1] + Inst IPL_030DFFSH_2_ IPL_030DFFSH[2] + Inst cpu_est_0_ cpu_est[0] + Inst cpu_est_1_ cpu_est[1] + Inst state_machine_un13_as_000_int state_machine.un13_as_000_int + Inst cpu_est_2_ cpu_est[2] + Inst cpu_est_3_ cpu_est[3] + Inst SM_AMIGA_7_ SM_AMIGA[7] + Inst cpu_est_d_0_ cpu_est_d[0] + Inst clk_RISING_CLK_AMIGA_1 clk.RISING_CLK_AMIGA_1 + Inst cpu_est_d_1_ cpu_est_d[1] + Inst cpu_est_d_i_3_ cpu_est_d_i[3] + Inst cpu_est_d_2_ cpu_est_d[2] + Inst cpu_est_d_i_0_ cpu_est_d_i[0] + Inst cpu_est_d_3_ cpu_est_d[3] + Inst SM_AMIGA_D_0_ SM_AMIGA_D[0] Inst SM_AMIGA_ns_i_6_ SM_AMIGA_ns_i[6] - Inst state_machine_AS_030_000_SYNC_3_1 state_machine.AS_030_000_SYNC_3_1 - Inst SM_AMIGA_i_3_ SM_AMIGA_i[3] - Inst state_machine_AS_030_000_SYNC_3 state_machine.AS_030_000_SYNC_3 - Inst SM_AMIGA_ns_i_a3_6_ SM_AMIGA_ns_i_a3[6] - Inst SM_AMIGA_ns_a3_0_7_ SM_AMIGA_ns_a3_0[7] - Inst SM_AMIGA_ns_7_ SM_AMIGA_ns[7] - Inst clk_cpu_est_11_0_1_3_ clk.cpu_est_11_0_1[3] - Inst SM_AMIGA_ns_i_3_ SM_AMIGA_ns_i[3] - Inst clk_cpu_est_11_0_3_ clk.cpu_est_11_0[3] - Inst SM_AMIGA_i_2_ SM_AMIGA_i[2] - Inst clk_cpu_est_11_0_1_1_ clk.cpu_est_11_0_1[1] + Inst SM_AMIGA_D_1_ SM_AMIGA_D[1] + Inst SM_AMIGA_ns_5_ SM_AMIGA_ns[5] + Inst SM_AMIGA_D_2_ SM_AMIGA_D[2] + Inst SM_AMIGA_ns_2_ SM_AMIGA_ns[2] + Inst IPL_030DFFSH_0_ IPL_030DFFSH[0] Inst SM_AMIGA_i_1_ SM_AMIGA_i[1] - Inst clk_cpu_est_11_0_2_1_ clk.cpu_est_11_0_2[1] + Inst SM_AMIGA_i_2_ SM_AMIGA_i[2] + Inst SM_AMIGA_ns_i_a2_0_6_ SM_AMIGA_ns_i_a2_0[6] + Inst state_machine_un13_clk_000_d_1_i state_machine.un13_clk_000_d_1_i + Inst SM_AMIGA_ns_a2_7_ SM_AMIGA_ns_a2[7] Inst SM_AMIGA_ns_i_a2_6_ SM_AMIGA_ns_i_a2[6] - Inst clk_cpu_est_11_0_1_ clk.cpu_est_11_0[1] - Inst SM_AMIGA_ns_a3_7_ SM_AMIGA_ns_a3[7] - Inst state_machine_un67_clk_000_d_i state_machine.un67_clk_000_d_i - Inst state_machine_un78_clk_000_d_i state_machine.un78_clk_000_d_i - Inst clk_RISING_CLK_AMIGA_1_i clk.RISING_CLK_AMIGA_1_i - Inst un1_CLK_000_CNT_0_ un1_CLK_000_CNT[0] - Inst un1_CLK_000_CNT_1_ un1_CLK_000_CNT[1] - Inst SM_AMIGA_ns_i_o2_i_6_ SM_AMIGA_ns_i_o2_i[6] - Inst un1_CLK_000_CNT_2_ un1_CLK_000_CNT[2] - Inst CLK_000_CNT_i_1_ CLK_000_CNT_i[1] - Inst un1_CLK_000_CNT_3_ un1_CLK_000_CNT[3] - Inst CLK_000_CNT_i_0_ CLK_000_CNT_i[0] - Inst CLK_000_CNT_i_3_ CLK_000_CNT_i[3] - Inst SM_AMIGA_ns_a3_0_1_7_ SM_AMIGA_ns_a3_0_1[7] - Inst CLK_000_CNT_i_2_ CLK_000_CNT_i[2] + Inst DSACK_INT_1_ DSACK_INT[1] + Inst SM_AMIGA_ns_a2_5_ SM_AMIGA_ns_a2[5] + Inst SM_AMIGA_ns_a2_2_ SM_AMIGA_ns_a2[2] + Inst state_machine_LDS_000_INT_8 state_machine.LDS_000_INT_8 + Inst state_machine_UDS_000_INT_8 state_machine.UDS_000_INT_8 + Inst BG_000_0_r BG_000_0.r + Inst BG_000_0_m BG_000_0.m + Inst BG_000_0_n BG_000_0.n + Inst CLK_CNT_0_ CLK_CNT[0] + Inst BG_000_0_p BG_000_0.p + Inst AS_030_000_SYNC_0_r AS_030_000_SYNC_0.r + Inst AS_030_000_SYNC_0_m AS_030_000_SYNC_0.m + Inst AS_030_000_SYNC_0_n AS_030_000_SYNC_0.n + Inst AS_030_000_SYNC_0_p AS_030_000_SYNC_0.p + Inst FPU_CS_INT_0_r FPU_CS_INT_0.r + Inst FPU_CS_INT_0_m FPU_CS_INT_0.m + Inst FPU_CS_INT_0_n FPU_CS_INT_0.n + Inst FPU_CS_INT_0_p FPU_CS_INT_0.p + Inst SIZE_0_ SIZE[0] + Inst state_machine_un13_clk_000_d_1 state_machine.un13_clk_000_d_1 + Inst SIZE_1_ SIZE[1] + Inst cpu_est_i_3_ cpu_est_i[3] + Inst A_0_ A[0] + Inst A_16_ A[16] + Inst A_17_ A[17] + Inst A_18_ A[18] + Inst A_19_ A[19] + Inst SM_AMIGA_i_3_ SM_AMIGA_i[3] + Inst A_20_ A[20] + Inst SM_AMIGA_i_0_ SM_AMIGA_i[0] + Inst A_21_ A[21] Inst SM_AMIGA_ns_i_o2_6_ SM_AMIGA_ns_i_o2[6] - Inst clk_un1_clk_000_i clk.un1_clk_000_i - Inst clk_un1_clk_000_i_a3 clk.un1_clk_000_i_a3 - Inst clk_RISING_CLK_AMIGA_1_0_a3 clk.RISING_CLK_AMIGA_1_0_a3 - Inst state_machine_un25_clk_000_d_1 state_machine.un25_clk_000_d_1 - Inst state_machine_un78_clk_000_d state_machine.un78_clk_000_d - Inst state_machine_AS_030_000_SYNC_3_i state_machine.AS_030_000_SYNC_3_i - Inst A_i_24_ A_i[24] - Inst A_i_25_ A_i[25] + Inst A_22_ A[22] + Inst SM_AMIGA_ns_7_ SM_AMIGA_ns[7] + Inst A_23_ A[23] + Inst A_24_ A[24] + Inst A_25_ A[25] + Inst state_machine_un42_clk_030_i state_machine.un42_clk_030_i + Inst A_26_ A[26] + Inst A_27_ A[27] + Inst state_machine_un17_clk_030 state_machine.un17_clk_030 + Inst A_28_ A[28] + Inst A_29_ A[29] + Inst state_machine_un1_clk_030 state_machine.un1_clk_030 + Inst A_30_ A[30] + Inst state_machine_un4_bgack_000 state_machine.un4_bgack_000 + Inst A_31_ A[31] + Inst A_i_19_ A_i[19] + Inst A_i_18_ A_i[18] + Inst A_i_16_ A_i[16] + Inst IPL_030_0_2__r IPL_030_0_2_.r + Inst IPL_030_0_2__m IPL_030_0_2_.m + Inst IPL_030_0_2__n IPL_030_0_2_.n + Inst IPL_030_0_2__p IPL_030_0_2_.p + Inst IPL_030_0_1__r IPL_030_0_1_.r + Inst IPL_030_0_1__m IPL_030_0_1_.m + Inst IPL_030_0_1__n IPL_030_0_1_.n + Inst IPL_030_0_1__p IPL_030_0_1_.p + Inst IPL_030_0_0__r IPL_030_0_0_.r + Inst IPL_030_0_0__m IPL_030_0_0_.m + Inst IPL_030_0_ IPL_030[0] + Inst IPL_030_0_0__n IPL_030_0_0_.n + Inst IPL_030_1_ IPL_030[1] + Inst IPL_030_0_0__p IPL_030_0_0_.p + Inst IPL_030_2_ IPL_030[2] + Inst BGACK_030_INT_0_r BGACK_030_INT_0.r + Inst IPL_0_ IPL[0] + Inst BGACK_030_INT_0_m BGACK_030_INT_0.m + Inst IPL_1_ IPL[1] + Inst BGACK_030_INT_0_n BGACK_030_INT_0.n + Inst IPL_2_ IPL[2] + Inst BGACK_030_INT_0_p BGACK_030_INT_0.p + Inst DSACK_0_ DSACK[0] + Inst clk_cpu_est_11_0_o4_1_ clk.cpu_est_11_0_o4[1] + Inst DSACK_1_ DSACK[1] + Inst clk_cpu_est_11_0_o4_3_ clk.cpu_est_11_0_o4[3] + Inst cpu_est_i_2_ cpu_est_i[2] + Inst clk_cpu_est_11_0_a4_1_3_ clk.cpu_est_11_0_a4_1[3] + Inst SM_AMIGA_i_4_ SM_AMIGA_i[4] + Inst SM_AMIGA_i_6_ SM_AMIGA_i[6] + Inst cpu_est_i_0_ cpu_est_i[0] + Inst FC_0_ FC[0] + Inst FC_1_ FC[1] + Inst cpu_est_i_1_ cpu_est_i[1] + Inst cpu_est_0_0_ cpu_est_0[0] + Inst SM_AMIGA_ns_i_a2_1_ SM_AMIGA_ns_i_a2[1] + Inst SM_AMIGA_i_5_ SM_AMIGA_i[5] + Inst SM_AMIGA_ns_i_a2_3_ SM_AMIGA_ns_i_a2[3] + Inst SM_AMIGA_ns_0_ SM_AMIGA_ns[0] + Inst SM_AMIGA_ns_i_3_ SM_AMIGA_ns_i[3] + Inst SM_AMIGA_ns_i_4_ SM_AMIGA_ns_i[4] + Inst SM_AMIGA_ns_i_o2_4_ SM_AMIGA_ns_i_o2[4] + Inst un9_i_a2_1_0_ un9_i_a2_1[0] + Inst clk_cpu_est_11_0_a4_1_ clk.cpu_est_11_0_a4[1] + Inst un9_i_a2_0_ un9_i_a2[0] + Inst clk_cpu_est_11_0_a4_0_1_ clk.cpu_est_11_0_a4_0[1] + Inst SM_AMIGA_ns_a2_0_1_5_ SM_AMIGA_ns_a2_0_1[5] + Inst clk_cpu_est_11_0_a4_1_1_ clk.cpu_est_11_0_a4_1[1] + Inst SM_AMIGA_ns_a2_0_5_ SM_AMIGA_ns_a2_0[5] + Inst clk_cpu_est_11_0_a4_2_1_ clk.cpu_est_11_0_a4_2[1] + Inst clk_cpu_est_11_0_a4_3_ clk.cpu_est_11_0_a4[3] + Inst clk_cpu_est_11_0_a4_0_3_ clk.cpu_est_11_0_a4_0[3] + Inst clk_cpu_est_11_i_2_ clk.cpu_est_11_i[2] + Inst clk_cpu_est_11_i_o4_2_ clk.cpu_est_11_i_o4[2] + Inst state_machine_un42_clk_030_3 state_machine.un42_clk_030_3 Inst A_i_26_ A_i[26] - Inst A_c_i_0_ A_c_i[0] + Inst state_machine_un42_clk_030_4 state_machine.un42_clk_030_4 Inst A_i_27_ A_i[27] - Inst state_machine_UDS_000_INT_8_i state_machine.UDS_000_INT_8_i + Inst state_machine_un42_clk_030_5 state_machine.un42_clk_030_5 Inst A_i_28_ A_i[28] - Inst state_machine_LDS_000_INT_8_i state_machine.LDS_000_INT_8_i + Inst state_machine_un42_clk_030 state_machine.un42_clk_030 Inst A_i_29_ A_i[29] + Inst state_machine_un13_clk_000_d_1_0 state_machine.un13_clk_000_d_1_0 Inst A_i_30_ A_i[30] + Inst state_machine_un13_clk_000_d state_machine.un13_clk_000_d Inst A_i_31_ A_i[31] - Inst state_machine_un14_as_000_int_i state_machine.un14_as_000_int_i - Inst SM_AMIGA_ns_i_7_ SM_AMIGA_ns_i[7] + Inst state_machine_un13_clk_000_d_4_1 state_machine.un13_clk_000_d_4_1 + Inst SM_AMIGA_i_7_ SM_AMIGA_i[7] + Inst state_machine_un13_clk_000_d_4 state_machine.un13_clk_000_d_4 + Inst state_machine_un5_clk_030_i_a2 state_machine.un5_clk_030_i_a2 + Inst state_machine_un8_clk_000_d_1 state_machine.un8_clk_000_d_1 + Inst SM_AMIGA_ns_a2_0_ SM_AMIGA_ns_a2[0] + Inst state_machine_un8_clk_000_d_2 state_machine.un8_clk_000_d_2 + Inst SM_AMIGA_ns_a2_0_0_ SM_AMIGA_ns_a2_0[0] + Inst state_machine_un8_clk_000_d_3 state_machine.un8_clk_000_d_3 + Inst SM_AMIGA_ns_a2_0_2_ SM_AMIGA_ns_a2_0[2] + Inst state_machine_un8_clk_000_d_4 state_machine.un8_clk_000_d_4 + Inst SM_AMIGA_ns_i_a2_4_ SM_AMIGA_ns_i_a2[4] + Inst state_machine_un8_clk_000_d state_machine.un8_clk_000_d + Inst SM_AMIGA_ns_i_a2_0_4_ SM_AMIGA_ns_i_a2_0[4] + Inst clk_un3_clk_000_dd_0_a2 clk.un3_clk_000_dd_0_a2 + Inst clk_cpu_est_11_i_a4_0_2_ clk.cpu_est_11_i_a4_0[2] + Inst state_machine_un13_as_000_int_i state_machine.un13_as_000_int_i + Inst un9_i_a2_1_2_ un9_i_a2_1[2] + Inst un9_i_a2_2_2_ un9_i_a2_2[2] Inst CLK_CNT_i_0_ CLK_CNT_i[0] - Inst un1_CLK_000_CNT_i_3_ un1_CLK_000_CNT_i[3] + Inst un9_i_a2_2_ un9_i_a2[2] + Inst A_i_24_ A_i[24] + Inst un9_i_a2_1_1_ un9_i_a2_1[1] + Inst A_i_25_ A_i[25] + Inst un9_i_a2_1_ un9_i_a2[1] + Inst SM_AMIGA_D_0_0__r SM_AMIGA_D_0_0_.r + Inst SM_AMIGA_D_0_0__m SM_AMIGA_D_0_0_.m + Inst SM_AMIGA_D_0_0__n SM_AMIGA_D_0_0_.n + Inst SM_AMIGA_D_0_0__p SM_AMIGA_D_0_0_.p + Inst state_machine_un42_clk_030_1 state_machine.un42_clk_030_1 + Inst state_machine_un42_clk_030_2 state_machine.un42_clk_030_2 + Inst SM_AMIGA_D_0_1__r SM_AMIGA_D_0_1_.r + Inst SM_AMIGA_D_0_1__m SM_AMIGA_D_0_1_.m + Inst SM_AMIGA_D_0_1__n SM_AMIGA_D_0_1_.n + Inst SM_AMIGA_D_0_1__p SM_AMIGA_D_0_1_.p + Inst cpu_est_0_1__r cpu_est_0_1_.r + Inst cpu_est_0_1__m cpu_est_0_1_.m + Inst cpu_est_0_1__n cpu_est_0_1_.n + Inst cpu_est_0_1__p cpu_est_0_1_.p + Inst clk_cpu_est_11_0_1_1_ clk.cpu_est_11_0_1[1] + Inst cpu_est_0_2__r cpu_est_0_2_.r + Inst clk_cpu_est_11_0_2_1_ clk.cpu_est_11_0_2[1] + Inst cpu_est_0_2__m cpu_est_0_2_.m + Inst clk_cpu_est_11_0_1_ clk.cpu_est_11_0[1] + Inst cpu_est_0_2__n cpu_est_0_2_.n + Inst clk_cpu_est_11_0_1_3_ clk.cpu_est_11_0_1[3] + Inst cpu_est_0_2__p cpu_est_0_2_.p + Inst clk_cpu_est_11_0_3_ clk.cpu_est_11_0[3] + Inst cpu_est_0_3__r cpu_est_0_3_.r + Inst clk_cpu_est_11_i_a4_1_2_ clk.cpu_est_11_i_a4_1[2] + Inst cpu_est_0_3__m cpu_est_0_3_.m + Inst clk_cpu_est_11_i_a4_2_ clk.cpu_est_11_i_a4[2] + Inst cpu_est_0_3__n cpu_est_0_3_.n + Inst clk_cpu_est_11_i_a4_0_1_2_ clk.cpu_est_11_i_a4_0_1[2] + Inst cpu_est_0_3__p cpu_est_0_3_.p + Inst SM_AMIGA_ns_i_0_ SM_AMIGA_ns_i[0] + Inst SM_AMIGA_ns_i_1_1_ SM_AMIGA_ns_i_1[1] + Inst SM_AMIGA_ns_i_1_ SM_AMIGA_ns_i[1] + Inst state_machine_AS_030_000_SYNC_3_1 state_machine.AS_030_000_SYNC_3_1 + Inst state_machine_AS_030_000_SYNC_3 state_machine.AS_030_000_SYNC_3 + Inst state_machine_un31_clk_000_d_1 state_machine.un31_clk_000_d_1 + Inst state_machine_un31_clk_000_d state_machine.un31_clk_000_d + Inst clk_cpu_est_11_0_i_1_ clk.cpu_est_11_0_i[1] + Inst clk_cpu_est_11_0_o4_i_3_ clk.cpu_est_11_0_o4_i[3] + Inst clk_cpu_est_11_0_o4_i_1_ clk.cpu_est_11_0_o4_i[1] + Inst clk_cpu_est_11_i_o4_i_2_ clk.cpu_est_11_i_o4_i[2] + Inst SM_AMIGA_ns_i_o2_i_4_ SM_AMIGA_ns_i_o2_i[4] Inst SIZE_c_i_1_ SIZE_c_i[1] - Inst state_machine_un25_clk_000_d_i_0 state_machine.un25_clk_000_d_i_0 - Inst state_machine_un80_clk_000_d_i state_machine.un80_clk_000_d_i - Inst SM_AMIGA_ns_i_o2_i_0_ SM_AMIGA_ns_i_o2_i[0] + Inst state_machine_un31_clk_000_d_i_0 state_machine.un31_clk_000_d_i_0 Inst state_machine_un4_bgack_000_i state_machine.un4_bgack_000_i Inst state_machine_un1_clk_030_i state_machine.un1_clk_030_i Inst state_machine_un17_clk_030_i state_machine.un17_clk_030_i - Inst SM_AMIGA_ns_i_o2_i_2_ SM_AMIGA_ns_i_o2_i[2] - Inst SM_AMIGA_ns_i_o2_i_1_ SM_AMIGA_ns_i_o2_i[1] - Net a_21__n A[21] - Net a_15__n A[15] - Net a_c_22__n A_c[22] - Net a_22__n A[22] - Net a_14__n A[14] - Net a_c_23__n A_c[23] - Net a_23__n A[23] - Net a_13__n A[13] - Net a_c_24__n A_c[24] - Net a_24__n A[24] - Net a_12__n A[12] - Net a_c_25__n A_c[25] - Net a_25__n A[25] - Net a_11__n A[11] - Net a_c_26__n A_c[26] - Net cpu_est_3__n cpu_est[3] - Net a_26__n A[26] - Net a_10__n A[10] - Net a_c_27__n A_c[27] - Net gnd_n_n GND - Net a_27__n A[27] - Net a_9__n A[9] - Net cpu_est_1__n cpu_est[1] - Net a_c_28__n A_c[28] - Net a_28__n A[28] - Net a_8__n A[8] - Net a_c_29__n A_c[29] - Net a_29__n A[29] - Net a_7__n A[7] + Inst state_machine_AS_030_000_SYNC_3_i state_machine.AS_030_000_SYNC_3_i + Inst clk_cpu_est_11_0_i_3_ clk.cpu_est_11_0_i[3] + Inst A_c_i_0_ A_c_i[0] + Inst state_machine_UDS_000_INT_8_i state_machine.UDS_000_INT_8_i + Inst state_machine_LDS_000_INT_8_i state_machine.LDS_000_INT_8_i + Inst SM_AMIGA_ns_i_2_ SM_AMIGA_ns_i[2] + Inst SM_AMIGA_ns_i_5_ SM_AMIGA_ns_i[5] Net a_c_30__n A_c[30] Net a_30__n A[30] - Net a_6__n A[6] Net a_c_31__n A_c[31] - Net a_5__n A[5] - Net vcc_n_n VCC - Net a_4__n A[4] + Net cpu_est_3__n cpu_est[3] + Net gnd_n_n GND Net cpu_est_0__n cpu_est[0] + Net cpu_est_1__n cpu_est[1] + Net cpu_est_d_0__n cpu_est_d[0] + Net cpu_est_d_3__n cpu_est_d[3] + Net ipl_030_c_0__n IPL_030_c[0] + Net ipl_030_0__n IPL_030[0] + Net vcc_n_n VCC + Net ipl_030_c_1__n IPL_030_c[1] + Net cpu_est_d_1__n cpu_est_d[1] + Net ipl_030_1__n IPL_030[1] + Net cpu_est_d_2__n cpu_est_d[2] + Net ipl_030_c_2__n IPL_030_c[2] Net cpu_est_2__n cpu_est[2] - Net a_3__n A[3] Net clk_cnt_0__n CLK_CNT[0] + Net ipl_c_0__n IPL_c[0] Net sm_amiga_6__n SM_AMIGA[6] - Net a_2__n A[2] + Net ipl_0__n IPL[0] Net sm_amiga_7__n SM_AMIGA[7] - Net a_1__n A[1] + Net ipl_c_1__n IPL_c[1] + Net ipl_1__n IPL[1] + Net ipl_c_2__n IPL_c[2] + Net clk_rising_clk_amiga_1_n clk.RISING_CLK_AMIGA_1 + Net dsack_0__n DSACK[0] + Net state_machine_un57_clk_000_d_n state_machine.un57_clk_000_d + Net dsack_c_1__n DSACK_c[1] + Net sm_amiga_1__n SM_AMIGA[1] Net dsack_int_1__n DSACK_INT[1] Net sm_amiga_4__n SM_AMIGA[4] Net sm_amiga_3__n SM_AMIGA[3] + Net state_machine_un13_as_000_int_n state_machine.un13_as_000_int Net sm_amiga_5__n SM_AMIGA[5] - Net un1_clk_000_cnt_3__n un1_CLK_000_CNT[3] - Net clk_000_cnt_0__n CLK_000_CNT[0] - Net clk_000_cnt_1__n CLK_000_CNT[1] - Net clk_000_cnt_2__n CLK_000_CNT[2] - Net clk_000_cnt_3__n CLK_000_CNT[3] - Net ipl_030_c_0__n IPL_030_c[0] - Net state_machine_un14_as_000_int_n state_machine.un14_as_000_int - Net ipl_030_0__n IPL_030[0] Net sm_amiga_2__n SM_AMIGA[2] - Net ipl_030_c_1__n IPL_030_c[1] - Net sm_amiga_1__n SM_AMIGA[1] - Net ipl_030_1__n IPL_030[1] Net sm_amiga_0__n SM_AMIGA[0] - Net ipl_030_c_2__n IPL_030_c[2] Net sm_amiga_d_0__n SM_AMIGA_D[0] Net sm_amiga_d_1__n SM_AMIGA_D[1] - Net ipl_c_0__n IPL_c[0] Net sm_amiga_d_2__n SM_AMIGA_D[2] - Net ipl_0__n IPL[0] - Net ipl_c_1__n IPL_c[1] - Net clk_clk_000_cnt_3_1__n clk.CLK_000_CNT_3[1] - Net ipl_1__n IPL[1] - Net clk_clk_000_cnt_3_2__n clk.CLK_000_CNT_3[2] - Net ipl_c_2__n IPL_c[2] - Net clk_clk_000_cnt_3_3__n clk.CLK_000_CNT_3[3] - Net dsack_0__n DSACK[0] - Net dsack_c_1__n DSACK_c[1] Net fc_c_0__n FC_c[0] Net fc_0__n FC[0] Net fc_c_1__n FC_c[1] - Net sm_amiga_ns_4__n SM_AMIGA_ns[4] - Net sm_amiga_ns_5__n SM_AMIGA_ns[5] - Net sm_amiga_ns_7__n SM_AMIGA_ns[7] - Net clk_rising_clk_amiga_1_n clk.RISING_CLK_AMIGA_1 - Net un1_clk_000_cnt_0__n un1_CLK_000_CNT[0] - Net clk_cpu_est_11_0_1__n clk.cpu_est_11_0[1] - Net un1_clk_000_cnt_1__n un1_CLK_000_CNT[1] - Net un1_clk_000_cnt_2__n un1_CLK_000_CNT[2] - Net state_machine_un69_clk_000_d_n state_machine.un69_clk_000_d - Net state_machine_un78_clk_000_d_n state_machine.un78_clk_000_d - Net clk_cpu_est_11_0_3__n clk.cpu_est_11_0[3] - Net state_machine_un67_clk_000_d_n state_machine.un67_clk_000_d - Net state_machine_un80_clk_000_d_n state_machine.un80_clk_000_d - Net sm_amiga_ns_0_5__n SM_AMIGA_ns_0[5] - Net state_machine_un25_clk_000_d_n state_machine.un25_clk_000_d - Net sm_amiga_ns_0_4__n SM_AMIGA_ns_0[4] - Net state_machine_lds_000_int_8_n state_machine.LDS_000_INT_8 - Net state_machine_uds_000_int_8_n state_machine.UDS_000_INT_8 - Net state_machine_un42_clk_030_n state_machine.un42_clk_030 - Net state_machine_un4_bgack_000_0_n state_machine.un4_bgack_000_0 - Net state_machine_as_030_000_sync_3_n state_machine.AS_030_000_SYNC_3 - Net state_machine_un1_clk_030_0_n state_machine.un1_clk_030_0 - Net state_machine_un17_clk_030_0_n state_machine.un17_clk_030_0 - Net state_machine_un17_clk_030_n state_machine.un17_clk_030 - Net state_machine_un1_clk_030_n state_machine.un1_clk_030 - Net state_machine_un4_bgack_000_n state_machine.un4_bgack_000 - Net state_machine_as_030_000_sync_3_2_n state_machine.AS_030_000_SYNC_3_2 + Net state_machine_un57_clk_000_d_0_n state_machine.un57_clk_000_d_0 Net a_c_i_0__n A_c_i[0] Net state_machine_uds_000_int_8_0_n state_machine.UDS_000_INT_8_0 Net state_machine_lds_000_int_8_0_n state_machine.LDS_000_INT_8_0 - Net state_machine_un15_clk_000_d_n state_machine.un15_clk_000_d + Net sm_amiga_ns_0_2__n SM_AMIGA_ns_0[2] + Net sm_amiga_ns_0_5__n SM_AMIGA_ns_0[5] + Net sm_amiga_ns_0__n SM_AMIGA_ns[0] + Net sm_amiga_ns_2__n SM_AMIGA_ns[2] + Net sm_amiga_ns_5__n SM_AMIGA_ns[5] Net sm_amiga_ns_0_7__n SM_AMIGA_ns_0[7] + Net sm_amiga_ns_7__n SM_AMIGA_ns[7] Net size_c_i_1__n SIZE_c_i[1] - Net state_machine_un25_clk_000_d_i_n state_machine.un25_clk_000_d_i - Net state_machine_un80_clk_000_d_i_n state_machine.un80_clk_000_d_i - Net state_machine_un67_clk_000_d_i_n state_machine.un67_clk_000_d_i - Net state_machine_un78_clk_000_d_0_n state_machine.un78_clk_000_d_0 - Net clk_rising_clk_amiga_1_i_n clk.RISING_CLK_AMIGA_1_i Net clk_un3_clk_000_dd_n clk.un3_clk_000_dd - Net clk_000_cnt_i_1__n CLK_000_CNT_i[1] - Net clk_000_cnt_i_0__n CLK_000_CNT_i[0] - Net clk_cpu_est_11_3__n clk.cpu_est_11[3] - Net clk_000_cnt_i_3__n CLK_000_CNT_i[3] - Net clk_000_cnt_i_2__n CLK_000_CNT_i[2] - Net state_machine_un69_clk_000_d_0_n state_machine.un69_clk_000_d_0 - Net state_machine_un69_clk_000_d_0_1_n state_machine.un69_clk_000_d_0_1 + Net state_machine_un31_clk_000_d_i_n state_machine.un31_clk_000_d_i Net clk_cpu_est_11_1__n clk.cpu_est_11[1] - Net state_machine_un69_clk_000_d_0_2_n state_machine.un69_clk_000_d_0_2 - Net state_machine_un25_clk_000_d_i_1_n state_machine.un25_clk_000_d_i_1 + Net clk_cpu_est_11_3__n clk.cpu_est_11[3] + Net state_machine_un4_bgack_000_0_n state_machine.un4_bgack_000_0 + Net state_machine_un1_clk_030_0_n state_machine.un1_clk_030_0 + Net state_machine_un17_clk_030_0_n state_machine.un17_clk_030_0 + Net state_machine_as_030_000_sync_3_2_n state_machine.AS_030_000_SYNC_3_2 + Net clk_cpu_est_11_0_3__n clk.cpu_est_11_0[3] + Net clk_cpu_est_11_0_1__n clk.cpu_est_11_0[1] + Net state_machine_un13_clk_000_d_1_n state_machine.un13_clk_000_d_1 + Net state_machine_un42_clk_030_n state_machine.un42_clk_030 + Net sm_amiga_ns_0_0__n SM_AMIGA_ns_0[0] + Net state_machine_as_030_000_sync_3_n state_machine.AS_030_000_SYNC_3 + Net state_machine_un17_clk_030_n state_machine.un17_clk_030 + Net state_machine_un1_clk_030_n state_machine.un1_clk_030 Net state_machine_as_030_000_sync_3_2_1_n state_machine.AS_030_000_SYNC_3_2_1 - Net clk_cpu_est_11_0_1_3__n clk.cpu_est_11_0_1[3] + Net state_machine_un4_bgack_000_n state_machine.un4_bgack_000 + Net state_machine_un31_clk_000_d_i_1_n state_machine.un31_clk_000_d_i_1 + Net state_machine_un31_clk_000_d_n state_machine.un31_clk_000_d + Net state_machine_un13_clk_000_d_n state_machine.un13_clk_000_d + Net state_machine_un13_clk_000_d_4_n state_machine.un13_clk_000_d_4 + Net state_machine_un8_clk_000_d_n state_machine.un8_clk_000_d Net clk_cpu_est_11_0_1_1__n clk.cpu_est_11_0_1[1] Net clk_cpu_est_11_0_2_1__n clk.cpu_est_11_0_2[1] - Net cpu_est_i_0__n cpu_est_i[0] - Net cpu_est_i_2__n cpu_est_i[2] - Net cpu_est_i_3__n cpu_est_i[3] - Net cpu_est_i_1__n cpu_est_i[1] + Net clk_cpu_est_11_0_1_3__n clk.cpu_est_11_0_1[3] + Net state_machine_lds_000_int_8_n state_machine.LDS_000_INT_8 + Net state_machine_uds_000_int_8_n state_machine.UDS_000_INT_8 Net state_machine_un42_clk_030_1_n state_machine.un42_clk_030_1 - Net sm_amiga_i_4__n SM_AMIGA_i[4] Net state_machine_un42_clk_030_2_n state_machine.un42_clk_030_2 - Net sm_amiga_i_6__n SM_AMIGA_i[6] Net state_machine_un42_clk_030_3_n state_machine.un42_clk_030_3 - Net sm_amiga_i_5__n SM_AMIGA_i[5] Net state_machine_un42_clk_030_4_n state_machine.un42_clk_030_4 Net state_machine_un42_clk_030_5_n state_machine.un42_clk_030_5 - Net state_machine_un15_clk_000_d_i_n state_machine.un15_clk_000_d_i - Net sm_amiga_i_0__n SM_AMIGA_i[0] - Net sm_amiga_i_7__n SM_AMIGA_i[7] + Net state_machine_un13_clk_000_d_1_0_n state_machine.un13_clk_000_d_1_0 + Net state_machine_un13_clk_000_d_4_1_n state_machine.un13_clk_000_d_4_1 + Net state_machine_un8_clk_000_d_1_n state_machine.un8_clk_000_d_1 + Net state_machine_un8_clk_000_d_2_n state_machine.un8_clk_000_d_2 + Net state_machine_un8_clk_000_d_3_n state_machine.un8_clk_000_d_3 + Net cpu_est_d_i_3__n cpu_est_d_i[3] + Net state_machine_un8_clk_000_d_4_n state_machine.un8_clk_000_d_4 + Net cpu_est_d_i_0__n cpu_est_d_i[0] Net dsack_i_1__n DSACK_i[1] - Net a_i_18__n A_i[18] - Net a_i_16__n A_i[16] - Net a_i_19__n A_i[19] - Net state_machine_un42_clk_030_i_n state_machine.un42_clk_030_i - Net cpu_est_0_1__un3_n cpu_est_0_1_.un3 - Net cpu_est_0_1__un1_n cpu_est_0_1_.un1 - Net sm_amiga_i_2__n SM_AMIGA_i[2] - Net cpu_est_0_1__un0_n cpu_est_0_1_.un0 + Net state_machine_un13_clk_000_d_i_n state_machine.un13_clk_000_d_i + Net state_machine_un8_clk_000_d_i_n state_machine.un8_clk_000_d_i + Net state_machine_un13_clk_000_d_1_i_n state_machine.un13_clk_000_d_1_i Net sm_amiga_i_1__n SM_AMIGA_i[1] - Net vma_int_0_un3_n VMA_INT_0.un3 + Net sm_amiga_i_2__n SM_AMIGA_i[2] + Net sm_amiga_d_0_2__un3_n SM_AMIGA_D_0_2_.un3 + Net sm_amiga_i_0__n SM_AMIGA_i[0] + Net sm_amiga_d_0_2__un1_n SM_AMIGA_D_0_2_.un1 Net sm_amiga_i_3__n SM_AMIGA_i[3] - Net vma_int_0_un1_n VMA_INT_0.un1 - Net vma_int_0_un0_n VMA_INT_0.un0 - Net a_i_30__n A_i[30] - Net cpu_est_0_3__un3_n cpu_est_0_3_.un3 - Net a_i_31__n A_i[31] - Net cpu_est_0_3__un1_n cpu_est_0_3_.un1 - Net a_i_28__n A_i[28] - Net cpu_est_0_3__un0_n cpu_est_0_3_.un0 - Net a_i_29__n A_i[29] - Net cpu_est_0_2__un3_n cpu_est_0_2_.un3 - Net a_i_26__n A_i[26] - Net cpu_est_0_2__un1_n cpu_est_0_2_.un1 - Net a_i_27__n A_i[27] - Net cpu_est_0_2__un0_n cpu_est_0_2_.un0 - Net a_i_24__n A_i[24] - Net dtack_sync_0_un3_n DTACK_SYNC_0.un3 - Net a_i_25__n A_i[25] - Net dtack_sync_0_un1_n DTACK_SYNC_0.un1 - Net clk_cnt_i_0__n CLK_CNT_i[0] - Net dtack_sync_0_un0_n DTACK_SYNC_0.un0 - Net state_machine_un14_as_000_int_i_n state_machine.un14_as_000_int_i - Net sm_amiga_d_0_0__un3_n SM_AMIGA_D_0_0_.un3 - Net sm_amiga_d_0_0__un1_n SM_AMIGA_D_0_0_.un1 - Net un1_clk_000_cnt_i_3__n un1_CLK_000_CNT_i[3] - Net sm_amiga_d_0_0__un0_n SM_AMIGA_D_0_0_.un0 - Net bgack_030_int_0_un3_n BGACK_030_INT_0.un3 - Net bgack_030_int_0_un1_n BGACK_030_INT_0.un1 - Net bgack_030_int_0_un0_n BGACK_030_INT_0.un0 - Net bg_000_0_un3_n BG_000_0.un3 - Net bg_000_0_un1_n BG_000_0.un1 - Net bg_000_0_un0_n BG_000_0.un0 - Net as_030_000_sync_0_un3_n AS_030_000_SYNC_0.un3 - Net as_030_000_sync_0_un1_n AS_030_000_SYNC_0.un1 - Net as_030_000_sync_0_un0_n AS_030_000_SYNC_0.un0 - Net fpu_cs_int_0_un3_n FPU_CS_INT_0.un3 - Net size_c_0__n SIZE_c[0] - Net fpu_cs_int_0_un1_n FPU_CS_INT_0.un1 - Net size_0__n SIZE[0] - Net fpu_cs_int_0_un0_n FPU_CS_INT_0.un0 - Net size_c_1__n SIZE_c[1] + Net sm_amiga_d_0_2__un0_n SM_AMIGA_D_0_2_.un0 Net dsack_int_0_1__un3_n DSACK_INT_0_1_.un3 Net dsack_int_0_1__un1_n DSACK_INT_0_1_.un1 - Net a_c_0__n A_c[0] Net dsack_int_0_1__un0_n DSACK_INT_0_1_.un0 - Net a_0__n A[0] + Net cpu_est_i_3__n cpu_est_i[3] + Net vma_int_0_un3_n VMA_INT_0.un3 + Net a_i_18__n A_i[18] + Net vma_int_0_un1_n VMA_INT_0.un1 + Net a_i_16__n A_i[16] + Net vma_int_0_un0_n VMA_INT_0.un0 + Net a_i_19__n A_i[19] Net vpa_sync_0_un3_n VPA_SYNC_0.un3 Net vpa_sync_0_un1_n VPA_SYNC_0.un1 + Net state_machine_un42_clk_030_i_n state_machine.un42_clk_030_i Net vpa_sync_0_un0_n VPA_SYNC_0.un0 Net as_000_int_0_un3_n AS_000_INT_0.un3 + Net cpu_est_i_1__n cpu_est_i[1] Net as_000_int_0_un1_n AS_000_INT_0.un1 Net as_000_int_0_un0_n AS_000_INT_0.un0 + Net cpu_est_i_0__n cpu_est_i[0] + Net dtack_sync_0_un3_n DTACK_SYNC_0.un3 + Net sm_amiga_i_4__n SM_AMIGA_i[4] + Net dtack_sync_0_un1_n DTACK_SYNC_0.un1 + Net sm_amiga_i_6__n SM_AMIGA_i[6] + Net dtack_sync_0_un0_n DTACK_SYNC_0.un0 + Net cpu_est_i_2__n cpu_est_i[2] + Net lds_000_int_0_un3_n LDS_000_INT_0.un3 + Net lds_000_int_0_un1_n LDS_000_INT_0.un1 + Net lds_000_int_0_un0_n LDS_000_INT_0.un0 + Net sm_amiga_i_5__n SM_AMIGA_i[5] + Net uds_000_int_0_un3_n UDS_000_INT_0.un3 + Net uds_000_int_0_un1_n UDS_000_INT_0.un1 + Net sm_amiga_i_7__n SM_AMIGA_i[7] + Net uds_000_int_0_un0_n UDS_000_INT_0.un0 + Net a_i_30__n A_i[30] + Net bg_000_0_un3_n BG_000_0.un3 + Net a_i_31__n A_i[31] + Net bg_000_0_un1_n BG_000_0.un1 + Net a_i_28__n A_i[28] + Net bg_000_0_un0_n BG_000_0.un0 + Net a_i_29__n A_i[29] + Net as_030_000_sync_0_un3_n AS_030_000_SYNC_0.un3 + Net a_i_26__n A_i[26] + Net as_030_000_sync_0_un1_n AS_030_000_SYNC_0.un1 + Net a_i_27__n A_i[27] + Net as_030_000_sync_0_un0_n AS_030_000_SYNC_0.un0 + Net a_i_24__n A_i[24] + Net fpu_cs_int_0_un3_n FPU_CS_INT_0.un3 + Net a_i_25__n A_i[25] + Net fpu_cs_int_0_un1_n FPU_CS_INT_0.un1 + Net clk_cnt_i_0__n CLK_CNT_i[0] + Net fpu_cs_int_0_un0_n FPU_CS_INT_0.un0 + Net state_machine_un13_as_000_int_i_n state_machine.un13_as_000_int_i Net ipl_030_0_2__un3_n IPL_030_0_2_.un3 Net ipl_030_0_2__un1_n IPL_030_0_2_.un1 Net ipl_030_0_2__un0_n IPL_030_0_2_.un0 @@ -567,29 +502,72 @@ Design 'BUS68030' created Thu May 15 19:20:52 2014 Net ipl_030_0_0__un3_n IPL_030_0_0_.un3 Net ipl_030_0_0__un1_n IPL_030_0_0_.un1 Net ipl_030_0_0__un0_n IPL_030_0_0_.un0 - Net sm_amiga_d_0_2__un3_n SM_AMIGA_D_0_2_.un3 - Net a_c_16__n A_c[16] - Net sm_amiga_d_0_2__un1_n SM_AMIGA_D_0_2_.un1 - Net a_16__n A[16] - Net sm_amiga_d_0_2__un0_n SM_AMIGA_D_0_2_.un0 - Net a_c_17__n A_c[17] + Net bgack_030_int_0_un3_n BGACK_030_INT_0.un3 + Net bgack_030_int_0_un1_n BGACK_030_INT_0.un1 + Net bgack_030_int_0_un0_n BGACK_030_INT_0.un0 + Net sm_amiga_d_0_0__un3_n SM_AMIGA_D_0_0_.un3 + Net sm_amiga_d_0_0__un1_n SM_AMIGA_D_0_0_.un1 + Net size_c_0__n SIZE_c[0] + Net sm_amiga_d_0_0__un0_n SM_AMIGA_D_0_0_.un0 + Net size_0__n SIZE[0] Net sm_amiga_d_0_1__un3_n SM_AMIGA_D_0_1_.un3 - Net a_17__n A[17] + Net size_c_1__n SIZE_c[1] Net sm_amiga_d_0_1__un1_n SM_AMIGA_D_0_1_.un1 - Net a_c_18__n A_c[18] Net sm_amiga_d_0_1__un0_n SM_AMIGA_D_0_1_.un0 + Net a_c_0__n A_c[0] + Net cpu_est_0_1__un3_n cpu_est_0_1_.un3 + Net a_0__n A[0] + Net cpu_est_0_1__un1_n cpu_est_0_1_.un1 + Net cpu_est_0_1__un0_n cpu_est_0_1_.un0 + Net cpu_est_0_2__un3_n cpu_est_0_2_.un3 + Net cpu_est_0_2__un1_n cpu_est_0_2_.un1 + Net cpu_est_0_2__un0_n cpu_est_0_2_.un0 + Net cpu_est_0_3__un3_n cpu_est_0_3_.un3 + Net cpu_est_0_3__un1_n cpu_est_0_3_.un1 + Net cpu_est_0_3__un0_n cpu_est_0_3_.un0 + Net a_15__n A[15] + Net a_14__n A[14] + Net a_13__n A[13] + Net a_12__n A[12] + Net a_c_16__n A_c[16] + Net a_11__n A[11] + Net a_16__n A[16] + Net a_c_17__n A_c[17] + Net a_10__n A[10] + Net a_17__n A[17] + Net a_c_18__n A_c[18] + Net a_9__n A[9] Net a_18__n A[18] - Net lds_000_int_0_un3_n LDS_000_INT_0.un3 Net a_c_19__n A_c[19] - Net lds_000_int_0_un1_n LDS_000_INT_0.un1 + Net a_8__n A[8] Net a_19__n A[19] - Net lds_000_int_0_un0_n LDS_000_INT_0.un0 Net a_c_20__n A_c[20] - Net uds_000_int_0_un3_n UDS_000_INT_0.un3 + Net a_7__n A[7] Net a_20__n A[20] - Net uds_000_int_0_un1_n UDS_000_INT_0.un1 Net a_c_21__n A_c[21] - Net uds_000_int_0_un0_n UDS_000_INT_0.un0 + Net a_6__n A[6] + Net a_21__n A[21] + Net a_c_22__n A_c[22] + Net a_5__n A[5] + Net a_22__n A[22] + Net a_c_23__n A_c[23] + Net a_4__n A[4] + Net a_23__n A[23] + Net a_c_24__n A_c[24] + Net a_3__n A[3] + Net a_24__n A[24] + Net a_c_25__n A_c[25] + Net a_2__n A[2] + Net a_25__n A[25] + Net a_c_26__n A_c[26] + Net a_1__n A[1] + Net a_26__n A[26] + Net a_c_27__n A_c[27] + Net a_27__n A[27] + Net a_c_28__n A_c[28] + Net a_28__n A[28] + Net a_c_29__n A_c[29] + Net a_29__n A[29] End Section Type Name // ---------------------------------------------------------------------- diff --git a/Logic/bus68030.srf b/Logic/bus68030.srf index 15c1c83..b6c1b9f 100644 --- a/Logic/bus68030.srf +++ b/Logic/bus68030.srf @@ -6,32 +6,32 @@ #Implementation: logic $ Start of Compile -#Thu May 15 19:20:46 2014 +#Thu May 15 22:17:20 2014 Synopsys VHDL Compiler, version comp201209rcp1, Build 283R, built Mar 19 2013 @N|Running in 64-bit mode Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc. @N: CD720 :"C:\Program Files (x86)\ispLever\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns -@N:"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":6:7:6:14|Top entity is set to BUS68030. -File C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd changed - recompiling +@N:"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":6:7:6:14|Top entity is set to BUS68030. +File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling VHDL syntax check successful! -File C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd changed - recompiling -@N: CD630 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":6:7:6:14|Synthesizing work.bus68030.behavioral -@W: CD638 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":109:7:109:15|Signal clk_030_d is undriven +File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling +@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":6:7:6:14|Synthesizing work.bus68030.behavioral +@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:7:109:15|Signal clk_030_d is undriven Post processing for work.bus68030.behavioral -@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":105:52:105:55|Pruning register VMA_INT_D -@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":91:32:91:34|Pruning register CLK_REF(1 downto 0) -@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":220:2:220:3|Pruning register AS_000_START -@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":113:38:113:40|Pruning register cpu_est_d(3 downto 0) -@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":112:37:112:39|Pruning register FALLING_CLK_AMIGA -@A: CL282 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":100:29:100:31|Feedback mux created for signal SM_AMIGA_D[2:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. -@W: CL190 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":100:29:100:31|Optimizing register bit DSACK_INT(0) to a constant 1 -@W: CL260 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":100:29:100:31|Pruning register bit 0 of DSACK_INT(1 downto 0) -@W: CL189 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":124:2:124:3|Register bit CLK_CNT(1) is always 0, optimizing ... -@W: CL260 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":124:2:124:3|Pruning register bit 1 of CLK_CNT(1 downto 0) -@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":113:38:113:40|Trying to extract state machine for register cpu_est -@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":220:2:220:3|Trying to extract state machine for register SM_AMIGA +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":105:52:105:55|Pruning register VMA_INT_D +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":91:32:91:34|Pruning register CLK_REF(1 downto 0) +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":220:2:220:3|Pruning register AS_000_START +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":113:38:113:40|Pruning register CLK_000_CNT(3 downto 0) +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":112:37:112:39|Pruning register FALLING_CLK_AMIGA +@A: CL282 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":100:29:100:31|Feedback mux created for signal SM_AMIGA_D[2:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. +@W: CL190 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":100:29:100:31|Optimizing register bit DSACK_INT(0) to a constant 1 +@W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":100:29:100:31|Pruning register bit 0 of DSACK_INT(1 downto 0) +@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:2:124:3|Register bit CLK_CNT(1) is always 0, optimizing ... +@W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:2:124:3|Pruning register bit 1 of CLK_CNT(1 downto 0) +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":113:38:113:40|Trying to extract state machine for register cpu_est +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":220:2:220:3|Trying to extract state machine for register SM_AMIGA Extracted state machine for register SM_AMIGA State machine has 8 reachable states with original encodings of: 000 @@ -42,10 +42,10 @@ State machine has 8 reachable states with original encodings of: 101 110 111 -@W: CL249 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":220:2:220:3|Initial value is not supported on state machine SM_AMIGA +@W: CL249 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":220:2:220:3|Initial value is not supported on state machine SM_AMIGA @END Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Thu May 15 19:20:46 2014 +# Thu May 15 22:17:20 2014 ###########################################################] Map & Optimize Report @@ -64,22 +64,22 @@ original code -> new code 101 -> 00100000 110 -> 01000000 111 -> 10000000 -@N: MO106 :"c:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":160:4:160:7|Found ROM, 'clk\.cpu_est_11[3:0]', 16 words by 4 bits +@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":160:4:160:7|Found ROM, 'clk\.cpu_est_11[3:0]', 16 words by 4 bits --------------------------------------- Resource Usage Report Simple gate primitives: DFFRH 7 uses -DFF 19 uses DFFSH 16 uses +DFF 19 uses IBUF 35 uses BUFTH 7 uses OBUF 15 uses BI_DIR 2 uses -AND2 179 uses -INV 143 uses +AND2 163 uses +INV 126 uses OR2 20 uses -XOR2 8 uses +XOR2 5 uses @N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis. @@ -89,6 +89,6 @@ Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 95MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Thu May 15 19:20:48 2014 +# Thu May 15 22:17:22 2014 ###########################################################] diff --git a/Logic/dm/BUS68030_compiler.xdm b/Logic/dm/BUS68030_compiler.xdm index d6c5518..59ec725 100644 --- a/Logic/dm/BUS68030_compiler.xdm +++ b/Logic/dm/BUS68030_compiler.xdm @@ -13,7 +13,7 @@ SS1SS1SS1S -SF<1kCsOR"b=Bk:\##Cs\0lNxNC\lNHo\sEN8sINCOEN n#\Ujjd-\0 DHFoOU\nj-djnjUjjk-L#E3P8N"R=""(R"D=PDE8"DROH=#0""-4RHbD#"0=-/4">< +SF<1kCsOR"b=Bk:\##Cs\0lNx8C\FlOkC#M0\0oHE\kLndUjj\0 DHFoOU\nj-djnjUjjk-L#E3P8N"R=""(R"D=PDE8"DROH=#0""-4RHbD#"0=-/4">< S/k1Fs#OC>S <-!-R8vFkRDCs0FFR>-- diff --git a/Logic/run_options.txt b/Logic/run_options.txt index 40699a8..87edc67 100644 --- a/Logic/run_options.txt +++ b/Logic/run_options.txt @@ -1,7 +1,7 @@ #-- Synopsys, Inc. #-- Version G-2012.09LC-SP1 -#-- Project file C:\users\matze\amiga\hardwarehacks\68030-tk\logic\run_options.txt -#-- Written on Thu May 15 19:20:46 2014 +#-- Project file C:\users\matze\documents\github\68030tk\logic\run_options.txt +#-- Written on Thu May 15 22:17:20 2014 #project files @@ -48,5 +48,5 @@ set_option -write_apr_constraint 1 project -result_file "./BUS68030.edi" #set log file -set_option log_file "C:/users/matze/amiga/hardwarehacks/68030-tk/logic/bus68030.srf" +set_option log_file "C:/users/matze/documents/github/68030tk/logic/bus68030.srf" impl -active "logic" diff --git a/Logic/scratchproject.prs b/Logic/scratchproject.prs index f9422ea..dc44126 100644 --- a/Logic/scratchproject.prs +++ b/Logic/scratchproject.prs @@ -1,13 +1,13 @@ #-- Synopsys, Inc. #-- Version G-2012.09LC-SP1 -#-- Project file C:\users\matze\amiga\hardwarehacks\68030-tk\logic\scratchproject.prs +#-- Project file C:\users\matze\documents\github\68030tk\logic\scratchproject.prs #project files -add_file -vhdl -lib work "C:/users/matze/amiga/hardwarehacks/68030-tk/logic/68030-68000-bus.vhd" +add_file -vhdl -lib work "C:/users/matze/documents/github/68030tk/logic/68030-68000-bus.vhd" #implementation: "logic" -impl -add C:\users\matze\amiga\hardwarehacks\68030-tk\logic -type fpga +impl -add C:\users\matze\documents\github\68030tk\logic -type fpga #device options set_option -technology mach @@ -43,8 +43,8 @@ set_option -resource_sharing 1 set_option -write_apr_constraint 1 #set result format/file last -project -result_file "C:/users/matze/amiga/hardwarehacks/68030-tk/logic/BUS68030.edi" +project -result_file "C:/users/matze/documents/github/68030tk/logic/BUS68030.edi" #set log file -set_option log_file "C:/users/matze/amiga/hardwarehacks/68030-tk/logic/bus68030.srf" +set_option log_file "C:/users/matze/documents/github/68030tk/logic/bus68030.srf" impl -active "logic" diff --git a/Logic/synlog/bus68030_fpga_mapper.srr b/Logic/synlog/bus68030_fpga_mapper.srr index a9a4eec..2d14f58 100644 --- a/Logic/synlog/bus68030_fpga_mapper.srr +++ b/Logic/synlog/bus68030_fpga_mapper.srr @@ -12,22 +12,22 @@ original code -> new code 101 -> 00100000 110 -> 01000000 111 -> 10000000 -@N: MO106 :"c:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":160:4:160:7|Found ROM, 'clk\.cpu_est_11[3:0]', 16 words by 4 bits +@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":160:4:160:7|Found ROM, 'clk\.cpu_est_11[3:0]', 16 words by 4 bits --------------------------------------- Resource Usage Report Simple gate primitives: DFFRH 7 uses -DFF 19 uses DFFSH 16 uses +DFF 19 uses IBUF 35 uses BUFTH 7 uses OBUF 15 uses BI_DIR 2 uses -AND2 179 uses -INV 143 uses +AND2 163 uses +INV 126 uses OR2 20 uses -XOR2 8 uses +XOR2 5 uses @N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis. @@ -37,6 +37,6 @@ Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 95MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Thu May 15 19:20:48 2014 +# Thu May 15 22:17:22 2014 ###########################################################] diff --git a/Logic/synlog/report/BUS68030_compiler_errors.txt b/Logic/synlog/report/BUS68030_compiler_errors.txt index 3ac15e8..226dbd1 100644 --- a/Logic/synlog/report/BUS68030_compiler_errors.txt +++ b/Logic/synlog/report/BUS68030_compiler_errors.txt @@ -1,3 +1,3 @@ -@E: CS187 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":300:12:300:12|Expecting <= +@E: CD255 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":317:36:317:36|No identifier "clk_00_dd" in scope @E|Parse errors encountered - exiting diff --git a/Logic/synlog/report/BUS68030_compiler_notes.txt b/Logic/synlog/report/BUS68030_compiler_notes.txt index a06d05c..85f68a0 100644 --- a/Logic/synlog/report/BUS68030_compiler_notes.txt +++ b/Logic/synlog/report/BUS68030_compiler_notes.txt @@ -1,7 +1,7 @@ @N|Running in 64-bit mode @N: CD720 :"C:\Program Files (x86)\ispLever\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns -@N:"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":6:7:6:14|Top entity is set to BUS68030. -@N: CD630 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":6:7:6:14|Synthesizing work.bus68030.behavioral -@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":113:38:113:40|Trying to extract state machine for register cpu_est -@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":220:2:220:3|Trying to extract state machine for register SM_AMIGA +@N:"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":6:7:6:14|Top entity is set to BUS68030. +@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":6:7:6:14|Synthesizing work.bus68030.behavioral +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":113:38:113:40|Trying to extract state machine for register cpu_est +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":220:2:220:3|Trying to extract state machine for register SM_AMIGA diff --git a/Logic/synlog/report/BUS68030_compiler_runstatus.xml b/Logic/synlog/report/BUS68030_compiler_runstatus.xml index d592b3c..4db8131 100644 --- a/Logic/synlog/report/BUS68030_compiler_runstatus.xml +++ b/Logic/synlog/report/BUS68030_compiler_runstatus.xml @@ -6,7 +6,7 @@ The file contains the job information from compiler to be displayed as part of t - C:\users\matze\amiga\hardwarehacks\68030-tk\logic\BUS68030.srr + C:\users\matze\documents\github\68030tk\logic\BUS68030.srr $ Start of Compile @@ -15,27 +15,27 @@ The file contains the job information from compiler to be displayed as part of t 6 - C:\users\matze\amiga\hardwarehacks\68030-tk\logic\synlog\report\BUS68030_compiler_notes.txt + C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_notes.txt 11 - C:\users\matze\amiga\hardwarehacks\68030-tk\logic\synlog\report\BUS68030_compiler_warnings.txt + C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_warnings.txt 0 - C:\users\matze\amiga\hardwarehacks\68030-tk\logic\synlog\report\BUS68030_compiler_errors.txt + C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_errors.txt - - 0h:00m:00s + 0h:00m:01s - - 1400174446 + 1400185040 \ No newline at end of file diff --git a/Logic/synlog/report/BUS68030_compiler_warnings.txt b/Logic/synlog/report/BUS68030_compiler_warnings.txt index 038af60..787dc1a 100644 --- a/Logic/synlog/report/BUS68030_compiler_warnings.txt +++ b/Logic/synlog/report/BUS68030_compiler_warnings.txt @@ -1,12 +1,12 @@ -@W: CD638 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":109:7:109:15|Signal clk_030_d is undriven -@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":105:52:105:55|Pruning register VMA_INT_D -@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":91:32:91:34|Pruning register CLK_REF(1 downto 0) -@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":220:2:220:3|Pruning register AS_000_START -@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":113:38:113:40|Pruning register cpu_est_d(3 downto 0) -@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":112:37:112:39|Pruning register FALLING_CLK_AMIGA -@W: CL190 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":100:29:100:31|Optimizing register bit DSACK_INT(0) to a constant 1 -@W: CL260 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":100:29:100:31|Pruning register bit 0 of DSACK_INT(1 downto 0) -@W: CL189 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":124:2:124:3|Register bit CLK_CNT(1) is always 0, optimizing ... -@W: CL260 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":124:2:124:3|Pruning register bit 1 of CLK_CNT(1 downto 0) -@W: CL249 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":220:2:220:3|Initial value is not supported on state machine SM_AMIGA +@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:7:109:15|Signal clk_030_d is undriven +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":105:52:105:55|Pruning register VMA_INT_D +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":91:32:91:34|Pruning register CLK_REF(1 downto 0) +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":220:2:220:3|Pruning register AS_000_START +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":113:38:113:40|Pruning register CLK_000_CNT(3 downto 0) +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":112:37:112:39|Pruning register FALLING_CLK_AMIGA +@W: CL190 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":100:29:100:31|Optimizing register bit DSACK_INT(0) to a constant 1 +@W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":100:29:100:31|Pruning register bit 0 of DSACK_INT(1 downto 0) +@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:2:124:3|Register bit CLK_CNT(1) is always 0, optimizing ... +@W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:2:124:3|Pruning register bit 1 of CLK_CNT(1 downto 0) +@W: CL249 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":220:2:220:3|Initial value is not supported on state machine SM_AMIGA diff --git a/Logic/synlog/report/BUS68030_fpga_mapper_notes.txt b/Logic/synlog/report/BUS68030_fpga_mapper_notes.txt index 0f22d7b..f838e66 100644 --- a/Logic/synlog/report/BUS68030_fpga_mapper_notes.txt +++ b/Logic/synlog/report/BUS68030_fpga_mapper_notes.txt @@ -1,3 +1,3 @@ @N: MF248 |Running in 64-bit mode. -@N: MO106 :"c:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":160:4:160:7|Found ROM, 'clk\.cpu_est_11[3:0]', 16 words by 4 bits +@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":160:4:160:7|Found ROM, 'clk\.cpu_est_11[3:0]', 16 words by 4 bits @N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis. diff --git a/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml b/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml index 4f93391..6c183fe 100644 --- a/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml +++ b/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml @@ -5,7 +5,7 @@ The file contains the job information from mapper to be displayed as part of the *******************************************************************************************--> -C:\users\matze\amiga\hardwarehacks\68030-tk\logic\synlog\BUS68030_fpga_mapper.srr +C:\users\matze\documents\github\68030tk\logic\synlog\BUS68030_fpga_mapper.srr Completed @@ -14,19 +14,19 @@ The file contains the job information from mapper to be displayed as part of the 3 -C:\users\matze\amiga\hardwarehacks\68030-tk\logic\synlog\report\BUS68030_fpga_mapper_notes.txt +C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_fpga_mapper_notes.txt 0 -C:\users\matze\amiga\hardwarehacks\68030-tk\logic\synlog\report\BUS68030_fpga_mapper_warnings.txt +C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_fpga_mapper_warnings.txt 0 -C:\users\matze\amiga\hardwarehacks\68030-tk\logic\synlog\report\BUS68030_fpga_mapper_errors.txt +C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_fpga_mapper_errors.txt @@ -39,7 +39,7 @@ The file contains the job information from mapper to be displayed as part of the 95MB -1400174448 +1400185042 diff --git a/Logic/syntmp/run_option.xml b/Logic/syntmp/run_option.xml index a8fc569..3a71ee4 100644 --- a/Logic/syntmp/run_option.xml +++ b/Logic/syntmp/run_option.xml @@ -2,8 +2,8 @@ diff --git a/Logic/synwork/BUS68030_compiler.fdep b/Logic/synwork/BUS68030_compiler.fdep index 28182d0..ac55656 100644 --- a/Logic/synwork/BUS68030_compiler.fdep +++ b/Logic/synwork/BUS68030_compiler.fdep @@ -10,8 +10,8 @@ #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328 -#CUR:"C:\\users\\matze\\amiga\\hardwarehacks\\68030-tk\\logic\\68030-68000-bus.vhd":1400174441 -0 "C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd" vhdl +#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1400185029 +0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl # Dependency Lists (Uses list) 0 -1 diff --git a/Logic/synwork/BUS68030_compiler.fdeporig b/Logic/synwork/BUS68030_compiler.fdeporig index 3b3bfec..87a5c25 100644 --- a/Logic/synwork/BUS68030_compiler.fdeporig +++ b/Logic/synwork/BUS68030_compiler.fdeporig @@ -10,8 +10,8 @@ #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328 -#CUR:"C:\\users\\matze\\amiga\\hardwarehacks\\68030-tk\\logic\\68030-68000-bus.vhd":1400174441 -0 "C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd" vhdl +#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1400185029 +0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl # Dependency Lists (Uses list) 0 -1 diff --git a/Logic/synwork/BUS68030_compiler.srs b/Logic/synwork/BUS68030_compiler.srs index cf01d59..32e46a3 100644 Binary files a/Logic/synwork/BUS68030_compiler.srs and b/Logic/synwork/BUS68030_compiler.srs differ diff --git a/Logic/synwork/BUS68030_compiler.tlg b/Logic/synwork/BUS68030_compiler.tlg index cc75776..ce77941 100644 --- a/Logic/synwork/BUS68030_compiler.tlg +++ b/Logic/synwork/BUS68030_compiler.tlg @@ -1,18 +1,18 @@ -@N: CD630 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":6:7:6:14|Synthesizing work.bus68030.behavioral -@W: CD638 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":109:7:109:15|Signal clk_030_d is undriven +@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":6:7:6:14|Synthesizing work.bus68030.behavioral +@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:7:109:15|Signal clk_030_d is undriven Post processing for work.bus68030.behavioral -@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":105:52:105:55|Pruning register VMA_INT_D -@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":91:32:91:34|Pruning register CLK_REF(1 downto 0) -@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":220:2:220:3|Pruning register AS_000_START -@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":113:38:113:40|Pruning register cpu_est_d(3 downto 0) -@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":112:37:112:39|Pruning register FALLING_CLK_AMIGA -@A: CL282 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":100:29:100:31|Feedback mux created for signal SM_AMIGA_D[2:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. -@W: CL190 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":100:29:100:31|Optimizing register bit DSACK_INT(0) to a constant 1 -@W: CL260 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":100:29:100:31|Pruning register bit 0 of DSACK_INT(1 downto 0) -@W: CL189 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":124:2:124:3|Register bit CLK_CNT(1) is always 0, optimizing ... -@W: CL260 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":124:2:124:3|Pruning register bit 1 of CLK_CNT(1 downto 0) -@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":113:38:113:40|Trying to extract state machine for register cpu_est -@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":220:2:220:3|Trying to extract state machine for register SM_AMIGA +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":105:52:105:55|Pruning register VMA_INT_D +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":91:32:91:34|Pruning register CLK_REF(1 downto 0) +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":220:2:220:3|Pruning register AS_000_START +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":113:38:113:40|Pruning register CLK_000_CNT(3 downto 0) +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":112:37:112:39|Pruning register FALLING_CLK_AMIGA +@A: CL282 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":100:29:100:31|Feedback mux created for signal SM_AMIGA_D[2:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. +@W: CL190 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":100:29:100:31|Optimizing register bit DSACK_INT(0) to a constant 1 +@W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":100:29:100:31|Pruning register bit 0 of DSACK_INT(1 downto 0) +@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:2:124:3|Register bit CLK_CNT(1) is always 0, optimizing ... +@W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:2:124:3|Pruning register bit 1 of CLK_CNT(1 downto 0) +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":113:38:113:40|Trying to extract state machine for register cpu_est +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":220:2:220:3|Trying to extract state machine for register SM_AMIGA Extracted state machine for register SM_AMIGA State machine has 8 reachable states with original encodings of: 000 @@ -23,4 +23,4 @@ State machine has 8 reachable states with original encodings of: 101 110 111 -@W: CL249 :"C:\users\matze\amiga\hardwarehacks\68030-tk\logic\68030-68000-bus.vhd":220:2:220:3|Initial value is not supported on state machine SM_AMIGA +@W: CL249 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":220:2:220:3|Initial value is not supported on state machine SM_AMIGA