From dd9d5e8c4e948274e5967d11d6ea15363195e320 Mon Sep 17 00:00:00 2001 From: MHeinrichs Date: Sat, 24 May 2014 15:17:08 +0200 Subject: [PATCH] better amiga timing --- Logic/68030-68000-bus.vhd | 83 +- Logic/68030_TK.tcl | 11069 ++++++++++++++++ Logic/68030_tk.bl2 | 1780 ++- Logic/68030_tk.bl3 | 808 +- Logic/68030_tk.crf | 2 +- Logic/68030_tk.eq3 | 179 +- Logic/68030_tk.fti | 106 +- Logic/68030_tk.grp | 22 +- Logic/68030_tk.ipr | 2 +- Logic/68030_tk.jed | 615 +- Logic/68030_tk.lco | 68 +- Logic/68030_tk.out | 5686 ++++++++ Logic/68030_tk.plc | 78 +- Logic/68030_tk.prd | 662 +- Logic/68030_tk.rpt | 579 +- Logic/68030_tk.tal | 12 +- Logic/68030_tk.tt2 | 635 +- Logic/68030_tk.tt3 | 635 +- Logic/68030_tk.tt4 | 283 +- Logic/68030_tk.tte | 283 +- Logic/68030_tk.vcl | 54 +- Logic/68030_tk.vco | 68 +- Logic/68030_tk.xrf | 2 +- Logic/BUS68030.bl0 | 1678 +-- Logic/BUS68030.bl1 | 1780 ++- Logic/BUS68030.edi | 2705 ++-- Logic/BUS68030.fse | 20 +- Logic/BUS68030.prj | 2 +- Logic/BUS68030.srm | 3678 ++--- Logic/BUS68030.srr | 34 +- Logic/BUS68030.srs | Bin 8594 -> 8980 bytes Logic/bus68030.exf | 716 +- Logic/bus68030.srf | 34 +- Logic/dm/BUS68030_compiler.xdm | 10 +- Logic/run_options.txt | 2 +- Logic/synlog/bus68030_fpga_mapper.srr | 15 +- .../report/BUS68030_compiler_errors.txt | 2 +- .../synlog/report/BUS68030_compiler_notes.txt | 4 +- .../report/BUS68030_compiler_runstatus.xml | 4 +- .../report/BUS68030_compiler_warnings.txt | 11 +- .../report/BUS68030_fpga_mapper_notes.txt | 2 +- .../report/BUS68030_fpga_mapper_runstatus.xml | 2 +- Logic/syntmp/run_option.xml | 2 +- Logic/synwork/BUS68030_compiler.fdep | 2 +- Logic/synwork/BUS68030_compiler.fdeporig | 2 +- Logic/synwork/BUS68030_compiler.srs | Bin 8594 -> 8980 bytes Logic/synwork/BUS68030_compiler.tlg | 15 +- 47 files changed, 25548 insertions(+), 8883 deletions(-) diff --git a/Logic/68030-68000-bus.vhd b/Logic/68030-68000-bus.vhd index ed19dd2..f8e30af 100644 --- a/Logic/68030-68000-bus.vhd +++ b/Logic/68030-68000-bus.vhd @@ -116,6 +116,7 @@ signal CLK_000_D2: STD_LOGIC := '1'; signal CLK_000_D3: STD_LOGIC := '1'; signal CLK_000_D4: STD_LOGIC := '1'; signal CLK_000_D5: STD_LOGIC := '1'; +signal CLK_000_D6: STD_LOGIC := '1'; begin @@ -144,6 +145,7 @@ begin CLK_000_D3 <= CLK_000_D2; CLK_000_D4 <= CLK_000_D3; CLK_000_D5 <= CLK_000_D4; + CLK_000_D6 <= CLK_000_D5; @@ -186,7 +188,7 @@ begin AS_030_000_SYNC <= '1'; UDS_000_INT <= '1'; LDS_000_INT <= '1'; - CLK_REF <= "01"; + CLK_REF <= "00"; VMA_INT <= '1'; FPU_CS_INT <= '1'; BG_000 <= '1'; @@ -211,7 +213,7 @@ begin if(BG_030= '1')then BG_000 <= '1'; elsif(CLK_030 ='0') then - if( BG_030= '0' AND (SM_AMIGA = IDLE_N or SM_AMIGA = IDLE_P) + if( BG_030= '0' AND (SM_AMIGA = IDLE_P) and nEXP_SPACE = '0' and AS_030='1') then --bus granted no local access and no AS_030 running! BG_000 <= '0'; else @@ -240,17 +242,12 @@ begin AMIGA_BUS_ENABLE <= '1'; elsif( CLK_030 = '1' AND --68030 has a valid AS on high clocks AS_030 = '0') then - if(FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0' AND BGACK_000='1') then FPU_CS_INT <= '0'; - AS_030_000_SYNC <= '1'; else - if(nEXP_SPACE ='1')then + if(nEXP_SPACE ='1' and SM_AMIGA = IDLE_P )then AS_030_000_SYNC <= '0'; - else - AS_030_000_SYNC <= '1'; end if; - FPU_CS_INT <= '1'; end if; end if; @@ -265,37 +262,39 @@ begin --Amiga statemachine case (SM_AMIGA) is when IDLE_P => --68000:S0 wait for a falling edge - if( CLK_000_D0='0' )then - SM_AMIGA<=IDLE_N; + if( CLK_000_D2='0' and CLK_000_D3= '1' and AS_030_000_SYNC = '0')then + SM_AMIGA<=IDLE_N; --go to s1 end if; - when IDLE_N => --68000:S1 wait for rising edge, on a rising CLK_000 look for a amiga adressrobe - if(nEXP_SPACE ='1')then + when IDLE_N => --68000:S1 place Adress on bus and wait for rising edge, on a rising CLK_000 look for a amiga adressrobe + if(nEXP_SPACE ='1')then AMIGA_BUS_ENABLE <= '0' ;--for now: allways on for amiga - else + else -- if this a delayed expansion space detection, aboard this cycle! AMIGA_BUS_ENABLE <= '1'; + AS_030_000_SYNC <= '1'; + SM_AMIGA <= IDLE_P; --aboard end if; - if(CLK_000_D1='1' and CLK_000_D2 = '0')then --sample AS only at the rising edge! - if( AS_030_000_SYNC = '0' )then - AS_000_INT <= '0'; - if (RW='1' and DS_030 = '0') then --read: set udl/lds - if(A(0)='0') then - UDS_000_INT <= '0'; - else - UDS_000_INT <= '1'; - end if; - if((A(0)='1' OR SIZE(0)='0' OR SIZE(1)='1')) then - LDS_000_INT <= '0'; - else - LDS_000_INT <= '1'; - end if; - end if; - SM_AMIGA <= AS_SET_P; --as for amiga set! - end if; + if(CLK_000_D0='1')then --go to s2 + SM_AMIGA <= AS_SET_P; --as for amiga set! end if; when AS_SET_P => --68000:S2 Amiga cycle starts here: since AS is asserted during transition to this state we simply wait here - if(CLK_000_D0='0')then - SM_AMIGA<=AS_SET_N; + AS_000_INT <= '0'; + if (RW='1' and DS_030 = '0') then --read: set udl/lds + if(A(0)='0') then + UDS_000_INT <= '0'; + else + UDS_000_INT <= '1'; + end if; + if((A(0)='1' OR SIZE(0)='0' OR SIZE(1)='1')) then + LDS_000_INT <= '0'; + else + LDS_000_INT <= '1'; + end if; + end if; + + + if(CLK_000_D0='0')then --go to s3 + SM_AMIGA<=AS_SET_N; end if; when AS_SET_N => --68000:S3: nothing happens here; on a transition to s4: assert uds/lds on write if (RW='0' and DS_030 = '0') then --write: set udl/lds earlier than in the specs. this does not seem to harm anything and is saver, than sampling uds/lds too late @@ -310,15 +309,15 @@ begin LDS_000_INT <= '1'; end if; end if; - if(CLK_000_D0='1')then - SM_AMIGA <= SAMPLE_DTACK_P; + if(CLK_000_D0='1')then --go to s4 + SM_AMIGA <= SAMPLE_DTACK_P; end if; when SAMPLE_DTACK_P=> --68000:S4 wait for dtack or VMA - if(CLK_000_D0='0' )then + if(CLK_000_D0='0' )then --go to s5 if(DTACK_SYNC = '0' OR VPA_SYNC ='0')then SM_AMIGA<=DATA_FETCH_N; end if; - elsif(CLK_000='1' )then -- high clock: sample DTACK + elsif(CLK_000_D0='1' )then -- high clock: sample DTACK if(VPA_D = '1' AND DTACK='0') then DTACK_SYNC <= '0'; elsif(VPA_D='0' AND cpu_est=E9 AND VMA_INT='0') then --vpa/vma cycle: sync VPA on E9: one 7M-clock to latch! @@ -326,16 +325,20 @@ begin end if; end if; when DATA_FETCH_N=> --68000:S5 nothing happens here just wait for positive clock - if(CLK_000_D0='1')then + if(CLK_000_D0='1')then --go to s6 SM_AMIGA<=DATA_FETCH_P; end if; when DATA_FETCH_P => --68000:S6: READ: here comes the data on the bus! - if( CLK_000_D0 ='0' AND CLK_OUT_PRE='1' ) then --next 030-clock is high: dsack is sampled at the falling edge + if( CLK_000_D4 ='1' AND CLK_000_D5 = '0' ) then --go to s7 next 030-clock is high: dsack is sampled at the falling edge DSACK_INT<="01"; + AS_030_000_SYNC <= '1'; --cycle end + elsif( CLK_000_D0 ='0') then --go to s7 next 030-clock is high: dsack is sampled at the falling edge + --DSACK_INT<="01"; SM_AMIGA<=END_CYCLE_N; + --AS_030_000_SYNC <= '1'; --cycle end end if; - when END_CYCLE_N =>--68000:S7: Latch/Store data and go to IDLE on high clock - if(CLK_000_D0='1' and AS_000_INT='1' )then + when END_CYCLE_N =>--68000:S7: Latch/Store data. Wait here for new cycle and go to IDLE on high clock + if(CLK_000_D0='1' and AS_000_INT = '1' )then --go to s0 SM_AMIGA<=IDLE_P; end if; end case; diff --git a/Logic/68030_TK.tcl b/Logic/68030_TK.tcl index 941e51c..995fc5f 100644 --- a/Logic/68030_TK.tcl +++ b/Logic/68030_TK.tcl @@ -136724,3 +136724,11072 @@ if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 6 ########## Tcl recorder end at 05/22/14 14:56:03 ########### + +########## Tcl recorder starts at 05/23/14 09:15:54 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 09:15:54 ########### + + +########## Tcl recorder starts at 05/23/14 09:15:59 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 09:15:59 ########### + + +########## Tcl recorder starts at 05/23/14 09:18:16 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 09:18:16 ########### + + +########## Tcl recorder starts at 05/23/14 09:18:24 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 09:18:24 ########### + + +########## Tcl recorder starts at 05/23/14 09:18:26 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 09:18:26 ########### + + +########## Tcl recorder starts at 05/23/14 09:20:04 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 09:20:04 ########### + + +########## Tcl recorder starts at 05/23/14 09:20:10 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 09:20:10 ########### + + +########## Tcl recorder starts at 05/23/14 09:20:58 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 09:20:58 ########### + + +########## Tcl recorder starts at 05/23/14 09:22:03 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 09:22:03 ########### + + +########## Tcl recorder starts at 05/23/14 09:22:30 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 09:22:30 ########### + + +########## Tcl recorder starts at 05/23/14 09:22:33 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 09:22:34 ########### + + +########## Tcl recorder starts at 05/23/14 09:24:00 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 09:24:00 ########### + + +########## Tcl recorder starts at 05/23/14 09:24:04 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 09:24:04 ########### + + +########## Tcl recorder starts at 05/23/14 09:25:06 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 09:25:06 ########### + + +########## Tcl recorder starts at 05/23/14 09:25:14 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 09:25:14 ########### + + +########## Tcl recorder starts at 05/23/14 09:26:41 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 09:26:41 ########### + + +########## Tcl recorder starts at 05/23/14 09:26:46 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 09:26:46 ########### + + +########## Tcl recorder starts at 05/23/14 09:28:26 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 09:28:26 ########### + + +########## Tcl recorder starts at 05/23/14 09:28:29 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 09:28:29 ########### + + +########## Tcl recorder starts at 05/23/14 09:31:44 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 09:31:44 ########### + + +########## Tcl recorder starts at 05/23/14 09:31:56 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 09:31:56 ########### + + +########## Tcl recorder starts at 05/23/14 09:32:00 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 09:32:00 ########### + + +########## Tcl recorder starts at 05/23/14 09:32:56 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 09:32:56 ########### + + +########## Tcl recorder starts at 05/23/14 09:33:09 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 09:33:09 ########### + + +########## Tcl recorder starts at 05/23/14 09:33:20 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 09:33:20 ########### + + +########## Tcl recorder starts at 05/23/14 09:33:26 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 09:33:26 ########### + + +########## Tcl recorder starts at 05/23/14 09:34:09 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 09:34:09 ########### + + +########## Tcl recorder starts at 05/23/14 09:34:18 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 09:34:18 ########### + + +########## Tcl recorder starts at 05/23/14 09:34:42 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 09:34:42 ########### + + +########## Tcl recorder starts at 05/23/14 09:34:49 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 09:34:49 ########### + + +########## Tcl recorder starts at 05/23/14 09:36:04 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 09:36:04 ########### + + +########## Tcl recorder starts at 05/23/14 09:36:08 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 09:36:08 ########### + + +########## Tcl recorder starts at 05/23/14 13:03:41 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 13:03:41 ########### + + +########## Tcl recorder starts at 05/23/14 13:03:56 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 13:03:56 ########### + + +########## Tcl recorder starts at 05/23/14 13:04:02 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 13:04:02 ########### + + +########## Tcl recorder starts at 05/23/14 13:04:59 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 13:04:59 ########### + + +########## Tcl recorder starts at 05/23/14 13:05:10 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 13:05:10 ########### + + +########## Tcl recorder starts at 05/23/14 13:05:38 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 13:05:38 ########### + + +########## Tcl recorder starts at 05/23/14 13:05:40 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 13:05:40 ########### + + +########## Tcl recorder starts at 05/23/14 13:12:44 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 13:12:44 ########### + + +########## Tcl recorder starts at 05/23/14 13:12:49 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 13:12:49 ########### + + +########## Tcl recorder starts at 05/23/14 13:13:55 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 13:13:55 ########### + + +########## Tcl recorder starts at 05/23/14 13:13:59 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 13:13:59 ########### + + +########## Tcl recorder starts at 05/23/14 13:16:57 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 13:16:57 ########### + + +########## Tcl recorder starts at 05/23/14 13:17:04 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 13:17:04 ########### + + +########## Tcl recorder starts at 05/23/14 13:18:23 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 13:18:23 ########### + + +########## Tcl recorder starts at 05/23/14 13:18:25 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 13:18:25 ########### + + +########## Tcl recorder starts at 05/23/14 13:27:35 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 13:27:35 ########### + + +########## Tcl recorder starts at 05/23/14 13:27:46 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 13:27:46 ########### + + +########## Tcl recorder starts at 05/23/14 13:27:49 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 13:27:49 ########### + + +########## Tcl recorder starts at 05/23/14 13:28:21 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 13:28:21 ########### + + +########## Tcl recorder starts at 05/23/14 13:28:25 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 13:28:25 ########### + + +########## Tcl recorder starts at 05/23/14 13:29:14 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 13:29:14 ########### + + +########## Tcl recorder starts at 05/23/14 13:29:17 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 13:29:17 ########### + + +########## Tcl recorder starts at 05/23/14 13:30:32 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 13:30:32 ########### + + +########## Tcl recorder starts at 05/23/14 13:30:39 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 13:30:39 ########### + + +########## Tcl recorder starts at 05/23/14 13:32:49 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 13:32:49 ########### + + +########## Tcl recorder starts at 05/23/14 13:33:10 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 13:33:10 ########### + + +########## Tcl recorder starts at 05/23/14 13:33:47 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 13:33:47 ########### + + +########## Tcl recorder starts at 05/23/14 13:33:52 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 13:33:52 ########### + + +########## Tcl recorder starts at 05/23/14 13:34:46 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 13:34:46 ########### + + +########## Tcl recorder starts at 05/23/14 13:34:49 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 13:34:49 ########### + + +########## Tcl recorder starts at 05/23/14 14:31:25 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 14:31:25 ########### + + +########## Tcl recorder starts at 05/23/14 14:31:29 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 14:31:29 ########### + + +########## Tcl recorder starts at 05/23/14 14:32:20 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 14:32:20 ########### + + +########## Tcl recorder starts at 05/23/14 14:32:27 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 14:32:27 ########### + + +########## Tcl recorder starts at 05/23/14 14:33:49 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 14:33:49 ########### + + +########## Tcl recorder starts at 05/23/14 14:33:54 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 14:33:54 ########### + + +########## Tcl recorder starts at 05/23/14 14:35:03 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 14:35:03 ########### + + +########## Tcl recorder starts at 05/23/14 14:35:07 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 14:35:07 ########### + + +########## Tcl recorder starts at 05/23/14 14:36:16 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 14:36:16 ########### + + +########## Tcl recorder starts at 05/23/14 14:36:20 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 14:36:20 ########### + + +########## Tcl recorder starts at 05/23/14 14:36:48 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 14:36:48 ########### + + +########## Tcl recorder starts at 05/23/14 14:36:53 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 14:36:53 ########### + + +########## Tcl recorder starts at 05/23/14 14:38:03 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 14:38:03 ########### + + +########## Tcl recorder starts at 05/23/14 14:38:07 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 14:38:07 ########### + + +########## Tcl recorder starts at 05/23/14 14:39:01 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 14:39:02 ########### + + +########## Tcl recorder starts at 05/23/14 14:39:09 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 14:39:09 ########### + + +########## Tcl recorder starts at 05/23/14 14:39:46 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 14:39:46 ########### + + +########## Tcl recorder starts at 05/23/14 14:39:53 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 14:39:53 ########### + + +########## Tcl recorder starts at 05/23/14 14:39:58 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 14:39:58 ########### + + +########## Tcl recorder starts at 05/23/14 14:40:34 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 14:40:34 ########### + + +########## Tcl recorder starts at 05/23/14 14:40:46 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 14:40:46 ########### + + +########## Tcl recorder starts at 05/23/14 14:41:54 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 14:41:54 ########### + + +########## Tcl recorder starts at 05/23/14 14:42:24 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 14:42:24 ########### + + +########## Tcl recorder starts at 05/23/14 14:42:38 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 14:42:38 ########### + + +########## Tcl recorder starts at 05/23/14 14:42:59 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 14:42:59 ########### + + +########## Tcl recorder starts at 05/23/14 14:43:04 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 14:43:04 ########### + + +########## Tcl recorder starts at 05/23/14 14:44:01 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 14:44:01 ########### + + +########## Tcl recorder starts at 05/23/14 14:44:07 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 14:44:07 ########### + + +########## Tcl recorder starts at 05/23/14 14:45:26 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 14:45:26 ########### + + +########## Tcl recorder starts at 05/23/14 14:45:28 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 14:45:28 ########### + + +########## Tcl recorder starts at 05/23/14 14:47:07 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 14:47:07 ########### + + +########## Tcl recorder starts at 05/23/14 14:47:12 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 14:47:12 ########### + + +########## Tcl recorder starts at 05/23/14 14:50:08 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 14:50:08 ########### + + +########## Tcl recorder starts at 05/23/14 14:50:12 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 14:50:12 ########### + + +########## Tcl recorder starts at 05/23/14 14:51:46 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 14:51:46 ########### + + +########## Tcl recorder starts at 05/23/14 14:51:50 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 14:51:50 ########### + + +########## Tcl recorder starts at 05/23/14 14:52:08 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 14:52:08 ########### + + +########## Tcl recorder starts at 05/23/14 14:52:14 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 14:52:14 ########### + + +########## Tcl recorder starts at 05/23/14 14:52:20 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 14:52:20 ########### + + +########## Tcl recorder starts at 05/23/14 14:52:22 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/23/14 14:52:22 ########### + + +########## Tcl recorder starts at 05/24/14 09:55:09 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 09:55:09 ########### + + +########## Tcl recorder starts at 05/24/14 10:00:24 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 10:00:24 ########### + + +########## Tcl recorder starts at 05/24/14 10:00:38 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 10:00:38 ########### + + +########## Tcl recorder starts at 05/24/14 10:01:40 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 10:01:40 ########### + + +########## Tcl recorder starts at 05/24/14 10:01:44 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 10:01:44 ########### + + +########## Tcl recorder starts at 05/24/14 10:08:06 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 10:08:06 ########### + + +########## Tcl recorder starts at 05/24/14 10:08:11 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 10:08:11 ########### + + +########## Tcl recorder starts at 05/24/14 10:15:36 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 10:15:36 ########### + + +########## Tcl recorder starts at 05/24/14 10:15:36 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 10:15:36 ########### + + +########## Tcl recorder starts at 05/24/14 10:16:39 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 10:16:39 ########### + + +########## Tcl recorder starts at 05/24/14 10:16:39 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 10:16:39 ########### + + +########## Tcl recorder starts at 05/24/14 10:17:19 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 10:17:19 ########### + + +########## Tcl recorder starts at 05/24/14 10:17:19 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 10:17:19 ########### + + +########## Tcl recorder starts at 05/24/14 10:34:16 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 10:34:16 ########### + + +########## Tcl recorder starts at 05/24/14 10:34:16 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 10:34:16 ########### + + +########## Tcl recorder starts at 05/24/14 10:35:47 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 10:35:47 ########### + + +########## Tcl recorder starts at 05/24/14 10:35:47 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 10:35:47 ########### + + +########## Tcl recorder starts at 05/24/14 10:37:24 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 10:37:24 ########### + + +########## Tcl recorder starts at 05/24/14 10:37:24 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 10:37:24 ########### + + +########## Tcl recorder starts at 05/24/14 10:38:11 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 10:38:11 ########### + + +########## Tcl recorder starts at 05/24/14 10:38:11 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 10:38:11 ########### + + +########## Tcl recorder starts at 05/24/14 10:39:06 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 10:39:06 ########### + + +########## Tcl recorder starts at 05/24/14 10:39:06 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 10:39:06 ########### + + +########## Tcl recorder starts at 05/24/14 10:41:37 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 10:41:37 ########### + + +########## Tcl recorder starts at 05/24/14 10:41:38 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 10:41:38 ########### + + +########## Tcl recorder starts at 05/24/14 10:42:14 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 10:42:14 ########### + + +########## Tcl recorder starts at 05/24/14 10:42:15 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 10:42:15 ########### + + +########## Tcl recorder starts at 05/24/14 10:43:38 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 10:43:38 ########### + + +########## Tcl recorder starts at 05/24/14 10:43:39 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 10:43:39 ########### + + +########## Tcl recorder starts at 05/24/14 10:44:26 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 10:44:26 ########### + + +########## Tcl recorder starts at 05/24/14 10:44:26 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 10:44:26 ########### + + +########## Tcl recorder starts at 05/24/14 11:44:02 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 11:44:02 ########### + + +########## Tcl recorder starts at 05/24/14 11:44:02 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 11:44:02 ########### + diff --git a/Logic/68030_tk.bl2 b/Logic/68030_tk.bl2 index d42a989..0b9262c 100644 --- a/Logic/68030_tk.bl2 +++ b/Logic/68030_tk.bl2 @@ -1,92 +1,75 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Thu May 22 14:56:10 2014 +#$ DATE Sat May 24 11:44:09 2014 #$ MODULE 68030_tk #$ PINS 74 SIZE_1_ A_31_ IPL_030_2_ IPL_2_ DSACK_1_ FC_1_ AS_030 AS_000 DS_030 UDS_000 \ -# LDS_000 nEXP_SPACE BERR SIZE_0_ BG_030 A_30_ BG_000 A_29_ BGACK_030 A_28_ BGACK_000 A_27_ \ -# CLK_030 A_26_ CLK_000 A_25_ CLK_OSZI A_24_ CLK_DIV_OUT A_23_ CLK_EXP A_22_ FPU_CS A_21_ \ -# DTACK A_20_ AVEC A_19_ AVEC_EXP A_18_ E A_17_ VPA A_16_ VMA A_15_ RST A_14_ RESET A_13_ RW \ -# A_12_ AMIGA_BUS_ENABLE A_11_ AMIGA_BUS_DATA_DIR A_10_ AMIGA_BUS_ENABLE_LOW A_9_ CIIN \ -# A_8_ A_7_ A_6_ A_5_ A_4_ A_3_ A_2_ A_1_ A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ IPL_0_ DSACK_0_ \ -# FC_0_ -#$ NODES 372 BG_000DFFSHreg BGACK_000_c CLK_030_c inst_BGACK_030_INTreg CLK_000_c \ -# inst_FPU_CS_INTreg cpu_est_3_reg CLK_OSZI_c inst_VMA_INTreg cpu_est_0_ cpu_est_1_ \ -# CLK_OUT_INTreg inst_AS_000_INTreg inst_AS_030_000_SYNC inst_DTACK_SYNC \ -# IPL_030DFFSH_0_reg inst_VPA_D inst_VPA_SYNC IPL_030DFFSH_1_reg inst_CLK_000_D0 \ -# inst_CLK_000_D1 IPL_030DFFSH_2_reg inst_CLK_000_D2 inst_CLK_OUT_PRE ipl_c_0__n \ -# SM_AMIGA_6_ vcc_n_n ipl_c_1__n gnd_n_n cpu_est_2_ ipl_c_2__n CLK_REF_0_ CLK_REF_1_ \ -# SM_AMIGA_7_ dsack_c_1__n inst_UDS_000_INTreg inst_LDS_000_INTreg DTACK_c \ -# DSACK_INT_1_ SM_AMIGA_4_ SM_AMIGA_1_ inst_DTACK_DMA clk_clk_cnt_n CLK_CNT_0_ \ -# CLK_CNT_1_ state_machine_un14_as_000_int_n RST_c SM_AMIGA_3_ RESETDFFreg \ -# SM_AMIGA_5_ RW_c SM_AMIGA_2_ SM_AMIGA_0_ fc_c_0__n fc_c_1__n AMIGA_BUS_ENABLEDFFreg \ -# N_101_i N_102_i N_103_i CLK_OUT_PRE_0 cpu_est_0_0_ N_91_0 N_125_i N_123_i N_124_i \ -# N_126_i clk_cpu_est_11_0_1__n N_131_i clk_cpu_est_11_0_3__n N_130_i N_129_i N_122_i \ -# G_86 N_121_i G_87 N_127_i state_machine_un30_clk_000_d1_n N_128_i N_148 N_118_i \ -# DTACK_SYNC_1_sqmuxa state_machine_un8_clk_000_d0_i_n N_96 \ -# state_machine_un13_clk_000_d0_i_n G_91 state_machine_un15_clk_000_d0_0_n N_89 \ -# N_100_i N_97 sm_amiga_ns_0_2__n N_90 clk_un4_clk_000_d1_i_n N_98 \ -# state_machine_un6_bgack_000_0_n N_99 state_machine_un23_clk_000_d0_i_n N_108 \ -# BG_030_c_i UDS_000_INT_0_sqmuxa state_machine_un1_clk_030_0_n \ -# UDS_000_INT_0_sqmuxa_1 state_machine_un17_clk_030_0_n \ -# state_machine_un13_clk_000_d0_1_n un1_as_030_3_0 N_168 N_148_i N_171 a_c_i_0__n \ -# N_105 state_machine_uds_000_int_7_0_n N_92 state_machine_lds_000_int_7_0_n N_106 \ -# AMIGA_BUS_ENABLE_i_m_i N_107 nEXP_SPACE_m_i N_104 \ -# state_machine_amiga_bus_enable_2_iv_i_n state_machine_un42_clk_030_n \ -# state_machine_as_030_000_sync_3_2_n state_machine_un44_clk_000_d1_n N_94_i \ -# un1_bg_030 un1_bg_030_0 N_94 size_c_i_1__n state_machine_as_030_000_sync_3_n \ -# state_machine_un44_clk_000_d1_i_n AMIGA_BUS_ENABLE_i_m N_105_i nEXP_SPACE_m \ -# N_104_i N_95 sm_amiga_ns_0_5__n state_machine_lds_000_int_7_n N_106_i \ -# state_machine_uds_000_int_7_n N_107_i DTACK_SYNC_1_sqmuxa_1 un1_as_030_4 \ -# CLK_OUT_PRE_i un1_as_030_3 N_92_0 DSACK_INT_1_sqmuxa N_90_0 \ -# state_machine_un17_clk_030_n N_89_i state_machine_un1_clk_030_n N_108_i \ -# state_machine_un23_clk_000_d0_n sm_amiga_ns_0_7__n VPA_SYNC_1_sqmuxa N_98_i \ -# VPA_SYNC_1_sqmuxa_1 N_99_i AS_000_INT_1_sqmuxa sm_amiga_ns_0_1__n \ -# state_machine_un6_bgack_000_n N_97_i clk_un4_clk_000_d1_n N_100 \ -# state_machine_un44_clk_000_d1_i_1_n state_machine_un15_clk_000_d0_n \ -# un1_bg_030_0_1 clk_cpu_est_11_3__n un1_bg_030_0_2 state_machine_un2_clk_000_n \ -# state_machine_as_030_000_sync_3_2_1_n state_machine_un13_clk_000_d0_n \ -# clk_cpu_est_11_0_1_1__n state_machine_un8_clk_000_d0_n clk_cpu_est_11_0_2_1__n \ -# N_129 N_168_1 N_122 N_168_2 N_130 N_168_3 N_127 N_168_4 N_128 N_168_5 N_121 N_168_6 \ -# state_machine_un13_clk_000_d0_2_n N_171_1 N_131 N_171_2 clk_cpu_est_11_1__n \ -# UDS_000_INT_0_sqmuxa_1_1 N_126 UDS_000_INT_0_sqmuxa_1_2 N_124 \ -# UDS_000_INT_0_sqmuxa_1_3 N_123 UDS_000_INT_0_sqmuxa_1_0 N_125 N_96_1 N_91 \ -# state_machine_un42_clk_030_1_n N_102 state_machine_un42_clk_030_2_n N_103 \ -# state_machine_un42_clk_030_3_n N_101 state_machine_un42_clk_030_4_n RW_i \ -# state_machine_un42_clk_030_5_n AS_000_INT_i AMIGA_BUS_ENABLE_i_m_1 dsack_i_1__n \ -# VPA_SYNC_1_sqmuxa_1_0 sm_amiga_i_4__n VPA_SYNC_1_sqmuxa_2 sm_amiga_i_5__n \ -# VPA_SYNC_1_sqmuxa_3 CLK_000_D0_i VPA_SYNC_1_sqmuxa_4 sm_amiga_i_3__n \ -# VPA_SYNC_1_sqmuxa_5 cpu_est_i_0__n VPA_SYNC_1_sqmuxa_6 cpu_est_i_3__n N_127_1 \ -# cpu_est_i_2__n N_128_1 VPA_D_i N_131_1 cpu_est_i_1__n clk_cpu_est_11_0_1_3__n \ -# DTACK_i N_105_1 VMA_INT_i DTACK_SYNC_1_sqmuxa_1_0 \ -# state_machine_un13_clk_000_d0_2_i_n DTACK_SYNC_1_sqmuxa_2 CLK_000_D1_i \ -# state_machine_un8_clk_000_d0_1_n VPA_SYNC_1_sqmuxa_i \ -# state_machine_un8_clk_000_d0_2_n AS_030_i state_machine_un8_clk_000_d0_3_n N_95_i \ -# state_machine_un8_clk_000_d0_4_n DTACK_SYNC_1_sqmuxa_i \ -# state_machine_un13_clk_000_d0_1_0_n N_96_i state_machine_un13_clk_000_d0_2_0_n \ -# a_i_18__n cpu_est_0_1__un3_n a_i_16__n cpu_est_0_1__un1_n a_i_19__n \ -# cpu_est_0_1__un0_n CLK_030_i cpu_est_0_3__un3_n state_machine_un42_clk_030_i_n \ -# cpu_est_0_3__un1_n sm_amiga_i_6__n cpu_est_0_3__un0_n sm_amiga_i_7__n \ -# ipl_030_0_0__un3_n AMIGA_BUS_ENABLE_i ipl_030_0_0__un1_n nEXP_SPACE_i \ -# ipl_030_0_0__un0_n sm_amiga_i_2__n ipl_030_0_1__un3_n sm_amiga_i_1__n \ -# ipl_030_0_1__un1_n DS_030_i ipl_030_0_1__un0_n AS_030_000_SYNC_i \ -# ipl_030_0_2__un3_n UDS_000_INT_0_sqmuxa_1_i ipl_030_0_2__un1_n \ -# UDS_000_INT_0_sqmuxa_i ipl_030_0_2__un0_n state_machine_un13_clk_000_d0_1_i_n \ -# uds_000_int_0_un3_n clk_clk_cnt_i_n uds_000_int_0_un1_n clk_cnt_i_0__n \ -# uds_000_int_0_un0_n CLK_000_D2_i vpa_sync_0_un3_n a_i_30__n vpa_sync_0_un1_n \ -# a_i_31__n vpa_sync_0_un0_n a_i_28__n as_000_int_0_un3_n a_i_29__n \ -# as_000_int_0_un1_n a_i_26__n as_000_int_0_un0_n a_i_27__n bgack_030_int_0_un3_n \ -# a_i_24__n bgack_030_int_0_un1_n a_i_25__n bgack_030_int_0_un0_n N_132_i \ -# vma_int_0_un3_n N_133_i vma_int_0_un1_n vma_int_0_un0_n RST_i cpu_est_0_2__un3_n \ -# FPU_CS_INT_i cpu_est_0_2__un1_n BGACK_030_INT_i cpu_est_0_2__un0_n AS_030_c \ -# dsack_int_0_1__un3_n dsack_int_0_1__un1_n dsack_int_0_1__un0_n DS_030_c \ -# bg_000_0_un3_n bg_000_0_un1_n bg_000_0_un0_n amiga_bus_enable_0_un3_n size_c_0__n \ -# amiga_bus_enable_0_un1_n amiga_bus_enable_0_un0_n size_c_1__n \ -# as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n a_c_0__n as_030_000_sync_0_un0_n \ -# fpu_cs_int_0_un3_n fpu_cs_int_0_un1_n fpu_cs_int_0_un0_n dtack_sync_0_un3_n \ -# dtack_sync_0_un1_n dtack_sync_0_un0_n lds_000_int_0_un3_n lds_000_int_0_un1_n \ -# lds_000_int_0_un0_n a_15__n a_14__n a_13__n a_12__n a_c_16__n a_11__n a_c_17__n \ -# a_10__n a_c_18__n a_9__n a_c_19__n a_8__n a_c_20__n a_7__n a_c_21__n a_6__n a_c_22__n \ -# a_5__n a_c_23__n a_4__n a_c_24__n a_3__n a_c_25__n a_2__n a_c_26__n a_1__n a_c_27__n \ -# a_c_28__n a_c_29__n a_c_30__n a_c_31__n nEXP_SPACE_c BG_030_c +# LDS_000 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 SIZE_0_ \ +# CLK_OSZI A_30_ CLK_DIV_OUT A_29_ CLK_EXP A_28_ FPU_CS A_27_ DTACK A_26_ AVEC A_25_ \ +# AVEC_EXP A_24_ E A_23_ VPA A_22_ VMA A_21_ RST A_20_ RESET A_19_ RW A_18_ AMIGA_BUS_ENABLE \ +# A_17_ AMIGA_BUS_DATA_DIR A_16_ AMIGA_BUS_ENABLE_LOW A_15_ CIIN A_14_ A_13_ A_12_ A_11_ \ +# A_10_ A_9_ A_8_ A_7_ A_6_ A_5_ A_4_ A_3_ A_2_ A_1_ A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ IPL_0_ \ +# DSACK_0_ FC_0_ +#$ NODES 376 BGACK_000_c CLK_030_c inst_BGACK_030_INTreg inst_FPU_CS_INTreg \ +# CLK_OSZI_c cpu_est_3_reg inst_VMA_INTreg cpu_est_0_ CLK_OUT_INTreg cpu_est_1_ \ +# inst_AS_000_INTreg inst_AS_030_000_SYNC IPL_030DFFSH_0_reg inst_DTACK_SYNC \ +# inst_VPA_D IPL_030DFFSH_1_reg inst_VPA_SYNC inst_CLK_000_D0 IPL_030DFFSH_2_reg \ +# inst_CLK_000_D1 inst_CLK_000_D2 ipl_c_0__n inst_CLK_000_D5 inst_CLK_OUT_PRE \ +# ipl_c_1__n SM_AMIGA_6_ SM_AMIGA_5_ ipl_c_2__n vcc_n_n gnd_n_n cpu_est_2_ dsack_c_1__n \ +# CLK_REF_1_ inst_UDS_000_INTreg DTACK_c inst_LDS_000_INTreg DSACK_INT_1_ SM_AMIGA_7_ \ +# AS_000_INT_1_sqmuxa state_machine_un8_clk_000_d2_n inst_CLK_000_D3 SM_AMIGA_4_ \ +# state_machine_un23_clk_000_d0_n RST_c state_machine_un6_clk_000_d4_n \ +# inst_CLK_000_D4 RESETDFFreg inst_DTACK_DMA clk_clk_cnt_n RW_c CLK_CNT_0_ CLK_CNT_1_ \ +# fc_c_0__n state_machine_un6_bgack_000_n SM_AMIGA_3_ fc_c_1__n SM_AMIGA_1_ \ +# SM_AMIGA_2_ AMIGA_BUS_ENABLEDFFreg SM_AMIGA_0_ state_machine_un7_as_000_int_n \ +# state_machine_un15_clk_000_d0_n clk_cpu_est_11_0_1__n \ +# state_machine_lds_000_int_5_n N_124_i state_machine_uds_000_int_5_n N_146_i \ +# un1_AMIGA_BUS_ENABLE_1_sqmuxa_2 N_121_i N_122_i N_66_0 N_65_0 N_145_i \ +# un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 DS_030_c_i N_63_i N_62_i \ +# state_machine_un6_clk_000_d4_i_n N_61_i CLK_OUT_PRE_0 N_60_i N_59_i N_58_i N_57_i \ +# CLK_000_D1_i N_56_i N_55_i N_52_i N_141_i N_142_i N_14_0 N_85_i N_139_i \ +# clk_cpu_est_11_1__n N_140_i clk_cpu_est_11_3__n sm_amiga_ns_0_0__n G_92 N_125_i G_96 \ +# N_138_i N_162 N_178_i N_163 clk_cpu_est_11_0_3__n N_164 N_119_i N_165 N_43_i N_30 \ +# N_117_i N_118_i N_51 N_123_i N_52 N_115_i N_55 N_116_i N_56 sm_amiga_ns_0_7__n N_57 \ +# N_98_i N_58 N_114_i N_59 N_39_0 N_60 N_94_i N_61 N_97_i N_62 sm_amiga_ns_0_5__n N_63 \ +# N_89_i N_65 N_90_i N_66 N_69 N_88_i N_72 N_73 N_86_i N_74 N_75 N_83_i N_76 N_77 N_81_i N_79 \ +# state_machine_lds_000_int_5_0_n N_81 state_machine_uds_000_int_5_0_n N_83 N_79_i \ +# N_85 N_30_0 N_86 N_165_0 N_88 N_76_i N_89 N_164_0 N_90 N_163_0 N_94 N_72_i N_97 N_73_i N_98 \ +# state_machine_un15_clk_000_d0_0_n N_114 N_162_0 N_115 \ +# state_machine_un6_bgack_000_0_n N_116 state_machine_un23_clk_000_d0_i_n N_117 \ +# N_188_1 N_118 N_188_2 N_119 N_188_3 N_120 N_188_4 N_121 N_188_5 N_122 N_188_6 N_124 \ +# N_191_1 N_125 N_191_2 N_178 state_machine_un8_clk_000_d2_1_n N_138 N_57_i_1 N_139 \ +# N_57_i_2 N_140 N_57_i_3 N_141 N_57_i_4 N_142 N_57_i_5 N_145 clk_cpu_est_11_0_1_1__n \ +# N_146 clk_cpu_est_11_0_2_1__n N_77_1 N_120_1 N_188 N_120_2 N_191 N_79_1 RW_i N_79_2 \ +# VPA_D_i N_77_1_0 CLK_000_D0_i N_75_1 cpu_est_i_0__n N_75_2 cpu_est_i_3__n N_75_3 \ +# VMA_INT_i N_75_4 cpu_est_i_1__n N_75_5 DTACK_i N_73_1 BG_030_i N_73_2 nEXP_SPACE_i \ +# N_72_1 sm_amiga_i_3__n N_72_2 AS_000_INT_i sm_amiga_ns_0_1_0__n sm_amiga_i_6__n \ +# clk_cpu_est_11_0_1_3__n cpu_est_i_2__n N_138_1 AMIGA_BUS_ENABLE_i N_119_1 AS_030_i \ +# N_118_1 sm_amiga_i_4__n N_117_1 sm_amiga_i_5__n N_97_1 \ +# state_machine_un8_clk_000_d2_i_n N_81_1 sm_amiga_i_7__n \ +# state_machine_uds_000_int_5_0_m2_un3_n a_i_0__n \ +# state_machine_uds_000_int_5_0_m2_un1_n size_i_1__n \ +# state_machine_uds_000_int_5_0_m2_un0_n dsack_i_1__n vpa_sync_0_un3_n \ +# clk_clk_cnt_i_n vpa_sync_0_un1_n clk_cnt_i_0__n vpa_sync_0_un0_n CLK_000_D2_i \ +# amiga_bus_enable_0_un3_n AS_030_000_SYNC_i amiga_bus_enable_0_un1_n a_i_30__n \ +# amiga_bus_enable_0_un0_n a_i_31__n uds_000_int_0_un3_n a_i_28__n \ +# uds_000_int_0_un1_n a_i_29__n uds_000_int_0_un0_n a_i_26__n lds_000_int_0_un3_n \ +# a_i_27__n lds_000_int_0_un1_n a_i_24__n lds_000_int_0_un0_n a_i_25__n \ +# vma_int_0_un3_n a_i_19__n vma_int_0_un1_n a_i_16__n vma_int_0_un0_n a_i_18__n \ +# bg_000_0_un3_n N_137_i bg_000_0_un1_n bg_000_0_un0_n RST_i bgack_030_int_0_un3_n \ +# N_120_i bgack_030_int_0_un1_n N_75_i bgack_030_int_0_un0_n N_74_i \ +# as_000_int_0_un3_n N_77_i as_000_int_0_un1_n FPU_CS_INT_i as_000_int_0_un0_n \ +# BGACK_030_INT_i cpu_est_0_1__un3_n CLK_000_D5_i cpu_est_0_1__un1_n AS_030_c \ +# cpu_est_0_1__un0_n cpu_est_0_2__un3_n cpu_est_0_2__un1_n DS_030_c \ +# cpu_est_0_2__un0_n cpu_est_0_3__un3_n cpu_est_0_3__un1_n cpu_est_0_3__un0_n \ +# size_c_0__n ipl_030_0_0__un3_n ipl_030_0_0__un1_n size_c_1__n ipl_030_0_0__un0_n \ +# ipl_030_0_1__un3_n a_c_0__n ipl_030_0_1__un1_n ipl_030_0_1__un0_n \ +# ipl_030_0_2__un3_n ipl_030_0_2__un1_n ipl_030_0_2__un0_n as_030_000_sync_0_un3_n \ +# as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n dtack_sync_0_un3_n \ +# dtack_sync_0_un1_n dtack_sync_0_un0_n fpu_cs_int_0_un3_n fpu_cs_int_0_un1_n \ +# fpu_cs_int_0_un0_n dsack_int_0_1__un3_n dsack_int_0_1__un1_n dsack_int_0_1__un0_n \ +# a_c_16__n a_15__n a_c_17__n a_14__n a_c_18__n a_13__n a_c_19__n a_12__n a_c_20__n \ +# a_11__n a_c_21__n a_10__n a_c_22__n a_9__n a_c_23__n a_8__n a_c_24__n a_7__n a_c_25__n \ +# a_6__n a_c_26__n a_5__n a_c_27__n a_4__n a_c_28__n a_3__n a_c_29__n a_2__n a_c_30__n \ +# a_1__n a_c_31__n nEXP_SPACE_c BG_030_c BG_000DFFSHreg .model bus68030 .inputs SIZE_1_.BLIF A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF AS_030.BLIF DS_030.BLIF \ nEXP_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF \ @@ -96,242 +79,223 @@ A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF A_15_.BLIF \ A_14_.BLIF A_13_.BLIF A_12_.BLIF A_11_.BLIF A_10_.BLIF A_9_.BLIF A_8_.BLIF \ A_7_.BLIF A_6_.BLIF A_5_.BLIF A_4_.BLIF A_3_.BLIF A_2_.BLIF A_1_.BLIF \ A_0_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF DSACK_1_.BLIF DTACK.BLIF \ -DSACK_0_.BLIF BG_000DFFSHreg.BLIF BGACK_000_c.BLIF CLK_030_c.BLIF \ -inst_BGACK_030_INTreg.BLIF CLK_000_c.BLIF inst_FPU_CS_INTreg.BLIF \ -cpu_est_3_reg.BLIF CLK_OSZI_c.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF \ -cpu_est_1_.BLIF CLK_OUT_INTreg.BLIF inst_AS_000_INTreg.BLIF \ -inst_AS_030_000_SYNC.BLIF inst_DTACK_SYNC.BLIF IPL_030DFFSH_0_reg.BLIF \ -inst_VPA_D.BLIF inst_VPA_SYNC.BLIF IPL_030DFFSH_1_reg.BLIF \ -inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF IPL_030DFFSH_2_reg.BLIF \ -inst_CLK_000_D2.BLIF inst_CLK_OUT_PRE.BLIF ipl_c_0__n.BLIF SM_AMIGA_6_.BLIF \ -vcc_n_n.BLIF ipl_c_1__n.BLIF gnd_n_n.BLIF cpu_est_2_.BLIF ipl_c_2__n.BLIF \ -CLK_REF_0_.BLIF CLK_REF_1_.BLIF SM_AMIGA_7_.BLIF dsack_c_1__n.BLIF \ -inst_UDS_000_INTreg.BLIF inst_LDS_000_INTreg.BLIF DTACK_c.BLIF \ -DSACK_INT_1_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_1_.BLIF inst_DTACK_DMA.BLIF \ -clk_clk_cnt_n.BLIF CLK_CNT_0_.BLIF CLK_CNT_1_.BLIF \ -state_machine_un14_as_000_int_n.BLIF RST_c.BLIF SM_AMIGA_3_.BLIF \ -RESETDFFreg.BLIF SM_AMIGA_5_.BLIF RW_c.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_0_.BLIF \ -fc_c_0__n.BLIF fc_c_1__n.BLIF AMIGA_BUS_ENABLEDFFreg.BLIF N_101_i.BLIF \ -N_102_i.BLIF N_103_i.BLIF CLK_OUT_PRE_0.BLIF cpu_est_0_0_.BLIF N_91_0.BLIF \ -N_125_i.BLIF N_123_i.BLIF N_124_i.BLIF N_126_i.BLIF clk_cpu_est_11_0_1__n.BLIF \ -N_131_i.BLIF clk_cpu_est_11_0_3__n.BLIF N_130_i.BLIF N_129_i.BLIF N_122_i.BLIF \ -G_86.BLIF N_121_i.BLIF G_87.BLIF N_127_i.BLIF \ -state_machine_un30_clk_000_d1_n.BLIF N_128_i.BLIF N_148.BLIF N_118_i.BLIF \ -DTACK_SYNC_1_sqmuxa.BLIF state_machine_un8_clk_000_d0_i_n.BLIF N_96.BLIF \ -state_machine_un13_clk_000_d0_i_n.BLIF G_91.BLIF \ -state_machine_un15_clk_000_d0_0_n.BLIF N_89.BLIF N_100_i.BLIF N_97.BLIF \ -sm_amiga_ns_0_2__n.BLIF N_90.BLIF clk_un4_clk_000_d1_i_n.BLIF N_98.BLIF \ -state_machine_un6_bgack_000_0_n.BLIF N_99.BLIF \ -state_machine_un23_clk_000_d0_i_n.BLIF N_108.BLIF BG_030_c_i.BLIF \ -UDS_000_INT_0_sqmuxa.BLIF state_machine_un1_clk_030_0_n.BLIF \ -UDS_000_INT_0_sqmuxa_1.BLIF state_machine_un17_clk_030_0_n.BLIF \ -state_machine_un13_clk_000_d0_1_n.BLIF un1_as_030_3_0.BLIF N_168.BLIF \ -N_148_i.BLIF N_171.BLIF a_c_i_0__n.BLIF N_105.BLIF \ -state_machine_uds_000_int_7_0_n.BLIF N_92.BLIF \ -state_machine_lds_000_int_7_0_n.BLIF N_106.BLIF AMIGA_BUS_ENABLE_i_m_i.BLIF \ -N_107.BLIF nEXP_SPACE_m_i.BLIF N_104.BLIF \ -state_machine_amiga_bus_enable_2_iv_i_n.BLIF state_machine_un42_clk_030_n.BLIF \ -state_machine_as_030_000_sync_3_2_n.BLIF state_machine_un44_clk_000_d1_n.BLIF \ -N_94_i.BLIF un1_bg_030.BLIF un1_bg_030_0.BLIF N_94.BLIF size_c_i_1__n.BLIF \ -state_machine_as_030_000_sync_3_n.BLIF state_machine_un44_clk_000_d1_i_n.BLIF \ -AMIGA_BUS_ENABLE_i_m.BLIF N_105_i.BLIF nEXP_SPACE_m.BLIF N_104_i.BLIF \ -N_95.BLIF sm_amiga_ns_0_5__n.BLIF state_machine_lds_000_int_7_n.BLIF \ -N_106_i.BLIF state_machine_uds_000_int_7_n.BLIF N_107_i.BLIF \ -DTACK_SYNC_1_sqmuxa_1.BLIF un1_as_030_4.BLIF CLK_OUT_PRE_i.BLIF \ -un1_as_030_3.BLIF N_92_0.BLIF DSACK_INT_1_sqmuxa.BLIF N_90_0.BLIF \ -state_machine_un17_clk_030_n.BLIF N_89_i.BLIF state_machine_un1_clk_030_n.BLIF \ -N_108_i.BLIF state_machine_un23_clk_000_d0_n.BLIF sm_amiga_ns_0_7__n.BLIF \ -VPA_SYNC_1_sqmuxa.BLIF N_98_i.BLIF VPA_SYNC_1_sqmuxa_1.BLIF N_99_i.BLIF \ -AS_000_INT_1_sqmuxa.BLIF sm_amiga_ns_0_1__n.BLIF \ -state_machine_un6_bgack_000_n.BLIF N_97_i.BLIF clk_un4_clk_000_d1_n.BLIF \ -N_100.BLIF state_machine_un44_clk_000_d1_i_1_n.BLIF \ -state_machine_un15_clk_000_d0_n.BLIF un1_bg_030_0_1.BLIF \ -clk_cpu_est_11_3__n.BLIF un1_bg_030_0_2.BLIF state_machine_un2_clk_000_n.BLIF \ -state_machine_as_030_000_sync_3_2_1_n.BLIF \ -state_machine_un13_clk_000_d0_n.BLIF clk_cpu_est_11_0_1_1__n.BLIF \ -state_machine_un8_clk_000_d0_n.BLIF clk_cpu_est_11_0_2_1__n.BLIF N_129.BLIF \ -N_168_1.BLIF N_122.BLIF N_168_2.BLIF N_130.BLIF N_168_3.BLIF N_127.BLIF \ -N_168_4.BLIF N_128.BLIF N_168_5.BLIF N_121.BLIF N_168_6.BLIF \ -state_machine_un13_clk_000_d0_2_n.BLIF N_171_1.BLIF N_131.BLIF N_171_2.BLIF \ -clk_cpu_est_11_1__n.BLIF UDS_000_INT_0_sqmuxa_1_1.BLIF N_126.BLIF \ -UDS_000_INT_0_sqmuxa_1_2.BLIF N_124.BLIF UDS_000_INT_0_sqmuxa_1_3.BLIF \ -N_123.BLIF UDS_000_INT_0_sqmuxa_1_0.BLIF N_125.BLIF N_96_1.BLIF N_91.BLIF \ -state_machine_un42_clk_030_1_n.BLIF N_102.BLIF \ -state_machine_un42_clk_030_2_n.BLIF N_103.BLIF \ -state_machine_un42_clk_030_3_n.BLIF N_101.BLIF \ -state_machine_un42_clk_030_4_n.BLIF RW_i.BLIF \ -state_machine_un42_clk_030_5_n.BLIF AS_000_INT_i.BLIF \ -AMIGA_BUS_ENABLE_i_m_1.BLIF dsack_i_1__n.BLIF VPA_SYNC_1_sqmuxa_1_0.BLIF \ -sm_amiga_i_4__n.BLIF VPA_SYNC_1_sqmuxa_2.BLIF sm_amiga_i_5__n.BLIF \ -VPA_SYNC_1_sqmuxa_3.BLIF CLK_000_D0_i.BLIF VPA_SYNC_1_sqmuxa_4.BLIF \ -sm_amiga_i_3__n.BLIF VPA_SYNC_1_sqmuxa_5.BLIF cpu_est_i_0__n.BLIF \ -VPA_SYNC_1_sqmuxa_6.BLIF cpu_est_i_3__n.BLIF N_127_1.BLIF cpu_est_i_2__n.BLIF \ -N_128_1.BLIF VPA_D_i.BLIF N_131_1.BLIF cpu_est_i_1__n.BLIF \ -clk_cpu_est_11_0_1_3__n.BLIF DTACK_i.BLIF N_105_1.BLIF VMA_INT_i.BLIF \ -DTACK_SYNC_1_sqmuxa_1_0.BLIF state_machine_un13_clk_000_d0_2_i_n.BLIF \ -DTACK_SYNC_1_sqmuxa_2.BLIF CLK_000_D1_i.BLIF \ -state_machine_un8_clk_000_d0_1_n.BLIF VPA_SYNC_1_sqmuxa_i.BLIF \ -state_machine_un8_clk_000_d0_2_n.BLIF AS_030_i.BLIF \ -state_machine_un8_clk_000_d0_3_n.BLIF N_95_i.BLIF \ -state_machine_un8_clk_000_d0_4_n.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF \ -state_machine_un13_clk_000_d0_1_0_n.BLIF N_96_i.BLIF \ -state_machine_un13_clk_000_d0_2_0_n.BLIF a_i_18__n.BLIF \ -cpu_est_0_1__un3_n.BLIF a_i_16__n.BLIF cpu_est_0_1__un1_n.BLIF a_i_19__n.BLIF \ -cpu_est_0_1__un0_n.BLIF CLK_030_i.BLIF cpu_est_0_3__un3_n.BLIF \ -state_machine_un42_clk_030_i_n.BLIF cpu_est_0_3__un1_n.BLIF \ -sm_amiga_i_6__n.BLIF cpu_est_0_3__un0_n.BLIF sm_amiga_i_7__n.BLIF \ -ipl_030_0_0__un3_n.BLIF AMIGA_BUS_ENABLE_i.BLIF ipl_030_0_0__un1_n.BLIF \ -nEXP_SPACE_i.BLIF ipl_030_0_0__un0_n.BLIF sm_amiga_i_2__n.BLIF \ -ipl_030_0_1__un3_n.BLIF sm_amiga_i_1__n.BLIF ipl_030_0_1__un1_n.BLIF \ -DS_030_i.BLIF ipl_030_0_1__un0_n.BLIF AS_030_000_SYNC_i.BLIF \ -ipl_030_0_2__un3_n.BLIF UDS_000_INT_0_sqmuxa_1_i.BLIF ipl_030_0_2__un1_n.BLIF \ -UDS_000_INT_0_sqmuxa_i.BLIF ipl_030_0_2__un0_n.BLIF \ -state_machine_un13_clk_000_d0_1_i_n.BLIF uds_000_int_0_un3_n.BLIF \ -clk_clk_cnt_i_n.BLIF uds_000_int_0_un1_n.BLIF clk_cnt_i_0__n.BLIF \ -uds_000_int_0_un0_n.BLIF CLK_000_D2_i.BLIF vpa_sync_0_un3_n.BLIF \ -a_i_30__n.BLIF vpa_sync_0_un1_n.BLIF a_i_31__n.BLIF vpa_sync_0_un0_n.BLIF \ -a_i_28__n.BLIF as_000_int_0_un3_n.BLIF a_i_29__n.BLIF as_000_int_0_un1_n.BLIF \ -a_i_26__n.BLIF as_000_int_0_un0_n.BLIF a_i_27__n.BLIF \ -bgack_030_int_0_un3_n.BLIF a_i_24__n.BLIF bgack_030_int_0_un1_n.BLIF \ -a_i_25__n.BLIF bgack_030_int_0_un0_n.BLIF N_132_i.BLIF vma_int_0_un3_n.BLIF \ -N_133_i.BLIF vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF RST_i.BLIF \ -cpu_est_0_2__un3_n.BLIF FPU_CS_INT_i.BLIF cpu_est_0_2__un1_n.BLIF \ -BGACK_030_INT_i.BLIF cpu_est_0_2__un0_n.BLIF AS_030_c.BLIF \ -dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF \ -DS_030_c.BLIF bg_000_0_un3_n.BLIF bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF \ -amiga_bus_enable_0_un3_n.BLIF size_c_0__n.BLIF amiga_bus_enable_0_un1_n.BLIF \ -amiga_bus_enable_0_un0_n.BLIF size_c_1__n.BLIF as_030_000_sync_0_un3_n.BLIF \ -as_030_000_sync_0_un1_n.BLIF a_c_0__n.BLIF as_030_000_sync_0_un0_n.BLIF \ -fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF \ +DSACK_0_.BLIF BGACK_000_c.BLIF CLK_030_c.BLIF inst_BGACK_030_INTreg.BLIF \ +inst_FPU_CS_INTreg.BLIF CLK_OSZI_c.BLIF cpu_est_3_reg.BLIF \ +inst_VMA_INTreg.BLIF cpu_est_0_.BLIF CLK_OUT_INTreg.BLIF cpu_est_1_.BLIF \ +inst_AS_000_INTreg.BLIF inst_AS_030_000_SYNC.BLIF IPL_030DFFSH_0_reg.BLIF \ +inst_DTACK_SYNC.BLIF inst_VPA_D.BLIF IPL_030DFFSH_1_reg.BLIF \ +inst_VPA_SYNC.BLIF inst_CLK_000_D0.BLIF IPL_030DFFSH_2_reg.BLIF \ +inst_CLK_000_D1.BLIF inst_CLK_000_D2.BLIF ipl_c_0__n.BLIF inst_CLK_000_D5.BLIF \ +inst_CLK_OUT_PRE.BLIF ipl_c_1__n.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_5_.BLIF \ +ipl_c_2__n.BLIF vcc_n_n.BLIF gnd_n_n.BLIF cpu_est_2_.BLIF dsack_c_1__n.BLIF \ +CLK_REF_1_.BLIF inst_UDS_000_INTreg.BLIF DTACK_c.BLIF inst_LDS_000_INTreg.BLIF \ +DSACK_INT_1_.BLIF SM_AMIGA_7_.BLIF AS_000_INT_1_sqmuxa.BLIF \ +state_machine_un8_clk_000_d2_n.BLIF inst_CLK_000_D3.BLIF SM_AMIGA_4_.BLIF \ +state_machine_un23_clk_000_d0_n.BLIF RST_c.BLIF \ +state_machine_un6_clk_000_d4_n.BLIF inst_CLK_000_D4.BLIF RESETDFFreg.BLIF \ +inst_DTACK_DMA.BLIF clk_clk_cnt_n.BLIF RW_c.BLIF CLK_CNT_0_.BLIF \ +CLK_CNT_1_.BLIF fc_c_0__n.BLIF state_machine_un6_bgack_000_n.BLIF \ +SM_AMIGA_3_.BLIF fc_c_1__n.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_2_.BLIF \ +AMIGA_BUS_ENABLEDFFreg.BLIF SM_AMIGA_0_.BLIF \ +state_machine_un7_as_000_int_n.BLIF state_machine_un15_clk_000_d0_n.BLIF \ +clk_cpu_est_11_0_1__n.BLIF state_machine_lds_000_int_5_n.BLIF N_124_i.BLIF \ +state_machine_uds_000_int_5_n.BLIF N_146_i.BLIF \ +un1_AMIGA_BUS_ENABLE_1_sqmuxa_2.BLIF N_121_i.BLIF N_122_i.BLIF N_66_0.BLIF \ +N_65_0.BLIF N_145_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0.BLIF \ +DS_030_c_i.BLIF N_63_i.BLIF N_62_i.BLIF state_machine_un6_clk_000_d4_i_n.BLIF \ +N_61_i.BLIF CLK_OUT_PRE_0.BLIF N_60_i.BLIF N_59_i.BLIF N_58_i.BLIF N_57_i.BLIF \ +CLK_000_D1_i.BLIF N_56_i.BLIF N_55_i.BLIF N_52_i.BLIF N_141_i.BLIF \ +N_142_i.BLIF N_14_0.BLIF N_85_i.BLIF N_139_i.BLIF clk_cpu_est_11_1__n.BLIF \ +N_140_i.BLIF clk_cpu_est_11_3__n.BLIF sm_amiga_ns_0_0__n.BLIF G_92.BLIF \ +N_125_i.BLIF G_96.BLIF N_138_i.BLIF N_162.BLIF N_178_i.BLIF N_163.BLIF \ +clk_cpu_est_11_0_3__n.BLIF N_164.BLIF N_119_i.BLIF N_165.BLIF N_43_i.BLIF \ +N_30.BLIF N_117_i.BLIF N_118_i.BLIF N_51.BLIF N_123_i.BLIF N_52.BLIF \ +N_115_i.BLIF N_55.BLIF N_116_i.BLIF N_56.BLIF sm_amiga_ns_0_7__n.BLIF \ +N_57.BLIF N_98_i.BLIF N_58.BLIF N_114_i.BLIF N_59.BLIF N_39_0.BLIF N_60.BLIF \ +N_94_i.BLIF N_61.BLIF N_97_i.BLIF N_62.BLIF sm_amiga_ns_0_5__n.BLIF N_63.BLIF \ +N_89_i.BLIF N_65.BLIF N_90_i.BLIF N_66.BLIF N_69.BLIF N_88_i.BLIF N_72.BLIF \ +N_73.BLIF N_86_i.BLIF N_74.BLIF N_75.BLIF N_83_i.BLIF N_76.BLIF N_77.BLIF \ +N_81_i.BLIF N_79.BLIF state_machine_lds_000_int_5_0_n.BLIF N_81.BLIF \ +state_machine_uds_000_int_5_0_n.BLIF N_83.BLIF N_79_i.BLIF N_85.BLIF \ +N_30_0.BLIF N_86.BLIF N_165_0.BLIF N_88.BLIF N_76_i.BLIF N_89.BLIF \ +N_164_0.BLIF N_90.BLIF N_163_0.BLIF N_94.BLIF N_72_i.BLIF N_97.BLIF \ +N_73_i.BLIF N_98.BLIF state_machine_un15_clk_000_d0_0_n.BLIF N_114.BLIF \ +N_162_0.BLIF N_115.BLIF state_machine_un6_bgack_000_0_n.BLIF N_116.BLIF \ +state_machine_un23_clk_000_d0_i_n.BLIF N_117.BLIF N_188_1.BLIF N_118.BLIF \ +N_188_2.BLIF N_119.BLIF N_188_3.BLIF N_120.BLIF N_188_4.BLIF N_121.BLIF \ +N_188_5.BLIF N_122.BLIF N_188_6.BLIF N_124.BLIF N_191_1.BLIF N_125.BLIF \ +N_191_2.BLIF N_178.BLIF state_machine_un8_clk_000_d2_1_n.BLIF N_138.BLIF \ +N_57_i_1.BLIF N_139.BLIF N_57_i_2.BLIF N_140.BLIF N_57_i_3.BLIF N_141.BLIF \ +N_57_i_4.BLIF N_142.BLIF N_57_i_5.BLIF N_145.BLIF clk_cpu_est_11_0_1_1__n.BLIF \ +N_146.BLIF clk_cpu_est_11_0_2_1__n.BLIF N_77_1.BLIF N_120_1.BLIF N_188.BLIF \ +N_120_2.BLIF N_191.BLIF N_79_1.BLIF RW_i.BLIF N_79_2.BLIF VPA_D_i.BLIF \ +N_77_1_0.BLIF CLK_000_D0_i.BLIF N_75_1.BLIF cpu_est_i_0__n.BLIF N_75_2.BLIF \ +cpu_est_i_3__n.BLIF N_75_3.BLIF VMA_INT_i.BLIF N_75_4.BLIF cpu_est_i_1__n.BLIF \ +N_75_5.BLIF DTACK_i.BLIF N_73_1.BLIF BG_030_i.BLIF N_73_2.BLIF \ +nEXP_SPACE_i.BLIF N_72_1.BLIF sm_amiga_i_3__n.BLIF N_72_2.BLIF \ +AS_000_INT_i.BLIF sm_amiga_ns_0_1_0__n.BLIF sm_amiga_i_6__n.BLIF \ +clk_cpu_est_11_0_1_3__n.BLIF cpu_est_i_2__n.BLIF N_138_1.BLIF \ +AMIGA_BUS_ENABLE_i.BLIF N_119_1.BLIF AS_030_i.BLIF N_118_1.BLIF \ +sm_amiga_i_4__n.BLIF N_117_1.BLIF sm_amiga_i_5__n.BLIF N_97_1.BLIF \ +state_machine_un8_clk_000_d2_i_n.BLIF N_81_1.BLIF sm_amiga_i_7__n.BLIF \ +state_machine_uds_000_int_5_0_m2_un3_n.BLIF a_i_0__n.BLIF \ +state_machine_uds_000_int_5_0_m2_un1_n.BLIF size_i_1__n.BLIF \ +state_machine_uds_000_int_5_0_m2_un0_n.BLIF dsack_i_1__n.BLIF \ +vpa_sync_0_un3_n.BLIF clk_clk_cnt_i_n.BLIF vpa_sync_0_un1_n.BLIF \ +clk_cnt_i_0__n.BLIF vpa_sync_0_un0_n.BLIF CLK_000_D2_i.BLIF \ +amiga_bus_enable_0_un3_n.BLIF AS_030_000_SYNC_i.BLIF \ +amiga_bus_enable_0_un1_n.BLIF a_i_30__n.BLIF amiga_bus_enable_0_un0_n.BLIF \ +a_i_31__n.BLIF uds_000_int_0_un3_n.BLIF a_i_28__n.BLIF \ +uds_000_int_0_un1_n.BLIF a_i_29__n.BLIF uds_000_int_0_un0_n.BLIF \ +a_i_26__n.BLIF lds_000_int_0_un3_n.BLIF a_i_27__n.BLIF \ +lds_000_int_0_un1_n.BLIF a_i_24__n.BLIF lds_000_int_0_un0_n.BLIF \ +a_i_25__n.BLIF vma_int_0_un3_n.BLIF a_i_19__n.BLIF vma_int_0_un1_n.BLIF \ +a_i_16__n.BLIF vma_int_0_un0_n.BLIF a_i_18__n.BLIF bg_000_0_un3_n.BLIF \ +N_137_i.BLIF bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF RST_i.BLIF \ +bgack_030_int_0_un3_n.BLIF N_120_i.BLIF bgack_030_int_0_un1_n.BLIF N_75_i.BLIF \ +bgack_030_int_0_un0_n.BLIF N_74_i.BLIF as_000_int_0_un3_n.BLIF N_77_i.BLIF \ +as_000_int_0_un1_n.BLIF FPU_CS_INT_i.BLIF as_000_int_0_un0_n.BLIF \ +BGACK_030_INT_i.BLIF cpu_est_0_1__un3_n.BLIF CLK_000_D5_i.BLIF \ +cpu_est_0_1__un1_n.BLIF AS_030_c.BLIF cpu_est_0_1__un0_n.BLIF \ +cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un1_n.BLIF DS_030_c.BLIF \ +cpu_est_0_2__un0_n.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un1_n.BLIF \ +cpu_est_0_3__un0_n.BLIF size_c_0__n.BLIF ipl_030_0_0__un3_n.BLIF \ +ipl_030_0_0__un1_n.BLIF size_c_1__n.BLIF ipl_030_0_0__un0_n.BLIF \ +ipl_030_0_1__un3_n.BLIF a_c_0__n.BLIF ipl_030_0_1__un1_n.BLIF \ +ipl_030_0_1__un0_n.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un1_n.BLIF \ +ipl_030_0_2__un0_n.BLIF as_030_000_sync_0_un3_n.BLIF \ +as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF \ dtack_sync_0_un3_n.BLIF dtack_sync_0_un1_n.BLIF dtack_sync_0_un0_n.BLIF \ -lds_000_int_0_un3_n.BLIF lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF \ -a_15__n.BLIF a_14__n.BLIF a_13__n.BLIF a_12__n.BLIF a_c_16__n.BLIF \ -a_11__n.BLIF a_c_17__n.BLIF a_10__n.BLIF a_c_18__n.BLIF a_9__n.BLIF \ -a_c_19__n.BLIF a_8__n.BLIF a_c_20__n.BLIF a_7__n.BLIF a_c_21__n.BLIF \ -a_6__n.BLIF a_c_22__n.BLIF a_5__n.BLIF a_c_23__n.BLIF a_4__n.BLIF \ -a_c_24__n.BLIF a_3__n.BLIF a_c_25__n.BLIF a_2__n.BLIF a_c_26__n.BLIF \ -a_1__n.BLIF a_c_27__n.BLIF a_c_28__n.BLIF a_c_29__n.BLIF a_c_30__n.BLIF \ -a_c_31__n.BLIF nEXP_SPACE_c.BLIF BG_030_c.BLIF DSACK_1_.PIN.BLIF \ -DTACK.PIN.BLIF +fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF \ +dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF \ +a_c_16__n.BLIF a_15__n.BLIF a_c_17__n.BLIF a_14__n.BLIF a_c_18__n.BLIF \ +a_13__n.BLIF a_c_19__n.BLIF a_12__n.BLIF a_c_20__n.BLIF a_11__n.BLIF \ +a_c_21__n.BLIF a_10__n.BLIF a_c_22__n.BLIF a_9__n.BLIF a_c_23__n.BLIF \ +a_8__n.BLIF a_c_24__n.BLIF a_7__n.BLIF a_c_25__n.BLIF a_6__n.BLIF \ +a_c_26__n.BLIF a_5__n.BLIF a_c_27__n.BLIF a_4__n.BLIF a_c_28__n.BLIF \ +a_3__n.BLIF a_c_29__n.BLIF a_2__n.BLIF a_c_30__n.BLIF a_1__n.BLIF \ +a_c_31__n.BLIF nEXP_SPACE_c.BLIF BG_030_c.BLIF BG_000DFFSHreg.BLIF \ +DSACK_1_.PIN.BLIF DTACK.PIN.BLIF .outputs IPL_030_2_ AS_000 UDS_000 LDS_000 BERR BG_000 BGACK_030 CLK_DIV_OUT \ CLK_EXP FPU_CS AVEC AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR \ -AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_6_.D SM_AMIGA_6_.C \ -SM_AMIGA_6_.AR SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D \ -SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR \ -SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C \ -SM_AMIGA_1_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR cpu_est_1_.D \ -cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_reg.D cpu_est_3_reg.C \ -IPL_030DFFSH_0_reg.D IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP \ -IPL_030DFFSH_1_reg.D IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP \ -IPL_030DFFSH_2_reg.D IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D \ -SM_AMIGA_7_.C SM_AMIGA_7_.AP inst_VMA_INTreg.D inst_VMA_INTreg.C \ -inst_VMA_INTreg.AP inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C \ -inst_BGACK_030_INTreg.AP inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C CLK_CNT_0_.D \ -CLK_CNT_0_.C CLK_CNT_1_.D CLK_CNT_1_.C cpu_est_0_.D cpu_est_0_.C \ -inst_VPA_SYNC.D inst_VPA_SYNC.C inst_VPA_SYNC.AP inst_FPU_CS_INTreg.D \ -inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP inst_AS_030_000_SYNC.D \ -inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_AS_000_INTreg.D \ -inst_AS_000_INTreg.C inst_AS_000_INTreg.AP AMIGA_BUS_ENABLEDFFreg.D \ -AMIGA_BUS_ENABLEDFFreg.C BG_000DFFSHreg.D BG_000DFFSHreg.C BG_000DFFSHreg.AP \ -DSACK_INT_1_.D DSACK_INT_1_.C DSACK_INT_1_.AP inst_UDS_000_INTreg.D \ +AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ IPL_030DFFSH_0_reg.D \ +IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP IPL_030DFFSH_1_reg.D \ +IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D \ +IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D SM_AMIGA_7_.C \ +SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.D \ +SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_4_.AR \ +SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C \ +SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.D \ +SM_AMIGA_0_.C SM_AMIGA_0_.AR CLK_CNT_0_.D CLK_CNT_0_.C CLK_CNT_1_.D \ +CLK_CNT_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D \ +cpu_est_2_.C cpu_est_3_reg.D cpu_est_3_reg.C inst_UDS_000_INTreg.D \ inst_UDS_000_INTreg.C inst_UDS_000_INTreg.AP inst_LDS_000_INTreg.D \ -inst_LDS_000_INTreg.C inst_LDS_000_INTreg.AP inst_DTACK_SYNC.D \ -inst_DTACK_SYNC.C inst_DTACK_SYNC.AP CLK_OUT_INTreg.D CLK_OUT_INTreg.C \ -inst_DTACK_DMA.D inst_DTACK_DMA.C inst_DTACK_DMA.AP inst_CLK_000_D2.D \ -inst_CLK_000_D2.C inst_VPA_D.D inst_VPA_D.C inst_CLK_000_D0.D \ -inst_CLK_000_D0.C RESETDFFreg.D RESETDFFreg.C inst_CLK_000_D1.D \ -inst_CLK_000_D1.C CLK_REF_0_.D CLK_REF_0_.LH CLK_REF_0_.AP CLK_REF_1_.D \ -CLK_REF_1_.LH CLK_REF_1_.AR DSACK_1_ DTACK DSACK_0_ BGACK_000_c CLK_030_c \ -CLK_000_c CLK_OSZI_c ipl_c_0__n vcc_n_n ipl_c_1__n gnd_n_n ipl_c_2__n \ -dsack_c_1__n DTACK_c clk_clk_cnt_n state_machine_un14_as_000_int_n RST_c RW_c \ -fc_c_0__n fc_c_1__n N_101_i N_102_i N_103_i N_91_0 N_125_i N_123_i N_124_i \ -N_126_i clk_cpu_est_11_0_1__n N_131_i clk_cpu_est_11_0_3__n N_130_i N_129_i \ -N_122_i N_121_i N_127_i state_machine_un30_clk_000_d1_n N_128_i N_148 N_118_i \ -DTACK_SYNC_1_sqmuxa state_machine_un8_clk_000_d0_i_n N_96 \ -state_machine_un13_clk_000_d0_i_n state_machine_un15_clk_000_d0_0_n N_89 \ -N_100_i N_97 sm_amiga_ns_0_2__n N_90 clk_un4_clk_000_d1_i_n N_98 \ -state_machine_un6_bgack_000_0_n N_99 state_machine_un23_clk_000_d0_i_n N_108 \ -BG_030_c_i UDS_000_INT_0_sqmuxa state_machine_un1_clk_030_0_n \ -UDS_000_INT_0_sqmuxa_1 state_machine_un17_clk_030_0_n \ -state_machine_un13_clk_000_d0_1_n un1_as_030_3_0 N_168 N_148_i N_171 \ -a_c_i_0__n N_105 state_machine_uds_000_int_7_0_n N_92 \ -state_machine_lds_000_int_7_0_n N_106 AMIGA_BUS_ENABLE_i_m_i N_107 \ -nEXP_SPACE_m_i N_104 state_machine_amiga_bus_enable_2_iv_i_n \ -state_machine_un42_clk_030_n state_machine_as_030_000_sync_3_2_n \ -state_machine_un44_clk_000_d1_n N_94_i un1_bg_030 un1_bg_030_0 N_94 \ -size_c_i_1__n state_machine_as_030_000_sync_3_n \ -state_machine_un44_clk_000_d1_i_n AMIGA_BUS_ENABLE_i_m N_105_i nEXP_SPACE_m \ -N_104_i N_95 sm_amiga_ns_0_5__n state_machine_lds_000_int_7_n N_106_i \ -state_machine_uds_000_int_7_n N_107_i DTACK_SYNC_1_sqmuxa_1 un1_as_030_4 \ -CLK_OUT_PRE_i un1_as_030_3 N_92_0 DSACK_INT_1_sqmuxa N_90_0 \ -state_machine_un17_clk_030_n N_89_i state_machine_un1_clk_030_n N_108_i \ -state_machine_un23_clk_000_d0_n sm_amiga_ns_0_7__n VPA_SYNC_1_sqmuxa N_98_i \ -VPA_SYNC_1_sqmuxa_1 N_99_i AS_000_INT_1_sqmuxa sm_amiga_ns_0_1__n \ -state_machine_un6_bgack_000_n N_97_i clk_un4_clk_000_d1_n N_100 \ -state_machine_un44_clk_000_d1_i_1_n state_machine_un15_clk_000_d0_n \ -un1_bg_030_0_1 clk_cpu_est_11_3__n un1_bg_030_0_2 state_machine_un2_clk_000_n \ -state_machine_as_030_000_sync_3_2_1_n state_machine_un13_clk_000_d0_n \ -clk_cpu_est_11_0_1_1__n state_machine_un8_clk_000_d0_n clk_cpu_est_11_0_2_1__n \ -N_129 N_168_1 N_122 N_168_2 N_130 N_168_3 N_127 N_168_4 N_128 N_168_5 N_121 \ -N_168_6 state_machine_un13_clk_000_d0_2_n N_171_1 N_131 N_171_2 \ -clk_cpu_est_11_1__n UDS_000_INT_0_sqmuxa_1_1 N_126 UDS_000_INT_0_sqmuxa_1_2 \ -N_124 UDS_000_INT_0_sqmuxa_1_3 N_123 UDS_000_INT_0_sqmuxa_1_0 N_125 N_96_1 \ -N_91 state_machine_un42_clk_030_1_n N_102 state_machine_un42_clk_030_2_n N_103 \ -state_machine_un42_clk_030_3_n N_101 state_machine_un42_clk_030_4_n RW_i \ -state_machine_un42_clk_030_5_n AS_000_INT_i AMIGA_BUS_ENABLE_i_m_1 \ -dsack_i_1__n VPA_SYNC_1_sqmuxa_1_0 sm_amiga_i_4__n VPA_SYNC_1_sqmuxa_2 \ -sm_amiga_i_5__n VPA_SYNC_1_sqmuxa_3 CLK_000_D0_i VPA_SYNC_1_sqmuxa_4 \ -sm_amiga_i_3__n VPA_SYNC_1_sqmuxa_5 cpu_est_i_0__n VPA_SYNC_1_sqmuxa_6 \ -cpu_est_i_3__n N_127_1 cpu_est_i_2__n N_128_1 VPA_D_i N_131_1 cpu_est_i_1__n \ -clk_cpu_est_11_0_1_3__n DTACK_i N_105_1 VMA_INT_i DTACK_SYNC_1_sqmuxa_1_0 \ -state_machine_un13_clk_000_d0_2_i_n DTACK_SYNC_1_sqmuxa_2 CLK_000_D1_i \ -state_machine_un8_clk_000_d0_1_n VPA_SYNC_1_sqmuxa_i \ -state_machine_un8_clk_000_d0_2_n AS_030_i state_machine_un8_clk_000_d0_3_n \ -N_95_i state_machine_un8_clk_000_d0_4_n DTACK_SYNC_1_sqmuxa_i \ -state_machine_un13_clk_000_d0_1_0_n N_96_i state_machine_un13_clk_000_d0_2_0_n \ -a_i_18__n cpu_est_0_1__un3_n a_i_16__n cpu_est_0_1__un1_n a_i_19__n \ -cpu_est_0_1__un0_n CLK_030_i cpu_est_0_3__un3_n state_machine_un42_clk_030_i_n \ -cpu_est_0_3__un1_n sm_amiga_i_6__n cpu_est_0_3__un0_n sm_amiga_i_7__n \ -ipl_030_0_0__un3_n AMIGA_BUS_ENABLE_i ipl_030_0_0__un1_n nEXP_SPACE_i \ -ipl_030_0_0__un0_n sm_amiga_i_2__n ipl_030_0_1__un3_n sm_amiga_i_1__n \ -ipl_030_0_1__un1_n DS_030_i ipl_030_0_1__un0_n AS_030_000_SYNC_i \ -ipl_030_0_2__un3_n UDS_000_INT_0_sqmuxa_1_i ipl_030_0_2__un1_n \ -UDS_000_INT_0_sqmuxa_i ipl_030_0_2__un0_n state_machine_un13_clk_000_d0_1_i_n \ -uds_000_int_0_un3_n clk_clk_cnt_i_n uds_000_int_0_un1_n clk_cnt_i_0__n \ -uds_000_int_0_un0_n CLK_000_D2_i vpa_sync_0_un3_n a_i_30__n vpa_sync_0_un1_n \ -a_i_31__n vpa_sync_0_un0_n a_i_28__n as_000_int_0_un3_n a_i_29__n \ -as_000_int_0_un1_n a_i_26__n as_000_int_0_un0_n a_i_27__n \ -bgack_030_int_0_un3_n a_i_24__n bgack_030_int_0_un1_n a_i_25__n \ -bgack_030_int_0_un0_n N_132_i vma_int_0_un3_n N_133_i vma_int_0_un1_n \ -vma_int_0_un0_n RST_i cpu_est_0_2__un3_n FPU_CS_INT_i cpu_est_0_2__un1_n \ -BGACK_030_INT_i cpu_est_0_2__un0_n AS_030_c dsack_int_0_1__un3_n \ -dsack_int_0_1__un1_n dsack_int_0_1__un0_n DS_030_c bg_000_0_un3_n \ -bg_000_0_un1_n bg_000_0_un0_n amiga_bus_enable_0_un3_n size_c_0__n \ -amiga_bus_enable_0_un1_n amiga_bus_enable_0_un0_n size_c_1__n \ -as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n a_c_0__n \ -as_030_000_sync_0_un0_n fpu_cs_int_0_un3_n fpu_cs_int_0_un1_n \ -fpu_cs_int_0_un0_n dtack_sync_0_un3_n dtack_sync_0_un1_n dtack_sync_0_un0_n \ -lds_000_int_0_un3_n lds_000_int_0_un1_n lds_000_int_0_un0_n a_15__n a_14__n \ -a_13__n a_12__n a_c_16__n a_11__n a_c_17__n a_10__n a_c_18__n a_9__n a_c_19__n \ -a_8__n a_c_20__n a_7__n a_c_21__n a_6__n a_c_22__n a_5__n a_c_23__n a_4__n \ -a_c_24__n a_3__n a_c_25__n a_2__n a_c_26__n a_1__n a_c_27__n a_c_28__n \ -a_c_29__n a_c_30__n a_c_31__n nEXP_SPACE_c BG_030_c DSACK_1_.OE DTACK.OE \ -AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE \ -CLK_OUT_PRE_0 cpu_est_0_0_ G_86 G_87 G_91 -.names sm_amiga_ns_0_1__n.BLIF SM_AMIGA_6_.D +inst_LDS_000_INTreg.C inst_LDS_000_INTreg.AP inst_VMA_INTreg.D \ +inst_VMA_INTreg.C inst_VMA_INTreg.AP BG_000DFFSHreg.D BG_000DFFSHreg.C \ +BG_000DFFSHreg.AP inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C \ +inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP \ +inst_AS_000_INTreg.D inst_AS_000_INTreg.C inst_AS_000_INTreg.AP \ +inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP \ +inst_DTACK_SYNC.D inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_FPU_CS_INTreg.D \ +inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP DSACK_INT_1_.D DSACK_INT_1_.C \ +DSACK_INT_1_.AP inst_VPA_SYNC.D inst_VPA_SYNC.C inst_VPA_SYNC.AP \ +AMIGA_BUS_ENABLEDFFreg.D AMIGA_BUS_ENABLEDFFreg.C inst_CLK_000_D5.D \ +inst_CLK_000_D5.C inst_DTACK_DMA.D inst_DTACK_DMA.C inst_DTACK_DMA.AP \ +CLK_OUT_INTreg.D CLK_OUT_INTreg.C inst_CLK_000_D4.D inst_CLK_000_D4.C \ +inst_CLK_000_D2.D inst_CLK_000_D2.C inst_CLK_000_D3.D inst_CLK_000_D3.C \ +inst_VPA_D.D inst_VPA_D.C inst_CLK_000_D0.D inst_CLK_000_D0.C RESETDFFreg.D \ +RESETDFFreg.C inst_CLK_000_D1.D inst_CLK_000_D1.C CLK_REF_1_.D CLK_REF_1_.LH \ +CLK_REF_1_.AR DSACK_1_ DTACK DSACK_0_ BGACK_000_c CLK_030_c CLK_OSZI_c \ +ipl_c_0__n ipl_c_1__n ipl_c_2__n vcc_n_n gnd_n_n dsack_c_1__n DTACK_c \ +AS_000_INT_1_sqmuxa state_machine_un8_clk_000_d2_n \ +state_machine_un23_clk_000_d0_n RST_c state_machine_un6_clk_000_d4_n \ +clk_clk_cnt_n RW_c fc_c_0__n state_machine_un6_bgack_000_n fc_c_1__n \ +state_machine_un7_as_000_int_n state_machine_un15_clk_000_d0_n \ +clk_cpu_est_11_0_1__n state_machine_lds_000_int_5_n N_124_i \ +state_machine_uds_000_int_5_n N_146_i un1_AMIGA_BUS_ENABLE_1_sqmuxa_2 N_121_i \ +N_122_i N_66_0 N_65_0 N_145_i un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 DS_030_c_i \ +N_63_i N_62_i state_machine_un6_clk_000_d4_i_n N_61_i N_60_i N_59_i N_58_i \ +N_57_i CLK_000_D1_i N_56_i N_55_i N_52_i N_141_i N_142_i N_14_0 N_85_i N_139_i \ +clk_cpu_est_11_1__n N_140_i clk_cpu_est_11_3__n sm_amiga_ns_0_0__n N_125_i \ +N_138_i N_162 N_178_i N_163 clk_cpu_est_11_0_3__n N_164 N_119_i N_165 N_43_i \ +N_30 N_117_i N_118_i N_51 N_123_i N_52 N_115_i N_55 N_116_i N_56 \ +sm_amiga_ns_0_7__n N_57 N_98_i N_58 N_114_i N_59 N_39_0 N_60 N_94_i N_61 \ +N_97_i N_62 sm_amiga_ns_0_5__n N_63 N_89_i N_65 N_90_i N_66 N_69 N_88_i N_72 \ +N_73 N_86_i N_74 N_75 N_83_i N_76 N_77 N_81_i N_79 \ +state_machine_lds_000_int_5_0_n N_81 state_machine_uds_000_int_5_0_n N_83 \ +N_79_i N_85 N_30_0 N_86 N_165_0 N_88 N_76_i N_89 N_164_0 N_90 N_163_0 N_94 \ +N_72_i N_97 N_73_i N_98 state_machine_un15_clk_000_d0_0_n N_114 N_162_0 N_115 \ +state_machine_un6_bgack_000_0_n N_116 state_machine_un23_clk_000_d0_i_n N_117 \ +N_188_1 N_118 N_188_2 N_119 N_188_3 N_120 N_188_4 N_121 N_188_5 N_122 N_188_6 \ +N_124 N_191_1 N_125 N_191_2 N_178 state_machine_un8_clk_000_d2_1_n N_138 \ +N_57_i_1 N_139 N_57_i_2 N_140 N_57_i_3 N_141 N_57_i_4 N_142 N_57_i_5 N_145 \ +clk_cpu_est_11_0_1_1__n N_146 clk_cpu_est_11_0_2_1__n N_77_1 N_120_1 N_188 \ +N_120_2 N_191 N_79_1 RW_i N_79_2 VPA_D_i N_77_1_0 CLK_000_D0_i N_75_1 \ +cpu_est_i_0__n N_75_2 cpu_est_i_3__n N_75_3 VMA_INT_i N_75_4 cpu_est_i_1__n \ +N_75_5 DTACK_i N_73_1 BG_030_i N_73_2 nEXP_SPACE_i N_72_1 sm_amiga_i_3__n \ +N_72_2 AS_000_INT_i sm_amiga_ns_0_1_0__n sm_amiga_i_6__n \ +clk_cpu_est_11_0_1_3__n cpu_est_i_2__n N_138_1 AMIGA_BUS_ENABLE_i N_119_1 \ +AS_030_i N_118_1 sm_amiga_i_4__n N_117_1 sm_amiga_i_5__n N_97_1 \ +state_machine_un8_clk_000_d2_i_n N_81_1 sm_amiga_i_7__n \ +state_machine_uds_000_int_5_0_m2_un3_n a_i_0__n \ +state_machine_uds_000_int_5_0_m2_un1_n size_i_1__n \ +state_machine_uds_000_int_5_0_m2_un0_n dsack_i_1__n vpa_sync_0_un3_n \ +clk_clk_cnt_i_n vpa_sync_0_un1_n clk_cnt_i_0__n vpa_sync_0_un0_n CLK_000_D2_i \ +amiga_bus_enable_0_un3_n AS_030_000_SYNC_i amiga_bus_enable_0_un1_n a_i_30__n \ +amiga_bus_enable_0_un0_n a_i_31__n uds_000_int_0_un3_n a_i_28__n \ +uds_000_int_0_un1_n a_i_29__n uds_000_int_0_un0_n a_i_26__n \ +lds_000_int_0_un3_n a_i_27__n lds_000_int_0_un1_n a_i_24__n \ +lds_000_int_0_un0_n a_i_25__n vma_int_0_un3_n a_i_19__n vma_int_0_un1_n \ +a_i_16__n vma_int_0_un0_n a_i_18__n bg_000_0_un3_n N_137_i bg_000_0_un1_n \ +bg_000_0_un0_n RST_i bgack_030_int_0_un3_n N_120_i bgack_030_int_0_un1_n \ +N_75_i bgack_030_int_0_un0_n N_74_i as_000_int_0_un3_n N_77_i \ +as_000_int_0_un1_n FPU_CS_INT_i as_000_int_0_un0_n BGACK_030_INT_i \ +cpu_est_0_1__un3_n CLK_000_D5_i cpu_est_0_1__un1_n AS_030_c cpu_est_0_1__un0_n \ +cpu_est_0_2__un3_n cpu_est_0_2__un1_n DS_030_c cpu_est_0_2__un0_n \ +cpu_est_0_3__un3_n cpu_est_0_3__un1_n cpu_est_0_3__un0_n size_c_0__n \ +ipl_030_0_0__un3_n ipl_030_0_0__un1_n size_c_1__n ipl_030_0_0__un0_n \ +ipl_030_0_1__un3_n a_c_0__n ipl_030_0_1__un1_n ipl_030_0_1__un0_n \ +ipl_030_0_2__un3_n ipl_030_0_2__un1_n ipl_030_0_2__un0_n \ +as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n \ +dtack_sync_0_un3_n dtack_sync_0_un1_n dtack_sync_0_un0_n fpu_cs_int_0_un3_n \ +fpu_cs_int_0_un1_n fpu_cs_int_0_un0_n dsack_int_0_1__un3_n \ +dsack_int_0_1__un1_n dsack_int_0_1__un0_n a_c_16__n a_15__n a_c_17__n a_14__n \ +a_c_18__n a_13__n a_c_19__n a_12__n a_c_20__n a_11__n a_c_21__n a_10__n \ +a_c_22__n a_9__n a_c_23__n a_8__n a_c_24__n a_7__n a_c_25__n a_6__n a_c_26__n \ +a_5__n a_c_27__n a_4__n a_c_28__n a_3__n a_c_29__n a_2__n a_c_30__n a_1__n \ +a_c_31__n nEXP_SPACE_c BG_030_c DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE \ +LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_OUT_PRE_0 G_92 G_96 +.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF IPL_030DFFSH_0_reg.D +1- 1 +-1 1 +.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF IPL_030DFFSH_1_reg.D +1- 1 +-1 1 +.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF IPL_030DFFSH_2_reg.D +1- 1 +-1 1 +.names sm_amiga_ns_0_0__n.BLIF SM_AMIGA_7_.D 0 1 -.names sm_amiga_ns_0_2__n.BLIF SM_AMIGA_5_.D -0 1 -.names CLK_000_D0_i.BLIF N_101_i.BLIF SM_AMIGA_4_.D +.names N_83_i.BLIF N_85_i.BLIF SM_AMIGA_6_.D 11 1 -.names N_102_i.BLIF N_103_i.BLIF SM_AMIGA_3_.D +.names inst_CLK_000_D0.BLIF N_86_i.BLIF SM_AMIGA_5_.D +11 1 +.names CLK_000_D0_i.BLIF N_88_i.BLIF SM_AMIGA_4_.D +11 1 +.names N_89_i.BLIF N_90_i.BLIF SM_AMIGA_3_.D 11 1 .names sm_amiga_ns_0_5__n.BLIF SM_AMIGA_2_.D 0 1 -.names N_106_i.BLIF N_107_i.BLIF SM_AMIGA_1_.D -11 1 +.names N_39_0.BLIF SM_AMIGA_1_.D +0 1 .names sm_amiga_ns_0_7__n.BLIF SM_AMIGA_0_.D 0 1 +.names clk_cnt_i_0__n.BLIF clk_clk_cnt_i_n.BLIF CLK_CNT_0_.D +11 1 +.names clk_clk_cnt_i_n.BLIF G_96.BLIF CLK_CNT_1_.D +11 1 +.names N_14_0.BLIF cpu_est_0_.D +0 1 .names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D 1- 1 -1 1 @@ -341,669 +305,632 @@ CLK_OUT_PRE_0 cpu_est_0_0_ G_86 G_87 G_91 .names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_reg.D 1- 1 -1 1 -.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF IPL_030DFFSH_0_reg.D -1- 1 --1 1 -.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF IPL_030DFFSH_1_reg.D -1- 1 --1 1 -.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF IPL_030DFFSH_2_reg.D -1- 1 --1 1 -.names inst_CLK_000_D0.BLIF N_97_i.BLIF SM_AMIGA_7_.D -11 1 -.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D -1- 1 --1 1 -.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF \ -inst_BGACK_030_INTreg.D -1- 1 --1 1 -.names clk_cnt_i_0__n.BLIF clk_clk_cnt_i_n.BLIF CLK_CNT_0_.D -11 1 -.names clk_clk_cnt_i_n.BLIF G_91.BLIF CLK_CNT_1_.D -11 1 -.names vpa_sync_0_un1_n.BLIF vpa_sync_0_un0_n.BLIF inst_VPA_SYNC.D -1- 1 --1 1 -.names fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF inst_FPU_CS_INTreg.D -1- 1 --1 1 -.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF \ -inst_AS_030_000_SYNC.D -1- 1 --1 1 -.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF inst_AS_000_INTreg.D -1- 1 --1 1 -.names amiga_bus_enable_0_un1_n.BLIF amiga_bus_enable_0_un0_n.BLIF \ -AMIGA_BUS_ENABLEDFFreg.D -1- 1 --1 1 -.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF BG_000DFFSHreg.D -1- 1 --1 1 -.names dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF DSACK_INT_1_.D -1- 1 --1 1 .names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INTreg.D 1- 1 -1 1 .names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF inst_LDS_000_INTreg.D 1- 1 -1 1 +.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D +1- 1 +-1 1 +.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF BG_000DFFSHreg.D +1- 1 +-1 1 +.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF \ +inst_BGACK_030_INTreg.D +1- 1 +-1 1 +.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF inst_AS_000_INTreg.D +1- 1 +-1 1 +.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF \ +inst_AS_030_000_SYNC.D +1- 1 +-1 1 .names dtack_sync_0_un1_n.BLIF dtack_sync_0_un0_n.BLIF inst_DTACK_SYNC.D 1- 1 -1 1 -.names state_machine_un14_as_000_int_n.BLIF inst_DTACK_DMA.D +.names fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF inst_FPU_CS_INTreg.D +1- 1 +-1 1 +.names dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF DSACK_INT_1_.D +1- 1 +-1 1 +.names vpa_sync_0_un1_n.BLIF vpa_sync_0_un0_n.BLIF inst_VPA_SYNC.D +1- 1 +-1 1 +.names amiga_bus_enable_0_un1_n.BLIF amiga_bus_enable_0_un0_n.BLIF \ +AMIGA_BUS_ENABLEDFFreg.D +1- 1 +-1 1 +.names state_machine_un7_as_000_int_n.BLIF inst_DTACK_DMA.D 0 1 .names vcc_n_n 1 .names gnd_n_n -.names N_132_i.BLIF N_133_i.BLIF clk_clk_cnt_n +.names AS_030_i.BLIF sm_amiga_i_5__n.BLIF AS_000_INT_1_sqmuxa 11 1 -.names AS_000_INT_i.BLIF dsack_i_1__n.BLIF state_machine_un14_as_000_int_n +.names state_machine_un8_clk_000_d2_1_n.BLIF CLK_000_D2_i.BLIF \ +state_machine_un8_clk_000_d2_n 11 1 -.names N_101.BLIF N_101_i +.names state_machine_un23_clk_000_d0_i_n.BLIF state_machine_un23_clk_000_d0_n 0 1 -.names N_102.BLIF N_102_i -0 1 -.names N_103.BLIF N_103_i -0 1 -.names SM_AMIGA_3_.BLIF state_machine_un23_clk_000_d0_i_n.BLIF N_91_0 +.names inst_CLK_000_D4.BLIF CLK_000_D5_i.BLIF state_machine_un6_clk_000_d4_n 11 1 -.names N_125.BLIF N_125_i +.names clk_cnt_i_0__n.BLIF N_137_i.BLIF clk_clk_cnt_n +11 1 +.names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n 0 1 -.names N_123.BLIF N_123_i -0 1 -.names N_124.BLIF N_124_i -0 1 -.names N_126.BLIF N_126_i +.names AS_000_INT_i.BLIF dsack_i_1__n.BLIF state_machine_un7_as_000_int_n +11 1 +.names state_machine_un15_clk_000_d0_0_n.BLIF state_machine_un15_clk_000_d0_n 0 1 .names clk_cpu_est_11_0_1_1__n.BLIF clk_cpu_est_11_0_2_1__n.BLIF \ clk_cpu_est_11_0_1__n 11 1 -.names N_131.BLIF N_131_i +.names state_machine_lds_000_int_5_0_n.BLIF state_machine_lds_000_int_5_n 0 1 -.names clk_cpu_est_11_0_1_3__n.BLIF N_130_i.BLIF clk_cpu_est_11_0_3__n -11 1 -.names N_130.BLIF N_130_i +.names N_124.BLIF N_124_i 0 1 -.names N_129.BLIF N_129_i +.names state_machine_uds_000_int_5_0_n.BLIF state_machine_uds_000_int_5_n 0 1 -.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_122_i -11 1 -.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF N_121_i -11 1 -.names N_127.BLIF N_127_i +.names N_146.BLIF N_146_i 0 1 -.names inst_CLK_000_D1.BLIF CLK_000_D2_i.BLIF state_machine_un30_clk_000_d1_n -11 1 -.names N_128.BLIF N_128_i +.names un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2 0 1 -.names UDS_000_INT_0_sqmuxa_1_i.BLIF UDS_000_INT_0_sqmuxa_i.BLIF N_148 -11 1 -.names N_127_i.BLIF N_128_i.BLIF N_118_i -11 1 -.names DTACK_SYNC_1_sqmuxa_1_0.BLIF DTACK_SYNC_1_sqmuxa_2.BLIF \ -DTACK_SYNC_1_sqmuxa -11 1 -.names state_machine_un8_clk_000_d0_n.BLIF state_machine_un8_clk_000_d0_i_n +.names N_121.BLIF N_121_i 0 1 -.names N_96_1.BLIF SM_AMIGA_1_.BLIF N_96 -11 1 -.names state_machine_un13_clk_000_d0_n.BLIF state_machine_un13_clk_000_d0_i_n +.names N_122.BLIF N_122_i 0 1 -.names state_machine_un8_clk_000_d0_i_n.BLIF \ -state_machine_un13_clk_000_d0_i_n.BLIF state_machine_un15_clk_000_d0_0_n +.names SM_AMIGA_3_.BLIF state_machine_un23_clk_000_d0_i_n.BLIF N_66_0 11 1 -.names N_89_i.BLIF N_89 +.names CLK_000_D0_i.BLIF N_58_i.BLIF N_65_0 +11 1 +.names N_145.BLIF N_145_i 0 1 -.names N_100.BLIF N_100_i +.names N_52_i.BLIF N_145_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 +11 1 +.names DS_030_c.BLIF DS_030_c_i 0 1 -.names N_90.BLIF sm_amiga_i_7__n.BLIF N_97 +.names DS_030_c_i.BLIF N_51.BLIF N_63_i 11 1 -.names N_95_i.BLIF N_100_i.BLIF sm_amiga_ns_0_2__n +.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_62_i 11 1 -.names N_90_0.BLIF N_90 +.names state_machine_un6_clk_000_d4_n.BLIF state_machine_un6_clk_000_d4_i_n 0 1 -.names clk_un4_clk_000_d1_n.BLIF clk_un4_clk_000_d1_i_n +.names CLK_000_D0_i.BLIF state_machine_un6_clk_000_d4_i_n.BLIF N_61_i +11 1 +.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF N_60_i +11 1 +.names inst_AS_000_INTreg.BLIF inst_CLK_000_D0.BLIF N_59_i +11 1 +.names SM_AMIGA_6_.BLIF nEXP_SPACE_c.BLIF N_58_i +11 1 +.names N_57_i_4.BLIF N_57_i_5.BLIF N_57_i +11 1 +.names inst_CLK_000_D1.BLIF CLK_000_D1_i 0 1 -.names N_89.BLIF SM_AMIGA_6_.BLIF N_98 +.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF N_56_i 11 1 -.names BGACK_000_c.BLIF clk_un4_clk_000_d1_i_n.BLIF \ -state_machine_un6_bgack_000_0_n +.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_55_i 11 1 -.names CLK_000_D0_i.BLIF SM_AMIGA_7_.BLIF N_99 +.names AS_030_i.BLIF N_74_i.BLIF N_52_i +11 1 +.names N_141.BLIF N_141_i +0 1 +.names N_142.BLIF N_142_i +0 1 +.names N_141_i.BLIF N_142_i.BLIF N_14_0 +11 1 +.names N_85.BLIF N_85_i +0 1 +.names N_139.BLIF N_139_i +0 1 +.names clk_cpu_est_11_0_1__n.BLIF clk_cpu_est_11_1__n +0 1 +.names N_140.BLIF N_140_i +0 1 +.names clk_cpu_est_11_0_3__n.BLIF clk_cpu_est_11_3__n +0 1 +.names sm_amiga_ns_0_1_0__n.BLIF N_139_i.BLIF sm_amiga_ns_0_0__n +11 1 +.names N_125.BLIF N_125_i +0 1 +.names N_138.BLIF N_138_i +0 1 +.names N_162_0.BLIF N_162 +0 1 +.names N_178.BLIF N_178_i +0 1 +.names N_163_0.BLIF N_163 +0 1 +.names clk_cpu_est_11_0_1_3__n.BLIF N_138_i.BLIF clk_cpu_est_11_0_3__n +11 1 +.names N_164_0.BLIF N_164 +0 1 +.names N_119.BLIF N_119_i +0 1 +.names N_165_0.BLIF N_165 +0 1 +.names N_58.BLIF N_119_i.BLIF N_43_i +11 1 +.names N_30_0.BLIF N_30 +0 1 +.names N_117.BLIF N_117_i +0 1 +.names N_118.BLIF N_118_i +0 1 +.names state_machine_uds_000_int_5_0_m2_un1_n.BLIF \ +state_machine_uds_000_int_5_0_m2_un0_n.BLIF N_51 +1- 1 +-1 1 +.names N_117_i.BLIF N_118_i.BLIF N_123_i +11 1 +.names N_52_i.BLIF N_52 +0 1 +.names N_115.BLIF N_115_i +0 1 +.names N_55_i.BLIF N_55 +0 1 +.names N_116.BLIF N_116_i +0 1 +.names N_56_i.BLIF N_56 +0 1 +.names N_115_i.BLIF N_116_i.BLIF sm_amiga_ns_0_7__n +11 1 +.names N_57_i.BLIF N_57 +0 1 +.names N_98.BLIF N_98_i +0 1 +.names N_58_i.BLIF N_58 +0 1 +.names N_114.BLIF N_114_i +0 1 +.names N_59_i.BLIF N_59 +0 1 +.names N_98_i.BLIF N_114_i.BLIF N_39_0 +11 1 +.names N_60_i.BLIF N_60 +0 1 +.names N_94.BLIF N_94_i +0 1 +.names N_61_i.BLIF N_61 +0 1 +.names N_97.BLIF N_97_i +0 1 +.names N_62_i.BLIF N_62 +0 1 +.names N_94_i.BLIF N_97_i.BLIF sm_amiga_ns_0_5__n +11 1 +.names N_63_i.BLIF N_63 +0 1 +.names N_89.BLIF N_89_i +0 1 +.names N_65_0.BLIF N_65 +0 1 +.names N_90.BLIF N_90_i +0 1 +.names N_66_0.BLIF N_66 +0 1 +.names BG_030_i.BLIF CLK_030_c.BLIF N_69 +11 1 +.names N_88.BLIF N_88_i +0 1 +.names N_72_1.BLIF N_72_2.BLIF N_72 +11 1 +.names N_73_1.BLIF N_73_2.BLIF N_73 +11 1 +.names N_86.BLIF N_86_i +0 1 +.names SM_AMIGA_1_.BLIF state_machine_un6_clk_000_d4_n.BLIF N_74 +11 1 +.names N_75_4.BLIF N_75_5.BLIF N_75 +11 1 +.names N_83.BLIF N_83_i +0 1 +.names CLK_030_c.BLIF N_57_i.BLIF N_76 +11 1 +.names N_77_1_0.BLIF inst_VPA_D.BLIF N_77 +11 1 +.names N_81.BLIF N_81_i +0 1 +.names N_79_1.BLIF N_79_2.BLIF N_79 +11 1 +.names N_63_i.BLIF N_81_i.BLIF state_machine_lds_000_int_5_0_n +11 1 +.names N_81_1.BLIF size_i_1__n.BLIF N_81 +11 1 +.names a_i_0__n.BLIF N_63_i.BLIF state_machine_uds_000_int_5_0_n +11 1 +.names N_65.BLIF sm_amiga_i_7__n.BLIF N_83 +11 1 +.names N_79.BLIF N_79_i +0 1 +.names SM_AMIGA_7_.BLIF state_machine_un8_clk_000_d2_i_n.BLIF N_85 +11 1 +.names N_79_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0.BLIF N_30_0 +11 1 +.names sm_amiga_i_5__n.BLIF sm_amiga_i_6__n.BLIF N_86 +11 1 +.names AS_030_i.BLIF N_77_i.BLIF N_165_0 +11 1 +.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_88 +11 1 +.names N_76.BLIF N_76_i +0 1 +.names CLK_000_D0_i.BLIF N_66.BLIF N_89 +11 1 +.names AS_030_i.BLIF N_76_i.BLIF N_164_0 +11 1 +.names sm_amiga_i_3__n.BLIF sm_amiga_i_4__n.BLIF N_90 +11 1 +.names AS_030_i.BLIF N_75_i.BLIF N_163_0 +11 1 +.names CLK_000_D0_i.BLIF SM_AMIGA_2_.BLIF N_94 +11 1 +.names N_72.BLIF N_72_i +0 1 +.names N_97_1.BLIF state_machine_un23_clk_000_d0_n.BLIF N_97 +11 1 +.names N_73.BLIF N_73_i +0 1 +.names N_61.BLIF SM_AMIGA_1_.BLIF N_98 +11 1 +.names N_72_i.BLIF N_73_i.BLIF state_machine_un15_clk_000_d0_0_n +11 1 +.names inst_CLK_000_D0.BLIF SM_AMIGA_2_.BLIF N_114 +11 1 +.names AS_030_i.BLIF N_63.BLIF N_162_0 +11 1 +.names N_59.BLIF SM_AMIGA_0_.BLIF N_115 +11 1 +.names BGACK_000_c.BLIF N_56.BLIF state_machine_un6_bgack_000_0_n +11 1 +.names N_61_i.BLIF SM_AMIGA_1_.BLIF N_116 11 1 .names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF \ state_machine_un23_clk_000_d0_i_n 11 1 -.names SM_AMIGA_0_.BLIF state_machine_un13_clk_000_d0_1_i_n.BLIF N_108 +.names N_117_1.BLIF cpu_est_i_3__n.BLIF N_117 11 1 -.names BG_030_c.BLIF BG_030_c_i -0 1 -.names UDS_000_INT_0_sqmuxa_1_0.BLIF RW_i.BLIF UDS_000_INT_0_sqmuxa +.names a_i_24__n.BLIF a_i_25__n.BLIF N_188_1 11 1 -.names BG_030_c_i.BLIF CLK_030_c.BLIF state_machine_un1_clk_030_0_n +.names N_118_1.BLIF cpu_est_i_2__n.BLIF N_118 11 1 -.names UDS_000_INT_0_sqmuxa_1_3.BLIF state_machine_un30_clk_000_d1_n.BLIF \ -UDS_000_INT_0_sqmuxa_1 +.names a_i_26__n.BLIF a_i_27__n.BLIF N_188_2 11 1 -.names AS_030_i.BLIF CLK_030_i.BLIF state_machine_un17_clk_030_0_n +.names N_119_1.BLIF sm_amiga_i_6__n.BLIF N_119 11 1 -.names inst_AS_000_INTreg.BLIF inst_CLK_000_D0.BLIF \ -state_machine_un13_clk_000_d0_1_n +.names a_i_28__n.BLIF a_i_29__n.BLIF N_188_3 11 1 -.names AS_030_i.BLIF state_machine_un42_clk_030_n.BLIF un1_as_030_3_0 +.names N_120_1.BLIF N_120_2.BLIF N_120 11 1 -.names N_168_5.BLIF N_168_6.BLIF N_168 +.names a_i_30__n.BLIF a_i_31__n.BLIF N_188_4 11 1 -.names N_148.BLIF N_148_i -0 1 -.names N_171_1.BLIF N_171_2.BLIF N_171 +.names N_60.BLIF cpu_est_i_0__n.BLIF N_121 11 1 -.names a_c_0__n.BLIF a_c_i_0__n -0 1 -.names N_105_1.BLIF state_machine_un23_clk_000_d0_n.BLIF N_105 +.names N_188_1.BLIF N_188_2.BLIF N_188_5 11 1 -.names a_c_i_0__n.BLIF N_148_i.BLIF state_machine_uds_000_int_7_0_n +.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_122 11 1 -.names N_92_0.BLIF N_92 -0 1 -.names N_148_i.BLIF state_machine_un44_clk_000_d1_n.BLIF \ -state_machine_lds_000_int_7_0_n +.names N_188_3.BLIF N_188_4.BLIF N_188_6 11 1 -.names CLK_000_D0_i.BLIF N_92.BLIF N_106 +.names N_55_i.BLIF cpu_est_3_reg.BLIF N_124 11 1 -.names AMIGA_BUS_ENABLE_i_m.BLIF AMIGA_BUS_ENABLE_i_m_i -0 1 -.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_107 +.names a_c_20__n.BLIF a_c_21__n.BLIF N_191_1 11 1 -.names nEXP_SPACE_m.BLIF nEXP_SPACE_m_i -0 1 -.names CLK_000_D0_i.BLIF SM_AMIGA_2_.BLIF N_104 +.names N_62.BLIF cpu_est_3_reg.BLIF N_125 11 1 -.names AMIGA_BUS_ENABLE_i_m_i.BLIF nEXP_SPACE_m_i.BLIF \ -state_machine_amiga_bus_enable_2_iv_i_n +.names a_c_22__n.BLIF a_c_23__n.BLIF N_191_2 11 1 -.names state_machine_un42_clk_030_4_n.BLIF state_machine_un42_clk_030_5_n.BLIF \ -state_machine_un42_clk_030_n +.names N_62_i.BLIF cpu_est_i_2__n.BLIF N_178 11 1 -.names state_machine_as_030_000_sync_3_2_1_n.BLIF \ -state_machine_un42_clk_030_i_n.BLIF state_machine_as_030_000_sync_3_2_n +.names inst_CLK_000_D3.BLIF AS_030_000_SYNC_i.BLIF \ +state_machine_un8_clk_000_d2_1_n 11 1 -.names state_machine_un44_clk_000_d1_i_n.BLIF state_machine_un44_clk_000_d1_n -0 1 -.names N_94.BLIF N_94_i -0 1 -.names un1_bg_030_0.BLIF un1_bg_030 -0 1 -.names un1_bg_030_0_1.BLIF un1_bg_030_0_2.BLIF un1_bg_030_0 +.names N_138_1.BLIF cpu_est_i_2__n.BLIF N_138 11 1 -.names sm_amiga_i_6__n.BLIF sm_amiga_i_7__n.BLIF N_94 +.names a_c_17__n.BLIF BGACK_000_c.BLIF N_57_i_1 11 1 -.names size_c_1__n.BLIF size_c_i_1__n -0 1 -.names state_machine_as_030_000_sync_3_2_n.BLIF \ -state_machine_as_030_000_sync_3_n -0 1 -.names state_machine_un44_clk_000_d1_i_1_n.BLIF size_c_i_1__n.BLIF \ -state_machine_un44_clk_000_d1_i_n +.names CLK_000_D0_i.BLIF N_145.BLIF N_139 11 1 -.names AMIGA_BUS_ENABLE_i_m_1.BLIF sm_amiga_i_6__n.BLIF AMIGA_BUS_ENABLE_i_m +.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_57_i_2 11 1 -.names N_105.BLIF N_105_i -0 1 -.names SM_AMIGA_6_.BLIF nEXP_SPACE_c.BLIF nEXP_SPACE_m +.names N_59_i.BLIF SM_AMIGA_0_.BLIF N_140 11 1 -.names N_104.BLIF N_104_i -0 1 -.names N_89_i.BLIF SM_AMIGA_6_.BLIF N_95 +.names a_i_19__n.BLIF a_i_16__n.BLIF N_57_i_3 11 1 -.names N_104_i.BLIF N_105_i.BLIF sm_amiga_ns_0_5__n +.names N_56.BLIF cpu_est_0_.BLIF N_141 11 1 -.names state_machine_lds_000_int_7_0_n.BLIF state_machine_lds_000_int_7_n -0 1 -.names N_106.BLIF N_106_i -0 1 -.names state_machine_uds_000_int_7_0_n.BLIF state_machine_uds_000_int_7_n -0 1 -.names N_107.BLIF N_107_i -0 1 -.names AS_030_i.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF DTACK_SYNC_1_sqmuxa_1 +.names N_57_i_1.BLIF N_57_i_2.BLIF N_57_i_4 11 1 -.names AS_030_i.BLIF N_148.BLIF un1_as_030_4 +.names N_56_i.BLIF cpu_est_i_0__n.BLIF N_142 11 1 -.names inst_CLK_OUT_PRE.BLIF CLK_OUT_PRE_i -0 1 -.names un1_as_030_3_0.BLIF un1_as_030_3 -0 1 -.names CLK_OUT_PRE_i.BLIF sm_amiga_i_2__n.BLIF N_92_0 +.names N_57_i_3.BLIF a_i_18__n.BLIF N_57_i_5 11 1 -.names AS_030_i.BLIF N_96_i.BLIF DSACK_INT_1_sqmuxa +.names SM_AMIGA_6_.BLIF nEXP_SPACE_i.BLIF N_145 11 1 -.names inst_AS_000_INTreg.BLIF SM_AMIGA_0_.BLIF N_90_0 +.names N_121_i.BLIF N_122_i.BLIF clk_cpu_est_11_0_1_1__n 11 1 -.names state_machine_un17_clk_030_0_n.BLIF state_machine_un17_clk_030_n -0 1 -.names AS_030_000_SYNC_i.BLIF state_machine_un30_clk_000_d1_n.BLIF N_89_i +.names N_60_i.BLIF cpu_est_0_.BLIF N_146 11 1 -.names state_machine_un1_clk_030_0_n.BLIF state_machine_un1_clk_030_n -0 1 -.names N_108.BLIF N_108_i -0 1 -.names state_machine_un23_clk_000_d0_i_n.BLIF state_machine_un23_clk_000_d0_n -0 1 -.names N_96_i.BLIF N_108_i.BLIF sm_amiga_ns_0_7__n +.names N_124_i.BLIF N_146_i.BLIF clk_cpu_est_11_0_2_1__n 11 1 -.names VPA_SYNC_1_sqmuxa_5.BLIF VPA_SYNC_1_sqmuxa_6.BLIF VPA_SYNC_1_sqmuxa +.names inst_CLK_000_D0.BLIF SM_AMIGA_3_.BLIF N_77_1 11 1 -.names N_98.BLIF N_98_i -0 1 -.names AS_030_i.BLIF VPA_SYNC_1_sqmuxa_i.BLIF VPA_SYNC_1_sqmuxa_1 +.names AS_030_c.BLIF BG_030_i.BLIF N_120_1 11 1 -.names N_99.BLIF N_99_i -0 1 -.names AS_030_i.BLIF N_95_i.BLIF AS_000_INT_1_sqmuxa +.names N_188_5.BLIF N_188_6.BLIF N_188 11 1 -.names N_98_i.BLIF N_99_i.BLIF sm_amiga_ns_0_1__n +.names SM_AMIGA_7_.BLIF nEXP_SPACE_i.BLIF N_120_2 11 1 -.names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n -0 1 -.names N_97.BLIF N_97_i -0 1 -.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF clk_un4_clk_000_d1_n +.names N_191_1.BLIF N_191_2.BLIF N_191 11 1 -.names inst_CLK_000_D0.BLIF SM_AMIGA_5_.BLIF N_100 -11 1 -.names size_c_0__n.BLIF a_c_i_0__n.BLIF state_machine_un44_clk_000_d1_i_1_n -11 1 -.names state_machine_un15_clk_000_d0_0_n.BLIF state_machine_un15_clk_000_d0_n -0 1 -.names BG_030_c_i.BLIF N_94_i.BLIF un1_bg_030_0_1 -11 1 -.names clk_cpu_est_11_0_3__n.BLIF clk_cpu_est_11_3__n -0 1 -.names AS_030_c.BLIF nEXP_SPACE_i.BLIF un1_bg_030_0_2 -11 1 -.names inst_CLK_000_D0.BLIF CLK_000_c.BLIF state_machine_un2_clk_000_n -11 1 -.names AS_030_i.BLIF nEXP_SPACE_c.BLIF state_machine_as_030_000_sync_3_2_1_n -11 1 -.names state_machine_un13_clk_000_d0_1_0_n.BLIF \ -state_machine_un13_clk_000_d0_2_0_n.BLIF state_machine_un13_clk_000_d0_n -11 1 -.names N_126_i.BLIF N_124_i.BLIF clk_cpu_est_11_0_1_1__n -11 1 -.names state_machine_un8_clk_000_d0_4_n.BLIF \ -state_machine_un8_clk_000_d0_3_n.BLIF state_machine_un8_clk_000_d0_n -11 1 -.names N_123_i.BLIF N_125_i.BLIF clk_cpu_est_11_0_2_1__n -11 1 -.names N_122.BLIF cpu_est_3_reg.BLIF N_129 -11 1 -.names a_i_24__n.BLIF a_i_25__n.BLIF N_168_1 -11 1 -.names N_122_i.BLIF N_122 -0 1 -.names a_i_26__n.BLIF a_i_27__n.BLIF N_168_2 -11 1 -.names N_122_i.BLIF cpu_est_i_2__n.BLIF N_130 -11 1 -.names a_i_28__n.BLIF a_i_29__n.BLIF N_168_3 -11 1 -.names N_127_1.BLIF state_machine_un13_clk_000_d0_2_i_n.BLIF N_127 -11 1 -.names a_i_30__n.BLIF a_i_31__n.BLIF N_168_4 -11 1 -.names N_128_1.BLIF cpu_est_i_2__n.BLIF N_128 -11 1 -.names N_168_1.BLIF N_168_2.BLIF N_168_5 -11 1 -.names N_121_i.BLIF N_121 -0 1 -.names N_168_3.BLIF N_168_4.BLIF N_168_6 -11 1 -.names cpu_est_1_.BLIF cpu_est_2_.BLIF state_machine_un13_clk_000_d0_2_n -11 1 -.names a_c_20__n.BLIF a_c_21__n.BLIF N_171_1 -11 1 -.names N_131_1.BLIF cpu_est_i_2__n.BLIF N_131 -11 1 -.names a_c_22__n.BLIF a_c_23__n.BLIF N_171_2 -11 1 -.names clk_cpu_est_11_0_1__n.BLIF clk_cpu_est_11_1__n -0 1 -.names AS_030_000_SYNC_i.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_1 -11 1 -.names cpu_est_3_reg.BLIF state_machine_un13_clk_000_d0_2_n.BLIF N_126 -11 1 -.names RW_c.BLIF SM_AMIGA_6_.BLIF UDS_000_INT_0_sqmuxa_1_2 -11 1 -.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_124 -11 1 -.names UDS_000_INT_0_sqmuxa_1_1.BLIF UDS_000_INT_0_sqmuxa_1_2.BLIF \ -UDS_000_INT_0_sqmuxa_1_3 -11 1 -.names N_121.BLIF cpu_est_i_0__n.BLIF N_123 -11 1 -.names SM_AMIGA_4_.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_0 -11 1 -.names N_121_i.BLIF cpu_est_0_.BLIF N_125 -11 1 -.names CLK_000_D0_i.BLIF inst_CLK_OUT_PRE.BLIF N_96_1 -11 1 -.names N_91_0.BLIF N_91 -0 1 -.names a_c_17__n.BLIF a_i_16__n.BLIF state_machine_un42_clk_030_1_n -11 1 -.names CLK_000_D0_i.BLIF N_91.BLIF N_102 -11 1 -.names a_i_18__n.BLIF a_i_19__n.BLIF state_machine_un42_clk_030_2_n -11 1 -.names sm_amiga_i_3__n.BLIF sm_amiga_i_4__n.BLIF N_103 -11 1 -.names fc_c_1__n.BLIF BGACK_000_c.BLIF state_machine_un42_clk_030_3_n -11 1 -.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_101 -11 1 -.names state_machine_un42_clk_030_1_n.BLIF state_machine_un42_clk_030_2_n.BLIF \ -state_machine_un42_clk_030_4_n +.names CLK_030_c.BLIF N_57.BLIF N_79_1 11 1 .names RW_c.BLIF RW_i 0 1 -.names state_machine_un42_clk_030_3_n.BLIF fc_c_0__n.BLIF \ -state_machine_un42_clk_030_5_n -11 1 -.names inst_AS_000_INTreg.BLIF AS_000_INT_i -0 1 -.names AMIGA_BUS_ENABLE_i.BLIF AS_030_i.BLIF AMIGA_BUS_ENABLE_i_m_1 -11 1 -.names dsack_c_1__n.BLIF dsack_i_1__n -0 1 -.names SM_AMIGA_3_.BLIF VMA_INT_i.BLIF VPA_SYNC_1_sqmuxa_1_0 -11 1 -.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n -0 1 -.names VPA_D_i.BLIF cpu_est_2_.BLIF VPA_SYNC_1_sqmuxa_2 -11 1 -.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n -0 1 -.names cpu_est_3_reg.BLIF cpu_est_i_0__n.BLIF VPA_SYNC_1_sqmuxa_3 -11 1 -.names inst_CLK_000_D0.BLIF CLK_000_D0_i -0 1 -.names cpu_est_i_1__n.BLIF state_machine_un2_clk_000_n.BLIF \ -VPA_SYNC_1_sqmuxa_4 -11 1 -.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n -0 1 -.names VPA_SYNC_1_sqmuxa_1_0.BLIF VPA_SYNC_1_sqmuxa_2.BLIF VPA_SYNC_1_sqmuxa_5 -11 1 -.names cpu_est_0_.BLIF cpu_est_i_0__n -0 1 -.names VPA_SYNC_1_sqmuxa_3.BLIF VPA_SYNC_1_sqmuxa_4.BLIF VPA_SYNC_1_sqmuxa_6 -11 1 -.names cpu_est_3_reg.BLIF cpu_est_i_3__n -0 1 -.names cpu_est_0_.BLIF cpu_est_i_3__n.BLIF N_127_1 -11 1 -.names cpu_est_2_.BLIF cpu_est_i_2__n -0 1 -.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_128_1 +.names SM_AMIGA_7_.BLIF nEXP_SPACE_c.BLIF N_79_2 11 1 .names inst_VPA_D.BLIF VPA_D_i 0 1 -.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_131_1 +.names DTACK_i.BLIF N_77_1.BLIF N_77_1_0 11 1 -.names cpu_est_1_.BLIF cpu_est_i_1__n +.names inst_CLK_000_D0.BLIF CLK_000_D0_i 0 1 -.names N_131_i.BLIF N_129_i.BLIF clk_cpu_est_11_0_1_3__n +.names N_77_1.BLIF VMA_INT_i.BLIF N_75_1 11 1 -.names DTACK_c.BLIF DTACK_i +.names cpu_est_0_.BLIF cpu_est_i_0__n 0 1 -.names CLK_000_D0_i.BLIF SM_AMIGA_3_.BLIF N_105_1 +.names VPA_D_i.BLIF cpu_est_2_.BLIF N_75_2 +11 1 +.names cpu_est_3_reg.BLIF cpu_est_i_3__n +0 1 +.names cpu_est_3_reg.BLIF cpu_est_i_0__n.BLIF N_75_3 11 1 .names inst_VMA_INTreg.BLIF VMA_INT_i 0 1 -.names DTACK_i.BLIF SM_AMIGA_3_.BLIF DTACK_SYNC_1_sqmuxa_1_0 +.names N_75_1.BLIF N_75_2.BLIF N_75_4 11 1 -.names state_machine_un13_clk_000_d0_2_n.BLIF \ -state_machine_un13_clk_000_d0_2_i_n +.names cpu_est_1_.BLIF cpu_est_i_1__n 0 1 -.names inst_VPA_D.BLIF state_machine_un2_clk_000_n.BLIF DTACK_SYNC_1_sqmuxa_2 +.names N_75_3.BLIF cpu_est_i_1__n.BLIF N_75_5 11 1 -.names inst_CLK_000_D1.BLIF CLK_000_D1_i +.names DTACK_c.BLIF DTACK_i 0 1 -.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF \ -state_machine_un8_clk_000_d0_1_n +.names N_55_i.BLIF N_59_i.BLIF N_73_1 11 1 -.names VPA_SYNC_1_sqmuxa.BLIF VPA_SYNC_1_sqmuxa_i +.names BG_030_c.BLIF BG_030_i 0 1 -.names CLK_000_D0_i.BLIF VPA_D_i.BLIF state_machine_un8_clk_000_d0_2_n -11 1 -.names AS_030_c.BLIF AS_030_i -0 1 -.names cpu_est_0_.BLIF cpu_est_2_.BLIF state_machine_un8_clk_000_d0_3_n -11 1 -.names N_95.BLIF N_95_i -0 1 -.names state_machine_un8_clk_000_d0_1_n.BLIF \ -state_machine_un8_clk_000_d0_2_n.BLIF state_machine_un8_clk_000_d0_4_n -11 1 -.names DTACK_SYNC_1_sqmuxa.BLIF DTACK_SYNC_1_sqmuxa_i -0 1 -.names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF \ -state_machine_un13_clk_000_d0_1_0_n -11 1 -.names N_96.BLIF N_96_i -0 1 -.names state_machine_un13_clk_000_d0_1_n.BLIF \ -state_machine_un13_clk_000_d0_2_n.BLIF state_machine_un13_clk_000_d0_2_0_n -11 1 -.names a_c_18__n.BLIF a_i_18__n -0 1 -.names clk_un4_clk_000_d1_n.BLIF cpu_est_0_1__un3_n -0 1 -.names a_c_16__n.BLIF a_i_16__n -0 1 -.names clk_cpu_est_11_1__n.BLIF clk_un4_clk_000_d1_n.BLIF cpu_est_0_1__un1_n -11 1 -.names a_c_19__n.BLIF a_i_19__n -0 1 -.names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n -11 1 -.names CLK_030_c.BLIF CLK_030_i -0 1 -.names clk_un4_clk_000_d1_n.BLIF cpu_est_0_3__un3_n -0 1 -.names state_machine_un42_clk_030_n.BLIF state_machine_un42_clk_030_i_n -0 1 -.names clk_cpu_est_11_3__n.BLIF clk_un4_clk_000_d1_n.BLIF cpu_est_0_3__un1_n -11 1 -.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n -0 1 -.names cpu_est_3_reg.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n -11 1 -.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n -0 1 -.names clk_un4_clk_000_d1_n.BLIF ipl_030_0_0__un3_n -0 1 -.names AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLE_i -0 1 -.names ipl_c_0__n.BLIF clk_un4_clk_000_d1_n.BLIF ipl_030_0_0__un1_n +.names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF N_73_2 11 1 .names nEXP_SPACE_c.BLIF nEXP_SPACE_i 0 1 -.names IPL_030DFFSH_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n +.names CLK_000_D0_i.BLIF N_146.BLIF N_72_1 11 1 -.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n +.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n 0 1 -.names clk_un4_clk_000_d1_n.BLIF ipl_030_0_1__un3_n -0 1 -.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n -0 1 -.names ipl_c_1__n.BLIF clk_un4_clk_000_d1_n.BLIF ipl_030_0_1__un1_n +.names VPA_D_i.BLIF cpu_est_2_.BLIF N_72_2 11 1 -.names DS_030_c.BLIF DS_030_i +.names inst_AS_000_INTreg.BLIF AS_000_INT_i 0 1 -.names IPL_030DFFSH_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n +.names N_140_i.BLIF N_85_i.BLIF sm_amiga_ns_0_1_0__n 11 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n 0 1 -.names clk_un4_clk_000_d1_n.BLIF ipl_030_0_2__un3_n -0 1 -.names UDS_000_INT_0_sqmuxa_1.BLIF UDS_000_INT_0_sqmuxa_1_i -0 1 -.names ipl_c_2__n.BLIF clk_un4_clk_000_d1_n.BLIF ipl_030_0_2__un1_n +.names N_178_i.BLIF N_125_i.BLIF clk_cpu_est_11_0_1_3__n 11 1 -.names UDS_000_INT_0_sqmuxa.BLIF UDS_000_INT_0_sqmuxa_i +.names cpu_est_2_.BLIF cpu_est_i_2__n 0 1 -.names IPL_030DFFSH_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n +.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_138_1 11 1 -.names state_machine_un13_clk_000_d0_1_n.BLIF \ -state_machine_un13_clk_000_d0_1_i_n +.names AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLE_i 0 1 -.names un1_as_030_4.BLIF uds_000_int_0_un3_n +.names AMIGA_BUS_ENABLE_i.BLIF AS_030_i.BLIF N_119_1 +11 1 +.names AS_030_c.BLIF AS_030_i +0 1 +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_118_1 +11 1 +.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n +0 1 +.names N_55.BLIF cpu_est_0_.BLIF N_117_1 +11 1 +.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +0 1 +.names CLK_000_D0_i.BLIF SM_AMIGA_3_.BLIF N_97_1 +11 1 +.names state_machine_un8_clk_000_d2_n.BLIF state_machine_un8_clk_000_d2_i_n +0 1 +.names a_i_0__n.BLIF size_c_0__n.BLIF N_81_1 +11 1 +.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n +0 1 +.names RW_c.BLIF state_machine_uds_000_int_5_0_m2_un3_n +0 1 +.names a_c_0__n.BLIF a_i_0__n +0 1 +.names SM_AMIGA_5_.BLIF RW_c.BLIF state_machine_uds_000_int_5_0_m2_un1_n +11 1 +.names size_c_1__n.BLIF size_i_1__n +0 1 +.names SM_AMIGA_4_.BLIF state_machine_uds_000_int_5_0_m2_un3_n.BLIF \ +state_machine_uds_000_int_5_0_m2_un0_n +11 1 +.names dsack_c_1__n.BLIF dsack_i_1__n +0 1 +.names N_163.BLIF vpa_sync_0_un3_n 0 1 .names clk_clk_cnt_n.BLIF clk_clk_cnt_i_n 0 1 -.names inst_UDS_000_INTreg.BLIF un1_as_030_4.BLIF uds_000_int_0_un1_n +.names N_75_i.BLIF N_163.BLIF vpa_sync_0_un1_n 11 1 .names CLK_CNT_0_.BLIF clk_cnt_i_0__n 0 1 -.names state_machine_uds_000_int_7_n.BLIF uds_000_int_0_un3_n.BLIF \ -uds_000_int_0_un0_n +.names inst_VPA_SYNC.BLIF vpa_sync_0_un3_n.BLIF vpa_sync_0_un0_n 11 1 .names inst_CLK_000_D2.BLIF CLK_000_D2_i 0 1 -.names VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un3_n +.names RST_c.BLIF amiga_bus_enable_0_un3_n 0 1 +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +0 1 +.names N_43_i.BLIF RST_c.BLIF amiga_bus_enable_0_un1_n +11 1 .names a_c_30__n.BLIF a_i_30__n 0 1 -.names inst_VPA_SYNC.BLIF VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un1_n +.names AMIGA_BUS_ENABLEDFFreg.BLIF amiga_bus_enable_0_un3_n.BLIF \ +amiga_bus_enable_0_un0_n 11 1 .names a_c_31__n.BLIF a_i_31__n 0 1 -.names VPA_SYNC_1_sqmuxa_i.BLIF vpa_sync_0_un3_n.BLIF vpa_sync_0_un0_n -11 1 +.names N_162.BLIF uds_000_int_0_un3_n +0 1 .names a_c_28__n.BLIF a_i_28__n 0 1 -.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n -0 1 +.names state_machine_uds_000_int_5_n.BLIF N_162.BLIF uds_000_int_0_un1_n +11 1 .names a_c_29__n.BLIF a_i_29__n 0 1 -.names inst_AS_000_INTreg.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n +.names inst_UDS_000_INTreg.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n 11 1 .names a_c_26__n.BLIF a_i_26__n 0 1 -.names N_95_i.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n -11 1 +.names N_162.BLIF lds_000_int_0_un3_n +0 1 .names a_c_27__n.BLIF a_i_27__n 0 1 +.names state_machine_lds_000_int_5_n.BLIF N_162.BLIF lds_000_int_0_un1_n +11 1 +.names a_c_24__n.BLIF a_i_24__n +0 1 +.names inst_LDS_000_INTreg.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n +11 1 +.names a_c_25__n.BLIF a_i_25__n +0 1 +.names state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un3_n +0 1 +.names a_c_19__n.BLIF a_i_19__n +0 1 +.names cpu_est_1_.BLIF state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un1_n +11 1 +.names a_c_16__n.BLIF a_i_16__n +0 1 +.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n +11 1 +.names a_c_18__n.BLIF a_i_18__n +0 1 +.names N_69.BLIF bg_000_0_un3_n +0 1 +.names G_92.BLIF N_137_i +0 1 +.names BG_000DFFSHreg.BLIF N_69.BLIF bg_000_0_un1_n +11 1 +.names N_120_i.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n +11 1 +.names RST_c.BLIF RST_i +0 1 .names state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n 0 1 -.names a_c_24__n.BLIF a_i_24__n +.names N_120.BLIF N_120_i 0 1 .names BGACK_000_c.BLIF state_machine_un6_bgack_000_n.BLIF \ bgack_030_int_0_un1_n 11 1 -.names a_c_25__n.BLIF a_i_25__n +.names N_75.BLIF N_75_i 0 1 .names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \ bgack_030_int_0_un0_n 11 1 -.names G_86.BLIF N_132_i +.names N_74.BLIF N_74_i 0 1 -.names state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un3_n +.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n 0 1 -.names G_87.BLIF N_133_i +.names N_77.BLIF N_77_i 0 1 -.names N_121.BLIF state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un1_n +.names inst_AS_000_INTreg.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n 11 1 -.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n -11 1 -.names RST_c.BLIF RST_i -0 1 -.names clk_un4_clk_000_d1_n.BLIF cpu_est_0_2__un3_n -0 1 .names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i 0 1 -.names N_118_i.BLIF clk_un4_clk_000_d1_n.BLIF cpu_est_0_2__un1_n +.names sm_amiga_i_5__n.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n 11 1 .names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i 0 1 -.names cpu_est_2_.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n -11 1 -.names DSACK_INT_1_sqmuxa.BLIF dsack_int_0_1__un3_n +.names N_56.BLIF cpu_est_0_1__un3_n 0 1 -.names DSACK_INT_1_.BLIF DSACK_INT_1_sqmuxa.BLIF dsack_int_0_1__un1_n -11 1 -.names N_96_i.BLIF dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un0_n -11 1 -.names state_machine_un1_clk_030_n.BLIF bg_000_0_un3_n +.names inst_CLK_000_D5.BLIF CLK_000_D5_i 0 1 -.names un1_bg_030.BLIF state_machine_un1_clk_030_n.BLIF bg_000_0_un1_n +.names cpu_est_1_.BLIF N_56.BLIF cpu_est_0_1__un1_n 11 1 -.names BG_000DFFSHreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n +.names clk_cpu_est_11_1__n.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n 11 1 -.names RST_c.BLIF amiga_bus_enable_0_un3_n +.names N_56.BLIF cpu_est_0_2__un3_n 0 1 -.names state_machine_amiga_bus_enable_2_iv_i_n.BLIF RST_c.BLIF \ -amiga_bus_enable_0_un1_n +.names cpu_est_2_.BLIF N_56.BLIF cpu_est_0_2__un1_n 11 1 -.names AMIGA_BUS_ENABLEDFFreg.BLIF amiga_bus_enable_0_un3_n.BLIF \ -amiga_bus_enable_0_un0_n +.names N_123_i.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n 11 1 -.names state_machine_un17_clk_030_n.BLIF as_030_000_sync_0_un3_n +.names N_56.BLIF cpu_est_0_3__un3_n 0 1 -.names state_machine_as_030_000_sync_3_n.BLIF \ -state_machine_un17_clk_030_n.BLIF as_030_000_sync_0_un1_n +.names cpu_est_3_reg.BLIF N_56.BLIF cpu_est_0_3__un1_n +11 1 +.names clk_cpu_est_11_3__n.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n +11 1 +.names N_56.BLIF ipl_030_0_0__un3_n +0 1 +.names IPL_030DFFSH_0_reg.BLIF N_56.BLIF ipl_030_0_0__un1_n +11 1 +.names ipl_c_0__n.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n +11 1 +.names N_56.BLIF ipl_030_0_1__un3_n +0 1 +.names IPL_030DFFSH_1_reg.BLIF N_56.BLIF ipl_030_0_1__un1_n +11 1 +.names ipl_c_1__n.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n +11 1 +.names N_56.BLIF ipl_030_0_2__un3_n +0 1 +.names IPL_030DFFSH_2_reg.BLIF N_56.BLIF ipl_030_0_2__un1_n +11 1 +.names ipl_c_2__n.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n +11 1 +.names N_30.BLIF as_030_000_sync_0_un3_n +0 1 +.names un1_AMIGA_BUS_ENABLE_1_sqmuxa_2.BLIF N_30.BLIF as_030_000_sync_0_un1_n 11 1 .names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF \ as_030_000_sync_0_un0_n 11 1 -.names state_machine_un17_clk_030_n.BLIF fpu_cs_int_0_un3_n +.names N_165.BLIF dtack_sync_0_un3_n 0 1 -.names un1_as_030_3.BLIF state_machine_un17_clk_030_n.BLIF fpu_cs_int_0_un1_n +.names N_77_i.BLIF N_165.BLIF dtack_sync_0_un1_n +11 1 +.names inst_DTACK_SYNC.BLIF dtack_sync_0_un3_n.BLIF dtack_sync_0_un0_n +11 1 +.names N_164.BLIF fpu_cs_int_0_un3_n +0 1 +.names AS_030_c.BLIF N_164.BLIF fpu_cs_int_0_un1_n 11 1 .names inst_FPU_CS_INTreg.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un0_n 11 1 -.names DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un3_n +.names N_52.BLIF dsack_int_0_1__un3_n 0 1 -.names inst_DTACK_SYNC.BLIF DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un1_n +.names N_74_i.BLIF N_52.BLIF dsack_int_0_1__un1_n 11 1 -.names DTACK_SYNC_1_sqmuxa_i.BLIF dtack_sync_0_un3_n.BLIF dtack_sync_0_un0_n -11 1 -.names un1_as_030_4.BLIF lds_000_int_0_un3_n -0 1 -.names inst_LDS_000_INTreg.BLIF un1_as_030_4.BLIF lds_000_int_0_un1_n -11 1 -.names state_machine_lds_000_int_7_n.BLIF lds_000_int_0_un3_n.BLIF \ -lds_000_int_0_un0_n +.names DSACK_INT_1_.BLIF dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un0_n 11 1 .names inst_CLK_OUT_PRE.BLIF clk_clk_cnt_n.BLIF CLK_OUT_PRE_0 01 1 10 1 11 0 00 0 -.names cpu_est_0_.BLIF clk_un4_clk_000_d1_n.BLIF cpu_est_0_0_ +.names CLK_REF_1_.BLIF CLK_CNT_1_.BLIF G_92 01 1 10 1 11 0 00 0 -.names CLK_REF_0_.BLIF CLK_CNT_0_.BLIF G_86 -01 1 -10 1 -11 0 -00 0 -.names CLK_REF_1_.BLIF CLK_CNT_1_.BLIF G_87 -01 1 -10 1 -11 0 -00 0 -.names CLK_CNT_0_.BLIF CLK_CNT_1_.BLIF G_91 +.names CLK_CNT_0_.BLIF CLK_CNT_1_.BLIF G_96 01 1 10 1 11 0 @@ -1062,7 +989,7 @@ lds_000_int_0_un0_n .names vcc_n_n.BLIF AMIGA_BUS_ENABLE_LOW 1 1 0 0 -.names N_171.BLIF CIIN +.names N_191.BLIF CIIN 1 1 0 0 .names IPL_030DFFSH_1_reg.BLIF IPL_030_1_ @@ -1071,6 +998,30 @@ lds_000_int_0_un0_n .names IPL_030DFFSH_0_reg.BLIF IPL_030_0_ 1 1 0 0 +.names CLK_OSZI_c.BLIF IPL_030DFFSH_0_reg.C +1 1 +0 0 +.names RST_i.BLIF IPL_030DFFSH_0_reg.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF IPL_030DFFSH_1_reg.C +1 1 +0 0 +.names RST_i.BLIF IPL_030DFFSH_1_reg.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF IPL_030DFFSH_2_reg.C +1 1 +0 0 +.names RST_i.BLIF IPL_030DFFSH_2_reg.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_7_.C +1 1 +0 0 +.names RST_i.BLIF SM_AMIGA_7_.AP +1 1 +0 0 .names CLK_OSZI_c.BLIF SM_AMIGA_6_.C 1 1 0 0 @@ -1113,6 +1064,15 @@ lds_000_int_0_un0_n .names RST_i.BLIF SM_AMIGA_0_.AR 1 1 0 0 +.names CLK_OSZI_c.BLIF CLK_CNT_0_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_CNT_1_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF cpu_est_0_.C +1 1 +0 0 .names CLK_OSZI_c.BLIF cpu_est_1_.C 1 1 0 0 @@ -1122,99 +1082,6 @@ lds_000_int_0_un0_n .names CLK_OSZI_c.BLIF cpu_est_3_reg.C 1 1 0 0 -.names CLK_OSZI_c.BLIF IPL_030DFFSH_0_reg.C -1 1 -0 0 -.names RST_i.BLIF IPL_030DFFSH_0_reg.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF IPL_030DFFSH_1_reg.C -1 1 -0 0 -.names RST_i.BLIF IPL_030DFFSH_1_reg.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF IPL_030DFFSH_2_reg.C -1 1 -0 0 -.names RST_i.BLIF IPL_030DFFSH_2_reg.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_7_.C -1 1 -0 0 -.names RST_i.BLIF SM_AMIGA_7_.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C -1 1 -0 0 -.names RST_i.BLIF inst_VMA_INTreg.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C -1 1 -0 0 -.names RST_i.BLIF inst_BGACK_030_INTreg.AP -1 1 -0 0 -.names CLK_OUT_PRE_0.BLIF inst_CLK_OUT_PRE.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_CNT_0_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_CNT_1_.C -1 1 -0 0 -.names cpu_est_0_0_.BLIF cpu_est_0_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF cpu_est_0_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_VPA_SYNC.C -1 1 -0 0 -.names RST_i.BLIF inst_VPA_SYNC.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_FPU_CS_INTreg.C -1 1 -0 0 -.names RST_i.BLIF inst_FPU_CS_INTreg.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C -1 1 -0 0 -.names RST_i.BLIF inst_AS_030_000_SYNC.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_AS_000_INTreg.C -1 1 -0 0 -.names RST_i.BLIF inst_AS_000_INTreg.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF AMIGA_BUS_ENABLEDFFreg.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C -1 1 -0 0 -.names RST_i.BLIF BG_000DFFSHreg.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF DSACK_INT_1_.C -1 1 -0 0 -.names RST_i.BLIF DSACK_INT_1_.AP -1 1 -0 0 .names CLK_OSZI_c.BLIF inst_UDS_000_INTreg.C 1 1 0 0 @@ -1227,16 +1094,73 @@ lds_000_int_0_un0_n .names RST_i.BLIF inst_LDS_000_INTreg.AP 1 1 0 0 +.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C +1 1 +0 0 +.names RST_i.BLIF inst_VMA_INTreg.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C +1 1 +0 0 +.names RST_i.BLIF BG_000DFFSHreg.AP +1 1 +0 0 +.names CLK_OUT_PRE_0.BLIF inst_CLK_OUT_PRE.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C +1 1 +0 0 +.names RST_i.BLIF inst_BGACK_030_INTreg.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AS_000_INTreg.C +1 1 +0 0 +.names RST_i.BLIF inst_AS_000_INTreg.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C +1 1 +0 0 +.names RST_i.BLIF inst_AS_030_000_SYNC.AP +1 1 +0 0 .names CLK_OSZI_c.BLIF inst_DTACK_SYNC.C 1 1 0 0 .names RST_i.BLIF inst_DTACK_SYNC.AP 1 1 0 0 -.names inst_CLK_OUT_PRE.BLIF CLK_OUT_INTreg.D +.names CLK_OSZI_c.BLIF inst_FPU_CS_INTreg.C 1 1 0 0 -.names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C +.names RST_i.BLIF inst_FPU_CS_INTreg.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF DSACK_INT_1_.C +1 1 +0 0 +.names RST_i.BLIF DSACK_INT_1_.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_VPA_SYNC.C +1 1 +0 0 +.names RST_i.BLIF inst_VPA_SYNC.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF AMIGA_BUS_ENABLEDFFreg.C +1 1 +0 0 +.names inst_CLK_000_D4.BLIF inst_CLK_000_D5.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_CLK_000_D5.C 1 1 0 0 .names CLK_OSZI_c.BLIF inst_DTACK_DMA.C @@ -1245,19 +1169,37 @@ lds_000_int_0_un0_n .names RST_i.BLIF inst_DTACK_DMA.AP 1 1 0 0 +.names inst_CLK_OUT_PRE.BLIF CLK_OUT_INTreg.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C +1 1 +0 0 +.names inst_CLK_000_D3.BLIF inst_CLK_000_D4.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_CLK_000_D4.C +1 1 +0 0 .names inst_CLK_000_D1.BLIF inst_CLK_000_D2.D 1 1 0 0 .names CLK_OSZI_c.BLIF inst_CLK_000_D2.C 1 1 0 0 +.names inst_CLK_000_D2.BLIF inst_CLK_000_D3.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_CLK_000_D3.C +1 1 +0 0 .names VPA.BLIF inst_VPA_D.D 1 1 0 0 .names CLK_OSZI_c.BLIF inst_VPA_D.C 1 1 0 0 -.names CLK_000_c.BLIF inst_CLK_000_D0.D +.names CLK_000.BLIF inst_CLK_000_D0.D 1 1 0 0 .names CLK_OSZI_c.BLIF inst_CLK_000_D0.C @@ -1275,15 +1217,6 @@ lds_000_int_0_un0_n .names CLK_OSZI_c.BLIF inst_CLK_000_D1.C 1 1 0 0 -.names gnd_n_n.BLIF CLK_REF_0_.D -1 1 -0 0 -.names gnd_n_n.BLIF CLK_REF_0_.LH -1 1 -0 0 -.names RST_i.BLIF CLK_REF_0_.AP -1 1 -0 0 .names gnd_n_n.BLIF CLK_REF_1_.D 1 1 0 0 @@ -1308,9 +1241,6 @@ lds_000_int_0_un0_n .names CLK_030.BLIF CLK_030_c 1 1 0 0 -.names CLK_000.BLIF CLK_000_c -1 1 -0 0 .names CLK_OSZI.BLIF CLK_OSZI_c 1 1 0 0 @@ -1356,96 +1286,96 @@ lds_000_int_0_un0_n .names A_0_.BLIF a_c_0__n 1 1 0 0 -.names A_15_.BLIF a_15__n -1 1 -0 0 -.names A_14_.BLIF a_14__n -1 1 -0 0 -.names A_13_.BLIF a_13__n -1 1 -0 0 -.names A_12_.BLIF a_12__n -1 1 -0 0 .names A_16_.BLIF a_c_16__n 1 1 0 0 -.names A_11_.BLIF a_11__n +.names A_15_.BLIF a_15__n 1 1 0 0 .names A_17_.BLIF a_c_17__n 1 1 0 0 -.names A_10_.BLIF a_10__n +.names A_14_.BLIF a_14__n 1 1 0 0 .names A_18_.BLIF a_c_18__n 1 1 0 0 -.names A_9_.BLIF a_9__n +.names A_13_.BLIF a_13__n 1 1 0 0 .names A_19_.BLIF a_c_19__n 1 1 0 0 -.names A_8_.BLIF a_8__n +.names A_12_.BLIF a_12__n 1 1 0 0 .names A_20_.BLIF a_c_20__n 1 1 0 0 -.names A_7_.BLIF a_7__n +.names A_11_.BLIF a_11__n 1 1 0 0 .names A_21_.BLIF a_c_21__n 1 1 0 0 -.names A_6_.BLIF a_6__n +.names A_10_.BLIF a_10__n 1 1 0 0 .names A_22_.BLIF a_c_22__n 1 1 0 0 -.names A_5_.BLIF a_5__n +.names A_9_.BLIF a_9__n 1 1 0 0 .names A_23_.BLIF a_c_23__n 1 1 0 0 -.names A_4_.BLIF a_4__n +.names A_8_.BLIF a_8__n 1 1 0 0 .names A_24_.BLIF a_c_24__n 1 1 0 0 -.names A_3_.BLIF a_3__n +.names A_7_.BLIF a_7__n 1 1 0 0 .names A_25_.BLIF a_c_25__n 1 1 0 0 -.names A_2_.BLIF a_2__n +.names A_6_.BLIF a_6__n 1 1 0 0 .names A_26_.BLIF a_c_26__n 1 1 0 0 -.names A_1_.BLIF a_1__n +.names A_5_.BLIF a_5__n 1 1 0 0 .names A_27_.BLIF a_c_27__n 1 1 0 0 +.names A_4_.BLIF a_4__n +1 1 +0 0 .names A_28_.BLIF a_c_28__n 1 1 0 0 +.names A_3_.BLIF a_3__n +1 1 +0 0 .names A_29_.BLIF a_c_29__n 1 1 0 0 +.names A_2_.BLIF a_2__n +1 1 +0 0 .names A_30_.BLIF a_c_30__n 1 1 0 0 +.names A_1_.BLIF a_1__n +1 1 +0 0 .names A_31_.BLIF a_c_31__n 1 1 0 0 @@ -1479,7 +1409,7 @@ lds_000_int_0_un0_n .names FPU_CS_INT_i.BLIF AVEC_EXP.OE 1 1 0 0 -.names N_168.BLIF CIIN.OE +.names N_188.BLIF CIIN.OE 1 1 0 0 .end diff --git a/Logic/68030_tk.bl3 b/Logic/68030_tk.bl3 index cba30fb..e3eb963 100644 --- a/Logic/68030_tk.bl3 +++ b/Logic/68030_tk.bl3 @@ -1,93 +1,129 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Thu May 22 14:56:10 2014 +#$ DATE Sat May 24 11:44:09 2014 #$ MODULE 68030_tk #$ PINS 59 SIZE_1_ A_31_ IPL_030_2_ IPL_2_ DSACK_1_ FC_1_ AS_030 AS_000 DS_030 UDS_000 \ -# LDS_000 nEXP_SPACE BERR SIZE_0_ BG_030 A_30_ BG_000 A_29_ BGACK_030 A_28_ BGACK_000 A_27_ \ -# CLK_030 A_26_ CLK_000 A_25_ CLK_OSZI A_24_ CLK_DIV_OUT A_23_ CLK_EXP A_22_ FPU_CS A_21_ \ -# DTACK A_20_ AVEC A_19_ AVEC_EXP A_18_ E A_17_ VPA A_16_ VMA RST RESET RW AMIGA_BUS_ENABLE \ -# AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ IPL_0_ \ -# DSACK_0_ FC_0_ -#$ NODES 39 BG_000DFFSHreg inst_BGACK_030_INTreg inst_FPU_CS_INTreg cpu_est_3_reg \ -# inst_VMA_INTreg cpu_est_0_ cpu_est_1_ CLK_OUT_INTreg inst_AS_000_INTreg \ -# inst_AS_030_000_SYNC inst_DTACK_SYNC IPL_030DFFSH_0_reg inst_VPA_D inst_VPA_SYNC \ -# IPL_030DFFSH_1_reg inst_CLK_000_D0 inst_CLK_000_D1 IPL_030DFFSH_2_reg \ -# inst_CLK_000_D2 inst_CLK_OUT_PRE SM_AMIGA_6_ cpu_est_2_ CLK_REF_0_ CLK_REF_1_ \ -# SM_AMIGA_7_ inst_UDS_000_INTreg inst_LDS_000_INTreg DSACK_INT_1_ SM_AMIGA_4_ \ -# SM_AMIGA_1_ inst_DTACK_DMA CLK_CNT_0_ CLK_CNT_1_ SM_AMIGA_3_ RESETDFFreg SM_AMIGA_5_ \ -# SM_AMIGA_2_ SM_AMIGA_0_ AMIGA_BUS_ENABLEDFFreg +# LDS_000 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 SIZE_0_ \ +# CLK_OSZI A_30_ CLK_DIV_OUT A_29_ CLK_EXP A_28_ FPU_CS A_27_ DTACK A_26_ AVEC A_25_ \ +# AVEC_EXP A_24_ E A_23_ VPA A_22_ VMA A_21_ RST A_20_ RESET A_19_ RW A_18_ AMIGA_BUS_ENABLE \ +# A_17_ AMIGA_BUS_DATA_DIR A_16_ AMIGA_BUS_ENABLE_LOW CIIN A_0_ IPL_030_1_ IPL_030_0_ \ +# IPL_1_ IPL_0_ DSACK_0_ FC_0_ +#$ NODES 41 inst_BGACK_030_INTreg inst_FPU_CS_INTreg cpu_est_3_reg \ +# inst_VMA_INTreg cpu_est_0_ CLK_OUT_INTreg cpu_est_1_ inst_AS_000_INTreg \ +# inst_AS_030_000_SYNC IPL_030DFFSH_0_reg inst_DTACK_SYNC inst_VPA_D \ +# IPL_030DFFSH_1_reg inst_VPA_SYNC inst_CLK_000_D0 IPL_030DFFSH_2_reg \ +# inst_CLK_000_D1 inst_CLK_000_D2 inst_CLK_000_D5 inst_CLK_OUT_PRE SM_AMIGA_6_ \ +# SM_AMIGA_5_ cpu_est_2_ CLK_REF_1_ inst_UDS_000_INTreg inst_LDS_000_INTreg \ +# DSACK_INT_1_ SM_AMIGA_7_ inst_CLK_000_D3 SM_AMIGA_4_ inst_CLK_000_D4 RESETDFFreg \ +# inst_DTACK_DMA CLK_CNT_0_ CLK_CNT_1_ SM_AMIGA_3_ SM_AMIGA_1_ SM_AMIGA_2_ \ +# AMIGA_BUS_ENABLEDFFreg SM_AMIGA_0_ BG_000DFFSHreg .model bus68030 .inputs SIZE_1_.BLIF A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF AS_030.BLIF DS_030.BLIF \ nEXP_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF \ CLK_OSZI.BLIF VPA.BLIF RST.BLIF RW.BLIF SIZE_0_.BLIF A_30_.BLIF A_29_.BLIF \ A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF \ A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF A_0_.BLIF \ -IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF BG_000DFFSHreg.BLIF \ -inst_BGACK_030_INTreg.BLIF inst_FPU_CS_INTreg.BLIF cpu_est_3_reg.BLIF \ -inst_VMA_INTreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF CLK_OUT_INTreg.BLIF \ -inst_AS_000_INTreg.BLIF inst_AS_030_000_SYNC.BLIF inst_DTACK_SYNC.BLIF \ -IPL_030DFFSH_0_reg.BLIF inst_VPA_D.BLIF inst_VPA_SYNC.BLIF \ -IPL_030DFFSH_1_reg.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF \ -IPL_030DFFSH_2_reg.BLIF inst_CLK_000_D2.BLIF inst_CLK_OUT_PRE.BLIF \ -SM_AMIGA_6_.BLIF cpu_est_2_.BLIF CLK_REF_0_.BLIF CLK_REF_1_.BLIF \ -SM_AMIGA_7_.BLIF inst_UDS_000_INTreg.BLIF inst_LDS_000_INTreg.BLIF \ -DSACK_INT_1_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_1_.BLIF inst_DTACK_DMA.BLIF \ -CLK_CNT_0_.BLIF CLK_CNT_1_.BLIF SM_AMIGA_3_.BLIF RESETDFFreg.BLIF \ -SM_AMIGA_5_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_0_.BLIF AMIGA_BUS_ENABLEDFFreg.BLIF \ -DSACK_1_.PIN.BLIF DTACK.PIN.BLIF +IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF inst_BGACK_030_INTreg.BLIF \ +inst_FPU_CS_INTreg.BLIF cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF \ +cpu_est_0_.BLIF CLK_OUT_INTreg.BLIF cpu_est_1_.BLIF inst_AS_000_INTreg.BLIF \ +inst_AS_030_000_SYNC.BLIF IPL_030DFFSH_0_reg.BLIF inst_DTACK_SYNC.BLIF \ +inst_VPA_D.BLIF IPL_030DFFSH_1_reg.BLIF inst_VPA_SYNC.BLIF \ +inst_CLK_000_D0.BLIF IPL_030DFFSH_2_reg.BLIF inst_CLK_000_D1.BLIF \ +inst_CLK_000_D2.BLIF inst_CLK_000_D5.BLIF inst_CLK_OUT_PRE.BLIF \ +SM_AMIGA_6_.BLIF SM_AMIGA_5_.BLIF cpu_est_2_.BLIF CLK_REF_1_.BLIF \ +inst_UDS_000_INTreg.BLIF inst_LDS_000_INTreg.BLIF DSACK_INT_1_.BLIF \ +SM_AMIGA_7_.BLIF inst_CLK_000_D3.BLIF SM_AMIGA_4_.BLIF inst_CLK_000_D4.BLIF \ +RESETDFFreg.BLIF inst_DTACK_DMA.BLIF CLK_CNT_0_.BLIF CLK_CNT_1_.BLIF \ +SM_AMIGA_3_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_2_.BLIF AMIGA_BUS_ENABLEDFFreg.BLIF \ +SM_AMIGA_0_.BLIF BG_000DFFSHreg.BLIF DSACK_1_.PIN.BLIF DTACK.PIN.BLIF .outputs IPL_030_2_ AS_000 UDS_000 LDS_000 BERR BG_000 BGACK_030 CLK_DIV_OUT \ CLK_EXP FPU_CS AVEC AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR \ -AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_6_.D SM_AMIGA_6_.C \ -SM_AMIGA_6_.AR SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D \ -SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR \ -SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C \ -SM_AMIGA_1_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR cpu_est_1_.D \ -cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_reg.C IPL_030DFFSH_0_reg.D \ +AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ IPL_030DFFSH_0_reg.D \ IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP IPL_030DFFSH_1_reg.D \ IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D \ IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D SM_AMIGA_7_.C \ -SM_AMIGA_7_.AP inst_VMA_INTreg.C inst_VMA_INTreg.AP inst_BGACK_030_INTreg.D \ -inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP inst_CLK_OUT_PRE.C \ -CLK_CNT_0_.D CLK_CNT_0_.C CLK_CNT_1_.D CLK_CNT_1_.C cpu_est_0_.D cpu_est_0_.C \ -inst_VPA_SYNC.D inst_VPA_SYNC.C inst_VPA_SYNC.AP inst_FPU_CS_INTreg.D \ -inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP inst_AS_030_000_SYNC.D \ -inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_AS_000_INTreg.D \ -inst_AS_000_INTreg.C inst_AS_000_INTreg.AP AMIGA_BUS_ENABLEDFFreg.D \ -AMIGA_BUS_ENABLEDFFreg.C BG_000DFFSHreg.D BG_000DFFSHreg.C BG_000DFFSHreg.AP \ -DSACK_INT_1_.D DSACK_INT_1_.C DSACK_INT_1_.AP inst_UDS_000_INTreg.D \ -inst_UDS_000_INTreg.C inst_UDS_000_INTreg.AP inst_LDS_000_INTreg.D \ -inst_LDS_000_INTreg.C inst_LDS_000_INTreg.AP inst_DTACK_SYNC.D \ -inst_DTACK_SYNC.C inst_DTACK_SYNC.AP CLK_OUT_INTreg.D CLK_OUT_INTreg.C \ -inst_DTACK_DMA.D inst_DTACK_DMA.C inst_DTACK_DMA.AP inst_CLK_000_D2.D \ -inst_CLK_000_D2.C inst_VPA_D.D inst_VPA_D.C inst_CLK_000_D0.D \ -inst_CLK_000_D0.C RESETDFFreg.D RESETDFFreg.C inst_CLK_000_D1.D \ -inst_CLK_000_D1.C CLK_REF_0_.D CLK_REF_0_.LH CLK_REF_0_.AP CLK_REF_1_.D \ -CLK_REF_1_.LH CLK_REF_1_.AR DSACK_1_ DTACK DSACK_0_ DSACK_1_.OE DTACK.OE \ -AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE \ -cpu_est_3_reg.D.X1 cpu_est_3_reg.D.X2 inst_VMA_INTreg.D.X1 \ -inst_VMA_INTreg.D.X2 inst_CLK_OUT_PRE.D.X1 inst_CLK_OUT_PRE.D.X2 -.names inst_AS_030_000_SYNC.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF \ -inst_CLK_000_D2.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_7_.BLIF SM_AMIGA_6_.D ----11- 1 ---0-1- 1 -1---1- 1 --0---1 1 -0110-- 0 -0-10-0 0 --1--0- 0 -----00 0 -.names inst_AS_030_000_SYNC.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF \ -inst_CLK_000_D2.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_5_.D -0-101- 1 --1---1 1 --0--0- 0 --0-1-- 0 --00--- 0 -10---- 0 -----00 0 ----1-0 0 ---0--0 0 -1----0 0 -.names inst_CLK_000_D0.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_4_.D +SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.D \ +SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_4_.AR \ +SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C \ +SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.D \ +SM_AMIGA_0_.C SM_AMIGA_0_.AR CLK_CNT_0_.D CLK_CNT_0_.C CLK_CNT_1_.D \ +CLK_CNT_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D \ +cpu_est_2_.C cpu_est_3_reg.C inst_UDS_000_INTreg.D inst_UDS_000_INTreg.C \ +inst_UDS_000_INTreg.AP inst_LDS_000_INTreg.D inst_LDS_000_INTreg.C \ +inst_LDS_000_INTreg.AP inst_VMA_INTreg.C inst_VMA_INTreg.AP BG_000DFFSHreg.D \ +BG_000DFFSHreg.C BG_000DFFSHreg.AP inst_CLK_OUT_PRE.C inst_BGACK_030_INTreg.D \ +inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP inst_AS_000_INTreg.D \ +inst_AS_000_INTreg.C inst_AS_000_INTreg.AP inst_AS_030_000_SYNC.D \ +inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_DTACK_SYNC.D \ +inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_FPU_CS_INTreg.D inst_FPU_CS_INTreg.C \ +inst_FPU_CS_INTreg.AP DSACK_INT_1_.D DSACK_INT_1_.C DSACK_INT_1_.AP \ +inst_VPA_SYNC.D inst_VPA_SYNC.C inst_VPA_SYNC.AP AMIGA_BUS_ENABLEDFFreg.D \ +AMIGA_BUS_ENABLEDFFreg.C inst_CLK_000_D5.D inst_CLK_000_D5.C inst_DTACK_DMA.D \ +inst_DTACK_DMA.C inst_DTACK_DMA.AP CLK_OUT_INTreg.D CLK_OUT_INTreg.C \ +inst_CLK_000_D4.D inst_CLK_000_D4.C inst_CLK_000_D2.D inst_CLK_000_D2.C \ +inst_CLK_000_D3.D inst_CLK_000_D3.C inst_VPA_D.D inst_VPA_D.C \ +inst_CLK_000_D0.D inst_CLK_000_D0.C RESETDFFreg.D RESETDFFreg.C \ +inst_CLK_000_D1.D inst_CLK_000_D1.C CLK_REF_1_.D CLK_REF_1_.LH CLK_REF_1_.AR \ +DSACK_1_ DTACK DSACK_0_ DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE \ +BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE cpu_est_3_reg.D.X1 cpu_est_3_reg.D.X2 \ +inst_VMA_INTreg.D.X1 inst_VMA_INTreg.D.X2 inst_CLK_OUT_PRE.D.X1 \ +inst_CLK_OUT_PRE.D.X2 +.names IPL_0_.BLIF IPL_030DFFSH_0_reg.BLIF inst_CLK_000_D0.BLIF \ +inst_CLK_000_D1.BLIF IPL_030DFFSH_0_reg.D +1-10 1 +-10- 1 +-1-1 1 +0-10 0 +-00- 0 +-0-1 0 +.names IPL_1_.BLIF IPL_030DFFSH_1_reg.BLIF inst_CLK_000_D0.BLIF \ +inst_CLK_000_D1.BLIF IPL_030DFFSH_1_reg.D +1-10 1 +-10- 1 +-1-1 1 +0-10 0 +-00- 0 +-0-1 0 +.names IPL_2_.BLIF inst_CLK_000_D0.BLIF IPL_030DFFSH_2_reg.BLIF \ +inst_CLK_000_D1.BLIF IPL_030DFFSH_2_reg.D +11-0 1 +-01- 1 +--11 1 +01-0 0 +-00- 0 +--01 0 +.names nEXP_SPACE.BLIF inst_AS_000_INTreg.BLIF inst_AS_030_000_SYNC.BLIF \ +inst_CLK_000_D0.BLIF inst_CLK_000_D2.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_7_.BLIF \ +inst_CLK_000_D3.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_7_.D +0--0-1--- 1 +-1-1----1 1 +------10- 1 +----1-1-- 1 +--1---1-- 1 +-0010--1- 0 +--0000-1- 0 +1-000--1- 0 +--010--10 0 +-0-1--0-- 0 +---0-00-- 0 +1--0--0-- 0 +---1--0-0 0 +.names nEXP_SPACE.BLIF inst_AS_030_000_SYNC.BLIF inst_CLK_000_D0.BLIF \ +inst_CLK_000_D2.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_7_.BLIF inst_CLK_000_D3.BLIF \ +SM_AMIGA_6_.D +-0-0-11 1 +1-0-10- 1 +---1-1- 0 +-1---1- 0 +----00- 0 +--1--0- 0 +0----0- 0 +-----10 0 +.names inst_CLK_000_D0.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_5_.D +11- 1 +1-1 1 +-00 0 +0-- 0 +.names inst_CLK_000_D0.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_4_.D 01- 1 0-1 1 -00 0 @@ -109,23 +145,44 @@ SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_2_.D 11--0 0 --1-- 0 ---00 0 -.names inst_CLK_000_D0.BLIF inst_CLK_OUT_PRE.BLIF SM_AMIGA_1_.BLIF \ -SM_AMIGA_2_.BLIF SM_AMIGA_1_.D --010 1 -1-1- 1 -1--1 1 -01-- 0 ---00 0 -0--1 0 -.names inst_AS_000_INTreg.BLIF inst_CLK_000_D0.BLIF inst_CLK_OUT_PRE.BLIF \ -SM_AMIGA_1_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_0_.D +.names inst_CLK_000_D0.BLIF inst_CLK_000_D5.BLIF inst_CLK_000_D4.BLIF \ +SM_AMIGA_1_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_1_.D -011- 1 -0---1 1 --0--1 1 -11--- 0 +1--1- 1 +1---1 1 +0-0-- 0 +01--- 0 +0--0- 0 ---00 0 ---0-0 0 --1--0 0 +.names inst_AS_000_INTreg.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D5.BLIF \ +inst_CLK_000_D4.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_0_.D +-0-01- 1 +-01-1- 1 +0----1 1 +-0---1 1 +11---- 0 +--01-0 0 +----00 0 +-1---0 0 +.names CLK_REF_1_.BLIF CLK_CNT_0_.BLIF CLK_CNT_1_.BLIF CLK_CNT_0_.D +100 1 +001 1 +0-0 0 +1-1 0 +-1- 0 +.names CLK_REF_1_.BLIF CLK_CNT_0_.BLIF CLK_CNT_1_.BLIF CLK_CNT_1_.D +001 1 +-10 1 +1-1 0 +-00 0 +-11 0 +.names cpu_est_0_.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF cpu_est_0_.D +010 1 +10- 1 +1-1 1 +110 0 +00- 0 +0-1 0 .names cpu_est_3_reg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_CLK_000_D0.BLIF \ inst_CLK_000_D1.BLIF cpu_est_2_.BLIF cpu_est_1_.D 0--100 1 @@ -153,37 +210,50 @@ inst_CLK_000_D1.BLIF cpu_est_2_.BLIF cpu_est_2_.D -01--0 0 ----10 0 ---0-0 0 -.names IPL_0_.BLIF IPL_030DFFSH_0_reg.BLIF inst_CLK_000_D0.BLIF \ -inst_CLK_000_D1.BLIF IPL_030DFFSH_0_reg.D -1-10 1 --10- 1 --1-1 1 -0-10 0 --00- 0 --0-1 0 -.names IPL_1_.BLIF IPL_030DFFSH_1_reg.BLIF inst_CLK_000_D0.BLIF \ -inst_CLK_000_D1.BLIF IPL_030DFFSH_1_reg.D -1-10 1 --10- 1 --1-1 1 -0-10 0 --00- 0 --0-1 0 -.names IPL_2_.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF \ -IPL_030DFFSH_2_reg.BLIF IPL_030DFFSH_2_reg.D -110- 1 ---11 1 --0-1 1 -010- 0 ---10 0 --0-0 0 -.names inst_AS_000_INTreg.BLIF inst_CLK_000_D0.BLIF SM_AMIGA_7_.BLIF \ -SM_AMIGA_0_.BLIF SM_AMIGA_7_.D --11- 1 -11-1 1 -0-0- 0 ---00 0 --0-- 0 +.names AS_030.BLIF DS_030.BLIF RW.BLIF A_0_.BLIF SM_AMIGA_5_.BLIF \ +inst_UDS_000_INTreg.BLIF SM_AMIGA_4_.BLIF inst_UDS_000_INTreg.D +-0111-- 1 +--1-01- 1 +-001--1 1 +--0--10 1 +-1---1- 1 +1-1-0-- 1 +1-0---0 1 +11----- 1 +-0101-- 0 +0-1-00- 0 +-000--1 0 +0-0--00 0 +01---0- 0 +.names SIZE_1_.BLIF AS_030.BLIF DS_030.BLIF RW.BLIF SIZE_0_.BLIF A_0_.BLIF \ +SM_AMIGA_5_.BLIF inst_LDS_000_INTreg.BLIF SM_AMIGA_4_.BLIF \ +inst_LDS_000_INTreg.D +0-01101-- 1 +0-0010--1 1 +---1--01- 1 +-1-1--0-- 1 +---0---10 1 +-1-0----0 1 +--1----1- 1 +-11------ 1 +-0-1--00- 0 +-01----0- 0 +--01-11-- 0 +--010-1-- 0 +1-01--1-- 0 +-0-0---00 0 +--00-1--1 0 +--000---1 0 +1-00----1 0 +.names AS_030.BLIF nEXP_SPACE.BLIF BG_030.BLIF CLK_030.BLIF SM_AMIGA_7_.BLIF \ +BG_000DFFSHreg.BLIF BG_000DFFSHreg.D +---1-1 1 +---00- 1 +-1-0-- 1 +0--0-- 1 +--1--- 1 +10001- 0 +--01-0 0 .names BGACK_000.BLIF inst_BGACK_030_INTreg.BLIF inst_CLK_000_D0.BLIF \ inst_CLK_000_D1.BLIF inst_BGACK_030_INTreg.D 1-10 1 @@ -191,89 +261,107 @@ inst_CLK_000_D1.BLIF inst_BGACK_030_INTreg.D -00- 0 0--- 0 -0-1 0 -.names CLK_REF_0_.BLIF CLK_REF_1_.BLIF CLK_CNT_0_.BLIF CLK_CNT_1_.BLIF \ -CLK_CNT_0_.D --100 1 --001 1 -1-0- 1 -00-0 0 -01-1 0 ---1- 0 -.names CLK_REF_0_.BLIF CLK_REF_1_.BLIF CLK_CNT_0_.BLIF CLK_CNT_1_.BLIF \ -CLK_CNT_1_.D --110 1 -0-10 1 --001 1 -1-01 1 -10-0 0 -010- 0 ---00 0 ---11 0 -.names AS_030.BLIF CLK_000.BLIF cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF \ -cpu_est_0_.BLIF cpu_est_1_.BLIF inst_VPA_D.BLIF inst_VPA_SYNC.BLIF \ -inst_CLK_000_D0.BLIF cpu_est_2_.BLIF SM_AMIGA_3_.BLIF inst_VPA_SYNC.D --------1-0- 1 --------10-- 1 -------11--- 1 ------1-1--- 1 -----1--1--- 1 ----1---1--- 1 ---0----1--- 1 --0-----1--- 1 --------1--0 1 -1--------0- 1 -1-------0-- 1 -1-----1---- 1 -1----1----- 1 -1---1------ 1 -1--1------- 1 -1-0-------- 1 -10--------- 1 -1---------0 1 --110000-111 0 -0------0--- 0 +.names AS_030.BLIF inst_AS_000_INTreg.BLIF SM_AMIGA_5_.BLIF \ +inst_AS_000_INTreg.D +-10 1 +1-0 1 +00- 0 +--1 0 +.names FC_1_.BLIF AS_030.BLIF nEXP_SPACE.BLIF BGACK_000.BLIF CLK_030.BLIF \ +A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF FC_0_.BLIF \ +inst_AS_030_000_SYNC.BLIF inst_CLK_000_D5.BLIF SM_AMIGA_6_.BLIF \ +SM_AMIGA_7_.BLIF inst_CLK_000_D4.BLIF SM_AMIGA_1_.BLIF inst_AS_030_000_SYNC.D +1--1-001011----- 1 +-----------0--11 1 +--0---------1--- 1 +----------1--0-- 1 +----0-----1----- 1 +--0-------1----- 1 +-1-------------- 1 +-0--------0-0-0- 0 +-0--------010--- 0 +-01-1----0---10- 0 +-01-1---1----10- 0 +-01-1--0-----10- 0 +-01-1-1------10- 0 +-01-11-------10- 0 +-0101--------10- 0 +001-1--------10- 0 +-01-1----0-1-1-- 0 +-01-1---1--1-1-- 0 +-01-1--0---1-1-- 0 +-01-1-1----1-1-- 0 +-01-11-----1-1-- 0 +-0101------1-1-- 0 +001-1------1-1-- 0 +-0--------0-0--0 0 +-01-1----0---1-0 0 +-01-1---1----1-0 0 +-01-1--0-----1-0 0 +-01-1-1------1-0 0 +-01-11-------1-0 0 +-0101--------1-0 0 +001-1--------1-0 0 +-01-------0---0- 0 +-01-------01---- 0 +-01-------0----0 0 +.names AS_030.BLIF inst_DTACK_SYNC.BLIF inst_VPA_D.BLIF inst_CLK_000_D0.BLIF \ +SM_AMIGA_3_.BLIF DTACK.PIN.BLIF inst_DTACK_SYNC.D +-1--0- 1 +-1-0-- 1 +-10--- 1 +-1---1 1 +1---0- 1 +1--0-- 1 +1-0--- 1 +1----1 1 +--1110 0 +00---- 0 .names FC_1_.BLIF AS_030.BLIF BGACK_000.BLIF CLK_030.BLIF A_19_.BLIF \ A_18_.BLIF A_17_.BLIF A_16_.BLIF FC_0_.BLIF inst_FPU_CS_INTreg.BLIF \ inst_FPU_CS_INTreg.D ----0-----1 1 ----1----0- 1 ----1---1-- 1 ----1--0--- 1 ----1-1---- 1 ----11----- 1 ---01------ 1 -0--1------ 1 -1-------- 1 +--------01 1 +-------1-1 1 +------0--1 1 +-----1---1 1 +----1----1 1 +---0-----1 1 +--0------1 1 +0--------1 1 101100101- 0 --0-0-----0 0 -.names FC_1_.BLIF AS_030.BLIF nEXP_SPACE.BLIF BGACK_000.BLIF CLK_030.BLIF \ -A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF FC_0_.BLIF \ -inst_AS_030_000_SYNC.BLIF inst_AS_030_000_SYNC.D -1--1100101- 1 -----0-----1 1 ---0-1------ 1 --1--------- 1 --01-1----0- 0 --01-1---1-- 0 --01-1--0--- 0 --01-1-1---- 0 --01-11----- 0 --0101------ 0 -001-1------ 0 --0--0-----0 0 -.names AS_030.BLIF inst_AS_000_INTreg.BLIF inst_AS_030_000_SYNC.BLIF \ -inst_CLK_000_D1.BLIF inst_CLK_000_D2.BLIF SM_AMIGA_6_.BLIF \ -inst_AS_000_INTreg.D --1--1- 1 --1-0-- 1 --11--- 1 --1---0 1 -1---1- 1 -1--0-- 1 -1-1--- 1 -1----0 1 ---0101 0 -00---- 0 +-0-------0 0 +.names AS_030.BLIF inst_CLK_000_D5.BLIF DSACK_INT_1_.BLIF inst_CLK_000_D4.BLIF \ +SM_AMIGA_1_.BLIF DSACK_INT_1_.D +--10- 1 +-11-- 1 +--1-0 1 +1--0- 1 +11--- 1 +1---0 1 +-0-11 0 +0-0-- 0 +.names AS_030.BLIF cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF \ +cpu_est_1_.BLIF inst_VPA_D.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D0.BLIF \ +cpu_est_2_.BLIF SM_AMIGA_3_.BLIF inst_VPA_SYNC.D +------1-0- 1 +------10-- 1 +-----11--- 1 +----1-1--- 1 +---1--1--- 1 +--1---1--- 1 +-0----1--- 1 +------1--0 1 +1-------0- 1 +1------0-- 1 +1----1---- 1 +1---1----- 1 +1--1------ 1 +1-1------- 1 +10-------- 1 +1--------0 1 +-10000-111 0 +0-----0--- 0 .names AS_030.BLIF nEXP_SPACE.BLIF RST.BLIF SM_AMIGA_6_.BLIF \ AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLEDFFreg.D 1-10- 1 @@ -283,95 +371,6 @@ AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLEDFFreg.D -111- 0 0--00 0 --0-0 0 -.names AS_030.BLIF nEXP_SPACE.BLIF BG_030.BLIF CLK_030.BLIF \ -BG_000DFFSHreg.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_7_.BLIF BG_000DFFSHreg.D ----11-- 1 ----0-00 1 --1-0--- 1 -0--0--- 1 ---1---- 1 -1000-1- 0 -1000--1 0 ---010-- 0 -.names AS_030.BLIF inst_CLK_000_D0.BLIF inst_CLK_OUT_PRE.BLIF \ -DSACK_INT_1_.BLIF SM_AMIGA_1_.BLIF DSACK_INT_1_.D ---01- 1 --1-1- 1 ----10 1 -1-0-- 1 -11--- 1 -1---0 1 --01-1 0 -0--0- 0 -.names AS_030.BLIF DS_030.BLIF RW.BLIF A_0_.BLIF inst_AS_030_000_SYNC.BLIF \ -inst_CLK_000_D1.BLIF inst_CLK_000_D2.BLIF SM_AMIGA_6_.BLIF \ -inst_UDS_000_INTreg.BLIF SM_AMIGA_4_.BLIF inst_UDS_000_INTreg.D --0110101-- 1 ---1----01- 1 ---1---1-1- 1 ---1--0--1- 1 ---1-1---1- 1 --001-----1 1 ---0-----10 1 --1------1- 1 -1-1----0-- 1 -1-1---1--- 1 -1-1--0---- 1 -1-1-1----- 1 -1-0------0 1 -11-------- 1 --0100101-- 0 --000-----1 0 -0-1----00- 0 -0-1---1-0- 0 -0-1--0--0- 0 -0-1-1---0- 0 -0-0-----00 0 -01------0- 0 -.names SIZE_1_.BLIF AS_030.BLIF DS_030.BLIF RW.BLIF SIZE_0_.BLIF A_0_.BLIF \ -inst_AS_030_000_SYNC.BLIF inst_CLK_000_D1.BLIF inst_CLK_000_D2.BLIF \ -SM_AMIGA_6_.BLIF inst_LDS_000_INTreg.BLIF SM_AMIGA_4_.BLIF \ -inst_LDS_000_INTreg.D -0-01100101-- 1 -0-0010-----1 1 ----1-----01- 1 ----1----1-1- 1 ----1---0--1- 1 ----1--1---1- 1 --1-1-----0-- 1 --1-1----1--- 1 --1-1---0---- 1 --1-1--1----- 1 ----0------10 1 --1-0-------0 1 ---1-------1- 1 --11--------- 1 ---01-10101-- 0 ---010-0101-- 0 -1-01--0101-- 0 --0-1-----00- 0 --0-1----1-0- 0 --0-1---0--0- 0 --0-1--1---0- 0 ---00-1-----1 0 ---000------1 0 -1-00-------1 0 --01-------0- 0 --0-0------00 0 -.names AS_030.BLIF CLK_000.BLIF inst_DTACK_SYNC.BLIF inst_VPA_D.BLIF \ -inst_CLK_000_D0.BLIF SM_AMIGA_3_.BLIF DTACK.PIN.BLIF inst_DTACK_SYNC.D ---1--0- 1 ---1-0-- 1 ---10--- 1 --01---- 1 ---1---1 1 -1----0- 1 -1---0-- 1 -1--0--- 1 -10----- 1 -1-----1 1 --1-1110 0 -0-0---- 0 .names inst_AS_000_INTreg.BLIF DSACK_1_.PIN.BLIF inst_DTACK_DMA.D 1- 1 -1 1 @@ -438,6 +437,30 @@ inst_CLK_000_D0.BLIF SM_AMIGA_3_.BLIF DTACK.PIN.BLIF inst_DTACK_SYNC.D .names IPL_030DFFSH_0_reg.BLIF IPL_030_0_ 1 1 0 0 +.names CLK_OSZI.BLIF IPL_030DFFSH_0_reg.C +1 1 +0 0 +.names RST.BLIF IPL_030DFFSH_0_reg.AP +0 1 +1 0 +.names CLK_OSZI.BLIF IPL_030DFFSH_1_reg.C +1 1 +0 0 +.names RST.BLIF IPL_030DFFSH_1_reg.AP +0 1 +1 0 +.names CLK_OSZI.BLIF IPL_030DFFSH_2_reg.C +1 1 +0 0 +.names RST.BLIF IPL_030DFFSH_2_reg.AP +0 1 +1 0 +.names CLK_OSZI.BLIF SM_AMIGA_7_.C +1 1 +0 0 +.names RST.BLIF SM_AMIGA_7_.AP +0 1 +1 0 .names CLK_OSZI.BLIF SM_AMIGA_6_.C 1 1 0 0 @@ -480,6 +503,15 @@ inst_CLK_000_D0.BLIF SM_AMIGA_3_.BLIF DTACK.PIN.BLIF inst_DTACK_SYNC.D .names RST.BLIF SM_AMIGA_0_.AR 0 1 1 0 +.names CLK_OSZI.BLIF CLK_CNT_0_.C +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_CNT_1_.C +1 1 +0 0 +.names CLK_OSZI.BLIF cpu_est_0_.C +1 1 +0 0 .names CLK_OSZI.BLIF cpu_est_1_.C 1 1 0 0 @@ -489,100 +521,6 @@ inst_CLK_000_D0.BLIF SM_AMIGA_3_.BLIF DTACK.PIN.BLIF inst_DTACK_SYNC.D .names CLK_OSZI.BLIF cpu_est_3_reg.C 1 1 0 0 -.names CLK_OSZI.BLIF IPL_030DFFSH_0_reg.C -1 1 -0 0 -.names RST.BLIF IPL_030DFFSH_0_reg.AP -0 1 -1 0 -.names CLK_OSZI.BLIF IPL_030DFFSH_1_reg.C -1 1 -0 0 -.names RST.BLIF IPL_030DFFSH_1_reg.AP -0 1 -1 0 -.names CLK_OSZI.BLIF IPL_030DFFSH_2_reg.C -1 1 -0 0 -.names RST.BLIF IPL_030DFFSH_2_reg.AP -0 1 -1 0 -.names CLK_OSZI.BLIF SM_AMIGA_7_.C -1 1 -0 0 -.names RST.BLIF SM_AMIGA_7_.AP -0 1 -1 0 -.names CLK_OSZI.BLIF inst_VMA_INTreg.C -1 1 -0 0 -.names RST.BLIF inst_VMA_INTreg.AP -0 1 -1 0 -.names CLK_OSZI.BLIF inst_BGACK_030_INTreg.C -1 1 -0 0 -.names RST.BLIF inst_BGACK_030_INTreg.AP -0 1 -1 0 -.names CLK_OSZI.BLIF inst_CLK_OUT_PRE.C -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_CNT_0_.C -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_CNT_1_.C -1 1 -0 0 -.names cpu_est_0_.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF cpu_est_0_.D -010 1 -10- 1 -1-1 1 -110 0 -00- 0 -0-1 0 -.names CLK_OSZI.BLIF cpu_est_0_.C -1 1 -0 0 -.names CLK_OSZI.BLIF inst_VPA_SYNC.C -1 1 -0 0 -.names RST.BLIF inst_VPA_SYNC.AP -0 1 -1 0 -.names CLK_OSZI.BLIF inst_FPU_CS_INTreg.C -1 1 -0 0 -.names RST.BLIF inst_FPU_CS_INTreg.AP -0 1 -1 0 -.names CLK_OSZI.BLIF inst_AS_030_000_SYNC.C -1 1 -0 0 -.names RST.BLIF inst_AS_030_000_SYNC.AP -0 1 -1 0 -.names CLK_OSZI.BLIF inst_AS_000_INTreg.C -1 1 -0 0 -.names RST.BLIF inst_AS_000_INTreg.AP -0 1 -1 0 -.names CLK_OSZI.BLIF AMIGA_BUS_ENABLEDFFreg.C -1 1 -0 0 -.names CLK_OSZI.BLIF BG_000DFFSHreg.C -1 1 -0 0 -.names RST.BLIF BG_000DFFSHreg.AP -0 1 -1 0 -.names CLK_OSZI.BLIF DSACK_INT_1_.C -1 1 -0 0 -.names RST.BLIF DSACK_INT_1_.AP -0 1 -1 0 .names CLK_OSZI.BLIF inst_UDS_000_INTreg.C 1 1 0 0 @@ -595,16 +533,70 @@ inst_CLK_000_D0.BLIF SM_AMIGA_3_.BLIF DTACK.PIN.BLIF inst_DTACK_SYNC.D .names RST.BLIF inst_LDS_000_INTreg.AP 0 1 1 0 +.names CLK_OSZI.BLIF inst_VMA_INTreg.C +1 1 +0 0 +.names RST.BLIF inst_VMA_INTreg.AP +0 1 +1 0 +.names CLK_OSZI.BLIF BG_000DFFSHreg.C +1 1 +0 0 +.names RST.BLIF BG_000DFFSHreg.AP +0 1 +1 0 +.names CLK_OSZI.BLIF inst_CLK_OUT_PRE.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_BGACK_030_INTreg.C +1 1 +0 0 +.names RST.BLIF inst_BGACK_030_INTreg.AP +0 1 +1 0 +.names CLK_OSZI.BLIF inst_AS_000_INTreg.C +1 1 +0 0 +.names RST.BLIF inst_AS_000_INTreg.AP +0 1 +1 0 +.names CLK_OSZI.BLIF inst_AS_030_000_SYNC.C +1 1 +0 0 +.names RST.BLIF inst_AS_030_000_SYNC.AP +0 1 +1 0 .names CLK_OSZI.BLIF inst_DTACK_SYNC.C 1 1 0 0 .names RST.BLIF inst_DTACK_SYNC.AP 0 1 1 0 -.names inst_CLK_OUT_PRE.BLIF CLK_OUT_INTreg.D +.names CLK_OSZI.BLIF inst_FPU_CS_INTreg.C 1 1 0 0 -.names CLK_OSZI.BLIF CLK_OUT_INTreg.C +.names RST.BLIF inst_FPU_CS_INTreg.AP +0 1 +1 0 +.names CLK_OSZI.BLIF DSACK_INT_1_.C +1 1 +0 0 +.names RST.BLIF DSACK_INT_1_.AP +0 1 +1 0 +.names CLK_OSZI.BLIF inst_VPA_SYNC.C +1 1 +0 0 +.names RST.BLIF inst_VPA_SYNC.AP +0 1 +1 0 +.names CLK_OSZI.BLIF AMIGA_BUS_ENABLEDFFreg.C +1 1 +0 0 +.names inst_CLK_000_D4.BLIF inst_CLK_000_D5.D +1 1 +0 0 +.names CLK_OSZI.BLIF inst_CLK_000_D5.C 1 1 0 0 .names CLK_OSZI.BLIF inst_DTACK_DMA.C @@ -613,12 +605,30 @@ inst_CLK_000_D0.BLIF SM_AMIGA_3_.BLIF DTACK.PIN.BLIF inst_DTACK_SYNC.D .names RST.BLIF inst_DTACK_DMA.AP 0 1 1 0 +.names inst_CLK_OUT_PRE.BLIF CLK_OUT_INTreg.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_OUT_INTreg.C +1 1 +0 0 +.names inst_CLK_000_D3.BLIF inst_CLK_000_D4.D +1 1 +0 0 +.names CLK_OSZI.BLIF inst_CLK_000_D4.C +1 1 +0 0 .names inst_CLK_000_D1.BLIF inst_CLK_000_D2.D 1 1 0 0 .names CLK_OSZI.BLIF inst_CLK_000_D2.C 1 1 0 0 +.names inst_CLK_000_D2.BLIF inst_CLK_000_D3.D +1 1 +0 0 +.names CLK_OSZI.BLIF inst_CLK_000_D3.C +1 1 +0 0 .names VPA.BLIF inst_VPA_D.D 1 1 0 0 @@ -643,13 +653,6 @@ inst_CLK_000_D0.BLIF SM_AMIGA_3_.BLIF DTACK.PIN.BLIF inst_DTACK_SYNC.D .names CLK_OSZI.BLIF inst_CLK_000_D1.C 1 1 0 0 -.names CLK_REF_0_.D - 0 -.names CLK_REF_0_.LH - 0 -.names RST.BLIF CLK_REF_0_.AP -0 1 -1 0 .names CLK_REF_1_.D 0 .names CLK_REF_1_.LH @@ -740,16 +743,13 @@ inst_VMA_INTreg.D.X2 01---1-- 0 01----1- 0 .names inst_CLK_OUT_PRE.BLIF inst_CLK_OUT_PRE.D.X1 -0 1 -1 0 -.names inst_CLK_OUT_PRE.BLIF CLK_REF_0_.BLIF CLK_REF_1_.BLIF CLK_CNT_0_.BLIF \ -CLK_CNT_1_.BLIF inst_CLK_OUT_PRE.D.X2 --0-1- 1 ---0-1 1 ---1-0 1 --1-0- 1 --1111 0 --0101 0 --1010 0 --0000 0 +1 1 +0 0 +.names inst_CLK_OUT_PRE.BLIF CLK_REF_1_.BLIF CLK_CNT_0_.BLIF CLK_CNT_1_.BLIF \ +inst_CLK_OUT_PRE.D.X2 +-000 1 +-101 1 +--1- 0 +-0-1 0 +-1-0 0 .end diff --git a/Logic/68030_tk.crf b/Logic/68030_tk.crf index 35a63e8..f425200 100644 --- a/Logic/68030_tk.crf +++ b/Logic/68030_tk.crf @@ -1,7 +1,7 @@ // Signal Name Cross Reference File // ispLEVER Classic 1.7.00.05.28.13 -// Design '68030_tk' created Thu May 22 14:56:10 2014 +// Design '68030_tk' created Sat May 24 11:44:09 2014 // LEGEND: '>' Functional Block Port Separator diff --git a/Logic/68030_tk.eq3 b/Logic/68030_tk.eq3 index 2f3700d..63b11ff 100644 --- a/Logic/68030_tk.eq3 +++ b/Logic/68030_tk.eq3 @@ -2,7 +2,7 @@ Copyright(C), 1992-2013, Lattice Semiconductor Corp. All Rights Reserved. -Design bus68030 created Thu May 22 14:56:10 2014 +Design bus68030 created Sat May 24 11:44:09 2014 P-Terms Fan-in Fan-out Type Name (attributes) @@ -28,18 +28,18 @@ Design bus68030 created Thu May 22 14:56:10 2014 1 1 1 Pin DSACK_1_.AP 1 1 1 Pin DSACK_1_.C 1 1 1 Pin AS_000.OE - 2 6 1 Pin AS_000.D- + 2 3 1 Pin AS_000.D 1 1 1 Pin AS_000.AP 1 1 1 Pin AS_000.C 1 1 1 Pin UDS_000.OE - 8 10 1 Pin UDS_000.D- + 5 7 1 Pin UDS_000.D- 1 1 1 Pin UDS_000.AP 1 1 1 Pin UDS_000.C 1 1 1 Pin LDS_000.OE - 12 12 1 Pin LDS_000.D- + 8 9 1 Pin LDS_000.D 1 1 1 Pin LDS_000.AP 1 1 1 Pin LDS_000.C - 3 7 1 Pin BG_000.D- + 2 6 1 Pin BG_000.D- 1 1 1 Pin BG_000.AP 1 1 1 Pin BG_000.C 2 4 1 Pin BGACK_030.D @@ -73,15 +73,15 @@ Design bus68030 created Thu May 22 14:56:10 2014 1 1 1 Node cpu_est_0_.C 4 6 1 Node cpu_est_1_.T 1 1 1 Node cpu_est_1_.C - 4 11 1 Node inst_AS_030_000_SYNC.D + 7 16 1 Node inst_AS_030_000_SYNC.D 1 1 1 Node inst_AS_030_000_SYNC.AP 1 1 1 Node inst_AS_030_000_SYNC.C - 2 7 1 Node inst_DTACK_SYNC.D- + 2 6 1 Node inst_DTACK_SYNC.D- 1 1 1 Node inst_DTACK_SYNC.AP 1 1 1 Node inst_DTACK_SYNC.C 1 1 1 Node inst_VPA_D.D 1 1 1 Node inst_VPA_D.C - 2 11 1 Node inst_VPA_SYNC.D- + 2 10 1 Node inst_VPA_SYNC.D- 1 1 1 Node inst_VPA_SYNC.AP 1 1 1 Node inst_VPA_SYNC.C 1 1 1 Node inst_CLK_000_D0.D @@ -90,49 +90,53 @@ Design bus68030 created Thu May 22 14:56:10 2014 1 1 1 Node inst_CLK_000_D1.C 1 1 1 Node inst_CLK_000_D2.D 1 1 1 Node inst_CLK_000_D2.C - 4 4 1 Node inst_CLK_OUT_PRE.T + 1 1 1 Node inst_CLK_000_D5.D + 1 1 1 Node inst_CLK_000_D5.C + 3 3 1 NodeX1 inst_CLK_OUT_PRE.D.X1 + 1 2 1 NodeX2 inst_CLK_OUT_PRE.D.X2 1 1 1 Node inst_CLK_OUT_PRE.C 1 1 1 Node SM_AMIGA_6_.AR - 4 6 1 Node SM_AMIGA_6_.D + 2 7 1 Node SM_AMIGA_6_.D 1 1 1 Node SM_AMIGA_6_.C + 1 1 1 Node SM_AMIGA_5_.AR + 2 3 1 Node SM_AMIGA_5_.D + 1 1 1 Node SM_AMIGA_5_.C 3 6 1 NodeX1 cpu_est_2_.D.X1 1 1 1 NodeX2 cpu_est_2_.D.X2 1 1 1 Node cpu_est_2_.C - 0 0 1 Node CLK_REF_0_.D - 1 1 1 Node CLK_REF_0_.AP - 0 0 1 Node CLK_REF_0_.LH 1 1 1 Node CLK_REF_1_.AR 0 0 1 Node CLK_REF_1_.D 0 0 1 Node CLK_REF_1_.LH - 2 4 1 Node SM_AMIGA_7_.D + 5 9 1 Node SM_AMIGA_7_.D 1 1 1 Node SM_AMIGA_7_.AP 1 1 1 Node SM_AMIGA_7_.C + 1 1 1 Node inst_CLK_000_D3.D + 1 1 1 Node inst_CLK_000_D3.C 1 1 1 Node SM_AMIGA_4_.AR 2 3 1 Node SM_AMIGA_4_.D 1 1 1 Node SM_AMIGA_4_.C - 1 1 1 Node SM_AMIGA_1_.AR - 3 4 1 Node SM_AMIGA_1_.D - 1 1 1 Node SM_AMIGA_1_.C - 3 4 1 Node CLK_CNT_0_.D + 1 1 1 Node inst_CLK_000_D4.D + 1 1 1 Node inst_CLK_000_D4.C + 2 3 1 Node CLK_CNT_0_.D 1 1 1 Node CLK_CNT_0_.C - 4 4 1 Node CLK_CNT_1_.D + 2 3 1 Node CLK_CNT_1_.D 1 1 1 Node CLK_CNT_1_.C 1 1 1 Node SM_AMIGA_3_.AR 3 5 1 Node SM_AMIGA_3_.D 1 1 1 Node SM_AMIGA_3_.C - 1 1 1 Node SM_AMIGA_5_.AR - 2 6 1 Node SM_AMIGA_5_.D - 1 1 1 Node SM_AMIGA_5_.C + 1 1 1 Node SM_AMIGA_1_.AR + 3 5 1 Node SM_AMIGA_1_.D + 1 1 1 Node SM_AMIGA_1_.C 1 1 1 Node SM_AMIGA_2_.AR 3 5 1 Node SM_AMIGA_2_.D 1 1 1 Node SM_AMIGA_2_.C 1 1 1 Node SM_AMIGA_0_.AR - 3 5 1 Node SM_AMIGA_0_.D + 4 6 1 Node SM_AMIGA_0_.D 1 1 1 Node SM_AMIGA_0_.C ========= - 185 P-Term Total: 185 + 184 P-Term Total: 184 Total Pins: 59 - Total Nodes: 23 + Total Nodes: 25 Average P-Term/Output: 2 @@ -165,7 +169,7 @@ DSACK_0_ = (1); DSACK_0_.OE = (nEXP_SPACE); IPL_030_2_.D = (!inst_CLK_000_D0.Q & IPL_030_2_.Q - # inst_CLK_000_D1.Q & IPL_030_2_.Q + # IPL_030_2_.Q & inst_CLK_000_D1.Q # IPL_2_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q); IPL_030_2_.AP = (!RST); @@ -175,7 +179,7 @@ IPL_030_2_.C = (CLK_OSZI); DSACK_1_.OE = (nEXP_SPACE); !DSACK_1_.D = (!AS_030 & !DSACK_1_.Q - # !inst_CLK_000_D0.Q & inst_CLK_OUT_PRE.Q & SM_AMIGA_1_.Q); + # !inst_CLK_000_D5.Q & inst_CLK_000_D4.Q & SM_AMIGA_1_.Q); DSACK_1_.AP = (!RST); @@ -183,8 +187,8 @@ DSACK_1_.C = (CLK_OSZI); AS_000.OE = (BGACK_030.Q); -!AS_000.D = (!AS_030 & !AS_000.Q - # !inst_AS_030_000_SYNC.Q & inst_CLK_000_D1.Q & !inst_CLK_000_D2.Q & SM_AMIGA_6_.Q); +AS_000.D = (AS_030 & !SM_AMIGA_5_.Q + # AS_000.Q & !SM_AMIGA_5_.Q); AS_000.AP = (!RST); @@ -193,13 +197,10 @@ AS_000.C = (CLK_OSZI); UDS_000.OE = (BGACK_030.Q); !UDS_000.D = (!AS_030 & DS_030 & !UDS_000.Q - # !AS_030 & RW & inst_AS_030_000_SYNC.Q & !UDS_000.Q - # !AS_030 & RW & !inst_CLK_000_D1.Q & !UDS_000.Q - # !AS_030 & RW & inst_CLK_000_D2.Q & !UDS_000.Q - # !AS_030 & RW & !SM_AMIGA_6_.Q & !UDS_000.Q + # !DS_030 & RW & !A_0_ & SM_AMIGA_5_.Q + # !AS_030 & RW & !SM_AMIGA_5_.Q & !UDS_000.Q # !DS_030 & !RW & !A_0_ & SM_AMIGA_4_.Q - # !AS_030 & !RW & !UDS_000.Q & !SM_AMIGA_4_.Q - # !DS_030 & RW & !A_0_ & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D1.Q & !inst_CLK_000_D2.Q & SM_AMIGA_6_.Q); + # !AS_030 & !RW & !UDS_000.Q & !SM_AMIGA_4_.Q); UDS_000.AP = (!RST); @@ -207,25 +208,20 @@ UDS_000.C = (CLK_OSZI); LDS_000.OE = (BGACK_030.Q); -!LDS_000.D = (!AS_030 & DS_030 & !LDS_000.Q - # !AS_030 & RW & inst_AS_030_000_SYNC.Q & !LDS_000.Q - # !AS_030 & RW & !inst_CLK_000_D1.Q & !LDS_000.Q - # !AS_030 & RW & inst_CLK_000_D2.Q & !LDS_000.Q - # !AS_030 & RW & !SM_AMIGA_6_.Q & !LDS_000.Q - # SIZE_1_ & !DS_030 & !RW & SM_AMIGA_4_.Q - # !DS_030 & !RW & !SIZE_0_ & SM_AMIGA_4_.Q - # !DS_030 & !RW & A_0_ & SM_AMIGA_4_.Q - # !AS_030 & !RW & !LDS_000.Q & !SM_AMIGA_4_.Q - # SIZE_1_ & !DS_030 & RW & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D1.Q & !inst_CLK_000_D2.Q & SM_AMIGA_6_.Q - # !DS_030 & RW & !SIZE_0_ & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D1.Q & !inst_CLK_000_D2.Q & SM_AMIGA_6_.Q - # !DS_030 & RW & A_0_ & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D1.Q & !inst_CLK_000_D2.Q & SM_AMIGA_6_.Q); +LDS_000.D = (AS_030 & DS_030 + # DS_030 & LDS_000.Q + # AS_030 & RW & !SM_AMIGA_5_.Q + # RW & !SM_AMIGA_5_.Q & LDS_000.Q + # AS_030 & !RW & !SM_AMIGA_4_.Q + # !RW & LDS_000.Q & !SM_AMIGA_4_.Q + # !SIZE_1_ & !DS_030 & RW & SIZE_0_ & !A_0_ & SM_AMIGA_5_.Q + # !SIZE_1_ & !DS_030 & !RW & SIZE_0_ & !A_0_ & SM_AMIGA_4_.Q); LDS_000.AP = (!RST); LDS_000.C = (CLK_OSZI); !BG_000.D = (!BG_030 & CLK_030 & !BG_000.Q - # AS_030 & !nEXP_SPACE & !BG_030 & !CLK_030 & SM_AMIGA_6_.Q # AS_030 & !nEXP_SPACE & !BG_030 & !CLK_030 & SM_AMIGA_7_.Q); BG_000.AP = (!RST); @@ -243,7 +239,7 @@ CLK_EXP.D = (inst_CLK_OUT_PRE.Q); CLK_EXP.C = (CLK_OSZI); -!FPU_CS.D = (!AS_030 & !CLK_030 & !FPU_CS.Q +!FPU_CS.D = (!AS_030 & !FPU_CS.Q # FC_1_ & !AS_030 & BGACK_000 & CLK_030 & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_); FPU_CS.AP = (!RST); @@ -311,16 +307,19 @@ cpu_est_1_.T = (E.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D0.Q & !inst_ cpu_est_1_.C = (CLK_OSZI); inst_AS_030_000_SYNC.D = (AS_030 - # !nEXP_SPACE & CLK_030 + # !nEXP_SPACE & inst_AS_030_000_SYNC.Q # !CLK_030 & inst_AS_030_000_SYNC.Q - # FC_1_ & BGACK_000 & CLK_030 & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_); + # !nEXP_SPACE & SM_AMIGA_6_.Q + # inst_AS_030_000_SYNC.Q & !SM_AMIGA_7_.Q + # !inst_CLK_000_D5.Q & inst_CLK_000_D4.Q & SM_AMIGA_1_.Q + # FC_1_ & BGACK_000 & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & inst_AS_030_000_SYNC.Q); inst_AS_030_000_SYNC.AP = (!RST); inst_AS_030_000_SYNC.C = (CLK_OSZI); !inst_DTACK_SYNC.D = (!AS_030 & !inst_DTACK_SYNC.Q - # CLK_000 & inst_VPA_D.Q & inst_CLK_000_D0.Q & SM_AMIGA_3_.Q & !DTACK.PIN); + # inst_VPA_D.Q & inst_CLK_000_D0.Q & SM_AMIGA_3_.Q & !DTACK.PIN); inst_DTACK_SYNC.AP = (!RST); @@ -331,7 +330,7 @@ inst_VPA_D.D = (VPA); inst_VPA_D.C = (CLK_OSZI); !inst_VPA_SYNC.D = (!AS_030 & !inst_VPA_SYNC.Q - # CLK_000 & E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_D0.Q & cpu_est_2_.Q & SM_AMIGA_3_.Q); + # E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_D0.Q & cpu_est_2_.Q & SM_AMIGA_3_.Q); inst_VPA_SYNC.AP = (!RST); @@ -349,22 +348,32 @@ inst_CLK_000_D2.D = (inst_CLK_000_D1.Q); inst_CLK_000_D2.C = (CLK_OSZI); -inst_CLK_OUT_PRE.T = (CLK_REF_0_.Q & CLK_REF_1_.Q & CLK_CNT_0_.Q & CLK_CNT_1_.Q - # !CLK_REF_0_.Q & CLK_REF_1_.Q & !CLK_CNT_0_.Q & CLK_CNT_1_.Q - # CLK_REF_0_.Q & !CLK_REF_1_.Q & CLK_CNT_0_.Q & !CLK_CNT_1_.Q - # !CLK_REF_0_.Q & !CLK_REF_1_.Q & !CLK_CNT_0_.Q & !CLK_CNT_1_.Q); +inst_CLK_000_D5.D = (inst_CLK_000_D4.Q); + +inst_CLK_000_D5.C = (CLK_OSZI); + +inst_CLK_OUT_PRE.D.X1 = (inst_CLK_OUT_PRE.Q & CLK_CNT_0_.Q + # inst_CLK_OUT_PRE.Q & CLK_CNT_1_.Q + # !inst_CLK_OUT_PRE.Q & !CLK_CNT_0_.Q & !CLK_CNT_1_.Q); + +inst_CLK_OUT_PRE.D.X2 = (CLK_REF_1_.Q & !CLK_CNT_0_.Q); inst_CLK_OUT_PRE.C = (CLK_OSZI); SM_AMIGA_6_.AR = (!RST); -SM_AMIGA_6_.D = (inst_AS_030_000_SYNC.Q & SM_AMIGA_6_.Q - # !inst_CLK_000_D1.Q & SM_AMIGA_6_.Q - # inst_CLK_000_D2.Q & SM_AMIGA_6_.Q - # !inst_CLK_000_D0.Q & SM_AMIGA_7_.Q); +SM_AMIGA_6_.D = (nEXP_SPACE & !inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !SM_AMIGA_7_.Q + # !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D2.Q & SM_AMIGA_7_.Q & inst_CLK_000_D3.Q); SM_AMIGA_6_.C = (CLK_OSZI); +SM_AMIGA_5_.AR = (!RST); + +SM_AMIGA_5_.D = (inst_CLK_000_D0.Q & SM_AMIGA_6_.Q + # inst_CLK_000_D0.Q & SM_AMIGA_5_.Q); + +SM_AMIGA_5_.C = (CLK_OSZI); + cpu_est_2_.D.X1 = (E.Q & cpu_est_0_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_2_.Q # !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_2_.Q # !E.Q & cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_2_.Q); @@ -373,50 +382,44 @@ cpu_est_2_.D.X2 = (cpu_est_2_.Q); cpu_est_2_.C = (CLK_OSZI); -CLK_REF_0_.D = (0); - -CLK_REF_0_.AP = (!RST); - -CLK_REF_0_.LH = (0); - CLK_REF_1_.AR = (!RST); CLK_REF_1_.D = (0); CLK_REF_1_.LH = (0); -SM_AMIGA_7_.D = (inst_CLK_000_D0.Q & SM_AMIGA_7_.Q +SM_AMIGA_7_.D = (inst_AS_030_000_SYNC.Q & SM_AMIGA_7_.Q + # inst_CLK_000_D2.Q & SM_AMIGA_7_.Q + # SM_AMIGA_7_.Q & !inst_CLK_000_D3.Q + # !nEXP_SPACE & !inst_CLK_000_D0.Q & SM_AMIGA_6_.Q # AS_000.Q & inst_CLK_000_D0.Q & SM_AMIGA_0_.Q); SM_AMIGA_7_.AP = (!RST); SM_AMIGA_7_.C = (CLK_OSZI); +inst_CLK_000_D3.D = (inst_CLK_000_D2.Q); + +inst_CLK_000_D3.C = (CLK_OSZI); + SM_AMIGA_4_.AR = (!RST); -SM_AMIGA_4_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_4_.Q - # !inst_CLK_000_D0.Q & SM_AMIGA_5_.Q); +SM_AMIGA_4_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_5_.Q + # !inst_CLK_000_D0.Q & SM_AMIGA_4_.Q); SM_AMIGA_4_.C = (CLK_OSZI); -SM_AMIGA_1_.AR = (!RST); +inst_CLK_000_D4.D = (inst_CLK_000_D3.Q); -SM_AMIGA_1_.D = (inst_CLK_000_D0.Q & SM_AMIGA_1_.Q - # inst_CLK_000_D0.Q & SM_AMIGA_2_.Q - # !inst_CLK_OUT_PRE.Q & SM_AMIGA_1_.Q & !SM_AMIGA_2_.Q); +inst_CLK_000_D4.C = (CLK_OSZI); -SM_AMIGA_1_.C = (CLK_OSZI); - -CLK_CNT_0_.D = (CLK_REF_0_.Q & !CLK_CNT_0_.Q - # !CLK_REF_1_.Q & !CLK_CNT_0_.Q & CLK_CNT_1_.Q +CLK_CNT_0_.D = (!CLK_REF_1_.Q & !CLK_CNT_0_.Q & CLK_CNT_1_.Q # CLK_REF_1_.Q & !CLK_CNT_0_.Q & !CLK_CNT_1_.Q); CLK_CNT_0_.C = (CLK_OSZI); -CLK_CNT_1_.D = (CLK_REF_0_.Q & !CLK_CNT_0_.Q & CLK_CNT_1_.Q - # !CLK_REF_1_.Q & !CLK_CNT_0_.Q & CLK_CNT_1_.Q - # !CLK_REF_0_.Q & CLK_CNT_0_.Q & !CLK_CNT_1_.Q - # CLK_REF_1_.Q & CLK_CNT_0_.Q & !CLK_CNT_1_.Q); +CLK_CNT_1_.D = (CLK_CNT_0_.Q & !CLK_CNT_1_.Q + # !CLK_REF_1_.Q & !CLK_CNT_0_.Q & CLK_CNT_1_.Q); CLK_CNT_1_.C = (CLK_OSZI); @@ -428,12 +431,13 @@ SM_AMIGA_3_.D = (inst_CLK_000_D0.Q & SM_AMIGA_4_.Q SM_AMIGA_3_.C = (CLK_OSZI); -SM_AMIGA_5_.AR = (!RST); +SM_AMIGA_1_.AR = (!RST); -SM_AMIGA_5_.D = (inst_CLK_000_D0.Q & SM_AMIGA_5_.Q - # !inst_AS_030_000_SYNC.Q & inst_CLK_000_D1.Q & !inst_CLK_000_D2.Q & SM_AMIGA_6_.Q); +SM_AMIGA_1_.D = (inst_CLK_000_D0.Q & SM_AMIGA_1_.Q + # inst_CLK_000_D0.Q & SM_AMIGA_2_.Q + # !inst_CLK_000_D5.Q & inst_CLK_000_D4.Q & SM_AMIGA_1_.Q); -SM_AMIGA_5_.C = (CLK_OSZI); +SM_AMIGA_1_.C = (CLK_OSZI); SM_AMIGA_2_.AR = (!RST); @@ -447,7 +451,8 @@ SM_AMIGA_0_.AR = (!RST); SM_AMIGA_0_.D = (!AS_000.Q & SM_AMIGA_0_.Q # !inst_CLK_000_D0.Q & SM_AMIGA_0_.Q - # !inst_CLK_000_D0.Q & inst_CLK_OUT_PRE.Q & SM_AMIGA_1_.Q); + # !inst_CLK_000_D0.Q & inst_CLK_000_D5.Q & SM_AMIGA_1_.Q + # !inst_CLK_000_D0.Q & !inst_CLK_000_D4.Q & SM_AMIGA_1_.Q); SM_AMIGA_0_.C = (CLK_OSZI); diff --git a/Logic/68030_tk.fti b/Logic/68030_tk.fti index 8e517b1..261fb98 100644 --- a/Logic/68030_tk.fti +++ b/Logic/68030_tk.fti @@ -6,7 +6,7 @@ DATA LOCATION AMIGA_BUS_DATA_DIR:E_0_48 // OUT DATA LOCATION AMIGA_BUS_ENABLE:D_4_34 // IO {RN_AMIGA_BUS_ENABLE} DATA LOCATION AMIGA_BUS_ENABLE_LOW:C_12_20 // OUT -DATA LOCATION AS_000:D_9_33 // IO {RN_AS_000} +DATA LOCATION AS_000:D_5_33 // IO {RN_AS_000} DATA LOCATION AS_030:H_*_82 // INP DATA LOCATION AVEC:A_4_92 // OUT DATA LOCATION AVEC_EXP:C_0_22 // OUT @@ -30,18 +30,17 @@ DATA LOCATION A_31_:B_*_4 // INP DATA LOCATION BERR:E_4_41 // OUT DATA LOCATION BGACK_000:D_*_28 // INP DATA LOCATION BGACK_030:H_4_83 // IO {RN_BGACK_030} -DATA LOCATION BG_000:D_1_29 // IO {RN_BG_000} +DATA LOCATION BG_000:D_13_29 // IO {RN_BG_000} DATA LOCATION BG_030:C_*_21 // INP DATA LOCATION CIIN:E_12_47 // OUT DATA LOCATION CLK_000:*_*_11 // INP DATA LOCATION CLK_030:*_*_64 // INP -DATA LOCATION CLK_CNT_0_:A_12 // NOD -DATA LOCATION CLK_CNT_1_:A_8 // NOD +DATA LOCATION CLK_CNT_0_:G_2 // NOD +DATA LOCATION CLK_CNT_1_:G_13 // NOD DATA LOCATION CLK_DIV_OUT:G_0_65 // OUT DATA LOCATION CLK_EXP:B_0_10 // OUT DATA LOCATION CLK_OSZI:*_*_61 // Cin -DATA LOCATION CLK_REF_0_:D_6 // NOD -DATA LOCATION CLK_REF_1_:B_2 // NOD +DATA LOCATION CLK_REF_1_:H_14 // NOD DATA LOCATION DSACK_0_:H_12_80 // OUT DATA LOCATION DSACK_1_:H_8_81 // IO {RN_DSACK_1_} DATA LOCATION DS_030:A_*_98 // INP @@ -59,9 +58,9 @@ DATA LOCATION IPL_2_:G_*_68 // INP DATA LOCATION LDS_000:D_8_31 // IO {RN_LDS_000} DATA LOCATION RESET:B_1_3 // OUT DATA LOCATION RN_AMIGA_BUS_ENABLE:D_4 // NOD {AMIGA_BUS_ENABLE} -DATA LOCATION RN_AS_000:D_9 // NOD {AS_000} +DATA LOCATION RN_AS_000:D_5 // NOD {AS_000} DATA LOCATION RN_BGACK_030:H_4 // NOD {BGACK_030} -DATA LOCATION RN_BG_000:D_1 // NOD {BG_000} +DATA LOCATION RN_BG_000:D_13 // NOD {BG_000} DATA LOCATION RN_DSACK_1_:H_8 // NOD {DSACK_1_} DATA LOCATION RN_E:G_4 // NOD {E} DATA LOCATION RN_FPU_CS:H_0 // NOD {FPU_CS} @@ -70,33 +69,36 @@ DATA LOCATION RN_IPL_030_1_:B_12 // NOD {IPL_030_1_} DATA LOCATION RN_IPL_030_2_:B_4 // NOD {IPL_030_2_} DATA LOCATION RN_LDS_000:D_8 // NOD {LDS_000} DATA LOCATION RN_UDS_000:D_12 // NOD {UDS_000} -DATA LOCATION RN_VMA:D_5 // NOD {VMA} +DATA LOCATION RN_VMA:D_1 // NOD {VMA} DATA LOCATION RST:*_*_86 // INP DATA LOCATION RW:G_*_71 // INP DATA LOCATION SIZE_0_:G_*_70 // INP DATA LOCATION SIZE_1_:H_*_79 // INP -DATA LOCATION SM_AMIGA_0_:H_9 // NOD -DATA LOCATION SM_AMIGA_1_:B_13 // NOD +DATA LOCATION SM_AMIGA_0_:H_6 // NOD +DATA LOCATION SM_AMIGA_1_:B_9 // NOD DATA LOCATION SM_AMIGA_2_:G_5 // NOD -DATA LOCATION SM_AMIGA_3_:G_9 // NOD -DATA LOCATION SM_AMIGA_4_:B_5 // NOD -DATA LOCATION SM_AMIGA_5_:G_2 // NOD -DATA LOCATION SM_AMIGA_6_:G_12 // NOD -DATA LOCATION SM_AMIGA_7_:H_5 // NOD +DATA LOCATION SM_AMIGA_3_:B_5 // NOD +DATA LOCATION SM_AMIGA_4_:D_10 // NOD +DATA LOCATION SM_AMIGA_5_:D_14 // NOD +DATA LOCATION SM_AMIGA_6_:H_5 // NOD +DATA LOCATION SM_AMIGA_7_:H_1 // NOD DATA LOCATION UDS_000:D_12_32 // IO {RN_UDS_000} -DATA LOCATION VMA:D_5_35 // IO {RN_VMA} +DATA LOCATION VMA:D_1_35 // IO {RN_VMA} DATA LOCATION VPA:*_*_36 // INP -DATA LOCATION cpu_est_0_:G_13 // NOD -DATA LOCATION cpu_est_1_:G_1 // NOD +DATA LOCATION cpu_est_0_:D_6 // NOD +DATA LOCATION cpu_est_1_:D_9 // NOD DATA LOCATION cpu_est_2_:D_2 // NOD -DATA LOCATION inst_AS_030_000_SYNC:H_1 // NOD +DATA LOCATION inst_AS_030_000_SYNC:H_2 // NOD DATA LOCATION inst_CLK_000_D0:G_8 // NOD -DATA LOCATION inst_CLK_000_D1:D_13 // NOD +DATA LOCATION inst_CLK_000_D1:G_12 // NOD DATA LOCATION inst_CLK_000_D2:G_6 // NOD -DATA LOCATION inst_CLK_OUT_PRE:A_0 // NOD -DATA LOCATION inst_DTACK_SYNC:F_0 // NOD -DATA LOCATION inst_VPA_D:B_9 // NOD -DATA LOCATION inst_VPA_SYNC:G_10 // NOD +DATA LOCATION inst_CLK_000_D3:H_10 // NOD +DATA LOCATION inst_CLK_000_D4:H_9 // NOD +DATA LOCATION inst_CLK_000_D5:H_13 // NOD +DATA LOCATION inst_CLK_OUT_PRE:G_9 // NOD +DATA LOCATION inst_DTACK_SYNC:A_0 // NOD +DATA LOCATION inst_VPA_D:G_1 // NOD +DATA LOCATION inst_VPA_SYNC:F_0 // NOD DATA LOCATION nEXP_SPACE:*_*_14 // INP DATA IO_DIR AMIGA_BUS_DATA_DIR:OUT DATA IO_DIR AMIGA_BUS_ENABLE:OUT @@ -173,57 +175,57 @@ DATA SLEW DS_030:0 DATA SLEW nEXP_SPACE:0 DATA PW_LEVEL BERR:0 DATA SLEW BERR:0 -DATA PW_LEVEL SIZE_0_:0 -DATA SLEW SIZE_0_:0 DATA PW_LEVEL BG_030:0 DATA SLEW BG_030:0 +DATA PW_LEVEL BGACK_000:0 +DATA SLEW BGACK_000:0 +DATA SLEW CLK_030:0 +DATA SLEW CLK_000:0 +DATA PW_LEVEL SIZE_0_:0 +DATA SLEW SIZE_0_:0 +DATA SLEW CLK_OSZI:0 DATA PW_LEVEL A_30_:0 DATA SLEW A_30_:0 +DATA PW_LEVEL CLK_DIV_OUT:0 +DATA SLEW CLK_DIV_OUT:0 DATA PW_LEVEL A_29_:0 DATA SLEW A_29_:0 DATA PW_LEVEL A_28_:0 DATA SLEW A_28_:0 -DATA PW_LEVEL BGACK_000:0 -DATA SLEW BGACK_000:0 DATA PW_LEVEL A_27_:0 DATA SLEW A_27_:0 -DATA SLEW CLK_030:0 DATA PW_LEVEL A_26_:0 DATA SLEW A_26_:0 -DATA SLEW CLK_000:0 +DATA PW_LEVEL AVEC:0 +DATA SLEW AVEC:0 DATA PW_LEVEL A_25_:0 DATA SLEW A_25_:0 -DATA SLEW CLK_OSZI:0 +DATA PW_LEVEL AVEC_EXP:0 +DATA SLEW AVEC_EXP:0 DATA PW_LEVEL A_24_:0 DATA SLEW A_24_:0 -DATA PW_LEVEL CLK_DIV_OUT:0 -DATA SLEW CLK_DIV_OUT:0 DATA PW_LEVEL A_23_:0 DATA SLEW A_23_:0 +DATA SLEW VPA:0 DATA PW_LEVEL A_22_:0 DATA SLEW A_22_:0 DATA PW_LEVEL A_21_:0 DATA SLEW A_21_:0 +DATA SLEW RST:0 DATA PW_LEVEL A_20_:0 DATA SLEW A_20_:0 -DATA PW_LEVEL AVEC:0 -DATA SLEW AVEC:0 DATA PW_LEVEL A_19_:0 DATA SLEW A_19_:0 -DATA PW_LEVEL AVEC_EXP:0 -DATA SLEW AVEC_EXP:0 +DATA PW_LEVEL RW:0 +DATA SLEW RW:0 DATA PW_LEVEL A_18_:0 DATA SLEW A_18_:0 DATA PW_LEVEL A_17_:0 DATA SLEW A_17_:0 -DATA SLEW VPA:0 -DATA PW_LEVEL A_16_:0 -DATA SLEW A_16_:0 -DATA SLEW RST:0 -DATA PW_LEVEL RW:0 -DATA SLEW RW:0 DATA PW_LEVEL AMIGA_BUS_DATA_DIR:0 DATA SLEW AMIGA_BUS_DATA_DIR:0 +DATA PW_LEVEL A_16_:0 +DATA SLEW A_16_:0 DATA PW_LEVEL AMIGA_BUS_ENABLE_LOW:0 DATA SLEW AMIGA_BUS_ENABLE_LOW:0 DATA PW_LEVEL CIIN:0 @@ -288,30 +290,34 @@ DATA PW_LEVEL inst_CLK_000_D1:0 DATA SLEW inst_CLK_000_D1:0 DATA PW_LEVEL inst_CLK_000_D2:0 DATA SLEW inst_CLK_000_D2:0 +DATA PW_LEVEL inst_CLK_000_D5:0 +DATA SLEW inst_CLK_000_D5:0 DATA PW_LEVEL inst_CLK_OUT_PRE:0 DATA SLEW inst_CLK_OUT_PRE:0 DATA PW_LEVEL SM_AMIGA_6_:0 DATA SLEW SM_AMIGA_6_:0 +DATA PW_LEVEL SM_AMIGA_5_:0 +DATA SLEW SM_AMIGA_5_:0 DATA PW_LEVEL cpu_est_2_:0 DATA SLEW cpu_est_2_:0 -DATA PW_LEVEL CLK_REF_0_:0 -DATA SLEW CLK_REF_0_:0 DATA PW_LEVEL CLK_REF_1_:0 DATA SLEW CLK_REF_1_:0 DATA PW_LEVEL SM_AMIGA_7_:0 DATA SLEW SM_AMIGA_7_:0 +DATA PW_LEVEL inst_CLK_000_D3:0 +DATA SLEW inst_CLK_000_D3:0 DATA PW_LEVEL SM_AMIGA_4_:0 DATA SLEW SM_AMIGA_4_:0 -DATA PW_LEVEL SM_AMIGA_1_:0 -DATA SLEW SM_AMIGA_1_:0 +DATA PW_LEVEL inst_CLK_000_D4:0 +DATA SLEW inst_CLK_000_D4:0 DATA PW_LEVEL CLK_CNT_0_:0 DATA SLEW CLK_CNT_0_:0 DATA PW_LEVEL CLK_CNT_1_:0 DATA SLEW CLK_CNT_1_:0 DATA PW_LEVEL SM_AMIGA_3_:0 DATA SLEW SM_AMIGA_3_:0 -DATA PW_LEVEL SM_AMIGA_5_:0 -DATA SLEW SM_AMIGA_5_:0 +DATA PW_LEVEL SM_AMIGA_1_:0 +DATA SLEW SM_AMIGA_1_:0 DATA PW_LEVEL SM_AMIGA_2_:0 DATA SLEW SM_AMIGA_2_:0 DATA PW_LEVEL SM_AMIGA_0_:0 diff --git a/Logic/68030_tk.grp b/Logic/68030_tk.grp index d34e1c4..0da7fcb 100644 --- a/Logic/68030_tk.grp +++ b/Logic/68030_tk.grp @@ -1,16 +1,16 @@ -GROUP MACH_SEG_A inst_CLK_OUT_PRE CLK_CNT_0_ CLK_CNT_1_ AVEC -GROUP MACH_SEG_B SM_AMIGA_1_ IPL_030_1_ RN_IPL_030_1_ IPL_030_0_ RN_IPL_030_0_ - IPL_030_2_ RN_IPL_030_2_ SM_AMIGA_4_ CLK_REF_1_ inst_VPA_D CLK_EXP - RESET +GROUP MACH_SEG_A inst_DTACK_SYNC AVEC +GROUP MACH_SEG_B SM_AMIGA_3_ SM_AMIGA_1_ IPL_030_1_ RN_IPL_030_1_ IPL_030_0_ + RN_IPL_030_0_ IPL_030_2_ RN_IPL_030_2_ CLK_EXP RESET GROUP MACH_SEG_C AVEC_EXP AMIGA_BUS_ENABLE_LOW GROUP MACH_SEG_D LDS_000 RN_LDS_000 UDS_000 RN_UDS_000 VMA RN_VMA BG_000 - RN_BG_000 AS_000 RN_AS_000 cpu_est_2_ AMIGA_BUS_ENABLE RN_AMIGA_BUS_ENABLE - DTACK CLK_REF_0_ inst_CLK_000_D1 + RN_BG_000 cpu_est_1_ cpu_est_2_ AMIGA_BUS_ENABLE RN_AMIGA_BUS_ENABLE + AS_000 RN_AS_000 SM_AMIGA_4_ SM_AMIGA_5_ DTACK cpu_est_0_ GROUP MACH_SEG_E CIIN BERR AMIGA_BUS_DATA_DIR -GROUP MACH_SEG_F inst_DTACK_SYNC -GROUP MACH_SEG_G inst_VPA_SYNC SM_AMIGA_5_ SM_AMIGA_6_ E RN_E cpu_est_1_ - SM_AMIGA_2_ SM_AMIGA_3_ cpu_est_0_ inst_CLK_000_D0 CLK_DIV_OUT inst_CLK_000_D2 +GROUP MACH_SEG_F inst_VPA_SYNC +GROUP MACH_SEG_G E RN_E SM_AMIGA_2_ inst_CLK_OUT_PRE CLK_CNT_0_ CLK_CNT_1_ + inst_VPA_D inst_CLK_000_D0 CLK_DIV_OUT inst_CLK_000_D2 inst_CLK_000_D1 -GROUP MACH_SEG_H inst_AS_030_000_SYNC FPU_CS RN_FPU_CS DSACK_1_ RN_DSACK_1_ - SM_AMIGA_0_ SM_AMIGA_7_ BGACK_030 RN_BGACK_030 DSACK_0_ \ No newline at end of file +GROUP MACH_SEG_H inst_AS_030_000_SYNC FPU_CS RN_FPU_CS SM_AMIGA_7_ SM_AMIGA_6_ + DSACK_1_ RN_DSACK_1_ SM_AMIGA_0_ BGACK_030 RN_BGACK_030 CLK_REF_1_ + inst_CLK_000_D3 inst_CLK_000_D4 inst_CLK_000_D5 DSACK_0_ \ No newline at end of file diff --git a/Logic/68030_tk.ipr b/Logic/68030_tk.ipr index b80f688..d38d77d 100644 --- a/Logic/68030_tk.ipr +++ b/Logic/68030_tk.ipr @@ -1 +1 @@ -0610226pI?E^&ðS \ No newline at end of file +95476<6qYWA7P \ No newline at end of file diff --git a/Logic/68030_tk.jed b/Logic/68030_tk.jed index 9531857..12b3bcd 100644 --- a/Logic/68030_tk.jed +++ b/Logic/68030_tk.jed @@ -10,7 +10,7 @@ AUTHOR: PATTERN: COMPANY: REVISION: -DATE: Thu May 22 14:56:14 2014 +DATE: Sat May 24 11:44:13 2014 ABEL mach447a * @@ -32,47 +32,48 @@ NOTE Run Time Upper Bound in 15 minutes 0 * NOTE Zero Hold Time For Input Registers? Y * NOTE Table of pin names and numbers* NOTE PINS SIZE_1_:79 A_31_:4 IPL_2_:68 FC_1_:58 AS_030:82* -NOTE PINS DS_030:98 nEXP_SPACE:14 BERR:41 SIZE_0_:70 BG_030:21* -NOTE PINS A_30_:5 A_29_:6 A_28_:15 BGACK_000:28 A_27_:16* -NOTE PINS CLK_030:64 A_26_:17 CLK_000:11 A_25_:18 CLK_OSZI:61* -NOTE PINS A_24_:19 CLK_DIV_OUT:65 A_23_:84 A_22_:85 A_21_:94* -NOTE PINS A_20_:93 AVEC:92 A_19_:97 AVEC_EXP:22 A_18_:95* -NOTE PINS A_17_:59 VPA:36 A_16_:96 RST:86 RW:71 AMIGA_BUS_DATA_DIR:48* +NOTE PINS DS_030:98 nEXP_SPACE:14 BERR:41 BG_030:21 BGACK_000:28* +NOTE PINS CLK_030:64 CLK_000:11 SIZE_0_:70 CLK_OSZI:61 A_30_:5* +NOTE PINS CLK_DIV_OUT:65 A_29_:6 A_28_:15 A_27_:16 A_26_:17* +NOTE PINS AVEC:92 A_25_:18 AVEC_EXP:22 A_24_:19 A_23_:84* +NOTE PINS VPA:36 A_22_:85 A_21_:94 RST:86 A_20_:93 A_19_:97* +NOTE PINS RW:71 A_18_:95 A_17_:59 AMIGA_BUS_DATA_DIR:48 A_16_:96* NOTE PINS AMIGA_BUS_ENABLE_LOW:20 CIIN:47 A_0_:69 IPL_1_:56* NOTE PINS IPL_0_:67 DSACK_0_:80 FC_0_:57 IPL_030_2_:9 DSACK_1_:81* NOTE PINS AS_000:33 UDS_000:32 LDS_000:31 BG_000:29 BGACK_030:83* NOTE PINS CLK_EXP:10 FPU_CS:78 DTACK:30 E:66 VMA:35 RESET:3* NOTE PINS AMIGA_BUS_ENABLE:34 IPL_030_1_:7 IPL_030_0_:8 * NOTE Table of node names and numbers* -NOTE NODES RN_IPL_030_2_:131 RN_DSACK_1_:281 RN_AS_000:187 * -NOTE NODES RN_UDS_000:191 RN_LDS_000:185 RN_BG_000:175 RN_BGACK_030:275 * -NOTE NODES RN_FPU_CS:269 RN_DTACK:173 RN_E:251 RN_VMA:181 * +NOTE NODES RN_IPL_030_2_:131 RN_DSACK_1_:281 RN_AS_000:181 * +NOTE NODES RN_UDS_000:191 RN_LDS_000:185 RN_BG_000:193 RN_BGACK_030:275 * +NOTE NODES RN_FPU_CS:269 RN_DTACK:173 RN_E:251 RN_VMA:175 * NOTE NODES RN_AMIGA_BUS_ENABLE:179 RN_IPL_030_1_:143 RN_IPL_030_0_:137 * -NOTE NODES cpu_est_0_:265 cpu_est_1_:247 inst_AS_030_000_SYNC:271 * -NOTE NODES inst_DTACK_SYNC:221 inst_VPA_D:139 inst_VPA_SYNC:260 * -NOTE NODES inst_CLK_000_D0:257 inst_CLK_000_D1:193 inst_CLK_000_D2:254 * -NOTE NODES inst_CLK_OUT_PRE:101 SM_AMIGA_6_:263 cpu_est_2_:176 * -NOTE NODES CLK_REF_0_:182 CLK_REF_1_:128 SM_AMIGA_7_:277 * -NOTE NODES SM_AMIGA_4_:133 SM_AMIGA_1_:145 CLK_CNT_0_:119 * -NOTE NODES CLK_CNT_1_:113 SM_AMIGA_3_:259 SM_AMIGA_5_:248 * -NOTE NODES SM_AMIGA_2_:253 SM_AMIGA_0_:283 * +NOTE NODES cpu_est_0_:182 cpu_est_1_:187 inst_AS_030_000_SYNC:272 * +NOTE NODES inst_DTACK_SYNC:101 inst_VPA_D:247 inst_VPA_SYNC:221 * +NOTE NODES inst_CLK_000_D0:257 inst_CLK_000_D1:263 inst_CLK_000_D2:254 * +NOTE NODES inst_CLK_000_D5:289 inst_CLK_OUT_PRE:259 SM_AMIGA_6_:277 * +NOTE NODES SM_AMIGA_5_:194 cpu_est_2_:176 CLK_REF_1_:290 * +NOTE NODES SM_AMIGA_7_:271 inst_CLK_000_D3:284 SM_AMIGA_4_:188 * +NOTE NODES inst_CLK_000_D4:283 CLK_CNT_0_:248 CLK_CNT_1_:265 * +NOTE NODES SM_AMIGA_3_:133 SM_AMIGA_1_:139 SM_AMIGA_2_:253 * +NOTE NODES SM_AMIGA_0_:278 * NOTE BLOCK 0 * L000000 111111111111111111111111111111111111111111111111111111111111111111 + 111111111011111111111111111111111111111111111111111111111111111111 + 111111111111111111111011111111111111111111111111111111110111111111 111111111111111111111111111111111111111111111111111111111111111111 + 111111111111111111111111111111111111111111111111101111111111111111 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111110111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111011111111111111111111111111111111111111111111111 - 111111011111111111111111111111111111111111111111111111111111111111 - 111111110111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111* + 111111111111111111111111111101111111111111111111111111111111111111 + 111111111111111111101111111111111111111111111111111111111111111111 + 101111111111111111111111111111011111111111111111111111111111111111* L000594 000000000000000000000000000000000000000000000000000000000000000000* -L000660 111111010111111111010111111111111111111111111111111111111111111111* -L000726 111111011011111111100111111111111111111111111111111111111111111111* -L000792 111111100111111111011011111111111111111111111111111111111111111111* -L000858 111111101011111111101011111111111111111111111111111111111111111111* +L000660 111111111111111111101111111111101111111111111111111111111111111111* +L000726 111111111111111111110111111110111111111111111111011111110111111111* +L000792 000000000000000000000000000000000000000000000000000000000000000000* +L000858 000000000000000000000000000000000000000000000000000000000000000000* L000924 000000000000000000000000000000000000000000000000000000000000000000* L000990 111111111111111111111111111111111111111111111111111111111111111111* L001056 111111111111111111111111111111111111111111111111111111111111111111* @@ -117,11 +118,11 @@ L003366 111111111111111111111111111111111111111111111111111111111111111111* L003432 111111111111111111111111111111111111111111111111111111111111111111* L003498 000000000000000000000000000000000000000000000000000000000000000000* -L003564 111111011111111111101011111111111111111111111111111111111111111111* -L003630 111111010111111111101111111111111111111111111111111111111111111111* -L003696 111111101011111111011111111111111111111111111111111111111111111111* -L003762 111111101111111111010111111111111111111111111111111111111111111111* -L003828 000000000000000000000000000000000000000000000000000000000000000000* +L003564 111111111111111111111111111111111111111111111111111111111111111111* +L003630 111111111111111111111111111111111111111111111111111111111111111111* +L003696 111111111111111111111111111111111111111111111111111111111111111111* +L003762 111111111111111111111111111111111111111111111111111111111111111111* +L003828 111111111111111111111111111111111111111111111111111111111111111111* L003894 111111111111111111111111111111111111111111111111111111111111111111* L003960 111111111111111111111111111111111111111111111111111111111111111111* L004026 111111111111111111111111111111111111111111111111111111111111111111* @@ -141,11 +142,11 @@ L004818 111111111111111111111111111111111111111111111111111111111111111111* L004884 111111111111111111111111111111111111111111111111111111111111111111* L004950 000000000000000000000000000000000000000000000000000000000000000000* -L005016 111111110111111111101111111111111111111111111111111111111111111111* -L005082 111111011111111111101011111111111111111111111111111111111111111111* -L005148 111111101111111111100111111111111111111111111111111111111111111111* -L005214 000000000000000000000000000000000000000000000000000000000000000000* -L005280 000000000000000000000000000000000000000000000000000000000000000000* +L005016 111111111111111111111111111111111111111111111111111111111111111111* +L005082 111111111111111111111111111111111111111111111111111111111111111111* +L005148 111111111111111111111111111111111111111111111111111111111111111111* +L005214 111111111111111111111111111111111111111111111111111111111111111111* +L005280 111111111111111111111111111111111111111111111111111111111111111111* L005346 111111111111111111111111111111111111111111111111111111111111111111* L005412 111111111111111111111111111111111111111111111111111111111111111111* L005478 111111111111111111111111111111111111111111111111111111111111111111* @@ -165,38 +166,38 @@ L006270 111111111111111111111111111111111111111111111111111111111111111111* L006336 111111111111111111111111111111111111111111111111111111111111111111* L006402 000000000000000000000000000000000000000000000000000000000000000000 - 000000000000000000000000000000000000000000000000000000000000000000* + 101111111111111111111111111111111111111111111111111111111111111111* L006534 0010* -L006538 10100111010000* +L006538 11100110010000* L006552 11011011111110* L006566 11110011110101* -L006580 11111111111111* -L006594 00111011111000* -L006608 11000011110011* -L006622 11110111110000* -L006636 11110011110010* -L006650 10100110010001* -L006664 11000111110011* -L006678 11111111110000* -L006692 11110011110011* -L006706 10100110010001* -L006720 11001011110011* -L006734 11110111110000* +L006580 11110111111111* +L006594 00110011111000* +L006608 11000111110011* +L006622 11110011110001* +L006636 11110111110011* +L006650 11110011110000* +L006664 11111011110011* +L006678 11110111110001* +L006692 11111111110011* +L006706 11110011110000* +L006720 11111011110011* +L006734 11110111110001* L006748 11111111110011* NOTE BLOCK 1 * L006762 - 111111111111111111111111011111111111111111111111111111110111111111 - 111111111111111111111111111111111111111111111111111111111110111111 - 111111101011111101111111111011111111111111111111111111111111110111 - 101111111111111111111111111111111111111111111010111111011111111111 + 110111111111111111111111111110111111111111111111111111111111111111 + 111111111111011111111011111111111111111111111111111111111110111111 + 111111101011111101111111111011111111111111111111111111110111111111 + 101111111111111111111111111111111111111111111011111111011111111111 + 111111111111111111111111111111111111111111111111111011111111111111 + 111101111111111011111111111111111111111111111111111111111111111111 + 111111111110111111111111111111111111111111111111111111111111111111 111111111111111111111111111111111111111111111111111111111111111111 - 110111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111110111111111011111111111101111111111111111111111* + 111111111111111111111111111111011111111111101111111111111111111111* L007356 111111111111111111111111111111111111111111111111111111111111111111* -L007422 111111111111111111111111111111011111111111111111111111111111111111* +L007422 111111111111111111110111111111111111111111111111111111111111111111* L007488 111111111111111111111111111111111111111111111111111111111101111111* L007554 000000000000000000000000000000000000000000000000000000000000000000* L007620 000000000000000000000000000000000000000000000000000000000000000000* @@ -204,13 +205,13 @@ L007686 000000000000000000000000000000000000000000000000000000000000000000* L007752 111111111111111111111111111111111111111111011111111111111111111111* L007818 111111111111111111111111111111111111111111111111111111111101111111* L007884 000000000000000000000000000000000000000000000000000000000000000000* -L007950 000000000000000000000000000000000000000000000000000000000000000000* -L008016 000000000000000000000000000000000000000000000000000000000000000000* +L007950 111111111111111111111111111111111111111111111111111111111111111111* +L008016 111111111111111111111111111111111111111111111111111111111111111111* L008082 111111111111111111111111111111111111111111111111111111111111111111* -L008148 000000000000000000000000000000000000000000000000000000000000000000* -L008214 000000000000000000000000000000000000000000000000000000000000000000* -L008280 111111111111111111111111111111111111111111101111111111111111111111* +L008148 111111111111111111111111111111111111111111111111111111111111111111* +L008214 111111111111111111111111111111111111111111111111111111111111111111* +L008280 111111111111111111111111111111111111111111111111111111111111111111* L008346 111111111111111111111111111111111111111111111111111111111111111111* L008412 111111111111111111111111111111111111111111111111111111111111111111* L008478 111111111111111111111111111111111111111111111111111111111111111111* @@ -220,14 +221,14 @@ L008676 111111111111111111111111111111111111111111111111111111111111111111* L008742 111111111111111111111111111111111111111111111111111111111111111111* L008808 111111111111111111111111111111111111111111111111111111111111111111* -L008874 111011110111111111111111110111111111111111111111111111111111111111* -L008940 111111111111111111111111111011111111111111111111111111011111111111* -L009006 110111111111111111111111111111111111111111111111111111011111111111* +L008874 111111111111111111111111111011111111111111111111111111011111111111* +L008940 111111111111111111111111111101111111111111111111111111011111111111* +L009006 111111110111111111111111110110111111111111111111111111111111111111* L009072 000000000000000000000000000000000000000000000000000000000000000000* L009138 000000000000000000000000000000000000000000000000000000000000000000* -L009204 111111111111111111111111111011111111111111111111111111111111110111* -L009270 111111111111111111111111111011111111111111111101111111111111111111* -L009336 000000000000000000000000000000000000000000000000000000000000000000* +L009204 111101111111111111111111110111111111111111111111111111111111111111* +L009270 111111111111111111111111111111011111111111111111110111110111111111* +L009336 111111111111111111111111110111111111111111111111111111110111111111* L009402 000000000000000000000000000000000000000000000000000000000000000000* L009468 000000000000000000000000000000000000000000000000000000000000000000* L009534 @@ -245,15 +246,15 @@ L010194 111111111111111111111111111111111111111111111111111111111111111111* L010260 000000000000000000000000000000000000000000000000000000000000000000* L010326 111111111111111101111111111011111111111111111111111111111111111111* -L010392 110111111111111101111111111111111111111111111111111111111111111111* -L010458 011011111111111111111111110111111111111111111111111111111111111111* +L010392 111111111111111101111111111101111111111111111111111111111111111111* +L010458 011111111111111111111111110110111111111111111111111111111111111111* L010524 000000000000000000000000000000000000000000000000000000000000000000* L010590 000000000000000000000000000000000000000000000000000000000000000000* -L010656 111111111111111111110111111111111111111111111111111111111111111111* -L010722 111111111111111111111111111111111111111111111111111111111101111111* -L010788 000000000000000000000000000000000000000000000000000000000000000000* -L010854 111111111111111111111111111111111111111111111111111111111111111111* -L010920 111111111111111111111111111111111111111111111111111111111111111111* +L010656 111111111101011011111111111111111111111111111111111111111111111111* +L010722 111111111111011111111111110111111111111111111111111111111111111111* +L010788 111111111111111111111111110111111111111111110111111111111111111111* +L010854 000000000000000000000000000000000000000000000000000000000000000000* +L010920 000000000000000000000000000000000000000000000000000000000000000000* L010986 000000000000000000000000000000000000000000000000000000000000000000* L011052 111111111111111111111111111111111111111111111111111111111111111111* @@ -268,16 +269,16 @@ L011580 111111111111111111111111111111111111111111111111111111111111111111* L011646 111111111111111111111111111111111111111111111111111111111111111111* L011712 000000000000000000000000000000000000000000000000000000000000000000* -L011778 111111111111111111111111011011111111111111111111111111111111111111* -L011844 110111111111111111111111011111111111111111111111111111111111111111* -L011910 111011011111111111111111110111111111111111111111111111111111111111* +L011778 110111111111111111111111111011111111111111111111111111111111111111* +L011844 110111111111111111111111111101111111111111111111111111111111111111* +L011910 111111011111111111111111110110111111111111111111111111111111111111* L011976 000000000000000000000000000000000000000000000000000000000000000000* L012042 000000000000000000000000000000000000000000000000000000000000000000* -L012108 111111111111111111111111110111111111111111111111111111110111111111* -L012174 111111111111111111111111110111111111111111110111111111111111111111* -L012240 111111111111111111111111111111101111111111111011111111110111111111* -L012306 000000000000000000000000000000000000000000000000000000000000000000* -L012372 000000000000000000000000000000000000000000000000000000000000000000* +L012108 111111111111111111111111111111111111111111111111111111111111111111* +L012174 111111111111111111111111111111111111111111111111111111111111111111* +L012240 111111111111111111111111111111111111111111111111111111111111111111* +L012306 111111111111111111111111111111111111111111111111111111111111111111* +L012372 111111111111111111111111111111111111111111111111111111111111111111* L012438 111111111111111111111111111111111111111111111111111111111111111111* L012504 111111111111111111111111111111111111111111111111111111111111111111* @@ -295,21 +296,21 @@ L013164 111111111111111111111111111111111111111111101111111111111111111111* L013296 0010* L013300 00101110000000* -L013314 00101110001110* -L013328 00011110100100* -L013342 11100011111111* -L013356 10100110010011* -L013370 10100100011111* -L013384 11011011110110* -L013398 11110011111111* -L013412 10100110011001* -L013426 00001110000011* -L013440 11011111110000* -L013454 11110011110010* -L013468 10100110011001* -L013482 10100100010011* -L013496 11011011111100* -L013510 11111111111111* +L013314 00011110001110* +L013328 11011111110100* +L013342 11111011111111* +L013356 10100110010010* +L013370 10100100011110* +L013384 11011111110111* +L013398 11111011111111* +L013412 10100110011000* +L013426 10100100010010* +L013440 11010011110000* +L013454 11111011110011* +L013468 10100110011000* +L013482 11001111110010* +L013496 11110011111101* +L013510 11111011111111* NOTE BLOCK 2 * L013524 111111111111111111111111111111111111111111111111111111111111111111 @@ -439,25 +440,25 @@ L020258 11110111110101* L020272 11111111111111* NOTE BLOCK 3 * L020286 - 111111111011111011111111111111111111111111111111111011111111111111 - 101111111101111110111111111111111111111111110111111111111110110111 - 111111111111111111111011111111101111111111111110111111110111111111 + 111111111111111011111111111111111111111110111111111111111111111111 + 101111111111111110111111111101011111111111111111111111111110111111 + 111111111111111111111111111111111111101111111111111111111011111111 111110111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111011111111111111111111111111110 - 110111111111101111111101111111111111111111111111111111111111111111 - 111111111111111111111111011111110110111111111111111111111111111111 - 111111111111111111101111111001111111111110111111011111111111111111 + 111111111111111111111111011111111101111111111111101111111111111111 + 110111111101101111111111111111111111111111111111111111111111011111 + 111111111111111111111111111111110111111111111111110111111111111110 + 111111110111111111100101111011111111111111111110111111111111111111 111111011111111111111111111111111111111011101111111111011111111111* L020880 111111111111111111111111111111111111111111111111111111111111111111* -L020946 111111111111111111111111101111111110111111111111111111111111111111* +L020946 111111111111111111111110111111111111111111111111111111111111111110* L021012 000000000000000000000000000000000000000000000000000000000000000000* L021078 000000000000000000000000000000000000000000000000000000000000000000* L021144 000000000000000000000000000000000000000000000000000000000000000000* L021210 000000000000000000000000000000000000000000000000000000000000000000* -L021276 111111110111111111111111111111111111111111111011111111101111111111* -L021342 111111111010110111011111111111111111111111111011111111111111111111* -L021408 111111111010111111011111110111111111111111111011111111111111111111* +L021276 111110011011111111111101111111111111111111111111110111100111111111* +L021342 111110010111111111111111111111111111111111111111101011011011111111* +L021408 000000000000000000000000000000000000000000000000000000000000000000* L021474 000000000000000000000000000000000000000000000000000000000000000000* L021540 000000000000000000000000000000000000000000000000000000000000000000* L021606 @@ -465,80 +466,80 @@ L021606 L021672 111111011111111111111111111111111111111111111111111111111111111111* L021738 111111111111111111111111111111111111111111111111111111111101111111* L021804 000000000000000000000000000000000000000000000000000000000000000000* -L021870 111001101111111111110111111111111111111111111111110111111111111111* -L021936 111011101111111111110111111111111111111111111111111011111111111110* -L022002 111010011111111111110111111111111111111111111111110111111111111110* +L021870 111101100111111011111111111111111111111111111111111111110111111111* +L021936 111111101011111011111111111111111111111111111111111011110111111111* +L022002 111110010111111011111111111111111111111111111111111011110111111111* L022068 000000000000000000000000000000000000000000000000000000000000000000* L022134 000000000000000000000000000000000000000000000000000000000000000000* L022200 000000000000000000000000000000000000000000000000000000000000000000* L022266 000000000000000000000000000000000000000000000000000000000000000000* L022332 - 111111111111111111111111111111111111111101111111111111111111111111* -L022398 111111111111111111111111111111111111111111111111111111111111111111* + 111111111111111111111111111111111111111111111101111111111111111111* +L022398 111111111111111111111111110111011111111111011111111111111111111111* L022464 111111111111111111111111111111111111111111111111111111111101111111* L022530 000000000000000000000000000000000000000000000000000000000000000000* -L022596 111111111111111111111111111111111111111111111111111111111111111111* -L022662 111111111111111111111111111111111111111111111111111111111111111111* -L022728 111111111101110111111111111111111111111111011111111111111111111111* -L022794 111111111111111111111111111110111111111111101111111111111111111111* -L022860 111111111111111011101111111110111111111111111111111111111111111111* +L022596 111111111111111111111011111111111111111111101111111111111111111111* +L022662 111111111111111111101011111011111111111111111111111111111111111111* +L022728 111111111111111111011111111111111110111111111111111111111111111111* +L022794 111111111111111111111101111111111110111111111111111111111111111111* +L022860 000000000000000000000000000000000000000000000000000000000000000000* L022926 000000000000000000000000000000000000000000000000000000000000000000* L022992 000000000000000000000000000000000000000000000000000000000000000000* L023058 - 111111111111111111111111111111111111111101111111111111111111111111* -L023124 000000000000000000000000000000000000000000000000000000000000000000* -L023190 000000000000000000000000000000000000000000000000000000000000000000* -L023256 111111111111111111111111111111111111111111101111111111111111111111* -L023322 111110011111111111110111011111111111111111111111101011111111111101* -L023388 111110011111111111111011111111111111111111111111010111111111111010* -L023454 110111111111010101111111111111111111101011111110111111111111111111* -L023520 100111111111110101111111111111111111101011111110111111111111111111* -L023586 110111111111110101111111111111011111101011111110111111111111111111* -L023652 111111111111111111101111111111111011011111111111111111111111111111* -L023718 111111111111111101101111111111111011110111111111111111111111111111* + 111111111111111111111111111111111111111111111101111111111111111111* +L023124 111111110111111111111111111111111111111111111111111111111011111111* +L023190 111111111111111111111111111111111111111111111111111111111101111111* +L023256 000000000000000000000000000000000000000000000000000000000000000000* +L023322 111111110111110111111111111111111111111111111111111111111111111111* +L023388 111111111011111011111111111111111111111111111111111111110111111111* +L023454 111111111111111111111111111111111111111111111111111111111111111111* +L023520 111111111111111111111111111111111111111111111111111111111111111111* +L023586 111111111111111111111111111111111111111111111111111111111111111111* +L023652 111111111111111111111111111111111111111111111111111111111111111111* +L023718 111111111111111111111111111111111111111111111111111111111111111111* L023784 - 111111111111111111111111111111111111111101111111111111111111111111* -L023850 111011111111111101101111111111111011111111111111111111111111111111* -L023916 111111111111111101101111111111111011111111111101111111111111111111* -L023982 111111111111111001101111111111111011111111111111111111111111111111* -L024048 111111111111011110111111111111111111101111111111111111110111111111* -L024114 101111111111111110111111111111111111101111111111111111110111111111* -L024180 111111111111111110111111111111011111101111111111111111110111111111* -L024246 111111111111111110101111111111111011111111111111111111111011111111* + 111111111111111111111111111111111111111111111101111111111111111111* +L023850 111111111111111111011111011111111111111111111111111111111111111111* +L023916 011111111111101101111111101111111101101111111111111111111111111111* +L023982 111111111111111101011111111111111110111111111111111111111111111111* +L024048 111111111111111111111111011111110111111111111111111111111111111111* +L024114 111111111111111101111111111111110110111111111111111111111111111111* +L024180 011111111111101110111111101111111111101111111111111111111111011111* +L024246 111111111111111111111111111111111111111111111111111111111101111111* L024312 000000000000000000000000000000000000000000000000000000000000000000* -L024378 000000000000000000000000000000000000000000000000000000000000000000* -L024444 000000000000000000000000000000000000000000000000000000000000000000* +L024378 111111111111111110011111111111111111111111111111111111111111101111* +L024444 111111111111111110111111111111110111111111111111111111111111101111* L024510 - 111111111111111111111111111111111111111110111111111111111111111111* -L024576 111111111111111111101111101111111111111111111111111111111111111111* -L024642 110111111111110111111111111111111111111011111110111111111111111111* + 111111111111111111111111111111111111111111111110111111111111111111* +L024576 111111111111111111111111111111111101111111111111111111111011111111* +L024642 111111111111111111111111111111111111111111111111111111111011011111* L024708 000000000000000000000000000000000000000000000000000000000000000000* L024774 000000000000000000000000000000000000000000000000000000000000000000* L024840 000000000000000000000000000000000000000000000000000000000000000000* -L024906 110111111111110101111111111111101111101011111110111111111111111111* -L024972 111111111111111111101110111111111111011111111111111111111111111111* -L025038 111111111111111101101110111111111111110111111111111111111111111111* -L025104 111011111111111101101110111111111111111111111111111111111111111111* -L025170 111111111111111101101110111111111111111111111101111111111111111111* +L024906 111101111011111011111111111111111111111111111111111011110111111111* +L024972 111110010111111011111111111111111111111111111111111111110111111111* +L025038 111101100111111011111111111111111111111111111111110111110111111111* +L025104 111110101111111011111111111111111111111111111111111011110111111111* +L025170 000000000000000000000000000000000000000000000000000000000000000000* L025236 111111111111111111111111111111111111111111111111111111111111111111* -L025302 111111111111111001101110111111111111111111111111111111111111111111* -L025368 111111111111111110111111111111101111101111111111111111110111111111* -L025434 111111111111111110101110111111111111111111111111111111111011111111* -L025500 000000000000000000000000000000000000000000000000000000000000000000* -L025566 000000000000000000000000000000000000000000000000000000000000000000* -L025632 111111111111111111110111111111111111111111111111111111111111111111* -L025698 111111111111111111111111111111111111111111111111111111111101111111* +L025302 111111111111111101111111101111111101101111111111111111111111111111* +L025368 111111111110111111101111011111111111111111111111111111111111111111* +L025434 111111111110111101101111111111111110111111111111111111111111111111* +L025500 111111111111111110111111101111111111101111111111111111111111011111* +L025566 111111111110111110101111111111111111111111111111111111111111101111* +L025632 111111111111111111011111111110101111110110111111111111111111111111* +L025698 111011111111111111111111111110111111111101111111111111111111111111* L025764 000000000000000000000000000000000000000000000000000000000000000000* L025830 000000000000000000000000000000000000000000000000000000000000000000* L025896 000000000000000000000000000000000000000000000000000000000000000000* L025962 000000000000000000000000000000000000000000000000000000000000000000* -L026028 111111111111111111111111111111111111111111111111111111111111111111* -L026094 111111111111111111111111111111111111111111111111111111111111111111* -L026160 111111111111111111111111111111111111111111111111111111111111111111* -L026226 111111111111111111111111111111111111111111111111111111111111111111* -L026292 111111111111111111111111111111111111111111111111111111111111111111* +L026028 111111111111111111111111110111111111111111111111111111110111111111* +L026094 111111111111111111111111111111111101111111111111111111110111111111* +L026160 000000000000000000000000000000000000000000000000000000000000000000* +L026226 000000000000000000000000000000000000000000000000000000000000000000* +L026292 000000000000000000000000000000000000000000000000000000000000000000* L026358 111111111111111111111111111111111111111111111111111111111111111111* L026424 111111111111111111111111111111111111111111111111111111111111111111* L026490 111111111111111111111111111111111111111111111111111111111111111111* @@ -548,22 +549,22 @@ L026688 000000000000000000000000000000000000000000000000000000000000000000 111111111111111111111111111111111111111111101111111111111111111111* L026820 0010* -L026824 01100110011010* -L026838 11100110011110* +L026824 01100110011000* +L026838 10100111011110* L026852 00101110000100* L026866 11110011111111* -L026880 11111110001011* -L026894 10110111011111* -L026908 00111100100110* -L026922 11011111111111* -L026936 11100110010001* -L026950 11110110011111* -L026964 11111011110110* -L026978 11011111110010* -L026992 11100110011010* -L027006 00111110001111* -L027020 11010011110000* -L027034 11111011110010* +L026880 11101110001001* +L026894 10100110011111* +L026908 10101110000110* +L026922 11101111111111* +L026936 10100110010001* +L026950 10111111001111* +L026964 10100100010110* +L026978 11001011110010* +L026992 11100110011000* +L027006 11100110011111* +L027020 10100100010000* +L027034 11101111110010* NOTE BLOCK 4 * L027048 111111111111111111111111111111111111111111111111111111111111111111 @@ -693,19 +694,19 @@ L033782 11110111110101* L033796 11111111111111* NOTE BLOCK 5 * L033810 - 111111011111111111111111111111111111111111111111111111111111111111 - 111111111011011111111011111111111111111111111111111111111111111111 - 111111111111111111111111111011111111111111111111111111111111111111 111111111111111111111111111111111111111111111111111111111111111111 - 111111111110111111111111111111111111111111111111111111111111111111 + 111111111011111111111111111111111111111111111111111111111111111111 + 111111111111111111111011111111111111111111111111111111110111111111 + 111111111111111111111110111111111111111111111111111111111111111111 + 111111111110111111111111111111111111111111111111101111111111111111 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111101111111111111111111111111111111111111 - 111111111111111111101111111111111111111111111111111111111111111111 - 101111111111111111111111111111111111111111111111111111111111111111* + 111111111111110111111111111111111111111111111111111111111111111111 + 111111111111111111101111111111110111111111111111111111111111111111 + 101101011111111111111111111111111111111111111111111111111111111111* L034404 000000000000000000000000000000000000000000000000000000000000000000* L034470 111111111110111111101111111111111111111111111111111111111111111111* -L034536 111111011111011111110111110110111111111111111111111111111111111111* +L034536 111110011111111011110101111111111011111111111111101111110111111111* L034602 000000000000000000000000000000000000000000000000000000000000000000* L034668 000000000000000000000000000000000000000000000000000000000000000000* L034734 000000000000000000000000000000000000000000000000000000000000000000* @@ -821,32 +822,32 @@ L040558 11111111111111* NOTE BLOCK 6 * L040572 111111011111111111101111111110111111111111111111111111111111111111 - 111111111010011111111111101111111111111111111111111111111111111111 - 111111111111111111111011111111111111111111111110111111110111111111 - 111110111111111111111111111111111111111111111011111111111111111011 - 111111111111111111111111111111111111111111111111101011111111111111 - 110111111111111111111111111111111111111111111111111111111111111111 + 111111111011111111111111101111111111111111111111111111111111111111 + 111111111111111111111111111011111111111111111111111111111111110111 + 111111111111111111111110111111111111111111111010111111111111111111 + 111110111110111111111111111111111111111111111111111111111111111111 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111110111111111111011111111111111111111111111111111111110 - 101111111111111111111111111111010111111011111111111111111111111111* + 111111111111110111111111111111111111111111111111111111111111111111 + 111111111111111111111111111111110111111111111111111111111111111111 + 101111111111111111110111111111011111111111111111111111110111111111* L041166 111111111111111111111111111111111111111111111111111111111111111111* -L041232 111111111111111111111111111111011111111111111111111111111111111111* +L041232 111111111111111111111111011111111111111111111111111111111111111111* L041298 000000000000000000000000000000000000000000000000000000000000000000* L041364 000000000000000000000000000000000000000000000000000000000000000000* L041430 000000000000000000000000000000000000000000000000000000000000000000* L041496 000000000000000000000000000000000000000000000000000000000000000000* -L041562 111001111111111111100111111111111111111111111111101111111111111111* -L041628 111010111111111111010111111111110111111111111111111111111111111111* -L041694 111001111111111111010111111111111011111111111111011111111111111111* -L041760 111010111111111111110111111111111011111111111111101111111111111111* +L041562 111111111111111111110111111111111111111111111111111111111111111111* +L041628 000000000000000000000000000000000000000000000000000000000000000000* +L041694 000000000000000000000000000000000000000000000000000000000000000000* +L041760 000000000000000000000000000000000000000000000000000000000000000000* L041826 000000000000000000000000000000000000000000000000000000000000000000* L041892 111111111111111111111111111111111111111111111111111111111111111111* -L041958 110111111111111111111111111101111111111011111110111111111111111111* -L042024 111111110111111111111111111111111111111111111111111111111111111111* -L042090 101111111111111111111111111111111111111111111111111111111111111111* -L042156 111111111111111111110111111111111111111111111111111111111111110111* +L041958 111110111111111111011111111111111111111111111110111111111111111111* +L042024 111101111111111111101111111111111111111111111110111111111111111111* +L042090 000000000000000000000000000000000000000000000000000000000000000000* +L042156 000000000000000000000000000000000000000000000000000000000000000000* L042222 000000000000000000000000000000000000000000000000000000000000000000* L042288 111111111111111111111111111111111111111111111111111111111111111111* L042354 111111111111111111111111111111111111111111111111111111111111111111* @@ -855,19 +856,19 @@ L042486 111111111111111111111111111111111111111111111111111111111111111111* L042552 111111111111111111111111111111111111111111111111111111111111111111* L042618 000000000000000000000000000000000000000000000000000000000000000000* -L042684 111001111111111111010111111111110111111111111111011111111111111111* -L042750 111010111111111111010111111111111011111111111111011111111111111111* -L042816 111010111111111111100111111111111011111111111111101111111111111111* +L042684 111111111111110111111101110110110111111111111111111111110111111111* +L042750 111111111111110111111110110110110111111111111111111111111011111111* +L042816 111111111111111011111110110110111011111111111111111111111011111111* L042882 000000000000000000000000000000000000000000000000000000000000000000* L042948 000000000000000000000000000000000000000000000000000000000000000000* -L043014 111111111111111111111011011111111111111111111111111011111111111111* +L043014 111111111111111111111111111011101111111111111111111111111111110111* L043080 111111110111111111111111111111111111111111111111111111111111111111* L043146 101111111111111111111111111111111111111111111111111111111111111111* -L043212 111111111110111111111011011111111111111111111111111111111111111111* -L043278 111111111111111111111011111111111111111111110111111111111111111111* +L043212 111111111110111111111111111011111111111111111111111111111111110111* +L043278 111111111111111111111111111011111111111111110111111111111111111111* L043344 000000000000000000000000000000000000000000000000000000000000000000* -L043410 110111111111111111111111111111111111111111111111111111111111111111* +L043410 111111111111111111111111111101111111111111111111111111111111111111* L043476 111111111111111111111111111111111111111111111111111111111111111111* L043542 111111111111111111111111111111111111111111111111111111111111111111* L043608 111111111111111111111111111111111111111111111111111111111111111111* @@ -884,18 +885,18 @@ L044202 111111111111111111111111111111111111111111111111111111111111111111* L044268 111111111111111111111111111111111111111111111111111111111111111111* L044334 111111111111111111111111111111111111111111111111111111111111111111* L044400 111111111111111111111111111111111111111111111111111111111111111111* -L044466 111111111111111111110111111111111111111111111111111111110111111111* -L044532 111111110111111111111111111111111111111111111111111111111111111111* -L044598 101111111111111111111111111111111111111111111111111111111111111111* -L044664 111111111101111111111111011111111111111111111111110111111111111111* -L044730 111111111111111111110111011111111111111111111111111111111111111111* +L044466 111101111111111111111111111111111111111111111110111111111111111111* +L044532 111111111111111111111111011111111111111111111101111111111111111111* +L044598 111111111111111111011111011111111111111111111111111111111111111111* +L044664 111111111111111111101111101111111111111111111110111111111111111111* +L044730 000000000000000000000000000000000000000000000000000000000000000000* L044796 000000000000000000000000000000000000000000000000000000000000000000* -L044862 111111111110111111111111111111111111111111111111111111111111111110* -L044928 111111110111111111111111111111111111111111111111111111111111111111* -L044994 101111111111111111111111111111111111111111111111111111111111111111* -L045060 111101011111101011100111011111110111111111111111101111111111111111* -L045126 000000000000000000000000000000000000000000000000000000000000000000* +L044862 111111111111111111111111111111111111111111111111111111111111111111* +L044928 111111111111111111111111111111111111111111111111111111111111111111* +L044994 111111111111111111111111111111111111111111111111111111111111111111* +L045060 111111111111111111111111111111111111111111111111111111111111111111* +L045126 111111111111111111111111111111111111111111111111111111111111111111* L045192 111111111111111111111111111111111111111111111111111111111111111111* L045258 111111111111111111111111111111111111111111111111111111111111111111* L045324 111111111111111111111111111111111111111111111111111111111111111111* @@ -903,23 +904,23 @@ L045390 111111111111111111111111111111111111111111111111111111111111111111* L045456 111111111111111111111111111111111111111111111111111111111111111111* L045522 000000000000000000000000000000000000000000000000000000000000000000* -L045588 111111111111111111111111111101111111110111111111111111111111111111* -L045654 111111110111111111111111111111111111111111111111111111111111111111* -L045720 101111111111111111111111111111111111111111111111111111111111111111* -L045786 111011111111111111111111111101111111111111111111111111111111111111* -L045852 111111111111111111111111111101111111111111111101111111111111111111* -L045918 111111111111111111011011111111111111111111111111111111111111111111* -L045984 110111111111111111011111111111111111111111111111111111111111111111* -L046050 111011111111111111100111111111111111111111111111111111111111111111* +L045588 111111111111111111111111110111111111111111111111111111111111111111* +L045654 111111111111111111111111111111111111111111111111111111111111111111* +L045720 111111111111111111111111111111111111111111111111111111111111111111* +L045786 111111111111111111111111111111111111111111111111111111111111111111* +L045852 111111111111111111111111111111111111111111111111111111111111111111* +L045918 111110111111111111011111111111111111111111111110111111111111111111* +L045984 111111111111111111101111111111111111111111111101111111111111111111* +L046050 000000000000000000000000000000000000000000000000000000000000000000* L046116 000000000000000000000000000000000000000000000000000000000000000000* L046182 000000000000000000000000000000000000000000000000000000000000000000* L046248 000000000000000000000000000000000000000000000000000000000000000000* -L046314 111111111111111111111011110111111111111111111111111111111111111111* -L046380 000000000000000000000000000000000000000000000000000000000000000000* -L046446 000000000000000000000000000000000000000000000000000000000000000000* -L046512 000000000000000000000000000000000000000000000000000000000000000000* -L046578 000000000000000000000000000000000000000000000000000000000000000000* +L046314 111111111111111111111111111111111111111111111111111111111111111111* +L046380 111111111111111111111111111111111111111111111111111111111111111111* +L046446 111111111111111111111111111111111111111111111111111111111111111111* +L046512 111111111111111111111111111111111111111111111111111111111111111111* +L046578 111111111111111111111111111111111111111111111111111111111111111111* L046644 111111111111111111111111111111111111111111111111111111111111111111* L046710 111111111111111111111111111111111111111111111111111111111111111111* L046776 111111111111111111111111111111111111111111111111111111111111111111* @@ -930,75 +931,75 @@ L046974 000000000000000000000000000000000000000000000000000000000000000000* L047106 0010* L047110 00100110010000* -L047124 10100111011110* -L047138 10101110000100* +L047124 00100110011110* +L047138 10100110010100* L047152 11100011111111* L047166 10100111011001* L047180 10101110000011* L047194 00010110010000* L047208 11101111110011* L047222 00110110010001* -L047236 10101110000011* -L047250 11101100000000* -L047264 11101011110010* -L047278 10101110000000* +L047236 00100110010011* +L047250 11011011110000* +L047264 11111111110010* +L047278 00110110010000* L047292 10100110010011* -L047306 11001111110000* -L047320 11110011111110* +L047306 11010011110000* +L047320 11111011111110* NOTE BLOCK 7 * L047334 - 111111111111111111110111111111111111111110111111111111111111111111 - 111111111101111111111111111111111111111111111111111111111111111111 - 111111111111101111111111111111111111111111111111111111111011111111 + 111111111011111011111111111111111111111111111111111111111111111111 + 111111111101111111111111111111110111111111111111111111111110111111 + 111111111111101111111111111111111111111111111110111111111011111111 111011111111111110111111111111111111111111111111111111111111111111 111111111111111111111111111111111111111111111111111111111111111111 - 111111110111111111111111011111111111111111011111111111111111111111 - 111111101111110111111101111111111101111111111111111111101111111111 - 111111111111111111101111111011111111111111111110111111111111111111 - 101111111111111111111111111111011111111011111111111111111111101111* + 111111111111111111111111011111111111101011111111111111111111111101 + 111111101111111111111101111111111101111111111111111111101111111111 + 111111111111111111101111111011111111111110101111011111111111111111 + 101111111111111111111011111110111111111111111111111111111111101111* L047928 000000000000000000000000000000000000000000000000000000000000000000* -L047994 110111110111011101101110101111111110111101111111111111111111111111* -L048060 111111111111111111101111111111111111111110111111111111111111101111* +L047994 110111110111011101101110101111111110111111111111111111111111111101* +L048060 111111111111111111101111111111111111111111111111111111111111101111* L048126 000000000000000000000000000000000000000000000000000000000000000000* L048192 000000000000000000000000000000000000000000000000000000000000000000* L048258 000000000000000000000000000000000000000000000000000000000000000000* -L048324 111111111111111111011111111111111111111111111111111111111111111111* -L048390 111111111110111111111111111111111111111101111111111111111111111111* -L048456 110111110111011101111110101111111110111101111111111111111111111111* -L048522 111111111111111111111111111111111111110110111111111111111111111111* -L048588 000000000000000000000000000000000000000000000000000000000000000000* +L048324 111111111110111111111111110111111111111111111111111111111011111111* +L048390 111111111111111111110111111101111111111111111111111111111111111111* +L048456 111111111111111111110111111111111111111111111101111111111111111111* +L048522 111111111111111111110111111111111111101111111111111111111111111111* +L048588 111111111111111111111111111111111111111111011111011111110111111111* L048654 000000000000000000000000000000000000000000000000000000000000000000* -L048720 111111111111111111111111111111111111111111111111111111111111111111* -L048786 111111111111111111111111111111111111111111111111111111111111111111* -L048852 111111111111111111111111111111111111111111111111111111111111111111* -L048918 111111111111111111111111111111111111111111111111111111111111111111* -L048984 111111111111111111111111111111111111111111111111111111111111111111* -L049050 111111111111111111111111111111111111111111111111111111111111111111* -L049116 111111111111111111111111111111111111111111111111111111111111111111* -L049182 111111111111111111111111111111111111111111111111111111111111111111* -L049248 111111111111111111111111111111111111111111111111111111111111111111* -L049314 111111111111111111111111111111111111111111111111111111111111111111* +L048720 111111111111111111111111111111110111111011111111111111011111111111* +L048786 111111111111111111011111111111111111111111111111111111111111111111* +L048852 111111111110111111111111111101111111111111111111111111111111111111* +L048918 111111111011111111111111111101111111111111111111111111111111111111* +L048984 110111111111011101111110101101111110111111111111111111111111111101* +L049050 111111111110111111111111110111111111111111111111111111111111111111* +L049116 111111111111111111111011111101111111111111111111111111111111111111* +L049182 000000000000000000000000000000000000000000000000000000000000000000* +L049248 000000000000000000000000000000000000000000000000000000000000000000* +L049314 000000000000000000000000000000000000000000000000000000000000000000* L049380 111111111111111111111111111111111111111111111111111111111111111111* -L049446 111111110111111111111111111111111111111111111101111111111111111111* -L049512 111111110111111111111111111111111111111111101111111111110111111111* +L049446 111111111111111111111111111111111111111101111111111111111111111101* +L049512 111111111111111011111111111111111111111111111111111111110111111101* L049578 000000000000000000000000000000000000000000000000000000000000000000* L049644 000000000000000000000000000000000000000000000000000000000000000000* L049710 000000000000000000000000000000000000000000000000000000000000000000* -L049776 111111111111111111111111110111111111111111111111111111110111111111* -L049842 111111111111110111111111111111111111111111111111111111010111111111* +L049776 111111111101111111111011110111111111111111111111111111111011111111* +L049842 111111111111111111110111111110111111011111111110111111111111111111* L049908 000000000000000000000000000000000000000000000000000000000000000000* L049974 000000000000000000000000000000000000000000000000000000000000000000* L050040 000000000000000000000000000000000000000000000000000000000000000000* L050106 000000000000000000000000000000000000000000000000000000000000000000* -L050172 111111111111111111111111111111111111111111111111111111111111111111* -L050238 111111111111111111111111111111111111111111111111111111111111111111* -L050304 111111111111111111111111111111111111111111111111111111111111111111* -L050370 111111111111111111111111111111111111111111111111111111111111111111* -L050436 111111111111111111111111111111111111111111111111111111111111111111* +L050172 111111111111111111111111111111110111110111111111111111111011111111* +L050238 111111111111111111111111111111110111111111111111111111101011111111* +L050304 111111111111111111111111111111111111111111011111101111111111111111* +L050370 111111111111111111111111111111111111111111011111111111111011111111* +L050436 000000000000000000000000000000000000000000000000000000000000000000* L050502 111111111111111111111111111111111111111111111111111111111111111111* L050568 111111111111111111111111111111111111111111111111111111111111111111* L050634 111111111111111111111111111111111111111111111111111111111111111111* @@ -1006,21 +1007,21 @@ L050700 111111111111111111111111111111111111111111111111111111111111111111* L050766 111111111111111111111111111111111111111111111111111111111111111111* L050832 111111111101111111111111111111111111111111111111111111111111111111* -L050898 111111101111111111101111111111111111111111111111111111111111111111* -L050964 111111111111111111110111111111011111111111111111111111111011111111* -L051030 000000000000000000000000000000000000000000000000000000000000000000* -L051096 000000000000000000000000000000000000000000000000000000000000000000* -L051162 000000000000000000000000000000000000000000000000000000000000000000* -L051228 111111111111111111110111111111011111111111111111111111111011111111* -L051294 111111111111111011111111111111111111111111111111111111011111111111* -L051360 111111111111111111111111111111111111111111111111111111011011111111* -L051426 000000000000000000000000000000000000000000000000000000000000000000* -L051492 000000000000000000000000000000000000000000000000000000000000000000* +L050898 111111111111111111111111111111111111111111111111111111111111111111* +L050964 111111111111111111111111111111111111111111111111111111111111111111* +L051030 111111111111111111111111111111111111111111111111111111111111111111* +L051096 111111111111111111111111111111111111111111111111111111111111111111* +L051162 111111111111111111111111111111111111111111111111111111111111111111* +L051228 111111111111111111111111111111111111011111111111111111111111111111* +L051294 111111111111111111111111111111111111111111111111111111111101111111* +L051360 000000000000000000000000000000000000000000000000000000000000000000* +L051426 111111101111111111101111111111111111111111111111111111111111111111* +L051492 111111111111111111111111111111110111111011111111111111011111111111* L051558 111111111101111111111111111111111111111111111111111111111111111111* -L051624 111111111111111111111111111111111111111111111111111111111111111111* -L051690 111111111111111111111111111111111111111111111111111111111111111111* -L051756 111111111111111111111111111111111111111111111111111111111111111111* +L051624 111111111111111111111111111111111111111111111101111111111111111111* +L051690 111111111111111111111111111111111111111111111111111111111101111111* +L051756 000000000000000000000000000000000000000000000000000000000000000000* L051822 111111111111111111111111111111111111111111111111111111111111111111* L051888 111111111111111111111111111111111111111111111111111111111111111111* L051954 111111111111111111111111111111111111111111111111111111111111111111* @@ -1035,16 +1036,16 @@ L052416 111111111111111111111111111111111111111111111111111111111111111111* L052482 111111111111111111111111111111111111111111111111111111111111111111* L052548 111111111111111111111111111111111111111111111111111111111111111111* L052614 111111111111111111111111111111111111111111111111111111111111111111* -L052680 111111111111111111111111111111111111111111111111111111111111111111* -L052746 111111111111111111111111111111111111111111111111111111111111111111* -L052812 111111111111111111111111111111111111111111111111111111111111111111* +L052680 111111111111111111111111111111111111111111111111111111011111111111* +L052746 111111111111111111111111111111111111111111111111111111111101111111* +L052812 000000000000000000000000000000000000000000000000000000000000000000* L052878 111111111111111111111111111111111111111111111111111111111111111111* L052944 111111111111111111111111111111111111111111111111111111111111111111* L053010 111111111111111111111111111111111111111111111111111111111111111111* -L053076 111111111111111111111111111111111111111111111111111111111111111111* -L053142 111111111111111111111111111111111111111111111111111111111111111111* -L053208 111111111111111111111111111111111111111111111111111111111111111111* +L053076 000000000000000000000000000000000000000000000000000000000000000000* +L053142 000000000000000000000000000000000000000000000000000000000000000000* +L053208 101111111111111111111111111111111111111111111111111111111111111111* L053274 111111111111111111111111111111111111111111111111111111111111111111* L053340 111111111111111111111111111111111111111111111111111111111111111111* L053406 111111111111111111111111111111111111111111111111111111111111111111* @@ -1058,20 +1059,20 @@ L053736 L053868 0010* L053872 11100110011000* L053886 10100110010010* -L053900 11011111110000* -L053914 11111011110011* -L053928 10100110010000* -L053942 10100110011110* -L053956 11011111110001* -L053970 11111011110011* -L053984 11100110010000* -L053998 10100100010010* -L054012 11010011110100* -L054026 11111011111111* +L053900 10100110010000* +L053914 11110011110011* +L053928 10100110010001* +L053942 10100100011111* +L053956 10100100010000* +L053970 11101111110011* +L053984 11110110010001* +L053998 00111110000011* +L054012 00011110000100* +L054026 11101011111110* L054040 00111111111000* -L054054 11000011110010* -L054068 11111011110101* -L054082 11111111111111* +L054054 00001110000011* +L054068 00011110100100* +L054082 11100011111110* E1 0 00000000 @@ -1091,6 +1092,6 @@ E1 00000000 1 * -C52A9* +C5CE6* U00000000000000000000000000000000* -BBAB +CCD1 diff --git a/Logic/68030_tk.lco b/Logic/68030_tk.lco index 3f381a2..9167295 100644 --- a/Logic/68030_tk.lco +++ b/Logic/68030_tk.lco @@ -16,8 +16,8 @@ RCS = "$Revision: 1.2 $"; Parent = m4a5.lci; SDS_File = m4a5.sds; Design = 68030_tk.tt4; -DATE = 5/22/14; -TIME = 14:56:14; +DATE = 5/24/14; +TIME = 11:44:13; Source_Format = Pure_VHDL; Type = TT2; Pre_Fit_Time = 1; @@ -84,34 +84,34 @@ AS_030 = pin,82,-,H,-; DS_030 = pin,98,-,A,-; nEXP_SPACE = pin,14,-,-,-; BERR = pin,41,-,E,-; -SIZE_0_ = pin,70,-,G,-; BG_030 = pin,21,-,C,-; +BGACK_000 = pin,28,-,D,-; +CLK_030 = pin,64,-,-,-; +CLK_000 = pin,11,-,-,-; +SIZE_0_ = pin,70,-,G,-; +CLK_OSZI = pin,61,-,-,-; A_30_ = pin,5,-,B,-; +CLK_DIV_OUT = pin,65,-,G,-; A_29_ = pin,6,-,B,-; A_28_ = pin,15,-,C,-; -BGACK_000 = pin,28,-,D,-; A_27_ = pin,16,-,C,-; -CLK_030 = pin,64,-,-,-; A_26_ = pin,17,-,C,-; -CLK_000 = pin,11,-,-,-; +AVEC = pin,92,-,A,-; A_25_ = pin,18,-,C,-; -CLK_OSZI = pin,61,-,-,-; +AVEC_EXP = pin,22,-,C,-; A_24_ = pin,19,-,C,-; -CLK_DIV_OUT = pin,65,-,G,-; A_23_ = pin,84,-,H,-; +VPA = pin,36,-,-,-; A_22_ = pin,85,-,H,-; A_21_ = pin,94,-,A,-; +RST = pin,86,-,-,-; A_20_ = pin,93,-,A,-; -AVEC = pin,92,-,A,-; A_19_ = pin,97,-,A,-; -AVEC_EXP = pin,22,-,C,-; +RW = pin,71,-,G,-; A_18_ = pin,95,-,A,-; A_17_ = pin,59,-,F,-; -VPA = pin,36,-,-,-; -A_16_ = pin,96,-,A,-; -RST = pin,86,-,-,-; -RW = pin,71,-,G,-; AMIGA_BUS_DATA_DIR = pin,48,-,E,-; +A_16_ = pin,96,-,A,-; AMIGA_BUS_ENABLE_LOW = pin,20,-,C,-; CIIN = pin,47,-,E,-; A_0_ = pin,69,-,G,-; @@ -135,29 +135,31 @@ RESET = pin,3,-,B,-; AMIGA_BUS_ENABLE = pin,34,-,D,-; IPL_030_1_ = pin,7,-,B,-; IPL_030_0_ = pin,8,-,B,-; -cpu_est_0_ = node,-,-,G,13; -cpu_est_1_ = node,-,-,G,1; -inst_AS_030_000_SYNC = node,-,-,H,1; -inst_DTACK_SYNC = node,-,-,F,0; -inst_VPA_D = node,-,-,B,9; -inst_VPA_SYNC = node,-,-,G,10; +cpu_est_0_ = node,-,-,D,6; +cpu_est_1_ = node,-,-,D,9; +inst_AS_030_000_SYNC = node,-,-,H,2; +inst_DTACK_SYNC = node,-,-,A,0; +inst_VPA_D = node,-,-,G,1; +inst_VPA_SYNC = node,-,-,F,0; inst_CLK_000_D0 = node,-,-,G,8; -inst_CLK_000_D1 = node,-,-,D,13; +inst_CLK_000_D1 = node,-,-,G,12; inst_CLK_000_D2 = node,-,-,G,6; -inst_CLK_OUT_PRE = node,-,-,A,0; -SM_AMIGA_6_ = node,-,-,G,12; +inst_CLK_000_D5 = node,-,-,H,13; +inst_CLK_OUT_PRE = node,-,-,G,9; +SM_AMIGA_6_ = node,-,-,H,5; +SM_AMIGA_5_ = node,-,-,D,14; cpu_est_2_ = node,-,-,D,2; -CLK_REF_0_ = node,-,-,D,6; -CLK_REF_1_ = node,-,-,B,2; -SM_AMIGA_7_ = node,-,-,H,5; -SM_AMIGA_4_ = node,-,-,B,5; -SM_AMIGA_1_ = node,-,-,B,13; -CLK_CNT_0_ = node,-,-,A,12; -CLK_CNT_1_ = node,-,-,A,8; -SM_AMIGA_3_ = node,-,-,G,9; -SM_AMIGA_5_ = node,-,-,G,2; +CLK_REF_1_ = node,-,-,H,14; +SM_AMIGA_7_ = node,-,-,H,1; +inst_CLK_000_D3 = node,-,-,H,10; +SM_AMIGA_4_ = node,-,-,D,10; +inst_CLK_000_D4 = node,-,-,H,9; +CLK_CNT_0_ = node,-,-,G,2; +CLK_CNT_1_ = node,-,-,G,13; +SM_AMIGA_3_ = node,-,-,B,5; +SM_AMIGA_1_ = node,-,-,B,9; SM_AMIGA_2_ = node,-,-,G,5; -SM_AMIGA_0_ = node,-,-,H,9; +SM_AMIGA_0_ = node,-,-,H,6; [GROUP ASSIGNMENTS] Layer = OFF; diff --git a/Logic/68030_tk.out b/Logic/68030_tk.out index 55004bf..522b200 100644 --- a/Logic/68030_tk.out +++ b/Logic/68030_tk.out @@ -57376,4 +57376,5690 @@ 5 A_29_ 1 -1 -1 1 4 5 -1 4 A_30_ 1 -1 -1 1 4 4 -1 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +96 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 321 7 1 3 80 -1 3 0 21 + 29 DTACK 5 -1 3 1 5 29 -1 1 0 21 + 30 LDS_000 5 324 3 0 30 -1 12 0 21 + 31 UDS_000 5 323 3 0 31 -1 8 0 21 + 65 E 5 328 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 330 3 0 33 -1 3 0 20 + 28 BG_000 5 325 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 320 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 319 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 318 1 0 6 -1 3 0 21 + 82 BGACK_030 5 326 7 0 82 -1 2 0 21 + 77 FPU_CS 5 327 7 0 77 -1 2 0 21 + 34 VMA 5 329 3 0 34 -1 2 0 21 + 32 AS_000 5 322 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 1 6 0 1 3 5 6 7 -1 -1 1 0 20 + 294 cpu_est_0_ 3 -1 1 4 0 1 3 6 -1 -1 3 0 20 + 301 inst_CLK_000_D1 3 -1 7 4 1 3 6 7 -1 -1 1 0 20 + 296 inst_AS_030_000_SYNC 3 -1 7 3 3 6 7 -1 -1 4 0 21 + 295 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 20 + 328 RN_E 3 65 6 3 0 3 6 65 -1 3 0 21 + 313 SM_AMIGA_3_ 3 -1 6 3 0 5 6 -1 -1 3 0 20 + 305 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 3 1 20 + 303 inst_CLK_OUT_PRE 3 -1 6 3 1 6 7 -1 -1 3 1 21 + 327 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 298 inst_VPA_D 3 -1 7 3 0 3 5 -1 -1 1 0 20 + 304 SM_AMIGA_6_ 3 -1 3 2 3 6 -1 -1 4 0 21 + 316 SM_AMIGA_2_ 3 -1 6 2 1 6 -1 -1 3 0 20 + 314 SM_AMIGA_1_ 3 -1 1 2 1 7 -1 -1 3 0 21 + 329 RN_VMA 3 34 3 2 0 3 34 -1 2 0 21 + 326 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 322 RN_AS_000 3 32 3 2 1 3 32 -1 2 0 21 + 309 SM_AMIGA_4_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 307 SM_AMIGA_7_ 3 -1 1 2 1 3 -1 -1 2 0 21 + 299 inst_VPA_SYNC 3 -1 0 2 0 6 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 5 2 5 6 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 6 2 3 6 -1 -1 1 0 21 + 324 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 323 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 330 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 325 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 321 RN_DSACK_1_ 3 80 7 1 7 80 -1 3 0 21 + 320 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 319 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 318 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 317 SM_AMIGA_0_ 3 -1 1 1 1 -1 -1 3 0 21 + 315 SM_AMIGA_5_ 3 -1 6 1 6 -1 -1 2 0 20 + 312 CLK_CNT_1_ 3 -1 6 1 6 -1 -1 2 0 21 + 311 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 2 0 21 + 310 inst_CLK_000_D3 3 -1 6 1 1 -1 -1 1 0 21 + 308 inst_CLK_000_D4 3 -1 1 1 7 -1 -1 1 0 20 + 306 CLK_REF_1_ 3 -1 3 1 6 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 6 0 1 3 5 6 7 60 -1 + 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 3 5 7 81 -1 + 10 CLK_000 1 -1 -1 3 0 1 5 10 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 7 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +97 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 322 7 1 3 80 -1 3 0 21 + 29 DTACK 5 -1 3 1 0 29 -1 1 0 21 + 30 LDS_000 5 325 3 0 30 -1 12 0 21 + 31 UDS_000 5 324 3 0 31 -1 8 0 21 + 65 E 5 329 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 331 3 0 33 -1 3 0 20 + 28 BG_000 5 326 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 321 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 320 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 319 1 0 6 -1 3 0 21 + 82 BGACK_030 5 327 7 0 82 -1 2 0 21 + 77 FPU_CS 5 328 7 0 77 -1 2 0 21 + 34 VMA 5 330 3 0 34 -1 2 0 21 + 32 AS_000 5 323 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 6 6 0 1 3 5 6 7 -1 -1 1 0 21 + 301 inst_CLK_000_D1 3 -1 3 4 1 3 6 7 -1 -1 1 0 20 + 296 inst_AS_030_000_SYNC 3 -1 7 3 3 6 7 -1 -1 4 0 21 + 295 cpu_est_1_ 3 -1 6 3 3 5 6 -1 -1 4 0 21 + 329 RN_E 3 65 6 3 3 5 6 65 -1 3 0 21 + 314 SM_AMIGA_3_ 3 -1 1 3 0 1 5 -1 -1 3 0 21 + 305 cpu_est_2_ 3 -1 6 3 3 5 6 -1 -1 3 1 21 + 303 inst_CLK_OUT_PRE 3 -1 1 3 1 6 7 -1 -1 3 1 20 + 294 cpu_est_0_ 3 -1 3 3 3 5 6 -1 -1 3 0 20 + 328 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 309 SM_AMIGA_4_ 3 -1 0 3 0 1 3 -1 -1 2 0 21 + 298 inst_VPA_D 3 -1 6 3 0 3 5 -1 -1 1 0 21 + 304 SM_AMIGA_6_ 3 -1 3 2 3 6 -1 -1 4 0 21 + 317 SM_AMIGA_2_ 3 -1 1 2 1 6 -1 -1 3 0 21 + 315 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 3 0 20 + 330 RN_VMA 3 34 3 2 3 5 34 -1 2 0 21 + 327 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 323 RN_AS_000 3 32 3 2 3 6 32 -1 2 0 21 + 316 SM_AMIGA_5_ 3 -1 6 2 0 6 -1 -1 2 0 20 + 307 SM_AMIGA_7_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 299 inst_VPA_SYNC 3 -1 5 2 1 5 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 0 2 0 1 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 7 2 3 6 -1 -1 1 0 20 + 325 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 324 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 331 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 326 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 322 RN_DSACK_1_ 3 80 7 1 7 80 -1 3 0 21 + 321 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 320 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 319 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 318 SM_AMIGA_0_ 3 -1 6 1 6 -1 -1 3 0 20 + 312 CLK_CNT_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 311 CLK_CNT_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 313 inst_CLK_000_D4 3 -1 6 1 1 -1 -1 1 0 21 + 310 inst_CLK_000_D3 3 -1 3 1 6 -1 -1 1 0 20 + 308 inst_CLK_000_D5 3 -1 1 1 7 -1 -1 1 0 20 + 306 CLK_REF_1_ 3 -1 7 1 1 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 6 0 1 3 5 6 7 60 -1 + 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 3 5 7 81 -1 + 10 CLK_000 1 -1 -1 3 0 5 6 10 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +96 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 319 7 1 3 80 -1 3 0 21 + 29 DTACK 5 -1 3 1 5 29 -1 1 0 21 + 30 LDS_000 5 322 3 0 30 -1 12 0 21 + 31 UDS_000 5 321 3 0 31 -1 8 0 21 + 65 E 5 326 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 328 3 0 33 -1 3 0 20 + 28 BG_000 5 323 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 318 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 330 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 329 1 0 6 -1 3 0 21 + 82 BGACK_030 5 324 7 0 82 -1 2 0 21 + 77 FPU_CS 5 325 7 0 77 -1 2 0 21 + 34 VMA 5 327 3 0 34 -1 2 0 21 + 32 AS_000 5 320 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 1 6 0 1 3 5 6 7 -1 -1 1 0 20 + 294 cpu_est_0_ 3 -1 1 4 0 1 3 6 -1 -1 3 0 20 + 301 inst_CLK_000_D1 3 -1 7 4 1 3 6 7 -1 -1 1 0 20 + 296 inst_AS_030_000_SYNC 3 -1 7 3 3 6 7 -1 -1 4 0 21 + 295 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 20 + 326 RN_E 3 65 6 3 0 3 6 65 -1 3 0 21 + 313 SM_AMIGA_3_ 3 -1 6 3 0 5 6 -1 -1 3 0 20 + 306 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 3 1 20 + 303 inst_CLK_OUT_PRE 3 -1 6 3 1 6 7 -1 -1 3 1 21 + 325 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 298 inst_VPA_D 3 -1 7 3 0 3 5 -1 -1 1 0 20 + 304 SM_AMIGA_6_ 3 -1 3 2 3 6 -1 -1 4 0 21 + 316 SM_AMIGA_2_ 3 -1 6 2 1 6 -1 -1 3 0 20 + 314 SM_AMIGA_1_ 3 -1 1 2 1 7 -1 -1 3 0 21 + 327 RN_VMA 3 34 3 2 0 3 34 -1 2 0 21 + 324 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 320 RN_AS_000 3 32 3 2 1 3 32 -1 2 0 21 + 309 SM_AMIGA_4_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 308 SM_AMIGA_7_ 3 -1 1 2 1 3 -1 -1 2 0 21 + 299 inst_VPA_SYNC 3 -1 0 2 0 6 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 5 2 5 6 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 6 2 3 6 -1 -1 1 0 21 + 322 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 321 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 330 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 329 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 328 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 323 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 319 RN_DSACK_1_ 3 80 7 1 7 80 -1 3 0 21 + 318 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 317 SM_AMIGA_0_ 3 -1 1 1 1 -1 -1 3 0 21 + 315 SM_AMIGA_5_ 3 -1 6 1 6 -1 -1 2 0 20 + 312 CLK_CNT_1_ 3 -1 6 1 6 -1 -1 2 0 21 + 311 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 2 0 21 + 310 inst_CLK_000_D3 3 -1 6 1 1 -1 -1 1 0 21 + 307 CLK_REF_1_ 3 -1 3 1 6 -1 -1 1 0 20 + 305 inst_CLK_000_D4 3 -1 1 1 7 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 6 0 1 3 5 6 7 60 -1 + 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 3 5 7 81 -1 + 10 CLK_000 1 -1 -1 3 0 1 5 10 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 7 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +96 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 321 7 1 3 80 -1 3 0 21 + 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 + 30 LDS_000 5 324 3 0 30 -1 12 0 21 + 31 UDS_000 5 323 3 0 31 -1 8 0 21 + 65 E 5 328 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 330 3 0 33 -1 3 0 20 + 28 BG_000 5 325 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 319 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 320 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 318 1 0 6 -1 3 0 21 + 82 BGACK_030 5 326 7 0 82 -1 2 0 21 + 77 FPU_CS 5 327 7 0 77 -1 2 0 21 + 34 VMA 5 329 3 0 34 -1 2 0 21 + 32 AS_000 5 322 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 301 inst_CLK_000_D1 3 -1 3 5 0 1 3 6 7 -1 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 1 5 0 1 3 6 7 -1 -1 1 0 20 + 296 inst_AS_030_000_SYNC 3 -1 7 4 0 1 3 7 -1 -1 4 0 21 + 305 SM_AMIGA_6_ 3 -1 0 3 0 1 3 -1 -1 4 0 21 + 304 inst_CLK_OUT_PRE 3 -1 6 3 1 6 7 -1 -1 3 1 21 + 327 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 310 SM_AMIGA_4_ 3 -1 1 3 1 3 6 -1 -1 2 0 21 + 309 SM_AMIGA_7_ 3 -1 1 3 0 1 3 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 3 3 0 1 3 -1 -1 1 0 20 + 295 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 20 + 328 RN_E 3 65 6 2 3 6 65 -1 3 0 21 + 316 SM_AMIGA_2_ 3 -1 6 2 1 6 -1 -1 3 0 20 + 314 SM_AMIGA_1_ 3 -1 1 2 1 7 -1 -1 3 0 21 + 307 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21 + 294 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 3 0 21 + 329 RN_VMA 3 34 3 2 3 6 34 -1 2 0 21 + 326 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 322 RN_AS_000 3 32 3 2 1 3 32 -1 2 0 21 + 298 inst_VPA_D 3 -1 7 2 3 6 -1 -1 1 0 20 + 324 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 323 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 330 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 325 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 321 RN_DSACK_1_ 3 80 7 1 7 80 -1 3 0 21 + 320 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 319 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 318 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 317 SM_AMIGA_0_ 3 -1 1 1 1 -1 -1 3 0 21 + 313 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 3 0 20 + 315 SM_AMIGA_5_ 3 -1 1 1 1 -1 -1 2 0 21 + 312 CLK_CNT_1_ 3 -1 6 1 6 -1 -1 2 0 21 + 311 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 2 0 21 + 299 inst_VPA_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 297 inst_DTACK_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 308 CLK_REF_1_ 3 -1 7 1 6 -1 -1 1 0 20 + 306 inst_CLK_000_D3 3 -1 3 1 7 -1 -1 1 0 20 + 303 inst_CLK_000_D4 3 -1 7 1 3 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 5 0 1 3 6 7 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 3 3 6 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 10 CLK_000 1 -1 -1 2 1 6 10 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 7 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +96 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 321 7 1 3 80 -1 3 0 21 + 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 + 30 LDS_000 5 324 3 0 30 -1 12 0 21 + 31 UDS_000 5 323 3 0 31 -1 8 0 21 + 65 E 5 328 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 330 3 0 33 -1 3 0 20 + 28 BG_000 5 325 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 319 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 320 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 318 1 0 6 -1 3 0 21 + 82 BGACK_030 5 326 7 0 82 -1 2 0 21 + 77 FPU_CS 5 327 7 0 77 -1 2 0 21 + 34 VMA 5 329 3 0 34 -1 2 0 21 + 32 AS_000 5 322 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 6 5 0 1 3 6 7 -1 -1 1 0 21 + 302 inst_CLK_000_D3 3 -1 3 4 0 1 3 7 -1 -1 1 0 20 + 301 inst_CLK_000_D1 3 -1 7 4 1 3 6 7 -1 -1 1 0 20 + 305 SM_AMIGA_6_ 3 -1 7 3 0 3 7 -1 -1 4 0 21 + 296 inst_AS_030_000_SYNC 3 -1 7 3 0 3 7 -1 -1 4 0 21 + 314 SM_AMIGA_1_ 3 -1 6 3 1 6 7 -1 -1 3 0 20 + 304 inst_CLK_OUT_PRE 3 -1 1 3 1 6 7 -1 -1 3 1 20 + 327 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 308 SM_AMIGA_7_ 3 -1 1 3 1 3 7 -1 -1 2 0 21 + 309 inst_CLK_000_D2 3 -1 6 3 0 3 7 -1 -1 1 0 21 + 295 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 20 + 328 RN_E 3 65 6 2 3 6 65 -1 3 0 21 + 306 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 1 20 + 294 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 20 + 329 RN_VMA 3 34 3 2 3 6 34 -1 2 0 21 + 326 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 322 RN_AS_000 3 32 3 2 1 3 32 -1 2 0 21 + 315 SM_AMIGA_5_ 3 -1 0 2 0 6 -1 -1 2 0 21 + 310 SM_AMIGA_4_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 298 inst_VPA_D 3 -1 7 2 3 6 -1 -1 1 0 20 + 324 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 323 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 330 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 325 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 321 RN_DSACK_1_ 3 80 7 1 7 80 -1 3 0 21 + 320 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 319 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 318 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 317 SM_AMIGA_0_ 3 -1 1 1 1 -1 -1 3 0 21 + 316 SM_AMIGA_2_ 3 -1 6 1 6 -1 -1 3 0 20 + 313 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 3 0 20 + 312 CLK_CNT_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 311 CLK_CNT_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 299 inst_VPA_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 297 inst_DTACK_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 307 CLK_REF_1_ 3 -1 6 1 1 -1 -1 1 0 20 + 303 inst_CLK_000_D4 3 -1 1 1 3 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 5 0 1 3 6 7 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 3 3 6 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 7 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 6 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +96 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 321 7 1 3 80 -1 3 0 21 + 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 + 30 LDS_000 5 324 3 0 30 -1 12 0 21 + 31 UDS_000 5 323 3 0 31 -1 8 0 21 + 65 E 5 328 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 330 3 0 33 -1 3 0 20 + 28 BG_000 5 325 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 319 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 320 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 318 1 0 6 -1 3 0 21 + 82 BGACK_030 5 326 7 0 82 -1 2 0 21 + 77 FPU_CS 5 327 7 0 77 -1 2 0 21 + 34 VMA 5 329 3 0 34 -1 2 0 21 + 32 AS_000 5 322 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 301 inst_CLK_000_D1 3 -1 3 5 0 1 3 6 7 -1 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 1 5 0 1 3 6 7 -1 -1 1 0 20 + 296 inst_AS_030_000_SYNC 3 -1 7 4 0 1 3 7 -1 -1 4 0 21 + 305 SM_AMIGA_6_ 3 -1 0 3 0 1 3 -1 -1 4 0 21 + 304 inst_CLK_OUT_PRE 3 -1 6 3 1 6 7 -1 -1 3 1 21 + 327 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 310 SM_AMIGA_4_ 3 -1 1 3 1 3 6 -1 -1 2 0 21 + 309 SM_AMIGA_7_ 3 -1 1 3 0 1 3 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 3 3 0 1 3 -1 -1 1 0 20 + 295 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 20 + 328 RN_E 3 65 6 2 3 6 65 -1 3 0 21 + 316 SM_AMIGA_2_ 3 -1 6 2 1 6 -1 -1 3 0 20 + 314 SM_AMIGA_1_ 3 -1 1 2 1 7 -1 -1 3 0 21 + 307 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21 + 294 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 3 0 21 + 329 RN_VMA 3 34 3 2 3 6 34 -1 2 0 21 + 326 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 322 RN_AS_000 3 32 3 2 1 3 32 -1 2 0 21 + 298 inst_VPA_D 3 -1 7 2 3 6 -1 -1 1 0 20 + 324 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 323 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 330 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 325 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 321 RN_DSACK_1_ 3 80 7 1 7 80 -1 3 0 21 + 320 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 319 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 318 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 317 SM_AMIGA_0_ 3 -1 1 1 1 -1 -1 3 0 21 + 313 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 3 0 20 + 315 SM_AMIGA_5_ 3 -1 1 1 1 -1 -1 2 0 21 + 312 CLK_CNT_1_ 3 -1 6 1 6 -1 -1 2 0 21 + 311 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 2 0 21 + 299 inst_VPA_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 297 inst_DTACK_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 308 CLK_REF_1_ 3 -1 7 1 6 -1 -1 1 0 20 + 306 inst_CLK_000_D3 3 -1 3 1 7 -1 -1 1 0 20 + 303 inst_CLK_000_D4 3 -1 7 1 3 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 5 0 1 3 6 7 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 3 3 6 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 10 CLK_000 1 -1 -1 2 1 6 10 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 7 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +96 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 321 7 1 3 80 -1 3 0 21 + 29 DTACK 5 -1 3 1 5 29 -1 1 0 21 + 30 LDS_000 5 324 3 0 30 -1 12 0 21 + 31 UDS_000 5 323 3 0 31 -1 8 0 21 + 65 E 5 328 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 330 3 0 33 -1 3 0 20 + 28 BG_000 5 325 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 320 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 319 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 318 1 0 6 -1 3 0 21 + 82 BGACK_030 5 326 7 0 82 -1 2 0 21 + 77 FPU_CS 5 327 7 0 77 -1 2 0 21 + 34 VMA 5 329 3 0 34 -1 2 0 21 + 32 AS_000 5 322 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 1 6 0 1 3 5 6 7 -1 -1 1 0 20 + 294 cpu_est_0_ 3 -1 1 4 0 1 3 6 -1 -1 3 0 20 + 301 inst_CLK_000_D1 3 -1 7 4 1 3 6 7 -1 -1 1 0 20 + 296 inst_AS_030_000_SYNC 3 -1 7 3 3 6 7 -1 -1 4 0 21 + 295 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 20 + 328 RN_E 3 65 6 3 0 3 6 65 -1 3 0 21 + 313 SM_AMIGA_3_ 3 -1 6 3 0 5 6 -1 -1 3 0 20 + 306 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 3 1 20 + 304 inst_CLK_OUT_PRE 3 -1 6 3 1 6 7 -1 -1 3 1 21 + 327 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 298 inst_VPA_D 3 -1 7 3 0 3 5 -1 -1 1 0 20 + 305 SM_AMIGA_6_ 3 -1 3 2 3 6 -1 -1 4 0 21 + 316 SM_AMIGA_2_ 3 -1 6 2 1 6 -1 -1 3 0 20 + 314 SM_AMIGA_1_ 3 -1 1 2 1 7 -1 -1 3 0 21 + 329 RN_VMA 3 34 3 2 0 3 34 -1 2 0 21 + 326 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 322 RN_AS_000 3 32 3 2 1 3 32 -1 2 0 21 + 309 SM_AMIGA_4_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 308 SM_AMIGA_7_ 3 -1 1 2 1 3 -1 -1 2 0 21 + 299 inst_VPA_SYNC 3 -1 0 2 0 6 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 5 2 5 6 -1 -1 2 0 21 + 303 inst_CLK_000_D4 3 -1 1 2 3 7 -1 -1 1 0 20 + 302 inst_CLK_000_D2 3 -1 6 2 3 6 -1 -1 1 0 21 + 324 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 323 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 330 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 325 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 321 RN_DSACK_1_ 3 80 7 1 7 80 -1 3 0 21 + 320 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 319 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 318 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 317 SM_AMIGA_0_ 3 -1 1 1 1 -1 -1 3 0 21 + 315 SM_AMIGA_5_ 3 -1 6 1 6 -1 -1 2 0 20 + 312 CLK_CNT_1_ 3 -1 6 1 6 -1 -1 2 0 21 + 311 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 2 0 21 + 310 inst_CLK_000_D3 3 -1 6 1 1 -1 -1 1 0 21 + 307 CLK_REF_1_ 3 -1 3 1 6 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 6 0 1 3 5 6 7 60 -1 + 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 3 5 7 81 -1 + 10 CLK_000 1 -1 -1 3 0 1 5 10 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 7 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +95 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 320 7 1 3 80 -1 3 0 21 + 29 DTACK 5 -1 3 1 1 29 -1 1 0 21 + 30 LDS_000 5 323 3 0 30 -1 12 0 21 + 31 UDS_000 5 322 3 0 31 -1 8 0 21 + 65 E 5 327 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 329 3 0 33 -1 3 0 20 + 28 BG_000 5 324 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 319 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 318 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 317 1 0 6 -1 3 0 21 + 82 BGACK_030 5 325 7 0 82 -1 2 0 21 + 77 FPU_CS 5 326 7 0 77 -1 2 0 21 + 34 VMA 5 328 3 0 34 -1 2 0 21 + 32 AS_000 5 321 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 1 5 0 1 3 6 7 -1 -1 1 0 20 + 301 inst_CLK_000_D1 3 -1 3 4 1 3 6 7 -1 -1 1 0 20 + 296 inst_AS_030_000_SYNC 3 -1 7 3 3 6 7 -1 -1 4 0 21 + 295 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 20 + 327 RN_E 3 65 6 3 0 3 6 65 -1 3 0 21 + 312 SM_AMIGA_3_ 3 -1 6 3 0 1 6 -1 -1 3 0 20 + 306 cpu_est_2_ 3 -1 6 3 0 3 6 -1 -1 3 1 21 + 304 inst_CLK_OUT_PRE 3 -1 1 3 1 6 7 -1 -1 3 1 20 + 294 cpu_est_0_ 3 -1 6 3 0 3 6 -1 -1 3 0 21 + 326 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 308 SM_AMIGA_7_ 3 -1 7 3 3 6 7 -1 -1 2 0 21 + 298 inst_VPA_D 3 -1 6 3 0 1 3 -1 -1 1 0 21 + 305 SM_AMIGA_6_ 3 -1 6 2 3 6 -1 -1 4 0 20 + 315 SM_AMIGA_2_ 3 -1 6 2 1 6 -1 -1 3 0 20 + 313 SM_AMIGA_1_ 3 -1 1 2 1 7 -1 -1 3 0 21 + 328 RN_VMA 3 34 3 2 0 3 34 -1 2 0 21 + 325 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 321 RN_AS_000 3 32 3 2 3 7 32 -1 2 0 21 + 309 SM_AMIGA_4_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 299 inst_VPA_SYNC 3 -1 0 2 0 6 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 1 2 1 6 -1 -1 2 0 21 + 303 inst_CLK_000_D3 3 -1 3 2 3 7 -1 -1 1 0 20 + 302 inst_CLK_000_D2 3 -1 3 2 3 6 -1 -1 1 0 20 + 323 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 322 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 329 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 324 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 320 RN_DSACK_1_ 3 80 7 1 7 80 -1 3 0 21 + 319 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 318 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 317 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 316 SM_AMIGA_0_ 3 -1 7 1 7 -1 -1 3 0 21 + 314 SM_AMIGA_5_ 3 -1 6 1 6 -1 -1 2 0 20 + 311 CLK_CNT_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 310 CLK_CNT_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 307 CLK_REF_1_ 3 -1 6 1 1 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 4 0 1 3 6 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 1 3 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 10 CLK_000 1 -1 -1 2 0 1 10 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +95 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 320 7 1 3 80 -1 3 0 21 + 29 DTACK 5 -1 3 1 1 29 -1 1 0 21 + 30 LDS_000 5 323 3 0 30 -1 13 0 21 + 31 UDS_000 5 322 3 0 31 -1 9 0 21 + 65 E 5 327 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 329 3 0 33 -1 3 0 20 + 28 BG_000 5 324 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 319 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 318 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 317 1 0 6 -1 3 0 21 + 82 BGACK_030 5 325 7 0 82 -1 2 0 21 + 77 FPU_CS 5 326 7 0 77 -1 2 0 21 + 34 VMA 5 328 3 0 34 -1 2 0 21 + 32 AS_000 5 321 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 1 5 0 1 3 6 7 -1 -1 1 0 20 + 301 inst_CLK_000_D1 3 -1 3 4 1 3 6 7 -1 -1 1 0 20 + 296 inst_AS_030_000_SYNC 3 -1 7 3 3 6 7 -1 -1 4 0 21 + 295 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 20 + 327 RN_E 3 65 6 3 0 3 6 65 -1 3 0 21 + 306 cpu_est_2_ 3 -1 6 3 0 3 6 -1 -1 3 1 21 + 304 inst_CLK_OUT_PRE 3 -1 6 3 1 6 7 -1 -1 3 1 21 + 294 cpu_est_0_ 3 -1 3 3 0 3 6 -1 -1 3 0 20 + 326 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 298 inst_VPA_D 3 -1 1 3 0 1 3 -1 -1 1 0 20 + 305 SM_AMIGA_6_ 3 -1 6 2 3 6 -1 -1 4 0 20 + 329 RN_AMIGA_BUS_ENABLE 3 33 3 2 3 6 33 -1 3 0 20 + 315 SM_AMIGA_2_ 3 -1 1 2 1 7 -1 -1 3 0 21 + 313 SM_AMIGA_1_ 3 -1 7 2 6 7 -1 -1 3 0 21 + 312 SM_AMIGA_3_ 3 -1 1 2 0 1 -1 -1 3 0 21 + 328 RN_VMA 3 34 3 2 0 3 34 -1 2 0 21 + 325 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 321 RN_AS_000 3 32 3 2 3 6 32 -1 2 0 21 + 314 SM_AMIGA_5_ 3 -1 6 2 1 6 -1 -1 2 0 20 + 309 SM_AMIGA_4_ 3 -1 1 2 1 3 -1 -1 2 0 21 + 308 SM_AMIGA_7_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 299 inst_VPA_SYNC 3 -1 0 2 0 1 -1 -1 2 0 21 + 303 inst_CLK_000_D3 3 -1 6 2 3 7 -1 -1 1 0 21 + 302 inst_CLK_000_D2 3 -1 7 2 3 6 -1 -1 1 0 20 + 323 RN_LDS_000 3 30 3 1 3 30 -1 13 0 21 + 322 RN_UDS_000 3 31 3 1 3 31 -1 9 0 21 + 324 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 320 RN_DSACK_1_ 3 80 7 1 7 80 -1 3 0 21 + 319 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 318 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 317 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 316 SM_AMIGA_0_ 3 -1 6 1 6 -1 -1 3 0 20 + 311 CLK_CNT_1_ 3 -1 6 1 6 -1 -1 2 0 21 + 310 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 1 1 1 -1 -1 2 0 21 + 307 CLK_REF_1_ 3 -1 3 1 6 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 5 0 1 3 6 7 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 1 3 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 10 CLK_000 1 -1 -1 2 0 1 10 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +95 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 320 7 1 3 80 -1 3 0 21 + 29 DTACK 5 -1 3 1 1 29 -1 1 0 21 + 30 LDS_000 5 323 3 0 30 -1 13 0 21 + 31 UDS_000 5 322 3 0 31 -1 9 0 21 + 65 E 5 327 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 329 3 0 33 -1 3 0 20 + 28 BG_000 5 324 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 318 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 319 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 317 1 0 6 -1 3 0 21 + 82 BGACK_030 5 325 7 0 82 -1 2 0 21 + 77 FPU_CS 5 326 7 0 77 -1 2 0 21 + 34 VMA 5 328 3 0 34 -1 2 0 21 + 32 AS_000 5 321 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 3 5 0 1 3 6 7 -1 -1 1 0 20 + 301 inst_CLK_000_D1 3 -1 1 4 1 3 6 7 -1 -1 1 0 20 + 296 inst_AS_030_000_SYNC 3 -1 7 3 3 6 7 -1 -1 4 0 21 + 295 cpu_est_1_ 3 -1 6 3 0 3 6 -1 -1 4 0 21 + 327 RN_E 3 65 6 3 0 3 6 65 -1 3 0 21 + 313 SM_AMIGA_1_ 3 -1 1 3 1 6 7 -1 -1 3 0 21 + 306 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 3 1 20 + 303 inst_CLK_OUT_PRE 3 -1 6 3 1 6 7 -1 -1 3 1 21 + 294 cpu_est_0_ 3 -1 3 3 0 3 6 -1 -1 3 0 20 + 326 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 298 inst_VPA_D 3 -1 6 3 0 1 3 -1 -1 1 0 21 + 304 SM_AMIGA_6_ 3 -1 6 2 3 6 -1 -1 4 0 20 + 329 RN_AMIGA_BUS_ENABLE 3 33 3 2 3 6 33 -1 3 0 20 + 312 SM_AMIGA_3_ 3 -1 1 2 0 1 -1 -1 3 0 21 + 328 RN_VMA 3 34 3 2 0 3 34 -1 2 0 21 + 325 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 321 RN_AS_000 3 32 3 2 3 6 32 -1 2 0 21 + 314 SM_AMIGA_5_ 3 -1 6 2 1 6 -1 -1 2 0 20 + 309 SM_AMIGA_4_ 3 -1 1 2 1 3 -1 -1 2 0 21 + 308 SM_AMIGA_7_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 299 inst_VPA_SYNC 3 -1 0 2 0 1 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 7 2 3 6 -1 -1 1 0 20 + 323 RN_LDS_000 3 30 3 1 3 30 -1 13 0 21 + 322 RN_UDS_000 3 31 3 1 3 31 -1 9 0 21 + 324 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 320 RN_DSACK_1_ 3 80 7 1 7 80 -1 3 0 21 + 319 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 318 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 317 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 316 SM_AMIGA_0_ 3 -1 6 1 6 -1 -1 3 0 20 + 315 SM_AMIGA_2_ 3 -1 1 1 1 -1 -1 3 0 21 + 311 CLK_CNT_1_ 3 -1 6 1 6 -1 -1 2 0 21 + 310 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 1 1 1 -1 -1 2 0 21 + 307 CLK_REF_1_ 3 -1 7 1 6 -1 -1 1 0 20 + 305 inst_CLK_000_D3 3 -1 3 1 7 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 5 0 1 3 6 7 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 1 3 7 81 -1 + 10 CLK_000 1 -1 -1 3 0 1 3 10 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +95 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 318 7 1 3 80 -1 3 0 21 + 29 DTACK 5 -1 3 1 1 29 -1 1 0 21 + 30 LDS_000 5 321 3 0 30 -1 13 0 21 + 31 UDS_000 5 320 3 0 31 -1 9 0 21 + 65 E 5 325 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 327 3 0 33 -1 3 0 20 + 28 BG_000 5 322 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 317 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 329 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 328 1 0 6 -1 3 0 21 + 82 BGACK_030 5 323 7 0 82 -1 2 0 21 + 77 FPU_CS 5 324 7 0 77 -1 2 0 21 + 34 VMA 5 326 3 0 34 -1 2 0 21 + 32 AS_000 5 319 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 1 5 0 1 3 6 7 -1 -1 1 0 20 + 301 inst_CLK_000_D1 3 -1 3 4 1 3 6 7 -1 -1 1 0 20 + 296 inst_AS_030_000_SYNC 3 -1 7 3 3 6 7 -1 -1 4 0 21 + 295 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 20 + 325 RN_E 3 65 6 3 0 3 6 65 -1 3 0 21 + 306 cpu_est_2_ 3 -1 6 3 0 3 6 -1 -1 3 1 21 + 303 inst_CLK_OUT_PRE 3 -1 6 3 1 6 7 -1 -1 3 1 21 + 294 cpu_est_0_ 3 -1 3 3 0 3 6 -1 -1 3 0 20 + 324 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 298 inst_VPA_D 3 -1 1 3 0 1 3 -1 -1 1 0 20 + 304 SM_AMIGA_6_ 3 -1 6 2 3 6 -1 -1 4 0 20 + 327 RN_AMIGA_BUS_ENABLE 3 33 3 2 3 6 33 -1 3 0 20 + 315 SM_AMIGA_2_ 3 -1 1 2 1 7 -1 -1 3 0 21 + 313 SM_AMIGA_1_ 3 -1 7 2 6 7 -1 -1 3 0 21 + 312 SM_AMIGA_3_ 3 -1 1 2 0 1 -1 -1 3 0 21 + 326 RN_VMA 3 34 3 2 0 3 34 -1 2 0 21 + 323 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 319 RN_AS_000 3 32 3 2 3 6 32 -1 2 0 21 + 314 SM_AMIGA_5_ 3 -1 6 2 1 6 -1 -1 2 0 20 + 309 SM_AMIGA_4_ 3 -1 1 2 1 3 -1 -1 2 0 21 + 308 SM_AMIGA_7_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 299 inst_VPA_SYNC 3 -1 0 2 0 1 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 7 2 3 6 -1 -1 1 0 20 + 321 RN_LDS_000 3 30 3 1 3 30 -1 13 0 21 + 320 RN_UDS_000 3 31 3 1 3 31 -1 9 0 21 + 329 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 328 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 322 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 318 RN_DSACK_1_ 3 80 7 1 7 80 -1 3 0 21 + 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 316 SM_AMIGA_0_ 3 -1 6 1 6 -1 -1 3 0 20 + 311 CLK_CNT_1_ 3 -1 6 1 6 -1 -1 2 0 21 + 310 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 1 1 1 -1 -1 2 0 21 + 307 CLK_REF_1_ 3 -1 3 1 6 -1 -1 1 0 20 + 305 inst_CLK_000_D3 3 -1 6 1 7 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 5 0 1 3 6 7 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 1 3 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 10 CLK_000 1 -1 -1 2 0 1 10 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +96 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 321 7 1 3 80 -1 3 0 21 + 29 DTACK 5 -1 3 1 5 29 -1 1 0 21 + 30 LDS_000 5 324 3 0 30 -1 12 0 21 + 31 UDS_000 5 323 3 0 31 -1 8 0 21 + 65 E 5 328 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 330 3 0 33 -1 3 0 20 + 28 BG_000 5 325 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 320 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 319 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 318 1 0 6 -1 3 0 21 + 82 BGACK_030 5 326 7 0 82 -1 2 0 21 + 77 FPU_CS 5 327 7 0 77 -1 2 0 21 + 34 VMA 5 329 3 0 34 -1 2 0 21 + 32 AS_000 5 322 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 1 6 0 1 3 5 6 7 -1 -1 1 0 20 + 294 cpu_est_0_ 3 -1 1 4 0 1 3 6 -1 -1 3 0 20 + 301 inst_CLK_000_D1 3 -1 7 4 1 3 6 7 -1 -1 1 0 20 + 296 inst_AS_030_000_SYNC 3 -1 7 3 3 6 7 -1 -1 4 0 21 + 295 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 20 + 328 RN_E 3 65 6 3 0 3 6 65 -1 3 0 21 + 313 SM_AMIGA_3_ 3 -1 6 3 0 5 6 -1 -1 3 0 20 + 305 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 3 1 20 + 303 inst_CLK_OUT_PRE 3 -1 6 3 1 6 7 -1 -1 3 1 21 + 327 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 298 inst_VPA_D 3 -1 7 3 0 3 5 -1 -1 1 0 20 + 304 SM_AMIGA_6_ 3 -1 3 2 3 6 -1 -1 4 0 21 + 316 SM_AMIGA_2_ 3 -1 6 2 1 6 -1 -1 3 0 20 + 314 SM_AMIGA_1_ 3 -1 1 2 1 7 -1 -1 3 0 21 + 329 RN_VMA 3 34 3 2 0 3 34 -1 2 0 21 + 326 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 322 RN_AS_000 3 32 3 2 1 3 32 -1 2 0 21 + 309 SM_AMIGA_4_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 307 SM_AMIGA_7_ 3 -1 1 2 1 3 -1 -1 2 0 21 + 299 inst_VPA_SYNC 3 -1 0 2 0 6 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 5 2 5 6 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 6 2 3 6 -1 -1 1 0 21 + 324 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 323 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 330 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 325 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 321 RN_DSACK_1_ 3 80 7 1 7 80 -1 3 0 21 + 320 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 319 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 318 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 317 SM_AMIGA_0_ 3 -1 1 1 1 -1 -1 3 0 21 + 315 SM_AMIGA_5_ 3 -1 6 1 6 -1 -1 2 0 20 + 312 CLK_CNT_1_ 3 -1 6 1 6 -1 -1 2 0 21 + 311 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 2 0 21 + 310 inst_CLK_000_D3 3 -1 6 1 1 -1 -1 1 0 21 + 308 inst_CLK_000_D4 3 -1 1 1 7 -1 -1 1 0 20 + 306 CLK_REF_1_ 3 -1 3 1 6 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 6 0 1 3 5 6 7 60 -1 + 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 3 5 7 81 -1 + 10 CLK_000 1 -1 -1 3 0 1 5 10 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 7 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +96 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 321 7 1 3 80 -1 3 0 21 + 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 + 30 LDS_000 5 324 3 0 30 -1 12 0 21 + 31 UDS_000 5 323 3 0 31 -1 8 0 21 + 65 E 5 328 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 330 3 0 33 -1 3 0 20 + 28 BG_000 5 325 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 320 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 319 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 318 1 0 6 -1 3 0 21 + 82 BGACK_030 5 326 7 0 82 -1 2 0 21 + 77 FPU_CS 5 327 7 0 77 -1 2 0 21 + 34 VMA 5 329 3 0 34 -1 2 0 21 + 32 AS_000 5 322 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 6 5 1 3 5 6 7 -1 -1 1 0 21 + 303 inst_CLK_OUT_PRE 3 -1 6 4 0 1 6 7 -1 -1 3 1 21 + 301 inst_CLK_000_D1 3 -1 1 4 1 3 6 7 -1 -1 1 0 20 + 296 inst_AS_030_000_SYNC 3 -1 7 3 1 3 7 -1 -1 4 0 21 + 295 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 4 0 20 + 328 RN_E 3 65 6 3 3 5 6 65 -1 3 0 21 + 314 SM_AMIGA_1_ 3 -1 1 3 0 1 7 -1 -1 3 0 21 + 305 cpu_est_2_ 3 -1 6 3 3 5 6 -1 -1 3 1 21 + 294 cpu_est_0_ 3 -1 6 3 3 5 6 -1 -1 3 0 21 + 327 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 322 RN_AS_000 3 32 3 3 0 1 3 32 -1 2 0 21 + 309 SM_AMIGA_4_ 3 -1 1 3 1 3 6 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 3 3 1 3 7 -1 -1 1 0 20 + 298 inst_VPA_D 3 -1 7 3 3 5 6 -1 -1 1 0 20 + 304 SM_AMIGA_6_ 3 -1 3 2 1 3 -1 -1 4 0 21 + 317 SM_AMIGA_0_ 3 -1 0 2 0 1 -1 -1 3 0 21 + 316 SM_AMIGA_2_ 3 -1 6 2 1 6 -1 -1 3 0 20 + 313 SM_AMIGA_3_ 3 -1 6 2 5 6 -1 -1 3 0 20 + 329 RN_VMA 3 34 3 2 3 5 34 -1 2 0 21 + 326 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 307 SM_AMIGA_7_ 3 -1 1 2 1 3 -1 -1 2 0 21 + 299 inst_VPA_SYNC 3 -1 5 2 5 6 -1 -1 2 0 21 + 324 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 323 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 330 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 325 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 321 RN_DSACK_1_ 3 80 7 1 7 80 -1 3 0 21 + 320 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 319 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 318 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 315 SM_AMIGA_5_ 3 -1 1 1 1 -1 -1 2 0 21 + 312 CLK_CNT_1_ 3 -1 6 1 6 -1 -1 2 0 21 + 311 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 310 inst_CLK_000_D3 3 -1 7 1 1 -1 -1 1 0 20 + 308 inst_CLK_000_D4 3 -1 1 1 7 -1 -1 1 0 20 + 306 CLK_REF_1_ 3 -1 3 1 6 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 5 1 3 5 6 7 60 -1 + 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1 + 10 CLK_000 1 -1 -1 5 0 1 5 6 7 10 -1 + 81 AS_030 1 -1 -1 4 3 5 6 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 7 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +95 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 318 7 1 3 80 -1 3 0 21 + 29 DTACK 5 -1 3 1 5 29 -1 1 0 21 + 30 LDS_000 5 321 3 0 30 -1 12 0 21 + 31 UDS_000 5 320 3 0 31 -1 8 0 21 + 65 E 5 325 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 327 3 0 33 -1 3 0 20 + 28 BG_000 5 322 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 317 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 329 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 328 1 0 6 -1 3 0 21 + 82 BGACK_030 5 323 7 0 82 -1 2 0 21 + 77 FPU_CS 5 324 7 0 77 -1 2 0 21 + 34 VMA 5 326 3 0 34 -1 2 0 21 + 32 AS_000 5 319 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 6 6 0 1 3 5 6 7 -1 -1 1 0 21 + 301 inst_CLK_000_D1 3 -1 6 4 1 3 6 7 -1 -1 1 0 21 + 304 SM_AMIGA_6_ 3 -1 3 3 1 3 6 -1 -1 4 0 21 + 296 inst_AS_030_000_SYNC 3 -1 7 3 1 3 7 -1 -1 4 0 21 + 295 cpu_est_1_ 3 -1 6 3 0 3 6 -1 -1 4 0 21 + 325 RN_E 3 65 6 3 0 3 6 65 -1 3 0 21 + 313 SM_AMIGA_3_ 3 -1 6 3 0 5 6 -1 -1 3 0 20 + 305 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 3 1 20 + 303 inst_CLK_OUT_PRE 3 -1 1 3 1 6 7 -1 -1 3 1 20 + 294 cpu_est_0_ 3 -1 3 3 0 3 6 -1 -1 3 0 20 + 324 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 298 inst_VPA_D 3 -1 1 3 0 3 5 -1 -1 1 0 20 + 314 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 3 0 20 + 326 RN_VMA 3 34 3 2 0 3 34 -1 2 0 21 + 323 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 315 SM_AMIGA_5_ 3 -1 1 2 1 6 -1 -1 2 0 21 + 309 SM_AMIGA_4_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 299 inst_VPA_SYNC 3 -1 0 2 0 6 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 5 2 5 6 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 6 2 1 3 -1 -1 1 0 21 + 321 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 320 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 329 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 328 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 327 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 322 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 318 RN_DSACK_1_ 3 80 7 1 7 80 -1 3 0 21 + 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 316 SM_AMIGA_2_ 3 -1 6 1 6 -1 -1 3 0 20 + 319 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 312 CLK_CNT_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 311 CLK_CNT_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 310 inst_CLK_000_D3 3 -1 1 1 6 -1 -1 1 0 20 + 308 inst_CLK_000_D4 3 -1 6 1 7 -1 -1 1 0 21 + 307 SM_AMIGA_7_ 3 -1 6 1 3 -1 -1 1 0 20 + 306 CLK_REF_1_ 3 -1 6 1 1 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 5 0 1 3 5 6 60 -1 + 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 3 5 7 81 -1 + 10 CLK_000 1 -1 -1 3 0 5 6 10 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +93 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 316 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 1 29 -1 1 0 21 + 30 LDS_000 5 319 3 0 30 -1 12 0 21 + 31 UDS_000 5 318 3 0 31 -1 8 0 21 + 65 E 5 323 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 325 3 0 33 -1 3 0 20 + 28 BG_000 5 320 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 315 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 327 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 326 1 0 6 -1 3 0 21 + 82 BGACK_030 5 321 7 0 82 -1 2 0 21 + 77 FPU_CS 5 322 7 0 77 -1 2 0 21 + 34 VMA 5 324 3 0 34 -1 2 0 21 + 32 AS_000 5 317 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 1 5 0 1 3 6 7 -1 -1 1 0 20 + 301 inst_CLK_000_D1 3 -1 6 4 1 3 6 7 -1 -1 1 0 21 + 296 inst_AS_030_000_SYNC 3 -1 7 3 3 6 7 -1 -1 4 0 21 + 295 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 20 + 323 RN_E 3 65 6 3 0 3 6 65 -1 3 0 21 + 312 SM_AMIGA_3_ 3 -1 6 3 0 1 6 -1 -1 3 0 20 + 305 cpu_est_2_ 3 -1 6 3 0 3 6 -1 -1 3 1 21 + 303 inst_CLK_OUT_PRE 3 -1 1 3 1 6 7 -1 -1 3 1 20 + 294 cpu_est_0_ 3 -1 6 3 0 3 6 -1 -1 3 0 21 + 322 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 298 inst_VPA_D 3 -1 1 3 0 1 3 -1 -1 1 0 20 + 304 SM_AMIGA_6_ 3 -1 6 2 3 6 -1 -1 4 0 20 + 309 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 3 0 20 + 324 RN_VMA 3 34 3 2 0 3 34 -1 2 0 21 + 321 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 308 SM_AMIGA_4_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 299 inst_VPA_SYNC 3 -1 0 2 0 6 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 1 2 1 6 -1 -1 2 0 21 + 307 SM_AMIGA_7_ 3 -1 6 2 3 6 -1 -1 1 0 20 + 302 inst_CLK_000_D2 3 -1 3 2 3 6 -1 -1 1 0 20 + 319 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 318 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 327 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 326 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 325 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 320 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 315 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 314 SM_AMIGA_2_ 3 -1 6 1 6 -1 -1 3 0 20 + 317 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 316 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 313 SM_AMIGA_5_ 3 -1 6 1 6 -1 -1 2 0 20 + 311 CLK_CNT_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 310 CLK_CNT_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 306 CLK_REF_1_ 3 -1 6 1 1 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 4 0 1 3 6 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 1 3 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 10 CLK_000 1 -1 -1 2 0 1 10 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +95 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 318 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 5 29 -1 1 0 21 + 30 LDS_000 5 321 3 0 30 -1 12 0 21 + 31 UDS_000 5 320 3 0 31 -1 8 0 21 + 65 E 5 325 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 329 3 0 33 -1 3 0 20 + 28 BG_000 5 322 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 317 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 328 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 327 1 0 6 -1 3 0 21 + 82 BGACK_030 5 323 7 0 82 -1 2 0 21 + 77 FPU_CS 5 324 7 0 77 -1 2 0 21 + 34 VMA 5 326 3 0 34 -1 2 0 21 + 32 AS_000 5 319 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 1 6 0 1 3 5 6 7 -1 -1 1 0 20 + 301 inst_CLK_000_D1 3 -1 3 4 1 3 6 7 -1 -1 1 0 20 + 296 inst_AS_030_000_SYNC 3 -1 7 3 3 6 7 -1 -1 4 0 21 + 295 cpu_est_1_ 3 -1 6 3 0 3 6 -1 -1 4 0 21 + 325 RN_E 3 65 6 3 0 3 6 65 -1 3 0 21 + 314 SM_AMIGA_3_ 3 -1 6 3 0 5 6 -1 -1 3 0 20 + 305 cpu_est_2_ 3 -1 6 3 0 3 6 -1 -1 3 1 21 + 294 cpu_est_0_ 3 -1 3 3 0 3 6 -1 -1 3 0 20 + 324 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 298 inst_VPA_D 3 -1 1 3 0 3 5 -1 -1 1 0 20 + 304 SM_AMIGA_6_ 3 -1 3 2 3 6 -1 -1 4 0 21 + 303 inst_CLK_OUT_PRE 3 -1 1 2 1 6 -1 -1 3 1 20 + 326 RN_VMA 3 34 3 2 0 3 34 -1 2 0 21 + 323 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 310 SM_AMIGA_4_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 308 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 2 0 20 + 299 inst_VPA_SYNC 3 -1 0 2 0 6 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 5 2 5 6 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 6 2 3 6 -1 -1 1 0 21 + 321 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 320 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 329 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 328 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 327 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 322 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 316 SM_AMIGA_2_ 3 -1 6 1 6 -1 -1 3 0 20 + 319 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 318 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 315 SM_AMIGA_5_ 3 -1 6 1 6 -1 -1 2 0 20 + 313 CLK_CNT_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 312 CLK_CNT_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 311 inst_CLK_000_D3 3 -1 6 1 1 -1 -1 1 0 21 + 309 inst_CLK_000_D4 3 -1 1 1 7 -1 -1 1 0 20 + 307 SM_AMIGA_7_ 3 -1 6 1 3 -1 -1 1 0 20 + 306 CLK_REF_1_ 3 -1 6 1 1 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 5 0 1 3 5 6 60 -1 + 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 3 5 7 81 -1 + 10 CLK_000 1 -1 -1 3 0 1 5 10 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +95 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 318 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 5 29 -1 1 0 21 + 30 LDS_000 5 321 3 0 30 -1 12 0 21 + 31 UDS_000 5 320 3 0 31 -1 8 0 21 + 65 E 5 325 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 328 3 0 33 -1 3 0 20 + 28 BG_000 5 322 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 317 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 329 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 327 1 0 6 -1 3 0 21 + 82 BGACK_030 5 323 7 0 82 -1 2 0 21 + 77 FPU_CS 5 324 7 0 77 -1 2 0 21 + 34 VMA 5 326 3 0 34 -1 2 0 21 + 32 AS_000 5 319 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 1 6 0 1 3 5 6 7 -1 -1 1 0 20 + 301 inst_CLK_000_D1 3 -1 3 4 1 3 6 7 -1 -1 1 0 20 + 296 inst_AS_030_000_SYNC 3 -1 7 3 3 6 7 -1 -1 4 0 21 + 295 cpu_est_1_ 3 -1 6 3 0 3 6 -1 -1 4 0 21 + 325 RN_E 3 65 6 3 0 3 6 65 -1 3 0 21 + 314 SM_AMIGA_3_ 3 -1 6 3 0 5 6 -1 -1 3 0 20 + 305 cpu_est_2_ 3 -1 6 3 0 3 6 -1 -1 3 1 21 + 294 cpu_est_0_ 3 -1 3 3 0 3 6 -1 -1 3 0 20 + 324 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 298 inst_VPA_D 3 -1 1 3 0 3 5 -1 -1 1 0 20 + 304 SM_AMIGA_6_ 3 -1 3 2 3 6 -1 -1 4 0 21 + 303 inst_CLK_OUT_PRE 3 -1 1 2 1 6 -1 -1 3 1 20 + 326 RN_VMA 3 34 3 2 0 3 34 -1 2 0 21 + 323 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 310 SM_AMIGA_4_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 308 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 2 0 20 + 299 inst_VPA_SYNC 3 -1 0 2 0 6 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 5 2 5 6 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 6 2 3 6 -1 -1 1 0 21 + 321 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 320 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 329 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 328 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 327 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 322 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 316 SM_AMIGA_2_ 3 -1 6 1 6 -1 -1 3 0 20 + 319 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 318 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 315 SM_AMIGA_5_ 3 -1 6 1 6 -1 -1 2 0 20 + 313 CLK_CNT_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 312 CLK_CNT_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 311 inst_CLK_000_D3 3 -1 6 1 1 -1 -1 1 0 21 + 309 inst_CLK_000_D4 3 -1 1 1 7 -1 -1 1 0 20 + 307 SM_AMIGA_7_ 3 -1 6 1 3 -1 -1 1 0 20 + 306 CLK_REF_1_ 3 -1 6 1 1 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 5 0 1 3 5 6 60 -1 + 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 3 5 7 81 -1 + 10 CLK_000 1 -1 -1 3 0 1 5 10 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +95 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 318 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 5 29 -1 1 0 21 + 30 LDS_000 5 321 3 0 30 -1 12 0 21 + 31 UDS_000 5 320 3 0 31 -1 8 0 21 + 65 E 5 325 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 329 3 0 33 -1 3 0 20 + 28 BG_000 5 322 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 317 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 328 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 327 1 0 6 -1 3 0 21 + 82 BGACK_030 5 323 7 0 82 -1 2 0 21 + 77 FPU_CS 5 324 7 0 77 -1 2 0 21 + 34 VMA 5 326 3 0 34 -1 2 0 21 + 32 AS_000 5 319 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 1 6 0 1 3 5 6 7 -1 -1 1 0 20 + 301 inst_CLK_000_D1 3 -1 3 4 1 3 6 7 -1 -1 1 0 20 + 296 inst_AS_030_000_SYNC 3 -1 7 3 3 6 7 -1 -1 4 0 21 + 295 cpu_est_1_ 3 -1 6 3 0 3 6 -1 -1 4 0 21 + 325 RN_E 3 65 6 3 0 3 6 65 -1 3 0 21 + 314 SM_AMIGA_3_ 3 -1 6 3 0 5 6 -1 -1 3 0 20 + 305 cpu_est_2_ 3 -1 6 3 0 3 6 -1 -1 3 1 21 + 294 cpu_est_0_ 3 -1 3 3 0 3 6 -1 -1 3 0 20 + 324 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 298 inst_VPA_D 3 -1 1 3 0 3 5 -1 -1 1 0 20 + 304 SM_AMIGA_6_ 3 -1 3 2 3 6 -1 -1 4 0 21 + 303 inst_CLK_OUT_PRE 3 -1 1 2 1 6 -1 -1 3 1 20 + 326 RN_VMA 3 34 3 2 0 3 34 -1 2 0 21 + 323 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 310 SM_AMIGA_4_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 308 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 2 0 20 + 299 inst_VPA_SYNC 3 -1 0 2 0 6 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 5 2 5 6 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 6 2 3 6 -1 -1 1 0 21 + 321 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 320 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 329 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 328 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 327 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 322 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 316 SM_AMIGA_2_ 3 -1 6 1 6 -1 -1 3 0 20 + 319 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 318 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 315 SM_AMIGA_5_ 3 -1 6 1 6 -1 -1 2 0 20 + 313 CLK_CNT_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 312 CLK_CNT_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 311 inst_CLK_000_D3 3 -1 6 1 1 -1 -1 1 0 21 + 309 inst_CLK_000_D4 3 -1 1 1 7 -1 -1 1 0 20 + 307 SM_AMIGA_7_ 3 -1 6 1 3 -1 -1 1 0 20 + 306 CLK_REF_1_ 3 -1 6 1 1 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 5 0 1 3 5 6 60 -1 + 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 3 5 7 81 -1 + 10 CLK_000 1 -1 -1 3 0 1 5 10 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +96 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 319 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 5 29 -1 1 0 21 + 30 LDS_000 5 322 3 0 30 -1 12 0 21 + 31 UDS_000 5 321 3 0 31 -1 8 0 21 + 65 E 5 326 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 328 3 0 33 -1 3 0 20 + 28 BG_000 5 323 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 318 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 330 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 329 1 0 6 -1 3 0 21 + 82 BGACK_030 5 324 7 0 82 -1 2 0 21 + 77 FPU_CS 5 325 7 0 77 -1 2 0 21 + 34 VMA 5 327 3 0 34 -1 2 0 21 + 32 AS_000 5 320 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 6 6 0 1 3 5 6 7 -1 -1 1 0 21 + 301 inst_CLK_000_D1 3 -1 6 4 1 3 6 7 -1 -1 1 0 21 + 304 SM_AMIGA_6_ 3 -1 3 3 1 3 6 -1 -1 4 0 21 + 296 inst_AS_030_000_SYNC 3 -1 7 3 1 3 7 -1 -1 4 0 21 + 295 cpu_est_1_ 3 -1 6 3 0 3 6 -1 -1 4 0 21 + 326 RN_E 3 65 6 3 0 3 6 65 -1 3 0 21 + 315 SM_AMIGA_3_ 3 -1 6 3 0 5 6 -1 -1 3 0 20 + 305 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 3 1 20 + 294 cpu_est_0_ 3 -1 6 3 0 3 6 -1 -1 3 0 21 + 325 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 6 3 1 3 6 -1 -1 1 0 21 + 298 inst_VPA_D 3 -1 1 3 0 3 5 -1 -1 1 0 20 + 303 inst_CLK_OUT_PRE 3 -1 1 2 1 6 -1 -1 3 1 20 + 327 RN_VMA 3 34 3 2 0 3 34 -1 2 0 21 + 324 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 316 SM_AMIGA_5_ 3 -1 1 2 1 6 -1 -1 2 0 21 + 310 SM_AMIGA_4_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 308 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 2 0 20 + 299 inst_VPA_SYNC 3 -1 0 2 0 6 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 5 2 5 6 -1 -1 2 0 21 + 322 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 321 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 330 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 329 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 328 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 323 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 318 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 317 SM_AMIGA_2_ 3 -1 6 1 6 -1 -1 3 0 20 + 320 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 319 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 313 CLK_CNT_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 312 CLK_CNT_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 314 inst_CLK_000_D4 3 -1 1 1 0 -1 -1 1 0 20 + 311 inst_CLK_000_D3 3 -1 6 1 1 -1 -1 1 0 21 + 309 inst_CLK_000_D5 3 -1 0 1 7 -1 -1 1 0 20 + 307 SM_AMIGA_7_ 3 -1 6 1 3 -1 -1 1 0 20 + 306 CLK_REF_1_ 3 -1 3 1 1 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 5 0 1 3 5 6 60 -1 + 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 3 5 7 81 -1 + 10 CLK_000 1 -1 -1 3 0 5 6 10 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +95 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 318 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 5 29 -1 1 0 21 + 30 LDS_000 5 321 3 0 30 -1 12 0 21 + 31 UDS_000 5 320 3 0 31 -1 8 0 21 + 65 E 5 325 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 328 3 0 33 -1 3 0 20 + 28 BG_000 5 322 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 317 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 329 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 327 1 0 6 -1 3 0 21 + 82 BGACK_030 5 323 7 0 82 -1 2 0 21 + 77 FPU_CS 5 324 7 0 77 -1 2 0 21 + 34 VMA 5 326 3 0 34 -1 2 0 21 + 32 AS_000 5 319 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 1 6 0 1 3 5 6 7 -1 -1 1 0 20 + 301 inst_CLK_000_D1 3 -1 3 4 1 3 6 7 -1 -1 1 0 20 + 296 inst_AS_030_000_SYNC 3 -1 7 3 3 6 7 -1 -1 4 0 21 + 295 cpu_est_1_ 3 -1 6 3 0 3 6 -1 -1 4 0 21 + 325 RN_E 3 65 6 3 0 3 6 65 -1 3 0 21 + 314 SM_AMIGA_3_ 3 -1 6 3 0 5 6 -1 -1 3 0 20 + 305 cpu_est_2_ 3 -1 6 3 0 3 6 -1 -1 3 1 21 + 294 cpu_est_0_ 3 -1 3 3 0 3 6 -1 -1 3 0 20 + 324 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 298 inst_VPA_D 3 -1 1 3 0 3 5 -1 -1 1 0 20 + 304 SM_AMIGA_6_ 3 -1 3 2 3 6 -1 -1 4 0 21 + 303 inst_CLK_OUT_PRE 3 -1 1 2 1 6 -1 -1 3 1 20 + 326 RN_VMA 3 34 3 2 0 3 34 -1 2 0 21 + 323 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 310 SM_AMIGA_4_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 308 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 2 0 20 + 299 inst_VPA_SYNC 3 -1 0 2 0 6 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 5 2 5 6 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 6 2 3 6 -1 -1 1 0 21 + 321 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 320 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 329 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 328 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 327 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 322 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 316 SM_AMIGA_2_ 3 -1 6 1 6 -1 -1 3 0 20 + 319 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 318 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 315 SM_AMIGA_5_ 3 -1 6 1 6 -1 -1 2 0 20 + 313 CLK_CNT_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 312 CLK_CNT_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 311 inst_CLK_000_D3 3 -1 6 1 1 -1 -1 1 0 21 + 309 inst_CLK_000_D4 3 -1 1 1 7 -1 -1 1 0 20 + 307 SM_AMIGA_7_ 3 -1 6 1 3 -1 -1 1 0 20 + 306 CLK_REF_1_ 3 -1 6 1 1 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 5 0 1 3 5 6 60 -1 + 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 3 5 7 81 -1 + 10 CLK_000 1 -1 -1 3 0 1 5 10 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +95 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 318 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 5 29 -1 1 0 21 + 30 LDS_000 5 321 3 0 30 -1 12 0 21 + 31 UDS_000 5 320 3 0 31 -1 8 0 21 + 65 E 5 325 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 329 3 0 33 -1 3 0 20 + 28 BG_000 5 322 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 317 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 328 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 327 1 0 6 -1 3 0 21 + 82 BGACK_030 5 323 7 0 82 -1 2 0 21 + 77 FPU_CS 5 324 7 0 77 -1 2 0 21 + 34 VMA 5 326 3 0 34 -1 2 0 21 + 32 AS_000 5 319 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 1 6 0 1 3 5 6 7 -1 -1 1 0 20 + 301 inst_CLK_000_D1 3 -1 3 4 1 3 6 7 -1 -1 1 0 20 + 296 inst_AS_030_000_SYNC 3 -1 7 3 3 6 7 -1 -1 4 0 21 + 295 cpu_est_1_ 3 -1 6 3 0 3 6 -1 -1 4 0 21 + 325 RN_E 3 65 6 3 0 3 6 65 -1 3 0 21 + 314 SM_AMIGA_3_ 3 -1 6 3 0 5 6 -1 -1 3 0 20 + 305 cpu_est_2_ 3 -1 6 3 0 3 6 -1 -1 3 1 21 + 294 cpu_est_0_ 3 -1 3 3 0 3 6 -1 -1 3 0 20 + 324 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 298 inst_VPA_D 3 -1 1 3 0 3 5 -1 -1 1 0 20 + 304 SM_AMIGA_6_ 3 -1 3 2 3 6 -1 -1 4 0 21 + 303 inst_CLK_OUT_PRE 3 -1 1 2 1 6 -1 -1 3 1 20 + 326 RN_VMA 3 34 3 2 0 3 34 -1 2 0 21 + 323 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 310 SM_AMIGA_4_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 308 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 2 0 20 + 299 inst_VPA_SYNC 3 -1 0 2 0 6 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 5 2 5 6 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 6 2 3 6 -1 -1 1 0 21 + 321 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 320 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 329 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 328 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 327 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 322 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 316 SM_AMIGA_2_ 3 -1 6 1 6 -1 -1 3 0 20 + 319 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 318 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 315 SM_AMIGA_5_ 3 -1 6 1 6 -1 -1 2 0 20 + 313 CLK_CNT_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 312 CLK_CNT_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 311 inst_CLK_000_D3 3 -1 6 1 1 -1 -1 1 0 21 + 309 inst_CLK_000_D4 3 -1 1 1 7 -1 -1 1 0 20 + 307 SM_AMIGA_7_ 3 -1 6 1 3 -1 -1 1 0 20 + 306 CLK_REF_1_ 3 -1 6 1 1 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 5 0 1 3 5 6 60 -1 + 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 3 5 7 81 -1 + 10 CLK_000 1 -1 -1 3 0 1 5 10 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +95 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 318 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 5 29 -1 1 0 21 + 30 LDS_000 5 321 3 0 30 -1 12 0 21 + 31 UDS_000 5 320 3 0 31 -1 8 0 21 + 65 E 5 325 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 329 3 0 33 -1 3 0 20 + 28 BG_000 5 322 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 317 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 328 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 327 1 0 6 -1 3 0 21 + 82 BGACK_030 5 323 7 0 82 -1 2 0 21 + 77 FPU_CS 5 324 7 0 77 -1 2 0 21 + 34 VMA 5 326 3 0 34 -1 2 0 21 + 32 AS_000 5 319 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 1 6 0 1 3 5 6 7 -1 -1 1 0 20 + 301 inst_CLK_000_D1 3 -1 3 4 1 3 6 7 -1 -1 1 0 20 + 296 inst_AS_030_000_SYNC 3 -1 7 3 3 6 7 -1 -1 4 0 21 + 295 cpu_est_1_ 3 -1 6 3 0 3 6 -1 -1 4 0 21 + 325 RN_E 3 65 6 3 0 3 6 65 -1 3 0 21 + 314 SM_AMIGA_3_ 3 -1 6 3 0 5 6 -1 -1 3 0 20 + 305 cpu_est_2_ 3 -1 6 3 0 3 6 -1 -1 3 1 21 + 294 cpu_est_0_ 3 -1 3 3 0 3 6 -1 -1 3 0 20 + 324 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 298 inst_VPA_D 3 -1 1 3 0 3 5 -1 -1 1 0 20 + 304 SM_AMIGA_6_ 3 -1 3 2 3 6 -1 -1 4 0 21 + 303 inst_CLK_OUT_PRE 3 -1 1 2 1 6 -1 -1 3 1 20 + 326 RN_VMA 3 34 3 2 0 3 34 -1 2 0 21 + 323 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 310 SM_AMIGA_4_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 308 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 2 0 20 + 299 inst_VPA_SYNC 3 -1 0 2 0 6 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 5 2 5 6 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 6 2 3 6 -1 -1 1 0 21 + 321 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 320 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 329 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 328 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 327 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 322 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 316 SM_AMIGA_2_ 3 -1 6 1 6 -1 -1 3 0 20 + 319 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 318 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 315 SM_AMIGA_5_ 3 -1 6 1 6 -1 -1 2 0 20 + 313 CLK_CNT_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 312 CLK_CNT_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 311 inst_CLK_000_D3 3 -1 6 1 1 -1 -1 1 0 21 + 309 inst_CLK_000_D4 3 -1 1 1 7 -1 -1 1 0 20 + 307 SM_AMIGA_7_ 3 -1 6 1 3 -1 -1 1 0 20 + 306 CLK_REF_1_ 3 -1 6 1 1 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 5 0 1 3 5 6 60 -1 + 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 3 5 7 81 -1 + 10 CLK_000 1 -1 -1 3 0 1 5 10 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +95 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 318 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 5 29 -1 1 0 21 + 30 LDS_000 5 321 3 0 30 -1 12 0 21 + 31 UDS_000 5 320 3 0 31 -1 8 0 21 + 65 E 5 325 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 328 3 0 33 -1 3 0 20 + 28 BG_000 5 322 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 317 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 329 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 327 1 0 6 -1 3 0 21 + 82 BGACK_030 5 323 7 0 82 -1 2 0 21 + 77 FPU_CS 5 324 7 0 77 -1 2 0 21 + 34 VMA 5 326 3 0 34 -1 2 0 21 + 32 AS_000 5 319 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 1 6 0 1 3 5 6 7 -1 -1 1 0 20 + 301 inst_CLK_000_D1 3 -1 3 4 1 3 6 7 -1 -1 1 0 20 + 296 inst_AS_030_000_SYNC 3 -1 7 3 3 6 7 -1 -1 4 0 21 + 295 cpu_est_1_ 3 -1 6 3 0 3 6 -1 -1 4 0 21 + 325 RN_E 3 65 6 3 0 3 6 65 -1 3 0 21 + 314 SM_AMIGA_3_ 3 -1 6 3 0 5 6 -1 -1 3 0 20 + 305 cpu_est_2_ 3 -1 6 3 0 3 6 -1 -1 3 1 21 + 303 inst_CLK_OUT_PRE 3 -1 1 3 1 6 7 -1 -1 3 1 20 + 294 cpu_est_0_ 3 -1 3 3 0 3 6 -1 -1 3 0 20 + 324 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 298 inst_VPA_D 3 -1 1 3 0 3 5 -1 -1 1 0 20 + 304 SM_AMIGA_6_ 3 -1 3 2 3 6 -1 -1 4 0 21 + 326 RN_VMA 3 34 3 2 0 3 34 -1 2 0 21 + 323 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 310 SM_AMIGA_4_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 308 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 2 0 20 + 299 inst_VPA_SYNC 3 -1 0 2 0 6 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 5 2 5 6 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 6 2 3 6 -1 -1 1 0 21 + 321 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 320 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 329 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 328 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 327 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 322 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 316 SM_AMIGA_2_ 3 -1 6 1 6 -1 -1 3 0 20 + 319 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 318 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 315 SM_AMIGA_5_ 3 -1 6 1 6 -1 -1 2 0 20 + 313 CLK_CNT_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 312 CLK_CNT_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 311 inst_CLK_000_D3 3 -1 6 1 1 -1 -1 1 0 21 + 309 inst_CLK_000_D4 3 -1 1 1 7 -1 -1 1 0 20 + 307 SM_AMIGA_7_ 3 -1 6 1 3 -1 -1 1 0 20 + 306 CLK_REF_1_ 3 -1 6 1 1 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 5 0 1 3 5 6 60 -1 + 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 3 5 7 81 -1 + 10 CLK_000 1 -1 -1 3 0 1 5 10 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +95 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 318 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 5 29 -1 1 0 21 + 30 LDS_000 5 321 3 0 30 -1 12 0 21 + 31 UDS_000 5 320 3 0 31 -1 8 0 21 + 65 E 5 325 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 329 3 0 33 -1 3 0 20 + 28 BG_000 5 322 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 317 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 328 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 327 1 0 6 -1 3 0 21 + 82 BGACK_030 5 323 7 0 82 -1 2 0 21 + 77 FPU_CS 5 324 7 0 77 -1 2 0 21 + 34 VMA 5 326 3 0 34 -1 2 0 21 + 32 AS_000 5 319 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 1 6 0 1 3 5 6 7 -1 -1 1 0 20 + 301 inst_CLK_000_D1 3 -1 3 4 1 3 6 7 -1 -1 1 0 20 + 296 inst_AS_030_000_SYNC 3 -1 7 3 3 6 7 -1 -1 4 0 21 + 295 cpu_est_1_ 3 -1 6 3 0 3 6 -1 -1 4 0 21 + 325 RN_E 3 65 6 3 0 3 6 65 -1 3 0 21 + 314 SM_AMIGA_3_ 3 -1 6 3 0 5 6 -1 -1 3 0 20 + 305 cpu_est_2_ 3 -1 6 3 0 3 6 -1 -1 3 1 21 + 294 cpu_est_0_ 3 -1 3 3 0 3 6 -1 -1 3 0 20 + 324 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 298 inst_VPA_D 3 -1 1 3 0 3 5 -1 -1 1 0 20 + 304 SM_AMIGA_6_ 3 -1 3 2 3 6 -1 -1 4 0 21 + 303 inst_CLK_OUT_PRE 3 -1 1 2 1 6 -1 -1 3 1 20 + 326 RN_VMA 3 34 3 2 0 3 34 -1 2 0 21 + 323 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 310 SM_AMIGA_4_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 308 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 2 0 20 + 299 inst_VPA_SYNC 3 -1 0 2 0 6 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 5 2 5 6 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 6 2 3 6 -1 -1 1 0 21 + 321 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 320 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 329 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 328 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 327 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 322 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 316 SM_AMIGA_2_ 3 -1 6 1 6 -1 -1 3 0 20 + 319 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 318 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 315 SM_AMIGA_5_ 3 -1 6 1 6 -1 -1 2 0 20 + 313 CLK_CNT_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 312 CLK_CNT_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 311 inst_CLK_000_D3 3 -1 6 1 1 -1 -1 1 0 21 + 309 inst_CLK_000_D4 3 -1 1 1 7 -1 -1 1 0 20 + 307 SM_AMIGA_7_ 3 -1 6 1 3 -1 -1 1 0 20 + 306 CLK_REF_1_ 3 -1 6 1 1 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 5 0 1 3 5 6 60 -1 + 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 3 5 7 81 -1 + 10 CLK_000 1 -1 -1 3 0 1 5 10 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +95 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 318 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 1 29 -1 1 0 21 + 30 LDS_000 5 321 3 0 30 -1 13 0 21 + 31 UDS_000 5 320 3 0 31 -1 9 0 21 + 65 E 5 325 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 327 3 0 33 -1 3 0 20 + 28 BG_000 5 322 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 317 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 329 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 328 1 0 6 -1 3 0 21 + 82 BGACK_030 5 323 7 0 82 -1 2 0 21 + 77 FPU_CS 5 324 7 0 77 -1 2 0 21 + 34 VMA 5 326 3 0 34 -1 2 0 21 + 32 AS_000 5 319 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 6 6 0 1 3 5 6 7 -1 -1 1 0 21 + 295 cpu_est_1_ 3 -1 1 4 0 1 3 6 -1 -1 4 0 20 + 325 RN_E 3 65 6 4 0 1 3 6 65 -1 3 0 21 + 305 cpu_est_2_ 3 -1 1 4 0 1 3 6 -1 -1 3 1 20 + 294 cpu_est_0_ 3 -1 6 4 0 1 3 6 -1 -1 3 0 21 + 301 inst_CLK_000_D1 3 -1 3 4 1 3 6 7 -1 -1 1 0 20 + 304 SM_AMIGA_6_ 3 -1 6 3 3 5 6 -1 -1 4 0 20 + 296 inst_AS_030_000_SYNC 3 -1 7 3 3 6 7 -1 -1 4 0 21 + 316 SM_AMIGA_2_ 3 -1 1 3 1 5 6 -1 -1 3 0 21 + 314 SM_AMIGA_3_ 3 -1 1 3 0 1 5 -1 -1 3 0 21 + 324 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 315 SM_AMIGA_5_ 3 -1 6 3 1 5 6 -1 -1 2 0 20 + 310 SM_AMIGA_4_ 3 -1 1 3 1 3 5 -1 -1 2 0 21 + 308 SM_AMIGA_1_ 3 -1 6 3 5 6 7 -1 -1 2 0 20 + 298 inst_VPA_D 3 -1 6 3 0 1 3 -1 -1 1 0 21 + 327 RN_AMIGA_BUS_ENABLE 3 33 3 2 3 6 33 -1 3 0 20 + 303 inst_CLK_OUT_PRE 3 -1 6 2 1 6 -1 -1 3 1 21 + 326 RN_VMA 3 34 3 2 0 3 34 -1 2 0 21 + 323 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 299 inst_VPA_SYNC 3 -1 0 2 0 1 -1 -1 2 0 21 + 307 SM_AMIGA_7_ 3 -1 5 2 3 6 -1 -1 1 0 21 + 302 inst_CLK_000_D2 3 -1 3 2 3 6 -1 -1 1 0 20 + 321 RN_LDS_000 3 30 3 1 3 30 -1 13 0 21 + 320 RN_UDS_000 3 31 3 1 3 31 -1 9 0 21 + 329 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 328 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 322 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 319 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 318 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 313 CLK_CNT_1_ 3 -1 6 1 6 -1 -1 2 0 21 + 312 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 1 1 1 -1 -1 2 0 21 + 311 inst_CLK_000_D3 3 -1 3 1 6 -1 -1 1 0 20 + 309 inst_CLK_000_D4 3 -1 6 1 7 -1 -1 1 0 21 + 306 CLK_REF_1_ 3 -1 6 1 6 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 5 0 1 3 5 6 60 -1 + 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 1 3 7 81 -1 + 10 CLK_000 1 -1 -1 3 0 1 6 10 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +95 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 318 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 1 29 -1 1 0 21 + 30 LDS_000 5 321 3 0 30 -1 13 0 21 + 31 UDS_000 5 320 3 0 31 -1 9 0 21 + 65 E 5 325 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 328 3 0 33 -1 3 0 20 + 28 BG_000 5 322 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 317 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 329 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 327 1 0 6 -1 3 0 21 + 82 BGACK_030 5 323 7 0 82 -1 2 0 21 + 77 FPU_CS 5 324 7 0 77 -1 2 0 21 + 34 VMA 5 326 3 0 34 -1 2 0 21 + 32 AS_000 5 319 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 6 6 0 1 3 5 6 7 -1 -1 1 0 21 + 295 cpu_est_1_ 3 -1 1 4 0 1 3 6 -1 -1 4 0 20 + 325 RN_E 3 65 6 4 0 1 3 6 65 -1 3 0 21 + 304 cpu_est_2_ 3 -1 1 4 0 1 3 6 -1 -1 3 1 20 + 294 cpu_est_0_ 3 -1 6 4 0 1 3 6 -1 -1 3 0 21 + 301 inst_CLK_000_D1 3 -1 3 4 1 3 6 7 -1 -1 1 0 20 + 306 SM_AMIGA_6_ 3 -1 6 3 3 5 6 -1 -1 4 0 20 + 296 inst_AS_030_000_SYNC 3 -1 7 3 3 6 7 -1 -1 4 0 21 + 316 SM_AMIGA_2_ 3 -1 1 3 1 5 6 -1 -1 3 0 21 + 314 SM_AMIGA_3_ 3 -1 1 3 0 1 5 -1 -1 3 0 21 + 324 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 315 SM_AMIGA_5_ 3 -1 6 3 1 5 6 -1 -1 2 0 20 + 310 SM_AMIGA_4_ 3 -1 1 3 1 3 5 -1 -1 2 0 21 + 308 SM_AMIGA_1_ 3 -1 6 3 5 6 7 -1 -1 2 0 20 + 298 inst_VPA_D 3 -1 6 3 0 1 3 -1 -1 1 0 21 + 328 RN_AMIGA_BUS_ENABLE 3 33 3 2 3 6 33 -1 3 0 20 + 303 inst_CLK_OUT_PRE 3 -1 6 2 1 6 -1 -1 3 1 21 + 326 RN_VMA 3 34 3 2 0 3 34 -1 2 0 21 + 323 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 299 inst_VPA_SYNC 3 -1 0 2 0 1 -1 -1 2 0 21 + 307 SM_AMIGA_7_ 3 -1 5 2 3 6 -1 -1 1 0 21 + 302 inst_CLK_000_D2 3 -1 3 2 3 6 -1 -1 1 0 20 + 321 RN_LDS_000 3 30 3 1 3 30 -1 13 0 21 + 320 RN_UDS_000 3 31 3 1 3 31 -1 9 0 21 + 329 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 327 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 322 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 319 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 318 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 313 CLK_CNT_1_ 3 -1 6 1 6 -1 -1 2 0 21 + 312 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 1 1 1 -1 -1 2 0 21 + 311 inst_CLK_000_D3 3 -1 3 1 6 -1 -1 1 0 20 + 309 inst_CLK_000_D4 3 -1 6 1 7 -1 -1 1 0 21 + 305 CLK_REF_1_ 3 -1 6 1 6 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 5 0 1 3 5 6 60 -1 + 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 1 3 7 81 -1 + 10 CLK_000 1 -1 -1 3 0 1 6 10 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +96 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 319 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 5 29 -1 1 0 21 + 30 LDS_000 5 322 3 0 30 -1 12 0 21 + 31 UDS_000 5 321 3 0 31 -1 8 0 21 + 65 E 5 326 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 328 3 0 33 -1 3 0 20 + 28 BG_000 5 323 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 318 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 330 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 329 1 0 6 -1 3 0 21 + 82 BGACK_030 5 324 7 0 82 -1 2 0 21 + 77 FPU_CS 5 325 7 0 77 -1 2 0 21 + 34 VMA 5 327 3 0 34 -1 2 0 21 + 32 AS_000 5 320 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 7 6 0 1 3 5 6 7 -1 -1 1 0 20 + 296 inst_AS_030_000_SYNC 3 -1 7 4 1 3 6 7 -1 -1 4 0 21 + 301 inst_CLK_000_D1 3 -1 6 4 1 3 6 7 -1 -1 1 0 21 + 295 cpu_est_1_ 3 -1 6 3 0 3 6 -1 -1 4 0 21 + 326 RN_E 3 65 6 3 0 3 6 65 -1 3 0 21 + 314 SM_AMIGA_3_ 3 -1 1 3 0 1 5 -1 -1 3 0 21 + 304 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 3 1 20 + 294 cpu_est_0_ 3 -1 3 3 0 3 6 -1 -1 3 0 20 + 325 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 308 SM_AMIGA_1_ 3 -1 6 3 1 6 7 -1 -1 2 0 20 + 298 inst_VPA_D 3 -1 6 3 0 3 5 -1 -1 1 0 21 + 306 SM_AMIGA_6_ 3 -1 3 2 3 6 -1 -1 4 0 21 + 316 SM_AMIGA_2_ 3 -1 1 2 1 6 -1 -1 3 0 21 + 307 SM_AMIGA_7_ 3 -1 1 2 1 3 -1 -1 3 0 21 + 303 inst_CLK_OUT_PRE 3 -1 6 2 1 6 -1 -1 3 1 21 + 327 RN_VMA 3 34 3 2 0 3 34 -1 2 0 21 + 324 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 315 SM_AMIGA_5_ 3 -1 6 2 1 6 -1 -1 2 0 20 + 310 SM_AMIGA_4_ 3 -1 1 2 1 3 -1 -1 2 0 21 + 299 inst_VPA_SYNC 3 -1 0 2 0 1 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 5 2 1 5 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 1 2 3 6 -1 -1 1 0 20 + 322 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 321 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 330 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 329 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 328 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 323 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 318 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 320 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 319 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 317 SM_AMIGA_0_ 3 -1 1 1 1 -1 -1 2 0 21 + 313 CLK_CNT_1_ 3 -1 6 1 6 -1 -1 2 0 21 + 312 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 2 0 21 + 311 inst_CLK_000_D3 3 -1 3 1 6 -1 -1 1 0 20 + 309 inst_CLK_000_D4 3 -1 6 1 7 -1 -1 1 0 21 + 305 CLK_REF_1_ 3 -1 3 1 6 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 6 0 1 3 5 6 7 60 -1 + 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 3 5 7 81 -1 + 10 CLK_000 1 -1 -1 3 0 5 7 10 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +94 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 317 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 + 30 LDS_000 5 320 3 0 30 -1 12 0 21 + 31 UDS_000 5 319 3 0 31 -1 8 0 21 + 65 E 5 324 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 326 3 0 33 -1 3 0 20 + 28 BG_000 5 321 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 316 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 328 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 327 1 0 6 -1 3 0 21 + 82 BGACK_030 5 322 7 0 82 -1 2 0 21 + 77 FPU_CS 5 323 7 0 77 -1 2 0 21 + 34 VMA 5 325 3 0 34 -1 2 0 21 + 32 AS_000 5 318 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 301 inst_CLK_000_D1 3 -1 6 5 0 1 3 6 7 -1 -1 1 0 21 + 300 inst_CLK_000_D0 3 -1 6 5 0 1 3 6 7 -1 -1 1 0 21 + 296 inst_AS_030_000_SYNC 3 -1 7 4 0 3 6 7 -1 -1 4 0 21 + 323 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 308 SM_AMIGA_4_ 3 -1 1 3 1 3 6 -1 -1 2 0 21 + 306 SM_AMIGA_6_ 3 -1 3 2 0 3 -1 -1 4 0 21 + 295 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 20 + 324 RN_E 3 65 6 2 3 6 65 -1 3 0 21 + 314 SM_AMIGA_2_ 3 -1 1 2 1 7 -1 -1 3 0 21 + 312 SM_AMIGA_3_ 3 -1 6 2 1 6 -1 -1 3 0 20 + 307 SM_AMIGA_7_ 3 -1 6 2 3 6 -1 -1 3 0 20 + 304 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 1 20 + 303 inst_CLK_OUT_PRE 3 -1 1 2 1 6 -1 -1 3 1 20 + 294 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 20 + 325 RN_VMA 3 34 3 2 3 6 34 -1 2 0 21 + 322 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 315 SM_AMIGA_0_ 3 -1 7 2 6 7 -1 -1 2 0 21 + 313 SM_AMIGA_5_ 3 -1 0 2 0 1 -1 -1 2 0 21 + 299 inst_VPA_SYNC 3 -1 6 2 1 6 -1 -1 2 0 20 + 297 inst_DTACK_SYNC 3 -1 6 2 1 6 -1 -1 2 0 20 + 302 inst_CLK_000_D2 3 -1 6 2 0 3 -1 -1 1 0 21 + 298 inst_VPA_D 3 -1 1 2 3 6 -1 -1 1 0 20 + 320 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 319 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 328 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 327 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 326 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 321 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 316 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 318 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 317 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 311 CLK_CNT_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 310 CLK_CNT_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 309 SM_AMIGA_1_ 3 -1 7 1 7 -1 -1 2 0 21 + 305 CLK_REF_1_ 3 -1 6 1 1 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 5 0 1 3 6 7 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 3 3 6 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 6 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +95 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 318 7 1 3 80 -1 3 0 21 + 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 + 30 LDS_000 5 321 3 0 30 -1 12 0 21 + 31 UDS_000 5 320 3 0 31 -1 8 0 21 + 65 E 5 325 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 327 3 0 33 -1 3 0 20 + 28 BG_000 5 322 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 317 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 329 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 328 1 0 6 -1 3 0 21 + 82 BGACK_030 5 323 7 0 82 -1 2 0 21 + 77 FPU_CS 5 324 7 0 77 -1 2 0 21 + 34 VMA 5 326 3 0 34 -1 2 0 21 + 32 AS_000 5 319 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 301 inst_CLK_000_D1 3 -1 3 5 0 1 3 6 7 -1 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 6 5 0 1 3 6 7 -1 -1 1 0 21 + 296 inst_AS_030_000_SYNC 3 -1 7 4 0 1 3 7 -1 -1 4 0 21 + 324 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 309 SM_AMIGA_4_ 3 -1 1 3 1 3 6 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 3 3 0 3 7 -1 -1 1 0 20 + 307 SM_AMIGA_6_ 3 -1 3 2 0 3 -1 -1 4 0 21 + 295 cpu_est_1_ 3 -1 6 2 3 6 -1 -1 4 0 21 + 325 RN_E 3 65 6 2 3 6 65 -1 3 0 21 + 308 SM_AMIGA_7_ 3 -1 1 2 1 3 -1 -1 3 0 21 + 305 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21 + 303 inst_CLK_OUT_PRE 3 -1 1 2 1 6 -1 -1 3 1 20 + 294 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 20 + 326 RN_VMA 3 34 3 2 3 6 34 -1 2 0 21 + 323 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 316 SM_AMIGA_0_ 3 -1 6 2 1 6 -1 -1 2 0 20 + 314 SM_AMIGA_5_ 3 -1 0 2 0 1 -1 -1 2 0 21 + 312 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 2 0 20 + 298 inst_VPA_D 3 -1 1 2 3 6 -1 -1 1 0 20 + 321 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 320 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 329 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 328 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 327 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 322 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 318 RN_DSACK_1_ 3 80 7 1 7 80 -1 3 0 21 + 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 315 SM_AMIGA_2_ 3 -1 6 1 6 -1 -1 3 0 20 + 313 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 3 0 20 + 319 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 311 CLK_CNT_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 310 CLK_CNT_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 299 inst_VPA_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 297 inst_DTACK_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 306 CLK_REF_1_ 3 -1 3 1 1 -1 -1 1 0 20 + 304 inst_CLK_000_D3 3 -1 7 1 7 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 5 0 1 3 6 7 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 3 3 6 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 6 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +97 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 320 7 1 3 80 -1 3 0 21 + 29 DTACK 5 -1 3 1 0 29 -1 1 0 21 + 30 LDS_000 5 323 3 0 30 -1 12 0 21 + 31 UDS_000 5 322 3 0 31 -1 8 0 21 + 65 E 5 327 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 329 3 0 33 -1 3 0 20 + 28 BG_000 5 324 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 319 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 331 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 330 1 0 6 -1 3 0 21 + 82 BGACK_030 5 325 7 0 82 -1 2 0 21 + 77 FPU_CS 5 326 7 0 77 -1 2 0 21 + 34 VMA 5 328 3 0 34 -1 2 0 21 + 32 AS_000 5 321 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 6 6 0 1 3 5 6 7 -1 -1 1 0 21 + 301 inst_CLK_000_D1 3 -1 3 4 1 3 6 7 -1 -1 1 0 20 + 296 inst_AS_030_000_SYNC 3 -1 7 3 3 6 7 -1 -1 4 0 21 + 295 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 4 0 20 + 327 RN_E 3 65 6 3 3 5 6 65 -1 3 0 21 + 315 SM_AMIGA_3_ 3 -1 0 3 0 1 5 -1 -1 3 0 21 + 305 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 3 1 20 + 294 cpu_est_0_ 3 -1 6 3 3 5 6 -1 -1 3 0 21 + 326 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 314 SM_AMIGA_1_ 3 -1 1 3 1 6 7 -1 -1 2 0 21 + 309 SM_AMIGA_4_ 3 -1 6 3 0 3 6 -1 -1 2 0 20 + 299 inst_VPA_SYNC 3 -1 5 3 0 1 5 -1 -1 2 0 21 + 298 inst_VPA_D 3 -1 1 3 0 3 5 -1 -1 1 0 20 + 307 SM_AMIGA_6_ 3 -1 3 2 3 6 -1 -1 4 0 21 + 308 SM_AMIGA_7_ 3 -1 6 2 3 6 -1 -1 3 0 20 + 303 inst_CLK_OUT_PRE 3 -1 1 2 1 6 -1 -1 3 1 20 + 328 RN_VMA 3 34 3 2 3 5 34 -1 2 0 21 + 325 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 0 2 0 1 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 6 2 3 6 -1 -1 1 0 21 + 323 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 322 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 331 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 330 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 329 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 324 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 320 RN_DSACK_1_ 3 80 7 1 7 80 -1 3 0 21 + 319 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 317 SM_AMIGA_2_ 3 -1 1 1 1 -1 -1 3 0 21 + 321 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 318 SM_AMIGA_0_ 3 -1 6 1 6 -1 -1 2 0 20 + 316 SM_AMIGA_5_ 3 -1 6 1 6 -1 -1 2 0 20 + 312 CLK_CNT_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 311 CLK_CNT_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 313 inst_CLK_000_D4 3 -1 6 1 6 -1 -1 1 0 21 + 310 inst_CLK_000_D3 3 -1 3 1 6 -1 -1 1 0 20 + 306 CLK_REF_1_ 3 -1 7 1 1 -1 -1 1 0 20 + 304 inst_CLK_000_D5 3 -1 6 1 7 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 5 0 1 3 5 6 60 -1 + 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 3 5 7 81 -1 + 10 CLK_000 1 -1 -1 3 0 5 6 10 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +96 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 319 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 + 30 LDS_000 5 322 3 0 30 -1 12 0 21 + 31 UDS_000 5 321 3 0 31 -1 8 0 21 + 65 E 5 326 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 328 3 0 33 -1 3 0 20 + 28 BG_000 5 323 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 318 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 330 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 329 1 0 6 -1 3 0 21 + 82 BGACK_030 5 324 7 0 82 -1 2 0 21 + 77 FPU_CS 5 325 7 0 77 -1 2 0 21 + 34 VMA 5 327 3 0 34 -1 2 0 21 + 32 AS_000 5 320 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 301 inst_CLK_000_D1 3 -1 6 5 0 1 3 6 7 -1 -1 1 0 21 + 300 inst_CLK_000_D0 3 -1 6 5 0 1 3 6 7 -1 -1 1 0 21 + 296 inst_AS_030_000_SYNC 3 -1 7 3 0 3 7 -1 -1 4 0 21 + 325 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 303 inst_CLK_000_D3 3 -1 6 3 3 6 7 -1 -1 1 0 21 + 302 inst_CLK_000_D2 3 -1 3 3 0 3 6 -1 -1 1 0 20 + 307 SM_AMIGA_6_ 3 -1 3 2 0 3 -1 -1 4 0 21 + 295 cpu_est_1_ 3 -1 6 2 3 6 -1 -1 4 0 21 + 326 RN_E 3 65 6 2 3 6 65 -1 3 0 21 + 316 SM_AMIGA_2_ 3 -1 6 2 1 6 -1 -1 3 0 20 + 314 SM_AMIGA_3_ 3 -1 1 2 1 6 -1 -1 3 0 21 + 308 SM_AMIGA_7_ 3 -1 7 2 3 7 -1 -1 3 0 21 + 305 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 1 20 + 304 inst_CLK_OUT_PRE 3 -1 6 2 1 6 -1 -1 3 1 21 + 294 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 20 + 327 RN_VMA 3 34 3 2 3 6 34 -1 2 0 21 + 324 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 315 SM_AMIGA_5_ 3 -1 0 2 0 1 -1 -1 2 0 21 + 313 CLK_CNT_1_ 3 -1 1 2 1 6 -1 -1 2 0 20 + 312 CLK_CNT_0_ 3 -1 1 2 1 6 -1 -1 2 0 20 + 311 SM_AMIGA_4_ 3 -1 1 2 1 3 -1 -1 2 0 21 + 309 SM_AMIGA_1_ 3 -1 1 2 1 7 -1 -1 2 0 21 + 299 inst_VPA_SYNC 3 -1 6 2 1 6 -1 -1 2 0 20 + 297 inst_DTACK_SYNC 3 -1 6 2 1 6 -1 -1 2 0 20 + 306 CLK_REF_1_ 3 -1 7 2 1 6 -1 -1 1 0 20 + 298 inst_VPA_D 3 -1 1 2 3 6 -1 -1 1 0 20 + 322 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 321 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 330 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 329 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 328 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 323 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 318 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 320 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 319 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 317 SM_AMIGA_0_ 3 -1 7 1 7 -1 -1 2 0 21 + 310 inst_CLK_000_D4 3 -1 6 1 7 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 5 0 1 3 6 7 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 3 3 6 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 6 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +95 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 318 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 1 29 -1 1 0 21 + 30 LDS_000 5 321 3 0 30 -1 12 0 21 + 31 UDS_000 5 320 3 0 31 -1 8 0 21 + 65 E 5 325 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 327 3 0 33 -1 3 0 20 + 28 BG_000 5 322 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 317 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 329 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 328 1 0 6 -1 3 0 21 + 82 BGACK_030 5 323 7 0 82 -1 2 0 21 + 77 FPU_CS 5 324 7 0 77 -1 2 0 21 + 34 VMA 5 326 3 0 34 -1 2 0 21 + 32 AS_000 5 319 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 6 5 0 1 3 6 7 -1 -1 1 0 21 + 301 inst_CLK_000_D1 3 -1 3 4 1 3 6 7 -1 -1 1 0 20 + 296 inst_AS_030_000_SYNC 3 -1 7 3 3 6 7 -1 -1 4 0 21 + 295 cpu_est_1_ 3 -1 6 3 0 3 6 -1 -1 4 0 21 + 325 RN_E 3 65 6 3 0 3 6 65 -1 3 0 21 + 305 cpu_est_2_ 3 -1 6 3 0 3 6 -1 -1 3 1 21 + 294 cpu_est_0_ 3 -1 3 3 0 3 6 -1 -1 3 0 20 + 324 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 310 SM_AMIGA_1_ 3 -1 1 3 1 6 7 -1 -1 2 0 21 + 309 SM_AMIGA_4_ 3 -1 7 3 1 3 7 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 3 3 1 3 6 -1 -1 1 0 20 + 298 inst_VPA_D 3 -1 1 3 0 1 3 -1 -1 1 0 20 + 307 SM_AMIGA_6_ 3 -1 3 2 3 6 -1 -1 4 0 21 + 313 SM_AMIGA_3_ 3 -1 1 2 0 1 -1 -1 3 0 21 + 308 SM_AMIGA_7_ 3 -1 6 2 3 6 -1 -1 3 0 20 + 304 inst_CLK_OUT_PRE 3 -1 6 2 1 6 -1 -1 3 1 21 + 326 RN_VMA 3 34 3 2 0 3 34 -1 2 0 21 + 323 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 314 SM_AMIGA_5_ 3 -1 6 2 6 7 -1 -1 2 0 20 + 299 inst_VPA_SYNC 3 -1 0 2 0 1 -1 -1 2 0 21 + 303 inst_CLK_000_D3 3 -1 1 2 3 6 -1 -1 1 0 20 + 321 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 320 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 329 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 328 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 327 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 322 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 315 SM_AMIGA_2_ 3 -1 1 1 1 -1 -1 3 0 21 + 319 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 318 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 316 SM_AMIGA_0_ 3 -1 6 1 6 -1 -1 2 0 20 + 312 CLK_CNT_1_ 3 -1 6 1 6 -1 -1 2 0 21 + 311 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 1 1 1 -1 -1 2 0 21 + 306 CLK_REF_1_ 3 -1 7 1 6 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 5 0 1 3 6 7 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 1 3 7 81 -1 + 10 CLK_000 1 -1 -1 3 0 1 6 10 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +96 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 319 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 5 29 -1 1 0 21 + 30 LDS_000 5 322 3 0 30 -1 12 0 21 + 31 UDS_000 5 321 3 0 31 -1 8 0 21 + 65 E 5 326 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 328 3 0 33 -1 3 0 20 + 28 BG_000 5 323 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 318 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 330 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 329 1 0 6 -1 3 0 21 + 82 BGACK_030 5 324 7 0 82 -1 2 0 21 + 77 FPU_CS 5 325 7 0 77 -1 2 0 21 + 34 VMA 5 327 3 0 34 -1 2 0 21 + 32 AS_000 5 320 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 1 6 0 1 3 5 6 7 -1 -1 1 0 20 + 295 cpu_est_1_ 3 -1 1 4 0 1 3 6 -1 -1 4 0 20 + 326 RN_E 3 65 6 4 0 1 3 6 65 -1 3 0 21 + 304 cpu_est_2_ 3 -1 1 4 0 1 3 6 -1 -1 3 1 20 + 294 cpu_est_0_ 3 -1 3 4 0 1 3 6 -1 -1 3 0 20 + 301 inst_CLK_000_D1 3 -1 3 4 1 3 6 7 -1 -1 1 0 20 + 296 inst_AS_030_000_SYNC 3 -1 7 3 3 6 7 -1 -1 4 0 21 + 314 SM_AMIGA_3_ 3 -1 1 3 0 1 5 -1 -1 3 0 21 + 325 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 310 SM_AMIGA_4_ 3 -1 6 3 1 3 6 -1 -1 2 0 20 + 298 inst_VPA_D 3 -1 6 3 0 3 5 -1 -1 1 0 21 + 306 SM_AMIGA_6_ 3 -1 3 2 3 6 -1 -1 4 0 21 + 316 SM_AMIGA_2_ 3 -1 1 2 1 7 -1 -1 3 0 21 + 307 SM_AMIGA_7_ 3 -1 6 2 3 6 -1 -1 3 0 20 + 303 inst_CLK_OUT_PRE 3 -1 6 2 1 6 -1 -1 3 1 21 + 327 RN_VMA 3 34 3 2 0 3 34 -1 2 0 21 + 324 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 308 SM_AMIGA_1_ 3 -1 7 2 6 7 -1 -1 2 0 21 + 299 inst_VPA_SYNC 3 -1 0 2 0 1 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 5 2 1 5 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 6 2 3 6 -1 -1 1 0 21 + 322 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 321 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 330 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 329 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 328 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 323 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 318 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 320 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 319 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 317 SM_AMIGA_0_ 3 -1 6 1 6 -1 -1 2 0 20 + 315 SM_AMIGA_5_ 3 -1 6 1 6 -1 -1 2 0 20 + 313 CLK_CNT_1_ 3 -1 6 1 6 -1 -1 2 0 21 + 312 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 2 0 21 + 311 inst_CLK_000_D3 3 -1 3 1 1 -1 -1 1 0 20 + 309 inst_CLK_000_D4 3 -1 1 1 7 -1 -1 1 0 20 + 305 CLK_REF_1_ 3 -1 3 1 6 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 6 0 1 3 5 6 7 60 -1 + 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 3 5 7 81 -1 + 10 CLK_000 1 -1 -1 3 0 1 5 10 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +96 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 319 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 5 29 -1 1 0 21 + 30 LDS_000 5 322 3 0 30 -1 12 0 21 + 31 UDS_000 5 321 3 0 31 -1 8 0 21 + 65 E 5 326 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 328 3 0 33 -1 3 0 20 + 28 BG_000 5 323 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 318 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 330 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 329 1 0 6 -1 3 0 21 + 82 BGACK_030 5 324 7 0 82 -1 2 0 21 + 77 FPU_CS 5 325 7 0 77 -1 2 0 21 + 34 VMA 5 327 3 0 34 -1 2 0 21 + 32 AS_000 5 320 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 7 6 0 1 3 5 6 7 -1 -1 1 0 20 + 296 inst_AS_030_000_SYNC 3 -1 7 4 1 3 6 7 -1 -1 4 0 21 + 301 inst_CLK_000_D1 3 -1 6 4 1 3 6 7 -1 -1 1 0 21 + 295 cpu_est_1_ 3 -1 6 3 0 3 6 -1 -1 4 0 21 + 326 RN_E 3 65 6 3 0 3 6 65 -1 3 0 21 + 314 SM_AMIGA_3_ 3 -1 1 3 0 1 5 -1 -1 3 0 21 + 304 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 3 1 20 + 294 cpu_est_0_ 3 -1 3 3 0 3 6 -1 -1 3 0 20 + 325 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 308 SM_AMIGA_1_ 3 -1 6 3 1 6 7 -1 -1 2 0 20 + 298 inst_VPA_D 3 -1 6 3 0 3 5 -1 -1 1 0 21 + 306 SM_AMIGA_6_ 3 -1 3 2 3 6 -1 -1 4 0 21 + 316 SM_AMIGA_2_ 3 -1 1 2 1 6 -1 -1 3 0 21 + 307 SM_AMIGA_7_ 3 -1 1 2 1 3 -1 -1 3 0 21 + 303 inst_CLK_OUT_PRE 3 -1 6 2 1 6 -1 -1 3 1 21 + 327 RN_VMA 3 34 3 2 0 3 34 -1 2 0 21 + 324 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 315 SM_AMIGA_5_ 3 -1 6 2 1 6 -1 -1 2 0 20 + 310 SM_AMIGA_4_ 3 -1 1 2 1 3 -1 -1 2 0 21 + 299 inst_VPA_SYNC 3 -1 0 2 0 1 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 5 2 1 5 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 1 2 3 6 -1 -1 1 0 20 + 322 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 321 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 330 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 329 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 328 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 323 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 318 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 320 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 319 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 317 SM_AMIGA_0_ 3 -1 1 1 1 -1 -1 2 0 21 + 313 CLK_CNT_1_ 3 -1 6 1 6 -1 -1 2 0 21 + 312 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 2 0 21 + 311 inst_CLK_000_D3 3 -1 3 1 6 -1 -1 1 0 20 + 309 inst_CLK_000_D4 3 -1 6 1 7 -1 -1 1 0 21 + 305 CLK_REF_1_ 3 -1 3 1 6 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 6 0 1 3 5 6 7 60 -1 + 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 3 5 7 81 -1 + 10 CLK_000 1 -1 -1 3 0 5 7 10 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +96 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 319 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 + 30 LDS_000 5 322 3 0 30 -1 12 0 21 + 31 UDS_000 5 321 3 0 31 -1 8 0 21 + 65 E 5 326 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 328 3 0 33 -1 3 0 20 + 28 BG_000 5 323 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 318 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 330 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 329 1 0 6 -1 3 0 21 + 82 BGACK_030 5 324 7 0 82 -1 2 0 21 + 77 FPU_CS 5 325 7 0 77 -1 2 0 21 + 34 VMA 5 327 3 0 34 -1 2 0 21 + 32 AS_000 5 320 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 301 inst_CLK_000_D1 3 -1 3 5 0 1 3 6 7 -1 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 6 5 0 1 3 6 7 -1 -1 1 0 21 + 296 inst_AS_030_000_SYNC 3 -1 7 4 0 1 3 7 -1 -1 4 0 21 + 310 inst_CLK_000_D3 3 -1 1 4 0 1 3 6 -1 -1 1 0 20 + 307 SM_AMIGA_7_ 3 -1 1 3 0 1 3 -1 -1 4 0 21 + 306 SM_AMIGA_6_ 3 -1 0 3 0 1 3 -1 -1 4 0 21 + 325 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 311 SM_AMIGA_4_ 3 -1 7 3 3 6 7 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 3 3 0 1 3 -1 -1 1 0 20 + 295 cpu_est_1_ 3 -1 6 2 3 6 -1 -1 4 0 21 + 326 RN_E 3 65 6 2 3 6 65 -1 3 0 21 + 304 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 1 20 + 303 inst_CLK_OUT_PRE 3 -1 1 2 1 6 -1 -1 3 1 20 + 294 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 3 0 21 + 327 RN_VMA 3 34 3 2 3 6 34 -1 2 0 21 + 324 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 317 SM_AMIGA_0_ 3 -1 6 2 1 6 -1 -1 2 0 20 + 315 SM_AMIGA_5_ 3 -1 1 2 1 7 -1 -1 2 0 21 + 308 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 2 0 20 + 298 inst_VPA_D 3 -1 6 2 3 6 -1 -1 1 0 21 + 322 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 321 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 330 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 329 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 328 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 323 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 318 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 316 SM_AMIGA_2_ 3 -1 6 1 6 -1 -1 3 0 20 + 314 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 3 0 20 + 320 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 319 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 313 CLK_CNT_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 312 CLK_CNT_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 299 inst_VPA_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 297 inst_DTACK_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 309 inst_CLK_000_D4 3 -1 6 1 7 -1 -1 1 0 21 + 305 CLK_REF_1_ 3 -1 3 1 1 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 5 0 1 3 6 7 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 3 3 6 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 6 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +96 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 319 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 5 29 -1 1 0 21 + 30 LDS_000 5 322 3 0 30 -1 12 0 21 + 31 UDS_000 5 321 3 0 31 -1 8 0 21 + 65 E 5 326 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 328 3 0 33 -1 3 0 20 + 28 BG_000 5 323 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 318 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 330 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 329 1 0 6 -1 3 0 21 + 82 BGACK_030 5 324 7 0 82 -1 2 0 21 + 77 FPU_CS 5 325 7 0 77 -1 2 0 21 + 34 VMA 5 327 3 0 34 -1 2 0 21 + 32 AS_000 5 320 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 1 6 0 1 3 5 6 7 -1 -1 1 0 20 + 301 inst_CLK_000_D1 3 -1 6 4 1 3 6 7 -1 -1 1 0 21 + 296 inst_AS_030_000_SYNC 3 -1 7 3 3 6 7 -1 -1 4 0 21 + 295 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 20 + 326 RN_E 3 65 6 3 0 3 6 65 -1 3 0 21 + 314 SM_AMIGA_3_ 3 -1 1 3 0 1 5 -1 -1 3 0 21 + 303 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 3 1 20 + 294 cpu_est_0_ 3 -1 6 3 0 3 6 -1 -1 3 0 21 + 325 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 307 SM_AMIGA_1_ 3 -1 1 3 1 6 7 -1 -1 2 0 21 + 298 inst_VPA_D 3 -1 6 3 0 3 5 -1 -1 1 0 21 + 305 SM_AMIGA_6_ 3 -1 3 2 3 6 -1 -1 4 0 21 + 306 SM_AMIGA_7_ 3 -1 6 2 3 6 -1 -1 3 0 20 + 302 inst_CLK_OUT_PRE 3 -1 6 2 1 6 -1 -1 3 1 21 + 327 RN_VMA 3 34 3 2 0 3 34 -1 2 0 21 + 324 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 315 SM_AMIGA_5_ 3 -1 6 2 1 6 -1 -1 2 0 20 + 309 SM_AMIGA_4_ 3 -1 1 2 1 3 -1 -1 2 0 21 + 299 inst_VPA_SYNC 3 -1 0 2 0 1 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 5 2 1 5 -1 -1 2 0 21 + 310 inst_CLK_000_D2 3 -1 3 2 3 6 -1 -1 1 0 20 + 322 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 321 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 330 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 329 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 328 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 323 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 318 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 316 SM_AMIGA_2_ 3 -1 1 1 1 -1 -1 3 0 21 + 320 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 319 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 317 SM_AMIGA_0_ 3 -1 6 1 6 -1 -1 2 0 20 + 313 CLK_CNT_1_ 3 -1 6 1 6 -1 -1 2 0 21 + 312 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 2 0 21 + 311 inst_CLK_000_D3 3 -1 3 1 1 -1 -1 1 0 20 + 308 inst_CLK_000_D4 3 -1 1 1 7 -1 -1 1 0 20 + 304 CLK_REF_1_ 3 -1 7 1 6 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 5 0 1 3 5 6 60 -1 + 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 3 5 7 81 -1 + 10 CLK_000 1 -1 -1 3 0 1 5 10 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +96 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 319 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 5 29 -1 1 0 21 + 30 LDS_000 5 322 3 0 30 -1 12 0 21 + 31 UDS_000 5 321 3 0 31 -1 8 0 21 + 65 E 5 326 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 328 3 0 33 -1 3 0 20 + 28 BG_000 5 323 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 318 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 330 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 329 1 0 6 -1 3 0 21 + 82 BGACK_030 5 324 7 0 82 -1 2 0 21 + 77 FPU_CS 5 325 7 0 77 -1 2 0 21 + 34 VMA 5 327 3 0 34 -1 2 0 21 + 32 AS_000 5 320 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 7 6 0 1 3 5 6 7 -1 -1 1 0 20 + 296 inst_AS_030_000_SYNC 3 -1 0 4 0 3 6 7 -1 -1 4 0 21 + 301 inst_CLK_000_D1 3 -1 7 4 1 3 6 7 -1 -1 1 0 20 + 295 cpu_est_1_ 3 -1 6 3 0 3 6 -1 -1 4 0 21 + 326 RN_E 3 65 6 3 0 3 6 65 -1 3 0 21 + 314 SM_AMIGA_3_ 3 -1 7 3 0 5 7 -1 -1 3 0 21 + 303 cpu_est_2_ 3 -1 6 3 0 3 6 -1 -1 3 1 21 + 294 cpu_est_0_ 3 -1 6 3 0 3 6 -1 -1 3 0 21 + 325 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 298 inst_VPA_D 3 -1 6 3 0 3 5 -1 -1 1 0 21 + 305 SM_AMIGA_6_ 3 -1 3 2 3 6 -1 -1 4 0 21 + 306 SM_AMIGA_7_ 3 -1 7 2 3 7 -1 -1 3 0 21 + 302 inst_CLK_OUT_PRE 3 -1 6 2 1 6 -1 -1 3 1 21 + 327 RN_VMA 3 34 3 2 0 3 34 -1 2 0 21 + 324 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 315 SM_AMIGA_5_ 3 -1 6 2 6 7 -1 -1 2 0 20 + 309 SM_AMIGA_4_ 3 -1 7 2 3 7 -1 -1 2 0 21 + 299 inst_VPA_SYNC 3 -1 0 2 0 7 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 5 2 5 7 -1 -1 2 0 21 + 322 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 321 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 330 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 329 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 328 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 323 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 318 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 316 SM_AMIGA_2_ 3 -1 7 1 7 -1 -1 3 0 21 + 320 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 319 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 317 SM_AMIGA_0_ 3 -1 7 1 7 -1 -1 2 0 21 + 313 CLK_CNT_1_ 3 -1 6 1 6 -1 -1 2 0 21 + 312 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 2 0 21 + 307 SM_AMIGA_1_ 3 -1 7 1 7 -1 -1 2 0 21 + 311 inst_CLK_000_D3 3 -1 1 1 7 -1 -1 1 0 20 + 310 inst_CLK_000_D2 3 -1 7 1 1 -1 -1 1 0 20 + 308 inst_CLK_000_D4 3 -1 7 1 7 -1 -1 1 0 20 + 304 CLK_REF_1_ 3 -1 7 1 6 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 6 0 1 3 5 6 7 60 -1 + 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 3 5 7 81 -1 + 63 CLK_030 1 -1 -1 3 0 3 7 63 -1 + 10 CLK_000 1 -1 -1 3 0 5 7 10 -1 + 96 A_19_ 1 -1 -1 2 0 7 96 -1 + 95 A_16_ 1 -1 -1 2 0 7 95 -1 + 94 A_18_ 1 -1 -1 2 0 7 94 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 58 A_17_ 1 -1 -1 2 0 7 58 -1 + 57 FC_1_ 1 -1 -1 2 0 7 57 -1 + 56 FC_0_ 1 -1 -1 2 0 7 56 -1 + 27 BGACK_000 1 -1 -1 2 0 7 27 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 3 0 3 7 -1 -1 +96 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 319 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 5 29 -1 1 0 21 + 30 LDS_000 5 322 3 0 30 -1 12 0 21 + 31 UDS_000 5 321 3 0 31 -1 8 0 21 + 65 E 5 326 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 328 3 0 33 -1 3 0 20 + 28 BG_000 5 323 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 318 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 330 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 329 1 0 6 -1 3 0 21 + 82 BGACK_030 5 324 7 0 82 -1 2 0 21 + 77 FPU_CS 5 325 7 0 77 -1 2 0 21 + 34 VMA 5 327 3 0 34 -1 2 0 21 + 32 AS_000 5 320 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 6 6 0 1 3 5 6 7 -1 -1 1 0 21 + 301 inst_CLK_000_D1 3 -1 7 4 1 3 6 7 -1 -1 1 0 20 + 296 inst_AS_030_000_SYNC 3 -1 0 3 0 3 7 -1 -1 4 0 21 + 295 cpu_est_1_ 3 -1 6 3 0 3 6 -1 -1 4 0 21 + 326 RN_E 3 65 6 3 0 3 6 65 -1 3 0 21 + 314 SM_AMIGA_3_ 3 -1 7 3 0 5 7 -1 -1 3 0 21 + 303 cpu_est_2_ 3 -1 6 3 0 3 6 -1 -1 3 1 21 + 294 cpu_est_0_ 3 -1 3 3 0 3 6 -1 -1 3 0 20 + 325 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 298 inst_VPA_D 3 -1 6 3 0 3 5 -1 -1 1 0 21 + 306 SM_AMIGA_7_ 3 -1 7 2 3 7 -1 -1 4 0 21 + 305 SM_AMIGA_6_ 3 -1 7 2 3 7 -1 -1 4 0 21 + 302 inst_CLK_OUT_PRE 3 -1 6 2 1 6 -1 -1 3 1 21 + 327 RN_VMA 3 34 3 2 0 3 34 -1 2 0 21 + 324 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 320 RN_AS_000 3 32 3 2 3 7 32 -1 2 0 21 + 309 SM_AMIGA_4_ 3 -1 7 2 3 7 -1 -1 2 0 21 + 299 inst_VPA_SYNC 3 -1 0 2 0 7 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 5 2 5 7 -1 -1 2 0 21 + 322 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 321 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 330 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 329 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 328 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 323 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 318 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 317 SM_AMIGA_0_ 3 -1 7 1 7 -1 -1 3 0 21 + 316 SM_AMIGA_2_ 3 -1 7 1 7 -1 -1 3 0 21 + 319 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 315 SM_AMIGA_5_ 3 -1 7 1 7 -1 -1 2 0 21 + 313 CLK_CNT_1_ 3 -1 6 1 6 -1 -1 2 0 21 + 312 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 2 0 21 + 307 SM_AMIGA_1_ 3 -1 7 1 7 -1 -1 2 0 21 + 311 inst_CLK_000_D3 3 -1 1 1 6 -1 -1 1 0 20 + 310 inst_CLK_000_D2 3 -1 7 1 1 -1 -1 1 0 20 + 308 inst_CLK_000_D4 3 -1 6 1 7 -1 -1 1 0 21 + 304 CLK_REF_1_ 3 -1 7 1 6 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 6 0 1 3 5 6 7 60 -1 + 85 RST 1 -1 -1 5 0 1 3 5 7 85 -1 + 81 AS_030 1 -1 -1 4 0 3 5 7 81 -1 + 63 CLK_030 1 -1 -1 3 0 3 7 63 -1 + 10 CLK_000 1 -1 -1 3 0 5 6 10 -1 + 96 A_19_ 1 -1 -1 2 0 7 96 -1 + 95 A_16_ 1 -1 -1 2 0 7 95 -1 + 94 A_18_ 1 -1 -1 2 0 7 94 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 58 A_17_ 1 -1 -1 2 0 7 58 -1 + 57 FC_1_ 1 -1 -1 2 0 7 57 -1 + 56 FC_0_ 1 -1 -1 2 0 7 56 -1 + 27 BGACK_000 1 -1 -1 2 0 7 27 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 3 0 3 7 -1 -1 +95 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 318 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 5 29 -1 1 0 21 + 30 LDS_000 5 321 3 0 30 -1 12 0 21 + 31 UDS_000 5 320 3 0 31 -1 8 0 21 + 65 E 5 325 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 329 3 0 33 -1 3 0 20 + 28 BG_000 5 322 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 317 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 327 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 326 1 0 6 -1 3 0 21 + 82 BGACK_030 5 323 7 0 82 -1 2 0 21 + 77 FPU_CS 5 324 7 0 77 -1 2 0 21 + 34 VMA 5 328 3 0 34 -1 2 0 21 + 32 AS_000 5 319 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 7 6 0 1 3 5 6 7 -1 -1 1 0 20 + 295 cpu_est_1_ 3 -1 7 4 0 3 6 7 -1 -1 4 0 20 + 325 RN_E 3 65 6 4 0 3 6 7 65 -1 3 0 21 + 314 SM_AMIGA_3_ 3 -1 1 4 0 1 5 6 -1 -1 3 0 21 + 303 cpu_est_2_ 3 -1 7 4 0 3 6 7 -1 -1 3 1 20 + 294 cpu_est_0_ 3 -1 3 4 0 3 6 7 -1 -1 3 0 20 + 309 SM_AMIGA_4_ 3 -1 6 4 0 1 3 6 -1 -1 2 0 20 + 301 inst_CLK_000_D1 3 -1 7 4 1 3 6 7 -1 -1 1 0 20 + 305 SM_AMIGA_6_ 3 -1 7 3 0 3 7 -1 -1 3 0 21 + 324 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 315 SM_AMIGA_5_ 3 -1 7 3 0 6 7 -1 -1 2 0 21 + 307 SM_AMIGA_1_ 3 -1 6 3 0 6 7 -1 -1 2 0 20 + 299 inst_VPA_SYNC 3 -1 0 3 0 1 6 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 5 3 1 5 6 -1 -1 2 0 21 + 298 inst_VPA_D 3 -1 7 3 0 3 5 -1 -1 1 0 20 + 296 inst_AS_030_000_SYNC 3 -1 7 2 3 7 -1 -1 4 0 21 + 316 SM_AMIGA_2_ 3 -1 6 2 0 6 -1 -1 3 0 20 + 302 inst_CLK_OUT_PRE 3 -1 6 2 1 6 -1 -1 3 1 21 + 328 RN_VMA 3 34 3 2 0 3 34 -1 2 0 21 + 323 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 306 SM_AMIGA_7_ 3 -1 0 2 3 7 -1 -1 1 0 21 + 321 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 320 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 329 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 327 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 326 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 322 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 319 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 318 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 313 CLK_CNT_1_ 3 -1 6 1 6 -1 -1 2 0 21 + 312 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 2 0 21 + 311 inst_CLK_000_D3 3 -1 6 1 6 -1 -1 1 0 21 + 310 inst_CLK_000_D2 3 -1 3 1 6 -1 -1 1 0 20 + 308 inst_CLK_000_D4 3 -1 6 1 7 -1 -1 1 0 21 + 304 CLK_REF_1_ 3 -1 7 1 6 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 6 0 1 3 5 6 7 60 -1 + 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 3 5 7 81 -1 + 10 CLK_000 1 -1 -1 3 0 5 7 10 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 7 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +95 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 318 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 5 29 -1 1 0 21 + 30 LDS_000 5 321 3 0 30 -1 13 0 21 + 31 UDS_000 5 320 3 0 31 -1 9 0 21 + 65 E 5 325 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 329 3 0 33 -1 3 0 20 + 28 BG_000 5 322 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 317 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 328 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 327 1 0 6 -1 3 0 21 + 82 BGACK_030 5 323 7 0 82 -1 2 0 21 + 77 FPU_CS 5 324 7 0 77 -1 2 0 21 + 34 VMA 5 326 3 0 34 -1 2 0 21 + 32 AS_000 5 319 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 1 6 0 1 3 5 6 7 -1 -1 1 0 20 + 301 inst_CLK_000_D1 3 -1 6 4 1 3 6 7 -1 -1 1 0 21 + 296 inst_AS_030_000_SYNC 3 -1 7 3 1 3 7 -1 -1 4 0 21 + 295 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 20 + 325 RN_E 3 65 6 3 0 3 6 65 -1 3 0 21 + 312 SM_AMIGA_3_ 3 -1 6 3 0 5 6 -1 -1 3 0 20 + 305 SM_AMIGA_6_ 3 -1 3 3 1 3 6 -1 -1 3 0 21 + 303 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 3 1 20 + 294 cpu_est_0_ 3 -1 6 3 0 3 6 -1 -1 3 0 21 + 324 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 307 SM_AMIGA_1_ 3 -1 1 3 1 6 7 -1 -1 2 0 21 + 298 inst_VPA_D 3 -1 1 3 0 3 5 -1 -1 1 0 20 + 329 RN_AMIGA_BUS_ENABLE 3 33 3 2 1 3 33 -1 3 0 20 + 313 SM_AMIGA_2_ 3 -1 6 2 1 6 -1 -1 3 0 20 + 302 inst_CLK_OUT_PRE 3 -1 6 2 1 6 -1 -1 3 1 21 + 326 RN_VMA 3 34 3 2 0 3 34 -1 2 0 21 + 323 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 311 SM_AMIGA_5_ 3 -1 1 2 1 6 -1 -1 2 0 21 + 309 SM_AMIGA_4_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 299 inst_VPA_SYNC 3 -1 0 2 0 6 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 5 2 5 6 -1 -1 2 0 21 + 310 inst_CLK_000_D2 3 -1 1 2 3 6 -1 -1 1 0 20 + 321 RN_LDS_000 3 30 3 1 3 30 -1 13 0 21 + 320 RN_UDS_000 3 31 3 1 3 31 -1 9 0 21 + 328 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 327 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 322 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 319 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 318 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 316 CLK_CNT_1_ 3 -1 6 1 6 -1 -1 2 0 21 + 315 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 2 0 21 + 314 inst_CLK_000_D3 3 -1 6 1 1 -1 -1 1 0 21 + 308 inst_CLK_000_D4 3 -1 1 1 7 -1 -1 1 0 20 + 306 SM_AMIGA_7_ 3 -1 6 1 3 -1 -1 1 0 20 + 304 CLK_REF_1_ 3 -1 6 1 6 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 5 0 1 3 5 6 60 -1 + 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 3 5 7 81 -1 + 10 CLK_000 1 -1 -1 3 0 1 5 10 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +94 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 317 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 1 29 -1 1 0 21 + 30 LDS_000 5 320 3 0 30 -1 11 0 21 + 31 UDS_000 5 319 3 0 31 -1 7 0 21 + 65 E 5 324 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 326 3 0 33 -1 3 0 20 + 28 BG_000 5 321 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 316 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 328 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 327 1 0 6 -1 3 0 21 + 82 BGACK_030 5 322 7 0 82 -1 2 0 21 + 77 FPU_CS 5 323 7 0 77 -1 2 0 21 + 34 VMA 5 325 3 0 34 -1 2 0 21 + 32 AS_000 5 318 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 299 inst_CLK_000_D0 3 -1 6 5 0 1 3 6 7 -1 -1 1 0 21 + 300 inst_CLK_000_D1 3 -1 7 4 1 3 6 7 -1 -1 1 0 20 + 295 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 20 + 324 RN_E 3 65 6 3 0 3 6 65 -1 3 0 21 + 311 SM_AMIGA_3_ 3 -1 6 3 0 1 6 -1 -1 3 0 20 + 304 cpu_est_2_ 3 -1 6 3 0 3 6 -1 -1 3 1 21 + 303 SM_AMIGA_6_ 3 -1 7 3 3 6 7 -1 -1 3 0 21 + 302 inst_CLK_OUT_PRE 3 -1 7 3 1 6 7 -1 -1 3 1 20 + 294 cpu_est_0_ 3 -1 3 3 0 3 6 -1 -1 3 0 20 + 323 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 301 inst_CLK_000_D2 3 -1 7 3 3 6 7 -1 -1 1 0 20 + 297 inst_VPA_D 3 -1 6 3 0 1 3 -1 -1 1 0 21 + 308 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 3 0 20 + 325 RN_VMA 3 34 3 2 0 3 34 -1 2 0 21 + 322 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 307 SM_AMIGA_4_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 306 SM_AMIGA_7_ 3 -1 7 2 3 7 -1 -1 2 0 21 + 298 inst_VPA_SYNC 3 -1 0 2 0 6 -1 -1 2 0 21 + 296 inst_DTACK_SYNC 3 -1 1 2 1 6 -1 -1 2 0 21 + 320 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21 + 319 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21 + 312 inst_AS_030_000_SYNC 3 -1 7 1 7 -1 -1 6 0 21 + 315 SM_AMIGA_0_ 3 -1 7 1 7 -1 -1 5 0 21 + 328 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 327 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 326 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 321 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 316 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 314 SM_AMIGA_2_ 3 -1 6 1 6 -1 -1 3 0 20 + 318 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 317 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 313 SM_AMIGA_5_ 3 -1 6 1 6 -1 -1 2 0 20 + 310 CLK_CNT_1_ 3 -1 7 1 7 -1 -1 2 0 20 + 309 CLK_CNT_0_ 3 -1 7 1 7 -1 -1 2 0 20 + 305 CLK_REF_1_ 3 -1 7 1 7 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 4 1 3 6 7 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 1 3 7 81 -1 + 10 CLK_000 1 -1 -1 3 0 1 6 10 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +94 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 317 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 1 29 -1 1 0 21 + 30 LDS_000 5 320 3 0 30 -1 11 0 21 + 31 UDS_000 5 319 3 0 31 -1 7 0 21 + 65 E 5 324 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 326 3 0 33 -1 3 0 20 + 28 BG_000 5 321 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 316 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 328 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 327 1 0 6 -1 3 0 21 + 82 BGACK_030 5 322 7 0 82 -1 2 0 21 + 77 FPU_CS 5 323 7 0 77 -1 2 0 21 + 34 VMA 5 325 3 0 34 -1 2 0 21 + 32 AS_000 5 318 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 299 inst_CLK_000_D0 3 -1 6 5 0 1 3 6 7 -1 -1 1 0 21 + 300 inst_CLK_000_D1 3 -1 7 4 1 3 6 7 -1 -1 1 0 20 + 295 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 20 + 324 RN_E 3 65 6 3 0 3 6 65 -1 3 0 21 + 311 SM_AMIGA_3_ 3 -1 6 3 0 1 6 -1 -1 3 0 20 + 304 cpu_est_2_ 3 -1 6 3 0 3 6 -1 -1 3 1 21 + 303 SM_AMIGA_6_ 3 -1 7 3 3 6 7 -1 -1 3 0 21 + 302 inst_CLK_OUT_PRE 3 -1 7 3 1 6 7 -1 -1 3 1 20 + 294 cpu_est_0_ 3 -1 3 3 0 3 6 -1 -1 3 0 20 + 323 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 301 inst_CLK_000_D2 3 -1 7 3 3 6 7 -1 -1 1 0 20 + 297 inst_VPA_D 3 -1 6 3 0 1 3 -1 -1 1 0 21 + 308 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 3 0 20 + 325 RN_VMA 3 34 3 2 0 3 34 -1 2 0 21 + 322 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 307 SM_AMIGA_4_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 306 SM_AMIGA_7_ 3 -1 7 2 3 7 -1 -1 2 0 21 + 298 inst_VPA_SYNC 3 -1 0 2 0 6 -1 -1 2 0 21 + 296 inst_DTACK_SYNC 3 -1 1 2 1 6 -1 -1 2 0 21 + 320 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21 + 319 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21 + 312 inst_AS_030_000_SYNC 3 -1 7 1 7 -1 -1 6 0 21 + 315 SM_AMIGA_0_ 3 -1 7 1 7 -1 -1 5 0 21 + 328 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 327 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 326 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 321 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 316 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 314 SM_AMIGA_2_ 3 -1 6 1 6 -1 -1 3 0 20 + 318 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 317 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 313 SM_AMIGA_5_ 3 -1 6 1 6 -1 -1 2 0 20 + 310 CLK_CNT_1_ 3 -1 7 1 7 -1 -1 2 0 20 + 309 CLK_CNT_0_ 3 -1 7 1 7 -1 -1 2 0 20 + 305 CLK_REF_1_ 3 -1 7 1 7 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 4 1 3 6 7 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 1 3 7 81 -1 + 10 CLK_000 1 -1 -1 3 0 1 6 10 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +93 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 316 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 1 29 -1 1 0 21 + 30 LDS_000 5 319 3 0 30 -1 10 0 21 + 31 UDS_000 5 318 3 0 31 -1 6 0 21 + 65 E 5 323 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 325 3 0 33 -1 3 0 20 + 28 BG_000 5 320 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 315 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 327 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 326 1 0 6 -1 3 0 21 + 82 BGACK_030 5 321 7 0 82 -1 2 0 21 + 77 FPU_CS 5 322 7 0 77 -1 2 0 21 + 34 VMA 5 324 3 0 34 -1 2 0 21 + 32 AS_000 5 317 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 299 inst_CLK_000_D0 3 -1 6 5 0 1 3 6 7 -1 -1 1 0 21 + 295 cpu_est_1_ 3 -1 6 3 0 3 6 -1 -1 4 0 21 + 323 RN_E 3 65 6 3 0 3 6 65 -1 3 0 21 + 311 SM_AMIGA_3_ 3 -1 7 3 0 1 7 -1 -1 3 0 21 + 304 cpu_est_2_ 3 -1 6 3 0 3 6 -1 -1 3 1 21 + 301 inst_CLK_OUT_PRE 3 -1 6 3 1 6 7 -1 -1 3 1 21 + 294 cpu_est_0_ 3 -1 6 3 0 3 6 -1 -1 3 0 21 + 322 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 300 inst_CLK_000_D1 3 -1 3 3 1 6 7 -1 -1 1 0 20 + 297 inst_VPA_D 3 -1 7 3 0 1 3 -1 -1 1 0 20 + 324 RN_VMA 3 34 3 2 0 3 34 -1 2 0 21 + 321 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 308 SM_AMIGA_4_ 3 -1 3 2 3 7 -1 -1 2 0 21 + 306 SM_AMIGA_7_ 3 -1 7 2 3 7 -1 -1 2 0 21 + 303 SM_AMIGA_6_ 3 -1 7 2 3 7 -1 -1 2 0 21 + 298 inst_VPA_SYNC 3 -1 0 2 0 7 -1 -1 2 0 21 + 296 inst_DTACK_SYNC 3 -1 1 2 1 7 -1 -1 2 0 21 + 319 RN_LDS_000 3 30 3 1 3 30 -1 10 0 21 + 318 RN_UDS_000 3 31 3 1 3 31 -1 6 0 21 + 312 inst_AS_030_000_SYNC 3 -1 7 1 7 -1 -1 6 0 21 + 314 SM_AMIGA_0_ 3 -1 7 1 7 -1 -1 4 0 21 + 327 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 326 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 325 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 320 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 315 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 313 SM_AMIGA_2_ 3 -1 7 1 7 -1 -1 3 0 21 + 307 SM_AMIGA_1_ 3 -1 7 1 7 -1 -1 3 0 21 + 317 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 316 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 310 CLK_CNT_1_ 3 -1 6 1 6 -1 -1 2 0 21 + 309 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 2 0 21 + 302 SM_AMIGA_5_ 3 -1 3 1 3 -1 -1 2 0 21 + 305 CLK_REF_1_ 3 -1 7 1 6 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 4 1 3 6 7 60 -1 + 85 RST 1 -1 -1 4 0 1 3 7 85 -1 + 81 AS_030 1 -1 -1 4 0 1 3 7 81 -1 + 10 CLK_000 1 -1 -1 3 0 1 6 10 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 7 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +93 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 316 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 + 30 LDS_000 5 319 3 0 30 -1 10 0 21 + 31 UDS_000 5 318 3 0 31 -1 6 0 21 + 65 E 5 323 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 325 3 0 33 -1 3 0 20 + 8 IPL_030_2_ 5 315 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 327 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 326 1 0 6 -1 3 0 21 + 82 BGACK_030 5 321 7 0 82 -1 2 0 21 + 77 FPU_CS 5 322 7 0 77 -1 2 0 21 + 34 VMA 5 324 3 0 34 -1 2 0 21 + 32 AS_000 5 317 3 0 32 -1 2 0 21 + 28 BG_000 5 320 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 299 inst_CLK_000_D0 3 -1 7 5 0 1 3 6 7 -1 -1 1 0 20 + 300 inst_CLK_000_D1 3 -1 7 4 1 3 6 7 -1 -1 1 0 20 + 295 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 20 + 323 RN_E 3 65 6 3 0 3 6 65 -1 3 0 21 + 313 SM_AMIGA_2_ 3 -1 6 3 1 6 7 -1 -1 3 0 20 + 311 SM_AMIGA_3_ 3 -1 6 3 0 1 6 -1 -1 3 0 20 + 307 SM_AMIGA_1_ 3 -1 7 3 1 6 7 -1 -1 3 0 21 + 304 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 3 1 20 + 301 inst_CLK_OUT_PRE 3 -1 6 3 1 6 7 -1 -1 3 1 21 + 294 cpu_est_0_ 3 -1 3 3 0 3 6 -1 -1 3 0 20 + 322 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 317 RN_AS_000 3 32 3 3 1 3 6 32 -1 2 0 21 + 308 SM_AMIGA_4_ 3 -1 3 3 1 3 6 -1 -1 2 0 21 + 303 SM_AMIGA_6_ 3 -1 7 3 1 3 7 -1 -1 2 0 21 + 302 SM_AMIGA_5_ 3 -1 7 3 1 3 7 -1 -1 2 0 21 + 297 inst_VPA_D 3 -1 7 3 0 3 6 -1 -1 1 0 20 + 312 inst_AS_030_000_SYNC 3 -1 7 2 1 7 -1 -1 7 0 21 + 306 SM_AMIGA_7_ 3 -1 1 2 3 7 -1 -1 4 0 21 + 314 SM_AMIGA_0_ 3 -1 6 2 1 6 -1 -1 3 0 20 + 324 RN_VMA 3 34 3 2 0 3 34 -1 2 0 21 + 321 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 298 inst_VPA_SYNC 3 -1 0 2 0 6 -1 -1 2 0 21 + 319 RN_LDS_000 3 30 3 1 3 30 -1 10 0 21 + 318 RN_UDS_000 3 31 3 1 3 31 -1 6 0 21 + 327 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 326 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 325 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 315 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 320 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 316 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 310 CLK_CNT_1_ 3 -1 6 1 6 -1 -1 2 0 21 + 309 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 2 0 21 + 296 inst_DTACK_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 305 CLK_REF_1_ 3 -1 7 1 6 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 5 0 1 3 6 7 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 3 6 7 81 -1 + 10 CLK_000 1 -1 -1 3 0 6 7 10 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 7 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 3 1 3 7 -1 -1 +96 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 319 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 0 29 -1 1 0 21 + 30 LDS_000 5 322 3 0 30 -1 10 0 21 + 31 UDS_000 5 321 3 0 31 -1 6 0 21 + 65 E 5 326 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 328 3 0 33 -1 3 0 20 + 8 IPL_030_2_ 5 318 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 330 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 329 1 0 6 -1 3 0 21 + 82 BGACK_030 5 324 7 0 82 -1 2 0 21 + 77 FPU_CS 5 325 7 0 77 -1 2 0 21 + 34 VMA 5 327 3 0 34 -1 2 0 21 + 32 AS_000 5 320 3 0 32 -1 2 0 21 + 28 BG_000 5 323 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 7 6 0 1 3 5 6 7 -1 -1 1 0 20 + 294 cpu_est_0_ 3 -1 7 4 3 5 6 7 -1 -1 3 0 20 + 295 cpu_est_1_ 3 -1 6 3 3 5 6 -1 -1 4 0 21 + 326 RN_E 3 65 6 3 3 5 6 65 -1 3 0 21 + 315 SM_AMIGA_3_ 3 -1 6 3 0 5 6 -1 -1 3 0 20 + 306 cpu_est_2_ 3 -1 6 3 3 5 6 -1 -1 3 1 21 + 303 inst_CLK_OUT_PRE 3 -1 6 3 1 6 7 -1 -1 3 1 21 + 325 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 301 inst_CLK_000_D1 3 -1 3 3 1 6 7 -1 -1 1 0 20 + 298 inst_VPA_D 3 -1 1 3 0 3 5 -1 -1 1 0 20 + 308 SM_AMIGA_7_ 3 -1 7 2 3 7 -1 -1 5 0 21 + 310 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 3 0 20 + 327 RN_VMA 3 34 3 2 3 5 34 -1 2 0 21 + 324 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 320 RN_AS_000 3 32 3 2 3 7 32 -1 2 0 21 + 312 SM_AMIGA_4_ 3 -1 3 2 3 6 -1 -1 2 0 21 + 304 SM_AMIGA_6_ 3 -1 7 2 3 7 -1 -1 2 0 21 + 299 inst_VPA_SYNC 3 -1 5 2 5 6 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 0 2 0 6 -1 -1 2 0 21 + 322 RN_LDS_000 3 30 3 1 3 30 -1 10 0 21 + 296 inst_AS_030_000_SYNC 3 -1 7 1 7 -1 -1 7 0 21 + 321 RN_UDS_000 3 31 3 1 3 31 -1 6 0 21 + 330 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 329 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 328 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 318 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 317 SM_AMIGA_0_ 3 -1 7 1 7 -1 -1 3 0 21 + 316 SM_AMIGA_2_ 3 -1 6 1 6 -1 -1 3 0 20 + 323 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 319 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 314 CLK_CNT_1_ 3 -1 6 1 6 -1 -1 2 0 21 + 313 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 2 0 21 + 305 SM_AMIGA_5_ 3 -1 3 1 3 -1 -1 2 0 21 + 311 inst_CLK_000_D2 3 -1 7 1 7 -1 -1 1 0 20 + 309 inst_CLK_000_D4 3 -1 7 1 7 -1 -1 1 0 20 + 307 CLK_REF_1_ 3 -1 3 1 6 -1 -1 1 0 20 + 302 inst_CLK_000_D3 3 -1 7 1 7 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 4 1 3 6 7 60 -1 + 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 3 5 7 81 -1 + 10 CLK_000 1 -1 -1 3 0 5 7 10 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +95 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 318 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 1 29 -1 1 0 21 + 30 LDS_000 5 321 3 0 30 -1 10 0 21 + 31 UDS_000 5 320 3 0 31 -1 6 0 21 + 65 E 5 325 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 327 3 0 33 -1 3 0 20 + 8 IPL_030_2_ 5 317 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 329 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 328 1 0 6 -1 3 0 21 + 82 BGACK_030 5 323 7 0 82 -1 2 0 21 + 77 FPU_CS 5 324 7 0 77 -1 2 0 21 + 34 VMA 5 326 3 0 34 -1 2 0 21 + 32 AS_000 5 319 3 0 32 -1 2 0 21 + 28 BG_000 5 322 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 7 5 0 1 3 6 7 -1 -1 1 0 20 + 301 inst_CLK_000_D1 3 -1 3 4 1 3 6 7 -1 -1 1 0 20 + 295 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 20 + 325 RN_E 3 65 6 3 0 3 6 65 -1 3 0 21 + 314 SM_AMIGA_3_ 3 -1 6 3 0 1 6 -1 -1 3 0 20 + 306 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 3 1 20 + 303 inst_CLK_OUT_PRE 3 -1 6 3 1 6 7 -1 -1 3 1 21 + 294 cpu_est_0_ 3 -1 6 3 0 3 6 -1 -1 3 0 21 + 324 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 304 SM_AMIGA_6_ 3 -1 7 3 3 6 7 -1 -1 2 0 21 + 298 inst_VPA_D 3 -1 7 3 0 1 3 -1 -1 1 0 20 + 308 SM_AMIGA_7_ 3 -1 7 2 3 7 -1 -1 5 0 21 + 315 SM_AMIGA_2_ 3 -1 6 2 6 7 -1 -1 3 0 20 + 326 RN_VMA 3 34 3 2 0 3 34 -1 2 0 21 + 323 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 319 RN_AS_000 3 32 3 2 3 7 32 -1 2 0 21 + 311 SM_AMIGA_4_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 305 SM_AMIGA_5_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 299 inst_VPA_SYNC 3 -1 0 2 0 6 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 1 2 1 6 -1 -1 2 0 21 + 321 RN_LDS_000 3 30 3 1 3 30 -1 10 0 21 + 296 inst_AS_030_000_SYNC 3 -1 7 1 7 -1 -1 7 0 21 + 320 RN_UDS_000 3 31 3 1 3 31 -1 6 0 21 + 329 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 328 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 327 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 316 SM_AMIGA_0_ 3 -1 7 1 7 -1 -1 3 0 21 + 310 SM_AMIGA_1_ 3 -1 7 1 7 -1 -1 3 0 21 + 322 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 318 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 313 CLK_CNT_1_ 3 -1 6 1 6 -1 -1 2 0 21 + 312 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 2 0 21 + 309 inst_CLK_000_D3 3 -1 7 1 7 -1 -1 1 0 20 + 307 CLK_REF_1_ 3 -1 7 1 6 -1 -1 1 0 20 + 302 inst_CLK_000_D2 3 -1 3 1 7 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 4 1 3 6 7 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 1 3 7 81 -1 + 10 CLK_000 1 -1 -1 3 0 1 7 10 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 7 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +97 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 320 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 2 29 -1 1 0 21 + 30 LDS_000 5 323 3 0 30 -1 10 0 21 + 31 UDS_000 5 322 3 0 31 -1 6 0 21 + 65 E 5 327 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 329 3 0 33 -1 3 0 20 + 8 IPL_030_2_ 5 319 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 331 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 330 1 0 6 -1 3 0 21 + 82 BGACK_030 5 325 7 0 82 -1 2 0 21 + 77 FPU_CS 5 326 7 0 77 -1 2 0 21 + 34 VMA 5 328 3 0 34 -1 2 0 21 + 32 AS_000 5 321 3 0 32 -1 2 0 21 + 28 BG_000 5 324 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 20 + 316 SM_AMIGA_3_ 3 -1 1 4 0 1 2 5 -1 -1 3 0 21 + 301 inst_CLK_000_D1 3 -1 3 4 1 3 6 7 -1 -1 1 0 20 + 309 SM_AMIGA_7_ 3 -1 6 3 3 6 7 -1 -1 5 0 20 + 295 cpu_est_1_ 3 -1 6 3 3 5 6 -1 -1 4 0 21 + 327 RN_E 3 65 6 3 3 5 6 65 -1 3 0 21 + 307 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 3 1 20 + 294 cpu_est_0_ 3 -1 3 3 3 5 6 -1 -1 3 0 20 + 326 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 305 SM_AMIGA_6_ 3 -1 6 3 3 6 7 -1 -1 2 0 20 + 299 inst_VPA_SYNC 3 -1 5 3 0 1 5 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 2 3 0 1 2 -1 -1 2 0 21 + 298 inst_VPA_D 3 -1 0 3 2 3 5 -1 -1 1 0 20 + 296 inst_AS_030_000_SYNC 3 -1 7 2 6 7 -1 -1 7 0 21 + 317 SM_AMIGA_2_ 3 -1 0 2 0 6 -1 -1 3 0 21 + 315 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 3 0 20 + 304 inst_CLK_OUT_PRE 3 -1 6 2 1 6 -1 -1 3 1 21 + 328 RN_VMA 3 34 3 2 3 5 34 -1 2 0 21 + 325 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 321 RN_AS_000 3 32 3 2 3 6 32 -1 2 0 21 + 312 SM_AMIGA_4_ 3 -1 3 2 1 3 -1 -1 2 0 21 + 306 SM_AMIGA_5_ 3 -1 7 2 3 7 -1 -1 2 0 21 + 311 inst_CLK_000_D4 3 -1 7 2 6 7 -1 -1 1 0 20 + 310 inst_CLK_000_D3 3 -1 7 2 6 7 -1 -1 1 0 20 + 303 inst_CLK_000_D5 3 -1 7 2 6 7 -1 -1 1 0 20 + 302 inst_CLK_000_D2 3 -1 7 2 6 7 -1 -1 1 0 20 + 323 RN_LDS_000 3 30 3 1 3 30 -1 10 0 21 + 322 RN_UDS_000 3 31 3 1 3 31 -1 6 0 21 + 318 SM_AMIGA_0_ 3 -1 6 1 6 -1 -1 4 0 20 + 331 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 330 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 329 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 319 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 324 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 320 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 314 CLK_CNT_1_ 3 -1 6 1 6 -1 -1 2 0 21 + 313 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 2 0 21 + 308 CLK_REF_1_ 3 -1 3 1 6 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 7 0 1 2 3 5 6 7 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 81 AS_030 1 -1 -1 4 2 3 5 7 81 -1 + 10 CLK_000 1 -1 -1 3 2 5 7 10 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 3 3 6 7 -1 -1 +97 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 320 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 + 30 LDS_000 5 323 3 0 30 -1 10 0 21 + 31 UDS_000 5 322 3 0 31 -1 6 0 21 + 65 E 5 327 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 329 3 0 33 -1 3 0 20 + 8 IPL_030_2_ 5 319 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 331 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 330 1 0 6 -1 3 0 21 + 82 BGACK_030 5 325 7 0 82 -1 2 0 21 + 77 FPU_CS 5 326 7 0 77 -1 2 0 21 + 34 VMA 5 328 3 0 34 -1 2 0 21 + 32 AS_000 5 321 3 0 32 -1 2 0 21 + 28 BG_000 5 324 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 7 6 0 1 3 5 6 7 -1 -1 1 0 20 + 305 SM_AMIGA_6_ 3 -1 7 4 0 3 6 7 -1 -1 2 0 21 + 301 inst_CLK_000_D1 3 -1 7 4 1 3 6 7 -1 -1 1 0 20 + 310 SM_AMIGA_7_ 3 -1 0 3 0 3 7 -1 -1 5 0 21 + 326 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 321 RN_AS_000 3 32 3 3 0 1 3 32 -1 2 0 21 + 308 SM_AMIGA_1_ 3 -1 5 3 1 5 7 -1 -1 2 0 21 + 296 inst_AS_030_000_SYNC 3 -1 7 2 0 7 -1 -1 7 0 21 + 295 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 20 + 327 RN_E 3 65 6 2 3 6 65 -1 3 0 21 + 318 SM_AMIGA_0_ 3 -1 1 2 0 1 -1 -1 3 0 21 + 317 SM_AMIGA_2_ 3 -1 6 2 5 6 -1 -1 3 0 20 + 306 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21 + 303 inst_CLK_OUT_PRE 3 -1 6 2 1 6 -1 -1 3 1 21 + 294 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 20 + 328 RN_VMA 3 34 3 2 3 6 34 -1 2 0 21 + 325 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 314 CLK_CNT_1_ 3 -1 7 2 6 7 -1 -1 2 0 20 + 313 CLK_CNT_0_ 3 -1 7 2 6 7 -1 -1 2 0 20 + 312 SM_AMIGA_4_ 3 -1 3 2 3 6 -1 -1 2 0 21 + 304 SM_AMIGA_5_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 311 inst_CLK_000_D3 3 -1 7 2 0 7 -1 -1 1 0 20 + 307 CLK_REF_1_ 3 -1 7 2 6 7 -1 -1 1 0 20 + 302 inst_CLK_000_D2 3 -1 3 2 0 7 -1 -1 1 0 20 + 298 inst_VPA_D 3 -1 6 2 3 6 -1 -1 1 0 21 + 323 RN_LDS_000 3 30 3 1 3 30 -1 10 0 21 + 322 RN_UDS_000 3 31 3 1 3 31 -1 6 0 21 + 331 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 330 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 329 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 319 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 316 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 3 0 20 + 324 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 320 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 299 inst_VPA_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 297 inst_DTACK_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 315 inst_CLK_000_D4 3 -1 7 1 7 -1 -1 1 0 20 + 309 inst_CLK_000_D5 3 -1 7 1 7 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 6 0 1 3 5 6 7 60 -1 + 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1 + 10 CLK_000 1 -1 -1 4 1 5 6 7 10 -1 + 81 AS_030 1 -1 -1 3 3 6 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 3 0 3 7 -1 -1 +97 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 320 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 0 29 -1 1 0 21 + 30 LDS_000 5 323 3 0 30 -1 10 0 21 + 31 UDS_000 5 322 3 0 31 -1 6 0 21 + 65 E 5 327 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 329 3 0 33 -1 3 0 20 + 8 IPL_030_2_ 5 319 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 331 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 330 1 0 6 -1 3 0 21 + 82 BGACK_030 5 325 7 0 82 -1 2 0 21 + 77 FPU_CS 5 326 7 0 77 -1 2 0 21 + 34 VMA 5 328 3 0 34 -1 2 0 21 + 32 AS_000 5 321 3 0 32 -1 2 0 21 + 28 BG_000 5 324 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 20 + 306 SM_AMIGA_6_ 3 -1 7 4 2 3 6 7 -1 -1 2 0 21 + 301 inst_CLK_000_D1 3 -1 3 4 1 3 6 7 -1 -1 1 0 20 + 309 SM_AMIGA_7_ 3 -1 2 3 2 3 7 -1 -1 5 0 21 + 295 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 4 0 20 + 327 RN_E 3 65 6 3 3 5 6 65 -1 3 0 21 + 316 SM_AMIGA_3_ 3 -1 6 3 0 5 6 -1 -1 3 0 20 + 315 SM_AMIGA_1_ 3 -1 1 3 0 1 7 -1 -1 3 0 21 + 307 cpu_est_2_ 3 -1 6 3 3 5 6 -1 -1 3 1 21 + 294 cpu_est_0_ 3 -1 3 3 3 5 6 -1 -1 3 0 20 + 326 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 321 RN_AS_000 3 32 3 3 0 2 3 32 -1 2 0 21 + 311 inst_CLK_000_D4 3 -1 7 3 0 1 7 -1 -1 1 0 20 + 303 inst_CLK_000_D5 3 -1 7 3 0 1 7 -1 -1 1 0 20 + 298 inst_VPA_D 3 -1 6 3 0 3 5 -1 -1 1 0 21 + 296 inst_AS_030_000_SYNC 3 -1 7 2 2 7 -1 -1 7 0 21 + 318 SM_AMIGA_0_ 3 -1 0 2 0 2 -1 -1 4 0 21 + 317 SM_AMIGA_2_ 3 -1 6 2 1 6 -1 -1 3 0 20 + 304 inst_CLK_OUT_PRE 3 -1 6 2 1 6 -1 -1 3 1 21 + 328 RN_VMA 3 34 3 2 3 5 34 -1 2 0 21 + 325 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 312 SM_AMIGA_4_ 3 -1 3 2 3 6 -1 -1 2 0 21 + 305 SM_AMIGA_5_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 299 inst_VPA_SYNC 3 -1 5 2 5 6 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 0 2 0 6 -1 -1 2 0 21 + 310 inst_CLK_000_D3 3 -1 7 2 2 7 -1 -1 1 0 20 + 302 inst_CLK_000_D2 3 -1 7 2 2 7 -1 -1 1 0 20 + 323 RN_LDS_000 3 30 3 1 3 30 -1 10 0 21 + 322 RN_UDS_000 3 31 3 1 3 31 -1 6 0 21 + 331 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 330 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 329 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 319 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 324 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 320 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 314 CLK_CNT_1_ 3 -1 6 1 6 -1 -1 2 0 21 + 313 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 2 0 21 + 308 CLK_REF_1_ 3 -1 3 1 6 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 7 0 1 2 3 5 6 7 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 3 5 7 81 -1 + 10 CLK_000 1 -1 -1 4 0 1 5 7 10 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 3 2 3 7 -1 -1 +96 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 319 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 1 29 -1 1 0 21 + 30 LDS_000 5 322 3 0 30 -1 10 0 21 + 31 UDS_000 5 321 3 0 31 -1 6 0 21 + 65 E 5 326 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 328 3 0 33 -1 3 0 20 + 8 IPL_030_2_ 5 318 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 330 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 329 1 0 6 -1 3 0 21 + 82 BGACK_030 5 324 7 0 82 -1 2 0 21 + 77 FPU_CS 5 325 7 0 77 -1 2 0 21 + 34 VMA 5 327 3 0 34 -1 2 0 21 + 32 AS_000 5 320 3 0 32 -1 2 0 21 + 28 BG_000 5 323 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 7 5 0 1 3 6 7 -1 -1 1 0 20 + 301 inst_CLK_000_D1 3 -1 7 4 1 3 6 7 -1 -1 1 0 20 + 295 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 20 + 326 RN_E 3 65 6 3 0 3 6 65 -1 3 0 21 + 315 SM_AMIGA_3_ 3 -1 6 3 0 1 6 -1 -1 3 0 20 + 307 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 3 1 20 + 294 cpu_est_0_ 3 -1 3 3 0 3 6 -1 -1 3 0 20 + 325 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 298 inst_VPA_D 3 -1 6 3 0 1 3 -1 -1 1 0 21 + 309 SM_AMIGA_7_ 3 -1 7 2 3 7 -1 -1 5 0 21 + 314 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 3 0 20 + 304 inst_CLK_OUT_PRE 3 -1 6 2 1 6 -1 -1 3 1 21 + 327 RN_VMA 3 34 3 2 0 3 34 -1 2 0 21 + 324 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 320 RN_AS_000 3 32 3 2 3 7 32 -1 2 0 21 + 311 SM_AMIGA_4_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 306 SM_AMIGA_6_ 3 -1 7 2 3 7 -1 -1 2 0 21 + 305 SM_AMIGA_5_ 3 -1 3 2 3 6 -1 -1 2 0 21 + 299 inst_VPA_SYNC 3 -1 0 2 0 6 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 1 2 1 6 -1 -1 2 0 21 + 310 inst_CLK_000_D3 3 -1 7 2 6 7 -1 -1 1 0 20 + 303 inst_CLK_000_D4 3 -1 7 2 6 7 -1 -1 1 0 20 + 322 RN_LDS_000 3 30 3 1 3 30 -1 10 0 21 + 296 inst_AS_030_000_SYNC 3 -1 7 1 7 -1 -1 7 0 21 + 321 RN_UDS_000 3 31 3 1 3 31 -1 6 0 21 + 317 SM_AMIGA_0_ 3 -1 7 1 7 -1 -1 4 0 21 + 330 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 329 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 328 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 318 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 316 SM_AMIGA_2_ 3 -1 6 1 6 -1 -1 3 0 20 + 323 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 319 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 313 CLK_CNT_1_ 3 -1 6 1 6 -1 -1 2 0 21 + 312 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 2 0 21 + 308 CLK_REF_1_ 3 -1 7 1 6 -1 -1 1 0 20 + 302 inst_CLK_000_D2 3 -1 7 1 7 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 4 1 3 6 7 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 1 3 7 81 -1 + 10 CLK_000 1 -1 -1 4 0 1 6 7 10 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +95 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 318 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 + 30 LDS_000 5 321 3 0 30 -1 10 0 21 + 31 UDS_000 5 320 3 0 31 -1 6 0 21 + 65 E 5 325 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 327 3 0 33 -1 3 0 20 + 8 IPL_030_2_ 5 317 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 329 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 328 1 0 6 -1 3 0 21 + 82 BGACK_030 5 323 7 0 82 -1 2 0 21 + 77 FPU_CS 5 324 7 0 77 -1 2 0 21 + 34 VMA 5 326 3 0 34 -1 2 0 21 + 32 AS_000 5 319 3 0 32 -1 2 0 21 + 28 BG_000 5 322 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 6 5 0 1 3 6 7 -1 -1 1 0 21 + 306 SM_AMIGA_6_ 3 -1 7 4 0 3 6 7 -1 -1 2 0 21 + 303 inst_CLK_000_D3 3 -1 7 4 0 1 6 7 -1 -1 1 0 20 + 302 inst_CLK_000_D2 3 -1 3 4 0 1 6 7 -1 -1 1 0 20 + 301 inst_CLK_000_D1 3 -1 7 4 1 3 6 7 -1 -1 1 0 20 + 309 SM_AMIGA_7_ 3 -1 0 3 0 3 7 -1 -1 5 0 21 + 313 SM_AMIGA_1_ 3 -1 6 3 1 6 7 -1 -1 3 0 20 + 294 cpu_est_0_ 3 -1 7 3 3 6 7 -1 -1 3 0 20 + 324 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 319 RN_AS_000 3 32 3 3 0 1 3 32 -1 2 0 21 + 296 inst_AS_030_000_SYNC 3 -1 7 2 0 7 -1 -1 7 0 21 + 316 SM_AMIGA_0_ 3 -1 1 2 0 1 -1 -1 4 0 21 + 295 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 20 + 325 RN_E 3 65 6 2 3 6 65 -1 3 0 21 + 307 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 1 20 + 304 inst_CLK_OUT_PRE 3 -1 6 2 1 6 -1 -1 3 1 21 + 326 RN_VMA 3 34 3 2 3 6 34 -1 2 0 21 + 323 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 312 CLK_CNT_1_ 3 -1 7 2 6 7 -1 -1 2 0 20 + 311 CLK_CNT_0_ 3 -1 7 2 6 7 -1 -1 2 0 20 + 310 SM_AMIGA_4_ 3 -1 3 2 3 6 -1 -1 2 0 21 + 305 SM_AMIGA_5_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 308 CLK_REF_1_ 3 -1 7 2 6 7 -1 -1 1 0 20 + 298 inst_VPA_D 3 -1 7 2 3 6 -1 -1 1 0 20 + 321 RN_LDS_000 3 30 3 1 3 30 -1 10 0 21 + 320 RN_UDS_000 3 31 3 1 3 31 -1 6 0 21 + 329 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 328 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 327 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 315 SM_AMIGA_2_ 3 -1 6 1 6 -1 -1 3 0 20 + 314 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 3 0 20 + 322 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 318 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 299 inst_VPA_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 297 inst_DTACK_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 60 CLK_OSZI 9 -1 4 1 3 6 7 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 3 3 6 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 10 CLK_000 1 -1 -1 2 1 6 10 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 7 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 3 0 3 7 -1 -1 +98 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 321 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 5 29 -1 1 0 21 + 30 LDS_000 5 324 3 0 30 -1 10 0 21 + 31 UDS_000 5 323 3 0 31 -1 6 0 21 + 65 E 5 328 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 330 3 0 33 -1 3 0 20 + 8 IPL_030_2_ 5 320 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 332 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 331 1 0 6 -1 3 0 21 + 82 BGACK_030 5 326 7 0 82 -1 2 0 21 + 77 FPU_CS 5 327 7 0 77 -1 2 0 21 + 34 VMA 5 329 3 0 34 -1 2 0 21 + 32 AS_000 5 322 3 0 32 -1 2 0 21 + 28 BG_000 5 325 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 6 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 306 SM_AMIGA_6_ 3 -1 7 4 0 3 5 7 -1 -1 2 0 21 + 301 inst_CLK_000_D1 3 -1 7 4 1 3 6 7 -1 -1 1 0 20 + 309 SM_AMIGA_7_ 3 -1 0 3 0 3 7 -1 -1 5 0 21 + 295 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 4 0 20 + 328 RN_E 3 65 6 3 2 3 6 65 -1 3 0 21 + 317 SM_AMIGA_3_ 3 -1 6 3 2 5 6 -1 -1 3 0 20 + 315 SM_AMIGA_1_ 3 -1 1 3 0 1 7 -1 -1 3 0 21 + 307 cpu_est_2_ 3 -1 6 3 2 3 6 -1 -1 3 1 21 + 294 cpu_est_0_ 3 -1 3 3 2 3 6 -1 -1 3 0 20 + 327 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 311 inst_CLK_000_D5 3 -1 6 3 0 1 7 -1 -1 1 0 21 + 303 inst_CLK_000_D6 3 -1 7 3 0 1 7 -1 -1 1 0 20 + 298 inst_VPA_D 3 -1 7 3 2 3 5 -1 -1 1 0 20 + 296 inst_AS_030_000_SYNC 3 -1 7 2 0 7 -1 -1 7 0 21 + 318 SM_AMIGA_2_ 3 -1 6 2 1 6 -1 -1 3 0 20 + 304 inst_CLK_OUT_PRE 3 -1 6 2 1 6 -1 -1 3 1 21 + 329 RN_VMA 3 34 3 2 2 3 34 -1 2 0 21 + 326 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 322 RN_AS_000 3 32 3 2 0 3 32 -1 2 0 21 + 312 SM_AMIGA_4_ 3 -1 3 2 3 6 -1 -1 2 0 21 + 305 SM_AMIGA_5_ 3 -1 5 2 3 5 -1 -1 2 0 21 + 299 inst_VPA_SYNC 3 -1 2 2 2 6 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 5 2 5 6 -1 -1 2 0 21 + 310 inst_CLK_000_D3 3 -1 7 2 0 7 -1 -1 1 0 20 + 302 inst_CLK_000_D2 3 -1 3 2 0 7 -1 -1 1 0 20 + 324 RN_LDS_000 3 30 3 1 3 30 -1 10 0 21 + 323 RN_UDS_000 3 31 3 1 3 31 -1 6 0 21 + 319 SM_AMIGA_0_ 3 -1 0 1 0 -1 -1 4 0 21 + 332 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 331 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 330 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 320 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 325 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 321 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 314 CLK_CNT_1_ 3 -1 6 1 6 -1 -1 2 0 21 + 313 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 2 0 21 + 316 inst_CLK_000_D4 3 -1 7 1 6 -1 -1 1 0 20 + 308 CLK_REF_1_ 3 -1 3 1 6 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 7 0 1 2 3 5 6 7 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 10 CLK_000 1 -1 -1 5 0 1 2 5 6 10 -1 + 81 AS_030 1 -1 -1 4 2 3 5 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 7 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 3 0 3 7 -1 -1 +97 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 320 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 0 29 -1 1 0 21 + 30 LDS_000 5 323 3 0 30 -1 10 0 21 + 31 UDS_000 5 322 3 0 31 -1 6 0 21 + 65 E 5 327 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 329 3 0 33 -1 3 0 20 + 8 IPL_030_2_ 5 319 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 331 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 330 1 0 6 -1 3 0 21 + 82 BGACK_030 5 325 7 0 82 -1 2 0 21 + 77 FPU_CS 5 326 7 0 77 -1 2 0 21 + 34 VMA 5 328 3 0 34 -1 2 0 21 + 32 AS_000 5 321 3 0 32 -1 2 0 21 + 28 BG_000 5 324 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 20 + 306 SM_AMIGA_6_ 3 -1 7 4 2 3 6 7 -1 -1 2 0 21 + 301 inst_CLK_000_D1 3 -1 3 4 1 3 6 7 -1 -1 1 0 20 + 309 SM_AMIGA_7_ 3 -1 2 3 2 3 7 -1 -1 5 0 21 + 295 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 4 0 20 + 327 RN_E 3 65 6 3 3 5 6 65 -1 3 0 21 + 316 SM_AMIGA_3_ 3 -1 6 3 0 5 6 -1 -1 3 0 20 + 315 SM_AMIGA_1_ 3 -1 1 3 0 1 7 -1 -1 3 0 21 + 307 cpu_est_2_ 3 -1 6 3 3 5 6 -1 -1 3 1 21 + 294 cpu_est_0_ 3 -1 3 3 3 5 6 -1 -1 3 0 20 + 326 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 321 RN_AS_000 3 32 3 3 0 2 3 32 -1 2 0 21 + 311 inst_CLK_000_D4 3 -1 7 3 0 1 7 -1 -1 1 0 20 + 303 inst_CLK_000_D5 3 -1 7 3 0 1 7 -1 -1 1 0 20 + 298 inst_VPA_D 3 -1 6 3 0 3 5 -1 -1 1 0 21 + 296 inst_AS_030_000_SYNC 3 -1 7 2 2 7 -1 -1 7 0 21 + 318 SM_AMIGA_0_ 3 -1 0 2 0 2 -1 -1 4 0 21 + 317 SM_AMIGA_2_ 3 -1 6 2 1 6 -1 -1 3 0 20 + 304 inst_CLK_OUT_PRE 3 -1 6 2 1 6 -1 -1 3 1 21 + 328 RN_VMA 3 34 3 2 3 5 34 -1 2 0 21 + 325 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 312 SM_AMIGA_4_ 3 -1 3 2 3 6 -1 -1 2 0 21 + 305 SM_AMIGA_5_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 299 inst_VPA_SYNC 3 -1 5 2 5 6 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 0 2 0 6 -1 -1 2 0 21 + 310 inst_CLK_000_D3 3 -1 7 2 2 7 -1 -1 1 0 20 + 302 inst_CLK_000_D2 3 -1 7 2 2 7 -1 -1 1 0 20 + 323 RN_LDS_000 3 30 3 1 3 30 -1 10 0 21 + 322 RN_UDS_000 3 31 3 1 3 31 -1 6 0 21 + 331 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 330 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 329 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 319 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 324 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 320 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 314 CLK_CNT_1_ 3 -1 6 1 6 -1 -1 2 0 21 + 313 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 2 0 21 + 308 CLK_REF_1_ 3 -1 3 1 6 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 7 0 1 2 3 5 6 7 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 3 5 7 81 -1 + 10 CLK_000 1 -1 -1 4 0 1 5 7 10 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 3 2 3 7 -1 -1 +96 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 319 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 + 30 LDS_000 5 322 3 0 30 -1 10 0 21 + 31 UDS_000 5 321 3 0 31 -1 6 0 21 + 65 E 5 326 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 328 3 0 33 -1 3 0 20 + 8 IPL_030_2_ 5 318 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 330 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 329 1 0 6 -1 3 0 21 + 82 BGACK_030 5 324 7 0 82 -1 2 0 21 + 77 FPU_CS 5 325 7 0 77 -1 2 0 21 + 34 VMA 5 327 3 0 34 -1 2 0 21 + 32 AS_000 5 320 3 0 32 -1 2 0 21 + 28 BG_000 5 323 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 294 cpu_est_0_ 3 -1 7 4 1 3 6 7 -1 -1 3 0 20 + 301 inst_CLK_000_D1 3 -1 7 4 1 3 6 7 -1 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 6 4 1 3 6 7 -1 -1 1 0 21 + 295 cpu_est_1_ 3 -1 3 3 1 3 6 -1 -1 4 0 20 + 326 RN_E 3 65 6 3 1 3 6 65 -1 3 0 21 + 307 cpu_est_2_ 3 -1 3 3 1 3 6 -1 -1 3 1 20 + 325 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 305 SM_AMIGA_6_ 3 -1 7 3 3 6 7 -1 -1 2 0 21 + 298 inst_VPA_D 3 -1 0 3 1 3 6 -1 -1 1 0 21 + 309 SM_AMIGA_7_ 3 -1 7 2 3 7 -1 -1 5 0 21 + 316 SM_AMIGA_2_ 3 -1 6 2 6 7 -1 -1 3 0 20 + 315 SM_AMIGA_3_ 3 -1 6 2 1 6 -1 -1 3 0 20 + 304 inst_CLK_OUT_PRE 3 -1 6 2 1 6 -1 -1 3 1 21 + 327 RN_VMA 3 34 3 2 1 3 34 -1 2 0 21 + 324 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 320 RN_AS_000 3 32 3 2 3 7 32 -1 2 0 21 + 311 SM_AMIGA_4_ 3 -1 3 2 3 6 -1 -1 2 0 21 + 306 SM_AMIGA_5_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 299 inst_VPA_SYNC 3 -1 1 2 1 6 -1 -1 2 0 21 + 322 RN_LDS_000 3 30 3 1 3 30 -1 10 0 21 + 296 inst_AS_030_000_SYNC 3 -1 7 1 7 -1 -1 7 0 21 + 321 RN_UDS_000 3 31 3 1 3 31 -1 6 0 21 + 317 SM_AMIGA_0_ 3 -1 7 1 7 -1 -1 4 0 21 + 330 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 329 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 328 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 318 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 314 SM_AMIGA_1_ 3 -1 7 1 7 -1 -1 3 0 21 + 323 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 319 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 313 CLK_CNT_1_ 3 -1 6 1 6 -1 -1 2 0 21 + 312 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 310 inst_CLK_000_D3 3 -1 7 1 7 -1 -1 1 0 20 + 308 CLK_REF_1_ 3 -1 3 1 6 -1 -1 1 0 20 + 303 inst_CLK_000_D4 3 -1 7 1 7 -1 -1 1 0 20 + 302 inst_CLK_000_D2 3 -1 7 1 7 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 5 0 1 3 6 7 60 -1 + 85 RST 1 -1 -1 4 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 4 1 3 6 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 10 CLK_000 1 -1 -1 2 1 6 10 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +97 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 320 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 2 29 -1 1 0 21 + 30 LDS_000 5 323 3 0 30 -1 10 0 21 + 31 UDS_000 5 322 3 0 31 -1 6 0 21 + 65 E 5 327 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 329 3 0 33 -1 3 0 20 + 8 IPL_030_2_ 5 319 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 331 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 330 1 0 6 -1 3 0 21 + 82 BGACK_030 5 325 7 0 82 -1 2 0 21 + 77 FPU_CS 5 326 7 0 77 -1 2 0 21 + 34 VMA 5 328 3 0 34 -1 2 0 21 + 32 AS_000 5 321 3 0 32 -1 2 0 21 + 28 BG_000 5 324 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 20 + 316 SM_AMIGA_3_ 3 -1 1 4 0 1 2 5 -1 -1 3 0 21 + 301 inst_CLK_000_D1 3 -1 3 4 1 3 6 7 -1 -1 1 0 20 + 309 SM_AMIGA_7_ 3 -1 6 3 3 6 7 -1 -1 5 0 20 + 295 cpu_est_1_ 3 -1 6 3 3 5 6 -1 -1 4 0 21 + 327 RN_E 3 65 6 3 3 5 6 65 -1 3 0 21 + 307 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 3 1 20 + 294 cpu_est_0_ 3 -1 3 3 3 5 6 -1 -1 3 0 20 + 326 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 305 SM_AMIGA_6_ 3 -1 6 3 3 6 7 -1 -1 2 0 20 + 299 inst_VPA_SYNC 3 -1 5 3 0 1 5 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 2 3 0 1 2 -1 -1 2 0 21 + 298 inst_VPA_D 3 -1 0 3 2 3 5 -1 -1 1 0 20 + 296 inst_AS_030_000_SYNC 3 -1 7 2 6 7 -1 -1 7 0 21 + 317 SM_AMIGA_2_ 3 -1 0 2 0 6 -1 -1 3 0 21 + 315 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 3 0 20 + 304 inst_CLK_OUT_PRE 3 -1 6 2 1 6 -1 -1 3 1 21 + 328 RN_VMA 3 34 3 2 3 5 34 -1 2 0 21 + 325 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 321 RN_AS_000 3 32 3 2 3 6 32 -1 2 0 21 + 312 SM_AMIGA_4_ 3 -1 3 2 1 3 -1 -1 2 0 21 + 306 SM_AMIGA_5_ 3 -1 7 2 3 7 -1 -1 2 0 21 + 311 inst_CLK_000_D4 3 -1 7 2 6 7 -1 -1 1 0 20 + 310 inst_CLK_000_D3 3 -1 7 2 6 7 -1 -1 1 0 20 + 303 inst_CLK_000_D5 3 -1 7 2 6 7 -1 -1 1 0 20 + 302 inst_CLK_000_D2 3 -1 7 2 6 7 -1 -1 1 0 20 + 323 RN_LDS_000 3 30 3 1 3 30 -1 10 0 21 + 322 RN_UDS_000 3 31 3 1 3 31 -1 6 0 21 + 318 SM_AMIGA_0_ 3 -1 6 1 6 -1 -1 4 0 20 + 331 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 330 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 329 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 319 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 324 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 320 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 314 CLK_CNT_1_ 3 -1 6 1 6 -1 -1 2 0 21 + 313 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 2 0 21 + 308 CLK_REF_1_ 3 -1 3 1 6 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 7 0 1 2 3 5 6 7 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 81 AS_030 1 -1 -1 4 2 3 5 7 81 -1 + 10 CLK_000 1 -1 -1 3 2 5 7 10 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 3 3 6 7 -1 -1 +97 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 320 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 0 29 -1 1 0 21 + 30 LDS_000 5 323 3 0 30 -1 8 0 21 + 31 UDS_000 5 322 3 0 31 -1 5 0 21 + 65 E 5 327 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 329 3 0 33 -1 3 0 20 + 8 IPL_030_2_ 5 319 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 331 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 330 1 0 6 -1 3 0 21 + 82 BGACK_030 5 325 7 0 82 -1 2 0 21 + 77 FPU_CS 5 326 7 0 77 -1 2 0 21 + 34 VMA 5 328 3 0 34 -1 2 0 21 + 32 AS_000 5 321 3 0 32 -1 2 0 21 + 28 BG_000 5 324 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 6 6 0 1 3 5 6 7 -1 -1 1 0 21 + 315 SM_AMIGA_3_ 3 -1 1 4 0 1 5 6 -1 -1 3 0 21 + 301 inst_CLK_000_D1 3 -1 6 4 1 3 6 7 -1 -1 1 0 21 + 295 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 4 0 20 + 327 RN_E 3 65 6 3 3 5 6 65 -1 3 0 21 + 307 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 3 1 20 + 294 cpu_est_0_ 3 -1 3 3 3 5 6 -1 -1 3 0 20 + 326 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 299 inst_VPA_SYNC 3 -1 5 3 1 5 6 -1 -1 2 0 21 + 297 inst_DTACK_SYNC 3 -1 0 3 0 1 6 -1 -1 2 0 21 + 298 inst_VPA_D 3 -1 6 3 0 3 5 -1 -1 1 0 21 + 309 SM_AMIGA_7_ 3 -1 7 2 3 7 -1 -1 5 0 21 + 317 SM_AMIGA_2_ 3 -1 6 2 1 6 -1 -1 3 0 20 + 316 SM_AMIGA_1_ 3 -1 1 2 1 7 -1 -1 3 0 21 + 304 inst_CLK_OUT_PRE 3 -1 6 2 1 6 -1 -1 3 1 21 + 328 RN_VMA 3 34 3 2 3 5 34 -1 2 0 21 + 325 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 321 RN_AS_000 3 32 3 2 3 7 32 -1 2 0 21 + 311 SM_AMIGA_4_ 3 -1 3 2 1 3 -1 -1 2 0 21 + 305 SM_AMIGA_6_ 3 -1 7 2 3 7 -1 -1 2 0 21 + 312 inst_CLK_000_D4 3 -1 7 2 1 7 -1 -1 1 0 20 + 303 inst_CLK_000_D5 3 -1 7 2 1 7 -1 -1 1 0 20 + 323 RN_LDS_000 3 30 3 1 3 30 -1 8 0 21 + 296 inst_AS_030_000_SYNC 3 -1 7 1 7 -1 -1 7 0 21 + 322 RN_UDS_000 3 31 3 1 3 31 -1 5 0 21 + 318 SM_AMIGA_0_ 3 -1 7 1 7 -1 -1 4 0 21 + 331 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 330 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 329 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 319 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 324 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 320 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 314 CLK_CNT_1_ 3 -1 6 1 6 -1 -1 2 0 21 + 313 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 2 0 21 + 306 SM_AMIGA_5_ 3 -1 3 1 3 -1 -1 2 0 21 + 310 inst_CLK_000_D3 3 -1 7 1 7 -1 -1 1 0 20 + 308 CLK_REF_1_ 3 -1 7 1 6 -1 -1 1 0 20 + 302 inst_CLK_000_D2 3 -1 6 1 7 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 6 0 1 3 5 6 7 60 -1 + 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 3 5 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 6 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 \ No newline at end of file diff --git a/Logic/68030_tk.plc b/Logic/68030_tk.plc index aa25424..ebb932a 100644 --- a/Logic/68030_tk.plc +++ b/Logic/68030_tk.plc @@ -8,7 +8,7 @@ ; Source file 68030_tk.tt4 ; FITTER-generated Placements. ; DEVICE mach447a -; DATE Thu May 22 14:56:14 2014 +; DATE Sat May 24 11:44:13 2014 Pin 79 SIZE_1_ @@ -19,34 +19,34 @@ Pin 82 AS_030 Pin 98 DS_030 Pin 14 nEXP_SPACE Pin 41 BERR Comb ; S6=1 S9=1 Pair 203 -Pin 70 SIZE_0_ Pin 21 BG_030 +Pin 28 BGACK_000 +Pin 64 CLK_030 +Pin 11 CLK_000 +Pin 70 SIZE_0_ +Pin 61 CLK_OSZI Pin 5 A_30_ +Pin 65 CLK_DIV_OUT Reg ; S6=1 S9=1 Pair 245 Pin 6 A_29_ Pin 15 A_28_ -Pin 28 BGACK_000 Pin 16 A_27_ -Pin 64 CLK_030 Pin 17 A_26_ -Pin 11 CLK_000 +Pin 92 AVEC Comb ; S6=1 S9=1 Pair 107 Pin 18 A_25_ -Pin 61 CLK_OSZI +Pin 22 AVEC_EXP Comb ; S6=1 S9=1 Pair 149 Pin 19 A_24_ -Pin 65 CLK_DIV_OUT Reg ; S6=1 S9=1 Pair 245 Pin 84 A_23_ +Pin 36 VPA Pin 85 A_22_ Pin 94 A_21_ +Pin 86 RST Pin 93 A_20_ -Pin 92 AVEC Comb ; S6=1 S9=1 Pair 107 Pin 97 A_19_ -Pin 22 AVEC_EXP Comb ; S6=1 S9=1 Pair 149 +Pin 71 RW Pin 95 A_18_ Pin 59 A_17_ -Pin 36 VPA -Pin 96 A_16_ -Pin 86 RST -Pin 71 RW Pin 48 AMIGA_BUS_DATA_DIR Comb ; S6=1 S9=1 Pair 197 +Pin 96 A_16_ Pin 20 AMIGA_BUS_ENABLE_LOW Comb ; S6=1 S9=1 Pair 167 Pin 47 CIIN Comb ; S6=1 S9=1 Pair 215 Pin 69 A_0_ @@ -56,56 +56,58 @@ Pin 80 DSACK_0_ Comb ; S6=1 S9=1 Pair 287 Pin 57 FC_0_ Pin 9 IPL_030_2_ Reg ; S6=1 S9=1 Pair 131 Pin 81 DSACK_1_ Reg ; S6=1 S9=1 Pair 281 -Pin 33 AS_000 Reg ; S6=1 S9=1 Pair 187 +Pin 33 AS_000 Reg ; S6=1 S9=1 Pair 181 Pin 32 UDS_000 Reg ; S6=1 S9=1 Pair 191 Pin 31 LDS_000 Reg ; S6=1 S9=1 Pair 185 -Pin 29 BG_000 Reg ; S6=1 S9=1 Pair 175 +Pin 29 BG_000 Reg ; S6=1 S9=1 Pair 193 Pin 83 BGACK_030 Reg ; S6=1 S9=1 Pair 275 Pin 10 CLK_EXP Reg ; S6=1 S9=0 Pair 125 Pin 78 FPU_CS Reg ; S6=1 S9=1 Pair 269 Pin 30 DTACK Reg ; S6=1 S9=1 Pair 173 Pin 66 E Reg ; S6=1 S9=1 Pair 251 -Pin 35 VMA Reg ; S6=1 S9=1 Pair 181 +Pin 35 VMA Reg ; S6=1 S9=1 Pair 175 Pin 3 RESET Reg ; S6=1 S9=0 Pair 127 Pin 34 AMIGA_BUS_ENABLE Reg ; S6=1 S9=0 Pair 179 Pin 7 IPL_030_1_ Reg ; S6=1 S9=1 Pair 143 Pin 8 IPL_030_0_ Reg ; S6=1 S9=1 Pair 137 Node 131 RN_IPL_030_2_ Reg ; S6=1 S9=1 Node 281 RN_DSACK_1_ Reg ; S6=1 S9=1 -Node 187 RN_AS_000 Reg ; S6=1 S9=1 +Node 181 RN_AS_000 Reg ; S6=1 S9=1 Node 191 RN_UDS_000 Reg ; S6=1 S9=1 Node 185 RN_LDS_000 Reg ; S6=1 S9=1 -Node 175 RN_BG_000 Reg ; S6=1 S9=1 +Node 193 RN_BG_000 Reg ; S6=1 S9=1 Node 275 RN_BGACK_030 Reg ; S6=1 S9=1 Node 269 RN_FPU_CS Reg ; S6=1 S9=1 Node 173 RN_DTACK Reg ; S6=1 S9=1 Node 251 RN_E Reg ; S6=1 S9=1 -Node 181 RN_VMA Reg ; S6=1 S9=1 +Node 175 RN_VMA Reg ; S6=1 S9=1 Node 179 RN_AMIGA_BUS_ENABLE Reg ; S6=1 S9=0 Node 143 RN_IPL_030_1_ Reg ; S6=1 S9=1 Node 137 RN_IPL_030_0_ Reg ; S6=1 S9=1 -Node 265 cpu_est_0_ Reg ; S6=1 S9=1 -Node 247 cpu_est_1_ Reg ; S6=1 S9=1 -Node 271 inst_AS_030_000_SYNC Reg ; S6=1 S9=1 -Node 221 inst_DTACK_SYNC Reg ; S6=1 S9=1 -Node 139 inst_VPA_D Reg ; S6=1 S9=0 -Node 260 inst_VPA_SYNC Reg ; S6=0 S9=0 +Node 182 cpu_est_0_ Reg ; S6=1 S9=0 +Node 187 cpu_est_1_ Reg ; S6=1 S9=0 +Node 272 inst_AS_030_000_SYNC Reg ; S6=1 S9=1 +Node 101 inst_DTACK_SYNC Reg ; S6=1 S9=1 +Node 247 inst_VPA_D Reg ; S6=1 S9=1 +Node 221 inst_VPA_SYNC Reg ; S6=1 S9=1 Node 257 inst_CLK_000_D0 Reg ; S6=1 S9=1 -Node 193 inst_CLK_000_D1 Reg ; S6=1 S9=0 +Node 263 inst_CLK_000_D1 Reg ; S6=1 S9=1 Node 254 inst_CLK_000_D2 Reg ; S6=1 S9=1 -Node 101 inst_CLK_OUT_PRE Reg ; S6=1 S9=1 -Node 263 SM_AMIGA_6_ Reg ; S6=1 S9=0 +Node 289 inst_CLK_000_D5 Reg ; S6=1 S9=0 +Node 259 inst_CLK_OUT_PRE Reg ; S6=1 S9=1 +Node 277 SM_AMIGA_6_ Reg ; S6=0 S9=1 +Node 194 SM_AMIGA_5_ Reg ; S6=0 S9=1 Node 176 cpu_est_2_ Reg ; S6=1 S9=0 -Node 182 CLK_REF_0_ Lat ; S6=0 S9=0 -Node 128 CLK_REF_1_ Lat ; S6=1 S9=0 -Node 277 SM_AMIGA_7_ Reg ; S6=1 S9=1 -Node 133 SM_AMIGA_4_ Reg ; S6=0 S9=1 -Node 145 SM_AMIGA_1_ Reg ; S6=0 S9=1 -Node 119 CLK_CNT_0_ Reg ; S6=1 S9=1 -Node 113 CLK_CNT_1_ Reg ; S6=1 S9=1 -Node 259 SM_AMIGA_3_ Reg ; S6=1 S9=0 -Node 248 SM_AMIGA_5_ Reg ; S6=1 S9=0 +Node 290 CLK_REF_1_ Lat ; S6=1 S9=0 +Node 271 SM_AMIGA_7_ Reg ; S6=1 S9=1 +Node 284 inst_CLK_000_D3 Reg ; S6=1 S9=0 +Node 188 SM_AMIGA_4_ Reg ; S6=0 S9=1 +Node 283 inst_CLK_000_D4 Reg ; S6=1 S9=0 +Node 248 CLK_CNT_0_ Reg ; S6=1 S9=1 +Node 265 CLK_CNT_1_ Reg ; S6=1 S9=1 +Node 133 SM_AMIGA_3_ Reg ; S6=0 S9=1 +Node 139 SM_AMIGA_1_ Reg ; S6=0 S9=1 Node 253 SM_AMIGA_2_ Reg ; S6=1 S9=0 -Node 283 SM_AMIGA_0_ Reg ; S6=0 S9=1 +Node 278 SM_AMIGA_0_ Reg ; S6=0 S9=1 ; Unused Pins & Nodes ; -> None Found. diff --git a/Logic/68030_tk.prd b/Logic/68030_tk.prd index 12cedad..2b55edc 100644 --- a/Logic/68030_tk.prd +++ b/Logic/68030_tk.prd @@ -5,8 +5,8 @@ |--------------------------------------------| -Start: Thu May 22 14:56:14 2014 -End : Thu May 22 14:56:14 2014 $$$ Elapsed time: 00:00:00 +Start: Sat May 24 11:44:13 2014 +End : Sat May 24 11:44:13 2014 $$$ Elapsed time: 00:00:00 =========================================================================== Part [C:/Program Files (x86)/ispLever/ispcpld/dat/mach4a/mach447a] Design [68030_tk.tt4] @@ -21,16 +21,16 @@ Part [C:/Program Files (x86)/ispLever/ispcpld/dat/mach4a/mach447a] Design [68030 | | +- Signals to Place | | +----- Logic Array Inputs | | | +- Placed | | | +- Array Inputs Used _|____|____|____|_______________|____|_____________|___|________________ - 0 | 16 | 4 | 4 => 100% | 8 | 7 => 87% | 33 | 4 => 12% - 1 | 16 | 9 | 9 => 100% | 8 | 8 => 100% | 33 | 16 => 48% + 0 | 16 | 2 | 2 => 100% | 8 | 7 => 87% | 33 | 8 => 24% + 1 | 16 | 7 | 7 => 100% | 8 | 8 => 100% | 33 | 19 => 57% 2 | 16 | 2 | 2 => 100% | 8 | 8 => 100% | 33 | 1 => 3% - 3 | 16 | 10 | 10 => 100% | 8 | 8 => 100% | 33 | 31 => 93% + 3 | 16 | 12 | 12 => 100% | 8 | 8 => 100% | 33 | 30 => 90% 4 | 16 | 3 | 3 => 100% | 8 | 3 => 37% | 33 | 14 => 42% - 5 | 16 | 1 | 1 => 100% | 8 | 4 => 50% | 33 | 9 => 27% - 6 | 16 | 11 | 11 => 100% | 8 | 7 => 87% | 33 | 23 => 69% - 7 | 16 | 7 | 7 => 100% | 8 | 8 => 100% | 33 | 22 => 66% + 5 | 16 | 1 | 1 => 100% | 8 | 4 => 50% | 33 | 12 => 36% + 6 | 16 | 10 | 10 => 100% | 8 | 7 => 87% | 33 | 18 => 54% + 7 | 16 | 12 | 12 => 100% | 8 | 8 => 100% | 33 | 27 => 81% ---|----|----|------------|-------|------------|-----|------------------ - | Avg number of array inputs in used blocks : 15.00 => 45% + | Avg number of array inputs in used blocks : 16.13 => 48% * Input/Clock Signal count: 35 -> placed: 35 = 100% @@ -41,13 +41,13 @@ _|____|____|____|_______________|____|_____________|___|________________ Clock Only Pins : 0 0 => 0% Clock/Input Pins : 4 4 => 100% Logic Blocks : 8 8 => 100% - Macrocells : 128 47 => 36% - PT Clusters : 128 36 => 28% - - Single PT Clusters : 128 17 => 13% + Macrocells : 128 49 => 38% + PT Clusters : 128 33 => 25% + - Single PT Clusters : 128 19 => 14% Input Registers : 0 * Routing Completion: 100% -* Attempts: Place [ 95] Route [ 0] +* Attempts: Place [ 97] Route [ 0] =========================================================================== Signal Fanout Table =========================================================================== @@ -63,7 +63,7 @@ ___|__|__|____|____________________________________________________________ 3| 2|OUT| 20|=> ....|....| AMIGA_BUS_ENABLE_LOW 4| 3| IO| 33|=> ....|....| AS_000 |=> Paired w/: RN_AS_000 - 5| 7|INP| 82|=> ...3|.567| AS_030 + 5| 7|INP| 82|=> 0..3|.5.7| AS_030 6| 0|OUT| 92|=> ....|....| AVEC 7| 2|OUT| 22|=> ....|....| AVEC_EXP 8| 6|INP| 69|=> ...3|....| A_0_ @@ -91,93 +91,95 @@ ___|__|__|____|____________________________________________________________ |=> Paired w/: RN_BG_000 29| 2|INP| 21|=> ...3|....| BG_030 30| 4|OUT| 47|=> ....|....| CIIN - 31| +|INP| 11|=> ....|.56.| CLK_000 + 31| +|INP| 11|=> ....|..6.| CLK_000 32| +|INP| 64|=> ...3|...7| CLK_030 - 33| 0|NOD| . |=> 0...|....| CLK_CNT_0_ - 34| 0|NOD| . |=> 0...|....| CLK_CNT_1_ + 33| 6|NOD| . |=> ....|..6.| CLK_CNT_0_ + 34| 6|NOD| . |=> ....|..6.| CLK_CNT_1_ 35| 6|OUT| 65|=> ....|....| CLK_DIV_OUT 36| 1|OUT| 10|=> ....|....| CLK_EXP - 37| +|Cin| 61|=> .1.3|.56.| CLK_OSZI - 38| 3|NOD| . |=> 0...|....| CLK_REF_0_ - 39| 1|NOD| . |=> 0...|....| CLK_REF_1_ - 40| 7|OUT| 80|=> ....|....| DSACK_0_ - 41| 7| IO| 81|=> ...3|....| DSACK_1_ + 37| +|Cin| 61|=> 01.3|.567| CLK_OSZI + 38| 7|NOD| . |=> ....|..6.| CLK_REF_1_ + 39| 7|OUT| 80|=> ....|....| DSACK_0_ + 40| 7| IO| 81|=> ...3|....| DSACK_1_ |=> Paired w/: RN_DSACK_1_ - 42| 0|INP| 98|=> ...3|....| DS_030 - 43| 3| IO| 30|=> ....|.5..| DTACK - 44| 6| IO| 66|=> ....|....| E + 41| 0|INP| 98|=> ...3|....| DS_030 + 42| 3| IO| 30|=> 0...|....| DTACK + 43| 6| IO| 66|=> ....|....| E |=> Paired w/: RN_E - 45| 5|INP| 57|=> ....|...7| FC_0_ - 46| 5|INP| 58|=> ....|...7| FC_1_ - 47| 7| IO| 78|=> ....|....| FPU_CS + 44| 5|INP| 57|=> ....|...7| FC_0_ + 45| 5|INP| 58|=> ....|...7| FC_1_ + 46| 7| IO| 78|=> ....|....| FPU_CS |=> Paired w/: RN_FPU_CS - 48| 1| IO| 8|=> ....|....| IPL_030_0_ + 47| 1| IO| 8|=> ....|....| IPL_030_0_ |=> Paired w/: RN_IPL_030_0_ - 49| 1| IO| 7|=> ....|....| IPL_030_1_ + 48| 1| IO| 7|=> ....|....| IPL_030_1_ |=> Paired w/: RN_IPL_030_1_ - 50| 1| IO| 9|=> ....|....| IPL_030_2_ + 49| 1| IO| 9|=> ....|....| IPL_030_2_ |=> Paired w/: RN_IPL_030_2_ - 51| 6|INP| 67|=> .1..|....| IPL_0_ - 52| 5|INP| 56|=> .1..|....| IPL_1_ - 53| 6|INP| 68|=> .1..|....| IPL_2_ - 54| 3| IO| 31|=> ....|....| LDS_000 + 50| 6|INP| 67|=> .1..|....| IPL_0_ + 51| 5|INP| 56|=> .1..|....| IPL_1_ + 52| 6|INP| 68|=> .1..|....| IPL_2_ + 53| 3| IO| 31|=> ....|....| LDS_000 |=> Paired w/: RN_LDS_000 - 55| 1|OUT| 3|=> ....|....| RESET - 56| 3|NOD| . |=> ...3|....| RN_AMIGA_BUS_ENABLE + 54| 1|OUT| 3|=> ....|....| RESET + 55| 3|NOD| . |=> ...3|....| RN_AMIGA_BUS_ENABLE |=> Paired w/: AMIGA_BUS_ENABLE - 57| 3|NOD| . |=> ...3|...7| RN_AS_000 + 56| 3|NOD| . |=> ...3|...7| RN_AS_000 |=> Paired w/: AS_000 - 58| 7|NOD| . |=> ...3|...7| RN_BGACK_030 + 57| 7|NOD| . |=> ...3|...7| RN_BGACK_030 |=> Paired w/: BGACK_030 - 59| 3|NOD| . |=> ...3|....| RN_BG_000 + 58| 3|NOD| . |=> ...3|....| RN_BG_000 |=> Paired w/: BG_000 - 60| 7|NOD| . |=> ....|...7| RN_DSACK_1_ + 59| 7|NOD| . |=> ....|...7| RN_DSACK_1_ |=> Paired w/: DSACK_1_ - 61| 6|NOD| . |=> ...3|..6.| RN_E + 60| 6|NOD| . |=> ...3|.56.| RN_E |=> Paired w/: E - 62| 7|NOD| . |=> ..2.|4..7| RN_FPU_CS + 61| 7|NOD| . |=> ..2.|4..7| RN_FPU_CS |=> Paired w/: FPU_CS - 63| 1|NOD| . |=> .1..|....| RN_IPL_030_0_ + 62| 1|NOD| . |=> .1..|....| RN_IPL_030_0_ |=> Paired w/: IPL_030_0_ - 64| 1|NOD| . |=> .1..|....| RN_IPL_030_1_ + 63| 1|NOD| . |=> .1..|....| RN_IPL_030_1_ |=> Paired w/: IPL_030_1_ - 65| 1|NOD| . |=> .1..|....| RN_IPL_030_2_ + 64| 1|NOD| . |=> .1..|....| RN_IPL_030_2_ |=> Paired w/: IPL_030_2_ - 66| 3|NOD| . |=> ...3|....| RN_LDS_000 + 65| 3|NOD| . |=> ...3|....| RN_LDS_000 |=> Paired w/: LDS_000 - 67| 3|NOD| . |=> ...3|....| RN_UDS_000 + 66| 3|NOD| . |=> ...3|....| RN_UDS_000 |=> Paired w/: UDS_000 - 68| 3|NOD| . |=> ...3|..6.| RN_VMA + 67| 3|NOD| . |=> ...3|.5..| RN_VMA |=> Paired w/: VMA - 69| +|INP| 86|=> .1.3|.567| RST - 70| 6|INP| 71|=> ...3|4...| RW - 71| 6|INP| 70|=> ...3|....| SIZE_0_ - 72| 7|INP| 79|=> ...3|....| SIZE_1_ - 73| 7|NOD| . |=> ....|...7| SM_AMIGA_0_ - 74| 1|NOD| . |=> .1..|...7| SM_AMIGA_1_ - 75| 6|NOD| . |=> .1..|..6.| SM_AMIGA_2_ - 76| 6|NOD| . |=> ....|.56.| SM_AMIGA_3_ - 77| 1|NOD| . |=> .1.3|..6.| SM_AMIGA_4_ - 78| 6|NOD| . |=> .1..|..6.| SM_AMIGA_5_ - 79| 6|NOD| . |=> ...3|..6.| SM_AMIGA_6_ - 80| 7|NOD| . |=> ...3|..67| SM_AMIGA_7_ - 81| 3| IO| 32|=> ....|....| UDS_000 + 68| +|INP| 86|=> 01.3|.567| RST + 69| 6|INP| 71|=> ...3|4...| RW + 70| 6|INP| 70|=> ...3|....| SIZE_0_ + 71| 7|INP| 79|=> ...3|....| SIZE_1_ + 72| 7|NOD| . |=> ....|...7| SM_AMIGA_0_ + 73| 1|NOD| . |=> .1..|...7| SM_AMIGA_1_ + 74| 6|NOD| . |=> .1..|..6.| SM_AMIGA_2_ + 75| 1|NOD| . |=> 01..|.56.| SM_AMIGA_3_ + 76| 3|NOD| . |=> .1.3|....| SM_AMIGA_4_ + 77| 3|NOD| . |=> ...3|....| SM_AMIGA_5_ + 78| 7|NOD| . |=> ...3|...7| SM_AMIGA_6_ + 79| 7|NOD| . |=> ...3|...7| SM_AMIGA_7_ + 80| 3| IO| 32|=> ....|....| UDS_000 |=> Paired w/: RN_UDS_000 - 82| 3| IO| 35|=> ....|....| VMA + 81| 3| IO| 35|=> ....|....| VMA |=> Paired w/: RN_VMA - 83| +|INP| 36|=> .1..|....| VPA - 84| 6|NOD| . |=> ...3|..6.| cpu_est_0_ - 85| 6|NOD| . |=> ...3|..6.| cpu_est_1_ - 86| 3|NOD| . |=> ...3|..6.| cpu_est_2_ - 87| 7|NOD| . |=> ...3|..67| inst_AS_030_000_SYNC - 88| 6|NOD| . |=> .1.3|.567| inst_CLK_000_D0 - 89| 3|NOD| . |=> .1.3|..67| inst_CLK_000_D1 - 90| 6|NOD| . |=> ...3|..6.| inst_CLK_000_D2 - 91| 0|NOD| . |=> .1..|..67| inst_CLK_OUT_PRE - 92| 5|NOD| . |=> ....|.56.| inst_DTACK_SYNC - 93| 1|NOD| . |=> ...3|.56.| inst_VPA_D - 94| 6|NOD| . |=> ....|..6.| inst_VPA_SYNC - 95| +|INP| 14|=> ...3|...7| nEXP_SPACE + 82| +|INP| 36|=> ....|..6.| VPA + 83| 3|NOD| . |=> ...3|.56.| cpu_est_0_ + 84| 3|NOD| . |=> ...3|.56.| cpu_est_1_ + 85| 3|NOD| . |=> ...3|.56.| cpu_est_2_ + 86| 7|NOD| . |=> ....|...7| inst_AS_030_000_SYNC + 87| 6|NOD| . |=> 01.3|.567| inst_CLK_000_D0 + 88| 6|NOD| . |=> .1.3|..67| inst_CLK_000_D1 + 89| 6|NOD| . |=> ....|...7| inst_CLK_000_D2 + 90| 7|NOD| . |=> ....|...7| inst_CLK_000_D3 + 91| 7|NOD| . |=> .1..|...7| inst_CLK_000_D4 + 92| 7|NOD| . |=> .1..|...7| inst_CLK_000_D5 + 93| 6|NOD| . |=> .1..|..6.| inst_CLK_OUT_PRE + 94| 0|NOD| . |=> 01..|..6.| inst_DTACK_SYNC + 95| 6|NOD| . |=> 0..3|.5..| inst_VPA_D + 96| 5|NOD| . |=> .1..|.56.| inst_VPA_SYNC + 97| +|INP| 14|=> ...3|...7| nEXP_SPACE --------------------------------------------------------------------------- =========================================================================== < C:/Program Files (x86)/ispLever/ispcpld/dat/mach4a/mach447a Device Pin Assignments > @@ -297,7 +299,7 @@ ____|_____|_________|______________________________________________________ | Sig Type-+ | | | | | | | XOR to Mcell Assignment | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ - 0|inst_CLK_OUT_PRE|NOD| | S | 4 | 4 to [ 0]| 1 XOR free + 0|inst_DTACK_SYNC|NOD| | S | 2 | 4 to [ 0]| 1 XOR free 1| | ? | | S | | 4 free | 1 XOR free 2| | ? | | S | | 4 free | 1 XOR free 3| | ? | | S | | 4 free | 1 XOR free @@ -305,11 +307,11 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ 5| | ? | | S | | 4 free | 1 XOR free 6| | ? | | S | | 4 free | 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free - 8| CLK_CNT_1_|NOD| | S | 4 | 4 to [ 8]| 1 XOR free + 8| | ? | | S | | 4 free | 1 XOR free 9| | ? | | S | | 4 free | 1 XOR free 10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free -12| CLK_CNT_0_|NOD| | S | 3 | 4 to [12]| 1 XOR free +12| | ? | | S | | 4 free | 1 XOR free 13| | ? | | S | | 4 free | 1 XOR free 14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free @@ -324,20 +326,20 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0|inst_CLK_OUT_PRE|NOD| | S | 4 |=> can support up to [ 15] logic PT(s) + 0|inst_DTACK_SYNC|NOD| | S | 2 |=> can support up to [ 15] logic PT(s) 1| | ? | | S | |=> can support up to [ 15] logic PT(s) 2| | ? | | S | |=> can support up to [ 19] logic PT(s) 3| | ? | | S | |=> can support up to [ 19] logic PT(s) 4| AVEC|OUT| | S | 1 |=> can support up to [ 20] logic PT(s) 5| | ? | | S | |=> can support up to [ 19] logic PT(s) - 6| | ? | | S | |=> can support up to [ 15] logic PT(s) - 7| | ? | | S | |=> can support up to [ 15] logic PT(s) - 8| CLK_CNT_1_|NOD| | S | 4 |=> can support up to [ 20] logic PT(s) - 9| | ? | | S | |=> can support up to [ 15] logic PT(s) -10| | ? | | S | |=> can support up to [ 15] logic PT(s) -11| | ? | | S | |=> can support up to [ 15] logic PT(s) -12| CLK_CNT_0_|NOD| | S | 3 |=> can support up to [ 20] logic PT(s) -13| | ? | | S | |=> can support up to [ 15] logic PT(s) + 6| | ? | | S | |=> can support up to [ 20] logic PT(s) + 7| | ? | | S | |=> can support up to [ 20] logic PT(s) + 8| | ? | | S | |=> can support up to [ 20] logic PT(s) + 9| | ? | | S | |=> can support up to [ 20] logic PT(s) +10| | ? | | S | |=> can support up to [ 20] logic PT(s) +11| | ? | | S | |=> can support up to [ 20] logic PT(s) +12| | ? | | S | |=> can support up to [ 20] logic PT(s) +13| | ? | | S | |=> can support up to [ 20] logic PT(s) 14| | ? | | S | |=> can support up to [ 15] logic PT(s) 15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- @@ -349,7 +351,7 @@ _|_________________|__|__|___|_____|_______________________________________ | Sig Type---+ | to | Block [ 0] IO Pin | Device Pin | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ - 0|inst_CLK_OUT_PRE|NOD| | => | 5 6 7 0 | 96 97 98 91 + 0|inst_DTACK_SYNC|NOD| | => | 5 6 7 0 | 96 97 98 91 1| | | | => | 5 6 7 0 | 96 97 98 91 2| | | | => | 6 7 0 1 | 97 98 91 92 3| | | | => | 6 7 0 1 | 97 98 91 92 @@ -357,11 +359,11 @@ _|_________________|__|_____|____________________|________________________ 5| | | | => | 7 0 1 2 | 98 91 92 93 6| | | | => | 0 1 2 3 | 91 92 93 94 7| | | | => | 0 1 2 3 | 91 92 93 94 - 8| CLK_CNT_1_|NOD| | => | 1 2 3 4 | 92 93 94 95 + 8| | | | => | 1 2 3 4 | 92 93 94 95 9| | | | => | 1 2 3 4 | 92 93 94 95 10| | | | => | 2 3 4 5 | 93 94 95 96 11| | | | => | 2 3 4 5 | 93 94 95 96 -12| CLK_CNT_0_|NOD| | => | 3 4 5 6 | 94 95 96 97 +12| | | | => | 3 4 5 6 | 94 95 96 97 13| | | | => | 3 4 5 6 | 94 95 96 97 14| | | | => | 4 5 6 7 | 95 96 97 98 15| | | | => | 4 5 6 7 | 95 96 97 98 @@ -413,7 +415,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number ---|-------|----|---|---|----------|------|-|------------------------------ 0 [IOpin 0 | 91| -| | ] [RegIn 0 |102| -| | ] - [MCell 0 |101|NOD inst_CLK_OUT_PRE| |*] + [MCell 0 |101|NOD inst_DTACK_SYNC| |*] [MCell 1 |103| -| | ] 1 [IOpin 1 | 92|OUT AVEC|*| ] @@ -433,7 +435,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 4 [IOpin 4 | 95|INP A_18_|*|*] [RegIn 4 |114| -| | ] - [MCell 8 |113|NOD CLK_CNT_1_| |*] + [MCell 8 |113| -| | ] [MCell 9 |115| -| | ] 5 [IOpin 5 | 96|INP A_16_|*|*] @@ -443,7 +445,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 6 [IOpin 6 | 97|INP A_19_|*|*] [RegIn 6 |120| -| | ] - [MCell 12 |119|NOD CLK_CNT_0_| |*] + [MCell 12 |119| -| | ] [MCell 13 |121| -| | ] 7 [IOpin 7 | 98|INP DS_030|*|*] @@ -457,22 +459,22 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| ... | ... +Mux00| Input Pin ( 86)| RST Mux01| ... | ... Mux02| ... | ... -Mux03| Mcel 0 8 ( 113)| CLK_CNT_1_ -Mux04| Mcel 3 6 ( 182)| CLK_REF_0_ +Mux03| ... | ... +Mux04| Input Pin ( 61)| CLK_OSZI Mux05| ... | ... Mux06| ... | ... Mux07| ... | ... Mux08| ... | ... -Mux09| Mcel 0 12 ( 119)| CLK_CNT_0_ -Mux10| Mcel 1 2 ( 128)| CLK_REF_1_ +Mux09| IOPin 7 3 ( 82)| AS_030 +Mux10| Mcel 6 8 ( 257)| inst_CLK_000_D0 Mux11| ... | ... Mux12| ... | ... Mux13| ... | ... -Mux14| ... | ... -Mux15| ... | ... +Mux14| IOPin 3 5 ( 30)| DTACK +Mux15| Mcel 0 0 ( 101)| inst_DTACK_SYNC Mux16| ... | ... Mux17| ... | ... Mux18| ... | ... @@ -481,11 +483,11 @@ Mux20| ... | ... Mux21| ... | ... Mux22| ... | ... Mux23| ... | ... -Mux24| ... | ... +Mux24| Mcel 6 1 ( 247)| inst_VPA_D Mux25| ... | ... Mux26| ... | ... Mux27| ... | ... -Mux28| ... | ... +Mux28| Mcel 1 5 ( 133)| SM_AMIGA_3_ Mux29| ... | ... Mux30| ... | ... Mux31| ... | ... @@ -503,18 +505,18 @@ Mux32| ... | ... _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| CLK_EXP|OUT| | A | 1 | 2 free | 1 XOR to [ 0] for 1 PT sig 1| RESET|OUT| | A | 1 | 2 free | 1 XOR to [ 1] for 1 PT sig - 2| CLK_REF_1_|NOD| | A | 1 | 2 free | 1 XOR to [ 2] for 1 PT sig + 2| | ? | | S | | 4 free | 1 XOR free 3| | ? | | S | | 4 free | 1 XOR free 4| IPL_030_2_| IO| | S | 3 | 4 to [ 4]| 1 XOR free - 5| SM_AMIGA_4_|NOD| | S | 2 | 4 to [ 5]| 1 XOR free + 5| SM_AMIGA_3_|NOD| | S | 3 | 4 to [ 5]| 1 XOR free 6| | ? | | S | | 4 free | 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free 8| IPL_030_0_| IO| | S | 3 | 4 to [ 8]| 1 XOR free - 9| inst_VPA_D|NOD| | A | 1 | 2 free | 1 XOR to [ 9] for 1 PT sig + 9| SM_AMIGA_1_|NOD| | S | 3 | 4 to [ 9]| 1 XOR free 10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free 12| IPL_030_1_| IO| | S | 3 | 4 to [12]| 1 XOR free -13| SM_AMIGA_1_|NOD| | S | 3 | 4 to [13]| 1 XOR free +13| | ? | | S | | 4 free | 1 XOR free 14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- @@ -528,21 +530,21 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| CLK_EXP|OUT| | A | 1 |=> can support up to [ 7] logic PT(s) - 1| RESET|OUT| | A | 1 |=> can support up to [ 12] logic PT(s) - 2| CLK_REF_1_|NOD| | A | 1 |=> can support up to [ 10] logic PT(s) - 3| | ? | | S | |=> can support up to [ 7] logic PT(s) + 0| CLK_EXP|OUT| | A | 1 |=> can support up to [ 10] logic PT(s) + 1| RESET|OUT| | A | 1 |=> can support up to [ 15] logic PT(s) + 2| | ? | | S | |=> can support up to [ 12] logic PT(s) + 3| | ? | | S | |=> can support up to [ 10] logic PT(s) 4| IPL_030_2_| IO| | S | 3 |=> can support up to [ 15] logic PT(s) - 5| SM_AMIGA_4_|NOD| | S | 2 |=> can support up to [ 15] logic PT(s) + 5| SM_AMIGA_3_|NOD| | S | 3 |=> can support up to [ 15] logic PT(s) 6| | ? | | S | |=> can support up to [ 10] logic PT(s) - 7| | ? | | S | |=> can support up to [ 12] logic PT(s) - 8| IPL_030_0_| IO| | S | 3 |=> can support up to [ 17] logic PT(s) - 9| inst_VPA_D|NOD| | A | 1 |=> can support up to [ 13] logic PT(s) -10| | ? | | S | |=> can support up to [ 12] logic PT(s) -11| | ? | | S | |=> can support up to [ 10] logic PT(s) -12| IPL_030_1_| IO| | S | 3 |=> can support up to [ 15] logic PT(s) -13| SM_AMIGA_1_|NOD| | S | 3 |=> can support up to [ 15] logic PT(s) -14| | ? | | S | |=> can support up to [ 10] logic PT(s) + 7| | ? | | S | |=> can support up to [ 10] logic PT(s) + 8| IPL_030_0_| IO| | S | 3 |=> can support up to [ 15] logic PT(s) + 9| SM_AMIGA_1_|NOD| | S | 3 |=> can support up to [ 15] logic PT(s) +10| | ? | | S | |=> can support up to [ 10] logic PT(s) +11| | ? | | S | |=> can support up to [ 15] logic PT(s) +12| IPL_030_1_| IO| | S | 3 |=> can support up to [ 20] logic PT(s) +13| | ? | | S | |=> can support up to [ 15] logic PT(s) +14| | ? | | S | |=> can support up to [ 15] logic PT(s) 15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- =========================================================================== @@ -555,18 +557,18 @@ _|_________________|__|__|___|_____|_______________________________________ _|_________________|__|_____|____________________|________________________ 0| CLK_EXP|OUT| | => | 5 6 7 ( 0)| 5 4 3 ( 10) 1| RESET|OUT| | => | 5 6 ( 7) 0 | 5 4 ( 3) 10 - 2| CLK_REF_1_|NOD| | => | 6 7 0 1 | 4 3 10 9 + 2| | | | => | 6 7 0 1 | 4 3 10 9 3| | | | => | 6 7 0 1 | 4 3 10 9 4| IPL_030_2_| IO| | => | 7 0 ( 1) 2 | 3 10 ( 9) 8 - 5| SM_AMIGA_4_|NOD| | => | 7 0 1 2 | 3 10 9 8 + 5| SM_AMIGA_3_|NOD| | => | 7 0 1 2 | 3 10 9 8 6| | | | => | 0 1 2 3 | 10 9 8 7 7| | | | => | 0 1 2 3 | 10 9 8 7 8| IPL_030_0_| IO| | => | 1 ( 2) 3 4 | 9 ( 8) 7 6 - 9| inst_VPA_D|NOD| | => | 1 2 3 4 | 9 8 7 6 + 9| SM_AMIGA_1_|NOD| | => | 1 2 3 4 | 9 8 7 6 10| | | | => | 2 3 4 5 | 8 7 6 5 11| | | | => | 2 3 4 5 | 8 7 6 5 12| IPL_030_1_| IO| | => |( 3) 4 5 6 |( 7) 6 5 4 -13| SM_AMIGA_1_|NOD| | => | 3 4 5 6 | 7 6 5 4 +13| | | | => | 3 4 5 6 | 7 6 5 4 14| | | | => | 4 5 6 7 | 6 5 4 3 15| | | | => | 4 5 6 7 | 6 5 4 3 --------------------------------------------------------------------------- @@ -625,13 +627,13 @@ IMX No. | +---- Block IO Pin or Macrocell Number 1 [IOpin 1 | 9| IO IPL_030_2_|*| ] paired w/[ RN_IPL_030_2_] [RegIn 1 |129| -| | ] - [MCell 2 |128|NOD CLK_REF_1_| |*] + [MCell 2 |128| -| | ] [MCell 3 |130| -| | ] 2 [IOpin 2 | 8| IO IPL_030_0_|*| ] paired w/[ RN_IPL_030_0_] [RegIn 2 |132| -| | ] [MCell 4 |131|NOD RN_IPL_030_2_| |*] paired w/[ IPL_030_2_] - [MCell 5 |133|NOD SM_AMIGA_4_| |*] + [MCell 5 |133|NOD SM_AMIGA_3_| |*] 3 [IOpin 3 | 7| IO IPL_030_1_|*| ] paired w/[ RN_IPL_030_1_] [RegIn 3 |135| -| | ] @@ -641,7 +643,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 4 [IOpin 4 | 6|INP A_29_|*|*] [RegIn 4 |138| -| | ] [MCell 8 |137|NOD RN_IPL_030_0_| |*] paired w/[ IPL_030_0_] - [MCell 9 |139|NOD inst_VPA_D| |*] + [MCell 9 |139|NOD SM_AMIGA_1_| |*] 5 [IOpin 5 | 5|INP A_30_|*|*] [RegIn 5 |141| -| | ] @@ -651,7 +653,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 6 [IOpin 6 | 4|INP A_31_|*|*] [RegIn 6 |144| -| | ] [MCell 12 |143|NOD RN_IPL_030_1_| |*] paired w/[ IPL_030_1_] - [MCell 13 |145|NOD SM_AMIGA_1_| |*] + [MCell 13 |145| -| | ] 7 [IOpin 7 | 3|OUT RESET|*| ] [RegIn 7 |147| -| | ] @@ -665,21 +667,21 @@ IMX No. | +---- Block IO Pin or Macrocell Number | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- Mux00| IOPin 6 2 ( 67)| IPL_0_ -Mux01| Mcel 3 13 ( 193)| inst_CLK_000_D1 -Mux02| ... | ... +Mux01| Mcel 1 12 ( 143)| RN_IPL_030_1_ +Mux02| Mcel 3 10 ( 188)| SM_AMIGA_4_ Mux03| IOPin 5 4 ( 56)| IPL_1_ Mux04| IOPin 6 3 ( 68)| IPL_2_ -Mux05| ... | ... -Mux06| ... | ... -Mux07| ... | ... +Mux05| Mcel 7 9 ( 283)| inst_CLK_000_D4 +Mux06| Mcel 1 9 ( 139)| SM_AMIGA_1_ +Mux07| Mcel 7 13 ( 289)| inst_CLK_000_D5 Mux08| Mcel 1 8 ( 137)| RN_IPL_030_0_ Mux09| ... | ... -Mux10| Input Pin ( 36)| VPA +Mux10| Mcel 6 9 ( 259)| inst_CLK_OUT_PRE Mux11| ... | ... -Mux12| Mcel 1 12 ( 143)| RN_IPL_030_1_ +Mux12| ... | ... Mux13| Mcel 6 8 ( 257)| inst_CLK_000_D0 -Mux14| ... | ... -Mux15| Mcel 0 0 ( 101)| inst_CLK_OUT_PRE +Mux14| Mcel 6 12 ( 263)| inst_CLK_000_D1 +Mux15| Mcel 0 0 ( 101)| inst_DTACK_SYNC Mux16| ... | ... Mux17| ... | ... Mux18| ... | ... @@ -687,15 +689,15 @@ Mux19| ... | ... Mux20| ... | ... Mux21| Input Pin ( 86)| RST Mux22| Mcel 6 5 ( 253)| SM_AMIGA_2_ -Mux23| Mcel 6 2 ( 248)| SM_AMIGA_5_ +Mux23| ... | ... Mux24| ... | ... -Mux25| ... | ... +Mux25| Mcel 5 0 ( 221)| inst_VPA_SYNC Mux26| ... | ... Mux27| Mcel 1 4 ( 131)| RN_IPL_030_2_ -Mux28| Mcel 1 13 ( 145)| SM_AMIGA_1_ +Mux28| Mcel 1 5 ( 133)| SM_AMIGA_3_ Mux29| Input Pin ( 61)| CLK_OSZI Mux30| ... | ... -Mux31| Mcel 1 5 ( 133)| SM_AMIGA_4_ +Mux31| ... | ... Mux32| ... | ... --------------------------------------------------------------------------- =========================================================================== @@ -913,20 +915,20 @@ Mux32| ... | ... | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| DTACK| IO| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig - 1| BG_000| IO| | S | 3 | 4 to [ 1]| 1 XOR free + 1| VMA| IO| | S | 2 | 4 to [ 1]| 1 XOR free 2| cpu_est_2_|NOD| | A | 3 :+: 1| 2 to [ 2]| 1 XOR to [ 2] 3| | ? | | S | | 4 to [ 2]| 1 XOR free - 4|AMIGA_BUS_ENABLE| IO| | A | 3 | 2 free | 1 XOR free - 5| VMA| IO| | S | 2 | 4 to [ 4]| 1 XOR free - 6| CLK_REF_0_|NOD| | A | 1 | 2 to [ 5]| 1 XOR to [ 6] for 1 PT sig - 7| | ? | | S | | 4 to [ 8]| 1 XOR free - 8| LDS_000| IO| | S |12 | 4 to [ 8]| 1 XOR to [ 8] as logic PT - 9| AS_000| IO| | S | 2 | 4 to [ 8]| 1 XOR to [ 8] as logic PT -10| | ? | | S | | 4 to [ 9]| 1 XOR free -11| | ? | | S | | 4 to [12]| 1 XOR free -12| UDS_000| IO| | S | 8 | 4 to [12]| 1 XOR to [12] as logic PT -13|inst_CLK_000_D1|NOD| | A | 1 | 2 to [12]| 1 XOR to [13] for 1 PT sig -14| | ? | | S | | 4 free | 1 XOR free + 4|AMIGA_BUS_ENABLE| IO| | A | 3 | 2 to [ 4]| 1 XOR to [ 4] as logic PT + 5| AS_000| IO| | S | 2 | 4 to [ 5]| 1 XOR free + 6| cpu_est_0_|NOD| | A | 3 | 2 to [ 6]| 1 XOR to [ 6] as logic PT + 7| | ? | | S | | 4 free | 1 XOR free + 8| LDS_000| IO| | S | 8 | 4 to [ 8]| 1 XOR to [ 8] as logic PT + 9| cpu_est_1_|NOD| | A | 4 | 2 to [ 8]| 1 XOR to [ 8] as logic PT +10| SM_AMIGA_4_|NOD| | S | 2 | 4 to [10]| 1 XOR free +11| | ? | | S | | 4 to [ 9]| 1 XOR free +12| UDS_000| IO| | S | 5 | 4 to [12]| 1 XOR to [12] as logic PT +13| BG_000| IO| | S | 2 | 4 to [13]| 1 XOR free +14| SM_AMIGA_5_|NOD| | S | 2 | 4 to [14]| 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== @@ -940,21 +942,21 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ 0| DTACK| IO| | S | 1 |=> can support up to [ 5] logic PT(s) - 1| BG_000| IO| | S | 3 |=> can support up to [ 9] logic PT(s) - 2| cpu_est_2_|NOD| | A | 3 :+: 1|=> can support up to [ 10] logic PT(s) - 3| | ? | | S | |=> can support up to [ 4] logic PT(s) - 4|AMIGA_BUS_ENABLE| IO| | A | 3 |=> can support up to [ 8] logic PT(s) - 5| VMA| IO| | S | 2 |=> can support up to [ 5] logic PT(s) - 6| CLK_REF_0_|NOD| | A | 1 |=> can support up to [ 1] logic PT(s) - 7| | ? | | S | |=> can support up to [ 1] logic PT(s) - 8| LDS_000| IO| | S |12 |=> can support up to [ 15] logic PT(s) - 9| AS_000| IO| | S | 2 |=> can support up to [ 5] logic PT(s) -10| | ? | | S | |=> can support up to [ 1] logic PT(s) + 1| VMA| IO| | S | 2 |=> can support up to [ 9] logic PT(s) + 2| cpu_est_2_|NOD| | A | 3 :+: 1|=> can support up to [ 7] logic PT(s) + 3| | ? | | S | |=> can support up to [ 1] logic PT(s) + 4|AMIGA_BUS_ENABLE| IO| | A | 3 |=> can support up to [ 3] logic PT(s) + 5| AS_000| IO| | S | 2 |=> can support up to [ 10] logic PT(s) + 6| cpu_est_0_|NOD| | A | 3 |=> can support up to [ 8] logic PT(s) + 7| | ? | | S | |=> can support up to [ 5] logic PT(s) + 8| LDS_000| IO| | S | 8 |=> can support up to [ 13] logic PT(s) + 9| cpu_est_1_|NOD| | A | 4 |=> can support up to [ 5] logic PT(s) +10| SM_AMIGA_4_|NOD| | S | 2 |=> can support up to [ 5] logic PT(s) 11| | ? | | S | |=> can support up to [ 1] logic PT(s) -12| UDS_000| IO| | S | 8 |=> can support up to [ 17] logic PT(s) -13|inst_CLK_000_D1|NOD| | A | 1 |=> can support up to [ 11] logic PT(s) -14| | ? | | S | |=> can support up to [ 10] logic PT(s) -15| | ? | | S | |=> can support up to [ 10] logic PT(s) +12| UDS_000| IO| | S | 5 |=> can support up to [ 5] logic PT(s) +13| BG_000| IO| | S | 2 |=> can support up to [ 10] logic PT(s) +14| SM_AMIGA_5_|NOD| | S | 2 |=> can support up to [ 10] logic PT(s) +15| | ? | | S | |=> can support up to [ 5] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 3] > Node-Pin Assignments @@ -965,20 +967,20 @@ _|_________________|__|__|___|_____|_______________________________________ | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ 0| DTACK| IO| | => |( 5) 6 7 0 |( 30) 29 28 35 - 1| BG_000| IO| | => | 5 ( 6) 7 0 | 30 ( 29) 28 35 + 1| VMA| IO| | => | 5 6 7 ( 0)| 30 29 28 ( 35) 2| cpu_est_2_|NOD| | => | 6 7 0 1 | 29 28 35 34 3| | | | => | 6 7 0 1 | 29 28 35 34 4|AMIGA_BUS_ENABLE| IO| | => | 7 0 ( 1) 2 | 28 35 ( 34) 33 - 5| VMA| IO| | => | 7 ( 0) 1 2 | 28 ( 35) 34 33 - 6| CLK_REF_0_|NOD| | => | 0 1 2 3 | 35 34 33 32 + 5| AS_000| IO| | => | 7 0 1 ( 2)| 28 35 34 ( 33) + 6| cpu_est_0_|NOD| | => | 0 1 2 3 | 35 34 33 32 7| | | | => | 0 1 2 3 | 35 34 33 32 8| LDS_000| IO| | => | 1 2 3 ( 4)| 34 33 32 ( 31) - 9| AS_000| IO| | => | 1 ( 2) 3 4 | 34 ( 33) 32 31 -10| | | | => | 2 3 4 5 | 33 32 31 30 + 9| cpu_est_1_|NOD| | => | 1 2 3 4 | 34 33 32 31 +10| SM_AMIGA_4_|NOD| | => | 2 3 4 5 | 33 32 31 30 11| | | | => | 2 3 4 5 | 33 32 31 30 12| UDS_000| IO| | => |( 3) 4 5 6 |( 32) 31 30 29 -13|inst_CLK_000_D1|NOD| | => | 3 4 5 6 | 32 31 30 29 -14| | | | => | 4 5 6 7 | 31 30 29 28 +13| BG_000| IO| | => | 3 4 5 ( 6)| 32 31 30 ( 29) +14| SM_AMIGA_5_|NOD| | => | 4 5 6 7 | 31 30 29 28 15| | | | => | 4 5 6 7 | 31 30 29 28 --------------------------------------------------------------------------- =========================================================================== @@ -990,13 +992,13 @@ _|_________________|__|_____|____________________|________________________ | Sig Type--+ | | | | Signal Name | | | | Node Destinations Via Output Matrix _|_________________|__|___|_____|___________________________________________ - 0| VMA| IO|*| 35| => | 0 1 2 3 4 ( 5) 6 7 + 0| VMA| IO|*| 35| => | 0 ( 1) 2 3 4 5 6 7 1|AMIGA_BUS_ENABLE| IO|*| 34| => | 2 3 ( 4) 5 6 7 8 9 - 2| AS_000| IO|*| 33| => | 4 5 6 7 8 ( 9) 10 11 + 2| AS_000| IO|*| 33| => | 4 ( 5) 6 7 8 9 10 11 3| UDS_000| IO|*| 32| => | 6 7 8 9 10 11 (12) 13 4| LDS_000| IO|*| 31| => | ( 8) 9 10 11 12 13 14 15 5| DTACK| IO|*| 30| => | 10 11 12 13 14 15 ( 0) 1 - 6| BG_000| IO|*| 29| => | 12 13 14 15 0 ( 1) 2 3 + 6| BG_000| IO|*| 29| => | 12 (13) 14 15 0 1 2 3 7| BGACK_000|INP|*| 28| => | 14 15 0 1 2 3 4 5 --------------------------------------------------------------------------- =========================================================================== @@ -1035,7 +1037,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 0 [IOpin 0 | 35| IO VMA|*| ] paired w/[ RN_VMA] [RegIn 0 |174| -| | ] [MCell 0 |173| IO DTACK| | ] - [MCell 1 |175|NOD RN_BG_000| |*] paired w/[ BG_000] + [MCell 1 |175|NOD RN_VMA| |*] paired w/[ VMA] 1 [IOpin 1 | 34| IO AMIGA_BUS_ENABLE|*| ] paired w/[RN_AMIGA_BUS_ENABLE] [RegIn 1 |177| -| | ] @@ -1045,31 +1047,31 @@ IMX No. | +---- Block IO Pin or Macrocell Number 2 [IOpin 2 | 33| IO AS_000|*| ] paired w/[ RN_AS_000] [RegIn 2 |180| -| | ] [MCell 4 |179|NOD RN_AMIGA_BUS_ENABLE| |*] paired w/[AMIGA_BUS_ENABLE] - [MCell 5 |181|NOD RN_VMA| |*] paired w/[ VMA] + [MCell 5 |181|NOD RN_AS_000| |*] paired w/[ AS_000] 3 [IOpin 3 | 32| IO UDS_000|*| ] paired w/[ RN_UDS_000] [RegIn 3 |183| -| | ] - [MCell 6 |182|NOD CLK_REF_0_| |*] + [MCell 6 |182|NOD cpu_est_0_| |*] [MCell 7 |184| -| | ] 4 [IOpin 4 | 31| IO LDS_000|*| ] paired w/[ RN_LDS_000] [RegIn 4 |186| -| | ] [MCell 8 |185|NOD RN_LDS_000| |*] paired w/[ LDS_000] - [MCell 9 |187|NOD RN_AS_000| |*] paired w/[ AS_000] + [MCell 9 |187|NOD cpu_est_1_| |*] 5 [IOpin 5 | 30| IO DTACK|*|*] [RegIn 5 |189| -| | ] - [MCell 10 |188| -| | ] + [MCell 10 |188|NOD SM_AMIGA_4_| |*] [MCell 11 |190| -| | ] 6 [IOpin 6 | 29| IO BG_000|*| ] paired w/[ RN_BG_000] [RegIn 6 |192| -| | ] [MCell 12 |191|NOD RN_UDS_000| |*] paired w/[ UDS_000] - [MCell 13 |193|NOD inst_CLK_000_D1| |*] + [MCell 13 |193|NOD RN_BG_000| |*] paired w/[ BG_000] 7 [IOpin 7 | 28|INP BGACK_000|*|*] [RegIn 7 |195| -| | ] - [MCell 14 |194| -| | ] + [MCell 14 |194|NOD SM_AMIGA_5_| |*] [MCell 15 |196| -| | ] --------------------------------------------------------------------------- =========================================================================== @@ -1079,38 +1081,38 @@ IMX No. | +---- Block IO Pin or Macrocell Number | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- Mux00| IOPin 6 5 ( 70)| SIZE_0_ -Mux01| Mcel 3 13 ( 193)| inst_CLK_000_D1 +Mux01| Mcel 3 13 ( 193)| RN_BG_000 Mux02| Mcel 6 4 ( 251)| RN_E Mux03| Mcel 3 2 ( 176)| cpu_est_2_ -Mux04| Input Pin ( 64)| CLK_030 -Mux05| Input Pin ( 14)| nEXP_SPACE +Mux04| Mcel 3 6 ( 182)| cpu_est_0_ +Mux05| Mcel 3 12 ( 191)| RN_UDS_000 Mux06| IOPin 7 6 ( 79)| SIZE_1_ -Mux07| Mcel 6 12 ( 263)| SM_AMIGA_6_ +Mux07| Mcel 6 12 ( 263)| inst_CLK_000_D1 Mux08| IOPin 6 6 ( 71)| RW Mux09| IOPin 7 3 ( 82)| AS_030 -Mux10| Mcel 6 8 ( 257)| inst_CLK_000_D0 -Mux11| Mcel 3 12 ( 191)| RN_UDS_000 -Mux12| Mcel 3 9 ( 187)| RN_AS_000 -Mux13| Mcel 7 5 ( 277)| SM_AMIGA_7_ -Mux14| Mcel 3 4 ( 179)| RN_AMIGA_BUS_ENABLE -Mux15| IOPin 6 4 ( 69)| A_0_ +Mux10| Mcel 3 4 ( 179)| RN_AMIGA_BUS_ENABLE +Mux11| Mcel 3 5 ( 181)| RN_AS_000 +Mux12| IOPin 0 7 ( 98)| DS_030 +Mux13| Mcel 7 5 ( 277)| SM_AMIGA_6_ +Mux14| IOPin 2 6 ( 21)| BG_030 +Mux15| Input Pin ( 14)| nEXP_SPACE Mux16| Mcel 3 8 ( 185)| RN_LDS_000 -Mux17| IOPin 7 4 ( 81)| DSACK_1_ -Mux18| IOPin 0 7 ( 98)| DS_030 -Mux19| Mcel 7 1 ( 271)| inst_AS_030_000_SYNC -Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux17| Mcel 3 14 ( 194)| SM_AMIGA_5_ +Mux18| IOPin 6 4 ( 69)| A_0_ +Mux19| Mcel 7 1 ( 271)| SM_AMIGA_7_ +Mux20| Input Pin ( 64)| CLK_030 Mux21| Input Pin ( 86)| RST -Mux22| IOPin 2 6 ( 21)| BG_030 -Mux23| Mcel 6 6 ( 254)| inst_CLK_000_D2 -Mux24| Mcel 3 5 ( 181)| RN_VMA -Mux25| Mcel 6 13 ( 265)| cpu_est_0_ +Mux22| ... | ... +Mux23| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux24| Mcel 6 1 ( 247)| inst_VPA_D +Mux25| Mcel 3 9 ( 187)| cpu_est_1_ Mux26| ... | ... -Mux27| Mcel 3 1 ( 175)| RN_BG_000 -Mux28| Mcel 1 5 ( 133)| SM_AMIGA_4_ +Mux27| Mcel 3 1 ( 175)| RN_VMA +Mux28| Mcel 6 8 ( 257)| inst_CLK_000_D0 Mux29| Input Pin ( 61)| CLK_OSZI -Mux30| ... | ... -Mux31| Mcel 1 9 ( 139)| inst_VPA_D -Mux32| Mcel 6 1 ( 247)| cpu_est_1_ +Mux30| Mcel 3 10 ( 188)| SM_AMIGA_4_ +Mux31| ... | ... +Mux32| IOPin 7 4 ( 81)| DSACK_1_ --------------------------------------------------------------------------- =========================================================================== < Block [ 4] > Macrocell (MCell) Cluster Assignments @@ -1326,7 +1328,7 @@ Mux32| ... | ... | Sig Type-+ | | | | | | | XOR to Mcell Assignment | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ - 0|inst_DTACK_SYNC|NOD| | S | 2 | 4 to [ 0]| 1 XOR free + 0| inst_VPA_SYNC|NOD| | S | 2 | 4 to [ 0]| 1 XOR free 1| | ? | | S | | 4 free | 1 XOR free 2| | ? | | S | | 4 free | 1 XOR free 3| | ? | | S | | 4 free | 1 XOR free @@ -1353,7 +1355,7 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0|inst_DTACK_SYNC|NOD| | S | 2 |=> can support up to [ 15] logic PT(s) + 0| inst_VPA_SYNC|NOD| | S | 2 |=> can support up to [ 15] logic PT(s) 1| | ? | | S | |=> can support up to [ 15] logic PT(s) 2| | ? | | S | |=> can support up to [ 20] logic PT(s) 3| | ? | | S | |=> can support up to [ 20] logic PT(s) @@ -1378,7 +1380,7 @@ _|_________________|__|__|___|_____|_______________________________________ | Sig Type---+ | to | Block [ 5] IO Pin | Device Pin | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ - 0|inst_DTACK_SYNC|NOD| | => | 5 6 7 0 | 55 54 53 60 + 0| inst_VPA_SYNC|NOD| | => | 5 6 7 0 | 55 54 53 60 1| | | | => | 5 6 7 0 | 55 54 53 60 2| | | | => | 6 7 0 1 | 54 53 60 59 3| | | | => | 6 7 0 1 | 54 53 60 59 @@ -1442,7 +1444,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number ---|-------|----|---|---|----------|------|-|------------------------------ 0 [IOpin 0 | 60| -| | ] [RegIn 0 |222| -| | ] - [MCell 0 |221|NOD inst_DTACK_SYNC| |*] + [MCell 0 |221|NOD inst_VPA_SYNC| |*] [MCell 1 |223| -| | ] 1 [IOpin 1 | 59|INP A_17_|*|*] @@ -1488,21 +1490,21 @@ IMX No. | +---- Block IO Pin or Macrocell Number --|--|--------------------|--------------------------------------------------- Mux00| Input Pin ( 86)| RST Mux01| ... | ... -Mux02| ... | ... -Mux03| Input Pin ( 11)| CLK_000 +Mux02| Mcel 3 1 ( 175)| RN_VMA +Mux03| Mcel 3 2 ( 176)| cpu_est_2_ Mux04| Input Pin ( 61)| CLK_OSZI -Mux05| Mcel 5 0 ( 221)| inst_DTACK_SYNC -Mux06| Mcel 1 9 ( 139)| inst_VPA_D -Mux07| ... | ... +Mux05| Mcel 5 0 ( 221)| inst_VPA_SYNC +Mux06| ... | ... +Mux07| Mcel 3 9 ( 187)| cpu_est_1_ Mux08| ... | ... Mux09| IOPin 7 3 ( 82)| AS_030 -Mux10| Mcel 6 9 ( 259)| SM_AMIGA_3_ -Mux11| ... | ... +Mux10| Mcel 6 8 ( 257)| inst_CLK_000_D0 +Mux11| Mcel 6 4 ( 251)| RN_E Mux12| ... | ... -Mux13| Mcel 6 8 ( 257)| inst_CLK_000_D0 -Mux14| IOPin 3 5 ( 30)| DTACK +Mux13| ... | ... +Mux14| ... | ... Mux15| ... | ... -Mux16| ... | ... +Mux16| Mcel 3 6 ( 182)| cpu_est_0_ Mux17| ... | ... Mux18| ... | ... Mux19| ... | ... @@ -1510,11 +1512,11 @@ Mux20| ... | ... Mux21| ... | ... Mux22| ... | ... Mux23| ... | ... -Mux24| ... | ... +Mux24| Mcel 6 1 ( 247)| inst_VPA_D Mux25| ... | ... Mux26| ... | ... Mux27| ... | ... -Mux28| ... | ... +Mux28| Mcel 1 5 ( 133)| SM_AMIGA_3_ Mux29| ... | ... Mux30| ... | ... Mux31| ... | ... @@ -1531,20 +1533,20 @@ Mux32| ... | ... | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| CLK_DIV_OUT|OUT| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig - 1| cpu_est_1_|NOD| | S | 4 | 4 to [ 1]| 1 XOR free - 2| SM_AMIGA_5_|NOD| | A | 2 | 2 to [ 2]| 1 XOR free + 1| inst_VPA_D|NOD| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig + 2| CLK_CNT_0_|NOD| | S | 2 | 4 to [ 2]| 1 XOR free 3| | ? | | S | | 4 free | 1 XOR free 4| E| IO| | S | 3 | 4 to [ 4]| 1 XOR free 5| SM_AMIGA_2_|NOD| | A | 3 | 2 to [ 5]| 1 XOR to [ 5] as logic PT 6|inst_CLK_000_D2|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig 7| | ? | | S | | 4 free | 1 XOR free 8|inst_CLK_000_D0|NOD| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig - 9| SM_AMIGA_3_|NOD| | A | 3 | 2 to [ 9]| 1 XOR to [ 9] as logic PT -10| inst_VPA_SYNC|NOD| | A | 2 | 2 to [10]| 1 XOR free + 9|inst_CLK_OUT_PRE|NOD| | S | 3 :+: 1| 4 to [ 9]| 1 XOR to [ 9] +10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free -12| SM_AMIGA_6_|NOD| | A | 4 | 2 to [12]| 1 XOR to [12] as logic PT -13| cpu_est_0_|NOD| | S | 3 | 4 to [13]| 1 XOR free -14| | ? | | S | | 4 to [12]| 1 XOR free +12|inst_CLK_000_D1|NOD| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig +13| CLK_CNT_1_|NOD| | S | 2 | 4 to [13]| 1 XOR free +14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== @@ -1557,22 +1559,22 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| CLK_DIV_OUT|OUT| | S | 1 |=> can support up to [ 5] logic PT(s) - 1| cpu_est_1_|NOD| | S | 4 |=> can support up to [ 14] logic PT(s) - 2| SM_AMIGA_5_|NOD| | A | 2 |=> can support up to [ 8] logic PT(s) + 0| CLK_DIV_OUT|OUT| | S | 1 |=> can support up to [ 9] logic PT(s) + 1| inst_VPA_D|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) + 2| CLK_CNT_0_|NOD| | S | 2 |=> can support up to [ 14] logic PT(s) 3| | ? | | S | |=> can support up to [ 5] logic PT(s) 4| E| IO| | S | 3 |=> can support up to [ 14] logic PT(s) 5| SM_AMIGA_2_|NOD| | A | 3 |=> can support up to [ 12] logic PT(s) 6|inst_CLK_000_D2|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) 7| | ? | | S | |=> can support up to [ 13] logic PT(s) - 8|inst_CLK_000_D0|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) - 9| SM_AMIGA_3_|NOD| | A | 3 |=> can support up to [ 12] logic PT(s) -10| inst_VPA_SYNC|NOD| | A | 2 |=> can support up to [ 8] logic PT(s) -11| | ? | | S | |=> can support up to [ 5] logic PT(s) -12| SM_AMIGA_6_|NOD| | A | 4 |=> can support up to [ 13] logic PT(s) -13| cpu_est_0_|NOD| | S | 3 |=> can support up to [ 10] logic PT(s) -14| | ? | | S | |=> can support up to [ 6] logic PT(s) -15| | ? | | S | |=> can support up to [ 5] logic PT(s) + 8|inst_CLK_000_D0|NOD| | S | 1 |=> can support up to [ 15] logic PT(s) + 9|inst_CLK_OUT_PRE|NOD| | S | 3 :+: 1|=> can support up to [ 18] logic PT(s) +10| | ? | | S | |=> can support up to [ 14] logic PT(s) +11| | ? | | S | |=> can support up to [ 14] logic PT(s) +12|inst_CLK_000_D1|NOD| | S | 1 |=> can support up to [ 15] logic PT(s) +13| CLK_CNT_1_|NOD| | S | 2 |=> can support up to [ 19] logic PT(s) +14| | ? | | S | |=> can support up to [ 10] logic PT(s) +15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 6] > Node-Pin Assignments @@ -1583,19 +1585,19 @@ _|_________________|__|__|___|_____|_______________________________________ | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ 0| CLK_DIV_OUT|OUT| | => | 5 6 7 ( 0)| 70 71 72 ( 65) - 1| cpu_est_1_|NOD| | => | 5 6 7 0 | 70 71 72 65 - 2| SM_AMIGA_5_|NOD| | => | 6 7 0 1 | 71 72 65 66 + 1| inst_VPA_D|NOD| | => | 5 6 7 0 | 70 71 72 65 + 2| CLK_CNT_0_|NOD| | => | 6 7 0 1 | 71 72 65 66 3| | | | => | 6 7 0 1 | 71 72 65 66 4| E| IO| | => | 7 0 ( 1) 2 | 72 65 ( 66) 67 5| SM_AMIGA_2_|NOD| | => | 7 0 1 2 | 72 65 66 67 6|inst_CLK_000_D2|NOD| | => | 0 1 2 3 | 65 66 67 68 7| | | | => | 0 1 2 3 | 65 66 67 68 8|inst_CLK_000_D0|NOD| | => | 1 2 3 4 | 66 67 68 69 - 9| SM_AMIGA_3_|NOD| | => | 1 2 3 4 | 66 67 68 69 -10| inst_VPA_SYNC|NOD| | => | 2 3 4 5 | 67 68 69 70 + 9|inst_CLK_OUT_PRE|NOD| | => | 1 2 3 4 | 66 67 68 69 +10| | | | => | 2 3 4 5 | 67 68 69 70 11| | | | => | 2 3 4 5 | 67 68 69 70 -12| SM_AMIGA_6_|NOD| | => | 3 4 5 6 | 68 69 70 71 -13| cpu_est_0_|NOD| | => | 3 4 5 6 | 68 69 70 71 +12|inst_CLK_000_D1|NOD| | => | 3 4 5 6 | 68 69 70 71 +13| CLK_CNT_1_|NOD| | => | 3 4 5 6 | 68 69 70 71 14| | | | => | 4 5 6 7 | 69 70 71 72 15| | | | => | 4 5 6 7 | 69 70 71 72 --------------------------------------------------------------------------- @@ -1648,11 +1650,11 @@ IMX No. | +---- Block IO Pin or Macrocell Number 0 [IOpin 0 | 65|OUT CLK_DIV_OUT|*| ] [RegIn 0 |246| -| | ] [MCell 0 |245|OUT CLK_DIV_OUT| | ] - [MCell 1 |247|NOD cpu_est_1_| |*] + [MCell 1 |247|NOD inst_VPA_D| |*] 1 [IOpin 1 | 66| IO E|*| ] paired w/[ RN_E] [RegIn 1 |249| -| | ] - [MCell 2 |248|NOD SM_AMIGA_5_| |*] + [MCell 2 |248|NOD CLK_CNT_0_| |*] [MCell 3 |250| -| | ] 2 [IOpin 2 | 67|INP IPL_0_|*|*] @@ -1668,17 +1670,17 @@ IMX No. | +---- Block IO Pin or Macrocell Number 4 [IOpin 4 | 69|INP A_0_|*|*] [RegIn 4 |258| -| | ] [MCell 8 |257|NOD inst_CLK_000_D0| |*] - [MCell 9 |259|NOD SM_AMIGA_3_| |*] + [MCell 9 |259|NOD inst_CLK_OUT_PRE| |*] 5 [IOpin 5 | 70|INP SIZE_0_|*|*] [RegIn 5 |261| -| | ] - [MCell 10 |260|NOD inst_VPA_SYNC| |*] + [MCell 10 |260| -| | ] [MCell 11 |262| -| | ] 6 [IOpin 6 | 71|INP RW|*|*] [RegIn 6 |264| -| | ] - [MCell 12 |263|NOD SM_AMIGA_6_| |*] - [MCell 13 |265|NOD cpu_est_0_| |*] + [MCell 12 |263|NOD inst_CLK_000_D1| |*] + [MCell 13 |265|NOD CLK_CNT_1_| |*] 7 [IOpin 7 | 72| -| | ] [RegIn 7 |267| -| | ] @@ -1692,38 +1694,38 @@ IMX No. | +---- Block IO Pin or Macrocell Number | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- Mux00| Input Pin ( 86)| RST -Mux01| Mcel 3 13 ( 193)| inst_CLK_000_D1 -Mux02| Mcel 6 4 ( 251)| RN_E +Mux01| ... | ... +Mux02| Mcel 7 14 ( 290)| CLK_REF_1_ Mux03| Input Pin ( 11)| CLK_000 Mux04| Input Pin ( 61)| CLK_OSZI -Mux05| Mcel 6 10 ( 260)| inst_VPA_SYNC -Mux06| Mcel 1 9 ( 139)| inst_VPA_D -Mux07| Mcel 3 5 ( 181)| RN_VMA +Mux05| Mcel 5 0 ( 221)| inst_VPA_SYNC +Mux06| ... | ... +Mux07| Mcel 3 9 ( 187)| cpu_est_1_ Mux08| ... | ... -Mux09| Mcel 6 13 ( 265)| cpu_est_0_ -Mux10| Mcel 6 8 ( 257)| inst_CLK_000_D0 -Mux11| ... | ... -Mux12| Mcel 6 9 ( 259)| SM_AMIGA_3_ -Mux13| Mcel 7 5 ( 277)| SM_AMIGA_7_ -Mux14| Mcel 6 12 ( 263)| SM_AMIGA_6_ -Mux15| Mcel 0 0 ( 101)| inst_CLK_OUT_PRE -Mux16| Mcel 3 2 ( 176)| cpu_est_2_ +Mux09| Mcel 6 13 ( 265)| CLK_CNT_1_ +Mux10| Input Pin ( 36)| VPA +Mux11| Mcel 6 4 ( 251)| RN_E +Mux12| Mcel 6 9 ( 259)| inst_CLK_OUT_PRE +Mux13| Mcel 6 8 ( 257)| inst_CLK_000_D0 +Mux14| Mcel 6 12 ( 263)| inst_CLK_000_D1 +Mux15| Mcel 0 0 ( 101)| inst_DTACK_SYNC +Mux16| Mcel 3 6 ( 182)| cpu_est_0_ Mux17| ... | ... Mux18| ... | ... -Mux19| Mcel 7 1 ( 271)| inst_AS_030_000_SYNC +Mux19| ... | ... Mux20| ... | ... Mux21| ... | ... Mux22| Mcel 6 5 ( 253)| SM_AMIGA_2_ -Mux23| Mcel 6 6 ( 254)| inst_CLK_000_D2 -Mux24| Mcel 6 1 ( 247)| cpu_est_1_ -Mux25| Mcel 5 0 ( 221)| inst_DTACK_SYNC +Mux23| Mcel 6 2 ( 248)| CLK_CNT_0_ +Mux24| ... | ... +Mux25| ... | ... Mux26| ... | ... Mux27| ... | ... -Mux28| Mcel 1 5 ( 133)| SM_AMIGA_4_ +Mux28| Mcel 3 2 ( 176)| cpu_est_2_ Mux29| ... | ... Mux30| ... | ... -Mux31| Mcel 6 2 ( 248)| SM_AMIGA_5_ -Mux32| IOPin 7 3 ( 82)| AS_030 +Mux31| Mcel 1 5 ( 133)| SM_AMIGA_3_ +Mux32| ... | ... --------------------------------------------------------------------------- =========================================================================== < Block [ 7] > Macrocell (MCell) Cluster Assignments @@ -1736,20 +1738,20 @@ Mux32| IOPin 7 3 ( 82)| AS_030 | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| FPU_CS| IO| | S | 2 | 4 to [ 0]| 1 XOR free - 1|inst_AS_030_000_SYNC|NOD| | S | 4 | 4 to [ 1]| 1 XOR free - 2| | ? | | S | | 4 free | 1 XOR free - 3| | ? | | S | | 4 free | 1 XOR free + 1| SM_AMIGA_7_|NOD| | S | 5 | 4 to [ 1]| 1 XOR to [ 1] as logic PT + 2|inst_AS_030_000_SYNC|NOD| | S | 7 | 4 to [ 2]| 1 XOR to [ 2] as logic PT + 3| | ? | | S | | 4 to [ 2]| 1 XOR free 4| BGACK_030| IO| | S | 2 | 4 to [ 4]| 1 XOR free - 5| SM_AMIGA_7_|NOD| | S | 2 | 4 to [ 5]| 1 XOR free - 6| | ? | | S | | 4 free | 1 XOR free + 5| SM_AMIGA_6_|NOD| | S | 2 | 4 to [ 5]| 1 XOR free + 6| SM_AMIGA_0_|NOD| | S | 4 | 4 to [ 6]| 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free - 8| DSACK_1_| IO| | S | 2 | 4 to [ 8]| 1 XOR free - 9| SM_AMIGA_0_|NOD| | S | 3 | 4 to [ 9]| 1 XOR free -10| | ? | | S | | 4 free | 1 XOR free + 8| DSACK_1_| IO| | S | 2 | 4 free | 1 XOR free + 9|inst_CLK_000_D4|NOD| | A | 1 | 2 to [ 8]| 1 XOR to [ 9] for 1 PT sig +10|inst_CLK_000_D3|NOD| | A | 1 | 2 free | 1 XOR to [10] for 1 PT sig 11| | ? | | S | | 4 free | 1 XOR free 12| DSACK_0_|OUT| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig -13| | ? | | S | | 4 free | 1 XOR free -14| | ? | | S | | 4 free | 1 XOR free +13|inst_CLK_000_D5|NOD| | A | 1 | 2 free | 1 XOR to [13] for 1 PT sig +14| CLK_REF_1_|NOD| | A | 1 | 2 free | 1 XOR to [14] for 1 PT sig 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== @@ -1762,22 +1764,22 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| FPU_CS| IO| | S | 2 |=> can support up to [ 10] logic PT(s) - 1|inst_AS_030_000_SYNC|NOD| | S | 4 |=> can support up to [ 15] logic PT(s) - 2| | ? | | S | |=> can support up to [ 10] logic PT(s) - 3| | ? | | S | |=> can support up to [ 10] logic PT(s) - 4| BGACK_030| IO| | S | 2 |=> can support up to [ 15] logic PT(s) - 5| SM_AMIGA_7_|NOD| | S | 2 |=> can support up to [ 15] logic PT(s) - 6| | ? | | S | |=> can support up to [ 10] logic PT(s) + 0| FPU_CS| IO| | S | 2 |=> can support up to [ 5] logic PT(s) + 1| SM_AMIGA_7_|NOD| | S | 5 |=> can support up to [ 5] logic PT(s) + 2|inst_AS_030_000_SYNC|NOD| | S | 7 |=> can support up to [ 10] logic PT(s) + 3| | ? | | S | |=> can support up to [ 1] logic PT(s) + 4| BGACK_030| IO| | S | 2 |=> can support up to [ 5] logic PT(s) + 5| SM_AMIGA_6_|NOD| | S | 2 |=> can support up to [ 10] logic PT(s) + 6| SM_AMIGA_0_|NOD| | S | 4 |=> can support up to [ 15] logic PT(s) 7| | ? | | S | |=> can support up to [ 10] logic PT(s) - 8| DSACK_1_| IO| | S | 2 |=> can support up to [ 15] logic PT(s) - 9| SM_AMIGA_0_|NOD| | S | 3 |=> can support up to [ 15] logic PT(s) -10| | ? | | S | |=> can support up to [ 14] logic PT(s) -11| | ? | | S | |=> can support up to [ 19] logic PT(s) -12| DSACK_0_|OUT| | S | 1 |=> can support up to [ 20] logic PT(s) -13| | ? | | S | |=> can support up to [ 19] logic PT(s) -14| | ? | | S | |=> can support up to [ 15] logic PT(s) -15| | ? | | S | |=> can support up to [ 10] logic PT(s) + 8| DSACK_1_| IO| | S | 2 |=> can support up to [ 14] logic PT(s) + 9|inst_CLK_000_D4|NOD| | A | 1 |=> can support up to [ 13] logic PT(s) +10|inst_CLK_000_D3|NOD| | A | 1 |=> can support up to [ 12] logic PT(s) +11| | ? | | S | |=> can support up to [ 13] logic PT(s) +12| DSACK_0_|OUT| | S | 1 |=> can support up to [ 14] logic PT(s) +13|inst_CLK_000_D5|NOD| | A | 1 |=> can support up to [ 14] logic PT(s) +14| CLK_REF_1_|NOD| | A | 1 |=> can support up to [ 10] logic PT(s) +15| | ? | | S | |=> can support up to [ 7] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 7] > Node-Pin Assignments @@ -1788,20 +1790,20 @@ _|_________________|__|__|___|_____|_______________________________________ | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ 0| FPU_CS| IO| | => | 5 6 ( 7) 0 | 80 79 ( 78) 85 - 1|inst_AS_030_000_SYNC|NOD| | => | 5 6 7 0 | 80 79 78 85 - 2| | | | => | 6 7 0 1 | 79 78 85 84 + 1| SM_AMIGA_7_|NOD| | => | 5 6 7 0 | 80 79 78 85 + 2|inst_AS_030_000_SYNC|NOD| | => | 6 7 0 1 | 79 78 85 84 3| | | | => | 6 7 0 1 | 79 78 85 84 4| BGACK_030| IO| | => | 7 0 1 ( 2)| 78 85 84 ( 83) - 5| SM_AMIGA_7_|NOD| | => | 7 0 1 2 | 78 85 84 83 - 6| | | | => | 0 1 2 3 | 85 84 83 82 + 5| SM_AMIGA_6_|NOD| | => | 7 0 1 2 | 78 85 84 83 + 6| SM_AMIGA_0_|NOD| | => | 0 1 2 3 | 85 84 83 82 7| | | | => | 0 1 2 3 | 85 84 83 82 8| DSACK_1_| IO| | => | 1 2 3 ( 4)| 84 83 82 ( 81) - 9| SM_AMIGA_0_|NOD| | => | 1 2 3 4 | 84 83 82 81 -10| | | | => | 2 3 4 5 | 83 82 81 80 + 9|inst_CLK_000_D4|NOD| | => | 1 2 3 4 | 84 83 82 81 +10|inst_CLK_000_D3|NOD| | => | 2 3 4 5 | 83 82 81 80 11| | | | => | 2 3 4 5 | 83 82 81 80 12| DSACK_0_|OUT| | => | 3 4 ( 5) 6 | 82 81 ( 80) 79 -13| | | | => | 3 4 5 6 | 82 81 80 79 -14| | | | => | 4 5 6 7 | 81 80 79 78 +13|inst_CLK_000_D5|NOD| | => | 3 4 5 6 | 82 81 80 79 +14| CLK_REF_1_|NOD| | => | 4 5 6 7 | 81 80 79 78 15| | | | => | 4 5 6 7 | 81 80 79 78 --------------------------------------------------------------------------- =========================================================================== @@ -1855,41 +1857,41 @@ IMX No. | +---- Block IO Pin or Macrocell Number 0 [IOpin 0 | 85|INP A_22_|*|*] [RegIn 0 |270| -| | ] [MCell 0 |269|NOD RN_FPU_CS| |*] paired w/[ FPU_CS] - [MCell 1 |271|NOD inst_AS_030_000_SYNC| |*] + [MCell 1 |271|NOD SM_AMIGA_7_| |*] 1 [IOpin 1 | 84|INP A_23_|*|*] [RegIn 1 |273| -| | ] - [MCell 2 |272| -| | ] + [MCell 2 |272|NOD inst_AS_030_000_SYNC| |*] [MCell 3 |274| -| | ] 2 [IOpin 2 | 83| IO BGACK_030|*| ] paired w/[ RN_BGACK_030] [RegIn 2 |276| -| | ] [MCell 4 |275|NOD RN_BGACK_030| |*] paired w/[ BGACK_030] - [MCell 5 |277|NOD SM_AMIGA_7_| |*] + [MCell 5 |277|NOD SM_AMIGA_6_| |*] 3 [IOpin 3 | 82|INP AS_030|*|*] [RegIn 3 |279| -| | ] - [MCell 6 |278| -| | ] + [MCell 6 |278|NOD SM_AMIGA_0_| |*] [MCell 7 |280| -| | ] 4 [IOpin 4 | 81| IO DSACK_1_|*|*] paired w/[ RN_DSACK_1_] [RegIn 4 |282| -| | ] [MCell 8 |281|NOD RN_DSACK_1_| |*] paired w/[ DSACK_1_] - [MCell 9 |283|NOD SM_AMIGA_0_| |*] + [MCell 9 |283|NOD inst_CLK_000_D4| |*] 5 [IOpin 5 | 80|OUT DSACK_0_|*| ] [RegIn 5 |285| -| | ] - [MCell 10 |284| -| | ] + [MCell 10 |284|NOD inst_CLK_000_D3| |*] [MCell 11 |286| -| | ] 6 [IOpin 6 | 79|INP SIZE_1_|*|*] [RegIn 6 |288| -| | ] [MCell 12 |287|OUT DSACK_0_| | ] - [MCell 13 |289| -| | ] + [MCell 13 |289|NOD inst_CLK_000_D5| |*] 7 [IOpin 7 | 78| IO FPU_CS|*| ] paired w/[ RN_FPU_CS] [RegIn 7 |291| -| | ] - [MCell 14 |290| -| | ] + [MCell 14 |290|NOD CLK_REF_1_| |*] [MCell 15 |292| -| | ] --------------------------------------------------------------------------- =========================================================================== @@ -1902,33 +1904,33 @@ Mux00| Input Pin ( 86)| RST Mux01| IOPin 5 2 ( 58)| FC_1_ Mux02| ... | ... Mux03| Mcel 7 8 ( 281)| RN_DSACK_1_ -Mux04| IOPin 3 7 ( 28)| BGACK_000 +Mux04| Input Pin ( 64)| CLK_030 Mux05| Input Pin ( 14)| nEXP_SPACE Mux06| IOPin 5 3 ( 57)| FC_0_ -Mux07| Mcel 3 9 ( 187)| RN_AS_000 +Mux07| Mcel 6 12 ( 263)| inst_CLK_000_D1 Mux08| IOPin 5 1 ( 59)| A_17_ Mux09| IOPin 7 3 ( 82)| AS_030 -Mux10| Mcel 1 13 ( 145)| SM_AMIGA_1_ +Mux10| Mcel 7 1 ( 271)| SM_AMIGA_7_ Mux11| IOPin 0 5 ( 96)| A_16_ Mux12| IOPin 0 6 ( 97)| A_19_ -Mux13| Mcel 7 5 ( 277)| SM_AMIGA_7_ -Mux14| ... | ... -Mux15| Mcel 0 0 ( 101)| inst_CLK_OUT_PRE -Mux16| ... | ... +Mux13| Mcel 7 5 ( 277)| SM_AMIGA_6_ +Mux14| Mcel 7 2 ( 272)| inst_AS_030_000_SYNC +Mux15| ... | ... +Mux16| Mcel 1 9 ( 139)| SM_AMIGA_1_ Mux17| IOPin 0 4 ( 95)| A_18_ -Mux18| ... | ... -Mux19| Mcel 7 1 ( 271)| inst_AS_030_000_SYNC -Mux20| Input Pin ( 64)| CLK_030 -Mux21| Mcel 3 13 ( 193)| inst_CLK_000_D1 +Mux18| Mcel 7 10 ( 284)| inst_CLK_000_D3 +Mux19| Mcel 7 13 ( 289)| inst_CLK_000_D5 +Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux21| Mcel 7 6 ( 278)| SM_AMIGA_0_ Mux22| ... | ... -Mux23| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux24| ... | ... +Mux23| Mcel 6 6 ( 254)| inst_CLK_000_D2 +Mux24| Mcel 3 5 ( 181)| RN_AS_000 Mux25| ... | ... Mux26| ... | ... -Mux27| Mcel 7 9 ( 283)| SM_AMIGA_0_ +Mux27| Mcel 7 9 ( 283)| inst_CLK_000_D4 Mux28| Mcel 6 8 ( 257)| inst_CLK_000_D0 -Mux29| ... | ... +Mux29| Input Pin ( 61)| CLK_OSZI Mux30| Mcel 7 0 ( 269)| RN_FPU_CS Mux31| ... | ... -Mux32| ... | ... +Mux32| IOPin 3 7 ( 28)| BGACK_000 --------------------------------------------------------------------------- \ No newline at end of file diff --git a/Logic/68030_tk.rpt b/Logic/68030_tk.rpt index 9623a68..0274065 100644 --- a/Logic/68030_tk.rpt +++ b/Logic/68030_tk.rpt @@ -12,7 +12,7 @@ Project_Summary Project Name : 68030_tk Project Path : C:\Users\Matze\Documents\GitHub\68030tk\Logic -Project Fitted on : Thu May 22 14:56:14 2014 +Project Fitted on : Sat May 24 11:44:13 2014 Device : M4A5-128/64 Package : 100TQFP @@ -40,8 +40,8 @@ Design_Summary Total Input Pins : 35 Total Output Pins : 22 Total Bidir I/O Pins : 2 - Total Flip-Flops : 40 - Total Product Terms : 116 + Total Flip-Flops : 42 + Total Product Terms : 111 Total Reserved Pins : 0 Total Reserved Blocks : 0 @@ -54,13 +54,13 @@ Dedicated Pins Input-Only Pins 2 2 0 --> 100% Clock/Input Pins 4 4 0 --> 100% I/O Pins 64 53 11 --> 82% -Logic Macrocells 128 47 81 --> 36% +Logic Macrocells 128 49 79 --> 38% Input Registers 64 0 64 --> 0% Unusable Macrocells .. 0 .. -CSM Outputs/Total Block Inputs 264 120 144 --> 45% -Logical Product Terms 640 117 523 --> 18% -Product Term Clusters 128 41 87 --> 32% +CSM Outputs/Total Block Inputs 264 129 135 --> 48% +Logical Product Terms 640 113 527 --> 17% +Product Term Clusters 128 40 88 --> 31%  Blocks_Resource_Summary @@ -71,14 +71,14 @@ Blocks_Resource_Summary --------------------------------------------------------------------------------- Maximum 33 8 8 -- -- 16 80 16 - --------------------------------------------------------------------------------- -Block A 4 7 0 4 0 12 12 13 Hi -Block B 16 8 0 9 0 7 18 11 Hi +Block A 8 7 0 2 0 14 3 15 Hi +Block B 19 8 0 7 0 9 17 11 Hi Block C 1 8 0 2 0 14 2 16 Hi -Block D 31 8 0 10 0 6 37 4 Hi +Block D 30 8 0 12 0 4 38 3 Hi Block E 14 3 0 3 0 13 3 16 Hi -Block F 9 4 0 1 0 15 2 15 Hi -Block G 23 7 0 11 0 5 27 7 Hi -Block H 22 8 0 7 0 9 16 10 Hi +Block F 12 4 0 1 0 15 2 15 Hi +Block G 18 7 0 10 0 6 19 11 Hi +Block H 27 8 0 12 0 4 29 8 Hi --------------------------------------------------------------------------------- Four rightmost columns above reflect last status of the placement process. @@ -287,7 +287,7 @@ Input_Signal_List Pin r e O Input Pin Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- - 82 H . I/O ---D-FGH Hi Fast AS_030 + 82 H . I/O A--D-F-H Hi Fast AS_030 69 G . I/O ---D---- Hi Fast A_0_ 96 A . I/O -------H Hi Fast A_16_ 59 F . I/O -------H Hi Fast A_17_ @@ -316,12 +316,12 @@ Pin Blk PTs Type e s E Fanout Pwr Slew Signal 71 G . I/O ---DE--- Hi Fast RW 70 G . I/O ---D---- Hi Fast SIZE_0_ 79 H . I/O ---D---- Hi Fast SIZE_1_ - 11 . . Ck/I -----FG- - Fast CLK_000 + 11 . . Ck/I ------G- - Fast CLK_000 14 . . Ck/I ---D---H - Fast nEXP_SPACE - 36 . . Ded -B------ - Fast VPA + 36 . . Ded ------G- - Fast VPA 61 . . Ck/I AB-D-FGH - Fast CLK_OSZI 64 . . Ck/I ---D---H - Fast CLK_030 - 86 . . Ded -B-D-FGH - Fast RST + 86 . . Ded AB-D-FGH - Fast RST ---------------------------------------------------------------------- Power : Hi = High @@ -345,7 +345,7 @@ Pin Blk PTs Type e s E Fanout Pwr Slew Signal 22 C 1 COM -------- Hi Fast AVEC_EXP 41 E 1 COM -------- Hi Fast BERR 83 H 2 DFF * * -------- Hi Fast BGACK_030 - 29 D 3 DFF * * -------- Hi Fast BG_000 + 29 D 2 DFF * * -------- Hi Fast BG_000 47 E 1 COM -------- Hi Fast CIIN 65 G 1 DFF * * -------- Hi Fast CLK_DIV_OUT 10 B 1 DFF * * -------- Hi Fast CLK_EXP @@ -355,9 +355,9 @@ Pin Blk PTs Type e s E Fanout Pwr Slew Signal 8 B 3 DFF * * -------- Hi Fast IPL_030_0_ 7 B 3 DFF * * -------- Hi Fast IPL_030_1_ 9 B 3 DFF * * -------- Hi Fast IPL_030_2_ - 31 D 12 DFF * * -------- Hi Fast LDS_000 + 31 D 8 DFF * * -------- Hi Fast LDS_000 3 B 1 DFF * * -------- Hi Fast RESET - 32 D 8 DFF * * -------- Hi Fast UDS_000 + 32 D 5 DFF * * -------- Hi Fast UDS_000 35 D 2 TFF * * -------- Hi Fast VMA ---------------------------------------------------------------------- @@ -375,7 +375,7 @@ Bidir_Signal_List Pin Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- 81 H 2 DFF * * ---D---- Hi Fast DSACK_1_ - 30 D 1 DFF * * -----F-- Hi Fast DTACK + 30 D 1 DFF * * A------- Hi Fast DTACK ---------------------------------------------------------------------- Power : Hi = High @@ -391,42 +391,44 @@ Buried_Signal_List Pin r e O Node #Mc Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- - A12 A 3 DFF * * A------- Hi Fast CLK_CNT_0_ - A8 A 4 DFF * * A------- Hi Fast CLK_CNT_1_ - D6 D 1 LAT * * A------- Hi Fast CLK_REF_0_ - B2 B 1 LAT * * A------- Hi Fast CLK_REF_1_ + G2 G 2 DFF * * ------G- Hi Fast CLK_CNT_0_ + G13 G 2 DFF * * ------G- Hi Fast CLK_CNT_1_ + H14 H 1 LAT * * ------G- Hi Fast CLK_REF_1_ D4 D 3 DFF * * ---D---- Hi - RN_AMIGA_BUS_ENABLE --> AMIGA_BUS_ENABLE - D9 D 2 DFF * * ---D---H Hi - RN_AS_000 --> AS_000 + D5 D 2 DFF * * ---D---H Hi - RN_AS_000 --> AS_000 H4 H 2 DFF * * ---D---H Hi - RN_BGACK_030 --> BGACK_030 - D1 D 3 DFF * * ---D---- Hi - RN_BG_000 --> BG_000 + D13 D 2 DFF * * ---D---- Hi - RN_BG_000 --> BG_000 H8 H 2 DFF * * -------H Hi - RN_DSACK_1_ --> DSACK_1_ - G4 G 3 TFF * * ---D--G- Hi - RN_E --> E + G4 G 3 TFF * * ---D-FG- Hi - RN_E --> E H0 H 2 DFF * * --C-E--H Hi - RN_FPU_CS --> FPU_CS B8 B 3 DFF * * -B------ Hi - RN_IPL_030_0_ --> IPL_030_0_ B12 B 3 DFF * * -B------ Hi - RN_IPL_030_1_ --> IPL_030_1_ B4 B 3 DFF * * -B------ Hi - RN_IPL_030_2_ --> IPL_030_2_ - D8 D 12 DFF * * ---D---- Hi - RN_LDS_000 --> LDS_000 - D12 D 8 DFF * * ---D---- Hi - RN_UDS_000 --> UDS_000 - D5 D 2 TFF * * ---D--G- Hi - RN_VMA --> VMA - H9 H 3 DFF * * -------H Hi Fast SM_AMIGA_0_ - B13 B 3 DFF * * -B-----H Hi Fast SM_AMIGA_1_ + D8 D 8 DFF * * ---D---- Hi - RN_LDS_000 --> LDS_000 + D12 D 5 DFF * * ---D---- Hi - RN_UDS_000 --> UDS_000 + D1 D 2 TFF * * ---D-F-- Hi - RN_VMA --> VMA + H6 H 4 DFF * * -------H Hi Fast SM_AMIGA_0_ + B9 B 3 DFF * * -B-----H Hi Fast SM_AMIGA_1_ G5 G 3 DFF * * -B----G- Hi Fast SM_AMIGA_2_ - G9 G 3 DFF * * -----FG- Hi Fast SM_AMIGA_3_ - B5 B 2 DFF * * -B-D--G- Hi Fast SM_AMIGA_4_ - G2 G 2 DFF * * -B----G- Hi Fast SM_AMIGA_5_ - G12 G 4 DFF * * ---D--G- Hi Fast SM_AMIGA_6_ - H5 H 2 DFF * * ---D--GH Hi Fast SM_AMIGA_7_ - G13 G 3 DFF * * ---D--G- Hi Fast cpu_est_0_ - G1 G 4 TFF * * ---D--G- Hi Fast cpu_est_1_ - D2 D 3 DFF * * ---D--G- Hi Fast cpu_est_2_ - H1 H 4 DFF * * ---D--GH Hi Fast inst_AS_030_000_SYNC - G8 G 1 DFF * * -B-D-FGH Hi Fast inst_CLK_000_D0 - D13 D 1 DFF * * -B-D--GH Hi Fast inst_CLK_000_D1 - G6 G 1 DFF * * ---D--G- Hi Fast inst_CLK_000_D2 - A0 A 4 TFF * * -B----GH Hi Fast inst_CLK_OUT_PRE - F0 F 2 DFF * * -----FG- Hi Fast inst_DTACK_SYNC - B9 B 1 DFF * * ---D-FG- Hi Fast inst_VPA_D - G10 G 2 DFF * * ------G- Hi Fast inst_VPA_SYNC + B5 B 3 DFF * * AB---FG- Hi Fast SM_AMIGA_3_ + D10 D 2 DFF * * -B-D---- Hi Fast SM_AMIGA_4_ + D14 D 2 DFF * * ---D---- Hi Fast SM_AMIGA_5_ + H5 H 2 DFF * * ---D---H Hi Fast SM_AMIGA_6_ + H1 H 5 DFF * * ---D---H Hi Fast SM_AMIGA_7_ + D6 D 3 DFF * * ---D-FG- Hi Fast cpu_est_0_ + D9 D 4 TFF * * ---D-FG- Hi Fast cpu_est_1_ + D2 D 3 DFF * * ---D-FG- Hi Fast cpu_est_2_ + H2 H 7 DFF * * -------H Hi Fast inst_AS_030_000_SYNC + G8 G 1 DFF * * AB-D-FGH Hi Fast inst_CLK_000_D0 + G12 G 1 DFF * * -B-D--GH Hi Fast inst_CLK_000_D1 + G6 G 1 DFF * * -------H Hi Fast inst_CLK_000_D2 + H10 H 1 DFF * * -------H Hi Fast inst_CLK_000_D3 + H9 H 1 DFF * * -B-----H Hi Fast inst_CLK_000_D4 + H13 H 1 DFF * * -B-----H Hi Fast inst_CLK_000_D5 + G9 G 3 DFF * * -B----G- Hi Fast inst_CLK_OUT_PRE + A0 A 2 DFF * * AB----G- Hi Fast inst_DTACK_SYNC + G1 G 1 DFF * * A--D-F-- Hi Fast inst_VPA_D + F0 F 2 DFF * * -B---FG- Hi Fast inst_VPA_SYNC ---------------------------------------------------------------------- Power : Hi = High @@ -447,42 +449,43 @@ Signal Source : Fanout List FC_1_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} AS_030{ I}: DSACK_1_{ H} AS_000{ D} UDS_000{ D} : LDS_000{ D} BG_000{ D} FPU_CS{ H} - :AMIGA_BUS_ENABLE{ D}inst_AS_030_000_SYNC{ H}inst_DTACK_SYNC{ F} - : inst_VPA_SYNC{ G} + :AMIGA_BUS_ENABLE{ D}inst_AS_030_000_SYNC{ H}inst_DTACK_SYNC{ A} + : inst_VPA_SYNC{ F} DS_030{ B}: UDS_000{ D} LDS_000{ D} nEXP_SPACE{. }: DSACK_0_{ H} DSACK_1_{ H} BG_000{ D} - :AMIGA_BUS_ENABLE{ D}inst_AS_030_000_SYNC{ H} - SIZE_0_{ H}: LDS_000{ D} + :AMIGA_BUS_ENABLE{ D}inst_AS_030_000_SYNC{ H} SM_AMIGA_6_{ H} + : SM_AMIGA_7_{ H} BG_030{ D}: BG_000{ D} + BGACK_000{ E}: BGACK_030{ H} FPU_CS{ H}inst_AS_030_000_SYNC{ H} + CLK_030{. }: BG_000{ D} FPU_CS{ H}inst_AS_030_000_SYNC{ H} + CLK_000{. }:inst_CLK_000_D0{ G} + SIZE_0_{ H}: LDS_000{ D} A_30_{ C}: CIIN{ E} A_29_{ C}: CIIN{ E} A_28_{ D}: CIIN{ E} - BGACK_000{ E}: BGACK_030{ H} FPU_CS{ H}inst_AS_030_000_SYNC{ H} A_27_{ D}: CIIN{ E} - CLK_030{. }: BG_000{ D} FPU_CS{ H}inst_AS_030_000_SYNC{ H} A_26_{ D}: CIIN{ E} - CLK_000{. }:inst_DTACK_SYNC{ F} inst_VPA_SYNC{ G}inst_CLK_000_D0{ G} A_25_{ D}: CIIN{ E} A_24_{ D}: CIIN{ E} A_23_{ I}: CIIN{ E} + VPA{. }: inst_VPA_D{ G} A_22_{ I}: CIIN{ E} A_21_{ B}: CIIN{ E} - A_20_{ B}: CIIN{ E} - A_19_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} - A_18_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} - A_17_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} - VPA{. }: inst_VPA_D{ B} - A_16_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} RST{. }: IPL_030_2_{ B} DSACK_1_{ H} AS_000{ D} : UDS_000{ D} LDS_000{ D} BG_000{ D} : BGACK_030{ H} FPU_CS{ H} DTACK{ D} : VMA{ D} RESET{ B}AMIGA_BUS_ENABLE{ D} : IPL_030_1_{ B} IPL_030_0_{ B}inst_AS_030_000_SYNC{ H} - :inst_DTACK_SYNC{ F} inst_VPA_SYNC{ G} SM_AMIGA_6_{ G} - : CLK_REF_0_{ D} CLK_REF_1_{ B} SM_AMIGA_7_{ H} - : SM_AMIGA_4_{ B} SM_AMIGA_1_{ B} SM_AMIGA_3_{ G} - : SM_AMIGA_5_{ G} SM_AMIGA_2_{ G} SM_AMIGA_0_{ H} + :inst_DTACK_SYNC{ A} inst_VPA_SYNC{ F} SM_AMIGA_6_{ H} + : SM_AMIGA_5_{ D} CLK_REF_1_{ H} SM_AMIGA_7_{ H} + : SM_AMIGA_4_{ D} SM_AMIGA_3_{ B} SM_AMIGA_1_{ B} + : SM_AMIGA_2_{ G} SM_AMIGA_0_{ H} + A_20_{ B}: CIIN{ E} + A_19_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} RW{ H}:AMIGA_BUS_DATA_DIR{ E} UDS_000{ D} LDS_000{ D} + A_18_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} + A_17_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} + A_16_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} A_0_{ H}: UDS_000{ D} LDS_000{ D} IPL_1_{ G}: IPL_030_1_{ B} IPL_0_{ H}: IPL_030_0_{ B} @@ -498,54 +501,55 @@ RN_DSACK_1_{ I}: DSACK_1_{ H} RN_BGACK_030{ I}: AS_000{ D} UDS_000{ D} LDS_000{ D} : BGACK_030{ H} DTACK{ D} RN_FPU_CS{ I}: BERR{ E} AVEC_EXP{ C} FPU_CS{ H} - DTACK{ E}:inst_DTACK_SYNC{ F} - RN_E{ H}: E{ G} VMA{ D} cpu_est_1_{ G} - : inst_VPA_SYNC{ G} cpu_est_2_{ D} - RN_VMA{ E}: VMA{ D} inst_VPA_SYNC{ G} + DTACK{ E}:inst_DTACK_SYNC{ A} + RN_E{ H}: E{ G} VMA{ D} cpu_est_1_{ D} + : inst_VPA_SYNC{ F} cpu_est_2_{ D} + RN_VMA{ E}: VMA{ D} inst_VPA_SYNC{ F} RN_AMIGA_BUS_ENABLE{ E}:AMIGA_BUS_ENABLE{ D} RN_IPL_030_1_{ C}: IPL_030_1_{ B} RN_IPL_030_0_{ C}: IPL_030_0_{ B} - cpu_est_0_{ H}: E{ G} VMA{ D} cpu_est_0_{ G} - : cpu_est_1_{ G} inst_VPA_SYNC{ G} cpu_est_2_{ D} - cpu_est_1_{ H}: E{ G} VMA{ D} cpu_est_1_{ G} - : inst_VPA_SYNC{ G} cpu_est_2_{ D} -inst_AS_030_000_SYNC{ I}: AS_000{ D} UDS_000{ D} LDS_000{ D} - :inst_AS_030_000_SYNC{ H} SM_AMIGA_6_{ G} SM_AMIGA_5_{ G} -inst_DTACK_SYNC{ G}:inst_DTACK_SYNC{ F} SM_AMIGA_3_{ G} SM_AMIGA_2_{ G} - inst_VPA_D{ C}: VMA{ D}inst_DTACK_SYNC{ F} inst_VPA_SYNC{ G} -inst_VPA_SYNC{ H}: inst_VPA_SYNC{ G} SM_AMIGA_3_{ G} SM_AMIGA_2_{ G} -inst_CLK_000_D0{ H}: IPL_030_2_{ B} DSACK_1_{ H} BGACK_030{ H} - : E{ G} VMA{ D} IPL_030_1_{ B} - : IPL_030_0_{ B} cpu_est_0_{ G} cpu_est_1_{ G} - :inst_DTACK_SYNC{ F} inst_VPA_SYNC{ G}inst_CLK_000_D1{ D} - : SM_AMIGA_6_{ G} cpu_est_2_{ D} SM_AMIGA_7_{ H} - : SM_AMIGA_4_{ B} SM_AMIGA_1_{ B} SM_AMIGA_3_{ G} - : SM_AMIGA_5_{ G} SM_AMIGA_2_{ G} SM_AMIGA_0_{ H} -inst_CLK_000_D1{ E}: IPL_030_2_{ B} AS_000{ D} UDS_000{ D} - : LDS_000{ D} BGACK_030{ H} E{ G} - : IPL_030_1_{ B} IPL_030_0_{ B} cpu_est_0_{ G} - : cpu_est_1_{ G}inst_CLK_000_D2{ G} SM_AMIGA_6_{ G} - : cpu_est_2_{ D} SM_AMIGA_5_{ G} -inst_CLK_000_D2{ H}: AS_000{ D} UDS_000{ D} LDS_000{ D} - : SM_AMIGA_6_{ G} SM_AMIGA_5_{ G} -inst_CLK_OUT_PRE{ B}: CLK_DIV_OUT{ G} DSACK_1_{ H} CLK_EXP{ B} + cpu_est_0_{ E}: E{ G} VMA{ D} cpu_est_0_{ D} + : cpu_est_1_{ D} inst_VPA_SYNC{ F} cpu_est_2_{ D} + cpu_est_1_{ E}: E{ G} VMA{ D} cpu_est_1_{ D} + : inst_VPA_SYNC{ F} cpu_est_2_{ D} +inst_AS_030_000_SYNC{ I}:inst_AS_030_000_SYNC{ H} SM_AMIGA_6_{ H} SM_AMIGA_7_{ H} +inst_DTACK_SYNC{ B}:inst_DTACK_SYNC{ A} SM_AMIGA_3_{ B} SM_AMIGA_2_{ G} + inst_VPA_D{ H}: VMA{ D}inst_DTACK_SYNC{ A} inst_VPA_SYNC{ F} +inst_VPA_SYNC{ G}: inst_VPA_SYNC{ F} SM_AMIGA_3_{ B} SM_AMIGA_2_{ G} +inst_CLK_000_D0{ H}: IPL_030_2_{ B} BGACK_030{ H} E{ G} + : VMA{ D} IPL_030_1_{ B} IPL_030_0_{ B} + : cpu_est_0_{ D} cpu_est_1_{ D}inst_DTACK_SYNC{ A} + : inst_VPA_SYNC{ F}inst_CLK_000_D1{ G} SM_AMIGA_6_{ H} + : SM_AMIGA_5_{ D} cpu_est_2_{ D} SM_AMIGA_7_{ H} + : SM_AMIGA_4_{ D} SM_AMIGA_3_{ B} SM_AMIGA_1_{ B} + : SM_AMIGA_2_{ G} SM_AMIGA_0_{ H} +inst_CLK_000_D1{ H}: IPL_030_2_{ B} BGACK_030{ H} E{ G} + : IPL_030_1_{ B} IPL_030_0_{ B} cpu_est_0_{ D} + : cpu_est_1_{ D}inst_CLK_000_D2{ G} cpu_est_2_{ D} +inst_CLK_000_D2{ H}: SM_AMIGA_6_{ H} SM_AMIGA_7_{ H}inst_CLK_000_D3{ H} +inst_CLK_000_D5{ I}: DSACK_1_{ H}inst_AS_030_000_SYNC{ H} SM_AMIGA_1_{ B} + : SM_AMIGA_0_{ H} +inst_CLK_OUT_PRE{ H}: CLK_DIV_OUT{ G} CLK_EXP{ B}inst_CLK_OUT_PRE{ G} +SM_AMIGA_6_{ I}:AMIGA_BUS_ENABLE{ D}inst_AS_030_000_SYNC{ H} SM_AMIGA_6_{ H} + : SM_AMIGA_5_{ D} SM_AMIGA_7_{ H} +SM_AMIGA_5_{ E}: AS_000{ D} UDS_000{ D} LDS_000{ D} + : SM_AMIGA_5_{ D} SM_AMIGA_4_{ D} + cpu_est_2_{ E}: E{ G} VMA{ D} cpu_est_1_{ D} + : inst_VPA_SYNC{ F} cpu_est_2_{ D} + CLK_REF_1_{ I}:inst_CLK_OUT_PRE{ G} CLK_CNT_0_{ G} CLK_CNT_1_{ G} +SM_AMIGA_7_{ I}: BG_000{ D}inst_AS_030_000_SYNC{ H} SM_AMIGA_6_{ H} + : SM_AMIGA_7_{ H} +inst_CLK_000_D3{ I}: SM_AMIGA_6_{ H} SM_AMIGA_7_{ H}inst_CLK_000_D4{ H} +SM_AMIGA_4_{ E}: UDS_000{ D} LDS_000{ D} SM_AMIGA_4_{ D} + : SM_AMIGA_3_{ B} +inst_CLK_000_D4{ I}: DSACK_1_{ H}inst_AS_030_000_SYNC{ H}inst_CLK_000_D5{ H} : SM_AMIGA_1_{ B} SM_AMIGA_0_{ H} -SM_AMIGA_6_{ H}: AS_000{ D} UDS_000{ D} LDS_000{ D} - : BG_000{ D}AMIGA_BUS_ENABLE{ D} SM_AMIGA_6_{ G} - : SM_AMIGA_5_{ G} - cpu_est_2_{ E}: E{ G} VMA{ D} cpu_est_1_{ G} - : inst_VPA_SYNC{ G} cpu_est_2_{ D} - CLK_REF_0_{ E}:inst_CLK_OUT_PRE{ A} CLK_CNT_0_{ A} CLK_CNT_1_{ A} - CLK_REF_1_{ C}:inst_CLK_OUT_PRE{ A} CLK_CNT_0_{ A} CLK_CNT_1_{ A} -SM_AMIGA_7_{ I}: BG_000{ D} SM_AMIGA_6_{ G} SM_AMIGA_7_{ H} -SM_AMIGA_4_{ C}: UDS_000{ D} LDS_000{ D} SM_AMIGA_4_{ B} - : SM_AMIGA_3_{ G} -SM_AMIGA_1_{ C}: DSACK_1_{ H} SM_AMIGA_1_{ B} SM_AMIGA_0_{ H} - CLK_CNT_0_{ B}:inst_CLK_OUT_PRE{ A} CLK_CNT_0_{ A} CLK_CNT_1_{ A} - CLK_CNT_1_{ B}:inst_CLK_OUT_PRE{ A} CLK_CNT_0_{ A} CLK_CNT_1_{ A} -SM_AMIGA_3_{ H}:inst_DTACK_SYNC{ F} inst_VPA_SYNC{ G} SM_AMIGA_3_{ G} + CLK_CNT_0_{ H}:inst_CLK_OUT_PRE{ G} CLK_CNT_0_{ G} CLK_CNT_1_{ G} + CLK_CNT_1_{ H}:inst_CLK_OUT_PRE{ G} CLK_CNT_0_{ G} CLK_CNT_1_{ G} +SM_AMIGA_3_{ C}:inst_DTACK_SYNC{ A} inst_VPA_SYNC{ F} SM_AMIGA_3_{ B} : SM_AMIGA_2_{ G} -SM_AMIGA_5_{ H}: SM_AMIGA_4_{ B} SM_AMIGA_5_{ G} +SM_AMIGA_1_{ C}: DSACK_1_{ H}inst_AS_030_000_SYNC{ H} SM_AMIGA_1_{ B} + : SM_AMIGA_0_{ H} SM_AMIGA_2_{ H}: SM_AMIGA_1_{ B} SM_AMIGA_2_{ G} SM_AMIGA_0_{ I}: SM_AMIGA_7_{ H} SM_AMIGA_0_{ H} ----------------------------------------------------------------------------- @@ -557,16 +561,14 @@ Set_Reset_Summary ~~~~~~~~~~~~~~~~~ Block A -block level set pt : GND +block level set pt : !RST block level reset pt : GND Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ | | | | | AVEC -| * | S | BS | BR | inst_CLK_OUT_PRE -| * | S | BS | BR | CLK_CNT_1_ -| * | S | BS | BR | CLK_CNT_0_ +| * | S | BS | BR | inst_DTACK_SYNC | | | | | DS_030 | | | | | A_19_ | | | | | A_16_ @@ -587,13 +589,11 @@ Equations : | * | S | BS | BR | IPL_030_1_ | * | A | | | CLK_EXP | * | A | | | RESET -| * | S | BR | BS | SM_AMIGA_4_ -| * | A | | | inst_VPA_D +| * | S | BR | BS | SM_AMIGA_3_ | * | S | BR | BS | SM_AMIGA_1_ | * | S | BS | BR | RN_IPL_030_0_ | * | S | BS | BR | RN_IPL_030_1_ | * | S | BS | BR | RN_IPL_030_2_ -| * | A | | | CLK_REF_1_ | | | | | A_29_ | | | | | A_30_ | | | | | A_31_ @@ -627,18 +627,20 @@ Equations : | * | S | BS | BR | LDS_000 | * | S | BS | BR | UDS_000 | * | A | | | AMIGA_BUS_ENABLE -| * | S | BS | BR | BG_000 | * | S | BS | BR | VMA | * | S | BS | BR | AS_000 -| * | A | | | inst_CLK_000_D1 +| * | S | BS | BR | BG_000 +| * | A | | | cpu_est_1_ | * | A | | | cpu_est_2_ +| * | A | | | cpu_est_0_ | * | S | BS | BR | RN_VMA | * | S | BS | BR | RN_AS_000 +| * | S | BR | BS | SM_AMIGA_4_ | * | S | BS | BR | RN_LDS_000 | * | S | BS | BR | RN_UDS_000 | * | A | | | RN_AMIGA_BUS_ENABLE | * | S | BS | BR | RN_BG_000 -| * | A | | | CLK_REF_0_ +| * | S | BR | BS | SM_AMIGA_5_ | | | | | BGACK_000 @@ -661,7 +663,7 @@ Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ -| * | S | BS | BR | inst_DTACK_SYNC +| * | S | BS | BR | inst_VPA_SYNC | | | | | A_17_ | | | | | FC_1_ | | | | | FC_0_ @@ -678,15 +680,14 @@ Equations : | * | S | BS | BR | E | * | S | BS | BR | CLK_DIV_OUT | * | S | BS | BR | inst_CLK_000_D0 -| * | A | | | SM_AMIGA_6_ -| * | S | BS | BR | cpu_est_1_ +| * | S | BS | BR | inst_CLK_000_D1 | * | S | BS | BR | RN_E +| * | S | BS | BR | inst_VPA_D | * | A | | | SM_AMIGA_2_ -| * | A | | | SM_AMIGA_3_ -| * | S | BS | BR | cpu_est_0_ -| * | A | | | SM_AMIGA_5_ +| * | S | BS | BR | inst_CLK_OUT_PRE +| * | S | BS | BR | CLK_CNT_1_ +| * | S | BS | BR | CLK_CNT_0_ | * | S | BS | BR | inst_CLK_000_D2 -| * | A | | | inst_VPA_SYNC | | | | | RW | | | | | SIZE_0_ | | | | | A_0_ @@ -705,12 +706,17 @@ Equations : | * | S | BS | BR | BGACK_030 | * | S | BS | BR | FPU_CS | | | | | DSACK_0_ -| * | S | BS | BR | inst_AS_030_000_SYNC | * | S | BS | BR | RN_FPU_CS | * | S | BS | BR | SM_AMIGA_7_ | * | S | BS | BR | RN_BGACK_030 +| * | S | BR | BS | SM_AMIGA_6_ +| * | A | | | inst_CLK_000_D4 +| * | A | | | inst_CLK_000_D5 +| * | S | BS | BR | inst_AS_030_000_SYNC | * | S | BR | BS | SM_AMIGA_0_ | * | S | BS | BR | RN_DSACK_1_ +| * | A | | | inst_CLK_000_D3 +| * | A | | | CLK_REF_1_ | | | | | AS_030 | | | | | A_22_ | | | | | A_23_ @@ -731,22 +737,22 @@ BLOCK_A_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx A0 ... ... mx A17 ... ... +mx A0 RST pin 86 mx A17 ... ... mx A1 ... ... mx A18 ... ... mx A2 ... ... mx A19 ... ... -mx A3 CLK_CNT_1_ mcell A8 mx A20 ... ... -mx A4 CLK_REF_0_ mcell D6 mx A21 ... ... +mx A3 ... ... mx A20 ... ... +mx A4 CLK_OSZI pin 61 mx A21 ... ... mx A5 ... ... mx A22 ... ... mx A6 ... ... mx A23 ... ... -mx A7 ... ... mx A24 ... ... +mx A7 ... ... mx A24 inst_VPA_D mcell G1 mx A8 ... ... mx A25 ... ... -mx A9 CLK_CNT_0_ mcell A12 mx A26 ... ... -mx A10 CLK_REF_1_ mcell B2 mx A27 ... ... -mx A11 ... ... mx A28 ... ... +mx A9 AS_030 pin 82 mx A26 ... ... +mx A10 inst_CLK_000_D0 mcell G8 mx A27 ... ... +mx A11 ... ... mx A28 SM_AMIGA_3_ mcell B5 mx A12 ... ... mx A29 ... ... mx A13 ... ... mx A30 ... ... -mx A14 ... ... mx A31 ... ... -mx A15 ... ... mx A32 ... ... +mx A14 DTACK pin 30 mx A31 ... ... +mx A15 inst_DTACK_SYNC mcell A0 mx A32 ... ... mx A16 ... ... ---------------------------------------------------------------------------- @@ -756,21 +762,21 @@ BLOCK_B_LOGIC_ARRAY_FANIN CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ mx B0 IPL_0_ pin 67 mx B17 ... ... -mx B1 inst_CLK_000_D1 mcell D13 mx B18 ... ... -mx B2 ... ... mx B19 ... ... +mx B1 RN_IPL_030_1_ mcell B12 mx B18 ... ... +mx B2 SM_AMIGA_4_ mcell D10 mx B19 ... ... mx B3 IPL_1_ pin 56 mx B20 ... ... mx B4 IPL_2_ pin 68 mx B21 RST pin 86 -mx B5 ... ... mx B22 SM_AMIGA_2_ mcell G5 -mx B6 ... ... mx B23 SM_AMIGA_5_ mcell G2 -mx B7 ... ... mx B24 ... ... -mx B8 RN_IPL_030_0_ mcell B8 mx B25 ... ... +mx B5 inst_CLK_000_D4 mcell H9 mx B22 SM_AMIGA_2_ mcell G5 +mx B6 SM_AMIGA_1_ mcell B9 mx B23 ... ... +mx B7 inst_CLK_000_D5 mcell H13 mx B24 ... ... +mx B8 RN_IPL_030_0_ mcell B8 mx B25 inst_VPA_SYNC mcell F0 mx B9 ... ... mx B26 ... ... -mx B10 VPA pin 36 mx B27 RN_IPL_030_2_ mcell B4 -mx B11 ... ... mx B28 SM_AMIGA_1_ mcell B13 -mx B12 RN_IPL_030_1_ mcell B12 mx B29 CLK_OSZI pin 61 +mx B10inst_CLK_OUT_PRE mcell G9 mx B27 RN_IPL_030_2_ mcell B4 +mx B11 ... ... mx B28 SM_AMIGA_3_ mcell B5 +mx B12 ... ... mx B29 CLK_OSZI pin 61 mx B13 inst_CLK_000_D0 mcell G8 mx B30 ... ... -mx B14 ... ... mx B31 SM_AMIGA_4_ mcell B5 -mx B15inst_CLK_OUT_PRE mcell A0 mx B32 ... ... +mx B14 inst_CLK_000_D1 mcell G12 mx B31 ... ... +mx B15 inst_DTACK_SYNC mcell A0 mx B32 ... ... mx B16 ... ... ---------------------------------------------------------------------------- @@ -803,22 +809,22 @@ BLOCK_D_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx D0 SIZE_0_ pin 70 mx D17 DSACK_1_ pin 81 -mx D1 inst_CLK_000_D1 mcell D13 mx D18 DS_030 pin 98 -mx D2 RN_E mcell G4 mx D19inst_AS_030_000_SYNC mcell H1 -mx D3 cpu_est_2_ mcell D2 mx D20 RN_BGACK_030 mcell H4 -mx D4 CLK_030 pin 64 mx D21 RST pin 86 -mx D5 nEXP_SPACE pin 14 mx D22 BG_030 pin 21 -mx D6 SIZE_1_ pin 79 mx D23 inst_CLK_000_D2 mcell G6 -mx D7 SM_AMIGA_6_ mcell G12 mx D24 RN_VMA mcell D5 -mx D8 RW pin 71 mx D25 cpu_est_0_ mcell G13 +mx D0 SIZE_0_ pin 70 mx D17 SM_AMIGA_5_ mcell D14 +mx D1 RN_BG_000 mcell D13 mx D18 A_0_ pin 69 +mx D2 RN_E mcell G4 mx D19 SM_AMIGA_7_ mcell H1 +mx D3 cpu_est_2_ mcell D2 mx D20 CLK_030 pin 64 +mx D4 cpu_est_0_ mcell D6 mx D21 RST pin 86 +mx D5 RN_UDS_000 mcell D12 mx D22 ... ... +mx D6 SIZE_1_ pin 79 mx D23 RN_BGACK_030 mcell H4 +mx D7 inst_CLK_000_D1 mcell G12 mx D24 inst_VPA_D mcell G1 +mx D8 RW pin 71 mx D25 cpu_est_1_ mcell D9 mx D9 AS_030 pin 82 mx D26 ... ... -mx D10 inst_CLK_000_D0 mcell G8 mx D27 RN_BG_000 mcell D1 -mx D11 RN_UDS_000 mcell D12 mx D28 SM_AMIGA_4_ mcell B5 -mx D12 RN_AS_000 mcell D9 mx D29 CLK_OSZI pin 61 -mx D13 SM_AMIGA_7_ mcell H5 mx D30 ... ... -mx D14RN_AMIGA_BUS_ENABLE mcell D4 mx D31 inst_VPA_D mcell B9 -mx D15 A_0_ pin 69 mx D32 cpu_est_1_ mcell G1 +mx D10RN_AMIGA_BUS_ENABLE mcell D4 mx D27 RN_VMA mcell D1 +mx D11 RN_AS_000 mcell D5 mx D28 inst_CLK_000_D0 mcell G8 +mx D12 DS_030 pin 98 mx D29 CLK_OSZI pin 61 +mx D13 SM_AMIGA_6_ mcell H5 mx D30 SM_AMIGA_4_ mcell D10 +mx D14 BG_030 pin 21 mx D31 ... ... +mx D15 nEXP_SPACE pin 14 mx D32 DSACK_1_ pin 81 mx D16 RN_LDS_000 mcell D8 ---------------------------------------------------------------------------- @@ -853,21 +859,21 @@ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ mx F0 RST pin 86 mx F17 ... ... mx F1 ... ... mx F18 ... ... -mx F2 ... ... mx F19 ... ... -mx F3 CLK_000 pin 11 mx F20 ... ... +mx F2 RN_VMA mcell D1 mx F19 ... ... +mx F3 cpu_est_2_ mcell D2 mx F20 ... ... mx F4 CLK_OSZI pin 61 mx F21 ... ... -mx F5 inst_DTACK_SYNC mcell F0 mx F22 ... ... -mx F6 inst_VPA_D mcell B9 mx F23 ... ... -mx F7 ... ... mx F24 ... ... +mx F5 inst_VPA_SYNC mcell F0 mx F22 ... ... +mx F6 ... ... mx F23 ... ... +mx F7 cpu_est_1_ mcell D9 mx F24 inst_VPA_D mcell G1 mx F8 ... ... mx F25 ... ... mx F9 AS_030 pin 82 mx F26 ... ... -mx F10 SM_AMIGA_3_ mcell G9 mx F27 ... ... -mx F11 ... ... mx F28 ... ... +mx F10 inst_CLK_000_D0 mcell G8 mx F27 ... ... +mx F11 RN_E mcell G4 mx F28 SM_AMIGA_3_ mcell B5 mx F12 ... ... mx F29 ... ... -mx F13 inst_CLK_000_D0 mcell G8 mx F30 ... ... -mx F14 DTACK pin 30 mx F31 ... ... +mx F13 ... ... mx F30 ... ... +mx F14 ... ... mx F31 ... ... mx F15 ... ... mx F32 ... ... -mx F16 ... ... +mx F16 cpu_est_0_ mcell D6 ---------------------------------------------------------------------------- @@ -876,22 +882,22 @@ BLOCK_G_LOGIC_ARRAY_FANIN CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ mx G0 RST pin 86 mx G17 ... ... -mx G1 inst_CLK_000_D1 mcell D13 mx G18 ... ... -mx G2 RN_E mcell G4 mx G19inst_AS_030_000_SYNC mcell H1 +mx G1 ... ... mx G18 ... ... +mx G2 CLK_REF_1_ mcell H14 mx G19 ... ... mx G3 CLK_000 pin 11 mx G20 ... ... mx G4 CLK_OSZI pin 61 mx G21 ... ... -mx G5 inst_VPA_SYNC mcell G10 mx G22 SM_AMIGA_2_ mcell G5 -mx G6 inst_VPA_D mcell B9 mx G23 inst_CLK_000_D2 mcell G6 -mx G7 RN_VMA mcell D5 mx G24 cpu_est_1_ mcell G1 -mx G8 ... ... mx G25 inst_DTACK_SYNC mcell F0 -mx G9 cpu_est_0_ mcell G13 mx G26 ... ... -mx G10 inst_CLK_000_D0 mcell G8 mx G27 ... ... -mx G11 ... ... mx G28 SM_AMIGA_4_ mcell B5 -mx G12 SM_AMIGA_3_ mcell G9 mx G29 ... ... -mx G13 SM_AMIGA_7_ mcell H5 mx G30 ... ... -mx G14 SM_AMIGA_6_ mcell G12 mx G31 SM_AMIGA_5_ mcell G2 -mx G15inst_CLK_OUT_PRE mcell A0 mx G32 AS_030 pin 82 -mx G16 cpu_est_2_ mcell D2 +mx G5 inst_VPA_SYNC mcell F0 mx G22 SM_AMIGA_2_ mcell G5 +mx G6 ... ... mx G23 CLK_CNT_0_ mcell G2 +mx G7 cpu_est_1_ mcell D9 mx G24 ... ... +mx G8 ... ... mx G25 ... ... +mx G9 CLK_CNT_1_ mcell G13 mx G26 ... ... +mx G10 VPA pin 36 mx G27 ... ... +mx G11 RN_E mcell G4 mx G28 cpu_est_2_ mcell D2 +mx G12inst_CLK_OUT_PRE mcell G9 mx G29 ... ... +mx G13 inst_CLK_000_D0 mcell G8 mx G30 ... ... +mx G14 inst_CLK_000_D1 mcell G12 mx G31 SM_AMIGA_3_ mcell B5 +mx G15 inst_DTACK_SYNC mcell A0 mx G32 ... ... +mx G16 cpu_est_0_ mcell D6 ---------------------------------------------------------------------------- @@ -900,22 +906,22 @@ BLOCK_H_LOGIC_ARRAY_FANIN CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ mx H0 RST pin 86 mx H17 A_18_ pin 95 -mx H1 FC_1_ pin 58 mx H18 ... ... -mx H2 ... ... mx H19inst_AS_030_000_SYNC mcell H1 -mx H3 RN_DSACK_1_ mcell H8 mx H20 CLK_030 pin 64 -mx H4 BGACK_000 pin 28 mx H21 inst_CLK_000_D1 mcell D13 +mx H1 FC_1_ pin 58 mx H18 inst_CLK_000_D3 mcell H10 +mx H2 ... ... mx H19 inst_CLK_000_D5 mcell H13 +mx H3 RN_DSACK_1_ mcell H8 mx H20 RN_BGACK_030 mcell H4 +mx H4 CLK_030 pin 64 mx H21 SM_AMIGA_0_ mcell H6 mx H5 nEXP_SPACE pin 14 mx H22 ... ... -mx H6 FC_0_ pin 57 mx H23 RN_BGACK_030 mcell H4 -mx H7 RN_AS_000 mcell D9 mx H24 ... ... +mx H6 FC_0_ pin 57 mx H23 inst_CLK_000_D2 mcell G6 +mx H7 inst_CLK_000_D1 mcell G12 mx H24 RN_AS_000 mcell D5 mx H8 A_17_ pin 59 mx H25 ... ... mx H9 AS_030 pin 82 mx H26 ... ... -mx H10 SM_AMIGA_1_ mcell B13 mx H27 SM_AMIGA_0_ mcell H9 +mx H10 SM_AMIGA_7_ mcell H1 mx H27 inst_CLK_000_D4 mcell H9 mx H11 A_16_ pin 96 mx H28 inst_CLK_000_D0 mcell G8 -mx H12 A_19_ pin 97 mx H29 ... ... -mx H13 SM_AMIGA_7_ mcell H5 mx H30 RN_FPU_CS mcell H0 -mx H14 ... ... mx H31 ... ... -mx H15inst_CLK_OUT_PRE mcell A0 mx H32 ... ... -mx H16 ... ... +mx H12 A_19_ pin 97 mx H29 CLK_OSZI pin 61 +mx H13 SM_AMIGA_6_ mcell H5 mx H30 RN_FPU_CS mcell H0 +mx H14inst_AS_030_000_SYNC mcell H2 mx H31 ... ... +mx H15 ... ... mx H32 BGACK_000 pin 28 +mx H16 SM_AMIGA_1_ mcell B9 ---------------------------------------------------------------------------- CSM indicates the mux inputs from the Central Switch Matrix. @@ -951,18 +957,18 @@ PostFit_Equations 1 1 1 Pin DSACK_1_.AP 1 1 1 Pin DSACK_1_.C 1 1 1 Pin AS_000.OE - 2 6 1 Pin AS_000.D- + 2 3 1 Pin AS_000.D 1 1 1 Pin AS_000.AP 1 1 1 Pin AS_000.C 1 1 1 Pin UDS_000.OE - 8 10 1 Pin UDS_000.D- + 5 7 1 Pin UDS_000.D- 1 1 1 Pin UDS_000.AP 1 1 1 Pin UDS_000.C 1 1 1 Pin LDS_000.OE - 12 12 1 Pin LDS_000.D- + 8 9 1 Pin LDS_000.D 1 1 1 Pin LDS_000.AP 1 1 1 Pin LDS_000.C - 3 7 1 Pin BG_000.D- + 2 6 1 Pin BG_000.D- 1 1 1 Pin BG_000.AP 1 1 1 Pin BG_000.C 2 4 1 Pin BGACK_030.D @@ -996,15 +1002,15 @@ PostFit_Equations 1 1 1 Node cpu_est_0_.C 4 6 1 Node cpu_est_1_.T 1 1 1 Node cpu_est_1_.C - 4 11 1 Node inst_AS_030_000_SYNC.D + 7 16 1 Node inst_AS_030_000_SYNC.D 1 1 1 Node inst_AS_030_000_SYNC.AP 1 1 1 Node inst_AS_030_000_SYNC.C - 2 7 1 Node inst_DTACK_SYNC.D- + 2 6 1 Node inst_DTACK_SYNC.D- 1 1 1 Node inst_DTACK_SYNC.AP 1 1 1 Node inst_DTACK_SYNC.C 1 1 1 Node inst_VPA_D.D 1 1 1 Node inst_VPA_D.C - 2 11 1 Node inst_VPA_SYNC.D- + 2 10 1 Node inst_VPA_SYNC.D- 1 1 1 Node inst_VPA_SYNC.AP 1 1 1 Node inst_VPA_SYNC.C 1 1 1 Node inst_CLK_000_D0.D @@ -1013,49 +1019,53 @@ PostFit_Equations 1 1 1 Node inst_CLK_000_D1.C 1 1 1 Node inst_CLK_000_D2.D 1 1 1 Node inst_CLK_000_D2.C - 4 4 1 Node inst_CLK_OUT_PRE.T + 1 1 1 Node inst_CLK_000_D5.D + 1 1 1 Node inst_CLK_000_D5.C + 3 3 1 NodeX1 inst_CLK_OUT_PRE.D.X1 + 1 2 1 NodeX2 inst_CLK_OUT_PRE.D.X2 1 1 1 Node inst_CLK_OUT_PRE.C 1 1 1 Node SM_AMIGA_6_.AR - 4 6 1 Node SM_AMIGA_6_.D + 2 7 1 Node SM_AMIGA_6_.D 1 1 1 Node SM_AMIGA_6_.C + 1 1 1 Node SM_AMIGA_5_.AR + 2 3 1 Node SM_AMIGA_5_.D + 1 1 1 Node SM_AMIGA_5_.C 3 6 1 NodeX1 cpu_est_2_.D.X1 1 1 1 NodeX2 cpu_est_2_.D.X2 1 1 1 Node cpu_est_2_.C - 0 0 1 Node CLK_REF_0_.D - 1 1 1 Node CLK_REF_0_.AP - 0 0 1 Node CLK_REF_0_.LH 1 1 1 Node CLK_REF_1_.AR 0 0 1 Node CLK_REF_1_.D 0 0 1 Node CLK_REF_1_.LH - 2 4 1 Node SM_AMIGA_7_.D + 5 9 1 Node SM_AMIGA_7_.D 1 1 1 Node SM_AMIGA_7_.AP 1 1 1 Node SM_AMIGA_7_.C + 1 1 1 Node inst_CLK_000_D3.D + 1 1 1 Node inst_CLK_000_D3.C 1 1 1 Node SM_AMIGA_4_.AR 2 3 1 Node SM_AMIGA_4_.D 1 1 1 Node SM_AMIGA_4_.C - 1 1 1 Node SM_AMIGA_1_.AR - 3 4 1 Node SM_AMIGA_1_.D - 1 1 1 Node SM_AMIGA_1_.C - 3 4 1 Node CLK_CNT_0_.D + 1 1 1 Node inst_CLK_000_D4.D + 1 1 1 Node inst_CLK_000_D4.C + 2 3 1 Node CLK_CNT_0_.D 1 1 1 Node CLK_CNT_0_.C - 4 4 1 Node CLK_CNT_1_.D + 2 3 1 Node CLK_CNT_1_.D 1 1 1 Node CLK_CNT_1_.C 1 1 1 Node SM_AMIGA_3_.AR 3 5 1 Node SM_AMIGA_3_.D 1 1 1 Node SM_AMIGA_3_.C - 1 1 1 Node SM_AMIGA_5_.AR - 2 6 1 Node SM_AMIGA_5_.D - 1 1 1 Node SM_AMIGA_5_.C + 1 1 1 Node SM_AMIGA_1_.AR + 3 5 1 Node SM_AMIGA_1_.D + 1 1 1 Node SM_AMIGA_1_.C 1 1 1 Node SM_AMIGA_2_.AR 3 5 1 Node SM_AMIGA_2_.D 1 1 1 Node SM_AMIGA_2_.C 1 1 1 Node SM_AMIGA_0_.AR - 3 5 1 Node SM_AMIGA_0_.D + 4 6 1 Node SM_AMIGA_0_.D 1 1 1 Node SM_AMIGA_0_.C ========= - 185 P-Term Total: 185 + 184 P-Term Total: 184 Total Pins: 59 - Total Nodes: 23 + Total Nodes: 25 Average P-Term/Output: 2 @@ -1088,7 +1098,7 @@ DSACK_0_ = (1); DSACK_0_.OE = (nEXP_SPACE); IPL_030_2_.D = (!inst_CLK_000_D0.Q & IPL_030_2_.Q - # inst_CLK_000_D1.Q & IPL_030_2_.Q + # IPL_030_2_.Q & inst_CLK_000_D1.Q # IPL_2_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q); IPL_030_2_.AP = (!RST); @@ -1098,7 +1108,7 @@ IPL_030_2_.C = (CLK_OSZI); DSACK_1_.OE = (nEXP_SPACE); !DSACK_1_.D = (!AS_030 & !DSACK_1_.Q - # !inst_CLK_000_D0.Q & inst_CLK_OUT_PRE.Q & SM_AMIGA_1_.Q); + # !inst_CLK_000_D5.Q & inst_CLK_000_D4.Q & SM_AMIGA_1_.Q); DSACK_1_.AP = (!RST); @@ -1106,8 +1116,8 @@ DSACK_1_.C = (CLK_OSZI); AS_000.OE = (BGACK_030.Q); -!AS_000.D = (!AS_030 & !AS_000.Q - # !inst_AS_030_000_SYNC.Q & inst_CLK_000_D1.Q & !inst_CLK_000_D2.Q & SM_AMIGA_6_.Q); +AS_000.D = (AS_030 & !SM_AMIGA_5_.Q + # AS_000.Q & !SM_AMIGA_5_.Q); AS_000.AP = (!RST); @@ -1116,13 +1126,10 @@ AS_000.C = (CLK_OSZI); UDS_000.OE = (BGACK_030.Q); !UDS_000.D = (!AS_030 & DS_030 & !UDS_000.Q - # !AS_030 & RW & inst_AS_030_000_SYNC.Q & !UDS_000.Q - # !AS_030 & RW & !inst_CLK_000_D1.Q & !UDS_000.Q - # !AS_030 & RW & inst_CLK_000_D2.Q & !UDS_000.Q - # !AS_030 & RW & !SM_AMIGA_6_.Q & !UDS_000.Q + # !DS_030 & RW & !A_0_ & SM_AMIGA_5_.Q + # !AS_030 & RW & !SM_AMIGA_5_.Q & !UDS_000.Q # !DS_030 & !RW & !A_0_ & SM_AMIGA_4_.Q - # !AS_030 & !RW & !UDS_000.Q & !SM_AMIGA_4_.Q - # !DS_030 & RW & !A_0_ & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D1.Q & !inst_CLK_000_D2.Q & SM_AMIGA_6_.Q); + # !AS_030 & !RW & !UDS_000.Q & !SM_AMIGA_4_.Q); UDS_000.AP = (!RST); @@ -1130,25 +1137,20 @@ UDS_000.C = (CLK_OSZI); LDS_000.OE = (BGACK_030.Q); -!LDS_000.D = (!AS_030 & DS_030 & !LDS_000.Q - # !AS_030 & RW & inst_AS_030_000_SYNC.Q & !LDS_000.Q - # !AS_030 & RW & !inst_CLK_000_D1.Q & !LDS_000.Q - # !AS_030 & RW & inst_CLK_000_D2.Q & !LDS_000.Q - # !AS_030 & RW & !SM_AMIGA_6_.Q & !LDS_000.Q - # SIZE_1_ & !DS_030 & !RW & SM_AMIGA_4_.Q - # !DS_030 & !RW & !SIZE_0_ & SM_AMIGA_4_.Q - # !DS_030 & !RW & A_0_ & SM_AMIGA_4_.Q - # !AS_030 & !RW & !LDS_000.Q & !SM_AMIGA_4_.Q - # SIZE_1_ & !DS_030 & RW & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D1.Q & !inst_CLK_000_D2.Q & SM_AMIGA_6_.Q - # !DS_030 & RW & !SIZE_0_ & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D1.Q & !inst_CLK_000_D2.Q & SM_AMIGA_6_.Q - # !DS_030 & RW & A_0_ & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D1.Q & !inst_CLK_000_D2.Q & SM_AMIGA_6_.Q); +LDS_000.D = (AS_030 & DS_030 + # DS_030 & LDS_000.Q + # AS_030 & RW & !SM_AMIGA_5_.Q + # RW & !SM_AMIGA_5_.Q & LDS_000.Q + # AS_030 & !RW & !SM_AMIGA_4_.Q + # !RW & LDS_000.Q & !SM_AMIGA_4_.Q + # !SIZE_1_ & !DS_030 & RW & SIZE_0_ & !A_0_ & SM_AMIGA_5_.Q + # !SIZE_1_ & !DS_030 & !RW & SIZE_0_ & !A_0_ & SM_AMIGA_4_.Q); LDS_000.AP = (!RST); LDS_000.C = (CLK_OSZI); !BG_000.D = (!BG_030 & CLK_030 & !BG_000.Q - # AS_030 & !nEXP_SPACE & !BG_030 & !CLK_030 & SM_AMIGA_6_.Q # AS_030 & !nEXP_SPACE & !BG_030 & !CLK_030 & SM_AMIGA_7_.Q); BG_000.AP = (!RST); @@ -1166,7 +1168,7 @@ CLK_EXP.D = (inst_CLK_OUT_PRE.Q); CLK_EXP.C = (CLK_OSZI); -!FPU_CS.D = (!AS_030 & !CLK_030 & !FPU_CS.Q +!FPU_CS.D = (!AS_030 & !FPU_CS.Q # FC_1_ & !AS_030 & BGACK_000 & CLK_030 & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_); FPU_CS.AP = (!RST); @@ -1234,16 +1236,19 @@ cpu_est_1_.T = (E.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D0.Q & !inst_ cpu_est_1_.C = (CLK_OSZI); inst_AS_030_000_SYNC.D = (AS_030 - # !nEXP_SPACE & CLK_030 + # !nEXP_SPACE & inst_AS_030_000_SYNC.Q # !CLK_030 & inst_AS_030_000_SYNC.Q - # FC_1_ & BGACK_000 & CLK_030 & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_); + # !nEXP_SPACE & SM_AMIGA_6_.Q + # inst_AS_030_000_SYNC.Q & !SM_AMIGA_7_.Q + # !inst_CLK_000_D5.Q & inst_CLK_000_D4.Q & SM_AMIGA_1_.Q + # FC_1_ & BGACK_000 & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & inst_AS_030_000_SYNC.Q); inst_AS_030_000_SYNC.AP = (!RST); inst_AS_030_000_SYNC.C = (CLK_OSZI); !inst_DTACK_SYNC.D = (!AS_030 & !inst_DTACK_SYNC.Q - # CLK_000 & inst_VPA_D.Q & inst_CLK_000_D0.Q & SM_AMIGA_3_.Q & !DTACK.PIN); + # inst_VPA_D.Q & inst_CLK_000_D0.Q & SM_AMIGA_3_.Q & !DTACK.PIN); inst_DTACK_SYNC.AP = (!RST); @@ -1254,7 +1259,7 @@ inst_VPA_D.D = (VPA); inst_VPA_D.C = (CLK_OSZI); !inst_VPA_SYNC.D = (!AS_030 & !inst_VPA_SYNC.Q - # CLK_000 & E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_D0.Q & cpu_est_2_.Q & SM_AMIGA_3_.Q); + # E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_D0.Q & cpu_est_2_.Q & SM_AMIGA_3_.Q); inst_VPA_SYNC.AP = (!RST); @@ -1272,22 +1277,32 @@ inst_CLK_000_D2.D = (inst_CLK_000_D1.Q); inst_CLK_000_D2.C = (CLK_OSZI); -inst_CLK_OUT_PRE.T = (CLK_REF_0_.Q & CLK_REF_1_.Q & CLK_CNT_0_.Q & CLK_CNT_1_.Q - # !CLK_REF_0_.Q & CLK_REF_1_.Q & !CLK_CNT_0_.Q & CLK_CNT_1_.Q - # CLK_REF_0_.Q & !CLK_REF_1_.Q & CLK_CNT_0_.Q & !CLK_CNT_1_.Q - # !CLK_REF_0_.Q & !CLK_REF_1_.Q & !CLK_CNT_0_.Q & !CLK_CNT_1_.Q); +inst_CLK_000_D5.D = (inst_CLK_000_D4.Q); + +inst_CLK_000_D5.C = (CLK_OSZI); + +inst_CLK_OUT_PRE.D.X1 = (inst_CLK_OUT_PRE.Q & CLK_CNT_0_.Q + # inst_CLK_OUT_PRE.Q & CLK_CNT_1_.Q + # !inst_CLK_OUT_PRE.Q & !CLK_CNT_0_.Q & !CLK_CNT_1_.Q); + +inst_CLK_OUT_PRE.D.X2 = (CLK_REF_1_.Q & !CLK_CNT_0_.Q); inst_CLK_OUT_PRE.C = (CLK_OSZI); SM_AMIGA_6_.AR = (!RST); -SM_AMIGA_6_.D = (inst_AS_030_000_SYNC.Q & SM_AMIGA_6_.Q - # !inst_CLK_000_D1.Q & SM_AMIGA_6_.Q - # inst_CLK_000_D2.Q & SM_AMIGA_6_.Q - # !inst_CLK_000_D0.Q & SM_AMIGA_7_.Q); +SM_AMIGA_6_.D = (nEXP_SPACE & !inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !SM_AMIGA_7_.Q + # !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D2.Q & SM_AMIGA_7_.Q & inst_CLK_000_D3.Q); SM_AMIGA_6_.C = (CLK_OSZI); +SM_AMIGA_5_.AR = (!RST); + +SM_AMIGA_5_.D = (inst_CLK_000_D0.Q & SM_AMIGA_6_.Q + # inst_CLK_000_D0.Q & SM_AMIGA_5_.Q); + +SM_AMIGA_5_.C = (CLK_OSZI); + cpu_est_2_.D.X1 = (E.Q & cpu_est_0_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_2_.Q # !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_2_.Q # !E.Q & cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_2_.Q); @@ -1296,50 +1311,44 @@ cpu_est_2_.D.X2 = (cpu_est_2_.Q); cpu_est_2_.C = (CLK_OSZI); -CLK_REF_0_.D = (0); - -CLK_REF_0_.AP = (!RST); - -CLK_REF_0_.LH = (0); - CLK_REF_1_.AR = (!RST); CLK_REF_1_.D = (0); CLK_REF_1_.LH = (0); -SM_AMIGA_7_.D = (inst_CLK_000_D0.Q & SM_AMIGA_7_.Q +SM_AMIGA_7_.D = (inst_AS_030_000_SYNC.Q & SM_AMIGA_7_.Q + # inst_CLK_000_D2.Q & SM_AMIGA_7_.Q + # SM_AMIGA_7_.Q & !inst_CLK_000_D3.Q + # !nEXP_SPACE & !inst_CLK_000_D0.Q & SM_AMIGA_6_.Q # AS_000.Q & inst_CLK_000_D0.Q & SM_AMIGA_0_.Q); SM_AMIGA_7_.AP = (!RST); SM_AMIGA_7_.C = (CLK_OSZI); +inst_CLK_000_D3.D = (inst_CLK_000_D2.Q); + +inst_CLK_000_D3.C = (CLK_OSZI); + SM_AMIGA_4_.AR = (!RST); -SM_AMIGA_4_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_4_.Q - # !inst_CLK_000_D0.Q & SM_AMIGA_5_.Q); +SM_AMIGA_4_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_5_.Q + # !inst_CLK_000_D0.Q & SM_AMIGA_4_.Q); SM_AMIGA_4_.C = (CLK_OSZI); -SM_AMIGA_1_.AR = (!RST); +inst_CLK_000_D4.D = (inst_CLK_000_D3.Q); -SM_AMIGA_1_.D = (inst_CLK_000_D0.Q & SM_AMIGA_1_.Q - # inst_CLK_000_D0.Q & SM_AMIGA_2_.Q - # !inst_CLK_OUT_PRE.Q & SM_AMIGA_1_.Q & !SM_AMIGA_2_.Q); +inst_CLK_000_D4.C = (CLK_OSZI); -SM_AMIGA_1_.C = (CLK_OSZI); - -CLK_CNT_0_.D = (CLK_REF_0_.Q & !CLK_CNT_0_.Q - # !CLK_REF_1_.Q & !CLK_CNT_0_.Q & CLK_CNT_1_.Q +CLK_CNT_0_.D = (!CLK_REF_1_.Q & !CLK_CNT_0_.Q & CLK_CNT_1_.Q # CLK_REF_1_.Q & !CLK_CNT_0_.Q & !CLK_CNT_1_.Q); CLK_CNT_0_.C = (CLK_OSZI); -CLK_CNT_1_.D = (CLK_REF_0_.Q & !CLK_CNT_0_.Q & CLK_CNT_1_.Q - # !CLK_REF_1_.Q & !CLK_CNT_0_.Q & CLK_CNT_1_.Q - # !CLK_REF_0_.Q & CLK_CNT_0_.Q & !CLK_CNT_1_.Q - # CLK_REF_1_.Q & CLK_CNT_0_.Q & !CLK_CNT_1_.Q); +CLK_CNT_1_.D = (CLK_CNT_0_.Q & !CLK_CNT_1_.Q + # !CLK_REF_1_.Q & !CLK_CNT_0_.Q & CLK_CNT_1_.Q); CLK_CNT_1_.C = (CLK_OSZI); @@ -1351,12 +1360,13 @@ SM_AMIGA_3_.D = (inst_CLK_000_D0.Q & SM_AMIGA_4_.Q SM_AMIGA_3_.C = (CLK_OSZI); -SM_AMIGA_5_.AR = (!RST); +SM_AMIGA_1_.AR = (!RST); -SM_AMIGA_5_.D = (inst_CLK_000_D0.Q & SM_AMIGA_5_.Q - # !inst_AS_030_000_SYNC.Q & inst_CLK_000_D1.Q & !inst_CLK_000_D2.Q & SM_AMIGA_6_.Q); +SM_AMIGA_1_.D = (inst_CLK_000_D0.Q & SM_AMIGA_1_.Q + # inst_CLK_000_D0.Q & SM_AMIGA_2_.Q + # !inst_CLK_000_D5.Q & inst_CLK_000_D4.Q & SM_AMIGA_1_.Q); -SM_AMIGA_5_.C = (CLK_OSZI); +SM_AMIGA_1_.C = (CLK_OSZI); SM_AMIGA_2_.AR = (!RST); @@ -1370,7 +1380,8 @@ SM_AMIGA_0_.AR = (!RST); SM_AMIGA_0_.D = (!AS_000.Q & SM_AMIGA_0_.Q # !inst_CLK_000_D0.Q & SM_AMIGA_0_.Q - # !inst_CLK_000_D0.Q & inst_CLK_OUT_PRE.Q & SM_AMIGA_1_.Q); + # !inst_CLK_000_D0.Q & inst_CLK_000_D5.Q & SM_AMIGA_1_.Q + # !inst_CLK_000_D0.Q & !inst_CLK_000_D4.Q & SM_AMIGA_1_.Q); SM_AMIGA_0_.C = (CLK_OSZI); diff --git a/Logic/68030_tk.tal b/Logic/68030_tk.tal index c9e8378..128a8d7 100644 --- a/Logic/68030_tk.tal +++ b/Logic/68030_tk.tal @@ -71,17 +71,19 @@ inst_AS_030_000_SYNC 1 1 .. .. .. .. 1 1 inst_CLK_000_D0 1 1 .. .. .. .. 1 1 inst_CLK_000_D1 .. .. .. .. .. .. 1 1 inst_CLK_000_D2 .. .. .. .. .. .. 1 1 + inst_CLK_000_D5 .. .. .. .. .. .. 1 1 inst_CLK_OUT_PRE .. .. .. .. .. .. 1 1 - SM_AMIGA_6_ .. .. .. .. .. .. 1 1 + SM_AMIGA_6_ 1 1 .. .. .. .. 1 1 + SM_AMIGA_5_ .. .. .. .. .. .. 1 1 cpu_est_2_ .. .. .. .. .. .. 1 1 - CLK_REF_0_ .. .. .. .. .. .. 1 1 CLK_REF_1_ .. .. .. .. .. .. 1 1 - SM_AMIGA_7_ .. .. .. .. .. .. 1 1 + SM_AMIGA_7_ 1 1 .. .. .. .. 1 1 + inst_CLK_000_D3 .. .. .. .. .. .. 1 1 SM_AMIGA_4_ .. .. .. .. .. .. 1 1 - SM_AMIGA_1_ .. .. .. .. .. .. 1 1 + inst_CLK_000_D4 .. .. .. .. .. .. 1 1 CLK_CNT_0_ .. .. .. .. .. .. 1 1 CLK_CNT_1_ .. .. .. .. .. .. 1 1 SM_AMIGA_3_ .. .. .. .. .. .. 1 1 - SM_AMIGA_5_ .. .. .. .. .. .. 1 1 + SM_AMIGA_1_ .. .. .. .. .. .. 1 1 SM_AMIGA_2_ .. .. .. .. .. .. 1 1 SM_AMIGA_0_ .. .. .. .. .. .. 1 1 \ No newline at end of file diff --git a/Logic/68030_tk.tt2 b/Logic/68030_tk.tt2 index 0b0c01d..8a20921 100644 --- a/Logic/68030_tk.tt2 +++ b/Logic/68030_tk.tt2 @@ -1,320 +1,323 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Thu May 22 14:56:10 2014 +#$ DATE Sat May 24 11:44:09 2014 #$ MODULE 68030_tk -#$ PINS 59 SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 nEXP_SPACE BERR SIZE_0_ BG_030 A_30_ A_29_ A_28_ BGACK_000 A_27_ CLK_030 A_26_ CLK_000 A_25_ CLK_OSZI A_24_ CLK_DIV_OUT A_23_ A_22_ A_21_ A_20_ AVEC A_19_ AVEC_EXP A_18_ A_17_ VPA A_16_ RST RW AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN A_0_ IPL_1_ IPL_0_ DSACK_0_ FC_0_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 BG_000 BGACK_030 CLK_EXP FPU_CS DTACK E VMA RESET AMIGA_BUS_ENABLE IPL_030_1_ IPL_030_0_ -#$ NODES 23 cpu_est_0_ cpu_est_1_ inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2 inst_CLK_OUT_PRE SM_AMIGA_6_ cpu_est_2_ CLK_REF_0_ CLK_REF_1_ SM_AMIGA_7_ SM_AMIGA_4_ SM_AMIGA_1_ CLK_CNT_0_ CLK_CNT_1_ SM_AMIGA_3_ SM_AMIGA_5_ SM_AMIGA_2_ SM_AMIGA_0_ +#$ PINS 59 SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 SIZE_0_ CLK_OSZI A_30_ CLK_DIV_OUT A_29_ A_28_ A_27_ A_26_ AVEC A_25_ AVEC_EXP A_24_ A_23_ VPA A_22_ A_21_ RST A_20_ A_19_ RW A_18_ A_17_ AMIGA_BUS_DATA_DIR A_16_ AMIGA_BUS_ENABLE_LOW CIIN A_0_ IPL_1_ IPL_0_ DSACK_0_ FC_0_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 BG_000 BGACK_030 CLK_EXP FPU_CS DTACK E VMA RESET AMIGA_BUS_ENABLE IPL_030_1_ IPL_030_0_ +#$ NODES 25 cpu_est_0_ cpu_est_1_ inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2 inst_CLK_000_D5 inst_CLK_OUT_PRE SM_AMIGA_6_ SM_AMIGA_5_ cpu_est_2_ CLK_REF_1_ SM_AMIGA_7_ inst_CLK_000_D3 SM_AMIGA_4_ inst_CLK_000_D4 CLK_CNT_0_ CLK_CNT_1_ SM_AMIGA_3_ SM_AMIGA_1_ SM_AMIGA_2_ SM_AMIGA_0_ .type fr -.i 73 -.o 121 -.ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_ BG_000.Q BGACK_030.Q FPU_CS.Q E.Q VMA.Q cpu_est_0_.Q cpu_est_1_.Q AS_000.Q inst_AS_030_000_SYNC.Q inst_DTACK_SYNC.Q IPL_030_0_.Q inst_VPA_D.Q inst_VPA_SYNC.Q IPL_030_1_.Q inst_CLK_000_D0.Q inst_CLK_000_D1.Q IPL_030_2_.Q inst_CLK_000_D2.Q inst_CLK_OUT_PRE.Q SM_AMIGA_6_.Q cpu_est_2_.Q CLK_REF_0_.Q CLK_REF_1_.Q SM_AMIGA_7_.Q UDS_000.Q LDS_000.Q DSACK_1_.Q SM_AMIGA_4_.Q SM_AMIGA_1_.Q CLK_CNT_0_.Q CLK_CNT_1_.Q SM_AMIGA_3_.Q SM_AMIGA_5_.Q SM_AMIGA_2_.Q SM_AMIGA_0_.Q AMIGA_BUS_ENABLE.Q DSACK_1_.PIN DTACK.PIN -.ob BERR AVEC AVEC_EXP AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.C SM_AMIGA_0_.AR cpu_est_1_.C cpu_est_2_.C E.C IPL_030_0_.C IPL_030_0_.AP IPL_030_1_.C IPL_030_1_.AP IPL_030_2_.C IPL_030_2_.AP SM_AMIGA_7_.C SM_AMIGA_7_.AP VMA.C VMA.AP BGACK_030.C BGACK_030.AP inst_CLK_OUT_PRE.C CLK_CNT_0_.C CLK_CNT_1_.C cpu_est_0_.C inst_VPA_SYNC.C inst_VPA_SYNC.AP FPU_CS.C FPU_CS.AP inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP AS_000.C AS_000.AP AMIGA_BUS_ENABLE.C BG_000.C BG_000.AP DSACK_1_.C DSACK_1_.AP UDS_000.C UDS_000.AP LDS_000.C LDS_000.AP inst_DTACK_SYNC.C inst_DTACK_SYNC.AP CLK_EXP.C DTACK.C DTACK.AP inst_CLK_000_D2.C inst_VPA_D.C inst_CLK_000_D0.C RESET.C inst_CLK_000_D1.C CLK_REF_0_.LH CLK_REF_0_.AP CLK_REF_1_.LH CLK_REF_1_.AR DSACK_0_ DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_DIV_OUT.C CLK_DIV_OUT.D BG_000.D BGACK_030.D FPU_CS.D E.T VMA.T cpu_est_0_.D cpu_est_1_.T CLK_EXP.D AS_000.D inst_AS_030_000_SYNC.D inst_DTACK_SYNC.D IPL_030_0_.D inst_VPA_D.D inst_VPA_SYNC.D IPL_030_1_.D inst_CLK_000_D0.D inst_CLK_000_D1.D IPL_030_2_.D inst_CLK_000_D2.D inst_CLK_OUT_PRE.T SM_AMIGA_6_.D cpu_est_2_.D CLK_REF_0_.D CLK_REF_1_.D SM_AMIGA_7_.D UDS_000.D LDS_000.D DSACK_1_.D SM_AMIGA_4_.D SM_AMIGA_1_.D DTACK.D CLK_CNT_0_.D CLK_CNT_1_.D SM_AMIGA_3_.D RESET.D SM_AMIGA_5_.D SM_AMIGA_2_.D SM_AMIGA_0_.D AMIGA_BUS_ENABLE.D -.p 308 -------------------------------------------------------------------------- ~1~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----1-------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----11------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~ -------1------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 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--------------------------------------------------1------------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~ --------------------------------------------------0------------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ ------------------------------------------------------0---------1----0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~ -------------------------------------------0--------------------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ -------------------------------------------1------1-------------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ --------------------------------------------------0-------------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ --------------0--------------------------------------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 -------------------------------------------------------0---------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 ------------------------------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~ -----1-------------------------------------------------------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------1---------------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------------------------------- 0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~00~~~~~~~~~~~~~~~ --1----------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------0------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------0---------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----00-1--1--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1-01--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------0-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~ ------------0------------------------------------------------------------- ~~~~~~0~0~0~0~0~0~0~0000~0~0~0~0~0~00000~0~0~0~00~0~0~0~0~00~00000~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------0------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------1----------------------------------------------------------- ~~~~~~~0~0~0~0~0~0~0~~~~0~0~0~0~0~0~~~~~0~0~0~0~~0~0~0~0~0~~0~~~~~~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------0----------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ ---------------1---------------------------------------------------------- ~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------1-------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------1------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------1------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------1----------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------1---------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------1--------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------1-------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------0------------------------------------------------- ~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------0------------------------------------------------ ~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------0----------------------------------------------- ~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------0---------------------------------------------- ~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1-----------------1--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1------------------1-------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1-------------------0------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1--------------------1------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----10---11-----------------0010---1-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1------------------------0-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------0-1-------------------------0------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------1------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------0------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~000~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------1----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0----0---------------------------0----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------1---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------01-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------01------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------10------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------1-10------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------00------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-------------------------------------0------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0----0---------------------------------0----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0---------------------------------------0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0------------------------------------------0------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~0~~ ----------------------------------------1---------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------1------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ -------------------------------------------0------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------------0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~0~~~~~~~~~0~~~~~~~0~~~~~~~~~~~~~~ -------------------------------------0------------0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------0--------0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------1-------0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------1-----0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ ---------------------------------------------0----0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ----------------------------------------------0---0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------1--0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------------0-0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ -------------------------------------------------00----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------0-------------1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------0---------1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------0----1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------0-1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------0---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ ---0----------------------------------------------10---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ ---------------------------------0----------------10---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------0---------------10---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------1--------10---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------0-10-------10---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ --------------------------------------------------00---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ --------------------------------------------------0-0--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------10--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------------0--1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ --------------------------------------------0-----11-0-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ --------------------------------------------------0---1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~ ------------------------------------------------------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----1-00-0--------------------------------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------1------1----------------------------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 --------------------------------------------0------1-0-1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -1----0--------1----------------------------0------1-0-1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ ------0--------10---------------------------0------1-0-1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ ------0--------1----------------1-----------0------1-0-1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ ------0--------1----------------0-----------0------1-0-1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ --------------------------------------------------1----0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ --------------------------------------------------0----0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ ---------------------------------------0----------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------0--------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------0-0--------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------1--1-------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------1----------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------0--1-------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ -----------------------------------------01-------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ --------------------------------------------------0-----0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ ---------------------------------------------------1----0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ -----1-00-0------------------------------------------------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------0---------------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ --------------------------------------------0------1-0-----0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ -------------------------------------------------------0---0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ -----01-----------------------------------------------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ -----0---------1----------------------------1---------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ -----0---------1-----------------------------------0--------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ -----0---------1-------------------------------------1------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ -----0---------1---------------------------------------0----0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ -----01------------------------------------------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ -----0---------1----------------------------1----------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ -----0---------1-----------------------------------0---------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ -----0---------1-------------------------------------1-------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ -----0---------1---------------------------------------0-----0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ -----0--------------------------------------------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~ -1----0--------0-----------------------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ ------0--------00----------------------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ ------0--------0----------------1------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ ------0--------0----------------0------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ -----0---------0--------------------------------------------0--0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ -----0---------0---------------------------------------------0-0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ --------------------------------------------------0---1---------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~ -----------------------------------------------------------------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ ---------------------------------------------------------0-------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------------1-------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------------01------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ ---------------------------------------------------------01-------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ ----------------------------------------------------------0-------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ -----------------------------------------------------------------11------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ ----------------------------------------------------------1-------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------------10-------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ ---------------------------------------------------------00-------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ -----------------------------------------------------------------00------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ -----------1---------------------------1000----0--1-----1----------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------------0----------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ---------------------------------------------------------------0---0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ --------------------------------------------1-----------------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ ---------------------------------------------------0----------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ -----------------------------------------------------1--------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ -------------------------------------------------------0------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ ---------------------------------------------------------------0----0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ --------------------------------------------------0------------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~ ---------------------------------------------1--1--------------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ ----------------------------------------------------------------0----0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~ -------------------------------------------------------------------0-0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ --------------------------------------------------1-------------------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ ------------------------------------------------------0---------------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ -----------------------------------------------------------0----------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ ----------------------------------------------------------------0-----0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ --------------0--------------------------------------------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 -----0-------------------------------------------------0---------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 -------------------------------------------0----------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~ -----------1-----------------------------------1--1----------------1-----0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +.i 75 +.o 124 +.ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q FPU_CS.Q E.Q VMA.Q cpu_est_0_.Q cpu_est_1_.Q AS_000.Q inst_AS_030_000_SYNC.Q IPL_030_0_.Q inst_DTACK_SYNC.Q inst_VPA_D.Q IPL_030_1_.Q inst_VPA_SYNC.Q inst_CLK_000_D0.Q IPL_030_2_.Q inst_CLK_000_D1.Q inst_CLK_000_D2.Q inst_CLK_000_D5.Q inst_CLK_OUT_PRE.Q SM_AMIGA_6_.Q SM_AMIGA_5_.Q cpu_est_2_.Q CLK_REF_1_.Q UDS_000.Q LDS_000.Q DSACK_1_.Q SM_AMIGA_7_.Q inst_CLK_000_D3.Q SM_AMIGA_4_.Q inst_CLK_000_D4.Q CLK_CNT_0_.Q CLK_CNT_1_.Q SM_AMIGA_3_.Q SM_AMIGA_1_.Q SM_AMIGA_2_.Q AMIGA_BUS_ENABLE.Q SM_AMIGA_0_.Q BG_000.Q DSACK_1_.PIN DTACK.PIN +.ob BERR AVEC AVEC_EXP AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN IPL_030_0_.C IPL_030_0_.AP IPL_030_1_.C IPL_030_1_.AP IPL_030_2_.C IPL_030_2_.AP SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.C SM_AMIGA_0_.AR CLK_CNT_0_.C CLK_CNT_1_.C cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C E.C UDS_000.C UDS_000.AP LDS_000.C LDS_000.AP VMA.C VMA.AP BG_000.C BG_000.AP inst_CLK_OUT_PRE.C BGACK_030.C BGACK_030.AP AS_000.C AS_000.AP inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_DTACK_SYNC.C inst_DTACK_SYNC.AP FPU_CS.C FPU_CS.AP DSACK_1_.C DSACK_1_.AP inst_VPA_SYNC.C inst_VPA_SYNC.AP AMIGA_BUS_ENABLE.C inst_CLK_000_D5.C DTACK.C DTACK.AP CLK_EXP.C inst_CLK_000_D4.C inst_CLK_000_D2.C inst_CLK_000_D3.C inst_VPA_D.C inst_CLK_000_D0.C RESET.C inst_CLK_000_D1.C CLK_REF_1_.LH CLK_REF_1_.AR DSACK_0_ DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_DIV_OUT.C CLK_DIV_OUT.D BGACK_030.D FPU_CS.D E.T VMA.T cpu_est_0_.D CLK_EXP.D cpu_est_1_.T AS_000.D inst_AS_030_000_SYNC.D IPL_030_0_.D inst_DTACK_SYNC.D inst_VPA_D.D IPL_030_1_.D inst_VPA_SYNC.D inst_CLK_000_D0.D IPL_030_2_.D inst_CLK_000_D1.D inst_CLK_000_D2.D inst_CLK_000_D5.D inst_CLK_OUT_PRE.D SM_AMIGA_6_.D SM_AMIGA_5_.D cpu_est_2_.D CLK_REF_1_.D UDS_000.D LDS_000.D DSACK_1_.D SM_AMIGA_7_.D inst_CLK_000_D3.D SM_AMIGA_4_.D inst_CLK_000_D4.D RESET.D DTACK.D CLK_CNT_0_.D CLK_CNT_1_.D SM_AMIGA_3_.D SM_AMIGA_1_.D SM_AMIGA_2_.D AMIGA_BUS_ENABLE.D SM_AMIGA_0_.D BG_000.D +.p 311 +--------------------------------------------------------------------------- ~1~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1---------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----11--------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~ +------1-------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------1------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +----0----0----------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +------1--0----------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +----------1---------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1--------------------------------------------------------------- ~~~~~~1~1~1~1~1~1~1~1~1~1~1~1111111~1~1~1~11~1~1~1~1~1~1~111~11111111~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------1-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~ +-------------0------------------------------------------------------------- ~~~~~~~1~1~1~1~1~1~1~1~1~1~1~~~~~~~1~1~1~1~~1~1~1~1~1~1~1~~~1~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------0------------------------------------------------------------ ~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-0--------------0000000---------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------1111------------------------------------------------ ~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------1--------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~111~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------1--------------------------1--------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------0--------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---0--------------------------------1-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------0---------------------------1-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------0--------------------------1-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------1--------1-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------1-------1-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------0------1-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------1-----1-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------0-1-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------0-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1--------------------------------0------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1---------------------------------1------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1----------------------------------1----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1-----------------------------------1---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------1--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~ +------0-----------------------------------1-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------0--------------------------------1-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1----1------------------0010---1-------1-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1----------------------------------------1----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1----------------------------------------0----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------10----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------0---------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1--------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------1-------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------1------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------1-1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~ +----1-------------------------------------------0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------1--------0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------1----0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------1---0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------1-0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------10-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------01------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------1----------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------1------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------1---1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------11------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +--1---------------------------------------------1-0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +--------1---------------------------------------1-0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------1---------------1-0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------1--------------1-0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------1-1--------1-0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ +---------------------------------------0--------1-0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------00-------1-0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ +-------------------------------------1-00-------1-0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +----1-----------------------------------------------1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +-----------------------------------------------------1--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------0-----------------------------------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------0------1----------------------------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +------------------------------------------------1-----1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ +------0-----------------------------------------0-----1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +----1--------1----------------------------------------0-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +-----0--------1----------------1-----------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~ +0----0--------11---------------0-----------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~ +------------------------------------------------1------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ +------------------------------------------------0------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +----1--------------------------------------------------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1---------1----------------------------------------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~ +-----------------------------------------1-------------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------1---------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ +-------------------------------------00011------1-------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------0-------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ +-------------------------------------0110----0--0-------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------1-----1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ +-------------------------------------0-1--------1-0-----1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------1-11-------1-0-----1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1---------------------------------------------------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------1--------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------1-11-------1-0-----0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------0-11-------1-0-----0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------0--0-------1-0-----0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------0-00-------1-0-----0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----1----------------------------------------------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~ +--------------1----------------------------------------0--1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~ +-----1-----------------------------------------------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~ +--------------1----------------------------------------0---1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~ +----------------------------------------------------1-------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +------------------------------------------1------------------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +---------------------------------------------------1---------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +---------0---------------------------------------------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +------------------------------------------1------------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------1-----------------------------------------0-----1------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------------------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~ +------------------------------------------0--------0---------11------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------------------10------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +-----0--------0----------------1-------------------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~ +0----0--------01---------------0-------------------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~ +------------------------------------------------1--------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~ +------------------------------------------------0--------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +----1---------0------------------------------------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~ +--------------0-------------------------------------------1----0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~ +--------------0--------------------------------------------1---0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~ +----------------------------------------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +----1-----------------------------------------------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +------------------------------------------------------------1---0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +-----------------------------------------------------1-----------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------1---0--------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------0---1-------01-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------------0-------01-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~ +-----------------------------------------------------1---1--------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------------------10-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ +---------------------------------------------------------1-------00-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~ +-----------------------------------------------------0---0-------00-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------1--1-------------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~ +------------------------------------------------1------------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~ +--------------------------------------------0---0------------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ +-----------------------------------------------00------------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ +----1--------------------------------------------------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------1----------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------1-------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------1-------------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ +------------------------------------------------0---1---------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +----------------------------------------------------0-----------1---1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ +------------------------------------------------0---------------0---1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +----1---------------------------------------------------------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +------------------------------------------------------------1-------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +------------------------------------------------1--------------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ +------------------------------------------------0--------------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ +-------------0--------------------------------------------------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +------------------------------------------------------0---------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +-----------------------------------------0-----------------------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +-----------------------------------------1------1----------------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +------------------------------------------------0----------------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +---------1--------------------------------------------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +-------------------------------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~ +----1---------------------------------------------------------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------1-----------------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------------------------------- 0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ +-1------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------0-------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------0------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------0---------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------0--------------------------------------------------------------- ~~~~~~0~0~0~0~0~0~0~0~0~0~0~0000000~0~0~0~00~0~0~0~0~0~0~000~00000000~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------0-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1------------------------------------------------------------- ~~~~~~~0~0~0~0~0~0~0~0~0~0~0~~~~~~~0~0~0~0~~0~0~0~0~0~0~0~~~0~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------0------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~ +--------------1------------------------------------------------------------ ~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------1---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------1--------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------1-------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------1------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------1------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------1----------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------1---------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------0--------------------------------------------------- ~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------0-------------------------------------------------- ~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------0------------------------------------------------- ~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------0------------------------------------------------ ~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---10---11-----------------0010---1---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------1--------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------0--------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~000~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------1-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-------------------------------0-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------1------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------01----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------01---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------10---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------1-10---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------00---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0------------------------------------0--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0---------------------------------------0------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0------------------------------------------0--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~0~~~ +--------------------------------------1---------1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------1------1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ +-----------------------------------------0------1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~0~~~~~~~~~0~~~~0~~~~~~~~~~~~~~~~~~~ +-----------------------------------0------------0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------0--------0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------1-------0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------0----0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------0---0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +---------------------------------------------1--0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------0-0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------00-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +------------------------------------------------00------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------0--------------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------0----------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------0------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------0---1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------01------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~ +--0---------------------------------------------1-0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------0---------------1-0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------0--------------1-0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------1--------1-0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------0-10-------1-0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ +---------------------------------------------------0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ +----0-1-----------------------------------0---------1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------0---1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +-----------------------------------------------------0--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------1------1----------------------------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ +----0-------------------------------------0---------1-0-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +1----0--------1----------------------------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ +-----0--------10---------------------------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ +-----0--------1----------------1-----------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ +-----0--------1----------------0-----------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ +------------------------------------------------------00------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ +-------------------------------------0------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------0----------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------0-0----------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------1--1---------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------1------------------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------0--1---------------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ +---------------------------------------01---------------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ +------------------------------------------------0-------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ +--------------------------------------------------1-----0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ +----01----------------------------------------------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ +----0---------1----------------------------------------0--0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ +----01-----------------------------------------------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ +----0---------1----------------------------------------0---0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ +----0-------------------------------------------------------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ +----1-00-0---------------------------------------------------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 +------------------------------------------1------------------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------1---------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ +---00-1--1------------------------------------------1--------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1-01------------------------------------------1--------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1-----------------1------------------------1--------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1------------------1-----------------------1--------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1-------------------0----------------------1--------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1--------------------1---------------------1--------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1------------------------0-----------------1--------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------0------------------------------------------------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------1------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------0------1------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +------1-----------------------------------------0------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +------------------------------------------------------0------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------0-----0------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +-----------------------------------------00-----1--0----------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +------1-----------------------------------0-----0--0----------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +------------------------------------------0-----0--0--0-------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +--------------------------------------------------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ +-------------------------------------------------------------10------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ +1----0--------0------------------------------------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ +-----0--------00-----------------------------------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ +-----0--------0----------------1-------------------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ +-----0--------0----------------0-------------------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ +-------------------------------------------------------0-------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~ +----0---------0-------------------------------------------0----0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ +----0---------0--------------------------------------------0---0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ +----------------------------------------------------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ +----0-1-----------------------------------0---------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------0---------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +----0-------------------------------------0-----------0---------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---00-1--1---------------------------------------------------1--0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1-01---------------------------------------------------1--0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1-----------------1---------------------------------1--0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1------------------1--------------------------------1--0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1-------------------0-------------------------------1--0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1--------------------1------------------------------1--0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1------------------------0--------------------------1--0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ +-----------------------------------------------------0-----------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------------1--------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~00~~~~~~ +-----------------------------------------------------0---0--------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------------------11-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +-----------------------------------------------------1---1-------01-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------0---1--------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------------0--------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ +-----------------------------------------------------------------00-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +-----------------------------------------------------1---0-------00-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------1000----0--1-------1----------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------0------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +---------------------------------------------------------------0---0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +----------------------------------------------------0-----------1---1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ +----0-1-----------------------------------0-------------------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------0-------------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +----0-------------------------------------0-----------0-------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---00-1--1---------------------------------------------------1------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1-01---------------------------------------------------1------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1-----------------1---------------------------------1------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1------------------1--------------------------------1------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1-------------------0-------------------------------1------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1--------------------1------------------------------1------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1------------------------0--------------------------1------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------1--1---------------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ +-------------------------------------------------------------------0-0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ +--------------------------------------------------------------------00----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +-------------0--------------------------------------------------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ +----0-------------------------------------------------0---------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ +------------------------------------------------1----------------------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ +------------------------------------------------1------------0---------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +------------------------------------------0-----1--0----------1--------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +----------------------------------------------------0-----------1------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ +--------------------------------------------------------------------0--0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ +-------0-1--------------------------------------------------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 +-----------------------------------------0-------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~ +---------------------------------------------1--1------------------1------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ .end diff --git a/Logic/68030_tk.tt3 b/Logic/68030_tk.tt3 index 1b9eb18..5fa70f8 100644 --- a/Logic/68030_tk.tt3 +++ b/Logic/68030_tk.tt3 @@ -1,320 +1,323 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Thu May 22 14:56:10 2014 +#$ DATE Sat May 24 11:44:09 2014 #$ MODULE 68030_tk -#$ PINS 59 SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 nEXP_SPACE BERR SIZE_0_ BG_030 A_30_ A_29_ A_28_ BGACK_000 A_27_ CLK_030 A_26_ CLK_000 A_25_ CLK_OSZI A_24_ CLK_DIV_OUT A_23_ A_22_ A_21_ A_20_ AVEC A_19_ AVEC_EXP A_18_ A_17_ VPA A_16_ RST RW AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN A_0_ IPL_1_ IPL_0_ DSACK_0_ FC_0_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 BG_000 BGACK_030 CLK_EXP FPU_CS DTACK E VMA RESET AMIGA_BUS_ENABLE IPL_030_1_ IPL_030_0_ -#$ NODES 23 cpu_est_0_ cpu_est_1_ inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2 inst_CLK_OUT_PRE SM_AMIGA_6_ cpu_est_2_ CLK_REF_0_ CLK_REF_1_ SM_AMIGA_7_ SM_AMIGA_4_ SM_AMIGA_1_ CLK_CNT_0_ CLK_CNT_1_ SM_AMIGA_3_ SM_AMIGA_5_ SM_AMIGA_2_ SM_AMIGA_0_ +#$ PINS 59 SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 SIZE_0_ CLK_OSZI A_30_ CLK_DIV_OUT A_29_ A_28_ A_27_ A_26_ AVEC A_25_ AVEC_EXP A_24_ A_23_ VPA A_22_ A_21_ RST A_20_ A_19_ RW A_18_ A_17_ AMIGA_BUS_DATA_DIR A_16_ AMIGA_BUS_ENABLE_LOW CIIN A_0_ IPL_1_ IPL_0_ DSACK_0_ FC_0_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 BG_000 BGACK_030 CLK_EXP FPU_CS DTACK E VMA RESET AMIGA_BUS_ENABLE IPL_030_1_ IPL_030_0_ +#$ NODES 25 cpu_est_0_ cpu_est_1_ inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2 inst_CLK_000_D5 inst_CLK_OUT_PRE SM_AMIGA_6_ SM_AMIGA_5_ cpu_est_2_ CLK_REF_1_ SM_AMIGA_7_ inst_CLK_000_D3 SM_AMIGA_4_ inst_CLK_000_D4 CLK_CNT_0_ CLK_CNT_1_ SM_AMIGA_3_ SM_AMIGA_1_ SM_AMIGA_2_ SM_AMIGA_0_ .type fr -.i 73 -.o 121 -.ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_ BG_000.Q BGACK_030.Q FPU_CS.Q E.Q VMA.Q cpu_est_0_.Q cpu_est_1_.Q AS_000.Q inst_AS_030_000_SYNC.Q inst_DTACK_SYNC.Q IPL_030_0_.Q inst_VPA_D.Q inst_VPA_SYNC.Q IPL_030_1_.Q inst_CLK_000_D0.Q inst_CLK_000_D1.Q IPL_030_2_.Q inst_CLK_000_D2.Q inst_CLK_OUT_PRE.Q SM_AMIGA_6_.Q cpu_est_2_.Q CLK_REF_0_.Q CLK_REF_1_.Q SM_AMIGA_7_.Q UDS_000.Q LDS_000.Q DSACK_1_.Q SM_AMIGA_4_.Q SM_AMIGA_1_.Q CLK_CNT_0_.Q CLK_CNT_1_.Q SM_AMIGA_3_.Q SM_AMIGA_5_.Q SM_AMIGA_2_.Q SM_AMIGA_0_.Q AMIGA_BUS_ENABLE.Q DSACK_1_.PIN DTACK.PIN -.ob BERR AVEC AVEC_EXP AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.C SM_AMIGA_0_.AR cpu_est_1_.C cpu_est_2_.C E.C IPL_030_0_.C IPL_030_0_.AP IPL_030_1_.C IPL_030_1_.AP IPL_030_2_.C IPL_030_2_.AP SM_AMIGA_7_.C SM_AMIGA_7_.AP VMA.C VMA.AP BGACK_030.C BGACK_030.AP inst_CLK_OUT_PRE.C CLK_CNT_0_.C CLK_CNT_1_.C cpu_est_0_.C inst_VPA_SYNC.C inst_VPA_SYNC.AP FPU_CS.C FPU_CS.AP inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP AS_000.C AS_000.AP AMIGA_BUS_ENABLE.C BG_000.C BG_000.AP DSACK_1_.C DSACK_1_.AP UDS_000.C UDS_000.AP LDS_000.C LDS_000.AP inst_DTACK_SYNC.C inst_DTACK_SYNC.AP CLK_EXP.C DTACK.C DTACK.AP inst_CLK_000_D2.C inst_VPA_D.C inst_CLK_000_D0.C RESET.C inst_CLK_000_D1.C CLK_REF_0_.LH CLK_REF_0_.AP CLK_REF_1_.LH CLK_REF_1_.AR DSACK_0_ DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_DIV_OUT.C CLK_DIV_OUT.D BG_000.D BGACK_030.D FPU_CS.D E.T VMA.T cpu_est_0_.D cpu_est_1_.T CLK_EXP.D AS_000.D inst_AS_030_000_SYNC.D inst_DTACK_SYNC.D IPL_030_0_.D inst_VPA_D.D inst_VPA_SYNC.D IPL_030_1_.D inst_CLK_000_D0.D inst_CLK_000_D1.D IPL_030_2_.D inst_CLK_000_D2.D inst_CLK_OUT_PRE.T SM_AMIGA_6_.D cpu_est_2_.D CLK_REF_0_.D CLK_REF_1_.D SM_AMIGA_7_.D UDS_000.D LDS_000.D DSACK_1_.D SM_AMIGA_4_.D SM_AMIGA_1_.D DTACK.D CLK_CNT_0_.D CLK_CNT_1_.D SM_AMIGA_3_.D RESET.D SM_AMIGA_5_.D SM_AMIGA_2_.D SM_AMIGA_0_.D AMIGA_BUS_ENABLE.D -.p 308 -------------------------------------------------------------------------- ~1~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----1-------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----11------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~ -------1------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------1----------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----0-----1--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------0--1--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------01--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0----0--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------1--0--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------1-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ -----1-----0-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~1~~~~~~~~~~~~~~~~~~~~~~~~~ ------------1------------------------------------------------------------- ~~~~~~1~1~1~1~1~1~1~1111~1~1~1~1~1~11111~1~1~1~11~1~1~1~1~11~11111~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------1------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------1----------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ --------------0----------------------------------------------------------- ~~~~~~~1~1~1~1~1~1~1~~~~1~1~1~1~1~1~~~~~1~1~1~1~~1~1~1~1~1~~1~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------0---------------------------------------------------------- ~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --0--------------0000000-------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------1111---------------------------------------------- ~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------1-----------------1--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------1------------------1-------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------1-------------------0------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------1--------------------1------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----1----11-----------------0010---1-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------1------------------------0-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------1-------------------------1------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------1------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~111~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------1---------------------------1------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------0------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------0---------------------------1----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------0----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----1---------------------------------0---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ -----1----------------------------------1--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ -----1-----------------------------------1-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ -----1------------------------------------1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~ -----1--------------------------------------1----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------0---------------------------------1----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----1---------1----------------------------1----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~ -------------------------------------------11----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------0---------------------------------1---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----1-----------------------------------------1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ -----1-----------------------------------------0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------1-0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------0------------------------------------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------0--------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------1-------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------1------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------1-----1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------11------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ -----1--------------------------------------------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ -----1--------------------------------------------0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~1~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------1--------0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------1----0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------1---0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------------1-0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------10----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~ -----------------------------------------1---------1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------1----1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------1-1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~ -----1---------------------------------------------0---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----1---------1-----------------------------------0---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~ -------------------------------------------1-------0---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---1----------------------------------------------10---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ ---------1----------------------------------------10---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------1----------------10---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------1---------------10---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------1-1--------10---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~ -----------------------------------------0--------10---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------00-------10---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~ ---------------------------------------1-00-------10---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------------0-1--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------11--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ -----1-----------------------------------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----1---------1-------------------------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~ -------------------------------------------1---------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----1------------------------------------------------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ -------0------1----------------------------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 --------------------------------------------1----------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ ---------------------------------------------------0---1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ -----------------------------------------------------1-1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ --------------------------------------------0------1-0-1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ ------0--------1----------------1-----------0------1-0-1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ -0----0--------11---------------0-----------0------1-0-1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ -----1-------------------------------------------------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----1--------1----------------------------------------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 -----1---------1---------------------------------------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~ -------------------------------------------1-----------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------1-------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~ ---------------------------------------00011------1-----1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------------0-----1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~ ---------------------------------------0110----0--0-----1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------1----1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~ ---------------------------------------0-1--------10----1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------1-11-------10----1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----1--------------------------------------------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------------1-------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------1-11-------10----0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------0-11-------10----0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------0--0-------10----0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------0-00-------10----0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------------1--------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ --------------------------------------------------0--------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ ----------0--------------------------------------------0---0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------1-----------------------------------------------------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ ---------------1----------------------------1---------------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ ---------------1-----------------------------------0--------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ ---------------1-------------------------------------1------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ ---------------1---------------------------------------0----1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ ------1------------------------------------------------------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ ---------------1----------------------------1----------------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ ---------------1-----------------------------------0---------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ ---------------1-------------------------------------1-------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ ---------------1---------------------------------------0-----1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ --------------------------------------------------1-----------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ ------------------------------------------------------0-------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ ------0--------0----------------1------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ -0----0--------01---------------0------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ --------------------------------------------------1------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~ --------------------------------------------------0------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~ -----1---------0-----------------------------------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~ ---------------0--------------------------------------------1--0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ ---------------0---------------------------------------------1-0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ --------------------------------------------------1-------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~ --------------------------------------------------0---1---------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ -----1----------------------------------------------------------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ --------------------------------------------------------------1-0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ ---------------------------------------------------------1-------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~ ---------------------------------------------------------11------11------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------------1-------01------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ ---------------------------------------------------------01------01------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------------0------01------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~ ---------------------------------------------------------0-------10------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ ----------------------------------------------------------1------10------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ ---------------------------------------------------------10------10------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------------1------00------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~ ---------------------------------------------------------00------00------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ ---------------------------------------------1--1------------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~ --------------------------------------------------1----------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~ ---------------------------------------------0----0----------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ ------------------------------------------------0-0----------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ -----1-------------------------------------------------------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~1~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------1---------------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------------1------------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------------1-----------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ --------------------------------------------------0-----------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~ --------------------------------------------------1------------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~ --------------------------------------------------0------------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ ------------------------------------------------------0---------1----0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~ -------------------------------------------0--------------------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ -------------------------------------------1------1-------------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ --------------------------------------------------0-------------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ --------------0--------------------------------------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 -------------------------------------------------------0---------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 ------------------------------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~ -----1-------------------------------------------------------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------1---------------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------------------------------- 0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~00~~~~~~~~~~~~~~~ --1----------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------0------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------0---------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----00-1--1--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1-01--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------0-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~ ------------0------------------------------------------------------------- ~~~~~~0~0~0~0~0~0~0~0000~0~0~0~0~0~00000~0~0~0~00~0~0~0~0~00~00000~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------0------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------1----------------------------------------------------------- ~~~~~~~0~0~0~0~0~0~0~~~~0~0~0~0~0~0~~~~~0~0~0~0~~0~0~0~0~0~~0~~~~~~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------0----------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ ---------------1---------------------------------------------------------- ~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------1-------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------1------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------1------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------1----------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------1---------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------1--------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------1-------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------0------------------------------------------------- ~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------0------------------------------------------------ ~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------0----------------------------------------------- ~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------0---------------------------------------------- ~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1-----------------1--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1------------------1-------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1-------------------0------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1--------------------1------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----10---11-----------------0010---1-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1------------------------0-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------0-1-------------------------0------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------1------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------0------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~000~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------1----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0----0---------------------------0----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------1---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------01-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------01------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------10------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------1-10------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------00------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-------------------------------------0------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0----0---------------------------------0----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0---------------------------------------0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0------------------------------------------0------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~0~~ ----------------------------------------1---------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------1------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ -------------------------------------------0------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------------0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~0~~~~~~~~~0~~~~~~~0~~~~~~~~~~~~~~ -------------------------------------0------------0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------0--------0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------1-------0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------1-----0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ ---------------------------------------------0----0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ----------------------------------------------0---0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------1--0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------------0-0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ -------------------------------------------------00----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------0-------------1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------0---------1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------0----1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------0-1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------0---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ ---0----------------------------------------------10---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ ---------------------------------0----------------10---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------0---------------10---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------1--------10---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------0-10-------10---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ --------------------------------------------------00---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ --------------------------------------------------0-0--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------10--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------------0--1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ --------------------------------------------0-----11-0-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ --------------------------------------------------0---1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~ ------------------------------------------------------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----1-00-0--------------------------------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------1------1----------------------------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 --------------------------------------------0------1-0-1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -1----0--------1----------------------------0------1-0-1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ ------0--------10---------------------------0------1-0-1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ ------0--------1----------------1-----------0------1-0-1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ ------0--------1----------------0-----------0------1-0-1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ --------------------------------------------------1----0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ --------------------------------------------------0----0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ ---------------------------------------0----------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------0--------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------0-0--------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------1--1-------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------1----------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------0--1-------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ -----------------------------------------01-------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ --------------------------------------------------0-----0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ ---------------------------------------------------1----0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ -----1-00-0------------------------------------------------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------0---------------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ --------------------------------------------0------1-0-----0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ -------------------------------------------------------0---0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ -----01-----------------------------------------------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ -----0---------1----------------------------1---------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ -----0---------1-----------------------------------0--------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ -----0---------1-------------------------------------1------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ -----0---------1---------------------------------------0----0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ -----01------------------------------------------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ -----0---------1----------------------------1----------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ -----0---------1-----------------------------------0---------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ -----0---------1-------------------------------------1-------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ -----0---------1---------------------------------------0-----0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ -----0--------------------------------------------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~ -1----0--------0-----------------------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ ------0--------00----------------------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ ------0--------0----------------1------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ ------0--------0----------------0------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ -----0---------0--------------------------------------------0--0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ -----0---------0---------------------------------------------0-0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ --------------------------------------------------0---1---------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~ -----------------------------------------------------------------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ ---------------------------------------------------------0-------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------------1-------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------------01------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ ---------------------------------------------------------01-------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ ----------------------------------------------------------0-------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ -----------------------------------------------------------------11------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ ----------------------------------------------------------1-------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------------10-------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ ---------------------------------------------------------00-------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ -----------------------------------------------------------------00------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ -----------1---------------------------1000----0--1-----1----------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------------0----------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ---------------------------------------------------------------0---0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ --------------------------------------------1-----------------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ ---------------------------------------------------0----------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ -----------------------------------------------------1--------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ -------------------------------------------------------0------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ ---------------------------------------------------------------0----0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ --------------------------------------------------0------------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~ ---------------------------------------------1--1--------------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ ----------------------------------------------------------------0----0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~ -------------------------------------------------------------------0-0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ --------------------------------------------------1-------------------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ ------------------------------------------------------0---------------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ -----------------------------------------------------------0----------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ ----------------------------------------------------------------0-----0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ --------------0--------------------------------------------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 -----0-------------------------------------------------0---------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 -------------------------------------------0----------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~ -----------1-----------------------------------1--1----------------1-----0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +.i 75 +.o 124 +.ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q FPU_CS.Q E.Q VMA.Q cpu_est_0_.Q cpu_est_1_.Q AS_000.Q inst_AS_030_000_SYNC.Q IPL_030_0_.Q inst_DTACK_SYNC.Q inst_VPA_D.Q IPL_030_1_.Q inst_VPA_SYNC.Q inst_CLK_000_D0.Q IPL_030_2_.Q inst_CLK_000_D1.Q inst_CLK_000_D2.Q inst_CLK_000_D5.Q inst_CLK_OUT_PRE.Q SM_AMIGA_6_.Q SM_AMIGA_5_.Q cpu_est_2_.Q CLK_REF_1_.Q UDS_000.Q LDS_000.Q DSACK_1_.Q SM_AMIGA_7_.Q inst_CLK_000_D3.Q SM_AMIGA_4_.Q inst_CLK_000_D4.Q CLK_CNT_0_.Q CLK_CNT_1_.Q SM_AMIGA_3_.Q SM_AMIGA_1_.Q SM_AMIGA_2_.Q AMIGA_BUS_ENABLE.Q SM_AMIGA_0_.Q BG_000.Q DSACK_1_.PIN DTACK.PIN +.ob BERR AVEC AVEC_EXP AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN IPL_030_0_.C IPL_030_0_.AP IPL_030_1_.C IPL_030_1_.AP IPL_030_2_.C IPL_030_2_.AP SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.C SM_AMIGA_0_.AR CLK_CNT_0_.C CLK_CNT_1_.C cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C E.C UDS_000.C UDS_000.AP LDS_000.C LDS_000.AP VMA.C VMA.AP BG_000.C BG_000.AP inst_CLK_OUT_PRE.C BGACK_030.C BGACK_030.AP AS_000.C AS_000.AP inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_DTACK_SYNC.C inst_DTACK_SYNC.AP FPU_CS.C FPU_CS.AP DSACK_1_.C DSACK_1_.AP inst_VPA_SYNC.C inst_VPA_SYNC.AP AMIGA_BUS_ENABLE.C inst_CLK_000_D5.C DTACK.C DTACK.AP CLK_EXP.C inst_CLK_000_D4.C inst_CLK_000_D2.C inst_CLK_000_D3.C inst_VPA_D.C inst_CLK_000_D0.C RESET.C inst_CLK_000_D1.C CLK_REF_1_.LH CLK_REF_1_.AR DSACK_0_ DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_DIV_OUT.C CLK_DIV_OUT.D BGACK_030.D FPU_CS.D E.T VMA.T cpu_est_0_.D CLK_EXP.D cpu_est_1_.T AS_000.D inst_AS_030_000_SYNC.D IPL_030_0_.D inst_DTACK_SYNC.D inst_VPA_D.D IPL_030_1_.D inst_VPA_SYNC.D inst_CLK_000_D0.D IPL_030_2_.D inst_CLK_000_D1.D inst_CLK_000_D2.D inst_CLK_000_D5.D inst_CLK_OUT_PRE.D SM_AMIGA_6_.D SM_AMIGA_5_.D cpu_est_2_.D CLK_REF_1_.D UDS_000.D LDS_000.D DSACK_1_.D SM_AMIGA_7_.D inst_CLK_000_D3.D SM_AMIGA_4_.D inst_CLK_000_D4.D RESET.D DTACK.D CLK_CNT_0_.D CLK_CNT_1_.D SM_AMIGA_3_.D SM_AMIGA_1_.D SM_AMIGA_2_.D AMIGA_BUS_ENABLE.D SM_AMIGA_0_.D BG_000.D +.p 311 +--------------------------------------------------------------------------- ~1~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1---------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----11--------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~ +------1-------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------1------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +----0----0----------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +------1--0----------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +----------1---------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1--------------------------------------------------------------- ~~~~~~1~1~1~1~1~1~1~1~1~1~1~1111111~1~1~1~11~1~1~1~1~1~1~111~11111111~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------1-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~ +-------------0------------------------------------------------------------- ~~~~~~~1~1~1~1~1~1~1~1~1~1~1~~~~~~~1~1~1~1~~1~1~1~1~1~1~1~~~1~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------0------------------------------------------------------------ ~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-0--------------0000000---------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------1111------------------------------------------------ ~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------1--------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~111~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------1--------------------------1--------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------0--------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---0--------------------------------1-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------0---------------------------1-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------0--------------------------1-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------1--------1-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------1-------1-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------0------1-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------1-----1-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------0-1-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------0-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1--------------------------------0------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1---------------------------------1------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1----------------------------------1----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1-----------------------------------1---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------1--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~ +------0-----------------------------------1-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------0--------------------------------1-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1----1------------------0010---1-------1-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1----------------------------------------1----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1----------------------------------------0----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------10----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------0---------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1--------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------1-------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------1------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------1-1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~ +----1-------------------------------------------0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------1--------0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------1----0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------1---0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------1-0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------10-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------01------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------1----------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------1------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------1---1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------11------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +--1---------------------------------------------1-0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +--------1---------------------------------------1-0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------1---------------1-0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------1--------------1-0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------1-1--------1-0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ +---------------------------------------0--------1-0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------00-------1-0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ +-------------------------------------1-00-------1-0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +----1-----------------------------------------------1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +-----------------------------------------------------1--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------0-----------------------------------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------0------1----------------------------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +------------------------------------------------1-----1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ +------0-----------------------------------------0-----1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +----1--------1----------------------------------------0-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +-----0--------1----------------1-----------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~ +0----0--------11---------------0-----------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~ +------------------------------------------------1------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ +------------------------------------------------0------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +----1--------------------------------------------------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1---------1----------------------------------------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~ +-----------------------------------------1-------------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------1---------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ +-------------------------------------00011------1-------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------0-------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ +-------------------------------------0110----0--0-------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------1-----1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ +-------------------------------------0-1--------1-0-----1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------1-11-------1-0-----1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1---------------------------------------------------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------1--------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------1-11-------1-0-----0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------0-11-------1-0-----0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------0--0-------1-0-----0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------0-00-------1-0-----0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----1----------------------------------------------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~ +--------------1----------------------------------------0--1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~ +-----1-----------------------------------------------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~ +--------------1----------------------------------------0---1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~ +----------------------------------------------------1-------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +------------------------------------------1------------------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +---------------------------------------------------1---------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +---------0---------------------------------------------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +------------------------------------------1------------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------1-----------------------------------------0-----1------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------------------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~ +------------------------------------------0--------0---------11------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------------------10------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +-----0--------0----------------1-------------------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~ +0----0--------01---------------0-------------------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~ +------------------------------------------------1--------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~ +------------------------------------------------0--------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +----1---------0------------------------------------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~ +--------------0-------------------------------------------1----0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~ +--------------0--------------------------------------------1---0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~ +----------------------------------------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +----1-----------------------------------------------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +------------------------------------------------------------1---0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +-----------------------------------------------------1-----------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------1---0--------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------0---1-------01-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------------0-------01-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~ +-----------------------------------------------------1---1--------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------------------10-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ +---------------------------------------------------------1-------00-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~ +-----------------------------------------------------0---0-------00-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------1--1-------------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~ +------------------------------------------------1------------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~ +--------------------------------------------0---0------------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ +-----------------------------------------------00------------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ +----1--------------------------------------------------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------1----------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------1-------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------1-------------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ +------------------------------------------------0---1---------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +----------------------------------------------------0-----------1---1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ +------------------------------------------------0---------------0---1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +----1---------------------------------------------------------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +------------------------------------------------------------1-------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +------------------------------------------------1--------------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ +------------------------------------------------0--------------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ +-------------0--------------------------------------------------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +------------------------------------------------------0---------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +-----------------------------------------0-----------------------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +-----------------------------------------1------1----------------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +------------------------------------------------0----------------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +---------1--------------------------------------------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +-------------------------------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~ +----1---------------------------------------------------------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------1-----------------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------------------------------- 0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ +-1------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------0-------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------0------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------0---------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------0--------------------------------------------------------------- ~~~~~~0~0~0~0~0~0~0~0~0~0~0~0000000~0~0~0~00~0~0~0~0~0~0~000~00000000~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------0-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1------------------------------------------------------------- ~~~~~~~0~0~0~0~0~0~0~0~0~0~0~~~~~~~0~0~0~0~~0~0~0~0~0~0~0~~~0~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------0------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~ +--------------1------------------------------------------------------------ ~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------1---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------1--------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------1-------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------1------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------1------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------1----------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------1---------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------0--------------------------------------------------- ~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------0-------------------------------------------------- ~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------0------------------------------------------------- ~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------0------------------------------------------------ ~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---10---11-----------------0010---1---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------1--------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------0--------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~000~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------1-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-------------------------------0-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------1------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------01----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------01---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------10---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------1-10---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------00---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0------------------------------------0--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0---------------------------------------0------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0------------------------------------------0--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~0~~~ +--------------------------------------1---------1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------1------1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ +-----------------------------------------0------1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~0~~~~~~~~~0~~~~0~~~~~~~~~~~~~~~~~~~ +-----------------------------------0------------0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------0--------0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------1-------0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------0----0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------0---0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +---------------------------------------------1--0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------0-0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------00-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +------------------------------------------------00------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------0--------------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------0----------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------0------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------0---1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------01------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~ +--0---------------------------------------------1-0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------0---------------1-0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------0--------------1-0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------1--------1-0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------0-10-------1-0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ +---------------------------------------------------0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ +----0-1-----------------------------------0---------1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------0---1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +-----------------------------------------------------0--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------1------1----------------------------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ +----0-------------------------------------0---------1-0-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +1----0--------1----------------------------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ +-----0--------10---------------------------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ +-----0--------1----------------1-----------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ +-----0--------1----------------0-----------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ +------------------------------------------------------00------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ +-------------------------------------0------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------0----------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------0-0----------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------1--1---------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------1------------------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------0--1---------------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ +---------------------------------------01---------------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ +------------------------------------------------0-------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ +--------------------------------------------------1-----0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ +----01----------------------------------------------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ +----0---------1----------------------------------------0--0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ +----01-----------------------------------------------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ +----0---------1----------------------------------------0---0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ +----0-------------------------------------------------------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ +----1-00-0---------------------------------------------------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 +------------------------------------------1------------------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------1---------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ +---00-1--1------------------------------------------1--------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1-01------------------------------------------1--------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1-----------------1------------------------1--------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1------------------1-----------------------1--------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1-------------------0----------------------1--------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1--------------------1---------------------1--------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1------------------------0-----------------1--------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------0------------------------------------------------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------1------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------0------1------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +------1-----------------------------------------0------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +------------------------------------------------------0------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------0-----0------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +-----------------------------------------00-----1--0----------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +------1-----------------------------------0-----0--0----------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +------------------------------------------0-----0--0--0-------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +--------------------------------------------------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ +-------------------------------------------------------------10------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ +1----0--------0------------------------------------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ +-----0--------00-----------------------------------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ +-----0--------0----------------1-------------------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ +-----0--------0----------------0-------------------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ +-------------------------------------------------------0-------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~ +----0---------0-------------------------------------------0----0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ +----0---------0--------------------------------------------0---0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ +----------------------------------------------------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ +----0-1-----------------------------------0---------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------0---------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +----0-------------------------------------0-----------0---------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---00-1--1---------------------------------------------------1--0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1-01---------------------------------------------------1--0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1-----------------1---------------------------------1--0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1------------------1--------------------------------1--0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1-------------------0-------------------------------1--0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1--------------------1------------------------------1--0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1------------------------0--------------------------1--0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ +-----------------------------------------------------0-----------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------------1--------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~00~~~~~~ +-----------------------------------------------------0---0--------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------------------11-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +-----------------------------------------------------1---1-------01-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------0---1--------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------------0--------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ +-----------------------------------------------------------------00-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +-----------------------------------------------------1---0-------00-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------1000----0--1-------1----------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------0------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +---------------------------------------------------------------0---0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +----------------------------------------------------0-----------1---1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ +----0-1-----------------------------------0-------------------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------0-------------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +----0-------------------------------------0-----------0-------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---00-1--1---------------------------------------------------1------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1-01---------------------------------------------------1------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1-----------------1---------------------------------1------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1------------------1--------------------------------1------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1-------------------0-------------------------------1------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1--------------------1------------------------------1------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1------------------------0--------------------------1------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------1--1---------------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ +-------------------------------------------------------------------0-0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ +--------------------------------------------------------------------00----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +-------------0--------------------------------------------------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ +----0-------------------------------------------------0---------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ +------------------------------------------------1----------------------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ +------------------------------------------------1------------0---------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +------------------------------------------0-----1--0----------1--------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +----------------------------------------------------0-----------1------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ +--------------------------------------------------------------------0--0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ +-------0-1--------------------------------------------------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 +-----------------------------------------0-------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~ +---------------------------------------------1--1------------------1------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ .end diff --git a/Logic/68030_tk.tt4 b/Logic/68030_tk.tt4 index 529ccb0..f3204d7 100644 --- a/Logic/68030_tk.tt4 +++ b/Logic/68030_tk.tt4 @@ -1,35 +1,36 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Thu May 22 14:56:10 2014 +#$ DATE Sat May 24 11:44:09 2014 #$ MODULE BUS68030 -#$ PINS 59 SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 nEXP_SPACE BERR SIZE_0_ - BG_030 A_30_ A_29_ A_28_ BGACK_000 A_27_ CLK_030 A_26_ CLK_000 A_25_ CLK_OSZI - A_24_ CLK_DIV_OUT A_23_ A_22_ A_21_ A_20_ AVEC A_19_ AVEC_EXP A_18_ A_17_ VPA - A_16_ RST RW AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN A_0_ IPL_1_ IPL_0_ +#$ PINS 59 SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 nEXP_SPACE BERR BG_030 + BGACK_000 CLK_030 CLK_000 SIZE_0_ CLK_OSZI A_30_ CLK_DIV_OUT A_29_ A_28_ A_27_ + A_26_ AVEC A_25_ AVEC_EXP A_24_ A_23_ VPA A_22_ A_21_ RST A_20_ A_19_ RW A_18_ + A_17_ AMIGA_BUS_DATA_DIR A_16_ AMIGA_BUS_ENABLE_LOW CIIN A_0_ IPL_1_ IPL_0_ DSACK_0_ FC_0_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 BG_000 BGACK_030 CLK_EXP FPU_CS DTACK E VMA RESET AMIGA_BUS_ENABLE IPL_030_1_ IPL_030_0_ -#$ NODES 23 cpu_est_0_ cpu_est_1_ inst_AS_030_000_SYNC inst_DTACK_SYNC +#$ NODES 25 cpu_est_0_ cpu_est_1_ inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2 - inst_CLK_OUT_PRE SM_AMIGA_6_ cpu_est_2_ CLK_REF_0_ CLK_REF_1_ SM_AMIGA_7_ - SM_AMIGA_4_ SM_AMIGA_1_ CLK_CNT_0_ CLK_CNT_1_ SM_AMIGA_3_ SM_AMIGA_5_ - SM_AMIGA_2_ SM_AMIGA_0_ + inst_CLK_000_D5 inst_CLK_OUT_PRE SM_AMIGA_6_ SM_AMIGA_5_ cpu_est_2_ CLK_REF_1_ + SM_AMIGA_7_ inst_CLK_000_D3 SM_AMIGA_4_ inst_CLK_000_D4 CLK_CNT_0_ CLK_CNT_1_ + SM_AMIGA_3_ SM_AMIGA_1_ SM_AMIGA_2_ SM_AMIGA_0_ .type f -.i 73 -.o 122 +.i 75 +.o 126 .ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_ - BG_000.Q BGACK_030.Q FPU_CS.Q E.Q VMA.Q cpu_est_0_.Q cpu_est_1_.Q AS_000.Q - inst_AS_030_000_SYNC.Q inst_DTACK_SYNC.Q IPL_030_0_.Q inst_VPA_D.Q - inst_VPA_SYNC.Q IPL_030_1_.Q inst_CLK_000_D0.Q inst_CLK_000_D1.Q IPL_030_2_.Q - inst_CLK_000_D2.Q inst_CLK_OUT_PRE.Q SM_AMIGA_6_.Q cpu_est_2_.Q CLK_REF_0_.Q - CLK_REF_1_.Q SM_AMIGA_7_.Q UDS_000.Q LDS_000.Q DSACK_1_.Q SM_AMIGA_4_.Q - SM_AMIGA_1_.Q CLK_CNT_0_.Q CLK_CNT_1_.Q SM_AMIGA_3_.Q SM_AMIGA_5_.Q - SM_AMIGA_2_.Q SM_AMIGA_0_.Q AMIGA_BUS_ENABLE.Q DSACK_1_.PIN DTACK.PIN + BGACK_030.Q FPU_CS.Q E.Q VMA.Q cpu_est_0_.Q cpu_est_1_.Q AS_000.Q + inst_AS_030_000_SYNC.Q IPL_030_0_.Q inst_DTACK_SYNC.Q inst_VPA_D.Q IPL_030_1_.Q + inst_VPA_SYNC.Q inst_CLK_000_D0.Q IPL_030_2_.Q inst_CLK_000_D1.Q + inst_CLK_000_D2.Q inst_CLK_000_D5.Q inst_CLK_OUT_PRE.Q SM_AMIGA_6_.Q + SM_AMIGA_5_.Q cpu_est_2_.Q CLK_REF_1_.Q UDS_000.Q LDS_000.Q DSACK_1_.Q + SM_AMIGA_7_.Q inst_CLK_000_D3.Q SM_AMIGA_4_.Q inst_CLK_000_D4.Q CLK_CNT_0_.Q + CLK_CNT_1_.Q SM_AMIGA_3_.Q SM_AMIGA_1_.Q SM_AMIGA_2_.Q AMIGA_BUS_ENABLE.Q + SM_AMIGA_0_.Q BG_000.Q DSACK_1_.PIN DTACK.PIN .ob BERR BERR.OE CLK_DIV_OUT.D CLK_DIV_OUT.C AVEC AVEC_EXP AVEC_EXP.OE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN CIIN.OE DSACK_0_ DSACK_0_.OE IPL_030_2_.D IPL_030_2_.C IPL_030_2_.AP DSACK_1_.D% DSACK_1_.C DSACK_1_.AP - DSACK_1_.OE AS_000.D% AS_000.C AS_000.AP AS_000.OE UDS_000.D% UDS_000.C - UDS_000.AP UDS_000.OE LDS_000.D% LDS_000.C LDS_000.AP LDS_000.OE BG_000.D% + DSACK_1_.OE AS_000.D AS_000.C AS_000.AP AS_000.OE UDS_000.D% UDS_000.C + UDS_000.AP UDS_000.OE LDS_000.D LDS_000.C LDS_000.AP LDS_000.OE BG_000.D% BG_000.C BG_000.AP BGACK_030.D BGACK_030.C BGACK_030.AP CLK_EXP.D CLK_EXP.C FPU_CS.D% FPU_CS.C FPU_CS.AP DTACK.D% DTACK.C DTACK.AP DTACK.OE E.T E.C VMA.T VMA.C VMA.AP RESET.D RESET.C AMIGA_BUS_ENABLE.D% AMIGA_BUS_ENABLE.C IPL_030_1_.D @@ -39,128 +40,126 @@ inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_VPA_D.D inst_VPA_D.C inst_VPA_SYNC.D% inst_VPA_SYNC.C inst_VPA_SYNC.AP inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_D2.D inst_CLK_000_D2.C - inst_CLK_OUT_PRE.T inst_CLK_OUT_PRE.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR - cpu_est_2_.D.X1 cpu_est_2_.D.X2 cpu_est_2_.C CLK_REF_0_.D CLK_REF_0_.LH - CLK_REF_0_.AP CLK_REF_1_.D CLK_REF_1_.LH CLK_REF_1_.AR SM_AMIGA_7_.D - SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_4_.AR - SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR CLK_CNT_0_.D CLK_CNT_0_.C + inst_CLK_000_D5.D inst_CLK_000_D5.C inst_CLK_OUT_PRE.D.X1 inst_CLK_OUT_PRE.D.X2 + inst_CLK_OUT_PRE.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.D + SM_AMIGA_5_.C SM_AMIGA_5_.AR cpu_est_2_.D.X1 cpu_est_2_.D.X2 cpu_est_2_.C + CLK_REF_1_.D CLK_REF_1_.LH CLK_REF_1_.AR SM_AMIGA_7_.D SM_AMIGA_7_.C + SM_AMIGA_7_.AP inst_CLK_000_D3.D inst_CLK_000_D3.C SM_AMIGA_4_.D SM_AMIGA_4_.C + SM_AMIGA_4_.AR inst_CLK_000_D4.D inst_CLK_000_D4.C CLK_CNT_0_.D CLK_CNT_0_.C CLK_CNT_1_.D CLK_CNT_1_.C SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR - SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C + SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR -.phase 11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 -.p 114 -------------------------------------------------------------------------- 00001000100100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 --------------------------------------0----------------------------------- 01000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ------------------------------------------------------1------------------- 00100000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000 ------------1------------------------------------------------------------- 00010000000000100100010001000100010010010100100010100101010010010101001001010010101010100010000000100100100101010010010010 ---------------0---------------------------------------------------------- 00000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ------------------------1111---------------------------------------------- 00000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 --0--------------0000000-------------------------------------------------- 00000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -------1------------------------------------------------------------------ 00000000000010000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ---1----------------------------------------------10---------------------- 00000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 --------------------------------------------------0-1--------------------- 00000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ---------------------------------------------------11--------------------- 00000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 --------------0----------------------------------------------------------- 00000000000000010010001000100010001001000010010000010000001001000000100100001000000000010000010010010010010000001001001001 -----0--------------------------------------------------------0----------- 00000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 --------------------------------------------------0---1---------1--------- 00000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 -----0-------------------------------------0------------------------------ 00000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 --------------------------------------------0------1-0-1------------------ 00000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000 -------------------------------------1------------------------------------ 00000000000000000000000100010001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ------0--------1----------------0-----------0------1-0-1------------------ 00000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -----01-----------------------------------------------------0------------- 00000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -----0---------1----------------------------1---------------0------------- 00000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -----0---------1-----------------------------------0--------0------------- 00000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -----0---------1-------------------------------------1------0------------- 00000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -----0---------1---------------------------------------0----0------------- 00000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ------0--------0----------------0------------------------------1---------- 00000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -----0---------0--------------------------------------------0--0---------- 00000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -1----0--------1----------------------------0------1-0-1------------------ 00000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ------0--------10---------------------------0------1-0-1------------------ 00000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ------0--------1----------------1-----------0------1-0-1------------------ 00000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -----01------------------------------------------------------0------------ 00000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -----0---------1----------------------------1----------------0------------ 00000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -----0---------1-----------------------------------0---------0------------ 00000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -----0---------1-------------------------------------1-------0------------ 00000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -----0---------1---------------------------------------0-----0------------ 00000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -1----0--------0-----------------------------------------------1---------- 00000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ------0--------00----------------------------------------------1---------- 00000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ------0--------0----------------1------------------------------1---------- 00000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -----0---------0---------------------------------------------0-0---------- 00000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 --------0-1-------------------------0------------------------------------- 00000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -----1-00-0--------------------------------------------1------------------ 00000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -----1-00-0------------------------------------------------1-------------- 00000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ---------1---------------------------1------------------------------------ 00000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ---------1----------------------------------------10---------------------- 00000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ----10---11-----------------0010---1-------------------------------------- 00000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000 -----0----0---------------------------0----------------------------------- 00000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000 -------------------------------------------0----------------------------0- 00000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000 -------------------------------------0------------------------------------ 00000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000 ---------------------------------------1-11-------10----1----------------- 00000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000 ---------------------------------------0-11-------10----0----------------- 00000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000 ---------------------------------------0-00-------10----0----------------- 00000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000 ---------------------------------------00011------1-----1----------------- 00000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000 ---------------------------------------0110----0--0-----1----------------- 00000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000 --------------1----------------------------------------------------------- 00000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000 -------1------1----------------------------------------1------------------ 00000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000 --------------0--------------------------------------------------------0-- 00000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000 -----0-------------------------------------------------0---------------0-- 00000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000 -------------------------------------------------10----------------------- 00000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000 -------------------------------------------------1-1---------------------- 00000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000 ---------------------------------1----------------10---------------------- 00000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000 ----------------------------------------------1---0----------------------- 00000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000 ----------------------------------------------1----1---------------------- 00000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000 ----------------------------------1---------------10---------------------- 00000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000 -----------------------------------------1--------0----------------------- 00000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000 -----------------------------------------1---------1---------------------- 00000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000 -----------------------------------------0--------10---------------------- 00000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000 ---------------------------------------1-00-------10---------------------- 00000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000 ---------------------------------------0-1--------10----1----------------- 00000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000 ---------------------------------------1-11-------10----0----------------- 00000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000 ---------------------------------------0--0-------10----0----------------- 00000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000 -----1-------------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000 -------0--1--------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000 ----1----11-----------------0010---1-------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000 ----------0---------------------------------1----------------------------- 00000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000 -----0---------------------------------------0---------------------------- 00000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000 -----------1-----------------------------------1--1----------------1-----0 00000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000 -------------1------------------------------------------------------------ 00000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000 -----0------------------------------------------0------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000 -----------1---------------------------1000----0--1-----1----------1------ 00000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000 -----------1-------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000 --------------------------------------------------1----------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000 ---------------------------------------------------1---------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000 ---------------------------------------------------------11------11------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000 ---------------------------------------------------------01------01------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000 ---------------------------------------------------------10------10------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000 ---------------------------------------------------------00------00------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000 --------------------------------------------1----------1------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000 ---------------------------------------------------0---1------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000 -----------------------------------------------------1-1------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000 --------------------------------------------------0--------1-------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000 ---------------------------------------1-1--------10----0----------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000 -----------------------------------------00-------10----0----------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000 ---------------------------------------0-10-------10----1----------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000 --------------------------------------------------------1----------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000 --------------------------------------------------1--------1-------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000 -------------------------------------------1------1-------------------1--- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000 --------------------------------------------------0------------1---------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000 --------------------------------------------------0-----------------1----- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000 --------------------------------------------------1-------------1--------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000 --------------------------------------------------1------------------1---- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000 ------------------------------------------------------0---------1----0---- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000 ---------------------------------------------------------1-------0-------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000 ----------------------------------------------------------0------01------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001010000000000000 ----------------------------------------------------------1------00------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000 ---------------------------------------------------------1-------01------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000 ---------------------------------------------------------0-------10------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000 ----------------------------------------------------------1------10------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000 --------------------------------------------------1------------1---------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000 ---------------------------------------------1--1------------------1------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000 --------------------------------------------------1----------------1------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000 --------------------------------------------------1-----------------1----- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000 ---------------------------------------------0----0----------------1------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000 ------------------------------------------------0-0----------------1------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000 --------------------------------------------------0------------------1---- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000 -------------------------------------------0--------------------------1--- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 --------------------------------------------------0-------------------1--- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 +.phase 111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 +.p 111 +--------------------------------------------------------------------------- 000010001001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +------------------------------------0-------------------------------------- 010000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +-----------------------------------------------------1--------------------- 001000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +-----------1--------------------------------------------------------------- 000100000000001001000100010001000100100101001000101001010100100101010010010100101010100101001000100001001010010101010010010010 +--------------0------------------------------------------------------------ 000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +-----------------------1111------------------------------------------------ 000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +-0--------------0000000---------------------------------------------------- 000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +------1-------------------------------------------------------------------- 000000000000100000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +------------------------------------------------01------------------------- 000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +-------------------------------------------------11------------------------ 000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +--1---------------------------------------------1-0------------------------ 000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +-------------0------------------------------------------------------------- 000000000000000100100010001000100010010000100100000100000010010000001001000010000000000000100100000100100001000000001001001001 +----0-------------------------------------------------------0-------------- 000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +----------------------------------------------------0-----------1---1------ 000000000000000010000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000100000000 +----1--------------------------------------------------0------------------- 000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +-----------------------------------------1-------------0------------------- 000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +-----------------------------------1--------------------------------------- 000000000000000000000001000100010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +-----0--------1----------------0-----------------------1------------------- 000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +----01----------------------------------------------------0---------------- 000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +----0---------1----------------------------------------0--0---------------- 000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +-----0--------0----------------0-------------------------------1----------- 000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +----0---------0-------------------------------------------0----0----------- 000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +----11--------------------------------------------------------------------- 000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +0----0--------11---------------0-----------------------1------------------- 000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +----1---------1----------------------------------------0------------------- 000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +-----1-----------------------------------------------------1--------------- 000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +--------------1----------------------------------------0---1--------------- 000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +0----0--------01---------------0-------------------------------1----------- 000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +----1---------0------------------------------------------------0----------- 000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +--------------0--------------------------------------------1---0----------- 000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +----1-00-0---------------------------------------------------1------------- 000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +-------0-1--------------------------------------------------------------0-- 000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +--------1--------------------------1--------------------------------------- 000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +--------1---------------------------------------1-0------------------------ 000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +---10---11-----------------0010---1---------------------------------------- 000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +----0-------------------------------0-------------------------------------- 000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +-----------------------------------------0-------------------------------0- 000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000 +-----------------------------------0--------------------------------------- 000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000 +-------------------------------------1-11-------1-0-----1------------------ 000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000 +-------------------------------------0-11-------1-0-----0------------------ 000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000 +-------------------------------------0-00-------1-0-----0------------------ 000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000 +-------------------------------------00011------1-------1------------------ 000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000 +-------------------------------------0110----0--0-------1------------------ 000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000 +-------------1------------------------------------------------------------- 000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000 +------1------1----------------------------------------1-------------------- 000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000 +-------------0--------------------------------------------------------0---- 000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000 +----0-------------------------------------------------0---------------0---- 000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000 +----------------------------------------------1-0-------------------------- 000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000 +----------------------------------------------1---1------------------------ 000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000 +--------------------------------1---------------1-0------------------------ 000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000 +-------------------------------------------1----0-------------------------- 000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000 +-------------------------------------------1------1------------------------ 000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000 +---------------------------------1--------------1-0------------------------ 000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000 +---------------------------------------1--------0-------------------------- 000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000 +---------------------------------------1----------1------------------------ 000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000 +---------------------------------------0--------1-0------------------------ 000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000 +-------------------------------------1-00-------1-0------------------------ 000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000 +-------------------------------------0-1--------1-0-----1------------------ 000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000 +-------------------------------------1-11-------1-0-----0------------------ 000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000 +-------------------------------------0--0-------1-0-----0------------------ 000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000 +----1---------------------------------------------------------------------- 000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000 +------0-----------------------------------1-------------------------------- 000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000 +---------0--------------------------------1-------------------------------- 000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000 +---1----1------------------0010---1-------1-------------------------------- 000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000 +------0-----------------------------------------------1-------------------- 000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000 +------------------------------------------1------------------0------------- 000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000 +----0---------------------------------------0------------------------------ 000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000 +---------------------------------------------1--1------------------1------0 000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000 +------------1-------------------------------------------------------------- 000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000 +----0------------------------------------------0--------------------------- 000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000 +-------------------------------------1000----0--1-------1----------1------- 000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000 +----------1---------------------------------------------------------------- 000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000 +------------------------------------------------1-------------------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000 +--------------------------------------------------1------------------------ 000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000 +----------------------------------------------------------------1---------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000 +-----------------------------------------------------1-----------1--------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000 +-----------------------------------------------------1------------1-------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000 +-----------------------------------------------------0-----------00-------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000 +---------------------------------------------------------1-------0--------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000 +------1-----------------------------------------0-----1------0------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000 +------------------------------------------0--------0---------11------------ 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000 +------------------------------------------------1-----1-------------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000 +------------------------------------------------1------1------------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000 +-------------------------------------1-1--------1-0-----0------------------ 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000 +---------------------------------------00-------1-0-----0------------------ 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000 +-------------------------------------0-10-------1-0-----1------------------ 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000 +--------------------------------------------------------1------------------ 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000 +------0-----------------------------------------0-----1-------------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000 +------------------------------------------1------------------1------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000 +---------------------------------------------------1---------1------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000 +-------------------------------------------------------------10------------ 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000 +-----------------------------------------1------1----------------------1--- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000 +---------------------------------------------------1----------------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000 +------------------------------------------------0------1------------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000 +------------------------------------------------0--------------1----------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000 +--------------------------------------------------------------1------------ 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000 +---------------------------------------------------------0-------01-------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001010000000000000 +---------------------------------------------------------1-------00-------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000 +-----------------------------------------------------------------10-------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000 +------------------------------------------------1--------------1----------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000 +--------------------------------------------1--1-------------------1------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000 +------------------------------------------------1------------------1------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000 +------------------------------------------------1-------------------1------ 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000 +------------------------------------------------1--------------------1----- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000 +--------------------------------------------0---0------------------1------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000 +-----------------------------------------------00------------------1------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000 +------------------------------------------------0--------------------1----- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000 +------------------------------------------------0---1---------------1------ 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 +------------------------------------------------0---------------0---1------ 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 +-----------------------------------------0-----------------------------1--- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 +------------------------------------------------0----------------------1--- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 .end diff --git a/Logic/68030_tk.tte b/Logic/68030_tk.tte index 4f9d020..999debc 100644 --- a/Logic/68030_tk.tte +++ b/Logic/68030_tk.tte @@ -1,35 +1,36 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Thu May 22 14:56:10 2014 +#$ DATE Sat May 24 11:44:09 2014 #$ MODULE BUS68030 -#$ PINS 59 SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 nEXP_SPACE BERR SIZE_0_ - BG_030 A_30_ A_29_ A_28_ BGACK_000 A_27_ CLK_030 A_26_ CLK_000 A_25_ CLK_OSZI - A_24_ CLK_DIV_OUT A_23_ A_22_ A_21_ A_20_ AVEC A_19_ AVEC_EXP A_18_ A_17_ VPA - A_16_ RST RW AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN A_0_ IPL_1_ IPL_0_ +#$ PINS 59 SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 nEXP_SPACE BERR BG_030 + BGACK_000 CLK_030 CLK_000 SIZE_0_ CLK_OSZI A_30_ CLK_DIV_OUT A_29_ A_28_ A_27_ + A_26_ AVEC A_25_ AVEC_EXP A_24_ A_23_ VPA A_22_ A_21_ RST A_20_ A_19_ RW A_18_ + A_17_ AMIGA_BUS_DATA_DIR A_16_ AMIGA_BUS_ENABLE_LOW CIIN A_0_ IPL_1_ IPL_0_ DSACK_0_ FC_0_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 BG_000 BGACK_030 CLK_EXP FPU_CS DTACK E VMA RESET AMIGA_BUS_ENABLE IPL_030_1_ IPL_030_0_ -#$ NODES 23 cpu_est_0_ cpu_est_1_ inst_AS_030_000_SYNC inst_DTACK_SYNC +#$ NODES 25 cpu_est_0_ cpu_est_1_ inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2 - inst_CLK_OUT_PRE SM_AMIGA_6_ cpu_est_2_ CLK_REF_0_ CLK_REF_1_ SM_AMIGA_7_ - SM_AMIGA_4_ SM_AMIGA_1_ CLK_CNT_0_ CLK_CNT_1_ SM_AMIGA_3_ SM_AMIGA_5_ - SM_AMIGA_2_ SM_AMIGA_0_ + inst_CLK_000_D5 inst_CLK_OUT_PRE SM_AMIGA_6_ SM_AMIGA_5_ cpu_est_2_ CLK_REF_1_ + SM_AMIGA_7_ inst_CLK_000_D3 SM_AMIGA_4_ inst_CLK_000_D4 CLK_CNT_0_ CLK_CNT_1_ + SM_AMIGA_3_ SM_AMIGA_1_ SM_AMIGA_2_ SM_AMIGA_0_ .type f -.i 73 -.o 122 +.i 75 +.o 126 .ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_ - BG_000.Q BGACK_030.Q FPU_CS.Q E.Q VMA.Q cpu_est_0_.Q cpu_est_1_.Q AS_000.Q - inst_AS_030_000_SYNC.Q inst_DTACK_SYNC.Q IPL_030_0_.Q inst_VPA_D.Q - inst_VPA_SYNC.Q IPL_030_1_.Q inst_CLK_000_D0.Q inst_CLK_000_D1.Q IPL_030_2_.Q - inst_CLK_000_D2.Q inst_CLK_OUT_PRE.Q SM_AMIGA_6_.Q cpu_est_2_.Q CLK_REF_0_.Q - CLK_REF_1_.Q SM_AMIGA_7_.Q UDS_000.Q LDS_000.Q DSACK_1_.Q SM_AMIGA_4_.Q - SM_AMIGA_1_.Q CLK_CNT_0_.Q CLK_CNT_1_.Q SM_AMIGA_3_.Q SM_AMIGA_5_.Q - SM_AMIGA_2_.Q SM_AMIGA_0_.Q AMIGA_BUS_ENABLE.Q DSACK_1_.PIN DTACK.PIN + BGACK_030.Q FPU_CS.Q E.Q VMA.Q cpu_est_0_.Q cpu_est_1_.Q AS_000.Q + inst_AS_030_000_SYNC.Q IPL_030_0_.Q inst_DTACK_SYNC.Q inst_VPA_D.Q IPL_030_1_.Q + inst_VPA_SYNC.Q inst_CLK_000_D0.Q IPL_030_2_.Q inst_CLK_000_D1.Q + inst_CLK_000_D2.Q inst_CLK_000_D5.Q inst_CLK_OUT_PRE.Q SM_AMIGA_6_.Q + SM_AMIGA_5_.Q cpu_est_2_.Q CLK_REF_1_.Q UDS_000.Q LDS_000.Q DSACK_1_.Q + SM_AMIGA_7_.Q inst_CLK_000_D3.Q SM_AMIGA_4_.Q inst_CLK_000_D4.Q CLK_CNT_0_.Q + CLK_CNT_1_.Q SM_AMIGA_3_.Q SM_AMIGA_1_.Q SM_AMIGA_2_.Q AMIGA_BUS_ENABLE.Q + SM_AMIGA_0_.Q BG_000.Q DSACK_1_.PIN DTACK.PIN .ob BERR BERR.OE CLK_DIV_OUT.D CLK_DIV_OUT.C AVEC AVEC_EXP AVEC_EXP.OE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN CIIN.OE DSACK_0_ DSACK_0_.OE IPL_030_2_.D IPL_030_2_.C IPL_030_2_.AP DSACK_1_.D- DSACK_1_.C DSACK_1_.AP - DSACK_1_.OE AS_000.D- AS_000.C AS_000.AP AS_000.OE UDS_000.D- UDS_000.C - UDS_000.AP UDS_000.OE LDS_000.D- LDS_000.C LDS_000.AP LDS_000.OE BG_000.D- + DSACK_1_.OE AS_000.D AS_000.C AS_000.AP AS_000.OE UDS_000.D- UDS_000.C + UDS_000.AP UDS_000.OE LDS_000.D LDS_000.C LDS_000.AP LDS_000.OE BG_000.D- BG_000.C BG_000.AP BGACK_030.D BGACK_030.C BGACK_030.AP CLK_EXP.D CLK_EXP.C FPU_CS.D- FPU_CS.C FPU_CS.AP DTACK.D- DTACK.C DTACK.AP DTACK.OE E.T E.C VMA.T VMA.C VMA.AP RESET.D RESET.C AMIGA_BUS_ENABLE.D- AMIGA_BUS_ENABLE.C IPL_030_1_.D @@ -39,128 +40,126 @@ inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_VPA_D.D inst_VPA_D.C inst_VPA_SYNC.D- inst_VPA_SYNC.C inst_VPA_SYNC.AP inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_D2.D inst_CLK_000_D2.C - inst_CLK_OUT_PRE.T inst_CLK_OUT_PRE.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR - cpu_est_2_.D.X1 cpu_est_2_.D.X2 cpu_est_2_.C CLK_REF_0_.D CLK_REF_0_.LH - CLK_REF_0_.AP CLK_REF_1_.D CLK_REF_1_.LH CLK_REF_1_.AR SM_AMIGA_7_.D - SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_4_.AR - SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR CLK_CNT_0_.D CLK_CNT_0_.C + inst_CLK_000_D5.D inst_CLK_000_D5.C inst_CLK_OUT_PRE.D.X1 inst_CLK_OUT_PRE.D.X2 + inst_CLK_OUT_PRE.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.D + SM_AMIGA_5_.C SM_AMIGA_5_.AR cpu_est_2_.D.X1 cpu_est_2_.D.X2 cpu_est_2_.C + CLK_REF_1_.D CLK_REF_1_.LH CLK_REF_1_.AR SM_AMIGA_7_.D SM_AMIGA_7_.C + SM_AMIGA_7_.AP inst_CLK_000_D3.D inst_CLK_000_D3.C SM_AMIGA_4_.D SM_AMIGA_4_.C + SM_AMIGA_4_.AR inst_CLK_000_D4.D inst_CLK_000_D4.C CLK_CNT_0_.D CLK_CNT_0_.C CLK_CNT_1_.D CLK_CNT_1_.C SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR - SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C + SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR -.phase 11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 -.p 114 -------------------------------------------------------------------------- 00001000100100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 --------------------------------------0----------------------------------- 01000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ------------------------------------------------------1------------------- 00100000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000 ------------1------------------------------------------------------------- 00010000000000100100010001000100010010010100100010100101010010010101001001010010101010100010000000100100100101010010010010 ---------------0---------------------------------------------------------- 00000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ------------------------1111---------------------------------------------- 00000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 --0--------------0000000-------------------------------------------------- 00000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -------1------------------------------------------------------------------ 00000000000010000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ---1----------------------------------------------10---------------------- 00000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 --------------------------------------------------0-1--------------------- 00000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ---------------------------------------------------11--------------------- 00000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 --------------0----------------------------------------------------------- 00000000000000010010001000100010001001000010010000010000001001000000100100001000000000010000010010010010010000001001001001 -----0--------------------------------------------------------0----------- 00000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 --------------------------------------------------0---1---------1--------- 00000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 -----0-------------------------------------0------------------------------ 00000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 --------------------------------------------0------1-0-1------------------ 00000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000 -------------------------------------1------------------------------------ 00000000000000000000000100010001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ------0--------1----------------0-----------0------1-0-1------------------ 00000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -----01-----------------------------------------------------0------------- 00000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -----0---------1----------------------------1---------------0------------- 00000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -----0---------1-----------------------------------0--------0------------- 00000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -----0---------1-------------------------------------1------0------------- 00000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -----0---------1---------------------------------------0----0------------- 00000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ------0--------0----------------0------------------------------1---------- 00000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -----0---------0--------------------------------------------0--0---------- 00000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -1----0--------1----------------------------0------1-0-1------------------ 00000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ------0--------10---------------------------0------1-0-1------------------ 00000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ------0--------1----------------1-----------0------1-0-1------------------ 00000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -----01------------------------------------------------------0------------ 00000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -----0---------1----------------------------1----------------0------------ 00000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -----0---------1-----------------------------------0---------0------------ 00000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -----0---------1-------------------------------------1-------0------------ 00000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -----0---------1---------------------------------------0-----0------------ 00000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -1----0--------0-----------------------------------------------1---------- 00000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ------0--------00----------------------------------------------1---------- 00000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ------0--------0----------------1------------------------------1---------- 00000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -----0---------0---------------------------------------------0-0---------- 00000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 --------0-1-------------------------0------------------------------------- 00000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -----1-00-0--------------------------------------------1------------------ 00000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -----1-00-0------------------------------------------------1-------------- 00000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ---------1---------------------------1------------------------------------ 00000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ---------1----------------------------------------10---------------------- 00000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ----10---11-----------------0010---1-------------------------------------- 00000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000 -----0----0---------------------------0----------------------------------- 00000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000 -------------------------------------------0----------------------------0- 00000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000 -------------------------------------0------------------------------------ 00000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000 ---------------------------------------1-11-------10----1----------------- 00000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000 ---------------------------------------0-11-------10----0----------------- 00000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000 ---------------------------------------0-00-------10----0----------------- 00000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000 ---------------------------------------00011------1-----1----------------- 00000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000 ---------------------------------------0110----0--0-----1----------------- 00000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000 --------------1----------------------------------------------------------- 00000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000 -------1------1----------------------------------------1------------------ 00000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000 --------------0--------------------------------------------------------0-- 00000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000 -----0-------------------------------------------------0---------------0-- 00000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000 -------------------------------------------------10----------------------- 00000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000 -------------------------------------------------1-1---------------------- 00000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000 ---------------------------------1----------------10---------------------- 00000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000 ----------------------------------------------1---0----------------------- 00000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000 ----------------------------------------------1----1---------------------- 00000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000 ----------------------------------1---------------10---------------------- 00000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000 -----------------------------------------1--------0----------------------- 00000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000 -----------------------------------------1---------1---------------------- 00000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000 -----------------------------------------0--------10---------------------- 00000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000 ---------------------------------------1-00-------10---------------------- 00000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000 ---------------------------------------0-1--------10----1----------------- 00000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000 ---------------------------------------1-11-------10----0----------------- 00000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000 ---------------------------------------0--0-------10----0----------------- 00000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000 -----1-------------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000 -------0--1--------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000 ----1----11-----------------0010---1-------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000 ----------0---------------------------------1----------------------------- 00000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000 -----0---------------------------------------0---------------------------- 00000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000 -----------1-----------------------------------1--1----------------1-----0 00000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000 -------------1------------------------------------------------------------ 00000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000 -----0------------------------------------------0------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000 -----------1---------------------------1000----0--1-----1----------1------ 00000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000 -----------1-------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000 --------------------------------------------------1----------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000 ---------------------------------------------------1---------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000 ---------------------------------------------------------11------11------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000 ---------------------------------------------------------01------01------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000 ---------------------------------------------------------10------10------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000 ---------------------------------------------------------00------00------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000 --------------------------------------------1----------1------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000 ---------------------------------------------------0---1------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000 -----------------------------------------------------1-1------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000 --------------------------------------------------0--------1-------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000 ---------------------------------------1-1--------10----0----------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000 -----------------------------------------00-------10----0----------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000 ---------------------------------------0-10-------10----1----------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000 --------------------------------------------------------1----------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000 --------------------------------------------------1--------1-------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000 -------------------------------------------1------1-------------------1--- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000 --------------------------------------------------0------------1---------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000 --------------------------------------------------0-----------------1----- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000 --------------------------------------------------1-------------1--------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000 --------------------------------------------------1------------------1---- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000 ------------------------------------------------------0---------1----0---- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000 ---------------------------------------------------------1-------0-------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000 ----------------------------------------------------------0------01------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001010000000000000 ----------------------------------------------------------1------00------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000 ---------------------------------------------------------1-------01------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000 ---------------------------------------------------------0-------10------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000 ----------------------------------------------------------1------10------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000 --------------------------------------------------1------------1---------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000 ---------------------------------------------1--1------------------1------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000 --------------------------------------------------1----------------1------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000 --------------------------------------------------1-----------------1----- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000 ---------------------------------------------0----0----------------1------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000 ------------------------------------------------0-0----------------1------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000 --------------------------------------------------0------------------1---- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000 -------------------------------------------0--------------------------1--- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 --------------------------------------------------0-------------------1--- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 +.phase 111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 +.p 111 +--------------------------------------------------------------------------- 000010001001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +------------------------------------0-------------------------------------- 010000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +-----------------------------------------------------1--------------------- 001000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +-----------1--------------------------------------------------------------- 000100000000001001000100010001000100100101001000101001010100100101010010010100101010100101001000100001001010010101010010010010 +--------------0------------------------------------------------------------ 000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +-----------------------1111------------------------------------------------ 000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +-0--------------0000000---------------------------------------------------- 000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +------1-------------------------------------------------------------------- 000000000000100000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +------------------------------------------------01------------------------- 000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +-------------------------------------------------11------------------------ 000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +--1---------------------------------------------1-0------------------------ 000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +-------------0------------------------------------------------------------- 000000000000000100100010001000100010010000100100000100000010010000001001000010000000000000100100000100100001000000001001001001 +----0-------------------------------------------------------0-------------- 000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +----------------------------------------------------0-----------1---1------ 000000000000000010000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000100000000 +----1--------------------------------------------------0------------------- 000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +-----------------------------------------1-------------0------------------- 000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +-----------------------------------1--------------------------------------- 000000000000000000000001000100010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +-----0--------1----------------0-----------------------1------------------- 000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +----01----------------------------------------------------0---------------- 000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +----0---------1----------------------------------------0--0---------------- 000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +-----0--------0----------------0-------------------------------1----------- 000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +----0---------0-------------------------------------------0----0----------- 000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +----11--------------------------------------------------------------------- 000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +0----0--------11---------------0-----------------------1------------------- 000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +----1---------1----------------------------------------0------------------- 000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +-----1-----------------------------------------------------1--------------- 000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +--------------1----------------------------------------0---1--------------- 000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +0----0--------01---------------0-------------------------------1----------- 000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +----1---------0------------------------------------------------0----------- 000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +--------------0--------------------------------------------1---0----------- 000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +----1-00-0---------------------------------------------------1------------- 000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +-------0-1--------------------------------------------------------------0-- 000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +--------1--------------------------1--------------------------------------- 000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +--------1---------------------------------------1-0------------------------ 000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +---10---11-----------------0010---1---------------------------------------- 000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +----0-------------------------------0-------------------------------------- 000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +-----------------------------------------0-------------------------------0- 000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000 +-----------------------------------0--------------------------------------- 000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000 +-------------------------------------1-11-------1-0-----1------------------ 000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000 +-------------------------------------0-11-------1-0-----0------------------ 000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000 +-------------------------------------0-00-------1-0-----0------------------ 000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000 +-------------------------------------00011------1-------1------------------ 000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000 +-------------------------------------0110----0--0-------1------------------ 000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000 +-------------1------------------------------------------------------------- 000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000 +------1------1----------------------------------------1-------------------- 000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000 +-------------0--------------------------------------------------------0---- 000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000 +----0-------------------------------------------------0---------------0---- 000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000 +----------------------------------------------1-0-------------------------- 000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000 +----------------------------------------------1---1------------------------ 000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000 +--------------------------------1---------------1-0------------------------ 000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000 +-------------------------------------------1----0-------------------------- 000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000 +-------------------------------------------1------1------------------------ 000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000 +---------------------------------1--------------1-0------------------------ 000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000 +---------------------------------------1--------0-------------------------- 000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000 +---------------------------------------1----------1------------------------ 000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000 +---------------------------------------0--------1-0------------------------ 000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000 +-------------------------------------1-00-------1-0------------------------ 000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000 +-------------------------------------0-1--------1-0-----1------------------ 000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000 +-------------------------------------1-11-------1-0-----0------------------ 000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000 +-------------------------------------0--0-------1-0-----0------------------ 000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000 +----1---------------------------------------------------------------------- 000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000 +------0-----------------------------------1-------------------------------- 000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000 +---------0--------------------------------1-------------------------------- 000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000 +---1----1------------------0010---1-------1-------------------------------- 000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000 +------0-----------------------------------------------1-------------------- 000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000 +------------------------------------------1------------------0------------- 000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000 +----0---------------------------------------0------------------------------ 000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000 +---------------------------------------------1--1------------------1------0 000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000 +------------1-------------------------------------------------------------- 000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000 +----0------------------------------------------0--------------------------- 000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000 +-------------------------------------1000----0--1-------1----------1------- 000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000 +----------1---------------------------------------------------------------- 000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000 +------------------------------------------------1-------------------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000 +--------------------------------------------------1------------------------ 000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000 +----------------------------------------------------------------1---------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000 +-----------------------------------------------------1-----------1--------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000 +-----------------------------------------------------1------------1-------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000 +-----------------------------------------------------0-----------00-------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000 +---------------------------------------------------------1-------0--------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000 +------1-----------------------------------------0-----1------0------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000 +------------------------------------------0--------0---------11------------ 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000 +------------------------------------------------1-----1-------------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000 +------------------------------------------------1------1------------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000 +-------------------------------------1-1--------1-0-----0------------------ 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000 +---------------------------------------00-------1-0-----0------------------ 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000 +-------------------------------------0-10-------1-0-----1------------------ 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000 +--------------------------------------------------------1------------------ 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000 +------0-----------------------------------------0-----1-------------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000 +------------------------------------------1------------------1------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000 +---------------------------------------------------1---------1------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000 +-------------------------------------------------------------10------------ 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000 +-----------------------------------------1------1----------------------1--- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000 +---------------------------------------------------1----------------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000 +------------------------------------------------0------1------------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000 +------------------------------------------------0--------------1----------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000 +--------------------------------------------------------------1------------ 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000 +---------------------------------------------------------0-------01-------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001010000000000000 +---------------------------------------------------------1-------00-------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000 +-----------------------------------------------------------------10-------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000 +------------------------------------------------1--------------1----------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000 +--------------------------------------------1--1-------------------1------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000 +------------------------------------------------1------------------1------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000 +------------------------------------------------1-------------------1------ 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000 +------------------------------------------------1--------------------1----- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000 +--------------------------------------------0---0------------------1------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000 +-----------------------------------------------00------------------1------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000 +------------------------------------------------0--------------------1----- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000 +------------------------------------------------0---1---------------1------ 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 +------------------------------------------------0---------------0---1------ 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 +-----------------------------------------0-----------------------------1--- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 +------------------------------------------------0----------------------1--- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 .end diff --git a/Logic/68030_tk.vcl b/Logic/68030_tk.vcl index 4e4b052..30f3d16 100644 --- a/Logic/68030_tk.vcl +++ b/Logic/68030_tk.vcl @@ -17,8 +17,8 @@ Parent = m4a5.lci; SDS_file = m4a5.sds; Design = 68030_tk.tt4; Rev = 0.01; -DATE = 5/22/14; -TIME = 14:56:14; +DATE = 5/24/14; +TIME = 11:44:13; Type = TT2; Pre_Fit_Time = 1; Source_Format = Pure_VHDL; @@ -137,7 +137,6 @@ LDS_000 = OUTPUT,31,3,-; UDS_000 = OUTPUT,32,3,-; E = OUTPUT,66,6,-; AMIGA_BUS_ENABLE = OUTPUT,34,3,-; -BG_000 = OUTPUT,29,3,-; IPL_030_2_ = OUTPUT,9,1,-; IPL_030_0_ = OUTPUT,8,1,-; IPL_030_1_ = OUTPUT,7,1,-; @@ -145,6 +144,7 @@ BGACK_030 = OUTPUT,83,7,-; FPU_CS = OUTPUT,78,7,-; VMA = OUTPUT,35,3,-; AS_000 = OUTPUT,33,3,-; +BG_000 = OUTPUT,29,3,-; AVEC = OUTPUT,92,0,-; DSACK_0_ = OUTPUT,80,7,-; CLK_DIV_OUT = OUTPUT,65,6,-; @@ -156,39 +156,41 @@ AMIGA_BUS_ENABLE_LOW = OUTPUT,20,2,-; CLK_EXP = OUTPUT,10,1,-; RESET = OUTPUT,3,1,-; inst_CLK_000_D0 = NODE,*,6,-; -inst_CLK_000_D1 = NODE,*,3,-; -inst_CLK_OUT_PRE = NODE,*,0,-; -inst_AS_030_000_SYNC = NODE,*,7,-; -RN_FPU_CS = NODE,-1,7,-; -SM_AMIGA_4_ = NODE,*,1,-; -SM_AMIGA_7_ = NODE,*,7,-; -inst_VPA_D = NODE,*,1,-; -SM_AMIGA_6_ = NODE,*,6,-; -cpu_est_1_ = NODE,*,6,-; +SM_AMIGA_3_ = NODE,*,1,-; +inst_CLK_000_D1 = NODE,*,6,-; +cpu_est_1_ = NODE,*,3,-; RN_E = NODE,-1,6,-; -SM_AMIGA_2_ = NODE,*,6,-; -SM_AMIGA_3_ = NODE,*,6,-; -SM_AMIGA_1_ = NODE,*,1,-; cpu_est_2_ = NODE,*,3,-; -cpu_est_0_ = NODE,*,6,-; +cpu_est_0_ = NODE,*,3,-; +RN_FPU_CS = NODE,-1,7,-; +inst_VPA_SYNC = NODE,*,5,-; +inst_DTACK_SYNC = NODE,*,0,-; +inst_VPA_D = NODE,*,6,-; +SM_AMIGA_7_ = NODE,*,7,-; +SM_AMIGA_2_ = NODE,*,6,-; +SM_AMIGA_1_ = NODE,*,1,-; +inst_CLK_OUT_PRE = NODE,*,6,-; RN_VMA = NODE,-1,3,-; RN_BGACK_030 = NODE,-1,7,-; RN_AS_000 = NODE,-1,3,-; -SM_AMIGA_5_ = NODE,*,6,-; -inst_DTACK_SYNC = NODE,*,5,-; -inst_CLK_000_D2 = NODE,*,6,-; +SM_AMIGA_4_ = NODE,*,3,-; +SM_AMIGA_6_ = NODE,*,7,-; +inst_CLK_000_D4 = NODE,*,7,-; +inst_CLK_000_D5 = NODE,*,7,-; RN_LDS_000 = NODE,-1,3,-; +inst_AS_030_000_SYNC = NODE,*,7,-; RN_UDS_000 = NODE,-1,3,-; -CLK_CNT_1_ = NODE,*,0,-; +SM_AMIGA_0_ = NODE,*,7,-; RN_IPL_030_0_ = NODE,-1,1,-; RN_IPL_030_1_ = NODE,-1,1,-; RN_AMIGA_BUS_ENABLE = NODE,-1,3,-; -RN_BG_000 = NODE,-1,3,-; RN_IPL_030_2_ = NODE,-1,1,-; -SM_AMIGA_0_ = NODE,*,7,-; -CLK_CNT_0_ = NODE,*,0,-; +RN_BG_000 = NODE,-1,3,-; RN_DSACK_1_ = NODE,-1,7,-; -inst_VPA_SYNC = NODE,*,6,-; -CLK_REF_1_ = NODE,*,1,-; -CLK_REF_0_ = NODE,*,3,-; +CLK_CNT_1_ = NODE,*,6,-; +CLK_CNT_0_ = NODE,*,6,-; +SM_AMIGA_5_ = NODE,*,3,-; +inst_CLK_000_D3 = NODE,*,7,-; +CLK_REF_1_ = NODE,*,7,-; +inst_CLK_000_D2 = NODE,*,6,-; CLK_OSZI = INPUT,61,-,-; diff --git a/Logic/68030_tk.vco b/Logic/68030_tk.vco index 18e40ae..8ef3d9c 100644 --- a/Logic/68030_tk.vco +++ b/Logic/68030_tk.vco @@ -17,8 +17,8 @@ Parent = m4a5.lci; SDS_file = m4a5.sds; Design = 68030_tk.tt4; Rev = 0.01; -DATE = 5/22/14; -TIME = 14:56:14; +DATE = 5/24/14; +TIME = 11:44:13; Type = TT2; Pre_Fit_Time = 1; Source_Format = Pure_VHDL; @@ -139,34 +139,34 @@ AS_030 = INPUT,82, H,-; DS_030 = INPUT,98, A,-; nEXP_SPACE = INPUT,14,-,-; BERR = OUTPUT,41, E,-; -SIZE_0_ = INPUT,70, G,-; BG_030 = INPUT,21, C,-; +BGACK_000 = INPUT,28, D,-; +CLK_030 = INPUT,64,-,-; +CLK_000 = INPUT,11,-,-; +SIZE_0_ = INPUT,70, G,-; +CLK_OSZI = INPUT,61,-,-; A_30_ = INPUT,5, B,-; +CLK_DIV_OUT = OUTPUT,65, G,-; A_29_ = INPUT,6, B,-; A_28_ = INPUT,15, C,-; -BGACK_000 = INPUT,28, D,-; A_27_ = INPUT,16, C,-; -CLK_030 = INPUT,64,-,-; A_26_ = INPUT,17, C,-; -CLK_000 = INPUT,11,-,-; +AVEC = OUTPUT,92, A,-; A_25_ = INPUT,18, C,-; -CLK_OSZI = INPUT,61,-,-; +AVEC_EXP = OUTPUT,22, C,-; A_24_ = INPUT,19, C,-; -CLK_DIV_OUT = OUTPUT,65, G,-; A_23_ = INPUT,84, H,-; +VPA = INPUT,36,-,-; A_22_ = INPUT,85, H,-; A_21_ = INPUT,94, A,-; +RST = INPUT,86,-,-; A_20_ = INPUT,93, A,-; -AVEC = OUTPUT,92, A,-; A_19_ = INPUT,97, A,-; -AVEC_EXP = OUTPUT,22, C,-; +RW = INPUT,71, G,-; A_18_ = INPUT,95, A,-; A_17_ = INPUT,59, F,-; -VPA = INPUT,36,-,-; -A_16_ = INPUT,96, A,-; -RST = INPUT,86,-,-; -RW = INPUT,71, G,-; AMIGA_BUS_DATA_DIR = OUTPUT,48, E,-; +A_16_ = INPUT,96, A,-; AMIGA_BUS_ENABLE_LOW = OUTPUT,20, C,-; CIIN = OUTPUT,47, E,-; A_0_ = INPUT,69, G,-; @@ -190,26 +190,28 @@ RESET = OUTPUT,3, B,-; AMIGA_BUS_ENABLE = OUTPUT,34, D,-; IPL_030_1_ = OUTPUT,7, B,-; IPL_030_0_ = OUTPUT,8, B,-; -cpu_est_0_ = NODE,13, G,-; -cpu_est_1_ = NODE,1, G,-; -inst_AS_030_000_SYNC = NODE,1, H,-; -inst_DTACK_SYNC = NODE,0, F,-; -inst_VPA_D = NODE,9, B,-; -inst_VPA_SYNC = NODE,10, G,-; +cpu_est_0_ = NODE,6, D,-; +cpu_est_1_ = NODE,9, D,-; +inst_AS_030_000_SYNC = NODE,2, H,-; +inst_DTACK_SYNC = NODE,0, A,-; +inst_VPA_D = NODE,1, G,-; +inst_VPA_SYNC = NODE,0, F,-; inst_CLK_000_D0 = NODE,8, G,-; -inst_CLK_000_D1 = NODE,13, D,-; +inst_CLK_000_D1 = NODE,12, G,-; inst_CLK_000_D2 = NODE,6, G,-; -inst_CLK_OUT_PRE = NODE,0, A,-; -SM_AMIGA_6_ = NODE,12, G,-; +inst_CLK_000_D5 = NODE,13, H,-; +inst_CLK_OUT_PRE = NODE,9, G,-; +SM_AMIGA_6_ = NODE,5, H,-; +SM_AMIGA_5_ = NODE,14, D,-; cpu_est_2_ = NODE,2, D,-; -CLK_REF_0_ = NODE,6, D,-; -CLK_REF_1_ = NODE,2, B,-; -SM_AMIGA_7_ = NODE,5, H,-; -SM_AMIGA_4_ = NODE,5, B,-; -SM_AMIGA_1_ = NODE,13, B,-; -CLK_CNT_0_ = NODE,12, A,-; -CLK_CNT_1_ = NODE,8, A,-; -SM_AMIGA_3_ = NODE,9, G,-; -SM_AMIGA_5_ = NODE,2, G,-; +CLK_REF_1_ = NODE,14, H,-; +SM_AMIGA_7_ = NODE,1, H,-; +inst_CLK_000_D3 = NODE,10, H,-; +SM_AMIGA_4_ = NODE,10, D,-; +inst_CLK_000_D4 = NODE,9, H,-; +CLK_CNT_0_ = NODE,2, G,-; +CLK_CNT_1_ = NODE,13, G,-; +SM_AMIGA_3_ = NODE,5, B,-; +SM_AMIGA_1_ = NODE,9, B,-; SM_AMIGA_2_ = NODE,5, G,-; -SM_AMIGA_0_ = NODE,9, H,-; +SM_AMIGA_0_ = NODE,6, H,-; diff --git a/Logic/68030_tk.xrf b/Logic/68030_tk.xrf index 4d4e2b8..50b701b 100644 --- a/Logic/68030_tk.xrf +++ b/Logic/68030_tk.xrf @@ -2,7 +2,7 @@ Signal Name Cross Reference File ispLEVER Classic 1.7.00.05.28.13 -Design '68030_tk' created Thu May 22 14:56:10 2014 +Design '68030_tk' created Sat May 24 11:44:09 2014 LEGEND: '>' Functional Block Port Separator diff --git a/Logic/BUS68030.bl0 b/Logic/BUS68030.bl0 index 213d74b..040abe3 100644 --- a/Logic/BUS68030.bl0 +++ b/Logic/BUS68030.bl0 @@ -1,137 +1,138 @@ -#$ DATE Thu May 22 14:56:10 2014 +#$ DATE Sat May 24 11:44:09 2014 #$ TOOL EDIF2BLIF version IspLever 1.0 #$ MODULE bus68030 -#$ PINS 74 SIZE_1_ A_31_ IPL_030_2_ IPL_2_ DSACK_1_ FC_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR SIZE_0_ BG_030 A_30_ BG_000 A_29_ BGACK_030 A_28_ BGACK_000 A_27_ CLK_030 A_26_ CLK_000 A_25_ CLK_OSZI A_24_ CLK_DIV_OUT A_23_ CLK_EXP A_22_ FPU_CS A_21_ DTACK A_20_ AVEC A_19_ AVEC_EXP A_18_ E A_17_ VPA A_16_ VMA A_15_ RST A_14_ RESET A_13_ RW A_12_ AMIGA_BUS_ENABLE A_11_ AMIGA_BUS_DATA_DIR A_10_ AMIGA_BUS_ENABLE_LOW A_9_ CIIN A_8_ A_7_ A_6_ A_5_ A_4_ A_3_ A_2_ A_1_ A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ IPL_0_ DSACK_0_ FC_0_ -#$ NODES 372 BG_000DFFSHreg BGACK_000_c CLK_030_c inst_BGACK_030_INTreg CLK_000_c inst_FPU_CS_INTreg cpu_est_3_reg CLK_OSZI_c inst_VMA_INTreg cpu_est_0_ \ -# cpu_est_1_ CLK_OUT_INTreg inst_AS_000_INTreg inst_AS_030_000_SYNC inst_DTACK_SYNC IPL_030DFFSH_0_reg inst_VPA_D inst_VPA_SYNC IPL_030DFFSH_1_reg inst_CLK_000_D0 \ -# inst_CLK_000_D1 IPL_030DFFSH_2_reg inst_CLK_000_D2 inst_CLK_OUT_PRE ipl_c_0__n SM_AMIGA_6_ vcc_n_n ipl_c_1__n gnd_n_n cpu_est_2_ \ -# ipl_c_2__n CLK_REF_0_ CLK_REF_1_ SM_AMIGA_7_ dsack_c_1__n inst_UDS_000_INTreg inst_LDS_000_INTreg DTACK_c DSACK_INT_1_ SM_AMIGA_4_ \ -# SM_AMIGA_1_ inst_DTACK_DMA clk_clk_cnt_n CLK_CNT_0_ CLK_CNT_1_ state_machine_un14_as_000_int_n RST_c SM_AMIGA_3_ RESETDFFreg SM_AMIGA_5_ \ -# RW_c SM_AMIGA_2_ SM_AMIGA_0_ fc_c_0__n fc_c_1__n AMIGA_BUS_ENABLEDFFreg N_101_i N_102_i N_103_i CLK_OUT_PRE_0 \ -# cpu_est_0_0_ N_91_0 N_125_i N_123_i N_124_i N_126_i clk_cpu_est_11_0_1__n N_131_i clk_cpu_est_11_0_3__n N_130_i \ -# N_129_i N_122_i G_86 N_121_i G_87 N_127_i state_machine_un30_clk_000_d1_n N_128_i N_148 N_118_i \ -# DTACK_SYNC_1_sqmuxa state_machine_un8_clk_000_d0_i_n N_96 state_machine_un13_clk_000_d0_i_n G_91 state_machine_un15_clk_000_d0_0_n N_89 N_100_i N_97 sm_amiga_ns_0_2__n \ -# N_90 clk_un4_clk_000_d1_i_n N_98 state_machine_un6_bgack_000_0_n N_99 state_machine_un23_clk_000_d0_i_n N_108 BG_030_c_i UDS_000_INT_0_sqmuxa state_machine_un1_clk_030_0_n \ -# UDS_000_INT_0_sqmuxa_1 state_machine_un17_clk_030_0_n state_machine_un13_clk_000_d0_1_n un1_as_030_3_0 N_168 N_148_i N_171 a_c_i_0__n N_105 state_machine_uds_000_int_7_0_n \ -# N_92 state_machine_lds_000_int_7_0_n N_106 AMIGA_BUS_ENABLE_i_m_i N_107 nEXP_SPACE_m_i N_104 state_machine_amiga_bus_enable_2_iv_i_n state_machine_un42_clk_030_n state_machine_as_030_000_sync_3_2_n \ -# state_machine_un44_clk_000_d1_n N_94_i un1_bg_030 un1_bg_030_0 N_94 size_c_i_1__n state_machine_as_030_000_sync_3_n state_machine_un44_clk_000_d1_i_n AMIGA_BUS_ENABLE_i_m N_105_i \ -# nEXP_SPACE_m N_104_i N_95 sm_amiga_ns_0_5__n state_machine_lds_000_int_7_n N_106_i state_machine_uds_000_int_7_n N_107_i DTACK_SYNC_1_sqmuxa_1 un1_as_030_4 \ -# CLK_OUT_PRE_i un1_as_030_3 N_92_0 DSACK_INT_1_sqmuxa N_90_0 state_machine_un17_clk_030_n N_89_i state_machine_un1_clk_030_n N_108_i state_machine_un23_clk_000_d0_n \ -# sm_amiga_ns_0_7__n VPA_SYNC_1_sqmuxa N_98_i VPA_SYNC_1_sqmuxa_1 N_99_i AS_000_INT_1_sqmuxa sm_amiga_ns_0_1__n state_machine_un6_bgack_000_n N_97_i clk_un4_clk_000_d1_n \ -# N_100 state_machine_un44_clk_000_d1_i_1_n state_machine_un15_clk_000_d0_n un1_bg_030_0_1 clk_cpu_est_11_3__n un1_bg_030_0_2 state_machine_un2_clk_000_n state_machine_as_030_000_sync_3_2_1_n state_machine_un13_clk_000_d0_n clk_cpu_est_11_0_1_1__n \ -# state_machine_un8_clk_000_d0_n clk_cpu_est_11_0_2_1__n N_129 N_168_1 N_122 N_168_2 N_130 N_168_3 N_127 N_168_4 \ -# N_128 N_168_5 N_121 N_168_6 state_machine_un13_clk_000_d0_2_n N_171_1 N_131 N_171_2 clk_cpu_est_11_1__n UDS_000_INT_0_sqmuxa_1_1 \ -# N_126 UDS_000_INT_0_sqmuxa_1_2 N_124 UDS_000_INT_0_sqmuxa_1_3 N_123 UDS_000_INT_0_sqmuxa_1_0 N_125 N_96_1 N_91 state_machine_un42_clk_030_1_n \ -# N_102 state_machine_un42_clk_030_2_n N_103 state_machine_un42_clk_030_3_n N_101 state_machine_un42_clk_030_4_n RW_i state_machine_un42_clk_030_5_n AS_000_INT_i AMIGA_BUS_ENABLE_i_m_1 \ -# dsack_i_1__n VPA_SYNC_1_sqmuxa_1_0 sm_amiga_i_4__n VPA_SYNC_1_sqmuxa_2 sm_amiga_i_5__n VPA_SYNC_1_sqmuxa_3 CLK_000_D0_i VPA_SYNC_1_sqmuxa_4 sm_amiga_i_3__n VPA_SYNC_1_sqmuxa_5 \ -# cpu_est_i_0__n VPA_SYNC_1_sqmuxa_6 cpu_est_i_3__n N_127_1 cpu_est_i_2__n N_128_1 VPA_D_i N_131_1 cpu_est_i_1__n clk_cpu_est_11_0_1_3__n \ -# DTACK_i N_105_1 VMA_INT_i DTACK_SYNC_1_sqmuxa_1_0 state_machine_un13_clk_000_d0_2_i_n DTACK_SYNC_1_sqmuxa_2 CLK_000_D1_i state_machine_un8_clk_000_d0_1_n VPA_SYNC_1_sqmuxa_i state_machine_un8_clk_000_d0_2_n \ -# AS_030_i state_machine_un8_clk_000_d0_3_n N_95_i state_machine_un8_clk_000_d0_4_n DTACK_SYNC_1_sqmuxa_i state_machine_un13_clk_000_d0_1_0_n N_96_i state_machine_un13_clk_000_d0_2_0_n a_i_18__n cpu_est_0_1__un3_n \ -# a_i_16__n cpu_est_0_1__un1_n a_i_19__n cpu_est_0_1__un0_n CLK_030_i cpu_est_0_3__un3_n state_machine_un42_clk_030_i_n cpu_est_0_3__un1_n sm_amiga_i_6__n cpu_est_0_3__un0_n \ -# sm_amiga_i_7__n ipl_030_0_0__un3_n AMIGA_BUS_ENABLE_i ipl_030_0_0__un1_n nEXP_SPACE_i ipl_030_0_0__un0_n sm_amiga_i_2__n ipl_030_0_1__un3_n sm_amiga_i_1__n ipl_030_0_1__un1_n \ -# DS_030_i ipl_030_0_1__un0_n AS_030_000_SYNC_i ipl_030_0_2__un3_n UDS_000_INT_0_sqmuxa_1_i ipl_030_0_2__un1_n UDS_000_INT_0_sqmuxa_i ipl_030_0_2__un0_n state_machine_un13_clk_000_d0_1_i_n uds_000_int_0_un3_n \ -# clk_clk_cnt_i_n uds_000_int_0_un1_n clk_cnt_i_0__n uds_000_int_0_un0_n CLK_000_D2_i vpa_sync_0_un3_n a_i_30__n vpa_sync_0_un1_n a_i_31__n vpa_sync_0_un0_n \ -# a_i_28__n as_000_int_0_un3_n a_i_29__n as_000_int_0_un1_n a_i_26__n as_000_int_0_un0_n a_i_27__n bgack_030_int_0_un3_n a_i_24__n bgack_030_int_0_un1_n \ -# a_i_25__n bgack_030_int_0_un0_n N_132_i vma_int_0_un3_n N_133_i vma_int_0_un1_n vma_int_0_un0_n RST_i cpu_est_0_2__un3_n FPU_CS_INT_i \ -# cpu_est_0_2__un1_n BGACK_030_INT_i cpu_est_0_2__un0_n AS_030_c dsack_int_0_1__un3_n dsack_int_0_1__un1_n dsack_int_0_1__un0_n DS_030_c bg_000_0_un3_n bg_000_0_un1_n \ -# bg_000_0_un0_n amiga_bus_enable_0_un3_n size_c_0__n amiga_bus_enable_0_un1_n amiga_bus_enable_0_un0_n size_c_1__n as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n a_c_0__n as_030_000_sync_0_un0_n \ -# fpu_cs_int_0_un3_n fpu_cs_int_0_un1_n fpu_cs_int_0_un0_n dtack_sync_0_un3_n dtack_sync_0_un1_n dtack_sync_0_un0_n lds_000_int_0_un3_n lds_000_int_0_un1_n lds_000_int_0_un0_n a_15__n \ -# a_14__n a_13__n a_12__n a_c_16__n a_11__n a_c_17__n a_10__n a_c_18__n a_9__n a_c_19__n \ -# a_8__n a_c_20__n a_7__n a_c_21__n a_6__n a_c_22__n a_5__n a_c_23__n a_4__n a_c_24__n \ -# a_3__n a_c_25__n a_2__n a_c_26__n a_1__n a_c_27__n a_c_28__n a_c_29__n a_c_30__n a_c_31__n \ -# nEXP_SPACE_c BG_030_c +#$ PINS 74 SIZE_1_ A_31_ IPL_030_2_ IPL_2_ DSACK_1_ FC_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 SIZE_0_ CLK_OSZI A_30_ CLK_DIV_OUT A_29_ CLK_EXP A_28_ FPU_CS A_27_ DTACK A_26_ AVEC A_25_ AVEC_EXP A_24_ E A_23_ VPA A_22_ VMA A_21_ RST A_20_ RESET A_19_ RW A_18_ AMIGA_BUS_ENABLE A_17_ AMIGA_BUS_DATA_DIR A_16_ AMIGA_BUS_ENABLE_LOW A_15_ CIIN A_14_ A_13_ A_12_ A_11_ A_10_ A_9_ A_8_ A_7_ A_6_ A_5_ A_4_ A_3_ A_2_ A_1_ A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ IPL_0_ DSACK_0_ FC_0_ +#$ NODES 376 BGACK_000_c CLK_030_c inst_BGACK_030_INTreg inst_FPU_CS_INTreg CLK_OSZI_c cpu_est_3_reg inst_VMA_INTreg cpu_est_0_ CLK_OUT_INTreg cpu_est_1_ \ +# inst_AS_000_INTreg inst_AS_030_000_SYNC IPL_030DFFSH_0_reg inst_DTACK_SYNC inst_VPA_D IPL_030DFFSH_1_reg inst_VPA_SYNC inst_CLK_000_D0 IPL_030DFFSH_2_reg inst_CLK_000_D1 \ +# inst_CLK_000_D2 ipl_c_0__n inst_CLK_000_D5 inst_CLK_OUT_PRE ipl_c_1__n SM_AMIGA_6_ SM_AMIGA_5_ ipl_c_2__n vcc_n_n gnd_n_n \ +# cpu_est_2_ dsack_c_1__n CLK_REF_1_ inst_UDS_000_INTreg DTACK_c inst_LDS_000_INTreg DSACK_INT_1_ SM_AMIGA_7_ AS_000_INT_1_sqmuxa state_machine_un8_clk_000_d2_n \ +# inst_CLK_000_D3 SM_AMIGA_4_ state_machine_un23_clk_000_d0_n RST_c state_machine_un6_clk_000_d4_n inst_CLK_000_D4 RESETDFFreg inst_DTACK_DMA clk_clk_cnt_n RW_c \ +# CLK_CNT_0_ CLK_CNT_1_ fc_c_0__n state_machine_un6_bgack_000_n SM_AMIGA_3_ fc_c_1__n SM_AMIGA_1_ SM_AMIGA_2_ AMIGA_BUS_ENABLEDFFreg SM_AMIGA_0_ \ +# state_machine_un7_as_000_int_n state_machine_un15_clk_000_d0_n clk_cpu_est_11_0_1__n state_machine_lds_000_int_5_n N_124_i state_machine_uds_000_int_5_n N_146_i un1_AMIGA_BUS_ENABLE_1_sqmuxa_2 N_121_i N_122_i \ +# N_66_0 N_65_0 N_145_i un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 DS_030_c_i N_63_i N_62_i state_machine_un6_clk_000_d4_i_n N_61_i CLK_OUT_PRE_0 \ +# N_60_i N_59_i N_58_i N_57_i CLK_000_D1_i N_56_i N_55_i N_52_i N_141_i N_142_i \ +# N_14_0 N_85_i N_139_i clk_cpu_est_11_1__n N_140_i clk_cpu_est_11_3__n sm_amiga_ns_0_0__n G_92 N_125_i G_96 \ +# N_138_i N_162 N_178_i N_163 clk_cpu_est_11_0_3__n N_164 N_119_i N_165 N_43_i N_30 \ +# N_117_i N_118_i N_51 N_123_i N_52 N_115_i N_55 N_116_i N_56 sm_amiga_ns_0_7__n \ +# N_57 N_98_i N_58 N_114_i N_59 N_39_0 N_60 N_94_i N_61 N_97_i \ +# N_62 sm_amiga_ns_0_5__n N_63 N_89_i N_65 N_90_i N_66 N_69 N_88_i N_72 \ +# N_73 N_86_i N_74 N_75 N_83_i N_76 N_77 N_81_i N_79 state_machine_lds_000_int_5_0_n \ +# N_81 state_machine_uds_000_int_5_0_n N_83 N_79_i N_85 N_30_0 N_86 N_165_0 N_88 N_76_i \ +# N_89 N_164_0 N_90 N_163_0 N_94 N_72_i N_97 N_73_i N_98 state_machine_un15_clk_000_d0_0_n \ +# N_114 N_162_0 N_115 state_machine_un6_bgack_000_0_n N_116 state_machine_un23_clk_000_d0_i_n N_117 N_188_1 N_118 N_188_2 \ +# N_119 N_188_3 N_120 N_188_4 N_121 N_188_5 N_122 N_188_6 N_124 N_191_1 \ +# N_125 N_191_2 N_178 state_machine_un8_clk_000_d2_1_n N_138 N_57_i_1 N_139 N_57_i_2 N_140 N_57_i_3 \ +# N_141 N_57_i_4 N_142 N_57_i_5 N_145 clk_cpu_est_11_0_1_1__n N_146 clk_cpu_est_11_0_2_1__n N_77_1 N_120_1 \ +# N_188 N_120_2 N_191 N_79_1 RW_i N_79_2 VPA_D_i N_77_1_0 CLK_000_D0_i N_75_1 \ +# cpu_est_i_0__n N_75_2 cpu_est_i_3__n N_75_3 VMA_INT_i N_75_4 cpu_est_i_1__n N_75_5 DTACK_i N_73_1 \ +# BG_030_i N_73_2 nEXP_SPACE_i N_72_1 sm_amiga_i_3__n N_72_2 AS_000_INT_i sm_amiga_ns_0_1_0__n sm_amiga_i_6__n clk_cpu_est_11_0_1_3__n \ +# cpu_est_i_2__n N_138_1 AMIGA_BUS_ENABLE_i N_119_1 AS_030_i N_118_1 sm_amiga_i_4__n N_117_1 sm_amiga_i_5__n N_97_1 \ +# state_machine_un8_clk_000_d2_i_n N_81_1 sm_amiga_i_7__n state_machine_uds_000_int_5_0_m2_un3_n a_i_0__n state_machine_uds_000_int_5_0_m2_un1_n size_i_1__n state_machine_uds_000_int_5_0_m2_un0_n dsack_i_1__n vpa_sync_0_un3_n \ +# clk_clk_cnt_i_n vpa_sync_0_un1_n clk_cnt_i_0__n vpa_sync_0_un0_n CLK_000_D2_i amiga_bus_enable_0_un3_n AS_030_000_SYNC_i amiga_bus_enable_0_un1_n a_i_30__n amiga_bus_enable_0_un0_n \ +# a_i_31__n uds_000_int_0_un3_n a_i_28__n uds_000_int_0_un1_n a_i_29__n uds_000_int_0_un0_n a_i_26__n lds_000_int_0_un3_n a_i_27__n lds_000_int_0_un1_n \ +# a_i_24__n lds_000_int_0_un0_n a_i_25__n vma_int_0_un3_n a_i_19__n vma_int_0_un1_n a_i_16__n vma_int_0_un0_n a_i_18__n bg_000_0_un3_n \ +# N_137_i bg_000_0_un1_n bg_000_0_un0_n RST_i bgack_030_int_0_un3_n N_120_i bgack_030_int_0_un1_n N_75_i bgack_030_int_0_un0_n N_74_i \ +# as_000_int_0_un3_n N_77_i as_000_int_0_un1_n FPU_CS_INT_i as_000_int_0_un0_n BGACK_030_INT_i cpu_est_0_1__un3_n CLK_000_D5_i cpu_est_0_1__un1_n AS_030_c \ +# cpu_est_0_1__un0_n cpu_est_0_2__un3_n cpu_est_0_2__un1_n DS_030_c cpu_est_0_2__un0_n cpu_est_0_3__un3_n cpu_est_0_3__un1_n cpu_est_0_3__un0_n size_c_0__n ipl_030_0_0__un3_n \ +# ipl_030_0_0__un1_n size_c_1__n ipl_030_0_0__un0_n ipl_030_0_1__un3_n a_c_0__n ipl_030_0_1__un1_n ipl_030_0_1__un0_n ipl_030_0_2__un3_n ipl_030_0_2__un1_n ipl_030_0_2__un0_n \ +# as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n dtack_sync_0_un3_n dtack_sync_0_un1_n dtack_sync_0_un0_n fpu_cs_int_0_un3_n fpu_cs_int_0_un1_n fpu_cs_int_0_un0_n dsack_int_0_1__un3_n \ +# dsack_int_0_1__un1_n dsack_int_0_1__un0_n a_c_16__n a_15__n a_c_17__n a_14__n a_c_18__n a_13__n a_c_19__n a_12__n \ +# a_c_20__n a_11__n a_c_21__n a_10__n a_c_22__n a_9__n a_c_23__n a_8__n a_c_24__n a_7__n \ +# a_c_25__n a_6__n a_c_26__n a_5__n a_c_27__n a_4__n a_c_28__n a_3__n a_c_29__n a_2__n \ +# a_c_30__n a_1__n a_c_31__n nEXP_SPACE_c BG_030_c BG_000DFFSHreg .model bus68030 .inputs SIZE_1_.BLIF A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF AS_030.BLIF DS_030.BLIF nEXP_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF \ CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF VPA.BLIF RST.BLIF RW.BLIF SIZE_0_.BLIF A_30_.BLIF A_29_.BLIF \ A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF \ A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF A_15_.BLIF A_14_.BLIF A_13_.BLIF A_12_.BLIF A_11_.BLIF \ A_10_.BLIF A_9_.BLIF A_8_.BLIF A_7_.BLIF A_6_.BLIF A_5_.BLIF A_4_.BLIF A_3_.BLIF A_2_.BLIF \ - A_1_.BLIF A_0_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF DSACK_1_.BLIF DTACK.BLIF DSACK_0_.BLIF BG_000DFFSHreg.BLIF BGACK_000_c.BLIF CLK_030_c.BLIF inst_BGACK_030_INTreg.BLIF \ - CLK_000_c.BLIF inst_FPU_CS_INTreg.BLIF cpu_est_3_reg.BLIF CLK_OSZI_c.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF CLK_OUT_INTreg.BLIF inst_AS_000_INTreg.BLIF \ - inst_AS_030_000_SYNC.BLIF inst_DTACK_SYNC.BLIF IPL_030DFFSH_0_reg.BLIF inst_VPA_D.BLIF inst_VPA_SYNC.BLIF IPL_030DFFSH_1_reg.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF IPL_030DFFSH_2_reg.BLIF \ - inst_CLK_000_D2.BLIF inst_CLK_OUT_PRE.BLIF ipl_c_0__n.BLIF SM_AMIGA_6_.BLIF vcc_n_n.BLIF ipl_c_1__n.BLIF gnd_n_n.BLIF cpu_est_2_.BLIF ipl_c_2__n.BLIF \ - CLK_REF_0_.BLIF CLK_REF_1_.BLIF SM_AMIGA_7_.BLIF dsack_c_1__n.BLIF inst_UDS_000_INTreg.BLIF inst_LDS_000_INTreg.BLIF DTACK_c.BLIF DSACK_INT_1_.BLIF SM_AMIGA_4_.BLIF \ - SM_AMIGA_1_.BLIF inst_DTACK_DMA.BLIF clk_clk_cnt_n.BLIF CLK_CNT_0_.BLIF CLK_CNT_1_.BLIF state_machine_un14_as_000_int_n.BLIF RST_c.BLIF SM_AMIGA_3_.BLIF RESETDFFreg.BLIF \ - SM_AMIGA_5_.BLIF RW_c.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_0_.BLIF fc_c_0__n.BLIF fc_c_1__n.BLIF AMIGA_BUS_ENABLEDFFreg.BLIF N_101_i.BLIF N_102_i.BLIF \ - N_103_i.BLIF CLK_OUT_PRE_0.BLIF cpu_est_0_0_.BLIF N_91_0.BLIF N_125_i.BLIF N_123_i.BLIF N_124_i.BLIF N_126_i.BLIF clk_cpu_est_11_0_1__n.BLIF \ - N_131_i.BLIF clk_cpu_est_11_0_3__n.BLIF N_130_i.BLIF N_129_i.BLIF N_122_i.BLIF G_86.BLIF N_121_i.BLIF G_87.BLIF N_127_i.BLIF \ - state_machine_un30_clk_000_d1_n.BLIF N_128_i.BLIF N_148.BLIF N_118_i.BLIF DTACK_SYNC_1_sqmuxa.BLIF state_machine_un8_clk_000_d0_i_n.BLIF N_96.BLIF state_machine_un13_clk_000_d0_i_n.BLIF G_91.BLIF \ - state_machine_un15_clk_000_d0_0_n.BLIF N_89.BLIF N_100_i.BLIF N_97.BLIF sm_amiga_ns_0_2__n.BLIF N_90.BLIF clk_un4_clk_000_d1_i_n.BLIF N_98.BLIF state_machine_un6_bgack_000_0_n.BLIF \ - N_99.BLIF state_machine_un23_clk_000_d0_i_n.BLIF N_108.BLIF BG_030_c_i.BLIF UDS_000_INT_0_sqmuxa.BLIF state_machine_un1_clk_030_0_n.BLIF UDS_000_INT_0_sqmuxa_1.BLIF state_machine_un17_clk_030_0_n.BLIF state_machine_un13_clk_000_d0_1_n.BLIF \ - un1_as_030_3_0.BLIF N_168.BLIF N_148_i.BLIF N_171.BLIF a_c_i_0__n.BLIF N_105.BLIF state_machine_uds_000_int_7_0_n.BLIF N_92.BLIF state_machine_lds_000_int_7_0_n.BLIF \ - N_106.BLIF AMIGA_BUS_ENABLE_i_m_i.BLIF N_107.BLIF nEXP_SPACE_m_i.BLIF N_104.BLIF state_machine_amiga_bus_enable_2_iv_i_n.BLIF state_machine_un42_clk_030_n.BLIF state_machine_as_030_000_sync_3_2_n.BLIF state_machine_un44_clk_000_d1_n.BLIF \ - N_94_i.BLIF un1_bg_030.BLIF un1_bg_030_0.BLIF N_94.BLIF size_c_i_1__n.BLIF state_machine_as_030_000_sync_3_n.BLIF state_machine_un44_clk_000_d1_i_n.BLIF AMIGA_BUS_ENABLE_i_m.BLIF N_105_i.BLIF \ - nEXP_SPACE_m.BLIF N_104_i.BLIF N_95.BLIF sm_amiga_ns_0_5__n.BLIF state_machine_lds_000_int_7_n.BLIF N_106_i.BLIF state_machine_uds_000_int_7_n.BLIF N_107_i.BLIF DTACK_SYNC_1_sqmuxa_1.BLIF \ - un1_as_030_4.BLIF CLK_OUT_PRE_i.BLIF un1_as_030_3.BLIF N_92_0.BLIF DSACK_INT_1_sqmuxa.BLIF N_90_0.BLIF state_machine_un17_clk_030_n.BLIF N_89_i.BLIF state_machine_un1_clk_030_n.BLIF \ - N_108_i.BLIF state_machine_un23_clk_000_d0_n.BLIF sm_amiga_ns_0_7__n.BLIF VPA_SYNC_1_sqmuxa.BLIF N_98_i.BLIF VPA_SYNC_1_sqmuxa_1.BLIF N_99_i.BLIF AS_000_INT_1_sqmuxa.BLIF sm_amiga_ns_0_1__n.BLIF \ - state_machine_un6_bgack_000_n.BLIF N_97_i.BLIF clk_un4_clk_000_d1_n.BLIF N_100.BLIF state_machine_un44_clk_000_d1_i_1_n.BLIF state_machine_un15_clk_000_d0_n.BLIF un1_bg_030_0_1.BLIF clk_cpu_est_11_3__n.BLIF un1_bg_030_0_2.BLIF \ - state_machine_un2_clk_000_n.BLIF state_machine_as_030_000_sync_3_2_1_n.BLIF state_machine_un13_clk_000_d0_n.BLIF clk_cpu_est_11_0_1_1__n.BLIF state_machine_un8_clk_000_d0_n.BLIF clk_cpu_est_11_0_2_1__n.BLIF N_129.BLIF N_168_1.BLIF N_122.BLIF \ - N_168_2.BLIF N_130.BLIF N_168_3.BLIF N_127.BLIF N_168_4.BLIF N_128.BLIF N_168_5.BLIF N_121.BLIF N_168_6.BLIF \ - state_machine_un13_clk_000_d0_2_n.BLIF N_171_1.BLIF N_131.BLIF N_171_2.BLIF clk_cpu_est_11_1__n.BLIF UDS_000_INT_0_sqmuxa_1_1.BLIF N_126.BLIF UDS_000_INT_0_sqmuxa_1_2.BLIF N_124.BLIF \ - UDS_000_INT_0_sqmuxa_1_3.BLIF N_123.BLIF UDS_000_INT_0_sqmuxa_1_0.BLIF N_125.BLIF N_96_1.BLIF N_91.BLIF state_machine_un42_clk_030_1_n.BLIF N_102.BLIF state_machine_un42_clk_030_2_n.BLIF \ - N_103.BLIF state_machine_un42_clk_030_3_n.BLIF N_101.BLIF state_machine_un42_clk_030_4_n.BLIF RW_i.BLIF state_machine_un42_clk_030_5_n.BLIF AS_000_INT_i.BLIF AMIGA_BUS_ENABLE_i_m_1.BLIF dsack_i_1__n.BLIF \ - VPA_SYNC_1_sqmuxa_1_0.BLIF sm_amiga_i_4__n.BLIF VPA_SYNC_1_sqmuxa_2.BLIF sm_amiga_i_5__n.BLIF VPA_SYNC_1_sqmuxa_3.BLIF CLK_000_D0_i.BLIF VPA_SYNC_1_sqmuxa_4.BLIF sm_amiga_i_3__n.BLIF VPA_SYNC_1_sqmuxa_5.BLIF \ - cpu_est_i_0__n.BLIF VPA_SYNC_1_sqmuxa_6.BLIF cpu_est_i_3__n.BLIF N_127_1.BLIF cpu_est_i_2__n.BLIF N_128_1.BLIF VPA_D_i.BLIF N_131_1.BLIF cpu_est_i_1__n.BLIF \ - clk_cpu_est_11_0_1_3__n.BLIF DTACK_i.BLIF N_105_1.BLIF VMA_INT_i.BLIF DTACK_SYNC_1_sqmuxa_1_0.BLIF state_machine_un13_clk_000_d0_2_i_n.BLIF DTACK_SYNC_1_sqmuxa_2.BLIF CLK_000_D1_i.BLIF state_machine_un8_clk_000_d0_1_n.BLIF \ - VPA_SYNC_1_sqmuxa_i.BLIF state_machine_un8_clk_000_d0_2_n.BLIF AS_030_i.BLIF state_machine_un8_clk_000_d0_3_n.BLIF N_95_i.BLIF state_machine_un8_clk_000_d0_4_n.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF state_machine_un13_clk_000_d0_1_0_n.BLIF N_96_i.BLIF \ - state_machine_un13_clk_000_d0_2_0_n.BLIF a_i_18__n.BLIF cpu_est_0_1__un3_n.BLIF a_i_16__n.BLIF cpu_est_0_1__un1_n.BLIF a_i_19__n.BLIF cpu_est_0_1__un0_n.BLIF CLK_030_i.BLIF cpu_est_0_3__un3_n.BLIF \ - state_machine_un42_clk_030_i_n.BLIF cpu_est_0_3__un1_n.BLIF sm_amiga_i_6__n.BLIF cpu_est_0_3__un0_n.BLIF sm_amiga_i_7__n.BLIF ipl_030_0_0__un3_n.BLIF AMIGA_BUS_ENABLE_i.BLIF ipl_030_0_0__un1_n.BLIF nEXP_SPACE_i.BLIF \ - ipl_030_0_0__un0_n.BLIF sm_amiga_i_2__n.BLIF ipl_030_0_1__un3_n.BLIF sm_amiga_i_1__n.BLIF ipl_030_0_1__un1_n.BLIF DS_030_i.BLIF ipl_030_0_1__un0_n.BLIF AS_030_000_SYNC_i.BLIF ipl_030_0_2__un3_n.BLIF \ - UDS_000_INT_0_sqmuxa_1_i.BLIF ipl_030_0_2__un1_n.BLIF UDS_000_INT_0_sqmuxa_i.BLIF ipl_030_0_2__un0_n.BLIF state_machine_un13_clk_000_d0_1_i_n.BLIF uds_000_int_0_un3_n.BLIF clk_clk_cnt_i_n.BLIF uds_000_int_0_un1_n.BLIF clk_cnt_i_0__n.BLIF \ - uds_000_int_0_un0_n.BLIF CLK_000_D2_i.BLIF vpa_sync_0_un3_n.BLIF a_i_30__n.BLIF vpa_sync_0_un1_n.BLIF a_i_31__n.BLIF vpa_sync_0_un0_n.BLIF a_i_28__n.BLIF as_000_int_0_un3_n.BLIF \ - a_i_29__n.BLIF as_000_int_0_un1_n.BLIF a_i_26__n.BLIF as_000_int_0_un0_n.BLIF a_i_27__n.BLIF bgack_030_int_0_un3_n.BLIF a_i_24__n.BLIF bgack_030_int_0_un1_n.BLIF a_i_25__n.BLIF \ - bgack_030_int_0_un0_n.BLIF N_132_i.BLIF vma_int_0_un3_n.BLIF N_133_i.BLIF vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF RST_i.BLIF cpu_est_0_2__un3_n.BLIF FPU_CS_INT_i.BLIF \ - cpu_est_0_2__un1_n.BLIF BGACK_030_INT_i.BLIF cpu_est_0_2__un0_n.BLIF AS_030_c.BLIF dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF DS_030_c.BLIF bg_000_0_un3_n.BLIF \ - bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF amiga_bus_enable_0_un3_n.BLIF size_c_0__n.BLIF amiga_bus_enable_0_un1_n.BLIF amiga_bus_enable_0_un0_n.BLIF size_c_1__n.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un1_n.BLIF \ - a_c_0__n.BLIF as_030_000_sync_0_un0_n.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF dtack_sync_0_un3_n.BLIF dtack_sync_0_un1_n.BLIF dtack_sync_0_un0_n.BLIF lds_000_int_0_un3_n.BLIF \ - lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF a_15__n.BLIF a_14__n.BLIF a_13__n.BLIF a_12__n.BLIF a_c_16__n.BLIF a_11__n.BLIF a_c_17__n.BLIF \ - a_10__n.BLIF a_c_18__n.BLIF a_9__n.BLIF a_c_19__n.BLIF a_8__n.BLIF a_c_20__n.BLIF a_7__n.BLIF a_c_21__n.BLIF a_6__n.BLIF \ - a_c_22__n.BLIF a_5__n.BLIF a_c_23__n.BLIF a_4__n.BLIF a_c_24__n.BLIF a_3__n.BLIF a_c_25__n.BLIF a_2__n.BLIF a_c_26__n.BLIF \ - a_1__n.BLIF a_c_27__n.BLIF a_c_28__n.BLIF a_c_29__n.BLIF a_c_30__n.BLIF a_c_31__n.BLIF nEXP_SPACE_c.BLIF BG_030_c.BLIF DSACK_1_.PIN \ - DTACK.PIN + A_1_.BLIF A_0_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF DSACK_1_.BLIF DTACK.BLIF DSACK_0_.BLIF BGACK_000_c.BLIF CLK_030_c.BLIF inst_BGACK_030_INTreg.BLIF inst_FPU_CS_INTreg.BLIF \ + CLK_OSZI_c.BLIF cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF CLK_OUT_INTreg.BLIF cpu_est_1_.BLIF inst_AS_000_INTreg.BLIF inst_AS_030_000_SYNC.BLIF IPL_030DFFSH_0_reg.BLIF \ + inst_DTACK_SYNC.BLIF inst_VPA_D.BLIF IPL_030DFFSH_1_reg.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D0.BLIF IPL_030DFFSH_2_reg.BLIF inst_CLK_000_D1.BLIF inst_CLK_000_D2.BLIF ipl_c_0__n.BLIF \ + inst_CLK_000_D5.BLIF inst_CLK_OUT_PRE.BLIF ipl_c_1__n.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_5_.BLIF ipl_c_2__n.BLIF vcc_n_n.BLIF gnd_n_n.BLIF cpu_est_2_.BLIF \ + dsack_c_1__n.BLIF CLK_REF_1_.BLIF inst_UDS_000_INTreg.BLIF DTACK_c.BLIF inst_LDS_000_INTreg.BLIF DSACK_INT_1_.BLIF SM_AMIGA_7_.BLIF AS_000_INT_1_sqmuxa.BLIF state_machine_un8_clk_000_d2_n.BLIF \ + inst_CLK_000_D3.BLIF SM_AMIGA_4_.BLIF state_machine_un23_clk_000_d0_n.BLIF RST_c.BLIF state_machine_un6_clk_000_d4_n.BLIF inst_CLK_000_D4.BLIF RESETDFFreg.BLIF inst_DTACK_DMA.BLIF clk_clk_cnt_n.BLIF \ + RW_c.BLIF CLK_CNT_0_.BLIF CLK_CNT_1_.BLIF fc_c_0__n.BLIF state_machine_un6_bgack_000_n.BLIF SM_AMIGA_3_.BLIF fc_c_1__n.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_2_.BLIF \ + AMIGA_BUS_ENABLEDFFreg.BLIF SM_AMIGA_0_.BLIF state_machine_un7_as_000_int_n.BLIF state_machine_un15_clk_000_d0_n.BLIF clk_cpu_est_11_0_1__n.BLIF state_machine_lds_000_int_5_n.BLIF N_124_i.BLIF state_machine_uds_000_int_5_n.BLIF N_146_i.BLIF \ + un1_AMIGA_BUS_ENABLE_1_sqmuxa_2.BLIF N_121_i.BLIF N_122_i.BLIF N_66_0.BLIF N_65_0.BLIF N_145_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0.BLIF DS_030_c_i.BLIF N_63_i.BLIF \ + N_62_i.BLIF state_machine_un6_clk_000_d4_i_n.BLIF N_61_i.BLIF CLK_OUT_PRE_0.BLIF N_60_i.BLIF N_59_i.BLIF N_58_i.BLIF N_57_i.BLIF CLK_000_D1_i.BLIF \ + N_56_i.BLIF N_55_i.BLIF N_52_i.BLIF N_141_i.BLIF N_142_i.BLIF N_14_0.BLIF N_85_i.BLIF N_139_i.BLIF clk_cpu_est_11_1__n.BLIF \ + N_140_i.BLIF clk_cpu_est_11_3__n.BLIF sm_amiga_ns_0_0__n.BLIF G_92.BLIF N_125_i.BLIF G_96.BLIF N_138_i.BLIF N_162.BLIF N_178_i.BLIF \ + N_163.BLIF clk_cpu_est_11_0_3__n.BLIF N_164.BLIF N_119_i.BLIF N_165.BLIF N_43_i.BLIF N_30.BLIF N_117_i.BLIF N_118_i.BLIF \ + N_51.BLIF N_123_i.BLIF N_52.BLIF N_115_i.BLIF N_55.BLIF N_116_i.BLIF N_56.BLIF sm_amiga_ns_0_7__n.BLIF N_57.BLIF \ + N_98_i.BLIF N_58.BLIF N_114_i.BLIF N_59.BLIF N_39_0.BLIF N_60.BLIF N_94_i.BLIF N_61.BLIF N_97_i.BLIF \ + N_62.BLIF sm_amiga_ns_0_5__n.BLIF N_63.BLIF N_89_i.BLIF N_65.BLIF N_90_i.BLIF N_66.BLIF N_69.BLIF N_88_i.BLIF \ + N_72.BLIF N_73.BLIF N_86_i.BLIF N_74.BLIF N_75.BLIF N_83_i.BLIF N_76.BLIF N_77.BLIF N_81_i.BLIF \ + N_79.BLIF state_machine_lds_000_int_5_0_n.BLIF N_81.BLIF state_machine_uds_000_int_5_0_n.BLIF N_83.BLIF N_79_i.BLIF N_85.BLIF N_30_0.BLIF N_86.BLIF \ + N_165_0.BLIF N_88.BLIF N_76_i.BLIF N_89.BLIF N_164_0.BLIF N_90.BLIF N_163_0.BLIF N_94.BLIF N_72_i.BLIF \ + N_97.BLIF N_73_i.BLIF N_98.BLIF state_machine_un15_clk_000_d0_0_n.BLIF N_114.BLIF N_162_0.BLIF N_115.BLIF state_machine_un6_bgack_000_0_n.BLIF N_116.BLIF \ + state_machine_un23_clk_000_d0_i_n.BLIF N_117.BLIF N_188_1.BLIF N_118.BLIF N_188_2.BLIF N_119.BLIF N_188_3.BLIF N_120.BLIF N_188_4.BLIF \ + N_121.BLIF N_188_5.BLIF N_122.BLIF N_188_6.BLIF N_124.BLIF N_191_1.BLIF N_125.BLIF N_191_2.BLIF N_178.BLIF \ + state_machine_un8_clk_000_d2_1_n.BLIF N_138.BLIF N_57_i_1.BLIF N_139.BLIF N_57_i_2.BLIF N_140.BLIF N_57_i_3.BLIF N_141.BLIF N_57_i_4.BLIF \ + N_142.BLIF N_57_i_5.BLIF N_145.BLIF clk_cpu_est_11_0_1_1__n.BLIF N_146.BLIF clk_cpu_est_11_0_2_1__n.BLIF N_77_1.BLIF N_120_1.BLIF N_188.BLIF \ + N_120_2.BLIF N_191.BLIF N_79_1.BLIF RW_i.BLIF N_79_2.BLIF VPA_D_i.BLIF N_77_1_0.BLIF CLK_000_D0_i.BLIF N_75_1.BLIF \ + cpu_est_i_0__n.BLIF N_75_2.BLIF cpu_est_i_3__n.BLIF N_75_3.BLIF VMA_INT_i.BLIF N_75_4.BLIF cpu_est_i_1__n.BLIF N_75_5.BLIF DTACK_i.BLIF \ + N_73_1.BLIF BG_030_i.BLIF N_73_2.BLIF nEXP_SPACE_i.BLIF N_72_1.BLIF sm_amiga_i_3__n.BLIF N_72_2.BLIF AS_000_INT_i.BLIF sm_amiga_ns_0_1_0__n.BLIF \ + sm_amiga_i_6__n.BLIF clk_cpu_est_11_0_1_3__n.BLIF cpu_est_i_2__n.BLIF N_138_1.BLIF AMIGA_BUS_ENABLE_i.BLIF N_119_1.BLIF AS_030_i.BLIF N_118_1.BLIF sm_amiga_i_4__n.BLIF \ + N_117_1.BLIF sm_amiga_i_5__n.BLIF N_97_1.BLIF state_machine_un8_clk_000_d2_i_n.BLIF N_81_1.BLIF sm_amiga_i_7__n.BLIF state_machine_uds_000_int_5_0_m2_un3_n.BLIF a_i_0__n.BLIF state_machine_uds_000_int_5_0_m2_un1_n.BLIF \ + size_i_1__n.BLIF state_machine_uds_000_int_5_0_m2_un0_n.BLIF dsack_i_1__n.BLIF vpa_sync_0_un3_n.BLIF clk_clk_cnt_i_n.BLIF vpa_sync_0_un1_n.BLIF clk_cnt_i_0__n.BLIF vpa_sync_0_un0_n.BLIF CLK_000_D2_i.BLIF \ + amiga_bus_enable_0_un3_n.BLIF AS_030_000_SYNC_i.BLIF amiga_bus_enable_0_un1_n.BLIF a_i_30__n.BLIF amiga_bus_enable_0_un0_n.BLIF a_i_31__n.BLIF uds_000_int_0_un3_n.BLIF a_i_28__n.BLIF uds_000_int_0_un1_n.BLIF \ + a_i_29__n.BLIF uds_000_int_0_un0_n.BLIF a_i_26__n.BLIF lds_000_int_0_un3_n.BLIF a_i_27__n.BLIF lds_000_int_0_un1_n.BLIF a_i_24__n.BLIF lds_000_int_0_un0_n.BLIF a_i_25__n.BLIF \ + vma_int_0_un3_n.BLIF a_i_19__n.BLIF vma_int_0_un1_n.BLIF a_i_16__n.BLIF vma_int_0_un0_n.BLIF a_i_18__n.BLIF bg_000_0_un3_n.BLIF N_137_i.BLIF bg_000_0_un1_n.BLIF \ + bg_000_0_un0_n.BLIF RST_i.BLIF bgack_030_int_0_un3_n.BLIF N_120_i.BLIF bgack_030_int_0_un1_n.BLIF N_75_i.BLIF bgack_030_int_0_un0_n.BLIF N_74_i.BLIF as_000_int_0_un3_n.BLIF \ + N_77_i.BLIF as_000_int_0_un1_n.BLIF FPU_CS_INT_i.BLIF as_000_int_0_un0_n.BLIF BGACK_030_INT_i.BLIF cpu_est_0_1__un3_n.BLIF CLK_000_D5_i.BLIF cpu_est_0_1__un1_n.BLIF AS_030_c.BLIF \ + cpu_est_0_1__un0_n.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un1_n.BLIF DS_030_c.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF size_c_0__n.BLIF \ + ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un1_n.BLIF size_c_1__n.BLIF ipl_030_0_0__un0_n.BLIF ipl_030_0_1__un3_n.BLIF a_c_0__n.BLIF ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF ipl_030_0_2__un3_n.BLIF \ + ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF dtack_sync_0_un3_n.BLIF dtack_sync_0_un1_n.BLIF dtack_sync_0_un0_n.BLIF fpu_cs_int_0_un3_n.BLIF \ + fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF a_c_16__n.BLIF a_15__n.BLIF a_c_17__n.BLIF a_14__n.BLIF \ + a_c_18__n.BLIF a_13__n.BLIF a_c_19__n.BLIF a_12__n.BLIF a_c_20__n.BLIF a_11__n.BLIF a_c_21__n.BLIF a_10__n.BLIF a_c_22__n.BLIF \ + a_9__n.BLIF a_c_23__n.BLIF a_8__n.BLIF a_c_24__n.BLIF a_7__n.BLIF a_c_25__n.BLIF a_6__n.BLIF a_c_26__n.BLIF a_5__n.BLIF \ + a_c_27__n.BLIF a_4__n.BLIF a_c_28__n.BLIF a_3__n.BLIF a_c_29__n.BLIF a_2__n.BLIF a_c_30__n.BLIF a_1__n.BLIF a_c_31__n.BLIF \ + nEXP_SPACE_c.BLIF BG_030_c.BLIF BG_000DFFSHreg.BLIF DSACK_1_.PIN DTACK.PIN .outputs IPL_030_2_ AS_000 UDS_000 LDS_000 BERR BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS AVEC \ - AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_6_.D \ - SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR \ - SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR cpu_est_1_.D cpu_est_1_.C \ - cpu_est_2_.D cpu_est_2_.C cpu_est_3_reg.D cpu_est_3_reg.C IPL_030DFFSH_0_reg.D IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP IPL_030DFFSH_1_reg.D IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D \ - IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D SM_AMIGA_7_.C SM_AMIGA_7_.AP inst_VMA_INTreg.D inst_VMA_INTreg.C inst_VMA_INTreg.AP inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP \ - inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C CLK_CNT_0_.D CLK_CNT_0_.C CLK_CNT_1_.D CLK_CNT_1_.C cpu_est_0_.D cpu_est_0_.C inst_VPA_SYNC.D inst_VPA_SYNC.C inst_VPA_SYNC.AP \ - inst_FPU_CS_INTreg.D inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_AS_000_INTreg.D inst_AS_000_INTreg.C inst_AS_000_INTreg.AP AMIGA_BUS_ENABLEDFFreg.D AMIGA_BUS_ENABLEDFFreg.C \ - BG_000DFFSHreg.D BG_000DFFSHreg.C BG_000DFFSHreg.AP DSACK_INT_1_.D DSACK_INT_1_.C DSACK_INT_1_.AP inst_UDS_000_INTreg.D inst_UDS_000_INTreg.C inst_UDS_000_INTreg.AP inst_LDS_000_INTreg.D inst_LDS_000_INTreg.C \ - inst_LDS_000_INTreg.AP inst_DTACK_SYNC.D inst_DTACK_SYNC.C inst_DTACK_SYNC.AP CLK_OUT_INTreg.D CLK_OUT_INTreg.C inst_DTACK_DMA.D inst_DTACK_DMA.C inst_DTACK_DMA.AP inst_CLK_000_D2.D inst_CLK_000_D2.C \ - inst_VPA_D.D inst_VPA_D.C inst_CLK_000_D0.D inst_CLK_000_D0.C RESETDFFreg.D RESETDFFreg.C inst_CLK_000_D1.D inst_CLK_000_D1.C CLK_REF_0_.D CLK_REF_0_.LH CLK_REF_0_.AP \ - CLK_REF_1_.D CLK_REF_1_.LH CLK_REF_1_.AR cpu_est_0_0_.X1 cpu_est_0_0_.X2 CLK_OUT_PRE_0.X1 CLK_OUT_PRE_0.X2 G_91.X1 G_91.X2 G_87.X1 G_87.X2 \ - G_86.X1 G_86.X2 DSACK_1_ DTACK DSACK_0_ BGACK_000_c CLK_030_c CLK_000_c CLK_OSZI_c ipl_c_0__n vcc_n_n ipl_c_1__n gnd_n_n ipl_c_2__n \ - dsack_c_1__n DTACK_c clk_clk_cnt_n state_machine_un14_as_000_int_n RST_c RW_c fc_c_0__n fc_c_1__n N_101_i N_102_i N_103_i \ - N_91_0 N_125_i N_123_i N_124_i N_126_i clk_cpu_est_11_0_1__n N_131_i clk_cpu_est_11_0_3__n N_130_i N_129_i N_122_i \ - N_121_i N_127_i state_machine_un30_clk_000_d1_n N_128_i N_148 N_118_i DTACK_SYNC_1_sqmuxa state_machine_un8_clk_000_d0_i_n N_96 state_machine_un13_clk_000_d0_i_n state_machine_un15_clk_000_d0_0_n \ - N_89 N_100_i N_97 sm_amiga_ns_0_2__n N_90 clk_un4_clk_000_d1_i_n N_98 state_machine_un6_bgack_000_0_n N_99 state_machine_un23_clk_000_d0_i_n N_108 \ - BG_030_c_i UDS_000_INT_0_sqmuxa state_machine_un1_clk_030_0_n UDS_000_INT_0_sqmuxa_1 state_machine_un17_clk_030_0_n state_machine_un13_clk_000_d0_1_n un1_as_030_3_0 N_168 N_148_i N_171 a_c_i_0__n \ - N_105 state_machine_uds_000_int_7_0_n N_92 state_machine_lds_000_int_7_0_n N_106 AMIGA_BUS_ENABLE_i_m_i N_107 nEXP_SPACE_m_i N_104 state_machine_amiga_bus_enable_2_iv_i_n state_machine_un42_clk_030_n \ - state_machine_as_030_000_sync_3_2_n state_machine_un44_clk_000_d1_n N_94_i un1_bg_030 un1_bg_030_0 N_94 size_c_i_1__n state_machine_as_030_000_sync_3_n state_machine_un44_clk_000_d1_i_n AMIGA_BUS_ENABLE_i_m N_105_i \ - nEXP_SPACE_m N_104_i N_95 sm_amiga_ns_0_5__n state_machine_lds_000_int_7_n N_106_i state_machine_uds_000_int_7_n N_107_i DTACK_SYNC_1_sqmuxa_1 un1_as_030_4 CLK_OUT_PRE_i \ - un1_as_030_3 N_92_0 DSACK_INT_1_sqmuxa N_90_0 state_machine_un17_clk_030_n N_89_i state_machine_un1_clk_030_n N_108_i state_machine_un23_clk_000_d0_n sm_amiga_ns_0_7__n VPA_SYNC_1_sqmuxa \ - N_98_i VPA_SYNC_1_sqmuxa_1 N_99_i AS_000_INT_1_sqmuxa sm_amiga_ns_0_1__n state_machine_un6_bgack_000_n N_97_i clk_un4_clk_000_d1_n N_100 state_machine_un44_clk_000_d1_i_1_n state_machine_un15_clk_000_d0_n \ - un1_bg_030_0_1 clk_cpu_est_11_3__n un1_bg_030_0_2 state_machine_un2_clk_000_n state_machine_as_030_000_sync_3_2_1_n state_machine_un13_clk_000_d0_n clk_cpu_est_11_0_1_1__n state_machine_un8_clk_000_d0_n clk_cpu_est_11_0_2_1__n N_129 N_168_1 \ - N_122 N_168_2 N_130 N_168_3 N_127 N_168_4 N_128 N_168_5 N_121 N_168_6 state_machine_un13_clk_000_d0_2_n \ - N_171_1 N_131 N_171_2 clk_cpu_est_11_1__n UDS_000_INT_0_sqmuxa_1_1 N_126 UDS_000_INT_0_sqmuxa_1_2 N_124 UDS_000_INT_0_sqmuxa_1_3 N_123 UDS_000_INT_0_sqmuxa_1_0 \ - N_125 N_96_1 N_91 state_machine_un42_clk_030_1_n N_102 state_machine_un42_clk_030_2_n N_103 state_machine_un42_clk_030_3_n N_101 state_machine_un42_clk_030_4_n RW_i \ - state_machine_un42_clk_030_5_n AS_000_INT_i AMIGA_BUS_ENABLE_i_m_1 dsack_i_1__n VPA_SYNC_1_sqmuxa_1_0 sm_amiga_i_4__n VPA_SYNC_1_sqmuxa_2 sm_amiga_i_5__n VPA_SYNC_1_sqmuxa_3 CLK_000_D0_i VPA_SYNC_1_sqmuxa_4 \ - sm_amiga_i_3__n VPA_SYNC_1_sqmuxa_5 cpu_est_i_0__n VPA_SYNC_1_sqmuxa_6 cpu_est_i_3__n N_127_1 cpu_est_i_2__n N_128_1 VPA_D_i N_131_1 cpu_est_i_1__n \ - clk_cpu_est_11_0_1_3__n DTACK_i N_105_1 VMA_INT_i DTACK_SYNC_1_sqmuxa_1_0 state_machine_un13_clk_000_d0_2_i_n DTACK_SYNC_1_sqmuxa_2 CLK_000_D1_i state_machine_un8_clk_000_d0_1_n VPA_SYNC_1_sqmuxa_i state_machine_un8_clk_000_d0_2_n \ - AS_030_i state_machine_un8_clk_000_d0_3_n N_95_i state_machine_un8_clk_000_d0_4_n DTACK_SYNC_1_sqmuxa_i state_machine_un13_clk_000_d0_1_0_n N_96_i state_machine_un13_clk_000_d0_2_0_n a_i_18__n cpu_est_0_1__un3_n a_i_16__n \ - cpu_est_0_1__un1_n a_i_19__n cpu_est_0_1__un0_n CLK_030_i cpu_est_0_3__un3_n state_machine_un42_clk_030_i_n cpu_est_0_3__un1_n sm_amiga_i_6__n cpu_est_0_3__un0_n sm_amiga_i_7__n ipl_030_0_0__un3_n \ - AMIGA_BUS_ENABLE_i ipl_030_0_0__un1_n nEXP_SPACE_i ipl_030_0_0__un0_n sm_amiga_i_2__n ipl_030_0_1__un3_n sm_amiga_i_1__n ipl_030_0_1__un1_n DS_030_i ipl_030_0_1__un0_n AS_030_000_SYNC_i \ - ipl_030_0_2__un3_n UDS_000_INT_0_sqmuxa_1_i ipl_030_0_2__un1_n UDS_000_INT_0_sqmuxa_i ipl_030_0_2__un0_n state_machine_un13_clk_000_d0_1_i_n uds_000_int_0_un3_n clk_clk_cnt_i_n uds_000_int_0_un1_n clk_cnt_i_0__n uds_000_int_0_un0_n \ - CLK_000_D2_i vpa_sync_0_un3_n a_i_30__n vpa_sync_0_un1_n a_i_31__n vpa_sync_0_un0_n a_i_28__n as_000_int_0_un3_n a_i_29__n as_000_int_0_un1_n a_i_26__n \ - as_000_int_0_un0_n a_i_27__n bgack_030_int_0_un3_n a_i_24__n bgack_030_int_0_un1_n a_i_25__n bgack_030_int_0_un0_n N_132_i vma_int_0_un3_n N_133_i vma_int_0_un1_n \ - vma_int_0_un0_n RST_i cpu_est_0_2__un3_n FPU_CS_INT_i cpu_est_0_2__un1_n BGACK_030_INT_i cpu_est_0_2__un0_n AS_030_c dsack_int_0_1__un3_n dsack_int_0_1__un1_n dsack_int_0_1__un0_n \ - DS_030_c bg_000_0_un3_n bg_000_0_un1_n bg_000_0_un0_n amiga_bus_enable_0_un3_n size_c_0__n amiga_bus_enable_0_un1_n amiga_bus_enable_0_un0_n size_c_1__n as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n \ - a_c_0__n as_030_000_sync_0_un0_n fpu_cs_int_0_un3_n fpu_cs_int_0_un1_n fpu_cs_int_0_un0_n dtack_sync_0_un3_n dtack_sync_0_un1_n dtack_sync_0_un0_n lds_000_int_0_un3_n lds_000_int_0_un1_n lds_000_int_0_un0_n \ - a_15__n a_14__n a_13__n a_12__n a_c_16__n a_11__n a_c_17__n a_10__n a_c_18__n a_9__n a_c_19__n \ - a_8__n a_c_20__n a_7__n a_c_21__n a_6__n a_c_22__n a_5__n a_c_23__n a_4__n a_c_24__n a_3__n \ - a_c_25__n a_2__n a_c_26__n a_1__n a_c_27__n a_c_28__n a_c_29__n a_c_30__n a_c_31__n nEXP_SPACE_c BG_030_c \ - DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE + AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ IPL_030DFFSH_0_reg.D \ + IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP IPL_030DFFSH_1_reg.D IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D SM_AMIGA_7_.C SM_AMIGA_7_.AP \ + SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C \ + SM_AMIGA_3_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR CLK_CNT_0_.D \ + CLK_CNT_0_.C CLK_CNT_1_.D CLK_CNT_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_reg.D cpu_est_3_reg.C \ + inst_UDS_000_INTreg.D inst_UDS_000_INTreg.C inst_UDS_000_INTreg.AP inst_LDS_000_INTreg.D inst_LDS_000_INTreg.C inst_LDS_000_INTreg.AP inst_VMA_INTreg.D inst_VMA_INTreg.C inst_VMA_INTreg.AP BG_000DFFSHreg.D BG_000DFFSHreg.C \ + BG_000DFFSHreg.AP inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP inst_AS_000_INTreg.D inst_AS_000_INTreg.C inst_AS_000_INTreg.AP inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \ + inst_AS_030_000_SYNC.AP inst_DTACK_SYNC.D inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_FPU_CS_INTreg.D inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP DSACK_INT_1_.D DSACK_INT_1_.C DSACK_INT_1_.AP inst_VPA_SYNC.D \ + inst_VPA_SYNC.C inst_VPA_SYNC.AP AMIGA_BUS_ENABLEDFFreg.D AMIGA_BUS_ENABLEDFFreg.C inst_CLK_000_D5.D inst_CLK_000_D5.C inst_DTACK_DMA.D inst_DTACK_DMA.C inst_DTACK_DMA.AP CLK_OUT_INTreg.D CLK_OUT_INTreg.C \ + inst_CLK_000_D4.D inst_CLK_000_D4.C inst_CLK_000_D2.D inst_CLK_000_D2.C inst_CLK_000_D3.D inst_CLK_000_D3.C inst_VPA_D.D inst_VPA_D.C inst_CLK_000_D0.D inst_CLK_000_D0.C RESETDFFreg.D \ + RESETDFFreg.C inst_CLK_000_D1.D inst_CLK_000_D1.C CLK_REF_1_.D CLK_REF_1_.LH CLK_REF_1_.AR CLK_OUT_PRE_0.X1 CLK_OUT_PRE_0.X2 G_96.X1 G_96.X2 G_92.X1 \ + G_92.X2 DSACK_1_ DTACK DSACK_0_ BGACK_000_c CLK_030_c CLK_OSZI_c ipl_c_0__n ipl_c_1__n ipl_c_2__n vcc_n_n gnd_n_n dsack_c_1__n DTACK_c \ + AS_000_INT_1_sqmuxa state_machine_un8_clk_000_d2_n state_machine_un23_clk_000_d0_n RST_c state_machine_un6_clk_000_d4_n clk_clk_cnt_n RW_c fc_c_0__n state_machine_un6_bgack_000_n fc_c_1__n state_machine_un7_as_000_int_n \ + state_machine_un15_clk_000_d0_n clk_cpu_est_11_0_1__n state_machine_lds_000_int_5_n N_124_i state_machine_uds_000_int_5_n N_146_i un1_AMIGA_BUS_ENABLE_1_sqmuxa_2 N_121_i N_122_i N_66_0 N_65_0 \ + N_145_i un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 DS_030_c_i N_63_i N_62_i state_machine_un6_clk_000_d4_i_n N_61_i N_60_i N_59_i N_58_i N_57_i \ + CLK_000_D1_i N_56_i N_55_i N_52_i N_141_i N_142_i N_14_0 N_85_i N_139_i clk_cpu_est_11_1__n N_140_i \ + clk_cpu_est_11_3__n sm_amiga_ns_0_0__n N_125_i N_138_i N_162 N_178_i N_163 clk_cpu_est_11_0_3__n N_164 N_119_i N_165 \ + N_43_i N_30 N_117_i N_118_i N_51 N_123_i N_52 N_115_i N_55 N_116_i N_56 \ + sm_amiga_ns_0_7__n N_57 N_98_i N_58 N_114_i N_59 N_39_0 N_60 N_94_i N_61 N_97_i \ + N_62 sm_amiga_ns_0_5__n N_63 N_89_i N_65 N_90_i N_66 N_69 N_88_i N_72 N_73 \ + N_86_i N_74 N_75 N_83_i N_76 N_77 N_81_i N_79 state_machine_lds_000_int_5_0_n N_81 state_machine_uds_000_int_5_0_n \ + N_83 N_79_i N_85 N_30_0 N_86 N_165_0 N_88 N_76_i N_89 N_164_0 N_90 \ + N_163_0 N_94 N_72_i N_97 N_73_i N_98 state_machine_un15_clk_000_d0_0_n N_114 N_162_0 N_115 state_machine_un6_bgack_000_0_n \ + N_116 state_machine_un23_clk_000_d0_i_n N_117 N_188_1 N_118 N_188_2 N_119 N_188_3 N_120 N_188_4 N_121 \ + N_188_5 N_122 N_188_6 N_124 N_191_1 N_125 N_191_2 N_178 state_machine_un8_clk_000_d2_1_n N_138 N_57_i_1 \ + N_139 N_57_i_2 N_140 N_57_i_3 N_141 N_57_i_4 N_142 N_57_i_5 N_145 clk_cpu_est_11_0_1_1__n N_146 \ + clk_cpu_est_11_0_2_1__n N_77_1 N_120_1 N_188 N_120_2 N_191 N_79_1 RW_i N_79_2 VPA_D_i N_77_1_0 \ + CLK_000_D0_i N_75_1 cpu_est_i_0__n N_75_2 cpu_est_i_3__n N_75_3 VMA_INT_i N_75_4 cpu_est_i_1__n N_75_5 DTACK_i \ + N_73_1 BG_030_i N_73_2 nEXP_SPACE_i N_72_1 sm_amiga_i_3__n N_72_2 AS_000_INT_i sm_amiga_ns_0_1_0__n sm_amiga_i_6__n clk_cpu_est_11_0_1_3__n \ + cpu_est_i_2__n N_138_1 AMIGA_BUS_ENABLE_i N_119_1 AS_030_i N_118_1 sm_amiga_i_4__n N_117_1 sm_amiga_i_5__n N_97_1 state_machine_un8_clk_000_d2_i_n \ + N_81_1 sm_amiga_i_7__n state_machine_uds_000_int_5_0_m2_un3_n a_i_0__n state_machine_uds_000_int_5_0_m2_un1_n size_i_1__n state_machine_uds_000_int_5_0_m2_un0_n dsack_i_1__n vpa_sync_0_un3_n clk_clk_cnt_i_n vpa_sync_0_un1_n \ + clk_cnt_i_0__n vpa_sync_0_un0_n CLK_000_D2_i amiga_bus_enable_0_un3_n AS_030_000_SYNC_i amiga_bus_enable_0_un1_n a_i_30__n amiga_bus_enable_0_un0_n a_i_31__n uds_000_int_0_un3_n a_i_28__n \ + uds_000_int_0_un1_n a_i_29__n uds_000_int_0_un0_n a_i_26__n lds_000_int_0_un3_n a_i_27__n lds_000_int_0_un1_n a_i_24__n lds_000_int_0_un0_n a_i_25__n vma_int_0_un3_n \ + a_i_19__n vma_int_0_un1_n a_i_16__n vma_int_0_un0_n a_i_18__n bg_000_0_un3_n N_137_i bg_000_0_un1_n bg_000_0_un0_n RST_i bgack_030_int_0_un3_n \ + N_120_i bgack_030_int_0_un1_n N_75_i bgack_030_int_0_un0_n N_74_i as_000_int_0_un3_n N_77_i as_000_int_0_un1_n FPU_CS_INT_i as_000_int_0_un0_n BGACK_030_INT_i \ + cpu_est_0_1__un3_n CLK_000_D5_i cpu_est_0_1__un1_n AS_030_c cpu_est_0_1__un0_n cpu_est_0_2__un3_n cpu_est_0_2__un1_n DS_030_c cpu_est_0_2__un0_n cpu_est_0_3__un3_n cpu_est_0_3__un1_n \ + cpu_est_0_3__un0_n size_c_0__n ipl_030_0_0__un3_n ipl_030_0_0__un1_n size_c_1__n ipl_030_0_0__un0_n ipl_030_0_1__un3_n a_c_0__n ipl_030_0_1__un1_n ipl_030_0_1__un0_n ipl_030_0_2__un3_n \ + ipl_030_0_2__un1_n ipl_030_0_2__un0_n as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n dtack_sync_0_un3_n dtack_sync_0_un1_n dtack_sync_0_un0_n fpu_cs_int_0_un3_n fpu_cs_int_0_un1_n fpu_cs_int_0_un0_n \ + dsack_int_0_1__un3_n dsack_int_0_1__un1_n dsack_int_0_1__un0_n a_c_16__n a_15__n a_c_17__n a_14__n a_c_18__n a_13__n a_c_19__n a_12__n \ + a_c_20__n a_11__n a_c_21__n a_10__n a_c_22__n a_9__n a_c_23__n a_8__n a_c_24__n a_7__n a_c_25__n \ + a_6__n a_c_26__n a_5__n a_c_27__n a_4__n a_c_28__n a_3__n a_c_29__n a_2__n a_c_30__n a_1__n \ + a_c_31__n nEXP_SPACE_c BG_030_c DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE BERR.OE \ + DSACK_0_.OE AVEC_EXP.OE CIIN.OE .names DSACK_INT_1_.BLIF DSACK_1_ 1 1 .names DSACK_1_.PIN dsack_c_1__n @@ -168,933 +169,940 @@ 1 1 .names FPU_CS_INT_i.BLIF AVEC_EXP.OE 1 1 -.names N_171.BLIF CIIN +.names N_191.BLIF CIIN 1 1 -.names N_168.BLIF CIIN.OE +.names N_188.BLIF CIIN.OE 1 1 -.names N_102.BLIF N_102_i +.names N_61_i.BLIF N_61 0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C -1 1 -.names N_103.BLIF N_103_i -0 1 -.names CLK_000_D0_i.BLIF N_101_i.BLIF SM_AMIGA_4_.D -11 1 -.names RST_i.BLIF SM_AMIGA_5_.AR -1 1 -.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n -0 1 -.names sm_amiga_i_3__n.BLIF sm_amiga_i_4__n.BLIF N_103 -11 1 -.names inst_CLK_000_D0.BLIF CLK_000_D0_i -0 1 -.names CLK_000_D0_i.BLIF N_91.BLIF N_102 -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C -1 1 -.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n -0 1 -.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n -0 1 -.names RST_i.BLIF SM_AMIGA_4_.AR -1 1 -.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_101 -11 1 -.names inst_AS_000_INTreg.BLIF AS_000_INT_i -0 1 -.names dsack_c_1__n.BLIF dsack_i_1__n -0 1 -.names AS_000_INT_i.BLIF dsack_i_1__n.BLIF state_machine_un14_as_000_int_n -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C -1 1 -.names clk_un4_clk_000_d1_n.BLIF cpu_est_0_1__un3_n -0 1 -.names clk_cpu_est_11_1__n.BLIF clk_un4_clk_000_d1_n.BLIF cpu_est_0_1__un1_n -11 1 -.names RST_i.BLIF SM_AMIGA_3_.AR -1 1 -.names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n -11 1 -.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D -1- 1 --1 1 -.names RW_c.BLIF RW_i -0 1 -.names DTACK_c.BLIF DTACK_i -0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C -1 1 -.names cpu_est_1_.BLIF cpu_est_i_1__n -0 1 -.names inst_VPA_D.BLIF VPA_D_i -0 1 -.names RST_i.BLIF SM_AMIGA_2_.AR -1 1 -.names inst_AS_000_INTreg.BLIF inst_CLK_000_D0.BLIF state_machine_un13_clk_000_d0_1_n -11 1 -.names cpu_est_1_.BLIF cpu_est_2_.BLIF state_machine_un13_clk_000_d0_2_n -11 1 -.names cpu_est_3_reg.BLIF state_machine_un13_clk_000_d0_2_n.BLIF N_126 -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C -1 1 -.names N_121_i.BLIF cpu_est_0_.BLIF N_125 -11 1 -.names cpu_est_3_reg.BLIF cpu_est_i_3__n -0 1 -.names RST_i.BLIF SM_AMIGA_1_.AR -1 1 -.names cpu_est_2_.BLIF cpu_est_i_2__n -0 1 -.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_124 -11 1 -.names cpu_est_0_.BLIF cpu_est_i_0__n -0 1 -.names N_121.BLIF cpu_est_i_0__n.BLIF N_123 -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C -1 1 -.names SM_AMIGA_3_.BLIF state_machine_un23_clk_000_d0_i_n.BLIF N_91_0 -11 1 -.names N_102_i.BLIF N_103_i.BLIF SM_AMIGA_3_.D -11 1 -.names RST_i.BLIF SM_AMIGA_0_.AR -1 1 -.names clk_un4_clk_000_d1_n.BLIF cpu_est_0_3__un3_n -0 1 -.names clk_cpu_est_11_3__n.BLIF clk_un4_clk_000_d1_n.BLIF cpu_est_0_3__un1_n -11 1 -.names cpu_est_3_reg.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n -11 1 -.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_reg.D -1- 1 --1 1 -.names CLK_OSZI_c.BLIF cpu_est_1_.C -1 1 -.names clk_un4_clk_000_d1_n.BLIF ipl_030_0_0__un3_n -0 1 -.names ipl_c_0__n.BLIF clk_un4_clk_000_d1_n.BLIF ipl_030_0_0__un1_n -11 1 -.names IPL_030DFFSH_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n -11 1 -.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF IPL_030DFFSH_0_reg.D -1- 1 --1 1 -.names CLK_OSZI_c.BLIF cpu_est_2_.C -1 1 -.names clk_un4_clk_000_d1_n.BLIF ipl_030_0_1__un3_n -0 1 -.names ipl_c_1__n.BLIF clk_un4_clk_000_d1_n.BLIF ipl_030_0_1__un1_n -11 1 -.names IPL_030DFFSH_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n -11 1 -.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF IPL_030DFFSH_1_reg.D -1- 1 --1 1 -.names CLK_OSZI_c.BLIF cpu_est_3_reg.C -1 1 -.names clk_un4_clk_000_d1_n.BLIF ipl_030_0_2__un3_n -0 1 -.names ipl_c_2__n.BLIF clk_un4_clk_000_d1_n.BLIF ipl_030_0_2__un1_n -11 1 -.names IPL_030DFFSH_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n -11 1 -.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF IPL_030DFFSH_2_reg.D -1- 1 --1 1 .names CLK_OSZI_c.BLIF IPL_030DFFSH_0_reg.C 1 1 -.names inst_CLK_000_D0.BLIF CLK_000_c.BLIF state_machine_un2_clk_000_n -11 1 -.names inst_CLK_000_D1.BLIF CLK_000_D1_i +.names N_60_i.BLIF N_60 +0 1 +.names N_59_i.BLIF N_59 0 1 .names RST_i.BLIF IPL_030DFFSH_0_reg.AP 1 1 -.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF clk_un4_clk_000_d1_n -11 1 -.names state_machine_un8_clk_000_d0_i_n.BLIF state_machine_un13_clk_000_d0_i_n.BLIF state_machine_un15_clk_000_d0_0_n -11 1 -.names N_122.BLIF cpu_est_3_reg.BLIF N_129 -11 1 -.names N_122_i.BLIF cpu_est_i_2__n.BLIF N_130 -11 1 +.names N_58_i.BLIF N_58 +0 1 +.names N_57_i.BLIF N_57 +0 1 +.names clk_cpu_est_11_0_1__n.BLIF clk_cpu_est_11_1__n +0 1 +.names N_124.BLIF N_124_i +0 1 .names CLK_OSZI_c.BLIF IPL_030DFFSH_1_reg.C 1 1 -.names N_127_i.BLIF N_128_i.BLIF N_118_i -11 1 -.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF N_121_i -11 1 +.names N_146.BLIF N_146_i +0 1 +.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n +0 1 .names RST_i.BLIF IPL_030DFFSH_1_reg.AP 1 1 -.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_122_i +.names SM_AMIGA_3_.BLIF state_machine_un23_clk_000_d0_i_n.BLIF N_66_0 11 1 -.names state_machine_un13_clk_000_d0_2_n.BLIF state_machine_un13_clk_000_d0_2_i_n +.names BG_030_c.BLIF BG_030_i 0 1 -.names inst_VMA_INTreg.BLIF VMA_INT_i +.names nEXP_SPACE_c.BLIF nEXP_SPACE_i 0 1 -.names un1_as_030_4.BLIF uds_000_int_0_un3_n +.names DTACK_c.BLIF DTACK_i 0 1 .names CLK_OSZI_c.BLIF IPL_030DFFSH_2_reg.C 1 1 -.names inst_UDS_000_INTreg.BLIF un1_as_030_4.BLIF uds_000_int_0_un1_n -11 1 -.names state_machine_uds_000_int_7_n.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n +.names cpu_est_1_.BLIF cpu_est_i_1__n +0 1 +.names inst_CLK_000_D0.BLIF SM_AMIGA_3_.BLIF N_77_1 11 1 .names RST_i.BLIF IPL_030DFFSH_2_reg.AP 1 1 -.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INTreg.D -1- 1 --1 1 -.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF state_machine_un23_clk_000_d0_i_n -11 1 -.names VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un3_n +.names inst_VMA_INTreg.BLIF VMA_INT_i +0 1 +.names cpu_est_0_.BLIF cpu_est_i_0__n +0 1 +.names cpu_est_3_reg.BLIF cpu_est_i_3__n +0 1 +.names inst_CLK_000_D0.BLIF CLK_000_D0_i 0 1 -.names inst_VPA_SYNC.BLIF VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un1_n -11 1 .names CLK_OSZI_c.BLIF SM_AMIGA_7_.C 1 1 -.names VPA_SYNC_1_sqmuxa_i.BLIF vpa_sync_0_un3_n.BLIF vpa_sync_0_un0_n -11 1 -.names vpa_sync_0_un1_n.BLIF vpa_sync_0_un0_n.BLIF inst_VPA_SYNC.D -1- 1 --1 1 +.names inst_VPA_D.BLIF VPA_D_i +0 1 +.names RW_c.BLIF RW_i +0 1 .names RST_i.BLIF SM_AMIGA_7_.AP 1 1 -.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n +.names RW_c.BLIF state_machine_uds_000_int_5_0_m2_un3_n 0 1 -.names inst_AS_000_INTreg.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n +.names SM_AMIGA_5_.BLIF RW_c.BLIF state_machine_uds_000_int_5_0_m2_un1_n 11 1 -.names N_95_i.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n +.names SM_AMIGA_4_.BLIF state_machine_uds_000_int_5_0_m2_un3_n.BLIF state_machine_uds_000_int_5_0_m2_un0_n 11 1 -.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF inst_AS_000_INTreg.D +.names state_machine_uds_000_int_5_0_m2_un1_n.BLIF state_machine_uds_000_int_5_0_m2_un0_n.BLIF N_51 1- 1 -1 1 -.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C +.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C 1 1 -.names state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n +.names AS_030_i.BLIF N_74_i.BLIF N_52_i +11 1 +.names cpu_est_2_.BLIF cpu_est_i_2__n 0 1 -.names BGACK_000_c.BLIF state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n -11 1 -.names RST_i.BLIF inst_VMA_INTreg.AP +.names RST_i.BLIF SM_AMIGA_6_.AR 1 1 -.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un0_n +.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_55_i 11 1 -.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF inst_BGACK_030_INTreg.D -1- 1 --1 1 -.names BGACK_000_c.BLIF clk_un4_clk_000_d1_i_n.BLIF state_machine_un6_bgack_000_0_n +.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF N_56_i 11 1 -.names N_95.BLIF N_95_i +.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n 0 1 -.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C -1 1 -.names AS_030_i.BLIF N_95_i.BLIF AS_000_INT_1_sqmuxa +.names SM_AMIGA_6_.BLIF nEXP_SPACE_c.BLIF N_58_i 11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C +1 1 +.names inst_AS_000_INTreg.BLIF AS_000_INT_i +0 1 +.names inst_AS_000_INTreg.BLIF inst_CLK_000_D0.BLIF N_59_i +11 1 +.names RST_i.BLIF SM_AMIGA_5_.AR +1 1 +.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF N_60_i +11 1 +.names CLK_000_D0_i.BLIF state_machine_un6_clk_000_d4_i_n.BLIF N_61_i +11 1 +.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_62_i +11 1 +.names DS_030_c_i.BLIF N_51.BLIF N_63_i +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C +1 1 +.names N_52_i.BLIF N_145_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 +11 1 +.names CLK_000_D0_i.BLIF N_58_i.BLIF N_65_0 +11 1 +.names RST_i.BLIF SM_AMIGA_4_.AR +1 1 +.names AS_030_i.BLIF N_76_i.BLIF N_164_0 +11 1 +.names AS_030_i.BLIF N_77_i.BLIF N_165_0 +11 1 +.names N_79_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0.BLIF N_30_0 +11 1 +.names a_i_0__n.BLIF N_63_i.BLIF state_machine_uds_000_int_5_0_n +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C +1 1 +.names N_63_i.BLIF N_81_i.BLIF state_machine_lds_000_int_5_0_n +11 1 +.names N_83_i.BLIF N_85_i.BLIF SM_AMIGA_6_.D +11 1 +.names RST_i.BLIF SM_AMIGA_3_.AR +1 1 +.names inst_CLK_000_D0.BLIF N_86_i.BLIF SM_AMIGA_5_.D +11 1 +.names CLK_000_D0_i.BLIF N_88_i.BLIF SM_AMIGA_4_.D +11 1 +.names N_89_i.BLIF N_90_i.BLIF SM_AMIGA_3_.D +11 1 +.names N_94_i.BLIF N_97_i.BLIF sm_amiga_ns_0_5__n +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C +1 1 +.names N_98_i.BLIF N_114_i.BLIF N_39_0 +11 1 +.names N_115_i.BLIF N_116_i.BLIF sm_amiga_ns_0_7__n +11 1 +.names RST_i.BLIF SM_AMIGA_2_.AR +1 1 +.names N_117_i.BLIF N_118_i.BLIF N_123_i +11 1 +.names N_58.BLIF N_119_i.BLIF N_43_i +11 1 +.names N_141_i.BLIF N_142_i.BLIF N_14_0 +11 1 +.names N_60.BLIF cpu_est_i_0__n.BLIF N_121 +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C +1 1 +.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_122 +11 1 +.names N_55_i.BLIF cpu_est_3_reg.BLIF N_124 +11 1 +.names RST_i.BLIF SM_AMIGA_1_.AR +1 1 +.names N_62.BLIF cpu_est_3_reg.BLIF N_125 +11 1 +.names N_62_i.BLIF cpu_est_i_2__n.BLIF N_178 +11 1 +.names CLK_000_D0_i.BLIF N_145.BLIF N_139 +11 1 +.names N_59_i.BLIF SM_AMIGA_0_.BLIF N_140 +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C +1 1 +.names N_56.BLIF cpu_est_0_.BLIF N_141 +11 1 +.names N_56_i.BLIF cpu_est_i_0__n.BLIF N_142 +11 1 +.names RST_i.BLIF SM_AMIGA_0_.AR +1 1 +.names SM_AMIGA_6_.BLIF nEXP_SPACE_i.BLIF N_145 +11 1 +.names N_60_i.BLIF cpu_est_0_.BLIF N_146 +11 1 +.names BGACK_000_c.BLIF N_56.BLIF state_machine_un6_bgack_000_0_n +11 1 +.names AS_030_i.BLIF N_63.BLIF N_162_0 +11 1 +.names CLK_OSZI_c.BLIF CLK_CNT_0_.C +1 1 +.names N_72_i.BLIF N_73_i.BLIF state_machine_un15_clk_000_d0_0_n +11 1 +.names AS_030_i.BLIF N_75_i.BLIF N_163_0 +11 1 +.names state_machine_un8_clk_000_d2_n.BLIF state_machine_un8_clk_000_d2_i_n +0 1 +.names SM_AMIGA_7_.BLIF state_machine_un8_clk_000_d2_i_n.BLIF N_85 +11 1 +.names CLK_OSZI_c.BLIF CLK_CNT_1_.C +1 1 +.names sm_amiga_i_5__n.BLIF sm_amiga_i_6__n.BLIF N_86 +11 1 +.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +0 1 +.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_88 +11 1 +.names CLK_000_D0_i.BLIF N_66.BLIF N_89 +11 1 +.names CLK_OSZI_c.BLIF cpu_est_0_.C +1 1 +.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n +0 1 +.names sm_amiga_i_3__n.BLIF sm_amiga_i_4__n.BLIF N_90 +11 1 +.names CLK_000_D0_i.BLIF SM_AMIGA_2_.BLIF N_94 +11 1 +.names N_61.BLIF SM_AMIGA_1_.BLIF N_98 +11 1 +.names CLK_OSZI_c.BLIF cpu_est_1_.C +1 1 +.names inst_CLK_000_D0.BLIF SM_AMIGA_2_.BLIF N_114 +11 1 +.names N_59.BLIF SM_AMIGA_0_.BLIF N_115 +11 1 +.names N_61_i.BLIF SM_AMIGA_1_.BLIF N_116 +11 1 +.names AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLE_i +0 1 +.names CLK_OSZI_c.BLIF cpu_est_2_.C +1 1 .names AS_030.BLIF AS_030_c 1 1 -.names VPA_SYNC_1_sqmuxa.BLIF VPA_SYNC_1_sqmuxa_i -0 1 -.names RST_i.BLIF inst_BGACK_030_INTreg.AP -1 1 .names AS_030_c.BLIF AS_030_i 0 1 +.names clk_clk_cnt_n.BLIF clk_clk_cnt_i_n +0 1 .names DS_030.BLIF DS_030_c 1 1 -.names AS_030_i.BLIF VPA_SYNC_1_sqmuxa_i.BLIF VPA_SYNC_1_sqmuxa_1 +.names clk_clk_cnt_i_n.BLIF G_96.BLIF CLK_CNT_1_.D 11 1 -.names inst_CLK_000_D0.BLIF SM_AMIGA_5_.BLIF N_100 -11 1 -.names N_95_i.BLIF N_100_i.BLIF sm_amiga_ns_0_2__n -11 1 -.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE.C +.names CLK_OSZI_c.BLIF cpu_est_3_reg.C 1 1 .names SIZE_0_.BLIF size_c_0__n 1 1 -.names state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un3_n -0 1 .names SIZE_1_.BLIF size_c_1__n 1 1 -.names N_121.BLIF state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un1_n +.names BG_030_i.BLIF CLK_030_c.BLIF N_69 11 1 .names A_0_.BLIF a_c_0__n 1 1 -.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n +.names AS_030_i.BLIF sm_amiga_i_5__n.BLIF AS_000_INT_1_sqmuxa 11 1 +.names CLK_OSZI_c.BLIF inst_UDS_000_INTreg.C +1 1 .names A_16_.BLIF a_c_16__n 1 1 -.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D -1- 1 --1 1 -.names CLK_OSZI_c.BLIF CLK_CNT_0_.C -1 1 +.names dsack_c_1__n.BLIF dsack_i_1__n +0 1 .names A_17_.BLIF a_c_17__n 1 1 -.names clk_un4_clk_000_d1_n.BLIF cpu_est_0_2__un3_n -0 1 +.names AS_000_INT_i.BLIF dsack_i_1__n.BLIF state_machine_un7_as_000_int_n +11 1 +.names RST_i.BLIF inst_UDS_000_INTreg.AP +1 1 .names A_18_.BLIF a_c_18__n 1 1 -.names N_118_i.BLIF clk_un4_clk_000_d1_n.BLIF cpu_est_0_2__un1_n +.names SM_AMIGA_1_.BLIF state_machine_un6_clk_000_d4_n.BLIF N_74 11 1 .names A_19_.BLIF a_c_19__n 1 1 -.names cpu_est_2_.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n +.names CLK_030_c.BLIF N_57_i.BLIF N_76 11 1 .names A_20_.BLIF a_c_20__n 1 1 -.names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D -1- 1 --1 1 -.names CLK_OSZI_c.BLIF CLK_CNT_1_.C -1 1 +.names a_c_0__n.BLIF a_i_0__n +0 1 .names A_21_.BLIF a_c_21__n 1 1 -.names AS_030_i.BLIF CLK_030_i.BLIF state_machine_un17_clk_030_0_n -11 1 +.names size_c_1__n.BLIF size_i_1__n +0 1 +.names CLK_OSZI_c.BLIF inst_LDS_000_INTreg.C +1 1 .names A_22_.BLIF a_c_22__n 1 1 -.names CLK_030_c.BLIF CLK_030_i +.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n 0 1 .names A_23_.BLIF a_c_23__n 1 1 -.names BG_030_c_i.BLIF CLK_030_c.BLIF state_machine_un1_clk_030_0_n +.names N_65.BLIF sm_amiga_i_7__n.BLIF N_83 11 1 +.names RST_i.BLIF inst_LDS_000_INTreg.AP +1 1 .names A_24_.BLIF a_c_24__n 1 1 -.names a_c_19__n.BLIF a_i_19__n +.names a_c_16__n.BLIF a_i_16__n 0 1 -.names CLK_OSZI_c.BLIF cpu_est_0_.C -1 1 .names A_25_.BLIF a_c_25__n 1 1 .names a_c_18__n.BLIF a_i_18__n 0 1 .names A_26_.BLIF a_c_26__n 1 1 -.names a_c_16__n.BLIF a_i_16__n +.names a_c_19__n.BLIF a_i_19__n 0 1 .names A_27_.BLIF a_c_27__n 1 1 -.names N_96.BLIF N_96_i +.names a_c_24__n.BLIF a_i_24__n 0 1 +.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C +1 1 .names A_28_.BLIF a_c_28__n 1 1 -.names DSACK_INT_1_sqmuxa.BLIF dsack_int_0_1__un3_n +.names a_c_25__n.BLIF a_i_25__n 0 1 -.names CLK_OSZI_c.BLIF inst_VPA_SYNC.C -1 1 .names A_29_.BLIF a_c_29__n 1 1 -.names DSACK_INT_1_.BLIF DSACK_INT_1_sqmuxa.BLIF dsack_int_0_1__un1_n -11 1 +.names a_c_26__n.BLIF a_i_26__n +0 1 +.names RST_i.BLIF inst_VMA_INTreg.AP +1 1 .names A_30_.BLIF a_c_30__n 1 1 -.names N_96_i.BLIF dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un0_n -11 1 -.names RST_i.BLIF inst_VPA_SYNC.AP -1 1 +.names a_c_27__n.BLIF a_i_27__n +0 1 .names A_31_.BLIF a_c_31__n 1 1 -.names dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF DSACK_INT_1_.D -1- 1 --1 1 +.names a_c_28__n.BLIF a_i_28__n +0 1 .names nEXP_SPACE.BLIF nEXP_SPACE_c 1 1 -.names state_machine_un1_clk_030_n.BLIF bg_000_0_un3_n +.names a_c_29__n.BLIF a_i_29__n 0 1 -.names un1_bg_030.BLIF state_machine_un1_clk_030_n.BLIF bg_000_0_un1_n -11 1 +.names a_c_30__n.BLIF a_i_30__n +0 1 +.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C +1 1 .names BG_030.BLIF BG_030_c 1 1 -.names BG_000DFFSHreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n -11 1 -.names CLK_OSZI_c.BLIF inst_FPU_CS_INTreg.C -1 1 +.names a_c_31__n.BLIF a_i_31__n +0 1 .names BG_000DFFSHreg.BLIF BG_000 1 1 -.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF BG_000DFFSHreg.D +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +0 1 +.names RST_i.BLIF BG_000DFFSHreg.AP +1 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030 +1 1 +.names inst_CLK_000_D2.BLIF CLK_000_D2_i +0 1 +.names BGACK_000.BLIF BGACK_000_c +1 1 +.names CLK_CNT_0_.BLIF clk_cnt_i_0__n +0 1 +.names CLK_030.BLIF CLK_030_c +1 1 +.names clk_cnt_i_0__n.BLIF clk_clk_cnt_i_n.BLIF CLK_CNT_0_.D +11 1 +.names CLK_000.BLIF inst_CLK_000_D0.D +1 1 +.names state_machine_un7_as_000_int_n.BLIF inst_DTACK_DMA.D +0 1 +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE.C +1 1 +.names CLK_OSZI.BLIF CLK_OSZI_c +1 1 +.names RST_c.BLIF RST_i +0 1 +.names CLK_OUT_INTreg.BLIF CLK_DIV_OUT +1 1 +.names G_92.BLIF N_137_i +0 1 +.names CLK_OUT_INTreg.BLIF CLK_EXP +1 1 +.names clk_cnt_i_0__n.BLIF N_137_i.BLIF clk_clk_cnt_n +11 1 +.names inst_FPU_CS_INTreg.BLIF FPU_CS +1 1 +.names N_163.BLIF vpa_sync_0_un3_n +0 1 +.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C +1 1 +.names IPL_030DFFSH_0_reg.BLIF IPL_030_0_ +1 1 +.names N_75_i.BLIF N_163.BLIF vpa_sync_0_un1_n +11 1 +.names IPL_030DFFSH_1_reg.BLIF IPL_030_1_ +1 1 +.names inst_VPA_SYNC.BLIF vpa_sync_0_un3_n.BLIF vpa_sync_0_un0_n +11 1 +.names RST_i.BLIF inst_BGACK_030_INTreg.AP +1 1 +.names IPL_030DFFSH_2_reg.BLIF IPL_030_2_ +1 1 +.names vpa_sync_0_un1_n.BLIF vpa_sync_0_un0_n.BLIF inst_VPA_SYNC.D 1- 1 -1 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030 +.names IPL_0_.BLIF ipl_c_0__n 1 1 .names RST_c.BLIF amiga_bus_enable_0_un3_n 0 1 -.names RST_i.BLIF inst_FPU_CS_INTreg.AP +.names IPL_1_.BLIF ipl_c_1__n 1 1 -.names BGACK_000.BLIF BGACK_000_c -1 1 -.names state_machine_amiga_bus_enable_2_iv_i_n.BLIF RST_c.BLIF amiga_bus_enable_0_un1_n +.names N_43_i.BLIF RST_c.BLIF amiga_bus_enable_0_un1_n 11 1 -.names CLK_030.BLIF CLK_030_c +.names IPL_2_.BLIF ipl_c_2__n 1 1 .names AMIGA_BUS_ENABLEDFFreg.BLIF amiga_bus_enable_0_un3_n.BLIF amiga_bus_enable_0_un0_n 11 1 -.names CLK_000.BLIF CLK_000_c +.names CLK_OSZI_c.BLIF inst_AS_000_INTreg.C 1 1 .names amiga_bus_enable_0_un1_n.BLIF amiga_bus_enable_0_un0_n.BLIF AMIGA_BUS_ENABLEDFFreg.D 1- 1 -1 1 -.names CLK_OSZI.BLIF CLK_OSZI_c -1 1 -.names state_machine_un17_clk_030_n.BLIF as_030_000_sync_0_un3_n -0 1 -.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C -1 1 -.names CLK_OUT_INTreg.BLIF CLK_DIV_OUT -1 1 -.names state_machine_as_030_000_sync_3_n.BLIF state_machine_un17_clk_030_n.BLIF as_030_000_sync_0_un1_n -11 1 -.names CLK_OUT_INTreg.BLIF CLK_EXP -1 1 -.names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n -11 1 -.names RST_i.BLIF inst_AS_030_000_SYNC.AP -1 1 -.names inst_FPU_CS_INTreg.BLIF FPU_CS -1 1 -.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF inst_AS_030_000_SYNC.D -1- 1 --1 1 -.names IPL_030DFFSH_0_reg.BLIF IPL_030_0_ -1 1 -.names state_machine_un17_clk_030_n.BLIF fpu_cs_int_0_un3_n -0 1 -.names IPL_030DFFSH_1_reg.BLIF IPL_030_1_ -1 1 -.names un1_as_030_3.BLIF state_machine_un17_clk_030_n.BLIF fpu_cs_int_0_un1_n -11 1 -.names IPL_030DFFSH_2_reg.BLIF IPL_030_2_ -1 1 -.names inst_FPU_CS_INTreg.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un0_n -11 1 -.names CLK_OSZI_c.BLIF inst_AS_000_INTreg.C -1 1 -.names IPL_0_.BLIF ipl_c_0__n -1 1 -.names fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF inst_FPU_CS_INTreg.D -1- 1 --1 1 -.names IPL_1_.BLIF ipl_c_1__n -1 1 -.names DTACK_SYNC_1_sqmuxa.BLIF DTACK_SYNC_1_sqmuxa_i +.names N_162.BLIF uds_000_int_0_un3_n 0 1 .names RST_i.BLIF inst_AS_000_INTreg.AP 1 1 -.names IPL_2_.BLIF ipl_c_2__n -1 1 -.names DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un3_n -0 1 -.names inst_DTACK_SYNC.BLIF DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un1_n +.names state_machine_uds_000_int_5_n.BLIF N_162.BLIF uds_000_int_0_un1_n 11 1 -.names DTACK_SYNC_1_sqmuxa_i.BLIF dtack_sync_0_un3_n.BLIF dtack_sync_0_un0_n -11 1 -.names dtack_sync_0_un1_n.BLIF dtack_sync_0_un0_n.BLIF inst_DTACK_SYNC.D -1- 1 --1 1 -.names CLK_OSZI_c.BLIF AMIGA_BUS_ENABLEDFFreg.C -1 1 .names vcc_n_n.BLIF AVEC 1 1 -.names un1_as_030_4.BLIF lds_000_int_0_un3_n -0 1 -.names inst_LDS_000_INTreg.BLIF un1_as_030_4.BLIF lds_000_int_0_un1_n +.names inst_UDS_000_INTreg.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n 11 1 +.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INTreg.D +1- 1 +-1 1 .names cpu_est_3_reg.BLIF E 1 1 -.names state_machine_lds_000_int_7_n.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n -11 1 +.names N_162.BLIF lds_000_int_0_un3_n +0 1 +.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C +1 1 .names VPA.BLIF inst_VPA_D.D 1 1 +.names state_machine_lds_000_int_5_n.BLIF N_162.BLIF lds_000_int_0_un1_n +11 1 +.names inst_VMA_INTreg.BLIF VMA +1 1 +.names inst_LDS_000_INTreg.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n +11 1 +.names RST_i.BLIF inst_AS_030_000_SYNC.AP +1 1 +.names RST.BLIF RST_c +1 1 .names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF inst_LDS_000_INTreg.D 1- 1 -1 1 -.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C -1 1 -.names inst_VMA_INTreg.BLIF VMA -1 1 -.names nEXP_SPACE_c.BLIF nEXP_SPACE_i -0 1 -.names RST.BLIF RST_c -1 1 -.names AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLE_i -0 1 -.names RST_i.BLIF BG_000DFFSHreg.AP -1 1 .names RESETDFFreg.BLIF RESET 1 1 -.names AMIGA_BUS_ENABLE_i_m_i.BLIF nEXP_SPACE_m_i.BLIF state_machine_amiga_bus_enable_2_iv_i_n -11 1 +.names state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un3_n +0 1 .names RW.BLIF RW_c 1 1 -.names SM_AMIGA_6_.BLIF nEXP_SPACE_c.BLIF nEXP_SPACE_m +.names cpu_est_1_.BLIF state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un1_n 11 1 .names FC_0_.BLIF fc_c_0__n 1 1 -.names N_89_i.BLIF SM_AMIGA_6_.BLIF N_95 -11 1 -.names FC_1_.BLIF fc_c_1__n -1 1 -.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n -0 1 -.names CLK_OSZI_c.BLIF DSACK_INT_1_.C -1 1 -.names AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLE -1 1 -.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n -0 1 -.names RW_i.BLIF AMIGA_BUS_DATA_DIR -1 1 -.names sm_amiga_i_6__n.BLIF sm_amiga_i_7__n.BLIF N_94 -11 1 -.names RST_i.BLIF DSACK_INT_1_.AP -1 1 -.names vcc_n_n.BLIF AMIGA_BUS_ENABLE_LOW -1 1 -.names N_148_i.BLIF state_machine_un44_clk_000_d1_n.BLIF state_machine_lds_000_int_7_0_n -11 1 -.names a_c_i_0__n.BLIF N_148_i.BLIF state_machine_uds_000_int_7_0_n -11 1 -.names DTACK_i.BLIF SM_AMIGA_3_.BLIF DTACK_SYNC_1_sqmuxa_1_0 -11 1 -.names AS_030_i.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF DTACK_SYNC_1_sqmuxa_1 -11 1 -.names inst_VPA_D.BLIF state_machine_un2_clk_000_n.BLIF DTACK_SYNC_1_sqmuxa_2 -11 1 -.names AS_030_i.BLIF N_148.BLIF un1_as_030_4 -11 1 -.names CLK_OSZI_c.BLIF inst_UDS_000_INTreg.C -1 1 -.names DTACK_SYNC_1_sqmuxa_1_0.BLIF DTACK_SYNC_1_sqmuxa_2.BLIF DTACK_SYNC_1_sqmuxa -11 1 -.names state_machine_un42_clk_030_n.BLIF state_machine_un42_clk_030_i_n -0 1 -.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF state_machine_un8_clk_000_d0_1_n -11 1 -.names AS_030_i.BLIF state_machine_un42_clk_030_n.BLIF un1_as_030_3_0 -11 1 -.names RST_i.BLIF inst_UDS_000_INTreg.AP -1 1 -.names CLK_000_D0_i.BLIF VPA_D_i.BLIF state_machine_un8_clk_000_d0_2_n -11 1 -.names AS_030_i.BLIF N_96_i.BLIF DSACK_INT_1_sqmuxa -11 1 -.names cpu_est_0_.BLIF cpu_est_2_.BLIF state_machine_un8_clk_000_d0_3_n -11 1 -.names UDS_000_INT_0_sqmuxa_1_i.BLIF UDS_000_INT_0_sqmuxa_i.BLIF N_148 -11 1 -.names state_machine_un8_clk_000_d0_1_n.BLIF state_machine_un8_clk_000_d0_2_n.BLIF state_machine_un8_clk_000_d0_4_n -11 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i -0 1 -.names state_machine_un8_clk_000_d0_4_n.BLIF state_machine_un8_clk_000_d0_3_n.BLIF state_machine_un8_clk_000_d0_n -11 1 -.names DS_030_c.BLIF DS_030_i -0 1 -.names CLK_OSZI_c.BLIF inst_LDS_000_INTreg.C -1 1 -.names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF state_machine_un13_clk_000_d0_1_0_n -11 1 -.names state_machine_un13_clk_000_d0_1_n.BLIF state_machine_un13_clk_000_d0_2_n.BLIF state_machine_un13_clk_000_d0_2_0_n -11 1 -.names RST_i.BLIF inst_LDS_000_INTreg.AP -1 1 -.names state_machine_un13_clk_000_d0_1_0_n.BLIF state_machine_un13_clk_000_d0_2_0_n.BLIF state_machine_un13_clk_000_d0_n -11 1 -.names cpu_est_3_reg.BLIF cpu_est_i_0__n.BLIF VPA_SYNC_1_sqmuxa_3 -11 1 -.names cpu_est_i_1__n.BLIF state_machine_un2_clk_000_n.BLIF VPA_SYNC_1_sqmuxa_4 -11 1 -.names CLK_OUT_PRE_i.BLIF sm_amiga_i_2__n.BLIF N_92_0 -11 1 -.names VPA_SYNC_1_sqmuxa_1_0.BLIF VPA_SYNC_1_sqmuxa_2.BLIF VPA_SYNC_1_sqmuxa_5 -11 1 -.names N_106_i.BLIF N_107_i.BLIF SM_AMIGA_1_.D +.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n 11 1 .names CLK_OSZI_c.BLIF inst_DTACK_SYNC.C 1 1 -.names VPA_SYNC_1_sqmuxa_3.BLIF VPA_SYNC_1_sqmuxa_4.BLIF VPA_SYNC_1_sqmuxa_6 -11 1 -.names N_104_i.BLIF N_105_i.BLIF sm_amiga_ns_0_5__n -11 1 -.names VPA_SYNC_1_sqmuxa_5.BLIF VPA_SYNC_1_sqmuxa_6.BLIF VPA_SYNC_1_sqmuxa -11 1 -.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n +.names FC_1_.BLIF fc_c_1__n +1 1 +.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D +1- 1 +-1 1 +.names AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLE +1 1 +.names N_120.BLIF N_120_i 0 1 .names RST_i.BLIF inst_DTACK_SYNC.AP 1 1 -.names cpu_est_0_.BLIF cpu_est_i_3__n.BLIF N_127_1 -11 1 -.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n -0 1 -.names N_127_1.BLIF state_machine_un13_clk_000_d0_2_i_n.BLIF N_127 -11 1 -.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_107 -11 1 -.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_128_1 -11 1 -.names CLK_000_D0_i.BLIF N_92.BLIF N_106 -11 1 -.names inst_CLK_OUT_PRE.BLIF CLK_OUT_INTreg.D +.names RW_i.BLIF AMIGA_BUS_DATA_DIR 1 1 -.names N_128_1.BLIF cpu_est_i_2__n.BLIF N_128 -11 1 -.names CLK_000_D0_i.BLIF SM_AMIGA_2_.BLIF N_104 -11 1 -.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_131_1 -11 1 -.names clk_cnt_i_0__n.BLIF clk_clk_cnt_i_n.BLIF CLK_CNT_0_.D -11 1 -.names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C -1 1 -.names N_131_1.BLIF cpu_est_i_2__n.BLIF N_131 -11 1 -.names clk_clk_cnt_n.BLIF clk_clk_cnt_i_n +.names N_69.BLIF bg_000_0_un3_n 0 1 -.names N_131_i.BLIF N_129_i.BLIF clk_cpu_est_11_0_1_3__n +.names vcc_n_n.BLIF AMIGA_BUS_ENABLE_LOW +1 1 +.names BG_000DFFSHreg.BLIF N_69.BLIF bg_000_0_un1_n 11 1 -.names clk_clk_cnt_i_n.BLIF G_91.BLIF CLK_CNT_1_.D +.names N_120_i.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n 11 1 -.names clk_cpu_est_11_0_1_3__n.BLIF N_130_i.BLIF clk_cpu_est_11_0_3__n +.names N_178_i.BLIF N_125_i.BLIF clk_cpu_est_11_0_1_3__n 11 1 -.names N_90.BLIF sm_amiga_i_7__n.BLIF N_97 +.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF BG_000DFFSHreg.D +1- 1 +-1 1 +.names CLK_OSZI_c.BLIF inst_FPU_CS_INTreg.C +1 1 +.names clk_cpu_est_11_0_1_3__n.BLIF N_138_i.BLIF clk_cpu_est_11_0_3__n 11 1 -.names CLK_000_D0_i.BLIF SM_AMIGA_3_.BLIF N_105_1 +.names state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n +0 1 +.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_138_1 11 1 -.names N_89.BLIF SM_AMIGA_6_.BLIF N_98 +.names BGACK_000_c.BLIF state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n +11 1 +.names RST_i.BLIF inst_FPU_CS_INTreg.AP +1 1 +.names N_138_1.BLIF cpu_est_i_2__n.BLIF N_138 +11 1 +.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un0_n +11 1 +.names AMIGA_BUS_ENABLE_i.BLIF AS_030_i.BLIF N_119_1 +11 1 +.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF inst_BGACK_030_INTreg.D +1- 1 +-1 1 +.names N_119_1.BLIF sm_amiga_i_6__n.BLIF N_119 +11 1 +.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n +0 1 +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_118_1 +11 1 +.names inst_AS_000_INTreg.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n +11 1 +.names CLK_OSZI_c.BLIF DSACK_INT_1_.C +1 1 +.names N_118_1.BLIF cpu_est_i_2__n.BLIF N_118 +11 1 +.names sm_amiga_i_5__n.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n +11 1 +.names N_55.BLIF cpu_est_0_.BLIF N_117_1 +11 1 +.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF inst_AS_000_INTreg.D +1- 1 +-1 1 +.names RST_i.BLIF DSACK_INT_1_.AP +1 1 +.names N_117_1.BLIF cpu_est_i_3__n.BLIF N_117 +11 1 +.names N_56.BLIF cpu_est_0_1__un3_n +0 1 +.names CLK_000_D0_i.BLIF SM_AMIGA_3_.BLIF N_97_1 +11 1 +.names cpu_est_1_.BLIF N_56.BLIF cpu_est_0_1__un1_n +11 1 +.names N_97_1.BLIF state_machine_un23_clk_000_d0_n.BLIF N_97 +11 1 +.names clk_cpu_est_11_1__n.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n +11 1 +.names a_i_0__n.BLIF size_c_0__n.BLIF N_81_1 +11 1 +.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D +1- 1 +-1 1 +.names CLK_OSZI_c.BLIF inst_VPA_SYNC.C +1 1 +.names N_81_1.BLIF size_i_1__n.BLIF N_81 +11 1 +.names N_56.BLIF cpu_est_0_2__un3_n +0 1 +.names N_77_1_0.BLIF inst_VPA_D.BLIF N_77 +11 1 +.names cpu_est_2_.BLIF N_56.BLIF cpu_est_0_2__un1_n +11 1 +.names RST_i.BLIF inst_VPA_SYNC.AP +1 1 +.names N_77_1.BLIF VMA_INT_i.BLIF N_75_1 +11 1 +.names N_123_i.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n +11 1 +.names VPA_D_i.BLIF cpu_est_2_.BLIF N_75_2 +11 1 +.names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D +1- 1 +-1 1 +.names cpu_est_3_reg.BLIF cpu_est_i_0__n.BLIF N_75_3 +11 1 +.names N_56.BLIF cpu_est_0_3__un3_n +0 1 +.names N_75_1.BLIF N_75_2.BLIF N_75_4 +11 1 +.names cpu_est_3_reg.BLIF N_56.BLIF cpu_est_0_3__un1_n +11 1 +.names CLK_OSZI_c.BLIF AMIGA_BUS_ENABLEDFFreg.C +1 1 +.names N_75_3.BLIF cpu_est_i_1__n.BLIF N_75_5 +11 1 +.names clk_cpu_est_11_3__n.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n +11 1 +.names N_75_4.BLIF N_75_5.BLIF N_75 +11 1 +.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_reg.D +1- 1 +-1 1 +.names N_55_i.BLIF N_59_i.BLIF N_73_1 +11 1 +.names N_56.BLIF ipl_030_0_0__un3_n +0 1 +.names inst_CLK_000_D4.BLIF inst_CLK_000_D5.D +1 1 +.names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF N_73_2 +11 1 +.names IPL_030DFFSH_0_reg.BLIF N_56.BLIF ipl_030_0_0__un1_n +11 1 +.names N_73_1.BLIF N_73_2.BLIF N_73 +11 1 +.names ipl_c_0__n.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n +11 1 +.names CLK_OSZI_c.BLIF inst_CLK_000_D5.C +1 1 +.names CLK_000_D0_i.BLIF N_146.BLIF N_72_1 +11 1 +.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF IPL_030DFFSH_0_reg.D +1- 1 +-1 1 +.names VPA_D_i.BLIF cpu_est_2_.BLIF N_72_2 +11 1 +.names N_56.BLIF ipl_030_0_1__un3_n +0 1 +.names N_72_1.BLIF N_72_2.BLIF N_72 +11 1 +.names IPL_030DFFSH_1_reg.BLIF N_56.BLIF ipl_030_0_1__un1_n +11 1 +.names N_140_i.BLIF N_85_i.BLIF sm_amiga_ns_0_1_0__n +11 1 +.names ipl_c_1__n.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n 11 1 .names CLK_OSZI_c.BLIF inst_DTACK_DMA.C 1 1 -.names N_105_1.BLIF state_machine_un23_clk_000_d0_n.BLIF N_105 +.names sm_amiga_ns_0_1_0__n.BLIF N_139_i.BLIF sm_amiga_ns_0_0__n 11 1 -.names CLK_000_D0_i.BLIF SM_AMIGA_7_.BLIF N_99 +.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF IPL_030DFFSH_1_reg.D +1- 1 +-1 1 +.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_57_i_2 11 1 -.names UDS_000_INT_0_sqmuxa_1_3.BLIF state_machine_un30_clk_000_d1_n.BLIF UDS_000_INT_0_sqmuxa_1 -11 1 -.names state_machine_un13_clk_000_d0_1_n.BLIF state_machine_un13_clk_000_d0_1_i_n +.names N_56.BLIF ipl_030_0_2__un3_n 0 1 .names RST_i.BLIF inst_DTACK_DMA.AP 1 1 -.names SM_AMIGA_4_.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_0 +.names a_i_19__n.BLIF a_i_16__n.BLIF N_57_i_3 11 1 -.names SM_AMIGA_0_.BLIF state_machine_un13_clk_000_d0_1_i_n.BLIF N_108 +.names IPL_030DFFSH_2_reg.BLIF N_56.BLIF ipl_030_0_2__un1_n 11 1 -.names UDS_000_INT_0_sqmuxa_1_0.BLIF RW_i.BLIF UDS_000_INT_0_sqmuxa +.names N_57_i_1.BLIF N_57_i_2.BLIF N_57_i_4 11 1 -.names inst_CLK_000_D0.BLIF N_97_i.BLIF SM_AMIGA_7_.D +.names ipl_c_2__n.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n 11 1 -.names CLK_000_D0_i.BLIF inst_CLK_OUT_PRE.BLIF N_96_1 +.names N_57_i_3.BLIF a_i_18__n.BLIF N_57_i_5 11 1 -.names N_98_i.BLIF N_99_i.BLIF sm_amiga_ns_0_1__n -11 1 -.names inst_CLK_000_D1.BLIF inst_CLK_000_D2.D +.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF IPL_030DFFSH_2_reg.D +1- 1 +-1 1 +.names inst_CLK_OUT_PRE.BLIF CLK_OUT_INTreg.D 1 1 -.names N_96_1.BLIF SM_AMIGA_1_.BLIF N_96 +.names N_57_i_4.BLIF N_57_i_5.BLIF N_57_i 11 1 -.names N_96_i.BLIF N_108_i.BLIF sm_amiga_ns_0_7__n +.names N_121_i.BLIF N_122_i.BLIF clk_cpu_est_11_0_1_1__n 11 1 -.names a_c_17__n.BLIF a_i_16__n.BLIF state_machine_un42_clk_030_1_n +.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF state_machine_un23_clk_000_d0_i_n 11 1 -.names AS_030_000_SYNC_i.BLIF state_machine_un30_clk_000_d1_n.BLIF N_89_i -11 1 -.names CLK_OSZI_c.BLIF inst_CLK_000_D2.C +.names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C 1 1 -.names a_i_18__n.BLIF a_i_19__n.BLIF state_machine_un42_clk_030_2_n +.names N_124_i.BLIF N_146_i.BLIF clk_cpu_est_11_0_2_1__n 11 1 -.names inst_AS_000_INTreg.BLIF SM_AMIGA_0_.BLIF N_90_0 -11 1 -.names fc_c_1__n.BLIF BGACK_000_c.BLIF state_machine_un42_clk_030_3_n -11 1 -.names UDS_000_INT_0_sqmuxa_1.BLIF UDS_000_INT_0_sqmuxa_1_i -0 1 -.names state_machine_un42_clk_030_1_n.BLIF state_machine_un42_clk_030_2_n.BLIF state_machine_un42_clk_030_4_n -11 1 -.names UDS_000_INT_0_sqmuxa.BLIF UDS_000_INT_0_sqmuxa_i -0 1 -.names state_machine_un42_clk_030_3_n.BLIF fc_c_0__n.BLIF state_machine_un42_clk_030_5_n -11 1 -.names G_86.BLIF N_132_i -0 1 -.names CLK_OSZI_c.BLIF inst_VPA_D.C -1 1 -.names state_machine_un42_clk_030_4_n.BLIF state_machine_un42_clk_030_5_n.BLIF state_machine_un42_clk_030_n -11 1 -.names G_87.BLIF N_133_i -0 1 -.names AMIGA_BUS_ENABLE_i.BLIF AS_030_i.BLIF AMIGA_BUS_ENABLE_i_m_1 -11 1 -.names N_132_i.BLIF N_133_i.BLIF clk_clk_cnt_n -11 1 -.names AMIGA_BUS_ENABLE_i_m_1.BLIF sm_amiga_i_6__n.BLIF AMIGA_BUS_ENABLE_i_m -11 1 -.names a_c_24__n.BLIF a_i_24__n -0 1 -.names CLK_000_c.BLIF inst_CLK_000_D0.D -1 1 -.names SM_AMIGA_3_.BLIF VMA_INT_i.BLIF VPA_SYNC_1_sqmuxa_1_0 -11 1 -.names a_c_25__n.BLIF a_i_25__n -0 1 -.names VPA_D_i.BLIF cpu_est_2_.BLIF VPA_SYNC_1_sqmuxa_2 -11 1 -.names a_c_26__n.BLIF a_i_26__n -0 1 -.names CLK_OSZI_c.BLIF inst_CLK_000_D0.C -1 1 -.names N_123_i.BLIF N_125_i.BLIF clk_cpu_est_11_0_2_1__n -11 1 -.names a_c_27__n.BLIF a_i_27__n +.names inst_CLK_000_D5.BLIF CLK_000_D5_i 0 1 .names clk_cpu_est_11_0_1_1__n.BLIF clk_cpu_est_11_0_2_1__n.BLIF clk_cpu_est_11_0_1__n 11 1 -.names a_c_28__n.BLIF a_i_28__n -0 1 -.names a_i_24__n.BLIF a_i_25__n.BLIF N_168_1 +.names inst_CLK_000_D4.BLIF CLK_000_D5_i.BLIF state_machine_un6_clk_000_d4_n 11 1 -.names a_c_29__n.BLIF a_i_29__n -0 1 -.names RST_c.BLIF RESETDFFreg.D -1 1 -.names a_i_26__n.BLIF a_i_27__n.BLIF N_168_2 -11 1 -.names a_c_30__n.BLIF a_i_30__n -0 1 -.names a_i_28__n.BLIF a_i_29__n.BLIF N_168_3 -11 1 -.names a_c_31__n.BLIF a_i_31__n -0 1 -.names CLK_OSZI_c.BLIF RESETDFFreg.C -1 1 -.names a_i_30__n.BLIF a_i_31__n.BLIF N_168_4 -11 1 -.names inst_CLK_000_D2.BLIF CLK_000_D2_i -0 1 -.names N_168_1.BLIF N_168_2.BLIF N_168_5 -11 1 -.names inst_CLK_000_D1.BLIF CLK_000_D2_i.BLIF state_machine_un30_clk_000_d1_n -11 1 -.names N_168_3.BLIF N_168_4.BLIF N_168_6 -11 1 -.names CLK_CNT_0_.BLIF clk_cnt_i_0__n -0 1 -.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D -1 1 -.names N_168_5.BLIF N_168_6.BLIF N_168 -11 1 -.names state_machine_un14_as_000_int_n.BLIF inst_DTACK_DMA.D -0 1 -.names a_c_20__n.BLIF a_c_21__n.BLIF N_171_1 -11 1 -.names RST_c.BLIF RST_i -0 1 -.names CLK_OSZI_c.BLIF inst_CLK_000_D1.C -1 1 -.names a_c_22__n.BLIF a_c_23__n.BLIF N_171_2 -11 1 -.names N_171_1.BLIF N_171_2.BLIF N_171 -11 1 -.names AS_030_000_SYNC_i.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_1 +.names AS_030_c.BLIF BG_030_i.BLIF N_120_1 11 1 .names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i 0 1 -.names gnd_n_n.BLIF CLK_REF_0_.D +.names inst_CLK_000_D3.BLIF inst_CLK_000_D4.D 1 1 -.names RW_c.BLIF SM_AMIGA_6_.BLIF UDS_000_INT_0_sqmuxa_1_2 +.names SM_AMIGA_7_.BLIF nEXP_SPACE_i.BLIF N_120_2 11 1 .names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i 0 1 -.names UDS_000_INT_0_sqmuxa_1_1.BLIF UDS_000_INT_0_sqmuxa_1_2.BLIF UDS_000_INT_0_sqmuxa_1_3 +.names N_120_1.BLIF N_120_2.BLIF N_120 11 1 -.names vcc_n_n -1 -.names gnd_n_n.BLIF CLK_REF_0_.LH -1 1 -.names N_89_i.BLIF N_89 +.names N_30.BLIF as_030_000_sync_0_un3_n 0 1 -.names gnd_n_n -.names N_108.BLIF N_108_i -0 1 -.names A_15_.BLIF a_15__n +.names CLK_OSZI_c.BLIF inst_CLK_000_D4.C 1 1 -.names RST_i.BLIF CLK_REF_0_.AP -1 1 -.names sm_amiga_ns_0_7__n.BLIF SM_AMIGA_0_.D -0 1 -.names A_14_.BLIF a_14__n -1 1 -.names N_98.BLIF N_98_i -0 1 -.names A_13_.BLIF a_13__n -1 1 -.names N_99.BLIF N_99_i -0 1 -.names A_12_.BLIF a_12__n -1 1 -.names gnd_n_n.BLIF CLK_REF_1_.D -1 1 -.names sm_amiga_ns_0_1__n.BLIF SM_AMIGA_6_.D -0 1 -.names A_11_.BLIF a_11__n -1 1 -.names N_97.BLIF N_97_i -0 1 -.names A_10_.BLIF a_10__n -1 1 -.names gnd_n_n.BLIF CLK_REF_1_.LH -1 1 -.names size_c_0__n.BLIF a_c_i_0__n.BLIF state_machine_un44_clk_000_d1_i_1_n +.names CLK_030_c.BLIF N_57.BLIF N_79_1 11 1 -.names A_9_.BLIF a_9__n -1 1 -.names state_machine_un44_clk_000_d1_i_1_n.BLIF size_c_i_1__n.BLIF state_machine_un44_clk_000_d1_i_n +.names un1_AMIGA_BUS_ENABLE_1_sqmuxa_2.BLIF N_30.BLIF as_030_000_sync_0_un1_n 11 1 -.names A_8_.BLIF a_8__n -1 1 -.names RST_i.BLIF CLK_REF_1_.AR -1 1 -.names BG_030_c_i.BLIF N_94_i.BLIF un1_bg_030_0_1 +.names SM_AMIGA_7_.BLIF nEXP_SPACE_c.BLIF N_79_2 11 1 -.names A_7_.BLIF a_7__n -1 1 -.names AS_030_c.BLIF nEXP_SPACE_i.BLIF un1_bg_030_0_2 +.names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n 11 1 -.names A_6_.BLIF a_6__n -1 1 -.names un1_bg_030_0_1.BLIF un1_bg_030_0_2.BLIF un1_bg_030_0 +.names N_79_1.BLIF N_79_2.BLIF N_79 11 1 -.names A_5_.BLIF a_5__n +.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF inst_AS_030_000_SYNC.D +1- 1 +-1 1 +.names inst_CLK_000_D1.BLIF inst_CLK_000_D2.D 1 1 -.names clk_un4_clk_000_d1_n.BLIF cpu_est_0_0_.X1 -1 1 -.names AS_030_i.BLIF nEXP_SPACE_c.BLIF state_machine_as_030_000_sync_3_2_1_n +.names DTACK_i.BLIF N_77_1.BLIF N_77_1_0 11 1 -.names A_4_.BLIF a_4__n -1 1 -.names state_machine_as_030_000_sync_3_2_1_n.BLIF state_machine_un42_clk_030_i_n.BLIF state_machine_as_030_000_sync_3_2_n -11 1 -.names A_3_.BLIF a_3__n -1 1 -.names cpu_est_0_.BLIF cpu_est_0_0_.X2 -1 1 -.names N_126_i.BLIF N_124_i.BLIF clk_cpu_est_11_0_1_1__n -11 1 -.names A_2_.BLIF a_2__n -1 1 -.names AMIGA_BUS_ENABLE_i_m.BLIF AMIGA_BUS_ENABLE_i_m_i -0 1 -.names A_1_.BLIF a_1__n -1 1 -.names nEXP_SPACE_m.BLIF nEXP_SPACE_m_i -0 1 -.names inst_CLK_OUT_PRE.BLIF CLK_OUT_PRE_0.X1 -1 1 -.names state_machine_as_030_000_sync_3_2_n.BLIF state_machine_as_030_000_sync_3_n -0 1 -.names N_94.BLIF N_94_i -0 1 -.names clk_clk_cnt_n.BLIF CLK_OUT_PRE_0.X2 -1 1 -.names un1_bg_030_0.BLIF un1_bg_030 -0 1 -.names size_c_1__n.BLIF size_c_i_1__n -0 1 -.names state_machine_un44_clk_000_d1_i_n.BLIF state_machine_un44_clk_000_d1_n -0 1 -.names CLK_CNT_0_.BLIF G_91.X1 -1 1 -.names N_105.BLIF N_105_i -0 1 -.names N_104.BLIF N_104_i -0 1 -.names CLK_CNT_1_.BLIF G_91.X2 -1 1 -.names sm_amiga_ns_0_5__n.BLIF SM_AMIGA_2_.D -0 1 -.names N_106.BLIF N_106_i -0 1 -.names N_107.BLIF N_107_i -0 1 -.names CLK_CNT_1_.BLIF G_87.X1 -1 1 -.names inst_CLK_OUT_PRE.BLIF CLK_OUT_PRE_i -0 1 -.names N_92_0.BLIF N_92 -0 1 -.names CLK_REF_1_.BLIF G_87.X2 -1 1 -.names N_90_0.BLIF N_90 -0 1 -.names state_machine_un13_clk_000_d0_n.BLIF state_machine_un13_clk_000_d0_i_n -0 1 -.names state_machine_un15_clk_000_d0_0_n.BLIF state_machine_un15_clk_000_d0_n -0 1 -.names CLK_CNT_0_.BLIF G_86.X1 -1 1 -.names N_100.BLIF N_100_i -0 1 -.names sm_amiga_ns_0_2__n.BLIF SM_AMIGA_5_.D -0 1 -.names CLK_REF_0_.BLIF G_86.X2 -1 1 -.names clk_un4_clk_000_d1_n.BLIF clk_un4_clk_000_d1_i_n +.names N_77.BLIF N_77_i 0 1 .names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n 0 1 +.names N_165.BLIF dtack_sync_0_un3_n +0 1 +.names CLK_OSZI_c.BLIF inst_CLK_000_D2.C +1 1 .names state_machine_un23_clk_000_d0_i_n.BLIF state_machine_un23_clk_000_d0_n 0 1 +.names N_77_i.BLIF N_165.BLIF dtack_sync_0_un1_n +11 1 +.names a_i_24__n.BLIF a_i_25__n.BLIF N_188_1 +11 1 +.names inst_DTACK_SYNC.BLIF dtack_sync_0_un3_n.BLIF dtack_sync_0_un0_n +11 1 +.names a_i_26__n.BLIF a_i_27__n.BLIF N_188_2 +11 1 +.names dtack_sync_0_un1_n.BLIF dtack_sync_0_un0_n.BLIF inst_DTACK_SYNC.D +1- 1 +-1 1 +.names inst_CLK_000_D2.BLIF inst_CLK_000_D3.D +1 1 +.names a_i_28__n.BLIF a_i_29__n.BLIF N_188_3 +11 1 +.names N_164.BLIF fpu_cs_int_0_un3_n +0 1 +.names a_i_30__n.BLIF a_i_31__n.BLIF N_188_4 +11 1 +.names AS_030_c.BLIF N_164.BLIF fpu_cs_int_0_un1_n +11 1 +.names CLK_OSZI_c.BLIF inst_CLK_000_D3.C +1 1 +.names N_188_1.BLIF N_188_2.BLIF N_188_5 +11 1 +.names inst_FPU_CS_INTreg.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un0_n +11 1 +.names N_188_3.BLIF N_188_4.BLIF N_188_6 +11 1 +.names fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF inst_FPU_CS_INTreg.D +1- 1 +-1 1 +.names N_188_5.BLIF N_188_6.BLIF N_188 +11 1 +.names N_74.BLIF N_74_i +0 1 +.names a_c_20__n.BLIF a_c_21__n.BLIF N_191_1 +11 1 +.names N_52.BLIF dsack_int_0_1__un3_n +0 1 +.names CLK_OSZI_c.BLIF inst_VPA_D.C +1 1 +.names a_c_22__n.BLIF a_c_23__n.BLIF N_191_2 +11 1 +.names N_74_i.BLIF N_52.BLIF dsack_int_0_1__un1_n +11 1 +.names N_191_1.BLIF N_191_2.BLIF N_191 +11 1 +.names DSACK_INT_1_.BLIF dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un0_n +11 1 +.names inst_CLK_000_D3.BLIF AS_030_000_SYNC_i.BLIF state_machine_un8_clk_000_d2_1_n +11 1 +.names dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF DSACK_INT_1_.D +1- 1 +-1 1 +.names state_machine_un8_clk_000_d2_1_n.BLIF CLK_000_D2_i.BLIF state_machine_un8_clk_000_d2_n +11 1 +.names N_75.BLIF N_75_i +0 1 +.names CLK_OSZI_c.BLIF inst_CLK_000_D0.C +1 1 +.names a_c_17__n.BLIF BGACK_000_c.BLIF N_57_i_1 +11 1 +.names vcc_n_n +1 +.names N_86.BLIF N_86_i +0 1 +.names gnd_n_n +.names N_83.BLIF N_83_i +0 1 +.names A_15_.BLIF a_15__n +1 1 +.names RST_c.BLIF RESETDFFreg.D +1 1 +.names N_81.BLIF N_81_i +0 1 +.names A_14_.BLIF a_14__n +1 1 +.names state_machine_lds_000_int_5_0_n.BLIF state_machine_lds_000_int_5_n +0 1 +.names A_13_.BLIF a_13__n +1 1 +.names CLK_OSZI_c.BLIF RESETDFFreg.C +1 1 +.names state_machine_uds_000_int_5_0_n.BLIF state_machine_uds_000_int_5_n +0 1 +.names A_12_.BLIF a_12__n +1 1 +.names N_79.BLIF N_79_i +0 1 +.names A_11_.BLIF a_11__n +1 1 +.names N_30_0.BLIF N_30 +0 1 +.names A_10_.BLIF a_10__n +1 1 +.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D +1 1 +.names N_165_0.BLIF N_165 +0 1 +.names A_9_.BLIF a_9__n +1 1 +.names N_76.BLIF N_76_i +0 1 +.names A_8_.BLIF a_8__n +1 1 +.names CLK_OSZI_c.BLIF inst_CLK_000_D1.C +1 1 +.names N_164_0.BLIF N_164 +0 1 +.names A_7_.BLIF a_7__n +1 1 +.names N_163_0.BLIF N_163 +0 1 +.names A_6_.BLIF a_6__n +1 1 +.names N_72.BLIF N_72_i +0 1 +.names A_5_.BLIF a_5__n +1 1 +.names gnd_n_n.BLIF CLK_REF_1_.D +1 1 +.names N_73.BLIF N_73_i +0 1 +.names A_4_.BLIF a_4__n +1 1 +.names state_machine_un15_clk_000_d0_0_n.BLIF state_machine_un15_clk_000_d0_n +0 1 +.names A_3_.BLIF a_3__n +1 1 +.names gnd_n_n.BLIF CLK_REF_1_.LH +1 1 +.names N_162_0.BLIF N_162 +0 1 +.names A_2_.BLIF a_2__n +1 1 +.names N_119.BLIF N_119_i +0 1 +.names A_1_.BLIF a_1__n +1 1 +.names RST_i.BLIF CLK_REF_1_.AR +1 1 +.names N_117.BLIF N_117_i +0 1 +.names N_118.BLIF N_118_i +0 1 +.names N_115.BLIF N_115_i +0 1 +.names inst_CLK_OUT_PRE.BLIF CLK_OUT_PRE_0.X1 +1 1 +.names N_116.BLIF N_116_i +0 1 +.names sm_amiga_ns_0_7__n.BLIF SM_AMIGA_0_.D +0 1 +.names clk_clk_cnt_n.BLIF CLK_OUT_PRE_0.X2 +1 1 +.names N_98.BLIF N_98_i +0 1 +.names N_114.BLIF N_114_i +0 1 +.names N_39_0.BLIF SM_AMIGA_1_.D +0 1 +.names CLK_CNT_0_.BLIF G_96.X1 +1 1 +.names N_94.BLIF N_94_i +0 1 +.names N_97.BLIF N_97_i +0 1 +.names CLK_CNT_1_.BLIF G_96.X2 +1 1 +.names sm_amiga_ns_0_5__n.BLIF SM_AMIGA_2_.D +0 1 +.names N_89.BLIF N_89_i +0 1 +.names N_90.BLIF N_90_i +0 1 +.names CLK_CNT_1_.BLIF G_92.X1 +1 1 +.names N_88.BLIF N_88_i +0 1 +.names inst_CLK_000_D1.BLIF CLK_000_D1_i +0 1 +.names CLK_REF_1_.BLIF G_92.X2 +1 1 +.names N_56_i.BLIF N_56 +0 1 +.names N_55_i.BLIF N_55 +0 1 +.names N_52_i.BLIF N_52 +0 1 .names CLK_OUT_PRE_0.BLIF inst_CLK_OUT_PRE.D 1 1 -.names BG_030_c.BLIF BG_030_c_i +.names N_141.BLIF N_141_i 0 1 -.names cpu_est_0_0_.BLIF cpu_est_0_.D -1 1 -.names state_machine_un1_clk_030_0_n.BLIF state_machine_un1_clk_030_n +.names N_142.BLIF N_142_i 0 1 -.names state_machine_un17_clk_030_0_n.BLIF state_machine_un17_clk_030_n +.names N_14_0.BLIF cpu_est_0_.D 0 1 -.names un1_as_030_3_0.BLIF un1_as_030_3 +.names N_85.BLIF N_85_i 0 1 -.names N_148.BLIF N_148_i +.names N_139.BLIF N_139_i 0 1 -.names a_c_0__n.BLIF a_c_i_0__n +.names N_140.BLIF N_140_i 0 1 -.names state_machine_uds_000_int_7_0_n.BLIF state_machine_uds_000_int_7_n -0 1 -.names state_machine_lds_000_int_7_0_n.BLIF state_machine_lds_000_int_7_n -0 1 -.names N_91_0.BLIF N_91 +.names sm_amiga_ns_0_0__n.BLIF SM_AMIGA_7_.D 0 1 .names N_125.BLIF N_125_i 0 1 -.names N_123.BLIF N_123_i +.names N_138.BLIF N_138_i 0 1 -.names N_124.BLIF N_124_i -0 1 -.names N_126.BLIF N_126_i -0 1 -.names clk_cpu_est_11_0_1__n.BLIF clk_cpu_est_11_1__n -0 1 -.names N_131.BLIF N_131_i +.names N_178.BLIF N_178_i 0 1 .names clk_cpu_est_11_0_3__n.BLIF clk_cpu_est_11_3__n 0 1 -.names N_130.BLIF N_130_i +.names N_121.BLIF N_121_i 0 1 -.names N_129.BLIF N_129_i +.names N_122.BLIF N_122_i 0 1 -.names N_122_i.BLIF N_122 +.names N_66_0.BLIF N_66 0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C -1 1 -.names N_121_i.BLIF N_121 +.names N_65_0.BLIF N_65 0 1 -.names N_127.BLIF N_127_i +.names N_145.BLIF N_145_i 0 1 -.names RST_i.BLIF SM_AMIGA_6_.AR -1 1 -.names N_128.BLIF N_128_i +.names un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2 0 1 -.names state_machine_un8_clk_000_d0_n.BLIF state_machine_un8_clk_000_d0_i_n +.names DS_030_c.BLIF DS_030_c_i 0 1 -.names N_101.BLIF N_101_i +.names N_63_i.BLIF N_63 +0 1 +.names N_62_i.BLIF N_62 +0 1 +.names state_machine_un6_clk_000_d4_n.BLIF state_machine_un6_clk_000_d4_i_n 0 1 .end diff --git a/Logic/BUS68030.bl1 b/Logic/BUS68030.bl1 index 52b9523..884c224 100644 --- a/Logic/BUS68030.bl1 +++ b/Logic/BUS68030.bl1 @@ -1,92 +1,75 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Thu May 22 14:56:10 2014 +#$ DATE Sat May 24 11:44:09 2014 #$ MODULE bus68030 #$ PINS 74 SIZE_1_ A_31_ IPL_030_2_ IPL_2_ DSACK_1_ FC_1_ AS_030 AS_000 DS_030 UDS_000 \ -# LDS_000 nEXP_SPACE BERR SIZE_0_ BG_030 A_30_ BG_000 A_29_ BGACK_030 A_28_ BGACK_000 A_27_ \ -# CLK_030 A_26_ CLK_000 A_25_ CLK_OSZI A_24_ CLK_DIV_OUT A_23_ CLK_EXP A_22_ FPU_CS A_21_ \ -# DTACK A_20_ AVEC A_19_ AVEC_EXP A_18_ E A_17_ VPA A_16_ VMA A_15_ RST A_14_ RESET A_13_ RW \ -# A_12_ AMIGA_BUS_ENABLE A_11_ AMIGA_BUS_DATA_DIR A_10_ AMIGA_BUS_ENABLE_LOW A_9_ CIIN \ -# A_8_ A_7_ A_6_ A_5_ A_4_ A_3_ A_2_ A_1_ A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ IPL_0_ DSACK_0_ \ -# FC_0_ -#$ NODES 372 BG_000DFFSHreg BGACK_000_c CLK_030_c inst_BGACK_030_INTreg CLK_000_c \ -# inst_FPU_CS_INTreg cpu_est_3_reg CLK_OSZI_c inst_VMA_INTreg cpu_est_0_ cpu_est_1_ \ -# CLK_OUT_INTreg inst_AS_000_INTreg inst_AS_030_000_SYNC inst_DTACK_SYNC \ -# IPL_030DFFSH_0_reg inst_VPA_D inst_VPA_SYNC IPL_030DFFSH_1_reg inst_CLK_000_D0 \ -# inst_CLK_000_D1 IPL_030DFFSH_2_reg inst_CLK_000_D2 inst_CLK_OUT_PRE ipl_c_0__n \ -# SM_AMIGA_6_ vcc_n_n ipl_c_1__n gnd_n_n cpu_est_2_ ipl_c_2__n CLK_REF_0_ CLK_REF_1_ \ -# SM_AMIGA_7_ dsack_c_1__n inst_UDS_000_INTreg inst_LDS_000_INTreg DTACK_c \ -# DSACK_INT_1_ SM_AMIGA_4_ SM_AMIGA_1_ inst_DTACK_DMA clk_clk_cnt_n CLK_CNT_0_ \ -# CLK_CNT_1_ state_machine_un14_as_000_int_n RST_c SM_AMIGA_3_ RESETDFFreg \ -# SM_AMIGA_5_ RW_c SM_AMIGA_2_ SM_AMIGA_0_ fc_c_0__n fc_c_1__n AMIGA_BUS_ENABLEDFFreg \ -# N_101_i N_102_i N_103_i CLK_OUT_PRE_0 cpu_est_0_0_ N_91_0 N_125_i N_123_i N_124_i \ -# N_126_i clk_cpu_est_11_0_1__n N_131_i clk_cpu_est_11_0_3__n N_130_i N_129_i N_122_i \ -# G_86 N_121_i G_87 N_127_i state_machine_un30_clk_000_d1_n N_128_i N_148 N_118_i \ -# DTACK_SYNC_1_sqmuxa state_machine_un8_clk_000_d0_i_n N_96 \ -# state_machine_un13_clk_000_d0_i_n G_91 state_machine_un15_clk_000_d0_0_n N_89 \ -# N_100_i N_97 sm_amiga_ns_0_2__n N_90 clk_un4_clk_000_d1_i_n N_98 \ -# state_machine_un6_bgack_000_0_n N_99 state_machine_un23_clk_000_d0_i_n N_108 \ -# BG_030_c_i UDS_000_INT_0_sqmuxa state_machine_un1_clk_030_0_n \ -# UDS_000_INT_0_sqmuxa_1 state_machine_un17_clk_030_0_n \ -# state_machine_un13_clk_000_d0_1_n un1_as_030_3_0 N_168 N_148_i N_171 a_c_i_0__n \ -# N_105 state_machine_uds_000_int_7_0_n N_92 state_machine_lds_000_int_7_0_n N_106 \ -# AMIGA_BUS_ENABLE_i_m_i N_107 nEXP_SPACE_m_i N_104 \ -# state_machine_amiga_bus_enable_2_iv_i_n state_machine_un42_clk_030_n \ -# state_machine_as_030_000_sync_3_2_n state_machine_un44_clk_000_d1_n N_94_i \ -# un1_bg_030 un1_bg_030_0 N_94 size_c_i_1__n state_machine_as_030_000_sync_3_n \ -# state_machine_un44_clk_000_d1_i_n AMIGA_BUS_ENABLE_i_m N_105_i nEXP_SPACE_m \ -# N_104_i N_95 sm_amiga_ns_0_5__n state_machine_lds_000_int_7_n N_106_i \ -# state_machine_uds_000_int_7_n N_107_i DTACK_SYNC_1_sqmuxa_1 un1_as_030_4 \ -# CLK_OUT_PRE_i un1_as_030_3 N_92_0 DSACK_INT_1_sqmuxa N_90_0 \ -# state_machine_un17_clk_030_n N_89_i state_machine_un1_clk_030_n N_108_i \ -# state_machine_un23_clk_000_d0_n sm_amiga_ns_0_7__n VPA_SYNC_1_sqmuxa N_98_i \ -# VPA_SYNC_1_sqmuxa_1 N_99_i AS_000_INT_1_sqmuxa sm_amiga_ns_0_1__n \ -# state_machine_un6_bgack_000_n N_97_i clk_un4_clk_000_d1_n N_100 \ -# state_machine_un44_clk_000_d1_i_1_n state_machine_un15_clk_000_d0_n \ -# un1_bg_030_0_1 clk_cpu_est_11_3__n un1_bg_030_0_2 state_machine_un2_clk_000_n \ -# state_machine_as_030_000_sync_3_2_1_n state_machine_un13_clk_000_d0_n \ -# clk_cpu_est_11_0_1_1__n state_machine_un8_clk_000_d0_n clk_cpu_est_11_0_2_1__n \ -# N_129 N_168_1 N_122 N_168_2 N_130 N_168_3 N_127 N_168_4 N_128 N_168_5 N_121 N_168_6 \ -# state_machine_un13_clk_000_d0_2_n N_171_1 N_131 N_171_2 clk_cpu_est_11_1__n \ -# UDS_000_INT_0_sqmuxa_1_1 N_126 UDS_000_INT_0_sqmuxa_1_2 N_124 \ -# UDS_000_INT_0_sqmuxa_1_3 N_123 UDS_000_INT_0_sqmuxa_1_0 N_125 N_96_1 N_91 \ -# state_machine_un42_clk_030_1_n N_102 state_machine_un42_clk_030_2_n N_103 \ -# state_machine_un42_clk_030_3_n N_101 state_machine_un42_clk_030_4_n RW_i \ -# state_machine_un42_clk_030_5_n AS_000_INT_i AMIGA_BUS_ENABLE_i_m_1 dsack_i_1__n \ -# VPA_SYNC_1_sqmuxa_1_0 sm_amiga_i_4__n VPA_SYNC_1_sqmuxa_2 sm_amiga_i_5__n \ -# VPA_SYNC_1_sqmuxa_3 CLK_000_D0_i VPA_SYNC_1_sqmuxa_4 sm_amiga_i_3__n \ -# VPA_SYNC_1_sqmuxa_5 cpu_est_i_0__n VPA_SYNC_1_sqmuxa_6 cpu_est_i_3__n N_127_1 \ -# cpu_est_i_2__n N_128_1 VPA_D_i N_131_1 cpu_est_i_1__n clk_cpu_est_11_0_1_3__n \ -# DTACK_i N_105_1 VMA_INT_i DTACK_SYNC_1_sqmuxa_1_0 \ -# state_machine_un13_clk_000_d0_2_i_n DTACK_SYNC_1_sqmuxa_2 CLK_000_D1_i \ -# state_machine_un8_clk_000_d0_1_n VPA_SYNC_1_sqmuxa_i \ -# state_machine_un8_clk_000_d0_2_n AS_030_i state_machine_un8_clk_000_d0_3_n N_95_i \ -# state_machine_un8_clk_000_d0_4_n DTACK_SYNC_1_sqmuxa_i \ -# state_machine_un13_clk_000_d0_1_0_n N_96_i state_machine_un13_clk_000_d0_2_0_n \ -# a_i_18__n cpu_est_0_1__un3_n a_i_16__n cpu_est_0_1__un1_n a_i_19__n \ -# cpu_est_0_1__un0_n CLK_030_i cpu_est_0_3__un3_n state_machine_un42_clk_030_i_n \ -# cpu_est_0_3__un1_n sm_amiga_i_6__n cpu_est_0_3__un0_n sm_amiga_i_7__n \ -# ipl_030_0_0__un3_n AMIGA_BUS_ENABLE_i ipl_030_0_0__un1_n nEXP_SPACE_i \ -# ipl_030_0_0__un0_n sm_amiga_i_2__n ipl_030_0_1__un3_n sm_amiga_i_1__n \ -# ipl_030_0_1__un1_n DS_030_i ipl_030_0_1__un0_n AS_030_000_SYNC_i \ -# ipl_030_0_2__un3_n UDS_000_INT_0_sqmuxa_1_i ipl_030_0_2__un1_n \ -# UDS_000_INT_0_sqmuxa_i ipl_030_0_2__un0_n state_machine_un13_clk_000_d0_1_i_n \ -# uds_000_int_0_un3_n clk_clk_cnt_i_n uds_000_int_0_un1_n clk_cnt_i_0__n \ -# uds_000_int_0_un0_n CLK_000_D2_i vpa_sync_0_un3_n a_i_30__n vpa_sync_0_un1_n \ -# a_i_31__n vpa_sync_0_un0_n a_i_28__n as_000_int_0_un3_n a_i_29__n \ -# as_000_int_0_un1_n a_i_26__n as_000_int_0_un0_n a_i_27__n bgack_030_int_0_un3_n \ -# a_i_24__n bgack_030_int_0_un1_n a_i_25__n bgack_030_int_0_un0_n N_132_i \ -# vma_int_0_un3_n N_133_i vma_int_0_un1_n vma_int_0_un0_n RST_i cpu_est_0_2__un3_n \ -# FPU_CS_INT_i cpu_est_0_2__un1_n BGACK_030_INT_i cpu_est_0_2__un0_n AS_030_c \ -# dsack_int_0_1__un3_n dsack_int_0_1__un1_n dsack_int_0_1__un0_n DS_030_c \ -# bg_000_0_un3_n bg_000_0_un1_n bg_000_0_un0_n amiga_bus_enable_0_un3_n size_c_0__n \ -# amiga_bus_enable_0_un1_n amiga_bus_enable_0_un0_n size_c_1__n \ -# as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n a_c_0__n as_030_000_sync_0_un0_n \ -# fpu_cs_int_0_un3_n fpu_cs_int_0_un1_n fpu_cs_int_0_un0_n dtack_sync_0_un3_n \ -# dtack_sync_0_un1_n dtack_sync_0_un0_n lds_000_int_0_un3_n lds_000_int_0_un1_n \ -# lds_000_int_0_un0_n a_15__n a_14__n a_13__n a_12__n a_c_16__n a_11__n a_c_17__n \ -# a_10__n a_c_18__n a_9__n a_c_19__n a_8__n a_c_20__n a_7__n a_c_21__n a_6__n a_c_22__n \ -# a_5__n a_c_23__n a_4__n a_c_24__n a_3__n a_c_25__n a_2__n a_c_26__n a_1__n a_c_27__n \ -# a_c_28__n a_c_29__n a_c_30__n a_c_31__n nEXP_SPACE_c BG_030_c +# LDS_000 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 SIZE_0_ \ +# CLK_OSZI A_30_ CLK_DIV_OUT A_29_ CLK_EXP A_28_ FPU_CS A_27_ DTACK A_26_ AVEC A_25_ \ +# AVEC_EXP A_24_ E A_23_ VPA A_22_ VMA A_21_ RST A_20_ RESET A_19_ RW A_18_ AMIGA_BUS_ENABLE \ +# A_17_ AMIGA_BUS_DATA_DIR A_16_ AMIGA_BUS_ENABLE_LOW A_15_ CIIN A_14_ A_13_ A_12_ A_11_ \ +# A_10_ A_9_ A_8_ A_7_ A_6_ A_5_ A_4_ A_3_ A_2_ A_1_ A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ IPL_0_ \ +# DSACK_0_ FC_0_ +#$ NODES 376 BGACK_000_c CLK_030_c inst_BGACK_030_INTreg inst_FPU_CS_INTreg \ +# CLK_OSZI_c cpu_est_3_reg inst_VMA_INTreg cpu_est_0_ CLK_OUT_INTreg cpu_est_1_ \ +# inst_AS_000_INTreg inst_AS_030_000_SYNC IPL_030DFFSH_0_reg inst_DTACK_SYNC \ +# inst_VPA_D IPL_030DFFSH_1_reg inst_VPA_SYNC inst_CLK_000_D0 IPL_030DFFSH_2_reg \ +# inst_CLK_000_D1 inst_CLK_000_D2 ipl_c_0__n inst_CLK_000_D5 inst_CLK_OUT_PRE \ +# ipl_c_1__n SM_AMIGA_6_ SM_AMIGA_5_ ipl_c_2__n vcc_n_n gnd_n_n cpu_est_2_ dsack_c_1__n \ +# CLK_REF_1_ inst_UDS_000_INTreg DTACK_c inst_LDS_000_INTreg DSACK_INT_1_ SM_AMIGA_7_ \ +# AS_000_INT_1_sqmuxa state_machine_un8_clk_000_d2_n inst_CLK_000_D3 SM_AMIGA_4_ \ +# state_machine_un23_clk_000_d0_n RST_c state_machine_un6_clk_000_d4_n \ +# inst_CLK_000_D4 RESETDFFreg inst_DTACK_DMA clk_clk_cnt_n RW_c CLK_CNT_0_ CLK_CNT_1_ \ +# fc_c_0__n state_machine_un6_bgack_000_n SM_AMIGA_3_ fc_c_1__n SM_AMIGA_1_ \ +# SM_AMIGA_2_ AMIGA_BUS_ENABLEDFFreg SM_AMIGA_0_ state_machine_un7_as_000_int_n \ +# state_machine_un15_clk_000_d0_n clk_cpu_est_11_0_1__n \ +# state_machine_lds_000_int_5_n N_124_i state_machine_uds_000_int_5_n N_146_i \ +# un1_AMIGA_BUS_ENABLE_1_sqmuxa_2 N_121_i N_122_i N_66_0 N_65_0 N_145_i \ +# un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 DS_030_c_i N_63_i N_62_i \ +# state_machine_un6_clk_000_d4_i_n N_61_i CLK_OUT_PRE_0 N_60_i N_59_i N_58_i N_57_i \ +# CLK_000_D1_i N_56_i N_55_i N_52_i N_141_i N_142_i N_14_0 N_85_i N_139_i \ +# clk_cpu_est_11_1__n N_140_i clk_cpu_est_11_3__n sm_amiga_ns_0_0__n G_92 N_125_i G_96 \ +# N_138_i N_162 N_178_i N_163 clk_cpu_est_11_0_3__n N_164 N_119_i N_165 N_43_i N_30 \ +# N_117_i N_118_i N_51 N_123_i N_52 N_115_i N_55 N_116_i N_56 sm_amiga_ns_0_7__n N_57 \ +# N_98_i N_58 N_114_i N_59 N_39_0 N_60 N_94_i N_61 N_97_i N_62 sm_amiga_ns_0_5__n N_63 \ +# N_89_i N_65 N_90_i N_66 N_69 N_88_i N_72 N_73 N_86_i N_74 N_75 N_83_i N_76 N_77 N_81_i N_79 \ +# state_machine_lds_000_int_5_0_n N_81 state_machine_uds_000_int_5_0_n N_83 N_79_i \ +# N_85 N_30_0 N_86 N_165_0 N_88 N_76_i N_89 N_164_0 N_90 N_163_0 N_94 N_72_i N_97 N_73_i N_98 \ +# state_machine_un15_clk_000_d0_0_n N_114 N_162_0 N_115 \ +# state_machine_un6_bgack_000_0_n N_116 state_machine_un23_clk_000_d0_i_n N_117 \ +# N_188_1 N_118 N_188_2 N_119 N_188_3 N_120 N_188_4 N_121 N_188_5 N_122 N_188_6 N_124 \ +# N_191_1 N_125 N_191_2 N_178 state_machine_un8_clk_000_d2_1_n N_138 N_57_i_1 N_139 \ +# N_57_i_2 N_140 N_57_i_3 N_141 N_57_i_4 N_142 N_57_i_5 N_145 clk_cpu_est_11_0_1_1__n \ +# N_146 clk_cpu_est_11_0_2_1__n N_77_1 N_120_1 N_188 N_120_2 N_191 N_79_1 RW_i N_79_2 \ +# VPA_D_i N_77_1_0 CLK_000_D0_i N_75_1 cpu_est_i_0__n N_75_2 cpu_est_i_3__n N_75_3 \ +# VMA_INT_i N_75_4 cpu_est_i_1__n N_75_5 DTACK_i N_73_1 BG_030_i N_73_2 nEXP_SPACE_i \ +# N_72_1 sm_amiga_i_3__n N_72_2 AS_000_INT_i sm_amiga_ns_0_1_0__n sm_amiga_i_6__n \ +# clk_cpu_est_11_0_1_3__n cpu_est_i_2__n N_138_1 AMIGA_BUS_ENABLE_i N_119_1 AS_030_i \ +# N_118_1 sm_amiga_i_4__n N_117_1 sm_amiga_i_5__n N_97_1 \ +# state_machine_un8_clk_000_d2_i_n N_81_1 sm_amiga_i_7__n \ +# state_machine_uds_000_int_5_0_m2_un3_n a_i_0__n \ +# state_machine_uds_000_int_5_0_m2_un1_n size_i_1__n \ +# state_machine_uds_000_int_5_0_m2_un0_n dsack_i_1__n vpa_sync_0_un3_n \ +# clk_clk_cnt_i_n vpa_sync_0_un1_n clk_cnt_i_0__n vpa_sync_0_un0_n CLK_000_D2_i \ +# amiga_bus_enable_0_un3_n AS_030_000_SYNC_i amiga_bus_enable_0_un1_n a_i_30__n \ +# amiga_bus_enable_0_un0_n a_i_31__n uds_000_int_0_un3_n a_i_28__n \ +# uds_000_int_0_un1_n a_i_29__n uds_000_int_0_un0_n a_i_26__n lds_000_int_0_un3_n \ +# a_i_27__n lds_000_int_0_un1_n a_i_24__n lds_000_int_0_un0_n a_i_25__n \ +# vma_int_0_un3_n a_i_19__n vma_int_0_un1_n a_i_16__n vma_int_0_un0_n a_i_18__n \ +# bg_000_0_un3_n N_137_i bg_000_0_un1_n bg_000_0_un0_n RST_i bgack_030_int_0_un3_n \ +# N_120_i bgack_030_int_0_un1_n N_75_i bgack_030_int_0_un0_n N_74_i \ +# as_000_int_0_un3_n N_77_i as_000_int_0_un1_n FPU_CS_INT_i as_000_int_0_un0_n \ +# BGACK_030_INT_i cpu_est_0_1__un3_n CLK_000_D5_i cpu_est_0_1__un1_n AS_030_c \ +# cpu_est_0_1__un0_n cpu_est_0_2__un3_n cpu_est_0_2__un1_n DS_030_c \ +# cpu_est_0_2__un0_n cpu_est_0_3__un3_n cpu_est_0_3__un1_n cpu_est_0_3__un0_n \ +# size_c_0__n ipl_030_0_0__un3_n ipl_030_0_0__un1_n size_c_1__n ipl_030_0_0__un0_n \ +# ipl_030_0_1__un3_n a_c_0__n ipl_030_0_1__un1_n ipl_030_0_1__un0_n \ +# ipl_030_0_2__un3_n ipl_030_0_2__un1_n ipl_030_0_2__un0_n as_030_000_sync_0_un3_n \ +# as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n dtack_sync_0_un3_n \ +# dtack_sync_0_un1_n dtack_sync_0_un0_n fpu_cs_int_0_un3_n fpu_cs_int_0_un1_n \ +# fpu_cs_int_0_un0_n dsack_int_0_1__un3_n dsack_int_0_1__un1_n dsack_int_0_1__un0_n \ +# a_c_16__n a_15__n a_c_17__n a_14__n a_c_18__n a_13__n a_c_19__n a_12__n a_c_20__n \ +# a_11__n a_c_21__n a_10__n a_c_22__n a_9__n a_c_23__n a_8__n a_c_24__n a_7__n a_c_25__n \ +# a_6__n a_c_26__n a_5__n a_c_27__n a_4__n a_c_28__n a_3__n a_c_29__n a_2__n a_c_30__n \ +# a_1__n a_c_31__n nEXP_SPACE_c BG_030_c BG_000DFFSHreg .model bus68030 .inputs SIZE_1_.BLIF A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF AS_030.BLIF DS_030.BLIF \ nEXP_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF \ @@ -96,242 +79,223 @@ A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF A_15_.BLIF \ A_14_.BLIF A_13_.BLIF A_12_.BLIF A_11_.BLIF A_10_.BLIF A_9_.BLIF A_8_.BLIF \ A_7_.BLIF A_6_.BLIF A_5_.BLIF A_4_.BLIF A_3_.BLIF A_2_.BLIF A_1_.BLIF \ A_0_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF DSACK_1_.BLIF DTACK.BLIF \ -DSACK_0_.BLIF BG_000DFFSHreg.BLIF BGACK_000_c.BLIF CLK_030_c.BLIF \ -inst_BGACK_030_INTreg.BLIF CLK_000_c.BLIF inst_FPU_CS_INTreg.BLIF \ -cpu_est_3_reg.BLIF CLK_OSZI_c.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF \ -cpu_est_1_.BLIF CLK_OUT_INTreg.BLIF inst_AS_000_INTreg.BLIF \ -inst_AS_030_000_SYNC.BLIF inst_DTACK_SYNC.BLIF IPL_030DFFSH_0_reg.BLIF \ -inst_VPA_D.BLIF inst_VPA_SYNC.BLIF IPL_030DFFSH_1_reg.BLIF \ -inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF IPL_030DFFSH_2_reg.BLIF \ -inst_CLK_000_D2.BLIF inst_CLK_OUT_PRE.BLIF ipl_c_0__n.BLIF SM_AMIGA_6_.BLIF \ -vcc_n_n.BLIF ipl_c_1__n.BLIF gnd_n_n.BLIF cpu_est_2_.BLIF ipl_c_2__n.BLIF \ -CLK_REF_0_.BLIF CLK_REF_1_.BLIF SM_AMIGA_7_.BLIF dsack_c_1__n.BLIF \ -inst_UDS_000_INTreg.BLIF inst_LDS_000_INTreg.BLIF DTACK_c.BLIF \ -DSACK_INT_1_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_1_.BLIF inst_DTACK_DMA.BLIF \ -clk_clk_cnt_n.BLIF CLK_CNT_0_.BLIF CLK_CNT_1_.BLIF \ -state_machine_un14_as_000_int_n.BLIF RST_c.BLIF SM_AMIGA_3_.BLIF \ -RESETDFFreg.BLIF SM_AMIGA_5_.BLIF RW_c.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_0_.BLIF \ -fc_c_0__n.BLIF fc_c_1__n.BLIF AMIGA_BUS_ENABLEDFFreg.BLIF N_101_i.BLIF \ -N_102_i.BLIF N_103_i.BLIF CLK_OUT_PRE_0.BLIF cpu_est_0_0_.BLIF N_91_0.BLIF \ -N_125_i.BLIF N_123_i.BLIF N_124_i.BLIF N_126_i.BLIF clk_cpu_est_11_0_1__n.BLIF \ -N_131_i.BLIF clk_cpu_est_11_0_3__n.BLIF N_130_i.BLIF N_129_i.BLIF N_122_i.BLIF \ -G_86.BLIF N_121_i.BLIF G_87.BLIF N_127_i.BLIF \ -state_machine_un30_clk_000_d1_n.BLIF N_128_i.BLIF N_148.BLIF N_118_i.BLIF \ -DTACK_SYNC_1_sqmuxa.BLIF state_machine_un8_clk_000_d0_i_n.BLIF N_96.BLIF \ -state_machine_un13_clk_000_d0_i_n.BLIF G_91.BLIF \ -state_machine_un15_clk_000_d0_0_n.BLIF N_89.BLIF N_100_i.BLIF N_97.BLIF \ -sm_amiga_ns_0_2__n.BLIF N_90.BLIF clk_un4_clk_000_d1_i_n.BLIF N_98.BLIF \ -state_machine_un6_bgack_000_0_n.BLIF N_99.BLIF \ -state_machine_un23_clk_000_d0_i_n.BLIF N_108.BLIF BG_030_c_i.BLIF \ -UDS_000_INT_0_sqmuxa.BLIF state_machine_un1_clk_030_0_n.BLIF \ -UDS_000_INT_0_sqmuxa_1.BLIF state_machine_un17_clk_030_0_n.BLIF \ -state_machine_un13_clk_000_d0_1_n.BLIF un1_as_030_3_0.BLIF N_168.BLIF \ -N_148_i.BLIF N_171.BLIF a_c_i_0__n.BLIF N_105.BLIF \ -state_machine_uds_000_int_7_0_n.BLIF N_92.BLIF \ -state_machine_lds_000_int_7_0_n.BLIF N_106.BLIF AMIGA_BUS_ENABLE_i_m_i.BLIF \ -N_107.BLIF nEXP_SPACE_m_i.BLIF N_104.BLIF \ -state_machine_amiga_bus_enable_2_iv_i_n.BLIF state_machine_un42_clk_030_n.BLIF \ -state_machine_as_030_000_sync_3_2_n.BLIF state_machine_un44_clk_000_d1_n.BLIF \ -N_94_i.BLIF un1_bg_030.BLIF un1_bg_030_0.BLIF N_94.BLIF size_c_i_1__n.BLIF \ -state_machine_as_030_000_sync_3_n.BLIF state_machine_un44_clk_000_d1_i_n.BLIF \ -AMIGA_BUS_ENABLE_i_m.BLIF N_105_i.BLIF nEXP_SPACE_m.BLIF N_104_i.BLIF \ -N_95.BLIF sm_amiga_ns_0_5__n.BLIF state_machine_lds_000_int_7_n.BLIF \ -N_106_i.BLIF state_machine_uds_000_int_7_n.BLIF N_107_i.BLIF \ -DTACK_SYNC_1_sqmuxa_1.BLIF un1_as_030_4.BLIF CLK_OUT_PRE_i.BLIF \ -un1_as_030_3.BLIF N_92_0.BLIF DSACK_INT_1_sqmuxa.BLIF N_90_0.BLIF \ -state_machine_un17_clk_030_n.BLIF N_89_i.BLIF state_machine_un1_clk_030_n.BLIF \ -N_108_i.BLIF state_machine_un23_clk_000_d0_n.BLIF sm_amiga_ns_0_7__n.BLIF \ -VPA_SYNC_1_sqmuxa.BLIF N_98_i.BLIF VPA_SYNC_1_sqmuxa_1.BLIF N_99_i.BLIF \ -AS_000_INT_1_sqmuxa.BLIF sm_amiga_ns_0_1__n.BLIF \ -state_machine_un6_bgack_000_n.BLIF N_97_i.BLIF clk_un4_clk_000_d1_n.BLIF \ -N_100.BLIF state_machine_un44_clk_000_d1_i_1_n.BLIF \ -state_machine_un15_clk_000_d0_n.BLIF un1_bg_030_0_1.BLIF \ -clk_cpu_est_11_3__n.BLIF un1_bg_030_0_2.BLIF state_machine_un2_clk_000_n.BLIF \ -state_machine_as_030_000_sync_3_2_1_n.BLIF \ -state_machine_un13_clk_000_d0_n.BLIF clk_cpu_est_11_0_1_1__n.BLIF \ -state_machine_un8_clk_000_d0_n.BLIF clk_cpu_est_11_0_2_1__n.BLIF N_129.BLIF \ -N_168_1.BLIF N_122.BLIF N_168_2.BLIF N_130.BLIF N_168_3.BLIF N_127.BLIF \ -N_168_4.BLIF N_128.BLIF N_168_5.BLIF N_121.BLIF N_168_6.BLIF \ -state_machine_un13_clk_000_d0_2_n.BLIF N_171_1.BLIF N_131.BLIF N_171_2.BLIF \ -clk_cpu_est_11_1__n.BLIF UDS_000_INT_0_sqmuxa_1_1.BLIF N_126.BLIF \ -UDS_000_INT_0_sqmuxa_1_2.BLIF N_124.BLIF UDS_000_INT_0_sqmuxa_1_3.BLIF \ -N_123.BLIF UDS_000_INT_0_sqmuxa_1_0.BLIF N_125.BLIF N_96_1.BLIF N_91.BLIF \ -state_machine_un42_clk_030_1_n.BLIF N_102.BLIF \ -state_machine_un42_clk_030_2_n.BLIF N_103.BLIF \ -state_machine_un42_clk_030_3_n.BLIF N_101.BLIF \ -state_machine_un42_clk_030_4_n.BLIF RW_i.BLIF \ -state_machine_un42_clk_030_5_n.BLIF AS_000_INT_i.BLIF \ -AMIGA_BUS_ENABLE_i_m_1.BLIF dsack_i_1__n.BLIF VPA_SYNC_1_sqmuxa_1_0.BLIF \ -sm_amiga_i_4__n.BLIF VPA_SYNC_1_sqmuxa_2.BLIF sm_amiga_i_5__n.BLIF \ -VPA_SYNC_1_sqmuxa_3.BLIF CLK_000_D0_i.BLIF VPA_SYNC_1_sqmuxa_4.BLIF \ -sm_amiga_i_3__n.BLIF VPA_SYNC_1_sqmuxa_5.BLIF cpu_est_i_0__n.BLIF \ -VPA_SYNC_1_sqmuxa_6.BLIF cpu_est_i_3__n.BLIF N_127_1.BLIF cpu_est_i_2__n.BLIF \ -N_128_1.BLIF VPA_D_i.BLIF N_131_1.BLIF cpu_est_i_1__n.BLIF \ -clk_cpu_est_11_0_1_3__n.BLIF DTACK_i.BLIF N_105_1.BLIF VMA_INT_i.BLIF \ -DTACK_SYNC_1_sqmuxa_1_0.BLIF state_machine_un13_clk_000_d0_2_i_n.BLIF \ -DTACK_SYNC_1_sqmuxa_2.BLIF CLK_000_D1_i.BLIF \ -state_machine_un8_clk_000_d0_1_n.BLIF VPA_SYNC_1_sqmuxa_i.BLIF \ -state_machine_un8_clk_000_d0_2_n.BLIF AS_030_i.BLIF \ -state_machine_un8_clk_000_d0_3_n.BLIF N_95_i.BLIF \ -state_machine_un8_clk_000_d0_4_n.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF \ -state_machine_un13_clk_000_d0_1_0_n.BLIF N_96_i.BLIF \ -state_machine_un13_clk_000_d0_2_0_n.BLIF a_i_18__n.BLIF \ -cpu_est_0_1__un3_n.BLIF a_i_16__n.BLIF cpu_est_0_1__un1_n.BLIF a_i_19__n.BLIF \ -cpu_est_0_1__un0_n.BLIF CLK_030_i.BLIF cpu_est_0_3__un3_n.BLIF \ -state_machine_un42_clk_030_i_n.BLIF cpu_est_0_3__un1_n.BLIF \ -sm_amiga_i_6__n.BLIF cpu_est_0_3__un0_n.BLIF sm_amiga_i_7__n.BLIF \ -ipl_030_0_0__un3_n.BLIF AMIGA_BUS_ENABLE_i.BLIF ipl_030_0_0__un1_n.BLIF \ -nEXP_SPACE_i.BLIF ipl_030_0_0__un0_n.BLIF sm_amiga_i_2__n.BLIF \ -ipl_030_0_1__un3_n.BLIF sm_amiga_i_1__n.BLIF ipl_030_0_1__un1_n.BLIF \ -DS_030_i.BLIF ipl_030_0_1__un0_n.BLIF AS_030_000_SYNC_i.BLIF \ -ipl_030_0_2__un3_n.BLIF UDS_000_INT_0_sqmuxa_1_i.BLIF ipl_030_0_2__un1_n.BLIF \ -UDS_000_INT_0_sqmuxa_i.BLIF ipl_030_0_2__un0_n.BLIF \ -state_machine_un13_clk_000_d0_1_i_n.BLIF uds_000_int_0_un3_n.BLIF \ -clk_clk_cnt_i_n.BLIF uds_000_int_0_un1_n.BLIF clk_cnt_i_0__n.BLIF \ -uds_000_int_0_un0_n.BLIF CLK_000_D2_i.BLIF vpa_sync_0_un3_n.BLIF \ -a_i_30__n.BLIF vpa_sync_0_un1_n.BLIF a_i_31__n.BLIF vpa_sync_0_un0_n.BLIF \ -a_i_28__n.BLIF as_000_int_0_un3_n.BLIF a_i_29__n.BLIF as_000_int_0_un1_n.BLIF \ -a_i_26__n.BLIF as_000_int_0_un0_n.BLIF a_i_27__n.BLIF \ -bgack_030_int_0_un3_n.BLIF a_i_24__n.BLIF bgack_030_int_0_un1_n.BLIF \ -a_i_25__n.BLIF bgack_030_int_0_un0_n.BLIF N_132_i.BLIF vma_int_0_un3_n.BLIF \ -N_133_i.BLIF vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF RST_i.BLIF \ -cpu_est_0_2__un3_n.BLIF FPU_CS_INT_i.BLIF cpu_est_0_2__un1_n.BLIF \ -BGACK_030_INT_i.BLIF cpu_est_0_2__un0_n.BLIF AS_030_c.BLIF \ -dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF \ -DS_030_c.BLIF bg_000_0_un3_n.BLIF bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF \ -amiga_bus_enable_0_un3_n.BLIF size_c_0__n.BLIF amiga_bus_enable_0_un1_n.BLIF \ -amiga_bus_enable_0_un0_n.BLIF size_c_1__n.BLIF as_030_000_sync_0_un3_n.BLIF \ -as_030_000_sync_0_un1_n.BLIF a_c_0__n.BLIF as_030_000_sync_0_un0_n.BLIF \ -fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF \ +DSACK_0_.BLIF BGACK_000_c.BLIF CLK_030_c.BLIF inst_BGACK_030_INTreg.BLIF \ +inst_FPU_CS_INTreg.BLIF CLK_OSZI_c.BLIF cpu_est_3_reg.BLIF \ +inst_VMA_INTreg.BLIF cpu_est_0_.BLIF CLK_OUT_INTreg.BLIF cpu_est_1_.BLIF \ +inst_AS_000_INTreg.BLIF inst_AS_030_000_SYNC.BLIF IPL_030DFFSH_0_reg.BLIF \ +inst_DTACK_SYNC.BLIF inst_VPA_D.BLIF IPL_030DFFSH_1_reg.BLIF \ +inst_VPA_SYNC.BLIF inst_CLK_000_D0.BLIF IPL_030DFFSH_2_reg.BLIF \ +inst_CLK_000_D1.BLIF inst_CLK_000_D2.BLIF ipl_c_0__n.BLIF inst_CLK_000_D5.BLIF \ +inst_CLK_OUT_PRE.BLIF ipl_c_1__n.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_5_.BLIF \ +ipl_c_2__n.BLIF vcc_n_n.BLIF gnd_n_n.BLIF cpu_est_2_.BLIF dsack_c_1__n.BLIF \ +CLK_REF_1_.BLIF inst_UDS_000_INTreg.BLIF DTACK_c.BLIF inst_LDS_000_INTreg.BLIF \ +DSACK_INT_1_.BLIF SM_AMIGA_7_.BLIF AS_000_INT_1_sqmuxa.BLIF \ +state_machine_un8_clk_000_d2_n.BLIF inst_CLK_000_D3.BLIF SM_AMIGA_4_.BLIF \ +state_machine_un23_clk_000_d0_n.BLIF RST_c.BLIF \ +state_machine_un6_clk_000_d4_n.BLIF inst_CLK_000_D4.BLIF RESETDFFreg.BLIF \ +inst_DTACK_DMA.BLIF clk_clk_cnt_n.BLIF RW_c.BLIF CLK_CNT_0_.BLIF \ +CLK_CNT_1_.BLIF fc_c_0__n.BLIF state_machine_un6_bgack_000_n.BLIF \ +SM_AMIGA_3_.BLIF fc_c_1__n.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_2_.BLIF \ +AMIGA_BUS_ENABLEDFFreg.BLIF SM_AMIGA_0_.BLIF \ +state_machine_un7_as_000_int_n.BLIF state_machine_un15_clk_000_d0_n.BLIF \ +clk_cpu_est_11_0_1__n.BLIF state_machine_lds_000_int_5_n.BLIF N_124_i.BLIF \ +state_machine_uds_000_int_5_n.BLIF N_146_i.BLIF \ +un1_AMIGA_BUS_ENABLE_1_sqmuxa_2.BLIF N_121_i.BLIF N_122_i.BLIF N_66_0.BLIF \ +N_65_0.BLIF N_145_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0.BLIF \ +DS_030_c_i.BLIF N_63_i.BLIF N_62_i.BLIF state_machine_un6_clk_000_d4_i_n.BLIF \ +N_61_i.BLIF CLK_OUT_PRE_0.BLIF N_60_i.BLIF N_59_i.BLIF N_58_i.BLIF N_57_i.BLIF \ +CLK_000_D1_i.BLIF N_56_i.BLIF N_55_i.BLIF N_52_i.BLIF N_141_i.BLIF \ +N_142_i.BLIF N_14_0.BLIF N_85_i.BLIF N_139_i.BLIF clk_cpu_est_11_1__n.BLIF \ +N_140_i.BLIF clk_cpu_est_11_3__n.BLIF sm_amiga_ns_0_0__n.BLIF G_92.BLIF \ +N_125_i.BLIF G_96.BLIF N_138_i.BLIF N_162.BLIF N_178_i.BLIF N_163.BLIF \ +clk_cpu_est_11_0_3__n.BLIF N_164.BLIF N_119_i.BLIF N_165.BLIF N_43_i.BLIF \ +N_30.BLIF N_117_i.BLIF N_118_i.BLIF N_51.BLIF N_123_i.BLIF N_52.BLIF \ +N_115_i.BLIF N_55.BLIF N_116_i.BLIF N_56.BLIF sm_amiga_ns_0_7__n.BLIF \ +N_57.BLIF N_98_i.BLIF N_58.BLIF N_114_i.BLIF N_59.BLIF N_39_0.BLIF N_60.BLIF \ +N_94_i.BLIF N_61.BLIF N_97_i.BLIF N_62.BLIF sm_amiga_ns_0_5__n.BLIF N_63.BLIF \ +N_89_i.BLIF N_65.BLIF N_90_i.BLIF N_66.BLIF N_69.BLIF N_88_i.BLIF N_72.BLIF \ +N_73.BLIF N_86_i.BLIF N_74.BLIF N_75.BLIF N_83_i.BLIF N_76.BLIF N_77.BLIF \ +N_81_i.BLIF N_79.BLIF state_machine_lds_000_int_5_0_n.BLIF N_81.BLIF \ +state_machine_uds_000_int_5_0_n.BLIF N_83.BLIF N_79_i.BLIF N_85.BLIF \ +N_30_0.BLIF N_86.BLIF N_165_0.BLIF N_88.BLIF N_76_i.BLIF N_89.BLIF \ +N_164_0.BLIF N_90.BLIF N_163_0.BLIF N_94.BLIF N_72_i.BLIF N_97.BLIF \ +N_73_i.BLIF N_98.BLIF state_machine_un15_clk_000_d0_0_n.BLIF N_114.BLIF \ +N_162_0.BLIF N_115.BLIF state_machine_un6_bgack_000_0_n.BLIF N_116.BLIF \ +state_machine_un23_clk_000_d0_i_n.BLIF N_117.BLIF N_188_1.BLIF N_118.BLIF \ +N_188_2.BLIF N_119.BLIF N_188_3.BLIF N_120.BLIF N_188_4.BLIF N_121.BLIF \ +N_188_5.BLIF N_122.BLIF N_188_6.BLIF N_124.BLIF N_191_1.BLIF N_125.BLIF \ +N_191_2.BLIF N_178.BLIF state_machine_un8_clk_000_d2_1_n.BLIF N_138.BLIF \ +N_57_i_1.BLIF N_139.BLIF N_57_i_2.BLIF N_140.BLIF N_57_i_3.BLIF N_141.BLIF \ +N_57_i_4.BLIF N_142.BLIF N_57_i_5.BLIF N_145.BLIF clk_cpu_est_11_0_1_1__n.BLIF \ +N_146.BLIF clk_cpu_est_11_0_2_1__n.BLIF N_77_1.BLIF N_120_1.BLIF N_188.BLIF \ +N_120_2.BLIF N_191.BLIF N_79_1.BLIF RW_i.BLIF N_79_2.BLIF VPA_D_i.BLIF \ +N_77_1_0.BLIF CLK_000_D0_i.BLIF N_75_1.BLIF cpu_est_i_0__n.BLIF N_75_2.BLIF \ +cpu_est_i_3__n.BLIF N_75_3.BLIF VMA_INT_i.BLIF N_75_4.BLIF cpu_est_i_1__n.BLIF \ +N_75_5.BLIF DTACK_i.BLIF N_73_1.BLIF BG_030_i.BLIF N_73_2.BLIF \ +nEXP_SPACE_i.BLIF N_72_1.BLIF sm_amiga_i_3__n.BLIF N_72_2.BLIF \ +AS_000_INT_i.BLIF sm_amiga_ns_0_1_0__n.BLIF sm_amiga_i_6__n.BLIF \ +clk_cpu_est_11_0_1_3__n.BLIF cpu_est_i_2__n.BLIF N_138_1.BLIF \ +AMIGA_BUS_ENABLE_i.BLIF N_119_1.BLIF AS_030_i.BLIF N_118_1.BLIF \ +sm_amiga_i_4__n.BLIF N_117_1.BLIF sm_amiga_i_5__n.BLIF N_97_1.BLIF \ +state_machine_un8_clk_000_d2_i_n.BLIF N_81_1.BLIF sm_amiga_i_7__n.BLIF \ +state_machine_uds_000_int_5_0_m2_un3_n.BLIF a_i_0__n.BLIF \ +state_machine_uds_000_int_5_0_m2_un1_n.BLIF size_i_1__n.BLIF \ +state_machine_uds_000_int_5_0_m2_un0_n.BLIF dsack_i_1__n.BLIF \ +vpa_sync_0_un3_n.BLIF clk_clk_cnt_i_n.BLIF vpa_sync_0_un1_n.BLIF \ +clk_cnt_i_0__n.BLIF vpa_sync_0_un0_n.BLIF CLK_000_D2_i.BLIF \ +amiga_bus_enable_0_un3_n.BLIF AS_030_000_SYNC_i.BLIF \ +amiga_bus_enable_0_un1_n.BLIF a_i_30__n.BLIF amiga_bus_enable_0_un0_n.BLIF \ +a_i_31__n.BLIF uds_000_int_0_un3_n.BLIF a_i_28__n.BLIF \ +uds_000_int_0_un1_n.BLIF a_i_29__n.BLIF uds_000_int_0_un0_n.BLIF \ +a_i_26__n.BLIF lds_000_int_0_un3_n.BLIF a_i_27__n.BLIF \ +lds_000_int_0_un1_n.BLIF a_i_24__n.BLIF lds_000_int_0_un0_n.BLIF \ +a_i_25__n.BLIF vma_int_0_un3_n.BLIF a_i_19__n.BLIF vma_int_0_un1_n.BLIF \ +a_i_16__n.BLIF vma_int_0_un0_n.BLIF a_i_18__n.BLIF bg_000_0_un3_n.BLIF \ +N_137_i.BLIF bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF RST_i.BLIF \ +bgack_030_int_0_un3_n.BLIF N_120_i.BLIF bgack_030_int_0_un1_n.BLIF N_75_i.BLIF \ +bgack_030_int_0_un0_n.BLIF N_74_i.BLIF as_000_int_0_un3_n.BLIF N_77_i.BLIF \ +as_000_int_0_un1_n.BLIF FPU_CS_INT_i.BLIF as_000_int_0_un0_n.BLIF \ +BGACK_030_INT_i.BLIF cpu_est_0_1__un3_n.BLIF CLK_000_D5_i.BLIF \ +cpu_est_0_1__un1_n.BLIF AS_030_c.BLIF cpu_est_0_1__un0_n.BLIF \ +cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un1_n.BLIF DS_030_c.BLIF \ +cpu_est_0_2__un0_n.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un1_n.BLIF \ +cpu_est_0_3__un0_n.BLIF size_c_0__n.BLIF ipl_030_0_0__un3_n.BLIF \ +ipl_030_0_0__un1_n.BLIF size_c_1__n.BLIF ipl_030_0_0__un0_n.BLIF \ +ipl_030_0_1__un3_n.BLIF a_c_0__n.BLIF ipl_030_0_1__un1_n.BLIF \ +ipl_030_0_1__un0_n.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un1_n.BLIF \ +ipl_030_0_2__un0_n.BLIF as_030_000_sync_0_un3_n.BLIF \ +as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF \ dtack_sync_0_un3_n.BLIF dtack_sync_0_un1_n.BLIF dtack_sync_0_un0_n.BLIF \ -lds_000_int_0_un3_n.BLIF lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF \ -a_15__n.BLIF a_14__n.BLIF a_13__n.BLIF a_12__n.BLIF a_c_16__n.BLIF \ -a_11__n.BLIF a_c_17__n.BLIF a_10__n.BLIF a_c_18__n.BLIF a_9__n.BLIF \ -a_c_19__n.BLIF a_8__n.BLIF a_c_20__n.BLIF a_7__n.BLIF a_c_21__n.BLIF \ -a_6__n.BLIF a_c_22__n.BLIF a_5__n.BLIF a_c_23__n.BLIF a_4__n.BLIF \ -a_c_24__n.BLIF a_3__n.BLIF a_c_25__n.BLIF a_2__n.BLIF a_c_26__n.BLIF \ -a_1__n.BLIF a_c_27__n.BLIF a_c_28__n.BLIF a_c_29__n.BLIF a_c_30__n.BLIF \ -a_c_31__n.BLIF nEXP_SPACE_c.BLIF BG_030_c.BLIF DSACK_1_.PIN.BLIF \ -DTACK.PIN.BLIF +fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF \ +dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF \ +a_c_16__n.BLIF a_15__n.BLIF a_c_17__n.BLIF a_14__n.BLIF a_c_18__n.BLIF \ +a_13__n.BLIF a_c_19__n.BLIF a_12__n.BLIF a_c_20__n.BLIF a_11__n.BLIF \ +a_c_21__n.BLIF a_10__n.BLIF a_c_22__n.BLIF a_9__n.BLIF a_c_23__n.BLIF \ +a_8__n.BLIF a_c_24__n.BLIF a_7__n.BLIF a_c_25__n.BLIF a_6__n.BLIF \ +a_c_26__n.BLIF a_5__n.BLIF a_c_27__n.BLIF a_4__n.BLIF a_c_28__n.BLIF \ +a_3__n.BLIF a_c_29__n.BLIF a_2__n.BLIF a_c_30__n.BLIF a_1__n.BLIF \ +a_c_31__n.BLIF nEXP_SPACE_c.BLIF BG_030_c.BLIF BG_000DFFSHreg.BLIF \ +DSACK_1_.PIN.BLIF DTACK.PIN.BLIF .outputs IPL_030_2_ AS_000 UDS_000 LDS_000 BERR BG_000 BGACK_030 CLK_DIV_OUT \ CLK_EXP FPU_CS AVEC AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR \ -AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_6_.D SM_AMIGA_6_.C \ -SM_AMIGA_6_.AR SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D \ -SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR \ -SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C \ -SM_AMIGA_1_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR cpu_est_1_.D \ -cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_reg.D cpu_est_3_reg.C \ -IPL_030DFFSH_0_reg.D IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP \ -IPL_030DFFSH_1_reg.D IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP \ -IPL_030DFFSH_2_reg.D IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D \ -SM_AMIGA_7_.C SM_AMIGA_7_.AP inst_VMA_INTreg.D inst_VMA_INTreg.C \ -inst_VMA_INTreg.AP inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C \ -inst_BGACK_030_INTreg.AP inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C CLK_CNT_0_.D \ -CLK_CNT_0_.C CLK_CNT_1_.D CLK_CNT_1_.C cpu_est_0_.D cpu_est_0_.C \ -inst_VPA_SYNC.D inst_VPA_SYNC.C inst_VPA_SYNC.AP inst_FPU_CS_INTreg.D \ -inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP inst_AS_030_000_SYNC.D \ -inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_AS_000_INTreg.D \ -inst_AS_000_INTreg.C inst_AS_000_INTreg.AP AMIGA_BUS_ENABLEDFFreg.D \ -AMIGA_BUS_ENABLEDFFreg.C BG_000DFFSHreg.D BG_000DFFSHreg.C BG_000DFFSHreg.AP \ -DSACK_INT_1_.D DSACK_INT_1_.C DSACK_INT_1_.AP inst_UDS_000_INTreg.D \ +AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ IPL_030DFFSH_0_reg.D \ +IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP IPL_030DFFSH_1_reg.D \ +IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D \ +IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D SM_AMIGA_7_.C \ +SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.D \ +SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_4_.AR \ +SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C \ +SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.D \ +SM_AMIGA_0_.C SM_AMIGA_0_.AR CLK_CNT_0_.D CLK_CNT_0_.C CLK_CNT_1_.D \ +CLK_CNT_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D \ +cpu_est_2_.C cpu_est_3_reg.D cpu_est_3_reg.C inst_UDS_000_INTreg.D \ inst_UDS_000_INTreg.C inst_UDS_000_INTreg.AP inst_LDS_000_INTreg.D \ -inst_LDS_000_INTreg.C inst_LDS_000_INTreg.AP inst_DTACK_SYNC.D \ -inst_DTACK_SYNC.C inst_DTACK_SYNC.AP CLK_OUT_INTreg.D CLK_OUT_INTreg.C \ -inst_DTACK_DMA.D inst_DTACK_DMA.C inst_DTACK_DMA.AP inst_CLK_000_D2.D \ -inst_CLK_000_D2.C inst_VPA_D.D inst_VPA_D.C inst_CLK_000_D0.D \ -inst_CLK_000_D0.C RESETDFFreg.D RESETDFFreg.C inst_CLK_000_D1.D \ -inst_CLK_000_D1.C CLK_REF_0_.D CLK_REF_0_.LH CLK_REF_0_.AP CLK_REF_1_.D \ -CLK_REF_1_.LH CLK_REF_1_.AR DSACK_1_ DTACK DSACK_0_ BGACK_000_c CLK_030_c \ -CLK_000_c CLK_OSZI_c ipl_c_0__n vcc_n_n ipl_c_1__n gnd_n_n ipl_c_2__n \ -dsack_c_1__n DTACK_c clk_clk_cnt_n state_machine_un14_as_000_int_n RST_c RW_c \ -fc_c_0__n fc_c_1__n N_101_i N_102_i N_103_i N_91_0 N_125_i N_123_i N_124_i \ -N_126_i clk_cpu_est_11_0_1__n N_131_i clk_cpu_est_11_0_3__n N_130_i N_129_i \ -N_122_i N_121_i N_127_i state_machine_un30_clk_000_d1_n N_128_i N_148 N_118_i \ -DTACK_SYNC_1_sqmuxa state_machine_un8_clk_000_d0_i_n N_96 \ -state_machine_un13_clk_000_d0_i_n state_machine_un15_clk_000_d0_0_n N_89 \ -N_100_i N_97 sm_amiga_ns_0_2__n N_90 clk_un4_clk_000_d1_i_n N_98 \ -state_machine_un6_bgack_000_0_n N_99 state_machine_un23_clk_000_d0_i_n N_108 \ -BG_030_c_i UDS_000_INT_0_sqmuxa state_machine_un1_clk_030_0_n \ -UDS_000_INT_0_sqmuxa_1 state_machine_un17_clk_030_0_n \ -state_machine_un13_clk_000_d0_1_n un1_as_030_3_0 N_168 N_148_i N_171 \ -a_c_i_0__n N_105 state_machine_uds_000_int_7_0_n N_92 \ -state_machine_lds_000_int_7_0_n N_106 AMIGA_BUS_ENABLE_i_m_i N_107 \ -nEXP_SPACE_m_i N_104 state_machine_amiga_bus_enable_2_iv_i_n \ -state_machine_un42_clk_030_n state_machine_as_030_000_sync_3_2_n \ -state_machine_un44_clk_000_d1_n N_94_i un1_bg_030 un1_bg_030_0 N_94 \ -size_c_i_1__n state_machine_as_030_000_sync_3_n \ -state_machine_un44_clk_000_d1_i_n AMIGA_BUS_ENABLE_i_m N_105_i nEXP_SPACE_m \ -N_104_i N_95 sm_amiga_ns_0_5__n state_machine_lds_000_int_7_n N_106_i \ -state_machine_uds_000_int_7_n N_107_i DTACK_SYNC_1_sqmuxa_1 un1_as_030_4 \ -CLK_OUT_PRE_i un1_as_030_3 N_92_0 DSACK_INT_1_sqmuxa N_90_0 \ -state_machine_un17_clk_030_n N_89_i state_machine_un1_clk_030_n N_108_i \ -state_machine_un23_clk_000_d0_n sm_amiga_ns_0_7__n VPA_SYNC_1_sqmuxa N_98_i \ -VPA_SYNC_1_sqmuxa_1 N_99_i AS_000_INT_1_sqmuxa sm_amiga_ns_0_1__n \ -state_machine_un6_bgack_000_n N_97_i clk_un4_clk_000_d1_n N_100 \ -state_machine_un44_clk_000_d1_i_1_n state_machine_un15_clk_000_d0_n \ -un1_bg_030_0_1 clk_cpu_est_11_3__n un1_bg_030_0_2 state_machine_un2_clk_000_n \ -state_machine_as_030_000_sync_3_2_1_n state_machine_un13_clk_000_d0_n \ -clk_cpu_est_11_0_1_1__n state_machine_un8_clk_000_d0_n clk_cpu_est_11_0_2_1__n \ -N_129 N_168_1 N_122 N_168_2 N_130 N_168_3 N_127 N_168_4 N_128 N_168_5 N_121 \ -N_168_6 state_machine_un13_clk_000_d0_2_n N_171_1 N_131 N_171_2 \ -clk_cpu_est_11_1__n UDS_000_INT_0_sqmuxa_1_1 N_126 UDS_000_INT_0_sqmuxa_1_2 \ -N_124 UDS_000_INT_0_sqmuxa_1_3 N_123 UDS_000_INT_0_sqmuxa_1_0 N_125 N_96_1 \ -N_91 state_machine_un42_clk_030_1_n N_102 state_machine_un42_clk_030_2_n N_103 \ -state_machine_un42_clk_030_3_n N_101 state_machine_un42_clk_030_4_n RW_i \ -state_machine_un42_clk_030_5_n AS_000_INT_i AMIGA_BUS_ENABLE_i_m_1 \ -dsack_i_1__n VPA_SYNC_1_sqmuxa_1_0 sm_amiga_i_4__n VPA_SYNC_1_sqmuxa_2 \ -sm_amiga_i_5__n VPA_SYNC_1_sqmuxa_3 CLK_000_D0_i VPA_SYNC_1_sqmuxa_4 \ -sm_amiga_i_3__n VPA_SYNC_1_sqmuxa_5 cpu_est_i_0__n VPA_SYNC_1_sqmuxa_6 \ -cpu_est_i_3__n N_127_1 cpu_est_i_2__n N_128_1 VPA_D_i N_131_1 cpu_est_i_1__n \ -clk_cpu_est_11_0_1_3__n DTACK_i N_105_1 VMA_INT_i DTACK_SYNC_1_sqmuxa_1_0 \ -state_machine_un13_clk_000_d0_2_i_n DTACK_SYNC_1_sqmuxa_2 CLK_000_D1_i \ -state_machine_un8_clk_000_d0_1_n VPA_SYNC_1_sqmuxa_i \ -state_machine_un8_clk_000_d0_2_n AS_030_i state_machine_un8_clk_000_d0_3_n \ -N_95_i state_machine_un8_clk_000_d0_4_n DTACK_SYNC_1_sqmuxa_i \ -state_machine_un13_clk_000_d0_1_0_n N_96_i state_machine_un13_clk_000_d0_2_0_n \ -a_i_18__n cpu_est_0_1__un3_n a_i_16__n cpu_est_0_1__un1_n a_i_19__n \ -cpu_est_0_1__un0_n CLK_030_i cpu_est_0_3__un3_n state_machine_un42_clk_030_i_n \ -cpu_est_0_3__un1_n sm_amiga_i_6__n cpu_est_0_3__un0_n sm_amiga_i_7__n \ -ipl_030_0_0__un3_n AMIGA_BUS_ENABLE_i ipl_030_0_0__un1_n nEXP_SPACE_i \ -ipl_030_0_0__un0_n sm_amiga_i_2__n ipl_030_0_1__un3_n sm_amiga_i_1__n \ -ipl_030_0_1__un1_n DS_030_i ipl_030_0_1__un0_n AS_030_000_SYNC_i \ -ipl_030_0_2__un3_n UDS_000_INT_0_sqmuxa_1_i ipl_030_0_2__un1_n \ -UDS_000_INT_0_sqmuxa_i ipl_030_0_2__un0_n state_machine_un13_clk_000_d0_1_i_n \ -uds_000_int_0_un3_n clk_clk_cnt_i_n uds_000_int_0_un1_n clk_cnt_i_0__n \ -uds_000_int_0_un0_n CLK_000_D2_i vpa_sync_0_un3_n a_i_30__n vpa_sync_0_un1_n \ -a_i_31__n vpa_sync_0_un0_n a_i_28__n as_000_int_0_un3_n a_i_29__n \ -as_000_int_0_un1_n a_i_26__n as_000_int_0_un0_n a_i_27__n \ -bgack_030_int_0_un3_n a_i_24__n bgack_030_int_0_un1_n a_i_25__n \ -bgack_030_int_0_un0_n N_132_i vma_int_0_un3_n N_133_i vma_int_0_un1_n \ -vma_int_0_un0_n RST_i cpu_est_0_2__un3_n FPU_CS_INT_i cpu_est_0_2__un1_n \ -BGACK_030_INT_i cpu_est_0_2__un0_n AS_030_c dsack_int_0_1__un3_n \ -dsack_int_0_1__un1_n dsack_int_0_1__un0_n DS_030_c bg_000_0_un3_n \ -bg_000_0_un1_n bg_000_0_un0_n amiga_bus_enable_0_un3_n size_c_0__n \ -amiga_bus_enable_0_un1_n amiga_bus_enable_0_un0_n size_c_1__n \ -as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n a_c_0__n \ -as_030_000_sync_0_un0_n fpu_cs_int_0_un3_n fpu_cs_int_0_un1_n \ -fpu_cs_int_0_un0_n dtack_sync_0_un3_n dtack_sync_0_un1_n dtack_sync_0_un0_n \ -lds_000_int_0_un3_n lds_000_int_0_un1_n lds_000_int_0_un0_n a_15__n a_14__n \ -a_13__n a_12__n a_c_16__n a_11__n a_c_17__n a_10__n a_c_18__n a_9__n a_c_19__n \ -a_8__n a_c_20__n a_7__n a_c_21__n a_6__n a_c_22__n a_5__n a_c_23__n a_4__n \ -a_c_24__n a_3__n a_c_25__n a_2__n a_c_26__n a_1__n a_c_27__n a_c_28__n \ -a_c_29__n a_c_30__n a_c_31__n nEXP_SPACE_c BG_030_c DSACK_1_.OE DTACK.OE \ -AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE \ -CLK_OUT_PRE_0 cpu_est_0_0_ G_86 G_87 G_91 -.names sm_amiga_ns_0_1__n.BLIF SM_AMIGA_6_.D +inst_LDS_000_INTreg.C inst_LDS_000_INTreg.AP inst_VMA_INTreg.D \ +inst_VMA_INTreg.C inst_VMA_INTreg.AP BG_000DFFSHreg.D BG_000DFFSHreg.C \ +BG_000DFFSHreg.AP inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C \ +inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP \ +inst_AS_000_INTreg.D inst_AS_000_INTreg.C inst_AS_000_INTreg.AP \ +inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP \ +inst_DTACK_SYNC.D inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_FPU_CS_INTreg.D \ +inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP DSACK_INT_1_.D DSACK_INT_1_.C \ +DSACK_INT_1_.AP inst_VPA_SYNC.D inst_VPA_SYNC.C inst_VPA_SYNC.AP \ +AMIGA_BUS_ENABLEDFFreg.D AMIGA_BUS_ENABLEDFFreg.C inst_CLK_000_D5.D \ +inst_CLK_000_D5.C inst_DTACK_DMA.D inst_DTACK_DMA.C inst_DTACK_DMA.AP \ +CLK_OUT_INTreg.D CLK_OUT_INTreg.C inst_CLK_000_D4.D inst_CLK_000_D4.C \ +inst_CLK_000_D2.D inst_CLK_000_D2.C inst_CLK_000_D3.D inst_CLK_000_D3.C \ +inst_VPA_D.D inst_VPA_D.C inst_CLK_000_D0.D inst_CLK_000_D0.C RESETDFFreg.D \ +RESETDFFreg.C inst_CLK_000_D1.D inst_CLK_000_D1.C CLK_REF_1_.D CLK_REF_1_.LH \ +CLK_REF_1_.AR DSACK_1_ DTACK DSACK_0_ BGACK_000_c CLK_030_c CLK_OSZI_c \ +ipl_c_0__n ipl_c_1__n ipl_c_2__n vcc_n_n gnd_n_n dsack_c_1__n DTACK_c \ +AS_000_INT_1_sqmuxa state_machine_un8_clk_000_d2_n \ +state_machine_un23_clk_000_d0_n RST_c state_machine_un6_clk_000_d4_n \ +clk_clk_cnt_n RW_c fc_c_0__n state_machine_un6_bgack_000_n fc_c_1__n \ +state_machine_un7_as_000_int_n state_machine_un15_clk_000_d0_n \ +clk_cpu_est_11_0_1__n state_machine_lds_000_int_5_n N_124_i \ +state_machine_uds_000_int_5_n N_146_i un1_AMIGA_BUS_ENABLE_1_sqmuxa_2 N_121_i \ +N_122_i N_66_0 N_65_0 N_145_i un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 DS_030_c_i \ +N_63_i N_62_i state_machine_un6_clk_000_d4_i_n N_61_i N_60_i N_59_i N_58_i \ +N_57_i CLK_000_D1_i N_56_i N_55_i N_52_i N_141_i N_142_i N_14_0 N_85_i N_139_i \ +clk_cpu_est_11_1__n N_140_i clk_cpu_est_11_3__n sm_amiga_ns_0_0__n N_125_i \ +N_138_i N_162 N_178_i N_163 clk_cpu_est_11_0_3__n N_164 N_119_i N_165 N_43_i \ +N_30 N_117_i N_118_i N_51 N_123_i N_52 N_115_i N_55 N_116_i N_56 \ +sm_amiga_ns_0_7__n N_57 N_98_i N_58 N_114_i N_59 N_39_0 N_60 N_94_i N_61 \ +N_97_i N_62 sm_amiga_ns_0_5__n N_63 N_89_i N_65 N_90_i N_66 N_69 N_88_i N_72 \ +N_73 N_86_i N_74 N_75 N_83_i N_76 N_77 N_81_i N_79 \ +state_machine_lds_000_int_5_0_n N_81 state_machine_uds_000_int_5_0_n N_83 \ +N_79_i N_85 N_30_0 N_86 N_165_0 N_88 N_76_i N_89 N_164_0 N_90 N_163_0 N_94 \ +N_72_i N_97 N_73_i N_98 state_machine_un15_clk_000_d0_0_n N_114 N_162_0 N_115 \ +state_machine_un6_bgack_000_0_n N_116 state_machine_un23_clk_000_d0_i_n N_117 \ +N_188_1 N_118 N_188_2 N_119 N_188_3 N_120 N_188_4 N_121 N_188_5 N_122 N_188_6 \ +N_124 N_191_1 N_125 N_191_2 N_178 state_machine_un8_clk_000_d2_1_n N_138 \ +N_57_i_1 N_139 N_57_i_2 N_140 N_57_i_3 N_141 N_57_i_4 N_142 N_57_i_5 N_145 \ +clk_cpu_est_11_0_1_1__n N_146 clk_cpu_est_11_0_2_1__n N_77_1 N_120_1 N_188 \ +N_120_2 N_191 N_79_1 RW_i N_79_2 VPA_D_i N_77_1_0 CLK_000_D0_i N_75_1 \ +cpu_est_i_0__n N_75_2 cpu_est_i_3__n N_75_3 VMA_INT_i N_75_4 cpu_est_i_1__n \ +N_75_5 DTACK_i N_73_1 BG_030_i N_73_2 nEXP_SPACE_i N_72_1 sm_amiga_i_3__n \ +N_72_2 AS_000_INT_i sm_amiga_ns_0_1_0__n sm_amiga_i_6__n \ +clk_cpu_est_11_0_1_3__n cpu_est_i_2__n N_138_1 AMIGA_BUS_ENABLE_i N_119_1 \ +AS_030_i N_118_1 sm_amiga_i_4__n N_117_1 sm_amiga_i_5__n N_97_1 \ +state_machine_un8_clk_000_d2_i_n N_81_1 sm_amiga_i_7__n \ +state_machine_uds_000_int_5_0_m2_un3_n a_i_0__n \ +state_machine_uds_000_int_5_0_m2_un1_n size_i_1__n \ +state_machine_uds_000_int_5_0_m2_un0_n dsack_i_1__n vpa_sync_0_un3_n \ +clk_clk_cnt_i_n vpa_sync_0_un1_n clk_cnt_i_0__n vpa_sync_0_un0_n CLK_000_D2_i \ +amiga_bus_enable_0_un3_n AS_030_000_SYNC_i amiga_bus_enable_0_un1_n a_i_30__n \ +amiga_bus_enable_0_un0_n a_i_31__n uds_000_int_0_un3_n a_i_28__n \ +uds_000_int_0_un1_n a_i_29__n uds_000_int_0_un0_n a_i_26__n \ +lds_000_int_0_un3_n a_i_27__n lds_000_int_0_un1_n a_i_24__n \ +lds_000_int_0_un0_n a_i_25__n vma_int_0_un3_n a_i_19__n vma_int_0_un1_n \ +a_i_16__n vma_int_0_un0_n a_i_18__n bg_000_0_un3_n N_137_i bg_000_0_un1_n \ +bg_000_0_un0_n RST_i bgack_030_int_0_un3_n N_120_i bgack_030_int_0_un1_n \ +N_75_i bgack_030_int_0_un0_n N_74_i as_000_int_0_un3_n N_77_i \ +as_000_int_0_un1_n FPU_CS_INT_i as_000_int_0_un0_n BGACK_030_INT_i \ +cpu_est_0_1__un3_n CLK_000_D5_i cpu_est_0_1__un1_n AS_030_c cpu_est_0_1__un0_n \ +cpu_est_0_2__un3_n cpu_est_0_2__un1_n DS_030_c cpu_est_0_2__un0_n \ +cpu_est_0_3__un3_n cpu_est_0_3__un1_n cpu_est_0_3__un0_n size_c_0__n \ +ipl_030_0_0__un3_n ipl_030_0_0__un1_n size_c_1__n ipl_030_0_0__un0_n \ +ipl_030_0_1__un3_n a_c_0__n ipl_030_0_1__un1_n ipl_030_0_1__un0_n \ +ipl_030_0_2__un3_n ipl_030_0_2__un1_n ipl_030_0_2__un0_n \ +as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n \ +dtack_sync_0_un3_n dtack_sync_0_un1_n dtack_sync_0_un0_n fpu_cs_int_0_un3_n \ +fpu_cs_int_0_un1_n fpu_cs_int_0_un0_n dsack_int_0_1__un3_n \ +dsack_int_0_1__un1_n dsack_int_0_1__un0_n a_c_16__n a_15__n a_c_17__n a_14__n \ +a_c_18__n a_13__n a_c_19__n a_12__n a_c_20__n a_11__n a_c_21__n a_10__n \ +a_c_22__n a_9__n a_c_23__n a_8__n a_c_24__n a_7__n a_c_25__n a_6__n a_c_26__n \ +a_5__n a_c_27__n a_4__n a_c_28__n a_3__n a_c_29__n a_2__n a_c_30__n a_1__n \ +a_c_31__n nEXP_SPACE_c BG_030_c DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE \ +LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_OUT_PRE_0 G_92 G_96 +.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF IPL_030DFFSH_0_reg.D +1- 1 +-1 1 +.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF IPL_030DFFSH_1_reg.D +1- 1 +-1 1 +.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF IPL_030DFFSH_2_reg.D +1- 1 +-1 1 +.names sm_amiga_ns_0_0__n.BLIF SM_AMIGA_7_.D 0 1 -.names sm_amiga_ns_0_2__n.BLIF SM_AMIGA_5_.D -0 1 -.names CLK_000_D0_i.BLIF N_101_i.BLIF SM_AMIGA_4_.D +.names N_83_i.BLIF N_85_i.BLIF SM_AMIGA_6_.D 11 1 -.names N_102_i.BLIF N_103_i.BLIF SM_AMIGA_3_.D +.names inst_CLK_000_D0.BLIF N_86_i.BLIF SM_AMIGA_5_.D +11 1 +.names CLK_000_D0_i.BLIF N_88_i.BLIF SM_AMIGA_4_.D +11 1 +.names N_89_i.BLIF N_90_i.BLIF SM_AMIGA_3_.D 11 1 .names sm_amiga_ns_0_5__n.BLIF SM_AMIGA_2_.D 0 1 -.names N_106_i.BLIF N_107_i.BLIF SM_AMIGA_1_.D -11 1 +.names N_39_0.BLIF SM_AMIGA_1_.D +0 1 .names sm_amiga_ns_0_7__n.BLIF SM_AMIGA_0_.D 0 1 +.names clk_cnt_i_0__n.BLIF clk_clk_cnt_i_n.BLIF CLK_CNT_0_.D +11 1 +.names clk_clk_cnt_i_n.BLIF G_96.BLIF CLK_CNT_1_.D +11 1 +.names N_14_0.BLIF cpu_est_0_.D +0 1 .names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D 1- 1 -1 1 @@ -341,647 +305,620 @@ CLK_OUT_PRE_0 cpu_est_0_0_ G_86 G_87 G_91 .names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_reg.D 1- 1 -1 1 -.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF IPL_030DFFSH_0_reg.D -1- 1 --1 1 -.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF IPL_030DFFSH_1_reg.D -1- 1 --1 1 -.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF IPL_030DFFSH_2_reg.D -1- 1 --1 1 -.names inst_CLK_000_D0.BLIF N_97_i.BLIF SM_AMIGA_7_.D -11 1 -.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D -1- 1 --1 1 -.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF \ -inst_BGACK_030_INTreg.D -1- 1 --1 1 -.names clk_cnt_i_0__n.BLIF clk_clk_cnt_i_n.BLIF CLK_CNT_0_.D -11 1 -.names clk_clk_cnt_i_n.BLIF G_91.BLIF CLK_CNT_1_.D -11 1 -.names vpa_sync_0_un1_n.BLIF vpa_sync_0_un0_n.BLIF inst_VPA_SYNC.D -1- 1 --1 1 -.names fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF inst_FPU_CS_INTreg.D -1- 1 --1 1 -.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF \ -inst_AS_030_000_SYNC.D -1- 1 --1 1 -.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF inst_AS_000_INTreg.D -1- 1 --1 1 -.names amiga_bus_enable_0_un1_n.BLIF amiga_bus_enable_0_un0_n.BLIF \ -AMIGA_BUS_ENABLEDFFreg.D -1- 1 --1 1 -.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF BG_000DFFSHreg.D -1- 1 --1 1 -.names dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF DSACK_INT_1_.D -1- 1 --1 1 .names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INTreg.D 1- 1 -1 1 .names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF inst_LDS_000_INTreg.D 1- 1 -1 1 +.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D +1- 1 +-1 1 +.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF BG_000DFFSHreg.D +1- 1 +-1 1 +.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF \ +inst_BGACK_030_INTreg.D +1- 1 +-1 1 +.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF inst_AS_000_INTreg.D +1- 1 +-1 1 +.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF \ +inst_AS_030_000_SYNC.D +1- 1 +-1 1 .names dtack_sync_0_un1_n.BLIF dtack_sync_0_un0_n.BLIF inst_DTACK_SYNC.D 1- 1 -1 1 -.names state_machine_un14_as_000_int_n.BLIF inst_DTACK_DMA.D +.names fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF inst_FPU_CS_INTreg.D +1- 1 +-1 1 +.names dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF DSACK_INT_1_.D +1- 1 +-1 1 +.names vpa_sync_0_un1_n.BLIF vpa_sync_0_un0_n.BLIF inst_VPA_SYNC.D +1- 1 +-1 1 +.names amiga_bus_enable_0_un1_n.BLIF amiga_bus_enable_0_un0_n.BLIF \ +AMIGA_BUS_ENABLEDFFreg.D +1- 1 +-1 1 +.names state_machine_un7_as_000_int_n.BLIF inst_DTACK_DMA.D 0 1 .names vcc_n_n 1 .names gnd_n_n -.names N_132_i.BLIF N_133_i.BLIF clk_clk_cnt_n +.names AS_030_i.BLIF sm_amiga_i_5__n.BLIF AS_000_INT_1_sqmuxa 11 1 -.names AS_000_INT_i.BLIF dsack_i_1__n.BLIF state_machine_un14_as_000_int_n +.names state_machine_un8_clk_000_d2_1_n.BLIF CLK_000_D2_i.BLIF \ +state_machine_un8_clk_000_d2_n 11 1 -.names N_101.BLIF N_101_i +.names state_machine_un23_clk_000_d0_i_n.BLIF state_machine_un23_clk_000_d0_n 0 1 -.names N_102.BLIF N_102_i -0 1 -.names N_103.BLIF N_103_i -0 1 -.names SM_AMIGA_3_.BLIF state_machine_un23_clk_000_d0_i_n.BLIF N_91_0 +.names inst_CLK_000_D4.BLIF CLK_000_D5_i.BLIF state_machine_un6_clk_000_d4_n 11 1 -.names N_125.BLIF N_125_i +.names clk_cnt_i_0__n.BLIF N_137_i.BLIF clk_clk_cnt_n +11 1 +.names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n 0 1 -.names N_123.BLIF N_123_i -0 1 -.names N_124.BLIF N_124_i -0 1 -.names N_126.BLIF N_126_i +.names AS_000_INT_i.BLIF dsack_i_1__n.BLIF state_machine_un7_as_000_int_n +11 1 +.names state_machine_un15_clk_000_d0_0_n.BLIF state_machine_un15_clk_000_d0_n 0 1 .names clk_cpu_est_11_0_1_1__n.BLIF clk_cpu_est_11_0_2_1__n.BLIF \ clk_cpu_est_11_0_1__n 11 1 -.names N_131.BLIF N_131_i +.names state_machine_lds_000_int_5_0_n.BLIF state_machine_lds_000_int_5_n 0 1 -.names clk_cpu_est_11_0_1_3__n.BLIF N_130_i.BLIF clk_cpu_est_11_0_3__n -11 1 -.names N_130.BLIF N_130_i +.names N_124.BLIF N_124_i 0 1 -.names N_129.BLIF N_129_i +.names state_machine_uds_000_int_5_0_n.BLIF state_machine_uds_000_int_5_n 0 1 -.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_122_i -11 1 -.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF N_121_i -11 1 -.names N_127.BLIF N_127_i +.names N_146.BLIF N_146_i 0 1 -.names inst_CLK_000_D1.BLIF CLK_000_D2_i.BLIF state_machine_un30_clk_000_d1_n -11 1 -.names N_128.BLIF N_128_i +.names un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2 0 1 -.names UDS_000_INT_0_sqmuxa_1_i.BLIF UDS_000_INT_0_sqmuxa_i.BLIF N_148 -11 1 -.names N_127_i.BLIF N_128_i.BLIF N_118_i -11 1 -.names DTACK_SYNC_1_sqmuxa_1_0.BLIF DTACK_SYNC_1_sqmuxa_2.BLIF \ -DTACK_SYNC_1_sqmuxa -11 1 -.names state_machine_un8_clk_000_d0_n.BLIF state_machine_un8_clk_000_d0_i_n +.names N_121.BLIF N_121_i 0 1 -.names N_96_1.BLIF SM_AMIGA_1_.BLIF N_96 -11 1 -.names state_machine_un13_clk_000_d0_n.BLIF state_machine_un13_clk_000_d0_i_n +.names N_122.BLIF N_122_i 0 1 -.names state_machine_un8_clk_000_d0_i_n.BLIF \ -state_machine_un13_clk_000_d0_i_n.BLIF state_machine_un15_clk_000_d0_0_n +.names SM_AMIGA_3_.BLIF state_machine_un23_clk_000_d0_i_n.BLIF N_66_0 11 1 -.names N_89_i.BLIF N_89 +.names CLK_000_D0_i.BLIF N_58_i.BLIF N_65_0 +11 1 +.names N_145.BLIF N_145_i 0 1 -.names N_100.BLIF N_100_i +.names N_52_i.BLIF N_145_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 +11 1 +.names DS_030_c.BLIF DS_030_c_i 0 1 -.names N_90.BLIF sm_amiga_i_7__n.BLIF N_97 +.names DS_030_c_i.BLIF N_51.BLIF N_63_i 11 1 -.names N_95_i.BLIF N_100_i.BLIF sm_amiga_ns_0_2__n +.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_62_i 11 1 -.names N_90_0.BLIF N_90 +.names state_machine_un6_clk_000_d4_n.BLIF state_machine_un6_clk_000_d4_i_n 0 1 -.names clk_un4_clk_000_d1_n.BLIF clk_un4_clk_000_d1_i_n +.names CLK_000_D0_i.BLIF state_machine_un6_clk_000_d4_i_n.BLIF N_61_i +11 1 +.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF N_60_i +11 1 +.names inst_AS_000_INTreg.BLIF inst_CLK_000_D0.BLIF N_59_i +11 1 +.names SM_AMIGA_6_.BLIF nEXP_SPACE_c.BLIF N_58_i +11 1 +.names N_57_i_4.BLIF N_57_i_5.BLIF N_57_i +11 1 +.names inst_CLK_000_D1.BLIF CLK_000_D1_i 0 1 -.names N_89.BLIF SM_AMIGA_6_.BLIF N_98 +.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF N_56_i 11 1 -.names BGACK_000_c.BLIF clk_un4_clk_000_d1_i_n.BLIF \ -state_machine_un6_bgack_000_0_n +.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_55_i 11 1 -.names CLK_000_D0_i.BLIF SM_AMIGA_7_.BLIF N_99 +.names AS_030_i.BLIF N_74_i.BLIF N_52_i +11 1 +.names N_141.BLIF N_141_i +0 1 +.names N_142.BLIF N_142_i +0 1 +.names N_141_i.BLIF N_142_i.BLIF N_14_0 +11 1 +.names N_85.BLIF N_85_i +0 1 +.names N_139.BLIF N_139_i +0 1 +.names clk_cpu_est_11_0_1__n.BLIF clk_cpu_est_11_1__n +0 1 +.names N_140.BLIF N_140_i +0 1 +.names clk_cpu_est_11_0_3__n.BLIF clk_cpu_est_11_3__n +0 1 +.names sm_amiga_ns_0_1_0__n.BLIF N_139_i.BLIF sm_amiga_ns_0_0__n +11 1 +.names N_125.BLIF N_125_i +0 1 +.names N_138.BLIF N_138_i +0 1 +.names N_162_0.BLIF N_162 +0 1 +.names N_178.BLIF N_178_i +0 1 +.names N_163_0.BLIF N_163 +0 1 +.names clk_cpu_est_11_0_1_3__n.BLIF N_138_i.BLIF clk_cpu_est_11_0_3__n +11 1 +.names N_164_0.BLIF N_164 +0 1 +.names N_119.BLIF N_119_i +0 1 +.names N_165_0.BLIF N_165 +0 1 +.names N_58.BLIF N_119_i.BLIF N_43_i +11 1 +.names N_30_0.BLIF N_30 +0 1 +.names N_117.BLIF N_117_i +0 1 +.names N_118.BLIF N_118_i +0 1 +.names state_machine_uds_000_int_5_0_m2_un1_n.BLIF \ +state_machine_uds_000_int_5_0_m2_un0_n.BLIF N_51 +1- 1 +-1 1 +.names N_117_i.BLIF N_118_i.BLIF N_123_i +11 1 +.names N_52_i.BLIF N_52 +0 1 +.names N_115.BLIF N_115_i +0 1 +.names N_55_i.BLIF N_55 +0 1 +.names N_116.BLIF N_116_i +0 1 +.names N_56_i.BLIF N_56 +0 1 +.names N_115_i.BLIF N_116_i.BLIF sm_amiga_ns_0_7__n +11 1 +.names N_57_i.BLIF N_57 +0 1 +.names N_98.BLIF N_98_i +0 1 +.names N_58_i.BLIF N_58 +0 1 +.names N_114.BLIF N_114_i +0 1 +.names N_59_i.BLIF N_59 +0 1 +.names N_98_i.BLIF N_114_i.BLIF N_39_0 +11 1 +.names N_60_i.BLIF N_60 +0 1 +.names N_94.BLIF N_94_i +0 1 +.names N_61_i.BLIF N_61 +0 1 +.names N_97.BLIF N_97_i +0 1 +.names N_62_i.BLIF N_62 +0 1 +.names N_94_i.BLIF N_97_i.BLIF sm_amiga_ns_0_5__n +11 1 +.names N_63_i.BLIF N_63 +0 1 +.names N_89.BLIF N_89_i +0 1 +.names N_65_0.BLIF N_65 +0 1 +.names N_90.BLIF N_90_i +0 1 +.names N_66_0.BLIF N_66 +0 1 +.names BG_030_i.BLIF CLK_030_c.BLIF N_69 +11 1 +.names N_88.BLIF N_88_i +0 1 +.names N_72_1.BLIF N_72_2.BLIF N_72 +11 1 +.names N_73_1.BLIF N_73_2.BLIF N_73 +11 1 +.names N_86.BLIF N_86_i +0 1 +.names SM_AMIGA_1_.BLIF state_machine_un6_clk_000_d4_n.BLIF N_74 +11 1 +.names N_75_4.BLIF N_75_5.BLIF N_75 +11 1 +.names N_83.BLIF N_83_i +0 1 +.names CLK_030_c.BLIF N_57_i.BLIF N_76 +11 1 +.names N_77_1_0.BLIF inst_VPA_D.BLIF N_77 +11 1 +.names N_81.BLIF N_81_i +0 1 +.names N_79_1.BLIF N_79_2.BLIF N_79 +11 1 +.names N_63_i.BLIF N_81_i.BLIF state_machine_lds_000_int_5_0_n +11 1 +.names N_81_1.BLIF size_i_1__n.BLIF N_81 +11 1 +.names a_i_0__n.BLIF N_63_i.BLIF state_machine_uds_000_int_5_0_n +11 1 +.names N_65.BLIF sm_amiga_i_7__n.BLIF N_83 +11 1 +.names N_79.BLIF N_79_i +0 1 +.names SM_AMIGA_7_.BLIF state_machine_un8_clk_000_d2_i_n.BLIF N_85 +11 1 +.names N_79_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0.BLIF N_30_0 +11 1 +.names sm_amiga_i_5__n.BLIF sm_amiga_i_6__n.BLIF N_86 +11 1 +.names AS_030_i.BLIF N_77_i.BLIF N_165_0 +11 1 +.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_88 +11 1 +.names N_76.BLIF N_76_i +0 1 +.names CLK_000_D0_i.BLIF N_66.BLIF N_89 +11 1 +.names AS_030_i.BLIF N_76_i.BLIF N_164_0 +11 1 +.names sm_amiga_i_3__n.BLIF sm_amiga_i_4__n.BLIF N_90 +11 1 +.names AS_030_i.BLIF N_75_i.BLIF N_163_0 +11 1 +.names CLK_000_D0_i.BLIF SM_AMIGA_2_.BLIF N_94 +11 1 +.names N_72.BLIF N_72_i +0 1 +.names N_97_1.BLIF state_machine_un23_clk_000_d0_n.BLIF N_97 +11 1 +.names N_73.BLIF N_73_i +0 1 +.names N_61.BLIF SM_AMIGA_1_.BLIF N_98 +11 1 +.names N_72_i.BLIF N_73_i.BLIF state_machine_un15_clk_000_d0_0_n +11 1 +.names inst_CLK_000_D0.BLIF SM_AMIGA_2_.BLIF N_114 +11 1 +.names AS_030_i.BLIF N_63.BLIF N_162_0 +11 1 +.names N_59.BLIF SM_AMIGA_0_.BLIF N_115 +11 1 +.names BGACK_000_c.BLIF N_56.BLIF state_machine_un6_bgack_000_0_n +11 1 +.names N_61_i.BLIF SM_AMIGA_1_.BLIF N_116 11 1 .names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF \ state_machine_un23_clk_000_d0_i_n 11 1 -.names SM_AMIGA_0_.BLIF state_machine_un13_clk_000_d0_1_i_n.BLIF N_108 +.names N_117_1.BLIF cpu_est_i_3__n.BLIF N_117 11 1 -.names BG_030_c.BLIF BG_030_c_i -0 1 -.names UDS_000_INT_0_sqmuxa_1_0.BLIF RW_i.BLIF UDS_000_INT_0_sqmuxa +.names a_i_24__n.BLIF a_i_25__n.BLIF N_188_1 11 1 -.names BG_030_c_i.BLIF CLK_030_c.BLIF state_machine_un1_clk_030_0_n +.names N_118_1.BLIF cpu_est_i_2__n.BLIF N_118 11 1 -.names UDS_000_INT_0_sqmuxa_1_3.BLIF state_machine_un30_clk_000_d1_n.BLIF \ -UDS_000_INT_0_sqmuxa_1 +.names a_i_26__n.BLIF a_i_27__n.BLIF N_188_2 11 1 -.names AS_030_i.BLIF CLK_030_i.BLIF state_machine_un17_clk_030_0_n +.names N_119_1.BLIF sm_amiga_i_6__n.BLIF N_119 11 1 -.names inst_AS_000_INTreg.BLIF inst_CLK_000_D0.BLIF \ -state_machine_un13_clk_000_d0_1_n +.names a_i_28__n.BLIF a_i_29__n.BLIF N_188_3 11 1 -.names AS_030_i.BLIF state_machine_un42_clk_030_n.BLIF un1_as_030_3_0 +.names N_120_1.BLIF N_120_2.BLIF N_120 11 1 -.names N_168_5.BLIF N_168_6.BLIF N_168 +.names a_i_30__n.BLIF a_i_31__n.BLIF N_188_4 11 1 -.names N_148.BLIF N_148_i -0 1 -.names N_171_1.BLIF N_171_2.BLIF N_171 +.names N_60.BLIF cpu_est_i_0__n.BLIF N_121 11 1 -.names a_c_0__n.BLIF a_c_i_0__n -0 1 -.names N_105_1.BLIF state_machine_un23_clk_000_d0_n.BLIF N_105 +.names N_188_1.BLIF N_188_2.BLIF N_188_5 11 1 -.names a_c_i_0__n.BLIF N_148_i.BLIF state_machine_uds_000_int_7_0_n +.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_122 11 1 -.names N_92_0.BLIF N_92 -0 1 -.names N_148_i.BLIF state_machine_un44_clk_000_d1_n.BLIF \ -state_machine_lds_000_int_7_0_n +.names N_188_3.BLIF N_188_4.BLIF N_188_6 11 1 -.names CLK_000_D0_i.BLIF N_92.BLIF N_106 +.names N_55_i.BLIF cpu_est_3_reg.BLIF N_124 11 1 -.names AMIGA_BUS_ENABLE_i_m.BLIF AMIGA_BUS_ENABLE_i_m_i -0 1 -.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_107 +.names a_c_20__n.BLIF a_c_21__n.BLIF N_191_1 11 1 -.names nEXP_SPACE_m.BLIF nEXP_SPACE_m_i -0 1 -.names CLK_000_D0_i.BLIF SM_AMIGA_2_.BLIF N_104 +.names N_62.BLIF cpu_est_3_reg.BLIF N_125 11 1 -.names AMIGA_BUS_ENABLE_i_m_i.BLIF nEXP_SPACE_m_i.BLIF \ -state_machine_amiga_bus_enable_2_iv_i_n +.names a_c_22__n.BLIF a_c_23__n.BLIF N_191_2 11 1 -.names state_machine_un42_clk_030_4_n.BLIF state_machine_un42_clk_030_5_n.BLIF \ -state_machine_un42_clk_030_n +.names N_62_i.BLIF cpu_est_i_2__n.BLIF N_178 11 1 -.names state_machine_as_030_000_sync_3_2_1_n.BLIF \ -state_machine_un42_clk_030_i_n.BLIF state_machine_as_030_000_sync_3_2_n +.names inst_CLK_000_D3.BLIF AS_030_000_SYNC_i.BLIF \ +state_machine_un8_clk_000_d2_1_n 11 1 -.names state_machine_un44_clk_000_d1_i_n.BLIF state_machine_un44_clk_000_d1_n -0 1 -.names N_94.BLIF N_94_i -0 1 -.names un1_bg_030_0.BLIF un1_bg_030 -0 1 -.names un1_bg_030_0_1.BLIF un1_bg_030_0_2.BLIF un1_bg_030_0 +.names N_138_1.BLIF cpu_est_i_2__n.BLIF N_138 11 1 -.names sm_amiga_i_6__n.BLIF sm_amiga_i_7__n.BLIF N_94 +.names a_c_17__n.BLIF BGACK_000_c.BLIF N_57_i_1 11 1 -.names size_c_1__n.BLIF size_c_i_1__n -0 1 -.names state_machine_as_030_000_sync_3_2_n.BLIF \ -state_machine_as_030_000_sync_3_n -0 1 -.names state_machine_un44_clk_000_d1_i_1_n.BLIF size_c_i_1__n.BLIF \ -state_machine_un44_clk_000_d1_i_n +.names CLK_000_D0_i.BLIF N_145.BLIF N_139 11 1 -.names AMIGA_BUS_ENABLE_i_m_1.BLIF sm_amiga_i_6__n.BLIF AMIGA_BUS_ENABLE_i_m +.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_57_i_2 11 1 -.names N_105.BLIF N_105_i -0 1 -.names SM_AMIGA_6_.BLIF nEXP_SPACE_c.BLIF nEXP_SPACE_m +.names N_59_i.BLIF SM_AMIGA_0_.BLIF N_140 11 1 -.names N_104.BLIF N_104_i -0 1 -.names N_89_i.BLIF SM_AMIGA_6_.BLIF N_95 +.names a_i_19__n.BLIF a_i_16__n.BLIF N_57_i_3 11 1 -.names N_104_i.BLIF N_105_i.BLIF sm_amiga_ns_0_5__n +.names N_56.BLIF cpu_est_0_.BLIF N_141 11 1 -.names state_machine_lds_000_int_7_0_n.BLIF state_machine_lds_000_int_7_n -0 1 -.names N_106.BLIF N_106_i -0 1 -.names state_machine_uds_000_int_7_0_n.BLIF state_machine_uds_000_int_7_n -0 1 -.names N_107.BLIF N_107_i -0 1 -.names AS_030_i.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF DTACK_SYNC_1_sqmuxa_1 +.names N_57_i_1.BLIF N_57_i_2.BLIF N_57_i_4 11 1 -.names AS_030_i.BLIF N_148.BLIF un1_as_030_4 +.names N_56_i.BLIF cpu_est_i_0__n.BLIF N_142 11 1 -.names inst_CLK_OUT_PRE.BLIF CLK_OUT_PRE_i -0 1 -.names un1_as_030_3_0.BLIF un1_as_030_3 -0 1 -.names CLK_OUT_PRE_i.BLIF sm_amiga_i_2__n.BLIF N_92_0 +.names N_57_i_3.BLIF a_i_18__n.BLIF N_57_i_5 11 1 -.names AS_030_i.BLIF N_96_i.BLIF DSACK_INT_1_sqmuxa +.names SM_AMIGA_6_.BLIF nEXP_SPACE_i.BLIF N_145 11 1 -.names inst_AS_000_INTreg.BLIF SM_AMIGA_0_.BLIF N_90_0 +.names N_121_i.BLIF N_122_i.BLIF clk_cpu_est_11_0_1_1__n 11 1 -.names state_machine_un17_clk_030_0_n.BLIF state_machine_un17_clk_030_n -0 1 -.names AS_030_000_SYNC_i.BLIF state_machine_un30_clk_000_d1_n.BLIF N_89_i +.names N_60_i.BLIF cpu_est_0_.BLIF N_146 11 1 -.names state_machine_un1_clk_030_0_n.BLIF state_machine_un1_clk_030_n -0 1 -.names N_108.BLIF N_108_i -0 1 -.names state_machine_un23_clk_000_d0_i_n.BLIF state_machine_un23_clk_000_d0_n -0 1 -.names N_96_i.BLIF N_108_i.BLIF sm_amiga_ns_0_7__n +.names N_124_i.BLIF N_146_i.BLIF clk_cpu_est_11_0_2_1__n 11 1 -.names VPA_SYNC_1_sqmuxa_5.BLIF VPA_SYNC_1_sqmuxa_6.BLIF VPA_SYNC_1_sqmuxa +.names inst_CLK_000_D0.BLIF SM_AMIGA_3_.BLIF N_77_1 11 1 -.names N_98.BLIF N_98_i -0 1 -.names AS_030_i.BLIF VPA_SYNC_1_sqmuxa_i.BLIF VPA_SYNC_1_sqmuxa_1 +.names AS_030_c.BLIF BG_030_i.BLIF N_120_1 11 1 -.names N_99.BLIF N_99_i -0 1 -.names AS_030_i.BLIF N_95_i.BLIF AS_000_INT_1_sqmuxa +.names N_188_5.BLIF N_188_6.BLIF N_188 11 1 -.names N_98_i.BLIF N_99_i.BLIF sm_amiga_ns_0_1__n +.names SM_AMIGA_7_.BLIF nEXP_SPACE_i.BLIF N_120_2 11 1 -.names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n -0 1 -.names N_97.BLIF N_97_i -0 1 -.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF clk_un4_clk_000_d1_n +.names N_191_1.BLIF N_191_2.BLIF N_191 11 1 -.names inst_CLK_000_D0.BLIF SM_AMIGA_5_.BLIF N_100 -11 1 -.names size_c_0__n.BLIF a_c_i_0__n.BLIF state_machine_un44_clk_000_d1_i_1_n -11 1 -.names state_machine_un15_clk_000_d0_0_n.BLIF state_machine_un15_clk_000_d0_n -0 1 -.names BG_030_c_i.BLIF N_94_i.BLIF un1_bg_030_0_1 -11 1 -.names clk_cpu_est_11_0_3__n.BLIF clk_cpu_est_11_3__n -0 1 -.names AS_030_c.BLIF nEXP_SPACE_i.BLIF un1_bg_030_0_2 -11 1 -.names inst_CLK_000_D0.BLIF CLK_000_c.BLIF state_machine_un2_clk_000_n -11 1 -.names AS_030_i.BLIF nEXP_SPACE_c.BLIF state_machine_as_030_000_sync_3_2_1_n -11 1 -.names state_machine_un13_clk_000_d0_1_0_n.BLIF \ -state_machine_un13_clk_000_d0_2_0_n.BLIF state_machine_un13_clk_000_d0_n -11 1 -.names N_126_i.BLIF N_124_i.BLIF clk_cpu_est_11_0_1_1__n -11 1 -.names state_machine_un8_clk_000_d0_4_n.BLIF \ -state_machine_un8_clk_000_d0_3_n.BLIF state_machine_un8_clk_000_d0_n -11 1 -.names N_123_i.BLIF N_125_i.BLIF clk_cpu_est_11_0_2_1__n -11 1 -.names N_122.BLIF cpu_est_3_reg.BLIF N_129 -11 1 -.names a_i_24__n.BLIF a_i_25__n.BLIF N_168_1 -11 1 -.names N_122_i.BLIF N_122 -0 1 -.names a_i_26__n.BLIF a_i_27__n.BLIF N_168_2 -11 1 -.names N_122_i.BLIF cpu_est_i_2__n.BLIF N_130 -11 1 -.names a_i_28__n.BLIF a_i_29__n.BLIF N_168_3 -11 1 -.names N_127_1.BLIF state_machine_un13_clk_000_d0_2_i_n.BLIF N_127 -11 1 -.names a_i_30__n.BLIF a_i_31__n.BLIF N_168_4 -11 1 -.names N_128_1.BLIF cpu_est_i_2__n.BLIF N_128 -11 1 -.names N_168_1.BLIF N_168_2.BLIF N_168_5 -11 1 -.names N_121_i.BLIF N_121 -0 1 -.names N_168_3.BLIF N_168_4.BLIF N_168_6 -11 1 -.names cpu_est_1_.BLIF cpu_est_2_.BLIF state_machine_un13_clk_000_d0_2_n -11 1 -.names a_c_20__n.BLIF a_c_21__n.BLIF N_171_1 -11 1 -.names N_131_1.BLIF cpu_est_i_2__n.BLIF N_131 -11 1 -.names a_c_22__n.BLIF a_c_23__n.BLIF N_171_2 -11 1 -.names clk_cpu_est_11_0_1__n.BLIF clk_cpu_est_11_1__n -0 1 -.names AS_030_000_SYNC_i.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_1 -11 1 -.names cpu_est_3_reg.BLIF state_machine_un13_clk_000_d0_2_n.BLIF N_126 -11 1 -.names RW_c.BLIF SM_AMIGA_6_.BLIF UDS_000_INT_0_sqmuxa_1_2 -11 1 -.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_124 -11 1 -.names UDS_000_INT_0_sqmuxa_1_1.BLIF UDS_000_INT_0_sqmuxa_1_2.BLIF \ -UDS_000_INT_0_sqmuxa_1_3 -11 1 -.names N_121.BLIF cpu_est_i_0__n.BLIF N_123 -11 1 -.names SM_AMIGA_4_.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_0 -11 1 -.names N_121_i.BLIF cpu_est_0_.BLIF N_125 -11 1 -.names CLK_000_D0_i.BLIF inst_CLK_OUT_PRE.BLIF N_96_1 -11 1 -.names N_91_0.BLIF N_91 -0 1 -.names a_c_17__n.BLIF a_i_16__n.BLIF state_machine_un42_clk_030_1_n -11 1 -.names CLK_000_D0_i.BLIF N_91.BLIF N_102 -11 1 -.names a_i_18__n.BLIF a_i_19__n.BLIF state_machine_un42_clk_030_2_n -11 1 -.names sm_amiga_i_3__n.BLIF sm_amiga_i_4__n.BLIF N_103 -11 1 -.names fc_c_1__n.BLIF BGACK_000_c.BLIF state_machine_un42_clk_030_3_n -11 1 -.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_101 -11 1 -.names state_machine_un42_clk_030_1_n.BLIF state_machine_un42_clk_030_2_n.BLIF \ -state_machine_un42_clk_030_4_n +.names CLK_030_c.BLIF N_57.BLIF N_79_1 11 1 .names RW_c.BLIF RW_i 0 1 -.names state_machine_un42_clk_030_3_n.BLIF fc_c_0__n.BLIF \ -state_machine_un42_clk_030_5_n -11 1 -.names inst_AS_000_INTreg.BLIF AS_000_INT_i -0 1 -.names AMIGA_BUS_ENABLE_i.BLIF AS_030_i.BLIF AMIGA_BUS_ENABLE_i_m_1 -11 1 -.names dsack_c_1__n.BLIF dsack_i_1__n -0 1 -.names SM_AMIGA_3_.BLIF VMA_INT_i.BLIF VPA_SYNC_1_sqmuxa_1_0 -11 1 -.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n -0 1 -.names VPA_D_i.BLIF cpu_est_2_.BLIF VPA_SYNC_1_sqmuxa_2 -11 1 -.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n -0 1 -.names cpu_est_3_reg.BLIF cpu_est_i_0__n.BLIF VPA_SYNC_1_sqmuxa_3 -11 1 -.names inst_CLK_000_D0.BLIF CLK_000_D0_i -0 1 -.names cpu_est_i_1__n.BLIF state_machine_un2_clk_000_n.BLIF \ -VPA_SYNC_1_sqmuxa_4 -11 1 -.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n -0 1 -.names VPA_SYNC_1_sqmuxa_1_0.BLIF VPA_SYNC_1_sqmuxa_2.BLIF VPA_SYNC_1_sqmuxa_5 -11 1 -.names cpu_est_0_.BLIF cpu_est_i_0__n -0 1 -.names VPA_SYNC_1_sqmuxa_3.BLIF VPA_SYNC_1_sqmuxa_4.BLIF VPA_SYNC_1_sqmuxa_6 -11 1 -.names cpu_est_3_reg.BLIF cpu_est_i_3__n -0 1 -.names cpu_est_0_.BLIF cpu_est_i_3__n.BLIF N_127_1 -11 1 -.names cpu_est_2_.BLIF cpu_est_i_2__n -0 1 -.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_128_1 +.names SM_AMIGA_7_.BLIF nEXP_SPACE_c.BLIF N_79_2 11 1 .names inst_VPA_D.BLIF VPA_D_i 0 1 -.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_131_1 +.names DTACK_i.BLIF N_77_1.BLIF N_77_1_0 11 1 -.names cpu_est_1_.BLIF cpu_est_i_1__n +.names inst_CLK_000_D0.BLIF CLK_000_D0_i 0 1 -.names N_131_i.BLIF N_129_i.BLIF clk_cpu_est_11_0_1_3__n +.names N_77_1.BLIF VMA_INT_i.BLIF N_75_1 11 1 -.names DTACK_c.BLIF DTACK_i +.names cpu_est_0_.BLIF cpu_est_i_0__n 0 1 -.names CLK_000_D0_i.BLIF SM_AMIGA_3_.BLIF N_105_1 +.names VPA_D_i.BLIF cpu_est_2_.BLIF N_75_2 +11 1 +.names cpu_est_3_reg.BLIF cpu_est_i_3__n +0 1 +.names cpu_est_3_reg.BLIF cpu_est_i_0__n.BLIF N_75_3 11 1 .names inst_VMA_INTreg.BLIF VMA_INT_i 0 1 -.names DTACK_i.BLIF SM_AMIGA_3_.BLIF DTACK_SYNC_1_sqmuxa_1_0 +.names N_75_1.BLIF N_75_2.BLIF N_75_4 11 1 -.names state_machine_un13_clk_000_d0_2_n.BLIF \ -state_machine_un13_clk_000_d0_2_i_n +.names cpu_est_1_.BLIF cpu_est_i_1__n 0 1 -.names inst_VPA_D.BLIF state_machine_un2_clk_000_n.BLIF DTACK_SYNC_1_sqmuxa_2 +.names N_75_3.BLIF cpu_est_i_1__n.BLIF N_75_5 11 1 -.names inst_CLK_000_D1.BLIF CLK_000_D1_i +.names DTACK_c.BLIF DTACK_i 0 1 -.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF \ -state_machine_un8_clk_000_d0_1_n +.names N_55_i.BLIF N_59_i.BLIF N_73_1 11 1 -.names VPA_SYNC_1_sqmuxa.BLIF VPA_SYNC_1_sqmuxa_i +.names BG_030_c.BLIF BG_030_i 0 1 -.names CLK_000_D0_i.BLIF VPA_D_i.BLIF state_machine_un8_clk_000_d0_2_n -11 1 -.names AS_030_c.BLIF AS_030_i -0 1 -.names cpu_est_0_.BLIF cpu_est_2_.BLIF state_machine_un8_clk_000_d0_3_n -11 1 -.names N_95.BLIF N_95_i -0 1 -.names state_machine_un8_clk_000_d0_1_n.BLIF \ -state_machine_un8_clk_000_d0_2_n.BLIF state_machine_un8_clk_000_d0_4_n -11 1 -.names DTACK_SYNC_1_sqmuxa.BLIF DTACK_SYNC_1_sqmuxa_i -0 1 -.names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF \ -state_machine_un13_clk_000_d0_1_0_n -11 1 -.names N_96.BLIF N_96_i -0 1 -.names state_machine_un13_clk_000_d0_1_n.BLIF \ -state_machine_un13_clk_000_d0_2_n.BLIF state_machine_un13_clk_000_d0_2_0_n -11 1 -.names a_c_18__n.BLIF a_i_18__n -0 1 -.names clk_un4_clk_000_d1_n.BLIF cpu_est_0_1__un3_n -0 1 -.names a_c_16__n.BLIF a_i_16__n -0 1 -.names clk_cpu_est_11_1__n.BLIF clk_un4_clk_000_d1_n.BLIF cpu_est_0_1__un1_n -11 1 -.names a_c_19__n.BLIF a_i_19__n -0 1 -.names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n -11 1 -.names CLK_030_c.BLIF CLK_030_i -0 1 -.names clk_un4_clk_000_d1_n.BLIF cpu_est_0_3__un3_n -0 1 -.names state_machine_un42_clk_030_n.BLIF state_machine_un42_clk_030_i_n -0 1 -.names clk_cpu_est_11_3__n.BLIF clk_un4_clk_000_d1_n.BLIF cpu_est_0_3__un1_n -11 1 -.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n -0 1 -.names cpu_est_3_reg.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n -11 1 -.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n -0 1 -.names clk_un4_clk_000_d1_n.BLIF ipl_030_0_0__un3_n -0 1 -.names AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLE_i -0 1 -.names ipl_c_0__n.BLIF clk_un4_clk_000_d1_n.BLIF ipl_030_0_0__un1_n +.names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF N_73_2 11 1 .names nEXP_SPACE_c.BLIF nEXP_SPACE_i 0 1 -.names IPL_030DFFSH_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n +.names CLK_000_D0_i.BLIF N_146.BLIF N_72_1 11 1 -.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n +.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n 0 1 -.names clk_un4_clk_000_d1_n.BLIF ipl_030_0_1__un3_n -0 1 -.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n -0 1 -.names ipl_c_1__n.BLIF clk_un4_clk_000_d1_n.BLIF ipl_030_0_1__un1_n +.names VPA_D_i.BLIF cpu_est_2_.BLIF N_72_2 11 1 -.names DS_030_c.BLIF DS_030_i +.names inst_AS_000_INTreg.BLIF AS_000_INT_i 0 1 -.names IPL_030DFFSH_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n +.names N_140_i.BLIF N_85_i.BLIF sm_amiga_ns_0_1_0__n 11 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n 0 1 -.names clk_un4_clk_000_d1_n.BLIF ipl_030_0_2__un3_n -0 1 -.names UDS_000_INT_0_sqmuxa_1.BLIF UDS_000_INT_0_sqmuxa_1_i -0 1 -.names ipl_c_2__n.BLIF clk_un4_clk_000_d1_n.BLIF ipl_030_0_2__un1_n +.names N_178_i.BLIF N_125_i.BLIF clk_cpu_est_11_0_1_3__n 11 1 -.names UDS_000_INT_0_sqmuxa.BLIF UDS_000_INT_0_sqmuxa_i +.names cpu_est_2_.BLIF cpu_est_i_2__n 0 1 -.names IPL_030DFFSH_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n +.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_138_1 11 1 -.names state_machine_un13_clk_000_d0_1_n.BLIF \ -state_machine_un13_clk_000_d0_1_i_n +.names AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLE_i 0 1 -.names un1_as_030_4.BLIF uds_000_int_0_un3_n +.names AMIGA_BUS_ENABLE_i.BLIF AS_030_i.BLIF N_119_1 +11 1 +.names AS_030_c.BLIF AS_030_i +0 1 +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_118_1 +11 1 +.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n +0 1 +.names N_55.BLIF cpu_est_0_.BLIF N_117_1 +11 1 +.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +0 1 +.names CLK_000_D0_i.BLIF SM_AMIGA_3_.BLIF N_97_1 +11 1 +.names state_machine_un8_clk_000_d2_n.BLIF state_machine_un8_clk_000_d2_i_n +0 1 +.names a_i_0__n.BLIF size_c_0__n.BLIF N_81_1 +11 1 +.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n +0 1 +.names RW_c.BLIF state_machine_uds_000_int_5_0_m2_un3_n +0 1 +.names a_c_0__n.BLIF a_i_0__n +0 1 +.names SM_AMIGA_5_.BLIF RW_c.BLIF state_machine_uds_000_int_5_0_m2_un1_n +11 1 +.names size_c_1__n.BLIF size_i_1__n +0 1 +.names SM_AMIGA_4_.BLIF state_machine_uds_000_int_5_0_m2_un3_n.BLIF \ +state_machine_uds_000_int_5_0_m2_un0_n +11 1 +.names dsack_c_1__n.BLIF dsack_i_1__n +0 1 +.names N_163.BLIF vpa_sync_0_un3_n 0 1 .names clk_clk_cnt_n.BLIF clk_clk_cnt_i_n 0 1 -.names inst_UDS_000_INTreg.BLIF un1_as_030_4.BLIF uds_000_int_0_un1_n +.names N_75_i.BLIF N_163.BLIF vpa_sync_0_un1_n 11 1 .names CLK_CNT_0_.BLIF clk_cnt_i_0__n 0 1 -.names state_machine_uds_000_int_7_n.BLIF uds_000_int_0_un3_n.BLIF \ -uds_000_int_0_un0_n +.names inst_VPA_SYNC.BLIF vpa_sync_0_un3_n.BLIF vpa_sync_0_un0_n 11 1 .names inst_CLK_000_D2.BLIF CLK_000_D2_i 0 1 -.names VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un3_n +.names RST_c.BLIF amiga_bus_enable_0_un3_n 0 1 +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +0 1 +.names N_43_i.BLIF RST_c.BLIF amiga_bus_enable_0_un1_n +11 1 .names a_c_30__n.BLIF a_i_30__n 0 1 -.names inst_VPA_SYNC.BLIF VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un1_n +.names AMIGA_BUS_ENABLEDFFreg.BLIF amiga_bus_enable_0_un3_n.BLIF \ +amiga_bus_enable_0_un0_n 11 1 .names a_c_31__n.BLIF a_i_31__n 0 1 -.names VPA_SYNC_1_sqmuxa_i.BLIF vpa_sync_0_un3_n.BLIF vpa_sync_0_un0_n -11 1 +.names N_162.BLIF uds_000_int_0_un3_n +0 1 .names a_c_28__n.BLIF a_i_28__n 0 1 -.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n -0 1 +.names state_machine_uds_000_int_5_n.BLIF N_162.BLIF uds_000_int_0_un1_n +11 1 .names a_c_29__n.BLIF a_i_29__n 0 1 -.names inst_AS_000_INTreg.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n +.names inst_UDS_000_INTreg.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n 11 1 .names a_c_26__n.BLIF a_i_26__n 0 1 -.names N_95_i.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n -11 1 +.names N_162.BLIF lds_000_int_0_un3_n +0 1 .names a_c_27__n.BLIF a_i_27__n 0 1 +.names state_machine_lds_000_int_5_n.BLIF N_162.BLIF lds_000_int_0_un1_n +11 1 +.names a_c_24__n.BLIF a_i_24__n +0 1 +.names inst_LDS_000_INTreg.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n +11 1 +.names a_c_25__n.BLIF a_i_25__n +0 1 +.names state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un3_n +0 1 +.names a_c_19__n.BLIF a_i_19__n +0 1 +.names cpu_est_1_.BLIF state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un1_n +11 1 +.names a_c_16__n.BLIF a_i_16__n +0 1 +.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n +11 1 +.names a_c_18__n.BLIF a_i_18__n +0 1 +.names N_69.BLIF bg_000_0_un3_n +0 1 +.names G_92.BLIF N_137_i +0 1 +.names BG_000DFFSHreg.BLIF N_69.BLIF bg_000_0_un1_n +11 1 +.names N_120_i.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n +11 1 +.names RST_c.BLIF RST_i +0 1 .names state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n 0 1 -.names a_c_24__n.BLIF a_i_24__n +.names N_120.BLIF N_120_i 0 1 .names BGACK_000_c.BLIF state_machine_un6_bgack_000_n.BLIF \ bgack_030_int_0_un1_n 11 1 -.names a_c_25__n.BLIF a_i_25__n +.names N_75.BLIF N_75_i 0 1 .names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \ bgack_030_int_0_un0_n 11 1 -.names G_86.BLIF N_132_i +.names N_74.BLIF N_74_i 0 1 -.names state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un3_n +.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n 0 1 -.names G_87.BLIF N_133_i +.names N_77.BLIF N_77_i 0 1 -.names N_121.BLIF state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un1_n +.names inst_AS_000_INTreg.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n 11 1 -.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n -11 1 -.names RST_c.BLIF RST_i -0 1 -.names clk_un4_clk_000_d1_n.BLIF cpu_est_0_2__un3_n -0 1 .names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i 0 1 -.names N_118_i.BLIF clk_un4_clk_000_d1_n.BLIF cpu_est_0_2__un1_n +.names sm_amiga_i_5__n.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n 11 1 .names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i 0 1 -.names cpu_est_2_.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n -11 1 -.names DSACK_INT_1_sqmuxa.BLIF dsack_int_0_1__un3_n +.names N_56.BLIF cpu_est_0_1__un3_n 0 1 -.names DSACK_INT_1_.BLIF DSACK_INT_1_sqmuxa.BLIF dsack_int_0_1__un1_n -11 1 -.names N_96_i.BLIF dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un0_n -11 1 -.names state_machine_un1_clk_030_n.BLIF bg_000_0_un3_n +.names inst_CLK_000_D5.BLIF CLK_000_D5_i 0 1 -.names un1_bg_030.BLIF state_machine_un1_clk_030_n.BLIF bg_000_0_un1_n +.names cpu_est_1_.BLIF N_56.BLIF cpu_est_0_1__un1_n 11 1 -.names BG_000DFFSHreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n +.names clk_cpu_est_11_1__n.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n 11 1 -.names RST_c.BLIF amiga_bus_enable_0_un3_n +.names N_56.BLIF cpu_est_0_2__un3_n 0 1 -.names state_machine_amiga_bus_enable_2_iv_i_n.BLIF RST_c.BLIF \ -amiga_bus_enable_0_un1_n +.names cpu_est_2_.BLIF N_56.BLIF cpu_est_0_2__un1_n 11 1 -.names AMIGA_BUS_ENABLEDFFreg.BLIF amiga_bus_enable_0_un3_n.BLIF \ -amiga_bus_enable_0_un0_n +.names N_123_i.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n 11 1 -.names state_machine_un17_clk_030_n.BLIF as_030_000_sync_0_un3_n +.names N_56.BLIF cpu_est_0_3__un3_n 0 1 -.names state_machine_as_030_000_sync_3_n.BLIF \ -state_machine_un17_clk_030_n.BLIF as_030_000_sync_0_un1_n +.names cpu_est_3_reg.BLIF N_56.BLIF cpu_est_0_3__un1_n +11 1 +.names clk_cpu_est_11_3__n.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n +11 1 +.names N_56.BLIF ipl_030_0_0__un3_n +0 1 +.names IPL_030DFFSH_0_reg.BLIF N_56.BLIF ipl_030_0_0__un1_n +11 1 +.names ipl_c_0__n.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n +11 1 +.names N_56.BLIF ipl_030_0_1__un3_n +0 1 +.names IPL_030DFFSH_1_reg.BLIF N_56.BLIF ipl_030_0_1__un1_n +11 1 +.names ipl_c_1__n.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n +11 1 +.names N_56.BLIF ipl_030_0_2__un3_n +0 1 +.names IPL_030DFFSH_2_reg.BLIF N_56.BLIF ipl_030_0_2__un1_n +11 1 +.names ipl_c_2__n.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n +11 1 +.names N_30.BLIF as_030_000_sync_0_un3_n +0 1 +.names un1_AMIGA_BUS_ENABLE_1_sqmuxa_2.BLIF N_30.BLIF as_030_000_sync_0_un1_n 11 1 .names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF \ as_030_000_sync_0_un0_n 11 1 -.names state_machine_un17_clk_030_n.BLIF fpu_cs_int_0_un3_n +.names N_165.BLIF dtack_sync_0_un3_n 0 1 -.names un1_as_030_3.BLIF state_machine_un17_clk_030_n.BLIF fpu_cs_int_0_un1_n +.names N_77_i.BLIF N_165.BLIF dtack_sync_0_un1_n +11 1 +.names inst_DTACK_SYNC.BLIF dtack_sync_0_un3_n.BLIF dtack_sync_0_un0_n +11 1 +.names N_164.BLIF fpu_cs_int_0_un3_n +0 1 +.names AS_030_c.BLIF N_164.BLIF fpu_cs_int_0_un1_n 11 1 .names inst_FPU_CS_INTreg.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un0_n 11 1 -.names DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un3_n +.names N_52.BLIF dsack_int_0_1__un3_n 0 1 -.names inst_DTACK_SYNC.BLIF DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un1_n +.names N_74_i.BLIF N_52.BLIF dsack_int_0_1__un1_n 11 1 -.names DTACK_SYNC_1_sqmuxa_i.BLIF dtack_sync_0_un3_n.BLIF dtack_sync_0_un0_n -11 1 -.names un1_as_030_4.BLIF lds_000_int_0_un3_n -0 1 -.names inst_LDS_000_INTreg.BLIF un1_as_030_4.BLIF lds_000_int_0_un1_n -11 1 -.names state_machine_lds_000_int_7_n.BLIF lds_000_int_0_un3_n.BLIF \ -lds_000_int_0_un0_n +.names DSACK_INT_1_.BLIF dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un0_n 11 1 .names IPL_030DFFSH_2_reg.BLIF IPL_030_2_ 1 1 @@ -1037,7 +974,7 @@ lds_000_int_0_un0_n .names vcc_n_n.BLIF AMIGA_BUS_ENABLE_LOW 1 1 0 0 -.names N_171.BLIF CIIN +.names N_191.BLIF CIIN 1 1 0 0 .names IPL_030DFFSH_1_reg.BLIF IPL_030_1_ @@ -1046,6 +983,30 @@ lds_000_int_0_un0_n .names IPL_030DFFSH_0_reg.BLIF IPL_030_0_ 1 1 0 0 +.names CLK_OSZI_c.BLIF IPL_030DFFSH_0_reg.C +1 1 +0 0 +.names RST_i.BLIF IPL_030DFFSH_0_reg.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF IPL_030DFFSH_1_reg.C +1 1 +0 0 +.names RST_i.BLIF IPL_030DFFSH_1_reg.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF IPL_030DFFSH_2_reg.C +1 1 +0 0 +.names RST_i.BLIF IPL_030DFFSH_2_reg.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_7_.C +1 1 +0 0 +.names RST_i.BLIF SM_AMIGA_7_.AP +1 1 +0 0 .names CLK_OSZI_c.BLIF SM_AMIGA_6_.C 1 1 0 0 @@ -1088,6 +1049,15 @@ lds_000_int_0_un0_n .names RST_i.BLIF SM_AMIGA_0_.AR 1 1 0 0 +.names CLK_OSZI_c.BLIF CLK_CNT_0_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_CNT_1_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF cpu_est_0_.C +1 1 +0 0 .names CLK_OSZI_c.BLIF cpu_est_1_.C 1 1 0 0 @@ -1097,99 +1067,6 @@ lds_000_int_0_un0_n .names CLK_OSZI_c.BLIF cpu_est_3_reg.C 1 1 0 0 -.names CLK_OSZI_c.BLIF IPL_030DFFSH_0_reg.C -1 1 -0 0 -.names RST_i.BLIF IPL_030DFFSH_0_reg.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF IPL_030DFFSH_1_reg.C -1 1 -0 0 -.names RST_i.BLIF IPL_030DFFSH_1_reg.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF IPL_030DFFSH_2_reg.C -1 1 -0 0 -.names RST_i.BLIF IPL_030DFFSH_2_reg.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_7_.C -1 1 -0 0 -.names RST_i.BLIF SM_AMIGA_7_.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C -1 1 -0 0 -.names RST_i.BLIF inst_VMA_INTreg.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C -1 1 -0 0 -.names RST_i.BLIF inst_BGACK_030_INTreg.AP -1 1 -0 0 -.names CLK_OUT_PRE_0.BLIF inst_CLK_OUT_PRE.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_CNT_0_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_CNT_1_.C -1 1 -0 0 -.names cpu_est_0_0_.BLIF cpu_est_0_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF cpu_est_0_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_VPA_SYNC.C -1 1 -0 0 -.names RST_i.BLIF inst_VPA_SYNC.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_FPU_CS_INTreg.C -1 1 -0 0 -.names RST_i.BLIF inst_FPU_CS_INTreg.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C -1 1 -0 0 -.names RST_i.BLIF inst_AS_030_000_SYNC.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_AS_000_INTreg.C -1 1 -0 0 -.names RST_i.BLIF inst_AS_000_INTreg.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF AMIGA_BUS_ENABLEDFFreg.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C -1 1 -0 0 -.names RST_i.BLIF BG_000DFFSHreg.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF DSACK_INT_1_.C -1 1 -0 0 -.names RST_i.BLIF DSACK_INT_1_.AP -1 1 -0 0 .names CLK_OSZI_c.BLIF inst_UDS_000_INTreg.C 1 1 0 0 @@ -1202,16 +1079,73 @@ lds_000_int_0_un0_n .names RST_i.BLIF inst_LDS_000_INTreg.AP 1 1 0 0 +.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C +1 1 +0 0 +.names RST_i.BLIF inst_VMA_INTreg.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C +1 1 +0 0 +.names RST_i.BLIF BG_000DFFSHreg.AP +1 1 +0 0 +.names CLK_OUT_PRE_0.BLIF inst_CLK_OUT_PRE.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C +1 1 +0 0 +.names RST_i.BLIF inst_BGACK_030_INTreg.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AS_000_INTreg.C +1 1 +0 0 +.names RST_i.BLIF inst_AS_000_INTreg.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C +1 1 +0 0 +.names RST_i.BLIF inst_AS_030_000_SYNC.AP +1 1 +0 0 .names CLK_OSZI_c.BLIF inst_DTACK_SYNC.C 1 1 0 0 .names RST_i.BLIF inst_DTACK_SYNC.AP 1 1 0 0 -.names inst_CLK_OUT_PRE.BLIF CLK_OUT_INTreg.D +.names CLK_OSZI_c.BLIF inst_FPU_CS_INTreg.C 1 1 0 0 -.names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C +.names RST_i.BLIF inst_FPU_CS_INTreg.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF DSACK_INT_1_.C +1 1 +0 0 +.names RST_i.BLIF DSACK_INT_1_.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_VPA_SYNC.C +1 1 +0 0 +.names RST_i.BLIF inst_VPA_SYNC.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF AMIGA_BUS_ENABLEDFFreg.C +1 1 +0 0 +.names inst_CLK_000_D4.BLIF inst_CLK_000_D5.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_CLK_000_D5.C 1 1 0 0 .names CLK_OSZI_c.BLIF inst_DTACK_DMA.C @@ -1220,19 +1154,37 @@ lds_000_int_0_un0_n .names RST_i.BLIF inst_DTACK_DMA.AP 1 1 0 0 +.names inst_CLK_OUT_PRE.BLIF CLK_OUT_INTreg.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C +1 1 +0 0 +.names inst_CLK_000_D3.BLIF inst_CLK_000_D4.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_CLK_000_D4.C +1 1 +0 0 .names inst_CLK_000_D1.BLIF inst_CLK_000_D2.D 1 1 0 0 .names CLK_OSZI_c.BLIF inst_CLK_000_D2.C 1 1 0 0 +.names inst_CLK_000_D2.BLIF inst_CLK_000_D3.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_CLK_000_D3.C +1 1 +0 0 .names VPA.BLIF inst_VPA_D.D 1 1 0 0 .names CLK_OSZI_c.BLIF inst_VPA_D.C 1 1 0 0 -.names CLK_000_c.BLIF inst_CLK_000_D0.D +.names CLK_000.BLIF inst_CLK_000_D0.D 1 1 0 0 .names CLK_OSZI_c.BLIF inst_CLK_000_D0.C @@ -1250,15 +1202,6 @@ lds_000_int_0_un0_n .names CLK_OSZI_c.BLIF inst_CLK_000_D1.C 1 1 0 0 -.names gnd_n_n.BLIF CLK_REF_0_.D -1 1 -0 0 -.names gnd_n_n.BLIF CLK_REF_0_.LH -1 1 -0 0 -.names RST_i.BLIF CLK_REF_0_.AP -1 1 -0 0 .names gnd_n_n.BLIF CLK_REF_1_.D 1 1 0 0 @@ -1283,9 +1226,6 @@ lds_000_int_0_un0_n .names CLK_030.BLIF CLK_030_c 1 1 0 0 -.names CLK_000.BLIF CLK_000_c -1 1 -0 0 .names CLK_OSZI.BLIF CLK_OSZI_c 1 1 0 0 @@ -1331,96 +1271,96 @@ lds_000_int_0_un0_n .names A_0_.BLIF a_c_0__n 1 1 0 0 -.names A_15_.BLIF a_15__n -1 1 -0 0 -.names A_14_.BLIF a_14__n -1 1 -0 0 -.names A_13_.BLIF a_13__n -1 1 -0 0 -.names A_12_.BLIF a_12__n -1 1 -0 0 .names A_16_.BLIF a_c_16__n 1 1 0 0 -.names A_11_.BLIF a_11__n +.names A_15_.BLIF a_15__n 1 1 0 0 .names A_17_.BLIF a_c_17__n 1 1 0 0 -.names A_10_.BLIF a_10__n +.names A_14_.BLIF a_14__n 1 1 0 0 .names A_18_.BLIF a_c_18__n 1 1 0 0 -.names A_9_.BLIF a_9__n +.names A_13_.BLIF a_13__n 1 1 0 0 .names A_19_.BLIF a_c_19__n 1 1 0 0 -.names A_8_.BLIF a_8__n +.names A_12_.BLIF a_12__n 1 1 0 0 .names A_20_.BLIF a_c_20__n 1 1 0 0 -.names A_7_.BLIF a_7__n +.names A_11_.BLIF a_11__n 1 1 0 0 .names A_21_.BLIF a_c_21__n 1 1 0 0 -.names A_6_.BLIF a_6__n +.names A_10_.BLIF a_10__n 1 1 0 0 .names A_22_.BLIF a_c_22__n 1 1 0 0 -.names A_5_.BLIF a_5__n +.names A_9_.BLIF a_9__n 1 1 0 0 .names A_23_.BLIF a_c_23__n 1 1 0 0 -.names A_4_.BLIF a_4__n +.names A_8_.BLIF a_8__n 1 1 0 0 .names A_24_.BLIF a_c_24__n 1 1 0 0 -.names A_3_.BLIF a_3__n +.names A_7_.BLIF a_7__n 1 1 0 0 .names A_25_.BLIF a_c_25__n 1 1 0 0 -.names A_2_.BLIF a_2__n +.names A_6_.BLIF a_6__n 1 1 0 0 .names A_26_.BLIF a_c_26__n 1 1 0 0 -.names A_1_.BLIF a_1__n +.names A_5_.BLIF a_5__n 1 1 0 0 .names A_27_.BLIF a_c_27__n 1 1 0 0 +.names A_4_.BLIF a_4__n +1 1 +0 0 .names A_28_.BLIF a_c_28__n 1 1 0 0 +.names A_3_.BLIF a_3__n +1 1 +0 0 .names A_29_.BLIF a_c_29__n 1 1 0 0 +.names A_2_.BLIF a_2__n +1 1 +0 0 .names A_30_.BLIF a_c_30__n 1 1 0 0 +.names A_1_.BLIF a_1__n +1 1 +0 0 .names A_31_.BLIF a_c_31__n 1 1 0 0 @@ -1454,7 +1394,7 @@ lds_000_int_0_un0_n .names FPU_CS_INT_i.BLIF AVEC_EXP.OE 1 1 0 0 -.names N_168.BLIF CIIN.OE +.names N_188.BLIF CIIN.OE 1 1 0 0 .names inst_CLK_OUT_PRE.BLIF clk_clk_cnt_n.BLIF CLK_OUT_PRE_0 @@ -1462,22 +1402,12 @@ lds_000_int_0_un0_n 10 1 11 0 00 0 -.names cpu_est_0_.BLIF clk_un4_clk_000_d1_n.BLIF cpu_est_0_0_ +.names CLK_REF_1_.BLIF CLK_CNT_1_.BLIF G_92 01 1 10 1 11 0 00 0 -.names CLK_REF_0_.BLIF CLK_CNT_0_.BLIF G_86 -01 1 -10 1 -11 0 -00 0 -.names CLK_REF_1_.BLIF CLK_CNT_1_.BLIF G_87 -01 1 -10 1 -11 0 -00 0 -.names CLK_CNT_0_.BLIF CLK_CNT_1_.BLIF G_91 +.names CLK_CNT_0_.BLIF CLK_CNT_1_.BLIF G_96 01 1 10 1 11 0 diff --git a/Logic/BUS68030.edi b/Logic/BUS68030.edi index cd73471..6f58570 100644 --- a/Logic/BUS68030.edi +++ b/Logic/BUS68030.edi @@ -4,7 +4,7 @@ (keywordMap (keywordLevel 0)) (status (written - (timeStamp 2014 5 22 14 56 5) + (timeStamp 2014 5 24 11 44 4) (author "Synopsys, Inc.") (program "Synplify Pro" (version "G-2012.09LC-SP1 , mapper maplat, Build 621R")) ) @@ -79,16 +79,6 @@ ) ) ) - (cell DLATSH (cellType GENERIC) - (view prim (viewType NETLIST) - (interface - (port Q (direction OUTPUT)) - (port D (direction INPUT)) - (port LAT (direction INPUT)) - (port S (direction INPUT)) - ) - ) - ) (cell IBUF (cellType GENERIC) (view prim (viewType NETLIST) (interface @@ -176,6 +166,14 @@ (port CIIN (direction OUTPUT)) ) (contents + (instance (rename IPL_030DFFSH_0 "IPL_030DFFSH[0]") (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance (rename IPL_030DFFSH_1 "IPL_030DFFSH[1]") (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance (rename IPL_030DFFSH_2 "IPL_030DFFSH[2]") (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance (rename SM_AMIGA_7 "SM_AMIGA[7]") (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) (instance (rename SM_AMIGA_6 "SM_AMIGA[6]") (viewRef prim (cellRef DFFRH (libraryRef mach))) ) (instance (rename SM_AMIGA_5 "SM_AMIGA[5]") (viewRef prim (cellRef DFFRH (libraryRef mach))) @@ -190,58 +188,56 @@ ) (instance (rename SM_AMIGA_0 "SM_AMIGA[0]") (viewRef prim (cellRef DFFRH (libraryRef mach))) ) - (instance (rename cpu_est_1 "cpu_est[1]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename cpu_est_2 "cpu_est[2]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename cpu_est_3 "cpu_est[3]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename IPL_030DFFSH_0 "IPL_030DFFSH[0]") (viewRef prim (cellRef DFFSH (libraryRef mach))) - ) - (instance (rename IPL_030DFFSH_1 "IPL_030DFFSH[1]") (viewRef prim (cellRef DFFSH (libraryRef mach))) - ) - (instance (rename IPL_030DFFSH_2 "IPL_030DFFSH[2]") (viewRef prim (cellRef DFFSH (libraryRef mach))) - ) - (instance (rename SM_AMIGA_7 "SM_AMIGA[7]") (viewRef prim (cellRef DFFSH (libraryRef mach))) - ) - (instance VMA_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) - ) - (instance BGACK_030_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) - ) - (instance CLK_OUT_PRE (viewRef prim (cellRef DFF (libraryRef mach))) - ) (instance (rename CLK_CNT_0 "CLK_CNT[0]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance (rename CLK_CNT_1 "CLK_CNT[1]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance (rename cpu_est_0 "cpu_est[0]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance VPA_SYNC (viewRef prim (cellRef DFFSH (libraryRef mach))) + (instance (rename cpu_est_1 "cpu_est[1]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance FPU_CS_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) + (instance (rename cpu_est_2 "cpu_est[2]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance AS_030_000_SYNC (viewRef prim (cellRef DFFSH (libraryRef mach))) - ) - (instance AS_000_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) - ) - (instance AMIGA_BUS_ENABLEDFF (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance BG_000DFFSH (viewRef prim (cellRef DFFSH (libraryRef mach))) - ) - (instance (rename DSACK_INT_1 "DSACK_INT[1]") (viewRef prim (cellRef DFFSH (libraryRef mach))) + (instance (rename cpu_est_3 "cpu_est[3]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance UDS_000_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) ) (instance LDS_000_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) ) + (instance VMA_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance BG_000DFFSH (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance CLK_OUT_PRE (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance BGACK_030_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance AS_000_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance AS_030_000_SYNC (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) (instance DTACK_SYNC (viewRef prim (cellRef DFFSH (libraryRef mach))) ) - (instance CLK_OUT_INT (viewRef prim (cellRef DFF (libraryRef mach))) + (instance FPU_CS_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance (rename DSACK_INT_1 "DSACK_INT[1]") (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance VPA_SYNC (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance AMIGA_BUS_ENABLEDFF (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance CLK_000_D5 (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance DTACK_DMA (viewRef prim (cellRef DFFSH (libraryRef mach))) ) + (instance CLK_OUT_INT (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance CLK_000_D4 (viewRef prim (cellRef DFF (libraryRef mach))) + ) (instance CLK_000_D2 (viewRef prim (cellRef DFF (libraryRef mach))) ) + (instance CLK_000_D3 (viewRef prim (cellRef DFF (libraryRef mach))) + ) (instance VPA_D (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance CLK_000_D0 (viewRef prim (cellRef DFF (libraryRef mach))) @@ -309,49 +305,52 @@ (instance AMIGA_BUS_DATA_DIR (viewRef prim (cellRef OBUF (libraryRef mach))) ) (instance AMIGA_BUS_ENABLE_LOW (viewRef prim (cellRef OBUF (libraryRef mach))) ) (instance CIIN (viewRef prim (cellRef BUFTH (libraryRef mach))) ) - (instance DTACK_SYNC_1_sqmuxa_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DTACK_SYNC_1_sqmuxa_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DTACK_SYNC_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un8_clk_000_d0_1 "state_machine.un8_clk_000_d0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un8_clk_000_d0_2 "state_machine.un8_clk_000_d0_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un8_clk_000_d0_3 "state_machine.un8_clk_000_d0_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un8_clk_000_d0_4 "state_machine.un8_clk_000_d0_4") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un8_clk_000_d0 "state_machine.un8_clk_000_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un13_clk_000_d0_1_0 "state_machine.un13_clk_000_d0_1_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un13_clk_000_d0_2_0 "state_machine.un13_clk_000_d0_2_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un13_clk_000_d0 "state_machine.un13_clk_000_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_SYNC_1_sqmuxa_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_SYNC_1_sqmuxa_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_SYNC_1_sqmuxa_5 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_SYNC_1_sqmuxa_6 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_SYNC_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_i_a4_1_2 "clk.cpu_est_11_i_a4_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_i_a4_2 "clk.cpu_est_11_i_a4[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_i_a4_0_1_2 "clk.cpu_est_11_i_a4_0_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_i_a4_0_2 "clk.cpu_est_11_i_a4_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_a4_1_1_3 "clk.cpu_est_11_0_a4_1_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_a4_1_3 "clk.cpu_est_11_0_a4_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_1_3 "clk.cpu_est_11_0_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_3 "clk.cpu_est_11_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_a3_0_1_5 "SM_AMIGA_ns_a3_0_1[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_a3_0_5 "SM_AMIGA_ns_a3_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance UDS_000_INT_0_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance UDS_000_INT_0_sqmuxa_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance UDS_000_INT_0_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_DSACK_INT_0_sqmuxa_i_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_DSACK_INT_0_sqmuxa_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un42_clk_030_1 "state_machine.un42_clk_030_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un42_clk_030_2 "state_machine.un42_clk_030_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un42_clk_030_3 "state_machine.un42_clk_030_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un42_clk_030_4 "state_machine.un42_clk_030_4") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un42_clk_030_5 "state_machine.un42_clk_030_5") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un42_clk_030 "state_machine.un42_clk_030") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_i_m_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_i_m (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_SYNC_1_sqmuxa_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_SYNC_1_sqmuxa_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_2_1 "clk.cpu_est_11_0_2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_1 "clk.cpu_est_11_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_0_1_3 "clk.cpu_est_11_0_0_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_0_3 "clk.cpu_est_11_0_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_0_a3_1_1_3 "clk.cpu_est_11_0_0_a3_1_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_0_a3_1_3 "clk.cpu_est_11_0_0_a3_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_AMIGA_BUS_ENABLE_3_f0_i_a3_1 "state_machine.AMIGA_BUS_ENABLE_3_f0_i_a3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_AMIGA_BUS_ENABLE_3_f0_i_a3 "state_machine.AMIGA_BUS_ENABLE_3_f0_i_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_i_0_a3_0_1_2 "clk.cpu_est_11_i_0_a3_0_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_i_0_a3_0_2 "clk.cpu_est_11_i_0_a3_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_i_0_a3_1_2 "clk.cpu_est_11_i_0_a3_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_i_0_a3_2 "clk.cpu_est_11_i_0_a3[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_a3_0_1_5 "SM_AMIGA_ns_0_a3_0_1[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_a3_0_5 "SM_AMIGA_ns_0_a3_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_LDS_000_INT_5_0_a3_1 "state_machine.LDS_000_INT_5_0_a3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_LDS_000_INT_5_0_a3 "state_machine.LDS_000_INT_5_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DTACK_SYNC_1_sqmuxa_1_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VPA_SYNC_1_sqmuxa_1_i_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VPA_SYNC_1_sqmuxa_1_i_a3_2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VPA_SYNC_1_sqmuxa_1_i_a3_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VPA_SYNC_1_sqmuxa_1_i_a3_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VPA_SYNC_1_sqmuxa_1_i_a3_5 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VPA_SYNC_1_sqmuxa_1_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un15_clk_000_d0_0_a3_0_1 "state_machine.un15_clk_000_d0_0_a3_0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un15_clk_000_d0_0_a3_0_2 "state_machine.un15_clk_000_d0_0_a3_0_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un15_clk_000_d0_0_a3_0 "state_machine.un15_clk_000_d0_0_a3_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un15_clk_000_d0_0_a3_1 "state_machine.un15_clk_000_d0_0_a3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un15_clk_000_d0_0_a3_2 "state_machine.un15_clk_000_d0_0_a3_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un15_clk_000_d0_0_a3 "state_machine.un15_clk_000_d0_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_1_0 "SM_AMIGA_ns_0_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0 "SM_AMIGA_ns_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_000_SYNC_1_sqmuxa_i_o2_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_000_SYNC_1_sqmuxa_i_o2_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_000_SYNC_1_sqmuxa_i_o2_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_000_SYNC_1_sqmuxa_i_o2_5 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_000_SYNC_1_sqmuxa_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_0_1_1 "clk.cpu_est_11_0_0_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_0_2_1 "clk.cpu_est_11_0_0_2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_0_1 "clk.cpu_est_11_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_bg_030_i_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_bg_030_i_a3_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_bg_030_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_000_SYNC_1_sqmuxa_i_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_000_SYNC_1_sqmuxa_i_a3_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_000_SYNC_1_sqmuxa_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DTACK_SYNC_1_sqmuxa_1_i_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un6_bgack_000_0_i "state_machine.un6_bgack_000_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un23_clk_000_d0_i_0 "state_machine.un23_clk_000_d0_i_0") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance un8_ciin_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un8_ciin_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un8_ciin_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) @@ -362,103 +361,223 @@ (instance un4_ciin_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un4_ciin_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un4_ciin (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance UDS_000_INT_0_sqmuxa_1_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance UDS_000_INT_0_sqmuxa_1_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance UDS_000_INT_0_sqmuxa_1_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_o3_i_1 "SM_AMIGA_ns_o3_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_108_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_7 "SM_AMIGA_ns_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un8_clk_000_d2_1 "state_machine.un8_clk_000_d2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un8_clk_000_d2 "state_machine.un8_clk_000_d2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_000_SYNC_1_sqmuxa_i_o2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance N_86_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_83_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_81_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_LDS_000_INT_5_0_i "state_machine.LDS_000_INT_5_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_UDS_000_INT_5_0_i "state_machine.UDS_000_INT_5_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_79_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_030_000_SYNC_1_sqmuxa_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DTACK_SYNC_1_sqmuxa_1_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_76_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_as_030_000_sync8_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance VPA_SYNC_1_sqmuxa_1_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_72_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_73_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un15_clk_000_d0_0_i "state_machine.un15_clk_000_d0_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_as_030_3_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_119_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_117_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_118_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_115_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_116_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_i_7 "SM_AMIGA_ns_0_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_98_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_99_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_1 "SM_AMIGA_ns_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_97_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un44_clk_000_d1_1 "state_machine.un44_clk_000_d1_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un44_clk_000_d1 "state_machine.un44_clk_000_d1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_bg_030_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_bg_030_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_bg_030 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_AS_030_000_SYNC_3_1 "state_machine.AS_030_000_SYNC_3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_AS_030_000_SYNC_3 "state_machine.AS_030_000_SYNC_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_1_1 "clk.cpu_est_11_0_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_i_m_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance nEXP_SPACE_m_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_AS_030_000_SYNC_3_i "state_machine.AS_030_000_SYNC_3_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_114_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_i_i_6 "SM_AMIGA_ns_i_i_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_94_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_bg_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SIZE_c_i_1 "SIZE_c_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un44_clk_000_d1_i_0 "state_machine.un44_clk_000_d1_i_0") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_105_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_104_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_5 "SM_AMIGA_ns_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_106_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_107_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance CLK_OUT_PRE_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_o3_i_6 "SM_AMIGA_ns_i_o3_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_o3_i_0 "SM_AMIGA_ns_i_o3_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un13_clk_000_d0_i "state_machine.un13_clk_000_d0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un15_clk_000_d0_i "state_machine.un15_clk_000_d0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_100_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_2 "SM_AMIGA_ns_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename clk_un4_clk_000_d1_i "clk.un4_clk_000_d1_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un6_bgack_000_i "state_machine.un6_bgack_000_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un23_clk_000_d0_i_0 "state_machine.un23_clk_000_d0_i_0") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance BG_030_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un1_clk_030_i "state_machine.un1_clk_030_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un17_clk_030_i "state_machine.un17_clk_030_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_as_030_3_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_148_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_c_i_0 "A_c_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_UDS_000_INT_7_i "state_machine.UDS_000_INT_7_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_LDS_000_INT_7_i "state_machine.LDS_000_INT_7_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_o3_i_4 "SM_AMIGA_ns_i_o3_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_97_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_i_5 "SM_AMIGA_ns_0_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_89_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_90_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_88_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_000_D1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename clk_un4_clk_000_d1_0_o2_i "clk.un4_clk_000_d1_0_o2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_i_0_o2_i_2 "clk.cpu_est_11_i_0_o2_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DSACK_INT_1_sqmuxa_i_o3_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_141_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_142_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_0_0_i_0 "cpu_est_0_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_85_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_139_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_140_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_i_0 "SM_AMIGA_ns_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_125_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_123_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_138_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_178_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_0_i_3 "clk.cpu_est_11_0_0_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_121_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_122_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_0_o2_i_4 "SM_AMIGA_ns_i_0_o2_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_0_o2_i_1 "SM_AMIGA_ns_i_0_o2_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_145_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0_o3_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DS_030_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_UDS_000_INT_5_0_o3_i "state_machine.UDS_000_INT_5_0_o3_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_0_o2_i_3 "clk.cpu_est_11_0_0_o2_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un6_clk_000_d4_i "state_machine.un6_clk_000_d4_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_i_o2_i_6 "SM_AMIGA_ns_i_i_o2_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_0_o2_i_1 "clk.cpu_est_11_0_0_o2_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_o2_i_7 "SM_AMIGA_ns_0_o2_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_AMIGA_BUS_ENABLE_3_f0_i_o2_i "state_machine.AMIGA_BUS_ENABLE_3_f0_i_o2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_030_000_SYNC_1_sqmuxa_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_0_i_1 "clk.cpu_est_11_0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_124_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_126_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_i_1 "clk.cpu_est_11_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_131_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_i_3 "clk.cpu_est_11_0_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_130_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_129_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_o4_i_3 "clk.cpu_est_11_0_o4_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_o4_i_1 "clk.cpu_est_11_0_o4_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_127_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_128_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un8_clk_000_d0_i "state_machine.un8_clk_000_d0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_101_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_102_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_103_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_3 "SM_AMIGA_ns_i[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance N_146_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_a3_0_4 "SM_AMIGA_ns_i_a3_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_0_o2_4 "SM_AMIGA_ns_i_0_o2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance BG_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance nEXP_SPACE_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_114 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_i_1 "cpu_est_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance VPA_SYNC_1_sqmuxa_1_i_a3_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VMA_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_i_0 "cpu_est_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_i_3 "cpu_est_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance CLK_000_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_a3_4 "SM_AMIGA_ns_i_a3[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_a3_3 "SM_AMIGA_ns_i_a3[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VPA_D_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RW_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_UDS_000_INT_5_0_m2_r "state_machine.UDS_000_INT_5_0_m2.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_UDS_000_INT_5_0_m2_m "state_machine.UDS_000_INT_5_0_m2.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_UDS_000_INT_5_0_m2_n "state_machine.UDS_000_INT_5_0_m2.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_UDS_000_INT_5_0_m2_p "state_machine.UDS_000_INT_5_0_m2.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance DSACK_INT_1_sqmuxa_i_o3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_i_2 "cpu_est_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_i_0_o2_2 "clk.cpu_est_11_i_0_o2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_un4_clk_000_d1_0_o2 "clk.un4_clk_000_d1_0_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_AMIGA_BUS_ENABLE_3_f0_i_o2 "state_machine.AMIGA_BUS_ENABLE_3_f0_i_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance AS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_109 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un14_as_000_int "state_machine.un14_as_000_int") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_o2_7 "SM_AMIGA_ns_0_o2[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_0_o2_1 "clk.cpu_est_11_0_0_o2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_i_o2_6 "SM_AMIGA_ns_i_i_o2[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_0_o2_3 "clk.cpu_est_11_0_0_o2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_UDS_000_INT_5_0_o3 "state_machine.UDS_000_INT_5_0_o3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0_o3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_0_o2_1 "SM_AMIGA_ns_i_0_o2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_as_030_000_sync8_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DTACK_SYNC_1_sqmuxa_1_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_000_SYNC_1_sqmuxa_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_UDS_000_INT_5_0 "state_machine.UDS_000_INT_5_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_LDS_000_INT_5_0 "state_machine.LDS_000_INT_5_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_0_1 "SM_AMIGA_ns_i_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_0_2 "SM_AMIGA_ns_i_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_0_3 "SM_AMIGA_ns_i_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_0_4 "SM_AMIGA_ns_i_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_5 "SM_AMIGA_ns_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_i_6 "SM_AMIGA_ns_i_i[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_7 "SM_AMIGA_ns_0[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_i_0_2 "clk.cpu_est_11_i_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_AMIGA_BUS_ENABLE_3_f0_i "state_machine.AMIGA_BUS_ENABLE_3_f0_i") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_0_0 "cpu_est_0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_0_a3_1 "clk.cpu_est_11_0_0_a3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_0_a3_0_1 "clk.cpu_est_11_0_0_a3_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_0_a3_1_1 "clk.cpu_est_11_0_0_a3_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_0_a3_3 "clk.cpu_est_11_0_0_a3[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_0_a3_0_3 "clk.cpu_est_11_0_0_a3_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_a3_0 "SM_AMIGA_ns_0_a3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_a3_0_0 "SM_AMIGA_ns_0_a3_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_0_a3_0 "cpu_est_0_0_a3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_0_a3_0_0 "cpu_est_0_0_a3_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_a2_0 "SM_AMIGA_ns_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_0_a2_1 "clk.cpu_est_11_0_0_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un6_bgack_000_0 "state_machine.un6_bgack_000_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_as_030_3_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un15_clk_000_d0_0 "state_machine.un15_clk_000_d0_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VPA_SYNC_1_sqmuxa_1_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un8_clk_000_d2_i "state_machine.un8_clk_000_d2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_0_a3_0_1 "SM_AMIGA_ns_i_0_a3_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_0_a3_2 "SM_AMIGA_ns_i_0_a3[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_0_a3_3 "SM_AMIGA_ns_i_0_a3[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_0_a3_4 "SM_AMIGA_ns_i_0_a3[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_0_a3_0_4 "SM_AMIGA_ns_i_0_a3_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_a3_5 "SM_AMIGA_ns_0_a3[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_i_a3_6 "SM_AMIGA_ns_i_i_a3[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_i_a3_0_6 "SM_AMIGA_ns_i_i_a3_0[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_a3_7 "SM_AMIGA_ns_0_a3[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_a3_0_7 "SM_AMIGA_ns_0_a3_0[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename clk_clk_cnt_i "clk.clk_cnt_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename clk_CLK_CNT_3_1 "clk.CLK_CNT_3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_OUT_PRE_0 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance G_96 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance G_92 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance (rename state_machine_un1_clk_030_i_a3 "state_machine.un1_clk_030_i_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_INT_1_sqmuxa_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance I_115 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un7_as_000_int_0_a3 "state_machine.un7_as_000_int_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_DSACK_INT_0_sqmuxa_i_o2_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_as_030_000_sync8_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename A_i_0 "A_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SIZE_i_1 "SIZE_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_0_a3_1 "SM_AMIGA_ns_i_0_a3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename A_i_16 "A_i[16]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_18 "A_i[18]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_19 "A_i[19]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_24 "A_i[24]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_25 "A_i[25]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_26 "A_i[26]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_27 "A_i[27]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_28 "A_i[28]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_29 "A_i[29]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_30 "A_i[30]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_31 "A_i[31]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_030_000_SYNC_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_000_D2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename CLK_CNT_i_0 "CLK_CNT_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename clk_CLK_CNT_3_0 "clk.CLK_CNT_3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un7_as_000_int_i "state_machine.un7_as_000_int_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RST_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_137_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance G_93 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename VPA_SYNC_0_r "VPA_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename VPA_SYNC_0_m "VPA_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename VPA_SYNC_0_n "VPA_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename VPA_SYNC_0_p "VPA_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_0_r "AMIGA_BUS_ENABLE_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_0_m "AMIGA_BUS_ENABLE_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_0_n "AMIGA_BUS_ENABLE_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_0_p "AMIGA_BUS_ENABLE_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_r "UDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_m "UDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_n "UDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_p "UDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename LDS_000_INT_0_r "LDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename LDS_000_INT_0_m "LDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename LDS_000_INT_0_n "LDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename LDS_000_INT_0_p "LDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename VMA_INT_0_r "VMA_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename VMA_INT_0_m "VMA_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename VMA_INT_0_n "VMA_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename VMA_INT_0_p "VMA_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance N_120_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename BG_000_0_r "BG_000_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename BG_000_0_m "BG_000_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BG_000_0_n "BG_000_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BG_000_0_p "BG_000_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename BGACK_030_INT_0_r "BGACK_030_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename BGACK_030_INT_0_m "BGACK_030_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BGACK_030_INT_0_n "BGACK_030_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BGACK_030_INT_0_p "BGACK_030_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename AS_000_INT_0_r "AS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AS_000_INT_0_m "AS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_000_INT_0_n "AS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_000_INT_0_p "AS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (instance (rename cpu_est_0_1__r "cpu_est_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename cpu_est_0_1__m "cpu_est_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename cpu_est_0_1__n "cpu_est_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename cpu_est_0_1__p "cpu_est_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance RW_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_110 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_i_1 "cpu_est_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance VPA_D_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un13_clk_000_d0_1 "state_machine.un13_clk_000_d0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un13_clk_000_d0_2 "state_machine.un13_clk_000_d0_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_0 "cpu_est_0[0]") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_a4_2_1 "clk.cpu_est_11_0_a4_2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_a4_1_1 "clk.cpu_est_11_0_a4_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_i_3 "cpu_est_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_i_2 "cpu_est_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_a4_0_1 "clk.cpu_est_11_0_a4_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_i_0 "cpu_est_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_a4_1 "clk.cpu_est_11_0_a4[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_o3_4 "SM_AMIGA_ns_i_o3[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_4 "SM_AMIGA_ns_i[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_2__r "cpu_est_0_2_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_0_2__m "cpu_est_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_2__n "cpu_est_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_2__p "cpu_est_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (instance (rename cpu_est_0_3__r "cpu_est_0_3_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename cpu_est_0_3__m "cpu_est_0_3_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename cpu_est_0_3__n "cpu_est_0_3_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) @@ -475,151 +594,31 @@ (instance (rename IPL_030_0_2__m "IPL_030_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename IPL_030_0_2__n "IPL_030_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename IPL_030_0_2__p "IPL_030_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename state_machine_un2_clk_000 "state_machine.un2_clk_000") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_000_D1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename clk_un4_clk_000_d1 "clk.un4_clk_000_d1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un15_clk_000_d0 "state_machine.un15_clk_000_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_a4_3 "clk.cpu_est_11_0_a4[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_a4_0_3 "clk.cpu_est_11_0_a4_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_i_2 "clk.cpu_est_11_i[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_o4_1 "clk.cpu_est_11_0_o4[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_o4_3 "clk.cpu_est_11_0_o4[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un13_clk_000_d0_2_i "state_machine.un13_clk_000_d0_2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance VMA_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename UDS_000_INT_0_r "UDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename UDS_000_INT_0_m "UDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename UDS_000_INT_0_n "UDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename UDS_000_INT_0_p "UDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename CLK_REF_1 "CLK_REF[1]") (viewRef prim (cellRef DLATRH (libraryRef mach))) ) (instance (rename state_machine_un23_clk_000_d0 "state_machine.un23_clk_000_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename VPA_SYNC_0_r "VPA_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename VPA_SYNC_0_m "VPA_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename VPA_SYNC_0_n "VPA_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename VPA_SYNC_0_p "VPA_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename AS_000_INT_0_r "AS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AS_000_INT_0_m "AS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AS_000_INT_0_n "AS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AS_000_INT_0_p "AS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename BGACK_030_INT_0_r "BGACK_030_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename BGACK_030_INT_0_m "BGACK_030_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename BGACK_030_INT_0_n "BGACK_030_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename BGACK_030_INT_0_p "BGACK_030_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename state_machine_un6_bgack_000 "state_machine.un6_bgack_000") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance N_95_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_000_INT_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_SYNC_1_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance VPA_SYNC_1_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_a3_2 "SM_AMIGA_ns_a3[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_2 "SM_AMIGA_ns[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename VMA_INT_0_r "VMA_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename VMA_INT_0_m "VMA_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename VMA_INT_0_n "VMA_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename VMA_INT_0_p "VMA_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename cpu_est_0_2__r "cpu_est_0_2_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_0_2__m "cpu_est_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_2__n "cpu_est_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_2__p "cpu_est_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename state_machine_un17_clk_030 "state_machine.un17_clk_030") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un1_clk_030 "state_machine.un1_clk_030") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename A_i_19 "A_i[19]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_i_18 "A_i[18]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_i_16 "A_i[16]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_96_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename DSACK_INT_0_1__r "DSACK_INT_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename DSACK_INT_0_1__m "DSACK_INT_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename DSACK_INT_0_1__n "DSACK_INT_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename DSACK_INT_0_1__p "DSACK_INT_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename BG_000_0_r "BG_000_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename BG_000_0_m "BG_000_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename BG_000_0_n "BG_000_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename BG_000_0_p "BG_000_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_0_r "AMIGA_BUS_ENABLE_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_0_m "AMIGA_BUS_ENABLE_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_0_n "AMIGA_BUS_ENABLE_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_0_p "AMIGA_BUS_ENABLE_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance CLK_000_D5_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un6_clk_000_d4 "state_machine.un6_clk_000_d4") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance BGACK_030_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance FPU_CS_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename AS_030_000_SYNC_0_r "AS_030_000_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename AS_030_000_SYNC_0_m "AS_030_000_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename AS_030_000_SYNC_0_n "AS_030_000_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename AS_030_000_SYNC_0_p "AS_030_000_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename FPU_CS_INT_0_r "FPU_CS_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename FPU_CS_INT_0_m "FPU_CS_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename FPU_CS_INT_0_n "FPU_CS_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename FPU_CS_INT_0_p "FPU_CS_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance DTACK_SYNC_1_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_77_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename DTACK_SYNC_0_r "DTACK_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename DTACK_SYNC_0_m "DTACK_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename DTACK_SYNC_0_n "DTACK_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename DTACK_SYNC_0_p "DTACK_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename LDS_000_INT_0_r "LDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename LDS_000_INT_0_m "LDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename LDS_000_INT_0_n "LDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename LDS_000_INT_0_p "LDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance nEXP_SPACE_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_AMIGA_BUS_ENABLE_2_iv "state_machine.AMIGA_BUS_ENABLE_2_iv") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance nEXP_SPACE_m (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_SM_AMIGA_0_sqmuxa_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un5_clk_030_i_a3 "state_machine.un5_clk_030_i_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_LDS_000_INT_7 "state_machine.LDS_000_INT_7") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_UDS_000_INT_7 "state_machine.UDS_000_INT_7") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DTACK_SYNC_1_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_as_030_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un42_clk_030_i "state_machine.un42_clk_030_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_as_030_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DSACK_INT_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_as_030_4_96 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_000_SYNC_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DS_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance CLK_OUT_PRE_0 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance G_91 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance G_87 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance G_86 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_o3_6 "SM_AMIGA_ns_i_o3[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_6 "SM_AMIGA_ns_i[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_5 "SM_AMIGA_ns[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_a3_0_6 "SM_AMIGA_ns_i_a3_0[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_a3_6 "SM_AMIGA_ns_i_a3[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_a3_5 "SM_AMIGA_ns_a3[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_CLK_CNT_3_0 "clk.CLK_CNT_3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_clk_cnt_i "clk.clk_cnt_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename clk_CLK_CNT_3_1 "clk.CLK_CNT_3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_a3_0 "SM_AMIGA_ns_i_a3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_a3_1 "SM_AMIGA_ns_a3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_a3_0_1 "SM_AMIGA_ns_a3_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un13_clk_000_d0_1_i "state_machine.un13_clk_000_d0_1_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_a3_7 "SM_AMIGA_ns_a3[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_0 "SM_AMIGA_ns_i[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_1 "SM_AMIGA_ns[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_7 "SM_AMIGA_ns[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_o3_1 "SM_AMIGA_ns_o3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_o3_0 "SM_AMIGA_ns_i_o3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance UDS_000_INT_0_sqmuxa_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance UDS_000_INT_0_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_132_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_133_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance G_88 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename A_i_24 "A_i[24]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_i_25 "A_i[25]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_i_26 "A_i[26]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_i_27 "A_i[27]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_i_28 "A_i[28]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_i_29 "A_i[29]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_i_30 "A_i[30]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_i_31 "A_i[31]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance CLK_000_D2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un30_clk_000_d1 "state_machine.un30_clk_000_d1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename CLK_CNT_i_0 "CLK_CNT_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un14_as_000_int_i "state_machine.un14_as_000_int_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RST_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename CLK_REF_0 "CLK_REF[0]") (viewRef prim (cellRef DLATSH (libraryRef mach))) ) - (instance (rename CLK_REF_1 "CLK_REF[1]") (viewRef prim (cellRef DLATRH (libraryRef mach))) ) - (instance BGACK_030_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance FPU_CS_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename FPU_CS_INT_0_r "FPU_CS_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename FPU_CS_INT_0_m "FPU_CS_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename FPU_CS_INT_0_n "FPU_CS_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename FPU_CS_INT_0_p "FPU_CS_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance N_74_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename DSACK_INT_0_1__r "DSACK_INT_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename DSACK_INT_0_1__m "DSACK_INT_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DSACK_INT_0_1__n "DSACK_INT_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DSACK_INT_0_1__p "DSACK_INT_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance N_75_i (viewRef prim (cellRef INV (libraryRef mach))) ) (net BGACK_030_INT (joined (portRef Q (instanceRef BGACK_030_INT)) (portRef I0 (instanceRef BGACK_030_INT_i)) @@ -631,17 +630,17 @@ )) (net FPU_CS_INT (joined (portRef Q (instanceRef FPU_CS_INT)) - (portRef I0 (instanceRef FPU_CS_INT_i)) (portRef I0 (instanceRef FPU_CS_INT_0_n)) + (portRef I0 (instanceRef FPU_CS_INT_i)) (portRef I0 (instanceRef FPU_CS)) )) (net (rename cpu_est_3 "cpu_est[3]") (joined (portRef Q (instanceRef cpu_est_3)) - (portRef I1 (instanceRef clk_cpu_est_11_0_a4_3)) - (portRef I0 (instanceRef cpu_est_0_3__n)) + (portRef I0 (instanceRef cpu_est_0_3__m)) + (portRef I1 (instanceRef clk_cpu_est_11_0_0_a3_3)) + (portRef I1 (instanceRef clk_cpu_est_11_0_0_a3_1_1)) (portRef I0 (instanceRef cpu_est_i_3)) - (portRef I0 (instanceRef clk_cpu_est_11_0_a4_2_1)) - (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_3)) + (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_3)) (portRef I0 (instanceRef E)) )) (net VMA_INT (joined @@ -652,83 +651,87 @@ )) (net (rename cpu_est_0 "cpu_est[0]") (joined (portRef Q (instanceRef cpu_est_0)) - (portRef I0 (instanceRef clk_cpu_est_11_0_o4_3)) + (portRef I1 (instanceRef clk_cpu_est_11_0_0_a2_1)) + (portRef I1 (instanceRef cpu_est_0_0_a3_0)) + (portRef I0 (instanceRef clk_cpu_est_11_0_0_o2_3)) (portRef I0 (instanceRef cpu_est_i_0)) - (portRef I1 (instanceRef clk_cpu_est_11_0_a4_1_1)) - (portRef I1 (instanceRef cpu_est_0_0)) - (portRef I0 (instanceRef clk_cpu_est_11_i_a4_1_2)) - (portRef I0 (instanceRef state_machine_un8_clk_000_d0_3)) + (portRef I1 (instanceRef clk_cpu_est_11_i_0_a3_1_2)) )) (net (rename cpu_est_1 "cpu_est[1]") (joined (portRef Q (instanceRef cpu_est_1)) - (portRef I1 (instanceRef clk_cpu_est_11_0_o4_3)) - (portRef I0 (instanceRef state_machine_un13_clk_000_d0_2)) + (portRef I0 (instanceRef cpu_est_0_1__m)) + (portRef I0 (instanceRef VMA_INT_0_m)) + (portRef I1 (instanceRef clk_cpu_est_11_0_0_o2_3)) + (portRef I0 (instanceRef clk_cpu_est_11_i_0_o2_2)) (portRef I0 (instanceRef cpu_est_i_1)) - (portRef I0 (instanceRef cpu_est_0_1__n)) - (portRef I0 (instanceRef clk_cpu_est_11_i_a4_0_1_2)) + (portRef I0 (instanceRef clk_cpu_est_11_i_0_a3_0_1_2)) )) (net AS_000_INT (joined (portRef Q (instanceRef AS_000_INT)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_o3_0)) (portRef I0 (instanceRef AS_000_INT_0_m)) - (portRef I0 (instanceRef state_machine_un13_clk_000_d0_1)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_o2_7)) (portRef I0 (instanceRef AS_000_INT_i)) (portRef I0 (instanceRef AS_000)) )) (net AS_030_000_SYNC (joined (portRef Q (instanceRef AS_030_000_SYNC)) - (portRef I0 (instanceRef AS_030_000_SYNC_i)) (portRef I0 (instanceRef AS_030_000_SYNC_0_n)) + (portRef I0 (instanceRef AS_030_000_SYNC_i)) )) (net DTACK_SYNC (joined (portRef Q (instanceRef DTACK_SYNC)) - (portRef I0 (instanceRef DTACK_SYNC_0_m)) + (portRef I0 (instanceRef DTACK_SYNC_0_n)) (portRef I0 (instanceRef state_machine_un23_clk_000_d0)) )) (net VPA_D (joined (portRef Q (instanceRef VPA_D)) (portRef I0 (instanceRef VPA_D_i)) - (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa_2)) + (portRef I1 (instanceRef DTACK_SYNC_1_sqmuxa_1_i_a3)) )) (net VPA_SYNC (joined (portRef Q (instanceRef VPA_SYNC)) - (portRef I0 (instanceRef VPA_SYNC_0_m)) (portRef I1 (instanceRef state_machine_un23_clk_000_d0)) + (portRef I0 (instanceRef VPA_SYNC_0_n)) )) (net CLK_000_D0 (joined (portRef Q (instanceRef CLK_000_D0)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_0)) - (portRef I0 (instanceRef SM_AMIGA_ns_a3_2)) - (portRef I0 (instanceRef clk_un4_clk_000_d1)) - (portRef I0 (instanceRef state_machine_un2_clk_000)) - (portRef I1 (instanceRef state_machine_un13_clk_000_d0_1)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_i_a3_0_6)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_0_2)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_o2_7)) + (portRef I0 (instanceRef clk_un4_clk_000_d1_0_o2)) (portRef I0 (instanceRef CLK_000_D0_i)) + (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_2)) (portRef D (instanceRef CLK_000_D1)) )) (net CLK_000_D1 (joined (portRef Q (instanceRef CLK_000_D1)) - (portRef I0 (instanceRef state_machine_un30_clk_000_d1)) (portRef I0 (instanceRef CLK_000_D1_i)) (portRef D (instanceRef CLK_000_D2)) )) (net CLK_000_D2 (joined (portRef Q (instanceRef CLK_000_D2)) (portRef I0 (instanceRef CLK_000_D2_i)) + (portRef D (instanceRef CLK_000_D3)) + )) + (net CLK_000_D5 (joined + (portRef Q (instanceRef CLK_000_D5)) + (portRef I0 (instanceRef CLK_000_D5_i)) )) (net CLK_OUT_PRE (joined (portRef Q (instanceRef CLK_OUT_PRE)) (portRef I0 (instanceRef CLK_OUT_PRE_0)) - (portRef I0 (instanceRef CLK_OUT_PRE_i)) - (portRef I1 (instanceRef un1_DSACK_INT_0_sqmuxa_i_a3_1)) (portRef D (instanceRef CLK_OUT_INT)) )) (net (rename SM_AMIGA_6 "SM_AMIGA[6]") (joined (portRef Q (instanceRef SM_AMIGA_6)) - (portRef I1 (instanceRef SM_AMIGA_ns_a3_1)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_a2_0)) + (portRef I0 (instanceRef state_machine_AMIGA_BUS_ENABLE_3_f0_i_o2)) (portRef I0 (instanceRef SM_AMIGA_i_6)) - (portRef I1 (instanceRef un1_SM_AMIGA_0_sqmuxa_i_a3)) - (portRef I0 (instanceRef nEXP_SPACE_m)) - (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa_1_2)) + )) + (net (rename SM_AMIGA_5 "SM_AMIGA[5]") (joined + (portRef Q (instanceRef SM_AMIGA_5)) + (portRef I0 (instanceRef SM_AMIGA_i_5)) + (portRef I0 (instanceRef state_machine_UDS_000_INT_5_0_m2_m)) )) (net VCC (joined (portRef I0 (instanceRef AMIGA_BUS_ENABLE_LOW)) @@ -738,88 +741,131 @@ (net GND (joined (portRef LAT (instanceRef CLK_REF_1)) (portRef D (instanceRef CLK_REF_1)) - (portRef LAT (instanceRef CLK_REF_0)) - (portRef D (instanceRef CLK_REF_0)) (portRef I0 (instanceRef AVEC_EXP)) (portRef I0 (instanceRef BERR)) )) (net (rename cpu_est_2 "cpu_est[2]") (joined (portRef Q (instanceRef cpu_est_2)) - (portRef I0 (instanceRef cpu_est_0_2__n)) + (portRef I0 (instanceRef cpu_est_0_2__m)) + (portRef I1 (instanceRef clk_cpu_est_11_i_0_o2_2)) (portRef I0 (instanceRef cpu_est_i_2)) - (portRef I1 (instanceRef state_machine_un13_clk_000_d0_2)) - (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_2)) - (portRef I1 (instanceRef state_machine_un8_clk_000_d0_3)) - )) - (net (rename CLK_REF_0 "CLK_REF[0]") (joined - (portRef Q (instanceRef CLK_REF_0)) - (portRef I1 (instanceRef G_86)) + (portRef I1 (instanceRef state_machine_un15_clk_000_d0_0_a3_2)) + (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_2_0)) )) (net (rename CLK_REF_1 "CLK_REF[1]") (joined (portRef Q (instanceRef CLK_REF_1)) - (portRef I1 (instanceRef G_87)) - )) - (net (rename SM_AMIGA_7 "SM_AMIGA[7]") (joined - (portRef Q (instanceRef SM_AMIGA_7)) - (portRef I1 (instanceRef SM_AMIGA_ns_a3_0_1)) - (portRef I0 (instanceRef SM_AMIGA_i_7)) + (portRef I1 (instanceRef G_92)) )) (net UDS_000_INT (joined (portRef Q (instanceRef UDS_000_INT)) - (portRef I0 (instanceRef UDS_000_INT_0_m)) + (portRef I0 (instanceRef UDS_000_INT_0_n)) (portRef I0 (instanceRef UDS_000)) )) (net LDS_000_INT (joined (portRef Q (instanceRef LDS_000_INT)) - (portRef I0 (instanceRef LDS_000_INT_0_m)) + (portRef I0 (instanceRef LDS_000_INT_0_n)) (portRef I0 (instanceRef LDS_000)) )) (net (rename DSACK_INT_1 "DSACK_INT[1]") (joined (portRef Q (instanceRef DSACK_INT_1)) - (portRef I0 (instanceRef DSACK_INT_0_1__m)) + (portRef I0 (instanceRef DSACK_INT_0_1__n)) (portRef I0 (instanceRef DSACK_1)) )) + (net (rename SM_AMIGA_7 "SM_AMIGA[7]") (joined + (portRef Q (instanceRef SM_AMIGA_7)) + (portRef I0 (instanceRef SM_AMIGA_i_7)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_0_a3_0_1)) + (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a3_2)) + (portRef I0 (instanceRef un1_bg_030_i_a3_2)) + )) + (net AS_000_INT_1_sqmuxa (joined + (portRef O (instanceRef AS_000_INT_1_sqmuxa_0_a3)) + (portRef I1 (instanceRef AS_000_INT_0_m)) + (portRef I0 (instanceRef AS_000_INT_0_r)) + )) + (net (rename state_machine_un8_clk_000_d2 "state_machine.un8_clk_000_d2") (joined + (portRef O (instanceRef state_machine_un8_clk_000_d2)) + (portRef I0 (instanceRef state_machine_un8_clk_000_d2_i)) + )) + (net CLK_000_D3 (joined + (portRef Q (instanceRef CLK_000_D3)) + (portRef I0 (instanceRef state_machine_un8_clk_000_d2_1)) + (portRef D (instanceRef CLK_000_D4)) + )) (net (rename SM_AMIGA_4 "SM_AMIGA[4]") (joined (portRef Q (instanceRef SM_AMIGA_4)) (portRef I0 (instanceRef SM_AMIGA_i_4)) - (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_1_0)) + (portRef I0 (instanceRef state_machine_UDS_000_INT_5_0_m2_n)) )) - (net (rename SM_AMIGA_1 "SM_AMIGA[1]") (joined - (portRef Q (instanceRef SM_AMIGA_1)) - (portRef I0 (instanceRef SM_AMIGA_i_1)) - (portRef I1 (instanceRef un1_DSACK_INT_0_sqmuxa_i_a3)) + (net (rename state_machine_un23_clk_000_d0 "state_machine.un23_clk_000_d0") (joined + (portRef O (instanceRef state_machine_un23_clk_000_d0_i_0)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_a3_0_5)) + )) + (net (rename state_machine_un6_clk_000_d4 "state_machine.un6_clk_000_d4") (joined + (portRef O (instanceRef state_machine_un6_clk_000_d4)) + (portRef I1 (instanceRef un1_DSACK_INT_0_sqmuxa_i_o2_i_a3)) + (portRef I0 (instanceRef state_machine_un6_clk_000_d4_i)) + )) + (net CLK_000_D4 (joined + (portRef Q (instanceRef CLK_000_D4)) + (portRef I0 (instanceRef state_machine_un6_clk_000_d4)) + (portRef D (instanceRef CLK_000_D5)) )) (net DTACK_DMA (joined (portRef Q (instanceRef DTACK_DMA)) (portRef I0 (instanceRef DTACK)) )) (net (rename clk_clk_cnt "clk.clk_cnt") (joined - (portRef O (instanceRef G_88)) - (portRef I0 (instanceRef clk_clk_cnt_i)) + (portRef O (instanceRef G_93)) (portRef I1 (instanceRef CLK_OUT_PRE_0)) + (portRef I0 (instanceRef clk_clk_cnt_i)) )) (net (rename CLK_CNT_0 "CLK_CNT[0]") (joined (portRef Q (instanceRef CLK_CNT_0)) (portRef I0 (instanceRef CLK_CNT_i_0)) - (portRef I0 (instanceRef G_86)) - (portRef I0 (instanceRef G_91)) + (portRef I0 (instanceRef G_96)) )) (net (rename CLK_CNT_1 "CLK_CNT[1]") (joined (portRef Q (instanceRef CLK_CNT_1)) - (portRef I0 (instanceRef G_87)) - (portRef I1 (instanceRef G_91)) + (portRef I0 (instanceRef G_92)) + (portRef I1 (instanceRef G_96)) )) - (net (rename state_machine_un14_as_000_int "state_machine.un14_as_000_int") (joined - (portRef O (instanceRef state_machine_un14_as_000_int)) - (portRef I0 (instanceRef state_machine_un14_as_000_int_i)) + (net (rename state_machine_un6_bgack_000 "state_machine.un6_bgack_000") (joined + (portRef O (instanceRef state_machine_un6_bgack_000_0_i)) + (portRef I1 (instanceRef BGACK_030_INT_0_m)) + (portRef I0 (instanceRef BGACK_030_INT_0_r)) )) (net (rename SM_AMIGA_3 "SM_AMIGA[3]") (joined (portRef Q (instanceRef SM_AMIGA_3)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_o3_4)) + (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_2)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_0_o2_4)) (portRef I0 (instanceRef SM_AMIGA_i_3)) - (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1_0)) - (portRef I1 (instanceRef SM_AMIGA_ns_a3_0_1_5)) - (portRef I1 (instanceRef DTACK_SYNC_1_sqmuxa_1_0)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_a3_0_1_5)) + )) + (net (rename SM_AMIGA_1 "SM_AMIGA[1]") (joined + (portRef Q (instanceRef SM_AMIGA_1)) + (portRef I0 (instanceRef un1_DSACK_INT_0_sqmuxa_i_o2_i_a3)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_a3_0_7)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_i_a3_6)) + )) + (net (rename SM_AMIGA_2 "SM_AMIGA[2]") (joined + (portRef Q (instanceRef SM_AMIGA_2)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_i_a3_0_6)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_a3_5)) + )) + (net (rename SM_AMIGA_0 "SM_AMIGA[0]") (joined + (portRef Q (instanceRef SM_AMIGA_0)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_a3_7)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_a3_0_0)) + )) + (net (rename state_machine_un7_as_000_int "state_machine.un7_as_000_int") (joined + (portRef O (instanceRef state_machine_un7_as_000_int_0_a3)) + (portRef I0 (instanceRef state_machine_un7_as_000_int_i)) + )) + (net (rename state_machine_un15_clk_000_d0 "state_machine.un15_clk_000_d0") (joined + (portRef O (instanceRef state_machine_un15_clk_000_d0_0_i)) + (portRef I1 (instanceRef VMA_INT_0_m)) + (portRef I0 (instanceRef VMA_INT_0_r)) )) (net (rename clk_CLK_CNT_3_0 "clk.CLK_CNT_3[0]") (joined (portRef O (instanceRef clk_CLK_CNT_3_0)) @@ -829,75 +875,72 @@ (portRef O (instanceRef clk_CLK_CNT_3_1)) (portRef D (instanceRef CLK_CNT_1)) )) - (net (rename SM_AMIGA_5 "SM_AMIGA[5]") (joined - (portRef Q (instanceRef SM_AMIGA_5)) - (portRef I1 (instanceRef SM_AMIGA_ns_a3_2)) - (portRef I0 (instanceRef SM_AMIGA_i_5)) + (net (rename state_machine_LDS_000_INT_5 "state_machine.LDS_000_INT_5") (joined + (portRef O (instanceRef state_machine_LDS_000_INT_5_0_i)) + (portRef I0 (instanceRef LDS_000_INT_0_m)) )) - (net (rename SM_AMIGA_2 "SM_AMIGA[2]") (joined - (portRef Q (instanceRef SM_AMIGA_2)) - (portRef I1 (instanceRef SM_AMIGA_ns_a3_5)) - (portRef I0 (instanceRef SM_AMIGA_i_2)) + (net (rename state_machine_UDS_000_INT_5 "state_machine.UDS_000_INT_5") (joined + (portRef O (instanceRef state_machine_UDS_000_INT_5_0_i)) + (portRef I0 (instanceRef UDS_000_INT_0_m)) )) - (net (rename SM_AMIGA_0 "SM_AMIGA[0]") (joined - (portRef Q (instanceRef SM_AMIGA_0)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_o3_0)) - (portRef I0 (instanceRef SM_AMIGA_ns_a3_7)) + (net un1_AMIGA_BUS_ENABLE_1_sqmuxa_2 (joined + (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0_o3_i)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_m)) )) (net N_1 (joined - (portRef O (instanceRef UDS_000_INT_0_p)) - (portRef D (instanceRef UDS_000_INT)) - )) - (net N_2 (joined - (portRef O (instanceRef LDS_000_INT_0_p)) - (portRef D (instanceRef LDS_000_INT)) - )) - (net N_3 (joined - (portRef O (instanceRef DTACK_SYNC_0_p)) - (portRef D (instanceRef DTACK_SYNC)) - )) - (net N_4 (joined - (portRef O (instanceRef VPA_SYNC_0_p)) - (portRef D (instanceRef VPA_SYNC)) - )) - (net N_5 (joined - (portRef O (instanceRef FPU_CS_INT_0_p)) - (portRef D (instanceRef FPU_CS_INT)) - )) - (net N_6 (joined (portRef O (instanceRef AS_030_000_SYNC_0_p)) (portRef D (instanceRef AS_030_000_SYNC)) )) - (net N_7 (joined - (portRef O (instanceRef AS_000_INT_0_p)) - (portRef D (instanceRef AS_000_INT)) + (net N_2 (joined + (portRef O (instanceRef DTACK_SYNC_0_p)) + (portRef D (instanceRef DTACK_SYNC)) )) - (net N_8 (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_0_p)) - (portRef D (instanceRef AMIGA_BUS_ENABLEDFF)) + (net N_3 (joined + (portRef O (instanceRef FPU_CS_INT_0_p)) + (portRef D (instanceRef FPU_CS_INT)) )) - (net N_9 (joined - (portRef O (instanceRef BG_000_0_p)) - (portRef D (instanceRef BG_000DFFSH)) - )) - (net N_10 (joined + (net N_4 (joined (portRef O (instanceRef DSACK_INT_0_1__p)) (portRef D (instanceRef DSACK_INT_1)) )) - (net N_11 (joined + (net N_5 (joined + (portRef O (instanceRef VPA_SYNC_0_p)) + (portRef D (instanceRef VPA_SYNC)) + )) + (net N_6 (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_0_p)) + (portRef D (instanceRef AMIGA_BUS_ENABLEDFF)) + )) + (net N_7 (joined + (portRef O (instanceRef UDS_000_INT_0_p)) + (portRef D (instanceRef UDS_000_INT)) + )) + (net N_8 (joined + (portRef O (instanceRef LDS_000_INT_0_p)) + (portRef D (instanceRef LDS_000_INT)) + )) + (net N_9 (joined (portRef O (instanceRef VMA_INT_0_p)) (portRef D (instanceRef VMA_INT)) )) + (net N_10 (joined + (portRef O (instanceRef BG_000_0_p)) + (portRef D (instanceRef BG_000DFFSH)) + )) + (net N_11 (joined + (portRef O (instanceRef CLK_OUT_PRE_0)) + (portRef D (instanceRef CLK_OUT_PRE)) + )) (net N_12 (joined (portRef O (instanceRef BGACK_030_INT_0_p)) (portRef D (instanceRef BGACK_030_INT)) )) (net N_13 (joined - (portRef O (instanceRef CLK_OUT_PRE_0)) - (portRef D (instanceRef CLK_OUT_PRE)) + (portRef O (instanceRef AS_000_INT_0_p)) + (portRef D (instanceRef AS_000_INT)) )) (net N_14 (joined - (portRef O (instanceRef cpu_est_0_0)) + (portRef O (instanceRef cpu_est_0_0_i_0)) (portRef D (instanceRef cpu_est_0)) )) (net N_15 (joined @@ -924,218 +967,80 @@ (portRef O (instanceRef IPL_030_0_2__p)) (portRef D (instanceRef IPL_030DFFSH_2)) )) - (net (rename SM_AMIGA_ns_1 "SM_AMIGA_ns[1]") (joined - (portRef O (instanceRef SM_AMIGA_ns_i_1)) - (portRef D (instanceRef SM_AMIGA_6)) - )) - (net (rename SM_AMIGA_ns_2 "SM_AMIGA_ns[2]") (joined - (portRef O (instanceRef SM_AMIGA_ns_i_2)) - (portRef D (instanceRef SM_AMIGA_5)) + (net (rename SM_AMIGA_ns_0 "SM_AMIGA_ns[0]") (joined + (portRef O (instanceRef SM_AMIGA_ns_0_i_0)) + (portRef D (instanceRef SM_AMIGA_7)) )) (net (rename SM_AMIGA_ns_5 "SM_AMIGA_ns[5]") (joined - (portRef O (instanceRef SM_AMIGA_ns_i_5)) + (portRef O (instanceRef SM_AMIGA_ns_0_i_5)) (portRef D (instanceRef SM_AMIGA_2)) )) (net (rename SM_AMIGA_ns_7 "SM_AMIGA_ns[7]") (joined - (portRef O (instanceRef SM_AMIGA_ns_i_7)) + (portRef O (instanceRef SM_AMIGA_ns_0_i_7)) (portRef D (instanceRef SM_AMIGA_0)) )) - (net N_132 (joined - (portRef O (instanceRef G_86)) - (portRef I0 (instanceRef N_132_i)) + (net (rename clk_cpu_est_11_1 "clk.cpu_est_11[1]") (joined + (portRef O (instanceRef clk_cpu_est_11_0_0_i_1)) + (portRef I0 (instanceRef cpu_est_0_1__n)) )) - (net N_133 (joined - (portRef O (instanceRef G_87)) - (portRef I0 (instanceRef N_133_i)) + (net (rename clk_cpu_est_11_3 "clk.cpu_est_11[3]") (joined + (portRef O (instanceRef clk_cpu_est_11_0_0_i_3)) + (portRef I0 (instanceRef cpu_est_0_3__n)) )) - (net (rename state_machine_un30_clk_000_d1 "state_machine.un30_clk_000_d1") (joined - (portRef O (instanceRef state_machine_un30_clk_000_d1)) - (portRef I1 (instanceRef SM_AMIGA_ns_o3_1)) - (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa_1)) - )) - (net N_148 (joined - (portRef O (instanceRef un1_as_030_4_96)) - (portRef I1 (instanceRef un1_as_030_4)) - (portRef I0 (instanceRef N_148_i)) - )) - (net DTACK_SYNC_1_sqmuxa (joined - (portRef O (instanceRef DTACK_SYNC_1_sqmuxa)) - (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa_i)) - )) - (net N_96 (joined - (portRef O (instanceRef un1_DSACK_INT_0_sqmuxa_i_a3)) - (portRef I0 (instanceRef N_96_i)) + (net N_137 (joined + (portRef O (instanceRef G_92)) + (portRef I0 (instanceRef N_137_i)) )) (net (rename un3_clk_cnt_1 "un3_clk_cnt[1]") (joined - (portRef O (instanceRef G_91)) + (portRef O (instanceRef G_96)) (portRef I1 (instanceRef clk_CLK_CNT_3_1)) )) - (net N_89 (joined - (portRef O (instanceRef SM_AMIGA_ns_o3_i_1)) - (portRef I0 (instanceRef SM_AMIGA_ns_a3_1)) - )) - (net N_97 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_a3_0)) - (portRef I0 (instanceRef N_97_i)) - )) - (net N_90 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_o3_i_0)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_a3_0)) - )) - (net N_98 (joined - (portRef O (instanceRef SM_AMIGA_ns_a3_1)) - (portRef I0 (instanceRef N_98_i)) - )) - (net N_99 (joined - (portRef O (instanceRef SM_AMIGA_ns_a3_0_1)) - (portRef I0 (instanceRef N_99_i)) - )) - (net N_108 (joined - (portRef O (instanceRef SM_AMIGA_ns_a3_7)) - (portRef I0 (instanceRef N_108_i)) - )) - (net UDS_000_INT_0_sqmuxa (joined - (portRef O (instanceRef UDS_000_INT_0_sqmuxa)) - (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_i)) - )) - (net UDS_000_INT_0_sqmuxa_1 (joined - (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1)) - (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_1_i)) - )) - (net (rename state_machine_un13_clk_000_d0_1 "state_machine.un13_clk_000_d0_1") (joined - (portRef O (instanceRef state_machine_un13_clk_000_d0_1)) - (portRef I0 (instanceRef state_machine_un13_clk_000_d0_1_i)) - (portRef I0 (instanceRef state_machine_un13_clk_000_d0_2_0)) - )) - (net N_168 (joined - (portRef O (instanceRef un8_ciin)) - (portRef OE (instanceRef CIIN)) - )) - (net N_171 (joined - (portRef O (instanceRef un4_ciin)) - (portRef I0 (instanceRef CIIN)) - )) - (net N_105 (joined - (portRef O (instanceRef SM_AMIGA_ns_a3_0_5)) - (portRef I0 (instanceRef N_105_i)) - )) - (net N_92 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_o3_i_6)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_a3_6)) - )) - (net N_106 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_a3_6)) - (portRef I0 (instanceRef N_106_i)) - )) - (net N_107 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_a3_0_6)) - (portRef I0 (instanceRef N_107_i)) - )) - (net N_104 (joined - (portRef O (instanceRef SM_AMIGA_ns_a3_5)) - (portRef I0 (instanceRef N_104_i)) - )) - (net (rename state_machine_un42_clk_030 "state_machine.un42_clk_030") (joined - (portRef O (instanceRef state_machine_un42_clk_030)) - (portRef I1 (instanceRef un1_as_030_3)) - (portRef I0 (instanceRef state_machine_un42_clk_030_i)) - )) - (net (rename state_machine_un44_clk_000_d1 "state_machine.un44_clk_000_d1") (joined - (portRef O (instanceRef state_machine_un44_clk_000_d1_i_0)) - (portRef I1 (instanceRef state_machine_LDS_000_INT_7)) - )) - (net un1_bg_030 (joined - (portRef O (instanceRef un1_bg_030_i)) - (portRef I0 (instanceRef BG_000_0_m)) - )) - (net N_94 (joined - (portRef O (instanceRef state_machine_un5_clk_030_i_a3)) - (portRef I0 (instanceRef N_94_i)) - )) - (net (rename state_machine_AS_030_000_SYNC_3 "state_machine.AS_030_000_SYNC_3") (joined - (portRef O (instanceRef state_machine_AS_030_000_SYNC_3_i)) - (portRef I0 (instanceRef AS_030_000_SYNC_0_m)) - )) - (net AMIGA_BUS_ENABLE_i_m (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_i_m)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_i_m_i)) - )) - (net nEXP_SPACE_m (joined - (portRef O (instanceRef nEXP_SPACE_m)) - (portRef I0 (instanceRef nEXP_SPACE_m_i)) - )) - (net N_95 (joined - (portRef O (instanceRef un1_SM_AMIGA_0_sqmuxa_i_a3)) - (portRef I0 (instanceRef N_95_i)) - )) - (net (rename state_machine_LDS_000_INT_7 "state_machine.LDS_000_INT_7") (joined - (portRef O (instanceRef state_machine_LDS_000_INT_7_i)) - (portRef I0 (instanceRef LDS_000_INT_0_n)) - )) - (net (rename state_machine_UDS_000_INT_7 "state_machine.UDS_000_INT_7") (joined - (portRef O (instanceRef state_machine_UDS_000_INT_7_i)) - (portRef I0 (instanceRef UDS_000_INT_0_n)) - )) - (net DTACK_SYNC_1_sqmuxa_1 (joined - (portRef O (instanceRef DTACK_SYNC_1_sqmuxa_1)) - (portRef I1 (instanceRef DTACK_SYNC_0_m)) - (portRef I0 (instanceRef DTACK_SYNC_0_r)) - )) - (net un1_as_030_4 (joined - (portRef O (instanceRef un1_as_030_4)) + (net N_162 (joined + (portRef O (instanceRef un1_as_030_3_i_i)) (portRef I1 (instanceRef LDS_000_INT_0_m)) (portRef I0 (instanceRef LDS_000_INT_0_r)) (portRef I1 (instanceRef UDS_000_INT_0_m)) (portRef I0 (instanceRef UDS_000_INT_0_r)) )) - (net un1_as_030_3 (joined - (portRef O (instanceRef un1_as_030_3_i)) - (portRef I0 (instanceRef FPU_CS_INT_0_m)) - )) - (net DSACK_INT_1_sqmuxa (joined - (portRef O (instanceRef DSACK_INT_1_sqmuxa)) - (portRef I1 (instanceRef DSACK_INT_0_1__m)) - (portRef I0 (instanceRef DSACK_INT_0_1__r)) - )) - (net (rename state_machine_un17_clk_030 "state_machine.un17_clk_030") (joined - (portRef O (instanceRef state_machine_un17_clk_030_i)) - (portRef I1 (instanceRef FPU_CS_INT_0_m)) - (portRef I0 (instanceRef FPU_CS_INT_0_r)) - (portRef I1 (instanceRef AS_030_000_SYNC_0_m)) - (portRef I0 (instanceRef AS_030_000_SYNC_0_r)) - )) - (net (rename state_machine_un1_clk_030 "state_machine.un1_clk_030") (joined - (portRef O (instanceRef state_machine_un1_clk_030_i)) - (portRef I1 (instanceRef BG_000_0_m)) - (portRef I0 (instanceRef BG_000_0_r)) - )) - (net (rename state_machine_un23_clk_000_d0 "state_machine.un23_clk_000_d0") (joined - (portRef O (instanceRef state_machine_un23_clk_000_d0_i_0)) - (portRef I1 (instanceRef SM_AMIGA_ns_a3_0_5)) - )) - (net VPA_SYNC_1_sqmuxa (joined - (portRef O (instanceRef VPA_SYNC_1_sqmuxa)) - (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_i)) - )) - (net VPA_SYNC_1_sqmuxa_1 (joined - (portRef O (instanceRef VPA_SYNC_1_sqmuxa_1)) + (net N_163 (joined + (portRef O (instanceRef VPA_SYNC_1_sqmuxa_1_i_i)) (portRef I1 (instanceRef VPA_SYNC_0_m)) (portRef I0 (instanceRef VPA_SYNC_0_r)) )) - (net AS_000_INT_1_sqmuxa (joined - (portRef O (instanceRef AS_000_INT_1_sqmuxa)) - (portRef I1 (instanceRef AS_000_INT_0_m)) - (portRef I0 (instanceRef AS_000_INT_0_r)) + (net N_164 (joined + (portRef O (instanceRef un1_as_030_000_sync8_i_i)) + (portRef I1 (instanceRef FPU_CS_INT_0_m)) + (portRef I0 (instanceRef FPU_CS_INT_0_r)) )) - (net (rename state_machine_un6_bgack_000 "state_machine.un6_bgack_000") (joined - (portRef O (instanceRef state_machine_un6_bgack_000_i)) - (portRef I1 (instanceRef BGACK_030_INT_0_m)) - (portRef I0 (instanceRef BGACK_030_INT_0_r)) + (net N_165 (joined + (portRef O (instanceRef DTACK_SYNC_1_sqmuxa_1_i_i)) + (portRef I1 (instanceRef DTACK_SYNC_0_m)) + (portRef I0 (instanceRef DTACK_SYNC_0_r)) )) - (net (rename clk_un4_clk_000_d1 "clk.un4_clk_000_d1") (joined - (portRef O (instanceRef clk_un4_clk_000_d1)) - (portRef I1 (instanceRef cpu_est_0_2__m)) - (portRef I0 (instanceRef cpu_est_0_2__r)) + (net N_30 (joined + (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_i)) + (portRef I1 (instanceRef AS_030_000_SYNC_0_m)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_r)) + )) + (net N_39 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_i_i_6)) + (portRef D (instanceRef SM_AMIGA_1)) + )) + (net N_51 (joined + (portRef O (instanceRef state_machine_UDS_000_INT_5_0_m2_p)) + (portRef I1 (instanceRef state_machine_UDS_000_INT_5_0_o3)) + )) + (net N_52 (joined + (portRef O (instanceRef DSACK_INT_1_sqmuxa_i_o3_i)) + (portRef I1 (instanceRef DSACK_INT_0_1__m)) + (portRef I0 (instanceRef DSACK_INT_0_1__r)) + )) + (net N_55 (joined + (portRef O (instanceRef clk_cpu_est_11_i_0_o2_i_2)) + (portRef I0 (instanceRef clk_cpu_est_11_i_0_a3_1_2)) + )) + (net N_56 (joined + (portRef O (instanceRef clk_un4_clk_000_d1_0_o2_i)) (portRef I1 (instanceRef IPL_030_0_2__m)) (portRef I0 (instanceRef IPL_030_0_2__r)) (portRef I1 (instanceRef IPL_030_0_1__m)) @@ -1144,311 +1049,357 @@ (portRef I0 (instanceRef IPL_030_0_0__r)) (portRef I1 (instanceRef cpu_est_0_3__m)) (portRef I0 (instanceRef cpu_est_0_3__r)) - (portRef I0 (instanceRef cpu_est_0_0)) + (portRef I1 (instanceRef cpu_est_0_2__m)) + (portRef I0 (instanceRef cpu_est_0_2__r)) (portRef I1 (instanceRef cpu_est_0_1__m)) (portRef I0 (instanceRef cpu_est_0_1__r)) - (portRef I0 (instanceRef clk_un4_clk_000_d1_i)) + (portRef I1 (instanceRef state_machine_un6_bgack_000_0)) + (portRef I0 (instanceRef cpu_est_0_0_a3_0)) )) - (net N_100 (joined - (portRef O (instanceRef SM_AMIGA_ns_a3_2)) - (portRef I0 (instanceRef N_100_i)) + (net N_57 (joined + (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_i)) + (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a3_1)) )) - (net (rename state_machine_un15_clk_000_d0 "state_machine.un15_clk_000_d0") (joined - (portRef O (instanceRef state_machine_un15_clk_000_d0_i)) - (portRef I1 (instanceRef VMA_INT_0_m)) - (portRef I0 (instanceRef VMA_INT_0_r)) + (net N_58 (joined + (portRef O (instanceRef state_machine_AMIGA_BUS_ENABLE_3_f0_i_o2_i)) + (portRef I0 (instanceRef state_machine_AMIGA_BUS_ENABLE_3_f0_i)) )) - (net (rename clk_cpu_est_11_3 "clk.cpu_est_11[3]") (joined - (portRef O (instanceRef clk_cpu_est_11_0_i_3)) - (portRef I0 (instanceRef cpu_est_0_3__m)) + (net N_59 (joined + (portRef O (instanceRef SM_AMIGA_ns_0_o2_i_7)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_a3_7)) )) - (net (rename state_machine_un2_clk_000 "state_machine.un2_clk_000") (joined - (portRef O (instanceRef state_machine_un2_clk_000)) - (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_4)) - (portRef I1 (instanceRef DTACK_SYNC_1_sqmuxa_2)) + (net N_60 (joined + (portRef O (instanceRef clk_cpu_est_11_0_0_o2_i_1)) + (portRef I0 (instanceRef clk_cpu_est_11_0_0_a3_1)) )) - (net (rename state_machine_un13_clk_000_d0 "state_machine.un13_clk_000_d0") (joined - (portRef O (instanceRef state_machine_un13_clk_000_d0)) - (portRef I0 (instanceRef state_machine_un13_clk_000_d0_i)) + (net N_61 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_i_o2_i_6)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_i_a3_6)) )) - (net (rename state_machine_un8_clk_000_d0 "state_machine.un8_clk_000_d0") (joined - (portRef O (instanceRef state_machine_un8_clk_000_d0)) - (portRef I0 (instanceRef state_machine_un8_clk_000_d0_i)) + (net N_62 (joined + (portRef O (instanceRef clk_cpu_est_11_0_0_o2_i_3)) + (portRef I0 (instanceRef clk_cpu_est_11_0_0_a3_3)) )) - (net N_129 (joined - (portRef O (instanceRef clk_cpu_est_11_0_a4_3)) - (portRef I0 (instanceRef N_129_i)) + (net N_63 (joined + (portRef O (instanceRef state_machine_UDS_000_INT_5_0_o3_i)) + (portRef I1 (instanceRef un1_as_030_3_i)) )) - (net N_122 (joined - (portRef O (instanceRef clk_cpu_est_11_0_o4_i_3)) - (portRef I0 (instanceRef clk_cpu_est_11_0_a4_3)) + (net N_65 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_0_o2_i_1)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_0_a3_1)) )) - (net N_130 (joined - (portRef O (instanceRef clk_cpu_est_11_0_a4_0_3)) - (portRef I0 (instanceRef N_130_i)) + (net N_66 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_0_o2_i_4)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_0_a3_4)) )) - (net N_127 (joined - (portRef O (instanceRef clk_cpu_est_11_i_a4_2)) - (portRef I0 (instanceRef N_127_i)) + (net N_69 (joined + (portRef O (instanceRef state_machine_un1_clk_030_i_a3)) + (portRef I1 (instanceRef BG_000_0_m)) + (portRef I0 (instanceRef BG_000_0_r)) )) - (net N_128 (joined - (portRef O (instanceRef clk_cpu_est_11_i_a4_0_2)) - (portRef I0 (instanceRef N_128_i)) + (net N_72 (joined + (portRef O (instanceRef state_machine_un15_clk_000_d0_0_a3)) + (portRef I0 (instanceRef N_72_i)) + )) + (net N_73 (joined + (portRef O (instanceRef state_machine_un15_clk_000_d0_0_a3_0)) + (portRef I0 (instanceRef N_73_i)) + )) + (net N_74 (joined + (portRef O (instanceRef un1_DSACK_INT_0_sqmuxa_i_o2_i_a3)) + (portRef I0 (instanceRef N_74_i)) + )) + (net N_75 (joined + (portRef O (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3)) + (portRef I0 (instanceRef N_75_i)) + )) + (net N_76 (joined + (portRef O (instanceRef un1_as_030_000_sync8_i_a3)) + (portRef I0 (instanceRef N_76_i)) + )) + (net N_77 (joined + (portRef O (instanceRef DTACK_SYNC_1_sqmuxa_1_i_a3)) + (portRef I0 (instanceRef N_77_i)) + )) + (net N_79 (joined + (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a3)) + (portRef I0 (instanceRef N_79_i)) + )) + (net N_81 (joined + (portRef O (instanceRef state_machine_LDS_000_INT_5_0_a3)) + (portRef I0 (instanceRef N_81_i)) + )) + (net N_83 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_0_a3_1)) + (portRef I0 (instanceRef N_83_i)) + )) + (net N_85 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_0_a3_0_1)) + (portRef I0 (instanceRef N_85_i)) + )) + (net N_86 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_0_a3_2)) + (portRef I0 (instanceRef N_86_i)) + )) + (net N_88 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_0_a3_3)) + (portRef I0 (instanceRef N_88_i)) + )) + (net N_89 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_0_a3_4)) + (portRef I0 (instanceRef N_89_i)) + )) + (net N_90 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_0_a3_0_4)) + (portRef I0 (instanceRef N_90_i)) + )) + (net N_94 (joined + (portRef O (instanceRef SM_AMIGA_ns_0_a3_5)) + (portRef I0 (instanceRef N_94_i)) + )) + (net N_97 (joined + (portRef O (instanceRef SM_AMIGA_ns_0_a3_0_5)) + (portRef I0 (instanceRef N_97_i)) + )) + (net N_98 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_i_a3_6)) + (portRef I0 (instanceRef N_98_i)) + )) + (net N_114 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_i_a3_0_6)) + (portRef I0 (instanceRef N_114_i)) + )) + (net N_115 (joined + (portRef O (instanceRef SM_AMIGA_ns_0_a3_7)) + (portRef I0 (instanceRef N_115_i)) + )) + (net N_116 (joined + (portRef O (instanceRef SM_AMIGA_ns_0_a3_0_7)) + (portRef I0 (instanceRef N_116_i)) + )) + (net N_117 (joined + (portRef O (instanceRef clk_cpu_est_11_i_0_a3_2)) + (portRef I0 (instanceRef N_117_i)) + )) + (net N_118 (joined + (portRef O (instanceRef clk_cpu_est_11_i_0_a3_0_2)) + (portRef I0 (instanceRef N_118_i)) + )) + (net N_119 (joined + (portRef O (instanceRef state_machine_AMIGA_BUS_ENABLE_3_f0_i_a3)) + (portRef I0 (instanceRef N_119_i)) + )) + (net N_120 (joined + (portRef O (instanceRef un1_bg_030_i_a3)) + (portRef I0 (instanceRef N_120_i)) )) (net N_121 (joined - (portRef O (instanceRef clk_cpu_est_11_0_o4_i_1)) - (portRef I0 (instanceRef VMA_INT_0_m)) - (portRef I0 (instanceRef clk_cpu_est_11_0_a4_1)) + (portRef O (instanceRef clk_cpu_est_11_0_0_a3_1)) + (portRef I0 (instanceRef N_121_i)) )) - (net (rename state_machine_un13_clk_000_d0_2 "state_machine.un13_clk_000_d0_2") (joined - (portRef O (instanceRef state_machine_un13_clk_000_d0_2)) - (portRef I0 (instanceRef state_machine_un13_clk_000_d0_2_i)) - (portRef I1 (instanceRef clk_cpu_est_11_0_a4_2_1)) - (portRef I1 (instanceRef state_machine_un13_clk_000_d0_2_0)) - )) - (net N_131 (joined - (portRef O (instanceRef clk_cpu_est_11_0_a4_1_3)) - (portRef I0 (instanceRef N_131_i)) - )) - (net (rename clk_cpu_est_11_1 "clk.cpu_est_11[1]") (joined - (portRef O (instanceRef clk_cpu_est_11_0_i_1)) - (portRef I0 (instanceRef cpu_est_0_1__m)) - )) - (net N_126 (joined - (portRef O (instanceRef clk_cpu_est_11_0_a4_2_1)) - (portRef I0 (instanceRef N_126_i)) + (net N_122 (joined + (portRef O (instanceRef clk_cpu_est_11_0_0_a3_0_1)) + (portRef I0 (instanceRef N_122_i)) )) (net N_124 (joined - (portRef O (instanceRef clk_cpu_est_11_0_a4_0_1)) + (portRef O (instanceRef clk_cpu_est_11_0_0_a3_1_1)) (portRef I0 (instanceRef N_124_i)) )) - (net N_123 (joined - (portRef O (instanceRef clk_cpu_est_11_0_a4_1)) - (portRef I0 (instanceRef N_123_i)) - )) (net N_125 (joined - (portRef O (instanceRef clk_cpu_est_11_0_a4_1_1)) + (portRef O (instanceRef clk_cpu_est_11_0_0_a3_3)) (portRef I0 (instanceRef N_125_i)) )) - (net N_91 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_o3_i_4)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_a3_4)) + (net N_178 (joined + (portRef O (instanceRef clk_cpu_est_11_0_0_a3_0_3)) + (portRef I0 (instanceRef N_178_i)) )) - (net N_102 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_a3_4)) - (portRef I0 (instanceRef N_102_i)) + (net N_138 (joined + (portRef O (instanceRef clk_cpu_est_11_0_0_a3_1_3)) + (portRef I0 (instanceRef N_138_i)) )) - (net N_103 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_a3_0_4)) - (portRef I0 (instanceRef N_103_i)) + (net N_139 (joined + (portRef O (instanceRef SM_AMIGA_ns_0_a3_0)) + (portRef I0 (instanceRef N_139_i)) )) - (net N_101 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_a3_3)) - (portRef I0 (instanceRef N_101_i)) + (net N_140 (joined + (portRef O (instanceRef SM_AMIGA_ns_0_a3_0_0)) + (portRef I0 (instanceRef N_140_i)) + )) + (net N_141 (joined + (portRef O (instanceRef cpu_est_0_0_a3_0)) + (portRef I0 (instanceRef N_141_i)) + )) + (net N_142 (joined + (portRef O (instanceRef cpu_est_0_0_a3_0_0)) + (portRef I0 (instanceRef N_142_i)) + )) + (net N_145 (joined + (portRef O (instanceRef SM_AMIGA_ns_0_a2_0)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_a3_0)) + (portRef I0 (instanceRef N_145_i)) + )) + (net N_146 (joined + (portRef O (instanceRef clk_cpu_est_11_0_0_a2_1)) + (portRef I0 (instanceRef N_146_i)) + (portRef I1 (instanceRef state_machine_un15_clk_000_d0_0_a3_1)) + )) + (net N_77_1 (joined + (portRef O (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_2)) + (portRef I1 (instanceRef DTACK_SYNC_1_sqmuxa_1_i_a3_1)) + (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_1)) + )) + (net N_188 (joined + (portRef O (instanceRef un8_ciin)) + (portRef OE (instanceRef CIIN)) + )) + (net N_191 (joined + (portRef O (instanceRef un4_ciin)) + (portRef I0 (instanceRef CIIN)) )) (net RW_i (joined (portRef O (instanceRef RW_i)) - (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa)) (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR)) )) - (net AS_000_INT_i (joined - (portRef O (instanceRef AS_000_INT_i)) - (portRef I0 (instanceRef state_machine_un14_as_000_int)) - )) - (net (rename DSACK_i_1 "DSACK_i[1]") (joined - (portRef O (instanceRef I_109)) - (portRef I1 (instanceRef state_machine_un14_as_000_int)) - )) - (net (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (joined - (portRef O (instanceRef SM_AMIGA_i_4)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_a3_3)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_a3_0_4)) - )) - (net (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (joined - (portRef O (instanceRef SM_AMIGA_i_5)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_a3_3)) - )) - (net CLK_000_D0_i (joined - (portRef O (instanceRef CLK_000_D0_i)) - (portRef I0 (instanceRef SM_AMIGA_ns_a3_0_1)) - (portRef I0 (instanceRef SM_AMIGA_ns_a3_5)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_a3_6)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_a3_4)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_3)) - (portRef I0 (instanceRef un1_DSACK_INT_0_sqmuxa_i_a3_1)) - (portRef I0 (instanceRef SM_AMIGA_ns_a3_0_1_5)) - (portRef I0 (instanceRef state_machine_un8_clk_000_d0_2)) - )) - (net (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (joined - (portRef O (instanceRef SM_AMIGA_i_3)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_a3_0_4)) - )) - (net (rename cpu_est_i_0 "cpu_est_i[0]") (joined - (portRef O (instanceRef cpu_est_i_0)) - (portRef I1 (instanceRef clk_cpu_est_11_0_a4_1)) - (portRef I0 (instanceRef clk_cpu_est_11_0_a4_1_1_3)) - (portRef I1 (instanceRef clk_cpu_est_11_i_a4_0_1_2)) - (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_3)) - (portRef I0 (instanceRef state_machine_un13_clk_000_d0_1_0)) - )) - (net (rename cpu_est_i_3 "cpu_est_i[3]") (joined - (portRef O (instanceRef cpu_est_i_3)) - (portRef I1 (instanceRef clk_cpu_est_11_0_o4_1)) - (portRef I1 (instanceRef clk_cpu_est_11_0_a4_0_1)) - (portRef I1 (instanceRef clk_cpu_est_11_i_a4_1_2)) - (portRef I1 (instanceRef state_machine_un13_clk_000_d0_1_0)) - (portRef I1 (instanceRef state_machine_un8_clk_000_d0_1)) - )) - (net (rename cpu_est_i_2 "cpu_est_i[2]") (joined - (portRef O (instanceRef cpu_est_i_2)) - (portRef I1 (instanceRef clk_cpu_est_11_0_a4_0_3)) - (portRef I0 (instanceRef clk_cpu_est_11_0_a4_0_1)) - (portRef I1 (instanceRef clk_cpu_est_11_0_a4_1_3)) - (portRef I1 (instanceRef clk_cpu_est_11_i_a4_0_2)) - )) (net VPA_D_i (joined (portRef O (instanceRef VPA_D_i)) - (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_2)) - (portRef I1 (instanceRef state_machine_un8_clk_000_d0_2)) + (portRef I0 (instanceRef state_machine_un15_clk_000_d0_0_a3_2)) + (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_2_0)) )) - (net (rename cpu_est_i_1 "cpu_est_i[1]") (joined - (portRef O (instanceRef cpu_est_i_1)) - (portRef I0 (instanceRef clk_cpu_est_11_0_o4_1)) - (portRef I1 (instanceRef clk_cpu_est_11_0_a4_1_1_3)) - (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_4)) - (portRef I0 (instanceRef state_machine_un8_clk_000_d0_1)) + (net CLK_000_D0_i (joined + (portRef O (instanceRef CLK_000_D0_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_a3_5)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_0_a3_4)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_a3_0)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_0_3)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_0_o2_1)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_i_o2_6)) + (portRef I0 (instanceRef state_machine_un15_clk_000_d0_0_a3_1)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_a3_0_1_5)) )) - (net DTACK_i (joined - (portRef O (instanceRef I_110)) - (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa_1_0)) + (net (rename cpu_est_i_0 "cpu_est_i[0]") (joined + (portRef O (instanceRef cpu_est_i_0)) + (portRef I1 (instanceRef cpu_est_0_0_a3_0_0)) + (portRef I1 (instanceRef clk_cpu_est_11_0_0_a3_1)) + (portRef I0 (instanceRef state_machine_un15_clk_000_d0_0_a3_0_2)) + (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_3)) + (portRef I1 (instanceRef clk_cpu_est_11_i_0_a3_0_1_2)) + (portRef I0 (instanceRef clk_cpu_est_11_0_0_a3_1_1_3)) + )) + (net (rename cpu_est_i_3 "cpu_est_i[3]") (joined + (portRef O (instanceRef cpu_est_i_3)) + (portRef I1 (instanceRef clk_cpu_est_11_0_0_a3_0_1)) + (portRef I1 (instanceRef clk_cpu_est_11_0_0_o2_1)) + (portRef I1 (instanceRef state_machine_un15_clk_000_d0_0_a3_0_2)) + (portRef I1 (instanceRef clk_cpu_est_11_i_0_a3_2)) )) (net VMA_INT_i (joined (portRef O (instanceRef VMA_INT_i)) - (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_1_0)) + (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_1)) )) - (net (rename state_machine_un13_clk_000_d0_2_i "state_machine.un13_clk_000_d0_2_i") (joined - (portRef O (instanceRef state_machine_un13_clk_000_d0_2_i)) - (portRef I1 (instanceRef clk_cpu_est_11_i_a4_2)) + (net (rename cpu_est_i_1 "cpu_est_i[1]") (joined + (portRef O (instanceRef cpu_est_i_1)) + (portRef I0 (instanceRef clk_cpu_est_11_0_0_o2_1)) + (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_5)) + (portRef I1 (instanceRef clk_cpu_est_11_0_0_a3_1_1_3)) )) - (net CLK_000_D1_i (joined - (portRef O (instanceRef CLK_000_D1_i)) - (portRef I1 (instanceRef clk_un4_clk_000_d1)) + (net DTACK_i (joined + (portRef O (instanceRef I_114)) + (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa_1_i_a3_1)) )) - (net VPA_SYNC_1_sqmuxa_i (joined - (portRef O (instanceRef VPA_SYNC_1_sqmuxa_i)) - (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_1)) - (portRef I0 (instanceRef VPA_SYNC_0_n)) - )) - (net AS_030_i (joined - (portRef O (instanceRef AS_030_i)) - (portRef I0 (instanceRef DSACK_INT_1_sqmuxa)) - (portRef I0 (instanceRef un1_as_030_3)) - (portRef I0 (instanceRef un1_as_030_4)) - (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa_1)) - (portRef I0 (instanceRef state_machine_un17_clk_030)) - (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1)) - (portRef I0 (instanceRef AS_000_INT_1_sqmuxa)) - (portRef I0 (instanceRef state_machine_AS_030_000_SYNC_3_1)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_i_m_1)) - )) - (net N_95_i (joined - (portRef O (instanceRef N_95_i)) - (portRef I0 (instanceRef SM_AMIGA_ns_2)) - (portRef I1 (instanceRef AS_000_INT_1_sqmuxa)) - (portRef I0 (instanceRef AS_000_INT_0_n)) - )) - (net DTACK_SYNC_1_sqmuxa_i (joined - (portRef O (instanceRef DTACK_SYNC_1_sqmuxa_i)) - (portRef I1 (instanceRef DTACK_SYNC_1_sqmuxa_1)) - (portRef I0 (instanceRef DTACK_SYNC_0_n)) - )) - (net N_96_i (joined - (portRef O (instanceRef N_96_i)) - (portRef I0 (instanceRef SM_AMIGA_ns_7)) - (portRef I1 (instanceRef DSACK_INT_1_sqmuxa)) - (portRef I0 (instanceRef DSACK_INT_0_1__n)) - )) - (net (rename A_i_18 "A_i[18]") (joined - (portRef O (instanceRef A_i_18)) - (portRef I0 (instanceRef state_machine_un42_clk_030_2)) - )) - (net (rename A_i_16 "A_i[16]") (joined - (portRef O (instanceRef A_i_16)) - (portRef I1 (instanceRef state_machine_un42_clk_030_1)) - )) - (net (rename A_i_19 "A_i[19]") (joined - (portRef O (instanceRef A_i_19)) - (portRef I1 (instanceRef state_machine_un42_clk_030_2)) - )) - (net CLK_030_i (joined - (portRef O (instanceRef CLK_030_i)) - (portRef I1 (instanceRef state_machine_un17_clk_030)) - )) - (net (rename state_machine_un42_clk_030_i "state_machine.un42_clk_030_i") (joined - (portRef O (instanceRef state_machine_un42_clk_030_i)) - (portRef I1 (instanceRef state_machine_AS_030_000_SYNC_3)) - )) - (net (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (joined - (portRef O (instanceRef SM_AMIGA_i_6)) - (portRef I0 (instanceRef state_machine_un5_clk_030_i_a3)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_i_m)) - )) - (net (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (joined - (portRef O (instanceRef SM_AMIGA_i_7)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_a3_0)) - (portRef I1 (instanceRef state_machine_un5_clk_030_i_a3)) - )) - (net AMIGA_BUS_ENABLE_i (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_i)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_i_m_1)) + (net BG_030_i (joined + (portRef O (instanceRef BG_030_i)) + (portRef I0 (instanceRef state_machine_un1_clk_030_i_a3)) + (portRef I1 (instanceRef un1_bg_030_i_a3_1)) )) (net nEXP_SPACE_i (joined (portRef O (instanceRef nEXP_SPACE_i)) - (portRef I1 (instanceRef un1_bg_030_2)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_a2_0)) + (portRef I1 (instanceRef un1_bg_030_i_a3_2)) )) - (net (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (joined - (portRef O (instanceRef SM_AMIGA_i_2)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_a3_0_6)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_o3_6)) + (net (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (joined + (portRef O (instanceRef SM_AMIGA_i_3)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_0_a3_0_4)) )) - (net (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (joined - (portRef O (instanceRef SM_AMIGA_i_1)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_a3_0_6)) + (net AS_000_INT_i (joined + (portRef O (instanceRef AS_000_INT_i)) + (portRef I0 (instanceRef state_machine_un7_as_000_int_0_a3)) )) - (net DS_030_i (joined - (portRef O (instanceRef DS_030_i)) - (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa_1_1)) - (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa_1_0)) + (net (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (joined + (portRef O (instanceRef SM_AMIGA_i_6)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_0_a3_2)) + (portRef I1 (instanceRef state_machine_AMIGA_BUS_ENABLE_3_f0_i_a3)) )) - (net AS_030_000_SYNC_i (joined - (portRef O (instanceRef AS_030_000_SYNC_i)) - (portRef I0 (instanceRef SM_AMIGA_ns_o3_1)) - (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_1_1)) + (net (rename cpu_est_i_2 "cpu_est_i[2]") (joined + (portRef O (instanceRef cpu_est_i_2)) + (portRef I1 (instanceRef clk_cpu_est_11_0_0_a3_0_3)) + (portRef I0 (instanceRef clk_cpu_est_11_0_0_a3_0_1)) + (portRef I1 (instanceRef clk_cpu_est_11_i_0_a3_0_2)) + (portRef I1 (instanceRef clk_cpu_est_11_0_0_a3_1_3)) )) - (net UDS_000_INT_0_sqmuxa_1_i (joined - (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1_i)) - (portRef I0 (instanceRef un1_as_030_4_96)) + (net AMIGA_BUS_ENABLE_i (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_i)) + (portRef I0 (instanceRef state_machine_AMIGA_BUS_ENABLE_3_f0_i_a3_1)) )) - (net UDS_000_INT_0_sqmuxa_i (joined - (portRef O (instanceRef UDS_000_INT_0_sqmuxa_i)) - (portRef I1 (instanceRef un1_as_030_4_96)) + (net AS_030_i (joined + (portRef O (instanceRef AS_030_i)) + (portRef I0 (instanceRef AS_000_INT_1_sqmuxa_0_a3)) + (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1_i)) + (portRef I0 (instanceRef un1_as_030_3_i)) + (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa_1_i)) + (portRef I0 (instanceRef un1_as_030_000_sync8_i)) + (portRef I0 (instanceRef DSACK_INT_1_sqmuxa_i_o3)) + (portRef I1 (instanceRef state_machine_AMIGA_BUS_ENABLE_3_f0_i_a3_1)) )) - (net (rename state_machine_un13_clk_000_d0_1_i "state_machine.un13_clk_000_d0_1_i") (joined - (portRef O (instanceRef state_machine_un13_clk_000_d0_1_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_a3_7)) + (net (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (joined + (portRef O (instanceRef SM_AMIGA_i_4)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_0_a3_0_4)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_0_a3_3)) + )) + (net (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (joined + (portRef O (instanceRef SM_AMIGA_i_5)) + (portRef I0 (instanceRef AS_000_INT_0_n)) + (portRef I1 (instanceRef AS_000_INT_1_sqmuxa_0_a3)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_0_a3_3)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_0_a3_2)) + )) + (net (rename state_machine_un8_clk_000_d2_i "state_machine.un8_clk_000_d2_i") (joined + (portRef O (instanceRef state_machine_un8_clk_000_d2_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_0_a3_0_1)) + )) + (net (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (joined + (portRef O (instanceRef SM_AMIGA_i_7)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_0_a3_1)) + )) + (net (rename A_i_0 "A_i[0]") (joined + (portRef O (instanceRef A_i_0)) + (portRef I0 (instanceRef state_machine_UDS_000_INT_5_0)) + (portRef I0 (instanceRef state_machine_LDS_000_INT_5_0_a3_1)) + )) + (net (rename SIZE_i_1 "SIZE_i[1]") (joined + (portRef O (instanceRef SIZE_i_1)) + (portRef I1 (instanceRef state_machine_LDS_000_INT_5_0_a3)) + )) + (net (rename DSACK_i_1 "DSACK_i[1]") (joined + (portRef O (instanceRef I_115)) + (portRef I1 (instanceRef state_machine_un7_as_000_int_0_a3)) )) (net (rename clk_clk_cnt_i "clk.clk_cnt_i") (joined (portRef O (instanceRef clk_clk_cnt_i)) - (portRef I0 (instanceRef clk_CLK_CNT_3_1)) (portRef I1 (instanceRef clk_CLK_CNT_3_0)) + (portRef I0 (instanceRef clk_CLK_CNT_3_1)) )) (net (rename CLK_CNT_i_0 "CLK_CNT_i[0]") (joined (portRef O (instanceRef CLK_CNT_i_0)) + (portRef I0 (instanceRef G_93)) (portRef I0 (instanceRef clk_CLK_CNT_3_0)) )) (net CLK_000_D2_i (joined (portRef O (instanceRef CLK_000_D2_i)) - (portRef I1 (instanceRef state_machine_un30_clk_000_d1)) + (portRef I1 (instanceRef state_machine_un8_clk_000_d2)) + )) + (net AS_030_000_SYNC_i (joined + (portRef O (instanceRef AS_030_000_SYNC_i)) + (portRef I1 (instanceRef state_machine_un8_clk_000_d2_1)) )) (net (rename A_i_30 "A_i[30]") (joined (portRef O (instanceRef A_i_30)) @@ -1482,22 +1433,29 @@ (portRef O (instanceRef A_i_25)) (portRef I1 (instanceRef un8_ciin_1)) )) - (net N_132_i (joined - (portRef O (instanceRef N_132_i)) - (portRef I0 (instanceRef G_88)) + (net (rename A_i_19 "A_i[19]") (joined + (portRef O (instanceRef A_i_19)) + (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_3)) )) - (net N_133_i (joined - (portRef O (instanceRef N_133_i)) - (portRef I1 (instanceRef G_88)) + (net (rename A_i_16 "A_i[16]") (joined + (portRef O (instanceRef A_i_16)) + (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_3)) )) - (net (rename state_machine_un14_as_000_int_i "state_machine.un14_as_000_int_i") (joined - (portRef O (instanceRef state_machine_un14_as_000_int_i)) + (net (rename A_i_18 "A_i[18]") (joined + (portRef O (instanceRef A_i_18)) + (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_5)) + )) + (net N_137_i (joined + (portRef O (instanceRef N_137_i)) + (portRef I1 (instanceRef G_93)) + )) + (net (rename state_machine_un7_as_000_int_i "state_machine.un7_as_000_int_i") (joined + (portRef O (instanceRef state_machine_un7_as_000_int_i)) (portRef D (instanceRef DTACK_DMA)) )) (net RST_i (joined (portRef O (instanceRef RST_i)) (portRef R (instanceRef CLK_REF_1)) - (portRef S (instanceRef CLK_REF_0)) (portRef S (instanceRef AS_000_INT)) (portRef S (instanceRef AS_030_000_SYNC)) (portRef S (instanceRef BGACK_030_INT)) @@ -1522,6 +1480,25 @@ (portRef S (instanceRef VMA_INT)) (portRef S (instanceRef VPA_SYNC)) )) + (net N_120_i (joined + (portRef O (instanceRef N_120_i)) + (portRef I0 (instanceRef BG_000_0_n)) + )) + (net N_75_i (joined + (portRef O (instanceRef N_75_i)) + (portRef I0 (instanceRef VPA_SYNC_0_m)) + (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_1_i)) + )) + (net N_74_i (joined + (portRef O (instanceRef N_74_i)) + (portRef I0 (instanceRef DSACK_INT_0_1__m)) + (portRef I1 (instanceRef DSACK_INT_1_sqmuxa_i_o3)) + )) + (net N_77_i (joined + (portRef O (instanceRef N_77_i)) + (portRef I0 (instanceRef DTACK_SYNC_0_m)) + (portRef I1 (instanceRef DTACK_SYNC_1_sqmuxa_1_i)) + )) (net FPU_CS_INT_i (joined (portRef O (instanceRef FPU_CS_INT_i)) (portRef OE (instanceRef AVEC_EXP)) @@ -1531,10 +1508,15 @@ (portRef O (instanceRef BGACK_030_INT_i)) (portRef OE (instanceRef DTACK)) )) + (net CLK_000_D5_i (joined + (portRef O (instanceRef CLK_000_D5_i)) + (portRef I1 (instanceRef state_machine_un6_clk_000_d4)) + )) (net AS_030_c (joined (portRef O (instanceRef AS_030)) + (portRef I0 (instanceRef FPU_CS_INT_0_m)) (portRef I0 (instanceRef AS_030_i)) - (portRef I0 (instanceRef un1_bg_030_2)) + (portRef I0 (instanceRef un1_bg_030_i_a3_1)) )) (net AS_030 (joined (portRef AS_030) @@ -1546,7 +1528,7 @@ )) (net DS_030_c (joined (portRef O (instanceRef DS_030)) - (portRef I0 (instanceRef DS_030_i)) + (portRef I0 (instanceRef DS_030_c_i)) )) (net DS_030 (joined (portRef DS_030) @@ -1562,7 +1544,7 @@ )) (net (rename SIZE_c_0 "SIZE_c[0]") (joined (portRef O (instanceRef SIZE_0)) - (portRef I0 (instanceRef state_machine_un44_clk_000_d1_1)) + (portRef I1 (instanceRef state_machine_LDS_000_INT_5_0_a3_1)) )) (net (rename SIZE_0 "SIZE[0]") (joined (portRef (member size 1)) @@ -1570,7 +1552,7 @@ )) (net (rename SIZE_c_1 "SIZE_c[1]") (joined (portRef O (instanceRef SIZE_1)) - (portRef I0 (instanceRef SIZE_c_i_1)) + (portRef I0 (instanceRef SIZE_i_1)) )) (net (rename SIZE_1 "SIZE[1]") (joined (portRef (member size 0)) @@ -1578,7 +1560,7 @@ )) (net (rename A_c_0 "A_c[0]") (joined (portRef O (instanceRef A_0)) - (portRef I0 (instanceRef A_c_i_0)) + (portRef I0 (instanceRef A_i_0)) )) (net (rename A_0 "A[0]") (joined (portRef (member a 31)) @@ -1639,7 +1621,7 @@ )) (net (rename A_c_17 "A_c[17]") (joined (portRef O (instanceRef A_17)) - (portRef I0 (instanceRef state_machine_un42_clk_030_1)) + (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_1)) )) (net (rename A_17 "A[17]") (joined (portRef (member a 14)) @@ -1759,9 +1741,9 @@ )) (net nEXP_SPACE_c (joined (portRef O (instanceRef nEXP_SPACE)) - (portRef I1 (instanceRef nEXP_SPACE_m)) + (portRef I1 (instanceRef state_machine_AMIGA_BUS_ENABLE_3_f0_i_o2)) (portRef I0 (instanceRef nEXP_SPACE_i)) - (portRef I1 (instanceRef state_machine_AS_030_000_SYNC_3_1)) + (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a3_2)) (portRef OE (instanceRef DSACK_0)) (portRef OE (instanceRef DSACK_1)) )) @@ -1775,7 +1757,7 @@ )) (net BG_030_c (joined (portRef O (instanceRef BG_030)) - (portRef I0 (instanceRef BG_030_c_i)) + (portRef I0 (instanceRef BG_030_i)) )) (net BG_030 (joined (portRef BG_030) @@ -1783,7 +1765,7 @@ )) (net BG_000_c (joined (portRef Q (instanceRef BG_000DFFSH)) - (portRef I0 (instanceRef BG_000_0_n)) + (portRef I0 (instanceRef BG_000_0_m)) (portRef I0 (instanceRef BG_000)) )) (net BG_000 (joined @@ -1796,9 +1778,9 @@ )) (net BGACK_000_c (joined (portRef O (instanceRef BGACK_000)) - (portRef I0 (instanceRef state_machine_un6_bgack_000)) (portRef I0 (instanceRef BGACK_030_INT_0_m)) - (portRef I1 (instanceRef state_machine_un42_clk_030_3)) + (portRef I0 (instanceRef state_machine_un6_bgack_000_0)) + (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_1)) )) (net BGACK_000 (joined (portRef BGACK_000) @@ -1806,8 +1788,9 @@ )) (net CLK_030_c (joined (portRef O (instanceRef CLK_030)) - (portRef I1 (instanceRef state_machine_un1_clk_030)) - (portRef I0 (instanceRef CLK_030_i)) + (portRef I0 (instanceRef un1_as_030_000_sync8_i_a3)) + (portRef I1 (instanceRef state_machine_un1_clk_030_i_a3)) + (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a3_1)) )) (net CLK_030 (joined (portRef CLK_030) @@ -1815,7 +1798,6 @@ )) (net CLK_000_c (joined (portRef O (instanceRef CLK_000)) - (portRef I1 (instanceRef state_machine_un2_clk_000)) (portRef D (instanceRef CLK_000_D0)) )) (net CLK_000 (joined @@ -1832,6 +1814,9 @@ (portRef CLK (instanceRef CLK_000_D0)) (portRef CLK (instanceRef CLK_000_D1)) (portRef CLK (instanceRef CLK_000_D2)) + (portRef CLK (instanceRef CLK_000_D3)) + (portRef CLK (instanceRef CLK_000_D4)) + (portRef CLK (instanceRef CLK_000_D5)) (portRef CLK (instanceRef CLK_CNT_0)) (portRef CLK (instanceRef CLK_CNT_1)) (portRef CLK (instanceRef CLK_OUT_INT)) @@ -1885,7 +1870,7 @@ )) (net (rename IPL_030_c_0 "IPL_030_c[0]") (joined (portRef Q (instanceRef IPL_030DFFSH_0)) - (portRef I0 (instanceRef IPL_030_0_0__n)) + (portRef I0 (instanceRef IPL_030_0_0__m)) (portRef I0 (instanceRef IPL_030_0)) )) (net (rename IPL_030_0 "IPL_030[0]") (joined @@ -1894,7 +1879,7 @@ )) (net (rename IPL_030_c_1 "IPL_030_c[1]") (joined (portRef Q (instanceRef IPL_030DFFSH_1)) - (portRef I0 (instanceRef IPL_030_0_1__n)) + (portRef I0 (instanceRef IPL_030_0_1__m)) (portRef I0 (instanceRef IPL_030_1)) )) (net (rename IPL_030_1 "IPL_030[1]") (joined @@ -1903,7 +1888,7 @@ )) (net (rename IPL_030_c_2 "IPL_030_c[2]") (joined (portRef Q (instanceRef IPL_030DFFSH_2)) - (portRef I0 (instanceRef IPL_030_0_2__n)) + (portRef I0 (instanceRef IPL_030_0_2__m)) (portRef I0 (instanceRef IPL_030_2)) )) (net (rename IPL_030_2 "IPL_030[2]") (joined @@ -1912,7 +1897,7 @@ )) (net (rename IPL_c_0 "IPL_c[0]") (joined (portRef O (instanceRef IPL_0)) - (portRef I0 (instanceRef IPL_030_0_0__m)) + (portRef I0 (instanceRef IPL_030_0_0__n)) )) (net (rename IPL_0 "IPL[0]") (joined (portRef (member ipl 2)) @@ -1920,7 +1905,7 @@ )) (net (rename IPL_c_1 "IPL_c[1]") (joined (portRef O (instanceRef IPL_1)) - (portRef I0 (instanceRef IPL_030_0_1__m)) + (portRef I0 (instanceRef IPL_030_0_1__n)) )) (net (rename IPL_1 "IPL[1]") (joined (portRef (member ipl 1)) @@ -1928,7 +1913,7 @@ )) (net (rename IPL_c_2 "IPL_c[2]") (joined (portRef O (instanceRef IPL_2)) - (portRef I0 (instanceRef IPL_030_0_2__m)) + (portRef I0 (instanceRef IPL_030_0_2__n)) )) (net (rename IPL_2 "IPL[2]") (joined (portRef (member ipl 0)) @@ -1940,7 +1925,7 @@ )) (net (rename DSACK_c_1 "DSACK_c[1]") (joined (portRef O (instanceRef DSACK_1)) - (portRef I0 (instanceRef I_109)) + (portRef I0 (instanceRef I_115)) )) (net (rename DSACK_1 "DSACK[1]") (joined (portRef (member dsack 0)) @@ -1948,7 +1933,7 @@ )) (net DTACK_c (joined (portRef O (instanceRef DTACK)) - (portRef I0 (instanceRef I_110)) + (portRef I0 (instanceRef I_114)) )) (net DTACK (joined (portRef IO (instanceRef DTACK)) @@ -1980,9 +1965,9 @@ )) (net RST_c (joined (portRef O (instanceRef RST)) - (portRef I0 (instanceRef RST_i)) (portRef I1 (instanceRef AMIGA_BUS_ENABLE_0_m)) (portRef I0 (instanceRef AMIGA_BUS_ENABLE_0_r)) + (portRef I0 (instanceRef RST_i)) (portRef D (instanceRef RESETDFF)) )) (net RST (joined @@ -1999,8 +1984,9 @@ )) (net RW_c (joined (portRef O (instanceRef RW)) + (portRef I1 (instanceRef state_machine_UDS_000_INT_5_0_m2_m)) + (portRef I0 (instanceRef state_machine_UDS_000_INT_5_0_m2_r)) (portRef I0 (instanceRef RW_i)) - (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_1_2)) )) (net RW (joined (portRef RW) @@ -2008,7 +1994,7 @@ )) (net (rename FC_c_0 "FC_c[0]") (joined (portRef O (instanceRef FC_0)) - (portRef I1 (instanceRef state_machine_un42_clk_030_5)) + (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_2)) )) (net (rename FC_0 "FC[0]") (joined (portRef (member fc 1)) @@ -2016,7 +2002,7 @@ )) (net (rename FC_c_1 "FC_c[1]") (joined (portRef O (instanceRef FC_1)) - (portRef I0 (instanceRef state_machine_un42_clk_030_3)) + (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_2)) )) (net (rename FC_1 "FC[1]") (joined (portRef (member fc 0)) @@ -2024,8 +2010,8 @@ )) (net AMIGA_BUS_ENABLE_c (joined (portRef Q (instanceRef AMIGA_BUS_ENABLEDFF)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_i)) (portRef I0 (instanceRef AMIGA_BUS_ENABLE_0_n)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_i)) (portRef I0 (instanceRef AMIGA_BUS_ENABLE)) )) (net AMIGA_BUS_ENABLE (joined @@ -2044,432 +2030,565 @@ (portRef O (instanceRef CIIN)) (portRef CIIN) )) - (net N_101_i (joined - (portRef O (instanceRef N_101_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_3)) - )) - (net N_82_i (joined - (portRef O (instanceRef SM_AMIGA_ns_i_3)) - (portRef D (instanceRef SM_AMIGA_4)) - )) - (net N_102_i (joined - (portRef O (instanceRef N_102_i)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_4)) - )) - (net N_103_i (joined - (portRef O (instanceRef N_103_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_4)) - )) - (net N_84_i (joined - (portRef O (instanceRef SM_AMIGA_ns_i_4)) - (portRef D (instanceRef SM_AMIGA_3)) - )) - (net N_91_0 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_o3_4)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_o3_i_4)) - )) - (net N_125_i (joined - (portRef O (instanceRef N_125_i)) - (portRef I1 (instanceRef clk_cpu_est_11_0_2_1)) - )) - (net N_123_i (joined - (portRef O (instanceRef N_123_i)) - (portRef I0 (instanceRef clk_cpu_est_11_0_2_1)) + (net (rename clk_cpu_est_11_0_1 "clk.cpu_est_11_0[1]") (joined + (portRef O (instanceRef clk_cpu_est_11_0_0_1)) + (portRef I0 (instanceRef clk_cpu_est_11_0_0_i_1)) )) (net N_124_i (joined (portRef O (instanceRef N_124_i)) - (portRef I1 (instanceRef clk_cpu_est_11_0_1_1)) + (portRef I0 (instanceRef clk_cpu_est_11_0_0_2_1)) )) - (net N_126_i (joined - (portRef O (instanceRef N_126_i)) - (portRef I0 (instanceRef clk_cpu_est_11_0_1_1)) - )) - (net (rename clk_cpu_est_11_0_1 "clk.cpu_est_11_0[1]") (joined - (portRef O (instanceRef clk_cpu_est_11_0_1)) - (portRef I0 (instanceRef clk_cpu_est_11_0_i_1)) - )) - (net N_131_i (joined - (portRef O (instanceRef N_131_i)) - (portRef I0 (instanceRef clk_cpu_est_11_0_1_3)) - )) - (net (rename clk_cpu_est_11_0_3 "clk.cpu_est_11_0[3]") (joined - (portRef O (instanceRef clk_cpu_est_11_0_3)) - (portRef I0 (instanceRef clk_cpu_est_11_0_i_3)) - )) - (net N_130_i (joined - (portRef O (instanceRef N_130_i)) - (portRef I1 (instanceRef clk_cpu_est_11_0_3)) - )) - (net N_129_i (joined - (portRef O (instanceRef N_129_i)) - (portRef I1 (instanceRef clk_cpu_est_11_0_1_3)) - )) - (net N_122_i (joined - (portRef O (instanceRef clk_cpu_est_11_0_o4_3)) - (portRef I0 (instanceRef clk_cpu_est_11_0_a4_0_3)) - (portRef I0 (instanceRef clk_cpu_est_11_0_o4_i_3)) + (net N_146_i (joined + (portRef O (instanceRef N_146_i)) + (portRef I1 (instanceRef clk_cpu_est_11_0_0_2_1)) )) (net N_121_i (joined - (portRef O (instanceRef clk_cpu_est_11_0_o4_1)) - (portRef I0 (instanceRef clk_cpu_est_11_0_a4_1_1)) - (portRef I0 (instanceRef clk_cpu_est_11_0_o4_i_1)) + (portRef O (instanceRef N_121_i)) + (portRef I0 (instanceRef clk_cpu_est_11_0_0_1_1)) )) - (net N_127_i (joined - (portRef O (instanceRef N_127_i)) - (portRef I0 (instanceRef clk_cpu_est_11_i_2)) + (net N_122_i (joined + (portRef O (instanceRef N_122_i)) + (portRef I1 (instanceRef clk_cpu_est_11_0_0_1_1)) )) - (net N_128_i (joined - (portRef O (instanceRef N_128_i)) - (portRef I1 (instanceRef clk_cpu_est_11_i_2)) + (net N_66_0 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_0_o2_4)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_0_o2_i_4)) )) - (net N_118_i (joined - (portRef O (instanceRef clk_cpu_est_11_i_2)) - (portRef I0 (instanceRef cpu_est_0_2__m)) + (net N_65_0 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_0_o2_1)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_0_o2_i_1)) )) - (net (rename state_machine_un8_clk_000_d0_i "state_machine.un8_clk_000_d0_i") (joined - (portRef O (instanceRef state_machine_un8_clk_000_d0_i)) - (portRef I0 (instanceRef state_machine_un15_clk_000_d0)) + (net N_145_i (joined + (portRef O (instanceRef N_145_i)) + (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0_o3)) )) - (net (rename state_machine_un13_clk_000_d0_i "state_machine.un13_clk_000_d0_i") (joined - (portRef O (instanceRef state_machine_un13_clk_000_d0_i)) - (portRef I1 (instanceRef state_machine_un15_clk_000_d0)) + (net un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 (joined + (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0_o3)) + (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_i)) + (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0_o3_i)) )) - (net (rename state_machine_un15_clk_000_d0_0 "state_machine.un15_clk_000_d0_0") (joined - (portRef O (instanceRef state_machine_un15_clk_000_d0)) - (portRef I0 (instanceRef state_machine_un15_clk_000_d0_i)) + (net DS_030_c_i (joined + (portRef O (instanceRef DS_030_c_i)) + (portRef I0 (instanceRef state_machine_UDS_000_INT_5_0_o3)) )) - (net N_100_i (joined - (portRef O (instanceRef N_100_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_2)) + (net N_63_i (joined + (portRef O (instanceRef state_machine_UDS_000_INT_5_0_o3)) + (portRef I0 (instanceRef state_machine_LDS_000_INT_5_0)) + (portRef I1 (instanceRef state_machine_UDS_000_INT_5_0)) + (portRef I0 (instanceRef state_machine_UDS_000_INT_5_0_o3_i)) )) - (net (rename SM_AMIGA_ns_0_2 "SM_AMIGA_ns_0[2]") (joined - (portRef O (instanceRef SM_AMIGA_ns_2)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_2)) + (net N_62_i (joined + (portRef O (instanceRef clk_cpu_est_11_0_0_o2_3)) + (portRef I0 (instanceRef clk_cpu_est_11_0_0_a3_0_3)) + (portRef I0 (instanceRef clk_cpu_est_11_0_0_o2_i_3)) )) - (net (rename clk_un4_clk_000_d1_i "clk.un4_clk_000_d1_i") (joined - (portRef O (instanceRef clk_un4_clk_000_d1_i)) - (portRef I1 (instanceRef state_machine_un6_bgack_000)) + (net (rename state_machine_un6_clk_000_d4_i "state_machine.un6_clk_000_d4_i") (joined + (portRef O (instanceRef state_machine_un6_clk_000_d4_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_i_o2_6)) )) - (net (rename state_machine_un6_bgack_000_0 "state_machine.un6_bgack_000_0") (joined - (portRef O (instanceRef state_machine_un6_bgack_000)) - (portRef I0 (instanceRef state_machine_un6_bgack_000_i)) + (net N_61_i (joined + (portRef O (instanceRef SM_AMIGA_ns_i_i_o2_6)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_a3_0_7)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_i_o2_i_6)) )) - (net (rename state_machine_un23_clk_000_d0_i "state_machine.un23_clk_000_d0_i") (joined - (portRef O (instanceRef state_machine_un23_clk_000_d0)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_o3_4)) - (portRef I0 (instanceRef state_machine_un23_clk_000_d0_i_0)) + (net N_60_i (joined + (portRef O (instanceRef clk_cpu_est_11_0_0_o2_1)) + (portRef I0 (instanceRef clk_cpu_est_11_0_0_a2_1)) + (portRef I0 (instanceRef clk_cpu_est_11_0_0_o2_i_1)) )) - (net BG_030_c_i (joined - (portRef O (instanceRef BG_030_c_i)) - (portRef I0 (instanceRef state_machine_un1_clk_030)) - (portRef I0 (instanceRef un1_bg_030_1)) + (net N_59_i (joined + (portRef O (instanceRef SM_AMIGA_ns_0_o2_7)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_a3_0_0)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_o2_i_7)) + (portRef I1 (instanceRef state_machine_un15_clk_000_d0_0_a3_0_1)) )) - (net (rename state_machine_un1_clk_030_0 "state_machine.un1_clk_030_0") (joined - (portRef O (instanceRef state_machine_un1_clk_030)) - (portRef I0 (instanceRef state_machine_un1_clk_030_i)) + (net N_58_i (joined + (portRef O (instanceRef state_machine_AMIGA_BUS_ENABLE_3_f0_i_o2)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_0_o2_1)) + (portRef I0 (instanceRef state_machine_AMIGA_BUS_ENABLE_3_f0_i_o2_i)) )) - (net (rename state_machine_un17_clk_030_0 "state_machine.un17_clk_030_0") (joined - (portRef O (instanceRef state_machine_un17_clk_030)) - (portRef I0 (instanceRef state_machine_un17_clk_030_i)) + (net N_57_i (joined + (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2)) + (portRef I1 (instanceRef un1_as_030_000_sync8_i_a3)) + (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_i)) )) - (net un1_as_030_3_0 (joined - (portRef O (instanceRef un1_as_030_3)) - (portRef I0 (instanceRef un1_as_030_3_i)) + (net CLK_000_D1_i (joined + (portRef O (instanceRef CLK_000_D1_i)) + (portRef I1 (instanceRef clk_un4_clk_000_d1_0_o2)) )) - (net N_148_i (joined - (portRef O (instanceRef N_148_i)) - (portRef I1 (instanceRef state_machine_UDS_000_INT_7)) - (portRef I0 (instanceRef state_machine_LDS_000_INT_7)) + (net N_56_i (joined + (portRef O (instanceRef clk_un4_clk_000_d1_0_o2)) + (portRef I0 (instanceRef cpu_est_0_0_a3_0_0)) + (portRef I0 (instanceRef clk_un4_clk_000_d1_0_o2_i)) )) - (net (rename A_c_i_0 "A_c_i[0]") (joined - (portRef O (instanceRef A_c_i_0)) - (portRef I0 (instanceRef state_machine_UDS_000_INT_7)) - (portRef I1 (instanceRef state_machine_un44_clk_000_d1_1)) + (net N_55_i (joined + (portRef O (instanceRef clk_cpu_est_11_i_0_o2_2)) + (portRef I0 (instanceRef clk_cpu_est_11_0_0_a3_1_1)) + (portRef I0 (instanceRef clk_cpu_est_11_i_0_o2_i_2)) + (portRef I0 (instanceRef state_machine_un15_clk_000_d0_0_a3_0_1)) )) - (net (rename state_machine_UDS_000_INT_7_0 "state_machine.UDS_000_INT_7_0") (joined - (portRef O (instanceRef state_machine_UDS_000_INT_7)) - (portRef I0 (instanceRef state_machine_UDS_000_INT_7_i)) + (net N_52_i (joined + (portRef O (instanceRef DSACK_INT_1_sqmuxa_i_o3)) + (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0_o3)) + (portRef I0 (instanceRef DSACK_INT_1_sqmuxa_i_o3_i)) )) - (net (rename state_machine_LDS_000_INT_7_0 "state_machine.LDS_000_INT_7_0") (joined - (portRef O (instanceRef state_machine_LDS_000_INT_7)) - (portRef I0 (instanceRef state_machine_LDS_000_INT_7_i)) + (net N_141_i (joined + (portRef O (instanceRef N_141_i)) + (portRef I0 (instanceRef cpu_est_0_0_0)) )) - (net AMIGA_BUS_ENABLE_i_m_i (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_i_m_i)) - (portRef I0 (instanceRef state_machine_AMIGA_BUS_ENABLE_2_iv)) + (net N_142_i (joined + (portRef O (instanceRef N_142_i)) + (portRef I1 (instanceRef cpu_est_0_0_0)) )) - (net nEXP_SPACE_m_i (joined - (portRef O (instanceRef nEXP_SPACE_m_i)) - (portRef I1 (instanceRef state_machine_AMIGA_BUS_ENABLE_2_iv)) + (net N_14_0 (joined + (portRef O (instanceRef cpu_est_0_0_0)) + (portRef I0 (instanceRef cpu_est_0_0_i_0)) )) - (net (rename state_machine_AMIGA_BUS_ENABLE_2_iv_i "state_machine.AMIGA_BUS_ENABLE_2_iv_i") (joined - (portRef O (instanceRef state_machine_AMIGA_BUS_ENABLE_2_iv)) + (net N_85_i (joined + (portRef O (instanceRef N_85_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_0_1)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_1_0)) + )) + (net N_139_i (joined + (portRef O (instanceRef N_139_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_0)) + )) + (net N_140_i (joined + (portRef O (instanceRef N_140_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_1_0)) + )) + (net (rename SM_AMIGA_ns_0_0 "SM_AMIGA_ns_0[0]") (joined + (portRef O (instanceRef SM_AMIGA_ns_0_0)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_i_0)) + )) + (net N_125_i (joined + (portRef O (instanceRef N_125_i)) + (portRef I1 (instanceRef clk_cpu_est_11_0_0_1_3)) + )) + (net N_138_i (joined + (portRef O (instanceRef N_138_i)) + (portRef I1 (instanceRef clk_cpu_est_11_0_0_3)) + )) + (net N_178_i (joined + (portRef O (instanceRef N_178_i)) + (portRef I0 (instanceRef clk_cpu_est_11_0_0_1_3)) + )) + (net (rename clk_cpu_est_11_0_3 "clk.cpu_est_11_0[3]") (joined + (portRef O (instanceRef clk_cpu_est_11_0_0_3)) + (portRef I0 (instanceRef clk_cpu_est_11_0_0_i_3)) + )) + (net N_119_i (joined + (portRef O (instanceRef N_119_i)) + (portRef I1 (instanceRef state_machine_AMIGA_BUS_ENABLE_3_f0_i)) + )) + (net N_43_i (joined + (portRef O (instanceRef state_machine_AMIGA_BUS_ENABLE_3_f0_i)) (portRef I0 (instanceRef AMIGA_BUS_ENABLE_0_m)) )) - (net (rename state_machine_AS_030_000_SYNC_3_2 "state_machine.AS_030_000_SYNC_3_2") (joined - (portRef O (instanceRef state_machine_AS_030_000_SYNC_3)) - (portRef I0 (instanceRef state_machine_AS_030_000_SYNC_3_i)) + (net N_117_i (joined + (portRef O (instanceRef N_117_i)) + (portRef I0 (instanceRef clk_cpu_est_11_i_0_2)) )) - (net N_94_i (joined - (portRef O (instanceRef N_94_i)) - (portRef I1 (instanceRef un1_bg_030_1)) + (net N_118_i (joined + (portRef O (instanceRef N_118_i)) + (portRef I1 (instanceRef clk_cpu_est_11_i_0_2)) )) - (net un1_bg_030_0 (joined - (portRef O (instanceRef un1_bg_030)) - (portRef I0 (instanceRef un1_bg_030_i)) + (net N_123_i (joined + (portRef O (instanceRef clk_cpu_est_11_i_0_2)) + (portRef I0 (instanceRef cpu_est_0_2__n)) )) - (net (rename SIZE_c_i_1 "SIZE_c_i[1]") (joined - (portRef O (instanceRef SIZE_c_i_1)) - (portRef I1 (instanceRef state_machine_un44_clk_000_d1)) + (net N_115_i (joined + (portRef O (instanceRef N_115_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_7)) )) - (net (rename state_machine_un44_clk_000_d1_i "state_machine.un44_clk_000_d1_i") (joined - (portRef O (instanceRef state_machine_un44_clk_000_d1)) - (portRef I0 (instanceRef state_machine_un44_clk_000_d1_i_0)) - )) - (net N_105_i (joined - (portRef O (instanceRef N_105_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_5)) - )) - (net N_104_i (joined - (portRef O (instanceRef N_104_i)) - (portRef I0 (instanceRef SM_AMIGA_ns_5)) - )) - (net (rename SM_AMIGA_ns_0_5 "SM_AMIGA_ns_0[5]") (joined - (portRef O (instanceRef SM_AMIGA_ns_5)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_5)) - )) - (net N_106_i (joined - (portRef O (instanceRef N_106_i)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_6)) - )) - (net N_107_i (joined - (portRef O (instanceRef N_107_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_6)) - )) - (net N_87_i (joined - (portRef O (instanceRef SM_AMIGA_ns_i_6)) - (portRef D (instanceRef SM_AMIGA_1)) - )) - (net CLK_OUT_PRE_i (joined - (portRef O (instanceRef CLK_OUT_PRE_i)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_o3_6)) - )) - (net N_92_0 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_o3_6)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_o3_i_6)) - )) - (net N_90_0 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_o3_0)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_o3_i_0)) - )) - (net N_89_i (joined - (portRef O (instanceRef SM_AMIGA_ns_o3_1)) - (portRef I0 (instanceRef un1_SM_AMIGA_0_sqmuxa_i_a3)) - (portRef I0 (instanceRef SM_AMIGA_ns_o3_i_1)) - )) - (net N_108_i (joined - (portRef O (instanceRef N_108_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_7)) + (net N_116_i (joined + (portRef O (instanceRef N_116_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_7)) )) (net (rename SM_AMIGA_ns_0_7 "SM_AMIGA_ns_0[7]") (joined - (portRef O (instanceRef SM_AMIGA_ns_7)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_7)) + (portRef O (instanceRef SM_AMIGA_ns_0_7)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_i_7)) )) (net N_98_i (joined (portRef O (instanceRef N_98_i)) - (portRef I0 (instanceRef SM_AMIGA_ns_1)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_i_6)) )) - (net N_99_i (joined - (portRef O (instanceRef N_99_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_1)) + (net N_114_i (joined + (portRef O (instanceRef N_114_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_i_6)) )) - (net (rename SM_AMIGA_ns_0_1 "SM_AMIGA_ns_0[1]") (joined - (portRef O (instanceRef SM_AMIGA_ns_1)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_1)) + (net N_39_0 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_i_6)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_i_i_6)) + )) + (net N_94_i (joined + (portRef O (instanceRef N_94_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_5)) )) (net N_97_i (joined (portRef O (instanceRef N_97_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_0)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_5)) + )) + (net (rename SM_AMIGA_ns_0_5 "SM_AMIGA_ns_0[5]") (joined + (portRef O (instanceRef SM_AMIGA_ns_0_5)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_i_5)) + )) + (net N_89_i (joined + (portRef O (instanceRef N_89_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_0_4)) + )) + (net N_90_i (joined + (portRef O (instanceRef N_90_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_0_4)) + )) + (net N_84_i (joined + (portRef O (instanceRef SM_AMIGA_ns_i_0_4)) + (portRef D (instanceRef SM_AMIGA_3)) + )) + (net N_88_i (joined + (portRef O (instanceRef N_88_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_0_3)) + )) + (net N_82_i (joined + (portRef O (instanceRef SM_AMIGA_ns_i_0_3)) + (portRef D (instanceRef SM_AMIGA_4)) + )) + (net N_86_i (joined + (portRef O (instanceRef N_86_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_0_2)) + )) + (net N_80_i (joined + (portRef O (instanceRef SM_AMIGA_ns_i_0_2)) + (portRef D (instanceRef SM_AMIGA_5)) + )) + (net N_83_i (joined + (portRef O (instanceRef N_83_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_0_1)) )) (net N_78_i (joined - (portRef O (instanceRef SM_AMIGA_ns_i_0)) - (portRef D (instanceRef SM_AMIGA_7)) + (portRef O (instanceRef SM_AMIGA_ns_i_0_1)) + (portRef D (instanceRef SM_AMIGA_6)) )) - (net (rename state_machine_un44_clk_000_d1_i_1 "state_machine.un44_clk_000_d1_i_1") (joined - (portRef O (instanceRef state_machine_un44_clk_000_d1_1)) - (portRef I0 (instanceRef state_machine_un44_clk_000_d1)) + (net N_81_i (joined + (portRef O (instanceRef N_81_i)) + (portRef I1 (instanceRef state_machine_LDS_000_INT_5_0)) )) - (net un1_bg_030_0_1 (joined - (portRef O (instanceRef un1_bg_030_1)) - (portRef I0 (instanceRef un1_bg_030)) + (net (rename state_machine_LDS_000_INT_5_0 "state_machine.LDS_000_INT_5_0") (joined + (portRef O (instanceRef state_machine_LDS_000_INT_5_0)) + (portRef I0 (instanceRef state_machine_LDS_000_INT_5_0_i)) )) - (net un1_bg_030_0_2 (joined - (portRef O (instanceRef un1_bg_030_2)) - (portRef I1 (instanceRef un1_bg_030)) + (net (rename state_machine_UDS_000_INT_5_0 "state_machine.UDS_000_INT_5_0") (joined + (portRef O (instanceRef state_machine_UDS_000_INT_5_0)) + (portRef I0 (instanceRef state_machine_UDS_000_INT_5_0_i)) )) - (net (rename state_machine_AS_030_000_SYNC_3_2_1 "state_machine.AS_030_000_SYNC_3_2_1") (joined - (portRef O (instanceRef state_machine_AS_030_000_SYNC_3_1)) - (portRef I0 (instanceRef state_machine_AS_030_000_SYNC_3)) + (net N_79_i (joined + (portRef O (instanceRef N_79_i)) + (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i)) )) - (net (rename clk_cpu_est_11_0_1_1 "clk.cpu_est_11_0_1[1]") (joined - (portRef O (instanceRef clk_cpu_est_11_0_1_1)) - (portRef I0 (instanceRef clk_cpu_est_11_0_1)) + (net N_30_0 (joined + (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i)) + (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_i)) )) - (net (rename clk_cpu_est_11_0_2_1 "clk.cpu_est_11_0_2[1]") (joined - (portRef O (instanceRef clk_cpu_est_11_0_2_1)) - (portRef I1 (instanceRef clk_cpu_est_11_0_1)) + (net N_165_0 (joined + (portRef O (instanceRef DTACK_SYNC_1_sqmuxa_1_i)) + (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa_1_i_i)) )) - (net N_168_1 (joined + (net N_76_i (joined + (portRef O (instanceRef N_76_i)) + (portRef I1 (instanceRef un1_as_030_000_sync8_i)) + )) + (net N_164_0 (joined + (portRef O (instanceRef un1_as_030_000_sync8_i)) + (portRef I0 (instanceRef un1_as_030_000_sync8_i_i)) + )) + (net N_163_0 (joined + (portRef O (instanceRef VPA_SYNC_1_sqmuxa_1_i)) + (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1_i_i)) + )) + (net N_72_i (joined + (portRef O (instanceRef N_72_i)) + (portRef I0 (instanceRef state_machine_un15_clk_000_d0_0)) + )) + (net N_73_i (joined + (portRef O (instanceRef N_73_i)) + (portRef I1 (instanceRef state_machine_un15_clk_000_d0_0)) + )) + (net (rename state_machine_un15_clk_000_d0_0 "state_machine.un15_clk_000_d0_0") (joined + (portRef O (instanceRef state_machine_un15_clk_000_d0_0)) + (portRef I0 (instanceRef state_machine_un15_clk_000_d0_0_i)) + )) + (net N_162_0 (joined + (portRef O (instanceRef un1_as_030_3_i)) + (portRef I0 (instanceRef un1_as_030_3_i_i)) + )) + (net (rename state_machine_un6_bgack_000_0 "state_machine.un6_bgack_000_0") (joined + (portRef O (instanceRef state_machine_un6_bgack_000_0)) + (portRef I0 (instanceRef state_machine_un6_bgack_000_0_i)) + )) + (net (rename state_machine_un23_clk_000_d0_i "state_machine.un23_clk_000_d0_i") (joined + (portRef O (instanceRef state_machine_un23_clk_000_d0)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_0_o2_4)) + (portRef I0 (instanceRef state_machine_un23_clk_000_d0_i_0)) + )) + (net N_188_1 (joined (portRef O (instanceRef un8_ciin_1)) (portRef I0 (instanceRef un8_ciin_5)) )) - (net N_168_2 (joined + (net N_188_2 (joined (portRef O (instanceRef un8_ciin_2)) (portRef I1 (instanceRef un8_ciin_5)) )) - (net N_168_3 (joined + (net N_188_3 (joined (portRef O (instanceRef un8_ciin_3)) (portRef I0 (instanceRef un8_ciin_6)) )) - (net N_168_4 (joined + (net N_188_4 (joined (portRef O (instanceRef un8_ciin_4)) (portRef I1 (instanceRef un8_ciin_6)) )) - (net N_168_5 (joined + (net N_188_5 (joined (portRef O (instanceRef un8_ciin_5)) (portRef I0 (instanceRef un8_ciin)) )) - (net N_168_6 (joined + (net N_188_6 (joined (portRef O (instanceRef un8_ciin_6)) (portRef I1 (instanceRef un8_ciin)) )) - (net N_171_1 (joined + (net N_191_1 (joined (portRef O (instanceRef un4_ciin_1)) (portRef I0 (instanceRef un4_ciin)) )) - (net N_171_2 (joined + (net N_191_2 (joined (portRef O (instanceRef un4_ciin_2)) (portRef I1 (instanceRef un4_ciin)) )) - (net UDS_000_INT_0_sqmuxa_1_1 (joined - (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1_1)) - (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_1_3)) + (net (rename state_machine_un8_clk_000_d2_1 "state_machine.un8_clk_000_d2_1") (joined + (portRef O (instanceRef state_machine_un8_clk_000_d2_1)) + (portRef I0 (instanceRef state_machine_un8_clk_000_d2)) )) - (net UDS_000_INT_0_sqmuxa_1_2 (joined - (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1_2)) - (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa_1_3)) + (net N_57_i_1 (joined + (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_1)) + (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_4)) )) - (net UDS_000_INT_0_sqmuxa_1_3 (joined - (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1_3)) - (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_1)) + (net N_57_i_2 (joined + (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_2)) + (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_4)) )) - (net UDS_000_INT_0_sqmuxa_1_0 (joined - (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1_0)) - (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa)) + (net N_57_i_3 (joined + (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_3)) + (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_5)) )) - (net N_96_1 (joined - (portRef O (instanceRef un1_DSACK_INT_0_sqmuxa_i_a3_1)) - (portRef I0 (instanceRef un1_DSACK_INT_0_sqmuxa_i_a3)) + (net N_57_i_4 (joined + (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_4)) + (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2)) )) - (net (rename state_machine_un42_clk_030_1 "state_machine.un42_clk_030_1") (joined - (portRef O (instanceRef state_machine_un42_clk_030_1)) - (portRef I0 (instanceRef state_machine_un42_clk_030_4)) + (net N_57_i_5 (joined + (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_5)) + (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2)) )) - (net (rename state_machine_un42_clk_030_2 "state_machine.un42_clk_030_2") (joined - (portRef O (instanceRef state_machine_un42_clk_030_2)) - (portRef I1 (instanceRef state_machine_un42_clk_030_4)) + (net (rename clk_cpu_est_11_0_1_1 "clk.cpu_est_11_0_1[1]") (joined + (portRef O (instanceRef clk_cpu_est_11_0_0_1_1)) + (portRef I0 (instanceRef clk_cpu_est_11_0_0_1)) )) - (net (rename state_machine_un42_clk_030_3 "state_machine.un42_clk_030_3") (joined - (portRef O (instanceRef state_machine_un42_clk_030_3)) - (portRef I0 (instanceRef state_machine_un42_clk_030_5)) + (net (rename clk_cpu_est_11_0_2_1 "clk.cpu_est_11_0_2[1]") (joined + (portRef O (instanceRef clk_cpu_est_11_0_0_2_1)) + (portRef I1 (instanceRef clk_cpu_est_11_0_0_1)) )) - (net (rename state_machine_un42_clk_030_4 "state_machine.un42_clk_030_4") (joined - (portRef O (instanceRef state_machine_un42_clk_030_4)) - (portRef I0 (instanceRef state_machine_un42_clk_030)) + (net N_120_1 (joined + (portRef O (instanceRef un1_bg_030_i_a3_1)) + (portRef I0 (instanceRef un1_bg_030_i_a3)) )) - (net (rename state_machine_un42_clk_030_5 "state_machine.un42_clk_030_5") (joined - (portRef O (instanceRef state_machine_un42_clk_030_5)) - (portRef I1 (instanceRef state_machine_un42_clk_030)) + (net N_120_2 (joined + (portRef O (instanceRef un1_bg_030_i_a3_2)) + (portRef I1 (instanceRef un1_bg_030_i_a3)) )) - (net AMIGA_BUS_ENABLE_i_m_1 (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_i_m_1)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_i_m)) + (net N_79_1 (joined + (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a3_1)) + (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a3)) )) - (net VPA_SYNC_1_sqmuxa_1_0 (joined - (portRef O (instanceRef VPA_SYNC_1_sqmuxa_1_0)) - (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_5)) + (net N_79_2 (joined + (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a3_2)) + (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a3)) )) - (net VPA_SYNC_1_sqmuxa_2 (joined - (portRef O (instanceRef VPA_SYNC_1_sqmuxa_2)) - (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_5)) + (net N_77_1_0 (joined + (portRef O (instanceRef DTACK_SYNC_1_sqmuxa_1_i_a3_1)) + (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa_1_i_a3)) )) - (net VPA_SYNC_1_sqmuxa_3 (joined - (portRef O (instanceRef VPA_SYNC_1_sqmuxa_3)) - (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_6)) + (net N_75_1 (joined + (portRef O (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_1)) + (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_4)) )) - (net VPA_SYNC_1_sqmuxa_4 (joined - (portRef O (instanceRef VPA_SYNC_1_sqmuxa_4)) - (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_6)) + (net N_75_2 (joined + (portRef O (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_2_0)) + (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_4)) )) - (net VPA_SYNC_1_sqmuxa_5 (joined - (portRef O (instanceRef VPA_SYNC_1_sqmuxa_5)) - (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa)) + (net N_75_3 (joined + (portRef O (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_3)) + (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_5)) )) - (net VPA_SYNC_1_sqmuxa_6 (joined - (portRef O (instanceRef VPA_SYNC_1_sqmuxa_6)) - (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa)) + (net N_75_4 (joined + (portRef O (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_4)) + (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3)) )) - (net N_127_1 (joined - (portRef O (instanceRef clk_cpu_est_11_i_a4_1_2)) - (portRef I0 (instanceRef clk_cpu_est_11_i_a4_2)) + (net N_75_5 (joined + (portRef O (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_5)) + (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3)) )) - (net N_128_1 (joined - (portRef O (instanceRef clk_cpu_est_11_i_a4_0_1_2)) - (portRef I0 (instanceRef clk_cpu_est_11_i_a4_0_2)) + (net N_73_1 (joined + (portRef O (instanceRef state_machine_un15_clk_000_d0_0_a3_0_1)) + (portRef I0 (instanceRef state_machine_un15_clk_000_d0_0_a3_0)) )) - (net N_131_1 (joined - (portRef O (instanceRef clk_cpu_est_11_0_a4_1_1_3)) - (portRef I0 (instanceRef clk_cpu_est_11_0_a4_1_3)) + (net N_73_2 (joined + (portRef O (instanceRef state_machine_un15_clk_000_d0_0_a3_0_2)) + (portRef I1 (instanceRef state_machine_un15_clk_000_d0_0_a3_0)) + )) + (net N_72_1 (joined + (portRef O (instanceRef state_machine_un15_clk_000_d0_0_a3_1)) + (portRef I0 (instanceRef state_machine_un15_clk_000_d0_0_a3)) + )) + (net N_72_2 (joined + (portRef O (instanceRef state_machine_un15_clk_000_d0_0_a3_2)) + (portRef I1 (instanceRef state_machine_un15_clk_000_d0_0_a3)) + )) + (net (rename SM_AMIGA_ns_0_1_0 "SM_AMIGA_ns_0_1[0]") (joined + (portRef O (instanceRef SM_AMIGA_ns_0_1_0)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_0)) )) (net (rename clk_cpu_est_11_0_1_3 "clk.cpu_est_11_0_1[3]") (joined - (portRef O (instanceRef clk_cpu_est_11_0_1_3)) - (portRef I0 (instanceRef clk_cpu_est_11_0_3)) + (portRef O (instanceRef clk_cpu_est_11_0_0_1_3)) + (portRef I0 (instanceRef clk_cpu_est_11_0_0_3)) )) - (net N_105_1 (joined - (portRef O (instanceRef SM_AMIGA_ns_a3_0_1_5)) - (portRef I0 (instanceRef SM_AMIGA_ns_a3_0_5)) + (net N_138_1 (joined + (portRef O (instanceRef clk_cpu_est_11_0_0_a3_1_1_3)) + (portRef I0 (instanceRef clk_cpu_est_11_0_0_a3_1_3)) )) - (net DTACK_SYNC_1_sqmuxa_1_0 (joined - (portRef O (instanceRef DTACK_SYNC_1_sqmuxa_1_0)) - (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa)) + (net N_119_1 (joined + (portRef O (instanceRef state_machine_AMIGA_BUS_ENABLE_3_f0_i_a3_1)) + (portRef I0 (instanceRef state_machine_AMIGA_BUS_ENABLE_3_f0_i_a3)) )) - (net DTACK_SYNC_1_sqmuxa_2 (joined - (portRef O (instanceRef DTACK_SYNC_1_sqmuxa_2)) - (portRef I1 (instanceRef DTACK_SYNC_1_sqmuxa)) + (net N_118_1 (joined + (portRef O (instanceRef clk_cpu_est_11_i_0_a3_0_1_2)) + (portRef I0 (instanceRef clk_cpu_est_11_i_0_a3_0_2)) )) - (net (rename state_machine_un8_clk_000_d0_1 "state_machine.un8_clk_000_d0_1") (joined - (portRef O (instanceRef state_machine_un8_clk_000_d0_1)) - (portRef I0 (instanceRef state_machine_un8_clk_000_d0_4)) + (net N_117_1 (joined + (portRef O (instanceRef clk_cpu_est_11_i_0_a3_1_2)) + (portRef I0 (instanceRef clk_cpu_est_11_i_0_a3_2)) )) - (net (rename state_machine_un8_clk_000_d0_2 "state_machine.un8_clk_000_d0_2") (joined - (portRef O (instanceRef state_machine_un8_clk_000_d0_2)) - (portRef I1 (instanceRef state_machine_un8_clk_000_d0_4)) + (net N_97_1 (joined + (portRef O (instanceRef SM_AMIGA_ns_0_a3_0_1_5)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_a3_0_5)) )) - (net (rename state_machine_un8_clk_000_d0_3 "state_machine.un8_clk_000_d0_3") (joined - (portRef O (instanceRef state_machine_un8_clk_000_d0_3)) - (portRef I1 (instanceRef state_machine_un8_clk_000_d0)) + (net N_81_1 (joined + (portRef O (instanceRef state_machine_LDS_000_INT_5_0_a3_1)) + (portRef I0 (instanceRef state_machine_LDS_000_INT_5_0_a3)) )) - (net (rename state_machine_un8_clk_000_d0_4 "state_machine.un8_clk_000_d0_4") (joined - (portRef O (instanceRef state_machine_un8_clk_000_d0_4)) - (portRef I0 (instanceRef state_machine_un8_clk_000_d0)) + (net (rename state_machine_UDS_000_INT_5_0_m2_un3 "state_machine.UDS_000_INT_5_0_m2.un3") (joined + (portRef O (instanceRef state_machine_UDS_000_INT_5_0_m2_r)) + (portRef I1 (instanceRef state_machine_UDS_000_INT_5_0_m2_n)) )) - (net (rename state_machine_un13_clk_000_d0_1_0 "state_machine.un13_clk_000_d0_1_0") (joined - (portRef O (instanceRef state_machine_un13_clk_000_d0_1_0)) - (portRef I0 (instanceRef state_machine_un13_clk_000_d0)) + (net (rename state_machine_UDS_000_INT_5_0_m2_un1 "state_machine.UDS_000_INT_5_0_m2.un1") (joined + (portRef O (instanceRef state_machine_UDS_000_INT_5_0_m2_m)) + (portRef I0 (instanceRef state_machine_UDS_000_INT_5_0_m2_p)) )) - (net (rename state_machine_un13_clk_000_d0_2_0 "state_machine.un13_clk_000_d0_2_0") (joined - (portRef O (instanceRef state_machine_un13_clk_000_d0_2_0)) - (portRef I1 (instanceRef state_machine_un13_clk_000_d0)) + (net (rename state_machine_UDS_000_INT_5_0_m2_un0 "state_machine.UDS_000_INT_5_0_m2.un0") (joined + (portRef O (instanceRef state_machine_UDS_000_INT_5_0_m2_n)) + (portRef I1 (instanceRef state_machine_UDS_000_INT_5_0_m2_p)) + )) + (net (rename VPA_SYNC_0_un3 "VPA_SYNC_0.un3") (joined + (portRef O (instanceRef VPA_SYNC_0_r)) + (portRef I1 (instanceRef VPA_SYNC_0_n)) + )) + (net (rename VPA_SYNC_0_un1 "VPA_SYNC_0.un1") (joined + (portRef O (instanceRef VPA_SYNC_0_m)) + (portRef I0 (instanceRef VPA_SYNC_0_p)) + )) + (net (rename VPA_SYNC_0_un0 "VPA_SYNC_0.un0") (joined + (portRef O (instanceRef VPA_SYNC_0_n)) + (portRef I1 (instanceRef VPA_SYNC_0_p)) + )) + (net (rename AMIGA_BUS_ENABLE_0_un3 "AMIGA_BUS_ENABLE_0.un3") (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_0_r)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_0_n)) + )) + (net (rename AMIGA_BUS_ENABLE_0_un1 "AMIGA_BUS_ENABLE_0.un1") (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_0_m)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_0_p)) + )) + (net (rename AMIGA_BUS_ENABLE_0_un0 "AMIGA_BUS_ENABLE_0.un0") (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_0_n)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_0_p)) + )) + (net (rename UDS_000_INT_0_un3 "UDS_000_INT_0.un3") (joined + (portRef O (instanceRef UDS_000_INT_0_r)) + (portRef I1 (instanceRef UDS_000_INT_0_n)) + )) + (net (rename UDS_000_INT_0_un1 "UDS_000_INT_0.un1") (joined + (portRef O (instanceRef UDS_000_INT_0_m)) + (portRef I0 (instanceRef UDS_000_INT_0_p)) + )) + (net (rename UDS_000_INT_0_un0 "UDS_000_INT_0.un0") (joined + (portRef O (instanceRef UDS_000_INT_0_n)) + (portRef I1 (instanceRef UDS_000_INT_0_p)) + )) + (net (rename LDS_000_INT_0_un3 "LDS_000_INT_0.un3") (joined + (portRef O (instanceRef LDS_000_INT_0_r)) + (portRef I1 (instanceRef LDS_000_INT_0_n)) + )) + (net (rename LDS_000_INT_0_un1 "LDS_000_INT_0.un1") (joined + (portRef O (instanceRef LDS_000_INT_0_m)) + (portRef I0 (instanceRef LDS_000_INT_0_p)) + )) + (net (rename LDS_000_INT_0_un0 "LDS_000_INT_0.un0") (joined + (portRef O (instanceRef LDS_000_INT_0_n)) + (portRef I1 (instanceRef LDS_000_INT_0_p)) + )) + (net (rename VMA_INT_0_un3 "VMA_INT_0.un3") (joined + (portRef O (instanceRef VMA_INT_0_r)) + (portRef I1 (instanceRef VMA_INT_0_n)) + )) + (net (rename VMA_INT_0_un1 "VMA_INT_0.un1") (joined + (portRef O (instanceRef VMA_INT_0_m)) + (portRef I0 (instanceRef VMA_INT_0_p)) + )) + (net (rename VMA_INT_0_un0 "VMA_INT_0.un0") (joined + (portRef O (instanceRef VMA_INT_0_n)) + (portRef I1 (instanceRef VMA_INT_0_p)) + )) + (net (rename BG_000_0_un3 "BG_000_0.un3") (joined + (portRef O (instanceRef BG_000_0_r)) + (portRef I1 (instanceRef BG_000_0_n)) + )) + (net (rename BG_000_0_un1 "BG_000_0.un1") (joined + (portRef O (instanceRef BG_000_0_m)) + (portRef I0 (instanceRef BG_000_0_p)) + )) + (net (rename BG_000_0_un0 "BG_000_0.un0") (joined + (portRef O (instanceRef BG_000_0_n)) + (portRef I1 (instanceRef BG_000_0_p)) + )) + (net (rename BGACK_030_INT_0_un3 "BGACK_030_INT_0.un3") (joined + (portRef O (instanceRef BGACK_030_INT_0_r)) + (portRef I1 (instanceRef BGACK_030_INT_0_n)) + )) + (net (rename BGACK_030_INT_0_un1 "BGACK_030_INT_0.un1") (joined + (portRef O (instanceRef BGACK_030_INT_0_m)) + (portRef I0 (instanceRef BGACK_030_INT_0_p)) + )) + (net (rename BGACK_030_INT_0_un0 "BGACK_030_INT_0.un0") (joined + (portRef O (instanceRef BGACK_030_INT_0_n)) + (portRef I1 (instanceRef BGACK_030_INT_0_p)) + )) + (net (rename AS_000_INT_0_un3 "AS_000_INT_0.un3") (joined + (portRef O (instanceRef AS_000_INT_0_r)) + (portRef I1 (instanceRef AS_000_INT_0_n)) + )) + (net (rename AS_000_INT_0_un1 "AS_000_INT_0.un1") (joined + (portRef O (instanceRef AS_000_INT_0_m)) + (portRef I0 (instanceRef AS_000_INT_0_p)) + )) + (net (rename AS_000_INT_0_un0 "AS_000_INT_0.un0") (joined + (portRef O (instanceRef AS_000_INT_0_n)) + (portRef I1 (instanceRef AS_000_INT_0_p)) )) (net (rename cpu_est_0_1__un3 "cpu_est_0_1_.un3") (joined (portRef O (instanceRef cpu_est_0_1__r)) @@ -2483,6 +2602,18 @@ (portRef O (instanceRef cpu_est_0_1__n)) (portRef I1 (instanceRef cpu_est_0_1__p)) )) + (net (rename cpu_est_0_2__un3 "cpu_est_0_2_.un3") (joined + (portRef O (instanceRef cpu_est_0_2__r)) + (portRef I1 (instanceRef cpu_est_0_2__n)) + )) + (net (rename cpu_est_0_2__un1 "cpu_est_0_2_.un1") (joined + (portRef O (instanceRef cpu_est_0_2__m)) + (portRef I0 (instanceRef cpu_est_0_2__p)) + )) + (net (rename cpu_est_0_2__un0 "cpu_est_0_2_.un0") (joined + (portRef O (instanceRef cpu_est_0_2__n)) + (portRef I1 (instanceRef cpu_est_0_2__p)) + )) (net (rename cpu_est_0_3__un3 "cpu_est_0_3_.un3") (joined (portRef O (instanceRef cpu_est_0_3__r)) (portRef I1 (instanceRef cpu_est_0_3__n)) @@ -2531,114 +2662,6 @@ (portRef O (instanceRef IPL_030_0_2__n)) (portRef I1 (instanceRef IPL_030_0_2__p)) )) - (net (rename UDS_000_INT_0_un3 "UDS_000_INT_0.un3") (joined - (portRef O (instanceRef UDS_000_INT_0_r)) - (portRef I1 (instanceRef UDS_000_INT_0_n)) - )) - (net (rename UDS_000_INT_0_un1 "UDS_000_INT_0.un1") (joined - (portRef O (instanceRef UDS_000_INT_0_m)) - (portRef I0 (instanceRef UDS_000_INT_0_p)) - )) - (net (rename UDS_000_INT_0_un0 "UDS_000_INT_0.un0") (joined - (portRef O (instanceRef UDS_000_INT_0_n)) - (portRef I1 (instanceRef UDS_000_INT_0_p)) - )) - (net (rename VPA_SYNC_0_un3 "VPA_SYNC_0.un3") (joined - (portRef O (instanceRef VPA_SYNC_0_r)) - (portRef I1 (instanceRef VPA_SYNC_0_n)) - )) - (net (rename VPA_SYNC_0_un1 "VPA_SYNC_0.un1") (joined - (portRef O (instanceRef VPA_SYNC_0_m)) - (portRef I0 (instanceRef VPA_SYNC_0_p)) - )) - (net (rename VPA_SYNC_0_un0 "VPA_SYNC_0.un0") (joined - (portRef O (instanceRef VPA_SYNC_0_n)) - (portRef I1 (instanceRef VPA_SYNC_0_p)) - )) - (net (rename AS_000_INT_0_un3 "AS_000_INT_0.un3") (joined - (portRef O (instanceRef AS_000_INT_0_r)) - (portRef I1 (instanceRef AS_000_INT_0_n)) - )) - (net (rename AS_000_INT_0_un1 "AS_000_INT_0.un1") (joined - (portRef O (instanceRef AS_000_INT_0_m)) - (portRef I0 (instanceRef AS_000_INT_0_p)) - )) - (net (rename AS_000_INT_0_un0 "AS_000_INT_0.un0") (joined - (portRef O (instanceRef AS_000_INT_0_n)) - (portRef I1 (instanceRef AS_000_INT_0_p)) - )) - (net (rename BGACK_030_INT_0_un3 "BGACK_030_INT_0.un3") (joined - (portRef O (instanceRef BGACK_030_INT_0_r)) - (portRef I1 (instanceRef BGACK_030_INT_0_n)) - )) - (net (rename BGACK_030_INT_0_un1 "BGACK_030_INT_0.un1") (joined - (portRef O (instanceRef BGACK_030_INT_0_m)) - (portRef I0 (instanceRef BGACK_030_INT_0_p)) - )) - (net (rename BGACK_030_INT_0_un0 "BGACK_030_INT_0.un0") (joined - (portRef O (instanceRef BGACK_030_INT_0_n)) - (portRef I1 (instanceRef BGACK_030_INT_0_p)) - )) - (net (rename VMA_INT_0_un3 "VMA_INT_0.un3") (joined - (portRef O (instanceRef VMA_INT_0_r)) - (portRef I1 (instanceRef VMA_INT_0_n)) - )) - (net (rename VMA_INT_0_un1 "VMA_INT_0.un1") (joined - (portRef O (instanceRef VMA_INT_0_m)) - (portRef I0 (instanceRef VMA_INT_0_p)) - )) - (net (rename VMA_INT_0_un0 "VMA_INT_0.un0") (joined - (portRef O (instanceRef VMA_INT_0_n)) - (portRef I1 (instanceRef VMA_INT_0_p)) - )) - (net (rename cpu_est_0_2__un3 "cpu_est_0_2_.un3") (joined - (portRef O (instanceRef cpu_est_0_2__r)) - (portRef I1 (instanceRef cpu_est_0_2__n)) - )) - (net (rename cpu_est_0_2__un1 "cpu_est_0_2_.un1") (joined - (portRef O (instanceRef cpu_est_0_2__m)) - (portRef I0 (instanceRef cpu_est_0_2__p)) - )) - (net (rename cpu_est_0_2__un0 "cpu_est_0_2_.un0") (joined - (portRef O (instanceRef cpu_est_0_2__n)) - (portRef I1 (instanceRef cpu_est_0_2__p)) - )) - (net (rename DSACK_INT_0_1__un3 "DSACK_INT_0_1_.un3") (joined - (portRef O (instanceRef DSACK_INT_0_1__r)) - (portRef I1 (instanceRef DSACK_INT_0_1__n)) - )) - (net (rename DSACK_INT_0_1__un1 "DSACK_INT_0_1_.un1") (joined - (portRef O (instanceRef DSACK_INT_0_1__m)) - (portRef I0 (instanceRef DSACK_INT_0_1__p)) - )) - (net (rename DSACK_INT_0_1__un0 "DSACK_INT_0_1_.un0") (joined - (portRef O (instanceRef DSACK_INT_0_1__n)) - (portRef I1 (instanceRef DSACK_INT_0_1__p)) - )) - (net (rename BG_000_0_un3 "BG_000_0.un3") (joined - (portRef O (instanceRef BG_000_0_r)) - (portRef I1 (instanceRef BG_000_0_n)) - )) - (net (rename BG_000_0_un1 "BG_000_0.un1") (joined - (portRef O (instanceRef BG_000_0_m)) - (portRef I0 (instanceRef BG_000_0_p)) - )) - (net (rename BG_000_0_un0 "BG_000_0.un0") (joined - (portRef O (instanceRef BG_000_0_n)) - (portRef I1 (instanceRef BG_000_0_p)) - )) - (net (rename AMIGA_BUS_ENABLE_0_un3 "AMIGA_BUS_ENABLE_0.un3") (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_0_r)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_0_n)) - )) - (net (rename AMIGA_BUS_ENABLE_0_un1 "AMIGA_BUS_ENABLE_0.un1") (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_0_m)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_0_p)) - )) - (net (rename AMIGA_BUS_ENABLE_0_un0 "AMIGA_BUS_ENABLE_0.un0") (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_0_n)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_0_p)) - )) (net (rename AS_030_000_SYNC_0_un3 "AS_030_000_SYNC_0.un3") (joined (portRef O (instanceRef AS_030_000_SYNC_0_r)) (portRef I1 (instanceRef AS_030_000_SYNC_0_n)) @@ -2651,18 +2674,6 @@ (portRef O (instanceRef AS_030_000_SYNC_0_n)) (portRef I1 (instanceRef AS_030_000_SYNC_0_p)) )) - (net (rename FPU_CS_INT_0_un3 "FPU_CS_INT_0.un3") (joined - (portRef O (instanceRef FPU_CS_INT_0_r)) - (portRef I1 (instanceRef FPU_CS_INT_0_n)) - )) - (net (rename FPU_CS_INT_0_un1 "FPU_CS_INT_0.un1") (joined - (portRef O (instanceRef FPU_CS_INT_0_m)) - (portRef I0 (instanceRef FPU_CS_INT_0_p)) - )) - (net (rename FPU_CS_INT_0_un0 "FPU_CS_INT_0.un0") (joined - (portRef O (instanceRef FPU_CS_INT_0_n)) - (portRef I1 (instanceRef FPU_CS_INT_0_p)) - )) (net (rename DTACK_SYNC_0_un3 "DTACK_SYNC_0.un3") (joined (portRef O (instanceRef DTACK_SYNC_0_r)) (portRef I1 (instanceRef DTACK_SYNC_0_n)) @@ -2675,17 +2686,29 @@ (portRef O (instanceRef DTACK_SYNC_0_n)) (portRef I1 (instanceRef DTACK_SYNC_0_p)) )) - (net (rename LDS_000_INT_0_un3 "LDS_000_INT_0.un3") (joined - (portRef O (instanceRef LDS_000_INT_0_r)) - (portRef I1 (instanceRef LDS_000_INT_0_n)) + (net (rename FPU_CS_INT_0_un3 "FPU_CS_INT_0.un3") (joined + (portRef O (instanceRef FPU_CS_INT_0_r)) + (portRef I1 (instanceRef FPU_CS_INT_0_n)) )) - (net (rename LDS_000_INT_0_un1 "LDS_000_INT_0.un1") (joined - (portRef O (instanceRef LDS_000_INT_0_m)) - (portRef I0 (instanceRef LDS_000_INT_0_p)) + (net (rename FPU_CS_INT_0_un1 "FPU_CS_INT_0.un1") (joined + (portRef O (instanceRef FPU_CS_INT_0_m)) + (portRef I0 (instanceRef FPU_CS_INT_0_p)) )) - (net (rename LDS_000_INT_0_un0 "LDS_000_INT_0.un0") (joined - (portRef O (instanceRef LDS_000_INT_0_n)) - (portRef I1 (instanceRef LDS_000_INT_0_p)) + (net (rename FPU_CS_INT_0_un0 "FPU_CS_INT_0.un0") (joined + (portRef O (instanceRef FPU_CS_INT_0_n)) + (portRef I1 (instanceRef FPU_CS_INT_0_p)) + )) + (net (rename DSACK_INT_0_1__un3 "DSACK_INT_0_1_.un3") (joined + (portRef O (instanceRef DSACK_INT_0_1__r)) + (portRef I1 (instanceRef DSACK_INT_0_1__n)) + )) + (net (rename DSACK_INT_0_1__un1 "DSACK_INT_0_1_.un1") (joined + (portRef O (instanceRef DSACK_INT_0_1__m)) + (portRef I0 (instanceRef DSACK_INT_0_1__p)) + )) + (net (rename DSACK_INT_0_1__un0 "DSACK_INT_0_1_.un0") (joined + (portRef O (instanceRef DSACK_INT_0_1__n)) + (portRef I1 (instanceRef DSACK_INT_0_1__p)) )) ) (property orig_inst_of (string "BUS68030")) diff --git a/Logic/BUS68030.fse b/Logic/BUS68030.fse index 272dfbe..98498ff 100644 --- a/Logic/BUS68030.fse +++ b/Logic/BUS68030.fse @@ -1,20 +1,20 @@ -fsm_encoding {718321831} onehot +fsm_encoding {718521851} onehot -fsm_state_encoding {718321831} idle_p {00000001} +fsm_state_encoding {718521851} idle_p {00000001} -fsm_state_encoding {718321831} idle_n {00000010} +fsm_state_encoding {718521851} idle_n {00000010} -fsm_state_encoding {718321831} as_set_p {00000100} +fsm_state_encoding {718521851} as_set_p {00000100} -fsm_state_encoding {718321831} as_set_n {00001000} +fsm_state_encoding {718521851} as_set_n {00001000} -fsm_state_encoding {718321831} sample_dtack_p {00010000} +fsm_state_encoding {718521851} sample_dtack_p {00010000} -fsm_state_encoding {718321831} data_fetch_n {00100000} +fsm_state_encoding {718521851} data_fetch_n {00100000} -fsm_state_encoding {718321831} data_fetch_p {01000000} +fsm_state_encoding {718521851} data_fetch_p {01000000} -fsm_state_encoding {718321831} end_cycle_n {10000000} +fsm_state_encoding {718521851} end_cycle_n {10000000} -fsm_registers {718321831} {SM_AMIGA[0]} {SM_AMIGA[1]} {SM_AMIGA[2]} {SM_AMIGA[3]} {SM_AMIGA[4]} {SM_AMIGA[5]} {SM_AMIGA[6]} {SM_AMIGA[7]} +fsm_registers {718521851} {SM_AMIGA[0]} {SM_AMIGA[1]} {SM_AMIGA[2]} {SM_AMIGA[3]} {SM_AMIGA[4]} {SM_AMIGA[5]} {SM_AMIGA[6]} {SM_AMIGA[7]} diff --git a/Logic/BUS68030.prj b/Logic/BUS68030.prj index 6306612..16f102d 100644 --- a/Logic/BUS68030.prj +++ b/Logic/BUS68030.prj @@ -1,6 +1,6 @@ #-- Lattice Semiconductor Corporation Ltd. #-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj -#-- Written on Thu May 22 14:56:03 2014 +#-- Written on Sat May 24 11:44:02 2014 #device options diff --git a/Logic/BUS68030.srm b/Logic/BUS68030.srm index 6ad2b62..51c64d4 100644 --- a/Logic/BUS68030.srm +++ b/Logic/BUS68030.srm @@ -33,9 +33,9 @@ af .is_vhdl 1; af .child_list "-1"; af .parent_list "-1"; VNAME 'mach.MACH_DFF.prim'; # view id 0 -VNAME 'mach.DFFRH.prim'; # view id 1 -VNAME 'mach.DFF.prim'; # view id 2 -VNAME 'mach.DFFSH.prim'; # view id 3 +VNAME 'mach.DFFSH.prim'; # view id 1 +VNAME 'mach.DFFRH.prim'; # view id 2 +VNAME 'mach.DFF.prim'; # view id 3 VNAME 'mach.IBUF.prim'; # view id 4 VNAME 'mach.BUFTH.prim'; # view id 5 VNAME 'mach.OBUF.prim'; # view id 6 @@ -45,9 +45,8 @@ VNAME 'mach.INV.prim'; # view id 9 VNAME 'mach.OR2.prim'; # view id 10 VNAME 'mach.XOR2.prim'; # view id 11 VNAME 'mach.MACH_LATCH.prim'; # view id 12 -VNAME 'mach.DLATSH.prim'; # view id 13 -VNAME 'mach.DLATRH.prim'; # view id 14 -VNAME 'work.BUS68030.behavioral'; # view id 15 +VNAME 'mach.DLATRH.prim'; # view id 13 +VNAME 'work.BUS68030.behavioral'; # view id 14 @ERMRlENORBvq]w_7wsRbH l;N3ORCV8HMCF8V;R4 RNP3#8H#PFDCRlC4N; @@ -68,42 +67,6 @@ bfjj:RPHMR4kMR4kMR );bjRf:0jRsRkC0CskRBeB;R bfjj:RDVN#VCRNCD#R7th;R bfjj:RV8VsT#RR7TRRiBpR4kMRjkM;R -MROlNEwR7wR)]blsH;P -NR#3HblsHR -4;FRRTk;Mj -7HR;R -HB;pi -)HR;M -oRjkM;M -NRN3#PMC_CV0_D#No46R.no; -MMRk4N; -M#R3N_PCM_C0VoDN#.4R6 -n;sjRf:ljRNROEv]qB_w7wRHbslhRQ1S4 -TM=kj7 -S=S7 -B=piB -piSk)=MS4 -1B=eBh -SmwaQQ= )t;h7 -fbRjR:jHRMPkRM4kRM4)b; -R:fjjsR0k0CRsRkCe;BB -fbRjR:jV#NDCNRVDR#Ct;h7 -RMRlENORw7wRHbslN; -PHR3#Hbsl;R4 -TFRRjkM;R -H7H; -RiBp;M -oRjkM;M -NRN3#PMC_CV0_D#No46R.ns; -R:fjjNRlOvERq_B]7RwwblsHR1QhcT -S=jkM -=S77B -SpBi=pSi -)B=eB1 -S=BeB -mShaQQw t)=h -7;bjRf:0jRsRkC0CskRBeB;R -bfjj:RDVN#VCRNCD#R7th;R MROlNEwR7wR1]blsH;P NR#3HblsHR 4;FRRTk;Mj @@ -124,6 +87,42 @@ SmwaQQ= )t;h7 fbRjR:jHRMPkRM4kRM41b; R:fjjsR0k0CRsRkCe;BB fbRjR:jV#NDCNRVDR#Ct;h7 +RMRlENORw7w)b]Rs;Hl +RNP3bH#sRHl4F; +RkTRM +j;H;R7 +BHRp +i;H;R) +RoMk;Mj +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR4kM;M +NRN3#PMC_CV0_D#No46R.ns; +R:fjjNRlOvERq_B]7RwwblsHR1Qh4T +S=jkM +=S77B +SpBi=pSi +)M=k41 +S=BeB +mShaQQw t)=h +7;bjRf:HjRMkPRMk4RM)4R;R +bfjj:Rk0sCsR0keCRB +B;bjRf:VjRNCD#RDVN#tCRh +7;MlRRNROE7RwwblsH;P +NR#3HblsHR +4;FRRTk;Mj +7HR;R +HB;pi +RoMk;Mj +RNM3P#NCC_M0D_VN4o#Rn.6;R +sfjj:ROlNEqRvB7]_wbwRsRHlQch1 +=STk +MjS77= +pSBip=Bi) +S=BeB +=S1e +BBSahmQ wQ)h=t7b; +R:fjjsR0k0CRsRkCe;BB +fbRjR:jV#NDCNRVDR#Ct;h7 RMRlENORzQAwsRbH l;N3PRHs#bH4lR;R FmH; @@ -215,12 +214,12 @@ fbRjR:jHRMPkRM4kRM4)b; R:fjjsR0k0CRsRkCe;BB fbRjR:jV#NDCNRVDR#Ct;h7 fbRjR:jDsN0#RRTTRR7pRqakRM4k;Mj -RMRlENORq7paR1]blsH;P +RMRlENORq7paR)]blsH;P NR#3HblsHR 4;FRRTk;Mj 7HR;R Hp;qa -1HR;M +)HR;M oRjkM;M NRN3#PMC_CV0_D#No46R.no; MMRk4N; @@ -229,34 +228,16 @@ n;sjRf:ljRNROEv]qB_apqBb]RsRHlQ6h1 =STk MjS77= qSpaq=pa) -S=BeB -=S1k -M4SahmQ wQ)h=t7b; -R:fjjMRHPMRk4MRk4;R1 +S=4kM +=S1e +BBSahmQ wQ)h=t7b; +R:fjjMRHPMRk4MRk4;R) fbRjR:j0CskRk0sCBReBb; -R:fjjNRVDR#CV#NDChRt7M; -RNRlO7ERp)qa]sRbH -l;N3PRHs#bH4lR;R -FTMRkjH; -R -7;HqRpaH; -R -);okMRM -j;N3MR#CNP_0MC_NVDoR#4.;6n -RoMk;M4 -RNM3P#NCC_M0D_VN4o#Rn.6;R -sfjj:ROlNEqRvBp]_q]aBRHbslhRQ1S6 -TM=kj7 -S=S7 -p=qap -qaSk)=MS4 -1B=eBh -SmwaQQ= )t;h7 -fbRjR:jHRMPkRM4kRM4)b; -R:fjjsR0k0CRsRkCe;BB -fbRjR:jV#NDCNRVDR#Ct;h7 +R:fjjNRVDR#CV#NDChRt7@; + + + -@ ftell; @E@MR@4U:d::(44d:cIRRFRs Anz1UjjdRELCNFPHs;ND RNP3MDHCRMF6 @@ -265,188 +246,258 @@ NR#3H_8PED;R4 RNP3ONsEDVHC;R( RNP38lFkVDCHRDC(N; P#R3$VM_lRNb"sIF "R\B\:\ks#C#l\\NC0x\F\8OCklM\0#\0oHE\kL\jnUd j0\F\Do\HO\jnUdnj-Ujjj-#Lk38PE\M"\"N; -POR3F0M#N_M0sRCo"q71BQi_hjar9"R4;P -NRHFsoM_H#F0_VAR"zU1nj"dj;P -NRs3FHNohl"CRAnz1Ujjd"N; -PVR3D_FI#00NC -R{N3PRVIDF_sbNC_M0H_b#NH##o8MCR -4;N3PRVIDF_FbsbN#_bHbDC48R;P -NRD3VFDI_F#Fb_FLs RCMjN; -PVR3D_FIkJMHkHHVC48R;; +POR3F0M#N_M0sRCo"iBp_w) rRj9j7\M1iqB_aQhrRj94 +";NFPRs_HoH0M#_RFV"1AzndUjj +";N3PRFosHhCNlRz"A1jnUd;j" +RNP3FVDI0_#NR0C{P +NRD3VFbI_NMsC0b_H##_N#MHoC48R;P +NRD3VFbI_s#Fb_bNbD8HCR +4;N3PRVIDF_FDFbL#_sCF M;Rj +RNP3FVDIM_kHHJkV8HCR +4;}N; +POR38#L_NRPC{P +NRM#$_VsCCMsCOOC_D FORN{ +P$R1#l0CRN{ +P#R3$sM_CDVOF_O 0C$bR +g;}}; +;; } -RNP3LO8_P#NC -R{N#PR$sM_CsVCCCMO_FODO{ R -RNP10$#C{lR -RNP3M#$_VsCOODF $_0bgCR;; -} - -};}N; -PFR3Lb#F0M8FC;R4 -@HR@4U:n::44nn::_q1jRdjqj1_d -j;N3HRs_0DFosHMCNlR1"q_jjd"N; -HFR3s8HoH'sRHkMF0 -';F@R@U(:4:44:(::nqj1_jqjR1j_jjN; -HsR30FD_sMHoNRlC"_q1j"jj;H -NRD3#bHFsos8HRM"HF"k0;H -NRF3bsD0N8RHs"0Fk"H; -RU@@::4U4U:4:7n:1d_jj1R7_jjd;H -NR03sDs_FHNoMl"CR7j1_d;j" +RNP3#FLF8b0FRMC4H; +RU@@::4n4n:4:qn:1d_jj1Rq_jjd;H +NR03sDs_FHNoMl"CRqj1_d;j" RNH3HFsos8HRM'HF'k0;R -F@:@U44g:::4g(7:z1j_jj7Rz1j_jjN; -HsR30FD_sMHoNRlC"1z7_jjj"N; -H#R3DsbFHHo8sHR"M0Fk"N; -HbR3FNs0Ds8HRk"F0 -";F@R@Uj:.:.4:j::(p_71jRjjp_71j;jj -RNH3Ds0_HFsolMNCpR"7j1_j;j" -RNH3b#DFosH8RHs"FHMk;0" -RNH3sbF08NDH"sRF"k0;R -H@:@U.44:::.4cQ:1Z4 r:Rj91 QZrj4:9QR1Z4 r:;j9 -RNH3Ds0_HFsolMNC1R"Q"Z ;H -NRs3FHHo8sHR'M0Fk'N; -HCR38NHVs$sNMCNlRH'#x;C' -@HR@.U:.::4.4.::dqr49:jRdqr49:jRdqr49:j;H -NR03sDs_FHNoMl"CRq -";N3HRFosH8RHs'FHMk;0' -RNH3HC8VsNsNN$Ml'CRN -';H@R@Ud:.:.4:dj:4:XM uu_1qRB Mu X_q1uB - ;N3HRs_0DFosHMCNlR "MX1u_u qB"F; -RU@@::.c4c:.:Ac: R))A) );H -NR03sDs_FHNoMl"CRA) )"N; -H#R3DsbFHHo8sHR"M0Fk"N; -HbR3FNs0Ds8HRk"F0 -";H@R@U6:.:.4:6::nAjt_dAjRtd_jjN; -HsR30FD_sMHoNRlC"_Atj"dj;R -F@:@U.4n:::.nnt:A_jjjR_Atj;jj -RNH3Ds0_HFsolMNCAR"tj_jj -";F@R@U(:.:.4:(::gABtqid_jjtRAq_Bij;dj -RNH3Ds0_HFsolMNCAR"tiqB_jjd"H; -RU@@::.U4U:.:Ag:tiqB_jjjRqAtBji_j -j;N3HRs_0DFosHMCNlRt"Aq_Bij"jj;R -H@:@U.4g:::.g(p:Bid_jjpRBid_jjN; -HsR30FD_sMHoNRlC"iBp_jjd"H; -RU@@::dj4j:d:B(:pji_jBjRpji_j -j;N3HRs_0DFosHMCNlRp"Bij_jj -";H@R@U4:d:d4:4::UB_pimQ1ZRiBp_Zm1QN; -HsR30FD_sMHoNRlC"iBp_Zm1Q -";F@R@U.:d:d4:.4:4:iBp_e7Q_amzRiBp_e7Q_amz;H -NR03sDs_FHNoMl"CRB_pi7_Qem"za;R -F@:@Ud4d:::dd(p:BiX_ upRBiX_ uN; -HsR30FD_sMHoNRlC"iBp_u X"F; -RU@@::dc4c:d:wn:uBz_1uRwz1_B;H -NR03sDs_FHNoMl"CRw_uzB;1" -@FR@dU:6::4d(6::pQu_jjdrj.:9uRQpd_jj:r.jQ9Rujp_d.jr:;j9 -RNH3Ds0_HFsolMNCQR"ujp_d;j" -RNH3HC8VsNsNN$Ml'CRH_bDj'dj;R -H@:@Ud4n:::dndu:Qp:r.jQ9Ru.pr:Rj9Qrup.9:j;H -NR03sDs_FHNoMl"CRQ"up;H -NR83CHsVNsMN$NRlC'DHb'L; -RU@@::d(4(:d:76:1iqBrj4:91R7qrBi49:jRq71B4ir:;j9 -RNH3Ds0_HFsolMNC7R"1iqB"N; -H#R3DsbFHHo8sHR"M0Fk"N; -HCR38NHVs$sNMCNlR#'8N'O ;R -L@:@Ud4U:::dU6a:7qRBi7BaqiN; -HsR30FD_sMHoNRlC"q7aB;i" -RNH#_$M0#sH0CN0R -4;F@R@Ug:d:d4:g::cqBe R qeBN; -HsR30FD_sMHoNRlC" qeB -";F@R@Uj:c:c4:j::UqBe _u XR qeBX_ uN; -HsR30FD_sMHoNRlC" qeBX_ u +F@:@U44(:::4(n1:q_jjjR_q1j;jj +RNH3Ds0_HFsolMNCqR"1j_jj ";N3HR#FDbs8HoH"sRHkMF0 ";N3HRb0FsNHD8sFR"k;0" -@FR@cU:4::4c44:: R;H -NR03sDs_FHNoMl"CR -";H@R@U.:c:c4:.::deRuqe;uq -RNH3Ds0_HFsolMNCeR"u;q" -@FR@cU:d::4cdd::qevRqev;H -NR03sDs_FHNoMl"CRe"vq;R -H@:@Uc4c:::ccd1:)a1R)aN; -HsR30FD_sMHoNRlC"a)1"F; -RU@@::c646:c:)6: a1 R1) -a;N3HRs_0DFosHMCNlR ")1" a;R -H@:@Uc4n:::cn.W:)R;)W -RNH3Ds0_HFsolMNC)R"W -";H@R@UU:c:c4:U::.w4Br:Rj9w4Br:Rj9w4Br:;j9 -RNH3Ds0_HFsolMNCwR"B -";N3HRCV8HNNss$lMNCVR'O -';F@R@Ug:c:c4:gn:4:QqvtAq_z 1_hpqA vRqQ_tqA_z1 Ahqp - ;N3HRs_0DFosHMCNlRv"qQ_tqA_z1 Ahqp; " -@FR@6U:j::464j:Uv:qQ_tqA_z17qqa_)7QRQqvtAq_z71_q_aq7;Q) -RNH3Ds0_HFsolMNCqR"vqQt_1Az_a7qqQ_7) -";F@R@U4:6:64:4j:.:QqvtAq_z 1_hpqA m_pWvRqQ_tqA_z1 Ahqpp _m -W;N3HRs_0DFosHMCNlRv"qQ_tqA_z1 Ahqpp _m;W" -@FR@6U:.::46c.::QBQhQRBQ -h;N3HRs_0DFosHMCNlRQ"BQ;h" -RoL7B1qi9rj;L -NRH3L0sbF0s8HR -.;ohMR_ -4;N3MR#CNP_0MC_NVDoR#4.;6n -RoMh;_. -RNM3P#NCC_M0D_VN4o#Rn.6;M -oRdh_;M +@HR@4U:U::44nU::_71jRdj7j1_d +j;N3HRs_0DFosHMCNlR1"7_jjd"N; +HFR3s8HoH'sRHkMF0 +';F@R@Ug:4:44:g::(z_71jRjjz_71j;jj +RNH3Ds0_HFsolMNCzR"7j1_j;j" +RNH3b#DFosH8RHs"FHMk;0" +RNH3sbF08NDH"sRF"k0;R +F@:@U.4j:::.j(7:p1j_jj7Rp1j_jjN; +HsR30FD_sMHoNRlC"1p7_jjj"N; +H#R3DsbFHHo8sHR"M0Fk"N; +HbR3FNs0Ds8HRk"F0 +";H@R@U4:.:.4:4::c1 QZrj4:9QR1Z4 r:Rj91 QZrj4:9N; +HsR30FD_sMHoNRlC"Z1Q +";N3HRFosH8RHs'FHMk;0' +RNH3HC8VsNsNN$Ml'CR#CHx'H; +RU@@::..4.:.:q4:r:d4jq9Rr:d4jq9Rr:d4j +9;N3HRs_0DFosHMCNlR""q;H +NRs3FHHo8sHR'M0Fk'N; +HCR38NHVs$sNMCNlR''N;R +H@:@U.4d:::.d4Mj: _Xu1Buq RMX1u_u qB;H +NR03sDs_FHNoMl"CRMu X_q1uB; " +@FR@.U:c::4.cc::)A ) RA) +);N3HRs_0DFosHMCNlR "A);)" +RNH3b#DFosH8RHs"FHMk;0" +RNH3sbF08NDH"sRF"k0;R +H@:@U.46:::.6nt:A_jjdR_Atj;dj +RNH3Ds0_HFsolMNCAR"td_jj +";F@R@Un:.:.4:n::nAjt_jAjRtj_jjN; +HsR30FD_sMHoNRlC"_Atj"jj;R +F@:@U.4(:::.(gt:Aq_BijRdjABtqid_jjN; +HsR30FD_sMHoNRlC"qAtBji_d;j" +@HR@.U:U::4.gU::qAtBji_jAjRtiqB_jjj;H +NR03sDs_FHNoMl"CRABtqij_jj +";H@R@Ug:.:.4:g::(B_pijRdjB_pij;dj +RNH3Ds0_HFsolMNCBR"pji_d;j" +@HR@dU:j::4d(j::iBp_jjjRiBp_jjj;H +NR03sDs_FHNoMl"CRB_pij"jj;R +H@:@Ud44:::d4Up:Bi1_mZBQRpmi_1;ZQ +RNH3Ds0_HFsolMNCBR"pmi_1"ZQ;R +F@:@Ud4.:::d.4B4:p7i_Qme_zBaRp7i_Qme_z +a;N3HRs_0DFosHMCNlRp"BiQ_7ez_ma +";F@R@Ud:d:d4:d::(B_pi RXuB_pi ;Xu +RNH3Ds0_HFsolMNCBR"p i_X;u" +@FR@dU:c::4dnc::zwu_RB1w_uzB +1;N3HRs_0DFosHMCNlRu"wz1_B"F; +RU@@::d646:d:Q(:ujp_d.jr:Rj9Q_upjrdj.9:jRpQu_jjdrj.:9N; +HsR30FD_sMHoNRlC"pQu_jjd"N; +HCR38NHVs$sNMCNlRb'HDd_jj +';H@R@Un:d:d4:n::dQrup.9:jRpQurj.:9uRQp:r.j +9;N3HRs_0DFosHMCNlRu"Qp +";N3HRCV8HNNss$lMNCHR'b;D' +@LR@dU:(::4d6(::q71B4ir:Rj97B1qi:r4j79R1iqBrj4:9N; +HsR30FD_sMHoNRlC"q71B;i" +RNH3b#DFosH8RHs"FHMk;0" +RNH3HC8VsNsNN$Ml'CR8O#N +';L@R@UU:d:d4:U::67BaqiaR7q;Bi +RNH3Ds0_HFsolMNC7R"aiqB"N; +H$R#Ms_0HN#004CR;R +F@:@Ud4g:::dgce:q qBRe; B +RNH3Ds0_HFsolMNCqR"e" B;R +F@:@Uc4j:::cjUe:q B_XquRe_ B ;Xu +RNH3Ds0_HFsolMNCqR"e_ B "Xu;H +NRD3#bHFsos8HRM"HF"k0;H +NRF3bsD0N8RHs"0Fk"F; +RU@@::c444:c: 4:R + ;N3HRs_0DFosHMCNlR"" ;R +H@:@Uc4.:::c.du:equReqN; +HsR30FD_sMHoNRlC"qeu"F; +RU@@::cd4d:c:ed:veqRv +q;N3HRs_0DFosHMCNlRv"eq +";H@R@Uc:c:c4:c::d)R1a);1a +RNH3Ds0_HFsolMNC)R"1;a" +@FR@cU:6::4c66::1) )aR a1 ;H +NR03sDs_FHNoMl"CR) 1a +";H@R@Un:c:c4:n::.))WRWN; +HsR30FD_sMHoNRlC"")W;R +H@:@Uc4U:::cU.B:wrj4:9BRwrj4:9BRwrj4:9N; +HsR30FD_sMHoNRlC""wB;H +NR83CHsVNsMN$NRlC''VO;R +F@:@Uc4g:::cg4qn:vqQt_1Az_q hARp qtvQqz_A1h_ q Ap;H +NR03sDs_FHNoMl"CRqtvQqz_A1h_ q Ap"F; +RU@@::6j4j:6::4UqtvQqz_A1q_7a7q_Qq)RvqQt_1Az_a7qqQ_7)N; +HsR30FD_sMHoNRlC"QqvtAq_z71_q_aq7"Q);R +F@:@U644:::64.qj:vqQt_1Az_q hA_p pRmWqtvQqz_A1h_ q Ap_Wpm;H +NR03sDs_FHNoMl"CRqtvQqz_A1h_ q Ap_Wpm"F; +RU@@::6.4.:6:Bc:QRQhBhQQ;H +NR03sDs_FHNoMl"CRBhQQ"o; +L1R7qrBij +9;N3LRLbH0F8s0H.sR;M +oR4kM_QqvtAq_z 1_hpqA __4#kJlG.N_;M NRN3#PMC_CV0_D#No46R.no; -M_RhcN; +M_Rh4N; M#R3N_PCM_C0VoDN#.4R6 n;ohMR_ -6;N3MR#CNP_0MC_NVDoR#4.;6n -RoMh;_n +.;N3MR#CNP_0MC_NVDoR#4.;6n +RoMh;_d RNM3P#NCC_M0D_VN4o#Rn.6;M -oR(h_;M +oRch_;M NRN3#PMC_CV0_D#No46R.no; -M_RhUN; +M_Rh6N; M#R3N_PCM_C0VoDN#.4R6 n;ohMR_ -g;N3MR#CNP_0MC_NVDoR#4.;6n -RoMhj_4;M +n;N3MR#CNP_0MC_NVDoR#4.;6n +RoMh;_( +RNM3P#NCC_M0D_VN4o#Rn.6;M +oRUh_;M NRN3#PMC_CV0_D#No46R.no; -M_Rh4 -4;N3MR#CNP_0MC_NVDoR#4.;6n -RoMh._4;M -NRN3#PMC_CV0_D#No46R.no; -M_Rh4 -d;N3MR#CNP_0MC_NVDoR#4.;6n -RoMhc_4;M -NRN3#PMC_CV0_D#No46R.no; -M_Rh4 -6;N3MR#CNP_0MC_NVDoR#4.;6n -RoMhn_4;M -NRN3#PMC_CV0_D#No46R.no; -M_Rh4 -(;N3MR#CNP_0MC_NVDoR#4.;6n -RoMhU_4;M -NRN3#PMC_CV0_D#No46R.no; -M_Rh4 -g;N3MR#CNP_0MC_NVDoR#4.;6n -RoMhj_.;M -NRN3#PMC_CV0_D#No46R.no; -M_Rh. -4;N3MR#CNP_0MC_NVDoR#4.;6n -RoMh._.;M -NRN3#PMC_CV0_D#No46R.no; -M_Rh. -d;N3MR#CNP_0MC_NVDoR#4.;6n -RoMhc_.;M -NRN3#PMC_CV0_D#No46R.no; -M_Rh. -6;N3MR#CNP_0MC_NVDoR#4.;6n -RoMhn_.;M -NRN3#PMC_CV0_D#No46R.no; -M_Rh. -(;N3MR#CNP_0MC_NVDoR#4.;6n -RoMhU_.;M -NRN3#PMC_CV0_D#No46R.no; -M_Rh4;d. +M_RhgN; +M#R3N_PCM_C0VoDN#.4R6 +n;ohMR_;4j +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR4h_4N; +M#R3N_PCM_C0VoDN#.4R6 +n;ohMR_;4. +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR4h_dN; +M#R3N_PCM_C0VoDN#.4R6 +n;ohMR_;4c +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR4h_6N; +M#R3N_PCM_C0VoDN#.4R6 +n;ohMR_;4n +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR4h_(N; +M#R3N_PCM_C0VoDN#.4R6 +n;ohMR_;4U +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR4h_gN; +M#R3N_PCM_C0VoDN#.4R6 +n;ohMR_;.j +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR.h_4N; +M#R3N_PCM_C0VoDN#.4R6 +n;ohMR_;.. +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR.h_dN; +M#R3N_PCM_C0VoDN#.4R6 +n;ohMR_;.c +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR.h_6N; +M#R3N_PCM_C0VoDN#.4R6 +n;ohMR_;.n +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR.h_(N; +M#R3N_PCM_C0VoDN#.4R6 +n;ohMR_;.U RNM3P#NCC_M0D_VN4o#Rn.6;M oR4h_d -d;N3MR#CNP_0MC_NVDoR#4.;6n -RoMhn_4UN; +(;N3MR#CNP_0MC_NVDoR#4.;6n +RoMhn_4.N; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_44(;M +n;ohMR_d4n;M NRN3#PMC_CV0_D#No46R.no; -MbROk#_C0__j4k_3M +M_Rh4;nc +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR4h_n +6;N3MR#CNP_0MC_NVDoR#4.;6n +RoMh(_4UN; +M#R3N_PCM_C0VoDN#.4R6 +n;ohMR_U4U;M +NRN3#PMC_CV0_D#No46R.no; +M_Rh4;g4 +RNM3P#NCC_M0D_VN4o#Rn.6;M +oRN#00lC_NHOEM3C\z_71j_jjQ_ha6__jlk.3M d;N3MR#CNP_0MC_NVDoR#4.;6n -RoMO_bkC_#0j__434kM;M +RoM#00NCN_lOMEHCz\37j1_jQj_h6a__lj_.M3k4N; +M#R3N_PCM_C0VoDN#.4R6 +n;o#MR0CN0_OlNECHM\73z1j_jjh_Qa__6j._l3jkM;M +NRN3#PMC_CV0_D#No46R.no; +MuReqY_1hjB_3dkM;M +NRN3#PMC_CV0_D#No46R.no; +MuReqY_1hjB_34kM;M +NRN3#PMC_CV0_D#No46R.no; +MuReqY_1hjB_3jkM;M +NRN3#PMC_CV0_D#No46R.no; +MvRqQ_tqA_z1 Ahqpj _3dkM;M +NRN3#PMC_CV0_D#No46R.no; +MvRqQ_tqA_z1 Ahqpj _34kM;M +NRN3#PMC_CV0_D#No46R.no; +MvRqQ_tqA_z1 Ahqpj _3jkM;M +NRN3#PMC_CV0_D#No46R.no; +M7Rz1j_jjh_Qa3_jk;Md +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR1z7_jjj_aQh_kj3M +4;N3MR#CNP_0MC_NVDoR#4.;6n +RoMz_71j_jjQ_hajM3kjN; +M#R3N_PCM_C0VoDN#.4R6 +n;opMR7j1_jQj_hja_3dkM;M +NRN3#PMC_CV0_D#No46R.no; +M7Rp1j_jjh_Qa3_jk;M4 +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR1p7_jjj_aQh_kj3M +j;N3MR#CNP_0MC_NVDoR#4.;6n +RoMe_vqQ_hajM3kdN; +M#R3N_PCM_C0VoDN#.4R6 +n;oeMRvQq_hja_34kM;M +NRN3#PMC_CV0_D#No46R.no; +MvReqh_Qa3_jk;Mj +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR_Atj_jjjM3kdN; +M#R3N_PCM_C0VoDN#.4R6 +n;oAMRtj_jj3_jk;M4 +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR_Atj_jjjM3kjN; +M#R3N_PCM_C0VoDN#.4R6 +n;oAMRtiqB_jjd_aQh_kj3M +d;N3MR#CNP_0MC_NVDoR#4.;6n +RoMABtqid_jjh_Qa3_jk;M4 +RNM3P#NCC_M0D_VN4o#Rn.6;M +oRqAtBji_dQj_hja_3jkM;M +NRN3#PMC_CV0_D#No46R.no; +M1Rq_jjj_aQh_kj3M +d;N3MR#CNP_0MC_NVDoR#4.;6n +RoMqj1_jQj_hja_34kM;M +NRN3#PMC_CV0_D#No46R.no; +M1Rq_jjj_aQh_kj3M +j;N3MR#CNP_0MC_NVDoR#4.;6n +RoMO_bkC_#0j__43dkM;M NRN3#PMC_CV0_D#No46R.no; MbROk#_C0__j4k_3M +4;N3MR#CNP_0MC_NVDoR#4.;6n +RoMO_bkC_#0j__43jkM;M +NRN3#PMC_CV0_D#No46R.no; +MbROk#_C0__j.k_3M +d;N3MR#CNP_0MC_NVDoR#4.;6n +RoMO_bkC_#0j__.34kM;M +NRN3#PMC_CV0_D#No46R.no; +MbROk#_C0__j.k_3M j;N3MR#CNP_0MC_NVDoR#4.;6n RoMO_bkC_#0j__d3dkM;M NRN3#PMC_CV0_D#No46R.no; @@ -472,89 +523,35 @@ RoMQ_upj_djj__.34kM;M NRN3#PMC_CV0_D#No46R.no; MuRQpd_jj__j.k_3M j;N3MR#CNP_0MC_NVDoR#4.;6n -RoMz_71j_jjQ_hajM3kdN; +RoMqj1_djj_j1j_Y_hBjM3kdN; M#R3N_PCM_C0VoDN#.4R6 -n;ozMR7j1_jQj_hja_34kM;M +n;oqMR1d_jjj_jjY_1hjB_34kM;M NRN3#PMC_CV0_D#No46R.no; -M7Rz1j_jjh_Qa3_jk;Mj +M1Rq_jjd_jjj_h1YB3_jk;Mj RNM3P#NCC_M0D_VN4o#Rn.6;M -oRqeu_h1YB3_jk;Md -RNM3P#NCC_M0D_VN4o#Rn.6;M -oRqeu_h1YB3_jk;M4 -RNM3P#NCC_M0D_VN4o#Rn.6;M -oRqeu_h1YB3_jk;Mj -RNM3P#NCC_M0D_VN4o#Rn.6;M -oR_q1j_jjQ_hajM3kdN; +oRq7aB1i_Y_hBjM3kdN; M#R3N_PCM_C0VoDN#.4R6 -n;oqMR1j_jjh_Qa3_jk;M4 +n;o7MRaiqB_h1YB3_jk;M4 RNM3P#NCC_M0D_VN4o#Rn.6;M -oR_q1j_jjQ_hajM3kjN; +oRq7aB1i_Y_hBjM3kjN; M#R3N_PCM_C0VoDN#.4R6 -n;oAMRtiqB_jjd_aQh_kj3M -d;N3MR#CNP_0MC_NVDoR#4.;6n -RoMABtqid_jjh_Qa3_jk;M4 +n;owMRuBz_1h_Qa3_jk;Md RNM3P#NCC_M0D_VN4o#Rn.6;M -oRqAtBji_dQj_hja_3jkM;M -NRN3#PMC_CV0_D#No46R.no; -MvReqh_Qa3_jk;Md -RNM3P#NCC_M0D_VN4o#Rn.6;M -oRqev_aQh_kj3M -4;N3MR#CNP_0MC_NVDoR#4.;6n -RoMe_vqQ_hajM3kjN; +oRzwu__B1Q_hajM3k4N; M#R3N_PCM_C0VoDN#.4R6 -n;oOMRbCk_#j0__3._k;Md -RNM3P#NCC_M0D_VN4o#Rn.6;M -oRkOb_0C#_.j__M3k4N; -M#R3N_PCM_C0VoDN#.4R6 -n;oOMRbCk_#j0__3._k;Mj +n;owMRuBz_1h_Qa3_jk;Mj RNM3P#NCC_M0D_VN4o#Rn.6;M oRq71BQi_hja__34_k;Md RNM3P#NCC_M0D_VN4o#Rn.6;M oRq71BQi_hja__34_k;M4 RNM3P#NCC_M0D_VN4o#Rn.6;M oRq71BQi_hja__34_k;Mj -RNM3P#NCC_M0D_VN4o#Rn.6;M -oR_Atj_jjjM3kdN; -M#R3N_PCM_C0VoDN#.4R6 -n;oAMRtj_jj3_jk;M4 -RNM3P#NCC_M0D_VN4o#Rn.6;M -oR_Atj_jjjM3kjN; -M#R3N_PCM_C0VoDN#.4R6 -n;oqMRvqQt_1Az_q hA_p jM3kdN; -M#R3N_PCM_C0VoDN#.4R6 -n;oqMRvqQt_1Az_q hA_p jM3k4N; -M#R3N_PCM_C0VoDN#.4R6 -n;oqMRvqQt_1Az_q hA_p jM3kjN; -M#R3N_PCM_C0VoDN#.4R6 -n;oqMR1d_jjj_jjY_1hjB_3dkM;M -NRN3#PMC_CV0_D#No46R.no; -M1Rq_jjd_jjj_h1YB3_jk;M4 -RNM3P#NCC_M0D_VN4o#Rn.6;M -oR_q1j_djj_jj1BYh_kj3M -j;N3MR#CNP_0MC_NVDoR#4.;6n -RoMw_uzBQ1_hja_3dkM;M -NRN3#PMC_CV0_D#No46R.no; -MuRwz1_B_aQh_kj3M -4;N3MR#CNP_0MC_NVDoR#4.;6n -RoMw_uzBQ1_hja_3jkM;M -NRN3#PMC_CV0_D#No46R.no; -MaR7q_Bi1BYh_kj3M -d;N3MR#CNP_0MC_NVDoR#4.;6n -RoM7BaqiY_1hjB_34kM;M -NRN3#PMC_CV0_D#No46R.no; -MaR7q_Bi1BYh_kj3M -j;N3MR#CNP_0MC_NVDoR#4.;6n -RoMp_71j_jjQ_hajM3kdN; -M#R3N_PCM_C0VoDN#.4R6 -n;opMR7j1_jQj_hja_34kM;M -NRN3#PMC_CV0_D#No46R.no; -M7Rp1j_jjh_Qa3_jk;Mj RNM3P#NCC_M0D_VN4o#Rn.6;R -b@:@44::44+:.406:sRkCfjj:Rk0sCsR0keCRB -B;b@R@4::44::4.6+4:DVN#fCRjR:jV#NDCNRVDR#Ct;h7 -@bR@4U:U.d::d4U:4d+6v:1_Qqvtjqr:R(9fjj:RFoE#10Rvv_qQrtqj9:(R.h_4_,h.h.,_,.dhc_.,.h_6_,h.hn,_,.(hU_.;H +b@:@44::44+:.40c:sRkCfjj:Rk0sCsR0keCRB +B;b@R@4::44::4.c+4:DVN#fCRjR:jV#NDCNRVDR#Ct;h7 +@bR@4U:U.6::64U:4d+cv:1_Qqvtjqr:R(9fjj:RFoE#10Rvv_qQrtqj9:(R.h_4_,h.h.,_,.dhc_.,.h_6_,h.hn,_,.(hU_.;H NR03sD0C_F;R4 -RNH#_$MV_#lH"8R(d4U.d4U4 +RNH#_$MV_#lH"8R(64U.64U4 ";N3HRs_0DFosHMCNlRv"1_Qqvt;q" RNH3lV#_FVslR#0"_1vqtvQq"Rd;H NR#3VlF_0#"0R1qv_vqQtR;U" @@ -562,1508 +559,1232 @@ RNH3lV#_L0ND0C#Rj"jjjR4jjjjjjjsjj4R4jjjjsjjjR4jjjj4jjjjs4j4Rjjj4jjjjjs4jjRjjjj4j RNH3lV#_HFsolMNC1R"vv_qQ"tq;H NR#3Vl0_#Ns0CC4oR;H NR03#N_0ClbNbHRMo"RRRjjjjj4jjRR->jjjjj4jj\RMRRjjjj4jjj>R-Rjjjj4jjjR\MRjRjj4jjj-jR>jRjj4jjjMj\RjRRj4jjjRjj-j>Rj4jjj\jjMRRRj4jjjjjjRR->j4jjjjjj\RMRR4jjjjjjj>R-R4jjjjjjjR\MR4Rjjjjjj-jR>4RjjjjjjMj\R4RRjjjjjRjj-4>Rjjjjj\jjM -";s@R@U4:.c6:.:c.4:+c.416:vv_qQrtqj9:(R:fjjNRlO7ERw]w)RHbslvR1_Qqvtnqr9T -S=_1vqtvQq9rn -=S71qv_vqQt_rM#4S9 -B=piB_pimQ1Z_SO -)1=)a;_H -RNH3Ds0CF_0R -4;N#HR$VM_#Hl_8(R"4.Ud44Ud"N; -HsR30FD_sMHoNRlC"_1vqtvQq -";N3HRV_#lVlsF#"0R1qv_vqQtR;d" -RNH3lV#_#0F01R"vv_qQRtqU -";N3HRV_#l0DNLCR#0"jjjRj4jjjjjjjsj44Rjjjjjjjjs4jjRjj4jjsjjjR44j4jjjjjjsj4jRjjjjj4jjjs44jRjj4jjj4js4jjRjjjjjs4j4R44jjjjj4jjs -";N3HRV_#lFosHMCNlRv"1_Qqvt;q" -RNH3lV#_N#00CCso;R4 -RNH3HFso#HM0lMNC1R'vv_qQrtqj9:('s; -RU@@:n.g:.c:g.n:j6+4:_1vqtvQq:rj(f9RjR:jlENORw7w)b]RsRHl1qv_vqQtr -69S1T=vv_qQrtq6S9 -7v=1_QqvtMq_#9r. -pSBip=Bi1_mZOQ_ -=S))_1aHN; -HsR30_DC04FR;H -NRM#$_lV#_RH8"U(4dU.4d;4" -RNH3Ds0_HFsolMNC1R"vv_qQ"tq;H -NR#3Vls_VF0l#Rv"1_QqvtdqR"N; -HVR3#0l_FR#0"_1vqtvQq"RU;H -NR#3VlN_0L#DC0jR"j4jRjjjjjsjjjRj4jj4jjjjjsjj4R4jjjjjjj4sj4jRjjj4jj4jsjjjRj4jjjsjj4Rj4jjjjjj4jsj44Rjjjj4jjj4s44jRjjjjjj"4s;H -NR#3Vls_FHNoMl"CR1qv_vqQt"N; -HVR3##l_0CN0sRCo4N; -HFR3sHHoMM#0NRlC'_1vqtvQq:rj(;9' -@sR@dU:jcj::jdj:+.j416:vv_qQrtqj9:(R:fjjNRlO7ERw]w)RHbslvR1_Qqvtcqr9T -S=_1vqtvQq9rc -=S7h._U_SH -B=piB_pimQ1Z_SO -)1=)a;_H -RNH3Ds0CF_0R -4;N#HR$VM_#Hl_8(R"4.Ud44Ud"N; -HsR30FD_sMHoNRlC"_1vqtvQq -";N3HRV_#lVlsF#"0R1qv_vqQtR;d" -RNH3lV#_#0F01R"vv_qQRtqU -";N3HRV_#l0DNLCR#0"jjjRj4jjjjjjjsj44Rjjjjjjjjs4jjRjj4jjsjjjR44j4jjjjjjsj4jRjjjjj4jjjs44jRjj4jjj4js4jjRjjjjjs4j4R44jjjjj4jjs -";N3HRV_#lFosHMCNlRv"1_Qqvt;q" -RNH3lV#_N#00CCso;R4 -RNH3HFso#HM0lMNC1R'vv_qQrtqj9:('s; -RU@@:nd4:dc:4.n:c6+4:_1vqtvQq:rj(f9RjR:jlENORw7w)b]RsRHl1qv_vqQtr -d9S1T=vv_qQrtqdS9 -7_=hUHc_ -pSBip=Bi1_mZOQ_ -=S))_1aHN; -HsR30_DC04FR;H -NRM#$_lV#_RH8"U(4dU.4d;4" -RNH3Ds0_HFsolMNC1R"vv_qQ"tq;H -NR#3Vls_VF0l#Rv"1_QqvtdqR"N; -HVR3#0l_FR#0"_1vqtvQq"RU;H -NR#3VlN_0L#DC0jR"j4jRjjjjjsjjjRj4jj4jjjjjsjj4R4jjjjjjj4sj4jRjjj4jj4jsjjjRj4jjjsjj4Rj4jjjjjj4jsj44Rjjjj4jjj4s44jRjjjjjj"4s;H -NR#3Vls_FHNoMl"CR1qv_vqQt"N; -HVR3##l_0CN0sRCo4N; -HFR3sHHoMM#0NRlC'_1vqtvQq:rj(;9' -@sR@dU:.cU::Ud.:+..416:vv_qQrtqj9:(R:fjjNRlO7ERw]w)RHbslvR1_Qqvt.qr9T -S=_1vqtvQq9r. -=S71qv_vqQt_rM#6S9 -B=piB_pimQ1Z_SO -)1=)a;_H -RNH3Ds0CF_0R -4;N#HR$VM_#Hl_8(R"4.Ud44Ud"N; -HsR30FD_sMHoNRlC"_1vqtvQq -";N3HRV_#lVlsF#"0R1qv_vqQtR;d" -RNH3lV#_#0F01R"vv_qQRtqU -";N3HRV_#l0DNLCR#0"jjjRj4jjjjjjjsj44Rjjjjjjjjs4jjRjj4jjsjjjR44j4jjjjjjsj4jRjjjjj4jjjs44jRjj4jjj4js4jjRjjjjjs4j4R44jjjjj4jjs -";N3HRV_#lFosHMCNlRv"1_Qqvt;q" -RNH3lV#_N#00CCso;R4 -RNH3HFso#HM0lMNC1R'vv_qQrtqj9:('s; -RU@@:.dd:dc:d..:d6+4:_1vqtvQq:rj(f9RjR:jlENORw7w)b]RsRHl1qv_vqQtr -49S1T=vv_qQrtq4S9 -7_=hUH(_ -pSBip=Bi1_mZOQ_ -=S))_1aHN; -HsR30_DC04FR;H -NRM#$_lV#_RH8"U(4dU.4d;4" -RNH3Ds0_HFsolMNC1R"vv_qQ"tq;H -NR#3Vls_VF0l#Rv"1_QqvtdqR"N; -HVR3#0l_FR#0"_1vqtvQq"RU;H -NR#3VlN_0L#DC0jR"j4jRjjjjjsjjjRj4jj4jjjjjsjj4R4jjjjjjj4sj4jRjjj4jj4jsjjjRj4jjjsjj4Rj4jjjjjj4jsj44Rjjjj4jjj4s44jRjjjjjj"4s;H -NR#3Vls_FHNoMl"CR1qv_vqQt"N; -HVR3##l_0CN0sRCo4N; -HFR3sHHoMM#0NRlC'_1vqtvQq:rj(;9' -@sR@dU:dc(::(dd:+..416:vv_qQrtqj9:(R:fjjNRlO7ERw]w)RHbslvR1_Qqvtjqr9T -S=_1vqtvQq9rj -=S71qv_vqQt_rM#(S9 -B=piB_pimQ1Z_SO -)1=)a;_H -RNH3Ds0CF_0R -4;N#HR$VM_#Hl_8(R"4.Ud44Ud"N; -HsR30FD_sMHoNRlC"_1vqtvQq -";N3HRV_#lVlsF#"0R1qv_vqQtR;d" -RNH3lV#_#0F01R"vv_qQRtqU -";N3HRV_#l0DNLCR#0"jjjRj4jjjjjjjsj44Rjjjjjjjjs4jjRjj4jjsjjjR44j4jjjjjjsj4jRjjjjj4jjjs44jRjj4jjj4js4jjRjjjjjs4j4R44jjjjj4jjs -";N3HRV_#lFosHMCNlRv"1_Qqvt;q" -RNH3lV#_N#00CCso;R4 -RNH3HFso#HM0lMNC1R'vv_qQrtqj9:('s; -RU@@:U44::d.4:4Ud4c+6b:Ok#_C0:rdjf9RjR:jlENORw7wRHbslbROk#_C09r4 -=STO_bkCr#04S9 -7_=h4S6 -B=piB_pimQ1Z_ -O;N3HRs_0DFosHMCNlRb"Ok#_C0 -";N3HRksMVNHO_MG8CR -4;N3HR#_$MH0MHPRND";j" -@sR@4U:4dU:.4:4Uc:d+:46O_bkCr#0d9:jR:fjjNRlO7ERwbwRsRHlO_bkCr#0.S9 -Tb=Ok#_C09r. -=S7hn_4 -pSBip=Bi1_mZOQ_;H -NR03sDs_FHNoMl"CRO_bkC"#0;H -NRM3kVOsN_8HMC.GR;H -NR$3#MM_HHN0PDjR""s; -RU@@:U44::d.4:4Ud4c+6b:Ok#_C0:rdjf9RjR:jlENORw7wRHbslbROk#_C09rd -=STO_bkCr#0dS9 -7_=h4S( -B=piB_pimQ1Z_ -O;N3HRs_0DFosHMCNlRb"Ok#_C0 -";N3HRksMVNHO_MG8CR -d;N3HR#_$MH0MHPRND";j" -@sR@4U:j6g:.j:4g6:6+:46Q_upjrdj.9:jR:fjjNRlO7ERw]w1RHbsluRQpd_jjw7w1j]r9T -S=pQu_jjd_jOr97 -S=4h_UB -SpBi=pmi_1_ZQO1 -S=a)1_ -H;N3HRs_0DFosHMCNlRu"Qpd_jj -";N3HRksMVNHO_MG8CR -j;s@R@Uj:4g.:6:g4j:+664Q6:ujp_d.jr:Rj9fjj:ROlNEwR7wR1]blsHRpQu_jjd71ww]9r4 -=STQ_upj_djO9r4 -=S7hg_4 +";s@R@Uj:4g.:6:g4j:+664Qc:ujp_d.jr:Rj9fjj:ROlNEwR7wR1]blsHRpQu_jjd71ww]9rj +=STQ_upj_djO9rj +=S7hU_4 pSBip=Bi1_mZOQ_ =S1)_1aHN; HsR30FD_sMHoNRlC"pQu_jjd"N; -HkR3MNVsOM_H8RCG4s; -RU@@:g4j::6.4:jg646+6u:Qpd_jj:r.jf9RjR:jlENORw7w1b]RsRHlQ_upj7djw]w1r -.9SQT=ujp_dOj_r -.9Sh7=_ -.jSiBp=iBp_Zm1Q +HkR3MNVsOM_H8RCGjs; +RU@@:g4j::6.4:jg646+cu:Qpd_jj:r.jf9RjR:jlENORw7w1b]RsRHlQ_upj7djw]w1r +49SQT=ujp_dOj_r +49Sh7=_ +4gSiBp=iBp_Zm1Q _OS)1=1Ha_;H NR03sDs_FHNoMl"CRQ_upj"dj;H -NRM3kVOsN_8HMC.GR;R -s@:@U.:4cc.(:4nc:c6+4:_1vqtvQq:rj(f9RjR:jlENORw7w1b]RsRHl1qv_vqQtr -(9S1T=vv_qQrtq(S9 -7_=h(HU_ -pSBip=Bi1_mZOQ_ -=S1)_1aHN; -HsR30_DC04FR;H -NRM#$_lV#_RH8"U(4dU.4d;4" -RNH3Ds0_HFsolMNC1R"vv_qQ"tq;H -NR#3Vls_VF0l#Rv"1_QqvtdqR"N; -HVR3#0l_FR#0"_1vqtvQq"RU;H -NR#3VlN_0L#DC0jR"j4jRjjjjjsjjjRj4jj4jjjjjsjj4R4jjjjjjj4sj4jRjjj4jj4jsjjjRj4jjjsjj4Rj4jjjjjj4jsj44Rjjjj4jjj4s44jRjjjjjj"4s;H -NR#3Vls_FHNoMl"CR1qv_vqQt"N; -HVR3##l_0CN0sRCo4N; -HFR3sHHoMM#0NRlC'_1vqtvQq:rj(;9' -@sR@4U:j6g:.j:4g6:6+:46e_vqQRhafjj:ROlNEwR7wR1]blsHRqev_aQh -=STe_vqQ -haSh7=_ -44SiBp=iBp_Zm1Q +NRM3kVOsN_8HMC4GR;R +s@:@U4:jg64.:j6g:6c+4:pQu_jjdrj.:9jRf:ljRNROE71ww]sRbHQlRujp_dwj7wr1].S9 +Tu=Qpd_jjr_O.S9 +7_=h.Sj +B=piB_pimQ1Z_SO +11=)a;_H +RNH3Ds0_HFsolMNCQR"ujp_d;j" +RNH3VkMs_NOHCM8G;R. +@sR@.U:4.n:64:.n.:c+:4c1qv_vqQtr(j:9jRf:ljRNROE71ww]sRbH1lRvv_qQrtq(S9 +Tv=1_Qqvt(qr97 +S=_1vqtvQq#_Mr +j9SiBp=iBp_Zm1Q +_OS)1=1Ha_;H +NR03sD0C_F;R4 +RNH#_$MV_#lH"8R(64U.64U4 +";N3HRs_0DFosHMCNlRv"1_Qqvt;q" +RNH3lV#_FVslR#0"_1vqtvQq"Rd;H +NR#3VlF_0#"0R1qv_vqQtR;U" +RNH3lV#_L0ND0C#Rj"jjjR4jjjjjjjsjj4R4jjjjsjjjR4jjjj4jjjjs4j4Rjjj4jjjjjs4jjRjjjj4j4jsjj4Rjjjj4sjj4R4jjjjjjjj4s444Rjjjjjjj4;s" +RNH3lV#_HFsolMNC1R"vv_qQ"tq;H +NR#3Vl0_#Ns0CC4oR;H +NRs3FHMoH#N0Ml'CR1qv_vqQtr(j:9 +';s@R@Un:.U::c.:nU44g+cv:1_Qqvtjqr:R(9fjj:ROlNEwR7wR)]blsHR_1vqtvQq9rn +=ST1qv_vqQtr +n9Sh7=__(UHB +SpBi=pmi_1_ZQO) +S=a)1_ +H;N3HRsC0D_R0F4N; +H$R#M#_Vl8_HR4"(U46.U"64;H +NR03sDs_FHNoMl"CR1qv_vqQt"N; +HVR3#Vl_s#Fl01R"vv_qQRtqd +";N3HRV_#l00F#Rv"1_QqvtUqR"N; +HVR3#0l_NCLD#"0RjRjj4jjjjjjjs4jjRjj4jjjjj4sjjjRj4jjjjjjs4j4Rjjj4jsjj4Rjjjjjj4jjjs44jRjjjjjj4j4s4jjRjjjjj44js4j4Rjjjjjsj4"N; +HVR3#Fl_sMHoNRlC"_1vqtvQq +";N3HRV_#l#00NCosCR +4;N3HRFosHH0M#MCNlRv'1_Qqvtjqr:'(9;R +s@:@U.:UjcU:.jj:.+:4c1qv_vqQtr(j:9jRf:ljRNROE7)ww]sRbH1lRvv_qQrtq6S9 +Tv=1_Qqvt6qr97 +S=Uh_j +_HSiBp=iBp_Zm1Q +_OS))=1Ha_;H +NR03sD0C_F;R4 +RNH#_$MV_#lH"8R(64U.64U4 +";N3HRs_0DFosHMCNlRv"1_Qqvt;q" +RNH3lV#_FVslR#0"_1vqtvQq"Rd;H +NR#3VlF_0#"0R1qv_vqQtR;U" +RNH3lV#_L0ND0C#Rj"jjjR4jjjjjjjsjj4R4jjjjsjjjR4jjjj4jjjjs4j4Rjjj4jjjjjs4jjRjjjj4j4jsjj4Rjjjj4sjj4R4jjjjjjjj4s444Rjjjjjjj4;s" +RNH3lV#_HFsolMNC1R"vv_qQ"tq;H +NR#3Vl0_#Ns0CC4oR;H +NRs3FHMoH#N0Ml'CR1qv_vqQtr(j:9 +';s@R@Ug:.g::c.:gg.4j+cv:1_Qqvtjqr:R(9fjj:ROlNEwR7wR)]blsHR_1vqtvQq9rc +=ST1qv_vqQtr +c9Sh7=__U.HB +SpBi=pmi_1_ZQO) +S=a)1_ +H;N3HRsC0D_R0F4N; +H$R#M#_Vl8_HR4"(U46.U"64;H +NR03sDs_FHNoMl"CR1qv_vqQt"N; +HVR3#Vl_s#Fl01R"vv_qQRtqd +";N3HRV_#l00F#Rv"1_QqvtUqR"N; +HVR3#0l_NCLD#"0RjRjj4jjjjjjjs4jjRjj4jjjjj4sjjjRj4jjjjjjs4j4Rjjj4jsjj4Rjjjjjj4jjjs44jRjjjjjj4j4s4jjRjjjjj44js4j4Rjjjjjsj4"N; +HVR3#Fl_sMHoNRlC"_1vqtvQq +";N3HRV_#l#00NCosCR +4;N3HRFosHH0M#MCNlRv'1_Qqvtjqr:'(9;R +s@:@Ud:46c4:d6c:.+:4c1qv_vqQtr(j:9jRf:ljRNROE7)ww]sRbH1lRvv_qQrtqdS9 +Tv=1_Qqvtdqr97 +S=Uh_c +_HSiBp=iBp_Zm1Q +_OS))=1Ha_;H +NR03sD0C_F;R4 +RNH#_$MV_#lH"8R(64U.64U4 +";N3HRs_0DFosHMCNlRv"1_Qqvt;q" +RNH3lV#_FVslR#0"_1vqtvQq"Rd;H +NR#3VlF_0#"0R1qv_vqQtR;U" +RNH3lV#_L0ND0C#Rj"jjjR4jjjjjjjsjj4R4jjjjsjjjR4jjjj4jjjjs4j4Rjjj4jjjjjs4jjRjjjj4j4jsjj4Rjjjj4sjj4R4jjjjjjjj4s444Rjjjjjjj4;s" +RNH3lV#_HFsolMNC1R"vv_qQ"tq;H +NR#3Vl0_#Ns0CC4oR;H +NRs3FHMoH#N0Ml'CR1qv_vqQtr(j:9 +';s@R@U.:d(::cd:.(.4.+cv:1_Qqvtjqr:R(9fjj:ROlNEwR7wR)]blsHR_1vqtvQq9r. +=ST1qv_vqQtr +.9S17=vv_qQ_tqM6#r9B +SpBi=pmi_1_ZQO) +S=a)1_ +H;N3HRsC0D_R0F4N; +H$R#M#_Vl8_HR4"(U46.U"64;H +NR03sDs_FHNoMl"CR1qv_vqQt"N; +HVR3#Vl_s#Fl01R"vv_qQRtqd +";N3HRV_#l00F#Rv"1_QqvtUqR"N; +HVR3#0l_NCLD#"0RjRjj4jjjjjjjs4jjRjj4jjjjj4sjjjRj4jjjjjjs4j4Rjjj4jsjj4Rjjjjjj4jjjs44jRjjjjjj4j4s4jjRjjjjj44js4j4Rjjjjjsj4"N; +HVR3#Fl_sMHoNRlC"_1vqtvQq +";N3HRV_#l#00NCosCR +4;N3HRFosHH0M#MCNlRv'1_Qqvtjqr:'(9;R +s@:@Ud:d4cd:d4d:.+:4c1qv_vqQtr(j:9jRf:ljRNROE7)ww]sRbH1lRvv_qQrtq4S9 +Tv=1_Qqvt4qr97 +S=dh_gB +SpBi=pmi_1_ZQO) +S=a)1_ +H;N3HRsC0D_R0F4N; +H$R#M#_Vl8_HR4"(U46.U"64;H +NR03sDs_FHNoMl"CR1qv_vqQt"N; +HVR3#Vl_s#Fl01R"vv_qQRtqd +";N3HRV_#l00F#Rv"1_QqvtUqR"N; +HVR3#0l_NCLD#"0RjRjj4jjjjjjjs4jjRjj4jjjjj4sjjjRj4jjjjjjs4j4Rjjj4jsjj4Rjjjjjj4jjjs44jRjjjjjj4j4s4jjRjjjjj44js4j4Rjjjjjsj4"N; +HVR3#Fl_sMHoNRlC"_1vqtvQq +";N3HRV_#l#00NCosCR +4;N3HRFosHH0M#MCNlRv'1_Qqvtjqr:'(9;R +s@:@Ud:cjcc:dj.:.+:4c1qv_vqQtr(j:9jRf:ljRNROE7)ww]sRbH1lRvv_qQrtqjS9 +Tv=1_Qqvtjqr97 +S=_1vqtvQq#_Mr +(9SiBp=iBp_Zm1Q +_OS))=1Ha_;H +NR03sD0C_F;R4 +RNH#_$MV_#lH"8R(64U.64U4 +";N3HRs_0DFosHMCNlRv"1_Qqvt;q" +RNH3lV#_FVslR#0"_1vqtvQq"Rd;H +NR#3VlF_0#"0R1qv_vqQtR;U" +RNH3lV#_L0ND0C#Rj"jjjR4jjjjjjjsjj4R4jjjjsjjjR4jjjj4jjjjs4j4Rjjj4jjjjjs4jjRjjjj4j4jsjj4Rjjjj4sjj4R4jjjjjjjj4s444Rjjjjjjj4;s" +RNH3lV#_HFsolMNC1R"vv_qQ"tq;H +NR#3Vl0_#Ns0CC4oR;H +NRs3FHMoH#N0Ml'CR1qv_vqQtr(j:9 +';s@R@U.:4U::.4:.Udc+4:iBp_aBhrj4:9jRf:ljRNROE7RwwblsHRiBp_aBhr +j9SBT=pBi_hjar97 +S= OD\p3Bih_Bar_djS9 +B=piB_pimQ1Z_ +O;N3HRs_0DFosHMCNlRp"Bih_Ba +";N3HRksMVNHO_MG8CR +j;N3HR#_$MH0MHPRND";j" +@sR@4U:..U::U4.:4d+cp:Bih_Ba:r4jf9RjR:jlENORw7wRHbslpRBih_Ba9r4 +=STB_piBrha4S9 +7D=O B\3pBi_hda_r +49SiBp=iBp_Zm1Q;_O +RNH3Ds0_HFsolMNCBR"pBi_h;a" +RNH3VkMs_NOHCM8G;R4 +RNH3M#$_HHM0DPNR""j;R +s@:@U4:4gd4.:4dg:cc+4:kOb_0C#rjd:9jRf:ljRNROE7RwwblsHRkOb_0C#r +j9SOT=bCk_#j0r97 +S=4h_cB +SpBi=pmi_1_ZQON; +HsR30FD_sMHoNRlC"kOb_0C#"N; +HkR3MNVsOM_H8RCGjN; +H#R3$HM_MPH0N"DRj +";s@R@U4:4g.:d:g44:+dc4Oc:bCk_#d0r:Rj9fjj:ROlNEwR7wsRbHOlRbCk_#40r9T +S=kOb_0C#r +49Sh7=_ +46SiBp=iBp_Zm1Q;_O +RNH3Ds0_HFsolMNCOR"bCk_#;0" +RNH3VkMs_NOHCM8G;R4 +RNH3M#$_HHM0DPNR""j;R +s@:@U4:4gd4.:4dg:cc+4:kOb_0C#rjd:9jRf:ljRNROE7RwwblsHRkOb_0C#r +.9SOT=bCk_#.0r97 +S=4h_nB +SpBi=pmi_1_ZQON; +HsR30FD_sMHoNRlC"kOb_0C#"N; +HkR3MNVsOM_H8RCG.N; +H#R3$HM_MPH0N"DRj +";s@R@U4:4g.:d:g44:+dc4Oc:bCk_#d0r:Rj9fjj:ROlNEwR7wsRbHOlRbCk_#d0r9T +S=kOb_0C#r +d9Sh7=_ +4(SiBp=iBp_Zm1Q;_O +RNH3Ds0_HFsolMNCOR"bCk_#;0" +RNH3VkMs_NOHCM8G;Rd +RNH3M#$_HHM0DPNR""j;R +s@:@U4:U6.U:46+:d4zc:7j1_jQj_hfaRjR:jlENORw7w1b]RsRHlz_71j_jjQ +haSzT=7j1_jQj_hSa +7_=h(B +SpBi=pmi_1_ZQO1 +S=a)1_ +H;N3HRs_0DFosHMCNlR7"z1j_jjh_Qa +";N3HR#_$MH0MHPRND";4" +RNH3_HMDbFFR +4;s@R@UU:46::.4:U6dc+4:1p7_jjj_aQhR:fjjNRlO7ERw]w1RHbsl7Rp1j_jjh_QaT +S=1p7_jjj_aQh +=S7h +_USiBp=iBp_Zm1Q +_OS)1=1Ha_;H +NR03sDs_FHNoMl"CRp_71j_jjQ"ha;H +NR$3#MM_HHN0PD4R""N; +HHR3MF_DF.bR;R +s@:@U4:jg64.:j6g:6c+4:qev_aQhR:fjjNRlO7ERw]w1RHbslvReqh_QaT +S=qev_aQh +=S7h +_gSiBp=iBp_Zm1Q _OS)1=1Ha_;H NR03sDs_FHNoMl"CRe_vqQ"ha;H NR$3#MM_HHN0PD4R""N; HHR3MF_DF(bR;R -s@:@U4:jg64.:j6g:66+4:qAtBji_dQj_hfaRjR:jlENORw7w1b]RsRHlABtqid_jjh_QaT -S=qAtBji_dQj_hSa -7_=h4S. -B=piB_pimQ1Z_SO -11=)a;_H -RNH3Ds0_HFsolMNCAR"tiqB_jjd_aQh"N; -H#R3$HM_MPH0N"DR4 -";N3HRHDM_FRFbcs; -RU@@:(4.:4.:.d(:+:46B_pim_zauR) fjj:ROlNEwR7wsRbHBlRpmi_zua_)S -Tp=Biz_ma)_u 7 -S=4h_dB -SpBi=pmi_1_ZQON; -HsR30FD_sMHoNRlC"iBp_amz_ u)"N; -HHR3MF_DF6bR;H -NR$3#MM_HHN0PD4R""s; -RU@@:(4.:4.:.d(:+:46B_piBrha49:jR:fjjNRlO7ERwbwRsRHlB_piBrhajS9 -Tp=Bih_Ba9rj -=S7O\D 3iBp_aBh_jdr9B -SpBi=pmi_1_ZQON; -HsR30FD_sMHoNRlC"iBp_aBh"N; -HkR3MNVsOM_H8RCGjN; -H#R3$HM_MPH0N"DRj -";s@R@U.:4(::.4:.(d6+4:iBp_aBhrj4:9jRf:ljRNROE7RwwblsHRiBp_aBhr -49SBT=pBi_h4ar97 -S= OD\p3Bih_Bar_d4S9 -B=piB_pimQ1Z_ -O;N3HRs_0DFosHMCNlRp"Bih_Ba -";N3HRksMVNHO_MG8CR -4;N3HR#_$MH0MHPRND";j" -@sR@4U:4dU:.4:4Uc:d+:46O_bkCr#0d9:jR:fjjNRlO7ERwbwRsRHlO_bkCr#0jS9 -Tb=Ok#_C09rj -=S7hc_4 -pSBip=Bi1_mZOQ_;H -NR03sDs_FHNoMl"CRO_bkC"#0;H -NRM3kVOsN_8HMCjGR;H -NR$3#MM_HHN0PDjR""s; -RU@@:g4j::6.4:jg646+6u:eqY_1hfBRjR:jlENORw7w1b]RsRHle_uq1BYh -=STe_uq1BYh -=S7h -_cSiBp=iBp_Zm1Q -_OS)1=1Ha_;H -NR03sDs_FHNoMl"CRe_uq1BYh"N; -H#R3$HM_MPH0N"DR4 -";s@R@Uj:4g.:6:g4j:+664w6:uBz_1h_QajRf:ljRNROE71ww]sRbHwlRuBz_1h_QaT -S=zwu__B1Q -haSh7=_S6 -B=piB_pimQ1Z_SO -11=)a;_H -RNH3Ds0_HFsolMNCwR"uBz_1h_Qa -";N3HR#_$MH0MHPRND";4" +s@:@U4:jg64.:j6g:6c+4:_AtjRjjfjj:ROlNEwR7wR1]blsHR_Atj7jjw]w1 +=STAjt_jOj_ +=S7hj_4 +pSBip=Bi1_mZOQ_ +=S1)_1aHN; +HsR30FD_sMHoNRlC"_Atj"jj;H +NRM3H_FDFb;Rd +@sR@4U:..U::U4.:4d+cp:Biz_ma)_u jRf:ljRNROE7RwwblsHRiBp_amz_ u) +=STB_pim_zau +) Sh7=_ +44SiBp=iBp_Zm1Q;_O +RNH3Ds0_HFsolMNCBR"pmi_zua_); " RNH3_HMDbFFR -n;s@R@UU:4d::.4:Udd6+4:_q1j_djj_jj1BYhR:fjjNRlO7ERw]w1RHbsl1Rq_jjd_jjj_h1YBT -S=_q1j_djj_jj1BYh -=S7h -_nSiBp=iBp_Zm1Q -_OS)1=1Ha_;H -NR03sDs_FHNoMl"CRqj1_djj_j1j_Y"hB;H -NR$3#MM_HHN0PD4R""s; -RU@@:d4U:4.:Udd:+:46qj1_jQj_hfaRjR:jlENORw7w1b]RsRHlqj1_jQj_hSa -T1=q_jjj_aQh -=S7h -_(SiBp=iBp_Zm1Q +6;N3HR#_$MH0MHPRND";4" +@sR@4U:j6g:.j:4g6:6+:4cABtqid_jjh_QajRf:ljRNROE71ww]sRbHAlRtiqB_jjd_aQh +=STABtqid_jjh_Qa7 +S=4h_.B +SpBi=pmi_1_ZQO1 +S=a)1_ +H;N3HRs_0DFosHMCNlRt"Aq_Bij_djQ"ha;H +NR$3#MM_HHN0PD4R""N; +HHR3MF_DFcbR;R +s@:@U4:U6.U:46+:d4qc:1j_jjh_QajRf:ljRNROE71ww]sRbHqlR1j_jjh_QaT +S=_q1j_jjQ +haSh7=_ +4dSiBp=iBp_Zm1Q _OS)1=1Ha_;H NR03sDs_FHNoMl"CRqj1_jQj_h;a" RNH3M#$_HHM0DPNR""4;H NRM3H_FDFb;Rj -@sR@4U:j6g:.j:4g6:6+:46qtvQqz_A1h_ q ApR:fjjNRlO7ERwbwRsRHlqtvQqz_A1h_ q Ap7 -wwSqT=vqQt_1Az_q hA_p O7 -S=Uh_ -pSBip=Bi1_mZOQ_;H -NR03sDs_FHNoMl"CRqtvQqz_A1h_ q Ap"N; -HHR3MF_DFUbR;R -s@:@U4:jg64.:j6g:66+4:_AtjRjjfjj:ROlNEwR7wR1]blsHR_Atj7jjw]w1 -=STAjt_jOj_ +@sR@4U:U.6::64U:4d+c1:q_jjd_jjj_h1YBjRf:ljRNROE71ww]sRbHqlR1d_jjj_jjY_1hSB +T1=q_jjd_jjj_h1YB7 +S=4h_ +pSBip=Bi1_mZOQ_ +=S1)_1aHN; +HsR30FD_sMHoNRlC"_q1j_djj_jj1BYh"N; +H#R3$HM_MPH0N"DR4 +";s@R@Uj:4g.:6:g4j:+6647c:aiqB_h1YBjRf:ljRNROE71ww]sRbH7lRaiqB_h1YBT +S=q7aB1i_Y +hBSh7=_S. +B=piB_pimQ1Z_SO +11=)a;_H +RNH3Ds0_HFsolMNC7R"aiqB_h1YB +";N3HR#_$MH0MHPRND";4" +@sR@4U:j6g:.j:4g6:6+:4cw_uzBQ1_hfaRjR:jlENORw7w1b]RsRHlw_uzBQ1_hSa +Tu=wz1_B_aQh =S7h -_gSiBp=iBp_Zm1Q +_dSiBp=iBp_Zm1Q _OS)1=1Ha_;H -NR03sDs_FHNoMl"CRAjt_j;j" -RNH3_HMDbFFR -d;s@R@Uj:4g.:6:g4j:+66476:1iqB_aQhrR49fjj:ROlNEwR7wR1]blsHRq71BQi_h4ar9T -S=q71BQi_h4ar97 -S=4h_jB +NR03sDs_FHNoMl"CRw_uzBQ1_h;a" +RNH3M#$_HHM0DPNR""4;H +NRM3H_FDFb;Rn +@sR@4U:j6g:.j:4g6:6+:4c7B1qih_Qa9r4R:fjjNRlO7ERw]w1RHbsl1R7q_BiQrha4S9 +T1=7q_BiQrha4S9 +7_=hcB SpBi=pmi_1_ZQO1 S=a)1_ H;N3HR#_$MH0MHPRND";4" RNH3Ds0_HFsolMNC7R"1iqB_aQh"s; -RU@@:d4U:4.:Udd:+:46z_71j_jjQRhafjj:ROlNEwR7wR1]blsHR1z7_jjj_aQh -=STz_71j_jjQ -haSh7=_S4 -B=piB_pimQ1Z_SO -11=)a;_H -RNH3Ds0_HFsolMNCzR"7j1_jQj_h;a" -RNH3M#$_HHM0DPNR""4;H -NRM3H_FDFb;R4 -@sR@4U:U.d::d4U:4d+67:p1j_jjh_QajRf:ljRNROE71ww]sRbHplR7j1_jQj_hSa -T7=p1j_jjh_Qa7 -S=.h_ -pSBip=Bi1_mZOQ_ -=S1)_1aHN; -HsR30FD_sMHoNRlC"1p7_jjj_aQh"N; +RU@@:g4j::6.4:jg646+cu:eqY_1hfBRjR:jlENORw7w1b]RsRHle_uq1BYh +=STe_uq1BYh +=S7h +_6SiBp=iBp_Zm1Q +_OS)1=1Ha_;H +NR03sDs_FHNoMl"CRe_uq1BYh"N; H#R3$HM_MPH0N"DR4 -";N3HRHDM_FRFb.s; -RU@@:g4j::6.4:jg646+6a:7q_Bi1BYhR:fjjNRlO7ERw]w1RHbslaR7q_Bi1BYh -=ST7BaqiY_1hSB -7_=hdB +";s@R@Uj:4g.:6:g4j:+664qc:vqQt_1Az_q hARp fjj:ROlNEwR7wsRbHqlRvqQt_1Az_q hA7p wSw +Tv=qQ_tqA_z1 AhqpO _ +=S7h +_nSiBp=iBp_Zm1Q;_O +RNH3Ds0_HFsolMNCqR"vqQt_1Az_q hA"p ;H +NRM3H_FDFb;RU +@sR@4U:4d(:.4:4(c:d+:4cB_pij_jj7f6RjR:jlENORw7wRHbslpRBij_jj6_7 +=STB_pij_jj7S6 +7p=Bij_jjc_7 +pSBip=Bi1_mZOQ_;H +NR03sDs_FHNoMl"CRB_pij_jj7;6" +RNH3M#$_HHM0DPNR""4;R +s@:@U4:jg64.:j6g:6c+4:q7aB7i_vfqRjR:jlENORw7w1b]RsRHl7Baqiv_7qT +S=q7aB7i_vSq +70=#N_0ClENOH\MC3(kM__N#j_jjH_M0HB SpBi=pmi_1_ZQO1 S=a)1_ -H;N3HRs_0DFosHMCNlRa"7q_Bi1BYh"N; -H#R3$HM_MPH0N"DR4 -";s@R@U.:4(::.4:.(d6+4:iBp_amz_aQhR:fjjNRlO7ERwbwRsRHlB_pim_zaQ -haSBT=p i_XOu_ -=S7B_pim_zau -) SiBp=iBp_Zm1Q;_O -RNH3Ds0_HFsolMNCBR"pmi_zQa_h;a" -RNH3M#$_HHM0DPNR""4;R -s@:@U4:jg64.:j6g:66+4:q7aB7i_vfqRjR:jlENORw7w1b]RsRHl7Baqiv_7qT -S=q7aB7i_vSq -70=#N_0ClENOH\MC34kMc#_N_jjj_0HM_SH -B=piB_pimQ1Z_SO -11=)a;_H -RNH3Ds0_HFsolMNC7R"aiqB_q7v"N; -H#R3$HM_MPH0N"DR4 -";s@R@U4:4c.:d:c44:+dc4B6:pji_j7j_.jRf:ljRNROE7RwwblsHRiBp_jjj_ -7.SBT=pji_j7j_.7 -S=iBp_jjj_ -74SiBp=iBp_Zm1Q;_O -RNH3Ds0_HFsolMNCBR"pji_j7j_. -";N3HR#_$MH0MHPRND";4" -@sR@(U:.6:.::(.d4j+6u:eqR_7fjj:ROlNEwR7wsRbHelRu7q_ -=STe_uq77 -S=qeu_SO +H;N3HRs_0DFosHMCNlRa"7q_Bi7"vq;H +NR$3#MM_HHN0PD4R""s; +RU@@:U4.:4.:.dU:+:4cB_pim_zaQRhafjj:ROlNEwR7wsRbHBlRpmi_zQa_hSa +Tp=BiX_ u +_OSB7=pmi_zua_)S B=piB_pimQ1Z_ -O;N3HRs_0DFosHMCNlRu"eq"_7;H -NR$3#MM_HHN0PD4R""s; -RU@@:444::d44:44d4d+6p:Bij_jjj_7R:fjjNRlO7ERwbwRsRHlB_pij_jj7Sj -Tp=Bij_jjj_7 -=S7B_pij_jjOB -SpBi=pmi_1_ZQON; -HsR30FD_sMHoNRlC"iBp_jjj_"7j;H -NR$3#MM_HHN0PD4R""s; -RU@@:(4.:4.:.d(:+:46) 1ajRf:ljRNROE7RwwblsHR1) wa7wT -S=1) Oa_ -=S7)_1aOB -SpBi=pmi_1_ZQON; -HsR30FD_sMHoNRlC"1) ;a" -@sR@4U:4dd:.4:4dc:d+:46B_pij_jj7f4RjR:jlENORw7wRHbslpRBij_jj4_7 -=STB_pij_jj7S4 -7p=Bij_jjj_7 +O;N3HRs_0DFosHMCNlRp"Biz_mah_Qa +";N3HR#_$MH0MHPRND";4" +@sR@4U:4dn:.4:4nc:d+:4cB_pij_jj7fcRjR:jlENORw7wRHbslpRBij_jjc_7 +=STB_pij_jj7Sc +7p=Bij_jjd_7 pSBip=Bi1_mZOQ_;H -NR03sDs_FHNoMl"CRB_pij_jj7;4" +NR03sDs_FHNoMl"CRB_pij_jj7;c" RNH3M#$_HHM0DPNR""4;R -sfjj:ROlNEARQzbwRsRHlqj1_dSj -m1=q_jjd_SO -Qqj=1d_jjs; -R:fjjNRlOAERz]waRHbsl1Rq_jjj -=Smqj1_jSj -Qqj=1j_jjh_Qam -S t=Aq_Bij_djQ;ha -fsRjR:jlENORzQAwsRbH7lR1d_jjm -S=_71j_djOQ -Sj1=7_jjd;R -sfjj:ROlNEzRAwRa]blsHR1z7_jjj -=Smz_71j -jjS=Qjz_71j_jjQ -haS=m ABtqid_jjh_Qas; -R:fjjNRlOAERz]waRHbsl7Rp1j_jjm -S=1p7_jjj -jSQ=1p7_jjj_aQh +s@:@U4:4cd4.:4dc:cc+4:iBp_jjj_R7.fjj:ROlNEwR7wsRbHBlRpji_j7j_.T +S=iBp_jjj_ +7.SB7=pji_j7j_4B +SpBi=pmi_1_ZQON; +HsR30FD_sMHoNRlC"iBp_jjj_"7.;H +NR$3#MM_HHN0PD4R""s; +RU@@:644::d.4:46d4c+cp:Bij_jjd_7R:fjjNRlO7ERwbwRsRHlB_pij_jj7Sd +Tp=Bij_jjd_7 +=S7B_pij_jj7S. +B=piB_pimQ1Z_ +O;N3HRs_0DFosHMCNlRp"Bij_jjd_7"N; +H#R3$HM_MPH0N"DR4 +";s@R@U.:(::.6(d.:jc+4:qeu_f7RjR:jlENORw7wRHbsluReq +_7SeT=u7q_ +=S7e_uqOB +SpBi=pmi_1_ZQON; +HsR30FD_sMHoNRlC"qeu_;7" +RNH3M#$_HHM0DPNR""4;R +s@:@U4:44d44:4d4:dc+4:iBp_jjj_R7jfjj:ROlNEwR7wsRbHBlRpji_j7j_jT +S=iBp_jjj_ +7jSB7=pji_jOj_ +pSBip=Bi1_mZOQ_;H +NR03sDs_FHNoMl"CRB_pij_jj7;j" +RNH3M#$_HHM0DPNR""4;R +s@:@U4:.U..:4U+:d4)c: a1 R:fjjNRlO7ERwbwRsRHl) 1aw7w +=ST) 1a +_OS)7=1Oa_ +pSBip=Bi1_mZOQ_;H +NR03sDs_FHNoMl"CR) 1a +";s@R@U4:4d.:d:d44:+dc4Bc:pji_j7j_4jRf:ljRNROE7RwwblsHRiBp_jjj_ +74SBT=pji_j7j_47 +S=iBp_jjj_ +7jSiBp=iBp_Zm1Q;_O +RNH3Ds0_HFsolMNCBR"pji_j7j_4 +";N3HR#_$MH0MHPRND";4" +fsRjR:jlENORzQAwsRbHqlR1d_jjm +S=_q1j_djOQ +Sj1=q_jjd;R +sfjj:ROlNEzRAwRa]blsHR_q1j +jjSqm=1j_jjQ +Sj1=q_jjj_aQh Sm=qAtBji_dQj_h -a;sjRf:ljRNROEQwAzRHbslQR1Zj r9m -S=Z1Q r_OjS9 -Q1j=QrZ j -9;sjRf:ljRNROEQwAzRHbslQR1Z4 r9m -S=Z1Q r_O4S9 -Q1j=QrZ 4 -9;sjRf:ljRNROEQwAzRHbslrRqjS9 -m_=qO9rj -jSQ=jqr9s; -R:fjjNRlOQERARzwblsHR4qrnS9 -m_=qOnr49Q -Sjr=q4;n9 -fsRjR:jlENORzQAwsRbHqlRr94( -=Smqr_O4 -(9S=Qjq(r49s; -R:fjjNRlOQERARzwblsHR4qrUS9 -m_=qOUr49Q -Sjr=q4;U9 -fsRjR:jlENORzQAwsRbHqlRr94g -=Smqr_O4 -g9S=Qjqgr49s; -R:fjjNRlOQERARzwblsHR.qrjS9 -m_=qOjr.9Q -Sjr=q.;j9 -fsRjR:jlENORzQAwsRbHqlRr9.4 -=Smqr_O. -49S=Qjq4r.9s; -R:fjjNRlOQERARzwblsHR.qr.S9 -m_=qO.r.9Q -Sjr=q.;.9 -fsRjR:jlENORzQAwsRbHqlRr9.d -=Smqr_O. -d9S=Qjqdr.9s; -R:fjjNRlOQERARzwblsHR.qrcS9 -m_=qOcr.9Q -Sjr=q.;c9 -fsRjR:jlENORzQAwsRbHqlRr9.6 -=Smqr_O. -69S=Qjq6r.9s; -R:fjjNRlOQERARzwblsHR.qrnS9 -m_=qOnr.9Q -Sjr=q.;n9 -fsRjR:jlENORzQAwsRbHqlRr9.( -=Smqr_O. -(9S=Qjq(r.9s; -R:fjjNRlOQERARzwblsHR.qrUS9 -m_=qOUr.9Q -Sjr=q.;U9 -fsRjR:jlENORzQAwsRbHqlRr9.g -=Smqr_O. -g9S=Qjqgr.9s; -R:fjjNRlOQERARzwblsHRdqrjS9 -m_=qOjrd9Q -Sjr=qd;j9 -fsRjR:jlENORzQAwsRbHqlRr9d4 -=Smqr_Od -49S=Qjq4rd9s; -R:fjjNRlOQERARzwblsHRXM uu_1q -B SMm= _Xu1Buq -_OS=QjMu X_q1uB - ;sjRf:ljRNROEAazw]sRbHAlR -))SAm= -))S=Qjt -h7S=m w_uzBQ1_hHa_;R -sfjj:ROlNEARQzbwRsRHlAjt_dSj -mt=A_jjd_SO -QAj=td_jjs; -R:fjjNRlOmERARzwblsHR_Atj -jjSAm=tj_jjQ -Sjt=A_jjj_ -O;sjRf:ljRNROEmwAzRHbsltRAq_Bij -djSAm=tiqB_jjd -jSQ=qAtBji_dQj_h -a;sjRf:ljRNROEQwAzRHbsltRAq_Bij -jjSAm=tiqB_jjj_SO -QAj=tiqB_jjj;R -sfjj:ROlNEARQzbwRsRHlB_pij -djSBm=pji_dOj_ -jSQ=iBp_jjd;R -sfjj:ROlNEARQzbwRsRHlB_pij -jjSBm=pji_jOj_ -jSQ=iBp_jjj;R -sfjj:ROlNEARQzbwRsRHlB_pimQ1Z -=SmB_pimQ1Z_SO -QBj=pmi_1;ZQ -fsRjR:jlENORzmAwsRbHBlRp7i_Qme_zSa -mp=BiQ_7ez_maQ -Sjp=BiX_ u;_O -fsRjR:jlENORzmAwsRbHBlRp i_XSu -mp=BiX_ uQ -Sjp=BiX_ u;_O -fsRjR:jlENORzmAwsRbHwlRuBz_1m -S=zwu_ -B1S=Qjw_uzBQ1_h -a;sjRf:ljRNROEmwAzRHbsluRQpd_jj9rj -=SmQ_upjrdjjS9 -QQj=ujp_dOj_r;j9 -fsRjR:jlENORzmAwsRbHQlRujp_d4jr9m +a;sjRf:ljRNROEQwAzRHbsl1R7_jjd +=Sm7j1_dOj_ +jSQ=_71j;dj +fsRjR:jlENORwAzab]RsRHlz_71j +jjSzm=7j1_jSj +Qzj=7j1_jQj_hSa +mA =tiqB_jjd_aQh;R +sfjj:ROlNEzRAwRa]blsHR1p7_jjj +=Smp_71j +jjS=Qjp_71j_jjQ +haS=m ABtqid_jjh_Qas; +R:fjjNRlOQERARzwblsHRZ1Q 9rj +=Sm1 QZ_jOr9Q +SjQ=1Zj r9s; +R:fjjNRlOQERARzwblsHRZ1Q 9r4 +=Sm1 QZ_4Or9Q +SjQ=1Z4 r9s; +R:fjjNRlOQERARzwblsHRjqr9m +S=Oq_r +j9S=Qjq9rj;R +sfjj:ROlNEARQzbwRsRHlqnr49m +S=Oq_r94n +jSQ=4qrn +9;sjRf:ljRNROEQwAzRHbslrRq4 +(9Sqm=_4Or(S9 +Qqj=r94(;R +sfjj:ROlNEARQzbwRsRHlqUr49m +S=Oq_r94U +jSQ=4qrU +9;sjRf:ljRNROEQwAzRHbslrRq4 +g9Sqm=_4OrgS9 +Qqj=r94g;R +sfjj:ROlNEARQzbwRsRHlqjr.9m +S=Oq_r9.j +jSQ=.qrj +9;sjRf:ljRNROEQwAzRHbslrRq. +49Sqm=_.Or4S9 +Qqj=r9.4;R +sfjj:ROlNEARQzbwRsRHlq.r.9m +S=Oq_r9.. +jSQ=.qr. +9;sjRf:ljRNROEQwAzRHbslrRq. +d9Sqm=_.OrdS9 +Qqj=r9.d;R +sfjj:ROlNEARQzbwRsRHlqcr.9m +S=Oq_r9.c +jSQ=.qrc +9;sjRf:ljRNROEQwAzRHbslrRq. +69Sqm=_.Or6S9 +Qqj=r9.6;R +sfjj:ROlNEARQzbwRsRHlqnr.9m +S=Oq_r9.n +jSQ=.qrn +9;sjRf:ljRNROEQwAzRHbslrRq. +(9Sqm=_.Or(S9 +Qqj=r9.(;R +sfjj:ROlNEARQzbwRsRHlqUr.9m +S=Oq_r9.U +jSQ=.qrU +9;sjRf:ljRNROEQwAzRHbslrRq. +g9Sqm=_.OrgS9 +Qqj=r9.g;R +sfjj:ROlNEARQzbwRsRHlqjrd9m +S=Oq_r9dj +jSQ=dqrj +9;sjRf:ljRNROEQwAzRHbslrRqd +49Sqm=_dOr4S9 +Qqj=r9d4;R +sfjj:ROlNEARQzbwRsRHlMu X_q1uBS +m =MX1u_u qB_SO +QMj= _Xu1Buq s; +R:fjjNRlOAERz]waRHbsl RA)S) +m =A)S) +Qtj=hS7 +mw =uBz_1h_Qa;_H +fsRjR:jlENORzQAwsRbHAlRtd_jjm +S=_Atj_djOQ +Sjt=A_jjd;R +sfjj:ROlNEARmzbwRsRHlAjt_jSj +mt=A_jjj +jSQ=_Atj_jjOs; +R:fjjNRlOmERARzwblsHRqAtBji_dSj +mt=Aq_Bij +djS=QjABtqid_jjh_Qas; +R:fjjNRlOQERARzwblsHRqAtBji_jSj +mt=Aq_Bij_jjOQ +Sjt=Aq_Bij;jj +fsRjR:jlENORzQAwsRbHBlRpji_dSj +mp=Bid_jj +_OS=QjB_pij;dj +fsRjR:jlENORzQAwsRbHBlRpji_jSj +mp=Bij_jj +_OS=QjB_pij;jj +fsRjR:jlENORzQAwsRbHBlRpmi_1 +ZQSBm=pmi_1_ZQOQ +Sjp=Bi1_mZ +Q;sjRf:ljRNROEmwAzRHbslpRBiQ_7ez_mam +S=iBp_e7Q_amz +jSQ=iBp_u X_ +O;sjRf:ljRNROEmwAzRHbslpRBiX_ um +S=iBp_u X +jSQ=iBp_u X_ +O;sjRf:ljRNROEmwAzRHbsluRwz1_B +=Smw_uzBS1 +Qwj=uBz_1h_Qas; +R:fjjNRlOmERARzwblsHRpQu_jjdr +j9SQm=ujp_djjr9Q +Sju=Qpd_jjr_Oj +9;sjRf:ljRNROEmwAzRHbsluRQpd_jj9r4 +=SmQ_upjrdj4S9 +QQj=ujp_dOj_r;49 +fsRjR:jlENORzmAwsRbHQlRujp_d.jr9m S=pQu_jjdr -49S=QjQ_upj_djO9r4;R -sfjj:ROlNEARmzbwRsRHlQ_upjrdj.S9 -mu=Qpd_jj9r. -jSQ=pQu_jjd_.Or9s; +.9S=QjQ_upj_djO9r.;R +sfjj:ROlNEARQzbwRsRHlQrupjS9 +mu=Qpr_OjS9 +QQj=ujpr9s; R:fjjNRlOQERARzwblsHRpQur -j9SQm=uOp_r -j9S=QjQrupj -9;sjRf:ljRNROEQwAzRHbsluRQp9r4 -=SmQ_upO9r4 -jSQ=pQur;49 -fsRjR:jlENORzQAwsRbHQlRu.pr9m -S=pQu_.Or9Q -Sju=Qp9r.;R -sfjj:ROlNEzRAwRa]blsHRq71Bjir9m -S=q71Bjir9Q -SjB=eBm -S =MX1u_u qB_ -O;sjRf:ljRNROEA7Q_Qb)RsRHl7B1qi9r4 -=Sm7B1qir_O4S9 -Q7j=1iqB_aQhr -49S=Qm7B1qi9r4 +49SQm=uOp_r +49S=QjQrup4 +9;sjRf:ljRNROEQwAzRHbsluRQp9r. +=SmQ_upO9r. +jSQ=pQur;.9 +fsRjR:jlENORwAzab]RsRHl7B1qi9rj +=Sm7B1qi9rj +jSQ=BeB Sm=XM uu_1q_B Os; -R:fjjNRlOAERQQ_7)sRbH7lRaiqB -=Sm7Baqi -_OS=Qj7Baqiv_7qQ -Sma=7q -BiS=m ABtqid_jjh_Qa;_H -fsRjR:jlENORzmAwsRbHqlRe - BSqm=e - BS=Qje;BB -fsRjR:jlENORwAzab]RsRHlqBe _u X -=SmqBe _u X -jSQ=7th - Sm=zwu__B1Q_haHs; -R:fjjNRlOmERARzwblsHRS -m -= S=QjO_bkCr#0d -9;sjRf:ljRNROEQwAzRHbsluReqm -S=qeu_SO -Qej=u -q;sjRf:ljRNROEmwAzRHbslvReqm -S=qev -jSQ=qev_aQh;R -sfjj:ROlNEARQzbwRsRHl) -1aS)m=1Oa_ -jSQ=a)1;R -sfjj:ROlNEARmzbwRsRHl) 1am -S=1) Sa -Q)j= a1 _ -O;sjRf:ljRNROEQwAzRHbslWR) -=Sm)OW_ -jSQ=;)W -fsRjR:jlENORzQAwsRbHwlRB9rj -=SmwOB_r -j9S=QjwjBr9s; -R:fjjNRlOQERARzwblsHRrwB4S9 -mB=w_4Or9Q -SjB=wr;49 -fsRjR:jlENORzmAwsRbHqlRvqQt_1Az_q hA -p Sqm=vqQt_1Az_q hA -p S=QjqtvQqz_A1h_ q Ap_ -O;sjRf:ljRNROEmwAzRHbslvRqQ_tqA_z17qqa_)7Q -=SmqtvQqz_A1q_7a7q_QS) -Q)j=W;_H -fsRjR:jlENORzmAwsRbHqlRvqQt_1Az_q hA_p p -mWSqm=vqQt_1Az_q hA_p p -mWS=Qje;BB -fsRjR:jlENORwAzab]RsRHlBhQQ -=SmBhQQ -jSQ=4h_(S4 -mh =_U4n;R -sfjj:ROlNEhRq7b.RsRHl7BaqiY_1h4B__l#Jk_GN4 -_jS7m=aiqB_h1YB__4#kJlG4N__Sj -Q7j=aiqB_SH -Q14=vv_qQrtqd -9;sjRf:ljRNROEq.h7RHbslaR7q_Bi1BYh_#4_JGlkN -_.S7m=aiqB_h1YB__4#kJlG.N_ -jSQ=qeu_S7 -Q#4=0CN0_OlNECHM\M3k.D_O j_jjs; -R:fjjNRlOqERhR7.blsHRq7aB1i_Y_hB4J_#lNkG -=Sm7BaqiY_1h4B__l#Jk -GNS=Qj7BaqiY_1h4B__l#Jk_GN4 -_jS=Q47BaqiY_1h4B__l#Jk_GN.s; -R:fjjNRlOqERhR7.blsHRN#00lC_NHOEM3C\k_MUO_D j_jj84j_ -=Sm#00NCN_lOMEHCk\3MOU_Dj _j8j_j -_4S=QjO_bkC_#0H9r4 -4SQ=kOb_0C#_dHr9s; -R:fjjNRlOqERhR7.blsHRN#00lC_NHOEM3C\k_MUO_D j_jj8.j_ -=Sm#00NCN_lOMEHCk\3MOU_Dj _j8j_j -_.S=QjB_pij_jj7Hj_ -4SQ=qeu_H7_;R -sfjj:ROlNEhRq7b.RsRHl#00NCN_lOMEHCk\3MOU_Dj _j8j_j -_dS#m=0CN0_OlNECHM\M3kUD_O j_jjj_8_Sd -QOj=bCk_#j0r9Q -S4b=Ok#_C09r.;R -sfjj:ROlNEhRq7b.RsRHl#00NCN_lOMEHCk\3MOU_Dj _j8j_j -_cS#m=0CN0_OlNECHM\M3kUD_O j_jjj_8_Sc -Q#j=0CN0_OlNECHM\M3kUD_O j_jjj_8_S4 -Q#4=0CN0_OlNECHM\M3kUD_O j_jjj_8_ -.;sjRf:ljRNROEq.h7RHbsl0R#N_0ClENOH\MC3UkM_ OD_jjj_ -8jS#m=0CN0_OlNECHM\M3kUD_O j_jjj_8 -jSQ=N#00lC_NHOEM3C\k_MUO_D j_jj8cj_ -4SQ=N#00lC_NHOEM3C\k_MUO_D j_jj8dj_;R -sfjj:ROlNEhRq7b.RsRHl#00NCN_lOMEHCk\3M_4dO_D j_jj84j__Sj -m0=#N_0ClENOH\MC34kMdD_O j_jjj_8_j4_ -jSQ=kOb_0C#_jHr9Q -S4b=Ok#_C0r_Hd -9;sjRf:ljRNROEq.h7RHbsl0R#N_0ClENOH\MC34kMdD_O j_jjj_8_j._ -=Sm#00NCN_lOMEHCk\3M_4dO_D j_jj8.j__Sj -Q#j=0CN0_OlNECHM\M3k4Od_Dj _j8j_j -_4S=Q4#00NCN_lOMEHCk\3M_4dO_D j_jj8.j_;R -sfjj:ROlNEhRq7b.RsRHl#00NCN_lOMEHCk\3M_4dO_D j_jj8Sj -m0=#N_0ClENOH\MC34kMdD_O j_jjj_8 -jSQ=N#00lC_NHOEM3C\kdM4_ OD_jjj__8j4 -_jS=Q4#00NCN_lOMEHCk\3M_4dO_D j_jj8.j__ -j;sjRf:ljRNROEq.h7RHbsluReqY_1h4B__l#Jk_GNdm -S=qeu_h1YB__4#kJlGdN_ -jSQ=kOb_0C#r -d9S=Q4O_bkC_#0H9rj;R -sfjj:ROlNEhRq7b.RsRHle_uq1BYh_#4_JGlkN -_cSem=u1q_Y_hB4J_#lNkG_Sc -QOj=bCk_#H0_r -49S=Q4#00NCN_lOMEHCk\3MO._Dj _j -j;sjRf:ljRNROEq.h7RHbsluReqY_1h4B__l#Jk_GN6m -S=qeu_h1YB__4#kJlG6N_ -jSQ=qeu_h1YB__4#kJlG4N__Sj -Qe4=u1q_Y_hB4J_#lNkG_ -.;sjRf:ljRNROEq.h7RHbsluReqY_1h4B__l#Jk_GNnm -S=qeu_h1YB__4#kJlGnN_ -jSQ=qeu_h1YB__4#kJlGdN_ -4SQ=qeu_h1YB__4#kJlGcN_;R -sfjj:ROlNEhRq7b.RsRHle_uq1BYh_#4_JGlkNm -S=qeu_h1YB__4#kJlGSN -Qej=u1q_Y_hB4J_#lNkG_S6 -Qe4=u1q_Y_hB4J_#lNkG_ -n;sjRf:ljRNROEq.h7RHbslDRO O\3bCk_#40_4__HN4c_r -.9Shm=_(4._S4 -QOj=bCk_#j0r9Q -S4b=Ok#_C0r_Hd -9;sjRf:ljRNROEq.h7RHbslDRO O\3bCk_#40_4__HN.cr9m -S=4h_.S( -Qhj=_(4._S4 -Q#4=0CN0_OlNECHM\M3k4Od_Dj _j8j_j__.Hs; -R:fjjNRlOqERhR7.blsHR OD\b3Ok#_C04_4_NH_c__j49r. -=Smh._4U -_4S=QjO_bkCr#04S9 -QO4=bCk_#H0_r;j9 -fsRjR:jlENOR7qh.sRbHOlRD3 \O_bkC_#04H4___Ncj9r. -=Smh._4UQ -Sj_=h4_.U4Q -S4b=Ok#_C0r_H. -9;sjRf:ljRNROEq.h7RHbslDRO O\3bCk_#40_4__jN4c__d4r9m -S=4h_d44_ -jSQ=kOb_0C#_jHr9Q -S4b=Ok#_C0r_H4 -9;sjRf:ljRNROEq.h7RHbslDRO O\3bCk_#40_4__jN4c_r -d9Shm=_44d -jSQ=4h_d44_ -4SQ=kOb_0C#_.Hr9s; -R:fjjNRlOqERhR7.blsHR OD\b3Ok#_C04_4_4j_r +R:fjjNRlOAERQQ_7)sRbH7lR1iqBr +49S7m=1iqB_4Or9Q +Sj1=7q_BiQrha4S9 +Q7m=1iqBr +49S=m Mu X_q1uBO _;R +sfjj:ROlNEQRA_)7QRHbslaR7q +BiS7m=aiqB_SO +Q7j=aiqB_q7v +mSQ=q7aBSi +mA =tiqB_jjd_aQh_ +H;sjRf:ljRNROEmwAzRHbsleRq SB +me=q SB +Qej=B +B;sjRf:ljRNROEAazw]sRbHqlRe_ B +XuSqm=e_ B +XuS=Qjt +h7S=m w_uzBQ1_hHa_;R +sfjj:ROlNEARmzbwRsRHl m +S=S +QOj=bCk_#d0r9s; +R:fjjNRlOQERARzwblsHRqeu +=Sme_uqOQ +Sju=eqs; +R:fjjNRlOmERARzwblsHRqev +=Sme +vqS=Qje_vqQ;ha +fsRjR:jlENORzQAwsRbH)lR1Sa +m1=)a +_OS=Qj);1a +fsRjR:jlENORzmAwsRbH)lR a1 +=Sm) 1aQ +Sj =)1_ aOs; +R:fjjNRlOQERARzwblsHR +)WS)m=W +_OS=Qj) +W;sjRf:ljRNROEQwAzRHbslBRwr +j9Swm=Br_OjS9 +Qwj=B9rj;R +sfjj:ROlNEARQzbwRsRHlw4Br9m +S=_wBO9r4 +jSQ=rwB4 +9;sjRf:ljRNROEmwAzRHbslvRqQ_tqA_z1 AhqpS +mv=qQ_tqA_z1 AhqpS +Qqj=vqQt_1Az_q hA_p Os; +R:fjjNRlOmERARzwblsHRQqvtAq_z71_q_aq7 +Q)Sqm=vqQt_1Az_a7qqQ_7)Q +SjW=)_ +H;sjRf:ljRNROEmwAzRHbslvRqQ_tqA_z1 Ahqpp _mSW +mv=qQ_tqA_z1 Ahqpp _mSW +Qej=B +B;sjRf:ljRNROEAazw]sRbHBlRQ +QhSBm=Q +QhS=Qjhg_44m +S _=h4;UU +fsRjR:jlENOR7qh.sRbHOlRD3 \O_bkC_#04j4__4j_r d9SOm=D3 \O_bkC_#04j4__d4r9Q -Sj_=h4_d4HQ -S4_=h4_.gHs; -R:fjjNRlOqERhR7.blsHR OD\b3Ok#_C04_4_djr9m -S= OD\b3Ok#_C04_4_djr9Q -SjD=O O\3bCk_#40_4__j49rd -4SQ=4h_dHj_;R -sfjj:ROlNEhRq7b.RsRHl1qv_vqQt__M#Njd__64r9m -S=4h_j46_ -jSQ=iBp_jjj__7jHQ -S4v=1_Qqvtdqr9s; -R:fjjNRlOqERhR7.blsHR_1vqtvQq#_M__Ndj9r6 -=Smhj_46Q -Sj_=h4_j64Q -S40=#N_0ClENOH\MC3.kMdD_O j_jjj_8;R -sfjj:ROlNEhRq7b.RsRHlz_71j_jjQ_hajJ_#lNkG_S4 -m7=z1j_jjh_Qa__j#kJlG4N_ -jSQ=1z7_jjj_aQh_#j_JGlkN__4dQ -S40=#N_0ClENOH\MC3dkMjD_O j_jj4_8;R -sfjj:ROlNEhRq7b.RsRHlz_71j_jjQ_hajJ_#lNkG_j4_ -=Smz_71j_jjQ_hajJ_#lNkG_j4_ -jSQ=_1vqtvQq9rc -4SQ=_71j_djHs; -R:fjjNRlOqERhR7.blsHR1z7_jjj_aQh_#j_JGlkNm -S=1z7_jjj_aQh_#j_JGlkNQ -Sj7=z1j_jjh_Qa__j#kJlG4N__Sj -Q)4=W;_H -fsRjR:jlENOR7qh.sRbHklRM74_1iqB_aQh_#j_JGlkN__HN4d_ -=Smhn_g_S4 -QBj=pji_j7j_j -_HS=Q4B_pim_zau;) -fsRjR:jlENOR7qh.sRbHklRM74_1iqB_aQh_#j_JGlkN__HNSd -m_=hgSn -Qhj=__gn4Q -S4v=1_Qqvt4qr9s; -R:fjjNRlOqERhR7.blsHRN#00lC_NHOEM3C\k.Mc_ OD_jjd_S4 -m0=#N_0ClENOH\MC3ckM.D_O d_jj -_4S=Qjqr_O4 -(9S=Q4qr_H4;n9 -fsRjR:jlENOR7qh.sRbH#lR0CN0_OlNECHM\M3kcO._Dj _d.j_ -=Sm#00NCN_lOMEHCk\3M_c.O_D j_dj.Q -Sj_=qHUr49Q -S4_=qHgr49s; -R:fjjNRlOqERhR7.blsHRN#00lC_NHOEM3C\k.Mc_ OD_jjd_Sd -m0=#N_0ClENOH\MC3ckM.D_O d_jj -_dS=QjwOB_r -49S=Q4ABtqij_jj;_O -fsRjR:jlENOR7qh.sRbH#lR0CN0_OlNECHM\M3kcO._Dj _dcj_ -=Sm#00NCN_lOMEHCk\3M_c.O_D j_djcQ -Sj0=#N_0ClENOH\MC3ckM.D_O d_jj -_4S=Q4#00NCN_lOMEHCk\3M_c.O_D j_dj.s; -R:fjjNRlOqERhR7.blsHRN#00lC_NHOEM3C\k.Mc_ OD_jjd_S6 -m0=#N_0ClENOH\MC3ckM.D_O d_jj -_6S=Qj#00NCN_lOMEHCk\3M_c.O_D j_djdQ -S4B=w_jOr9s; -R:fjjNRlOqERhR7.blsHRN#00lC_NHOEM3C\k.Mc_ OD_jjd -=Sm#00NCN_lOMEHCk\3M_c.O_D j -djS=Qj#00NCN_lOMEHCk\3M_c.O_D j_djcQ -S40=#N_0ClENOH\MC3ckM.D_O d_jj;_6 -fsRjR:jlENOR7qh.sRbHqlRvqQt_1Az_q hA_p H__l4m -S=QqvtAq_z 1_hpqA __Hl +Sj_=h4_(UHQ +S4_=h4_.6Hs; +R:fjjNRlOqERhR7.blsHR OD\b3Ok#_C04_4_jj_r +d9SOm=D3 \O_bkC_#04j4_r +d9S=QjO\D 3kOb_0C#__44jr_4dS9 +Qh4=_U4d_ +H;sjRf:ljRNROEq.h7RHbslDRO O\3bCk_#40_4__jjd_N_44_r +d9Shm=_U4d_S4 +QOj=bCk_#H0_r +j9S=Q4O_bkC_#0H9r4;R +sfjj:ROlNEhRq7b.RsRHlO\D 3kOb_0C#__44j__jN4d_r +d9Shm=_U4d +jSQ=4h_d4U_ +4SQ=kOb_0C#_.Hr9s; +R:fjjNRlOqERhR7.blsHRN#00lC_NHOEM3C\qtvQqz_A1h_ q Ap_Vd_j__HN4d_ +=Smh4_4g _4S=QjqtvQqz_A1h_ q Ap_SH Qq4=1d_jj;_H -fsRjR:jlENOR7qh.sRbHqlRvqQt_1Az_q hA_p H -_lSqm=vqQt_1Az_q hA_p H -_lS=QjqtvQqz_A1h_ q Ap_lH__S4 -Q14=vv_qQ_tqH9rn;R -sfjj:ROlNEhRq7b.RsRHle_uq1BYh_#4_JGlkN__4jm -S=qeu_h1YB__4#kJlG4N__Sj -Q1j=vv_qQrtqdS9 +fsRjR:jlENOR7qh.sRbH#lR0CN0_OlNECHM\v3qQ_tqA_z1 Ahqpd ___VjHd_N +=Smh4_4gQ +Sj_=h4_4g4Q +S4v=1_QqvtHq_r;n9 +fsRjR:jlENOR7qh.sRbHOlRD3 \O_bkC_#04H4__Nj_d__j49r. +=Smh4_4U +_4S=QjO_bkCr#04S9 +QO4=bCk_#H0_r;j9 +fsRjR:jlENOR7qh.sRbHOlRD3 \O_bkC_#04H4__Nj_dr_j.S9 +m_=h4 +4US=Qjh4_4U +_4S=Q4O_bkC_#0H9r.;R +sfjj:ROlNEhRq7b.RsRHlO\D 3kOb_0C#__44H__jN4d_r +.9Shm=_(44_S4 +Qhj=_ +66S=Q4O_bkCr#0j +9;sjRf:ljRNROEq.h7RHbslDRO O\3bCk_#40_4__Hjd_Nr +.9Shm=_(44 +jSQ=4h_44(_ +4SQ=kOb_0C#_dHr9s; +R:fjjNRlOqERhR7.blsHR_1vqtvQq#_M_Nj_d__j49r6 +=Smh(_g_S4 +QBj=pji_j7j_j +_HS=Q41qv_vqQtr;d9 +fsRjR:jlENOR7qh.sRbH1lRvv_qQ_tqMj#___Ndj9r6 +=Smh(_g +jSQ=gh_( +_4S=Q4#00NCN_lOMEHCk\3M_.dO_D j_jj8 +j;sjRf:ljRNROEq.h7RHbsl0R#N_0ClENOH\MC31p7_jjj_aQh_j6___Nd4m +S=Uh_4 +_4S=Qjqr_HjS9 +Q14=Q_Z O9rj;R +sfjj:ROlNEhRq7b.RsRHl#00NCN_lOMEHCp\37j1_jQj_h6a__Nj_dm +S=Uh_4Q +Sj_=hU44_ +4SQ=Z1Q r_H4 +9;sjRf:ljRNROEq.h7RHbslaR7q_Bi1BYh_#4_JGlkN__4Hd_N +=Smh(_( +jSQ=(h_(__4jQ +S4u=eq;_7 +fsRjR:jlENOR7qh.sRbHelRu1q_Y_hB4J_#lNkG_H4___Nd4m +S=(h_6 +_4S=Qjh(_(_S4 Qe4=vQq_hHa_;R -sfjj:ROlNEhRq7b.RsRHle_uq1BYh_#4_JGlkN -_.Sem=u1q_Y_hB4J_#lNkG_S. +sfjj:ROlNEhRq7b.RsRHle_uq1BYh_#4_JGlkN__4Hd_N_j._ +=Smh6_(_S. Qej=u7q__SH QO4=bCk_#.0r9s; -R:fjjNRlOqERhR7.blsHR OD\b3Ok#_C04_4_.j_r +R:fjjNRlOqERhR7.blsHRqeu_h1YB__4#kJlG4N__NH_d +_dShm=__(6dQ +Sjb=Ok#_C09rd +4SQ=kOb_0C#_jHr9s; +R:fjjNRlOqERhR7.blsHRqeu_h1YB__4#kJlG4N__NH_d +_cShm=__(6cQ +Sj_=h(46_ +4SQ=(h_6;_. +fsRjR:jlENOR7qh.sRbHelRu1q_Y_hB4J_#lNkG_H4___Nd6m +S=(h_6 +_6S=Qjh6_(_Sd +QO4=bCk_#H0_r;49 +fsRjR:jlENOR7qh.sRbHelRu1q_Y_hB4J_#lNkG_H4__ +NdShm=_ +(6S=Qjh6_(_Sc +Qh4=__(66s; +R:fjjNRlOqERhR7.blsHRN#00lC_NHOEM3C\k6M4_ OD_jjj__8jjd_N_4j_ +=Smhd_(_S4 +Qhj=__66HQ +S4_=h6Hg_;R +sfjj:ROlNEhRq7b.RsRHl#00NCN_lOMEHCk\3M_46O_D j_jj8jj___Ndj +_.Shm=__(d.Q +Sjb=Ok#_C0r_HjS9 +QO4=bCk_#H0_r;d9 +fsRjR:jlENOR7qh.sRbH#lR0CN0_OlNECHM\M3k4O6_Dj _j8j_j__jNjd_ +=Smhd_( +jSQ=(h_d +_4S=Q4hd_(_ +.;sjRf:ljRNROEq.h7RHbsl0R#N_0ClENOH\MC34kM6D_O j_jjj_8_Nj_d +_4Shm=__(.4Q +Sjp=Bij_jjj_7_SH +Qh4=_n4c;R +sfjj:ROlNEhRq7b.RsRHl#00NCN_lOMEHCk\3M_46O_D j_jj8jj___Nd.m +S=(h_. +_.S=Qje_uq7 +_HS=Q4O_bkCr#0. +9;sjRf:ljRNROEq.h7RHbsl0R#N_0ClENOH\MC34kM6D_O j_jjj_8_Nj_dm +S=(h_.Q +Sj_=h(4._ +4SQ=(h_.;_. +fsRjR:jlENOR7qh.sRbH1lRvv_qQ_tqMj#__j4r9m +S=_1vqtvQq#_M_4j_r +j9S=Qjhc_4j +_HS=Q4h6_U_ +H;sjRf:ljRNROEq.h7RHbslvR1_QqvtMq_#r_jjS9 +mv=1_QqvtMq_#r_jjS9 +Q1j=vv_qQ_tqMj#__j4r9Q +S4_=h4_dgHs; +R:fjjNRlOqERhR7.blsHR_q1j_djj_jj1BYh_#4_JGlkN__HF.._ +=Smh(_6_.H_ +jSQ=_wBO9rj +4SQ=_wBO9r4;R +sfjj:ROlNEhRq7b.RsRHlqj1_djj_j1j_Y_hB4J_#lNkG_FH_. +_dShm=__6(H +_dS=Qjqr_H4 +g9S=Q4qr_H4;n9 +fsRjR:jlENOR7qh.sRbHqlR1d_jjj_jjY_1h4B__l#Jk_GNH._F_Sc +m_=h6H(__Sc +Qhj=__6(H +_4S=Q4h(_6_.H_;R +sfjj:ROlNEhRq7b.RsRHlqj1_djj_j1j_Y_hB4J_#lNkG_FH_. +_6Shm=__6(H +_6S=Qjh(_6_dH_ +4SQ=Hq_r94U;R +sfjj:ROlNEhRq7b.RsRHlqj1_djj_j1j_Y_hB4J_#lNkG_FH_.m +S=6h_( +_HS=Qjh(_6_cH_ +4SQ=6h_(__H6s; +R:fjjNRlOqERhR7.blsHR OD\b3Ok#_C04_4_jj__44r9m +S= OD\b3Ok#_C04_4_4j_r +49S=Qjh._44 +_HS=Q4h._4.;_H +fsRjR:jlENOR7qh.sRbHOlRD3 \O_bkC_#04j4__.j_r 49SOm=D3 \O_bkC_#04j4__4.r9Q -Sj_=h4_.dHQ -S4_=h4_.6Hs; -R:fjjNRlOqERhR7.blsHR OD\b3Ok#_C04_4_4jr9m -S= OD\b3Ok#_C04_4_4jr9Q -SjD=O O\3bCk_#40_4__j49r4 -4SQ= OD\b3Ok#_C04_4_.j_r;49 -fsRjR:jlENOR7qh.sRbHklRMOU_H_HM4m -S=4h_n4U_ -jSQ=Hq_r9.c -4SQ=Hq_r9.6;R -sfjj:ROlNEhRq7b.RsRHlk_MUOMHH_S. -m_=h4_nU.Q -Sj_=qHnr.9Q -S4_=qH(r.9s; -R:fjjNRlOqERhR7.blsHRUkM_HOHM -_dShm=_U4n_Sd -Qqj=_.HrUS9 -Qq4=_.Hrg -9;sjRf:ljRNROEq.h7RHbslMRkUH_OHcM_ -=Smhn_4U -_cS=Qjqr_Hd -j9S=Q4qr_Hd;49 -fsRjR:jlENOR7qh.sRbHklRMOU_H_HM6m -S=4h_n6U_ -jSQ=4h_n4U_ -4SQ=4h_n.U_;R -sfjj:ROlNEhRq7b.RsRHlk_MUOMHH_Sn -m_=h4_nUnQ -Sj_=h4_nUdQ -S4_=h4_nUcs; -R:fjjNRlOqERhR7.blsHRUkM_HOHMm -S=4h_nSU -Qhj=_U4n_S6 -Qh4=_U4n_ -n;sjRf:ljRNROEq.h7RHbslMRkcH_OH4M_ -=Smh(_44 -_4S=Qjqr_O. -j9S=Q4qr_O.;49 -fsRjR:jlENOR7qh.sRbHklRMOc_H_HM.m -S=4h_(.4_ -jSQ=Oq_r9.. -4SQ=Oq_r9.d;R -sfjj:ROlNEhRq7b.RsRHlk_McOMHH -=Smh(_44Q -Sj_=h4_(44Q -S4_=h4_(4.s; -R:fjjNRlOqERhR7.blsHR1z7_jjj_aQh_#j_JGlkN__44m -S=1z7_jjj_aQh_#j_JGlkN__44Q -Sj1=q_jjd_jjj_h1YB -_HS=Q47j1_dHj_;R -sfjj:ROlNEhRq7b.RsRHlz_71j_jjQ_hajJ_#lNkG_.4_ -=Smz_71j_jjQ_hajJ_#lNkG_.4_ -jSQ=_)WOQ -S4v=1_Qqvtnqr9s; -R:fjjNRlOqERhR7.blsHR1z7_jjj_aQh_#j_JGlkN__4dm -S=1z7_jjj_aQh_#j_JGlkN__4dQ -Sj7=z1j_jjh_Qa__j#kJlG4N__S4 -Qz4=7j1_jQj_hja__l#Jk_GN4;_. -fsRjR:jlENOReQhRHbslvR1_QqvtMq_#d_F_4Hr9m -S=Uh_gQ -Sj_=hUHg_;R -sfjj:ROlNEhRQesRbHhlR_U4j_SH -m_=h4_jUHQ -Sj_=h4;jU -fsRjR:jlENOReQhRHbslvR1_QqvtMq_#r_H(S9 -mv=1_QqvtMq_#9r( -jSQ=_1vqtvQq#_M_(jr9s; -R:fjjNRlOQERhbeRsRHlhU_g_SH -m_=hgHU_ -jSQ=gh_Us; -R:fjjNRlOQERhbeRsRHlhg_g_SH -m_=hgHg_ -jSQ=gh_gs; -R:fjjNRlOQERhbeRsRHl1qv_vqQt__M#H9r4 -=Sm1qv_vqQt_rM#4S9 -Q1j=vv_qQ_tqMj#_r;49 -fsRjR:jlENOReQhRHbsl_RhgH(_ -=Smh(_g_SH -Qhj=_;g( -fsRjR:jlENOR7qh.sRbH#lR0CN0_OlNECHM\M3kcOc_Dj _j8j_4 -_4S#m=0CN0_OlNECHM\M3kcOc_Dj _j8j_4__H4Q -SjQ=1ZO _r -j9S=Q4q__OH9rj;R -sfjj:ROlNEhRq7b.RsRHl#00NCN_lOMEHCk\3M_ccO_D j_jj8S4 -m0=#N_0ClENOH\MC3ckMcD_O j_jj4_8_SH -Q#j=0CN0_OlNECHM\M3kcOc_Dj _j8j_4__H4Q -S4Q=1ZO __4Hr9s; -R:fjjNRlOqERhR7.blsHR4kM__Loj_dj4m -S=4kM__Loj_djj -_4S=QjAjt_dOj__SH -Qh4=__gcHs; -R:fjjNRlOqERhR7.blsHR4kM__Loj_dj.m -S=4kM__Loj_djj -_.S=Qjqj1_dOj_ -4SQ=XM uu_1q_B Hs; -R:fjjNRlOqERhR7.blsHR4kM__Loj -djSkm=ML4_od_jj -_jS=Qjk_M4Ljo_djj__S4 -Qk4=ML4_od_jj__j.s; -R:fjjNRlOqERhR7.blsHRN#00lC_NHOEM3C\qj1_djj_j1j_Y_hBd -_4S#m=0CN0_OlNECHM\13q_jjd_jjj_h1YB__d. -_4S=Qjqj1_dHj_ -4SQ=XM uu_1q_B Os; -R:fjjNRlOqERhR7.blsHRN#00lC_NHOEM3C\qj1_djj_j1j_Y_hBdm -S=N#00lC_NHOEM3C\qj1_djj_j1j_Y_hBd -_.S=Qj#00NCN_lOMEHCq\31d_jjj_jjY_1hdB__4._ -4SQ=N#00lC_NHOEM3C\k.Mc_ OD_jjd_ -H;sjRf:ljRNROEq.h7RHbslDRO O\3bCk_#40_4__j49r4 -=SmO\D 3kOb_0C#__44jr_44S9 -Qhj=_n4._SH -Qh4=_c4._ -H;sjRf:ljRNROEQRheblsHRQqvtAq_z 1_hpqA __Hl -_HSqm=vqQt_1Az_q hA_p H__lHQ -Sjv=qQ_tqA_z1 AhqpH __ -l;sjRf:ljRNROEQRheblsHRXM uu_1q_B l -_HSMm= _Xu1Buq __lHQ -Sj =MX1u_u qB_ -l;sjRf:ljRNROEQRheblsHRN#00lC_NHOEM3C\qj1_djj_j1j_Y_hBd -_HS#m=0CN0_OlNECHM\13q_jjd_jjj_h1YB -_dS=Qj#00NCN_lOMEHCq\31d_jjj_jjY_1hdB__ -.;sjRf:ljRNROEQRheblsHRgh_c -_HShm=__gcHQ -Sj_=hg -c;sjRf:ljRNROEQRheblsHR4kM__Loj_djHm -S=4kM__Loj -djS=Qjk_M4Ljo_djj_;R -sfjj:ROlNEhRQesRbH1lRQ_Z Or_H4S9 -mQ=1ZO __4Hr9Q -SjQ=1ZO _r;49 -fsRjR:jlENOReQhRHbsl0R#N_0ClENOH\MC3ckMcD_O j_jj4_8_jH_ -=Sm#00NCN_lOMEHCk\3M_ccO_D j_jj8S4 -Q#j=0CN0_OlNECHM\M3kcOc_Dj _j8j_4;_H -fsRjR:jlENOReQhRHbsl_Rh4_j6Hm -S=4h_jH6_ -jSQ=4h_j -6;sjRf:ljRNROEQRheblsHR4h_jHc_ -=Smhj_4c -_HS=Qjhj_4cs; -R:fjjNRlOQERhbeRsRHl1qv_vqQt__M#H9r6 -=Sm1qv_vqQt_rM#6S9 -Q1j=vv_qQ_tqMj#_r;69 -fsRjR:jlENOReQhRHbsl_Rh4_jnHm -S=4h_jHn_ -jSQ=4h_j -n;sjRf:ljRNROEQRheblsHR4h_jH(_ -=Smhj_4( -_HS=Qjhj_4(s; -R:fjjNRlOQERhbeRsRHlB_pim_zau_) Hm -S=iBp_amz_ u)_SH -QBj=pmi_zua_) - ;sjRf:ljRNROEQRheblsHR_1vqtvQq#_M_FH_dr_HnS9 -m_=hgS. -Qhj=__g.js; -R:fjjNRlOQERhbeRsRHl1qv_vqQt__M#Hd_F_jHr9m -S=gh_jQ -Sj_=hgjj_;R -sfjj:ROlNEhRQesRbH#lR0CN0_OlNECHM\M3k4Od_Dj _j8j_j -_HS#m=0CN0_OlNECHM\M3k4Od_Dj _j8j_j -_HS=Qj#00NCN_lOMEHCk\3M_4dO_D j_jj8 -j;sjRf:ljRNROEQRheblsHRN#00lC_NHOEM3C\k6M4_ OD_jjj__8jHm -S=N#00lC_NHOEM3C\k6M4_ OD_jjj_ -8jS=Qj#00NCN_lOMEHCk\3M_46O_D j_jj8jj_;R -sfjj:ROlNEhRQesRbHhlR_j4j_SH -m_=h4_jjHQ -Sj_=h4;jj -fsRjR:jlENOReQhRHbslvR1_QqvtMq_#r_H.S9 -mv=1_QqvtMq_#9r. -jSQ=_1vqtvQq#_M_.jr9s; -R:fjjNRlOQERhbeRsRHlO\D 3ckM_ OD_jjj__84Hm -S= OD\M3kcD_O j_jj4_8_SH -QOj=D3 \k_McO_D j_jj8 -4;sjRf:ljRNROEQRheblsHRN#00lC_NHOEM3C\k_MnLOoN j_jj +Sj_=h4_.cHQ +S4_=h4_cnHs; +R:fjjNRlOqERhR7.blsHR OD\b3Ok#_C04_4_jj_r +49SOm=D3 \O_bkC_#04j4_r +49S=QjO\D 3kOb_0C#__44jr_44S9 +QO4=D3 \O_bkC_#04j4__4.r9s; +R:fjjNRlOqERhR7.blsHR4kM__Loj_djHd_N_S4 +m_=h4_.j4Q +Sj1=q_jjd_SO +QA4=td_jj;_H +fsRjR:jlENOR7qh.sRbHklRML4_od_jj__HN.d_ +=Smh._4j +_.S=Qj1qv_vqQtr +(9S=Q4Mu X_q1uBH _;R +sfjj:ROlNEhRq7b.RsRHlk_M4Ljo_dHj__ +NdShm=_j4. +jSQ=4h_.4j_ +4SQ=4h_..j_;R +sfjj:ROlNEhRq7b.RsRHlqj1_djj_j1j_Y_hB4J_#lNkG_NH_d +_4Shm=__(g4Q +Sjp=Bid_jj +_OS=Q4h(_6;R +sfjj:ROlNEhRq7b.RsRHlqj1_djj_j1j_Y_hB4J_#lNkG_NH_d +_.Shm=__(g.Q +Sjv=1_Qqvt(qr9Q +S4 =MX1u_u qB_ +O;sjRf:ljRNROEq.h7RHbsl1Rq_jjd_jjj_h1YB__4#kJlGHN__ +NdShm=_ +(gS=Qjhg_(_S4 +Qh4=__(g.s; +R:fjjNRlOqERhR7.blsHRq7aB1i_Y_hB4J_#lNkG_H4___Nd4m +S=(h_(__4jQ +Sja=7q_BiHQ +S4_=h(4(_;R +sfjj:ROlNEhRQesRbH#lR0CN0_OlNECHM\M3kno_LN_O j_jjj _HS#m=0CN0_OlNECHM\M3kno_LN_O j jjS=Qj#00NCN_lOMEHCk\3MLn_o NO_jjj_ j;sjRf:ljRNROEQRheblsHRN#00lC_NHOEM3C\kdM._ OD_jjj__8jH _jS#m=0CN0_OlNECHM\M3k.Od_Dj _j8j_jQ Sj0=#N_0ClENOH\MC3.kMdD_O j_jjj_8_ -H;sjRf:ljRNROEQRheblsHR_Atj_djO -_HSAm=td_jj__OHQ -Sjt=A_jjd_ -O;sjRf:ljRNROEQRheblsHRN#00lC_NHOEM3C\k_M4O_D j_djHm -S=N#00lC_NHOEM3C\k_M4O_D j -djS=Qj#00NCN_lOMEHCk\3MO4_Dj _djj_;R -sfjj:ROlNEhRQesRbH#lR0CN0_OlNECHM\M3k4O(_Dj _dHj_ -=Sm#00NCN_lOMEHCk\3M_4(O_D j -djS=Qj#00NCN_lOMEHCk\3M_4(O_D j_djjs; -R:fjjNRlOQERhbeRsRHlk_M4Nj#_ddj__SH -mM=k4#_N_jjd_Sd -Qkj=MN4_#d_jj__djs; -R:fjjNRlOQERhbeRsRHlhc_4U -_HShm=_U4c_SH -Qhj=_U4c;R -sfjj:ROlNEhRQesRbHqlR_HO_r -j9Sqm=_HO_r -j9S=Qjqr_Oj -9;sjRf:ljRNROEQRheblsHRN#00lC_NHOEM3C\z_71j_jjQ_ha( -_HS#m=0CN0_OlNECHM\73z1j_jjh_Qa -_(S=Qj#00NCN_lOMEHCz\37j1_jQj_h(a__ -j;sjRf:ljRNROEQRheblsHRN#00lC_NHOEM3C\p_71j_jjQ_ha( -_HS#m=0CN0_OlNECHM\73p1j_jjh_Qa -_(S=Qj#00NCN_lOMEHCp\37j1_jQj_h(a__ -j;sjRf:ljRNROEQRheblsHR_1vqtvQq#_M_FH_dr_HcS9 -m_=hgS4 -Qhj=__g4js; -R:fjjNRlOQERhbeRsRHlh._46 -_HShm=_64._SH -Qhj=_64.;R -sfjj:ROlNEhRQesRbHhlR_d4._SH -m_=h4_.dHQ -Sj_=h4;.d -fsRjR:jlENOReQhRHbsl_Rh4_.cHm -S=4h_.Hc_ +H;sjRf:ljRNROEq.h7RHbslMRkUH_OH4M_ +=SmhU_4U +_4S=Qjqr_H. +c9S=Q4qr_H.;69 +fsRjR:jlENOR7qh.sRbHklRMOU_H_HM.m +S=4h_U.U_ +jSQ=Hq_r9.n +4SQ=Hq_r9.(;R +sfjj:ROlNEhRq7b.RsRHlk_MUOMHH_Sd +m_=h4_UUdQ +Sj_=qHUr.9Q +S4_=qHgr.9s; +R:fjjNRlOqERhR7.blsHRUkM_HOHM +_cShm=_U4U_Sc +Qqj=_dHrjS9 +Qq4=_dHr4 +9;sjRf:ljRNROEq.h7RHbslMRkUH_OH6M_ +=SmhU_4U +_6S=QjhU_4U +_4S=Q4hU_4U;_. +fsRjR:jlENOR7qh.sRbHklRMOU_H_HMnm +S=4h_UnU_ +jSQ=4h_UdU_ +4SQ=4h_UcU_;R +sfjj:ROlNEhRq7b.RsRHlk_MUOMHH +=SmhU_4UQ +Sj_=h4_UU6Q +S4_=h4_UUns; +R:fjjNRlOqERhR7.blsHRckM_HOHM +_4Shm=_44g_S4 +Qqj=_.OrjS9 +Qq4=_.Or4 +9;sjRf:ljRNROEq.h7RHbslMRkcH_OH.M_ +=Smhg_44 +_.S=Qjqr_O. +.9S=Q4qr_O.;d9 +fsRjR:jlENOR7qh.sRbHklRMOc_H +HMShm=_44g +jSQ=4h_g44_ +4SQ=4h_g.4_;R +sfjj:ROlNEhRq7b.RsRHl#00NCN_lOMEHCk\3MOU_Dj _j8j_. +_4S#m=0CN0_OlNECHM\M3kUD_O j_jj._8_S4 +QBj=pji_j7j_dQ +S41=q_jjd_jjj_h1YB;_H +fsRjR:jlENOR7qh.sRbH#lR0CN0_OlNECHM\M3kUD_O j_jj._8 +=Sm#00NCN_lOMEHCk\3MOU_Dj _j8j_.Q +Sj0=#N_0ClENOH\MC3UkM_ OD_jjj__8.4Q +S4p=Bij_jj._7_ +H;sjRf:ljRNROEq.h7RHbsl1Rq_jjd_jjj_h1YB__4#kJlGHN___F.4m +S=6h_(__H4Q +Sj_=qO(r49Q +S4t=Aq_Bij_jjOs; +R:fjjNRlOQERhbeRsRHlhn_U_SH +m_=hUHn_ +jSQ=Uh_ns; +R:fjjNRlOQERhbeRsRHlhd_U_SH +m_=hUHd_ +jSQ=Uh_ds; +R:fjjNRlOQERhbeRsRHlh4_U_SH +m_=hUH4_ +jSQ=Uh_4s; +R:fjjNRlOQERhbeRsRHl#00NCN_lOMEHCp\37j1_jQj_h6a__Hj_ +=Sm#00NCN_lOMEHCp\37j1_jQj_h6a_ +jSQ=N#00lC_NHOEM3C\p_71j_jjQ_ha6;_j +fsRjR:jlENOReQhRHbsl0R#N_0ClENOH\MC31z7_jjj_aQh_j6__SH +m0=#N_0ClENOH\MC31z7_jjj_aQh_S6 +Q#j=0CN0_OlNECHM\73z1j_jjh_Qa__6js; +R:fjjNRlOQERhbeRsRHlhg_(_SH +m_=h(Hg_ +jSQ=(h_gs; +R:fjjNRlOQERhbeRsRHlqj1_djj_j1j_Y_hB4J_#lNkG_HH_ +=Smhj_d +jSQ=dh_j;_j +fsRjR:jlENOReQhRHbslaR7q_Bi1BYh_#4_JGlkN__4H +_HShm=_64n +jSQ=4h_nj6_;R +sfjj:ROlNEhRQesRbHhlR__(nHm +S=(h_n +_HS=Qjhn_(;R +sfjj:ROlNEhRQesRbHklRMN4_#d_jjj_jj$_#M_OUH +_HShm=_c4n +jSQ=4h_njc_;R +sfjj:ROlNEhRQesRbHelRu1q_Y_hB4J_#lNkG_H4__SH +m_=h4 +ndS=Qjhn_4d;_j +fsRjR:jlENOReQhRHbsl_Rh(H._ +=Smh._(_SH +Qhj=_;(. +fsRjR:jlENOReQhRHbsl_Rh(Hd_ +=Smhd_(_SH +Qhj=_;(d +fsRjR:jlENOReQhRHbsl0R#N_0ClENOH\MC34kM6D_O j_jjj_8_Hj_ +=Sm#00NCN_lOMEHCk\3M_46O_D j_jj8Sj +Q#j=0CN0_OlNECHM\M3k4O6_Dj _j8j_j;_j +fsRjR:jlENOReQhRHbslMRk4#_N_jjd_Hd__SH +m_=h4 +n.S=Qjhn_4.;_j +fsRjR:jlENOReQhRHbsl_Rh4_4gHm +S=4h_4Hg_ +jSQ=4h_4 +g;sjRf:ljRNROEQRheblsHR4h_4H(_ +=Smh4_4( +_HS=Qjh4_4(s; +R:fjjNRlOQERhbeRsRHlh4_4U +_HShm=_U44_SH +Qhj=_U44;R +sfjj:ROlNEhRQesRbHhlR_644_SH +m_=h4_46HQ +Sj_=h4;46 +fsRjR:jlENOReQhRHbsl_Rh4_4nHm +S=4h_4Hn_ +jSQ=4h_4 +n;sjRf:ljRNROEQRheblsHR_1vqtvQq#_M_Hj_r +(9S1m=vv_qQ_tqM(#r9Q +Sjv=1_QqvtMq_#r_j( +9;sjRf:ljRNROEQRheblsHRgh_U +_HShm=__gUHQ +Sj_=hg +U;sjRf:ljRNROEQRheblsHR4h_4Hc_ +=Smh4_4c +_HS=Qjh4_4cs; +R:fjjNRlOQERhbeRsRHl1qv_vqQt__M#H__HH9rn +=Smhg_d +jSQ=dh_g;_j +fsRjR:jlENOReQhRHbsl_RhgHc_ +=Smhc_g_SH +Qhj=_;gc +fsRjR:jlENOReQhRHbsl_RhgH(_ +=Smh(_g_SH +Qhj=_;g( +fsRjR:jlENOReQhRHbslvR1_QqvtMq_#__jH9r6 +=Sm1qv_vqQt_rM#6S9 +Q1j=vv_qQ_tqMj#_r;69 +fsRjR:jlENOReQhRHbsl_RhUHg_ +=Smhg_U_SH +Qhj=_;Ug +fsRjR:jlENOReQhRHbsl_RhgHj_ +=Smhj_g_SH +Qhj=_;gj +fsRjR:jlENOReQhRHbsl_RhUHU_ +=SmhU_U_SH +Qhj=_;UU +fsRjR:jlENOReQhRHbslpRBij_jj4_7_SH +mp=Bij_jj4_7_SH +QBj=pji_j7j_4s; +R:fjjNRlOQERhbeRsRHlO\D 3ckM_ OD_jjj__84j._F_SH +m_=h6Sn +Qhj=__6nHs; +R:fjjNRlOQERhbeRsRHlO\D 3kOb_0C#__44H__jFH._r +.9Shm=_ +66S=Qjh6_6_ +H;sjRf:ljRNROEQRheblsHRq71BQi_h4a__l#Jk_GNHd_F_SH +m_=h6S. +Qhj=__6.Hs; +R:fjjNRlOQERhbeRsRHlhc_44 +_HShm=_44c_SH +Qhj=_44c;R +sfjj:ROlNEhRQesRbHhlR_.4c_SH +m_=h4_c.HQ +Sj_=h4;c. +fsRjR:jlENOReQhRHbslbROk#_C0__jjr_HjS9 +m_=h4Sc +Qhj=__4cjs; +R:fjjNRlOQERhbeRsRHlh6_U_SH +m_=hUH6_ +jSQ=Uh_6s; +R:fjjNRlOQERhbeRsRHlhd_4g +_HShm=_g4d_SH +Qhj=_g4d;R +sfjj:ROlNEhRQesRbHhlR_j4c_SH +m_=h4_cjHQ +Sj_=h4;cj +fsRjR:jlENOReQhRHbslvR1_QqvtMq_#__jH9rj +=Sm1qv_vqQt_rM#jS9 +Q1j=vv_qQ_tqMj#_r;j9 +fsRjR:jlENOReQhRHbsl_Rh4_.6Hm +S=4h_.H6_ jSQ=4h_. -c;sjRf:ljRNROEQRheblsHR4h_.Hn_ -=Smh._4n -_HS=Qjh._4ns; -R:fjjNRlOQERhbeRsRHlO\D 3kOb_0C#__44jr_H4S9 +6;sjRf:ljRNROEQRheblsHR4h_dHU_ +=Smhd_4U +_HS=Qjhd_4Us; +R:fjjNRlOQERhbeRsRHlh(_4U +_HShm=_U4(_SH +Qhj=_U4(;R +sfjj:ROlNEhRQesRbHOlRD3 \O_bkC_#04j4__Hj_r +d9SOm=D3 \O_bkC_#04d4r9Q +SjD=O O\3bCk_#40_4r_jd +9;sjRf:ljRNROEQRheblsHR4h_.H4_ +=Smh._44 +_HS=Qjh._44s; +R:fjjNRlOQERhbeRsRHlh._4. +_HShm=_.4._SH +Qhj=_.4.;R +sfjj:ROlNEhRQesRbH1lRvv_qQ_tqMH#__Fj_.r_HcS9 +m_=hnSn +Qhj=__nnjs; +R:fjjNRlOQERhbeRsRHl1qv_vqQt__M#H__jFH._r +49Shm=_ +n6S=Qjh6_n_ +j;sjRf:ljRNROEQRheblsHR4h_cH6_ +=Smhc_46 +_HS=Qjhc_46s; +R:fjjNRlOQERhbeRsRHlk_M4qtvQqz_A1h_ q Ap_#4_JGlkN__.jd_F_SH +mM=k4v_qQ_tqA_z1 Ahqp4 __l#Jk_GN.Q +SjM=k4v_qQ_tqA_z1 Ahqp4 __l#Jk_GN.;_j +fsRjR:jlENOReQhRHbsl1R7_jjd_HO_ +=Sm7j1_dOj__SH +Q7j=1d_jj;_O +fsRjR:jlENOReQhRHbsl0R#N_0ClENOH\MC31z7_jjj_aQh_j6___FdHm +S=nh_dQ +Sj_=hnHd_;R +sfjj:ROlNEhRQesRbHOlRD3 \O_bkC_#04j4__Fj_.r_HdS9 +m_=hnS. +Qhj=__n.Hs; +R:fjjNRlOQERhbeRsRHl#00NCN_lOMEHCk\3MOn_Dj _j8j_c +_HS#m=0CN0_OlNECHM\M3knD_O j_jjc_8_SH +Q#j=0CN0_OlNECHM\M3knD_O j_jjc_8;R +sfjj:ROlNEhRQesRbH1lRvv_qQ_tqMH#__FH_.r_HnS9 +m_=hnS4 +Qhj=__n4Hs; +R:fjjNRlOQERhbeRsRHlO\D 3kOb_0C#__44j__jFH._r +49Shm=_ +njS=Qjhj_n_ +H;sjRf:ljRNROEQRheblsHR_1vqtvQq#_M_Fj_.r_H(S9 +m_=h6Sg +Qhj=__6gHs; +R:fjjNRlOQERhbeRsRHl#00NCN_lOMEHCq\3vqQt_1Az_q hA_p dj_V_FH_. +_HShm=_ +6US=QjhU_6_ +H;sjRf:ljRNROEQRheblsHR_q1j_djj_jj1BYh_#4_JGlkN__HFH._ +=Smh(_6 +jSQ=6h_(;_H +fsRjR:jlENOReQhRHbslDRO O\3bCk_#40_4__jjr_H4S9 mD=O O\3bCk_#40_49r4 jSQ= OD\b3Ok#_C04_4_4jr9s; -R:fjjNRlOQERhbeRsRHlhd_44 -_HShm=_44d_SH -Qhj=_44d;R -sfjj:ROlNEhRQesRbHOlRD3 \O_bkC_#04j4__dHr9m -S= OD\b3Ok#_C04_4r -d9S=QjO\D 3kOb_0C#__44j9rd;R -sfjj:ROlNEhRQesRbHhlR_j4d_SH -m_=h4_djHQ -Sj_=h4;dj -fsRjR:jlENOReQhRHbsl_Rh4_.gHm -S=4h_.Hg_ -jSQ=4h_. -g;sjRf:ljRNROEQRheblsHR OD\b3Ok#_C04_4_Fj_cr_HdS9 -m_=h4 -..S=Qjh._4.;_H -fsRjR:jlENOReQhRHbslDRO O\3bCk_#40_4__jFHc_r -49Shm=_44. -jSQ=4h_.H4_;R -sfjj:ROlNEhRQesRbHhlR_(4._SH -m_=h4_.(HQ -Sj_=h4;.( -fsRjR:jlENOReQhRHbsl_Rh4_.UHm -S=4h_.HU_ -jSQ=4h_. -U;sjRf:ljRNROEQRheblsHRN#00lC_NHOEM3C\k_MUO_D j_jj8Hj_ -=Sm#00NCN_lOMEHCk\3MOU_Dj _j8j_j -_HS=Qj#00NCN_lOMEHCk\3MOU_Dj _j8j_js; -R:fjjNRlOQERhbeRsRHlhj_44 -_HShm=_44j_SH -Qhj=_44j;R -sfjj:ROlNEhRQesRbHhlR_.4j_SH -m_=h4_j.HQ -Sj_=h4;j. -fsRjR:jlENOReQhRHbsl_Rh4_jdHm -S=4h_jHd_ -jSQ=4h_j -d;sjRf:ljRNROEq.h7RHbslvR1_QqvtMq_#r_HdS9 -m_=hUH._ -jSQ=iBp_jjj__7jHQ -S4_=h4_j4Hs; -R:fjjNRlOQERhbeRsRHl1qv_vqQt_dHr9m -S=_1vqtvQqr_HdS9 -Q1j=vv_qQrtqd -9;sjRf:ljRNROEq.h7RHbslvR1_QqvtMq_#__HNjd_r -c9Shm=_d4j -jSQ=_1vqtvQqr_HdS9 -Q14=vv_qQ_tqH9rc;R -sfjj:ROlNEhRQesRbHBlRpji_j7j_j -_HSBm=pji_j7j_j -_HS=QjB_pij_jj7 -j;sjRf:ljRNROEq.h7RHbslvR1_QqvtMq_#__HNcdr9m -S=4h_jS. -QBj=pji_j7j_j -_HS=Q4h4_g;R -sfjj:ROlNEhRQesRbH1lRvv_qQ_tqH9rc -=Sm1qv_vqQt_cHr9Q -Sjv=1_Qqvtcqr9s; -R:fjjNRlOQERhbeRsRHl1qv_vqQt_6Hr9m -S=_1vqtvQqr_H6S9 -Q1j=vv_qQrtq6 -9;sjRf:ljRNROEq.h7RHbslvR1_QqvtMq_#__HNddr9m -S=4h_jS4 -Q1j=vv_qQ_tqH9rc -4SQ=_1vqtvQqr_H6 -9;sjRf:ljRNROEQRheblsHR_q1j_jjQ_haHm -S=_q1j_jjQ_haHQ -Sj1=q_jjj_aQh;R -sfjj:ROlNEhRQesRbHQlR_g4j -=Sm7B1qir_H4S9 -Q7j=1iqB_4Or9s; -R:fjjNRlOqERhR7.blsHRN#00lC_NHOEM3C\kcM4__N#j_jjH -M0S#m=0CN0_OlNECHM\M3k4Nc_#j_jjM_H0Q -Sj1=q_jjj_aQh_SH -Q74=1iqB_4Hr9s; -R:fjjNRlOQERhbeRsRHlO_bkC_#0j__43Ss -mb=Ok#_C0__j4k_3MSd -QOj=D3 \k_McO_D j_jj8 -4;sjRf:ljRNROEq.h7RHbslbROk#_C0__j4l_3 -=SmO_bkC_#0j__434kM -jSQ= OD\b3Ok#_C04_4r -49S=Q4O\D 3ckM_ OD_jjj_;84 -fsRjR:jlENOR7qh.sRbHOlRbCk_#j0__34_Mm -S=kOb_0C#_4j__M3kjQ -Sjb=Ok#_C09r4 -4SQ=kOb_0C#_4j__M3kds; -R:fjjNRlOmER)b.RsRHlO_bkC_#0j__43Sb -m_=h4S6 -QOj=bCk_#j0__34_k -M4S=Q4O_bkC_#0j__43jkM;R -sfjj:ROlNEhRQesRbH)lRW -_HS)m=W -_HS=Qj)OW_;R -sfjj:ROlNEhRQesRbHQlR_j44 +R:fjjNRlOQERhbeRsRHlh._4c +_HShm=_c4._SH +Qhj=_c4.;R +sfjj:ROlNEhRQesRbHhlR_n4c_SH +m_=h4_cnHQ +Sj_=h4;cn +fsRjR:jlENOReQhRHbslvR1_QqvtHq_r +d9S1m=vv_qQ_tqH9rd +jSQ=_1vqtvQq9rd;R +sfjj:ROlNEhRq7b.RsRHl1qv_vqQt__M#H__jFc.r9m +S=nh_n +_jS=Qj1qv_vqQtr +d9S=Q4#00NCN_lOMEHCk\3M_.dO_D j_jj8Hj_;R +sfjj:ROlNEhRQesRbHAlRtd_jj +_HSAm=td_jj +_HS=QjAjt_dOj_;R +sfjj:ROlNEhRQesRbHMlR _Xu1Buq +_HSMm= _Xu1Buq +_HS=QjMu X_q1uBO _;R +sfjj:ROlNEhRQesRbHQlR_c44 =Sm7Baqi _HS=Qj7Baqi;_O fsRjR:jlENOReQhRHbslbROk#_C0r_H4S9 mb=Ok#_C0r_H4S9 QOj=bCk_#40r9s; -R:fjjNRlOQERhbeRsRHle_uq7 -_HSem=u7q__SH -Qej=u7q_;R -sfjj:ROlNEhRq7b.RsRHl#00NCN_lOMEHCk\3M_4dO_D j_jj84j_ -=Sm#00NCN_lOMEHCk\3M_4dO_D j_jj84j_ -jSQ=_q1j_jjQ -haS=Q4B_pij_jj7 -j;sjRf:ljRNROEq.h7RHbsl0R#N_0ClENOH\MC34kMdD_O j_jjj_8_S. -m0=#N_0ClENOH\MC34kMdD_O j_jjj_8_S. -QOj=bCk_#40r9Q -S4b=Ok#_C09r.;R -sfjj:ROlNEmRX)b.RsRHlO_bkC_#0j9rj -=Smhc_4 -jSQ= OD\M3kcD_O j_jj4_8 -4SQ=kOb_0C#r;j9 -fsRjR:jlENOR7qh.sRbHOlRD3 \O_bkC_#04j4___Nc.9r4 -=Smh._4nQ -Sjb=Ok#_C09rd -4SQ=N#00lC_NHOEM3C\kdM4_ OD_jjj__8j.s; -R:fjjNRlOqERhR7.blsHR OD\b3Ok#_C04_4_Nj_cr_44S9 -m_=h4 -.6S=Qjh._44 -_HS=Q4O_bkCr#0j -9;sjRf:ljRNROEQRheblsHRkOb_0C#_dHr9m -S=kOb_0C#_dHr9Q -Sjb=Ok#_C09rd;R +R:fjjNRlOqERhR7.blsHRqeu_h1YB__4#kJlG4N__NH_d +_.Shm=__((4Q +Sjp=Bij_jjj_7 +4SQ=_1vqtvQq9rd;R +sfjj:ROlNEhRQesRbHelRvQq_hHa_ +=Sme_vqQ_haHQ +Sjv=eqh_Qas; +R:fjjNRlOQERhbeRsRHlO_bkC_#0H9rj +=SmO_bkC_#0H9rj +jSQ=kOb_0C#r;j9 +fsRjR:jlENOReQhRHbslbROk#_C0r_HdS9 +mb=Ok#_C0r_HdS9 +QOj=bCk_#d0r9s; +R:fjjNRlOQERhbeRsRHlB_pij_jj7Hj_ +=SmB_pij_jj7Hj_ +jSQ=iBp_jjj_;7j +fsRjR:jlENOReQhRHbsluReq__7Hm +S=qeu_H7_ +jSQ=qeu_ +7;sjRf:ljRNROEQRheblsHR_)WHm +S=_)WHQ +SjW=)_ +O;sjRf:ljRNROEQRheblsHRN#00lC_NHOEM3C\z_71j_jjQ_ha6__jls.3 +=Sm#00NCN_lOMEHCz\37j1_jQj_h6a__lj_.M3kdQ +SjW=)_ +O;sjRf:ljRNROEq.h7RHbsl0R#N_0ClENOH\MC31z7_jjj_aQh_j6__3l.lm +S=N#00lC_NHOEM3C\z_71j_jjQ_ha6__jlk.3MS4 +Q1j=vv_qQrtq6S9 +Q)4=W;_O +fsRjR:jlENOR7qh.sRbH#lR0CN0_OlNECHM\73z1j_jjh_Qa__6j._l3SM +m0=#N_0ClENOH\MC31z7_jjj_aQh_j6__3l.k +MjS=Qj1qv_vqQtr +c9S=Q4#00NCN_lOMEHCz\37j1_jQj_h6a__lj_.M3kds; +R:fjjNRlOmER)b.RsRHl#00NCN_lOMEHCz\37j1_jQj_h6a__lj_. +3bShm=_ +64S=Qj#00NCN_lOMEHCz\37j1_jQj_h6a__lj_.M3k4Q +S40=#N_0ClENOH\MC31z7_jjj_aQh_j6__3l.k;Mj +fsRjR:jlENOR7qh.sRbH7lR1iqB_aQh_#4_JGlkN__HFSd +m_=h6H._ +jSQ=_q1j_djHQ +S4_=h(Hc_;R sfjj:ROlNEhRQesRbHOlRbCk_#H0_r .9SOm=bCk_#H0_r .9S=QjO_bkCr#0. -9;sjRf:ljRNROEq.h7RHbslDRO O\3bCk_#40_4__jNjc_r -49Shm=_c4. +9;sjRf:ljRNROEq.h7RHbslDRO O\3bCk_#40_4__Hj._Fr +.9Shm=__66HQ +Sjb=Ok#_C09r4 +4SQ=kOb_0C#r;.9 +fsRjR:jlENOR7qh.sRbHOlRD3 \k_McO_D j_jj8j4__ +F.Shm=__6nHQ +Sjp=Bij_jjj_7 +4SQ=iBp_jjj__74Hs; +R:fjjNRlOQERhbeRsRHl1qv_vqQt_nHr9m +S=_1vqtvQqr_HnS9 +Q1j=vv_qQrtqn +9;sjRf:ljRNROEq.h7RHbsl0R#N_0ClENOH\MC3QqvtAq_z 1_hpqA __dVHj__ +F.Shm=__6UHQ +Sjv=1_Qqvtnqr9Q +S4 =MX1u_u qB_ +O;sjRf:ljRNROEQRheblsHR_q1j_jjQ_haHm +S=_q1j_jjQ_haHQ +Sj1=q_jjj_aQh;R +sfjj:ROlNEhRq7b.RsRHl1qv_vqQt__M#j._Fr +(9Shm=__6gHQ +Sj1=q_jjj_aQh +4SQ=iBp_jjj_;7j +fsRjR:jlENOR7qh.sRbHOlRD3 \O_bkC_#04j4__Fj_.9r4 +=Smhj_n_SH +QOj=bCk_#H0_r +49S=Q4O_bkC_#0H9rd;R +sfjj:ROlNEhRq7b.RsRHl1qv_vqQt__M#H__HFn.r9m +S=nh_4 +_HS=QjB_pij_jj7Hj_ +4SQ=N#00lC_NHOEM3C\k_MnO_D j_jj8Hc_;R +sfjj:ROlNEhRq7b.RsRHlO\D 3kOb_0C#__44j__jFd.r9m +S=nh_. +_HS=QjO_bkCr#0jS9 +QO4=bCk_#40r9s; +R:fjjNRlOqERhR7.blsHRN#00lC_NHOEM3C\z_71j_jjQ_ha6__jFSd +m_=hnHd_ +jSQ=_71j_djO +_HS=Q4h4_6;R +sfjj:ROlNEhRq7b.RsRHlk_M4qtvQqz_A1h_ q Ap_#4_JGlkN__.jd_F +=Smk_M4qtvQqz_A1h_ q Ap_#4_JGlkN__.jQ +Sj_=h6H._ +4SQ=4h_cH6_;R +sfjj:ROlNEhRq7b.RsRHl1qv_vqQt__M#H__jF4.r9m +S=nh_6 +_jS=QjB_pij_jj7Hj_ +4SQ=6h_U;_H +fsRjR:jlENOR7qh.sRbHklRMN4_#d_jjj_jj$_#M_OUHm +S=4h_njc_ +jSQ=_q1j_djHQ +S4_=h(Hn_;R +sfjj:ROlNEhRq7b.RsRHl7BaqiY_1h4B__l#Jk_GN4 +_HShm=_64n_Sj +Qqj=1d_jj +_HS=Q4h(_(_ +H;sjRf:ljRNROEq.h7RHbsl1Rq_jjd_jjj_h1YB__4#kJlGHN_ +=Smhj_d_Sj +Qhj=__(gHQ +S4M=k4v_qQ_tqA_z1 Ahqp4 __l#Jk_GN.;_j +fsRjR:jlENOR7qh.sRbH#lR0CN0_OlNECHM\73z1j_jjh_Qa__6jm +S=N#00lC_NHOEM3C\z_71j_jjQ_ha6 +_jS=Qjqr_HjS9 +Qh4=__ndHs; +R:fjjNRlOqERhR7.blsHRN#00lC_NHOEM3C\p_71j_jjQ_ha6 +_jS#m=0CN0_OlNECHM\73p1j_jjh_Qa__6jQ +Sj_=hnHd_ +4SQ=Uh_4;_H +fsRjR:jlENOR7qh.sRbH1lRvv_qQ_tqMH#__4jr9m +S=(h_U +_HS=Qjhd_U_SH +Qh4=__U6Hs; +R:fjjNRlOqERhR7.blsHR_1vqtvQq#_M_jH_r +.9Shm=__UjHQ +Sjp=Bij_jjj_7 +4SQ=Uh_n;_H +fsRjR:jlENOR7qh.sRbH1lRvv_qQ_tqMH#__djr9m +S=Uh_. +_HS=QjB_pij_jj7Hj_ +4SQ=Uh_U;_H +fsRjR:jlENOR7qh.sRbH1lRvv_qQ_tqMH#__cjr9m +S=Uh_c +_HS=Qjhg_U_SH +Qh4=__gjHs; +R:fjjNRlOqERhR7.blsHR_1vqtvQq#_M_6jr9m +S=_1vqtvQq#_M_6jr9Q +Sj_=hgHc_ +4SQ=gh_(;_H +fsRjR:jlENOR7qh.sRbH1lRvv_qQ_tqMH#__nHr9m +S=dh_g +_jS=QjhU_g_SH +Qh4=_c44_ +H;sjRf:ljRNROEq.h7RHbslvR1_QqvtMq_#r_j(S9 +mv=1_QqvtMq_#r_j(S9 +Qhj=_644_SH +Qh4=_n44_ +H;sjRf:ljRNROEq.h7RHbslDRO O\3bCk_#40_4__Hj9r. +=Smh._4d +_HS=Qjh4_4( +_HS=Q4h4_4U;_H +fsRjR:jlENOR7qh.sRbH#lR0CN0_OlNECHM\v3qQ_tqA_z1 Ahqpd ___VjHm +S=ch_d +_HS=QjhU_6 +4SQ=4h_4Hg_;R +sfjj:ROlNEhRq7b.RsRHlO_bkC_#0jr_jjS9 +m_=h4jc_ +jSQ=4h_cH4_ +4SQ=4h_cH._;R +sfjj:ROlNEhRq7b.RsRHlO\D 3kOb_0C#__44j__jN4dr9m +S=4h_.S4 +Qhj=_ +njS=Q4O_bkC_#0H9rj;R +sfjj:ROlNEhRq7b.RsRHlO\D 3kOb_0C#__44j__jNjd_r +49Shm=_.4. jSQ=kOb_0C#_.Hr9Q S4b=Ok#_C0r_Hd -9;sjRf:ljRNROEQRheblsHRkOb_0C#_jHr9m -S=kOb_0C#_jHr9Q -Sjb=Ok#_C09rj;R -sfjj:ROlNEhRq7b.RsRHlO\D 3kOb_0C#__44jc_Nr -49Shm=_d4. -jSQ=4h_.S4 -QO4=bCk_#H0_r;j9 -fsRjR:jlENOR7qh.sRbH1lRvv_qQ_tqMH#__rFdcS9 -m_=hgj4_ -jSQ=_1vqtvQq9rd -4SQ=N#00lC_NHOEM3C\kdM._ OD_jjj__8jHs; -R:fjjNRlOqERhR7.blsHR_1vqtvQq#_M_cHr9m -S=Uh_c -_HS=Qjhj_4. -_HS=Q4hj_4d;_H -fsRjR:jlENOReQhRHbslbROk#_C0__jds_3 -=SmO_bkC_#0j__d3dkM -jSQ= OD\M3kcD_O j_jj4_8;R -sfjj:ROlNEhRq7b.RsRHlO_bkC_#0j__d3Sl -mb=Ok#_C0__jdk_3MS4 -QOj=D3 \O_bkC_#04d4r9Q -S4D=O k\3MOc_Dj _j8j_4s; -R:fjjNRlOqERhR7.blsHRkOb_0C#_dj__ -3MSOm=bCk_#j0__3d_k -MjS=QjO_bkCr#0dS9 -QO4=bCk_#j0__3d_k;Md -fsRjR:jlENOR.m)RHbslbROk#_C0__jdb_3 -=Smh(_4 -jSQ=kOb_0C#_dj__M3k4Q -S4b=Ok#_C0__jdk_3M -j;sjRf:ljRNROEQRheblsHRpQu_jjd_jj__ -3sSQm=ujp_djj__3j_k -MdS=QjO\D 3ckM_ OD_jjj_;84 -fsRjR:jlENOR7qh.sRbHQlRujp_djj__3j_lm -S=pQu_jjd_jj__M3k4Q -Sju=Qpr_OjS9 -QO4=D3 \k_McO_D j_jj8 -4;sjRf:ljRNROEq.h7RHbsluRQpd_jj__jjM_3 -=SmQ_upj_djj__j3jkM -jSQ=pQu_jjd_jOr9Q -S4u=Qpd_jj__jjk_3M -d;sjRf:ljRNROEmR).blsHRpQu_jjd_jj__ -3bShm=_ -4US=QjQ_upj_djj__j34kM -4SQ=pQu_jjd_jj__M3kjs; -R:fjjNRlOQERhbeRsRHlQ_upj_djj__43Ss -mu=Qpd_jj__j4k_3MSd -QOj=D3 \k_McO_D j_jj8 -4;sjRf:ljRNROEq.h7RHbsluRQpd_jj__j4l_3 -=SmQ_upj_djj__434kM -jSQ=pQu_4Or9Q -S4D=O k\3MOc_Dj _j8j_4s; -R:fjjNRlOqERhR7.blsHRpQu_jjd_4j__ -3MSQm=ujp_djj__34_k -MjS=QjQ_upj_djO9r4 -4SQ=pQu_jjd_4j__M3kds; -R:fjjNRlOmER)b.RsRHlQ_upj_djj__43Sb -m_=h4Sg -QQj=ujp_djj__34_k -M4S=Q4Q_upj_djj__43jkM;R -sfjj:ROlNEhRQesRbHQlRujp_djj__3._sm -S=pQu_jjd_.j__M3kdQ -SjD=O k\3MOc_Dj _j8j_4s; -R:fjjNRlOqERhR7.blsHRpQu_jjd_.j__ -3lSQm=ujp_djj__3._k -M4S=QjQ_upO9r. -4SQ= OD\M3kcD_O j_jj4_8;R -sfjj:ROlNEhRq7b.RsRHlQ_upj_djj__.3SM -mu=Qpd_jj__j.k_3MSj -QQj=ujp_dOj_r -.9S=Q4Q_upj_djj__.3dkM;R -sfjj:ROlNE)Rm.sRbHQlRujp_djj__3._bm -S=.h_jQ -Sju=Qpd_jj__j.k_3MS4 -QQ4=ujp_djj__3._k;Mj -fsRjR:jlENOR7qh.sRbH#lR0CN0_OlNECHM\M3k.D_O j_jjm -S=N#00lC_NHOEM3C\k_M.O_D j -jjS=QjB_pij_jj7Sj -QB4=pji_jOj_;R -sfjj:ROlNEhRQesRbHBlRpji_j7j_4 -_HSBm=pji_j7j_4 -_HS=QjB_pij_jj7 -4;sjRf:ljRNROEq.h7RHbslDRO k\3MOc_Dj _j8j_4m -S= OD\M3kcD_O j_jj4_8 -jSQ=iBp_jjj_ -7jS=Q4B_pij_jj7H4_;R -sfjj:ROlNEhRq7b.RsRHl#00NCN_lOMEHCk\3M_46O_D j_jj8Sj -m0=#N_0ClENOH\MC34kM6D_O j_jjj_8_Sj -Q#j=0CN0_OlNECHM\M3kUD_O j_jjj_8_SH -Q#4=0CN0_OlNECHM\M3k4Od_Dj _j8j_j;_H -fsRjR:jlENOR7qh.sRbHOlRD3 \O_bkC_#04j4__rNcdS9 -m_=h4 -.gS=Qjh._4.Q +9;sjRf:ljRNROEq.h7RHbslDRO O\3bCk_#40_4__jjd_N_44r9m +S=4h_.Sc +Qhj=__66HQ S4b=Ok#_C09rd;R -sfjj:ROlNEhRq7b.RsRHlO\D 3kOb_0C#__44jc_N_djr9m -S=4h_dSj -Qhj=_.4._SH -QO4=bCk_#H0_r;.9 -fsRjR:jlENOR7qh.sRbHOlRD3 \O_bkC_#04H4_r -.9Shm=_U44_SH -Qhj=_(4._SH -Qh4=_U4._ -H;sjRf:ljRNROEq.h7RHbslDRO O\3bCk_#40_4__jF4cr9m -S=4h_.H4_ -jSQ=kOb_0C#_4Hr9Q -S4b=Ok#_C0r_Hd -9;sjRf:ljRNROEq.h7RHbslDRO O\3bCk_#40_4__jFdcr9m -S=4h_.H._ -jSQ=kOb_0C#r -j9S=Q4O_bkCr#04 -9;sjRf:ljRNROEQRheblsHRN#00lC_NHOEM3C\kdM4_ OD_jjj__8j. -_HS#m=0CN0_OlNECHM\M3k4Od_Dj _j8j_j__.HQ -Sj0=#N_0ClENOH\MC34kMdD_O j_jjj_8_ -.;sjRf:ljRNROEQRheblsHRqev_aQh_SH -mv=eqh_Qa -_HS=Qje_vqQ;ha -fsRjR:jlENOReQhRHbsl7Rz1j_jjh_Qa3_jsm -S=1z7_jjj_aQh_kj3MSd -Qkj=MN4_#d_jj;_c -fsRjR:jlENOR7qh.sRbHzlR7j1_jQj_hja_3Sl -m7=z1j_jjh_Qa3_jk -M4S=Qjz_71j_jjQ -haS=Q4k_M4Nj#_dcj_;R -sfjj:ROlNEhRq7b.RsRHlz_71j_jjQ_haj -3MSzm=7j1_jQj_hja_3jkM -jSQ=N#00lC_NHOEM3C\z_71j_jjQ_ha(Q -S47=z1j_jjh_Qa3_jk;Md -fsRjR:jlENOR.m)RHbsl7Rz1j_jjh_Qa3_jbm -S=4h_ -jSQ=1z7_jjj_aQh_kj3MS4 -Qz4=7j1_jQj_hja_3jkM;R -sfjj:ROlNEhRq7b.RsRHl#00NCN_lOMEHCk\3M_.dO_D j_jj8Sj -m0=#N_0ClENOH\MC3.kMdD_O j_jjj_8_SH -Q7j=aiqB_h1YBQ -S4u=eqY_1h -B;sjRf:ljRNROEQRheblsHRqeu_h1YB3_jsm -S=qeu_h1YB3_jk -MdS=Qje_uq1BYh_#4_JGlkN;_4 -fsRjR:jlENOR7qh.sRbHelRu1q_Y_hBj -3lSem=u1q_Y_hBjM3k4Q -Sju=eqY_1hSB -Qe4=u1q_Y_hB4J_#lNkG_ -4;sjRf:ljRNROEq.h7RHbsluReqY_1hjB_3SM -mu=eqY_1hjB_3jkM -jSQ=qeu_h1YB__4#kJlGHN_ -4SQ=qeu_h1YB3_jk;Md -fsRjR:jlENOR.m)RHbsluReqY_1hjB_3Sb -m_=hcQ -Sju=eqY_1hjB_34kM -4SQ=qeu_h1YB3_jk;Mj -fsRjR:jlENOReQhRHbsl1Rq_jjj_aQh_sj3 -=Smqj1_jQj_hja_3dkM -jSQ=_q1j_jjQ_ha4J_#lNkG;R -sfjj:ROlNEhRq7b.RsRHlqj1_jQj_hja_3Sl -m1=q_jjj_aQh_kj3MS4 -Qqj=1j_jjh_QaQ -S41=q_jjj_aQh_#4_JGlkNs; -R:fjjNRlOqERhR7.blsHR_q1j_jjQ_haj -3MSqm=1j_jjh_Qa3_jk -MjS=Qjh6_g_SH -Qq4=1j_jjh_Qa3_jk;Md -fsRjR:jlENOR.m)RHbsl1Rq_jjj_aQh_bj3 -=Smh -_(S=Qjqj1_jQj_hja_34kM -4SQ=_q1j_jjQ_hajM3kjs; -R:fjjNRlOQERhbeRsRHlABtqid_jjh_Qa3_jsm -S=qAtBji_dQj_hja_3dkM -jSQ=N#00lC_NHOEM3C\k_MnLOoN j_jjs; -R:fjjNRlOqERhR7.blsHRqAtBji_dQj_hja_3Sl -mt=Aq_Bij_djQ_hajM3k4Q +sfjj:ROlNEhRq7b.RsRHlO\D 3kOb_0C#__44j__jNddr9m +S=4h_.S6 +Qhj=_ +n.S=Q4O_bkCr#0d +9;sjRf:ljRNROEq.h7RHbslDRO O\3bCk_#40_4__jjd_N_djr9m +S=4h_(SU +Qhj=__n.HQ +S4b=Ok#_C0r_H. +9;sjRf:ljRNROEq.h7RHbslvR1_QqvtMq_#__jNjdr9m +S=4h_dSg +QBj=pji_j7j_j +_HS=Q4hc_46s; +R:fjjNRlOqERhR7.blsHR_1vqtvQq#_M_Nj_dr_jjS9 +m_=h4 +cjS=Qjhg_6_SH +Q14=vv_qQrtqj +9;sjRf:ljRNROEq.h7RHbslbROk#_C0__jjd_Nr +j9Shm=_44c +jSQ=6h_nQ +S4b=Ok#_C09rj;R +sfjj:ROlNEhRq7b.RsRHlO_bkC_#0j__jNjd_r +j9Shm=_.4c +jSQ=6h_n +_HS=Q4O_bkC_#0H9rj;R +sfjj:ROlNEhRq7b.RsRHl1qv_vqQt__M#j._Nr +j9Shm=_64c +jSQ=_1vqtvQq9rn +4SQ=XM uu_1q_B Hs; +R:fjjNRlOqERhR7.blsHR OD\b3Ok#_C04_4_jj__rN.4S9 +m_=h4 +cnS=Qjhj_n_SH +QO4=bCk_#j0r9s; +R:fjjNRlOqERhR7.blsHRN#00lC_NHOEM3C\k_MnLOoN j_jj +_jS#m=0CN0_OlNECHM\M3kno_LN_O j_jjjQ Sjt=Aq_Bij_jjOQ -S40=#N_0ClENOH\MC3nkM_NLoOj _j -j;sjRf:ljRNROEq.h7RHbsltRAq_Bij_djQ_haj -3MSAm=tiqB_jjd_aQh_kj3MSj -QAj=tiqB_jjd_aQh -4SQ=qAtBji_dQj_hja_3dkM;R -sfjj:ROlNE)Rm.sRbHAlRtiqB_jjd_aQh_bj3 -=Smh._4 -jSQ=qAtBji_dQj_hja_34kM -4SQ=qAtBji_dQj_hja_3jkM;R -sfjj:ROlNEhRq7b.RsRHl#00NCN_lOMEHCk\3MLn_o NO_jjj -=Sm#00NCN_lOMEHCk\3MLn_o NO_jjj_Sj -QAj=tiqB_jjj_SO -QO4=D3 \k_McO_D j_jj8H4_;R -sfjj:ROlNEhRQesRbHhlR__g6Hm -S=gh_6 -_HS=Qjh6_g;R -sfjj:ROlNEhRq7b.RsRHlqj1_jQj_h4a__l#Jk -GNSqm=1j_jjh_Qa__4#kJlGSN -Qqj=1d_jj -_HS=Q4h6_g_ -H;sjRf:ljRNROEQRheblsHRqeu_h1YB__4#kJlGHN_ -=Sme_uq1BYh_#4_JGlkN -_HS=Qje_uq1BYh_#4_JGlkNs; -R:fjjNRlOQERhbeRsRHlqj1_dHj_ -=Smqj1_dHj_ -jSQ=_q1j_djOs; -R:fjjNRlOqERhR7.blsHRqeu_h1YB__4#kJlG4N_ -=Sme_uq1BYh_#4_JGlkN -_4S=Qjqj1_dHj_ -4SQ=qeu_h1YB__4#kJlGHN_;R -sfjj:ROlNEhRq7b.RsRHl1qv_vqQt__M#N.dr9m -S=4h_jSj -QBj=pji_j7j_jQ -S4v=1_Qqvt6qr9s; -R:fjjNRlOqERhR7.blsHR_1vqtvQq#_Mr -.9S1m=vv_qQ_tqMj#_r -.9S=Qjh6_g_SH -Qh4=_j4j_ -H;sjRf:ljRNROEQRheblsHRqev_aQh_sj3 -=Sme_vqQ_hajM3kdQ -Sj0=#N_0ClENOH\MC34kM6D_O j_jjj_8;R -sfjj:ROlNEhRq7b.RsRHle_vqQ_haj -3lSem=vQq_hja_34kM -jSQ=4h_.S4 -Q#4=0CN0_OlNECHM\M3k4O6_Dj _j8j_js; -R:fjjNRlOqERhR7.blsHRqev_aQh_Mj3 -=Sme_vqQ_hajM3kjQ -Sjv=eqh_QaQ -S4v=eqh_Qa3_jk;Md -fsRjR:jlENOR.m)RHbslvReqh_Qa3_jbm -S=4h_4Q -Sjv=eqh_Qa3_jk -M4S=Q4e_vqQ_hajM3kjs; -R:fjjNRlOQERhbeRsRHlO_bkC_#0j__.3Ss -mb=Ok#_C0__j.k_3MSd -QOj=D3 \k_McO_D j_jj8 -4;sjRf:ljRNROEq.h7RHbslbROk#_C0__j.l_3 -=SmO_bkC_#0j__.34kM -jSQ=4h_4HU_ -4SQ= OD\M3kcD_O j_jj4_8;R -sfjj:ROlNEhRq7b.RsRHlO_bkC_#0j__.3SM -mb=Ok#_C0__j.k_3MSj -QOj=bCk_#.0r9Q -S4b=Ok#_C0__j.k_3M -d;sjRf:ljRNROEmR).blsHRkOb_0C#_.j__ -3bShm=_ -4nS=QjO_bkC_#0j__.34kM -4SQ=kOb_0C#_.j__M3kjs; -R:fjjNRlOqERhR7.blsHRN#00lC_NHOEM3C\k(M4_ OD_jjd -=Sm#00NCN_lOMEHCk\3M_4(O_D j_djjQ -Sj1=q_jjd_SH -QB4=pji_dHj_;R -sfjj:ROlNEhRQesRbHBlRpji_dHj_ -=SmB_pij_djHQ -Sjp=Bid_jj;_O -fsRjR:jlENOR7qh.sRbH#lR0CN0_OlNECHM\M3k4D_O d_jjm -S=N#00lC_NHOEM3C\k_M4O_D j_djjQ -Sjt=A_jjd_HO_ -4SQ=iBp_jjd_ -O;sjRf:ljRNROEQRheblsHRHq_r94g -=Smqr_H4 -g9S=Qjqr_O4;g9 -fsRjR:jlENOReQhRHbsl_RqHUr49m -S=Hq_r94U -jSQ=Oq_r94U;R -sfjj:ROlNEhRQesRbHqlR_4HrnS9 -m_=qHnr49Q -Sj_=qOnr49s; -R:fjjNRlOQERhbeRsRHlhn_g_SH -m_=hgHn_ -jSQ=gh_ns; -R:fjjNRlOQERhbeRsRHl7B1qih_Qa__j4s_3 -=Sm7B1qih_Qa__j4k_3MSd -Q7j=1iqB_aQh_#4_JGlkNs; -R:fjjNRlOqERhR7.blsHRq71BQi_hja__34_lm -S=q71BQi_hja__34_k -M4S=Qj7B1qih_Qa9r4 -4SQ=q71BQi_h4a__l#Jk;GN -fsRjR:jlENOR7qh.sRbH7lR1iqB_aQh_4j__ -3MS7m=1iqB_aQh_4j__M3kjQ -Sj_=hgHn_ -4SQ=q71BQi_hja__34_k;Md -fsRjR:jlENOR.m)RHbsl1R7q_BiQ_haj__43Sb -m_=h4Sj -Q7j=1iqB_aQh_4j__M3k4Q -S41=7q_BiQ_haj__43jkM;R -sfjj:ROlNEhRQesRbHAlRtj_jj3_jsm -S=_Atj_jjjM3kdQ -Sj0=#N_0ClENOH\MC34kM_ OD_jjd;R -sfjj:ROlNEhRq7b.RsRHlAjt_jjj_3Sl -mt=A_jjj_kj3MS4 -Qkj=ML4_od_jjQ -S40=#N_0ClENOH\MC34kM_ OD_jjd;R -sfjj:ROlNEhRq7b.RsRHlAjt_jjj_3SM -mt=A_jjj_kj3MSj -QAj=tj_jj -_OS=Q4Ajt_jjj_3dkM;R -sfjj:ROlNE)Rm.sRbHAlRtj_jj3_jbm -S=gh_ -jSQ=_Atj_jjjM3k4Q -S4t=A_jjj_kj3M -j;sjRf:ljRNROEQRheblsHRQqvtAq_z 1_hpqA 3_jsm -S=QqvtAq_z 1_hpqA 3_jk -MdS=Qj)_1aOs; -R:fjjNRlOqERhR7.blsHRQqvtAq_z 1_hpqA 3_jlm -S=QqvtAq_z 1_hpqA 3_jk -M4S=Qj#00NCN_lOMEHCq\3vqQt_1Az_q hA_p .P_H_SH -Q)4=1Oa_;R -sfjj:ROlNEhRq7b.RsRHlqtvQqz_A1h_ q Ap_Mj3 -=SmqtvQqz_A1h_ q Ap_kj3MSj -Qqj=vqQt_1Az_q hA_p OQ -S4v=qQ_tqA_z1 Ahqpj _3dkM;R -sfjj:ROlNE)Rm.sRbHqlRvqQt_1Az_q hA_p j -3bShm=_SU -Qqj=vqQt_1Az_q hA_p jM3k4Q -S4v=qQ_tqA_z1 Ahqpj _3jkM;R -sfjj:ROlNEhRQesRbHqlR1d_jjj_jjY_1hjB_3Ss -m1=q_jjd_jjj_h1YB3_jk -MdS=Qj#00NCN_lOMEHCk\3M_4(O_D j;dj -fsRjR:jlENOR7qh.sRbHqlR1d_jjj_jjY_1hjB_3Sl -m1=q_jjd_jjj_h1YB3_jk -M4S=Qj#00NCN_lOMEHCq\31d_jjj_jjY_1hdB_ -4SQ=N#00lC_NHOEM3C\k(M4_ OD_jjd;R -sfjj:ROlNEhRq7b.RsRHlqj1_djj_j1j_Y_hBj -3MSqm=1d_jjj_jjY_1hjB_3jkM -jSQ=_q1j_djj_jj1BYh -4SQ=_q1j_djj_jj1BYh_kj3M -d;sjRf:ljRNROEmR).blsHR_q1j_djj_jj1BYh_bj3 -=Smh -_nS=Qjqj1_djj_j1j_Y_hBjM3k4Q -S41=q_jjd_jjj_h1YB3_jk;Mj -fsRjR:jlENOReQhRHbsluRwz1_B_aQh_sj3 -=Smw_uzBQ1_hja_3dkM -jSQ=N#00lC_NHOEM3C\k(M4_ OD_jjd;R -sfjj:ROlNEhRq7b.RsRHlw_uzBQ1_hja_3Sl -mu=wz1_B_aQh_kj3MS4 -Qkj=MN4_#d_jj -_dS=Q4#00NCN_lOMEHCk\3M_4(O_D j;dj -fsRjR:jlENOR7qh.sRbHwlRuBz_1h_Qa3_jMm -S=zwu__B1Q_hajM3kjQ -Sju=wz1_B_aQh -4SQ=zwu__B1Q_hajM3kds; -R:fjjNRlOmER)b.RsRHlw_uzBQ1_hja_3Sb -m_=h6Q -Sju=wz1_B_aQh_kj3MS4 -Qw4=uBz_1h_Qa3_jk;Mj -fsRjR:jlENOReQhRHbslaR7q_Bi1BYh_#4_JGlkN -_HS7m=aiqB_h1YB__4#kJlGHN_ -jSQ=q7aB1i_Y_hB4J_#lNkG;R -sfjj:ROlNEhRQesRbH7lRaiqB_h1YB3_jsm -S=q7aB1i_Y_hBjM3kdQ -Sja=7q_Bi1BYh_#4_JGlkN;_4 -fsRjR:jlENOR7qh.sRbH7lRaiqB_h1YB3_jlm -S=q7aB1i_Y_hBjM3k4Q -Sja=7q_Bi1BYh -4SQ=q7aB1i_Y_hB4J_#lNkG_ -4;sjRf:ljRNROEq.h7RHbslaR7q_Bi1BYh_Mj3 -=Sm7BaqiY_1hjB_3jkM -jSQ=q7aB1i_Y_hB4J_#lNkG_SH -Q74=aiqB_h1YB3_jk;Md -fsRjR:jlENOR.m)RHbslaR7q_Bi1BYh_bj3 -=Smh -_dS=Qj7BaqiY_1hjB_34kM -4SQ=q7aB1i_Y_hBjM3kjs; -R:fjjNRlOQERhbeRsRHlp_71j_jjQ_haj -3sSpm=7j1_jQj_hja_3dkM -jSQ=4kM__N#j_djcs; -R:fjjNRlOqERhR7.blsHR1p7_jjj_aQh_lj3 -=Smp_71j_jjQ_hajM3k4Q -Sj7=p1j_jjh_QaQ -S4M=k4#_N_jjd_ -c;sjRf:ljRNROEq.h7RHbsl7Rp1j_jjh_Qa3_jMm -S=1p7_jjj_aQh_kj3MSj -Q#j=0CN0_OlNECHM\73p1j_jjh_Qa -_(S=Q4p_71j_jjQ_hajM3kds; -R:fjjNRlOmER)b.RsRHlp_71j_jjQ_haj -3bShm=_S. -Qpj=7j1_jQj_hja_34kM -4SQ=1p7_jjj_aQh_kj3M -j;sjRf:ljRNROEQRheblsHRXM uu_1q_B Hm -S=XM uu_1q_B HQ -Sj =MX1u_u qB_ -O;sjRf:ljRNROEQRheblsHRQqvtAq_z 1_hpqA +S4_=h6 +n;sjRf:ljRNROEq.h7RHbslMRk4#_N_jjd_Hd_ +=Smhn_4. +_jS=Qjqj1_dHj_ +4SQ=nh_ds; +R:fjjNRlOqERhR7.blsHRN#00lC_NHOEM3C\k6M4_ OD_jjj__8jjm +S=N#00lC_NHOEM3C\k6M4_ OD_jjj__8jjQ +Sj_=h(H._ +4SQ=(h_d;_H +fsRjR:jlENOR7qh.sRbHelRu1q_Y_hB4J_#lNkG_H4_ +=Smhn_4d +_jS=Qjqj1_dHj_ +4SQ=(h_6;_H +fsRjR:jlENOReQhRHbsl0R#N_0ClENOH\MC3UkM_ OD_jjj__8.Hm +S=N#00lC_NHOEM3C\k_MUO_D j_jj8H._ +jSQ=N#00lC_NHOEM3C\k_MUO_D j_jj8 +.;sjRf:ljRNROEq.h7RHbslvR1_QqvtMq_#__Hjd_N_4jr9m +S=Uh_6Q +Sjv=1_Qqvt(qr9Q +S40=#N_0ClENOH\MC3UkM_ OD_jjj__8.Hs; +R:fjjNRlOqERhR7.blsHR_1vqtvQq#_M_jH__rNd.S9 +m_=hUSn +Q1j=vv_qQ_tqH9r6 +4SQ=_1vqtvQqr_Hn +9;sjRf:ljRNROEQRheblsHR_1vqtvQqr_H6S9 +mv=1_QqvtHq_r +69S=Qj1qv_vqQtr;69 +fsRjR:jlENOR7qh.sRbH1lRvv_qQ_tqMH#__Nj_d9rd +=SmhU_U +jSQ=_1vqtvQqr_HcS9 +Q14=vv_qQ_tqH9r6;R +sfjj:ROlNEhRq7b.RsRHl1qv_vqQt__M#H__jNcdr9m +S=Uh_gQ +Sjp=Bij_jjj_7_SH +Qh4=_;nn +fsRjR:jlENOReQhRHbslvR1_QqvtHq_r +c9S1m=vv_qQ_tqH9rc +jSQ=_1vqtvQq9rc;R +sfjj:ROlNEhRq7b.RsRHl1qv_vqQt__M#H__jNjd_r +c9Shm=_ +gjS=Qj1qv_vqQt_dHr9Q +S4v=1_QqvtHq_r;c9 +fsRjR:jlENOR7qh.sRbH1lRvv_qQ_tqMj#__rNd6S9 +m_=hgSc +QBj=pji_j7j_j +_HS=Q41qv_vqQtr;.9 +fsRjR:jlENOR7qh.sRbH1lRvv_qQ_tqMH#__NH_d9rn +=SmhU_g +jSQ=nh_4Q +S4v=1_Qqvt4qr9s; +R:fjjNRlOqERhR7.blsHR_1vqtvQq#_M_HH___Ndj9rn +=Smh4_4cQ +Sjp=Bij_jjj_7 +4SQ=_1vqtvQq9r.;R +sfjj:ROlNEhRq7b.RsRHl1qv_vqQt__M#jd_Nr +(9Shm=_644 +jSQ=6h_gQ +S4v=1_Qqvtjqr9s; +R:fjjNRlOqERhR7.blsHR_1vqtvQq#_M_Nj_dr_j(S9 +m_=h4 +4nS=Qjh4_n_SH +Q14=vv_qQrtq4 +9;sjRf:ljRNROEQRheblsHRQqvtAq_z 1_hpqA _HSqm=vqQt_1Az_q hA_p HQ Sjv=qQ_tqA_z1 AhqpO _;R -sfjj:ROlNEhRq7b.RsRHl#00NCN_lOMEHCq\3vqQt_1Az_q hA_p .P_H -=Sm#00NCN_lOMEHCq\3vqQt_1Az_q hA_p .P_H_SH -Qqj=vqQt_1Az_q hA_p H__lHQ -S4 =MX1u_u qB_Hl_;R -sfjj:ROlNEhRq7b.RsRHlMu X_q1uBl _ -=SmMu X_q1uBl _ -jSQ=_1vqtvQq9rn -4SQ=XM uu_1q_B Os; -R:fjjNRlOqERhR7.blsHR4kM__1vqtvQq__j#kJlGHN__ -NdShm=_ -g6S=Qjhg_U_SH -Q14=vv_qQrtqn -9;sjRf:ljRNROEQRheblsHR_1vqtvQqr_HnS9 -mv=1_QqvtHq_r -n9S=Qj1qv_vqQtr;n9 -fsRjR:jlENOReQhRHbslvR1_QqvtHq_r -(9S1m=vv_qQ_tqH9r( -jSQ=_1vqtvQq9r(;R -sfjj:ROlNEhRq7b.RsRHl#00NCN_lOMEHCk\3MO6_Dj _dHj__ -NdShm=_ -gcS=Qj1qv_vqQt_nHr9Q -S4v=1_QqvtHq_r;(9 -fsRjR:jlENOR7qh.sRbH#lR0CN0_OlNECHM\73p1j_jjh_Qa -_(S#m=0CN0_OlNECHM\73p1j_jjh_Qa__(jQ -Sj_=h4_cUHQ -S40=#N_0ClENOH\MC3ckMcD_O j_jj4_8;R -sfjj:ROlNEhRq7b.RsRHl#00NCN_lOMEHCz\37j1_jQj_h(a_ -=Sm#00NCN_lOMEHCz\37j1_jQj_h(a__Sj -Qqj=_HO_r -j9S=Q4hc_4U;_H -fsRjR:jlENOR7qh.sRbH7lRaiqB_h1YB__4#kJlG4N_ -=Sm7BaqiY_1h4B__l#Jk_GN4Q -Sj1=q_jjd_SH -Q74=aiqB_h1YB__4#kJlGHN_;R -sfjj:ROlNEhRq7b.RsRHlk_M4Nj#_dcj_ -=Smk_M4Nj#_dcj_ -jSQ=_q1j_djHQ -S4_=h4;cU -fsRjR:jlENOReQhRHbsl0R#N_0ClENOH\MC3ckM.D_O d_jj -_HS#m=0CN0_OlNECHM\M3kcO._Dj _dHj_ -jSQ=N#00lC_NHOEM3C\k.Mc_ OD_jjd;R -sfjj:ROlNEhRq7b.RsRHlk_M4Nj#_ddj_ -=Smk_M4Nj#_ddj__Sj -Qqj=1d_jj -_HS=Q4#00NCN_lOMEHCk\3M_c.O_D j;dj -fsRjR:jlENOR7qh.sRbH7lR1iqB_aQh_#4_JGlkNm -S=q71BQi_h4a__l#Jk -GNS=Qjqj1_dHj_ -4SQ=gh_n;_H -fsRjR:jlENOR7qh.sRbHklRMN4_#d_jj__cgSn -m_=h4 -cUS=Qjz_71j_jjQ_hajJ_#lNkG_H4_ -4SQ=1z7_jjj_aQh_#j_JGlkN;_H -fsRjR:jlENOReQhRHbsl1Rq_jjd_jjj_h1YB -_HSqm=1d_jjj_jjY_1hHB_ -jSQ=_q1j_djj_jj1BYh;R -sfjj:ROlNEhRQesRbH7lR1d_jj -_HS7m=1d_jj -_HS=Qj7j1_dOj_;R -sfjj:ROlNEmRX)b.RsRHlB_pim_zau_) jm -S=4h_dQ -Sjp=Biz_ma)_u Q -S4D=O O\3DO _M -0;sjRf:ljRNROEX.m)RHbsl_RtgS4 -mM=kdD_O M_O09r4 -jSQ=iBp_aBhr -j9S=Q4B_piBrha4 -9;sjRf:ljRNROEX.m)RHbsl_RtUS( -m_=h4 -ddS=QjB_piBrha4S9 -QB4=p)i_ 4wr9s; -R:fjjNRlOXERmR).blsHRUt_nm -S=4h_dS. -QBj=pBi_hjar9Q -S4p=Bi _)w9rj;R -sfjj:ROlNEhRq7b.RsRHl1qv_vqQt__M#Hd_Fr -n9Shm=__g.jQ -Sjp=Biz_ma)_u -_HS=Q41qv_vqQt_.Hr9s; -R:fjjNRlOqERhR7.blsHR_1vqtvQq#_M_nHr9m -S=Uh_( -_HS=Qjhj_4n -_HS=Q4hj_4(;_H -fsRjR:jlENOR7qh.sRbH1lRvv_qQ_tqM6#r9m -S=_1vqtvQq#_M_6jr9Q -Sj_=h4_jcHQ -S4_=h4_j6Hs; -R:fjjNRlOQERhbeRsRHl1qv_vqQt_.Hr9m -S=_1vqtvQqr_H.S9 -Q1j=vv_qQrtq. -9;sjRf:ljRNROEQRheblsHR_1vqtvQqr_H4S9 -mv=1_QqvtHq_r -49S=Qj1qv_vqQtr;49 -fsRjR:jlENOR7qh.sRbH1lRvv_qQ_tqMH#___Ndj9rn -=Smhj_4(Q -Sjv=1_QqvtHq_r -49S=Q41qv_vqQt_.Hr9s; -R:fjjNRlOqERhR7.blsHR_1vqtvQq#_M_NH_d9rn -=Smhj_4nQ -Sjp=Bij_jjj_7_SH -Qh4=_;g. -fsRjR:jlENOR7qh.sRbH1lRvv_qQ_tqMN#_d9r6 -=Smhj_4cQ -Sjp=Bij_jjj_7_SH -Q14=vv_qQrtq. -9;sjRf:ljRNROEq.h7RHbslDRO B\3pBi_hda_r -j9SOm=D3 \B_piB_had9rj -jSQ=iBp_aBh_jHr9Q -S4D=O O\3DO _MH0_;R +sfjj:ROlNEhRQesRbHqlR1d_jj +_HSqm=1d_jj +_HS=Qjqj1_dOj_;R sfjj:ROlNEhRQesRbHOlRD3 \O_D O_M0Hm S= OD\D3O M_O0 _HS=QjO\D 3 OD_0OM;R @@ -2071,62 +1792,64 @@ sfjj:ROlNEhRq7b.RsRHlO\D 3iBp_aBh_4dr9m S= OD\p3Bih_Bar_d4S9 QOj=D3 \O_D O_M0HQ S4M=kdD_O M_O09r4;R -sfjj:ROlNEhRq7b.RsRHl1qv_vqQt__M#Hd_Nr -j9Shm=_ -g(S=Qjhj_g -4SQ=_1vqtvQqr_H( -9;sjRf:ljRNROEq.h7RHbslvR1_QqvtMq_#d_Nr -49Shm=_ -gUS=Qjhg_U -4SQ=_1vqtvQq9rn;R -sfjj:ROlNEhRq7b.RsRHl1qv_vqQt__M#Njd_r -49Shm=_ -ggS=QjB_pij_jj7Hj_ -4SQ=_1vqtvQq9r(;R -sfjj:ROlNEhRQesRbH#lR0CN0_OlNECHM\M3k4Od_Dj _j8j_j__4Hm -S=N#00lC_NHOEM3C\kdM4_ OD_jjj__8j4 -_HS=Qj#00NCN_lOMEHCk\3M_4dO_D j_jj84j_;R -sfjj:ROlNEhRq7b.RsRHl1qv_vqQt__M#N(dr9m -S=4h_jSU -Q1j=vv_qQrtqjS9 -Q#4=0CN0_OlNECHM\M3k4Od_Dj _j8j_j__4Hs; -R:fjjNRlOqERhR7.blsHR_1vqtvQq#_M_jHr9m -S=(h_U -_HS=QjB_pij_jj7Sj -Qh4=__g(Hs; -R:fjjNRlOqERhR7.blsHR_1vqtvQq#_Mr -49S1m=vv_qQ_tqMj#_r -49S=QjhU_g_SH -Qh4=__ggHs; -R:fjjNRlOqERhR7.blsHR_1vqtvQq#_Mr -(9S1m=vv_qQ_tqMj#_r -(9S=Qjhn_g_SH -Qh4=_U4j_ -H;sjRf:ljRNROEq.h7RHbslvR1_QqvtMq_#d_Fr -49Shm=__UgHQ -Sj1=q_jjd_jjj_h1YB -_HS=Q4#00NCN_lOMEHCk\3M_djO_D j_jj8 -4;sjRf:ljRNROEq.h7RHbslvR1_QqvtMq_#__HFjdr9m -S=gh_j -_jS=Qjqj1_jQj_hSa -Q14=vv_qQrtqj -9;sjRf:ljRNROEQRheblsHR1z7_jjj_aQh_#j_JGlkN__4Hm -S=1z7_jjj_aQh_#j_JGlkN__4HQ -Sj7=z1j_jjh_Qa__j#kJlG4N_;R -sfjj:ROlNEhRQesRbHzlR7j1_jQj_hja__l#Jk_GNHm -S=1z7_jjj_aQh_#j_JGlkN -_HS=Qjz_71j_jjQ_hajJ_#lNkG;R -sfjj:ROlNEhRQesRbHhlR_.4d_SH -m_=h4_d.HQ -Sj_=h4;d. -fsRjR:jlENOReQhRHbsl_Rh4_ddHm -S=4h_dHd_ -jSQ=4h_d -d;sjRf:ljRNROEq.h7RHbsl_RtUSU -mD=O O\3DO _MS0 -Qhj=_.4d_SH -Qh4=_d4d_ -H;sjRf:ljRNROEQRheblsHRHq_r9.c +sfjj:ROlNEmRX)b.RsRHlB_pim_zau_) jm +S=4h_4Q +Sjp=Biz_ma)_u Q +S4D=O O\3DO _M +0;sjRf:ljRNROEX.m)RHbsl_RtgSn +mM=kdD_O M_O09r4 +jSQ=iBp_aBhr +j9S=Q4B_piBrha4 +9;sjRf:ljRNROEX.m)RHbsl_RtgS. +m_=h4 +d(S=QjB_piBrha4S9 +QB4=p)i_ 4wr9s; +R:fjjNRlOqERhR7.blsHRN#00lC_NHOEM3C\k_M4O_D j_djHd_N +=Smhg_n +jSQ=_Atj_djHQ +S4p=Bid_jj;_O +fsRjR:jlENOR7qh.sRbHqlR1j_jjh_Qa__4#kJlGjN__ +NdSqm=1j_jjh_Qa__4#kJlGSN +Qqj=1d_jj +_HS=Q41qv_vqQt_6Hr9s; +R:fjjNRlOQERhbeRsRHlQ4_46m +S=q71BHi_r +49S=Qj7B1qir_O4 +9;sjRf:ljRNROEq.h7RHbsl0R#N_0ClENOH\MC3(kM__N#j_jjH_M0jd_N +=Sm#00NCN_lOMEHCk\3MN(_#j_jjM_H0Q +Sj1=q_jjj_aQh_SH +Q74=1iqB_4Hr9s; +R:fjjNRlOqERhR7.blsHR4kM_q71BQi_hja__l#Jk_GNH._F_NH_dm +S=(h_cQ +Sjv=1_Qqvt4qr9Q +S40=#N_0ClENOH\MC3nkM_ OD_jjj_;8c +fsRjR:jlENOR7qh.sRbHklRMN4_#d_jjj_jj$_#M_OUHd_N +=Smhn_( +jSQ=iBp_jjd_SO +Qh4=__6(Hs; +R:fjjNRlOQERhbeRsRHlqr_HjS9 +m_=qH9rj +jSQ=Oq_r;j9 +fsRjR:jlENOReQhRHbslQR1ZH _r +49S1m=Q_Z H9r4 +jSQ=Z1Q r_O4 +9;sjRf:ljRNROEQRheblsHR_1vqtvQqr_H(S9 +mv=1_QqvtHq_r +(9S=Qj1qv_vqQtr;(9 +fsRjR:jlENOR7qh.sRbH1lRvv_qQ_tqMH#__Nj_d9r4 +=Smhd_U +jSQ=nh_6Q +S4v=1_QqvtHq_r;(9 +fsRjR:jlENOReQhRHbsl_RqHnr49m +S=Hq_r94n +jSQ=Oq_r94n;R +sfjj:ROlNEhRQesRbHqlR_4HrUS9 +m_=qHUr49Q +Sj_=qOUr49s; +R:fjjNRlOQERhbeRsRHlqr_H4 +g9Sqm=_4HrgS9 +Qqj=_4Org +9;sjRf:ljRNROEQRheblsHRHq_r9.c =Smqr_H. c9S=Qjqr_O.;c9 fsRjR:jlENOReQhRHbsl_RqH6r.9m @@ -2150,36 +1873,333 @@ Sj_=qOjrd9s; R:fjjNRlOQERhbeRsRHlqr_Hd 49Sqm=_dHr4S9 Qqj=_dOr4 -9;sjRf:ljRNROEQRheblsHRiBp_jjj__7.Hm -S=iBp_jjj__7.HQ -Sjp=Bij_jj._7;R -sfjj:ROlNEhRq7b.RsRHl#00NCN_lOMEHCk\3M_djO_D j_jj8S4 -m0=#N_0ClENOH\MC3dkMjD_O j_jj4_8 -jSQ=iBp_jjj_ -74S=Q4B_pij_jj7H._;R -sfjj:ROlNEhRQesRbHBlRpBi_hHa_r -j9SBm=pBi_hHa_r -j9S=QjB_piBrhaj -9;sjRf:ljRNROEQRheblsHRN#00lC_NHOEM3C\kcM4__N#j_jjH_M0Hm -S=N#00lC_NHOEM3C\kcM4__N#j_jjH_M0HQ -Sj0=#N_0ClENOH\MC34kMc#_N_jjj_0HM;R +9;sjRf:ljRNROEQRheblsHR_q1j_djj_jj1BYh_SH +m1=q_jjd_jjj_h1YB +_HS=Qjqj1_djj_j1j_Y;hB +fsRjR:jlENOReQhRHbslpRBij_jj._7_SH +mp=Bij_jj._7_SH +QBj=pji_j7j_.s; +R:fjjNRlOQERhbeRsRHlB_piB_haH9rj +=SmB_piB_haH9rj +jSQ=iBp_aBhr;j9 +fsRjR:jlENOR7qh.sRbHOlRD3 \B_piB_had9rj +=SmO\D 3iBp_aBh_jdr9Q +Sjp=Bih_Bar_HjS9 +QO4=D3 \O_D O_M0Hs; +R:fjjNRlOQERhbeRsRHl#00NCN_lOMEHCk\3MN(_#j_jjM_H0 +_HS#m=0CN0_OlNECHM\M3k(#_N_jjj_0HM_SH +Q#j=0CN0_OlNECHM\M3k(#_N_jjj_0HM;R sfjj:ROlNEhRQesRbH)lR1Ha_ =Sm)_1aHQ Sj1=)a;_O -fsRjR:jlENORq7paR1]blsHRiBp_w) r -j9SBT=p)i_ jwr97 -S=7th -qSpah=t71 -S=a)1_ -H;sjRf:ljRNROE7apq)b]RsRHlB_pi)r w4S9 -Tp=Bi _)w9r4 -=S7t -h7Sapq=7th -=S))_1aHs; -R:fjjNRlOQERhbeRsRHlABtqid_jjh_Qa -_HSAm=tiqB_jjd_aQh_SH -QAj=tiqB_jjd_aQh;R -sfjj:ROlNEhRQesRbHwlRuBz_1h_Qa -_HSwm=uBz_1h_Qa -_HS=Qjw_uzBQ1_h -a; +fsRjR:jlENOReQhRHbsl_Rh4_d(Hm +S=4h_dH(_ +jSQ=4h_d +(;sjRf:ljRNROEq.h7RHbsl_RtgSd +mD=O O\3DO _MS0 +QBj=pBi_hHa_r +j9S=Q4hd_4(;_H +fsRjR:jlENOReQhRHbsluReqY_1hjB_3Ss +mu=eqY_1hjB_3dkM +jSQ=4h_n +d;sjRf:ljRNROEq.h7RHbsluReqY_1hjB_3Sl +mu=eqY_1hjB_34kM +jSQ=(h_6 +_HS=Q4hn_4ds; +R:fjjNRlOqERhR7.blsHRqeu_h1YB3_jMm +S=qeu_h1YB3_jk +MjS=Qje_uq1BYh +4SQ=qeu_h1YB3_jk;Md +fsRjR:jlENOR.m)RHbsluReqY_1hjB_3Sb +m_=h6Q +Sju=eqY_1hjB_34kM +4SQ=qeu_h1YB3_jk;Mj +fsRjR:jlENOReQhRHbslvRqQ_tqA_z1 Ahqpj _3Ss +mv=qQ_tqA_z1 Ahqpj _3dkM +jSQ=a)1_ +O;sjRf:ljRNROEq.h7RHbslvRqQ_tqA_z1 Ahqpj _3Sl +mv=qQ_tqA_z1 Ahqpj _34kM +jSQ=ch_d +_HS=Q4)_1aOs; +R:fjjNRlOqERhR7.blsHRQqvtAq_z 1_hpqA 3_jMm +S=QqvtAq_z 1_hpqA 3_jk +MjS=QjqtvQqz_A1h_ q Ap_SO +Qq4=vqQt_1Az_q hA_p jM3kds; +R:fjjNRlOmER)b.RsRHlqtvQqz_A1h_ q Ap_bj3 +=Smh +_nS=QjqtvQqz_A1h_ q Ap_kj3MS4 +Qq4=vqQt_1Az_q hA_p jM3kjs; +R:fjjNRlOQERhbeRsRHlz_71j_jjQ_haj +3sSzm=7j1_jQj_hja_3dkM +jSQ=4h_n +.;sjRf:ljRNROEq.h7RHbsl7Rz1j_jjh_Qa3_jlm +S=1z7_jjj_aQh_kj3MS4 +Q#j=0CN0_OlNECHM\73z1j_jjh_Qa +_6S=Q4hn_4.s; +R:fjjNRlOqERhR7.blsHR1z7_jjj_aQh_Mj3 +=Smz_71j_jjQ_hajM3kjQ +Sj7=z1j_jjh_QaQ +S47=z1j_jjh_Qa3_jk;Md +fsRjR:jlENOR.m)RHbsl7Rz1j_jjh_Qa3_jbm +S=(h_ +jSQ=1z7_jjj_aQh_kj3MS4 +Qz4=7j1_jQj_hja_3jkM;R +sfjj:ROlNEhRQesRbHplR7j1_jQj_hja_3Ss +m7=p1j_jjh_Qa3_jk +MdS=Qjhn_4.s; +R:fjjNRlOqERhR7.blsHR1p7_jjj_aQh_lj3 +=Smp_71j_jjQ_hajM3k4Q +Sj0=#N_0ClENOH\MC31p7_jjj_aQh_S6 +Qh4=_.4n;R +sfjj:ROlNEhRq7b.RsRHlp_71j_jjQ_haj +3MSpm=7j1_jQj_hja_3jkM +jSQ=1p7_jjj_aQh +4SQ=1p7_jjj_aQh_kj3M +d;sjRf:ljRNROEmR).blsHR1p7_jjj_aQh_bj3 +=Smh +_US=Qjp_71j_jjQ_hajM3k4Q +S47=p1j_jjh_Qa3_jk;Mj +fsRjR:jlENOReQhRHbslvReqh_Qa3_jsm +S=qev_aQh_kj3MSd +Q#j=0CN0_OlNECHM\M3k4O6_Dj _j8j_js; +R:fjjNRlOqERhR7.blsHRqev_aQh_lj3 +=Sme_vqQ_hajM3k4Q +Sjb=Ok#_C09r4 +4SQ=N#00lC_NHOEM3C\k6M4_ OD_jjj_;8j +fsRjR:jlENOR7qh.sRbHelRvQq_hja_3SM +mv=eqh_Qa3_jk +MjS=Qje_vqQ +haS=Q4e_vqQ_hajM3kds; +R:fjjNRlOmER)b.RsRHle_vqQ_haj +3bShm=_Sg +Qej=vQq_hja_34kM +4SQ=qev_aQh_kj3M +j;sjRf:ljRNROEQRheblsHR4h_.Hj_ +=Smh._4j +_HS=Qjh._4js; +R:fjjNRlOQERhbeRsRHlAjt_jjj_3Ss +mt=A_jjj_kj3MSd +Qhj=_;ng +fsRjR:jlENOR7qh.sRbHAlRtj_jj3_jlm +S=_Atj_jjjM3k4Q +Sjt=A_jjj_SO +Qh4=_;ng +fsRjR:jlENOR7qh.sRbHAlRtj_jj3_jMm +S=_Atj_jjjM3kjQ +Sj_=h4_.jHQ +S4t=A_jjj_kj3M +d;sjRf:ljRNROEmR).blsHR_Atj_jjj +3bShm=_ +4jS=QjAjt_jjj_34kM +4SQ=_Atj_jjjM3kjs; +R:fjjNRlOQERhbeRsRHlABtqid_jjh_Qa3_jsm +S=qAtBji_dQj_hja_3dkM +jSQ=N#00lC_NHOEM3C\k_MnLOoN j_jjs; +R:fjjNRlOqERhR7.blsHRqAtBji_dQj_hja_3Sl +mt=Aq_Bij_djQ_hajM3k4Q +Sjt=Aq_Bij_jjOQ +S40=#N_0ClENOH\MC3nkM_NLoOj _j +j;sjRf:ljRNROEq.h7RHbsltRAq_Bij_djQ_haj +3MSAm=tiqB_jjd_aQh_kj3MSj +QAj=tiqB_jjd_aQh +4SQ=qAtBji_dQj_hja_3dkM;R +sfjj:ROlNE)Rm.sRbHAlRtiqB_jjd_aQh_bj3 +=Smh._4 +jSQ=qAtBji_dQj_hja_34kM +4SQ=qAtBji_dQj_hja_3jkM;R +sfjj:ROlNEhRQesRbHqlR1j_jjh_Qa3_jsm +S=_q1j_jjQ_hajM3kdQ +Sj1=q_jjj_aQh_#4_JGlkNs; +R:fjjNRlOqERhR7.blsHR_q1j_jjQ_haj +3lSqm=1j_jjh_Qa3_jk +M4S=Qjqj1_jQj_hSa +Qq4=1j_jjh_Qa__4#kJlG +N;sjRf:ljRNROEq.h7RHbsl1Rq_jjj_aQh_Mj3 +=Smqj1_jQj_hja_3jkM +jSQ=_1vqtvQqr_H6S9 +Qq4=1j_jjh_Qa3_jk;Md +fsRjR:jlENOR.m)RHbsl1Rq_jjj_aQh_bj3 +=Smhd_4 +jSQ=_q1j_jjQ_hajM3k4Q +S41=q_jjj_aQh_kj3M +j;sjRf:ljRNROEQRheblsHRkOb_0C#_4j__ +3sSOm=bCk_#j0__34_k +MdS=Qjhn_6;R +sfjj:ROlNEhRq7b.RsRHlO_bkC_#0j__43Sl +mb=Ok#_C0__j4k_3MS4 +QOj=bCk_#40r9Q +S4_=h6 +n;sjRf:ljRNROEq.h7RHbslbROk#_C0__j4M_3 +=SmO_bkC_#0j__43jkM +jSQ= OD\b3Ok#_C04_4r +49S=Q4O_bkC_#0j__43dkM;R +sfjj:ROlNE)Rm.sRbHOlRbCk_#j0__34_bm +S=4h_6Q +Sjb=Ok#_C0__j4k_3MS4 +QO4=bCk_#j0__34_k;Mj +fsRjR:jlENOReQhRHbslbROk#_C0__j.s_3 +=SmO_bkC_#0j__.3dkM +jSQ=6h_ns; +R:fjjNRlOqERhR7.blsHRkOb_0C#_.j__ +3lSOm=bCk_#j0__3._k +M4S=QjO_bkCr#0.S9 +Qh4=_;6n +fsRjR:jlENOR7qh.sRbHOlRbCk_#j0__3._Mm +S=kOb_0C#_.j__M3kjQ +Sj_=h4_.dHQ +S4b=Ok#_C0__j.k_3M +d;sjRf:ljRNROEmR).blsHRkOb_0C#_.j__ +3bShm=_ +4nS=QjO_bkC_#0j__.34kM +4SQ=kOb_0C#_.j__M3kjs; +R:fjjNRlOQERhbeRsRHlO_bkC_#0j__d3Ss +mb=Ok#_C0__jdk_3MSd +Qhj=_;6n +fsRjR:jlENOR7qh.sRbHOlRbCk_#j0__3d_lm +S=kOb_0C#_dj__M3k4Q +Sjb=Ok#_C09rd +4SQ=6h_ns; +R:fjjNRlOqERhR7.blsHRkOb_0C#_dj__ +3MSOm=bCk_#j0__3d_k +MjS=QjO\D 3kOb_0C#_r44dS9 +QO4=bCk_#j0__3d_k;Md +fsRjR:jlENOR.m)RHbslbROk#_C0__jdb_3 +=Smh(_4 +jSQ=kOb_0C#_dj__M3k4Q +S4b=Ok#_C0__jdk_3M +j;sjRf:ljRNROEQRheblsHRpQu_jjd_jj__ +3sSQm=ujp_djj__3j_k +MdS=Qjhn_6;R +sfjj:ROlNEhRq7b.RsRHlQ_upj_djj__j3Sl +mu=Qpd_jj__jjk_3MS4 +QQj=ujp_dOj_r +j9S=Q4hn_6;R +sfjj:ROlNEhRq7b.RsRHlQ_upj_djj__j3SM +mu=Qpd_jj__jjk_3MSj +QQj=uOp_r +j9S=Q4Q_upj_djj__j3dkM;R +sfjj:ROlNE)Rm.sRbHQlRujp_djj__3j_bm +S=4h_UQ +Sju=Qpd_jj__jjk_3MS4 +QQ4=ujp_djj__3j_k;Mj +fsRjR:jlENOReQhRHbsluRQpd_jj__j4s_3 +=SmQ_upj_djj__43dkM +jSQ=6h_ns; +R:fjjNRlOqERhR7.blsHRpQu_jjd_4j__ +3lSQm=ujp_djj__34_k +M4S=QjQ_upj_djO9r4 +4SQ=6h_ns; +R:fjjNRlOqERhR7.blsHRpQu_jjd_4j__ +3MSQm=ujp_djj__34_k +MjS=QjQ_upO9r4 +4SQ=pQu_jjd_4j__M3kds; +R:fjjNRlOmER)b.RsRHlQ_upj_djj__43Sb +m_=h4Sg +QQj=ujp_djj__34_k +M4S=Q4Q_upj_djj__43jkM;R +sfjj:ROlNEhRQesRbHQlRujp_djj__3._sm +S=pQu_jjd_.j__M3kdQ +Sj_=h6 +n;sjRf:ljRNROEq.h7RHbsluRQpd_jj__j.l_3 +=SmQ_upj_djj__.34kM +jSQ=pQu_jjd_.Or9Q +S4_=h6 +n;sjRf:ljRNROEq.h7RHbsluRQpd_jj__j.M_3 +=SmQ_upj_djj__.3jkM +jSQ=pQu_.Or9Q +S4u=Qpd_jj__j.k_3M +d;sjRf:ljRNROEmR).blsHRpQu_jjd_.j__ +3bShm=_ +.jS=QjQ_upj_djj__.34kM +4SQ=pQu_jjd_.j__M3kjs; +R:fjjNRlO7ERp)qa]sRbHBlRp)i_ 4wr9T +S=iBp_w) r +49St7=hS7 +p=qat +h7S))=1Ha_;R +sfjj:ROlNEhRq7b.RsRHl#00NCN_lOMEHCk\3M_.dO_D j_jj8Sj +m0=#N_0ClENOH\MC3.kMdD_O j_jjj_8_SH +Q7j=aiqB_h1YBQ +S4u=eqY_1h +B;sjRf:ljRNROEQRheblsHRiBp_jjj__76Hm +S=iBp_jjj__76HQ +Sjp=Bij_jj6_7;R +sfjj:ROlNEhRq7b.RsRHl#00NCN_lOMEHCk\3MOn_Dj _j8j_cm +S=N#00lC_NHOEM3C\k_MnO_D j_jj8Sc +QBj=pji_j7j_cQ +S4p=Bij_jj6_7_ +H;sjRf:ljRNROEQRheblsHRqAtBji_dQj_hHa_ +=SmABtqid_jjh_Qa +_HS=QjABtqid_jjh_Qas; +R:fjjNRlOQERhbeRsRHlw_uzBQ1_hHa_ +=Smw_uzBQ1_hHa_ +jSQ=zwu__B1Q;ha +fsRjR:jlENOReQhRHbsl1Rq_jjd_jjj_h1YB3_jsm +S=_q1j_djj_jj1BYh_kj3MSd +Qhj=_;dj +fsRjR:jlENOR7qh.sRbHqlR1d_jjj_jjY_1hjB_3Sl +m1=q_jjd_jjj_h1YB3_jk +M4S=Qjk_M4qtvQqz_A1h_ q Ap_#4_JGlkN +_.S=Q4hj_d;R +sfjj:ROlNEhRq7b.RsRHlqj1_djj_j1j_Y_hBj +3MSqm=1d_jjj_jjY_1hjB_3jkM +jSQ=_q1j_djj_jj1BYh +4SQ=_q1j_djj_jj1BYh_kj3M +d;sjRf:ljRNROEmR).blsHR_q1j_djj_jj1BYh_bj3 +=Smh +_4S=Qjqj1_djj_j1j_Y_hBjM3k4Q +S41=q_jjd_jjj_h1YB3_jk;Mj +fsRjR:jlENOReQhRHbsl_Rh(H(_ +=Smh(_(_SH +Qhj=_;(( +fsRjR:jlENOReQhRHbslaR7q_Bi1BYh_sj3 +=Sm7BaqiY_1hjB_3dkM +jSQ=4h_n +6;sjRf:ljRNROEq.h7RHbslaR7q_Bi1BYh_lj3 +=Sm7BaqiY_1hjB_34kM +jSQ=(h_( +_HS=Q4hn_46s; +R:fjjNRlOqERhR7.blsHRq7aB1i_Y_hBj +3MS7m=aiqB_h1YB3_jk +MjS=Qj7BaqiY_1hSB +Q74=aiqB_h1YB3_jk;Md +fsRjR:jlENOR.m)RHbslaR7q_Bi1BYh_bj3 +=Smh +_.S=Qj7BaqiY_1hjB_34kM +4SQ=q7aB1i_Y_hBjM3kjs; +R:fjjNRlOQERhbeRsRHlw_uzBQ1_hja_3Ss +mu=wz1_B_aQh_kj3MSd +Qhj=_c4n;R +sfjj:ROlNEhRq7b.RsRHlw_uzBQ1_hja_3Sl +mu=wz1_B_aQh_kj3MS4 +Qqj=1d_jj +_OS=Q4hn_4cs; +R:fjjNRlOqERhR7.blsHRzwu__B1Q_haj +3MSwm=uBz_1h_Qa3_jk +MjS=Qjw_uzBQ1_hSa +Qw4=uBz_1h_Qa3_jk;Md +fsRjR:jlENOR.m)RHbsluRwz1_B_aQh_bj3 +=Smh +_dS=Qjw_uzBQ1_hja_34kM +4SQ=zwu__B1Q_hajM3kjs; +R:fjjNRlOQERhbeRsRHlhc_(_SH +m_=h(Hc_ +jSQ=(h_cs; +R:fjjNRlOQERhbeRsRHl7B1qih_Qa__j4s_3 +=Sm7B1qih_Qa__j4k_3MSd +Qhj=_;6. +fsRjR:jlENOR7qh.sRbH7lR1iqB_aQh_4j__ +3lS7m=1iqB_aQh_4j__M3k4Q +Sj_=h(Hc_ +4SQ=6h_.s; +R:fjjNRlOqERhR7.blsHRq71BQi_hja__34_Mm +S=q71BQi_hja__34_k +MjS=Qj7B1qih_Qa9r4 +4SQ=q71BQi_hja__34_k;Md +fsRjR:jlENOR.m)RHbsl1R7q_BiQ_haj__43Sb +m_=hcQ +Sj1=7q_BiQ_haj__434kM +4SQ=q71BQi_hja__34_k;Mj +fsRjR:jlENOReQhRHbsl_Rh(H6_ +=Smh6_(_SH +Qhj=_;(6 diff --git a/Logic/BUS68030.srr b/Logic/BUS68030.srr index 1fc62ae..1adcd7f 100644 --- a/Logic/BUS68030.srr +++ b/Logic/BUS68030.srr @@ -6,7 +6,7 @@ #Implementation: logic $ Start of Compile -#Thu May 22 14:56:04 2014 +#Sat May 24 11:44:03 2014 Synopsys VHDL Compiler, version comp201209rcp1, Build 283R, built Mar 19 2013 @N|Running in 64-bit mode @@ -20,16 +20,15 @@ File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - @N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral @W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":112:7:112:15|Signal clk_030_d is undriven Post processing for work.bus68030.behavioral -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":118:32:118:34|Pruning register cpu_est_d(3 downto 0) -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":117:32:117:34|Pruning register CLK_000_D5 -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":116:32:116:34|Pruning register CLK_000_D4 -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":115:32:115:34|Pruning register CLK_000_D3 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":119:32:119:34|Pruning register cpu_est_d(3 downto 0) +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":118:32:118:34|Pruning register CLK_000_D6 @A: CL282 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:52:109:55|Feedback mux created for signal AMIGA_BUS_ENABLE -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. -@W: CL117 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":183:2:183:3|Latch generated from process for signal CLK_REF(1 downto 0); possible missing assignment in an if or case statement. +@W: CL111 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":185:2:185:3|All reachable assignments to CLK_REF(0) assign '0'; register removed by optimization +@W: CL117 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":185:2:185:3|Latch generated from process for signal CLK_REF(1 downto 0); possible missing assignment in an if or case statement. @W: CL190 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:52:109:55|Optimizing register bit DSACK_INT(0) to a constant 1 @W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:52:109:55|Pruning register bit 0 of DSACK_INT(1 downto 0) -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":118:32:118:34|Trying to extract state machine for register cpu_est -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":183:2:183:3|Trying to extract state machine for register SM_AMIGA +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":119:32:119:34|Trying to extract state machine for register cpu_est +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":185:2:185:3|Trying to extract state machine for register SM_AMIGA Extracted state machine for register SM_AMIGA State machine has 8 reachable states with original encodings of: 000 @@ -40,10 +39,10 @@ State machine has 8 reachable states with original encodings of: 101 110 111 -@W: CL249 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":183:2:183:3|Initial value is not supported on state machine SM_AMIGA +@W: CL249 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":185:2:185:3|Initial value is not supported on state machine SM_AMIGA @END Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Thu May 22 14:56:04 2014 +# Sat May 24 11:44:03 2014 ###########################################################] Map & Optimize Report @@ -62,23 +61,22 @@ original code -> new code 101 -> 00100000 110 -> 01000000 111 -> 10000000 -@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":152:4:152:7|Found ROM, 'clk\.cpu_est_11[3:0]', 16 words by 4 bits +@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":154:4:154:7|Found ROM, 'clk\.cpu_est_11[3:0]', 16 words by 4 bits --------------------------------------- Resource Usage Report Simple gate primitives: -DFFRH 7 uses -DFF 14 uses DFFSH 16 uses +DFFRH 7 uses +DFF 17 uses IBUF 35 uses BUFTH 7 uses OBUF 15 uses BI_DIR 2 uses AND2 159 uses -INV 127 uses -OR2 18 uses -XOR2 5 uses -DLATSH 1 use +INV 132 uses +OR2 19 uses +XOR2 3 uses DLATRH 1 use @@ -89,6 +87,6 @@ Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 95MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Thu May 22 14:56:05 2014 +# Sat May 24 11:44:04 2014 ###########################################################] diff --git a/Logic/BUS68030.srs b/Logic/BUS68030.srs index 7cc84e012e0390516102bcfa6e3a4c379f29eb0f..36d245ebd21fcfdbe545f8609f5b455021c2d338 100644 GIT binary patch delta 6314 zcmV;b7**$zLzG64Gk@P}+b|Hv-}_e_=}QZB@Grb1kIfh>bZuGM!N3q?>1=DYB~6l> zdiamuDNV<=hdr#pAmp>|b6=gm(&@?mfwe{EQ9w1qW>lt=^$1@+zQ2aG?v3ow!V_92 zwE|9oG)~fZX}L)*;Bt_ifOL_4hT7`>kj|waFW^e?d4Ov(T7TKJ9?sV1kSv#Z6bNCd zHg0q;3*o+%4xFz2j#&iXA~5GPmwRDC^PxxOnGYhu0RCWEusKbb0p*jeJ7p&g{R$an1@engfxdF zS>^dE&VU-2zx=z~yZfu#o6TxAMP8ff@?ldf;w+vb>WA>7!O0!|=$0Z=BI0mrG-;OK|311Pn@DodZe+N(l{pAAg74holcQu{eKj>mf4W6)fBP8YezBJC~a{& zD1o(9D7Kxf0;igG+CI)sPS+2gSF`o1Ebpvt2m>F;Sq{#g7sYv5N@uQ-TvnDrZ^ayz zWhGUSmnGjmwW6EjGtO2?R%FF8D~kAkfTX4@2}U!`_gFk ze8}@8O^5tT!#S2acy@<5zz{B0)-D=ti7KpcU~1;FR6*g01tyHoT&)U730Nmu8*9}Y zSwOOJHtDff(twhQEr??vUi-#RU_WVpJnJ0=tT4whGRY=HEBPO4%vw244RVHjF*S}C z40AW^0$($=plLUr!@dh4?Ac`$s{>L>HYY9G#xmYS?j>EI^56Hj$IEXBM<74%hw6Iw zxA5^eQb@PH(Q#?KVVe8C1iJmEL)fw?w6V)=q7usad06*`b%l_B00030{|v#ii3D#6 ze@fE6j(-KhxnQId%ZQc%bCaA05bGAFiNn0d3!47{1K8AZJSj@%wkUXMZOM=vmId$ZA| zZG2wAXV!6d_zm0bTzCvZVB3)M$dn-Df0l(EEYoWNPQo8#Go@&^XeSf@Bj%L?S^^`T04D{k6}dzxpvtw`_^L8T_;00f4FST zM)T(HM0Btm*V5k!%W@s{onY1|&c74tJK;(_Kc9zR%@tqy(Ny*GHS||2ZbmTm!&B=U zPr4`1XpL5%;d5t>!&=OpgS!qOe55r!Okbl9GLz#ge~9?>g9It>y|?69mgR4)*&4qO zI;s4p79YzGTx?}=?Mc|nXD$qxe~!0vV;AMW1J|PQlDGF+a_0Blg!h;IgwK*Ycu!_; zynBD<_#m0_{@vejr}rXes3mT^v-Dd3Vdm*tQHvR`T zUfr{c`_aZzYgwmjq0QRqwJbSG+k5VM|7_IUlK#@`KC3?Z-ZFXqhj%xIm##&+WC0!K zN}LQ!_xg$P6ZVjP`*h+@e|?~Py-(Oy(03v(t)JR$y8n1IK7NtV7*8IYaP#xIA`Zw- zj9ZLG0!-+&KXKHGOm6yG{f;(E{T=I|B?yMb&35`bkMEVr_DLr_#z_}tAD`^OQ!ga% z7jtH@`lq~S&)#0OfYt(nN3@i(KnB#Um2-tcH*!Q3L?B^3dd&|q~pU?a}Tk?&uOvkp= z*oXwyTx{WCLGt;=Tc`5xng3jtbu?xKJ!|HQSOfxX{t?E#4?k#KKlyoi;&&}JhUo|I zM^BA+TJk&A;%eT@f1hXU^{$Zp+`*|c2i$zmk6_yR_iof(=6EM)pDp1AaVn!I!+qc^ z_Z199O!ij7{&-HZv0}6-g*~QiM}EX#rs0>skAC!CqTrRA4_hAj;e#{wA;K0fK97Rw zm$2vmh+bcUXv-hWko%GUFm}KIXhHa`d*Y{7;^qFr-3hUCe=PxSu7};^owW5W#ewd- z!o7FsBH+Eh?UKV#%T!qOCE|uC`N6Dxwm#h#?=pCQ=gI8wmN*6OpmRV>W;g>7`S`#1 z>FmwAe6w9b_zP{OPvrQe{DH`D z>kW$cxlKy)f9S4jTX2M}Z~MnBZ0(~@Yn8ZGdWRYZ<3(gHP~865RM&>Db+UsEoQ|+u zxq!jq1Wzb~{u4hXeYz%{?DC)AjaijjoZ3%G8*MuwA)(Nj3z*U z!I&5bSdhKc;Dfd^_51y2cNUF|;0Qf?GUmrHc#Yu2e{XABZ1?5OG08S*gT&m0#b5#5 zyH@LN39V(f1+BRAcxZ*;}5;ePw@k; zbLdLYeoG2>n2j@uUhD@L`)wxiKak8|BZ=}sx6h;;8FYd7a>NX}0KAX}zCo#EZSf(# zmuzH6e_+%U9~z9hzzb=pC)fhprVrD8>2vB3+tNrtZw-2sw^buhZ!`zGpgCXyit=30W6jVi#`WO)pV6mw62iLmue|w!_H+9A#mTS3l;kaOrqa*d-;&;D@ zt5P4o?pg<6!-W}*{RkFgFnxuaBhxk@3VP$C&4bDD^(Bma58C^?XWkn9YO8ml`4LA9 z?eSxTBeD{P&Cw59bL6csh{DHfnaURDFXmrc_!{LLZo^wi>weEo$^ZKLvW?34)_|45 ze_h8ohKP}W+HedMC(_uBI+t^#`z5?RCmwNn!Ya_R*$Mm_sTT4=iF+0F;jFk6V&$2* zKlY)1Gv0N9Sq5mnh}KASaXn|YgyTMdzMe;S-&eMu{i?B(`!|m`EzN7R1mpi!Fo7WK zd)?&uz%AAvLYL;sti!Mi{p8?1GmX#Ef5oWCoyW+f)-+#wkGRQbFOz=Pvz|HarRt03 zNYB58t<#Bj6YyGvzjVaTQTiCG{UJZQ{m~1jvEtowfO=T>tjr-8@8hmOiANN1(%Nxd zhrrpA6F6S_O4TPz`8`HxwjbGi`VxKdgYZY#+p;kR3?yUp3AA5o3=93(hv}H^e+wOB zyEzgLlD}Gm4Q7PE^ztQ|20uc-w=TZ9_Qj~*>nR_9kcN=dz4nQREG`RI{#OhiSJTA5 zj2Q*`f0s!VTg;+4gfOVCjWeP8#@Ms*T{f<=|8k64#5tB?DX5^x1*1XoSiv9m7dKy` z?N=ZhLGO8Pp?}^d_h?zn-2V0Qe{~x{*kxS#c;hXh@yh(Bj&DSd;Q(};!8gl%jJjuK zZeehCqkm_O{X26E+v@gdp6?SH%)qMZ$~@OUi*VqY7Z;pZRAL$(7obk=V#VK(*RZu( zXOrAm#BaS*`l#1EJnVkU^R(^|xwh7b!xr(PXmEZ^ae{C_E^|E0@djlre{=cg<2h=4 zxci&dIwJ2dGAl?iopSCCe@%tvq;hRb>~G{fYx|~k z$XyzkLSU!)&GWAl=U!Lo$P*;3mdC$gK&)cs@_XdCr5xPa!MH&>YuBOp8RanJr@cG~ zX;B=wpPk4i4#OV;|WdEvLD0b97tcj}xg@V?GfE3SY%UhRWrf1{rOo!_<;PL^}rrFw&-{5sAT zoRn`~&qd^TOMI}IL+iPge5~w3lE+yWId+!k*z}GanZ|Q+zMEj|UdQ)JHLQv*e?IK^>xXDcvdeWodU%}@#!RJ}kMcuW zUk#S71EnU&kH?fxX7dKF?%aqYoicvZazf(u83)eghk`@xicyS?6~zj-C?86Em?Q63 zc^Ar!Qf&p9m-h2Td@P2!zH6K)*K$hsMi`}S&MMnnffFK^S@QILnL`#x5b+=3S}JDD ze|+XeOhmqO_I$xdig~hOHICfn*dOQnFNh8k2bzm$t>mGwkaz>drNJ}^a~yV3+}$0l z0-G}|p5rr(CF=P)4~F^G`V+-d*$ISmRAx#hc&r;rJ#WMm6YAok>tV z1QB?Ea}?wsLOwG1G9jCen+4=WSb7jb|-B5cXO;Cwn zO48!5N)t1crUjLk?Xk2SN`FD;0VtnDz76^Nj`CIX@i-Xx24D54|G?)VEGCt_Bg@-` z)pm0kBbSyE^@}FLBa>8eWg0zYLyI7sq`5te*onWb*A~qcV_uUIDP7ihp=!s~gEEhxJcRI3LJ{2}6Yw3zz# zm)gE#86$6!Y2OS6D9!2g<2dxW5%z*rxV0k_H>TuUZraOr&c@n?qRb~WZ#BGDZ-v}D zvcnhf&0HUAuqo#w79SYn-gH8xf4)q&!8`^54_|$M@M@U7=p&;0(f3U|%@-VPbYJEx z#&LwZpYVSmKQXmX#*9xA??099@j?1tX7?<6uQV|Ip4HqdjV$#qSz6l2@6%F8(Vp(5 zAwOl~XZP9rOw;rJWUB3~bT5m0rteGNs|ts@XR3W_HR=0Lbe)z{aCzB!f7CO2FN^kB zf1hO5UK;-%0qF<8WRdCsq&lGS#rFAR1d6j0XIUWp2JHcK(C#h#zvc!PeB!;G=6Oa* zJI@KHF)?!|F&rsQdtm%kpSM9Do1VA1e{1k}>^jD#^07o)Lpx@5F}=!}P#(~f{Np^F z{_cHkZ0{7Y|E>CL#fO&9e<+mvXrM^pQW z6pP)8a_w7O)V^u_?m4enOIqgdP5; z;{c=t{$f!+XK`_j_V8ohOV4xM@ly+Uo}*Lm5X%*hXsTIe{ann$!Fk-OVN$$^p4f3Z z?(PVaN(}+^%efWbe>$a@(ikYte5=kNYx*zyyIWYGY$(obNa>G|aoO$+QPs}?^|Sw& z=2MgYyUwYqYm-%cXD97TaytlbX;hCym%GD6Zjk&fTf2b2~Y|b*}mC@9W&o?K*cgCzI#wSb-aLf6snbr>n`|SQUSipAU-T zqK>9Kj7%{{p!~FGlYZ{M=yr_2rggRK5Dj$j3n=I3Ktq<=>{;Z4> zq+j;YtkbQ$fBkRrBo&-}@&O|czIj@vztd%YE^~ODA2IEkSlKD;zfKRc81=u&k93;O z>uCHVKTvnAvG$fNWZyK+qf$R6yd*o%az*(W4A#2Tg~~Y$R`~qu^BekG%F)-v=0zM| ziiwDSWO{MIf$E;=I-y9?z01zSD7~bb-L|iMFJWX|f4zauf_R(RjC%}bFx%v{03Flo zvm1z2XfQ}56;=tVzo}fZlC!r#7%1|~SI@9dg%Q(3Xj4qA=9ZpC`$Of`%f9e7&r8qF zqWxXe*6W_vJiFzKn)ft43)uL+RL^g0)5I}L`oOMpHSChVUGU9ozB~FFRqAQcu0Cgl z>#2KIe;p&M_g>f4%J#B_m#^3UuylTho6aS6^m|3k&ETr;dQp?3Ghkc4vBqVUd5~4` zvGRVBUS9a1^N(KMm$T&8e5cHd)j3nD?b}0jjwGuY5mc3 zRwu`Z#ILl;v6Fma*bDe%JXwukUOAhs&zgG5o~pSy&CfU7TOLsL%eAmZpW@Z}6IrUq zRq7JuGi~MTD_NIq!O?ygW@&6kzIbaFap;K0mDNubJ`w!T78vko?$crxP(uSGG^A*1_;??@}6SUPh z?TvRc2D#?Mq;rMuOV0)nW|6H@j{O4He=>gEq;GW?c!P^x)%VhI+eLlfa$~_zm@$jp zd3MIIHdaVEUVY4>&%-s>a7FRAOE+SP+P_;!V`uutoPG@FWq)4MYju9)+D1mxd4)Sn zcBwsKOw@$Wd~4l)uX9p2+FbwL$TfG#|2~S9&0m^v_k|tu-l+AfvoK`vy^WWgxuJLSC#^dYxM0KrsZlr-z)X5;1dEYC(y*dw= z%l(G^)sEW~!_s&o?>Fbt1i?M=l$dJ3_4;j9^_x%U)-^}1*b8dR4ZFR4{0EJB+(~+W)BYRgk)BhmJf90h1|)EaW7^JiJkfZ@q8O`kPxEOy6KrJ|SZ7O3 g^K3qYQM7H!e;EGA_zwU80RR630A1mPubfc;06D}H$N&HU delta 5937 zcmV-17tZLEMv_C2Gk;xA+b|S{@A(x+|#`rEa$}Md0(F#`}k=0z|wHyID=+{)hKl@HY0rb^x+zoYS5zR2A;XG zLP?+)$kQxO=Z5O+3@*Ls8RWC#9yUe|`*bSYcm`LJP9t3D(SL}xb8xaeg={`AlSqh5 zmA0dOT?h}Iuwd23ZHeLFIu68IMa9k-Q`8S!I^v>Tmj2fHj=SM#Qvx@=> z0e_IeYJ@NpMc0$hNV;${5J{lcY{p3p8PJ$M(A5KJ>tY&3X|pNw^>w_v!-dP?URt=w ztena+lX5D*EZkCcf=8dP5vJI9U5DhXCq{V@z||}i(trxY0~2m6LTwaC0zQb&r`ilo zE65Hm7CR3{J1{!)iUbDYWoX9*{3lH}dw-&US1fT(OtS^iYyO88i%!o=i<}|fT#a*s zaqXv5zZSqoy0YUh|*t`}qFx_8UP-`t-6} zawBssA4UrgTIJ6@6^~9ho3`cdbp`bJfKE}7J^ugz0RR6C!7&QJAPfM&-Dfy;RI{H1 zV+nuA(!L)53WRfEq>W{Z79Zv&V-w=Dip@|G>~2n^7ULelv?mOPVR8ehpBd{>+znyRo$=&#A4Wm^0<*S1 z8?D>Mr$_k2EN_F~u+7GUhcE(`Mx4i{1R;M@9nov=#Af6Oo#?%2uoH+R+=?&JuJ$4}lT z%Vszl&$d|v;RE%(<1qtksPwXSY`BArjW$CqgT_wZlrrpiCs!UD7T?-TdaG;*JCA>@ z*l2$JI}z{fo@eXtgl&60^_^h$C@H@a>O0{{($9sA#*Kd^U%UVKz*#0;F7Q^mlK;ck zK5Ierw|n4+R_0e@oYNTRD?P?n{x#;)I|)+F|JUhje1~1gH@MHZ|13wcoYNJ_w^q5{ zHtKyh9jm#oUqAa>`qlChhO6x*8=HURy+bzRZ`nORy8SF$@=kvSv+Vs1B^~=N&-gOy z!>rRW{u(`gf=|}QOFUe|4S044(F5tXPyYqcp7DSE1syHJLY+L%TCq^%_AzDrF-W;- zJ39}UTE8iOOoN^2*h7y&I(_6$VD2RIhNX>JE9}O?_Cm|j-z4d<>N9b6!$*IZrX~-Z z;jSF#%A#?uHcZ=S#<)xKxaPAZ%`**;)@nIh1JBee^ogaK+m(faQ30}By)JqCYJHoY zo!dY;mKBW!7m984So;1ld;W*J>(qy+&-n5=^VK&?=+ip8{y%Fy7UoIYl4NT*SK3Ci zrvp#>5Ir$|z%PLAjefpP*cN|nlfDxyO!DzlJ2&J1z}hGIPyCRP4E0@I*94seF+sA# z6MF3L{3+A(rmx>2|JC0K#^^hSk~jLhEg7tujlR-3w?)aJFMYmMulk0}b;hp~r87&) zHS-zY%4aV7lCye$4Exi4jrvUE7_)kw*F!yO^IXbF?UVlOE#!UKykCFKvu&ZPGYdTN z719NL+vl^VA8=frU;p68Woa)c+qTJK5JbKTNc{zDThIJ&|4{w@c;?61lCOCS^2d?44jn#aFz()c*YXa$(_*Cek^fkB5JsxGM>Mv*xeyhG zIeWAGU3T0OZ%ClKgbF87r`9)BJ<_uX=S1;!{e z{$!)9EUA3p{>{hr6f<2zP zcQ`lp!i>j342vuq-5`oXt<)#7jK zew}T%E&jv#3-+Tl$Z@5x)~`0C*#e%R52 zg}!ZiXF~Tw81d*KbmI0Hn6_thj09cXOK1@{37UWOgXuVN5c8L5^f?UD@7-wH<70Wp z1u|wQh#fwCi9ZKn^gZgPy)hCwVgq$d1Oq_dTQ!Vif@mlsXtt5%MlfiQWh+^-L6%Lj zXyK^;2F%dwCcG7!uW%N@TRE@~iK9xwe&RsrY3iQv@_q>?SX$Z}MlJlaBHoJ_8usC+ z$P<6^-6L^+>_hz$pMv%B-ha!UMZvoa$mbP%z<{tqU3$!su-}Ggm4zPewom%%-wPZc zEy4KrBTOKS`o5bz@3_tSLvTq~X77eB@~55u%#2|v3)$!#Wvy1EubcBLM)^k8cYXVr z?~s$KzDP%U{&&U4r$2N#>2ylN14C3g4uuZK=lCQ}C{jKTQ8E?VWff{$I z@}rf=-56}yY-jAMoiS}^m?O}7DH*jKpo-xM>M!wM{Q zDj|xC{7>7+#zv-qJdkoqnyYi1lP%6)%s*535-ZMd!5)*N%RIbJ|w#}Cl}VqBeSNJu;PM@Jd!0CJetOZb}RI_WW%^bWY@+ewXBnTO6NMGwXgZ3 zQ2s>(IT30N$@gc^Cu1lvK#$dp;r*Rwv)x<9DCex@4<*i?b8$~tj7kGxFXw-`nA;IH z?Z6)9dZLWs&MvWM#D*ouCEiCI7r7XO&K}z=efG@NZ~qxoj+ph|FSsvZqRxRtLX?9g zNx@I6xNn!S-M3FUg3Et=GiJ?kxv7_u|44X<@e0>JnMPpu~7Yw>kyCAzS*%4@ZCIHpWD$W1_5LqWph#Oq5kjltapk znqr|)H7hai>G@mYTB8}2en>Tpk^ijin#Lh}_yH^In(RR5c(jgBkhNMq|9f%B`C|P& za)??T1POzUeXYD6MDA?o{M8D$fy4p3jhs zqOQev$m>Wyof{H%G;xI{o?7(LaaiW@zK-d69pWhi z-q-o4tk)XtlUk##cox~Ju3y$_!y62wo*819L3D(tf*y-@1~>3xxf$~+GRhZR-RAuFd9EjCSZT`8ggCM*7hUOm!(8&m)-^* zCi@0k-jsU-=kvb7d5^!oP6=1EoquKg^)8;O+={S)=A_0S8|{JWY}f5p+c|i$OX-oD*Ed2$sh%{6=BWbQd{H$FHToR{Jzm zKQ)5u{7>gqGAnsgy=GkIdAb&&+l{`&C58&@mGXbQc%$a0#uJ%ZkA9qU9K^wsoX+I2 zn)8&E{5x+`$Smgo$ui1F@bA@pI8Nv@DRD)d2K!5LS&}0{&iQZgn3Fn* z-s?lWENdv#p~jtbme-*Y5sNDq2_mY!*@4_Z)`4H3iqH`g(ys-VU-$?>{>Q~n#fZOGsjjii;H@H_# z*E%O@tTA!cD>=uF`VY-fW4xc&IQ6eMjgEiA$^$7MOEw~$>e^(tee(uq zz1W8@@%@aG==Eyw^WH6X~YY=yxC6dx>1T!;6(&RqQdf~)KOlM?S~kM%m|p#1U@ho7KL%mQ=w=6x0#L(~oV zWITBsfpvB6`au~3FY4G=>Mf1>*V}*A@#vavXZuE_+!|)9jVX_@gm_(XwngzXg`;0z z3AgU$+m%|gIOXe29E0qiYJSW=;TZaCL+Q^4IBlnK7R{U`3Vo>Vo)mS#rSCqU`Dw#5 z%?*dUOTNjYBJY(d?rA6t`~GFE^=#goo?kq> z!SBkwCsx^N)3eJn3uioC*AK~0Y_F$$9(uijxmX1G9tnog`?vCpm3-yGmlt)St9vkL zlNb2&)>i#09uq=0n(*;NJi>pia~Idf_FMDN#1&o=NX;*&zT|e#&!vfzab@4TZvIwE zS|{Oig$w7g(P8SWM4fvy*~laM+qpkn?!VZlI=**L_ipS~t^@6JzyI;udq;nq@3HH+ z3URf6q{oT&_($c#n=`zfU!3b1hmvsG%N>83X1(5bmHYaQ zyjSX)<82-&%C!&`54^^8n$}9;UG2sR}ub6Qt8 zhplz!TPHA^R@Z5o^SUpz*ZxgjNIr&tME#6%;TOFVzv$KXh?8sfeZfJ{hnk*U#Ip08 z;8rXm_ zliE4jYx7<5-v)k%<1o+tvE1Xv#X$1(-#m^&9!E{1OEzs1sZa;RKpi8a6K46zG04w{ z747&Uj3&CaVbQtj{EQKO9tMLk?>-u;f1K+Do$aSHBAD9ts6CxQpHRg&;4qXtWF}L1h~t1S(CI%%=Xwa@^`wWeZJcQ~kbpKCFQ$R> zxv_6S+pEIL`(`k}S(;8ijH7@X7{ec<)QQcPppKVi{T_cht;@QEUDYM@|LbrKtIlgh zq0x<;$CU8Xtev|u#@*=zrgtTVnfoy0(Q6P4UJbJwf8fz{9|WeO{Su+rd_~;BuZ@rL z<45@Tk>zH?jE^7bUe@keaW8A{wTa>P*g^iizAxSvM<2`nl$kPvmG|mdt-X3?$d83S z#eMNUH|u}$UYWV9>8nk@)?PiMd;I+<3-_RV1|N%iEnlA9Q-8T@894l6y!5`Nk9seS z|Birc0${Q@@lhQkoPbY8p!R%e|7C$LAGQZT8{0Pi)p715Homv>I`t^K(1f}$!mXzom$RspZiGR<;!_&sh#2DrgiE^ z{cd%3!{8RFcXGCa_7~{P=rt}_k2`if?o|Bt1=24kzJC1PE&H;T{G3nJ`KU!)bB7ed z8J2lZBVRS_6Hdf#)|m<$fVF@1|NqeI;>USDYJ8jNS{>!2jd?c3yTOV|NjF3H1 new code 101 -> 00100000 110 -> 01000000 111 -> 10000000 -@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":152:4:152:7|Found ROM, 'clk\.cpu_est_11[3:0]', 16 words by 4 bits +@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":154:4:154:7|Found ROM, 'clk\.cpu_est_11[3:0]', 16 words by 4 bits --------------------------------------- Resource Usage Report Simple gate primitives: -DFFRH 7 uses -DFF 14 uses DFFSH 16 uses +DFFRH 7 uses +DFF 17 uses IBUF 35 uses BUFTH 7 uses OBUF 15 uses BI_DIR 2 uses AND2 159 uses -INV 127 uses -OR2 18 uses -XOR2 5 uses -DLATSH 1 use +INV 132 uses +OR2 19 uses +XOR2 3 uses DLATRH 1 use @@ -89,6 +87,6 @@ Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 95MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Thu May 22 14:56:05 2014 +# Sat May 24 11:44:04 2014 ###########################################################] diff --git a/Logic/dm/BUS68030_compiler.xdm b/Logic/dm/BUS68030_compiler.xdm index 446166e..6cb1414 100644 --- a/Logic/dm/BUS68030_compiler.xdm +++ b/Logic/dm/BUS68030_compiler.xdm @@ -26,10 +26,10 @@ S7RCVMI="F3s Anz1Ujjd3ELCNFPHs"NDR"D=PDE8"S> SRSqS SRSqSSqS"/ - - +/>SqS"/ +S +S /S<7>CV ]sC diff --git a/Logic/run_options.txt b/Logic/run_options.txt index 371813f..58f511e 100644 --- a/Logic/run_options.txt +++ b/Logic/run_options.txt @@ -1,7 +1,7 @@ #-- Synopsys, Inc. #-- Version G-2012.09LC-SP1 #-- Project file C:\users\matze\documents\github\68030tk\logic\run_options.txt -#-- Written on Thu May 22 14:56:04 2014 +#-- Written on Sat May 24 11:44:03 2014 #project files diff --git a/Logic/synlog/bus68030_fpga_mapper.srr b/Logic/synlog/bus68030_fpga_mapper.srr index 99f269a..d49a658 100644 --- a/Logic/synlog/bus68030_fpga_mapper.srr +++ b/Logic/synlog/bus68030_fpga_mapper.srr @@ -12,23 +12,22 @@ original code -> new code 101 -> 00100000 110 -> 01000000 111 -> 10000000 -@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":152:4:152:7|Found ROM, 'clk\.cpu_est_11[3:0]', 16 words by 4 bits +@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":154:4:154:7|Found ROM, 'clk\.cpu_est_11[3:0]', 16 words by 4 bits --------------------------------------- Resource Usage Report Simple gate primitives: -DFFRH 7 uses -DFF 14 uses DFFSH 16 uses +DFFRH 7 uses +DFF 17 uses IBUF 35 uses BUFTH 7 uses OBUF 15 uses BI_DIR 2 uses AND2 159 uses -INV 127 uses -OR2 18 uses -XOR2 5 uses -DLATSH 1 use +INV 132 uses +OR2 19 uses +XOR2 3 uses DLATRH 1 use @@ -39,6 +38,6 @@ Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 95MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Thu May 22 14:56:05 2014 +# Sat May 24 11:44:04 2014 ###########################################################] diff --git a/Logic/synlog/report/BUS68030_compiler_errors.txt b/Logic/synlog/report/BUS68030_compiler_errors.txt index 42a0fbf..7b271c5 100644 --- a/Logic/synlog/report/BUS68030_compiler_errors.txt +++ b/Logic/synlog/report/BUS68030_compiler_errors.txt @@ -1,3 +1,3 @@ -@E: CD204 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":151:49:151:49|Expecting sequential statement +@E: CG119 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":272:31:272:40|Expecting closing ) @E|Parse errors encountered - exiting diff --git a/Logic/synlog/report/BUS68030_compiler_notes.txt b/Logic/synlog/report/BUS68030_compiler_notes.txt index aa76227..947b038 100644 --- a/Logic/synlog/report/BUS68030_compiler_notes.txt +++ b/Logic/synlog/report/BUS68030_compiler_notes.txt @@ -2,6 +2,6 @@ @N: CD720 :"C:\Program Files (x86)\ispLever\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns @N:"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Top entity is set to BUS68030. @N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":118:32:118:34|Trying to extract state machine for register cpu_est -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":183:2:183:3|Trying to extract state machine for register SM_AMIGA +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":119:32:119:34|Trying to extract state machine for register cpu_est +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":185:2:185:3|Trying to extract state machine for register SM_AMIGA diff --git a/Logic/synlog/report/BUS68030_compiler_runstatus.xml b/Logic/synlog/report/BUS68030_compiler_runstatus.xml index 838e05e..07e6671 100644 --- a/Logic/synlog/report/BUS68030_compiler_runstatus.xml +++ b/Logic/synlog/report/BUS68030_compiler_runstatus.xml @@ -18,7 +18,7 @@ The file contains the job information from compiler to be displayed as part of t C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_notes.txt - 9 + 8 C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_warnings.txt @@ -35,7 +35,7 @@ The file contains the job information from compiler to be displayed as part of t - - 1400763364 + 1400924643 \ No newline at end of file diff --git a/Logic/synlog/report/BUS68030_compiler_warnings.txt b/Logic/synlog/report/BUS68030_compiler_warnings.txt index a2e1070..561fb4f 100644 --- a/Logic/synlog/report/BUS68030_compiler_warnings.txt +++ b/Logic/synlog/report/BUS68030_compiler_warnings.txt @@ -1,10 +1,9 @@ @W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":112:7:112:15|Signal clk_030_d is undriven -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":118:32:118:34|Pruning register cpu_est_d(3 downto 0) -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":117:32:117:34|Pruning register CLK_000_D5 -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":116:32:116:34|Pruning register CLK_000_D4 -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":115:32:115:34|Pruning register CLK_000_D3 -@W: CL117 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":183:2:183:3|Latch generated from process for signal CLK_REF(1 downto 0); possible missing assignment in an if or case statement. +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":119:32:119:34|Pruning register cpu_est_d(3 downto 0) +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":118:32:118:34|Pruning register CLK_000_D6 +@W: CL111 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":185:2:185:3|All reachable assignments to CLK_REF(0) assign '0'; register removed by optimization +@W: CL117 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":185:2:185:3|Latch generated from process for signal CLK_REF(1 downto 0); possible missing assignment in an if or case statement. @W: CL190 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:52:109:55|Optimizing register bit DSACK_INT(0) to a constant 1 @W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:52:109:55|Pruning register bit 0 of DSACK_INT(1 downto 0) -@W: CL249 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":183:2:183:3|Initial value is not supported on state machine SM_AMIGA +@W: CL249 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":185:2:185:3|Initial value is not supported on state machine SM_AMIGA diff --git a/Logic/synlog/report/BUS68030_fpga_mapper_notes.txt b/Logic/synlog/report/BUS68030_fpga_mapper_notes.txt index d5f05b4..78363a8 100644 --- a/Logic/synlog/report/BUS68030_fpga_mapper_notes.txt +++ b/Logic/synlog/report/BUS68030_fpga_mapper_notes.txt @@ -1,3 +1,3 @@ @N: MF248 |Running in 64-bit mode. -@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":152:4:152:7|Found ROM, 'clk\.cpu_est_11[3:0]', 16 words by 4 bits +@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":154:4:154:7|Found ROM, 'clk\.cpu_est_11[3:0]', 16 words by 4 bits @N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis. diff --git a/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml b/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml index df171d3..bbb5cf9 100644 --- a/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml +++ b/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml @@ -39,7 +39,7 @@ The file contains the job information from mapper to be displayed as part of the 95MB -1400763365 +1400924644 diff --git a/Logic/syntmp/run_option.xml b/Logic/syntmp/run_option.xml index 9ab0a9c..ee999c5 100644 --- a/Logic/syntmp/run_option.xml +++ b/Logic/syntmp/run_option.xml @@ -3,7 +3,7 @@ Synopsys, Inc. Version G-2012.09LC-SP1 Project file C:\users\matze\documents\github\68030tk\logic\syntmp\run_option.xml - Written on Thu May 22 14:56:04 2014 + Written on Sat May 24 11:44:03 2014 --> diff --git a/Logic/synwork/BUS68030_compiler.fdep b/Logic/synwork/BUS68030_compiler.fdep index b8e42ee..c474942 100644 --- a/Logic/synwork/BUS68030_compiler.fdep +++ b/Logic/synwork/BUS68030_compiler.fdep @@ -10,7 +10,7 @@ #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328 -#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1400763359 +#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1400924608 0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl # Dependency Lists (Uses list) diff --git a/Logic/synwork/BUS68030_compiler.fdeporig b/Logic/synwork/BUS68030_compiler.fdeporig index e97ab28..5e3e626 100644 --- a/Logic/synwork/BUS68030_compiler.fdeporig +++ b/Logic/synwork/BUS68030_compiler.fdeporig @@ -10,7 +10,7 @@ #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328 -#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1400763359 +#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1400924608 0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl # Dependency Lists (Uses list) diff --git a/Logic/synwork/BUS68030_compiler.srs b/Logic/synwork/BUS68030_compiler.srs index 7cc84e012e0390516102bcfa6e3a4c379f29eb0f..36d245ebd21fcfdbe545f8609f5b455021c2d338 100644 GIT binary patch delta 6314 zcmV;b7**$zLzG64Gk@P}+b|Hv-}_e_=}QZB@Grb1kIfh>bZuGM!N3q?>1=DYB~6l> zdiamuDNV<=hdr#pAmp>|b6=gm(&@?mfwe{EQ9w1qW>lt=^$1@+zQ2aG?v3ow!V_92 zwE|9oG)~fZX}L)*;Bt_ifOL_4hT7`>kj|waFW^e?d4Ov(T7TKJ9?sV1kSv#Z6bNCd zHg0q;3*o+%4xFz2j#&iXA~5GPmwRDC^PxxOnGYhu0RCWEusKbb0p*jeJ7p&g{R$an1@engfxdF zS>^dE&VU-2zx=z~yZfu#o6TxAMP8ff@?ldf;w+vb>WA>7!O0!|=$0Z=BI0mrG-;OK|311Pn@DodZe+N(l{pAAg74holcQu{eKj>mf4W6)fBP8YezBJC~a{& zD1o(9D7Kxf0;igG+CI)sPS+2gSF`o1Ebpvt2m>F;Sq{#g7sYv5N@uQ-TvnDrZ^ayz zWhGUSmnGjmwW6EjGtO2?R%FF8D~kAkfTX4@2}U!`_gFk ze8}@8O^5tT!#S2acy@<5zz{B0)-D=ti7KpcU~1;FR6*g01tyHoT&)U730Nmu8*9}Y zSwOOJHtDff(twhQEr??vUi-#RU_WVpJnJ0=tT4whGRY=HEBPO4%vw244RVHjF*S}C z40AW^0$($=plLUr!@dh4?Ac`$s{>L>HYY9G#xmYS?j>EI^56Hj$IEXBM<74%hw6Iw zxA5^eQb@PH(Q#?KVVe8C1iJmEL)fw?w6V)=q7usad06*`b%l_B00030{|v#ii3D#6 ze@fE6j(-KhxnQId%ZQc%bCaA05bGAFiNn0d3!47{1K8AZJSj@%wkUXMZOM=vmId$ZA| zZG2wAXV!6d_zm0bTzCvZVB3)M$dn-Df0l(EEYoWNPQo8#Go@&^XeSf@Bj%L?S^^`T04D{k6}dzxpvtw`_^L8T_;00f4FST zM)T(HM0Btm*V5k!%W@s{onY1|&c74tJK;(_Kc9zR%@tqy(Ny*GHS||2ZbmTm!&B=U zPr4`1XpL5%;d5t>!&=OpgS!qOe55r!Okbl9GLz#ge~9?>g9It>y|?69mgR4)*&4qO zI;s4p79YzGTx?}=?Mc|nXD$qxe~!0vV;AMW1J|PQlDGF+a_0Blg!h;IgwK*Ycu!_; zynBD<_#m0_{@vejr}rXes3mT^v-Dd3Vdm*tQHvR`T zUfr{c`_aZzYgwmjq0QRqwJbSG+k5VM|7_IUlK#@`KC3?Z-ZFXqhj%xIm##&+WC0!K zN}LQ!_xg$P6ZVjP`*h+@e|?~Py-(Oy(03v(t)JR$y8n1IK7NtV7*8IYaP#xIA`Zw- zj9ZLG0!-+&KXKHGOm6yG{f;(E{T=I|B?yMb&35`bkMEVr_DLr_#z_}tAD`^OQ!ga% z7jtH@`lq~S&)#0OfYt(nN3@i(KnB#Um2-tcH*!Q3L?B^3dd&|q~pU?a}Tk?&uOvkp= z*oXwyTx{WCLGt;=Tc`5xng3jtbu?xKJ!|HQSOfxX{t?E#4?k#KKlyoi;&&}JhUo|I zM^BA+TJk&A;%eT@f1hXU^{$Zp+`*|c2i$zmk6_yR_iof(=6EM)pDp1AaVn!I!+qc^ z_Z199O!ij7{&-HZv0}6-g*~QiM}EX#rs0>skAC!CqTrRA4_hAj;e#{wA;K0fK97Rw zm$2vmh+bcUXv-hWko%GUFm}KIXhHa`d*Y{7;^qFr-3hUCe=PxSu7};^owW5W#ewd- z!o7FsBH+Eh?UKV#%T!qOCE|uC`N6Dxwm#h#?=pCQ=gI8wmN*6OpmRV>W;g>7`S`#1 z>FmwAe6w9b_zP{OPvrQe{DH`D z>kW$cxlKy)f9S4jTX2M}Z~MnBZ0(~@Yn8ZGdWRYZ<3(gHP~865RM&>Db+UsEoQ|+u zxq!jq1Wzb~{u4hXeYz%{?DC)AjaijjoZ3%G8*MuwA)(Nj3z*U z!I&5bSdhKc;Dfd^_51y2cNUF|;0Qf?GUmrHc#Yu2e{XABZ1?5OG08S*gT&m0#b5#5 zyH@LN39V(f1+BRAcxZ*;}5;ePw@k; zbLdLYeoG2>n2j@uUhD@L`)wxiKak8|BZ=}sx6h;;8FYd7a>NX}0KAX}zCo#EZSf(# zmuzH6e_+%U9~z9hzzb=pC)fhprVrD8>2vB3+tNrtZw-2sw^buhZ!`zGpgCXyit=30W6jVi#`WO)pV6mw62iLmue|w!_H+9A#mTS3l;kaOrqa*d-;&;D@ zt5P4o?pg<6!-W}*{RkFgFnxuaBhxk@3VP$C&4bDD^(Bma58C^?XWkn9YO8ml`4LA9 z?eSxTBeD{P&Cw59bL6csh{DHfnaURDFXmrc_!{LLZo^wi>weEo$^ZKLvW?34)_|45 ze_h8ohKP}W+HedMC(_uBI+t^#`z5?RCmwNn!Ya_R*$Mm_sTT4=iF+0F;jFk6V&$2* zKlY)1Gv0N9Sq5mnh}KASaXn|YgyTMdzMe;S-&eMu{i?B(`!|m`EzN7R1mpi!Fo7WK zd)?&uz%AAvLYL;sti!Mi{p8?1GmX#Ef5oWCoyW+f)-+#wkGRQbFOz=Pvz|HarRt03 zNYB58t<#Bj6YyGvzjVaTQTiCG{UJZQ{m~1jvEtowfO=T>tjr-8@8hmOiANN1(%Nxd zhrrpA6F6S_O4TPz`8`HxwjbGi`VxKdgYZY#+p;kR3?yUp3AA5o3=93(hv}H^e+wOB zyEzgLlD}Gm4Q7PE^ztQ|20uc-w=TZ9_Qj~*>nR_9kcN=dz4nQREG`RI{#OhiSJTA5 zj2Q*`f0s!VTg;+4gfOVCjWeP8#@Ms*T{f<=|8k64#5tB?DX5^x1*1XoSiv9m7dKy` z?N=ZhLGO8Pp?}^d_h?zn-2V0Qe{~x{*kxS#c;hXh@yh(Bj&DSd;Q(};!8gl%jJjuK zZeehCqkm_O{X26E+v@gdp6?SH%)qMZ$~@OUi*VqY7Z;pZRAL$(7obk=V#VK(*RZu( zXOrAm#BaS*`l#1EJnVkU^R(^|xwh7b!xr(PXmEZ^ae{C_E^|E0@djlre{=cg<2h=4 zxci&dIwJ2dGAl?iopSCCe@%tvq;hRb>~G{fYx|~k z$XyzkLSU!)&GWAl=U!Lo$P*;3mdC$gK&)cs@_XdCr5xPa!MH&>YuBOp8RanJr@cG~ zX;B=wpPk4i4#OV;|WdEvLD0b97tcj}xg@V?GfE3SY%UhRWrf1{rOo!_<;PL^}rrFw&-{5sAT zoRn`~&qd^TOMI}IL+iPge5~w3lE+yWId+!k*z}GanZ|Q+zMEj|UdQ)JHLQv*e?IK^>xXDcvdeWodU%}@#!RJ}kMcuW zUk#S71EnU&kH?fxX7dKF?%aqYoicvZazf(u83)eghk`@xicyS?6~zj-C?86Em?Q63 zc^Ar!Qf&p9m-h2Td@P2!zH6K)*K$hsMi`}S&MMnnffFK^S@QILnL`#x5b+=3S}JDD ze|+XeOhmqO_I$xdig~hOHICfn*dOQnFNh8k2bzm$t>mGwkaz>drNJ}^a~yV3+}$0l z0-G}|p5rr(CF=P)4~F^G`V+-d*$ISmRAx#hc&r;rJ#WMm6YAok>tV z1QB?Ea}?wsLOwG1G9jCen+4=WSb7jb|-B5cXO;Cwn zO48!5N)t1crUjLk?Xk2SN`FD;0VtnDz76^Nj`CIX@i-Xx24D54|G?)VEGCt_Bg@-` z)pm0kBbSyE^@}FLBa>8eWg0zYLyI7sq`5te*onWb*A~qcV_uUIDP7ihp=!s~gEEhxJcRI3LJ{2}6Yw3zz# zm)gE#86$6!Y2OS6D9!2g<2dxW5%z*rxV0k_H>TuUZraOr&c@n?qRb~WZ#BGDZ-v}D zvcnhf&0HUAuqo#w79SYn-gH8xf4)q&!8`^54_|$M@M@U7=p&;0(f3U|%@-VPbYJEx z#&LwZpYVSmKQXmX#*9xA??099@j?1tX7?<6uQV|Ip4HqdjV$#qSz6l2@6%F8(Vp(5 zAwOl~XZP9rOw;rJWUB3~bT5m0rteGNs|ts@XR3W_HR=0Lbe)z{aCzB!f7CO2FN^kB zf1hO5UK;-%0qF<8WRdCsq&lGS#rFAR1d6j0XIUWp2JHcK(C#h#zvc!PeB!;G=6Oa* zJI@KHF)?!|F&rsQdtm%kpSM9Do1VA1e{1k}>^jD#^07o)Lpx@5F}=!}P#(~f{Np^F z{_cHkZ0{7Y|E>CL#fO&9e<+mvXrM^pQW z6pP)8a_w7O)V^u_?m4enOIqgdP5; z;{c=t{$f!+XK`_j_V8ohOV4xM@ly+Uo}*Lm5X%*hXsTIe{ann$!Fk-OVN$$^p4f3Z z?(PVaN(}+^%efWbe>$a@(ikYte5=kNYx*zyyIWYGY$(obNa>G|aoO$+QPs}?^|Sw& z=2MgYyUwYqYm-%cXD97TaytlbX;hCym%GD6Zjk&fTf2b2~Y|b*}mC@9W&o?K*cgCzI#wSb-aLf6snbr>n`|SQUSipAU-T zqK>9Kj7%{{p!~FGlYZ{M=yr_2rggRK5Dj$j3n=I3Ktq<=>{;Z4> zq+j;YtkbQ$fBkRrBo&-}@&O|czIj@vztd%YE^~ODA2IEkSlKD;zfKRc81=u&k93;O z>uCHVKTvnAvG$fNWZyK+qf$R6yd*o%az*(W4A#2Tg~~Y$R`~qu^BekG%F)-v=0zM| ziiwDSWO{MIf$E;=I-y9?z01zSD7~bb-L|iMFJWX|f4zauf_R(RjC%}bFx%v{03Flo zvm1z2XfQ}56;=tVzo}fZlC!r#7%1|~SI@9dg%Q(3Xj4qA=9ZpC`$Of`%f9e7&r8qF zqWxXe*6W_vJiFzKn)ft43)uL+RL^g0)5I}L`oOMpHSChVUGU9ozB~FFRqAQcu0Cgl z>#2KIe;p&M_g>f4%J#B_m#^3UuylTho6aS6^m|3k&ETr;dQp?3Ghkc4vBqVUd5~4` zvGRVBUS9a1^N(KMm$T&8e5cHd)j3nD?b}0jjwGuY5mc3 zRwu`Z#ILl;v6Fma*bDe%JXwukUOAhs&zgG5o~pSy&CfU7TOLsL%eAmZpW@Z}6IrUq zRq7JuGi~MTD_NIq!O?ygW@&6kzIbaFap;K0mDNubJ`w!T78vko?$crxP(uSGG^A*1_;??@}6SUPh z?TvRc2D#?Mq;rMuOV0)nW|6H@j{O4He=>gEq;GW?c!P^x)%VhI+eLlfa$~_zm@$jp zd3MIIHdaVEUVY4>&%-s>a7FRAOE+SP+P_;!V`uutoPG@FWq)4MYju9)+D1mxd4)Sn zcBwsKOw@$Wd~4l)uX9p2+FbwL$TfG#|2~S9&0m^v_k|tu-l+AfvoK`vy^WWgxuJLSC#^dYxM0KrsZlr-z)X5;1dEYC(y*dw= z%l(G^)sEW~!_s&o?>Fbt1i?M=l$dJ3_4;j9^_x%U)-^}1*b8dR4ZFR4{0EJB+(~+W)BYRgk)BhmJf90h1|)EaW7^JiJkfZ@q8O`kPxEOy6KrJ|SZ7O3 g^K3qYQM7H!e;EGA_zwU80RR630A1mPubfc;06D}H$N&HU delta 5937 zcmV-17tZLEMv_C2Gk;xA+b|S{@A(x+|#`rEa$}Md0(F#`}k=0z|wHyID=+{)hKl@HY0rb^x+zoYS5zR2A;XG zLP?+)$kQxO=Z5O+3@*Ls8RWC#9yUe|`*bSYcm`LJP9t3D(SL}xb8xaeg={`AlSqh5 zmA0dOT?h}Iuwd23ZHeLFIu68IMa9k-Q`8S!I^v>Tmj2fHj=SM#Qvx@=> z0e_IeYJ@NpMc0$hNV;${5J{lcY{p3p8PJ$M(A5KJ>tY&3X|pNw^>w_v!-dP?URt=w ztena+lX5D*EZkCcf=8dP5vJI9U5DhXCq{V@z||}i(trxY0~2m6LTwaC0zQb&r`ilo zE65Hm7CR3{J1{!)iUbDYWoX9*{3lH}dw-&US1fT(OtS^iYyO88i%!o=i<}|fT#a*s zaqXv5zZSqoy0YUh|*t`}qFx_8UP-`t-6} zawBssA4UrgTIJ6@6^~9ho3`cdbp`bJfKE}7J^ugz0RR6C!7&QJAPfM&-Dfy;RI{H1 zV+nuA(!L)53WRfEq>W{Z79Zv&V-w=Dip@|G>~2n^7ULelv?mOPVR8ehpBd{>+znyRo$=&#A4Wm^0<*S1 z8?D>Mr$_k2EN_F~u+7GUhcE(`Mx4i{1R;M@9nov=#Af6Oo#?%2uoH+R+=?&JuJ$4}lT z%Vszl&$d|v;RE%(<1qtksPwXSY`BArjW$CqgT_wZlrrpiCs!UD7T?-TdaG;*JCA>@ z*l2$JI}z{fo@eXtgl&60^_^h$C@H@a>O0{{($9sA#*Kd^U%UVKz*#0;F7Q^mlK;ck zK5Ierw|n4+R_0e@oYNTRD?P?n{x#;)I|)+F|JUhje1~1gH@MHZ|13wcoYNJ_w^q5{ zHtKyh9jm#oUqAa>`qlChhO6x*8=HURy+bzRZ`nORy8SF$@=kvSv+Vs1B^~=N&-gOy z!>rRW{u(`gf=|}QOFUe|4S044(F5tXPyYqcp7DSE1syHJLY+L%TCq^%_AzDrF-W;- zJ39}UTE8iOOoN^2*h7y&I(_6$VD2RIhNX>JE9}O?_Cm|j-z4d<>N9b6!$*IZrX~-Z z;jSF#%A#?uHcZ=S#<)xKxaPAZ%`**;)@nIh1JBee^ogaK+m(faQ30}By)JqCYJHoY zo!dY;mKBW!7m984So;1ld;W*J>(qy+&-n5=^VK&?=+ip8{y%Fy7UoIYl4NT*SK3Ci zrvp#>5Ir$|z%PLAjefpP*cN|nlfDxyO!DzlJ2&J1z}hGIPyCRP4E0@I*94seF+sA# z6MF3L{3+A(rmx>2|JC0K#^^hSk~jLhEg7tujlR-3w?)aJFMYmMulk0}b;hp~r87&) zHS-zY%4aV7lCye$4Exi4jrvUE7_)kw*F!yO^IXbF?UVlOE#!UKykCFKvu&ZPGYdTN z719NL+vl^VA8=frU;p68Woa)c+qTJK5JbKTNc{zDThIJ&|4{w@c;?61lCOCS^2d?44jn#aFz()c*YXa$(_*Cek^fkB5JsxGM>Mv*xeyhG zIeWAGU3T0OZ%ClKgbF87r`9)BJ<_uX=S1;!{e z{$!)9EUA3p{>{hr6f<2zP zcQ`lp!i>j342vuq-5`oXt<)#7jK zew}T%E&jv#3-+Tl$Z@5x)~`0C*#e%R52 zg}!ZiXF~Tw81d*KbmI0Hn6_thj09cXOK1@{37UWOgXuVN5c8L5^f?UD@7-wH<70Wp z1u|wQh#fwCi9ZKn^gZgPy)hCwVgq$d1Oq_dTQ!Vif@mlsXtt5%MlfiQWh+^-L6%Lj zXyK^;2F%dwCcG7!uW%N@TRE@~iK9xwe&RsrY3iQv@_q>?SX$Z}MlJlaBHoJ_8usC+ z$P<6^-6L^+>_hz$pMv%B-ha!UMZvoa$mbP%z<{tqU3$!su-}Ggm4zPewom%%-wPZc zEy4KrBTOKS`o5bz@3_tSLvTq~X77eB@~55u%#2|v3)$!#Wvy1EubcBLM)^k8cYXVr z?~s$KzDP%U{&&U4r$2N#>2ylN14C3g4uuZK=lCQ}C{jKTQ8E?VWff{$I z@}rf=-56}yY-jAMoiS}^m?O}7DH*jKpo-xM>M!wM{Q zDj|xC{7>7+#zv-qJdkoqnyYi1lP%6)%s*535-ZMd!5)*N%RIbJ|w#}Cl}VqBeSNJu;PM@Jd!0CJetOZb}RI_WW%^bWY@+ewXBnTO6NMGwXgZ3 zQ2s>(IT30N$@gc^Cu1lvK#$dp;r*Rwv)x<9DCex@4<*i?b8$~tj7kGxFXw-`nA;IH z?Z6)9dZLWs&MvWM#D*ouCEiCI7r7XO&K}z=efG@NZ~qxoj+ph|FSsvZqRxRtLX?9g zNx@I6xNn!S-M3FUg3Et=GiJ?kxv7_u|44X<@e0>JnMPpu~7Yw>kyCAzS*%4@ZCIHpWD$W1_5LqWph#Oq5kjltapk znqr|)H7hai>G@mYTB8}2en>Tpk^ijin#Lh}_yH^In(RR5c(jgBkhNMq|9f%B`C|P& za)??T1POzUeXYD6MDA?o{M8D$fy4p3jhs zqOQev$m>Wyof{H%G;xI{o?7(LaaiW@zK-d69pWhi z-q-o4tk)XtlUk##cox~Ju3y$_!y62wo*819L3D(tf*y-@1~>3xxf$~+GRhZR-RAuFd9EjCSZT`8ggCM*7hUOm!(8&m)-^* zCi@0k-jsU-=kvb7d5^!oP6=1EoquKg^)8;O+={S)=A_0S8|{JWY}f5p+c|i$OX-oD*Ed2$sh%{6=BWbQd{H$FHToR{Jzm zKQ)5u{7>gqGAnsgy=GkIdAb&&+l{`&C58&@mGXbQc%$a0#uJ%ZkA9qU9K^wsoX+I2 zn)8&E{5x+`$Smgo$ui1F@bA@pI8Nv@DRD)d2K!5LS&}0{&iQZgn3Fn* z-s?lWENdv#p~jtbme-*Y5sNDq2_mY!*@4_Z)`4H3iqH`g(ys-VU-$?>{>Q~n#fZOGsjjii;H@H_# z*E%O@tTA!cD>=uF`VY-fW4xc&IQ6eMjgEiA$^$7MOEw~$>e^(tee(uq zz1W8@@%@aG==Eyw^WH6X~YY=yxC6dx>1T!;6(&RqQdf~)KOlM?S~kM%m|p#1U@ho7KL%mQ=w=6x0#L(~oV zWITBsfpvB6`au~3FY4G=>Mf1>*V}*A@#vavXZuE_+!|)9jVX_@gm_(XwngzXg`;0z z3AgU$+m%|gIOXe29E0qiYJSW=;TZaCL+Q^4IBlnK7R{U`3Vo>Vo)mS#rSCqU`Dw#5 z%?*dUOTNjYBJY(d?rA6t`~GFE^=#goo?kq> z!SBkwCsx^N)3eJn3uioC*AK~0Y_F$$9(uijxmX1G9tnog`?vCpm3-yGmlt)St9vkL zlNb2&)>i#09uq=0n(*;NJi>pia~Idf_FMDN#1&o=NX;*&zT|e#&!vfzab@4TZvIwE zS|{Oig$w7g(P8SWM4fvy*~laM+qpkn?!VZlI=**L_ipS~t^@6JzyI;udq;nq@3HH+ z3URf6q{oT&_($c#n=`zfU!3b1hmvsG%N>83X1(5bmHYaQ zyjSX)<82-&%C!&`54^^8n$}9;UG2sR}ub6Qt8 zhplz!TPHA^R@Z5o^SUpz*ZxgjNIr&tME#6%;TOFVzv$KXh?8sfeZfJ{hnk*U#Ip08 z;8rXm_ zliE4jYx7<5-v)k%<1o+tvE1Xv#X$1(-#m^&9!E{1OEzs1sZa;RKpi8a6K46zG04w{ z747&Uj3&CaVbQtj{EQKO9tMLk?>-u;f1K+Do$aSHBAD9ts6CxQpHRg&;4qXtWF}L1h~t1S(CI%%=Xwa@^`wWeZJcQ~kbpKCFQ$R> zxv_6S+pEIL`(`k}S(;8ijH7@X7{ec<)QQcPppKVi{T_cht;@QEUDYM@|LbrKtIlgh zq0x<;$CU8Xtev|u#@*=zrgtTVnfoy0(Q6P4UJbJwf8fz{9|WeO{Su+rd_~;BuZ@rL z<45@Tk>zH?jE^7bUe@keaW8A{wTa>P*g^iizAxSvM<2`nl$kPvmG|mdt-X3?$d83S z#eMNUH|u}$UYWV9>8nk@)?PiMd;I+<3-_RV1|N%iEnlA9Q-8T@894l6y!5`Nk9seS z|Birc0${Q@@lhQkoPbY8p!R%e|7C$LAGQZT8{0Pi)p715Homv>I`t^K(1f}$!mXzom$RspZiGR<;!_&sh#2DrgiE^ z{cd%3!{8RFcXGCa_7~{P=rt}_k2`if?o|Bt1=24kzJC1PE&H;T{G3nJ`KU!)bB7ed z8J2lZBVRS_6Hdf#)|m<$fVF@1|NqeI;>USDYJ8jNS{>!2jd?c3yTOV|NjF3H1