-
+
#Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014
#install: E:\ispLEVER_Classic2_0\synpbase
#OS: Windows 7 6.2
@@ -8,32 +8,32 @@
#Implementation: logic
$ Start of Compile
-#Fri Nov 18 19:32:29 2016
+#Thu Dec 29 16:01:49 2016
Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
-@N: : | Running in 64-bit mode
+@N: : | Running in 64-bit mode
Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited.
-@N:CD720 : std.vhd(123) | Setting time resolution to ns
-@N: : 68030-68000-bus.vhd(13) | Top entity is set to BUS68030.
+@N:CD720 : std.vhd(123) | Setting time resolution to ns
+@N: : 68030-68000-bus.vhd(13) | Top entity is set to BUS68030.
File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd changed - recompiling
VHDL syntax check successful!
File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd changed - recompiling
-@N:CD630 : 68030-68000-bus.vhd(13) | Synthesizing work.bus68030.behavioral
-@N:CD233 : 68030-68000-bus.vhd(70) | Using sequential encoding for type sm_e
-@N:CD233 : 68030-68000-bus.vhd(87) | Using sequential encoding for type sm_68000
-@W:CD638 : 68030-68000-bus.vhd(129) | Signal clk_out_pre is undriven
-@W:CD638 : 68030-68000-bus.vhd(133) | Signal clk_030_h is undriven
+@N:CD630 : 68030-68000-bus.vhd(13) | Synthesizing work.bus68030.behavioral
+@N:CD233 : 68030-68000-bus.vhd(70) | Using sequential encoding for type sm_e
+@N:CD233 : 68030-68000-bus.vhd(87) | Using sequential encoding for type sm_68000
+@W:CD638 : 68030-68000-bus.vhd(129) | Signal clk_out_pre is undriven
+@W:CD638 : 68030-68000-bus.vhd(133) | Signal clk_030_h is undriven
Post processing for work.bus68030.behavioral
-@W:CL169 : 68030-68000-bus.vhd(132) | Pruning register AS_000_D0_3
-@W:CL169 : 68030-68000-bus.vhd(132) | Pruning register DS_030_D0_3
-@W:CL169 : 68030-68000-bus.vhd(132) | Pruning register nEXP_SPACE_D0_3
-@W:CL169 : 68030-68000-bus.vhd(132) | Pruning register BGACK_030_INT_PRE_2
-@W:CL169 : 68030-68000-bus.vhd(131) | Pruning register CLK_OUT_EXP_INT_1
-@W:CL169 : 68030-68000-bus.vhd(127) | Pruning register CLK_OUT_PRE_25_3
-@W:CL169 : 68030-68000-bus.vhd(156) | Pruning register CLK_030_D0_2
-@W:CL271 : 68030-68000-bus.vhd(132) | Pruning bits 12 to 5 of CLK_000_D_3(12 downto 0) -- not in use ...
-@N:CL201 : 68030-68000-bus.vhd(132) | Trying to extract state machine for register SM_AMIGA
+@W:CL169 : 68030-68000-bus.vhd(132) | Pruning register AS_000_D0_3
+@W:CL169 : 68030-68000-bus.vhd(132) | Pruning register DS_030_D0_3
+@W:CL169 : 68030-68000-bus.vhd(132) | Pruning register nEXP_SPACE_D0_3
+@W:CL169 : 68030-68000-bus.vhd(132) | Pruning register BGACK_030_INT_PRE_2
+@W:CL169 : 68030-68000-bus.vhd(131) | Pruning register CLK_OUT_EXP_INT_1
+@W:CL169 : 68030-68000-bus.vhd(127) | Pruning register CLK_OUT_PRE_25_3
+@W:CL169 : 68030-68000-bus.vhd(156) | Pruning register CLK_030_D0_2
+@W:CL271 : 68030-68000-bus.vhd(132) | Pruning bits 12 to 5 of CLK_000_D_3(12 downto 0) -- not in use ...
+@N:CL201 : 68030-68000-bus.vhd(132) | Trying to extract state machine for register SM_AMIGA
Extracted state machine for register SM_AMIGA
State machine has 8 reachable states with original encodings of:
000
@@ -44,24 +44,24 @@ State machine has 8 reachable states with original encodings of:
101
110
111
-@N:CL201 : 68030-68000-bus.vhd(132) | Trying to extract state machine for register cpu_est
-@W:CL246 : 68030-68000-bus.vhd(24) | Input port bits 15 to 2 of a_decode(23 downto 2) are unused
+@N:CL201 : 68030-68000-bus.vhd(132) | Trying to extract state machine for register cpu_est
+@W:CL246 : 68030-68000-bus.vhd(24) | Input port bits 15 to 2 of a_decode(23 downto 2) are unused
@END
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Fri Nov 18 19:32:29 2016
+# Thu Dec 29 16:01:49 2016
###########################################################]
Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
-@N: : | Running in 64-bit mode
+@N: : | Running in 64-bit mode
File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\synwork\BUS68030_comp.srs changed - recompiling
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Fri Nov 18 19:32:31 2016
+# Thu Dec 29 16:01:50 2016
###########################################################]
Map & Optimize Report
@@ -69,8 +69,8 @@ Map & Optimize Report
Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
Product Version I-2014.03LC
-@N:MF248 : | Running in 64-bit mode.
-@N: : 68030-68000-bus.vhd(132) | Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
+@N:MF248 : | Running in 64-bit mode.
+@N: : 68030-68000-bus.vhd(132) | Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
original code -> new code
000 -> 00000000
@@ -96,14 +96,14 @@ OR2 23 uses
XOR2 8 uses
-@N:FC100 : | Timing Report not generated for this device, please use place and route tools for timing analysis.
+@N:FC100 : | Timing Report not generated for this device, please use place and route tools for timing analysis.
I-2014.03LC
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Fri Nov 18 19:32:31 2016
+# Thu Dec 29 16:01:51 2016
###########################################################]
diff --git a/Logic/syntmp/BUS68030_toc.htm b/Logic/syntmp/BUS68030_toc.htm
index a55eb31..d33688c 100644
--- a/Logic/syntmp/BUS68030_toc.htm
+++ b/Logic/syntmp/BUS68030_toc.htm
@@ -16,7 +16,7 @@
Mapper Report
-Session Log (19:32 18-Nov)
+Session Log (16:01 29-Dec)
diff --git a/Logic/syntmp/run_option.xml b/Logic/syntmp/run_option.xml
index 6336888..a6aaffc 100644
--- a/Logic/syntmp/run_option.xml
+++ b/Logic/syntmp/run_option.xml
@@ -3,7 +3,7 @@
Synopsys, Inc.
Version I-2014.03LC
Project file C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\syntmp\run_option.xml
- Written on Fri Nov 18 19:32:29 2016
+ Written on Thu Dec 29 16:01:49 2016
-->
diff --git a/Logic/syntmp/statusReport.html b/Logic/syntmp/statusReport.html
index a84036a..ac2d20b 100644
--- a/Logic/syntmp/statusReport.html
+++ b/Logic/syntmp/statusReport.html
@@ -38,7 +38,7 @@
- |
0m:00s |
- |
-18.11.2016
19:32:29 |
+29.12.2016
16:01:49 |
@@ -49,12 +49,12 @@
| 0m:00s |
0m:00s |
105MB |
-18.11.2016
19:32:31 |
+29.12.2016
16:01:51 |
| Multi-srs Generator |
- Complete | | | | 0m:01s | | | 18.11.2016
19:32:31 |
+ Complete | | | | 0m:01s | | | 29.12.2016
16:01:50 |
\ No newline at end of file
diff --git a/Logic/synwork/BUS68030_comp.fdep b/Logic/synwork/BUS68030_comp.fdep
index 74cf7b2..3048e9d 100644
--- a/Logic/synwork/BUS68030_comp.fdep
+++ b/Logic/synwork/BUS68030_comp.fdep
@@ -9,7 +9,7 @@
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\umr_capim.vhd":1401220368
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\arith.vhd":1401220122
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\unsigned.vhd":1401220122
-#CUR:"C:\\users\\matze\\amiga\\hardwarehacks\\68030-tk\\github\\logic\\68030-68000-bus.vhd":1479493940
+#CUR:"C:\\users\\matze\\amiga\\hardwarehacks\\68030-tk\\github\\logic\\68030-68000-bus.vhd":1483023695
0 "C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd" vhdl
# Dependency Lists (Uses list)
diff --git a/Logic/synwork/BUS68030_comp.fdeporig b/Logic/synwork/BUS68030_comp.fdeporig
index b732480..3ac167f 100644
--- a/Logic/synwork/BUS68030_comp.fdeporig
+++ b/Logic/synwork/BUS68030_comp.fdeporig
@@ -9,7 +9,7 @@
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\umr_capim.vhd":1401220368
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\arith.vhd":1401220122
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\unsigned.vhd":1401220122
-#CUR:"C:\\users\\matze\\amiga\\hardwarehacks\\68030-tk\\github\\logic\\68030-68000-bus.vhd":1479493940
+#CUR:"C:\\users\\matze\\amiga\\hardwarehacks\\68030-tk\\github\\logic\\68030-68000-bus.vhd":1483023695
0 "C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd" vhdl
# Dependency Lists (Uses list)
diff --git a/Logic/synwork/BUS68030_comp.srs b/Logic/synwork/BUS68030_comp.srs
index c56c224..1789330 100644
Binary files a/Logic/synwork/BUS68030_comp.srs and b/Logic/synwork/BUS68030_comp.srs differ
diff --git a/Logic/synwork/BUS68030_mult.srs b/Logic/synwork/BUS68030_mult.srs
index 63c82f8..bc001f9 100644
Binary files a/Logic/synwork/BUS68030_mult.srs and b/Logic/synwork/BUS68030_mult.srs differ
diff --git a/Logic/synwork/BUS68030_mult_srs/skeleton.srs b/Logic/synwork/BUS68030_mult_srs/skeleton.srs
index ccb7ca0..cad3475 100644
Binary files a/Logic/synwork/BUS68030_mult_srs/skeleton.srs and b/Logic/synwork/BUS68030_mult_srs/skeleton.srs differ
diff --git a/Logic/synwork/BUS68030_s.srs b/Logic/synwork/BUS68030_s.srs
index c56c224..1789330 100644
Binary files a/Logic/synwork/BUS68030_s.srs and b/Logic/synwork/BUS68030_s.srs differ