From f65f1a4bec01a476dd8f3648477db64d4e05a399 Mon Sep 17 00:00:00 2001 From: MHeinrichs Date: Thu, 29 Dec 2016 21:50:37 +0100 Subject: [PATCH] resetfix + pdfs --- Layout and PCB/68030-TK-V09f.brd.pdf | Bin 0 -> 587399 bytes Layout and PCB/68030-TK-V09f.sch.pdf | Bin 0 -> 37333 bytes Layout and PCB/68030-TK-V09g.b#1 | 8330 +++++++++ Layout and PCB/68030-TK-V09g.brd | 8127 +++++++++ Layout and PCB/68030-TK-V09g.s#1 | 14769 +++++++++++++++ Layout and PCB/68030-TK-V09g.sch | 14884 ++++++++++++++++ Logic/68030-68000-bus_working.vhd | 561 + Logic/68030_TK.tcl | 1281 ++ Logic/68030_tk-Resetfix-soft_timing.zip | Bin 0 -> 7280 bytes Logic/68030_tk.bl2 | 2 +- Logic/68030_tk.bl3 | 2 +- Logic/68030_tk.crf | 2 +- Logic/68030_tk.eq3 | 2 +- Logic/68030_tk.ipr | 2 +- Logic/68030_tk.jed | 2 +- Logic/68030_tk.lco | 4 +- Logic/68030_tk.out | 900 + Logic/68030_tk.plc | 2 +- Logic/68030_tk.prd | 4 +- Logic/68030_tk.rpt | 2 +- Logic/68030_tk.tt2 | 2 +- Logic/68030_tk.tt3 | 2 +- Logic/68030_tk.tt4 | 2 +- Logic/68030_tk.tte | 2 +- Logic/68030_tk.vcl | 4 +- Logic/68030_tk.vco | 4 +- Logic/68030_tk.xrf | 2 +- Logic/68030_tk.zip | Bin 0 -> 7375 bytes Logic/BUS68030.bl0 | 2 +- Logic/BUS68030.bl1 | 2 +- Logic/BUS68030.edi | 2 +- Logic/BUS68030.prj | 2 +- Logic/BUS68030.srm | 6 +- Logic/BUS68030.srr | 8 +- Logic/BUS68030.srs | Bin 13149 -> 13150 bytes Logic/Programming.xcf | 8 +- Logic/bus68030.exf | 2 +- Logic/bus68030.srf | 48 +- Logic/dm/BUS68030_comp.xdm | 4 +- Logic/run_options.txt | 2 +- Logic/synlog/BUS68030_multi_srs_gen.srr | 2 +- Logic/synlog/bus68030_fpga_mapper.srr | 2 +- .../report/BUS68030_compiler_runstatus.xml | 2 +- .../report/BUS68030_fpga_mapper_runstatus.xml | 2 +- Logic/syntmp/BUS68030_srr.htm | 56 +- Logic/syntmp/BUS68030_toc.htm | 2 +- Logic/syntmp/run_option.xml | 2 +- Logic/syntmp/statusReport.html | 6 +- Logic/synwork/BUS68030_comp.fdep | 2 +- Logic/synwork/BUS68030_comp.fdeporig | 2 +- Logic/synwork/BUS68030_comp.srs | Bin 12720 -> 12719 bytes Logic/synwork/BUS68030_mult.srs | Bin 13149 -> 13150 bytes Logic/synwork/BUS68030_mult_srs/skeleton.srs | Bin 1282 -> 1283 bytes Logic/synwork/BUS68030_s.srs | Bin 12720 -> 12719 bytes 54 files changed, 48977 insertions(+), 81 deletions(-) create mode 100644 Layout and PCB/68030-TK-V09f.brd.pdf create mode 100644 Layout and PCB/68030-TK-V09f.sch.pdf create mode 100644 Layout and PCB/68030-TK-V09g.b#1 create mode 100644 Layout and PCB/68030-TK-V09g.brd create mode 100644 Layout and PCB/68030-TK-V09g.s#1 create mode 100644 Layout and PCB/68030-TK-V09g.sch create mode 100644 Logic/68030-68000-bus_working.vhd create mode 100644 Logic/68030_tk-Resetfix-soft_timing.zip create mode 100644 Logic/68030_tk.zip diff --git a/Layout and PCB/68030-TK-V09f.brd.pdf b/Layout and PCB/68030-TK-V09f.brd.pdf new file mode 100644 index 0000000000000000000000000000000000000000..e237b6ed3c43f0e699ad545c4e9af24c13792441 GIT binary patch literal 587399 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+<b>Motorola MC68000 Processors</b><p> +<author>Created by librarian@cadsoft.de</author> + + +<b>micro Ball Grid Array</b> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +<b>Dual In Line</b> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +<b>PLASTIC LEADED CHIP CARRIER</b><p> +square + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<b>Resistors, Capacitors, Inductors</b><p> +Based on the previous libraries: +<ul> +<li>r.lbr +<li>cap.lbr +<li>cap-fe.lbr +<li>captant.lbr +<li>polcap.lbr +<li>ipc-smd.lbr +</ul> +All SMD packages are defined according to the IPC specifications and CECC<p> +<author>Created by librarian@cadsoft.de</author><p> +<p> +for Electrolyt Capacitors see also :<p> +www.bccomponents.com <p> +www.panasonic.com<p> +www.kemet.com<p> +http://www.secc.co.jp/pdf/os_e/2004/e_os_all.pdf <b>(SANYO)</b> +<p> +for trimmer refence see : <u>www.electrospec-inc.com/cross_references/trimpotcrossref.asp</u><p> + +<table border=0 cellspacing=0 cellpadding=0 width="100%" cellpaddding=0> +<tr valign="top"> + +<! <td width="10">&nbsp;</td> +<td width="90%"> + +<b><font color="#0000FF" size="4">TRIM-POT CROSS REFERENCE</font></b> +<P> +<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=2> + <TR> + <TD COLSPAN=8> + <FONT SIZE=3 FACE=ARIAL><B>RECTANGULAR MULTI-TURN</B></FONT> + </TD> + </TR> + <TR> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">BOURNS</FONT> + </B> + </TD> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">BI&nbsp;TECH</FONT> + </B> + </TD> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">DALE-VISHAY</FONT> + </B> + </TD> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">PHILIPS/MEPCO</FONT> + </B> + </TD> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">MURATA</FONT> + </B> + </TD> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">PANASONIC</FONT> + </B> + </TD> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">SPECTROL</FONT> + </B> + </TD> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">MILSPEC</FONT> + </B> + </TD><TD>&nbsp;</TD> + </TR> + <TR> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3 > + 3005P<BR> + 3006P<BR> + 3006W<BR> + 3006Y<BR> + 3009P<BR> + 3009W<BR> + 3009Y<BR> + 3057J<BR> + 3057L<BR> + 3057P<BR> + 3057Y<BR> + 3059J<BR> + 3059L<BR> + 3059P<BR> + 3059Y<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + 89P<BR> + 89W<BR> + 89X<BR> + 89PH<BR> + 76P<BR> + 89XH<BR> + 78SLT<BR> + 78L&nbsp;ALT<BR> + 56P&nbsp;ALT<BR> + 78P&nbsp;ALT<BR> + T8S<BR> + 78L<BR> + 56P<BR> + 78P<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + T18/784<BR> + 783<BR> + 781<BR> + -<BR> + -<BR> + -<BR> + 2199<BR> + 1697/1897<BR> + 1680/1880<BR> + 2187<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + 8035EKP/CT20/RJ-20P<BR> + -<BR> + RJ-20X<BR> + -<BR> + -<BR> + -<BR> + 1211L<BR> + 8012EKQ&nbsp;ALT<BR> + 8012EKR&nbsp;ALT<BR> + 1211P<BR> + 8012EKJ<BR> + 8012EKL<BR> + 8012EKQ<BR> + 8012EKR<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + 2101P<BR> + 2101W<BR> + 2101Y<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 2102L<BR> + 2102S<BR> + 2102Y<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + EVMCOG<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + 43P<BR> + 43W<BR> + 43Y<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 40L<BR> + 40P<BR> + 40Y<BR> + 70Y-T602<BR> + 70L<BR> + 70P<BR> + 70Y<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + RT/RTR12<BR> + RT/RTR12<BR> + RT/RTR12<BR> + -<BR> + RJ/RJR12<BR> + RJ/RJR12<BR> + RJ/RJR12<BR></FONT> + </TD> + </TR> + <TR> + <TD COLSPAN=8>&nbsp; + </TD> + </TR> + <TR> + <TD COLSPAN=8> + <FONT SIZE=4 FACE=ARIAL><B>SQUARE MULTI-TURN</B></FONT> + </TD> + </TR> + <TR> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>BI&nbsp;TECH</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT> + </TD> + </TR> + <TR> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 3250L<BR> + 3250P<BR> + 3250W<BR> + 3250X<BR> + 3252P<BR> + 3252W<BR> + 3252X<BR> + 3260P<BR> + 3260W<BR> + 3260X<BR> + 3262P<BR> + 3262W<BR> + 3262X<BR> + 3266P<BR> + 3266W<BR> + 3266X<BR> + 3290H<BR> + 3290P<BR> + 3290W<BR> + 3292P<BR> + 3292W<BR> + 3292X<BR> + 3296P<BR> + 3296W<BR> + 3296X<BR> + 3296Y<BR> + 3296Z<BR> + 3299P<BR> + 3299W<BR> + 3299X<BR> + 3299Y<BR> + 3299Z<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + 66P&nbsp;ALT<BR> + 66W&nbsp;ALT<BR> + 66X&nbsp;ALT<BR> + 66P&nbsp;ALT<BR> + 66W&nbsp;ALT<BR> + 66X&nbsp;ALT<BR> + -<BR> + 64W&nbsp;ALT<BR> + -<BR> + 64P&nbsp;ALT<BR> + 64W&nbsp;ALT<BR> + 64X&nbsp;ALT<BR> + 64P<BR> + 64W<BR> + 64X<BR> + 66X&nbsp;ALT<BR> + 66P&nbsp;ALT<BR> + 66W&nbsp;ALT<BR> + 66P<BR> + 66W<BR> + 66X<BR> + 67P<BR> + 67W<BR> + 67X<BR> + 67Y<BR> + 67Z<BR> + 68P<BR> + 68W<BR> + 68X<BR> + 67Y&nbsp;ALT<BR> + 67Z&nbsp;ALT<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 5050<BR> + 5091<BR> + 5080<BR> + 5087<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + T63YB<BR> + T63XB<BR> + -<BR> + -<BR> + -<BR> + 5887<BR> + 5891<BR> + 5880<BR> + -<BR> + -<BR> + -<BR> + T93Z<BR> + T93YA<BR> + T93XA<BR> + T93YB<BR> + T93XB<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 8026EKP<BR> + 8026EKW<BR> + 8026EKM<BR> + 8026EKP<BR> + 8026EKB<BR> + 8026EKM<BR> + 1309X<BR> + 1309P<BR> + 1309W<BR> + 8024EKP<BR> + 8024EKW<BR> + 8024EKN<BR> + RJ-9P/CT9P<BR> + RJ-9W<BR> + RJ-9X<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 3103P<BR> + 3103Y<BR> + 3103Z<BR> + 3103P<BR> + 3103Y<BR> + 3103Z<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 3105P/3106P<BR> + 3105W/3106W<BR> + 3105X/3106X<BR> + 3105Y/3106Y<BR> + 3105Z/3105Z<BR> + 3102P<BR> + 3102W<BR> + 3102X<BR> + 3102Y<BR> + 3102Z<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + EVMCBG<BR> + EVMCCG<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 55-1-X<BR> + 55-4-X<BR> + 55-3-X<BR> + 55-2-X<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 50-2-X<BR> + 50-4-X<BR> + 50-3-X<BR> + -<BR> + -<BR> + -<BR> + 64P<BR> + 64W<BR> + 64X<BR> + 64Y<BR> + 64Z<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + RT/RTR22<BR> + RT/RTR22<BR> + RT/RTR22<BR> + RT/RTR22<BR> + RJ/RJR22<BR> + RJ/RJR22<BR> + RJ/RJR22<BR> + RT/RTR26<BR> + RT/RTR26<BR> + RT/RTR26<BR> + RJ/RJR26<BR> + RJ/RJR26<BR> + RJ/RJR26<BR> + RJ/RJR26<BR> + RJ/RJR26<BR> + RJ/RJR26<BR> + RT/RTR24<BR> + RT/RTR24<BR> + RT/RTR24<BR> + RJ/RJR24<BR> + RJ/RJR24<BR> + RJ/RJR24<BR> + RJ/RJR24<BR> + RJ/RJR24<BR> + RJ/RJR24<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + </TR> + <TR> + <TD COLSPAN=8>&nbsp; + </TD> + </TR> + <TR> + <TD COLSPAN=8> + <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT> + </TD> + </TR> + <TR> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>BI&nbsp;TECH</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT> + </TD> + </TR> + <TR> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 3323P<BR> + 3323S<BR> + 3323W<BR> + 3329H<BR> + 3329P<BR> + 3329W<BR> + 3339H<BR> + 3339P<BR> + 3339W<BR> + 3352E<BR> + 3352H<BR> + 3352K<BR> + 3352P<BR> + 3352T<BR> + 3352V<BR> + 3352W<BR> + 3362H<BR> + 3362M<BR> + 3362P<BR> + 3362R<BR> + 3362S<BR> + 3362U<BR> + 3362W<BR> + 3362X<BR> + 3386B<BR> + 3386C<BR> + 3386F<BR> + 3386H<BR> + 3386K<BR> + 3386M<BR> + 3386P<BR> + 3386S<BR> + 3386W<BR> + 3386X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 25P<BR> + 25S<BR> + 25RX<BR> + 82P<BR> + 82M<BR> + 82PA<BR> + -<BR> + -<BR> + -<BR> + 91E<BR> + 91X<BR> + 91T<BR> + 91B<BR> + 91A<BR> + 91V<BR> + 91W<BR> + 25W<BR> + 25V<BR> + 25P<BR> + -<BR> + 25S<BR> + 25U<BR> + 25RX<BR> + 25X<BR> + 72XW<BR> + 72XL<BR> + 72PM<BR> + 72RX<BR> + -<BR> + 72PX<BR> + 72P<BR> + 72RXW<BR> + 72RXL<BR> + 72X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + T7YB<BR> + T7YA<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + TXD<BR> + TYA<BR> + TYP<BR> + -<BR> + TYD<BR> + TX<BR> + -<BR> + 150SX<BR> + 100SX<BR> + 102T<BR> + 101S<BR> + 190T<BR> + 150TX<BR> + 101<BR> + -<BR> + -<BR> + 101SX<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + ET6P<BR> + ET6S<BR> + ET6X<BR> + RJ-6W/8014EMW<BR> + RJ-6P/8014EMP<BR> + RJ-6X/8014EMX<BR> + TM7W<BR> + TM7P<BR> + TM7X<BR> + -<BR> + 8017SMS<BR> + -<BR> + 8017SMB<BR> + 8017SMA<BR> + -<BR> + -<BR> + CT-6W<BR> + CT-6H<BR> + CT-6P<BR> + CT-6R<BR> + -<BR> + CT-6V<BR> + CT-6X<BR> + -<BR> + -<BR> + 8038EKV<BR> + -<BR> + 8038EKX<BR> + -<BR> + -<BR> + 8038EKP<BR> + 8038EKZ<BR> + 8038EKW<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + 3321H<BR> + 3321P<BR> + 3321N<BR> + 1102H<BR> + 1102P<BR> + 1102T<BR> + RVA0911V304A<BR> + -<BR> + RVA0911H413A<BR> + RVG0707V100A<BR> + RVA0607V(H)306A<BR> + RVA1214H213A<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 3104B<BR> + 3104C<BR> + 3104F<BR> + 3104H<BR> + -<BR> + 3104M<BR> + 3104P<BR> + 3104S<BR> + 3104W<BR> + 3104X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + EVMQ0G<BR> + EVMQIG<BR> + EVMQ3G<BR> + EVMS0G<BR> + EVMQ0G<BR> + EVMG0G<BR> + -<BR> + -<BR> + -<BR> + EVMK4GA00B<BR> + EVM30GA00B<BR> + EVMK0GA00B<BR> + EVM38GA00B<BR> + EVMB6<BR> + EVLQ0<BR> + -<BR> + EVMMSG<BR> + EVMMBG<BR> + EVMMAG<BR> + -<BR> + -<BR> + EVMMCS<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + EVMM1<BR> + -<BR> + -<BR> + EVMM0<BR> + -<BR> + -<BR> + EVMM3<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + 62-3-1<BR> + 62-1-2<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 67R<BR> + -<BR> + 67P<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 67X<BR> + 63V<BR> + 63S<BR> + 63M<BR> + -<BR> + -<BR> + 63H<BR> + 63P<BR> + -<BR> + -<BR> + 63X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + RJ/RJR50<BR> + RJ/RJR50<BR> + RJ/RJR50<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + </TR> +</TABLE> +<P>&nbsp;<P> +<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=3> + <TR> + <TD COLSPAN=7> + <FONT color="#0000FF" SIZE=4 FACE=ARIAL><B>SMD TRIM-POT CROSS REFERENCE</B></FONT> + <P> + <FONT SIZE=4 FACE=ARIAL><B>MULTI-TURN</B></FONT> + </TD> + </TR> + <TR> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>BI&nbsp;TECH</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT> + </TD> + </TR> + <TR> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 3224G<BR> + 3224J<BR> + 3224W<BR> + 3269P<BR> + 3269W<BR> + 3269X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 44G<BR> + 44J<BR> + 44W<BR> + 84P<BR> + 84W<BR> + 84X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + ST63Z<BR> + ST63Y<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + ST5P<BR> + ST5W<BR> + ST5X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + </TR> + <TR> + <TD COLSPAN=7>&nbsp; + </TD> + </TR> + <TR> + <TD COLSPAN=7> + <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT> + </TD> + </TR> + <TR> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>BI&nbsp;TECH</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT> + </TD> + </TR> + <TR> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 3314G<BR> + 3314J<BR> + 3364A/B<BR> + 3364C/D<BR> + 3364W/X<BR> + 3313G<BR> + 3313J<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 23B<BR> + 23A<BR> + 21X<BR> + 21W<BR> + -<BR> + 22B<BR> + 22A<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + ST5YL/ST53YL<BR> + ST5YJ/5T53YJ<BR> + ST-23A<BR> + ST-22B<BR> + ST-22<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + ST-4B<BR> + ST-4A<BR> + -<BR> + -<BR> + -<BR> + ST-3B<BR> + ST-3A<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + EVM-6YS<BR> + EVM-1E<BR> + EVM-1G<BR> + EVM-1D<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + G4B<BR> + G4A<BR> + TR04-3S1<BR> + TRG04-2S1<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + DVR-43A<BR> + CVR-42C<BR> + CVR-42A/C<BR> + -<BR> + -<BR></FONT> + </TD> + </TR> +</TABLE> +<P> +<FONT SIZE=4 FACE=ARIAL><B>ALT =&nbsp;ALTERNATE</B></FONT> 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PCB/68030-TK-V09g.brd new file mode 100644 index 0000000..4af43c9 --- /dev/null +++ b/Layout and PCB/68030-TK-V09g.brd @@ -0,0 +1,8127 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +TOP +Bot +a1k.org 68030-TK v0.9d +(c) 2014 Matthias Heinrichs +thx BukoCharly, Georg Braun, Herzi +a1k.org 68030-TK V0.9 +(c)2013 Matthias Heinrichs +Free for non commercial +reproduction + +JTAG + + + +<b>Motorola MC68000 Processors</b><p> +<author>Created by librarian@cadsoft.de</author> + + +<b>micro Ball Grid Array</b> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +<b>Dual In Line</b> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + +<b>PLASTIC LEADED CHIP CARRIER</b><p> +square + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<b>Resistors, Capacitors, Inductors</b><p> +Based on the previous libraries: +<ul> +<li>r.lbr +<li>cap.lbr +<li>cap-fe.lbr +<li>captant.lbr +<li>polcap.lbr +<li>ipc-smd.lbr +</ul> +All SMD packages are defined according to the IPC specifications and CECC<p> +<author>Created by librarian@cadsoft.de</author><p> +<p> +for Electrolyt Capacitors see also :<p> +www.bccomponents.com <p> +www.panasonic.com<p> +www.kemet.com<p> +http://www.secc.co.jp/pdf/os_e/2004/e_os_all.pdf <b>(SANYO)</b> +<p> +for trimmer refence see : <u>www.electrospec-inc.com/cross_references/trimpotcrossref.asp</u><p> + +<table border=0 cellspacing=0 cellpadding=0 width="100%" cellpaddding=0> +<tr valign="top"> + +<! <td width="10">&nbsp;</td> +<td width="90%"> + +<b><font color="#0000FF" size="4">TRIM-POT CROSS REFERENCE</font></b> +<P> +<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=2> + <TR> + <TD COLSPAN=8> + <FONT SIZE=3 FACE=ARIAL><B>RECTANGULAR MULTI-TURN</B></FONT> + </TD> + </TR> + <TR> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">BOURNS</FONT> + </B> + </TD> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">BI&nbsp;TECH</FONT> + </B> + </TD> + <TD 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FACE=ARIAL><B>BI&nbsp;TECH</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT> + </TD> + </TR> + <TR> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 3314G<BR> + 3314J<BR> + 3364A/B<BR> + 3364C/D<BR> + 3364W/X<BR> + 3313G<BR> + 3313J<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 23B<BR> + 23A<BR> + 21X<BR> + 21W<BR> + -<BR> + 22B<BR> + 22A<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + ST5YL/ST53YL<BR> + ST5YJ/5T53YJ<BR> + ST-23A<BR> + ST-22B<BR> + ST-22<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + ST-4B<BR> + ST-4A<BR> + -<BR> + -<BR> + -<BR> + ST-3B<BR> + ST-3A<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + EVM-6YS<BR> + EVM-1E<BR> + EVM-1G<BR> + EVM-1D<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + G4B<BR> + G4A<BR> + TR04-3S1<BR> + TRG04-2S1<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + DVR-43A<BR> + CVR-42C<BR> + CVR-42A/C<BR> + -<BR> + -<BR></FONT> + </TD> + </TR> +</TABLE> +<P> +<FONT SIZE=4 FACE=ARIAL><B>ALT =&nbsp;ALTERNATE</B></FONT> +<P> + +&nbsp; +<P> +</td> +</tr> +</table> + + +<b>Ceramic Chip Capacitor KEMET 0603 reflow solder</b><p> +Metric Code Size 1608 + + + + +>NAME +>VALUE + + + + +<b>Ceramic Chip Capacitor KEMET 0805 reflow solder</b><p> +Metric Code Size 2012 + + + + +>NAME +>VALUE + + + + +<b>RESISTOR</b><p> + + + + + + + + +>NAME +>VALUE + + + + + +<b>RESISTOR</b> + + + + + + + + +>NAME +>VALUE + + + + + +<b>CAPACITOR</b> + + + + + + + + +>NAME +>VALUE + + + + + + + +<b>TTL Devices, 74xx Series with European Symbols</b><p> +Based on the following sources: +<ul> +<li>Texas Instruments <i>TTL Data Book</i>&nbsp;&nbsp;&nbsp;Volume 1, 1996. +<li>TTL Data Book, Volume 2 , 1993 +<li>National Seminconductor Databook 1990, ALS/LS Logic +<li>ttl 74er digital data dictionary, ECA Electronic + Acustic GmbH, ISBN 3-88109-032-0 +<li>http://icmaster.com/ViewCompare.asp +</ul> +<author>Created by librarian@cadsoft.de</author> + + +<b>Wide Small Outline package</b> 300 mil + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>VALUE +>NAME + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<b>Harting & 3M Connectors</b><p> +Low profile connectors, straight<p> +<author>Created by librarian@cadsoft.de</author> + + +<b>HARTING</b> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +10 +>NAME +>VALUE +1 +2 + + + + + + + + + + + + + + +<b>Crystals and Crystal Resonators</b><p> +<author>Created by librarian@cadsoft.de</author> + + +<b>CRYSTAL RESONATOR</b> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE +1 + + + + +<b>VG Connectors (DIN 41612/DIN 41617)</b><p> +The library contains devices which allow to place the contacts individually or +in one or several blocks.<p> +This behavior is indicated by the key words <i>single</i> and <i>block</i> in +the respective device descriptions.<p> +<author>Created by librarian@cadsoft.de</author> + + +<b>CONNECTOR</b><p> +female, 96 pins, type R, rows ABC, grid 2.54 mm + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE +1 +a +b +c +32 +DIN41612-R + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +<b>Resistors in DIL Packages</b><p> +<author>Created by librarian@cadsoft.de</author> + + +<b>Chip Resistor Array 0603x4</b> 4 resistors in 3.20 mm x 1.60 mm size<p> +Source: PANASONIC .. aoc0000ce1.pdf + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + +<b>AMD MACH4/MACH5 Family (Vantis)</b><p> +<author>Created by librarian@cadsoft.de</author> + + +<b>THIN QUAD FLAT PACK</b> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE +TQFP 100 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +>NAME +>VALUE + + + + +<b>Jumpers</b><p> +<author>Created by librarian@cadsoft.de</author> + + +<b>Solder jumper</b> + + + + + + + + + + + + + + +>NAME +>VALUE + + + + + + + + + + + + + + +<b>LeitOn Design-Regeln</b> +<p> +Diese DRU-Datei enthält viele erforderliche Design Einstellungen, damit Ihre Standardleiterplatte bei uns fehlerfrei und ohne Zusatzkosten produziert werden kann. Die Optionen Shapes und Misc sind nicht relevant und der minimale und maximale Wert für Roundness Shapes kann frei gewählt werden. Nach unten abweichende Design-Regeln sind möglich, können jedoch Aufpreise erfordern. Hinweis: Freistellungen und Streichstärken von Bestückungsdruck werden nicht im DRC geprüft! +<br><br> +<b>Übersicht der LeitOn Regeln:</b<<br><br> +<u>allgemein:</u><br> +minimale Leiterbahnbreite/-abstand: <b>0.15 mm</b><br> +(Strichstärke für Kupferschrift sollte mind. 0.2 mm sein um gut lesbar zu bleiben)<br> +kleinster Bohrdurchmesser: <b>0.3 mm</b><br><br> +<u>Kupferrestringe um DK-Bohrungen:</u><br> +Aussenlagen: <b>0.15 mm</b><br> +Innenlagen: <b>0.2 mm</b><br> +<br> +<u>Masselagen-Freimachungen:</u><br> +Innenlagen: <b>0.35 mm</b><br> +<br> +<u>Bestückungsdruck</u><br> +minimale Strichstärke: <b>0.2 mm</b><br><br> +<b><u><font color= "blue">Wichtig:</font></b></u> Verwenden Sie als Strichstärke für Masseflächen keine Strichstärken kleiner 0.1mm. Es entstehen sonst extrem große Datenmengen, weil Eagle die Massefläche stets mit Polygonen der gleichen Strichstärke füllt. + +</p> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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and CECC<p> +<author>Created by librarian@cadsoft.de</author><p> +<p> +for Electrolyt Capacitors see also :<p> +www.bccomponents.com <p> +www.panasonic.com<p> +www.kemet.com<p> +http://www.secc.co.jp/pdf/os_e/2004/e_os_all.pdf <b>(SANYO)</b> +<p> +for trimmer refence see : <u>www.electrospec-inc.com/cross_references/trimpotcrossref.asp</u><p> + +<table border=0 cellspacing=0 cellpadding=0 width="100%" cellpaddding=0> +<tr valign="top"> + +<! <td width="10">&nbsp;</td> +<td width="90%"> + +<b><font color="#0000FF" size="4">TRIM-POT CROSS REFERENCE</font></b> +<P> +<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=2> + <TR> + <TD COLSPAN=8> + <FONT SIZE=3 FACE=ARIAL><B>RECTANGULAR MULTI-TURN</B></FONT> + </TD> + </TR> + <TR> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">BOURNS</FONT> + </B> + </TD> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">BI&nbsp;TECH</FONT> + </B> + </TD> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">DALE-VISHAY</FONT> + </B> + </TD> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">PHILIPS/MEPCO</FONT> + </B> + </TD> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">MURATA</FONT> + </B> + </TD> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">PANASONIC</FONT> + </B> + </TD> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">SPECTROL</FONT> + </B> + </TD> + <TD ALIGN=CENTER> + <B> + <FONT SIZE=3 FACE=ARIAL color="#FF0000">MILSPEC</FONT> + </B> + </TD><TD>&nbsp;</TD> + </TR> + <TR> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3 > + 3005P<BR> + 3006P<BR> + 3006W<BR> + 3006Y<BR> + 3009P<BR> + 3009W<BR> + 3009Y<BR> + 3057J<BR> + 3057L<BR> + 3057P<BR> + 3057Y<BR> + 3059J<BR> + 3059L<BR> + 3059P<BR> + 3059Y<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + 89P<BR> + 89W<BR> + 89X<BR> + 89PH<BR> + 76P<BR> + 89XH<BR> + 78SLT<BR> + 78L&nbsp;ALT<BR> + 56P&nbsp;ALT<BR> + 78P&nbsp;ALT<BR> + T8S<BR> + 78L<BR> + 56P<BR> + 78P<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + T18/784<BR> + 783<BR> + 781<BR> + -<BR> + -<BR> + -<BR> + 2199<BR> + 1697/1897<BR> + 1680/1880<BR> + 2187<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + 8035EKP/CT20/RJ-20P<BR> + -<BR> + RJ-20X<BR> + -<BR> + -<BR> + -<BR> + 1211L<BR> + 8012EKQ&nbsp;ALT<BR> + 8012EKR&nbsp;ALT<BR> + 1211P<BR> + 8012EKJ<BR> + 8012EKL<BR> + 8012EKQ<BR> + 8012EKR<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + 2101P<BR> + 2101W<BR> + 2101Y<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 2102L<BR> + 2102S<BR> + 2102Y<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + EVMCOG<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + 43P<BR> + 43W<BR> + 43Y<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 40L<BR> + 40P<BR> + 40Y<BR> + 70Y-T602<BR> + 70L<BR> + 70P<BR> + 70Y<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + RT/RTR12<BR> + RT/RTR12<BR> + RT/RTR12<BR> + -<BR> + RJ/RJR12<BR> + RJ/RJR12<BR> + RJ/RJR12<BR></FONT> + </TD> + </TR> + <TR> + <TD COLSPAN=8>&nbsp; + </TD> + </TR> + <TR> + <TD COLSPAN=8> + <FONT SIZE=4 FACE=ARIAL><B>SQUARE MULTI-TURN</B></FONT> + </TD> + </TR> + <TR> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>BI&nbsp;TECH</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT> + </TD> + </TR> + <TR> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 3250L<BR> + 3250P<BR> + 3250W<BR> + 3250X<BR> + 3252P<BR> + 3252W<BR> + 3252X<BR> + 3260P<BR> + 3260W<BR> + 3260X<BR> + 3262P<BR> + 3262W<BR> + 3262X<BR> + 3266P<BR> + 3266W<BR> + 3266X<BR> + 3290H<BR> + 3290P<BR> + 3290W<BR> + 3292P<BR> + 3292W<BR> + 3292X<BR> + 3296P<BR> + 3296W<BR> + 3296X<BR> + 3296Y<BR> + 3296Z<BR> + 3299P<BR> + 3299W<BR> + 3299X<BR> + 3299Y<BR> + 3299Z<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + 66P&nbsp;ALT<BR> + 66W&nbsp;ALT<BR> + 66X&nbsp;ALT<BR> + 66P&nbsp;ALT<BR> + 66W&nbsp;ALT<BR> + 66X&nbsp;ALT<BR> + -<BR> + 64W&nbsp;ALT<BR> + -<BR> + 64P&nbsp;ALT<BR> + 64W&nbsp;ALT<BR> + 64X&nbsp;ALT<BR> + 64P<BR> + 64W<BR> + 64X<BR> + 66X&nbsp;ALT<BR> + 66P&nbsp;ALT<BR> + 66W&nbsp;ALT<BR> + 66P<BR> + 66W<BR> + 66X<BR> + 67P<BR> + 67W<BR> + 67X<BR> + 67Y<BR> + 67Z<BR> + 68P<BR> + 68W<BR> + 68X<BR> + 67Y&nbsp;ALT<BR> + 67Z&nbsp;ALT<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 5050<BR> + 5091<BR> + 5080<BR> + 5087<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + T63YB<BR> + T63XB<BR> + -<BR> + -<BR> + -<BR> + 5887<BR> + 5891<BR> + 5880<BR> + -<BR> + -<BR> + -<BR> + T93Z<BR> + T93YA<BR> + T93XA<BR> + T93YB<BR> + T93XB<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 8026EKP<BR> + 8026EKW<BR> + 8026EKM<BR> + 8026EKP<BR> + 8026EKB<BR> + 8026EKM<BR> + 1309X<BR> + 1309P<BR> + 1309W<BR> + 8024EKP<BR> + 8024EKW<BR> + 8024EKN<BR> + RJ-9P/CT9P<BR> + RJ-9W<BR> + RJ-9X<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 3103P<BR> + 3103Y<BR> + 3103Z<BR> + 3103P<BR> + 3103Y<BR> + 3103Z<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 3105P/3106P<BR> + 3105W/3106W<BR> + 3105X/3106X<BR> + 3105Y/3106Y<BR> + 3105Z/3105Z<BR> + 3102P<BR> + 3102W<BR> + 3102X<BR> + 3102Y<BR> + 3102Z<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + EVMCBG<BR> + EVMCCG<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 55-1-X<BR> + 55-4-X<BR> + 55-3-X<BR> + 55-2-X<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 50-2-X<BR> + 50-4-X<BR> + 50-3-X<BR> + -<BR> + -<BR> + -<BR> + 64P<BR> + 64W<BR> + 64X<BR> + 64Y<BR> + 64Z<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + RT/RTR22<BR> + RT/RTR22<BR> + RT/RTR22<BR> + RT/RTR22<BR> + RJ/RJR22<BR> + RJ/RJR22<BR> + RJ/RJR22<BR> + RT/RTR26<BR> + RT/RTR26<BR> + RT/RTR26<BR> + RJ/RJR26<BR> + RJ/RJR26<BR> + RJ/RJR26<BR> + RJ/RJR26<BR> + RJ/RJR26<BR> + RJ/RJR26<BR> + RT/RTR24<BR> + RT/RTR24<BR> + RT/RTR24<BR> + RJ/RJR24<BR> + RJ/RJR24<BR> + RJ/RJR24<BR> + RJ/RJR24<BR> + RJ/RJR24<BR> + RJ/RJR24<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + </TR> + <TR> + <TD COLSPAN=8>&nbsp; + </TD> + </TR> + <TR> + <TD COLSPAN=8> + <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT> + </TD> + </TR> + <TR> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>BI&nbsp;TECH</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT> + </TD> + </TR> + <TR> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 3323P<BR> + 3323S<BR> + 3323W<BR> + 3329H<BR> + 3329P<BR> + 3329W<BR> + 3339H<BR> + 3339P<BR> + 3339W<BR> + 3352E<BR> + 3352H<BR> + 3352K<BR> + 3352P<BR> + 3352T<BR> + 3352V<BR> + 3352W<BR> + 3362H<BR> + 3362M<BR> + 3362P<BR> + 3362R<BR> + 3362S<BR> + 3362U<BR> + 3362W<BR> + 3362X<BR> + 3386B<BR> + 3386C<BR> + 3386F<BR> + 3386H<BR> + 3386K<BR> + 3386M<BR> + 3386P<BR> + 3386S<BR> + 3386W<BR> + 3386X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 25P<BR> + 25S<BR> + 25RX<BR> + 82P<BR> + 82M<BR> + 82PA<BR> + -<BR> + -<BR> + -<BR> + 91E<BR> + 91X<BR> + 91T<BR> + 91B<BR> + 91A<BR> + 91V<BR> + 91W<BR> + 25W<BR> + 25V<BR> + 25P<BR> + -<BR> + 25S<BR> + 25U<BR> + 25RX<BR> + 25X<BR> + 72XW<BR> + 72XL<BR> + 72PM<BR> + 72RX<BR> + -<BR> + 72PX<BR> + 72P<BR> + 72RXW<BR> + 72RXL<BR> + 72X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + T7YB<BR> + T7YA<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + TXD<BR> + TYA<BR> + TYP<BR> + -<BR> + TYD<BR> + TX<BR> + -<BR> + 150SX<BR> + 100SX<BR> + 102T<BR> + 101S<BR> + 190T<BR> + 150TX<BR> + 101<BR> + -<BR> + -<BR> + 101SX<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + ET6P<BR> + ET6S<BR> + ET6X<BR> + RJ-6W/8014EMW<BR> + RJ-6P/8014EMP<BR> + RJ-6X/8014EMX<BR> + TM7W<BR> + TM7P<BR> + TM7X<BR> + -<BR> + 8017SMS<BR> + -<BR> + 8017SMB<BR> + 8017SMA<BR> + -<BR> + -<BR> + CT-6W<BR> + CT-6H<BR> + CT-6P<BR> + CT-6R<BR> + -<BR> + CT-6V<BR> + CT-6X<BR> + -<BR> + -<BR> + 8038EKV<BR> + -<BR> + 8038EKX<BR> + -<BR> + -<BR> + 8038EKP<BR> + 8038EKZ<BR> + 8038EKW<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + 3321H<BR> + 3321P<BR> + 3321N<BR> + 1102H<BR> + 1102P<BR> + 1102T<BR> + RVA0911V304A<BR> + -<BR> + RVA0911H413A<BR> + RVG0707V100A<BR> + RVA0607V(H)306A<BR> + RVA1214H213A<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 3104B<BR> + 3104C<BR> + 3104F<BR> + 3104H<BR> + -<BR> + 3104M<BR> + 3104P<BR> + 3104S<BR> + 3104W<BR> + 3104X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + EVMQ0G<BR> + EVMQIG<BR> + EVMQ3G<BR> + EVMS0G<BR> + EVMQ0G<BR> + EVMG0G<BR> + -<BR> + -<BR> + -<BR> + EVMK4GA00B<BR> + EVM30GA00B<BR> + EVMK0GA00B<BR> + EVM38GA00B<BR> + EVMB6<BR> + EVLQ0<BR> + -<BR> + EVMMSG<BR> + EVMMBG<BR> + EVMMAG<BR> + -<BR> + -<BR> + EVMMCS<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + EVMM1<BR> + -<BR> + -<BR> + EVMM0<BR> + -<BR> + -<BR> + EVMM3<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + 62-3-1<BR> + 62-1-2<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 67R<BR> + -<BR> + 67P<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 67X<BR> + 63V<BR> + 63S<BR> + 63M<BR> + -<BR> + -<BR> + 63H<BR> + 63P<BR> + -<BR> + -<BR> + 63X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + RJ/RJR50<BR> + RJ/RJR50<BR> + RJ/RJR50<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + </TR> +</TABLE> +<P>&nbsp;<P> +<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=3> + <TR> + <TD COLSPAN=7> + <FONT color="#0000FF" SIZE=4 FACE=ARIAL><B>SMD TRIM-POT CROSS REFERENCE</B></FONT> + <P> + <FONT SIZE=4 FACE=ARIAL><B>MULTI-TURN</B></FONT> + </TD> + </TR> + <TR> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>BI&nbsp;TECH</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT> + </TD> + </TR> + <TR> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 3224G<BR> + 3224J<BR> + 3224W<BR> + 3269P<BR> + 3269W<BR> + 3269X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 44G<BR> + 44J<BR> + 44W<BR> + 84P<BR> + 84W<BR> + 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FACE=ARIAL><B>MURATA</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT> + </TD> + </TR> + <TR> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 3250L<BR> + 3250P<BR> + 3250W<BR> + 3250X<BR> + 3252P<BR> + 3252W<BR> + 3252X<BR> + 3260P<BR> + 3260W<BR> + 3260X<BR> + 3262P<BR> + 3262W<BR> + 3262X<BR> + 3266P<BR> + 3266W<BR> + 3266X<BR> + 3290H<BR> + 3290P<BR> + 3290W<BR> + 3292P<BR> + 3292W<BR> + 3292X<BR> + 3296P<BR> + 3296W<BR> + 3296X<BR> + 3296Y<BR> + 3296Z<BR> + 3299P<BR> + 3299W<BR> + 3299X<BR> + 3299Y<BR> + 3299Z<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + 66P&nbsp;ALT<BR> + 66W&nbsp;ALT<BR> + 66X&nbsp;ALT<BR> + 66P&nbsp;ALT<BR> + 66W&nbsp;ALT<BR> + 66X&nbsp;ALT<BR> + -<BR> + 64W&nbsp;ALT<BR> + -<BR> + 64P&nbsp;ALT<BR> + 64W&nbsp;ALT<BR> + 64X&nbsp;ALT<BR> + 64P<BR> + 64W<BR> + 64X<BR> + 66X&nbsp;ALT<BR> + 66P&nbsp;ALT<BR> + 66W&nbsp;ALT<BR> + 66P<BR> + 66W<BR> + 66X<BR> + 67P<BR> + 67W<BR> + 67X<BR> + 67Y<BR> + 67Z<BR> + 68P<BR> + 68W<BR> + 68X<BR> + 67Y&nbsp;ALT<BR> + 67Z&nbsp;ALT<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 5050<BR> + 5091<BR> + 5080<BR> + 5087<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + T63YB<BR> + T63XB<BR> + -<BR> + -<BR> + -<BR> + 5887<BR> + 5891<BR> + 5880<BR> + -<BR> + -<BR> + -<BR> + T93Z<BR> + T93YA<BR> + T93XA<BR> + T93YB<BR> + T93XB<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 8026EKP<BR> + 8026EKW<BR> + 8026EKM<BR> + 8026EKP<BR> + 8026EKB<BR> + 8026EKM<BR> + 1309X<BR> + 1309P<BR> + 1309W<BR> + 8024EKP<BR> + 8024EKW<BR> + 8024EKN<BR> + RJ-9P/CT9P<BR> + RJ-9W<BR> + RJ-9X<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 3103P<BR> + 3103Y<BR> + 3103Z<BR> + 3103P<BR> + 3103Y<BR> + 3103Z<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 3105P/3106P<BR> + 3105W/3106W<BR> + 3105X/3106X<BR> + 3105Y/3106Y<BR> + 3105Z/3105Z<BR> + 3102P<BR> + 3102W<BR> + 3102X<BR> + 3102Y<BR> + 3102Z<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + EVMCBG<BR> + EVMCCG<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 55-1-X<BR> + 55-4-X<BR> + 55-3-X<BR> + 55-2-X<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 50-2-X<BR> + 50-4-X<BR> + 50-3-X<BR> + -<BR> + -<BR> + -<BR> + 64P<BR> + 64W<BR> + 64X<BR> + 64Y<BR> + 64Z<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + RT/RTR22<BR> + RT/RTR22<BR> + RT/RTR22<BR> + RT/RTR22<BR> + RJ/RJR22<BR> + RJ/RJR22<BR> + RJ/RJR22<BR> + RT/RTR26<BR> + RT/RTR26<BR> + RT/RTR26<BR> + RJ/RJR26<BR> + RJ/RJR26<BR> + RJ/RJR26<BR> + RJ/RJR26<BR> + RJ/RJR26<BR> + RJ/RJR26<BR> + RT/RTR24<BR> + RT/RTR24<BR> + RT/RTR24<BR> + RJ/RJR24<BR> + RJ/RJR24<BR> + RJ/RJR24<BR> + RJ/RJR24<BR> + RJ/RJR24<BR> + RJ/RJR24<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + </TR> + <TR> + <TD COLSPAN=8>&nbsp; + </TD> + </TR> + <TR> + <TD COLSPAN=8> + <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT> + </TD> + </TR> + <TR> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>BI&nbsp;TECH</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT> + </TD> + <TD ALIGN=CENTER> + <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT> + </TD> + </TR> + <TR> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 3323P<BR> + 3323S<BR> + 3323W<BR> + 3329H<BR> + 3329P<BR> + 3329W<BR> + 3339H<BR> + 3339P<BR> + 3339W<BR> + 3352E<BR> + 3352H<BR> + 3352K<BR> + 3352P<BR> + 3352T<BR> + 3352V<BR> + 3352W<BR> + 3362H<BR> + 3362M<BR> + 3362P<BR> + 3362R<BR> + 3362S<BR> + 3362U<BR> + 3362W<BR> + 3362X<BR> + 3386B<BR> + 3386C<BR> + 3386F<BR> + 3386H<BR> + 3386K<BR> + 3386M<BR> + 3386P<BR> + 3386S<BR> + 3386W<BR> + 3386X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 25P<BR> + 25S<BR> + 25RX<BR> + 82P<BR> + 82M<BR> + 82PA<BR> + -<BR> + -<BR> + -<BR> + 91E<BR> + 91X<BR> + 91T<BR> + 91B<BR> + 91A<BR> + 91V<BR> + 91W<BR> + 25W<BR> + 25V<BR> + 25P<BR> + -<BR> + 25S<BR> + 25U<BR> + 25RX<BR> + 25X<BR> + 72XW<BR> + 72XL<BR> + 72PM<BR> + 72RX<BR> + -<BR> + 72PX<BR> + 72P<BR> + 72RXW<BR> + 72RXL<BR> + 72X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + T7YB<BR> + T7YA<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + TXD<BR> + TYA<BR> + TYP<BR> + -<BR> + TYD<BR> + TX<BR> + -<BR> + 150SX<BR> + 100SX<BR> + 102T<BR> + 101S<BR> + 190T<BR> + 150TX<BR> + 101<BR> + -<BR> + -<BR> + 101SX<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + ET6P<BR> + ET6S<BR> + ET6X<BR> + RJ-6W/8014EMW<BR> + RJ-6P/8014EMP<BR> + RJ-6X/8014EMX<BR> + TM7W<BR> + TM7P<BR> + TM7X<BR> + -<BR> + 8017SMS<BR> + -<BR> + 8017SMB<BR> + 8017SMA<BR> + -<BR> + -<BR> + CT-6W<BR> + CT-6H<BR> + CT-6P<BR> + CT-6R<BR> + -<BR> + CT-6V<BR> + CT-6X<BR> + -<BR> + -<BR> + 8038EKV<BR> + -<BR> + 8038EKX<BR> + -<BR> + -<BR> + 8038EKP<BR> + 8038EKZ<BR> + 8038EKW<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + 3321H<BR> + 3321P<BR> + 3321N<BR> + 1102H<BR> + 1102P<BR> + 1102T<BR> + RVA0911V304A<BR> + -<BR> + RVA0911H413A<BR> + RVG0707V100A<BR> + RVA0607V(H)306A<BR> + RVA1214H213A<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 3104B<BR> + 3104C<BR> + 3104F<BR> + 3104H<BR> + -<BR> + 3104M<BR> + 3104P<BR> + 3104S<BR> + 3104W<BR> + 3104X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + EVMQ0G<BR> + EVMQIG<BR> + EVMQ3G<BR> + EVMS0G<BR> + EVMQ0G<BR> + EVMG0G<BR> + -<BR> + -<BR> + -<BR> + EVMK4GA00B<BR> + EVM30GA00B<BR> + EVMK0GA00B<BR> + EVM38GA00B<BR> + EVMB6<BR> + EVLQ0<BR> + -<BR> + EVMMSG<BR> + EVMMBG<BR> + EVMMAG<BR> + -<BR> + -<BR> + EVMMCS<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + EVMM1<BR> + -<BR> + -<BR> + EVMM0<BR> + -<BR> + -<BR> + EVMM3<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + 62-3-1<BR> + 62-1-2<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 67R<BR> + -<BR> + 67P<BR> + -<BR> + -<BR> + -<BR> + -<BR> + 67X<BR> + 63V<BR> + 63S<BR> + 63M<BR> + -<BR> + -<BR> + 63H<BR> + 63P<BR> + -<BR> + -<BR> + 63X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + RJ/RJR50<BR> + RJ/RJR50<BR> + RJ/RJR50<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + </TR> +</TABLE> +<P>&nbsp;<P> +<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=3> + <TR> + <TD COLSPAN=7> + <FONT color="#0000FF" SIZE=4 FACE=ARIAL><B>SMD TRIM-POT CROSS REFERENCE</B></FONT> + <P> + <FONT SIZE=4 FACE=ARIAL><B>MULTI-TURN</B></FONT> + </TD> + </TR> + <TR> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>BI&nbsp;TECH</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT> + </TD> + </TR> + <TR> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 3224G<BR> + 3224J<BR> + 3224W<BR> + 3269P<BR> + 3269W<BR> + 3269X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 44G<BR> + 44J<BR> + 44W<BR> + 84P<BR> + 84W<BR> + 84X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + ST63Z<BR> + ST63Y<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + ST5P<BR> + ST5W<BR> + ST5X<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR> + -<BR></FONT> + </TD> + </TR> + <TR> + <TD COLSPAN=7>&nbsp; + </TD> + </TR> + <TR> + <TD COLSPAN=7> + <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT> + </TD> + </TR> + <TR> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>BI&nbsp;TECH</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT> + </TD> + <TD> + <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT> + </TD> + </TR> + <TR> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 3314G<BR> + 3314J<BR> + 3364A/B<BR> + 3364C/D<BR> + 3364W/X<BR> + 3313G<BR> + 3313J<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + 23B<BR> + 23A<BR> + 21X<BR> + 21W<BR> + -<BR> + 22B<BR> + 22A<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + ST5YL/ST53YL<BR> + ST5YJ/5T53YJ<BR> + ST-23A<BR> + ST-22B<BR> + ST-22<BR> + -<BR> + -<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3> + ST-4B<BR> + ST-4A<BR> + -<BR> + -<BR> + -<BR> + ST-3B<BR> + ST-3A<BR></FONT> + </TD> + <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Logic/68030-68000-bus_working.vhd b/Logic/68030-68000-bus_working.vhd new file mode 100644 index 0000000..7cbd345 --- /dev/null +++ b/Logic/68030-68000-bus_working.vhd @@ -0,0 +1,561 @@ +-- Copyright: Matthias Heinrichs 2014 +-- Free for non-comercial use +-- No warranty just for fun +-- If you want to earn money with this code, ask me first! + + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity BUS68030 is + +port( + AS_030: inout std_logic ; + AS_000: inout std_logic ; + RW_000: inout std_logic ; + DS_030: inout std_logic ; + UDS_000: inout std_logic; + LDS_000: inout std_logic; + SIZE: inout std_logic_vector ( 1 downto 0 ); + AHIGH: inout std_logic_vector ( 31 downto 24 ); + A_DECODE: in std_logic_vector ( 23 downto 2 ); + A: inout std_logic_vector ( 1 downto 0 ); + --A0: inout std_logic; + --A1: in std_logic; + nEXP_SPACE: in std_logic ; + BERR: inout std_logic ; + BG_030: in std_logic ; + BG_000: out std_logic ; + BGACK_030: out std_logic ; + BGACK_000: in std_logic ; + CLK_030: in std_logic ; + CLK_000: in std_logic ; + CLK_OSZI: in std_logic ; + CLK_DIV_OUT: out std_logic ; + CLK_EXP: out std_logic ; + FPU_CS: out std_logic ; + FPU_SENSE: in std_logic ; + IPL_030: out std_logic_vector ( 2 downto 0 ); + IPL: in std_logic_vector ( 2 downto 0 ); + DSACK1: inout std_logic; + DTACK: inout std_logic ; + AVEC: out std_logic ; + E: out std_logic ; + VPA: in std_logic ; + VMA: out std_logic ; + RST: in std_logic ; + RESET: inout std_logic ; + RW: inout std_logic ; +-- D: inout std_logic_vector ( 31 downto 28 ); + FC: in std_logic_vector ( 1 downto 0 ); + AMIGA_ADDR_ENABLE: out std_logic ; + AMIGA_BUS_DATA_DIR: out std_logic ; + AMIGA_BUS_ENABLE_LOW: out std_logic; + AMIGA_BUS_ENABLE_HIGH: out std_logic; + CIIN: out std_logic + ); +end BUS68030; + +architecture Behavioral of BUS68030 is + +-- values are determined empirically +constant DS_SAMPLE : integer := 12; -- for 7.09 MHz Clock with a base clock of 100Mhz and CPU running at 25MHZ +--constant DS_SAMPLE : integer := 12; -- for 7.09 MHz Clock with a base clock of 100Mhz and CPU running at 50MHZ + + + +TYPE SM_E IS ( + E1, + E2, + E3, + E4, + E5, + E6, + E7, + E8, + E9, + E10 + ); + + + +signal cpu_est : SM_E; + +TYPE SM_68000 IS ( + IDLE_P, + IDLE_N, + AS_SET_P, + AS_SET_N, + SAMPLE_DTACK_P, + DATA_FETCH_N, + DATA_FETCH_P, + END_CYCLE_N + ); + + +signal SM_AMIGA : SM_68000; + +--signal Dout:STD_LOGIC_VECTOR(3 downto 0) := "0000"; +signal AS_000_INT:STD_LOGIC := '1'; +signal AS_000_D0:STD_LOGIC := '1'; +signal RW_000_INT:STD_LOGIC := '1'; +signal AMIGA_BUS_ENABLE_DMA_HIGH:STD_LOGIC := '1'; +signal AMIGA_BUS_ENABLE_DMA_LOW:STD_LOGIC := '1'; +signal AS_030_D0:STD_LOGIC := '1'; +signal nEXP_SPACE_D0:STD_LOGIC := '0'; +signal DS_030_D0:STD_LOGIC := '1'; +signal AS_030_000_SYNC:STD_LOGIC := '1'; +signal BGACK_030_INT:STD_LOGIC := '1'; +signal BGACK_030_INT_D:STD_LOGIC := '1'; +signal BGACK_030_INT_PRE:STD_LOGIC := '1'; +signal AS_000_DMA:STD_LOGIC := '1'; +signal DS_000_DMA:STD_LOGIC := '1'; +signal RW_000_DMA:STD_LOGIC := '1'; +signal CYCLE_DMA: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00"; +signal SIZE_DMA: STD_LOGIC_VECTOR ( 1 downto 0 ) := "11"; +signal IPL_D0: STD_LOGIC_VECTOR ( 2 downto 0 ) := "111"; +signal A0_DMA: STD_LOGIC := '1'; +signal VMA_INT: STD_LOGIC := '1'; +signal VPA_D: STD_LOGIC := '1'; +signal UDS_000_INT: STD_LOGIC := '1'; +signal LDS_000_INT: STD_LOGIC := '1'; +signal DS_000_ENABLE: STD_LOGIC := '0'; +signal DSACK1_INT: STD_LOGIC := '1'; +signal CLK_OUT_PRE_50: STD_LOGIC := '1'; +signal CLK_OUT_PRE_25: STD_LOGIC := '1'; +signal CLK_OUT_PRE: STD_LOGIC := '1'; +signal CLK_OUT_PRE_D: STD_LOGIC := '1'; +signal CLK_OUT_INT: STD_LOGIC := '1'; +signal CLK_OUT_EXP_INT: STD_LOGIC := '1'; +signal CLK_030_H: STD_LOGIC := '1'; +signal CLK_000_D: STD_LOGIC_VECTOR ( DS_SAMPLE downto 0 ); +signal CLK_000_PE: STD_LOGIC := '0'; +signal CLK_000_NE: STD_LOGIC := '0'; +signal DTACK_D0: STD_LOGIC := '1'; +signal RESET_OUT: STD_LOGIC := '0'; +signal CLK_030_D0: STD_LOGIC := '0'; +signal RST_DLY: STD_LOGIC_VECTOR ( 2 downto 0 ) := "000"; +signal CLK_030_PE: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00"; +signal AMIGA_DS: STD_LOGIC := '1'; +begin + + CLK_000_PE <= CLK_000_D(0) AND NOT CLK_000_D(1); + CLK_000_NE <= NOT CLK_000_D(0) AND CLK_000_D(1); + + + --pos edge clock process + --no ansynchronious reset! the reset is sampled synchroniously + --this mut be because of the e-clock: The E-Clock has to run CONSTANTLY + --or the Amiga will fail to boot from a reset. + --However a compilation with no resets on the E-Clock and resets on other signals does not work, either! + pos_clk: process(CLK_OSZI) + begin + if(rising_edge(CLK_OSZI)) then + --clk generation : + CLK_030_D0 <=CLK_030; + CLK_OUT_PRE_50 <= not CLK_OUT_PRE_50; + if(CLK_OUT_PRE_50 = '1' )then + CLK_OUT_PRE_25<= not CLK_OUT_PRE_25; + end if; + + + --here the clock is selected + --CLK_OUT_PRE_D <= CLK_OUT_PRE_25; + CLK_OUT_PRE_D <= CLK_OUT_PRE_50; + + -- the external clock to the processor is generated here + CLK_OUT_INT <= CLK_OUT_PRE_D; --this way we know the clock of the next state: Its like looking in the future, cool! + CLK_OUT_EXP_INT <= CLK_OUT_PRE_D; + --delayed Clocks and signals for edge detection + CLK_000_D(0) <= CLK_000; + CLK_000_D(DS_SAMPLE downto 1) <= CLK_000_D((DS_SAMPLE-1) downto 0); + + -- e-clock is changed on the FALLING edge! + + if(CLK_000_NE = '1' ) then + case (cpu_est) is + when E1 => cpu_est <= E2 ; + when E2 => cpu_est <= E3 ; + when E3 => cpu_est <= E4; + when E4 => cpu_est <= E5 ; + when E5 => cpu_est <= E6 ; + when E6 => cpu_est <= E7 ; + when E7 => cpu_est <= E8 ; + when E8 => cpu_est <= E9 ; + when E9 => cpu_est <= E10; + when E10 => cpu_est <= E1 ; + end case; + end if; + + --the statemachine + if(RST = '0' ) then + VPA_D <= '1'; + DTACK_D0 <= '1'; + SM_AMIGA <= IDLE_P; + AS_000_INT <= '1'; + RW_000_INT <= '1'; + RW_000_DMA <= '1'; + AS_030_000_SYNC <= '1'; + UDS_000_INT <= '1'; + LDS_000_INT <= '1'; + DS_000_ENABLE <= '0'; + VMA_INT <= '1'; + BG_000 <= '1'; + BGACK_030_INT <= '1'; + BGACK_030_INT_D <= '1'; + BGACK_030_INT_PRE<= '1'; + DSACK1_INT <= '1'; + IPL_D0 <= "111"; + IPL_030 <= "111"; + AS_000_DMA <= '1'; + DS_000_DMA <= '1'; + SIZE_DMA <= "11"; + A0_DMA <= '1'; + AMIGA_BUS_ENABLE_DMA_HIGH <= '1'; + AMIGA_BUS_ENABLE_DMA_LOW <= '1'; + AS_030_D0 <= '1'; + nEXP_SPACE_D0 <= '1'; + DS_030_D0 <= '1'; + CYCLE_DMA <= "00"; + RST_DLY <= "000"; + RESET_OUT <= '0'; + AS_000_D0 <='1'; + AMIGA_DS <='1'; + CLK_030_PE <= "00"; + else + + if(CLK_000_NE='1')then + if(RST_DLY="111")then + RESET_OUT <= '1'; + else + RST_DLY <= RST_DLY+1; + end if; + end if; + + --now: 68000 state machine and signals + + --buffering signals + AS_030_D0 <= AS_030; + nEXP_SPACE_D0 <= nEXP_SPACE; + DS_030_D0 <= DS_030; + DTACK_D0 <= DTACK; + VPA_D <= VPA; + + + --bgack is simple: assert as soon as Amiga asserts but hold bg_ack for one amiga-clock + if(BGACK_000='0') then + BGACK_030_INT <= '0'; + --BGACK_030_INT_PRE<= '0'; + elsif ( BGACK_000='1' + AND CLK_000_NE='1' + AND AS_000 = '1' --the amiga AS can be still active while bgack is deasserted, so wait for this signal too! + ) then -- BGACK_000 is high here! + --BGACK_030_INT_PRE<= '1'; + BGACK_030_INT <= '1'; --hold this signal high until 7m clock goes low + end if; + BGACK_030_INT_D <= BGACK_030_INT; + + + + --bus grant only in idle state + if(BG_030= '1')then + BG_000 <= '1'; + elsif( BG_030= '0' --AND (SM_AMIGA = IDLE_P) + and nEXP_SPACE = '1' and AS_030_D0='1' + and CLK_000_D(0)='1' + ) then --bus granted no local access and no AS_030 running! + BG_000 <= '0'; + end if; + + + --interrupt buffering to avoid ghost interrupts + IPL_D0<=IPL; + if(IPL = IPL_D0) then --and CLK_000_PE = '1')then + IPL_030<=IPL; + end if; + + -- as030-sampling and FPU-Select + if(AS_030 ='1') then -- "async" reset of various signals + AS_030_000_SYNC <= '1'; + DSACK1_INT <= '1'; + AS_000_INT <= '1'; + DS_000_ENABLE <= '0'; + --RW_000_INT <= '1'; + elsif( --CLK_030 = '1' AND --68030 has a valid AS on high clocks + AS_030_D0 = '0' AND --as set + BGACK_030_INT='1' AND + BGACK_030_INT_D='1' AND --no dma -cycle + NOT (FC(1)='1' and FC(0)='1' and A_DECODE(19)='0' and A_DECODE(18)='0' and A_DECODE(17)='1' and A_DECODE(16)='0') AND --FPU-Select + nEXP_SPACE ='1' and --not an expansion space cycle + SM_AMIGA = IDLE_P --last amiga cycle terminated + ) then + AS_030_000_SYNC <= '0'; + end if; + + + -- VMA generation + if(CLK_000_NE='1' AND VPA_D='0' AND cpu_est = E4)then --assert + VMA_INT <= '0'; + elsif(CLK_000_PE='1' AND cpu_est=E1)then --deassert + VMA_INT <= '1'; + end if; + + --uds/lds precalculation + if (SM_AMIGA = IDLE_N) then --DS: set udl/lds + if(A(0)='0') then + UDS_000_INT <= '0'; + else + UDS_000_INT <= '1'; + end if; + if((A(0)='1' OR SIZE(0)='0' OR SIZE(1)='1')) then + LDS_000_INT <= '0'; + else + LDS_000_INT <= '1'; + end if; + end if; + + + --Amiga statemachine + + case (SM_AMIGA) is + when IDLE_P => --68000:S0 wait for a falling edge + RW_000_INT <= '1'; + if( CLK_000_D(3)='0' and CLK_000_D(4)= '1' and AS_030_000_SYNC = '0' and nEXP_SPACE ='1')then -- if this a delayed expansion space detection, do not start an amiga cycle! + SM_AMIGA<=IDLE_N; --go to s1 + end if; + when IDLE_N => --68000:S1 place Adress on bus and wait for rising edge, on a rising CLK_000 look for a amiga adressrobe + if(CLK_000_PE='1')then --go to s2 + SM_AMIGA <= AS_SET_P; --as for amiga set! + RW_000_INT <= RW; + AS_000_INT <= '0'; + if (RW='1' ) then --read: set udl/lds + DS_000_ENABLE <= '1'; + end if; + end if; + when AS_SET_P => --68000:S2 Amiga cycle starts here: since AS is asserted during transition to this state we simply wait here + if(CLK_000_NE='1')then --go to s3 + SM_AMIGA<=AS_SET_N; + end if; + when AS_SET_N => --68000:S3: nothing happens here; on a transition to s4: assert uds/lds on write + + if(CLK_000_PE='1')then --go to s4 + -- set DS-Enable without respect to rw: this simplifies the life for the syntesizer + DS_000_ENABLE <= '1';--write: set udl/lds earlier than in the specs. this does not seem to harm anything and is saver, than sampling uds/lds too late + SM_AMIGA <= SAMPLE_DTACK_P; + end if; + when SAMPLE_DTACK_P=> --68000:S4 wait for dtack or VMA + if( CLK_000_NE='1' and --falling edge + ((VPA_D = '1' AND DTACK_D0='0') OR --DTACK end cycle + (BERR='0') OR --Bus error + (VPA_D='0' AND cpu_est=E9 AND VMA_INT='0')) --VPA end cycle + )then --go to s5 + SM_AMIGA<=DATA_FETCH_N; + end if; + when DATA_FETCH_N=> --68000:S5 nothing happens here just wait for positive clock + if(CLK_000_PE = '1')then --go to s6 + SM_AMIGA<=DATA_FETCH_P; + end if; + when DATA_FETCH_P => --68000:S6: READ: here comes the data on the bus! + --if( (CLK_000_D(DS_SAMPLE-2)='0' AND CLK_000_D((DS_SAMPLE-1))='1' AND not (CLK_030 ='1' and CLK_OUT_PRE_D='0')) OR + -- (CLK_000_D(DS_SAMPLE-1)='0' AND CLK_000_D((DS_SAMPLE-0))='1' )) then --go to s7 next 030-clock is not a falling edge: dsack is sampled at the falling edge + -- DSACK1_INT <='0'; + --end if; + + --go to s7 dsack is sampled at the falling edge of the 030-clock + --if(CLK_000_D(0)='0' and CLK_000_D(1)='1')then + if( CLK_000_NE ='1') then + SM_AMIGA<=END_CYCLE_N; + DSACK1_INT <='0'; + end if; + when END_CYCLE_N =>--68000:S7: Latch/Store data. Wait here for new cycle and go to IDLE on high clock + if(CLK_000_PE='1')then --go to s0 + SM_AMIGA<=IDLE_P; + RW_000_INT <= '1'; + end if; + end case; + + --dma stuff + AS_000_D0 <=AS_000; + if(UDS_000='0' or LDS_000='0') then + AMIGA_DS <='0'; + else + AMIGA_DS <='1'; + end if; + + if(BGACK_030_INT='0')then + --set some signals NOT linked to AS_000='0' + RW_000_DMA <= RW_000; + -- now determine the size: if both uds and lds is set its 16 bit else 8 bit! + + + + if(UDS_000='0' and LDS_000='0') then + SIZE_DMA <= "10"; --16bit + else + SIZE_DMA <= "01"; --8 bit + end if; + --now calculate the offset: + --if uds is set low, a0 is so too. + --if only lds is set a1 is high + --therefore a1 = uds + --great! life is simple here! + A0_DMA <= UDS_000; + --A0_DMA <= '0'; + --A1 is set by the amiga side + --here we determine the upper or lower half of the databus + AMIGA_BUS_ENABLE_DMA_HIGH <= A(1); + AMIGA_BUS_ENABLE_DMA_LOW <= not A(1); + + elsif(BGACK_030_INT_D='0' and BGACK_030_INT='1')then + RW_000_DMA <= '1'; + SIZE_DMA <= "00"; + A0_DMA <= '0'; + AMIGA_BUS_ENABLE_DMA_HIGH <= '1'; + AMIGA_BUS_ENABLE_DMA_LOW <= '1'; + end if; + + if(BGACK_030_INT='0' and AS_000='0')then + -- an 68000-memory cycle is three negative edges long! + if(CLK_000_NE='1' and CYCLE_DMA<"11")then + CYCLE_DMA <= CYCLE_DMA+1; + end if; + else + CYCLE_DMA <= "00"; + end if; + + --as can only be done if we know the uds/lds! + if( CYCLE_DMA >"00" + and AS_000 = '0' + and AMIGA_DS ='0' + and ( + CYCLE_DMA < "11" + or RW_000 = '1') + )then + --set AS_000 + if( not(CLK_OUT_INT='0' and CLK_OUT_PRE_D ='1')) then --sampled on rising edges, so we can set AS only if the next clock is not rising!! + AS_000_DMA <= '0'; + if(RW_000='1') then + DS_000_DMA <='0'; + end if; + end if; + + if( CLK_OUT_INT='0' and CLK_OUT_PRE_D ='1' and CLK_030_PE <"11" and AS_000_DMA = '0') then --sample rising edges + CLK_030_PE <= CLK_030_PE+1; + end if; + + if(RW_000='0' and CLK_030_PE="01" and CLK_030='1')then + DS_000_DMA <= '0'; -- write: one clock delayed! + end if; + + else + CLK_030_PE <= "00"; + AS_000_DMA <= '1'; + DS_000_DMA <= '1'; + end if; + end if; + + end if; + end process pos_clk; + + --output clock assignment + CLK_DIV_OUT <= CLK_OUT_INT; + CLK_EXP <= CLK_OUT_INT;--not CLK_OUT_EXP_INT; + --CLK_DIV_OUT <= 'Z'; + --CLK_EXP <= CLK_030; + + + RESET <= 'Z'; + --RESET <= 'Z' when RESET_OUT ='1' else '0'; + --RST <= '0' when RESET_OUT_AMIGA = '1' else 'Z'; + --RESET <= RESET_OUT; + + -- bus drivers + AMIGA_ADDR_ENABLE <= '0'; + AMIGA_BUS_ENABLE_HIGH <= '0' WHEN BGACK_030_INT ='1' and AS_030_000_SYNC='0' and AS_030 = '0' else --not (SM_AMIGA = IDLE_P or (SM_AMIGA = END_CYCLE_N and CLK_000 = '1')) ELSE + '0' WHEN BGACK_030_INT ='0' AND AMIGA_BUS_ENABLE_DMA_HIGH = '0' ELSE + '1'; + AMIGA_BUS_ENABLE_LOW <= '0' WHEN BGACK_030_INT ='0' AND AMIGA_BUS_ENABLE_DMA_LOW = '0' ELSE + '1'; + + + AMIGA_BUS_DATA_DIR <= not RW_000 WHEN (BGACK_030_INT ='1') ELSE --Amiga READ/WRITE + --'0' WHEN (RW_000='1' AND BGACK_030_INT ='1') ELSE --Amiga READ + '1' WHEN (RW_000='1' AND BGACK_030_INT ='0' AND nEXP_SPACE = '0' AND AS_000 = '0') ELSE --DMA READ to expansion space + --'0' WHEN (RW_000='0' AND BGACK_030_INT ='0' AND AS_000 = '0') ELSE --DMA WRITE to expansion space + '0'; --Point towarts TK + + + --dma stuff + DTACK <= 'Z' when AS_000_DMA='1' else '0'; --DTACK will be generated by GARY! + + AS_030 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' or RESET_OUT ='0' else + '0' when AS_000_DMA ='0' and AS_000 ='0' else + '1'; + DS_030 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' or RESET_OUT ='0' else + '0' when DS_000_DMA ='0' and AS_000 ='0' else + '1'; + A(0) <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' or RESET_OUT ='0' --tristate on CPU-Cycle + else A0_DMA; --drive on DMA-Cycle + A(1) <= 'Z'; + AHIGH <= "ZZZZZZZZ" when BGACK_030_INT ='1' OR nEXP_SPACE = '1' OR RESET = '0' else x"00"; + SIZE <= "ZZ" when BGACK_030_INT ='1' OR nEXP_SPACE = '1' else + SIZE_DMA; + --rw + RW <= 'Z' when BGACK_030_INT ='1' or RESET_OUT ='0' --tristate on CPU cycle + else RW_000_DMA; --drive on DMA-Cycle + + BGACK_030 <= BGACK_030_INT; + + --fpu + FPU_CS <= '0' when AS_030 ='0' and FC(1)='1' and FC(0)='1' and A_DECODE(19)='0' and A_DECODE(18)='0' and A_DECODE(17)='1' and A_DECODE(16)='0' AND BGACK_000='1' AND FPU_SENSE ='0' + else '1'; + + --if no copro is installed: + BERR <= '0' when AS_030 ='0' and FC(1)='1' and FC(0)='1' and A_DECODE(19)='0' and A_DECODE(18)='0' and A_DECODE(17)='1' and A_DECODE(16)='0' AND BGACK_000='1' AND FPU_SENSE ='1' + else 'Z'; + + + --cache inhibit: Tristate for expansion (it decides) and off for the Amiga + CIIN <= '1' WHEN AHIGH(31 downto 24) = x"00" and A_DECODE(23 downto 20) = x"F" and AS_030_D0 ='0' ELSE -- Enable for Kick-rom + 'Z' WHEN nEXP_SPACE = '0' ELSE --Tristate for expansion (it decides) + '0'; --off for the Amiga + + --e and VMA + E <= '1' when + cpu_est = E7 or + cpu_est = E8 or + cpu_est = E9 or + cpu_est = E10 + else '0'; + VMA <= VMA_INT; + + + --AVEC + AVEC <= '1'; + + --as and uds/lds + AS_000 <= 'Z' when BGACK_030_INT ='0' or RESET_OUT ='0' else + '0' when AS_000_INT ='0' and AS_030 ='0' else + '1'; + RW_000 <= 'Z' when BGACK_030_INT ='0' or RESET_OUT ='0' --tristate on DMA-cycle + else RW_000_INT; -- drive on CPU cycle + + UDS_000 <= 'Z' when BGACK_030_INT ='0' or RESET_OUT ='0' else --tristate on DMA cycle + --'1' when DS_000_ENABLE ='0' else + UDS_000_INT when DS_000_ENABLE ='1' -- output on cpu cycle + else '1'; -- datastrobe not ready jet + LDS_000 <= 'Z' when BGACK_030_INT ='0' or RESET_OUT ='0' else --tristate on DMA cycle + --'1' when DS_000_ENABLE ='0' else + LDS_000_INT when DS_000_ENABLE ='1' -- output on cpu cycle + else '1'; -- datastrobe not ready jet + + --dsack + DSACK1 <= 'Z' when nEXP_SPACE = '0' else --tristate on expansionboard cycle + DSACK1_INT when AS_030 = '0' else -- output on amiga cycle + '1'; + + +end Behavioral; diff --git a/Logic/68030_TK.tcl b/Logic/68030_TK.tcl index 7f8bbe2..0359930 100644 --- a/Logic/68030_TK.tcl +++ b/Logic/68030_TK.tcl @@ -425660,3 +425660,1284 @@ if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 6 ########## Tcl recorder end at 11/18/16 19:32:22 ########### + +########## Tcl recorder starts at 12/08/16 21:23:14 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 12/08/16 21:23:14 ########### + + +########## Tcl recorder starts at 12/08/16 21:23:14 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 12/08/16 21:23:14 ########### + + +########## Tcl recorder starts at 12/08/16 21:50:43 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 12/08/16 21:50:43 ########### + + +########## Tcl recorder starts at 12/08/16 21:50:43 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 12/08/16 21:50:43 ########### + + +########## Tcl recorder starts at 12/29/16 15:51:49 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 12/29/16 15:51:49 ########### + + +########## Tcl recorder starts at 12/29/16 15:51:49 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 12/29/16 15:51:49 ########### + + +########## Tcl recorder starts at 12/29/16 15:59:07 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 12/29/16 15:59:07 ########### + + +########## Tcl recorder starts at 12/29/16 15:59:08 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 12/29/16 15:59:08 ########### + + +########## Tcl recorder starts at 12/29/16 15:59:47 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 12/29/16 15:59:47 ########### + + +########## Tcl recorder starts at 12/29/16 15:59:47 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 12/29/16 15:59:47 ########### + + +########## Tcl recorder starts at 12/29/16 16:00:49 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 12/29/16 16:00:49 ########### + + +########## Tcl recorder starts at 12/29/16 16:00:49 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 12/29/16 16:00:49 ########### + + +########## Tcl recorder starts at 12/29/16 16:01:41 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 12/29/16 16:01:41 ########### + + +########## Tcl recorder starts at 12/29/16 16:01:42 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 12/29/16 16:01:42 ########### + diff --git a/Logic/68030_tk-Resetfix-soft_timing.zip b/Logic/68030_tk-Resetfix-soft_timing.zip new file mode 100644 index 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2016 +#$ DATE Thu Dec 29 16:01:56 2016 #$ MODULE 68030_tk #$ PINS 75 A_DECODE_2_ A_0_ SIZE_1_ IPL_030_1_ IPL_030_0_ AHIGH_31_ IPL_1_ IPL_0_ \ # A_DECODE_23_ FC_0_ A_1_ IPL_030_2_ IPL_2_ FC_1_ AS_030 AS_000 RW_000 DS_030 UDS_000 \ diff --git a/Logic/68030_tk.bl3 b/Logic/68030_tk.bl3 index 8737403..2f15fc4 100644 --- a/Logic/68030_tk.bl3 +++ b/Logic/68030_tk.bl3 @@ -1,5 +1,5 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Fri Nov 18 19:32:36 2016 +#$ DATE Thu Dec 29 16:01:56 2016 #$ MODULE 68030_tk #$ PINS 61 A_0_ SIZE_1_ IPL_030_1_ IPL_030_0_ AHIGH_31_ IPL_1_ IPL_0_ A_DECODE_23_ \ # FC_0_ A_1_ IPL_030_2_ IPL_2_ FC_1_ AS_030 AS_000 RW_000 DS_030 UDS_000 LDS_000 nEXP_SPACE \ diff --git a/Logic/68030_tk.crf b/Logic/68030_tk.crf index aade194..491c0f9 100644 --- a/Logic/68030_tk.crf +++ b/Logic/68030_tk.crf @@ -1,7 +1,7 @@ // Signal Name Cross Reference File // ispLEVER Classic 2.0.00.17.20.15 -// Design '68030_tk' created Fri Nov 18 19:32:36 2016 +// Design '68030_tk' created Thu Dec 29 16:01:56 2016 // LEGEND: '>' Functional Block Port Separator diff --git a/Logic/68030_tk.eq3 b/Logic/68030_tk.eq3 index 43f1c17..fc3aa63 100644 --- a/Logic/68030_tk.eq3 +++ b/Logic/68030_tk.eq3 @@ -2,7 +2,7 @@ Copyright(C), 1992-2015, Lattice Semiconductor Corp. All Rights Reserved. -Design bus68030 created Fri Nov 18 19:32:36 2016 +Design bus68030 created Thu Dec 29 16:01:56 2016 P-Terms Fan-in Fan-out Type Name (attributes) diff --git a/Logic/68030_tk.ipr b/Logic/68030_tk.ipr index d075273..091112f 100644 --- a/Logic/68030_tk.ipr +++ b/Logic/68030_tk.ipr @@ -1 +1 @@ -64;0=1?P_reM=E> \ No newline at end of file +6050655){ N diff --git a/Logic/68030_tk.jed b/Logic/68030_tk.jed index 0c900f7..a7544f4 100644 --- a/Logic/68030_tk.jed +++ b/Logic/68030_tk.jed @@ -10,7 +10,7 @@ AUTHOR: PATTERN: COMPANY: REVISION: -DATE: Fri Nov 18 19:32:41 2016 +DATE: Thu Dec 29 16:02:00 2016 ABEL mach447a * diff --git a/Logic/68030_tk.lco b/Logic/68030_tk.lco index 2b54089..3e3384c 100644 --- a/Logic/68030_tk.lco +++ b/Logic/68030_tk.lco @@ -16,8 +16,8 @@ RCS = "$Revision: 1.2 $"; Parent = m4a5.lci; SDS_File = m4a5.sds; Design = 68030_tk.tt4; -DATE = 11/18/16; -TIME = 19:32:41; +DATE = 12/29/16; +TIME = 16:02:00; Source_Format = Pure_VHDL; Type = TT2; Pre_Fit_Time = 1; diff --git a/Logic/68030_tk.out b/Logic/68030_tk.out index e4e66e9..ab5d2b0 100644 --- a/Logic/68030_tk.out +++ b/Logic/68030_tk.out @@ -8870,6 +8870,906 @@ 316 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 315 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 314 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 + 306 inst_DTACK_D0 3 -1 1 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_DECODE_19_ 1 -1 -1 3 1 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 1 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 1 4 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 1 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 1 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 1 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 2 RESET 1 -1 -1 2 1 2 2 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 63 CLK_030 1 -1 -1 1 0 63 -1 + 59 A_1_ 1 -1 -1 1 5 59 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 5 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 +115 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 -1 7 5 2 3 4 6 7 81 -1 1 0 21 + 41 AS_000 5 -1 4 4 0 4 5 7 41 -1 1 0 21 + 79 RW_000 5 339 7 3 4 5 6 79 -1 4 0 21 + 31 UDS_000 5 -1 3 3 5 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 5 6 7 30 -1 1 0 21 + 68 A_0_ 5 345 6 2 0 2 68 -1 3 0 21 + 70 RW 5 344 6 2 3 7 70 -1 2 0 21 + 78 SIZE_1_ 5 337 7 1 2 78 -1 3 0 21 + 69 SIZE_0_ 5 340 6 1 2 69 -1 3 0 21 + 40 BERR 5 -1 4 1 0 40 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 338 1 0 8 -1 9 0 21 + 7 IPL_030_0_ 5 347 1 0 7 -1 9 0 21 + 6 IPL_030_1_ 5 346 1 0 6 -1 9 0 21 + 82 BGACK_030 5 342 7 0 82 -1 3 0 21 + 34 VMA 5 343 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 341 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 80 DSACK1 0 7 0 80 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 342 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 322 SM_AMIGA_6_ 3 -1 1 7 0 1 2 3 5 6 7 -1 -1 3 0 21 + 309 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 311 CLK_000_D_0_ 3 -1 3 6 0 1 3 5 6 7 -1 -1 1 0 21 + 310 CLK_000_D_1_ 3 -1 7 6 0 1 3 5 6 7 -1 -1 1 0 21 + 300 inst_AS_030_000_SYNC 3 -1 2 3 1 2 3 -1 -1 7 0 21 + 295 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 + 293 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 + 335 SM_AMIGA_i_7_ 3 -1 1 3 1 2 7 -1 -1 3 1 21 + 324 SM_AMIGA_1_ 3 -1 0 3 0 6 7 -1 -1 3 0 21 + 301 inst_BGACK_030_INT_D 3 -1 7 3 2 6 7 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 7 3 2 3 4 -1 -1 1 0 21 + 296 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 1 1 21 + 303 inst_DS_000_DMA 3 -1 5 2 0 5 -1 -1 9 0 21 + 302 inst_AS_000_DMA 3 -1 5 2 5 7 -1 -1 7 0 21 + 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 + 332 SM_AMIGA_5_ 3 -1 5 2 0 5 -1 -1 3 0 21 + 325 SM_AMIGA_0_ 3 -1 7 2 1 7 -1 -1 3 0 21 + 323 SM_AMIGA_4_ 3 -1 0 2 0 3 -1 -1 3 0 21 + 319 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 + 304 CYCLE_DMA_0_ 3 -1 0 2 0 5 -1 -1 3 0 21 + 294 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21 + 331 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21 + 330 inst_DSACK1_INT 3 -1 6 2 6 7 -1 -1 2 0 21 + 321 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 + 307 CLK_000_D_3_ 3 -1 2 2 1 7 -1 -1 1 0 21 + 306 inst_VPA_D 3 -1 3 2 0 3 -1 -1 1 0 21 + 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 + 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 + 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 + 329 inst_CLK_030_H 3 -1 5 1 5 -1 -1 8 0 21 + 334 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 5 0 21 + 333 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 + 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 326 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 + 305 CYCLE_DMA_1_ 3 -1 5 1 5 -1 -1 4 0 21 + 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 340 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 + 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 + 320 inst_DS_000_ENABLE 3 -1 3 1 3 -1 -1 3 0 21 + 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 341 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 328 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 + 327 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 + 318 CLK_000_D_4_ 3 -1 7 1 1 -1 -1 1 0 21 + 317 CLK_000_D_2_ 3 -1 7 1 2 -1 -1 1 0 21 + 316 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 315 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 314 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21 + 312 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 308 inst_DTACK_D0 3 -1 0 1 0 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 + 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 66 IPL_0_ 1 -1 -1 2 1 2 66 -1 + 59 A_1_ 1 -1 -1 2 2 6 59 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 63 CLK_030 1 -1 -1 1 5 63 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 3 35 -1 + 29 DTACK 1 -1 -1 1 0 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 +119 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 -1 7 6 0 1 2 3 4 7 81 -1 1 0 21 + 79 RW_000 5 345 7 3 0 4 6 79 -1 4 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 31 UDS_000 5 -1 3 3 2 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 2 6 7 30 -1 1 0 21 + 70 RW 5 350 6 2 2 7 70 -1 2 0 21 + 78 SIZE_1_ 5 341 7 1 5 78 -1 3 0 21 + 69 SIZE_0_ 5 348 6 1 5 69 -1 3 0 21 + 68 A_0_ 5 340 6 1 5 68 -1 3 0 21 + 40 BERR 5 -1 4 1 2 40 -1 1 0 21 + 29 DTACK 5 -1 3 1 1 29 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 344 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 343 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 342 1 0 6 -1 10 0 21 + 82 BGACK_030 5 347 7 0 82 -1 3 0 21 + 34 VMA 5 349 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 346 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 80 DSACK1 0 7 0 80 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 347 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 311 CLK_000_D_0_ 3 -1 3 6 0 2 3 5 6 7 -1 -1 1 0 21 + 310 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 + 307 inst_RESET_OUT 3 -1 6 5 0 3 4 6 7 -1 -1 2 0 21 + 322 SM_AMIGA_6_ 3 -1 5 4 2 5 6 7 -1 -1 3 0 21 + 301 inst_BGACK_030_INT_D 3 -1 7 4 1 5 6 7 -1 -1 1 0 21 + 300 inst_AS_030_000_SYNC 3 -1 1 3 1 3 5 -1 -1 7 0 21 + 302 inst_AS_000_DMA 3 -1 0 3 0 3 7 -1 -1 6 0 21 + 295 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 + 293 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 + 337 SM_AMIGA_i_7_ 3 -1 5 3 1 5 7 -1 -1 3 1 21 + 325 SM_AMIGA_0_ 3 -1 0 3 0 5 7 -1 -1 3 0 21 + 296 cpu_est_0_ 3 -1 6 3 2 3 6 -1 -1 3 0 21 + 338 CLK_OUT_INTreg 3 -1 3 3 0 1 6 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 7 3 1 3 4 -1 -1 1 0 21 + 294 cpu_est_2_ 3 -1 3 3 2 3 6 -1 -1 1 1 21 + 336 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 5 0 21 + 349 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 + 334 SM_AMIGA_5_ 3 -1 6 2 0 6 -1 -1 3 0 21 + 324 SM_AMIGA_1_ 3 -1 5 2 0 5 -1 -1 3 0 21 + 323 SM_AMIGA_4_ 3 -1 0 2 0 2 -1 -1 3 0 21 + 320 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 + 319 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 + 333 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 332 inst_DSACK1_INT 3 -1 0 2 0 7 -1 -1 2 0 21 + 321 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 2 3 5 -1 -1 2 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 4 2 0 3 -1 -1 1 0 21 + 312 inst_CLK_OUT_PRE_50 3 -1 6 2 4 6 -1 -1 1 0 21 + 305 CLK_000_D_3_ 3 -1 5 2 2 5 -1 -1 1 0 21 + 304 inst_VPA_D 3 -1 5 2 2 3 -1 -1 1 0 21 + 344 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 343 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 342 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 328 CLK_030_PE_0_ 3 -1 0 1 0 -1 -1 9 0 21 + 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 308 CLK_030_PE_1_ 3 -1 0 1 0 -1 -1 6 0 21 + 335 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 + 345 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 329 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 + 326 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 4 0 21 + 348 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 + 341 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 + 340 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 350 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 346 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 339 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 331 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 + 330 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 + 327 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 2 0 21 + 309 inst_AMIGA_DS 3 -1 2 1 0 -1 -1 2 0 21 + 318 CLK_000_D_4_ 3 -1 2 1 5 -1 -1 1 0 21 + 317 CLK_000_D_2_ 3 -1 7 1 5 -1 -1 1 0 21 + 316 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 315 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 314 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 + 306 inst_DTACK_D0 3 -1 1 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_DECODE_19_ 1 -1 -1 3 1 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 1 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 1 4 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 1 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 1 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 1 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 2 RESET 1 -1 -1 2 1 2 2 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 63 CLK_030 1 -1 -1 1 0 63 -1 + 59 A_1_ 1 -1 -1 1 5 59 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 5 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 +125 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 -1 7 6 1 2 3 4 5 7 81 -1 1 0 21 + 41 AS_000 5 -1 4 4 0 4 5 7 41 -1 1 0 21 + 79 RW_000 5 348 7 3 0 4 6 79 -1 4 0 21 + 70 RW 5 355 6 2 5 7 70 -1 2 0 21 + 31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21 + 78 SIZE_1_ 5 346 7 1 5 78 -1 3 0 21 + 69 SIZE_0_ 5 356 6 1 5 69 -1 3 0 21 + 68 A_0_ 5 349 6 1 5 68 -1 3 0 21 + 40 BERR 5 -1 4 1 2 40 -1 1 0 21 + 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 347 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 351 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 350 1 0 6 -1 10 0 21 + 82 BGACK_030 5 353 7 0 82 -1 3 0 21 + 34 VMA 5 354 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 352 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 80 DSACK1 0 7 0 80 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 353 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 314 CLK_000_D_0_ 3 -1 4 6 0 2 3 5 6 7 -1 -1 1 0 21 + 313 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 + 310 inst_RESET_OUT 3 -1 0 5 0 3 4 6 7 -1 -1 2 0 21 + 301 inst_BGACK_030_INT_D 3 -1 7 4 0 1 6 7 -1 -1 1 0 21 + 300 inst_AS_030_000_SYNC 3 -1 1 3 1 3 5 -1 -1 7 0 21 + 302 inst_AS_000_DMA 3 -1 0 3 0 3 7 -1 -1 6 0 21 + 295 cpu_est_1_ 3 -1 6 3 2 3 6 -1 -1 4 0 21 + 293 cpu_est_3_ 3 -1 6 3 2 3 6 -1 -1 4 0 21 + 343 SM_AMIGA_i_7_ 3 -1 5 3 1 5 7 -1 -1 3 1 21 + 330 SM_AMIGA_0_ 3 -1 6 3 5 6 7 -1 -1 3 0 21 + 294 cpu_est_0_ 3 -1 3 3 2 3 6 -1 -1 3 0 21 + 344 CLK_OUT_INTreg 3 -1 2 3 0 1 6 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 7 3 1 3 4 -1 -1 1 0 21 + 296 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 1 1 21 + 342 SM_AMIGA_2_ 3 -1 2 2 2 6 -1 -1 5 0 21 + 337 inst_DSACK1_INT 3 -1 2 2 2 7 -1 -1 5 0 21 + 331 CYCLE_DMA_0_ 3 -1 5 2 0 5 -1 -1 4 0 21 + 354 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 + 339 SM_AMIGA_1_ 3 -1 6 2 2 6 -1 -1 3 0 21 + 329 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21 + 328 SM_AMIGA_6_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 326 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 + 325 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 + 338 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 + 332 CYCLE_DMA_1_ 3 -1 5 2 0 5 -1 -1 2 0 21 + 327 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 320 CLK_000_D_4_ 3 -1 1 2 1 5 -1 -1 1 0 21 + 315 inst_CLK_OUT_PRE_50 3 -1 3 2 2 3 -1 -1 1 0 21 + 307 CLK_000_D_8_ 3 -1 3 2 2 3 -1 -1 1 0 21 + 306 CLK_000_D_3_ 3 -1 1 2 1 5 -1 -1 1 0 21 + 305 inst_CLK_OUT_PRE_D 3 -1 2 2 0 2 -1 -1 1 0 21 + 304 inst_VPA_D 3 -1 3 2 2 3 -1 -1 1 0 21 + 351 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 350 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 347 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 333 CLK_030_PE_0_ 3 -1 0 1 0 -1 -1 9 0 21 + 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 311 CLK_030_PE_1_ 3 -1 0 1 0 -1 -1 6 0 21 + 341 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 + 348 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 334 RST_DLY_0_ 3 -1 0 1 0 -1 -1 4 0 21 + 356 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 + 349 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 346 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 + 340 SM_AMIGA_5_ 3 -1 5 1 5 -1 -1 3 0 21 + 355 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 352 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 345 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 336 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21 + 335 RST_DLY_1_ 3 -1 0 1 0 -1 -1 2 1 21 + 312 inst_AMIGA_DS 3 -1 7 1 0 -1 -1 2 0 21 + 324 CLK_000_D_10_ 3 -1 2 1 2 -1 -1 1 0 21 + 323 CLK_000_D_7_ 3 -1 6 1 3 -1 -1 1 0 21 + 322 CLK_000_D_6_ 3 -1 3 1 6 -1 -1 1 0 21 + 321 CLK_000_D_5_ 3 -1 1 1 3 -1 -1 1 0 21 + 319 CLK_000_D_2_ 3 -1 7 1 1 -1 -1 1 0 21 + 318 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 317 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 316 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 + 309 inst_DTACK_D0 3 -1 6 1 2 -1 -1 1 0 21 + 308 CLK_000_D_9_ 3 -1 3 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_DECODE_19_ 1 -1 -1 3 1 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 1 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 1 4 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 1 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 1 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 1 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 + 63 CLK_030 1 -1 -1 2 0 2 63 -1 + 59 A_1_ 1 -1 -1 2 0 6 59 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 2 RESET 1 -1 -1 2 1 2 2 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 3 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 4 10 -1 +127 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 -1 7 7 0 1 3 4 5 6 7 81 -1 1 0 21 + 41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21 + 79 RW_000 5 350 7 3 2 4 6 79 -1 4 0 21 + 70 RW 5 357 6 2 0 7 70 -1 2 0 21 + 31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21 + 78 SIZE_1_ 5 348 7 1 0 78 -1 3 0 21 + 69 SIZE_0_ 5 358 6 1 0 69 -1 3 0 21 + 68 A_0_ 5 351 6 1 0 68 -1 3 0 21 + 40 BERR 5 -1 4 1 3 40 -1 1 0 21 + 29 DTACK 5 -1 3 1 2 29 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 349 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 355 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 353 1 0 6 -1 10 0 21 + 82 BGACK_030 5 354 7 0 82 -1 3 0 21 + 34 VMA 5 356 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 352 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 80 DSACK1 0 7 0 80 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 354 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 314 CLK_000_D_0_ 3 -1 2 6 0 1 3 5 6 7 -1 -1 1 0 21 + 313 CLK_000_D_1_ 3 -1 7 6 0 1 3 5 6 7 -1 -1 1 0 21 + 310 inst_RESET_OUT 3 -1 6 5 0 3 4 6 7 -1 -1 2 0 21 + 300 inst_AS_030_000_SYNC 3 -1 5 3 0 3 5 -1 -1 7 0 21 + 302 inst_AS_000_DMA 3 -1 2 3 2 3 7 -1 -1 6 0 21 + 345 SM_AMIGA_i_7_ 3 -1 0 3 0 5 7 -1 -1 3 1 21 + 332 SM_AMIGA_0_ 3 -1 5 3 0 5 7 -1 -1 3 0 21 + 330 SM_AMIGA_6_ 3 -1 0 3 0 6 7 -1 -1 3 0 21 + 346 CLK_OUT_INTreg 3 -1 6 3 1 2 6 -1 -1 1 0 21 + 305 inst_CLK_OUT_PRE_D 3 -1 6 3 1 2 6 -1 -1 1 0 21 + 301 inst_BGACK_030_INT_D 3 -1 4 3 5 6 7 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 7 3 3 4 5 -1 -1 1 0 21 + 303 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 + 344 SM_AMIGA_2_ 3 -1 3 2 1 3 -1 -1 5 0 21 + 339 inst_DSACK1_INT 3 -1 1 2 1 7 -1 -1 5 0 21 + 333 CYCLE_DMA_0_ 3 -1 0 2 0 2 -1 -1 4 0 21 + 295 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 21 + 293 cpu_est_3_ 3 -1 3 2 3 6 -1 -1 4 0 21 + 342 SM_AMIGA_5_ 3 -1 7 2 0 7 -1 -1 3 0 21 + 341 SM_AMIGA_1_ 3 -1 1 2 1 5 -1 -1 3 0 21 + 331 SM_AMIGA_4_ 3 -1 0 2 0 3 -1 -1 3 0 21 + 328 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21 + 327 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 + 294 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 3 0 21 + 340 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21 + 334 CYCLE_DMA_1_ 3 -1 0 2 0 2 -1 -1 2 0 21 + 329 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 2 3 5 -1 -1 2 0 21 + 315 inst_CLK_OUT_PRE_50 3 -1 5 2 5 6 -1 -1 1 0 21 + 306 CLK_000_D_3_ 3 -1 1 2 0 5 -1 -1 1 0 21 + 296 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 1 1 21 + 355 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 353 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 349 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 335 CLK_030_PE_0_ 3 -1 2 1 2 -1 -1 9 0 21 + 311 CLK_030_PE_1_ 3 -1 2 1 2 -1 -1 6 0 21 + 343 SM_AMIGA_3_ 3 -1 3 1 3 -1 -1 5 0 21 + 350 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 336 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 + 358 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 + 356 RN_VMA 3 34 3 1 3 34 -1 3 0 21 + 351 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 348 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 + 357 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 352 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 347 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 338 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 + 337 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 + 312 inst_AMIGA_DS 3 -1 7 1 2 -1 -1 2 0 21 + 326 CLK_000_D_12_ 3 -1 1 1 1 -1 -1 1 0 21 + 325 CLK_000_D_9_ 3 -1 5 1 2 -1 -1 1 0 21 + 324 CLK_000_D_8_ 3 -1 2 1 5 -1 -1 1 0 21 + 323 CLK_000_D_7_ 3 -1 1 1 2 -1 -1 1 0 21 + 322 CLK_000_D_6_ 3 -1 6 1 1 -1 -1 1 0 21 + 321 CLK_000_D_5_ 3 -1 0 1 6 -1 -1 1 0 21 + 320 CLK_000_D_4_ 3 -1 5 1 0 -1 -1 1 0 21 + 319 CLK_000_D_2_ 3 -1 7 1 1 -1 -1 1 0 21 + 318 IPL_D0_2_ 3 -1 5 1 1 -1 -1 1 0 21 + 317 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 316 IPL_D0_0_ 3 -1 5 1 1 -1 -1 1 0 21 + 309 inst_DTACK_D0 3 -1 2 1 3 -1 -1 1 0 21 + 308 CLK_000_D_11_ 3 -1 1 1 1 -1 -1 1 0 21 + 307 CLK_000_D_10_ 3 -1 2 1 1 -1 -1 1 0 21 + 304 inst_VPA_D 3 -1 3 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 + 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 5 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 5 66 -1 + 63 CLK_030 1 -1 -1 2 1 2 63 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 2 RESET 1 -1 -1 2 1 2 2 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 59 A_1_ 1 -1 -1 1 5 59 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 3 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 2 10 -1 +126 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 -1 7 6 0 2 3 4 5 7 81 -1 1 0 21 + 41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21 + 79 RW_000 5 349 7 3 2 4 6 79 -1 4 0 21 + 70 RW 5 356 6 2 0 7 70 -1 2 0 21 + 31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21 + 78 SIZE_1_ 5 347 7 1 3 78 -1 3 0 21 + 69 SIZE_0_ 5 357 6 1 3 69 -1 3 0 21 + 68 A_0_ 5 350 6 1 3 68 -1 3 0 21 + 40 BERR 5 -1 4 1 0 40 -1 1 0 21 + 29 DTACK 5 -1 3 1 2 29 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 348 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 353 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 351 1 0 6 -1 10 0 21 + 82 BGACK_030 5 354 7 0 82 -1 3 0 21 + 34 VMA 5 355 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 352 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 80 DSACK1 0 7 0 80 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 354 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 314 CLK_000_D_0_ 3 -1 6 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21 + 313 CLK_000_D_1_ 3 -1 4 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 310 inst_RESET_OUT 3 -1 5 6 0 3 4 5 6 7 -1 -1 2 0 21 + 329 SM_AMIGA_6_ 3 -1 1 4 0 1 3 7 -1 -1 3 0 21 + 300 inst_AS_030_000_SYNC 3 -1 5 3 1 3 5 -1 -1 7 0 21 + 302 inst_AS_000_DMA 3 -1 2 3 2 3 7 -1 -1 6 0 21 + 295 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 + 293 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 + 344 SM_AMIGA_i_7_ 3 -1 1 3 1 5 7 -1 -1 3 1 21 + 340 SM_AMIGA_1_ 3 -1 6 3 2 6 7 -1 -1 3 0 21 + 345 CLK_OUT_INTreg 3 -1 6 3 1 2 6 -1 -1 1 0 21 + 301 inst_BGACK_030_INT_D 3 -1 7 3 5 6 7 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 7 3 3 4 5 -1 -1 1 0 21 + 296 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 + 303 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 + 343 SM_AMIGA_2_ 3 -1 0 2 0 6 -1 -1 5 0 21 + 338 inst_DSACK1_INT 3 -1 2 2 2 7 -1 -1 5 0 21 + 332 CYCLE_DMA_0_ 3 -1 1 2 1 2 -1 -1 4 0 21 + 355 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 + 331 SM_AMIGA_0_ 3 -1 7 2 1 7 -1 -1 3 0 21 + 327 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21 + 294 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21 + 339 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21 + 333 CYCLE_DMA_1_ 3 -1 1 2 1 2 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 320 CLK_000_D_4_ 3 -1 5 2 0 1 -1 -1 1 0 21 + 315 inst_CLK_OUT_PRE_50 3 -1 0 2 0 1 -1 -1 1 0 21 + 308 CLK_000_D_10_ 3 -1 5 2 2 5 -1 -1 1 0 21 + 307 CLK_000_D_9_ 3 -1 2 2 2 5 -1 -1 1 0 21 + 306 CLK_000_D_3_ 3 -1 3 2 1 5 -1 -1 1 0 21 + 305 inst_CLK_OUT_PRE_D 3 -1 1 2 2 6 -1 -1 1 0 21 + 304 inst_VPA_D 3 -1 6 2 0 3 -1 -1 1 0 21 + 353 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 351 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 348 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 334 CLK_030_PE_0_ 3 -1 2 1 2 -1 -1 9 0 21 + 311 CLK_030_PE_1_ 3 -1 2 1 2 -1 -1 6 0 21 + 342 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 + 349 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 335 RST_DLY_0_ 3 -1 5 1 5 -1 -1 4 0 21 + 357 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 + 350 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 347 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 + 341 SM_AMIGA_5_ 3 -1 0 1 0 -1 -1 3 0 21 + 330 SM_AMIGA_4_ 3 -1 0 1 0 -1 -1 3 0 21 + 326 inst_LDS_000_INT 3 -1 3 1 3 -1 -1 3 0 21 + 356 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 352 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 346 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 337 RST_DLY_2_ 3 -1 5 1 5 -1 -1 2 0 21 + 336 RST_DLY_1_ 3 -1 5 1 5 -1 -1 2 1 21 + 328 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21 + 312 inst_AMIGA_DS 3 -1 7 1 2 -1 -1 2 0 21 + 325 CLK_000_D_11_ 3 -1 5 1 2 -1 -1 1 0 21 + 324 CLK_000_D_8_ 3 -1 6 1 2 -1 -1 1 0 21 + 323 CLK_000_D_7_ 3 -1 5 1 6 -1 -1 1 0 21 + 322 CLK_000_D_6_ 3 -1 6 1 5 -1 -1 1 0 21 + 321 CLK_000_D_5_ 3 -1 0 1 6 -1 -1 1 0 21 + 319 CLK_000_D_2_ 3 -1 7 1 3 -1 -1 1 0 21 + 318 IPL_D0_2_ 3 -1 5 1 1 -1 -1 1 0 21 + 317 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 316 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 + 309 inst_DTACK_D0 3 -1 2 1 0 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 5 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 2 RESET 1 -1 -1 2 1 2 2 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 63 CLK_030 1 -1 -1 1 2 63 -1 + 59 A_1_ 1 -1 -1 1 6 59 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 6 10 -1 +127 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 -1 7 7 0 1 3 4 5 6 7 81 -1 1 0 21 + 41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21 + 79 RW_000 5 350 7 3 2 4 6 79 -1 4 0 21 + 70 RW 5 357 6 2 0 7 70 -1 2 0 21 + 31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21 + 78 SIZE_1_ 5 348 7 1 0 78 -1 3 0 21 + 69 SIZE_0_ 5 358 6 1 0 69 -1 3 0 21 + 68 A_0_ 5 351 6 1 0 68 -1 3 0 21 + 40 BERR 5 -1 4 1 3 40 -1 1 0 21 + 29 DTACK 5 -1 3 1 2 29 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 349 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 355 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 353 1 0 6 -1 10 0 21 + 82 BGACK_030 5 354 7 0 82 -1 3 0 21 + 34 VMA 5 356 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 352 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 80 DSACK1 0 7 0 80 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 354 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 314 CLK_000_D_0_ 3 -1 2 6 0 1 3 5 6 7 -1 -1 1 0 21 + 313 CLK_000_D_1_ 3 -1 7 6 0 1 3 5 6 7 -1 -1 1 0 21 + 310 inst_RESET_OUT 3 -1 6 5 0 3 4 6 7 -1 -1 2 0 21 + 300 inst_AS_030_000_SYNC 3 -1 5 3 0 3 5 -1 -1 7 0 21 + 302 inst_AS_000_DMA 3 -1 2 3 2 3 7 -1 -1 6 0 21 + 345 SM_AMIGA_i_7_ 3 -1 0 3 0 5 7 -1 -1 3 1 21 + 332 SM_AMIGA_0_ 3 -1 5 3 0 5 7 -1 -1 3 0 21 + 330 SM_AMIGA_6_ 3 -1 0 3 0 6 7 -1 -1 3 0 21 + 346 CLK_OUT_INTreg 3 -1 6 3 1 2 6 -1 -1 1 0 21 + 305 inst_CLK_OUT_PRE_D 3 -1 6 3 1 2 6 -1 -1 1 0 21 + 301 inst_BGACK_030_INT_D 3 -1 4 3 5 6 7 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 7 3 3 4 5 -1 -1 1 0 21 + 303 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 + 344 SM_AMIGA_2_ 3 -1 3 2 1 3 -1 -1 5 0 21 + 339 inst_DSACK1_INT 3 -1 1 2 1 7 -1 -1 5 0 21 + 333 CYCLE_DMA_0_ 3 -1 0 2 0 2 -1 -1 4 0 21 + 295 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 21 + 293 cpu_est_3_ 3 -1 3 2 3 6 -1 -1 4 0 21 + 342 SM_AMIGA_5_ 3 -1 7 2 0 7 -1 -1 3 0 21 + 341 SM_AMIGA_1_ 3 -1 1 2 1 5 -1 -1 3 0 21 + 331 SM_AMIGA_4_ 3 -1 0 2 0 3 -1 -1 3 0 21 + 328 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21 + 327 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 + 294 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 3 0 21 + 340 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21 + 334 CYCLE_DMA_1_ 3 -1 0 2 0 2 -1 -1 2 0 21 + 329 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 2 3 5 -1 -1 2 0 21 + 315 inst_CLK_OUT_PRE_50 3 -1 5 2 5 6 -1 -1 1 0 21 + 306 CLK_000_D_3_ 3 -1 1 2 0 5 -1 -1 1 0 21 + 296 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 1 1 21 + 355 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 353 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 349 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 335 CLK_030_PE_0_ 3 -1 2 1 2 -1 -1 9 0 21 + 311 CLK_030_PE_1_ 3 -1 2 1 2 -1 -1 6 0 21 + 343 SM_AMIGA_3_ 3 -1 3 1 3 -1 -1 5 0 21 + 350 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 336 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 + 358 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 + 356 RN_VMA 3 34 3 1 3 34 -1 3 0 21 + 351 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 348 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 + 357 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 352 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 347 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 338 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 + 337 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 + 312 inst_AMIGA_DS 3 -1 7 1 2 -1 -1 2 0 21 + 326 CLK_000_D_12_ 3 -1 1 1 1 -1 -1 1 0 21 + 325 CLK_000_D_9_ 3 -1 5 1 2 -1 -1 1 0 21 + 324 CLK_000_D_8_ 3 -1 2 1 5 -1 -1 1 0 21 + 323 CLK_000_D_7_ 3 -1 1 1 2 -1 -1 1 0 21 + 322 CLK_000_D_6_ 3 -1 6 1 1 -1 -1 1 0 21 + 321 CLK_000_D_5_ 3 -1 0 1 6 -1 -1 1 0 21 + 320 CLK_000_D_4_ 3 -1 5 1 0 -1 -1 1 0 21 + 319 CLK_000_D_2_ 3 -1 7 1 1 -1 -1 1 0 21 + 318 IPL_D0_2_ 3 -1 5 1 1 -1 -1 1 0 21 + 317 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 316 IPL_D0_0_ 3 -1 5 1 1 -1 -1 1 0 21 + 309 inst_DTACK_D0 3 -1 2 1 3 -1 -1 1 0 21 + 308 CLK_000_D_11_ 3 -1 1 1 1 -1 -1 1 0 21 + 307 CLK_000_D_10_ 3 -1 2 1 1 -1 -1 1 0 21 + 304 inst_VPA_D 3 -1 3 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 + 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 5 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 5 66 -1 + 63 CLK_030 1 -1 -1 2 1 2 63 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 2 RESET 1 -1 -1 2 1 2 2 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 59 A_1_ 1 -1 -1 1 5 59 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 3 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 2 10 -1 +119 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 -1 7 6 0 1 2 3 4 7 81 -1 1 0 21 + 79 RW_000 5 345 7 3 0 4 6 79 -1 4 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 31 UDS_000 5 -1 3 3 2 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 2 6 7 30 -1 1 0 21 + 70 RW 5 350 6 2 2 7 70 -1 2 0 21 + 78 SIZE_1_ 5 341 7 1 5 78 -1 3 0 21 + 69 SIZE_0_ 5 348 6 1 5 69 -1 3 0 21 + 68 A_0_ 5 340 6 1 5 68 -1 3 0 21 + 40 BERR 5 -1 4 1 2 40 -1 1 0 21 + 29 DTACK 5 -1 3 1 1 29 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 344 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 343 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 342 1 0 6 -1 10 0 21 + 82 BGACK_030 5 347 7 0 82 -1 3 0 21 + 34 VMA 5 349 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 346 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 80 DSACK1 0 7 0 80 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 347 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 311 CLK_000_D_0_ 3 -1 3 6 0 2 3 5 6 7 -1 -1 1 0 21 + 310 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 + 307 inst_RESET_OUT 3 -1 6 5 0 3 4 6 7 -1 -1 2 0 21 + 322 SM_AMIGA_6_ 3 -1 5 4 2 5 6 7 -1 -1 3 0 21 + 301 inst_BGACK_030_INT_D 3 -1 7 4 1 5 6 7 -1 -1 1 0 21 + 300 inst_AS_030_000_SYNC 3 -1 1 3 1 3 5 -1 -1 7 0 21 + 302 inst_AS_000_DMA 3 -1 0 3 0 3 7 -1 -1 6 0 21 + 295 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 + 293 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 + 337 SM_AMIGA_i_7_ 3 -1 5 3 1 5 7 -1 -1 3 1 21 + 325 SM_AMIGA_0_ 3 -1 0 3 0 5 7 -1 -1 3 0 21 + 296 cpu_est_0_ 3 -1 6 3 2 3 6 -1 -1 3 0 21 + 338 CLK_OUT_INTreg 3 -1 3 3 0 1 6 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 7 3 1 3 4 -1 -1 1 0 21 + 294 cpu_est_2_ 3 -1 3 3 2 3 6 -1 -1 1 1 21 + 336 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 5 0 21 + 349 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 + 334 SM_AMIGA_5_ 3 -1 6 2 0 6 -1 -1 3 0 21 + 324 SM_AMIGA_1_ 3 -1 5 2 0 5 -1 -1 3 0 21 + 323 SM_AMIGA_4_ 3 -1 0 2 0 2 -1 -1 3 0 21 + 320 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 + 319 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 + 333 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 332 inst_DSACK1_INT 3 -1 0 2 0 7 -1 -1 2 0 21 + 321 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 2 3 5 -1 -1 2 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 4 2 0 3 -1 -1 1 0 21 + 312 inst_CLK_OUT_PRE_50 3 -1 6 2 4 6 -1 -1 1 0 21 + 305 CLK_000_D_3_ 3 -1 5 2 2 5 -1 -1 1 0 21 + 304 inst_VPA_D 3 -1 5 2 2 3 -1 -1 1 0 21 + 344 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 343 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 342 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 328 CLK_030_PE_0_ 3 -1 0 1 0 -1 -1 9 0 21 + 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 308 CLK_030_PE_1_ 3 -1 0 1 0 -1 -1 6 0 21 + 335 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 + 345 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 329 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 + 326 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 4 0 21 + 348 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 + 341 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 + 340 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 350 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 346 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 339 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 331 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 + 330 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 + 327 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 2 0 21 + 309 inst_AMIGA_DS 3 -1 2 1 0 -1 -1 2 0 21 + 318 CLK_000_D_4_ 3 -1 2 1 5 -1 -1 1 0 21 + 317 CLK_000_D_2_ 3 -1 7 1 5 -1 -1 1 0 21 + 316 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 315 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 314 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 306 inst_DTACK_D0 3 -1 1 1 2 -1 -1 1 0 21 60 CLK_OSZI 9 -1 0 60 -1 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 diff --git a/Logic/68030_tk.plc b/Logic/68030_tk.plc index 1b8e1cf..1d59f16 100644 --- a/Logic/68030_tk.plc +++ b/Logic/68030_tk.plc @@ -8,7 +8,7 @@ ; Source file 68030_tk.tt4 ; FITTER-generated Placements. ; DEVICE mach447a -; DATE Fri Nov 18 19:32:41 2016 +; DATE Thu Dec 29 16:02:00 2016 Pin 4 AHIGH_31_ Comb ; S6=1 S9=1 Pair 143 diff --git a/Logic/68030_tk.prd b/Logic/68030_tk.prd index 1f40fbf..1bcad98 100644 --- a/Logic/68030_tk.prd +++ b/Logic/68030_tk.prd @@ -5,8 +5,8 @@ |--------------------------------------------| -Start: Fri Nov 18 19:32:40 2016 -End : Fri Nov 18 19:32:41 2016 $$$ Elapsed time: 00:00:01 +Start: Thu Dec 29 16:02:00 2016 +End : Thu Dec 29 16:02:00 2016 $$$ Elapsed time: 00:00:00 =========================================================================== Part [E:/ispLEVER_Classic2_0/ispcpld/dat/mach4a/mach447a] Design [68030_tk.tt4] diff --git a/Logic/68030_tk.rpt b/Logic/68030_tk.rpt index a40a29e..bd4efef 100644 --- a/Logic/68030_tk.rpt +++ b/Logic/68030_tk.rpt @@ -12,7 +12,7 @@ Project_Summary Project Name : 68030_tk Project Path : C:\Users\Matze\Amiga\Hardwarehacks\68030-TK\GitHub\Logic -Project Fitted on : Fri Nov 18 19:32:41 2016 +Project Fitted on : Thu Dec 29 16:02:00 2016 Device : M4A5-128/64 Package : 100TQFP diff --git a/Logic/68030_tk.tt2 b/Logic/68030_tk.tt2 index b99de3c..d37f5d5 100644 --- a/Logic/68030_tk.tt2 +++ b/Logic/68030_tk.tt2 @@ -1,5 +1,5 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Fri Nov 18 19:32:36 2016 +#$ DATE Thu Dec 29 16:01:56 2016 #$ MODULE 68030_tk #$ PINS 61 AHIGH_31_ IPL_1_ IPL_0_ A_DECODE_23_ FC_0_ A_1_ IPL_2_ FC_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS FPU_SENSE DSACK1 DTACK AVEC E AHIGH_30_ VPA AHIGH_29_ AHIGH_28_ RST AHIGH_27_ RESET AHIGH_26_ AHIGH_25_ AMIGA_ADDR_ENABLE AHIGH_24_ AMIGA_BUS_DATA_DIR A_DECODE_22_ AMIGA_BUS_ENABLE_LOW A_DECODE_21_ AMIGA_BUS_ENABLE_HIGH A_DECODE_20_ CIIN A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ A_0_ SIZE_1_ IPL_030_1_ IPL_030_0_ IPL_030_2_ RW_000 BG_000 BGACK_030 SIZE_0_ VMA RW #$ NODES 46 cpu_est_1_ cpu_est_2_ cpu_est_3_ cpu_est_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA inst_VPA_D CLK_000_D_3_ inst_DTACK_D0 inst_RESET_OUT CLK_030_PE_1_ inst_AMIGA_DS CLK_000_D_1_ CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_D IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ CLK_000_D_4_ inst_LDS_000_INT inst_DS_000_ENABLE inst_UDS_000_INT SM_AMIGA_6_ SM_AMIGA_4_ SM_AMIGA_1_ SM_AMIGA_0_ CYCLE_DMA_0_ CYCLE_DMA_1_ CLK_030_PE_0_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ inst_DSACK1_INT inst_AS_000_INT SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ CLK_OUT_INTreg diff --git a/Logic/68030_tk.tt3 b/Logic/68030_tk.tt3 index 9fa727a..9cfabe9 100644 --- a/Logic/68030_tk.tt3 +++ b/Logic/68030_tk.tt3 @@ -1,5 +1,5 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Fri Nov 18 19:32:36 2016 +#$ DATE Thu Dec 29 16:01:56 2016 #$ MODULE 68030_tk #$ PINS 61 AHIGH_31_ IPL_1_ IPL_0_ A_DECODE_23_ FC_0_ A_1_ IPL_2_ FC_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS FPU_SENSE DSACK1 DTACK AVEC E AHIGH_30_ VPA AHIGH_29_ AHIGH_28_ RST AHIGH_27_ RESET AHIGH_26_ AHIGH_25_ AMIGA_ADDR_ENABLE AHIGH_24_ AMIGA_BUS_DATA_DIR A_DECODE_22_ AMIGA_BUS_ENABLE_LOW A_DECODE_21_ AMIGA_BUS_ENABLE_HIGH A_DECODE_20_ CIIN A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ A_0_ SIZE_1_ IPL_030_1_ IPL_030_0_ IPL_030_2_ RW_000 BG_000 BGACK_030 SIZE_0_ VMA RW #$ NODES 46 cpu_est_1_ cpu_est_2_ cpu_est_3_ cpu_est_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA inst_VPA_D CLK_000_D_3_ inst_DTACK_D0 inst_RESET_OUT CLK_030_PE_1_ inst_AMIGA_DS CLK_000_D_1_ CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_D IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ CLK_000_D_4_ inst_LDS_000_INT inst_DS_000_ENABLE inst_UDS_000_INT SM_AMIGA_6_ SM_AMIGA_4_ SM_AMIGA_1_ SM_AMIGA_0_ CYCLE_DMA_0_ CYCLE_DMA_1_ CLK_030_PE_0_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ inst_DSACK1_INT inst_AS_000_INT SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ CLK_OUT_INTreg diff --git a/Logic/68030_tk.tt4 b/Logic/68030_tk.tt4 index 5772bf2..33a84d8 100644 --- a/Logic/68030_tk.tt4 +++ b/Logic/68030_tk.tt4 @@ -1,5 +1,5 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Fri Nov 18 19:32:36 2016 +#$ DATE Thu Dec 29 16:01:56 2016 #$ MODULE BUS68030 #$ PINS 61 AHIGH_31_ IPL_1_ IPL_0_ A_DECODE_23_ FC_0_ A_1_ IPL_2_ FC_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 diff --git a/Logic/68030_tk.tte b/Logic/68030_tk.tte index 99a4f75..0cfc5a1 100644 --- a/Logic/68030_tk.tte +++ b/Logic/68030_tk.tte @@ -1,5 +1,5 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Fri Nov 18 19:32:36 2016 +#$ DATE Thu Dec 29 16:01:56 2016 #$ MODULE BUS68030 #$ PINS 61 AHIGH_31_ IPL_1_ IPL_0_ A_DECODE_23_ FC_0_ A_1_ IPL_2_ FC_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 diff --git a/Logic/68030_tk.vcl b/Logic/68030_tk.vcl index de660aa..b72a354 100644 --- a/Logic/68030_tk.vcl +++ b/Logic/68030_tk.vcl @@ -17,8 +17,8 @@ Parent = m4a5.lci; SDS_file = m4a5.sds; Design = 68030_tk.tt4; Rev = 0.01; -DATE = 11/18/16; -TIME = 19:32:40; +DATE = 12/29/16; +TIME = 16:02:00; Type = TT2; Pre_Fit_Time = 1; Source_Format = Pure_VHDL; diff --git a/Logic/68030_tk.vco b/Logic/68030_tk.vco index 6081306..05984ef 100644 --- a/Logic/68030_tk.vco +++ b/Logic/68030_tk.vco @@ -17,8 +17,8 @@ Parent = m4a5.lci; SDS_file = m4a5.sds; Design = 68030_tk.tt4; Rev = 0.01; -DATE = 11/18/16; -TIME = 19:32:41; +DATE = 12/29/16; +TIME = 16:02:00; Type = TT2; Pre_Fit_Time = 1; Source_Format = Pure_VHDL; diff --git a/Logic/68030_tk.xrf b/Logic/68030_tk.xrf index b3b5104..548fe7d 100644 --- a/Logic/68030_tk.xrf +++ b/Logic/68030_tk.xrf @@ -2,7 +2,7 @@ Signal Name Cross Reference File ispLEVER Classic 2.0.00.17.20.15 -Design '68030_tk' created Fri Nov 18 19:32:36 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100644 --- a/Logic/BUS68030.bl0 +++ b/Logic/BUS68030.bl0 @@ -1,4 +1,4 @@ -#$ DATE Fri Nov 18 19:32:36 2016 +#$ DATE Thu Dec 29 16:01:56 2016 #$ TOOL EDIF2BLIF version IspLever 1.0 #$ MODULE bus68030 #$ PINS 75 A_DECODE_2_ A_0_ SIZE_1_ IPL_030_1_ IPL_030_0_ AHIGH_31_ IPL_1_ IPL_0_ A_DECODE_23_ FC_0_ A_1_ IPL_030_2_ IPL_2_ FC_1_ AS_030 AS_000 RW_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS FPU_SENSE DSACK1 DTACK AVEC SIZE_0_ E AHIGH_30_ VPA AHIGH_29_ VMA AHIGH_28_ RST AHIGH_27_ RESET AHIGH_26_ RW AHIGH_25_ AMIGA_ADDR_ENABLE AHIGH_24_ AMIGA_BUS_DATA_DIR A_DECODE_22_ AMIGA_BUS_ENABLE_LOW A_DECODE_21_ AMIGA_BUS_ENABLE_HIGH A_DECODE_20_ CIIN A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ A_DECODE_15_ A_DECODE_14_ A_DECODE_13_ A_DECODE_12_ A_DECODE_11_ A_DECODE_10_ A_DECODE_9_ A_DECODE_8_ A_DECODE_7_ A_DECODE_6_ A_DECODE_5_ A_DECODE_4_ A_DECODE_3_ diff --git a/Logic/BUS68030.bl1 b/Logic/BUS68030.bl1 index 252ebe3..1860a37 100644 --- a/Logic/BUS68030.bl1 +++ b/Logic/BUS68030.bl1 @@ -1,5 +1,5 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Fri Nov 18 19:32:36 2016 +#$ DATE Thu Dec 29 16:01:56 2016 #$ MODULE bus68030 #$ PINS 75 A_DECODE_2_ A_0_ SIZE_1_ IPL_030_1_ IPL_030_0_ AHIGH_31_ IPL_1_ IPL_0_ \ # A_DECODE_23_ FC_0_ A_1_ IPL_030_2_ IPL_2_ FC_1_ AS_030 AS_000 RW_000 DS_030 UDS_000 \ diff --git a/Logic/BUS68030.edi b/Logic/BUS68030.edi index 6b9ddf5..64d4f60 100644 --- a/Logic/BUS68030.edi +++ b/Logic/BUS68030.edi @@ -4,7 +4,7 @@ (keywordMap (keywordLevel 0)) (status (written - (timeStamp 2016 11 18 19 32 31) + (timeStamp 2016 12 29 16 1 51) (author "Synopsys, Inc.") (program "Synplify Pro" (version "I-2014.03LC , mapper maplat, Build 923R")) ) diff --git a/Logic/BUS68030.prj b/Logic/BUS68030.prj index fdec7cd..3c00fbe 100644 --- a/Logic/BUS68030.prj +++ b/Logic/BUS68030.prj @@ -1,6 +1,6 @@ #-- Lattice Semiconductor Corporation Ltd. #-- Synplify OEM project file c:/users/matze/amiga/hardwarehacks/68030-tk/github/logic\BUS68030.prj -#-- Written on Fri Nov 18 19:32:22 2016 +#-- Written on Thu Dec 29 16:01:42 2016 #device options diff --git a/Logic/BUS68030.srm b/Logic/BUS68030.srm index 0f1cf90..bd62af7 100644 --- a/Logic/BUS68030.srm +++ b/Logic/BUS68030.srm @@ -188,8 +188,8 @@ RNP3ONsEDVHC;R( RNP38lFkVDCHRDC(N; P#R3$VM_lRNb"sIF "R\B\:\ks#C#l\\NC0x\l\NH\oN\sEN8sINCOEN \#\ndUjj -0\H\o0LEk\F\Do\HO\jnUdnj-Ujjj-#Lk38PE\M"\"N; POR3DMCNk#b_0.Cb_l0HC3Rjj.d46;jj -RNP3CODNbMk_C#0b04_HRlCjj3jjjjj;P -NR03#lH0D#H00ljCR36j4nj.6;P +RNP3CODNbMk_C#0b04_HRlCj43j66n.jN; +P#R30Dl0H0#0HRlCjj3jjjjj;P NRHFsoM_H#F0_VAR"zU1nj"dj;P NRs3FHNohl"CRAnz1Ujjd"N; P#R3$lM_#_s##HC08;Rj @@ -202,7 +202,7 @@ j;}N; P$R#M#_HlCHG8MDNo;R4 RNP3M#$_#lV_FoskHb_8;Rj RNP3M#$_lMkOsEN#4RU4 -.;N3PR#_$MD HMC8sHRj"{jnn(n-UUnjjj-Ucnwj-qnBj-c6j6gd Ag}(d"N; +.;N3PR#_$MD HMC8sHR6"{jBw.7- qgcg6-(cg g-q 7j-(A476g(dd}Bc"N; POR38#L_NRPC{P NRM#$_VsCCMsCOOC_D FORN{ P$R1#l0CRN{ diff --git a/Logic/BUS68030.srr b/Logic/BUS68030.srr index ab5582c..d27def8 100644 --- a/Logic/BUS68030.srr +++ b/Logic/BUS68030.srr @@ -6,7 +6,7 @@ #Implementation: logic $ Start of Compile -#Fri Nov 18 19:32:29 2016 +#Thu Dec 29 16:01:49 2016 Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014 @N|Running in 64-bit mode @@ -49,7 +49,7 @@ State machine has 8 reachable states with original encodings of: At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Fri Nov 18 19:32:29 2016 +# Thu Dec 29 16:01:49 2016 ###########################################################] Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014 @@ -59,7 +59,7 @@ File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\synwork\BUS68030_c At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Fri Nov 18 19:32:31 2016 +# Thu Dec 29 16:01:50 2016 ###########################################################] Map & Optimize Report @@ -101,6 +101,6 @@ Mapper successful! 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zeO=o}QCTjHb*zXJOnmyKGt8553+$aV#deu(!lkUp>-=2F53XbiEGd_LSsU}UFJrG! z{^0p-M`9sUe1hyUUb01;F1lTUd|p)$^}!xU~K46ob^;%3(m|^ENB5 zy`@*k*lwQfYj{I9AigNe{ya8VK5KM)sJ?!F$mgWrX&B)EooSXo7*J^^(>d3F@f z`Cco=rgRn>$;U)hU9UXvw65*wc-v7;+f~;~*Hqg@c^a=dk$=+xim~!ok6H0vb?aP{ zy;|Ps9YGx|h|iqJ;YDh0sCUq9dQzkR)m;}=XYpqHQ_Yt$WIAL*bkcN}I2R}^PA4R9fifc5IVzutl zPTf16Dcy^qJa3`6ui}x{qnNk+Je4u5m=7OHa(R|!mTynKtL!!K6Ld$H+QhthGDlQsN*krr zCLyxq%wi3z2V%leNb{J^2FubwJsWL-Sc78JS3>)G>*A#b4+;; zqh_9Ug`@U+ilNh{IIlD64*pMBUl3(Qmvh1hiCj5i4LY9?e z4v!PrE)u(l+a-$bld>YdDa*p8PilF<Y-Hs{jDO6ke$S diff --git a/Logic/Programming.xcf b/Logic/Programming.xcf index 308e284..af14317 100644 --- a/Logic/Programming.xcf +++ b/Logic/Programming.xcf @@ -1,6 +1,6 @@ - + JTAG @@ -19,14 +19,15 @@ 0 C:\Users\Matze\Amiga\Hardwarehacks\68030-TK\GitHub\Logic\68030_tk.jed - 10/15/16 23:48:29 - 0x1315 + 12/29/16 15:52:11 + 0x82ED Erase,Program,Verify diff --git a/Logic/bus68030.exf b/Logic/bus68030.exf index faad6e2..73a2373 100644 --- a/Logic/bus68030.exf +++ b/Logic/bus68030.exf @@ -54,7 +54,7 @@ Section Member Rename Array-Notation Array Number Port FC_0_ FC[0] 3 1 End Section Cross Reference File -Design 'BUS68030' created Fri Nov 18 19:32:36 2016 +Design 'BUS68030' created Thu Dec 29 16:01:56 2016 Type New Name Original Name // ---------------------------------------------------------------------- Inst i_z3939 AS_030 diff --git a/Logic/bus68030.srf b/Logic/bus68030.srf index 9617cc4..d27def8 100644 --- a/Logic/bus68030.srf +++ b/Logic/bus68030.srf @@ -6,7 +6,7 @@ #Implementation: logic $ Start of Compile -#Fri Nov 18 19:32:29 2016 +#Thu Dec 29 16:01:49 2016 Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014 @N|Running in 64-bit mode @@ -49,7 +49,7 @@ State machine has 8 reachable states with original encodings of: At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Fri Nov 18 19:32:29 2016 +# Thu Dec 29 16:01:49 2016 ###########################################################] Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014 @@ -59,6 +59,48 @@ File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\synwork\BUS68030_c At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Fri Nov 18 19:32:31 2016 +# Thu Dec 29 16:01:50 2016 + +###########################################################] +Map & Optimize Report + +Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014 +Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited. +Product Version I-2014.03LC +@N: MF248 |Running in 64-bit mode. +@N:"c:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":132:38:132:40|Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0] +Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral)) +original code -> new code + 000 -> 00000000 + 001 -> 00000011 + 010 -> 00000101 + 011 -> 00001001 + 100 -> 00010001 + 101 -> 00100001 + 110 -> 01000001 + 111 -> 10000001 +--------------------------------------- +Resource Usage Report + +Simple gate primitives: +DFF 57 uses +BI_DIR 19 uses +BUFTH 3 uses +IBUF 38 uses +OBUF 15 uses +AND2 277 uses +INV 236 uses +OR2 23 uses +XOR2 8 uses + + +@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis. +I-2014.03LC +Mapper successful! + +At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Thu Dec 29 16:01:51 2016 ###########################################################] diff --git a/Logic/dm/BUS68030_comp.xdm b/Logic/dm/BUS68030_comp.xdm index 88e9350..4faa0ad 100644 --- a/Logic/dm/BUS68030_comp.xdm +++ b/Logic/dm/BUS68030_comp.xdm @@ -27,8 +27,8 @@ SRSqS SRSqSSqSSqSS +/>SqSSqSS S SR"/ /S<7>CV diff --git a/Logic/run_options.txt b/Logic/run_options.txt index 9a62b56..979996b 100644 --- a/Logic/run_options.txt +++ b/Logic/run_options.txt @@ -1,7 +1,7 @@ #-- Synopsys, Inc. #-- Version I-2014.03LC #-- Project file C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\run_options.txt -#-- Written on Fri Nov 18 19:32:29 2016 +#-- Written on Thu Dec 29 16:01:49 2016 #project files diff --git a/Logic/synlog/BUS68030_multi_srs_gen.srr b/Logic/synlog/BUS68030_multi_srs_gen.srr index 6d3db1a..5e2a06a 100644 --- a/Logic/synlog/BUS68030_multi_srs_gen.srr +++ b/Logic/synlog/BUS68030_multi_srs_gen.srr @@ -5,6 +5,6 @@ File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\synwork\BUS68030_c At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Fri Nov 18 19:32:31 2016 +# Thu Dec 29 16:01:50 2016 ###########################################################] diff --git a/Logic/synlog/bus68030_fpga_mapper.srr b/Logic/synlog/bus68030_fpga_mapper.srr index 2150646..676291d 100644 --- a/Logic/synlog/bus68030_fpga_mapper.srr +++ b/Logic/synlog/bus68030_fpga_mapper.srr @@ -35,6 +35,6 @@ Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Fri Nov 18 19:32:31 2016 +# Thu Dec 29 16:01:51 2016 ###########################################################] diff --git a/Logic/synlog/report/BUS68030_compiler_runstatus.xml b/Logic/synlog/report/BUS68030_compiler_runstatus.xml index 5a8289a..3e1ea28 100644 --- a/Logic/synlog/report/BUS68030_compiler_runstatus.xml +++ b/Logic/synlog/report/BUS68030_compiler_runstatus.xml @@ -35,7 +35,7 @@ The file contains the job information from compiler to be displayed as part of t - - 1479493949 + 1483023709 \ No newline at end of file diff --git a/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml b/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml index 0ee4b71..e9316ba 100644 --- a/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml +++ b/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml @@ -40,7 +40,7 @@ The file contains the job information from mapper to be displayed as part of the 105MB -1479493951 +1483023711 diff --git a/Logic/syntmp/BUS68030_srr.htm b/Logic/syntmp/BUS68030_srr.htm index 226641d..f7ce836 100644 --- a/Logic/syntmp/BUS68030_srr.htm +++ b/Logic/syntmp/BUS68030_srr.htm @@ -1,5 +1,5 @@ 

-
+
 #Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014
 #install: E:\ispLEVER_Classic2_0\synpbase
 #OS: Windows 7 6.2
@@ -8,32 +8,32 @@
 #Implementation: logic
 
 $ Start of Compile
-#Fri Nov 18 19:32:29 2016
+#Thu Dec 29 16:01:49 2016
 
 Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
-@N: :  | Running in 64-bit mode 
+@N: :  | Running in 64-bit mode 
 Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
 
-@N:CD720 : std.vhd(123) | Setting time resolution to ns
-@N: : 68030-68000-bus.vhd(13) | Top entity is set to BUS68030.
+@N:CD720 : std.vhd(123) | Setting time resolution to ns
+@N: : 68030-68000-bus.vhd(13) | Top entity is set to BUS68030.
 File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd changed - recompiling
 VHDL syntax check successful!
 File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd changed - recompiling
-@N:CD630 : 68030-68000-bus.vhd(13) | Synthesizing work.bus68030.behavioral 
-@N:CD233 : 68030-68000-bus.vhd(70) | Using sequential encoding for type sm_e
-@N:CD233 : 68030-68000-bus.vhd(87) | Using sequential encoding for type sm_68000
-@W:CD638 : 68030-68000-bus.vhd(129) | Signal clk_out_pre is undriven 
-@W:CD638 : 68030-68000-bus.vhd(133) | Signal clk_030_h is undriven 
+@N:CD630 : 68030-68000-bus.vhd(13) | Synthesizing work.bus68030.behavioral 
+@N:CD233 : 68030-68000-bus.vhd(70) | Using sequential encoding for type sm_e
+@N:CD233 : 68030-68000-bus.vhd(87) | Using sequential encoding for type sm_68000
+@W:CD638 : 68030-68000-bus.vhd(129) | Signal clk_out_pre is undriven 
+@W:CD638 : 68030-68000-bus.vhd(133) | Signal clk_030_h is undriven 
 Post processing for work.bus68030.behavioral
-@W:CL169 : 68030-68000-bus.vhd(132) | Pruning register AS_000_D0_3  
-@W:CL169 : 68030-68000-bus.vhd(132) | Pruning register DS_030_D0_3  
-@W:CL169 : 68030-68000-bus.vhd(132) | Pruning register nEXP_SPACE_D0_3  
-@W:CL169 : 68030-68000-bus.vhd(132) | Pruning register BGACK_030_INT_PRE_2  
-@W:CL169 : 68030-68000-bus.vhd(131) | Pruning register CLK_OUT_EXP_INT_1  
-@W:CL169 : 68030-68000-bus.vhd(127) | Pruning register CLK_OUT_PRE_25_3  
-@W:CL169 : 68030-68000-bus.vhd(156) | Pruning register CLK_030_D0_2  
-@W:CL271 : 68030-68000-bus.vhd(132) | Pruning bits 12 to 5 of CLK_000_D_3(12 downto 0) -- not in use ... 
-@N:CL201 : 68030-68000-bus.vhd(132) | Trying to extract state machine for register SM_AMIGA
+@W:CL169 : 68030-68000-bus.vhd(132) | Pruning register AS_000_D0_3  
+@W:CL169 : 68030-68000-bus.vhd(132) | Pruning register DS_030_D0_3  
+@W:CL169 : 68030-68000-bus.vhd(132) | Pruning register nEXP_SPACE_D0_3  
+@W:CL169 : 68030-68000-bus.vhd(132) | Pruning register BGACK_030_INT_PRE_2  
+@W:CL169 : 68030-68000-bus.vhd(131) | Pruning register CLK_OUT_EXP_INT_1  
+@W:CL169 : 68030-68000-bus.vhd(127) | Pruning register CLK_OUT_PRE_25_3  
+@W:CL169 : 68030-68000-bus.vhd(156) | Pruning register CLK_030_D0_2  
+@W:CL271 : 68030-68000-bus.vhd(132) | Pruning bits 12 to 5 of CLK_000_D_3(12 downto 0) -- not in use ... 
+@N:CL201 : 68030-68000-bus.vhd(132) | Trying to extract state machine for register SM_AMIGA
 Extracted state machine for register SM_AMIGA
 State machine has 8 reachable states with original encodings of:
    000
@@ -44,24 +44,24 @@ State machine has 8 reachable states with original encodings of:
    101
    110
    111
-@N:CL201 : 68030-68000-bus.vhd(132) | Trying to extract state machine for register cpu_est
-@W:CL246 : 68030-68000-bus.vhd(24) | Input port bits 15 to 2 of a_decode(23 downto 2) are unused 
+@N:CL201 : 68030-68000-bus.vhd(132) | Trying to extract state machine for register cpu_est
+@W:CL246 : 68030-68000-bus.vhd(24) | Input port bits 15 to 2 of a_decode(23 downto 2) are unused 
 @END
 
 At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Fri Nov 18 19:32:29 2016
+# Thu Dec 29 16:01:49 2016
 
 ###########################################################]
 Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
-@N: :  | Running in 64-bit mode 
+@N: :  | Running in 64-bit mode 
 File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\synwork\BUS68030_comp.srs changed - recompiling
 
 At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Fri Nov 18 19:32:31 2016
+# Thu Dec 29 16:01:50 2016
 
 ###########################################################]
 Map & Optimize Report
@@ -69,8 +69,8 @@ Map & Optimize Report
 Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May  6 2014
 Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
 Product Version I-2014.03LC 
-@N:MF248 :  | Running in 64-bit mode. 
-@N: : 68030-68000-bus.vhd(132) | Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
+@N:MF248 :  | Running in 64-bit mode. 
+@N: : 68030-68000-bus.vhd(132) | Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
 Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
 original code -> new code
    000 -> 00000000
@@ -96,14 +96,14 @@ OR2             23 uses
 XOR2            8 uses
 
 
-@N:FC100 :  | Timing Report not generated for this device, please use place and route tools for timing analysis. 
+@N:FC100 :  | Timing Report not generated for this device, please use place and route tools for timing analysis. 
 I-2014.03LC 
 Mapper successful!
 
 At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Fri Nov 18 19:32:31 2016
+# Thu Dec 29 16:01:51 2016
 
 ###########################################################]
 
diff --git a/Logic/syntmp/BUS68030_toc.htm b/Logic/syntmp/BUS68030_toc.htm
index a55eb31..d33688c 100644
--- a/Logic/syntmp/BUS68030_toc.htm
+++ b/Logic/syntmp/BUS68030_toc.htm
@@ -16,7 +16,7 @@
 
  • Mapper Report  
 
    • 
-
  • Session Log (19:32 18-Nov)  
+
  • Session Log (16:01 29-Dec)  
 
      •          
         
    
diff --git a/Logic/syntmp/run_option.xml b/Logic/syntmp/run_option.xml
index 6336888..a6aaffc 100644
--- a/Logic/syntmp/run_option.xml
+++ b/Logic/syntmp/run_option.xml
@@ -3,7 +3,7 @@
   Synopsys, Inc.
   Version I-2014.03LC 
   Project file C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\syntmp\run_option.xml
-  Written on Fri Nov 18 19:32:29 2016
+  Written on Thu Dec 29 16:01:49 2016
 
 
 --> 
diff --git a/Logic/syntmp/statusReport.html b/Logic/syntmp/statusReport.html
index a84036a..ac2d20b 100644
--- a/Logic/syntmp/statusReport.html
+++ b/Logic/syntmp/statusReport.html
@@ -38,7 +38,7 @@
 -
 0m:00s
 -
-18.11.2016
      19:32:29
+29.12.2016
      16:01:49
  
 
  
@@ -49,12 +49,12 @@
 0m:00s
 0m:00s
 105MB
-18.11.2016
      19:32:31
+29.12.2016
      16:01:51
  
 
 
   Multi-srs Generator
-  Complete0m:01s18.11.2016
      19:32:31 		
+  Complete0m:01s29.12.2016
      16:01:50 		
      
   
  
\ No newline at end of file
diff --git a/Logic/synwork/BUS68030_comp.fdep b/Logic/synwork/BUS68030_comp.fdep
index 74cf7b2..3048e9d 100644
--- a/Logic/synwork/BUS68030_comp.fdep
+++ b/Logic/synwork/BUS68030_comp.fdep
@@ -9,7 +9,7 @@
 #CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\umr_capim.vhd":1401220368
 #CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\arith.vhd":1401220122
 #CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\unsigned.vhd":1401220122
-#CUR:"C:\\users\\matze\\amiga\\hardwarehacks\\68030-tk\\github\\logic\\68030-68000-bus.vhd":1479493940
+#CUR:"C:\\users\\matze\\amiga\\hardwarehacks\\68030-tk\\github\\logic\\68030-68000-bus.vhd":1483023695
 0 "C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd" vhdl
 
 # Dependency Lists (Uses list)
diff --git a/Logic/synwork/BUS68030_comp.fdeporig b/Logic/synwork/BUS68030_comp.fdeporig
index b732480..3ac167f 100644
--- a/Logic/synwork/BUS68030_comp.fdeporig
+++ b/Logic/synwork/BUS68030_comp.fdeporig
@@ -9,7 +9,7 @@
 #CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\umr_capim.vhd":1401220368
 #CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\arith.vhd":1401220122
 #CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\unsigned.vhd":1401220122
-#CUR:"C:\\users\\matze\\amiga\\hardwarehacks\\68030-tk\\github\\logic\\68030-68000-bus.vhd":1479493940
+#CUR:"C:\\users\\matze\\amiga\\hardwarehacks\\68030-tk\\github\\logic\\68030-68000-bus.vhd":1483023695
 0 "C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd" vhdl
 
 # Dependency Lists (Uses list)
diff --git a/Logic/synwork/BUS68030_comp.srs b/Logic/synwork/BUS68030_comp.srs
index c56c2243139cb2bdbc6fdee1dc4626cf375a6eb0..1789330fb4f4d7f14eee76eb73a3f90720ab4f34 100644
GIT binary patch
delta 681
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P1OhDx=Re)+Z+!p&SyxfW

diff --git a/Logic/synwork/BUS68030_mult.srs b/Logic/synwork/BUS68030_mult.srs
index 63c82f8d2da384e556e8c8dec01bc81035d244ca..bc001f98526cde0cf2376fb944c6beae9262de7f 100644
GIT binary patch
delta 11461
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diff --git a/Logic/synwork/BUS68030_mult_srs/skeleton.srs b/Logic/synwork/BUS68030_mult_srs/skeleton.srs
index ccb7ca09920ffb44ececefefe7432a82a4a35159..cad3475ba199b245c7b367042ab0b88a89b3861e 100644
GIT binary patch
delta 1174
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delta 1173
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diff --git a/Logic/synwork/BUS68030_s.srs b/Logic/synwork/BUS68030_s.srs
index c56c2243139cb2bdbc6fdee1dc4626cf375a6eb0..1789330fb4f4d7f14eee76eb73a3f90720ab4f34 100644
GIT binary patch
delta 681
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