ispLEVER Classic 2.0.00.17.20.15 SDFGEN
Copyright(C),1992-2015, Lattice Semiconductor Corporation. All Rights Reserved.
Output Files:
  Netlist File: 68030_tk.vho
  Delay   File: 68030_tk.sdf

Parsing E:/ispLEVER_Classic2_0/ispcpld/dat/sdf.mdl
Input file: c:/users/matze/documents/github/68030tk/logic\68030_tk.tte
Reading library information ...
Mapping to combinational gates 
Mapping to netlist view.
Note 18862: NODE name cpu_est_2_bus.D.X1 being renamed to GATE_cpu_est_2_bus_D_X1.
Note 18862: NODE name RST_DLY_1_bus.D.X1 being renamed to GATE_RST_DLY_1_bus_D_X1.
Note 18862: NODE name RST_DLY_1_bus.D.X2 being renamed to GATE_RST_DLY_1_bus_D_X2.
Note 18862: NODE name SM_AMIGA_3_bus.D.X1 being renamed to GATE_SM_AMIGA_3_bus_D_X1.
Note 18862: NODE name SM_AMIGA_3_bus.D.X2 being renamed to GATE_SM_AMIGA_3_bus_D_X2.
Note 18862: NODE name SM_AMIGA_i_7_bus.D.X1 being renamed to GATE_SM_AMIGA_i_7_bus_D_X1.
Note 18862: NODE name SM_AMIGA_i_7_bus.D.X2 being renamed to GATE_SM_AMIGA_i_7_bus_D_X2.
Note 18862: NODE name CIIN_0 being renamed to GATE_CIIN_OE.
Utilization Estimate
    Combinational Macros:        524
    Flip-Flop and Latch Macros:   61
    I/O Pads:                     61
Elapsed time: 1 seconds