|--------------------------------------------| |- ispLEVER Fitter Report File -| |- Version 2.0.00.17.20.15 -| |- (c)Copyright, Lattice Semiconductor 2002 -| |--------------------------------------------| Start: Thu Jan 11 20:16:38 2018 End : Thu Jan 11 20:16:38 2018 $$$ Elapsed time: 00:00:00 =========================================================================== Part [E:/ispLEVER_Classic2_0/ispcpld/dat/mach4a/mach447a] Design [68030_tk.tt4] * Place/Route options (keycode = 540674) = Spread Placement: ON = No. Routing Attempts/Placement 2 * Placement Completion +- Block +------- IO Pins Available | +- Macrocells Available | +-- IO Pins Used | | +- Signals to Place | | +----- Logic Array Inputs | | | +- Placed | | | +- Array Inputs Used _|____|____|____|_______________|____|_____________|___|________________ 0 | 16 | 11 | 11 => 100% | 8 | 8 => 100% | 33 | 21 => 63% 1 | 16 | 10 | 10 => 100% | 8 | 7 => 87% | 33 | 22 => 66% 2 | 16 | 10 | 10 => 100% | 8 | 7 => 87% | 33 | 20 => 60% 3 | 16 | 10 | 10 => 100% | 8 | 8 => 100% | 33 | 23 => 69% 4 | 16 | 8 | 8 => 100% | 8 | 4 => 50% | 33 | 30 => 90% 5 | 16 | 8 | 8 => 100% | 8 | 5 => 62% | 33 | 22 => 66% 6 | 16 | 11 | 11 => 100% | 8 | 7 => 87% | 33 | 22 => 66% 7 | 16 | 10 | 10 => 100% | 8 | 8 => 100% | 33 | 25 => 75% ---|----|----|------------|-------|------------|-----|------------------ | Avg number of array inputs in used blocks : 23.13 => 70% * Input/Clock Signal count: 23 -> placed: 23 = 100% Resources Available Used ----------------------------------------------------------------- Input Pins : 2 2 => 100% I/O Pins : 64 54 => 84% Clock Only Pins : 0 0 => 0% Clock/Input Pins : 4 3 => 75% Logic Blocks : 8 8 => 100% Macrocells : 128 78 => 60% PT Clusters : 128 48 => 37% - Single PT Clusters : 128 38 => 29% Input Registers : 0 * Routing Completion: 100% * Attempts: Place [ 108] Route [ 0] =========================================================================== Signal Fanout Table =========================================================================== +- Signal Number | +- Block Location ('+' for dedicated inputs) | | +- Sig Type | | | +- Signal-to-Pin Assignment | | | | Fanout to Logic Blocks Signal Name ___|__|__|____|____________________________________________________________ 1| 2| IO| 19|=> ....|4...| AHIGH_24_ 2| 2| IO| 18|=> ....|4...| AHIGH_25_ 3| 2| IO| 17|=> ....|4...| AHIGH_26_ 4| 2| IO| 16|=> ....|4...| AHIGH_27_ 5| 2| IO| 15|=> ....|4...| AHIGH_28_ 6| 1| IO| 6|=> ....|4...| AHIGH_29_ 7| 1| IO| 5|=> ....|4...| AHIGH_30_ 8| 1| IO| 4|=> ....|4...| AHIGH_31_ 9| 3|OUT| 33|=> ....|....| AMIGA_ADDR_ENABLE 10| 4|OUT| 48|=> ....|....| AMIGA_BUS_DATA_DIR 11| 3|OUT| 34|=> ....|....| AMIGA_BUS_ENABLE_HIGH 12| 2|OUT| 20|=> ....|....| AMIGA_BUS_ENABLE_LOW 13| 4| IO| 42|=> 0...|4.67| AS_000 14| 7| IO| 82|=> 0.23|4567| AS_030 15| 0|OUT| 92|=> ....|....| AVEC 16| 6| IO| 69|=> 0..3|....| A_0_ 17| 5|INP| 60|=> ....|4...| A_1_ 18| 0|INP| 96|=> ....|45.7| A_DECODE_16_ 19| 5|INP| 59|=> ....|45.7| A_DECODE_17_ 20| 0|INP| 95|=> ....|45.7| A_DECODE_18_ 21| 0|INP| 97|=> ....|45.7| A_DECODE_19_ 22| 0|INP| 93|=> ....|4...| A_DECODE_20_ 23| 0|INP| 94|=> ....|4...| A_DECODE_21_ 24| 7|INP| 84|=> ....|4...| A_DECODE_22_ 25| 7|INP| 85|=> ....|4...| A_DECODE_23_ 26| 4| IO| 41|=> ..2.|....| BERR 27| 3|INP| 28|=> ....|4..7| BGACK_000 28| 7| IO| 83|=> ....|....| BGACK_030 |=> Paired w/: RN_BGACK_030 29| 3| IO| 29|=> ....|....| BG_000 |=> Paired w/: RN_BG_000 30| 2|INP| 21|=> ...3|....| BG_030 31| 4|OUT| 47|=> ....|....| CIIN 32| +|INP| 11|=> ....|.5..| CLK_000 33| 5|NOD| . |=> 0123|.567| CLK_000_D_0_ 34| 0|NOD| . |=> 0123|.567| CLK_000_D_1_ 35| 7|NOD| . |=> ...3|....| CLK_000_D_2_ 36| 3|NOD| . |=> .1..|.5..| CLK_000_D_3_ 37| 5|NOD| . |=> .1..|....| CLK_000_D_4_ 38| 6|OUT| 65|=> ....|....| CLK_DIV_OUT 39| 1|OUT| 10|=> ....|....| CLK_EXP 40| +|Cin| 61|=> ....|....| CLK_OSZI 41| 0|NOD| . |=> .1..|..6.| CLK_OUT_INTreg 42| 6|NOD| . |=> ....|..6.| CYCLE_DMA_0_ 43| 6|NOD| . |=> ....|..6.| CYCLE_DMA_1_ 44| 7|OUT| 81|=> ....|....| DSACK1 45| 0|OUT| 98|=> ....|....| DS_030 46| 3|INP| 30|=> ....|.5..| DTACK 47| 6|OUT| 66|=> ....|....| E 48| 5|INP| 57|=> ....|45.7| FC_0_ 49| 5|INP| 58|=> ....|45.7| FC_1_ 50| 7|OUT| 78|=> ....|....| FPU_CS 51| 0|INP| 91|=> ....|4..7| FPU_SENSE 52| 1| IO| 8|=> ....|....| IPL_030_0_ |=> Paired w/: RN_IPL_030_0_ 53| 1| IO| 7|=> ....|....| IPL_030_1_ |=> Paired w/: RN_IPL_030_1_ 54| 1| IO| 9|=> ....|....| IPL_030_2_ |=> Paired w/: RN_IPL_030_2_ 55| 6|INP| 67|=> .1..|.5..| IPL_0_ 56| 5|INP| 56|=> 01..|....| IPL_1_ 57| 6|INP| 68|=> .12.|....| IPL_2_ 58| 5|NOD| . |=> .1..|....| IPL_D0_0_ 59| 0|NOD| . |=> .1..|....| IPL_D0_1_ 60| 2|NOD| . |=> .1..|....| IPL_D0_2_ 61| 3| IO| 31|=> ....|..67| LDS_000 62| 4|NOD| . |=> ....|4...| N_205 63| 7|NOD| . |=> 0123|4567| RN_BGACK_030 |=> Paired w/: BGACK_030 64| 3|NOD| . |=> ...3|....| RN_BG_000 |=> Paired w/: BG_000 65| 1|NOD| . |=> .1..|....| RN_IPL_030_0_ |=> Paired w/: IPL_030_0_ 66| 1|NOD| . |=> .1..|....| RN_IPL_030_1_ |=> Paired w/: IPL_030_1_ 67| 1|NOD| . |=> .1..|....| RN_IPL_030_2_ |=> Paired w/: IPL_030_2_ 68| 7|NOD| . |=> ....|...7| RN_RW_000 |=> Paired w/: RW_000 69| 3|NOD| . |=> ..23|....| RN_VMA |=> Paired w/: VMA 70| +|INP| 86|=> 0123|4567| RST 71| 6| IO| 71|=> 0...|...7| RW 72| 7| IO| 80|=> ....|4.6.| RW_000 |=> Paired w/: RN_RW_000 73| 6| IO| 70|=> 0...|....| SIZE_0_ 74| 7| IO| 79|=> 0...|....| SIZE_1_ 75| 0|NOD| . |=> 01..|...7| SM_AMIGA_0_ 76| 0|NOD| . |=> 0...|..6.| SM_AMIGA_1_ 77| 2|NOD| . |=> 0.2.|....| SM_AMIGA_2_ 78| 2|NOD| . |=> ..2.|....| SM_AMIGA_3_ 79| 0|NOD| . |=> 0.2.|....| SM_AMIGA_4_ 80| 0|NOD| . |=> 0...|....| SM_AMIGA_5_ 81| 1|NOD| . |=> 0123|...7| SM_AMIGA_6_ 82| 1|NOD| . |=> .1..|.5.7| SM_AMIGA_i_7_ 83| 3| IO| 32|=> ....|..67| UDS_000 84| 3| IO| 35|=> ....|....| VMA |=> Paired w/: RN_VMA 85| +|INP| 36|=> .1..|....| VPA 86| 5|NOD| . |=> ..23|.56.| cpu_est_0_ 87| 6|NOD| . |=> ..23|..6.| cpu_est_1_ 88| 3|NOD| . |=> ..23|..6.| cpu_est_2_ 89| 3|NOD| . |=> ..23|..6.| cpu_est_3_ 90| 4|NOD| . |=> ...3|....| inst_AMIGA_BUS_ENABLE_DMA_HIGH 91| 4|NOD| . |=> ..2.|....| inst_AMIGA_BUS_ENABLE_DMA_LOW 92| 7|NOD| . |=> ....|..6.| inst_AMIGA_DS 93| 6|NOD| . |=> ....|..67| inst_AS_000_DMA 94| 2|NOD| . |=> ..2.|4...| inst_AS_000_INT 95| 5|NOD| . |=> .1.3|.5..| inst_AS_030_000_SYNC 96| 5|NOD| . |=> ...3|45..| inst_AS_030_D0 97| 5|NOD| . |=> ....|.5..| inst_AS_030_D1 98| 4|NOD| . |=> ....|.5..| inst_BGACK_030_INT_D 99| 7|NOD| . |=> ....|...7| inst_CLK_OUT_PRE_50 100| 7|NOD| . |=> 0...|..6.| inst_CLK_OUT_PRE_D 101| 6|NOD| . |=> ....|..67| inst_DSACK1_INT 102| 6|NOD| . |=> 0...|..6.| inst_DS_000_DMA 103| 0|NOD| . |=> 0..3|....| inst_DS_000_ENABLE 104| 5|NOD| . |=> ..2.|....| inst_DTACK_D0 105| 0|NOD| . |=> 0..3|....| inst_LDS_000_INT 106| 3|NOD| . |=> ...3|....| inst_UDS_000_INT 107| 1|NOD| . |=> ..23|....| inst_VPA_D 108| +|INP| 14|=> .1.3|45.7| nEXP_SPACE --------------------------------------------------------------------------- =========================================================================== < E:/ispLEVER_Classic2_0/ispcpld/dat/mach4a/mach447a Device Pin Assignments > =========================================================================== +- Device Pin No | Pin Type +- Signal Fixed (*) | | | Signal Name ____|_____|_________|______________________________________________________ 1 | GND | | | (pwr/test) 2 | JTAG | | | (pwr/test) 3 | I_O | 1_07| | - 4 | I_O | 1_06|*| AHIGH_31_ 5 | I_O | 1_05|*| AHIGH_30_ 6 | I_O | 1_04|*| AHIGH_29_ 7 | I_O | 1_03|*| IPL_030_1_ 8 | I_O | 1_02|*| IPL_030_0_ 9 | I_O | 1_01|*| IPL_030_2_ 10 | I_O | 1_00|*| CLK_EXP 11 | CkIn | |*| CLK_000 12 | Vcc | | | (pwr/test) 13 | GND | | | (pwr/test) 14 | CkIn | |*| nEXP_SPACE 15 | I_O | 2_00|*| AHIGH_28_ 16 | I_O | 2_01|*| AHIGH_27_ 17 | I_O | 2_02|*| AHIGH_26_ 18 | I_O | 2_03|*| AHIGH_25_ 19 | I_O | 2_04|*| AHIGH_24_ 20 | I_O | 2_05|*| AMIGA_BUS_ENABLE_LOW 21 | I_O | 2_06|*| BG_030 22 | I_O | 2_07| | - 23 | JTAG | | | (pwr/test) 24 | JTAG | | | (pwr/test) 25 | GND | | | (pwr/test) 26 | GND | | | (pwr/test) 27 | GND | | | (pwr/test) 28 | I_O | 3_07|*| BGACK_000 29 | I_O | 3_06|*| BG_000 30 | I_O | 3_05|*| DTACK 31 | I_O | 3_04|*| LDS_000 32 | I_O | 3_03|*| UDS_000 33 | I_O | 3_02|*| AMIGA_ADDR_ENABLE 34 | I_O | 3_01|*| AMIGA_BUS_ENABLE_HIGH 35 | I_O | 3_00|*| VMA 36 | Inp | |*| VPA 37 | Vcc | | | (pwr/test) 38 | GND | | | (pwr/test) 39 | GND | | | (pwr/test) 40 | Vcc | | | (pwr/test) 41 | I_O | 4_00|*| BERR 42 | I_O | 4_01|*| AS_000 43 | I_O | 4_02| | - 44 | I_O | 4_03| | - 45 | I_O | 4_04| | - 46 | I_O | 4_05| | - 47 | I_O | 4_06|*| CIIN 48 | I_O | 4_07|*| AMIGA_BUS_DATA_DIR 49 | GND | | | (pwr/test) 50 | GND | | | (pwr/test) 51 | GND | | | (pwr/test) 52 | JTAG | | | (pwr/test) 53 | I_O | 5_07| | - 54 | I_O | 5_06| | - 55 | I_O | 5_05| | - 56 | I_O | 5_04|*| IPL_1_ 57 | I_O | 5_03|*| FC_0_ 58 | I_O | 5_02|*| FC_1_ 59 | I_O | 5_01|*| A_DECODE_17_ 60 | I_O | 5_00|*| A_1_ 61 | CkIn | |*| CLK_OSZI 62 | Vcc | | | (pwr/test) 63 | GND | | | (pwr/test) 64 | CkIn | | | - 65 | I_O | 6_00|*| CLK_DIV_OUT 66 | I_O | 6_01|*| E 67 | I_O | 6_02|*| IPL_0_ 68 | I_O | 6_03|*| IPL_2_ 69 | I_O | 6_04|*| A_0_ 70 | I_O | 6_05|*| SIZE_0_ 71 | I_O | 6_06|*| RW 72 | I_O | 6_07| | - 73 | JTAG | | | (pwr/test) 74 | JTAG | | | (pwr/test) 75 | GND | | | (pwr/test) 76 | GND | | | (pwr/test) 77 | GND | | | (pwr/test) 78 | I_O | 7_07|*| FPU_CS 79 | I_O | 7_06|*| SIZE_1_ 80 | I_O | 7_05|*| RW_000 81 | I_O | 7_04|*| DSACK1 82 | I_O | 7_03|*| AS_030 83 | I_O | 7_02|*| BGACK_030 84 | I_O | 7_01|*| A_DECODE_22_ 85 | I_O | 7_00|*| A_DECODE_23_ 86 | Inp | |*| RST 87 | Vcc | | | (pwr/test) 88 | GND | | | (pwr/test) 89 | GND | | | (pwr/test) 90 | Vcc | | | (pwr/test) 91 | I_O | 0_00|*| FPU_SENSE 92 | I_O | 0_01|*| AVEC 93 | I_O | 0_02|*| A_DECODE_20_ 94 | I_O | 0_03|*| A_DECODE_21_ 95 | I_O | 0_04|*| A_DECODE_18_ 96 | I_O | 0_05|*| A_DECODE_16_ 97 | I_O | 0_06|*| A_DECODE_19_ 98 | I_O | 0_07|*| DS_030 99 | GND | | | (pwr/test) 100 | GND | | | (pwr/test) --------------------------------------------------------------------------- =========================================================================== < Block [ 0] > Macrocell (MCell) Cluster Assignments =========================================================================== + Macrocell Number | PT Requirements------ Logic XOR+ +--- Macrocell PT Cluster Size | Sync/Async-------+ | | | Cluster to Mcell Assignment | Node Fixed(*)----+ | | | | | +- XOR PT Size | Sig Type-+ | | | | | | | XOR to Mcell Assignment | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| DS_030|OUT| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig 1| SM_AMIGA_1_|NOD| | S | 3 | 4 to [ 1]| 1 XOR free 2|CLK_OUT_INTreg|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig 3| | ? | | S | | 4 free | 1 XOR free 4| AVEC|OUT| | S | 1 | 4 free | 1 XOR to [ 4] for 1 PT sig 5| SM_AMIGA_4_|NOD| | S | 3 | 4 to [ 5]| 1 XOR free 6| SM_AMIGA_5_|NOD| | S | 3 | 4 to [ 6]| 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free 8| CLK_000_D_1_|NOD| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig 9|inst_LDS_000_INT|NOD| | S | 3 | 4 to [ 9]| 1 XOR free 10| IPL_D0_1_|NOD| | S | 1 | 4 free | 1 XOR to [10] for 1 PT sig 11| | ? | | S | | 4 free | 1 XOR free 12| SM_AMIGA_0_|NOD| | S | 3 | 4 to [12]| 1 XOR free 13|inst_DS_000_ENABLE|NOD| | S | 3 | 4 to [13]| 1 XOR free 14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== < Block [ 0] > Maximum PT Capacity =========================================================================== + Macrocell Number | PT Requirements------ Logic XOR+ | Sync/Async-------+ | | | Node Fixed(*)----+ | | | | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ 0| DS_030|OUT| | S | 1 |=> can support up to [ 9] logic PT(s) 1| SM_AMIGA_1_|NOD| | S | 3 |=> can support up to [ 18] logic PT(s) 2|CLK_OUT_INTreg|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) 3| | ? | | S | |=> can support up to [ 13] logic PT(s) 4| AVEC|OUT| | S | 1 |=> can support up to [ 10] logic PT(s) 5| SM_AMIGA_4_|NOD| | S | 3 |=> can support up to [ 14] logic PT(s) 6| SM_AMIGA_5_|NOD| | S | 3 |=> can support up to [ 14] logic PT(s) 7| | ? | | S | |=> can support up to [ 9] logic PT(s) 8| CLK_000_D_1_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) 9|inst_LDS_000_INT|NOD| | S | 3 |=> can support up to [ 18] logic PT(s) 10| IPL_D0_1_|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) 11| | ? | | S | |=> can support up to [ 9] logic PT(s) 12| SM_AMIGA_0_|NOD| | S | 3 |=> can support up to [ 15] logic PT(s) 13|inst_DS_000_ENABLE|NOD| | S | 3 |=> can support up to [ 15] logic PT(s) 14| | ? | | S | |=> can support up to [ 10] logic PT(s) 15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 0] > Node-Pin Assignments =========================================================================== + Macrocell Number | Node Fixed(*)------+ | Sig Type---+ | to | Block [ 0] IO Pin | Device Pin | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ 0| DS_030|OUT| | => | 5 6 ( 7) 0 | 96 97 ( 98) 91 1| SM_AMIGA_1_|NOD| | => | 5 6 7 0 | 96 97 98 91 2|CLK_OUT_INTreg|NOD| | => | 6 7 0 1 | 97 98 91 92 3| | | | => | 6 7 0 1 | 97 98 91 92 4| AVEC|OUT| | => | 7 0 ( 1) 2 | 98 91 ( 92) 93 5| SM_AMIGA_4_|NOD| | => | 7 0 1 2 | 98 91 92 93 6| SM_AMIGA_5_|NOD| | => | 0 1 2 3 | 91 92 93 94 7| | | | => | 0 1 2 3 | 91 92 93 94 8| CLK_000_D_1_|NOD| | => | 1 2 3 4 | 92 93 94 95 9|inst_LDS_000_INT|NOD| | => | 1 2 3 4 | 92 93 94 95 10| IPL_D0_1_|NOD| | => | 2 3 4 5 | 93 94 95 96 11| | | | => | 2 3 4 5 | 93 94 95 96 12| SM_AMIGA_0_|NOD| | => | 3 4 5 6 | 94 95 96 97 13|inst_DS_000_ENABLE|NOD| | => | 3 4 5 6 | 94 95 96 97 14| | | | => | 4 5 6 7 | 95 96 97 98 15| | | | => | 4 5 6 7 | 95 96 97 98 --------------------------------------------------------------------------- =========================================================================== < Block [ 0] > IO-to-Node Pin Mapping =========================================================================== +- Block IO Pin | Device Pin No.--------+ | Pin Fixed(*)----+ | | Sig Type--+ | | | | Signal Name | | | | Node Destinations Via Output Matrix _|_________________|__|___|_____|___________________________________________ 0| FPU_SENSE|INP|*| 91| => | 0 1 2 3 4 5 6 7 1| AVEC|OUT|*| 92| => | 2 3 ( 4) 5 6 7 8 9 2| A_DECODE_20_|INP|*| 93| => | 4 5 6 7 8 9 10 11 3| A_DECODE_21_|INP|*| 94| => | 6 7 8 9 10 11 12 13 4| A_DECODE_18_|INP|*| 95| => | 8 9 10 11 12 13 14 15 5| A_DECODE_16_|INP|*| 96| => | 10 11 12 13 14 15 0 1 6| A_DECODE_19_|INP|*| 97| => | 12 13 14 15 0 1 2 3 7| DS_030|OUT|*| 98| => | 14 15 ( 0) 1 2 3 4 5 --------------------------------------------------------------------------- =========================================================================== < Block [ 0] > IO/Node and IO/Input Macrocell Pairing Table =========================================================================== +- Block IO Pin | Device Pin No.--------+ | Pin Fixed(*)----+ | | Sig Type--+ | | | | Signal Name | | | | Input Macrocell and Node Pairs _|_________________|__|___|_____|__________________________________________ 0| FPU_SENSE|INP|*| 91| => | Input macrocell [ -] 1| AVEC|OUT|*| 92| => | Input macrocell [ -] 2| A_DECODE_20_|INP|*| 93| => | Input macrocell [ -] 3| A_DECODE_21_|INP|*| 94| => | Input macrocell [ -] 4| A_DECODE_18_|INP|*| 95| => | Input macrocell [ -] 5| A_DECODE_16_|INP|*| 96| => | Input macrocell [ -] 6| A_DECODE_19_|INP|*| 97| => | Input macrocell [ -] 7| DS_030|OUT|*| 98| => | Input macrocell [ -] --------------------------------------------------------------------------- =========================================================================== < Block [ 0] > Input Multiplexer (IMX) Assignments =========================================================================== +----- IO pin/Input Register, or Macrocell IMX No. | +---- Block IO Pin or Macrocell Number | | | ABEL Node/ +-- Signal using the Pin or Macrocell | | | Pin Number | +- Signal Fixed (*) to Pin/Mcell | | | | Sig Type | | +- Feedback Required (*) ---|-------|----|---|---|----------|------|-|------------------------------ 0 [IOpin 0 | 91|INP FPU_SENSE|*|*] [RegIn 0 |102| -| | ] [MCell 0 |101|OUT DS_030| | ] [MCell 1 |103|NOD SM_AMIGA_1_| |*] 1 [IOpin 1 | 92|OUT AVEC|*| ] [RegIn 1 |105| -| | ] [MCell 2 |104|NOD CLK_OUT_INTreg| |*] [MCell 3 |106| -| | ] 2 [IOpin 2 | 93|INP A_DECODE_20_|*|*] [RegIn 2 |108| -| | ] [MCell 4 |107|OUT AVEC| | ] [MCell 5 |109|NOD SM_AMIGA_4_| |*] 3 [IOpin 3 | 94|INP A_DECODE_21_|*|*] [RegIn 3 |111| -| | ] [MCell 6 |110|NOD SM_AMIGA_5_| |*] [MCell 7 |112| -| | ] 4 [IOpin 4 | 95|INP A_DECODE_18_|*|*] [RegIn 4 |114| -| | ] [MCell 8 |113|NOD CLK_000_D_1_| |*] [MCell 9 |115|NOD inst_LDS_000_INT| |*] 5 [IOpin 5 | 96|INP A_DECODE_16_|*|*] [RegIn 5 |117| -| | ] [MCell 10 |116|NOD IPL_D0_1_| |*] [MCell 11 |118| -| | ] 6 [IOpin 6 | 97|INP A_DECODE_19_|*|*] [RegIn 6 |120| -| | ] [MCell 12 |119|NOD SM_AMIGA_0_| |*] [MCell 13 |121|NOD inst_DS_000_ENABLE| |*] 7 [IOpin 7 | 98|OUT DS_030|*| ] [RegIn 7 |123| -| | ] [MCell 14 |122| -| | ] [MCell 15 |124| -| | ] --------------------------------------------------------------------------- =========================================================================== < Block [ 0] > Logic Array Fan-in =========================================================================== +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- Mux00| IOPin 6 4 ( 69)| A_0_ Mux01| ... | ... Mux02| Mcel 0 9 ( 115)| inst_LDS_000_INT Mux03| IOPin 5 4 ( 56)| IPL_1_ Mux04| Mcel 7 5 ( 277)| inst_CLK_OUT_PRE_D Mux05| Mcel 5 0 ( 221)| CLK_000_D_0_ Mux06| IOPin 7 6 ( 79)| SIZE_1_ Mux07| ... | ... Mux08| IOPin 6 6 ( 71)| RW Mux09| Mcel 0 12 ( 119)| SM_AMIGA_0_ Mux10| Mcel 1 13 ( 145)| SM_AMIGA_6_ Mux11| ... | ... Mux12| Mcel 0 1 ( 103)| SM_AMIGA_1_ Mux13| Mcel 2 9 ( 163)| SM_AMIGA_2_ Mux14| IOPin 6 5 ( 70)| SIZE_0_ Mux15| Mcel 0 6 ( 110)| SM_AMIGA_5_ Mux16| IOPin 4 1 ( 42)| AS_000 Mux17| ... | ... Mux18| Mcel 0 5 ( 109)| SM_AMIGA_4_ Mux19| IOPin 7 3 ( 82)| AS_030 Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 Mux21| Input Pin ( 86)| RST Mux22| ... | ... Mux23| ... | ... Mux24| ... | ... Mux25| Mcel 0 13 ( 121)| inst_DS_000_ENABLE Mux26| ... | ... Mux27| Mcel 6 9 ( 259)| inst_DS_000_DMA Mux28| ... | ... Mux29| ... | ... Mux30| Mcel 0 8 ( 113)| CLK_000_D_1_ Mux31| ... | ... Mux32| ... | ... --------------------------------------------------------------------------- =========================================================================== < Block [ 1] > Macrocell (MCell) Cluster Assignments =========================================================================== + Macrocell Number | PT Requirements------ Logic XOR+ +--- Macrocell PT Cluster Size | Sync/Async-------+ | | | Cluster to Mcell Assignment | Node Fixed(*)----+ | | | | | +- XOR PT Size | Sig Type-+ | | | | | | | XOR to Mcell Assignment | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| AHIGH_30_| IO| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig 1| CLK_EXP|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig 2| SM_AMIGA_i_7_|NOD| | S | 3 :+: 1| 4 to [ 2]| 1 XOR to [ 2] 3| | ? | | S | | 4 to [ 4]| 1 XOR to [ 4] as logic PT 4| IPL_030_2_| IO| | S |10 | 4 to [ 4]| 1 XOR to [ 4] as logic PT 5| IPL_030_0_| IO| | S |10 | 4 to [ 5]| 1 XOR to [ 5] as logic PT 6| inst_VPA_D|NOD| | S | 1 | 4 to [ 5]| 1 XOR to [ 6] for 1 PT sig 7| | ? | | S | | 4 to [ 5]| 1 XOR free 8| AHIGH_29_| IO| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig 9| IPL_030_1_| IO| | S |10 | 4 to [ 9]| 1 XOR to [ 9] as logic PT 10| | ? | | S | | 4 to [ 9]| 1 XOR free 11| | ? | | S | | 4 to [ 9]| 1 XOR free 12| AHIGH_31_| IO| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig 13| SM_AMIGA_6_|NOD| | S | 3 | 4 to [13]| 1 XOR free 14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== < Block [ 1] > Maximum PT Capacity =========================================================================== + Macrocell Number | PT Requirements------ Logic XOR+ | Sync/Async-------+ | | | Node Fixed(*)----+ | | | | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ 0| AHIGH_30_| IO| | S | 1 |=> can support up to [ 9] logic PT(s) 1| CLK_EXP|OUT| | S | 1 |=> can support up to [ 9] logic PT(s) 2| SM_AMIGA_i_7_|NOD| | S | 3 :+: 1|=> can support up to [ 8] logic PT(s) 3| | ? | | S | |=> [ 0] PT capacity 4| IPL_030_2_| IO| | S |10 |=> can support up to [ 10] logic PT(s) 5| IPL_030_0_| IO| | S |10 |=> can support up to [ 14] logic PT(s) 6| inst_VPA_D|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) 7| | ? | | S | |=> can support up to [ 5] logic PT(s) 8| AHIGH_29_| IO| | S | 1 |=> can support up to [ 5] logic PT(s) 9| IPL_030_1_| IO| | S |10 |=> can support up to [ 19] logic PT(s) 10| | ? | | S | |=> can support up to [ 5] logic PT(s) 11| | ? | | S | |=> can support up to [ 5] logic PT(s) 12| AHIGH_31_| IO| | S | 1 |=> can support up to [ 10] logic PT(s) 13| SM_AMIGA_6_|NOD| | S | 3 |=> can support up to [ 19] logic PT(s) 14| | ? | | S | |=> can support up to [ 10] logic PT(s) 15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 1] > Node-Pin Assignments =========================================================================== + Macrocell Number | Node Fixed(*)------+ | Sig Type---+ | to | Block [ 1] IO Pin | Device Pin | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ 0| AHIGH_30_| IO| | => |( 5) 6 7 0 |( 5) 4 3 10 1| CLK_EXP|OUT| | => | 5 6 7 ( 0)| 5 4 3 ( 10) 2| SM_AMIGA_i_7_|NOD| | => | 6 7 0 1 | 4 3 10 9 3| | | | => | 6 7 0 1 | 4 3 10 9 4| IPL_030_2_| IO| | => | 7 0 ( 1) 2 | 3 10 ( 9) 8 5| IPL_030_0_| IO| | => | 7 0 1 ( 2)| 3 10 9 ( 8) 6| inst_VPA_D|NOD| | => | 0 1 2 3 | 10 9 8 7 7| | | | => | 0 1 2 3 | 10 9 8 7 8| AHIGH_29_| IO| | => | 1 2 3 ( 4)| 9 8 7 ( 6) 9| IPL_030_1_| IO| | => | 1 2 ( 3) 4 | 9 8 ( 7) 6 10| | | | => | 2 3 4 5 | 8 7 6 5 11| | | | => | 2 3 4 5 | 8 7 6 5 12| AHIGH_31_| IO| | => | 3 4 5 ( 6)| 7 6 5 ( 4) 13| SM_AMIGA_6_|NOD| | => | 3 4 5 6 | 7 6 5 4 14| | | | => | 4 5 6 7 | 6 5 4 3 15| | | | => | 4 5 6 7 | 6 5 4 3 --------------------------------------------------------------------------- =========================================================================== < Block [ 1] > IO-to-Node Pin Mapping =========================================================================== +- Block IO Pin | Device Pin No.--------+ | Pin Fixed(*)----+ | | Sig Type--+ | | | | Signal Name | | | | Node Destinations Via Output Matrix _|_________________|__|___|_____|___________________________________________ 0| CLK_EXP|OUT|*| 10| => | 0 ( 1) 2 3 4 5 6 7 1| IPL_030_2_| IO|*| 9| => | 2 3 ( 4) 5 6 7 8 9 2| IPL_030_0_| IO|*| 8| => | 4 ( 5) 6 7 8 9 10 11 3| IPL_030_1_| IO|*| 7| => | 6 7 8 ( 9) 10 11 12 13 4| AHIGH_29_| IO|*| 6| => | ( 8) 9 10 11 12 13 14 15 5| AHIGH_30_| IO|*| 5| => | 10 11 12 13 14 15 ( 0) 1 6| AHIGH_31_| IO|*| 4| => | (12) 13 14 15 0 1 2 3 7| | | | 3| => | 14 15 0 1 2 3 4 5 --------------------------------------------------------------------------- =========================================================================== < Block [ 1] > IO/Node and IO/Input Macrocell Pairing Table =========================================================================== +- Block IO Pin | Device Pin No.--------+ | Pin Fixed(*)----+ | | Sig Type--+ | | | | Signal Name | | | | Input Macrocell and Node Pairs _|_________________|__|___|_____|__________________________________________ 0| CLK_EXP|OUT|*| 10| => | Input macrocell [ -] 1| IPL_030_2_| IO|*| 9| => | Input macrocell [ -] | | | | | | IO paired w/ node [ RN_IPL_030_2_] 2| IPL_030_0_| IO|*| 8| => | Input macrocell [ -] | | | | | | IO paired w/ node [ RN_IPL_030_0_] 3| IPL_030_1_| IO|*| 7| => | Input macrocell [ -] | | | | | | IO paired w/ node [ RN_IPL_030_1_] 4| AHIGH_29_| IO|*| 6| => | Input macrocell [ -] 5| AHIGH_30_| IO|*| 5| => | Input macrocell [ -] 6| AHIGH_31_| IO|*| 4| => | Input macrocell [ -] 7| | | | 3| => | Input macrocell [ -] --------------------------------------------------------------------------- =========================================================================== < Block [ 1] > Input Multiplexer (IMX) Assignments =========================================================================== +----- IO pin/Input Register, or Macrocell IMX No. | +---- Block IO Pin or Macrocell Number | | | ABEL Node/ +-- Signal using the Pin or Macrocell | | | Pin Number | +- Signal Fixed (*) to Pin/Mcell | | | | Sig Type | | +- Feedback Required (*) ---|-------|----|---|---|----------|------|-|------------------------------ 0 [IOpin 0 | 10|OUT CLK_EXP|*| ] [RegIn 0 |126| -| | ] [MCell 0 |125| IO AHIGH_30_| | ] [MCell 1 |127|OUT CLK_EXP| | ] 1 [IOpin 1 | 9| IO IPL_030_2_|*| ] paired w/[ RN_IPL_030_2_] [RegIn 1 |129| -| | ] [MCell 2 |128|NOD SM_AMIGA_i_7_| |*] [MCell 3 |130| -| | ] 2 [IOpin 2 | 8| IO IPL_030_0_|*| ] paired w/[ RN_IPL_030_0_] [RegIn 2 |132| -| | ] [MCell 4 |131|NOD RN_IPL_030_2_| |*] paired w/[ IPL_030_2_] [MCell 5 |133|NOD RN_IPL_030_0_| |*] paired w/[ IPL_030_0_] 3 [IOpin 3 | 7| IO IPL_030_1_|*| ] paired w/[ RN_IPL_030_1_] [RegIn 3 |135| -| | ] [MCell 6 |134|NOD inst_VPA_D| |*] [MCell 7 |136| -| | ] 4 [IOpin 4 | 6| IO AHIGH_29_|*|*] [RegIn 4 |138| -| | ] [MCell 8 |137| IO AHIGH_29_| | ] [MCell 9 |139|NOD RN_IPL_030_1_| |*] paired w/[ IPL_030_1_] 5 [IOpin 5 | 5| IO AHIGH_30_|*|*] [RegIn 5 |141| -| | ] [MCell 10 |140| -| | ] [MCell 11 |142| -| | ] 6 [IOpin 6 | 4| IO AHIGH_31_|*|*] [RegIn 6 |144| -| | ] [MCell 12 |143| IO AHIGH_31_| | ] [MCell 13 |145|NOD SM_AMIGA_6_| |*] 7 [IOpin 7 | 3| -| | ] [RegIn 7 |147| -| | ] [MCell 14 |146| -| | ] [MCell 15 |148| -| | ] --------------------------------------------------------------------------- =========================================================================== < Block [ 1] > Logic Array Fan-in =========================================================================== +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- Mux00| IOPin 6 2 ( 67)| IPL_0_ Mux01| Mcel 5 9 ( 235)| IPL_D0_0_ Mux02| Mcel 5 8 ( 233)| inst_AS_030_000_SYNC Mux03| IOPin 5 4 ( 56)| IPL_1_ Mux04| IOPin 6 3 ( 68)| IPL_2_ Mux05| Input Pin ( 14)| nEXP_SPACE Mux06| Mcel 1 9 ( 139)| RN_IPL_030_1_ Mux07| ... | ... Mux08| Mcel 0 10 ( 116)| IPL_D0_1_ Mux09| Mcel 2 6 ( 158)| IPL_D0_2_ Mux10| Mcel 1 13 ( 145)| SM_AMIGA_6_ Mux11| ... | ... Mux12| ... | ... Mux13| Input Pin ( 36)| VPA Mux14| Mcel 5 5 ( 229)| CLK_000_D_4_ Mux15| Mcel 0 12 ( 119)| SM_AMIGA_0_ Mux16| Mcel 3 2 ( 176)| CLK_000_D_3_ Mux17| ... | ... Mux18| Mcel 1 2 ( 128)| SM_AMIGA_i_7_ Mux19| ... | ... Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 Mux21| Input Pin ( 86)| RST Mux22| Mcel 0 2 ( 104)| CLK_OUT_INTreg Mux23| ... | ... Mux24| ... | ... Mux25| Mcel 5 0 ( 221)| CLK_000_D_0_ Mux26| ... | ... Mux27| Mcel 1 4 ( 131)| RN_IPL_030_2_ Mux28| Mcel 1 5 ( 133)| RN_IPL_030_0_ Mux29| ... | ... Mux30| Mcel 0 8 ( 113)| CLK_000_D_1_ Mux31| ... | ... Mux32| ... | ... --------------------------------------------------------------------------- =========================================================================== < Block [ 2] > Macrocell (MCell) Cluster Assignments =========================================================================== + Macrocell Number | PT Requirements------ Logic XOR+ +--- Macrocell PT Cluster Size | Sync/Async-------+ | | | Cluster to Mcell Assignment | Node Fixed(*)----+ | | | | | +- XOR PT Size | Sig Type-+ | | | | | | | XOR to Mcell Assignment | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| AHIGH_28_| IO| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig 1|AMIGA_BUS_ENABLE_LOW|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig 2| SM_AMIGA_3_|NOD| | S | 5 | 4 to [ 2]| 1 XOR to [ 2] as logic PT 3| | ? | | S | | 4 free | 1 XOR free 4| AHIGH_26_| IO| | S | 1 | 4 free | 1 XOR to [ 4] for 1 PT sig 5| AHIGH_27_| IO| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig 6| IPL_D0_2_|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig 7| | ? | | S | | 4 free | 1 XOR free 8| AHIGH_24_| IO| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig 9| SM_AMIGA_2_|NOD| | S | 5 | 4 to [ 9]| 1 XOR to [ 9] as logic PT 10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free 12| AHIGH_25_| IO| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig 13|inst_AS_000_INT|NOD| | S | 2 | 4 to [13]| 1 XOR free 14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== < Block [ 2] > Maximum PT Capacity =========================================================================== + Macrocell Number | PT Requirements------ Logic XOR+ | Sync/Async-------+ | | | Node Fixed(*)----+ | | | | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ 0| AHIGH_28_| IO| | S | 1 |=> can support up to [ 9] logic PT(s) 1|AMIGA_BUS_ENABLE_LOW|OUT| | S | 1 |=> can support up to [ 14] logic PT(s) 2| SM_AMIGA_3_|NOD| | S | 5 |=> can support up to [ 18] logic PT(s) 3| | ? | | S | |=> can support up to [ 13] logic PT(s) 4| AHIGH_26_| IO| | S | 1 |=> can support up to [ 18] logic PT(s) 5| AHIGH_27_| IO| | S | 1 |=> can support up to [ 18] logic PT(s) 6| IPL_D0_2_|NOD| | S | 1 |=> can support up to [ 18] logic PT(s) 7| | ? | | S | |=> can support up to [ 13] logic PT(s) 8| AHIGH_24_| IO| | S | 1 |=> can support up to [ 15] logic PT(s) 9| SM_AMIGA_2_|NOD| | S | 5 |=> can support up to [ 19] logic PT(s) 10| | ? | | S | |=> can support up to [ 14] logic PT(s) 11| | ? | | S | |=> can support up to [ 14] logic PT(s) 12| AHIGH_25_| IO| | S | 1 |=> can support up to [ 15] logic PT(s) 13|inst_AS_000_INT|NOD| | S | 2 |=> can support up to [ 19] logic PT(s) 14| | ? | | S | |=> can support up to [ 10] logic PT(s) 15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 2] > Node-Pin Assignments =========================================================================== + Macrocell Number | Node Fixed(*)------+ | Sig Type---+ | to | Block [ 2] IO Pin | Device Pin | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ 0| AHIGH_28_| IO| | => | 5 6 7 ( 0)| 20 21 22 ( 15) 1|AMIGA_BUS_ENABLE_LOW|OUT| | => |( 5) 6 7 0 |( 20) 21 22 15 2| SM_AMIGA_3_|NOD| | => | 6 7 0 1 | 21 22 15 16 3| | | | => | 6 7 0 1 | 21 22 15 16 4| AHIGH_26_| IO| | => | 7 0 1 ( 2)| 22 15 16 ( 17) 5| AHIGH_27_| IO| | => | 7 0 ( 1) 2 | 22 15 ( 16) 17 6| IPL_D0_2_|NOD| | => | 0 1 2 3 | 15 16 17 18 7| | | | => | 0 1 2 3 | 15 16 17 18 8| AHIGH_24_| IO| | => | 1 2 3 ( 4)| 16 17 18 ( 19) 9| SM_AMIGA_2_|NOD| | => | 1 2 3 4 | 16 17 18 19 10| | | | => | 2 3 4 5 | 17 18 19 20 11| | | | => | 2 3 4 5 | 17 18 19 20 12| AHIGH_25_| IO| | => |( 3) 4 5 6 |( 18) 19 20 21 13|inst_AS_000_INT|NOD| | => | 3 4 5 6 | 18 19 20 21 14| | | | => | 4 5 6 7 | 19 20 21 22 15| | | | => | 4 5 6 7 | 19 20 21 22 --------------------------------------------------------------------------- =========================================================================== < Block [ 2] > IO-to-Node Pin Mapping =========================================================================== +- Block IO Pin | Device Pin No.--------+ | Pin Fixed(*)----+ | | Sig Type--+ | | | | Signal Name | | | | Node Destinations Via Output Matrix _|_________________|__|___|_____|___________________________________________ 0| AHIGH_28_| IO|*| 15| => | ( 0) 1 2 3 4 5 6 7 1| AHIGH_27_| IO|*| 16| => | 2 3 4 ( 5) 6 7 8 9 2| AHIGH_26_| IO|*| 17| => | ( 4) 5 6 7 8 9 10 11 3| AHIGH_25_| IO|*| 18| => | 6 7 8 9 10 11 (12) 13 4| AHIGH_24_| IO|*| 19| => | ( 8) 9 10 11 12 13 14 15 5|AMIGA_BUS_ENABLE_LOW|OUT|*| 20| => | 10 11 12 13 14 15 0 ( 1) 6| BG_030|INP|*| 21| => | 12 13 14 15 0 1 2 3 7| | | | 22| => | 14 15 0 1 2 3 4 5 --------------------------------------------------------------------------- =========================================================================== < Block [ 2] > IO/Node and IO/Input Macrocell Pairing Table =========================================================================== +- Block IO Pin | Device Pin No.--------+ | Pin Fixed(*)----+ | | Sig Type--+ | | | | Signal Name | | | | Input Macrocell and Node Pairs _|_________________|__|___|_____|__________________________________________ 0| AHIGH_28_| IO|*| 15| => | Input macrocell [ -] 1| AHIGH_27_| IO|*| 16| => | Input macrocell [ -] 2| AHIGH_26_| IO|*| 17| => | Input macrocell [ -] 3| AHIGH_25_| IO|*| 18| => | Input macrocell [ -] 4| AHIGH_24_| IO|*| 19| => | Input macrocell [ -] 5|AMIGA_BUS_ENABLE_LOW|OUT|*| 20| => | Input macrocell [ -] 6| BG_030|INP|*| 21| => | Input macrocell [ -] 7| | | | 22| => | Input macrocell [ -] --------------------------------------------------------------------------- =========================================================================== < Block [ 2] > Input Multiplexer (IMX) Assignments =========================================================================== +----- IO pin/Input Register, or Macrocell IMX No. | +---- Block IO Pin or Macrocell Number | | | ABEL Node/ +-- Signal using the Pin or Macrocell | | | Pin Number | +- Signal Fixed (*) to Pin/Mcell | | | | Sig Type | | +- Feedback Required (*) ---|-------|----|---|---|----------|------|-|------------------------------ 0 [IOpin 0 | 15| IO AHIGH_28_|*|*] [RegIn 0 |150| -| | ] [MCell 0 |149| IO AHIGH_28_| | ] [MCell 1 |151|OUT AMIGA_BUS_ENABLE_LOW| | ] 1 [IOpin 1 | 16| IO AHIGH_27_|*|*] [RegIn 1 |153| -| | ] [MCell 2 |152|NOD SM_AMIGA_3_| |*] [MCell 3 |154| -| | ] 2 [IOpin 2 | 17| IO AHIGH_26_|*|*] [RegIn 2 |156| -| | ] [MCell 4 |155| IO AHIGH_26_| | ] [MCell 5 |157| IO AHIGH_27_| | ] 3 [IOpin 3 | 18| IO AHIGH_25_|*|*] [RegIn 3 |159| -| | ] [MCell 6 |158|NOD IPL_D0_2_| |*] [MCell 7 |160| -| | ] 4 [IOpin 4 | 19| IO AHIGH_24_|*|*] [RegIn 4 |162| -| | ] [MCell 8 |161| IO AHIGH_24_| | ] [MCell 9 |163|NOD SM_AMIGA_2_| |*] 5 [IOpin 5 | 20|OUT AMIGA_BUS_ENABLE_LOW|*| ] [RegIn 5 |165| -| | ] [MCell 10 |164| -| | ] [MCell 11 |166| -| | ] 6 [IOpin 6 | 21|INP BG_030|*|*] [RegIn 6 |168| -| | ] [MCell 12 |167| IO AHIGH_25_| | ] [MCell 13 |169|NOD inst_AS_000_INT| |*] 7 [IOpin 7 | 22| -| | ] [RegIn 7 |171| -| | ] [MCell 14 |170| -| | ] [MCell 15 |172| -| | ] --------------------------------------------------------------------------- =========================================================================== < Block [ 2] > Logic Array Fan-in =========================================================================== +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- Mux00| Input Pin ( 86)| RST Mux01| Mcel 3 0 ( 173)| RN_VMA Mux02| Mcel 2 2 ( 152)| SM_AMIGA_3_ Mux03| Mcel 0 8 ( 113)| CLK_000_D_1_ Mux04| IOPin 6 3 ( 68)| IPL_2_ Mux05| Mcel 5 0 ( 221)| CLK_000_D_0_ Mux06| Mcel 5 13 ( 241)| inst_DTACK_D0 Mux07| Mcel 3 9 ( 187)| cpu_est_3_ Mux08| Mcel 4 8 ( 209)| inst_AMIGA_BUS_ENABLE_DMA_LOW Mux09| IOPin 7 3 ( 82)| AS_030 Mux10| Mcel 5 4 ( 227)| cpu_est_0_ Mux11| Mcel 1 6 ( 134)| inst_VPA_D Mux12| ... | ... Mux13| Mcel 2 9 ( 163)| SM_AMIGA_2_ Mux14| ... | ... Mux15| ... | ... Mux16| ... | ... Mux17| IOPin 4 0 ( 41)| BERR Mux18| Mcel 0 5 ( 109)| SM_AMIGA_4_ Mux19| ... | ... Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 Mux21| Mcel 3 13 ( 193)| cpu_est_2_ Mux22| Mcel 6 5 ( 253)| cpu_est_1_ Mux23| ... | ... Mux24| ... | ... Mux25| ... | ... Mux26| ... | ... Mux27| ... | ... Mux28| Mcel 1 13 ( 145)| SM_AMIGA_6_ Mux29| ... | ... Mux30| Mcel 2 13 ( 169)| inst_AS_000_INT Mux31| ... | ... Mux32| ... | ... --------------------------------------------------------------------------- =========================================================================== < Block [ 3] > Macrocell (MCell) Cluster Assignments =========================================================================== + Macrocell Number | PT Requirements------ Logic XOR+ +--- Macrocell PT Cluster Size | Sync/Async-------+ | | | Cluster to Mcell Assignment | Node Fixed(*)----+ | | | | | +- XOR PT Size | Sig Type-+ | | | | | | | XOR to Mcell Assignment | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| VMA| IO| | S | 3 | 4 to [ 0]| 1 XOR free 1| BG_000| IO| | S | 2 | 4 to [ 1]| 1 XOR free 2| CLK_000_D_3_|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig 3| | ? | | S | | 4 free | 1 XOR free 4|AMIGA_BUS_ENABLE_HIGH|OUT| | S | 2 | 4 to [ 4]| 1 XOR free 5|AMIGA_ADDR_ENABLE|OUT| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig 6|inst_UDS_000_INT|NOD| | S | 2 | 4 to [ 6]| 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free 8| UDS_000| IO| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig 9| cpu_est_3_|NOD| | S | 4 | 4 to [ 9]| 1 XOR free 10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free 12| LDS_000| IO| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig 13| cpu_est_2_|NOD| | S | 1 :+: 1| 4 to [13]| 1 XOR to [13] 14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== < Block [ 3] > Maximum PT Capacity =========================================================================== + Macrocell Number | PT Requirements------ Logic XOR+ | Sync/Async-------+ | | | Node Fixed(*)----+ | | | | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ 0| VMA| IO| | S | 3 |=> can support up to [ 9] logic PT(s) 1| BG_000| IO| | S | 2 |=> can support up to [ 14] logic PT(s) 2| CLK_000_D_3_|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) 3| | ? | | S | |=> can support up to [ 13] logic PT(s) 4|AMIGA_BUS_ENABLE_HIGH|OUT| | S | 2 |=> can support up to [ 14] logic PT(s) 5|AMIGA_ADDR_ENABLE|OUT| | S | 1 |=> can support up to [ 10] logic PT(s) 6|inst_UDS_000_INT|NOD| | S | 2 |=> can support up to [ 18] logic PT(s) 7| | ? | | S | |=> can support up to [ 9] logic PT(s) 8| UDS_000| IO| | S | 1 |=> can support up to [ 15] logic PT(s) 9| cpu_est_3_|NOD| | S | 4 |=> can support up to [ 19] logic PT(s) 10| | ? | | S | |=> can support up to [ 14] logic PT(s) 11| | ? | | S | |=> can support up to [ 14] logic PT(s) 12| LDS_000| IO| | S | 1 |=> can support up to [ 15] logic PT(s) 13| cpu_est_2_|NOD| | S | 1 :+: 1|=> can support up to [ 18] logic PT(s) 14| | ? | | S | |=> can support up to [ 10] logic PT(s) 15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 3] > Node-Pin Assignments =========================================================================== + Macrocell Number | Node Fixed(*)------+ | Sig Type---+ | to | Block [ 3] IO Pin | Device Pin | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ 0| VMA| IO| | => | 5 6 7 ( 0)| 30 29 28 ( 35) 1| BG_000| IO| | => | 5 ( 6) 7 0 | 30 ( 29) 28 35 2| CLK_000_D_3_|NOD| | => | 6 7 0 1 | 29 28 35 34 3| | | | => | 6 7 0 1 | 29 28 35 34 4|AMIGA_BUS_ENABLE_HIGH|OUT| | => | 7 0 ( 1) 2 | 28 35 ( 34) 33 5|AMIGA_ADDR_ENABLE|OUT| | => | 7 0 1 ( 2)| 28 35 34 ( 33) 6|inst_UDS_000_INT|NOD| | => | 0 1 2 3 | 35 34 33 32 7| | | | => | 0 1 2 3 | 35 34 33 32 8| UDS_000| IO| | => | 1 2 ( 3) 4 | 34 33 ( 32) 31 9| cpu_est_3_|NOD| | => | 1 2 3 4 | 34 33 32 31 10| | | | => | 2 3 4 5 | 33 32 31 30 11| | | | => | 2 3 4 5 | 33 32 31 30 12| LDS_000| IO| | => | 3 ( 4) 5 6 | 32 ( 31) 30 29 13| cpu_est_2_|NOD| | => | 3 4 5 6 | 32 31 30 29 14| | | | => | 4 5 6 7 | 31 30 29 28 15| | | | => | 4 5 6 7 | 31 30 29 28 --------------------------------------------------------------------------- =========================================================================== < Block [ 3] > IO-to-Node Pin Mapping =========================================================================== +- Block IO Pin | Device Pin No.--------+ | Pin Fixed(*)----+ | | Sig Type--+ | | | | Signal Name | | | | Node Destinations Via Output Matrix _|_________________|__|___|_____|___________________________________________ 0| VMA| IO|*| 35| => | ( 0) 1 2 3 4 5 6 7 1|AMIGA_BUS_ENABLE_HIGH|OUT|*| 34| => | 2 3 ( 4) 5 6 7 8 9 2|AMIGA_ADDR_ENABLE|OUT|*| 33| => | 4 ( 5) 6 7 8 9 10 11 3| UDS_000| IO|*| 32| => | 6 7 ( 8) 9 10 11 12 13 4| LDS_000| IO|*| 31| => | 8 9 10 11 (12) 13 14 15 5| DTACK|INP|*| 30| => | 10 11 12 13 14 15 0 1 6| BG_000| IO|*| 29| => | 12 13 14 15 0 ( 1) 2 3 7| BGACK_000|INP|*| 28| => | 14 15 0 1 2 3 4 5 --------------------------------------------------------------------------- =========================================================================== < Block [ 3] > IO/Node and IO/Input Macrocell Pairing Table =========================================================================== +- Block IO Pin | Device Pin No.--------+ | Pin Fixed(*)----+ | | Sig Type--+ | | | | Signal Name | | | | Input Macrocell and Node Pairs _|_________________|__|___|_____|__________________________________________ 0| VMA| IO|*| 35| => | Input macrocell [ -] | | | | | | IO paired w/ node [ RN_VMA] 1|AMIGA_BUS_ENABLE_HIGH|OUT|*| 34| => | Input macrocell [ -] 2|AMIGA_ADDR_ENABLE|OUT|*| 33| => | Input macrocell [ -] 3| UDS_000| IO|*| 32| => | Input macrocell [ -] 4| LDS_000| IO|*| 31| => | Input macrocell [ -] 5| DTACK|INP|*| 30| => | Input macrocell [ -] 6| BG_000| IO|*| 29| => | Input macrocell [ -] | | | | | | IO paired w/ node [ RN_BG_000] 7| BGACK_000|INP|*| 28| => | Input macrocell [ -] --------------------------------------------------------------------------- =========================================================================== < Block [ 3] > Input Multiplexer (IMX) Assignments =========================================================================== +----- IO pin/Input Register, or Macrocell IMX No. | +---- Block IO Pin or Macrocell Number | | | ABEL Node/ +-- Signal using the Pin or Macrocell | | | Pin Number | +- Signal Fixed (*) to Pin/Mcell | | | | Sig Type | | +- Feedback Required (*) ---|-------|----|---|---|----------|------|-|------------------------------ 0 [IOpin 0 | 35| IO VMA|*| ] paired w/[ RN_VMA] [RegIn 0 |174| -| | ] [MCell 0 |173|NOD RN_VMA| |*] paired w/[ VMA] [MCell 1 |175|NOD RN_BG_000| |*] paired w/[ BG_000] 1 [IOpin 1 | 34|OUT AMIGA_BUS_ENABLE_HIGH|*| ] [RegIn 1 |177| -| | ] [MCell 2 |176|NOD CLK_000_D_3_| |*] [MCell 3 |178| -| | ] 2 [IOpin 2 | 33|OUT AMIGA_ADDR_ENABLE|*| ] [RegIn 2 |180| -| | ] [MCell 4 |179|OUT AMIGA_BUS_ENABLE_HIGH| | ] [MCell 5 |181|OUT AMIGA_ADDR_ENABLE| | ] 3 [IOpin 3 | 32| IO UDS_000|*|*] [RegIn 3 |183| -| | ] [MCell 6 |182|NOD inst_UDS_000_INT| |*] [MCell 7 |184| -| | ] 4 [IOpin 4 | 31| IO LDS_000|*|*] [RegIn 4 |186| -| | ] [MCell 8 |185| IO UDS_000| | ] [MCell 9 |187|NOD cpu_est_3_| |*] 5 [IOpin 5 | 30|INP DTACK|*|*] [RegIn 5 |189| -| | ] [MCell 10 |188| -| | ] [MCell 11 |190| -| | ] 6 [IOpin 6 | 29| IO BG_000|*| ] paired w/[ RN_BG_000] [RegIn 6 |192| -| | ] [MCell 12 |191| IO LDS_000| | ] [MCell 13 |193|NOD cpu_est_2_| |*] 7 [IOpin 7 | 28|INP BGACK_000|*|*] [RegIn 7 |195| -| | ] [MCell 14 |194| -| | ] [MCell 15 |196| -| | ] --------------------------------------------------------------------------- =========================================================================== < Block [ 3] > Logic Array Fan-in =========================================================================== +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- Mux00| IOPin 6 4 ( 69)| A_0_ Mux01| Mcel 3 13 ( 193)| cpu_est_2_ Mux02| Mcel 4 9 ( 211)| inst_AMIGA_BUS_ENABLE_DMA_HIGH Mux03| Mcel 0 8 ( 113)| CLK_000_D_1_ Mux04| IOPin 2 6 ( 21)| BG_030 Mux05| Mcel 5 0 ( 221)| CLK_000_D_0_ Mux06| ... | ... Mux07| Mcel 3 9 ( 187)| cpu_est_3_ Mux08| ... | ... Mux09| IOPin 7 3 ( 82)| AS_030 Mux10| Mcel 5 4 ( 227)| cpu_est_0_ Mux11| Mcel 1 6 ( 134)| inst_VPA_D Mux12| ... | ... Mux13| ... | ... Mux14| Mcel 7 2 ( 272)| CLK_000_D_2_ Mux15| Input Pin ( 14)| nEXP_SPACE Mux16| Mcel 3 6 ( 182)| inst_UDS_000_INT Mux17| Mcel 3 1 ( 175)| RN_BG_000 Mux18| Mcel 3 0 ( 173)| RN_VMA Mux19| Mcel 0 9 ( 115)| inst_LDS_000_INT Mux20| Mcel 5 8 ( 233)| inst_AS_030_000_SYNC Mux21| Input Pin ( 86)| RST Mux22| Mcel 6 5 ( 253)| cpu_est_1_ Mux23| Mcel 7 4 ( 275)| RN_BGACK_030 Mux24| ... | ... Mux25| Mcel 0 13 ( 121)| inst_DS_000_ENABLE Mux26| ... | ... Mux27| ... | ... Mux28| Mcel 1 13 ( 145)| SM_AMIGA_6_ Mux29| ... | ... Mux30| ... | ... Mux31| Mcel 5 12 ( 239)| inst_AS_030_D0 Mux32| ... | ... --------------------------------------------------------------------------- =========================================================================== < Block [ 4] > Macrocell (MCell) Cluster Assignments =========================================================================== + Macrocell Number | PT Requirements------ Logic XOR+ +--- Macrocell PT Cluster Size | Sync/Async-------+ | | | Cluster to Mcell Assignment | Node Fixed(*)----+ | | | | | +- XOR PT Size | Sig Type-+ | | | | | | | XOR to Mcell Assignment | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| BERR| IO| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig 1|AMIGA_BUS_DATA_DIR|OUT| | S | 2 | 4 to [ 1]| 1 XOR free 2| | ? | | S | | 4 free | 1 XOR free 3| | ? | | S | | 4 free | 1 XOR free 4| AS_000| IO| | S | 1 | 4 free | 1 XOR to [ 4] for 1 PT sig 5| N_205|NOD| | S | 2 | 4 to [ 5]| 1 XOR free 6| | ? | | S | | 4 free | 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free 8|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | S | 4 | 4 to [ 8]| 1 XOR free 9|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | S | 2 | 4 to [ 9]| 1 XOR free 10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free 12| CIIN|OUT| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig 13|inst_BGACK_030_INT_D|NOD| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig 14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== < Block [ 4] > Maximum PT Capacity =========================================================================== + Macrocell Number | PT Requirements------ Logic XOR+ | Sync/Async-------+ | | | Node Fixed(*)----+ | | | | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ 0| BERR| IO| | S | 1 |=> can support up to [ 10] logic PT(s) 1|AMIGA_BUS_DATA_DIR|OUT| | S | 2 |=> can support up to [ 19] logic PT(s) 2| | ? | | S | |=> can support up to [ 14] logic PT(s) 3| | ? | | S | |=> can support up to [ 14] logic PT(s) 4| AS_000| IO| | S | 1 |=> can support up to [ 15] logic PT(s) 5| N_205|NOD| | S | 2 |=> can support up to [ 19] logic PT(s) 6| | ? | | S | |=> can support up to [ 10] logic PT(s) 7| | ? | | S | |=> can support up to [ 10] logic PT(s) 8|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | S | 4 |=> can support up to [ 15] logic PT(s) 9|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | S | 2 |=> can support up to [ 15] logic PT(s) 10| | ? | | S | |=> can support up to [ 14] logic PT(s) 11| | ? | | S | |=> can support up to [ 18] logic PT(s) 12| CIIN|OUT| | S | 1 |=> can support up to [ 19] logic PT(s) 13|inst_BGACK_030_INT_D|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) 14| | ? | | S | |=> can support up to [ 14] logic PT(s) 15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 4] > Node-Pin Assignments =========================================================================== + Macrocell Number | Node Fixed(*)------+ | Sig Type---+ | to | Block [ 4] IO Pin | Device Pin | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ 0| BERR| IO| | => | 5 6 7 ( 0)| 46 47 48 ( 41) 1|AMIGA_BUS_DATA_DIR|OUT| | => | 5 6 ( 7) 0 | 46 47 ( 48) 41 2| | | | => | 6 7 0 1 | 47 48 41 42 3| | | | => | 6 7 0 1 | 47 48 41 42 4| AS_000| IO| | => | 7 0 ( 1) 2 | 48 41 ( 42) 43 5| N_205|NOD| | => | 7 0 1 2 | 48 41 42 43 6| | | | => | 0 1 2 3 | 41 42 43 44 7| | | | => | 0 1 2 3 | 41 42 43 44 8|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | => | 1 2 3 4 | 42 43 44 45 9|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | => | 1 2 3 4 | 42 43 44 45 10| | | | => | 2 3 4 5 | 43 44 45 46 11| | | | => | 2 3 4 5 | 43 44 45 46 12| CIIN|OUT| | => | 3 4 5 ( 6)| 44 45 46 ( 47) 13|inst_BGACK_030_INT_D|NOD| | => | 3 4 5 6 | 44 45 46 47 14| | | | => | 4 5 6 7 | 45 46 47 48 15| | | | => | 4 5 6 7 | 45 46 47 48 --------------------------------------------------------------------------- =========================================================================== < Block [ 4] > IO-to-Node Pin Mapping =========================================================================== +- Block IO Pin | Device Pin No.--------+ | Pin Fixed(*)----+ | | Sig Type--+ | | | | Signal Name | | | | Node Destinations Via Output Matrix _|_________________|__|___|_____|___________________________________________ 0| BERR| IO|*| 41| => | ( 0) 1 2 3 4 5 6 7 1| AS_000| IO|*| 42| => | 2 3 ( 4) 5 6 7 8 9 2| | | | 43| => | 4 5 6 7 8 9 10 11 3| | | | 44| => | 6 7 8 9 10 11 12 13 4| | | | 45| => | 8 9 10 11 12 13 14 15 5| | | | 46| => | 10 11 12 13 14 15 0 1 6| CIIN|OUT|*| 47| => | (12) 13 14 15 0 1 2 3 7|AMIGA_BUS_DATA_DIR|OUT|*| 48| => | 14 15 0 ( 1) 2 3 4 5 --------------------------------------------------------------------------- =========================================================================== < Block [ 4] > IO/Node and IO/Input Macrocell Pairing Table =========================================================================== +- Block IO Pin | Device Pin No.--------+ | Pin Fixed(*)----+ | | Sig Type--+ | | | | Signal Name | | | | Input Macrocell and Node Pairs _|_________________|__|___|_____|__________________________________________ 0| BERR| IO|*| 41| => | Input macrocell [ -] 1| AS_000| IO|*| 42| => | Input macrocell [ -] 2| | | | 43| => | Input macrocell [ -] 3| | | | 44| => | Input macrocell [ -] 4| | | | 45| => | Input macrocell [ -] 5| | | | 46| => | Input macrocell [ -] 6| CIIN|OUT|*| 47| => | Input macrocell [ -] 7|AMIGA_BUS_DATA_DIR|OUT|*| 48| => | Input macrocell [ -] --------------------------------------------------------------------------- =========================================================================== < Block [ 4] > Input Multiplexer (IMX) Assignments =========================================================================== +----- IO pin/Input Register, or Macrocell IMX No. | +---- Block IO Pin or Macrocell Number | | | ABEL Node/ +-- Signal using the Pin or Macrocell | | | Pin Number | +- Signal Fixed (*) to Pin/Mcell | | | | Sig Type | | +- Feedback Required (*) ---|-------|----|---|---|----------|------|-|------------------------------ 0 [IOpin 0 | 41| IO BERR|*|*] [RegIn 0 |198| -| | ] [MCell 0 |197| IO BERR| | ] [MCell 1 |199|OUT AMIGA_BUS_DATA_DIR| | ] 1 [IOpin 1 | 42| IO AS_000|*|*] [RegIn 1 |201| -| | ] [MCell 2 |200| -| | ] [MCell 3 |202| -| | ] 2 [IOpin 2 | 43| -| | ] [RegIn 2 |204| -| | ] [MCell 4 |203| IO AS_000| | ] [MCell 5 |205|NOD N_205| |*] 3 [IOpin 3 | 44| -| | ] [RegIn 3 |207| -| | ] [MCell 6 |206| -| | ] [MCell 7 |208| -| | ] 4 [IOpin 4 | 45| -| | ] [RegIn 4 |210| -| | ] [MCell 8 |209|NOD inst_AMIGA_BUS_ENABLE_DMA_LOW| |*] [MCell 9 |211|NOD inst_AMIGA_BUS_ENABLE_DMA_HIGH| |*] 5 [IOpin 5 | 46| -| | ] [RegIn 5 |213| -| | ] [MCell 10 |212| -| | ] [MCell 11 |214| -| | ] 6 [IOpin 6 | 47|OUT CIIN|*| ] [RegIn 6 |216| -| | ] [MCell 12 |215|OUT CIIN| | ] [MCell 13 |217|NOD inst_BGACK_030_INT_D| |*] 7 [IOpin 7 | 48|OUT AMIGA_BUS_DATA_DIR|*| ] [RegIn 7 |219| -| | ] [MCell 14 |218| -| | ] [MCell 15 |220| -| | ] --------------------------------------------------------------------------- =========================================================================== < Block [ 4] > Logic Array Fan-in =========================================================================== +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- Mux00| Input Pin ( 86)| RST Mux01| IOPin 5 2 ( 58)| FC_1_ Mux02| IOPin 4 1 ( 42)| AS_000 Mux03| IOPin 2 1 ( 16)| AHIGH_27_ Mux04| IOPin 0 4 ( 95)| A_DECODE_18_ Mux05| IOPin 2 4 ( 19)| AHIGH_24_ Mux06| IOPin 0 5 ( 96)| A_DECODE_16_ Mux07| IOPin 2 0 ( 15)| AHIGH_28_ Mux08| IOPin 7 0 ( 85)| A_DECODE_23_ Mux09| IOPin 7 1 ( 84)| A_DECODE_22_ Mux10| ... | ... Mux11| IOPin 0 0 ( 91)| FPU_SENSE Mux12| IOPin 0 6 ( 97)| A_DECODE_19_ Mux13| IOPin 1 4 ( 6)| AHIGH_29_ Mux14| Mcel 4 5 ( 205)| N_205 Mux15| IOPin 0 3 ( 94)| A_DECODE_21_ Mux16| ... | ... Mux17| IOPin 0 2 ( 93)| A_DECODE_20_ Mux18| IOPin 3 7 ( 28)| BGACK_000 Mux19| IOPin 1 5 ( 5)| AHIGH_30_ Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 Mux21| Input Pin ( 14)| nEXP_SPACE Mux22| IOPin 2 3 ( 18)| AHIGH_25_ Mux23| IOPin 5 0 ( 60)| A_1_ Mux24| IOPin 5 3 ( 57)| FC_0_ Mux25| IOPin 1 6 ( 4)| AHIGH_31_ Mux26| IOPin 2 2 ( 17)| AHIGH_26_ Mux27| IOPin 5 1 ( 59)| A_DECODE_17_ Mux28| IOPin 7 5 ( 80)| RW_000 Mux29| ... | ... Mux30| Mcel 2 13 ( 169)| inst_AS_000_INT Mux31| Mcel 5 12 ( 239)| inst_AS_030_D0 Mux32| IOPin 7 3 ( 82)| AS_030 --------------------------------------------------------------------------- =========================================================================== < Block [ 5] > Macrocell (MCell) Cluster Assignments =========================================================================== + Macrocell Number | PT Requirements------ Logic XOR+ +--- Macrocell PT Cluster Size | Sync/Async-------+ | | | Cluster to Mcell Assignment | Node Fixed(*)----+ | | | | | +- XOR PT Size | Sig Type-+ | | | | | | | XOR to Mcell Assignment | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| CLK_000_D_0_|NOD| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig 1|inst_AS_030_D1|NOD| | S | 2 | 4 to [ 1]| 1 XOR free 2| | ? | | S | | 4 free | 1 XOR free 3| | ? | | S | | 4 free | 1 XOR free 4| cpu_est_0_|NOD| | S | 3 | 4 to [ 4]| 1 XOR free 5| CLK_000_D_4_|NOD| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig 6| | ? | | S | | 4 free | 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free 8|inst_AS_030_000_SYNC|NOD| | S | 7 | 4 to [ 8]| 1 XOR to [ 8] as logic PT 9| IPL_D0_0_|NOD| | S | 1 | 4 to [ 8]| 1 XOR to [ 9] for 1 PT sig 10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free 12|inst_AS_030_D0|NOD| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig 13| inst_DTACK_D0|NOD| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig 14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== < Block [ 5] > Maximum PT Capacity =========================================================================== + Macrocell Number | PT Requirements------ Logic XOR+ | Sync/Async-------+ | | | Node Fixed(*)----+ | | | | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ 0| CLK_000_D_0_|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) 1|inst_AS_030_D1|NOD| | S | 2 |=> can support up to [ 19] logic PT(s) 2| | ? | | S | |=> can support up to [ 10] logic PT(s) 3| | ? | | S | |=> can support up to [ 14] logic PT(s) 4| cpu_est_0_|NOD| | S | 3 |=> can support up to [ 19] logic PT(s) 5| CLK_000_D_4_|NOD| | S | 1 |=> can support up to [ 15] logic PT(s) 6| | ? | | S | |=> can support up to [ 14] logic PT(s) 7| | ? | | S | |=> can support up to [ 10] logic PT(s) 8|inst_AS_030_000_SYNC|NOD| | S | 7 |=> can support up to [ 19] logic PT(s) 9| IPL_D0_0_|NOD| | S | 1 |=> can support up to [ 11] logic PT(s) 10| | ? | | S | |=> can support up to [ 14] logic PT(s) 11| | ? | | S | |=> can support up to [ 18] logic PT(s) 12|inst_AS_030_D0|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) 13| inst_DTACK_D0|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) 14| | ? | | S | |=> can support up to [ 14] logic PT(s) 15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 5] > Node-Pin Assignments =========================================================================== + Macrocell Number | Node Fixed(*)------+ | Sig Type---+ | to | Block [ 5] IO Pin | Device Pin | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ 0| CLK_000_D_0_|NOD| | => | 5 6 7 0 | 55 54 53 60 1|inst_AS_030_D1|NOD| | => | 5 6 7 0 | 55 54 53 60 2| | | | => | 6 7 0 1 | 54 53 60 59 3| | | | => | 6 7 0 1 | 54 53 60 59 4| cpu_est_0_|NOD| | => | 7 0 1 2 | 53 60 59 58 5| CLK_000_D_4_|NOD| | => | 7 0 1 2 | 53 60 59 58 6| | | | => | 0 1 2 3 | 60 59 58 57 7| | | | => | 0 1 2 3 | 60 59 58 57 8|inst_AS_030_000_SYNC|NOD| | => | 1 2 3 4 | 59 58 57 56 9| IPL_D0_0_|NOD| | => | 1 2 3 4 | 59 58 57 56 10| | | | => | 2 3 4 5 | 58 57 56 55 11| | | | => | 2 3 4 5 | 58 57 56 55 12|inst_AS_030_D0|NOD| | => | 3 4 5 6 | 57 56 55 54 13| inst_DTACK_D0|NOD| | => | 3 4 5 6 | 57 56 55 54 14| | | | => | 4 5 6 7 | 56 55 54 53 15| | | | => | 4 5 6 7 | 56 55 54 53 --------------------------------------------------------------------------- =========================================================================== < Block [ 5] > IO-to-Node Pin Mapping =========================================================================== +- Block IO Pin | Device Pin No.--------+ | Pin Fixed(*)----+ | | Sig Type--+ | | | | Signal Name | | | | Node Destinations Via Output Matrix _|_________________|__|___|_____|___________________________________________ 0| A_1_|INP|*| 60| => | 0 1 2 3 4 5 6 7 1| A_DECODE_17_|INP|*| 59| => | 2 3 4 5 6 7 8 9 2| FC_1_|INP|*| 58| => | 4 5 6 7 8 9 10 11 3| FC_0_|INP|*| 57| => | 6 7 8 9 10 11 12 13 4| IPL_1_|INP|*| 56| => | 8 9 10 11 12 13 14 15 5| | | | 55| => | 10 11 12 13 14 15 0 1 6| | | | 54| => | 12 13 14 15 0 1 2 3 7| | | | 53| => | 14 15 0 1 2 3 4 5 --------------------------------------------------------------------------- =========================================================================== < Block [ 5] > IO/Node and IO/Input Macrocell Pairing Table =========================================================================== +- Block IO Pin | Device Pin No.--------+ | Pin Fixed(*)----+ | | Sig Type--+ | | | | Signal Name | | | | Input Macrocell and Node Pairs _|_________________|__|___|_____|__________________________________________ 0| A_1_|INP|*| 60| => | Input macrocell [ -] 1| A_DECODE_17_|INP|*| 59| => | Input macrocell [ -] 2| FC_1_|INP|*| 58| => | Input macrocell [ -] 3| FC_0_|INP|*| 57| => | Input macrocell [ -] 4| IPL_1_|INP|*| 56| => | Input macrocell [ -] 5| | | | 55| => | Input macrocell [ -] 6| | | | 54| => | Input macrocell [ -] 7| | | | 53| => | Input macrocell [ -] --------------------------------------------------------------------------- =========================================================================== < Block [ 5] > Input Multiplexer (IMX) Assignments =========================================================================== +----- IO pin/Input Register, or Macrocell IMX No. | +---- Block IO Pin or Macrocell Number | | | ABEL Node/ +-- Signal using the Pin or Macrocell | | | Pin Number | +- Signal Fixed (*) to Pin/Mcell | | | | Sig Type | | +- Feedback Required (*) ---|-------|----|---|---|----------|------|-|------------------------------ 0 [IOpin 0 | 60|INP A_1_|*|*] [RegIn 0 |222| -| | ] [MCell 0 |221|NOD CLK_000_D_0_| |*] [MCell 1 |223|NOD inst_AS_030_D1| |*] 1 [IOpin 1 | 59|INP A_DECODE_17_|*|*] [RegIn 1 |225| -| | ] [MCell 2 |224| -| | ] [MCell 3 |226| -| | ] 2 [IOpin 2 | 58|INP FC_1_|*|*] [RegIn 2 |228| -| | ] [MCell 4 |227|NOD cpu_est_0_| |*] [MCell 5 |229|NOD CLK_000_D_4_| |*] 3 [IOpin 3 | 57|INP FC_0_|*|*] [RegIn 3 |231| -| | ] [MCell 6 |230| -| | ] [MCell 7 |232| -| | ] 4 [IOpin 4 | 56|INP IPL_1_|*|*] [RegIn 4 |234| -| | ] [MCell 8 |233|NOD inst_AS_030_000_SYNC| |*] [MCell 9 |235|NOD IPL_D0_0_| |*] 5 [IOpin 5 | 55| -| | ] [RegIn 5 |237| -| | ] [MCell 10 |236| -| | ] [MCell 11 |238| -| | ] 6 [IOpin 6 | 54| -| | ] [RegIn 6 |240| -| | ] [MCell 12 |239|NOD inst_AS_030_D0| |*] [MCell 13 |241|NOD inst_DTACK_D0| |*] 7 [IOpin 7 | 53| -| | ] [RegIn 7 |243| -| | ] [MCell 14 |242| -| | ] [MCell 15 |244| -| | ] --------------------------------------------------------------------------- =========================================================================== < Block [ 5] > Logic Array Fan-in =========================================================================== +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- Mux00| IOPin 6 2 ( 67)| IPL_0_ Mux01| IOPin 5 2 ( 58)| FC_1_ Mux02| Mcel 4 13 ( 217)| inst_BGACK_030_INT_D Mux03| Input Pin ( 11)| CLK_000 Mux04| IOPin 0 4 ( 95)| A_DECODE_18_ Mux05| Input Pin ( 14)| nEXP_SPACE Mux06| IOPin 5 3 ( 57)| FC_0_ Mux07| ... | ... Mux08| IOPin 5 1 ( 59)| A_DECODE_17_ Mux09| IOPin 3 5 ( 30)| DTACK Mux10| Mcel 5 1 ( 223)| inst_AS_030_D1 Mux11| IOPin 0 5 ( 96)| A_DECODE_16_ Mux12| IOPin 0 6 ( 97)| A_DECODE_19_ Mux13| ... | ... Mux14| Mcel 5 4 ( 227)| cpu_est_0_ Mux15| ... | ... Mux16| Mcel 3 2 ( 176)| CLK_000_D_3_ Mux17| Mcel 5 12 ( 239)| inst_AS_030_D0 Mux18| Mcel 1 2 ( 128)| SM_AMIGA_i_7_ Mux19| IOPin 7 3 ( 82)| AS_030 Mux20| Mcel 5 8 ( 233)| inst_AS_030_000_SYNC Mux21| Input Pin ( 86)| RST Mux22| ... | ... Mux23| Mcel 7 4 ( 275)| RN_BGACK_030 Mux24| ... | ... Mux25| Mcel 5 0 ( 221)| CLK_000_D_0_ Mux26| ... | ... Mux27| ... | ... Mux28| ... | ... Mux29| ... | ... Mux30| Mcel 0 8 ( 113)| CLK_000_D_1_ Mux31| ... | ... Mux32| ... | ... --------------------------------------------------------------------------- =========================================================================== < Block [ 6] > Macrocell (MCell) Cluster Assignments =========================================================================== + Macrocell Number | PT Requirements------ Logic XOR+ +--- Macrocell PT Cluster Size | Sync/Async-------+ | | | Cluster to Mcell Assignment | Node Fixed(*)----+ | | | | | +- XOR PT Size | Sig Type-+ | | | | | | | XOR to Mcell Assignment | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| RW| IO| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig 1| CLK_DIV_OUT|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig 2|inst_DSACK1_INT|NOD| | S | 2 | 4 to [ 2]| 1 XOR free 3| | ? | | S | | 4 free | 1 XOR free 4| E|OUT| | S | 2 | 4 to [ 4]| 1 XOR free 5| cpu_est_1_|NOD| | S | 4 | 4 to [ 5]| 1 XOR free 6| CYCLE_DMA_0_|NOD| | S | 4 | 4 to [ 6]| 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free 8| A_0_| IO| | S | 2 | 4 to [ 8]| 1 XOR free 9|inst_DS_000_DMA|NOD| | S | 6 | 4 to [ 9]| 1 XOR to [ 9] as logic PT 10| CYCLE_DMA_1_|NOD| | S | 2 | 4 to [10]| 1 XOR free 11| | ? | | S | | 4 to [ 9]| 1 XOR free 12| SIZE_0_| IO| | S | 2 | 4 to [12]| 1 XOR free 13|inst_AS_000_DMA|NOD| | S | 6 | 4 to [13]| 1 XOR to [13] as logic PT 14| | ? | | S | | 4 to [13]| 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== < Block [ 6] > Maximum PT Capacity =========================================================================== + Macrocell Number | PT Requirements------ Logic XOR+ | Sync/Async-------+ | | | Node Fixed(*)----+ | | | | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ 0| RW| IO| | S | 1 |=> can support up to [ 9] logic PT(s) 1| CLK_DIV_OUT|OUT| | S | 1 |=> can support up to [ 14] logic PT(s) 2|inst_DSACK1_INT|NOD| | S | 2 |=> can support up to [ 14] logic PT(s) 3| | ? | | S | |=> can support up to [ 5] logic PT(s) 4| E|OUT| | S | 2 |=> can support up to [ 10] logic PT(s) 5| cpu_est_1_|NOD| | S | 4 |=> can support up to [ 10] logic PT(s) 6| CYCLE_DMA_0_|NOD| | S | 4 |=> can support up to [ 10] logic PT(s) 7| | ? | | S | |=> can support up to [ 5] logic PT(s) 8| A_0_| IO| | S | 2 |=> can support up to [ 10] logic PT(s) 9|inst_DS_000_DMA|NOD| | S | 6 |=> can support up to [ 10] logic PT(s) 10| CYCLE_DMA_1_|NOD| | S | 2 |=> can support up to [ 5] logic PT(s) 11| | ? | | S | |=> can support up to [ 1] logic PT(s) 12| SIZE_0_| IO| | S | 2 |=> can support up to [ 5] logic PT(s) 13|inst_AS_000_DMA|NOD| | S | 6 |=> can support up to [ 15] logic PT(s) 14| | ? | | S | |=> can support up to [ 6] logic PT(s) 15| | ? | | S | |=> can support up to [ 5] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 6] > Node-Pin Assignments =========================================================================== + Macrocell Number | Node Fixed(*)------+ | Sig Type---+ | to | Block [ 6] IO Pin | Device Pin | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ 0| RW| IO| | => | 5 ( 6) 7 0 | 70 ( 71) 72 65 1| CLK_DIV_OUT|OUT| | => | 5 6 7 ( 0)| 70 71 72 ( 65) 2|inst_DSACK1_INT|NOD| | => | 6 7 0 1 | 71 72 65 66 3| | | | => | 6 7 0 1 | 71 72 65 66 4| E|OUT| | => | 7 0 ( 1) 2 | 72 65 ( 66) 67 5| cpu_est_1_|NOD| | => | 7 0 1 2 | 72 65 66 67 6| CYCLE_DMA_0_|NOD| | => | 0 1 2 3 | 65 66 67 68 7| | | | => | 0 1 2 3 | 65 66 67 68 8| A_0_| IO| | => | 1 2 3 ( 4)| 66 67 68 ( 69) 9|inst_DS_000_DMA|NOD| | => | 1 2 3 4 | 66 67 68 69 10| CYCLE_DMA_1_|NOD| | => | 2 3 4 5 | 67 68 69 70 11| | | | => | 2 3 4 5 | 67 68 69 70 12| SIZE_0_| IO| | => | 3 4 ( 5) 6 | 68 69 ( 70) 71 13|inst_AS_000_DMA|NOD| | => | 3 4 5 6 | 68 69 70 71 14| | | | => | 4 5 6 7 | 69 70 71 72 15| | | | => | 4 5 6 7 | 69 70 71 72 --------------------------------------------------------------------------- =========================================================================== < Block [ 6] > IO-to-Node Pin Mapping =========================================================================== +- Block IO Pin | Device Pin No.--------+ | Pin Fixed(*)----+ | | Sig Type--+ | | | | Signal Name | | | | Node Destinations Via Output Matrix _|_________________|__|___|_____|___________________________________________ 0| CLK_DIV_OUT|OUT|*| 65| => | 0 ( 1) 2 3 4 5 6 7 1| E|OUT|*| 66| => | 2 3 ( 4) 5 6 7 8 9 2| IPL_0_|INP|*| 67| => | 4 5 6 7 8 9 10 11 3| IPL_2_|INP|*| 68| => | 6 7 8 9 10 11 12 13 4| A_0_| IO|*| 69| => | ( 8) 9 10 11 12 13 14 15 5| SIZE_0_| IO|*| 70| => | 10 11 (12) 13 14 15 0 1 6| RW| IO|*| 71| => | 12 13 14 15 ( 0) 1 2 3 7| | | | 72| => | 14 15 0 1 2 3 4 5 --------------------------------------------------------------------------- =========================================================================== < Block [ 6] > IO/Node and IO/Input Macrocell Pairing Table =========================================================================== +- Block IO Pin | Device Pin No.--------+ | Pin Fixed(*)----+ | | Sig Type--+ | | | | Signal Name | | | | Input Macrocell and Node Pairs _|_________________|__|___|_____|__________________________________________ 0| CLK_DIV_OUT|OUT|*| 65| => | Input macrocell [ -] 1| E|OUT|*| 66| => | Input macrocell [ -] 2| IPL_0_|INP|*| 67| => | Input macrocell [ -] 3| IPL_2_|INP|*| 68| => | Input macrocell [ -] 4| A_0_| IO|*| 69| => | Input macrocell [ -] 5| SIZE_0_| IO|*| 70| => | Input macrocell [ -] 6| RW| IO|*| 71| => | Input macrocell [ -] 7| | | | 72| => | Input macrocell [ -] --------------------------------------------------------------------------- =========================================================================== < Block [ 6] > Input Multiplexer (IMX) Assignments =========================================================================== +----- IO pin/Input Register, or Macrocell IMX No. | +---- Block IO Pin or Macrocell Number | | | ABEL Node/ +-- Signal using the Pin or Macrocell | | | Pin Number | +- Signal Fixed (*) to Pin/Mcell | | | | Sig Type | | +- Feedback Required (*) ---|-------|----|---|---|----------|------|-|------------------------------ 0 [IOpin 0 | 65|OUT CLK_DIV_OUT|*| ] [RegIn 0 |246| -| | ] [MCell 0 |245| IO RW| | ] [MCell 1 |247|OUT CLK_DIV_OUT| | ] 1 [IOpin 1 | 66|OUT E|*| ] [RegIn 1 |249| -| | ] [MCell 2 |248|NOD inst_DSACK1_INT| |*] [MCell 3 |250| -| | ] 2 [IOpin 2 | 67|INP IPL_0_|*|*] [RegIn 2 |252| -| | ] [MCell 4 |251|OUT E| | ] [MCell 5 |253|NOD cpu_est_1_| |*] 3 [IOpin 3 | 68|INP IPL_2_|*|*] [RegIn 3 |255| -| | ] [MCell 6 |254|NOD CYCLE_DMA_0_| |*] [MCell 7 |256| -| | ] 4 [IOpin 4 | 69| IO A_0_|*|*] [RegIn 4 |258| -| | ] [MCell 8 |257| IO A_0_| | ] [MCell 9 |259|NOD inst_DS_000_DMA| |*] 5 [IOpin 5 | 70| IO SIZE_0_|*|*] [RegIn 5 |261| -| | ] [MCell 10 |260|NOD CYCLE_DMA_1_| |*] [MCell 11 |262| -| | ] 6 [IOpin 6 | 71| IO RW|*|*] [RegIn 6 |264| -| | ] [MCell 12 |263| IO SIZE_0_| | ] [MCell 13 |265|NOD inst_AS_000_DMA| |*] 7 [IOpin 7 | 72| -| | ] [RegIn 7 |267| -| | ] [MCell 14 |266| -| | ] [MCell 15 |268| -| | ] --------------------------------------------------------------------------- =========================================================================== < Block [ 6] > Logic Array Fan-in =========================================================================== +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- Mux00| Mcel 0 2 ( 104)| CLK_OUT_INTreg Mux01| Mcel 3 13 ( 193)| cpu_est_2_ Mux02| IOPin 4 1 ( 42)| AS_000 Mux03| Mcel 6 5 ( 253)| cpu_est_1_ Mux04| Mcel 7 5 ( 277)| inst_CLK_OUT_PRE_D Mux05| Mcel 5 0 ( 221)| CLK_000_D_0_ Mux06| IOPin 7 5 ( 80)| RW_000 Mux07| Mcel 7 13 ( 289)| inst_AMIGA_DS Mux08| IOPin 3 3 ( 32)| UDS_000 Mux09| Mcel 0 1 ( 103)| SM_AMIGA_1_ Mux10| Mcel 6 9 ( 259)| inst_DS_000_DMA Mux11| ... | ... Mux12| Mcel 6 13 ( 265)| inst_AS_000_DMA Mux13| ... | ... Mux14| Mcel 5 4 ( 227)| cpu_est_0_ Mux15| ... | ... Mux16| ... | ... Mux17| ... | ... Mux18| Mcel 0 8 ( 113)| CLK_000_D_1_ Mux19| IOPin 7 3 ( 82)| AS_030 Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 Mux21| Input Pin ( 86)| RST Mux22| Mcel 6 10 ( 260)| CYCLE_DMA_1_ Mux23| Mcel 6 6 ( 254)| CYCLE_DMA_0_ Mux24| IOPin 3 4 ( 31)| LDS_000 Mux25| Mcel 3 9 ( 187)| cpu_est_3_ Mux26| ... | ... Mux27| ... | ... Mux28| ... | ... Mux29| ... | ... Mux30| ... | ... Mux31| Mcel 6 2 ( 248)| inst_DSACK1_INT Mux32| ... | ... --------------------------------------------------------------------------- =========================================================================== < Block [ 7] > Macrocell (MCell) Cluster Assignments =========================================================================== + Macrocell Number | PT Requirements------ Logic XOR+ +--- Macrocell PT Cluster Size | Sync/Async-------+ | | | Cluster to Mcell Assignment | Node Fixed(*)----+ | | | | | +- XOR PT Size | Sig Type-+ | | | | | | | XOR to Mcell Assignment | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| RW_000| IO| | S | 4 | 4 to [ 0]| 1 XOR free 1| FPU_CS|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig 2| CLK_000_D_2_|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig 3| | ? | | S | | 4 free | 1 XOR free 4| BGACK_030| IO| | S | 3 | 4 to [ 4]| 1 XOR free 5|inst_CLK_OUT_PRE_D|NOD| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig 6|inst_CLK_OUT_PRE_50|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig 7| | ? | | S | | 4 free | 1 XOR free 8| AS_030| IO| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig 9| DSACK1|OUT| | S | 1 | 4 free | 1 XOR to [ 9] for 1 PT sig 10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free 12| SIZE_1_| IO| | S | 2 | 4 to [12]| 1 XOR free 13| inst_AMIGA_DS|NOD| | S | 2 | 4 to [13]| 1 XOR free 14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== < Block [ 7] > Maximum PT Capacity =========================================================================== + Macrocell Number | PT Requirements------ Logic XOR+ | Sync/Async-------+ | | | Node Fixed(*)----+ | | | | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ 0| RW_000| IO| | S | 4 |=> can support up to [ 13] logic PT(s) 1| FPU_CS|OUT| | S | 1 |=> can support up to [ 14] logic PT(s) 2| CLK_000_D_2_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) 3| | ? | | S | |=> can support up to [ 13] logic PT(s) 4| BGACK_030| IO| | S | 3 |=> can support up to [ 18] logic PT(s) 5|inst_CLK_OUT_PRE_D|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) 6|inst_CLK_OUT_PRE_50|NOD| | S | 1 |=> can support up to [ 18] logic PT(s) 7| | ? | | S | |=> can support up to [ 17] logic PT(s) 8| AS_030| IO| | S | 1 |=> can support up to [ 19] logic PT(s) 9| DSACK1|OUT| | S | 1 |=> can support up to [ 19] logic PT(s) 10| | ? | | S | |=> can support up to [ 14] logic PT(s) 11| | ? | | S | |=> can support up to [ 10] logic PT(s) 12| SIZE_1_| IO| | S | 2 |=> can support up to [ 15] logic PT(s) 13| inst_AMIGA_DS|NOD| | S | 2 |=> can support up to [ 15] logic PT(s) 14| | ? | | S | |=> can support up to [ 10] logic PT(s) 15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 7] > Node-Pin Assignments =========================================================================== + Macrocell Number | Node Fixed(*)------+ | Sig Type---+ | to | Block [ 7] IO Pin | Device Pin | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ 0| RW_000| IO| | => |( 5) 6 7 0 |( 80) 79 78 85 1| FPU_CS|OUT| | => | 5 6 ( 7) 0 | 80 79 ( 78) 85 2| CLK_000_D_2_|NOD| | => | 6 7 0 1 | 79 78 85 84 3| | | | => | 6 7 0 1 | 79 78 85 84 4| BGACK_030| IO| | => | 7 0 1 ( 2)| 78 85 84 ( 83) 5|inst_CLK_OUT_PRE_D|NOD| | => | 7 0 1 2 | 78 85 84 83 6|inst_CLK_OUT_PRE_50|NOD| | => | 0 1 2 3 | 85 84 83 82 7| | | | => | 0 1 2 3 | 85 84 83 82 8| AS_030| IO| | => | 1 2 ( 3) 4 | 84 83 ( 82) 81 9| DSACK1|OUT| | => | 1 2 3 ( 4)| 84 83 82 ( 81) 10| | | | => | 2 3 4 5 | 83 82 81 80 11| | | | => | 2 3 4 5 | 83 82 81 80 12| SIZE_1_| IO| | => | 3 4 5 ( 6)| 82 81 80 ( 79) 13| inst_AMIGA_DS|NOD| | => | 3 4 5 6 | 82 81 80 79 14| | | | => | 4 5 6 7 | 81 80 79 78 15| | | | => | 4 5 6 7 | 81 80 79 78 --------------------------------------------------------------------------- =========================================================================== < Block [ 7] > IO-to-Node Pin Mapping =========================================================================== +- Block IO Pin | Device Pin No.--------+ | Pin Fixed(*)----+ | | Sig Type--+ | | | | Signal Name | | | | Node Destinations Via Output Matrix _|_________________|__|___|_____|___________________________________________ 0| A_DECODE_23_|INP|*| 85| => | 0 1 2 3 4 5 6 7 1| A_DECODE_22_|INP|*| 84| => | 2 3 4 5 6 7 8 9 2| BGACK_030| IO|*| 83| => | ( 4) 5 6 7 8 9 10 11 3| AS_030| IO|*| 82| => | 6 7 ( 8) 9 10 11 12 13 4| DSACK1|OUT|*| 81| => | 8 ( 9) 10 11 12 13 14 15 5| RW_000| IO|*| 80| => | 10 11 12 13 14 15 ( 0) 1 6| SIZE_1_| IO|*| 79| => | (12) 13 14 15 0 1 2 3 7| FPU_CS|OUT|*| 78| => | 14 15 0 ( 1) 2 3 4 5 --------------------------------------------------------------------------- =========================================================================== < Block [ 7] > IO/Node and IO/Input Macrocell Pairing Table =========================================================================== +- Block IO Pin | Device Pin No.--------+ | Pin Fixed(*)----+ | | Sig Type--+ | | | | Signal Name | | | | Input Macrocell and Node Pairs _|_________________|__|___|_____|__________________________________________ 0| A_DECODE_23_|INP|*| 85| => | Input macrocell [ -] 1| A_DECODE_22_|INP|*| 84| => | Input macrocell [ -] 2| BGACK_030| IO|*| 83| => | Input macrocell [ -] | | | | | | IO paired w/ node [ RN_BGACK_030] 3| AS_030| IO|*| 82| => | Input macrocell [ -] 4| DSACK1|OUT|*| 81| => | Input macrocell [ -] 5| RW_000| IO|*| 80| => | Input macrocell [ -] | | | | | | IO paired w/ node [ RN_RW_000] 6| SIZE_1_| IO|*| 79| => | Input macrocell [ -] 7| FPU_CS|OUT|*| 78| => | Input macrocell [ -] --------------------------------------------------------------------------- =========================================================================== < Block [ 7] > Input Multiplexer (IMX) Assignments =========================================================================== +----- IO pin/Input Register, or Macrocell IMX No. | +---- Block IO Pin or Macrocell Number | | | ABEL Node/ +-- Signal using the Pin or Macrocell | | | Pin Number | +- Signal Fixed (*) to Pin/Mcell | | | | Sig Type | | +- Feedback Required (*) ---|-------|----|---|---|----------|------|-|------------------------------ 0 [IOpin 0 | 85|INP A_DECODE_23_|*|*] [RegIn 0 |270| -| | ] [MCell 0 |269|NOD RN_RW_000| |*] paired w/[ RW_000] [MCell 1 |271|OUT FPU_CS| | ] 1 [IOpin 1 | 84|INP A_DECODE_22_|*|*] [RegIn 1 |273| -| | ] [MCell 2 |272|NOD CLK_000_D_2_| |*] [MCell 3 |274| -| | ] 2 [IOpin 2 | 83| IO BGACK_030|*| ] paired w/[ RN_BGACK_030] [RegIn 2 |276| -| | ] [MCell 4 |275|NOD RN_BGACK_030| |*] paired w/[ BGACK_030] [MCell 5 |277|NOD inst_CLK_OUT_PRE_D| |*] 3 [IOpin 3 | 82| IO AS_030|*|*] [RegIn 3 |279| -| | ] [MCell 6 |278|NOD inst_CLK_OUT_PRE_50| |*] [MCell 7 |280| -| | ] 4 [IOpin 4 | 81|OUT DSACK1|*| ] [RegIn 4 |282| -| | ] [MCell 8 |281| IO AS_030| | ] [MCell 9 |283|OUT DSACK1| | ] 5 [IOpin 5 | 80| IO RW_000|*|*] paired w/[ RN_RW_000] [RegIn 5 |285| -| | ] [MCell 10 |284| -| | ] [MCell 11 |286| -| | ] 6 [IOpin 6 | 79| IO SIZE_1_|*|*] [RegIn 6 |288| -| | ] [MCell 12 |287| IO SIZE_1_| | ] [MCell 13 |289|NOD inst_AMIGA_DS| |*] 7 [IOpin 7 | 78|OUT FPU_CS|*| ] [RegIn 7 |291| -| | ] [MCell 14 |290| -| | ] [MCell 15 |292| -| | ] --------------------------------------------------------------------------- =========================================================================== < Block [ 7] > Logic Array Fan-in =========================================================================== +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- Mux00| IOPin 3 4 ( 31)| LDS_000 Mux01| IOPin 5 2 ( 58)| FC_1_ Mux02| IOPin 4 1 ( 42)| AS_000 Mux03| Mcel 0 8 ( 113)| CLK_000_D_1_ Mux04| IOPin 3 7 ( 28)| BGACK_000 Mux05| Mcel 5 0 ( 221)| CLK_000_D_0_ Mux06| IOPin 0 6 ( 97)| A_DECODE_19_ Mux07| Mcel 7 6 ( 278)| inst_CLK_OUT_PRE_50 Mux08| IOPin 6 6 ( 71)| RW Mux09| IOPin 7 3 ( 82)| AS_030 Mux10| Mcel 1 13 ( 145)| SM_AMIGA_6_ Mux11| IOPin 0 5 ( 96)| A_DECODE_16_ Mux12| IOPin 3 3 ( 32)| UDS_000 Mux13| IOPin 5 1 ( 59)| A_DECODE_17_ Mux14| ... | ... Mux15| Input Pin ( 14)| nEXP_SPACE Mux16| ... | ... Mux17| IOPin 5 3 ( 57)| FC_0_ Mux18| Mcel 1 2 ( 128)| SM_AMIGA_i_7_ Mux19| IOPin 0 0 ( 91)| FPU_SENSE Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 Mux21| Input Pin ( 86)| RST Mux22| ... | ... Mux23| Mcel 6 2 ( 248)| inst_DSACK1_INT Mux24| Mcel 0 12 ( 119)| SM_AMIGA_0_ Mux25| Mcel 6 13 ( 265)| inst_AS_000_DMA Mux26| ... | ... Mux27| ... | ... Mux28| ... | ... Mux29| ... | ... Mux30| Mcel 7 0 ( 269)| RN_RW_000 Mux31| IOPin 0 4 ( 95)| A_DECODE_18_ Mux32| ... | ... ---------------------------------------------------------------------------