|--------------------------------------------| |- ispLEVER Fitter Report File -| |- Version 1.7.00.05.28.13 -| |- (c)Copyright, Lattice Semiconductor 2002 -| |--------------------------------------------| Project_Summary ~~~~~~~~~~~~~~~ Project Name : 68030_tk Project Path : C:\Users\Matze\Documents\GitHub\68030tk\Logic Project Fitted on : Sat Jun 07 23:03:24 2014 Device : M4A5-128/64 Package : 100TQFP Speed : -10 Partnumber : M4A5-128/64-10VC Source Format : Pure_VHDL // Project '68030_tk' was Fitted Successfully! // Compilation_Times ~~~~~~~~~~~~~~~~~ Reading/DRC 0 sec Partition 0 sec Place 0 sec Route 0 sec Jedec/Report generation 0 sec -------- Fitter 00:00:00 Design_Summary ~~~~~~~~~~~~~~ Total Input Pins : 29 Total Output Pins : 18 Total Bidir I/O Pins : 12 Total Flip-Flops : 44 Total Product Terms : 146 Total Reserved Pins : 0 Total Reserved Blocks : 0 Device_Resource_Summary ~~~~~~~~~~~~~~~~~~~~~~~ Total Available Used Available Utilization Dedicated Pins Input-Only Pins 2 2 0 --> 100% Clock/Input Pins 4 4 0 --> 100% I/O Pins 64 53 11 --> 82% Logic Macrocells 128 54 74 --> 42% Input Registers 64 0 64 --> 0% Unusable Macrocells .. 0 .. CSM Outputs/Total Block Inputs 264 147 117 --> 55% Logical Product Terms 640 149 491 --> 23% Product Term Clusters 128 40 88 --> 31%  Blocks_Resource_Summary ~~~~~~~~~~~~~~~~~~~~~~~ # of PT I/O Inp Macrocells Macrocells logic clusters Fanin Pins Reg Used Unusable available PTs available Pwr --------------------------------------------------------------------------------- Maximum 33 8 8 -- -- 16 80 16 - --------------------------------------------------------------------------------- Block A 23 7 0 6 0 10 18 11 Hi Block B 22 8 0 10 0 6 23 10 Hi Block C 1 8 0 2 0 14 2 16 Hi Block D 29 8 0 12 0 4 41 4 Hi Block E 17 3 0 3 0 13 4 15 Hi Block F 0 4 0 0 0 16 0 16 Hi Block G 27 7 0 8 0 8 30 9 Hi Block H 28 8 0 13 0 3 31 7 Hi --------------------------------------------------------------------------------- Four rightmost columns above reflect last status of the placement process. Pwr (Power) : Hi = High Lo = Low.  Optimizer_and_Fitter_Options ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Pin Assignment : Yes Group Assignment : No Pin Reservation : No (1) Block Reservation : No @Ignore_Project_Constraints : Pin Assignments : No Keep Block Assignment -- Keep Segment Assignment -- Group Assignments : No Macrocell Assignment : No Keep Block Assignment -- Keep Segment Assignment -- @Backannotate_Project_Constraints Pin Assignments : No Pin And Block Assignments : No Pin, Macrocell and Block : No @Timing_Constraints : No @Global_Project_Optimization : Balanced Partitioning : No Spread Placement : No Note : Pack Design : Balanced Partitioning = No Spread Placement = No Spread Design : Balanced Partitioning = Yes Spread Placement = Yes @Logic_Synthesis : Logic Reduction : Yes Node Collapsing : Yes D/T Synthesis : Yes Clock Optimization : No Input Register Optimization : Yes XOR Synthesis : Yes Max. P-Term for Collapsing : 16 Max. P-Term for Splitting : 16 Max. Equation Fanin : 32 Keep Xor : Yes @Utilization_options Max. % of macrocells used : 100 Max. % of block inputs used : 100 Max. % of segment lines used : --- Max. % of macrocells used : --- @Import_Source_Constraint_Option No @Zero_Hold_Time Yes @Pull_up Yes @User_Signature #H0 @Output_Slew_Rate Default = Slow(2) @Power Default = High(2) Device Options: 1 : Reserved unused I/Os can be independently driven to Low or High, and does not follow the drive level set for the Global Configure Unused I/O Option. 2 : For user-specified constraints on individual signals, refer to the Output, Bidir and Burried Signal Lists.  Pinout_Listing ~~~~~~~~~~~~~~ | Pin |Blk |Assigned| Pin No| Type |Pad |Pin | Signal name --------------------------------------------------------------- 1 | GND | | | 2 | JTAG | | | 3 | I_O | B7 | * |RESET 4 | I_O | B6 | * |A_31_ 5 | I_O | B5 | * |A_30_ 6 | I_O | B4 | * |A_29_ 7 | I_O | B3 | * |IPL_030_1_ 8 | I_O | B2 | * |IPL_030_0_ 9 | I_O | B1 | * |IPL_030_2_ 10 | I_O | B0 | * |CLK_EXP 11 | CkIn | | * |CLK_000 12 | Vcc | | | 13 | GND | | | 14 | CkIn | | * |nEXP_SPACE 15 | I_O | C0 | * |A_28_ 16 | I_O | C1 | * |A_27_ 17 | I_O | C2 | * |A_26_ 18 | I_O | C3 | * |A_25_ 19 | I_O | C4 | * |A_24_ 20 | I_O | C5 | * |AMIGA_BUS_ENABLE_LOW 21 | I_O | C6 | * |BG_030 22 | I_O | C7 | * |AVEC_EXP 23 | JTAG | | | 24 | JTAG | | | 25 | GND | | | 26 | GND | | | 27 | GND | | | 28 | I_O | D7 | * |BGACK_000 29 | I_O | D6 | * |BG_000 30 | I_O | D5 | * |DTACK 31 | I_O | D4 | * |LDS_000 32 | I_O | D3 | * |UDS_000 33 | I_O | D2 | * |AS_000 34 | I_O | D1 | * |AMIGA_BUS_ENABLE 35 | I_O | D0 | * |VMA 36 | Inp | | * |VPA 37 | Vcc | | | 38 | GND | | | 39 | GND | | | 40 | Vcc | | | 41 | I_O | E0 | * |BERR 42 | I_O | E1 | | 43 | I_O | E2 | | 44 | I_O | E3 | | 45 | I_O | E4 | | 46 | I_O | E5 | | 47 | I_O | E6 | * |CIIN 48 | I_O | E7 | * |AMIGA_BUS_DATA_DIR 49 | GND | | | 50 | GND | | | 51 | GND | | | 52 | JTAG | | | 53 | I_O | F7 | | 54 | I_O | F6 | | 55 | I_O | F5 | | 56 | I_O | F4 | * |IPL_1_ 57 | I_O | F3 | * |FC_0_ 58 | I_O | F2 | * |FC_1_ 59 | I_O | F1 | * |A_17_ 60 | I_O | F0 | | 61 | CkIn | | * |CLK_OSZI 62 | Vcc | | | 63 | GND | | | 64 | CkIn | | * |CLK_030 65 | I_O | G0 | * |CLK_DIV_OUT 66 | I_O | G1 | * |E 67 | I_O | G2 | * |IPL_0_ 68 | I_O | G3 | * |IPL_2_ 69 | I_O | G4 | * |A0 70 | I_O | G5 | * |SIZE_0_ 71 | I_O | G6 | * |RW 72 | I_O | G7 | | 73 | JTAG | | | 74 | JTAG | | | 75 | GND | | | 76 | GND | | | 77 | GND | | | 78 | I_O | H7 | * |FPU_CS 79 | I_O | H6 | * |SIZE_1_ 80 | I_O | H5 | * |RW_000 81 | I_O | H4 | * |DSACK1 82 | I_O | H3 | * |AS_030 83 | I_O | H2 | * |BGACK_030 84 | I_O | H1 | * |A_23_ 85 | I_O | H0 | * |A_22_ 86 | Inp | | * |RST 87 | Vcc | | | 88 | GND | | | 89 | GND | | | 90 | Vcc | | | 91 | I_O | A0 | | 92 | I_O | A1 | * |AVEC 93 | I_O | A2 | * |A_20_ 94 | I_O | A3 | * |A_21_ 95 | I_O | A4 | * |A_18_ 96 | I_O | A5 | * |A_16_ 97 | I_O | A6 | * |A_19_ 98 | I_O | A7 | * |DS_030 99 | GND | | | 100 | GND | | | --------------------------------------------------------------------------- Blk Pad : This notation refers to the Block I/O pad number in the device. Assigned Pin : user or dedicated input assignment (E.g. Clock pins). Pin Type : CkIn : Dedicated input or clock pin CLK : Dedicated clock pin INP : Dedicated input pin JTAG : JTAG Control and test pin NC : No connected  Input_Signal_List ~~~~~~~~~~~~~~~~~ P R Pin r e O Input Pin Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- 96 A . I/O -------H Hi Slow A_16_ 59 F . I/O -------H Hi Slow A_17_ 95 A . I/O -------H Hi Slow A_18_ 97 A . I/O -------H Hi Slow A_19_ 93 A . I/O ----E--- Hi Slow A_20_ 94 A . I/O ----E--- Hi Slow A_21_ 85 H . I/O ----E--- Hi Slow A_22_ 84 H . I/O ----E--- Hi Slow A_23_ 19 C . I/O ----E--- Hi Slow A_24_ 18 C . I/O ----E--- Hi Slow A_25_ 17 C . I/O ----E--- Hi Slow A_26_ 16 C . I/O ----E--- Hi Slow A_27_ 15 C . I/O ----E--- Hi Slow A_28_ 6 B . I/O ----E--- Hi Slow A_29_ 5 B . I/O ----E--- Hi Slow A_30_ 4 B . I/O ----E--- Hi Slow A_31_ 28 D . I/O -------H Hi Slow BGACK_000 21 C . I/O ---D---- Hi Slow BG_030 57 F . I/O -------H Hi Slow FC_0_ 58 F . I/O -------H Hi Slow FC_1_ 67 G . I/O -B------ Hi Slow IPL_0_ 56 F . I/O -B------ Hi Slow IPL_1_ 68 G . I/O -B------ Hi Slow IPL_2_ 11 . . Ck/I ---D---H - Slow CLK_000 14 . . Ck/I A--DE-GH - Slow nEXP_SPACE 36 . . Ded A------- - Slow VPA 61 . . Ck/I AB-D--GH - Slow CLK_OSZI 64 . . Ck/I AB----GH - Slow CLK_030 86 . . Ded AB-D--GH - Slow RST ---------------------------------------------------------------------- Power : Hi = High MH = Medium High ML = Medium Low Lo = Low  Output_Signal_List ~~~~~~~~~~~~~~~~~~ P R Pin r e O Output Pin Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- 48 E 2 COM -------- Hi Slow AMIGA_BUS_DATA_DIR 34 D 1 COM -------- Hi Slow AMIGA_BUS_ENABLE 20 C 1 COM -------- Hi Slow AMIGA_BUS_ENABLE_LOW 92 A 1 COM -------- Hi Slow AVEC 22 C 1 COM -------- Hi Slow AVEC_EXP 41 E 1 COM -------- Hi Slow BERR 83 H 2 DFF * -------- Hi Slow BGACK_030 29 D 2 DFF * -------- Hi Slow BG_000 47 E 1 COM -------- Hi Slow CIIN 65 G 1 DFF * -------- Hi Slow CLK_DIV_OUT 10 B 1 DFF * -------- Hi Slow CLK_EXP 66 G 3 DFF * -------- Hi Slow E 78 H 2 DFF * -------- Hi Slow FPU_CS 8 B 3 DFF * -------- Hi Slow IPL_030_0_ 7 B 3 DFF * -------- Hi Slow IPL_030_1_ 9 B 3 DFF * -------- Hi Slow IPL_030_2_ 3 B 1 DFF * -------- Hi Slow RESET 35 D 2 DFF * -------- Hi Slow VMA ---------------------------------------------------------------------- Power : Hi = High MH = Medium High ML = Medium Low Lo = Low  Bidir_Signal_List ~~~~~~~~~~~~~~~~~ P R Pin r e O Bidir Pin Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- 69 G 1 DFF * ---D---- Hi Slow A0 33 D 2 DFF * AB--E-GH Hi Slow AS_000 82 H 4 DFF * ---D--GH Hi Slow AS_030 81 H 2 DFF * ---D---- Hi Slow DSACK1 98 A 7 DFF * ---D---- Hi Slow DS_030 30 D 1 COM -B------ Hi Slow DTACK 31 D 11 DFF * AB----GH Hi Slow LDS_000 71 G 1 COM ---DE-G- Hi Slow RW 80 H 1 COM A-----G- Hi Slow RW_000 70 G 1 DFF * ---D---- Hi Slow SIZE_0_ 79 H 2 DFF * ---D---- Hi Slow SIZE_1_ 32 D 7 DFF * AB----GH Hi Slow UDS_000 ---------------------------------------------------------------------- Power : Hi = High MH = Medium High ML = Medium Low Lo = Low  Buried_Signal_List ~~~~~~~~~~~~~~~~~~ P R Pin r e O Node #Mc Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- D4 D 2 DFF * ---D---- Hi - RN_AS_000 --> AS_000 H6 H 4 DFF * AB-D--GH Hi - RN_AS_030 --> AS_030 H4 H 2 DFF * AB-DE-GH Hi - RN_BGACK_030 --> BGACK_030 D2 D 2 DFF * ---D---- Hi - RN_BG_000 --> BG_000 H8 H 2 DFF * -------H Hi - RN_DSACK1 --> DSACK1 A0 A 7 DFF * A------- Hi - RN_DS_030 --> DS_030 G2 G 3 DFF * A--D--G- Hi - RN_E --> E H2 H 2 DFF * ----E--H Hi - RN_FPU_CS --> FPU_CS B4 B 3 DFF * -B------ Hi - RN_IPL_030_0_ --> IPL_030_0_ B6 B 3 DFF * -B------ Hi - RN_IPL_030_1_ --> IPL_030_1_ B2 B 3 DFF * -B------ Hi - RN_IPL_030_2_ --> IPL_030_2_ D8 D 11 DFF * ---D---- Hi - RN_LDS_000 --> LDS_000 D6 D 7 DFF * ---D---- Hi - RN_UDS_000 --> UDS_000 D1 D 2 DFF * A--D---- Hi - RN_VMA --> VMA H9 H 2 DFF * ------GH Hi Slow SM_AMIGA_0_ B3 B 2 DFF * -B----GH Hi Slow SM_AMIGA_1_ A1 A 3 DFF * AB------ Hi Slow SM_AMIGA_2_ A4 A 4 DFF * A------- Hi Slow SM_AMIGA_3_ A5 A 2 DFF * A------- Hi Slow SM_AMIGA_4_ D11 D 2 DFF * A--D---- Hi Slow SM_AMIGA_5_ G6 G 2 DFF * ---D--G- Hi Slow SM_AMIGA_6_ H5 H 4 DFF * ---D--GH Hi Slow SM_AMIGA_7_ D10 D 3 DFF * ---D--G- Hi Slow cpu_est_0_ D7 D 4 TFF * A--D--G- Hi Slow cpu_est_1_ D9 D 3 DFF * ---D--G- Hi Slow cpu_est_2_ H7 H 8 DFF * ------GH Hi Slow inst_AS_030_000_SYNC B9 B 1 DFF * ------G- Hi Slow inst_BGACK_030_INT_D H3 H 1 DFF * AB-D--GH Hi Slow inst_CLK_000_D0 D5 D 1 DFF * AB-D--GH Hi Slow inst_CLK_000_D1 H10 H 1 DFF * ------GH Hi Slow inst_CLK_000_D2 B5 B 5 DFF AB------ Hi Slow inst_CLK_030_H B7 B 3 DFF * -B----G- Hi Slow inst_CLK_OUT_PRE_25 H11 H 1 DFF * -B-----H Hi Slow inst_CLK_OUT_PRE_50 H12 H 1 DFF * -B------ Hi Slow inst_CLK_OUT_PRE_50_D B8 B 1 DFF * A------- Hi Slow inst_DTACK_D0 G5 G 14 DFF * ------GH Hi Slow inst_RW_000_INT A3 A 1 DFF * A--D---- Hi Slow inst_VPA_D G4 G 6 DFF * --CD--G- Hi Slow inst_avec_expreg ---------------------------------------------------------------------- Power : Hi = High MH = Medium High ML = Medium Low Lo = Low  Signals_Fanout_List ~~~~~~~~~~~~~~~~~~~ Signal Source : Fanout List ----------------------------------------------------------------------------- A_22_{ I}: CIIN{ E} A_21_{ B}: CIIN{ E} A_20_{ B}: CIIN{ E} A_19_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} A_31_{ C}: CIIN{ E} A_18_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} A_17_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} A_16_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} IPL_2_{ H}: IPL_030_2_{ B} IPL_1_{ G}: IPL_030_1_{ B} FC_1_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} IPL_0_{ H}: IPL_030_0_{ B} FC_0_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} RW_000{ I}: DS_030{ A}inst_RW_000_INT{ G} nEXP_SPACE{. }: DTACK{ D}AMIGA_BUS_DATA_DIR{ E} SIZE_1_{ H} : AS_030{ H} DS_030{ A} A0{ G} : BG_000{ D} DSACK1{ H} SIZE_0_{ G} :inst_avec_expreg{ G}inst_AS_030_000_SYNC{ H} SM_AMIGA_6_{ G} : SM_AMIGA_7_{ H} BG_030{ D}: BG_000{ D} BGACK_000{ E}: BGACK_030{ H} FPU_CS{ H}inst_AS_030_000_SYNC{ H} CLK_030{. }: AS_030{ H} DS_030{ A} FPU_CS{ H} :inst_AS_030_000_SYNC{ H}inst_RW_000_INT{ G} inst_CLK_030_H{ B} CLK_000{. }: BG_000{ D}inst_CLK_000_D0{ H} DTACK{ E}: inst_DTACK_D0{ B} VPA{. }: inst_VPA_D{ A} RST{. }: CLK_DIV_OUT{ G} SIZE_1_{ H} IPL_030_2_{ B} : IPL_030_1_{ B} IPL_030_0_{ B} AS_030{ H} : AS_000{ D} DS_030{ A} UDS_000{ D} : LDS_000{ D} A0{ G} BG_000{ D} : BGACK_030{ H} CLK_EXP{ B} FPU_CS{ H} : DSACK1{ H} E{ G} VMA{ D} : RESET{ B} SIZE_0_{ G}inst_avec_expreg{ G} :inst_AS_030_000_SYNC{ H}inst_BGACK_030_INT_D{ B} inst_VPA_D{ A} :inst_CLK_OUT_PRE_50_D{ H}inst_CLK_000_D0{ H}inst_CLK_000_D1{ D} : inst_DTACK_D0{ B}inst_CLK_OUT_PRE_50{ H}inst_CLK_OUT_PRE_25{ B} : SM_AMIGA_1_{ B} SM_AMIGA_6_{ G} SM_AMIGA_0_{ H} : SM_AMIGA_7_{ H}inst_RW_000_INT{ G}inst_CLK_000_D2{ H} : inst_CLK_030_H{ B} SM_AMIGA_5_{ D} SM_AMIGA_4_{ A} : SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} cpu_est_0_{ D} : cpu_est_1_{ D} cpu_est_2_{ D} RW{ H}:AMIGA_BUS_DATA_DIR{ E} UDS_000{ D} LDS_000{ D} :inst_RW_000_INT{ G} A_30_{ C}: CIIN{ E} A_29_{ C}: CIIN{ E} A_28_{ D}: CIIN{ E} A_27_{ D}: CIIN{ E} A_26_{ D}: CIIN{ E} A_25_{ D}: CIIN{ E} A_24_{ D}: CIIN{ E} A_23_{ I}: CIIN{ E} SIZE_1_{ I}: LDS_000{ D} RN_IPL_030_2_{ C}: IPL_030_2_{ B} RN_IPL_030_1_{ C}: IPL_030_1_{ B} RN_IPL_030_0_{ C}: IPL_030_0_{ B} AS_030{ I}: AS_000{ D} UDS_000{ D} LDS_000{ D} : BG_000{ D} FPU_CS{ H} DSACK1{ H} :inst_avec_expreg{ G}inst_AS_030_000_SYNC{ H} RN_AS_030{ I}: DTACK{ D} SIZE_1_{ H} AS_030{ H} : DS_030{ A} A0{ G} SIZE_0_{ G} : inst_CLK_030_H{ B} AS_000{ E}:AMIGA_BUS_DATA_DIR{ E} SIZE_1_{ H} AS_030{ H} : DS_030{ A} A0{ G} SIZE_0_{ G} :inst_RW_000_INT{ G} inst_CLK_030_H{ B} RN_AS_000{ E}: AS_000{ D} VMA{ D} DS_030{ B}: UDS_000{ D} LDS_000{ D} RN_DS_030{ B}: DS_030{ A} UDS_000{ E}: SIZE_1_{ H} AS_030{ H} DS_030{ A} : A0{ G} SIZE_0_{ G}inst_RW_000_INT{ G} : inst_CLK_030_H{ B} RN_UDS_000{ E}: UDS_000{ D} LDS_000{ E}: SIZE_1_{ H} AS_030{ H} DS_030{ A} : A0{ G} SIZE_0_{ G}inst_RW_000_INT{ G} : inst_CLK_030_H{ B} RN_LDS_000{ E}: LDS_000{ D} A0{ H}: UDS_000{ D} LDS_000{ D} RN_BG_000{ E}: BG_000{ D} RN_BGACK_030{ I}: RW_000{ H} DTACK{ D} RW{ G} :AMIGA_BUS_DATA_DIR{ E} SIZE_1_{ H} AS_030{ H} : AS_000{ D} DS_030{ A} UDS_000{ D} : LDS_000{ D} A0{ G} BGACK_030{ H} : SIZE_0_{ G}inst_avec_expreg{ G}inst_AS_030_000_SYNC{ H} :inst_BGACK_030_INT_D{ B}inst_RW_000_INT{ G} inst_CLK_030_H{ B} RN_FPU_CS{ I}: BERR{ E} FPU_CS{ H} DSACK1{ I}: DTACK{ D} RN_DSACK1{ I}: DSACK1{ H} RN_E{ H}: E{ G} VMA{ D} SM_AMIGA_3_{ A} : SM_AMIGA_2_{ A} cpu_est_1_{ D} cpu_est_2_{ D} RN_VMA{ E}: VMA{ D} SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} SIZE_0_{ H}: LDS_000{ D} inst_avec_expreg{ H}: AVEC_EXP{ C}AMIGA_BUS_ENABLE{ D}inst_avec_expreg{ G} inst_AS_030_000_SYNC{ I}:inst_avec_expreg{ G}inst_AS_030_000_SYNC{ H} SM_AMIGA_6_{ G} : SM_AMIGA_7_{ H} inst_BGACK_030_INT_D{ C}:inst_avec_expreg{ G} inst_VPA_D{ B}: VMA{ D} SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} inst_CLK_OUT_PRE_50_D{ I}:inst_CLK_OUT_PRE_25{ B} inst_CLK_000_D0{ I}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} : AS_000{ D} UDS_000{ D} LDS_000{ D} : BGACK_030{ H} E{ G} VMA{ D} :inst_avec_expreg{ G}inst_CLK_000_D1{ D} SM_AMIGA_1_{ B} : SM_AMIGA_6_{ G} SM_AMIGA_0_{ H} SM_AMIGA_7_{ H} :inst_RW_000_INT{ G} SM_AMIGA_5_{ D} SM_AMIGA_4_{ A} : SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} cpu_est_0_{ D} : cpu_est_1_{ D} cpu_est_2_{ D} inst_CLK_000_D1{ E}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} : BGACK_030{ H} E{ G}inst_avec_expreg{ G} :inst_AS_030_000_SYNC{ H} SM_AMIGA_6_{ G} SM_AMIGA_7_{ H} :inst_CLK_000_D2{ H} SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} : cpu_est_0_{ D} cpu_est_1_{ D} cpu_est_2_{ D} inst_DTACK_D0{ C}: SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} inst_CLK_OUT_PRE_50{ I}:inst_CLK_OUT_PRE_50_D{ H}inst_CLK_OUT_PRE_50{ H}inst_CLK_OUT_PRE_25{ B} inst_CLK_OUT_PRE_25{ C}: CLK_DIV_OUT{ G} CLK_EXP{ B}inst_CLK_OUT_PRE_25{ B} SM_AMIGA_1_{ C}: DSACK1{ H}inst_avec_expreg{ G}inst_AS_030_000_SYNC{ H} : SM_AMIGA_1_{ B} SM_AMIGA_0_{ H} SM_AMIGA_6_{ H}: AS_000{ D} UDS_000{ D} LDS_000{ D} : SM_AMIGA_6_{ G}inst_RW_000_INT{ G} SM_AMIGA_5_{ D} SM_AMIGA_0_{ I}:inst_avec_expreg{ G} SM_AMIGA_0_{ H} SM_AMIGA_7_{ H} :inst_RW_000_INT{ G} SM_AMIGA_7_{ I}: BG_000{ D}inst_avec_expreg{ G}inst_AS_030_000_SYNC{ H} : SM_AMIGA_6_{ G} SM_AMIGA_7_{ H} inst_RW_000_INT{ H}: RW_000{ H} RW{ G}inst_RW_000_INT{ G} inst_CLK_000_D2{ I}:inst_avec_expreg{ G}inst_AS_030_000_SYNC{ H} SM_AMIGA_6_{ G} : SM_AMIGA_7_{ H} inst_CLK_030_H{ C}: DS_030{ A} inst_CLK_030_H{ B} SM_AMIGA_5_{ E}: UDS_000{ D} LDS_000{ D} SM_AMIGA_5_{ D} : SM_AMIGA_4_{ A} SM_AMIGA_4_{ B}: SM_AMIGA_4_{ A} SM_AMIGA_3_{ A} SM_AMIGA_3_{ B}: SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} SM_AMIGA_2_{ B}: SM_AMIGA_1_{ B} SM_AMIGA_2_{ A} cpu_est_0_{ E}: E{ G} VMA{ D} cpu_est_0_{ D} : cpu_est_1_{ D} cpu_est_2_{ D} cpu_est_1_{ E}: E{ G} VMA{ D} SM_AMIGA_3_{ A} : SM_AMIGA_2_{ A} cpu_est_1_{ D} cpu_est_2_{ D} cpu_est_2_{ E}: E{ G} VMA{ D} cpu_est_1_{ D} : cpu_est_2_{ D} ----------------------------------------------------------------------------- {.} : Indicates block location of signal  Set_Reset_Summary ~~~~~~~~~~~~~~~~~ Block A block level set pt : !RST block level reset pt : Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ | * | S | BS | BR | DS_030 | | | | | AVEC | * | S | BR | BS | SM_AMIGA_2_ | * | S | BS | BR | inst_VPA_D | * | S | BS | BR | RN_DS_030 | * | S | BR | BS | SM_AMIGA_3_ | * | S | BR | BS | SM_AMIGA_4_ | | | | | A_19_ | | | | | A_16_ | | | | | A_18_ | | | | | A_21_ | | | | | A_20_ Block B block level set pt : !RST block level reset pt : Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ | * | S | BS | BR | IPL_030_2_ | * | S | BS | BR | IPL_030_0_ | * | S | BS | BR | IPL_030_1_ | * | S | BR | BS | CLK_EXP | * | S | BR | BS | RESET | * | S | BR | BS | SM_AMIGA_1_ | * | S | BR | BR | inst_CLK_030_H | * | S | BR | BS | inst_CLK_OUT_PRE_25 | * | S | BS | BR | RN_IPL_030_0_ | * | S | BS | BR | RN_IPL_030_1_ | * | S | BS | BR | RN_IPL_030_2_ | * | S | BS | BR | inst_DTACK_D0 | * | S | BS | BR | inst_BGACK_030_INT_D | | | | | A_29_ | | | | | A_30_ | | | | | A_31_ Block C block level set pt : block level reset pt : Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ | | | | | AVEC_EXP | | | | | AMIGA_BUS_ENABLE_LOW | | | | | BG_030 | | | | | A_24_ | | | | | A_25_ | | | | | A_26_ | | | | | A_27_ | | | | | A_28_ Block D block level set pt : !RST block level reset pt : Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ | * | S | BS | BR | AS_000 | * | S | BS | BR | LDS_000 | * | S | BS | BR | UDS_000 | | | | | DTACK | * | S | BS | BR | VMA | * | S | BS | BR | BG_000 | | | | | AMIGA_BUS_ENABLE | * | S | BS | BR | inst_CLK_000_D1 | * | S | BR | BS | cpu_est_1_ | * | S | BR | BS | cpu_est_2_ | * | S | BR | BS | cpu_est_0_ | * | S | BS | BR | RN_VMA | * | S | BR | BS | SM_AMIGA_5_ | * | S | BS | BR | RN_LDS_000 | * | S | BS | BR | RN_UDS_000 | * | S | BS | BR | RN_BG_000 | * | S | BS | BR | RN_AS_000 | | | | | BGACK_000 Block E block level set pt : block level reset pt : Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ | | | | | AMIGA_BUS_DATA_DIR | | | | | CIIN | | | | | BERR Block F block level set pt : block level reset pt : Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ | | | | | A_17_ | | | | | FC_1_ | | | | | FC_0_ | | | | | IPL_1_ Block G block level set pt : block level reset pt : !RST Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ | | | | | RW | * | S | BR | BS | SIZE_0_ | * | S | BR | BS | A0 | * | S | BS | BR | E | * | S | BS | BR | CLK_DIV_OUT | * | S | BR | BS | inst_avec_expreg | * | S | BS | BR | RN_E | * | S | BR | BS | inst_RW_000_INT | * | S | BS | BR | SM_AMIGA_6_ | | | | | IPL_2_ | | | | | IPL_0_ Block H block level set pt : !RST block level reset pt : Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ | * | S | BS | BR | AS_030 | | | | | RW_000 | * | S | BS | BR | DSACK1 | * | S | BS | BR | SIZE_1_ | * | S | BS | BR | BGACK_030 | * | S | BS | BR | FPU_CS | * | S | BS | BR | RN_BGACK_030 | * | S | BS | BR | RN_AS_030 | * | S | BS | BR | inst_CLK_000_D0 | * | S | BS | BR | SM_AMIGA_7_ | * | S | BS | BR | inst_AS_030_000_SYNC | * | S | BS | BR | RN_FPU_CS | * | S | BR | BS | SM_AMIGA_0_ | * | S | BS | BR | inst_CLK_000_D2 | * | S | BR | BS | inst_CLK_OUT_PRE_50 | * | S | BS | BR | RN_DSACK1 | * | S | BR | BS | inst_CLK_OUT_PRE_50_D | | | | | A_22_ | | | | | A_23_ (S) means the macrocell is configured in synchronous mode i.e. it uses the block-level set and reset pt. (A) means the macrocell is configured in asynchronous mode i.e. it can have its independant set or reset pt. (BS) means the block-level set pt is selected. (BR) means the block-level reset pt is selected.  BLOCK_A_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ mx A0 RST pin 86 mx A17 RN_VMA mcell D1 mx A1 SM_AMIGA_3_ mcell A4 mx A18 ... ... mx A2 SM_AMIGA_4_ mcell A5 mx A19 ... ... mx A3 SM_AMIGA_5_ mcell D11 mx A20 RN_BGACK_030 mcell H4 mx A4 CLK_030 pin 64 mx A21 RN_AS_030 mcell H6 mx A5 nEXP_SPACE pin 14 mx A22 ... ... mx A6 RW_000 pin 80 mx A23 RN_E mcell G2 mx A7 inst_CLK_000_D1 mcell D5 mx A24 LDS_000 pin 31 mx A8 inst_DTACK_D0 mcell B8 mx A25 inst_VPA_D mcell A3 mx A9 SM_AMIGA_2_ mcell A1 mx A26 AS_000 pin 33 mx A10 VPA pin 36 mx A27 ... ... mx A11 inst_CLK_000_D0 mcell H3 mx A28 inst_CLK_030_H mcell B5 mx A12 UDS_000 pin 32 mx A29 ... ... mx A13 cpu_est_1_ mcell D7 mx A30 ... ... mx A14 ... ... mx A31 ... ... mx A15 RN_DS_030 mcell A0 mx A32 ... ... mx A16 ... ... ---------------------------------------------------------------------------- BLOCK_B_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ mx B0 LDS_000 pin 31 mx B17 ... ... mx B1inst_CLK_OUT_PRE_50 mcell H11 mx B18 ... ... mx B2 RN_IPL_030_1_ mcell B6 mx B19 ... ... mx B3 IPL_1_ pin 56 mx B20 CLK_030 pin 64 mx B4 IPL_2_ pin 68 mx B21 RST pin 86 mx B5 SM_AMIGA_1_ mcell B3 mx B22 ... ... mx B6 ... ... mx B23 RN_BGACK_030 mcell H4 mx B7 inst_CLK_000_D1 mcell D5 mx B24inst_CLK_OUT_PRE_25 mcell B7 mx B8inst_CLK_OUT_PRE_50_D mcell H12 mx B25 ... ... mx B9 SM_AMIGA_2_ mcell A1 mx B26 AS_000 pin 33 mx B10 RN_IPL_030_2_ mcell B2 mx B27 RN_IPL_030_0_ mcell B4 mx B11 inst_CLK_000_D0 mcell H3 mx B28 inst_CLK_030_H mcell B5 mx B12 UDS_000 pin 32 mx B29 ... ... mx B13 ... ... mx B30 RN_AS_030 mcell H6 mx B14 DTACK pin 30 mx B31 ... ... mx B15 ... ... mx B32 ... ... mx B16 IPL_0_ pin 67 ---------------------------------------------------------------------------- BLOCK_C_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ mx C0 ... ... mx C17 ... ... mx C1 ... ... mx C18 ... ... mx C2inst_avec_expreg mcell G4 mx C19 ... ... mx C3 ... ... mx C20 ... ... mx C4 ... ... mx C21 ... ... mx C5 ... ... mx C22 ... ... mx C6 ... ... mx C23 ... ... mx C7 ... ... mx C24 ... ... mx C8 ... ... mx C25 ... ... mx C9 ... ... mx C26 ... ... mx C10 ... ... mx C27 ... ... mx C11 ... ... mx C28 ... ... mx C12 ... ... mx C29 ... ... mx C13 ... ... mx C30 ... ... mx C14 ... ... mx C31 ... ... mx C15 ... ... mx C32 ... ... mx C16 ... ... ---------------------------------------------------------------------------- BLOCK_D_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ mx D0 RN_BGACK_030 mcell H4 mx D17 SIZE_0_ pin 70 mx D1 ... ... mx D18 A0 pin 69 mx D2inst_avec_expreg mcell G4 mx D19 SM_AMIGA_5_ mcell D11 mx D3 RN_BG_000 mcell D2 mx D20 cpu_est_0_ mcell D10 mx D4 SM_AMIGA_7_ mcell H5 mx D21 RST pin 86 mx D5 DS_030 pin 98 mx D22 BG_030 pin 21 mx D6 SIZE_1_ pin 79 mx D23 SM_AMIGA_6_ mcell G6 mx D7 RN_AS_030 mcell H6 mx D24 CLK_000 pin 11 mx D8 RW pin 71 mx D25 inst_VPA_D mcell A3 mx D9 AS_030 pin 82 mx D26 ... ... mx D10 inst_CLK_000_D0 mcell H3 mx D27 RN_VMA mcell D1 mx D11 inst_CLK_000_D1 mcell D5 mx D28 ... ... mx D12 cpu_est_2_ mcell D9 mx D29 ... ... mx D13 cpu_est_1_ mcell D7 mx D30 RN_UDS_000 mcell D6 mx D14 RN_AS_000 mcell D4 mx D31 RN_E mcell G2 mx D15 nEXP_SPACE pin 14 mx D32 DSACK1 pin 81 mx D16 RN_LDS_000 mcell D8 ---------------------------------------------------------------------------- BLOCK_E_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ mx E0 RN_BGACK_030 mcell H4 mx E17 A_26_ pin 17 mx E1 A_31_ pin 4 mx E18 ... ... mx E2 ... ... mx E19 ... ... mx E3 A_27_ pin 16 mx E20 ... ... mx E4 A_29_ pin 6 mx E21 nEXP_SPACE pin 14 mx E5 A_24_ pin 19 mx E22 ... ... mx E6 ... ... mx E23 AS_000 pin 33 mx E7 A_28_ pin 15 mx E24 ... ... mx E8 A_22_ pin 85 mx E25 RW pin 71 mx E9 A_30_ pin 5 mx E26 ... ... mx E10 ... ... mx E27 ... ... mx E11 A_23_ pin 84 mx E28 ... ... mx E12 A_25_ pin 18 mx E29 A_20_ pin 93 mx E13 ... ... mx E30 ... ... mx E14 RN_FPU_CS mcell H2 mx E31 ... ... mx E15 A_21_ pin 94 mx E32 ... ... mx E16 ... ... ---------------------------------------------------------------------------- BLOCK_G_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ mx G0 LDS_000 pin 31 mx G17 ... ... mx G1inst_CLK_OUT_PRE_25 mcell B7 mx G18 inst_CLK_000_D2 mcell H10 mx G2 cpu_est_0_ mcell D10 mx G19 ... ... mx G3 inst_RW_000_INT mcell G5 mx G20 RN_BGACK_030 mcell H4 mx G4 CLK_030 pin 64 mx G21 RST pin 86 mx G5 SM_AMIGA_0_ mcell H9 mx G22 ... ... mx G6inst_BGACK_030_INT_D mcell B9 mx G23 SM_AMIGA_6_ mcell G6 mx G7 cpu_est_2_ mcell D9 mx G24 inst_CLK_000_D1 mcell D5 mx G8 cpu_est_1_ mcell D7 mx G25 RW pin 71 mx G9 AS_030 pin 82 mx G26 AS_000 pin 33 mx G10 inst_CLK_000_D0 mcell H3 mx G27 SM_AMIGA_7_ mcell H5 mx G11inst_avec_expreg mcell G4 mx G28 RW_000 pin 80 mx G12 UDS_000 pin 32 mx G29inst_AS_030_000_SYNC mcell H7 mx G13 SM_AMIGA_1_ mcell B3 mx G30 RN_AS_030 mcell H6 mx G14 ... ... mx G31 RN_E mcell G2 mx G15 nEXP_SPACE pin 14 mx G32 ... ... mx G16 ... ... ---------------------------------------------------------------------------- BLOCK_H_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ mx H0 LDS_000 pin 31 mx H17 FC_0_ pin 57 mx H1 FC_1_ pin 58 mx H18 inst_CLK_000_D2 mcell H10 mx H2 ... ... mx H19 SM_AMIGA_1_ mcell B3 mx H3 CLK_000 pin 11 mx H20inst_AS_030_000_SYNC mcell H7 mx H4 BGACK_000 pin 28 mx H21 RST pin 86 mx H5 SM_AMIGA_0_ mcell H9 mx H22inst_CLK_OUT_PRE_50 mcell H11 mx H6 A_19_ pin 97 mx H23 RN_BGACK_030 mcell H4 mx H7 RN_AS_030 mcell H6 mx H24 inst_CLK_000_D1 mcell D5 mx H8 A_17_ pin 59 mx H25 ... ... mx H9 AS_030 pin 82 mx H26 AS_000 pin 33 mx H10 inst_CLK_000_D0 mcell H3 mx H27 SM_AMIGA_7_ mcell H5 mx H11 A_16_ pin 96 mx H28 CLK_030 pin 64 mx H12 UDS_000 pin 32 mx H29 ... ... mx H13 RN_DSACK1 mcell H8 mx H30 ... ... mx H14 RN_FPU_CS mcell H2 mx H31 A_18_ pin 95 mx H15 nEXP_SPACE pin 14 mx H32 inst_RW_000_INT mcell G5 mx H16 ... ... ---------------------------------------------------------------------------- CSM indicates the mux inputs from the Central Switch Matrix. Source indicates where the signal comes from (pin or macrocell).  PostFit_Equations ~~~~~~~~~~~~~~~~~ P-Terms Fan-in Fan-out Type Name (attributes) --------- ------ ------- ---- ----------------- 1 1 1 Pin RW_000 1 1 1 Pin RW_000.OE 0 0 1 Pin BERR 1 1 1 Pin BERR.OE 1 1 1 Pin CLK_DIV_OUT.AR 1 1 1 Pin CLK_DIV_OUT.D 1 1 1 Pin CLK_DIV_OUT.C 1 1 1 Pin DTACK 1 3 1 Pin DTACK.OE 1 0 1 Pin AVEC 1 1 1 Pin AVEC_EXP 1 1 1 Pin RW 1 1 1 Pin RW.OE 1 1 1 Pin AMIGA_BUS_ENABLE 2 4 1 Pin AMIGA_BUS_DATA_DIR 1 0 1 Pin AMIGA_BUS_ENABLE_LOW 1 4 1 Pin CIIN 1 8 1 Pin CIIN.OE 1 3 1 Pin SIZE_1_.OE 2 4 1 Pin SIZE_1_.D- 1 1 1 Pin SIZE_1_.AP 1 1 1 Pin SIZE_1_.C 3 4 1 Pin IPL_030_2_.D 1 1 1 Pin IPL_030_2_.AP 1 1 1 Pin IPL_030_2_.C 3 4 1 Pin IPL_030_1_.D 1 1 1 Pin IPL_030_1_.AP 1 1 1 Pin IPL_030_1_.C 3 4 1 Pin IPL_030_0_.D 1 1 1 Pin IPL_030_0_.AP 1 1 1 Pin IPL_030_0_.C 1 3 1 Pin AS_030.OE 4 6 1 Pin AS_030.D 1 1 1 Pin AS_030.AP 1 1 1 Pin AS_030.C 1 1 1 Pin AS_000.OE 2 4 1 Pin AS_000.D- 1 1 1 Pin AS_000.AP 1 1 1 Pin AS_000.C 1 3 1 Pin DS_030.OE 7 9 1 Pin DS_030.D 1 1 1 Pin DS_030.AP 1 1 1 Pin DS_030.C 1 1 1 Pin UDS_000.OE 7 8 1 Pin UDS_000.D- 1 1 1 Pin UDS_000.AP 1 1 1 Pin UDS_000.C 1 1 1 Pin LDS_000.OE 11 10 1 Pin LDS_000.D- 1 1 1 Pin LDS_000.AP 1 1 1 Pin LDS_000.C 1 3 1 Pin A0.OE 1 4 1 Pin A0.D 1 1 1 Pin A0.AP 1 1 1 Pin A0.C 2 6 1 Pin BG_000.D- 1 1 1 Pin BG_000.AP 1 1 1 Pin BG_000.C 2 4 1 Pin BGACK_030.D 1 1 1 Pin BGACK_030.AP 1 1 1 Pin BGACK_030.C 1 1 1 Pin CLK_EXP.AR 1 1 1 Pin CLK_EXP.D 1 1 1 Pin CLK_EXP.C 2 10 1 Pin FPU_CS.D- 1 1 1 Pin FPU_CS.AP 1 1 1 Pin FPU_CS.C 1 1 1 Pin DSACK1.OE 2 3 1 Pin DSACK1.D 1 1 1 Pin DSACK1.AP 1 1 1 Pin DSACK1.C 3 6 1 PinX1 E.D.X1 1 1 1 PinX2 E.D.X2 1 1 1 Pin E.AR 1 1 1 Pin E.C 2 7 1 PinX1 VMA.D.X1 1 5 1 PinX2 VMA.D.X2 1 1 1 Pin VMA.AP 1 1 1 Pin VMA.C 1 1 1 Pin RESET.AR 1 0 1 Pin RESET.D 1 1 1 Pin RESET.C 1 3 1 Pin SIZE_0_.OE 1 4 1 Pin SIZE_0_.D- 1 1 1 Pin SIZE_0_.AP 1 1 1 Pin SIZE_0_.C 6 12 1 Node inst_avec_expreg.D- 1 1 1 Node inst_avec_expreg.AP 1 1 1 Node inst_avec_expreg.C 8 16 1 Node inst_AS_030_000_SYNC.D 1 1 1 Node inst_AS_030_000_SYNC.AP 1 1 1 Node inst_AS_030_000_SYNC.C 1 1 1 Node inst_BGACK_030_INT_D.D 1 1 1 Node inst_BGACK_030_INT_D.AP 1 1 1 Node inst_BGACK_030_INT_D.C 1 1 1 Node inst_VPA_D.D 1 1 1 Node inst_VPA_D.AP 1 1 1 Node inst_VPA_D.C 1 1 1 Node inst_CLK_OUT_PRE_50_D.AR 1 1 1 Node inst_CLK_OUT_PRE_50_D.D 1 1 1 Node inst_CLK_OUT_PRE_50_D.C 1 1 1 Node inst_CLK_000_D0.D 1 1 1 Node inst_CLK_000_D0.AP 1 1 1 Node inst_CLK_000_D0.C 1 1 1 Node inst_CLK_000_D1.D 1 1 1 Node inst_CLK_000_D1.AP 1 1 1 Node inst_CLK_000_D1.C 1 1 1 Node inst_DTACK_D0.D 1 1 1 Node inst_DTACK_D0.AP 1 1 1 Node inst_DTACK_D0.C 1 1 1 Node inst_CLK_OUT_PRE_50.AR 1 1 1 Node inst_CLK_OUT_PRE_50.D 1 1 1 Node inst_CLK_OUT_PRE_50.C 1 1 1 Node inst_CLK_OUT_PRE_25.AR 3 3 1 Node inst_CLK_OUT_PRE_25.D 1 1 1 Node inst_CLK_OUT_PRE_25.C 1 1 1 Node SM_AMIGA_1_.AR 2 3 1 Node SM_AMIGA_1_.D 1 1 1 Node SM_AMIGA_1_.C 1 1 1 Node SM_AMIGA_6_.AR 2 7 1 Node SM_AMIGA_6_.D 1 1 1 Node SM_AMIGA_6_.C 1 1 1 Node SM_AMIGA_0_.AR 2 3 1 Node SM_AMIGA_0_.D 1 1 1 Node SM_AMIGA_0_.C 4 7 1 Node SM_AMIGA_7_.D- 1 1 1 Node SM_AMIGA_7_.AP 1 1 1 Node SM_AMIGA_7_.C 14 11 1 Node inst_RW_000_INT.D- 1 1 1 Node inst_RW_000_INT.AP 1 1 1 Node inst_RW_000_INT.C 1 1 1 Node inst_CLK_000_D2.D 1 1 1 Node inst_CLK_000_D2.AP 1 1 1 Node inst_CLK_000_D2.C 5 8 1 Node inst_CLK_030_H.D 1 1 1 Node inst_CLK_030_H.C 1 1 1 Node SM_AMIGA_5_.AR 2 3 1 Node SM_AMIGA_5_.D 1 1 1 Node SM_AMIGA_5_.C 1 1 1 Node SM_AMIGA_4_.AR 2 3 1 Node SM_AMIGA_4_.D 1 1 1 Node SM_AMIGA_4_.C 1 1 1 Node SM_AMIGA_3_.AR 4 9 1 Node SM_AMIGA_3_.D- 1 1 1 Node SM_AMIGA_3_.C 1 1 1 Node SM_AMIGA_2_.AR 3 9 1 Node SM_AMIGA_2_.D 1 1 1 Node SM_AMIGA_2_.C 1 1 1 Node cpu_est_0_.AR 3 3 1 Node cpu_est_0_.D 1 1 1 Node cpu_est_0_.C 1 1 1 Node cpu_est_1_.AR 4 6 1 Node cpu_est_1_.T 1 1 1 Node cpu_est_1_.C 3 6 1 NodeX1 cpu_est_2_.D.X1 1 1 1 NodeX2 cpu_est_2_.D.X2 1 1 1 Node cpu_est_2_.AR 1 1 1 Node cpu_est_2_.C ========= 249 P-Term Total: 249 Total Pins: 59 Total Nodes: 24 Average P-Term/Output: 2 Equations: RW_000 = (inst_RW_000_INT.Q); RW_000.OE = (BGACK_030.Q); BERR = (0); BERR.OE = (!FPU_CS.Q); CLK_DIV_OUT.AR = (!RST); CLK_DIV_OUT.D = (inst_CLK_OUT_PRE_25.Q); CLK_DIV_OUT.C = (CLK_OSZI); DTACK = (DSACK1.PIN); DTACK.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q); AVEC = (1); AVEC_EXP = (inst_avec_expreg.Q); RW = (inst_RW_000_INT.Q); RW.OE = (!BGACK_030.Q); AMIGA_BUS_ENABLE = (inst_avec_expreg.Q); AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW.PIN # !nEXP_SPACE & !BGACK_030.Q & !AS_000.PIN & RW.PIN); AMIGA_BUS_ENABLE_LOW = (1); CIIN = (A_23_ & A_22_ & A_21_ & A_20_); CIIN.OE = (!A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_); SIZE_1_.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q); !SIZE_1_.D = (!BGACK_030.Q & !AS_000.PIN & !UDS_000.PIN & LDS_000.PIN # !BGACK_030.Q & !AS_000.PIN & UDS_000.PIN & !LDS_000.PIN); SIZE_1_.AP = (!RST); SIZE_1_.C = (CLK_OSZI); IPL_030_2_.D = (!inst_CLK_000_D0.Q & IPL_030_2_.Q # inst_CLK_000_D1.Q & IPL_030_2_.Q # IPL_2_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q); IPL_030_2_.AP = (!RST); IPL_030_2_.C = (CLK_OSZI); IPL_030_1_.D = (!inst_CLK_000_D0.Q & IPL_030_1_.Q # inst_CLK_000_D1.Q & IPL_030_1_.Q # IPL_1_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q); IPL_030_1_.AP = (!RST); IPL_030_1_.C = (CLK_OSZI); IPL_030_0_.D = (!inst_CLK_000_D0.Q & IPL_030_0_.Q # inst_CLK_000_D1.Q & IPL_030_0_.Q # IPL_0_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q); IPL_030_0_.AP = (!RST); IPL_030_0_.C = (CLK_OSZI); AS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q); AS_030.D = (BGACK_030.Q # AS_000.PIN # CLK_030 & AS_030.Q # UDS_000.PIN & LDS_000.PIN); AS_030.AP = (!RST); AS_030.C = (CLK_OSZI); AS_000.OE = (BGACK_030.Q); !AS_000.D = (inst_CLK_000_D0.Q & SM_AMIGA_6_.Q # !AS_000.Q & !AS_030.PIN); AS_000.AP = (!RST); AS_000.C = (CLK_OSZI); DS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q); DS_030.D = (BGACK_030.Q # AS_000.PIN # AS_030.Q & RW_000.PIN # UDS_000.PIN & LDS_000.PIN # !CLK_030 & AS_030.Q & inst_CLK_030_H.Q # CLK_030 & DS_030.Q & !RW_000.PIN # !inst_CLK_030_H.Q & DS_030.Q & !RW_000.PIN); DS_030.AP = (!RST); DS_030.C = (CLK_OSZI); UDS_000.OE = (BGACK_030.Q); !UDS_000.D = (!UDS_000.Q & !AS_030.PIN & DS_030.PIN # !inst_CLK_000_D0.Q & !UDS_000.Q & !AS_030.PIN & RW.PIN # !SM_AMIGA_6_.Q & !UDS_000.Q & !AS_030.PIN & RW.PIN # inst_CLK_000_D0.Q & !UDS_000.Q & !AS_030.PIN & !RW.PIN # !UDS_000.Q & !SM_AMIGA_5_.Q & !AS_030.PIN & !RW.PIN # inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !DS_030.PIN & !A0.PIN & RW.PIN # !inst_CLK_000_D0.Q & SM_AMIGA_5_.Q & !DS_030.PIN & !A0.PIN & !RW.PIN); UDS_000.AP = (!RST); UDS_000.C = (CLK_OSZI); LDS_000.OE = (BGACK_030.Q); !LDS_000.D = (!LDS_000.Q & !AS_030.PIN & DS_030.PIN # !inst_CLK_000_D0.Q & !LDS_000.Q & !SM_AMIGA_5_.Q & !AS_030.PIN # !inst_CLK_000_D0.Q & !LDS_000.Q & !AS_030.PIN & RW.PIN # !SM_AMIGA_6_.Q & !LDS_000.Q & !AS_030.PIN & RW.PIN # inst_CLK_000_D0.Q & !LDS_000.Q & !AS_030.PIN & !RW.PIN # inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !DS_030.PIN & !SIZE_0_.PIN & RW.PIN # inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !DS_030.PIN & SIZE_1_.PIN & RW.PIN # inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !DS_030.PIN & A0.PIN & RW.PIN # !inst_CLK_000_D0.Q & SM_AMIGA_5_.Q & !DS_030.PIN & !SIZE_0_.PIN & !RW.PIN # !inst_CLK_000_D0.Q & SM_AMIGA_5_.Q & !DS_030.PIN & SIZE_1_.PIN & !RW.PIN # !inst_CLK_000_D0.Q & SM_AMIGA_5_.Q & !DS_030.PIN & A0.PIN & !RW.PIN); LDS_000.AP = (!RST); LDS_000.C = (CLK_OSZI); A0.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q); A0.D = (!BGACK_030.Q & !AS_000.PIN & UDS_000.PIN & !LDS_000.PIN); A0.AP = (!RST); A0.C = (CLK_OSZI); !BG_000.D = (!BG_030 & !BG_000.Q # nEXP_SPACE & !BG_030 & CLK_000 & SM_AMIGA_7_.Q & AS_030.PIN); BG_000.AP = (!RST); BG_000.C = (CLK_OSZI); BGACK_030.D = (BGACK_000 & BGACK_030.Q # BGACK_000 & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q); BGACK_030.AP = (!RST); BGACK_030.C = (CLK_OSZI); CLK_EXP.AR = (!RST); CLK_EXP.D = (inst_CLK_OUT_PRE_25.Q); CLK_EXP.C = (CLK_OSZI); !FPU_CS.D = (!FPU_CS.Q & !AS_030.PIN # FC_1_ & BGACK_000 & CLK_030 & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN); FPU_CS.AP = (!RST); FPU_CS.C = (CLK_OSZI); DSACK1.OE = (nEXP_SPACE); DSACK1.D = (!SM_AMIGA_1_.Q & DSACK1.Q # !SM_AMIGA_1_.Q & AS_030.PIN); DSACK1.AP = (!RST); DSACK1.C = (CLK_OSZI); E.D.X1 = (inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_1_.Q & cpu_est_2_.Q & E.Q # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_0_.Q & !cpu_est_2_.Q & !E.Q # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !E.Q); E.D.X2 = (E.Q); E.AR = (!RST); E.C = (CLK_OSZI); VMA.D.X1 = (VMA.Q # !VMA.Q & inst_CLK_000_D0.Q & AS_000.Q & !cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & !E.Q); VMA.D.X2 = (VMA.Q & !inst_VPA_D.Q & !inst_CLK_000_D0.Q & cpu_est_0_.Q & !cpu_est_1_.Q); VMA.AP = (!RST); VMA.C = (CLK_OSZI); RESET.AR = (!RST); RESET.D = (1); RESET.C = (CLK_OSZI); SIZE_0_.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q); !SIZE_0_.D = (!BGACK_030.Q & !AS_000.PIN & !UDS_000.PIN & !LDS_000.PIN); SIZE_0_.AP = (!RST); SIZE_0_.C = (CLK_OSZI); !inst_avec_expreg.D = (!BGACK_030.Q # !inst_avec_expreg.Q & inst_BGACK_030_INT_D.Q & SM_AMIGA_1_.Q & !AS_030.PIN # !inst_avec_expreg.Q & inst_BGACK_030_INT_D.Q & SM_AMIGA_0_.Q & !AS_030.PIN # !inst_avec_expreg.Q & inst_BGACK_030_INT_D.Q & inst_CLK_000_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_7_.Q # !inst_avec_expreg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_7_.Q # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & inst_BGACK_030_INT_D.Q & !inst_CLK_000_D1.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q & SM_AMIGA_7_.Q & inst_CLK_000_D2.Q); inst_avec_expreg.AP = (!RST); inst_avec_expreg.C = (CLK_OSZI); inst_AS_030_000_SYNC.D = (SM_AMIGA_1_.Q # AS_030.PIN # !nEXP_SPACE & inst_AS_030_000_SYNC.Q # !CLK_030 & inst_AS_030_000_SYNC.Q # !BGACK_030.Q & inst_AS_030_000_SYNC.Q # inst_AS_030_000_SYNC.Q & !SM_AMIGA_7_.Q # !nEXP_SPACE & !inst_CLK_000_D1.Q & SM_AMIGA_7_.Q & inst_CLK_000_D2.Q # FC_1_ & BGACK_000 & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & inst_AS_030_000_SYNC.Q); inst_AS_030_000_SYNC.AP = (!RST); inst_AS_030_000_SYNC.C = (CLK_OSZI); inst_BGACK_030_INT_D.D = (BGACK_030.Q); inst_BGACK_030_INT_D.AP = (!RST); inst_BGACK_030_INT_D.C = (CLK_OSZI); inst_VPA_D.D = (VPA); inst_VPA_D.AP = (!RST); inst_VPA_D.C = (CLK_OSZI); inst_CLK_OUT_PRE_50_D.AR = (!RST); inst_CLK_OUT_PRE_50_D.D = (inst_CLK_OUT_PRE_50.Q); inst_CLK_OUT_PRE_50_D.C = (CLK_OSZI); inst_CLK_000_D0.D = (CLK_000); inst_CLK_000_D0.AP = (!RST); inst_CLK_000_D0.C = (CLK_OSZI); inst_CLK_000_D1.D = (inst_CLK_000_D0.Q); inst_CLK_000_D1.AP = (!RST); inst_CLK_000_D1.C = (CLK_OSZI); inst_DTACK_D0.D = (DTACK.PIN); inst_DTACK_D0.AP = (!RST); inst_DTACK_D0.C = (CLK_OSZI); inst_CLK_OUT_PRE_50.AR = (!RST); inst_CLK_OUT_PRE_50.D = (!inst_CLK_OUT_PRE_50.Q); inst_CLK_OUT_PRE_50.C = (CLK_OSZI); inst_CLK_OUT_PRE_25.AR = (!RST); inst_CLK_OUT_PRE_25.D = (inst_CLK_OUT_PRE_50_D.Q & inst_CLK_OUT_PRE_25.Q # !inst_CLK_OUT_PRE_50.Q & inst_CLK_OUT_PRE_25.Q # !inst_CLK_OUT_PRE_50_D.Q & inst_CLK_OUT_PRE_50.Q & !inst_CLK_OUT_PRE_25.Q); inst_CLK_OUT_PRE_25.C = (CLK_OSZI); SM_AMIGA_1_.AR = (!RST); SM_AMIGA_1_.D = (inst_CLK_000_D0.Q & SM_AMIGA_1_.Q # inst_CLK_000_D0.Q & SM_AMIGA_2_.Q); SM_AMIGA_1_.C = (CLK_OSZI); SM_AMIGA_6_.AR = (!RST); SM_AMIGA_6_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !SM_AMIGA_7_.Q # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D1.Q & SM_AMIGA_7_.Q & inst_CLK_000_D2.Q); SM_AMIGA_6_.C = (CLK_OSZI); SM_AMIGA_0_.AR = (!RST); SM_AMIGA_0_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_1_.Q # !inst_CLK_000_D0.Q & SM_AMIGA_0_.Q); SM_AMIGA_0_.C = (CLK_OSZI); !SM_AMIGA_7_.D = (!inst_CLK_000_D0.Q & !SM_AMIGA_7_.Q # !SM_AMIGA_0_.Q & !SM_AMIGA_7_.Q # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & inst_CLK_000_D2.Q # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D1.Q & !SM_AMIGA_0_.Q & inst_CLK_000_D2.Q); SM_AMIGA_7_.AP = (!RST); SM_AMIGA_7_.C = (CLK_OSZI); !inst_RW_000_INT.D = (CLK_030 & !inst_CLK_000_D0.Q & !inst_RW_000_INT.Q # BGACK_030.Q & !inst_CLK_000_D0.Q & !inst_RW_000_INT.Q # !inst_CLK_000_D0.Q & !inst_RW_000_INT.Q & AS_000.PIN # CLK_030 & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !inst_RW_000_INT.Q # BGACK_030.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !inst_RW_000_INT.Q # !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !inst_RW_000_INT.Q & AS_000.PIN # !inst_CLK_000_D0.Q & !inst_RW_000_INT.Q & UDS_000.PIN & LDS_000.PIN # CLK_030 & inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !RW.PIN # BGACK_030.Q & inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !RW.PIN # inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & AS_000.PIN & !RW.PIN # !CLK_030 & !BGACK_030.Q & !AS_000.PIN & !RW_000.PIN & !UDS_000.PIN # !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !inst_RW_000_INT.Q & UDS_000.PIN & LDS_000.PIN # !CLK_030 & !BGACK_030.Q & !AS_000.PIN & !RW_000.PIN & !LDS_000.PIN # inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & UDS_000.PIN & LDS_000.PIN & !RW.PIN); inst_RW_000_INT.AP = (!RST); inst_RW_000_INT.C = (CLK_OSZI); inst_CLK_000_D2.D = (inst_CLK_000_D1.Q); inst_CLK_000_D2.AP = (!RST); inst_CLK_000_D2.C = (CLK_OSZI); inst_CLK_030_H.D = (!RST & inst_CLK_030_H.Q # !BGACK_030.Q & inst_CLK_030_H.Q & !AS_000.PIN & !UDS_000.PIN # !BGACK_030.Q & inst_CLK_030_H.Q & !AS_000.PIN & !LDS_000.PIN # CLK_030 & RST & !BGACK_030.Q & !AS_030.Q & !AS_000.PIN & !UDS_000.PIN # CLK_030 & RST & !BGACK_030.Q & !AS_030.Q & !AS_000.PIN & !LDS_000.PIN); inst_CLK_030_H.C = (CLK_OSZI); SM_AMIGA_5_.AR = (!RST); SM_AMIGA_5_.D = (inst_CLK_000_D0.Q & SM_AMIGA_6_.Q # inst_CLK_000_D0.Q & SM_AMIGA_5_.Q); SM_AMIGA_5_.C = (CLK_OSZI); SM_AMIGA_4_.AR = (!RST); SM_AMIGA_4_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_5_.Q # !inst_CLK_000_D0.Q & SM_AMIGA_4_.Q); SM_AMIGA_4_.C = (CLK_OSZI); SM_AMIGA_3_.AR = (!RST); !SM_AMIGA_3_.D = (!inst_CLK_000_D0.Q & !SM_AMIGA_3_.Q # !SM_AMIGA_4_.Q & !SM_AMIGA_3_.Q # inst_VPA_D.Q & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & !inst_DTACK_D0.Q # !VMA.Q & !inst_VPA_D.Q & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & !cpu_est_1_.Q & E.Q); SM_AMIGA_3_.C = (CLK_OSZI); SM_AMIGA_2_.AR = (!RST); SM_AMIGA_2_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_2_.Q # inst_VPA_D.Q & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & !inst_DTACK_D0.Q & SM_AMIGA_3_.Q # !VMA.Q & !inst_VPA_D.Q & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & SM_AMIGA_3_.Q & !cpu_est_1_.Q & E.Q); SM_AMIGA_2_.C = (CLK_OSZI); cpu_est_0_.AR = (!RST); cpu_est_0_.D = (!inst_CLK_000_D0.Q & cpu_est_0_.Q # inst_CLK_000_D1.Q & cpu_est_0_.Q # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_0_.Q); cpu_est_0_.C = (CLK_OSZI); cpu_est_1_.AR = (!RST); cpu_est_1_.T = (inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_1_.Q & cpu_est_2_.Q & E.Q # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_0_.Q & !cpu_est_2_.Q & E.Q # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_0_.Q & cpu_est_2_.Q & !E.Q # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !E.Q); cpu_est_1_.C = (CLK_OSZI); cpu_est_2_.D.X1 = (inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_0_.Q & !cpu_est_2_.Q & E.Q # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_0_.Q & !cpu_est_1_.Q & cpu_est_2_.Q & !E.Q); cpu_est_2_.D.X2 = (cpu_est_2_.Q); cpu_est_2_.AR = (!RST); cpu_est_2_.C = (CLK_OSZI); Reverse-Polarity Equations: