Synopsys CPLD Technology Mapper, Version maplat, Build 621R, Built Mar 19 2013
Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
Product Version G-2012.09LC-SP1 
@N: MF248 |Running in 64-bit mode.
Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
original code -> new code
   000 -> 00000001
   001 -> 00000010
   010 -> 00000100
   011 -> 00001000
   100 -> 00010000
   101 -> 00100000
   110 -> 01000000
   111 -> 10000000
@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":216:4:216:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits 
@W: BN132 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:34:138:36|Removing instance CLK_000_P_SYNC[10],  because it is equivalent to instance CLK_000_PE
@W: MT462 :|Net RST_c appears to be an unidentified clock source. Assuming default frequency. 
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Resource Usage Report

Simple gate primitives:
DFFRH           17 uses
DFF             33 uses
DFFSH           28 uses
BI_DIR          11 uses
IBUF            32 uses
OBUF            16 uses
BUFTH           2 uses
AND2            230 uses
INV             180 uses
DLATRH          1 use
OR2             20 uses
XOR2            9 uses


@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
G-2012.09LC-SP1 
Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 96MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Feb 03 20:27:45 2015

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