#$ TOOL  ispLEVER Classic 1.7.00.05.28.13
#$ DATE  Thu May 15 19:20:52 2014
#$ MODULE  BUS68030
#$ PINS 59 A_30_ A_29_ SIZE_1_ A_28_ A_27_ A_31_ A_26_ A_25_ A_24_ A_23_ IPL_2_
 A_22_ A_21_ A_20_ A_19_ FC_1_ A_18_ AS_030 A_17_ A_16_ DS_030 CPU_SPACE BERR
 BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_EXP A_0_ AVEC AVEC_EXP IPL_1_ VPA
 IPL_0_ DSACK_0_ RST FC_0_ RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR
 AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000
 BG_000 BGACK_030 CLK_DIV_OUT FPU_CS DTACK IPL_030_1_ IPL_030_0_ E VMA RESET
#$ NODES 28 cpu_est_1_ inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D
 inst_VPA_SYNC inst_CLK_000_D inst_CLK_000_DD inst_CLK_OUT_PRE cpu_est_0_
 cpu_est_2_ CLK_CNT_0_ SM_AMIGA_6_ SM_AMIGA_7_ inst_RISING_CLK_AMIGA SM_AMIGA_4_
 SM_AMIGA_3_ SM_AMIGA_5_ CLK_000_CNT_0_ CLK_000_CNT_1_ CLK_000_CNT_2_
 CLK_000_CNT_3_ SM_AMIGA_2_ SM_AMIGA_1_ SM_AMIGA_0_ SM_AMIGA_D_0_ SM_AMIGA_D_1_
 SM_AMIGA_D_2_ un1_UDS_000_INT_0_sqmuxa_2_0
.type f
.i 77
.o 128
.ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 CPU_SPACE BG_030 BGACK_000 CLK_030
 CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_
 A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_
 BGACK_030.Q FPU_CS.Q E.Q VMA.Q cpu_est_1_.Q AS_000.Q inst_AS_030_000_SYNC.Q
 inst_DTACK_SYNC.Q inst_VPA_D.Q inst_VPA_SYNC.Q inst_CLK_000_D.Q
 inst_CLK_000_DD.Q inst_CLK_OUT_PRE.Q cpu_est_0_.Q cpu_est_2_.Q CLK_CNT_0_.Q
 SM_AMIGA_6_.Q BG_000.Q SM_AMIGA_7_.Q UDS_000.Q LDS_000.Q inst_RISING_CLK_AMIGA.Q
 DSACK_1_.Q SM_AMIGA_4_.Q SM_AMIGA_3_.Q SM_AMIGA_5_.Q CLK_000_CNT_0_.Q
 CLK_000_CNT_1_.Q CLK_000_CNT_2_.Q CLK_000_CNT_3_.Q IPL_030_0_.Q SM_AMIGA_2_.Q
 IPL_030_1_.Q SM_AMIGA_1_.Q SM_AMIGA_0_.Q IPL_030_2_.Q SM_AMIGA_D_0_.Q
 SM_AMIGA_D_1_.Q SM_AMIGA_D_2_.Q un1_UDS_000_INT_0_sqmuxa_2_0 DSACK_1_.PIN
 DTACK.PIN
.ob BERR BERR.OE CLK_EXP.X1 CLK_EXP.X2 AVEC AVEC_EXP AVEC_EXP.OE DSACK_0_
 DSACK_0_.OE AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN
 CIIN.OE IPL_030_2_.D IPL_030_2_.C IPL_030_2_.AP DSACK_1_.D% DSACK_1_.C
 DSACK_1_.AP DSACK_1_.OE AS_000.D% AS_000.C AS_000.AP AS_000.OE UDS_000.D%
 UDS_000.C UDS_000.AP UDS_000.OE LDS_000.D LDS_000.C LDS_000.AP LDS_000.OE
 BG_000.D% BG_000.C BG_000.AP BGACK_030.D BGACK_030.C BGACK_030.AP CLK_DIV_OUT.D
 CLK_DIV_OUT.C FPU_CS.D% FPU_CS.C FPU_CS.AP DTACK.D% DTACK.C DTACK.AP DTACK.OE
 IPL_030_1_.D IPL_030_1_.C IPL_030_1_.AP IPL_030_0_.D IPL_030_0_.C IPL_030_0_.AP
 E.T E.C VMA.D VMA.C VMA.AP RESET.D RESET.C cpu_est_1_.T cpu_est_1_.C
 inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP
 inst_DTACK_SYNC.D% inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_VPA_D.D
 inst_VPA_D.C inst_VPA_SYNC.D% inst_VPA_SYNC.C inst_VPA_SYNC.AP inst_CLK_000_D.D
 inst_CLK_000_D.C inst_CLK_000_DD.D inst_CLK_000_DD.C inst_CLK_OUT_PRE.D
 inst_CLK_OUT_PRE.C cpu_est_0_.D cpu_est_0_.C cpu_est_2_.D.X1 cpu_est_2_.D.X2
 cpu_est_2_.C CLK_CNT_0_.D CLK_CNT_0_.C SM_AMIGA_6_.D SM_AMIGA_6_.C
 SM_AMIGA_6_.AR SM_AMIGA_7_.D SM_AMIGA_7_.C SM_AMIGA_7_.AP
 inst_RISING_CLK_AMIGA.D inst_RISING_CLK_AMIGA.C SM_AMIGA_4_.D SM_AMIGA_4_.C
 SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_5_.D
 SM_AMIGA_5_.C SM_AMIGA_5_.AR CLK_000_CNT_0_.D% CLK_000_CNT_0_.C CLK_000_CNT_1_.D
 CLK_000_CNT_1_.C CLK_000_CNT_2_.D% CLK_000_CNT_2_.C CLK_000_CNT_3_.T
 CLK_000_CNT_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D%
 SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR
 SM_AMIGA_D_0_.D% SM_AMIGA_D_0_.C SM_AMIGA_D_1_.D% SM_AMIGA_D_1_.C
 SM_AMIGA_D_2_.D% SM_AMIGA_D_2_.C un1_UDS_000_INT_0_sqmuxa_2_0
.phase 11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
.p 142
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.end