@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral 
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":65:10:65:11|Using sequential encoding for type sm_e
@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":82:14:82:15|Using sequential encoding for type sm_68000
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:7:124:17|Signal clk_out_pre is undriven 
Post processing for work.bus68030.behavioral
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Pruning register DS_030_D0_3  
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Pruning register AMIGA_BUS_ENABLE_INT_4  
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_000_D4_2  
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_000_D3_2  
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_000_D2_2  
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":155:2:155:3|Pruning register CLK_030_D0_2  
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:61:134:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ... 
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ... 
@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ...
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Trying to extract state machine for register SM_AMIGA
Extracted state machine for register SM_AMIGA
State machine has 8 reachable states with original encodings of:
   000
   001
   010
   011
   100
   101
   110
   111
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Trying to extract state machine for register cpu_est
@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":23:1:23:1|Input port bits 15 to 2 of a(31 downto 2) are unused