[DEVICE]
Family = M4A5;
PartType = M4A5-128/64;
Package = 100TQFP;
PartNumber = M4A5-128/64-10VC;
Speed = -10;
Operating_condition = COM;
EN_Segment = No;
Pin_MC_1to1 = No;
EN_PinReserve_IO = Yes;
EN_PinReserve_BIDIR = Yes;
Voltage = 5.0;

[REVISION]
RCS = "$Revision: 1.2 $";
Parent = m4a5.lci;
SDS_File = m4a5.sds;
Design = 68030_tk.tt4;
DATE = 8/19/16;
TIME = 00:39:40;
Source_Format = Pure_VHDL;
Type = TT2;
Pre_Fit_Time = 1;

[IGNORE ASSIGNMENTS]
Pin_Assignments = No;
Pin_Keep_Block = No;
Pin_Keep_Segment = No;
Group_Assignments = No;
Macrocell_Assignments = No;
Macrocell_Keep_Block = No;
Macrocell_Keep_Segment = No;
Pin_Reservation = No;
Block_Reservation = No;
Segment_Reservation = No;
Timing_Constraints = No;

[CLEAR ASSIGNMENTS]
Pin_Assignments = No;
Pin_Keep_Block = No;
Pin_Keep_Segment = No;
Group_Assignments = No;
Macrocell_Assignments = No;
Macrocell_Keep_Block = No;
Macrocell_Keep_Segment = No;
Pin_Reservation = No;
Block_Reservation = No;
Segment_Reservation = No;
Timing_Constraints = No;

[BACKANNOTATE ASSIGNMENTS]
Pin_Block = No;
Pin_Macrocell_Block = No;
Routing = No;

[GLOBAL CONSTRAINTS]
Max_PTerm_Split = 16;
Max_PTerm_Collapse = 16;
Max_Pin_Percent = 100;
Max_Macrocell_Percent = 100;
Max_GLB_Input_Percent = 100;
Max_Seg_In_Percent = 100;
Logic_Reduction = Yes;
XOR_Synthesis = Yes;
DT_Synthesis = Yes;
Node_Collapse = Yes;
Run_Time = 0;
Set_Reset_Dont_Care = No;
Clock_Optimize = No;
In_Reg_Optimize = Yes;
Balanced_Partitioning = Yes;
Device_max_fanin = 33;
Device_max_pterms = 20;
Usercode = 0;
Usercode_Format = Hex;

[LOCATION ASSIGNMENTS]
Layer = OFF;
SIZE_1_ = pin,79,-,H,-;
AHIGH_31_ = pin,4,-,B,-;
A_DECODE_23_ = pin,85,-,H,-;
IPL_2_ = pin,68,-,G,-;
FC_1_ = pin,58,-,F,-;
AS_030 = pin,82,-,H,-;
AS_000 = pin,42,-,E,-;
DS_030 = pin,98,-,A,-;
UDS_000 = pin,32,-,D,-;
LDS_000 = pin,31,-,D,-;
nEXP_SPACE = pin,14,-,-,-;
BERR = pin,41,-,E,-;
BG_030 = pin,21,-,C,-;
SIZE_0_ = pin,70,-,G,-;
AHIGH_30_ = pin,5,-,B,-;
BGACK_000 = pin,28,-,D,-;
AHIGH_29_ = pin,6,-,B,-;
CLK_030 = pin,64,-,-,-;
AHIGH_28_ = pin,15,-,C,-;
CLK_000 = pin,11,-,-,-;
AHIGH_27_ = pin,16,-,C,-;
CLK_OSZI = pin,61,-,-,-;
AHIGH_26_ = pin,17,-,C,-;
CLK_DIV_OUT = pin,65,-,G,-;
AHIGH_25_ = pin,18,-,C,-;
AHIGH_24_ = pin,19,-,C,-;
FPU_CS = pin,78,-,H,-;
A_DECODE_22_ = pin,84,-,H,-;
FPU_SENSE = pin,91,-,A,-;
A_DECODE_21_ = pin,94,-,A,-;
A_DECODE_20_ = pin,93,-,A,-;
DTACK = pin,30,-,D,-;
A_DECODE_19_ = pin,97,-,A,-;
AVEC = pin,92,-,A,-;
A_DECODE_18_ = pin,95,-,A,-;
E = pin,66,-,G,-;
A_DECODE_17_ = pin,59,-,F,-;
VPA = pin,36,-,-,-;
A_DECODE_16_ = pin,96,-,A,-;
RST = pin,86,-,-,-;
RESET = pin,3,-,B,-;
AMIGA_ADDR_ENABLE = pin,33,-,D,-;
AMIGA_BUS_DATA_DIR = pin,48,-,E,-;
AMIGA_BUS_ENABLE_LOW = pin,20,-,C,-;
AMIGA_BUS_ENABLE_HIGH = pin,34,-,D,-;
CIIN = pin,47,-,E,-;
IPL_1_ = pin,56,-,F,-;
IPL_0_ = pin,67,-,G,-;
FC_0_ = pin,57,-,F,-;
A_1_ = pin,60,-,F,-;
IPL_030_2_ = pin,9,-,B,-;
RW_000 = pin,80,-,H,-;
BG_000 = pin,29,-,D,-;
BGACK_030 = pin,83,-,H,-;
CLK_EXP = pin,10,-,B,-;
DSACK1 = pin,81,-,H,-;
VMA = pin,35,-,D,-;
RW = pin,71,-,G,-;
A_0_ = pin,69,-,G,-;
IPL_030_1_ = pin,7,-,B,-;
IPL_030_0_ = pin,8,-,B,-;
cpu_est_3_ = node,-,-,D,9;
cpu_est_0_ = node,-,-,D,2;
cpu_est_1_ = node,-,-,F,8;
cpu_est_2_ = node,-,-,D,13;
inst_AS_000_INT = node,-,-,C,15;
inst_AMIGA_BUS_ENABLE_DMA_LOW = node,-,-,G,10;
inst_AS_030_D0 = node,-,-,A,6;
inst_AS_030_000_SYNC = node,-,-,C,6;
inst_BGACK_030_INT_D = node,-,-,H,13;
inst_AS_000_DMA = node,-,-,A,12;
inst_DS_000_DMA = node,-,-,A,1;
CYCLE_DMA_0_ = node,-,-,A,13;
CYCLE_DMA_1_ = node,-,-,A,9;
SIZE_DMA_0_ = node,-,-,G,2;
SIZE_DMA_1_ = node,-,-,G,9;
inst_VPA_D = node,-,-,F,2;
inst_UDS_000_INT = node,-,-,D,10;
inst_LDS_000_INT = node,-,-,D,6;
inst_CLK_OUT_PRE_D = node,-,-,E,8;
CLK_000_D_1_ = node,-,-,H,3;
CLK_000_D_10_ = node,-,-,C,14;
CLK_000_D_11_ = node,-,-,H,0;
inst_DTACK_D0 = node,-,-,G,7;
inst_RESET_OUT = node,-,-,A,8;
CLK_000_D_0_ = node,-,-,C,13;
inst_CLK_OUT_PRE_50 = node,-,-,E,6;
IPL_D0_0_ = node,-,-,B,3;
IPL_D0_1_ = node,-,-,B,14;
IPL_D0_2_ = node,-,-,A,3;
CLK_000_D_2_ = node,-,-,E,2;
CLK_000_D_3_ = node,-,-,E,9;
CLK_000_D_4_ = node,-,-,C,11;
CLK_000_D_5_ = node,-,-,E,5;
CLK_000_D_6_ = node,-,-,D,14;
CLK_000_D_7_ = node,-,-,A,14;
CLK_000_D_8_ = node,-,-,G,3;
CLK_000_D_9_ = node,-,-,A,10;
CLK_000_D_12_ = node,-,-,G,14;
inst_AMIGA_BUS_ENABLE_DMA_HIGH = node,-,-,G,6;
inst_DS_000_ENABLE = node,-,-,B,6;
SM_AMIGA_6_ = node,-,-,C,2;
SM_AMIGA_0_ = node,-,-,G,5;
SM_AMIGA_4_ = node,-,-,B,10;
RST_DLY_0_ = node,-,-,F,0;
RST_DLY_1_ = node,-,-,F,13;
RST_DLY_2_ = node,-,-,F,9;
inst_CLK_030_H = node,-,-,A,5;
SM_AMIGA_1_ = node,-,-,F,1;
SM_AMIGA_5_ = node,-,-,F,5;
SM_AMIGA_3_ = node,-,-,F,10;
SM_AMIGA_2_ = node,-,-,F,6;
SM_AMIGA_i_7_ = node,-,-,F,4;
CIIN_0 = node,-,-,E,10;

[GROUP ASSIGNMENTS]
Layer = OFF;

[RESOURCE RESERVATIONS]
Layer = OFF;

[SLEWRATE]
Default = SLOW;
FAST =  CLK_DIV_OUT,CLK_EXP,FPU_CS,AMIGA_BUS_DATA_DIR,AMIGA_BUS_ENABLE_LOW,AMIGA_ADDR_ENABLE,AMIGA_BUS_ENABLE_HIGH;

[PULLUP]
Default = Up;

[NETLIST/DELAY FORMAT]
Delay_File = SDF;
Netlist = VHDL;

[OSM BYPASS]

[FITTER REPORT FORMAT]
Fitter_Options = Yes;
Pinout_Diagram = No;
Pinout_Listing = Yes;
Detailed_Block_Segment_Summary = Yes;
Input_Signal_List = Yes;
Output_Signal_List = Yes;
Bidir_Signal_List = Yes;
Node_Signal_List = Yes;
Signal_Fanout_List = Yes;
Block_Segment_Fanin_List = Yes;
Postfit_Eqn = Yes;
Prefit_Eqn = Yes;
Page_Break = Yes;

[POWER]
Powerlevel =  Low,High;
Default = High;
Low =  H,G,F,E,D,C,B,A;
Type = GLB;

[SOURCE CONSTRAINT OPTION]

[TIMING ANALYZER]
Last_source=;
Last_source_type=Fmax;