[DEVICE]

Family = M4A5;
PartType = M4A5-128/64;
Package = 100TQFP;
PartNumber = M4A5-128/64-10VC;
Speed = -10;
Operating_condition = COM;
EN_Segment = NO;
Pin_MC_1to1 = NO;
Voltage = 5.0;

[REVISION]

RCS = "$Revision: 1.2 $";
Parent = m4a5.lci;
SDS_file = m4a5.sds;
Design = 68030_tk.tt4;
Rev = 0.01;
DATE = 8/19/16;
TIME = 00:39:40;
Type = TT2;
Pre_Fit_Time = 1;
Source_Format = Pure_VHDL;

[IGNORE ASSIGNMENTS]

Pin_Assignments = NO;
Pin_Keep_Block = NO;
Pin_Keep_Segment = NO;
Group_Assignments = NO;
Macrocell_Assignments = NO;
Macrocell_Keep_Block = NO;
Macrocell_Keep_Segment = NO;
Pin_Reservation = NO;
Timing_Constraints = NO;
Block_Reservation = NO;
Segment_Reservation = NO;
Ignore_Source_Location = NO;
Ignore_Source_Optimization = NO;
Ignore_Source_Timing = NO;

[CLEAR ASSIGNMENTS]

Pin_Assignments = NO;
Pin_Keep_Block = NO;
Pin_Keep_Segment = NO;
Group_Assignments = NO;
Macrocell_Assignments = NO;
Macrocell_Keep_Block = NO;
Macrocell_Keep_Segment = NO;
Pin_Reservation = NO;
Timing_Constraints = NO;
Block_Reservation = NO;
Segment_Reservation = NO;
Ignore_Source_Location = NO;
Ignore_Source_Optimization = NO;
Ignore_Source_Timing = NO;

[BACKANNOTATE NETLIST]

Netlist = VHDL;
Delay_File = SDF;
Generic_VCC = ;
Generic_GND = ;

[BACKANNOTATE ASSIGNMENTS]

Pin_Assignment = NO;
Pin_Block = NO;
Pin_Macrocell_Block = NO;
Routing = NO;

[GLOBAL PROJECT OPTIMIZATION]

Balanced_Partitioning = YES;
Spread_Placement = YES;
Max_Pin_Percent = 100;
Max_Macrocell_Percent = 100;
Max_Inter_Seg_Percent = 100;
Max_Seg_In_Percent = 100;
Max_Blk_In_Percent = 100;

[FITTER REPORT FORMAT]

Fitter_Options = YES;
Pinout_Diagram = NO;
Pinout_Listing = YES;
Detailed_Block_Segment_Summary = YES;
Input_Signal_List = YES;
Output_Signal_List = YES;
Bidir_Signal_List = YES;
Node_Signal_List = YES;
Signal_Fanout_List = YES;
Block_Segment_Fanin_List = YES;
Prefit_Eqn = YES;
Postfit_Eqn = YES;
Page_Break = YES;

[OPTIMIZATION OPTIONS]

Logic_Reduction = YES;
Max_PTerm_Split = 16;
Max_PTerm_Collapse = 16;
XOR_Synthesis = YES;
Node_Collapse = Yes;
DT_Synthesis = Yes;

[FITTER GLOBAL OPTIONS]

Run_Time = 0;
Set_Reset_Dont_Care = NO;
In_Reg_Optimize = YES;
Clock_Optimize = NO;
Conf_Unused_IOs = OUT_LOW;

[POWER]
Powerlevel = Low, High;
Default = High;
Low = 8, H, G, F, E, D, C, B, A;
Type = GLB;

[HARDWARE DEVICE OPTIONS]
Zero_Hold_Time = Yes;
Signature_Word = 0;
Pull_up = Yes;
Out_Slew_Rate = SLOW, FAST, 7, CLK_DIV_OUT, CLK_EXP, FPU_CS, AMIGA_BUS_DATA_DIR, AMIGA_BUS_ENABLE_LOW, 
	AMIGA_ADDR_ENABLE, AMIGA_BUS_ENABLE_HIGH;
Device_max_fanin = 33;
Device_max_pterms = 20;
Usercode_Format = Hex;

[PIN RESERVATIONS]
layer = OFF;

[LOCATION ASSIGNMENT]

Layer = OFF;
SIZE_1_ = BIDIR,79, H,-;
AHIGH_31_ = BIDIR,4, B,-;
A_DECODE_23_ = INPUT,85, H,-;
IPL_2_ = INPUT,68, G,-;
FC_1_ = INPUT,58, F,-;
AS_030 = BIDIR,82, H,-;
AS_000 = BIDIR,42, E,-;
DS_030 = OUTPUT,98, A,-;
UDS_000 = BIDIR,32, D,-;
LDS_000 = BIDIR,31, D,-;
nEXP_SPACE = INPUT,14,-,-;
BERR = BIDIR,41, E,-;
BG_030 = INPUT,21, C,-;
SIZE_0_ = BIDIR,70, G,-;
AHIGH_30_ = BIDIR,5, B,-;
BGACK_000 = INPUT,28, D,-;
AHIGH_29_ = BIDIR,6, B,-;
CLK_030 = INPUT,64,-,-;
AHIGH_28_ = BIDIR,15, C,-;
CLK_000 = INPUT,11,-,-;
AHIGH_27_ = BIDIR,16, C,-;
CLK_OSZI = INPUT,61,-,-;
AHIGH_26_ = BIDIR,17, C,-;
CLK_DIV_OUT = OUTPUT,65, G,-;
AHIGH_25_ = BIDIR,18, C,-;
AHIGH_24_ = BIDIR,19, C,-;
FPU_CS = OUTPUT,78, H,-;
A_DECODE_22_ = INPUT,84, H,-;
FPU_SENSE = INPUT,91, A,-;
A_DECODE_21_ = INPUT,94, A,-;
A_DECODE_20_ = INPUT,93, A,-;
DTACK = INPUT,30, D,-;
A_DECODE_19_ = INPUT,97, A,-;
AVEC = OUTPUT,92, A,-;
A_DECODE_18_ = INPUT,95, A,-;
E = OUTPUT,66, G,-;
A_DECODE_17_ = INPUT,59, F,-;
VPA = INPUT,36,-,-;
A_DECODE_16_ = INPUT,96, A,-;
RST = INPUT,86,-,-;
RESET = OUTPUT,3, B,-;
AMIGA_ADDR_ENABLE = OUTPUT,33, D,-;
AMIGA_BUS_DATA_DIR = OUTPUT,48, E,-;
AMIGA_BUS_ENABLE_LOW = OUTPUT,20, C,-;
AMIGA_BUS_ENABLE_HIGH = OUTPUT,34, D,-;
CIIN = OUTPUT,47, E,-;
IPL_1_ = INPUT,56, F,-;
IPL_0_ = INPUT,67, G,-;
FC_0_ = INPUT,57, F,-;
A_1_ = INPUT,60, F,-;
IPL_030_2_ = OUTPUT,9, B,-;
RW_000 = BIDIR,80, H,-;
BG_000 = OUTPUT,29, D,-;
BGACK_030 = OUTPUT,83, H,-;
CLK_EXP = OUTPUT,10, B,-;
DSACK1 = OUTPUT,81, H,-;
VMA = OUTPUT,35, D,-;
RW = BIDIR,71, G,-;
A_0_ = BIDIR,69, G,-;
IPL_030_1_ = OUTPUT,7, B,-;
IPL_030_0_ = OUTPUT,8, B,-;
cpu_est_3_ = NODE,9, D,-;
cpu_est_0_ = NODE,2, D,-;
cpu_est_1_ = NODE,8, F,-;
cpu_est_2_ = NODE,13, D,-;
inst_AS_000_INT = NODE,15, C,-;
inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,10, G,-;
inst_AS_030_D0 = NODE,6, A,-;
inst_AS_030_000_SYNC = NODE,6, C,-;
inst_BGACK_030_INT_D = NODE,13, H,-;
inst_AS_000_DMA = NODE,12, A,-;
inst_DS_000_DMA = NODE,1, A,-;
CYCLE_DMA_0_ = NODE,13, A,-;
CYCLE_DMA_1_ = NODE,9, A,-;
SIZE_DMA_0_ = NODE,2, G,-;
SIZE_DMA_1_ = NODE,9, G,-;
inst_VPA_D = NODE,2, F,-;
inst_UDS_000_INT = NODE,10, D,-;
inst_LDS_000_INT = NODE,6, D,-;
inst_CLK_OUT_PRE_D = NODE,8, E,-;
CLK_000_D_1_ = NODE,3, H,-;
CLK_000_D_10_ = NODE,14, C,-;
CLK_000_D_11_ = NODE,0, H,-;
inst_DTACK_D0 = NODE,7, G,-;
inst_RESET_OUT = NODE,8, A,-;
CLK_000_D_0_ = NODE,13, C,-;
inst_CLK_OUT_PRE_50 = NODE,6, E,-;
IPL_D0_0_ = NODE,3, B,-;
IPL_D0_1_ = NODE,14, B,-;
IPL_D0_2_ = NODE,3, A,-;
CLK_000_D_2_ = NODE,2, E,-;
CLK_000_D_3_ = NODE,9, E,-;
CLK_000_D_4_ = NODE,11, C,-;
CLK_000_D_5_ = NODE,5, E,-;
CLK_000_D_6_ = NODE,14, D,-;
CLK_000_D_7_ = NODE,14, A,-;
CLK_000_D_8_ = NODE,3, G,-;
CLK_000_D_9_ = NODE,10, A,-;
CLK_000_D_12_ = NODE,14, G,-;
inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,6, G,-;
inst_DS_000_ENABLE = NODE,6, B,-;
SM_AMIGA_6_ = NODE,2, C,-;
SM_AMIGA_0_ = NODE,5, G,-;
SM_AMIGA_4_ = NODE,10, B,-;
RST_DLY_0_ = NODE,0, F,-;
RST_DLY_1_ = NODE,13, F,-;
RST_DLY_2_ = NODE,9, F,-;
inst_CLK_030_H = NODE,5, A,-;
SM_AMIGA_1_ = NODE,1, F,-;
SM_AMIGA_5_ = NODE,5, F,-;
SM_AMIGA_3_ = NODE,10, F,-;
SM_AMIGA_2_ = NODE,6, F,-;
SM_AMIGA_i_7_ = NODE,4, F,-;
CIIN_0 = NODE,10, E,-;