@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral 
Post processing for work.bus68030.behavioral
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":136:34:136:36|Pruning register CLK_000_NE_D  
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":117:53:117:56|Pruning register FPU_CS_INT  
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:32:138:34|Pruning register CLK_REF(1 downto 0)  
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":110:29:110:31|Pruning register DTACK_D0  
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_000_D4  
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:35:124:37|Pruning register CLK_OUT_NE  
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:61:133:75|Pruning bit 12 of CLK_000_N_SYNC(12 downto 0) -- not in use ... 
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":102:36:102:38|Pruning bits 12 to 10 of CLK_000_P_SYNC(12 downto 0) -- not in use ... 
@A: CL282 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:35:137:37|Feedback mux created for signal CLK_030_H -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:32:138:34|Trying to extract state machine for register SM_AMIGA
Extracted state machine for register SM_AMIGA
State machine has 8 reachable states with original encodings of:
   000
   001
   010
   011
   100
   101
   110
   111
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:34:126:36|Trying to extract state machine for register cpu_est
Extracted state machine for register cpu_est
State machine has 11 reachable states with original encodings of:
   0000
   0010
   0011
   0100
   0101
   0110
   0111
   1010
   1011
   1100
   1111