[Device]
Family = M4A5;
PartNumber = M4A5-128/64-10VC;
Package = 100TQFP;
PartType = M4A5-128/64;
Speed = -10;
Operating_condition = COM;
Status = Production;
EN_PinGLB = Yes;
EN_PinMacrocell = Yes;

[Revision]
Parent = m4a5.lci;
DATE = 02/16/2017;
TIME = 19:15:23;
Source_Format = Pure_VHDL;
Synthesis = Synplify;

[Ignore Assignments]

[Clear Assignments]

[Backannotate Assignments]

[Global Constraints]
Spread_placement = Yes;
Zero_hold_time = Yes;
Max_pterm_split = 20;
Max_pterm_collapse = 20;
Nodes_collapsing_mode = Speed;
Max_fanin = 32;
Set_reset_dont_care = Yes;
Balanced_partitioning = Yes;
Max_macrocell_percent = 100;
Dt_synthesis = Yes;
Xor_synthesis = Yes;
Logic_reduction = Yes;
Node_collapse = Yes;

[Location Assignments]
layer = OFF;
AS_030 = Pin, 82, -, H, -;
A_16_ = Pin, 96, -, A, -;
A_17_ = Pin, 59, -, F, -;
A_18_ = Pin, 95, -, A, -;
A_19_ = Pin, 97, -, A, -;
BGACK_000 = Pin, 28, -, D, -;
BG_030 = Pin, 21, -, C, -;
CLK_000 = Pin, 11, -, -, -;
CLK_030 = Pin, 64, -, -, -;
CLK_OSZI = Pin, 61, -, -, -;
FC_0_ = Pin, 57, -, F, -;
FC_1_ = Pin, 58, -, F, -;
IPL_0_ = Pin, 67, -, G, -;
IPL_1_ = Pin, 56, -, F, -;
IPL_2_ = Pin, 68, -, G, -;
RST = Pin, 86, -, -, -;
RW = Pin, 71, -, G, -;
SIZE_1_ = Pin, 79, -, H, -;
SIZE_0_ = Pin, 70, -, G, -;
VPA = Pin, 36, -, -, -;
AVEC = Pin, 92, -, A, -;
BGACK_030 = Pin, 83, -, H, -;
BG_000 = Pin, 29, -, D, -;
CLK_DIV_OUT = Pin, 65, -, G, -;
CLK_EXP = Pin, 10, -, B, -;
E = Pin, 66, -, G, -;
FPU_CS = Pin, 78, -, H, -;
IPL_030_0_ = Pin, 8, -, B, -;
IPL_030_1_ = Pin, 7, -, B, -;
IPL_030_2_ = Pin, 9, -, B, -;
LDS_000 = Pin, 31, -, D, -;
UDS_000 = Pin, 32, -, D, -;
VMA = Pin, 35, -, D, -;
DTACK = Pin, 30, -, D, -;
RESET = Pin, 3, -, B, -;
AMIGA_BUS_DATA_DIR = Pin, 48, -, E, -;
AMIGA_BUS_ENABLE_LOW = Pin, 20, -, C, -;
CIIN = Pin, 47, -, E, -;
A_20_ = Pin, 93, -, A, -;
A_21_ = Pin, 94, -, A, -;
A_22_ = Pin, 84, -, H, -;
A_24_ = Pin, 19, -, C, -;
A_25_ = Pin, 18, -, C, -;
A_26_ = Pin, 17, -, C, -;
A_27_ = Pin, 16, -, C, -;
A_28_ = Pin, 15, -, C, -;
A_29_ = Pin, 6, -, B, -;
A_30_ = Pin, 5, -, B, -;
A_31_ = Pin, 4, -, B, -;
DS_030 = Pin, 98, -, A, -;
BERR = Pin, 41, -, E, -;
nEXP_SPACE = Pin, 14, -, -, -;
A0 = Pin, 69, -, G, -;
DSACK1 = Pin, 81, -, H, -;
RW_000 = Pin, 80, -, H, -;
AS_000 = Pin, 42, -, E, -;
AMIGA_ADDR_ENABLE = Pin, 33, -, D, -;
AMIGA_BUS_ENABLE_HIGH = Pin, 34, -, D, -;
A_23_ = Pin, 85, -, H, -;
FPU_SENSE = Pin, 91, -, A, -;
A1 = Pin, 60, -, F, -;
A_3_ = Pin, 44, -, E, -;
A_2_ = Pin, 43, -, E, -;
AHIGH_24_ = Pin, 19, -, C, -;
AHIGH_25_ = Pin, 18, -, C, -;
AHIGH_26_ = Pin, 17, -, C, -;
AHIGH_27_ = Pin, 16, -, C, -;
AHIGH_28_ = Pin, 15, -, C, -;
AHIGH_29_ = Pin, 6, -, B, -;
AHIGH_30_ = Pin, 5, -, B, -;
AHIGH_31_ = Pin, 4, -, B, -;
A_1_ = Pin, 60, -, F, -;
A_0_ = Pin, 69, -, G, -;
A_DECODE_16_ = Pin, 96, -, A, -;
A_DECODE_17_ = Pin, 59, -, F, -;
A_DECODE_18_ = Pin, 95, -, A, -;
A_DECODE_19_ = Pin, 97, -, A, -;
A_DECODE_20_ = Pin, 93, -, A, -;
A_DECODE_21_ = Pin, 94, -, A, -;
A_DECODE_22_ = Pin, 84, -, H, -;
A_DECODE_23_ = Pin, 85, -, H, -;

[Group Assignments]
layer = OFF;

[Resource Reservations]
layer = OFF;

[Fitter Report Format]

[Power]
Default = High;
Low = H, G, F, E, D, C, B, A;
High = B;

[Source Constraint Option]

[Fast Bypass]

[OSM Bypass]

[Input Registers]

[Netlist/Delay Format]
NetList = VHDL;

[IO Types]
layer = OFF;

[Pullup]
Default = HOLD;

[Slewrate]
FAST = CLK_DIV_OUT, CLK_EXP, FPU_CS, AMIGA_BUS_DATA_DIR, AMIGA_BUS_ENABLE_LOW, 
	AMIGA_ADDR_ENABLE, AMIGA_BUS_ENABLE_HIGH, AS_030, A_16_, A_17_, A_18_, 
	A_19_, RW, SIZE_1_, SIZE_0_, AVEC, BGACK_030, BG_000, E, IPL_030_0_, IPL_030_1_, 
	IPL_030_2_, LDS_000, UDS_000, VMA, RESET, CIIN, A_20_, A_21_, A_22_, A_24_, 
	A_25_, A_26_, A_27_, A_28_, A_29_, A_30_, A_31_, DS_030, BERR, A0, DSACK1, 
	RW_000, AS_000, A_23_, A1, A_3_, A_2_, AHIGH_24_, AHIGH_25_, AHIGH_26_, 
	AHIGH_27_, AHIGH_28_, AHIGH_29_, AHIGH_30_, AHIGH_31_, A_0_;
Default = Slow;

[Region]

[Timing Constraints]

[HSI Attributes]

[Input Delay]

[opt global constraints list]

[Explorer User Settings]

[Pin attributes list]

[global constraints list]

[Global Constraints Process Update]

[pin lock limitation]

[LOCATION ASSIGNMENTS LIST]

[RESOURCE RESERVATIONS LIST]

[individual constraints list]

[Attributes list setting]

[Timing Analyzer]

[PLL Assignments]

[Dual Function Macrocell]

[Explorer Results]

[VHDL synplify constraints]

[VHDL spectrum constraints]

[verilog synplify constraints]

[verilog spectrum constraints]

[VHDL synplify constraints list]

[VHDL spectrum constraints list]

[verilog synplify constraints list]

[verilog spectrum constraints list]

[Constraint Version]
version = 1.0;

[ORP ASSIGNMENTS]
layer = OFF;

[Node attribute]
layer = OFF;

[SYMBOL/MODULE attribute]
layer = OFF;