ispLEVER Classic 2.0.00.17.20.15 Linked Equations File Copyright(C), 1992-2015, Lattice Semiconductor Corp. All Rights Reserved. Design bus68030 created Sat Dec 30 00:43:37 2017 P-Terms Fan-in Fan-out Type Name (attributes) --------- ------ ------- ---- ----------------- 0 0 1 Pin AHIGH_27_ 1 1 1 Pin AHIGH_27_.OE 0 0 1 Pin AHIGH_26_ 1 1 1 Pin AHIGH_26_.OE 0 0 1 Pin AHIGH_25_ 1 1 1 Pin AHIGH_25_.OE 0 0 1 Pin AHIGH_24_ 1 1 1 Pin AHIGH_24_.OE 0 0 1 Pin AHIGH_31_ 1 1 1 Pin AHIGH_31_.OE 1 2 1 Pin AS_030- 1 1 1 Pin AS_030.OE 1 2 1 Pin AS_000- 1 2 1 Pin AS_000.OE 1 2 1 Pin DS_030- 1 1 1 Pin DS_030.OE 1 2 1 Pin UDS_000- 1 2 1 Pin UDS_000.OE 1 2 1 Pin LDS_000- 1 2 1 Pin LDS_000.OE 0 0 1 Pin BERR 1 9 1 Pin BERR.OE 1 1 1 Pin CLK_DIV_OUT 1 1 1 Pin CLK_EXP 1 9 1 Pin FPU_CS- 1 2 1 Pin DSACK1- 1 2 1 Pin DSACK1.OE 1 0 1 Pin AVEC 2 3 1 Pin E 0 0 1 Pin AMIGA_ADDR_ENABLE 2 4 1 Pin AMIGA_BUS_DATA_DIR 1 2 1 Pin AMIGA_BUS_ENABLE_LOW- 2 4 1 Pin AMIGA_BUS_ENABLE_HIGH- 1 13 1 Pin CIIN 1 1 1 Pin CIIN.OE 0 0 1 Pin AHIGH_30_ 1 1 1 Pin AHIGH_30_.OE 0 0 1 Pin AHIGH_29_ 1 1 1 Pin AHIGH_29_.OE 0 0 1 Pin AHIGH_28_ 1 1 1 Pin AHIGH_28_.OE 1 1 1 Pin SIZE_1_.OE 2 4 1 Pin SIZE_1_.D 1 1 1 Pin SIZE_1_.C 10 8 1 Pin IPL_030_2_.D- 1 1 1 Pin IPL_030_2_.C 1 2 1 Pin RW_000.OE 4 8 1 Pin RW_000.D- 1 1 1 Pin RW_000.C 2 6 1 Pin BG_000.D- 1 1 1 Pin BG_000.C 3 6 1 Pin BGACK_030.D 1 1 1 Pin BGACK_030.C 1 1 1 Pin A_0_.OE 2 3 1 Pin A_0_.D 1 1 1 Pin A_0_.C 10 8 1 Pin IPL_030_1_.D- 1 1 1 Pin IPL_030_1_.C 10 8 1 Pin IPL_030_0_.D- 1 1 1 Pin IPL_030_0_.C 1 1 1 Pin VMA.OE 3 9 1 Pin VMA.T 1 1 1 Pin VMA.C 1 1 1 Pin RW.OE 1 3 1 Pin RW.D- 1 1 1 Pin RW.C 1 1 1 Pin SIZE_0_.OE 2 4 1 Pin SIZE_0_.D- 1 1 1 Pin SIZE_0_.C 3 3 1 Node cpu_est_0_.D 1 1 1 Node cpu_est_0_.C 4 5 1 Node cpu_est_1_.D 1 1 1 Node cpu_est_1_.C 1 4 1 NodeX1 cpu_est_2_.D.X1 1 1 1 NodeX2 cpu_est_2_.D.X2 1 1 1 Node cpu_est_2_.C 4 6 1 Node cpu_est_3_.D 1 1 1 Node cpu_est_3_.C 1 3 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- 1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.C 1 3 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.D- 1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.C 1 2 1 Node inst_AS_030_D0.D- 1 1 1 Node inst_AS_030_D0.C 2 3 1 Node inst_AS_030_D1.D 1 1 1 Node inst_AS_030_D1.C 7 14 1 Node inst_AS_030_000_SYNC.D- 1 1 1 Node inst_AS_030_000_SYNC.C 6 9 1 Node inst_AS_000_DMA.D 1 1 1 Node inst_AS_000_DMA.C 6 9 1 Node inst_DS_000_DMA.D 1 1 1 Node inst_DS_000_DMA.C 1 2 1 Node inst_VPA_D.D- 1 1 1 Node inst_VPA_D.C 1 1 1 Node CLK_000_D_3_.D 1 1 1 Node CLK_000_D_3_.C 1 2 1 Node inst_DTACK_D0.D- 1 1 1 Node inst_DTACK_D0.C 2 3 1 Node inst_AMIGA_DS.D 1 1 1 Node inst_AMIGA_DS.C 1 1 1 Node CLK_000_D_1_.D 1 1 1 Node CLK_000_D_1_.C 1 1 1 Node CLK_000_D_0_.D 1 1 1 Node CLK_000_D_0_.C 1 1 1 Node inst_CLK_OUT_PRE_50.D 1 1 1 Node inst_CLK_OUT_PRE_50.C 1 1 1 Node inst_CLK_OUT_PRE_D.D 1 1 1 Node inst_CLK_OUT_PRE_D.C 1 2 1 Node IPL_D0_0_.D- 1 1 1 Node IPL_D0_0_.C 1 2 1 Node IPL_D0_1_.D- 1 1 1 Node IPL_D0_1_.C 1 2 1 Node IPL_D0_2_.D- 1 1 1 Node IPL_D0_2_.C 1 1 1 Node CLK_000_D_2_.D 1 1 1 Node CLK_000_D_2_.C 1 1 1 Node CLK_000_D_4_.D 1 1 1 Node CLK_000_D_4_.C 2 4 1 Node inst_UDS_000_INT.D- 1 1 1 Node inst_UDS_000_INT.C 3 8 1 Node inst_DS_000_ENABLE.D 1 1 1 Node inst_DS_000_ENABLE.C 3 6 1 Node inst_LDS_000_INT.D 1 1 1 Node inst_LDS_000_INT.C 1 2 1 Node inst_BGACK_030_INT_D.D- 1 1 1 Node inst_BGACK_030_INT_D.C 3 9 1 Node SM_AMIGA_6_.D 1 1 1 Node SM_AMIGA_6_.C 3 5 1 Node SM_AMIGA_4_.D 1 1 1 Node SM_AMIGA_4_.C 3 5 1 Node SM_AMIGA_1_.D 1 1 1 Node SM_AMIGA_1_.C 3 5 1 Node SM_AMIGA_0_.D 1 1 1 Node SM_AMIGA_0_.C 4 7 1 Node CYCLE_DMA_0_.D 1 1 1 Node CYCLE_DMA_0_.C 2 7 1 Node CYCLE_DMA_1_.D 1 1 1 Node CYCLE_DMA_1_.C 2 6 1 Node inst_DSACK1_INT.D- 1 1 1 Node inst_DSACK1_INT.C 2 6 1 Node inst_AS_000_INT.D- 1 1 1 Node inst_AS_000_INT.C 3 5 1 Node SM_AMIGA_5_.D 1 1 1 Node SM_AMIGA_5_.C 5 13 1 Node SM_AMIGA_3_.T 1 1 1 Node SM_AMIGA_3_.C 5 13 1 Node SM_AMIGA_2_.D 1 1 1 Node SM_AMIGA_2_.C 1 1 1 Node CLK_OUT_INTreg.D 1 1 1 Node CLK_OUT_INTreg.C 3 9 1 NodeX1 SM_AMIGA_i_7_.T.X1 1 9 1 NodeX2 SM_AMIGA_i_7_.T.X2 1 1 1 Node SM_AMIGA_i_7_.C 2 14 1 Node N_60 ========= 243 P-Term Total: 243 Total Pins: 59 Total Nodes: 42 Average P-Term/Output: 2 Equations: AHIGH_27_ = (0); AHIGH_27_.OE = (!BGACK_030.Q); AHIGH_26_ = (0); AHIGH_26_.OE = (!BGACK_030.Q); AHIGH_25_ = (0); AHIGH_25_.OE = (!BGACK_030.Q); AHIGH_24_ = (0); AHIGH_24_.OE = (!BGACK_030.Q); AHIGH_31_ = (0); AHIGH_31_.OE = (!BGACK_030.Q); !AS_030 = (!inst_AS_000_DMA.Q & !AS_000.PIN); AS_030.OE = (!BGACK_030.Q); !AS_000 = (!inst_AS_000_INT.Q & !AS_030.PIN); AS_000.OE = (RST & BGACK_030.Q); !DS_030 = (!inst_DS_000_DMA.Q & !AS_000.PIN); DS_030.OE = (!BGACK_030.Q); !UDS_000 = (!inst_UDS_000_INT.Q & inst_DS_000_ENABLE.Q); UDS_000.OE = (RST & BGACK_030.Q); !LDS_000 = (inst_DS_000_ENABLE.Q & !inst_LDS_000_INT.Q); LDS_000.OE = (RST & BGACK_030.Q); BERR = (0); BERR.OE = (FC_1_ & BGACK_000 & FPU_SENSE & !A_DECODE_19_ & !A_DECODE_18_ & A_DECODE_17_ & !A_DECODE_16_ & FC_0_ & !AS_030.PIN); CLK_DIV_OUT = (CLK_OUT_INTreg.Q); CLK_EXP = (CLK_OUT_INTreg.Q); !FPU_CS = (FC_1_ & BGACK_000 & !FPU_SENSE & !A_DECODE_19_ & !A_DECODE_18_ & A_DECODE_17_ & !A_DECODE_16_ & FC_0_ & !AS_030.PIN); !DSACK1 = (!inst_DSACK1_INT.Q & !AS_030.PIN); DSACK1.OE = (nEXP_SPACE & BGACK_030.Q); AVEC = (1); E = (!cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q # cpu_est_1_.Q & cpu_est_2_.Q & !cpu_est_3_.Q); AMIGA_ADDR_ENABLE = (0); AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW_000.PIN # !nEXP_SPACE & !BGACK_030.Q & !AS_000.PIN & RW_000.PIN); !AMIGA_BUS_ENABLE_LOW = (!BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_LOW.Q); !AMIGA_BUS_ENABLE_HIGH = (!BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q # BGACK_030.Q & !inst_AS_030_000_SYNC.Q & !AS_030.PIN); CIIN = (A_DECODE_23_ & A_DECODE_22_ & A_DECODE_21_ & A_DECODE_20_ & !inst_AS_030_D0.Q & !AHIGH_24_.PIN & !AHIGH_25_.PIN & !AHIGH_26_.PIN & !AHIGH_27_.PIN & !AHIGH_28_.PIN & !AHIGH_29_.PIN & !AHIGH_30_.PIN & !AHIGH_31_.PIN); CIIN.OE = (N_60); AHIGH_30_ = (0); AHIGH_30_.OE = (!BGACK_030.Q); AHIGH_29_ = (0); AHIGH_29_.OE = (!BGACK_030.Q); AHIGH_28_ = (0); AHIGH_28_.OE = (!BGACK_030.Q); SIZE_1_.OE = (!BGACK_030.Q); SIZE_1_.D = (!RST # !BGACK_030.Q & !UDS_000.PIN & !LDS_000.PIN); SIZE_1_.C = (CLK_OSZI); !IPL_030_2_.D = (!IPL_2_ & RST & !IPL_030_2_.Q # RST & !IPL_D0_2_.Q & !IPL_030_2_.Q # RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_2_.Q # RST & IPL_0_ & !IPL_D0_0_.Q & !IPL_030_2_.Q # RST & !IPL_1_ & IPL_D0_1_.Q & !IPL_030_2_.Q # RST & IPL_1_ & !IPL_D0_1_.Q & !IPL_030_2_.Q # !IPL_2_ & RST & IPL_1_ & IPL_0_ & IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q # !IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q # !IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q # !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q); IPL_030_2_.C = (CLK_OSZI); RW_000.OE = (RST & BGACK_030.Q); !RW_000.D = (RST & CLK_000_D_1_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q # RST & !CLK_000_D_0_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q # RST & !SM_AMIGA_6_.Q & !RW_000.Q & !SM_AMIGA_0_.Q & SM_AMIGA_i_7_.Q # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & SM_AMIGA_i_7_.Q & !RW.PIN); RW_000.C = (CLK_OSZI); !BG_000.D = (!BG_030 & RST & !BG_000.Q # nEXP_SPACE & !BG_030 & RST & inst_AS_030_D0.Q & CLK_000_D_0_.Q); BG_000.C = (CLK_OSZI); BGACK_030.D = (!RST # BGACK_000 & BGACK_030.Q # BGACK_000 & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & AS_000.PIN); BGACK_030.C = (CLK_OSZI); A_0_.OE = (!BGACK_030.Q); A_0_.D = (!RST # !BGACK_030.Q & UDS_000.PIN); A_0_.C = (CLK_OSZI); !IPL_030_1_.D = (RST & !IPL_1_ & !IPL_030_1_.Q # RST & !IPL_D0_1_.Q & !IPL_030_1_.Q # RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_1_.Q # RST & IPL_0_ & !IPL_D0_0_.Q & !IPL_030_1_.Q # !IPL_2_ & RST & IPL_D0_2_.Q & !IPL_030_1_.Q # IPL_2_ & RST & !IPL_D0_2_.Q & !IPL_030_1_.Q # IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q # IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q # !IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q # !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q); IPL_030_1_.C = (CLK_OSZI); !IPL_030_0_.D = (RST & !IPL_0_ & !IPL_030_0_.Q # RST & !IPL_D0_0_.Q & !IPL_030_0_.Q # RST & !IPL_1_ & IPL_D0_1_.Q & !IPL_030_0_.Q # RST & IPL_1_ & !IPL_D0_1_.Q & !IPL_030_0_.Q # !IPL_2_ & RST & IPL_D0_2_.Q & !IPL_030_0_.Q # IPL_2_ & RST & !IPL_D0_2_.Q & !IPL_030_0_.Q # IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & IPL_D0_2_.Q # IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q # !IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q # !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q); IPL_030_0_.C = (CLK_OSZI); VMA.OE = (BGACK_030.Q); VMA.T = (!RST & !VMA.Q # !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & !VMA.Q & !CLK_000_D_1_.Q & CLK_000_D_0_.Q # RST & cpu_est_0_.Q & cpu_est_1_.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & VMA.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q); VMA.C = (CLK_OSZI); RW.OE = (!BGACK_030.Q); !RW.D = (RST & !BGACK_030.Q & !RW_000.PIN); RW.C = (CLK_OSZI); SIZE_0_.OE = (!BGACK_030.Q); !SIZE_0_.D = (RST & BGACK_030.Q # RST & !UDS_000.PIN & !LDS_000.PIN); SIZE_0_.C = (CLK_OSZI); cpu_est_0_.D = (cpu_est_0_.Q & !CLK_000_D_1_.Q # cpu_est_0_.Q & CLK_000_D_0_.Q # !cpu_est_0_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q); cpu_est_0_.C = (CLK_OSZI); cpu_est_1_.D = (!cpu_est_0_.Q & cpu_est_1_.Q # cpu_est_1_.Q & !CLK_000_D_1_.Q # cpu_est_1_.Q & CLK_000_D_0_.Q # cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_3_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q); cpu_est_1_.C = (CLK_OSZI); cpu_est_2_.D.X1 = (cpu_est_0_.Q & cpu_est_1_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q); cpu_est_2_.D.X2 = (cpu_est_2_.Q); cpu_est_2_.C = (CLK_OSZI); cpu_est_3_.D = (!cpu_est_0_.Q & cpu_est_3_.Q # cpu_est_3_.Q & !CLK_000_D_1_.Q # cpu_est_3_.Q & CLK_000_D_0_.Q # cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q); cpu_est_3_.C = (CLK_OSZI); !inst_AMIGA_BUS_ENABLE_DMA_HIGH.D = (RST & !A_1_ & !BGACK_030.Q); inst_AMIGA_BUS_ENABLE_DMA_HIGH.C = (CLK_OSZI); !inst_AMIGA_BUS_ENABLE_DMA_LOW.D = (RST & A_1_ & !BGACK_030.Q); inst_AMIGA_BUS_ENABLE_DMA_LOW.C = (CLK_OSZI); !inst_AS_030_D0.D = (RST & !AS_030.PIN); inst_AS_030_D0.C = (CLK_OSZI); inst_AS_030_D1.D = (RST & inst_AS_030_D0.Q # !RST & inst_AS_030_D1.Q); inst_AS_030_D1.C = (CLK_OSZI); !inst_AS_030_000_SYNC.D = (RST & !inst_AS_030_000_SYNC.Q & !AS_030.PIN # !FC_1_ & nEXP_SPACE & RST & BGACK_030.Q & !inst_AS_030_D1.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN # nEXP_SPACE & RST & A_DECODE_19_ & BGACK_030.Q & !inst_AS_030_D1.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN # nEXP_SPACE & RST & A_DECODE_18_ & BGACK_030.Q & !inst_AS_030_D1.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN # nEXP_SPACE & RST & !A_DECODE_17_ & BGACK_030.Q & !inst_AS_030_D1.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN # nEXP_SPACE & RST & A_DECODE_16_ & BGACK_030.Q & !inst_AS_030_D1.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN # nEXP_SPACE & RST & !FC_0_ & BGACK_030.Q & !inst_AS_030_D1.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN); inst_AS_030_000_SYNC.C = (CLK_OSZI); inst_AS_000_DMA.D = (!RST # inst_AMIGA_DS.Q # AS_000.PIN # !CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q # inst_AS_000_DMA.Q & inst_CLK_OUT_PRE_D.Q & !CLK_OUT_INTreg.Q # CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !RW_000.PIN); inst_AS_000_DMA.C = (CLK_OSZI); inst_DS_000_DMA.D = (!RST # inst_AMIGA_DS.Q # AS_000.PIN # !CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q # inst_DS_000_DMA.Q & inst_CLK_OUT_PRE_D.Q & !CLK_OUT_INTreg.Q # CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !RW_000.PIN); inst_DS_000_DMA.C = (CLK_OSZI); !inst_VPA_D.D = (!VPA & RST); inst_VPA_D.C = (CLK_OSZI); CLK_000_D_3_.D = (CLK_000_D_2_.Q); CLK_000_D_3_.C = (CLK_OSZI); !inst_DTACK_D0.D = (!DTACK & RST); inst_DTACK_D0.C = (CLK_OSZI); inst_AMIGA_DS.D = (!RST # UDS_000.PIN & LDS_000.PIN); inst_AMIGA_DS.C = (CLK_OSZI); CLK_000_D_1_.D = (CLK_000_D_0_.Q); CLK_000_D_1_.C = (CLK_OSZI); CLK_000_D_0_.D = (CLK_000); CLK_000_D_0_.C = (CLK_OSZI); inst_CLK_OUT_PRE_50.D = (!inst_CLK_OUT_PRE_50.Q); inst_CLK_OUT_PRE_50.C = (CLK_OSZI); inst_CLK_OUT_PRE_D.D = (inst_CLK_OUT_PRE_50.Q); inst_CLK_OUT_PRE_D.C = (CLK_OSZI); !IPL_D0_0_.D = (RST & !IPL_0_); IPL_D0_0_.C = (CLK_OSZI); !IPL_D0_1_.D = (RST & !IPL_1_); IPL_D0_1_.C = (CLK_OSZI); !IPL_D0_2_.D = (!IPL_2_ & RST); IPL_D0_2_.C = (CLK_OSZI); CLK_000_D_2_.D = (CLK_000_D_1_.Q); CLK_000_D_2_.C = (CLK_OSZI); CLK_000_D_4_.D = (CLK_000_D_3_.Q); CLK_000_D_4_.C = (CLK_OSZI); !inst_UDS_000_INT.D = (RST & !inst_UDS_000_INT.Q & !SM_AMIGA_6_.Q # RST & SM_AMIGA_6_.Q & !A_0_.PIN); inst_UDS_000_INT.C = (CLK_OSZI); inst_DS_000_ENABLE.D = (RST & inst_DS_000_ENABLE.Q & !AS_030.PIN # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_4_.Q # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q & RW.PIN); inst_DS_000_ENABLE.C = (CLK_OSZI); inst_LDS_000_INT.D = (!RST # inst_LDS_000_INT.Q & !SM_AMIGA_6_.Q # SM_AMIGA_6_.Q & SIZE_0_.PIN & !SIZE_1_.PIN & !A_0_.PIN); inst_LDS_000_INT.C = (CLK_OSZI); !inst_BGACK_030_INT_D.D = (RST & !BGACK_030.Q); inst_BGACK_030_INT_D.C = (CLK_OSZI); SM_AMIGA_6_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_6_.Q # RST & !CLK_000_D_0_.Q & SM_AMIGA_6_.Q # nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_3_.Q & CLK_000_D_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_i_7_.Q); SM_AMIGA_6_.C = (CLK_OSZI); SM_AMIGA_4_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_4_.Q # RST & !CLK_000_D_0_.Q & SM_AMIGA_4_.Q # RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_5_.Q); SM_AMIGA_4_.C = (CLK_OSZI); SM_AMIGA_1_.D = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_2_.Q # RST & !CLK_000_D_1_.Q & SM_AMIGA_1_.Q & !SM_AMIGA_2_.Q # RST & CLK_000_D_0_.Q & SM_AMIGA_1_.Q & !SM_AMIGA_2_.Q); SM_AMIGA_1_.C = (CLK_OSZI); SM_AMIGA_0_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_0_.Q # RST & !CLK_000_D_0_.Q & SM_AMIGA_0_.Q # RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_1_.Q); SM_AMIGA_0_.C = (CLK_OSZI); CYCLE_DMA_0_.D = (RST & !BGACK_030.Q & !CLK_000_D_1_.Q & CYCLE_DMA_0_.Q & !AS_000.PIN # RST & !BGACK_030.Q & CLK_000_D_0_.Q & CYCLE_DMA_0_.Q & !AS_000.PIN # RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_000.PIN # RST & !BGACK_030.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & !CYCLE_DMA_0_.Q & !AS_000.PIN); CYCLE_DMA_0_.C = (CLK_OSZI); CYCLE_DMA_1_.D = (RST & !BGACK_030.Q & CYCLE_DMA_1_.Q & !AS_000.PIN # RST & !BGACK_030.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & CYCLE_DMA_0_.Q & !AS_000.PIN); CYCLE_DMA_1_.C = (CLK_OSZI); !inst_DSACK1_INT.D = (RST & !inst_DSACK1_INT.Q & !AS_030.PIN # RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_1_.Q); inst_DSACK1_INT.C = (CLK_OSZI); !inst_AS_000_INT.D = (RST & !inst_AS_000_INT.Q & !AS_030.PIN # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q); inst_AS_000_INT.C = (CLK_OSZI); SM_AMIGA_5_.D = (RST & !CLK_000_D_1_.Q & SM_AMIGA_5_.Q # RST & CLK_000_D_0_.Q & SM_AMIGA_5_.Q # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q); SM_AMIGA_5_.C = (CLK_OSZI); SM_AMIGA_3_.T = (!RST & SM_AMIGA_3_.Q # CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & !BERR.PIN # inst_VPA_D.Q & !inst_DTACK_D0.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_4_.Q & !SM_AMIGA_3_.Q # !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !VMA.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q); SM_AMIGA_3_.C = (CLK_OSZI); SM_AMIGA_2_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_2_.Q # RST & !CLK_000_D_0_.Q & SM_AMIGA_2_.Q # RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & !BERR.PIN # RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q # RST & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !VMA.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q); SM_AMIGA_2_.C = (CLK_OSZI); CLK_OUT_INTreg.D = (inst_CLK_OUT_PRE_D.Q); CLK_OUT_INTreg.C = (CLK_OSZI); SM_AMIGA_i_7_.T.X1 = (!RST & SM_AMIGA_i_7_.Q # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_0_.Q & SM_AMIGA_i_7_.Q # nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_3_.Q & CLK_000_D_4_.Q & !SM_AMIGA_i_7_.Q); SM_AMIGA_i_7_.T.X2 = (nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_3_.Q & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & CLK_000_D_4_.Q & SM_AMIGA_0_.Q & !SM_AMIGA_i_7_.Q); SM_AMIGA_i_7_.C = (CLK_OSZI); N_60 = (nEXP_SPACE # A_DECODE_23_ & A_DECODE_22_ & A_DECODE_21_ & A_DECODE_20_ & !inst_AS_030_D0.Q & !AHIGH_24_.PIN & !AHIGH_25_.PIN & !AHIGH_26_.PIN & !AHIGH_27_.PIN & !AHIGH_28_.PIN & !AHIGH_29_.PIN & !AHIGH_30_.PIN & !AHIGH_31_.PIN); Reverse-Polarity Equations: