@W: CD638 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":130:7:130:17|Signal clk_out_pre is undriven 
@W: CD638 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":134:7:134:15|Signal clk_030_h is undriven 
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":133:38:133:40|Pruning register DTACK_DMA_4  
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":133:38:133:40|Pruning register CLK_030_PE_2(1 downto 0)  
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":133:38:133:40|Pruning register AS_000_D0_3  
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":133:38:133:40|Pruning register RESET_OUT_4  
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":133:38:133:40|Pruning register RST_DLY_6(2 downto 0)  
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":133:38:133:40|Pruning register DS_030_D0_3  
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":133:38:133:40|Pruning register nEXP_SPACE_D0_3  
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":133:38:133:40|Pruning register BGACK_030_INT_PRE_2  
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_OUT_EXP_INT_1  
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":128:36:128:38|Pruning register CLK_OUT_PRE_25_3  
@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":158:2:158:3|Pruning register CLK_030_D0_2  
@W: CL271 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":133:38:133:40|Pruning bits 12 to 5 of CLK_000_D_3(12 downto 0) -- not in use ... 
@W: CL246 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":24:1:24:8|Input port bits 15 to 2 of a_decode(23 downto 2) are unused 
@W: CL159 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":34:1:34:7|Input CLK_030 is unused
@W: CL158 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":50:1:50:5|Inout RESET is unused