#$ TOOL  ispLEVER Classic 2.0.00.17.20.15
#$ DATE  Wed Sep 14 23:54:26 2016
#$ MODULE  BUS68030
#$ PINS 61 SIZE_1_ AHIGH_31_ A_DECODE_23_ IPL_2_ FC_1_ AS_030 AS_000 DS_030
 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 SIZE_0_
 CLK_OSZI AHIGH_30_ CLK_DIV_OUT AHIGH_29_ AHIGH_28_ FPU_CS AHIGH_27_ FPU_SENSE
 AHIGH_26_ AHIGH_25_ DTACK AHIGH_24_ AVEC A_DECODE_22_ E A_DECODE_21_ VPA
 A_DECODE_20_ A_DECODE_19_ RST A_DECODE_18_ RESET A_DECODE_17_ A_DECODE_16_
 AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH
 CIIN IPL_1_ IPL_0_ FC_0_ A_1_ IPL_030_2_ RW_000 BG_000 BGACK_030 CLK_EXP DSACK1
 VMA RW A_0_ IPL_030_1_ IPL_030_0_
#$ NODES 44 cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_ inst_AS_000_INT
 inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_000_SYNC
 inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_
 SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D CLK_000_D_1_ inst_DTACK_D0 inst_RESET_OUT
 CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 inst_CLK_OUT_PRE_D
 IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ inst_AMIGA_BUS_ENABLE_DMA_HIGH
 inst_LDS_000_INT inst_DS_000_ENABLE inst_UDS_000_INT SM_AMIGA_6_ SM_AMIGA_4_
 SM_AMIGA_1_ SM_AMIGA_0_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ inst_CLK_030_H
 SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ CIIN_0
.type f
.i 96
.o 161
.ilb A_DECODE_23_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000
 CLK_OSZI FPU_SENSE DTACK VPA RST A_DECODE_22_ A_DECODE_21_ A_DECODE_20_
 A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_1_ IPL_0_ FC_0_ A_1_
 BGACK_030.Q VMA.Q cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q
 inst_AS_000_INT.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q
 inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q
 inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q
 inst_VPA_D.Q CLK_000_D_1_.Q inst_DTACK_D0.Q inst_RESET_OUT.Q CLK_000_D_0_.Q
 inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_25.Q inst_CLK_OUT_PRE_D.Q IPL_D0_0_.Q
 IPL_D0_1_.Q IPL_D0_2_.Q CLK_000_D_2_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q
 inst_LDS_000_INT.Q inst_DS_000_ENABLE.Q inst_UDS_000_INT.Q SM_AMIGA_6_.Q
 SM_AMIGA_4_.Q SM_AMIGA_1_.Q SM_AMIGA_0_.Q RW_000.Q RW.Q RST_DLY_0_.Q
 RST_DLY_1_.Q RST_DLY_2_.Q A_0_.Q inst_CLK_030_H.Q SM_AMIGA_5_.Q SM_AMIGA_3_.Q
 SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q
 AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN
 AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN
 AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN CIIN_0
.ob SIZE_1_ SIZE_1_.OE AHIGH_31_ AHIGH_31_.OE AS_030- AS_030.OE AS_000-
 AS_000.OE DS_030- DS_030.OE UDS_000- UDS_000.OE LDS_000- LDS_000.OE BERR BERR.OE
 SIZE_0_ SIZE_0_.OE AHIGH_30_ AHIGH_30_.OE CLK_DIV_OUT.D CLK_DIV_OUT.C AHIGH_29_
 AHIGH_29_.OE AHIGH_28_ AHIGH_28_.OE FPU_CS- AHIGH_27_ AHIGH_27_.OE AHIGH_26_
 AHIGH_26_.OE AHIGH_25_ AHIGH_25_.OE AHIGH_24_ AHIGH_24_.OE AVEC E RESET RESET.OE
 AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW- AMIGA_BUS_ENABLE_HIGH
 CIIN CIIN.OE IPL_030_2_.D- IPL_030_2_.C RW_000.D- RW_000.C RW_000.OE BG_000.D-
 BG_000.C BGACK_030.D BGACK_030.C CLK_EXP.D CLK_EXP.C DSACK1.D- DSACK1.C
 DSACK1.OE VMA.T VMA.C RW.D- RW.C RW.OE A_0_.D A_0_.C A_0_.OE IPL_030_1_.D-
 IPL_030_1_.C IPL_030_0_.D- IPL_030_0_.C cpu_est_2_.D.X1 cpu_est_2_.D.X2
 cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D
 cpu_est_1_.C inst_AS_000_INT.D- inst_AS_000_INT.C
 inst_AMIGA_BUS_ENABLE_DMA_LOW.D- inst_AMIGA_BUS_ENABLE_DMA_LOW.C
 inst_AS_030_D0.D- inst_AS_030_D0.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C
 inst_BGACK_030_INT_D.D- inst_BGACK_030_INT_D.C inst_AS_000_DMA.D
 inst_AS_000_DMA.C inst_DS_000_DMA.D inst_DS_000_DMA.C CYCLE_DMA_0_.D
 CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D- SIZE_DMA_0_.C
 SIZE_DMA_1_.D SIZE_DMA_1_.C inst_VPA_D.D- inst_VPA_D.C CLK_000_D_1_.D
 CLK_000_D_1_.C inst_DTACK_D0.D- inst_DTACK_D0.C inst_RESET_OUT.D
 inst_RESET_OUT.C CLK_000_D_0_.D CLK_000_D_0_.C inst_CLK_OUT_PRE_50.D
 inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_25.D inst_CLK_OUT_PRE_25.C
 inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C IPL_D0_0_.D- IPL_D0_0_.C IPL_D0_1_.D-
 IPL_D0_1_.C IPL_D0_2_.D- IPL_D0_2_.C CLK_000_D_2_.D CLK_000_D_2_.C
 inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- inst_AMIGA_BUS_ENABLE_DMA_HIGH.C
 inst_LDS_000_INT.D inst_LDS_000_INT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C
 inst_UDS_000_INT.D- inst_UDS_000_INT.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_4_.D
 SM_AMIGA_4_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C
 RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D.X1 RST_DLY_1_.D.X2 RST_DLY_1_.C
 RST_DLY_2_.D RST_DLY_2_.C inst_CLK_030_H.D inst_CLK_030_H.C SM_AMIGA_5_.D
 SM_AMIGA_5_.C SM_AMIGA_3_.T SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C
 SM_AMIGA_i_7_.D.X1 SM_AMIGA_i_7_.D.X2 SM_AMIGA_i_7_.C CIIN_0
.phase 11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
.p 183
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.end