|--------------------------------------------| |- ispLEVER Fitter Report File -| |- Version 1.7.00.05.28.13 -| |- (c)Copyright, Lattice Semiconductor 2002 -| |--------------------------------------------| Project_Summary ~~~~~~~~~~~~~~~ Project Name : 68030_tk Project Path : C:\Users\Matze\Documents\GitHub\68030tk\Logic Project Fitted on : Sun Jun 22 21:24:26 2014 Device : M4A5-128/64 Package : 100TQFP Speed : -10 Partnumber : M4A5-128/64-10VC Source Format : Pure_VHDL // Project '68030_tk' was Fitted Successfully! // Compilation_Times ~~~~~~~~~~~~~~~~~ Reading/DRC 0 sec Partition 0 sec Place 0 sec Route 0 sec Jedec/Report generation 0 sec -------- Fitter 00:00:00 Design_Summary ~~~~~~~~~~~~~~ Total Input Pins : 30 Total Output Pins : 17 Total Bidir I/O Pins : 12 Total Flip-Flops : 76 Total Product Terms : 173 Total Reserved Pins : 0 Total Reserved Blocks : 0 Device_Resource_Summary ~~~~~~~~~~~~~~~~~~~~~~~ Total Available Used Available Utilization Dedicated Pins Input-Only Pins 2 2 0 --> 100% Clock/Input Pins 4 4 0 --> 100% I/O Pins 64 53 11 --> 82% Logic Macrocells 128 86 42 --> 67% Input Registers 64 0 64 --> 0% Unusable Macrocells .. 0 .. CSM Outputs/Total Block Inputs 264 204 60 --> 77% Logical Product Terms 640 174 466 --> 27% Product Term Clusters 128 45 83 --> 35%  Blocks_Resource_Summary ~~~~~~~~~~~~~~~~~~~~~~~ # of PT I/O Inp Macrocells Macrocells logic clusters Fanin Pins Reg Used Unusable available PTs available Pwr --------------------------------------------------------------------------------- Maximum 33 8 8 -- -- 16 80 16 - --------------------------------------------------------------------------------- Block A 22 7 0 11 0 5 23 12 Hi Block B 23 8 0 11 0 5 18 10 Hi Block C 25 8 0 11 0 5 16 14 Hi Block D 31 8 0 11 0 5 23 8 Hi Block E 27 3 0 11 0 5 17 11 Hi Block F 25 4 0 10 0 6 34 7 Hi Block G 24 7 0 11 0 5 25 11 Hi Block H 27 8 0 10 0 6 18 11 Hi --------------------------------------------------------------------------------- Four rightmost columns above reflect last status of the placement process. Pwr (Power) : Hi = High Lo = Low.  Optimizer_and_Fitter_Options ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Pin Assignment : Yes Group Assignment : No Pin Reservation : No (1) Block Reservation : No @Ignore_Project_Constraints : Pin Assignments : No Keep Block Assignment -- Keep Segment Assignment -- Group Assignments : No Macrocell Assignment : No Keep Block Assignment -- Keep Segment Assignment -- @Backannotate_Project_Constraints Pin Assignments : No Pin And Block Assignments : No Pin, Macrocell and Block : No @Timing_Constraints : No @Global_Project_Optimization : Balanced Partitioning : Yes Spread Placement : Yes Note : Pack Design : Balanced Partitioning = No Spread Placement = No Spread Design : Balanced Partitioning = Yes Spread Placement = Yes @Logic_Synthesis : Logic Reduction : Yes Node Collapsing : Yes D/T Synthesis : Yes Clock Optimization : No Input Register Optimization : Yes XOR Synthesis : Yes Max. P-Term for Collapsing : 16 Max. P-Term for Splitting : 16 Max. Equation Fanin : 32 Keep Xor : Yes @Utilization_options Max. % of macrocells used : 100 Max. % of block inputs used : 100 Max. % of segment lines used : --- Max. % of macrocells used : --- @Import_Source_Constraint_Option No @Zero_Hold_Time Yes @Pull_up Yes @User_Signature #H0 @Output_Slew_Rate Default = Slow(2) @Power Default = High(2) Device Options: 1 : Reserved unused I/Os can be independently driven to Low or High, and does not follow the drive level set for the Global Configure Unused I/O Option. 2 : For user-specified constraints on individual signals, refer to the Output, Bidir and Burried Signal Lists.  Pinout_Listing ~~~~~~~~~~~~~~ | Pin |Blk |Assigned| Pin No| Type |Pad |Pin | Signal name --------------------------------------------------------------- 1 | GND | | | 2 | JTAG | | | 3 | I_O | B7 | * |RESET 4 | I_O | B6 | * |A_31_ 5 | I_O | B5 | * |A_30_ 6 | I_O | B4 | * |A_29_ 7 | I_O | B3 | * |IPL_030_1_ 8 | I_O | B2 | * |IPL_030_0_ 9 | I_O | B1 | * |IPL_030_2_ 10 | I_O | B0 | * |CLK_EXP 11 | CkIn | | * |CLK_000 12 | Vcc | | | 13 | GND | | | 14 | CkIn | | * |nEXP_SPACE 15 | I_O | C0 | * |A_28_ 16 | I_O | C1 | * |A_27_ 17 | I_O | C2 | * |A_26_ 18 | I_O | C3 | * |A_25_ 19 | I_O | C4 | * |A_24_ 20 | I_O | C5 | * |AMIGA_BUS_ENABLE_LOW 21 | I_O | C6 | * |BG_030 22 | I_O | C7 | * |AVEC_EXP 23 | JTAG | | | 24 | JTAG | | | 25 | GND | | | 26 | GND | | | 27 | GND | | | 28 | I_O | D7 | * |BGACK_000 29 | I_O | D6 | * |BG_000 30 | I_O | D5 | * |DTACK 31 | I_O | D4 | * |LDS_000 32 | I_O | D3 | * |UDS_000 33 | I_O | D2 | * |AS_000 34 | I_O | D1 | * |AMIGA_BUS_ENABLE 35 | I_O | D0 | * |VMA 36 | Inp | | * |VPA 37 | Vcc | | | 38 | GND | | | 39 | GND | | | 40 | Vcc | | | 41 | I_O | E0 | * |BERR 42 | I_O | E1 | | 43 | I_O | E2 | | 44 | I_O | E3 | | 45 | I_O | E4 | | 46 | I_O | E5 | | 47 | I_O | E6 | * |CIIN 48 | I_O | E7 | * |AMIGA_BUS_DATA_DIR 49 | GND | | | 50 | GND | | | 51 | GND | | | 52 | JTAG | | | 53 | I_O | F7 | | 54 | I_O | F6 | | 55 | I_O | F5 | | 56 | I_O | F4 | * |IPL_1_ 57 | I_O | F3 | * |FC_0_ 58 | I_O | F2 | * |FC_1_ 59 | I_O | F1 | * |A_17_ 60 | I_O | F0 | | 61 | CkIn | | * |CLK_OSZI 62 | Vcc | | | 63 | GND | | | 64 | CkIn | | * |CLK_030 65 | I_O | G0 | * |CLK_DIV_OUT 66 | I_O | G1 | * |E 67 | I_O | G2 | * |IPL_0_ 68 | I_O | G3 | * |IPL_2_ 69 | I_O | G4 | * |A0 70 | I_O | G5 | * |SIZE_0_ 71 | I_O | G6 | * |RW 72 | I_O | G7 | | 73 | JTAG | | | 74 | JTAG | | | 75 | GND | | | 76 | GND | | | 77 | GND | | | 78 | I_O | H7 | * |FPU_CS 79 | I_O | H6 | * |SIZE_1_ 80 | I_O | H5 | * |RW_000 81 | I_O | H4 | * |DSACK1 82 | I_O | H3 | * |AS_030 83 | I_O | H2 | * |BGACK_030 84 | I_O | H1 | * |A_23_ 85 | I_O | H0 | * |A_22_ 86 | Inp | | * |RST 87 | Vcc | | | 88 | GND | | | 89 | GND | | | 90 | Vcc | | | 91 | I_O | A0 | | 92 | I_O | A1 | * |AVEC 93 | I_O | A2 | * |A_20_ 94 | I_O | A3 | * |A_21_ 95 | I_O | A4 | * |A_18_ 96 | I_O | A5 | * |A_16_ 97 | I_O | A6 | * |A_19_ 98 | I_O | A7 | * |DS_030 99 | GND | | | 100 | GND | | | --------------------------------------------------------------------------- Blk Pad : This notation refers to the Block I/O pad number in the device. Assigned Pin : user or dedicated input assignment (E.g. Clock pins). Pin Type : CkIn : Dedicated input or clock pin CLK : Dedicated clock pin INP : Dedicated input pin JTAG : JTAG Control and test pin NC : No connected  Input_Signal_List ~~~~~~~~~~~~~~~~~ P R Pin r e O Input Pin Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- 96 A . I/O --C----H Hi Slow A_16_ 59 F . I/O --C----H Hi Slow A_17_ 95 A . I/O --C----H Hi Slow A_18_ 97 A . I/O --C----H Hi Slow A_19_ 93 A . I/O ----E--- Hi Slow A_20_ 94 A . I/O ----E--- Hi Slow A_21_ 85 H . I/O ----E--- Hi Slow A_22_ 84 H . I/O ----E--- Hi Slow A_23_ 19 C . I/O ----E--- Hi Slow A_24_ 18 C . I/O ----E--- Hi Slow A_25_ 17 C . I/O ----E--- Hi Slow A_26_ 16 C . I/O ----E--- Hi Slow A_27_ 15 C . I/O ----E--- Hi Slow A_28_ 6 B . I/O ----E--- Hi Slow A_29_ 5 B . I/O ----E--- Hi Slow A_30_ 4 B . I/O ----E--- Hi Slow A_31_ 41 E . I/O -BCD-F-H Hi Slow BERR 28 D . I/O --C----H Hi Slow BGACK_000 21 C . I/O ---D---- Hi Slow BG_030 57 F . I/O --C----H Hi Slow FC_0_ 58 F . I/O --C----H Hi Slow FC_1_ 67 G . I/O -B------ Hi Slow IPL_0_ 56 F . I/O -B------ Hi Slow IPL_1_ 68 G . I/O -B------ Hi Slow IPL_2_ 11 . . Ck/I ---D-F-- - Slow CLK_000 14 . . Ck/I A-CDEFGH - Slow nEXP_SPACE 36 . . Ded --C--F-- - Slow VPA 61 . . Ck/I ABCDEFGH - Slow CLK_OSZI 64 . . Ck/I A-----GH - Slow CLK_030 86 . . Ded ABCDEFGH - Slow RST ---------------------------------------------------------------------- Power : Hi = High MH = Medium High ML = Medium Low Lo = Low  Output_Signal_List ~~~~~~~~~~~~~~~~~~ P R Pin r e O Output Pin Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- 48 E 2 COM -------- Hi Slow AMIGA_BUS_DATA_DIR 34 D 6 DFF * -------- Hi Slow AMIGA_BUS_ENABLE 20 C 1 DFF * -------- Hi Slow AMIGA_BUS_ENABLE_LOW 92 A 1 COM -------- Hi Slow AVEC 22 C 1 DFF * -------- Hi Slow AVEC_EXP 83 H 2 DFF * -------- Hi Slow BGACK_030 29 D 2 DFF * -------- Hi Slow BG_000 47 E 1 COM -------- Hi Slow CIIN 65 G 1 DFF * -------- Hi Slow CLK_DIV_OUT 10 B 1 DFF * -------- Hi Slow CLK_EXP 66 G 4 DFF * -------- Hi Slow E 78 H 1 COM -------- Hi Slow FPU_CS 8 B 2 DFF * -------- Hi Slow IPL_030_0_ 7 B 2 DFF * -------- Hi Slow IPL_030_1_ 9 B 2 DFF * -------- Hi Slow IPL_030_2_ 3 B 1 DFF * -------- Hi Slow RESET 35 D 2 DFF * -------- Hi Slow VMA ---------------------------------------------------------------------- Power : Hi = High MH = Medium High ML = Medium Low Lo = Low  Bidir_Signal_List ~~~~~~~~~~~~~~~~~ P R Pin r e O Bidir Pin Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- 69 G 1 DFF * -B----G- Hi Slow A0 33 D 2 DFF * A---E-GH Hi Slow AS_000 82 H 4 DFF * -BCDE--H Hi Slow AS_030 81 H 2 DFF * ---D---- Hi Slow DSACK1 98 A 7 DFF * -B----G- Hi Slow DS_030 30 D 1 COM -----F-- Hi Slow DTACK 31 D 1 COM A-----GH Hi Slow LDS_000 71 G 4 DFF * -B--E--H Hi Slow RW 80 H 3 DFF * A-----G- Hi Slow RW_000 70 G 1 DFF * ------G- Hi Slow SIZE_0_ 79 H 2 DFF * ------G- Hi Slow SIZE_1_ 32 D 1 COM A-----GH Hi Slow UDS_000 ---------------------------------------------------------------------- Power : Hi = High MH = Medium High ML = Medium Low Lo = Low  Buried_Signal_List ~~~~~~~~~~~~~~~~~~ P R Pin r e O Node #Mc Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- E5 E 2 COM --C----- Hi Slow AMIGA_BUS_ENABLE_LOW_0 A5 A 1 DFF * -B------ Hi Slow CLK_000_N_SYNC_0_ E13 E 1 DFF * A------- Hi Slow CLK_000_N_SYNC_10_ A6 A 1 DFF * --C----- Hi Slow CLK_000_N_SYNC_11_ B2 B 1 DFF * -----F-- Hi Slow CLK_000_N_SYNC_1_ F2 F 1 DFF * A------- Hi Slow CLK_000_N_SYNC_2_ A1 A 1 DFF * ------G- Hi Slow CLK_000_N_SYNC_3_ G2 G 1 DFF * --C----- Hi Slow CLK_000_N_SYNC_4_ C5 C 1 DFF * --C----- Hi Slow CLK_000_N_SYNC_5_ C6 C 1 DFF * -------H Hi Slow CLK_000_N_SYNC_6_ H2 H 1 DFF * --C----- Hi Slow CLK_000_N_SYNC_7_ C1 C 1 DFF * -----F-- Hi Slow CLK_000_N_SYNC_8_ F13 F 1 DFF * ----E--- Hi Slow CLK_000_N_SYNC_9_ A2 A 1 DFF * -B------ Hi Slow CLK_000_P_SYNC_0_ B10 B 1 DFF * -B------ Hi Slow CLK_000_P_SYNC_1_ B6 B 1 DFF * A------- Hi Slow CLK_000_P_SYNC_2_ A13 A 1 DFF * ----E--- Hi Slow CLK_000_P_SYNC_3_ E2 E 1 DFF * --C----- Hi Slow CLK_000_P_SYNC_4_ C13 C 1 DFF * --C----- Hi Slow CLK_000_P_SYNC_5_ C9 C 1 DFF * -----F-- Hi Slow CLK_000_P_SYNC_6_ F6 F 1 DFF * A------- Hi Slow CLK_000_P_SYNC_7_ A9 A 1 DFF * ------G- Hi Slow CLK_000_P_SYNC_8_ G6 G 1 DFF * --C----- Hi Slow CLK_000_P_SYNC_9_ E9 E 2 DFF * ----E--- Hi Slow CLK_CNT_N_0_ E6 E 1 DFF * ----E--- Hi Slow CLK_CNT_N_1_ E8 E 2 DFF * --C-E--- Hi Slow CLK_CNT_P_0_ C2 C 1 DFF * ----E--- Hi Slow CLK_CNT_P_1_ D5 D 6 DFF * ---D---- Hi - RN_AMIGA_BUS_ENABLE --> AMIGA_BUS_ENABLE C12 C 1 DFF * --C----- Hi - RN_AMIGA_BUS_ENABLE_LOW --> AMIGA_BUS_ENABLE_LOW D4 D 2 DFF * ---D---- Hi - RN_AS_000 --> AS_000 H8 H 4 DFF * A--D--GH Hi - RN_AS_030 --> AS_030 C0 C 1 DFF * -B-D-FGH Hi - RN_AVEC_EXP --> AVEC_EXP H4 H 2 DFF * A-CDE-GH Hi - RN_BGACK_030 --> BGACK_030 D13 D 2 DFF * ---D---- Hi - RN_BG_000 --> BG_000 H12 H 2 DFF * -------H Hi - RN_DSACK1 --> DSACK1 A0 A 7 DFF * A------- Hi - RN_DS_030 --> DS_030 G4 G 4 DFF * ---D-FG- Hi - RN_E --> E B8 B 2 DFF * -B------ Hi - RN_IPL_030_0_ --> IPL_030_0_ B12 B 2 DFF * -B------ Hi - RN_IPL_030_1_ --> IPL_030_1_ B4 B 2 DFF * -B------ Hi - RN_IPL_030_2_ --> IPL_030_2_ G0 G 4 DFF * ------G- Hi - RN_RW --> RW H0 H 3 DFF * -------H Hi - RN_RW_000 --> RW_000 D1 D 2 DFF * ---D-F-- Hi - RN_VMA --> VMA D6 D 2 DFF * ---D-F-- Hi Slow SM_AMIGA_0_ F8 F 2 DFF * ---D-F-H Hi Slow SM_AMIGA_1_ F9 F 3 DFF * -----F-- Hi Slow SM_AMIGA_2_ F1 F 6 DFF * -----F-- Hi Slow SM_AMIGA_3_ B13 B 2 DFF * -B---F-- Hi Slow SM_AMIGA_4_ F12 F 2 DFF * -B---F-- Hi Slow SM_AMIGA_5_ D9 D 2 DFF * -B-D-F-H Hi Slow SM_AMIGA_6_ F4 F 13 DFF * --CD---H Hi Slow SM_AMIGA_7_ F5 F 4 COM -----F-- Hi Slow SM_AMIGA_7__0 D2 D 2 DFF * ---D--G- Hi Slow cpu_est_0_ G5 G 5 DFF * ---D-FG- Hi Slow cpu_est_1_ G9 G 4 DFF * ---D--G- Hi Slow cpu_est_2_ C4 C 6 DFF * --CD-F-- Hi Slow inst_AS_030_000_SYNC D10 D 1 DFF * ---D---- Hi Slow inst_BGACK_030_INT_D F0 F 1 DFF * A--DEF-- Hi Slow inst_CLK_000_D0 E4 E 1 DFF * A--D-FG- Hi Slow inst_CLK_000_D1 G10 G 1 DFF * A------- Hi Slow inst_CLK_000_D2 A10 A 1 DFF * A------- Hi Slow inst_CLK_000_D3 C8 C 1 DFF * -B-D-F-- Hi Slow inst_CLK_000_NE A12 A 5 DFF A------- Hi Slow inst_CLK_030_H E10 E 1 DFF * -------H Hi Slow inst_CLK_OUT_PRE A8 A 3 DFF * A---E--- Hi Slow inst_CLK_OUT_PRE_25 H13 H 1 DFF * A------H Hi Slow inst_CLK_OUT_PRE_50 H6 H 1 DFF * A------- Hi Slow inst_CLK_OUT_PRE_50_D H9 H 1 DFF * -B----G- Hi Slow inst_CLK_OUT_PRE_D B5 B 3 DFF * -B-D---- Hi Slow inst_DS_000_ENABLE G13 G 2 DFF * ---D--G- Hi Slow inst_LDS_000_INT B9 B 2 DFF * -B-D---- Hi Slow inst_UDS_000_INT C10 C 1 DFF * ---D---- Hi Slow inst_VPA_D E1 E 3 COM ----E--- Hi Slow un16_ciin ---------------------------------------------------------------------- Power : Hi = High MH = Medium High ML = Medium Low Lo = Low  Signals_Fanout_List ~~~~~~~~~~~~~~~~~~~ Signal Source : Fanout List ----------------------------------------------------------------------------- A_31_{ C}: CIIN{ E} un16_ciin{ E} IPL_2_{ H}: IPL_030_2_{ B} FC_1_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ C} A_30_{ C}: CIIN{ E} un16_ciin{ E} UDS_000{ E}: SIZE_1_{ H} AS_030{ H} SIZE_0_{ G} : DS_030{ A} A0{ G} RW{ G} : inst_CLK_030_H{ A} A_29_{ C}: CIIN{ E} un16_ciin{ E} LDS_000{ E}: SIZE_1_{ H} AS_030{ H} SIZE_0_{ G} : DS_030{ A} A0{ G} RW{ G} : inst_CLK_030_H{ A} A_28_{ D}: CIIN{ E} un16_ciin{ E} A_27_{ D}: CIIN{ E} un16_ciin{ E} nEXP_SPACE{. }: DTACK{ D}AMIGA_BUS_DATA_DIR{ E} SIZE_1_{ H} : AS_030{ H} SIZE_0_{ G} DS_030{ A} : A0{ G} BG_000{ D} DSACK1{ H} :AMIGA_BUS_ENABLE{ D}inst_AS_030_000_SYNC{ C} SM_AMIGA_7_{ F} : SM_AMIGA_6_{ D} un16_ciin{ E} A_26_{ D}: CIIN{ E} un16_ciin{ E} BERR{ F}: AS_000{ D} DSACK1{ H}inst_AS_030_000_SYNC{ C} : SM_AMIGA_7_{ F} SM_AMIGA_6_{ D} SM_AMIGA_1_{ F} : SM_AMIGA_0_{ D} SM_AMIGA_4_{ B}inst_DS_000_ENABLE{ B} : SM_AMIGA_5_{ F} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} A_25_{ D}: CIIN{ E} un16_ciin{ E} BG_030{ D}: BG_000{ D} A_24_{ D}: CIIN{ E} un16_ciin{ E} A_23_{ I}: CIIN{ E} un16_ciin{ E} A_22_{ I}: CIIN{ E} un16_ciin{ E} BGACK_000{ E}: FPU_CS{ H} BGACK_030{ H}inst_AS_030_000_SYNC{ C} A_21_{ B}: CIIN{ E} un16_ciin{ E} CLK_030{. }: AS_030{ H} DS_030{ A} RW{ G} : inst_CLK_030_H{ A} A_20_{ B}: CIIN{ E} un16_ciin{ E} CLK_000{. }: BG_000{ D}inst_CLK_000_D0{ F} A_19_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ C} A_18_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ C} A_17_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ C} A_16_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ C} DTACK{ E}: SM_AMIGA_7_{ F} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} IPL_1_{ G}: IPL_030_1_{ B} IPL_0_{ H}: IPL_030_0_{ B} FC_0_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ C} VPA{. }: inst_VPA_D{ C} SM_AMIGA_7_{ F} SM_AMIGA_3_{ F} : SM_AMIGA_2_{ F} RST{. }: CLK_DIV_OUT{ G} SIZE_1_{ H} IPL_030_2_{ B} : AS_030{ H} AS_000{ D} RW_000{ H} : SIZE_0_{ G} DS_030{ A} A0{ G} : BG_000{ D} BGACK_030{ H} CLK_EXP{ B} : IPL_030_1_{ B} DSACK1{ H} IPL_030_0_{ B} : AVEC_EXP{ C} E{ G} VMA{ D} : RESET{ B} RW{ G}AMIGA_BUS_ENABLE{ D} :AMIGA_BUS_ENABLE_LOW{ C}inst_AS_030_000_SYNC{ C}inst_BGACK_030_INT_D{ D} : inst_VPA_D{ C}inst_CLK_OUT_PRE_50_D{ H} CLK_CNT_N_0_{ E} :inst_CLK_OUT_PRE_50{ H}inst_CLK_OUT_PRE_25{ A}inst_CLK_000_D1{ E} :inst_CLK_000_D2{ G}inst_CLK_000_D3{ A}inst_CLK_000_D0{ F} :inst_CLK_000_NE{ C}inst_CLK_OUT_PRE_D{ H}inst_CLK_OUT_PRE{ E} :CLK_000_P_SYNC_9_{ G}CLK_000_N_SYNC_11_{ A} SM_AMIGA_7_{ F} : SM_AMIGA_6_{ D} SM_AMIGA_1_{ F} SM_AMIGA_0_{ D} : SM_AMIGA_4_{ B}CLK_000_N_SYNC_6_{ C} inst_CLK_030_H{ A} : CLK_CNT_P_1_{ C} CLK_CNT_N_1_{ E} CLK_CNT_P_0_{ E} :inst_LDS_000_INT{ G}inst_DS_000_ENABLE{ B}inst_UDS_000_INT{ B} :CLK_000_P_SYNC_0_{ A}CLK_000_P_SYNC_1_{ B}CLK_000_P_SYNC_2_{ B} :CLK_000_P_SYNC_3_{ A}CLK_000_P_SYNC_4_{ E}CLK_000_P_SYNC_5_{ C} :CLK_000_P_SYNC_6_{ C}CLK_000_P_SYNC_7_{ F}CLK_000_P_SYNC_8_{ A} :CLK_000_N_SYNC_0_{ A}CLK_000_N_SYNC_1_{ B}CLK_000_N_SYNC_2_{ F} :CLK_000_N_SYNC_3_{ A}CLK_000_N_SYNC_4_{ G}CLK_000_N_SYNC_5_{ C} :CLK_000_N_SYNC_7_{ H}CLK_000_N_SYNC_8_{ C}CLK_000_N_SYNC_9_{ F} :CLK_000_N_SYNC_10_{ E} SM_AMIGA_5_{ F} SM_AMIGA_3_{ F} : SM_AMIGA_2_{ F} cpu_est_0_{ D} cpu_est_1_{ G} : cpu_est_2_{ G} SIZE_1_{ I}:inst_LDS_000_INT{ G} RN_IPL_030_2_{ C}: IPL_030_2_{ B} AS_030{ I}: FPU_CS{ H} CIIN{ E} AS_000{ D} : BG_000{ D} DSACK1{ H}AMIGA_BUS_ENABLE{ D} :inst_AS_030_000_SYNC{ C}inst_DS_000_ENABLE{ B} un16_ciin{ E} RN_AS_030{ I}: DTACK{ D} SIZE_1_{ H} AS_030{ H} : SIZE_0_{ G} DS_030{ A} A0{ G} : inst_CLK_030_H{ A} AS_000{ E}:AMIGA_BUS_DATA_DIR{ E} SIZE_1_{ H} AS_030{ H} : SIZE_0_{ G} DS_030{ A} A0{ G} : RW{ G} inst_CLK_030_H{ A} RN_AS_000{ E}: AS_000{ D} VMA{ D} RW_000{ I}: DS_030{ A} RW{ G} RN_RW_000{ I}: RW_000{ H} SIZE_0_{ H}:inst_LDS_000_INT{ G} DS_030{ B}:inst_LDS_000_INT{ G}inst_UDS_000_INT{ B} RN_DS_030{ B}: DS_030{ A} A0{ H}:inst_LDS_000_INT{ G}inst_UDS_000_INT{ B} RN_BG_000{ E}: BG_000{ D} RN_BGACK_030{ I}: UDS_000{ D} LDS_000{ D} DTACK{ D} :AMIGA_BUS_DATA_DIR{ E} SIZE_1_{ H} AS_030{ H} : AS_000{ D} RW_000{ H} SIZE_0_{ G} : DS_030{ A} A0{ G} BGACK_030{ H} : RW{ G}AMIGA_BUS_ENABLE{ D}inst_AS_030_000_SYNC{ C} :inst_BGACK_030_INT_D{ D} inst_CLK_030_H{ A} RN_IPL_030_1_{ C}: IPL_030_1_{ B} DSACK1{ I}: DTACK{ D} RN_DSACK1{ I}: DSACK1{ H} RN_IPL_030_0_{ C}: IPL_030_0_{ B} RN_AVEC_EXP{ D}: IPL_030_2_{ B} AS_000{ D} RW_000{ H} : BGACK_030{ H} IPL_030_1_{ B} IPL_030_0_{ B} : E{ G} VMA{ D} SM_AMIGA_7_{ F} : SM_AMIGA_6_{ D} SM_AMIGA_1_{ F} SM_AMIGA_0_{ D} : SM_AMIGA_4_{ B}inst_DS_000_ENABLE{ B} SM_AMIGA_5_{ F} : SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} cpu_est_0_{ D} : cpu_est_1_{ G} cpu_est_2_{ G} SM_AMIGA_7__0{ F} RN_E{ H}: E{ G} VMA{ D} SM_AMIGA_7_{ F} : SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} cpu_est_1_{ G} : cpu_est_2_{ G} RN_VMA{ E}: VMA{ D} SM_AMIGA_7_{ F} SM_AMIGA_3_{ F} : SM_AMIGA_2_{ F} RW{ H}:AMIGA_BUS_DATA_DIR{ E} RW_000{ H}inst_DS_000_ENABLE{ B} RN_RW{ H}: RW{ G} RN_AMIGA_BUS_ENABLE{ E}:AMIGA_BUS_ENABLE{ D} RN_AMIGA_BUS_ENABLE_LOW{ D}:AMIGA_BUS_ENABLE_LOW{ C} inst_AS_030_000_SYNC{ D}:AMIGA_BUS_ENABLE{ D}inst_AS_030_000_SYNC{ C} SM_AMIGA_6_{ D} : SM_AMIGA_7__0{ F} inst_BGACK_030_INT_D{ E}:AMIGA_BUS_ENABLE{ D} inst_VPA_D{ D}: VMA{ D} inst_CLK_OUT_PRE_50_D{ I}:inst_CLK_OUT_PRE_25{ A} CLK_CNT_N_0_{ F}: CLK_CNT_N_0_{ E} CLK_CNT_N_1_{ E}AMIGA_BUS_ENABLE_LOW_0{ E} inst_CLK_OUT_PRE_50{ I}:inst_CLK_OUT_PRE_50_D{ H}inst_CLK_OUT_PRE_50{ H}inst_CLK_OUT_PRE_25{ A} inst_CLK_OUT_PRE_25{ B}:inst_CLK_OUT_PRE_25{ A}inst_CLK_OUT_PRE{ E} inst_CLK_000_D1{ F}:AMIGA_BUS_ENABLE{ D}inst_CLK_000_D2{ G} SM_AMIGA_6_{ D} :CLK_000_P_SYNC_0_{ A}CLK_000_N_SYNC_0_{ A} SM_AMIGA_7__0{ F} inst_CLK_000_D2{ H}:inst_CLK_000_D3{ A}CLK_000_P_SYNC_0_{ A}CLK_000_N_SYNC_0_{ A} inst_CLK_000_D3{ B}:CLK_000_P_SYNC_0_{ A}CLK_000_N_SYNC_0_{ A} inst_CLK_000_D0{ G}:AMIGA_BUS_ENABLE{ D}inst_CLK_000_D1{ E} SM_AMIGA_6_{ D} :CLK_000_P_SYNC_0_{ A}CLK_000_N_SYNC_0_{ A} SM_AMIGA_7__0{ F} inst_CLK_000_NE{ D}: VMA{ D}AMIGA_BUS_ENABLE{ D} SM_AMIGA_7_{ F} : SM_AMIGA_1_{ F} SM_AMIGA_0_{ D} SM_AMIGA_4_{ B} : SM_AMIGA_5_{ F} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} inst_CLK_OUT_PRE_D{ I}: CLK_DIV_OUT{ G} CLK_EXP{ B} inst_CLK_OUT_PRE{ F}:inst_CLK_OUT_PRE_D{ H} CLK_000_P_SYNC_9_{ H}: AVEC_EXP{ C} CLK_000_N_SYNC_11_{ B}:inst_CLK_000_NE{ C} SM_AMIGA_7_{ G}: RW_000{ H}AMIGA_BUS_ENABLE{ D}inst_AS_030_000_SYNC{ C} : SM_AMIGA_6_{ D} SM_AMIGA_6_{ E}: AS_000{ D} RW_000{ H} SM_AMIGA_7_{ F} : SM_AMIGA_6_{ D}inst_DS_000_ENABLE{ B} SM_AMIGA_5_{ F} : SM_AMIGA_7__0{ F} SM_AMIGA_1_{ G}: DSACK1{ H}AMIGA_BUS_ENABLE{ D} SM_AMIGA_7_{ F} : SM_AMIGA_1_{ F} SM_AMIGA_0_{ D} SM_AMIGA_7__0{ F} SM_AMIGA_0_{ E}:AMIGA_BUS_ENABLE{ D} SM_AMIGA_7_{ F} SM_AMIGA_0_{ D} : SM_AMIGA_7__0{ F} SM_AMIGA_4_{ C}: SM_AMIGA_7_{ F} SM_AMIGA_4_{ B}inst_DS_000_ENABLE{ B} : SM_AMIGA_3_{ F} SM_AMIGA_7__0{ F} CLK_000_N_SYNC_6_{ D}: DSACK1{ H}CLK_000_N_SYNC_7_{ H} inst_CLK_030_H{ B}: DS_030{ A} inst_CLK_030_H{ A} CLK_CNT_P_1_{ D}: CLK_CNT_P_0_{ E}AMIGA_BUS_ENABLE_LOW_0{ E} CLK_CNT_N_1_{ F}: CLK_CNT_N_0_{ E}AMIGA_BUS_ENABLE_LOW_0{ E} CLK_CNT_P_0_{ F}: CLK_CNT_P_1_{ C} CLK_CNT_P_0_{ E}AMIGA_BUS_ENABLE_LOW_0{ E} inst_LDS_000_INT{ H}: LDS_000{ D}inst_LDS_000_INT{ G} inst_DS_000_ENABLE{ C}: UDS_000{ D} LDS_000{ D}inst_DS_000_ENABLE{ B} inst_UDS_000_INT{ C}: UDS_000{ D}inst_UDS_000_INT{ B} CLK_000_P_SYNC_0_{ B}:CLK_000_P_SYNC_1_{ B} CLK_000_P_SYNC_1_{ C}:CLK_000_P_SYNC_2_{ B} CLK_000_P_SYNC_2_{ C}:CLK_000_P_SYNC_3_{ A} CLK_000_P_SYNC_3_{ B}:CLK_000_P_SYNC_4_{ E} CLK_000_P_SYNC_4_{ F}:CLK_000_P_SYNC_5_{ C} CLK_000_P_SYNC_5_{ D}:CLK_000_P_SYNC_6_{ C} CLK_000_P_SYNC_6_{ D}:CLK_000_P_SYNC_7_{ F} CLK_000_P_SYNC_7_{ G}:CLK_000_P_SYNC_8_{ A} CLK_000_P_SYNC_8_{ B}:CLK_000_P_SYNC_9_{ G} CLK_000_N_SYNC_0_{ B}:CLK_000_N_SYNC_1_{ B} CLK_000_N_SYNC_1_{ C}:CLK_000_N_SYNC_2_{ F} CLK_000_N_SYNC_2_{ G}:CLK_000_N_SYNC_3_{ A} CLK_000_N_SYNC_3_{ B}:CLK_000_N_SYNC_4_{ G} CLK_000_N_SYNC_4_{ H}:CLK_000_N_SYNC_5_{ C} CLK_000_N_SYNC_5_{ D}:CLK_000_N_SYNC_6_{ C} CLK_000_N_SYNC_7_{ I}:CLK_000_N_SYNC_8_{ C} CLK_000_N_SYNC_8_{ D}:CLK_000_N_SYNC_9_{ F} CLK_000_N_SYNC_9_{ G}:CLK_000_N_SYNC_10_{ E} CLK_000_N_SYNC_10_{ F}:CLK_000_N_SYNC_11_{ A} SM_AMIGA_5_{ G}: SM_AMIGA_7_{ F} SM_AMIGA_4_{ B} SM_AMIGA_5_{ F} : SM_AMIGA_7__0{ F} SM_AMIGA_3_{ G}: SM_AMIGA_7_{ F} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} : SM_AMIGA_7__0{ F} SM_AMIGA_2_{ G}: SM_AMIGA_7_{ F} SM_AMIGA_1_{ F} SM_AMIGA_2_{ F} : SM_AMIGA_7__0{ F} un16_ciin{ F}: CIIN{ E} cpu_est_0_{ E}: E{ G} VMA{ D} cpu_est_0_{ D} : cpu_est_1_{ G} cpu_est_2_{ G} cpu_est_1_{ H}: E{ G} VMA{ D} SM_AMIGA_7_{ F} : SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} cpu_est_1_{ G} : cpu_est_2_{ G} cpu_est_2_{ H}: E{ G} VMA{ D} cpu_est_1_{ G} : cpu_est_2_{ G} AMIGA_BUS_ENABLE_LOW_0{ F}:AMIGA_BUS_ENABLE_LOW{ C} SM_AMIGA_7__0{ G}: SM_AMIGA_7_{ F} ----------------------------------------------------------------------------- {.} : Indicates block location of signal  Set_Reset_Summary ~~~~~~~~~~~~~~~~~ Block A block level set pt : !RST block level reset pt : Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ | * | S | BS | BR | DS_030 | | | | | AVEC | * | S | BR | BS | inst_CLK_OUT_PRE_25 | * | S | BS | BR | RN_DS_030 | * | S | BR | BR | inst_CLK_030_H | * | S | BR | BS | CLK_000_N_SYNC_3_ | * | S | BR | BS | CLK_000_N_SYNC_0_ | * | S | BR | BS | CLK_000_P_SYNC_8_ | * | S | BR | BS | CLK_000_P_SYNC_3_ | * | S | BR | BS | CLK_000_P_SYNC_0_ | * | S | BR | BS | CLK_000_N_SYNC_11_ | * | S | BS | BR | inst_CLK_000_D3 | | | | | A_19_ | | | | | A_16_ | | | | | A_18_ | | | | | A_21_ | | | | | A_20_ Block B block level set pt : !RST block level reset pt : Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ | * | S | BS | BR | IPL_030_2_ | * | S | BS | BR | IPL_030_0_ | * | S | BS | BR | IPL_030_1_ | * | S | BR | BS | CLK_EXP | * | S | BR | BS | RESET | * | S | BR | BS | inst_DS_000_ENABLE | * | S | BS | BR | inst_UDS_000_INT | * | S | BR | BS | SM_AMIGA_4_ | * | S | BS | BR | RN_IPL_030_0_ | * | S | BS | BR | RN_IPL_030_1_ | * | S | BS | BR | RN_IPL_030_2_ | * | S | BR | BS | CLK_000_N_SYNC_1_ | * | S | BR | BS | CLK_000_P_SYNC_2_ | * | S | BR | BS | CLK_000_P_SYNC_1_ | | | | | A_29_ | | | | | A_30_ | | | | | A_31_ Block C block level set pt : block level reset pt : !RST Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ | * | S | BS | BR | AVEC_EXP | * | A | | | AMIGA_BUS_ENABLE_LOW | * | S | BS | BR | RN_AVEC_EXP | * | S | BR | BS | inst_AS_030_000_SYNC | * | S | BS | BR | inst_CLK_000_NE | * | A | | | RN_AMIGA_BUS_ENABLE_LOW | * | S | BS | BR | CLK_000_N_SYNC_8_ | * | S | BS | BR | CLK_000_N_SYNC_5_ | * | S | BS | BR | CLK_000_P_SYNC_6_ | * | S | BS | BR | CLK_000_P_SYNC_5_ | * | S | BS | BR | CLK_CNT_P_1_ | * | S | BS | BR | CLK_000_N_SYNC_6_ | * | S | BR | BS | inst_VPA_D | | | | | BG_030 | | | | | A_24_ | | | | | A_25_ | | | | | A_26_ | | | | | A_27_ | | | | | A_28_ Block D block level set pt : !RST block level reset pt : Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ | * | S | BS | BR | AS_000 | | | | | UDS_000 | | | | | LDS_000 | | | | | DTACK | * | S | BS | BR | AMIGA_BUS_ENABLE | * | S | BS | BR | VMA | * | S | BS | BR | BG_000 | * | S | BR | BS | SM_AMIGA_6_ | * | S | BS | BR | RN_VMA | * | S | BR | BS | cpu_est_0_ | * | S | BR | BS | SM_AMIGA_0_ | * | S | BS | BR | RN_AMIGA_BUS_ENABLE | * | S | BS | BR | RN_BG_000 | * | S | BS | BR | RN_AS_000 | * | S | BS | BR | inst_BGACK_030_INT_D | | | | | BGACK_000 Block E block level set pt : block level reset pt : !RST Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ | | | | | AMIGA_BUS_DATA_DIR | | | | | CIIN | * | S | BR | BS | inst_CLK_000_D1 | * | S | BS | BR | CLK_CNT_P_0_ | | | | | un16_ciin | | | | | AMIGA_BUS_ENABLE_LOW_0 | * | S | BS | BR | CLK_CNT_N_0_ | * | S | BS | BR | CLK_000_N_SYNC_10_ | * | S | BS | BR | CLK_000_P_SYNC_4_ | * | S | BR | BS | CLK_CNT_N_1_ | * | S | BS | BR | inst_CLK_OUT_PRE | | | | | BERR Block F block level set pt : !RST block level reset pt : Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ | * | S | BS | BR | inst_CLK_000_D0 | * | S | BS | BR | SM_AMIGA_7_ | * | S | BR | BS | SM_AMIGA_1_ | * | S | BR | BS | SM_AMIGA_5_ | * | S | BR | BS | SM_AMIGA_3_ | | | | | SM_AMIGA_7__0 | * | S | BR | BS | SM_AMIGA_2_ | * | S | BR | BS | CLK_000_N_SYNC_9_ | * | S | BR | BS | CLK_000_N_SYNC_2_ | * | S | BR | BS | CLK_000_P_SYNC_7_ | | | | | A_17_ | | | | | FC_1_ | | | | | FC_0_ | | | | | IPL_1_ Block G block level set pt : !RST block level reset pt : Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ | * | S | BS | BR | RW | * | S | BS | BR | A0 | * | S | BS | BR | SIZE_0_ | * | S | BR | BS | E | * | S | BR | BS | CLK_DIV_OUT | * | S | BR | BS | cpu_est_1_ | * | S | BR | BS | RN_E | * | S | BR | BS | cpu_est_2_ | * | S | BS | BR | inst_LDS_000_INT | * | S | BS | BR | RN_RW | * | S | BR | BS | CLK_000_N_SYNC_4_ | * | S | BR | BS | CLK_000_P_SYNC_9_ | * | S | BS | BR | inst_CLK_000_D2 | | | | | IPL_2_ | | | | | IPL_0_ Block H block level set pt : !RST block level reset pt : Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ | * | S | BS | BR | AS_030 | * | S | BS | BR | RW_000 | * | S | BS | BR | DSACK1 | * | S | BS | BR | SIZE_1_ | * | S | BS | BR | BGACK_030 | | | | | FPU_CS | * | S | BS | BR | RN_BGACK_030 | * | S | BS | BR | RN_AS_030 | * | S | BR | BS | inst_CLK_OUT_PRE_D | * | S | BR | BS | inst_CLK_OUT_PRE_50 | * | S | BS | BR | RN_RW_000 | * | S | BS | BR | RN_DSACK1 | * | S | BR | BS | CLK_000_N_SYNC_7_ | * | S | BR | BS | inst_CLK_OUT_PRE_50_D | | | | | A_22_ | | | | | A_23_ (S) means the macrocell is configured in synchronous mode i.e. it uses the block-level set and reset pt. (A) means the macrocell is configured in asynchronous mode i.e. it can have its independant set or reset pt. (BS) means the block-level set pt is selected. (BR) means the block-level reset pt is selected.  BLOCK_A_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ mx A0 RST pin 86 mx A17 ... ... mx A1CLK_000_P_SYNC_7_ mcell F6 mx A18inst_CLK_OUT_PRE_25 mcell A8 mx A2CLK_000_P_SYNC_2_ mcell B6 mx A19inst_CLK_OUT_PRE_50 mcell H13 mx A3 RN_AS_030 mcell H8 mx A20 RN_BGACK_030 mcell H4 mx A4 CLK_030 pin 64 mx A21 RW_000 pin 80 mx A5 nEXP_SPACE pin 14 mx A22 inst_CLK_000_D2 mcell G10 mx A6 inst_CLK_000_D1 mcell E4 mx A23 AS_000 pin 33 mx A7inst_CLK_OUT_PRE_50_D mcell H6 mx A24 LDS_000 pin 31 mx A8 inst_CLK_000_D3 mcell A10 mx A25 inst_CLK_000_D0 mcell F0 mx A9CLK_000_N_SYNC_2_ mcell F2 mx A26 ... ... mx A10 ... ... mx A27 ... ... mx A11 ... ... mx A28 ... ... mx A12 UDS_000 pin 32 mx A29 RN_DS_030 mcell A0 mx A13CLK_000_N_SYNC_10_ mcell E13 mx A30 ... ... mx A14 ... ... mx A31 ... ... mx A15 inst_CLK_030_H mcell A12 mx A32 ... ... mx A16 ... ... ---------------------------------------------------------------------------- BLOCK_B_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ mx B0 IPL_0_ pin 67 mx B17 RN_IPL_030_0_ mcell B8 mx B1 SM_AMIGA_5_ mcell F12 mx B18CLK_000_N_SYNC_0_ mcell A5 mx B2CLK_000_P_SYNC_1_ mcell B10 mx B19 AS_030 pin 82 mx B3 IPL_1_ pin 56 mx B20 ... ... mx B4 IPL_2_ pin 68 mx B21 RST pin 86 mx B5 DS_030 pin 98 mx B22CLK_000_P_SYNC_0_ mcell A2 mx B6inst_UDS_000_INT mcell B9 mx B23 ... ... mx B7 SM_AMIGA_6_ mcell D9 mx B24 ... ... mx B8 RW pin 71 mx B25 BERR pin 41 mx B9 RN_AVEC_EXP mcell C0 mx B26 ... ... mx B10 SM_AMIGA_4_ mcell B13 mx B27 RN_IPL_030_2_ mcell B4 mx B11inst_CLK_OUT_PRE_D mcell H9 mx B28inst_DS_000_ENABLE mcell B5 mx B12 RN_IPL_030_1_ mcell B12 mx B29 ... ... mx B13 ... ... mx B30 ... ... mx B14 ... ... mx B31 ... ... mx B15 A0 pin 69 mx B32 ... ... mx B16 inst_CLK_000_NE mcell C8 ---------------------------------------------------------------------------- BLOCK_C_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ mx C0 RST pin 86 mx C17 A_18_ pin 95 mx C1 FC_1_ pin 58 mx C18 BGACK_000 pin 28 mx C2 ... ... mx C19 ... ... mx C3CLK_000_P_SYNC_4_ mcell E2 mx C20 RN_BGACK_030 mcell H4 mx C4RN_AMIGA_BUS_ENABLE_LOW mcell C12 mx C21 ... ... mx C5 nEXP_SPACE pin 14 mx C22 ... ... mx C6 FC_0_ pin 57 mx C23CLK_000_P_SYNC_9_ mcell G6 mx C7CLK_000_N_SYNC_5_ mcell C5 mx C24 ... ... mx C8 A_17_ pin 59 mx C25 BERR pin 41 mx C9 AS_030 pin 82 mx C26AMIGA_BUS_ENABLE_LOW_0 mcell E5 mx C10 SM_AMIGA_7_ mcell F4 mx C27 ... ... mx C11 A_16_ pin 96 mx C28 ... ... mx C12 A_19_ pin 97 mx C29inst_AS_030_000_SYNC mcell C4 mx C13 VPA pin 36 mx C30CLK_000_P_SYNC_5_ mcell C13 mx C14CLK_000_N_SYNC_7_ mcell H2 mx C31CLK_000_N_SYNC_4_ mcell G2 mx C15CLK_000_N_SYNC_11_ mcell A6 mx C32 ... ... mx C16 CLK_CNT_P_0_ mcell E8 ---------------------------------------------------------------------------- BLOCK_D_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ mx D0 RST pin 86 mx D17 DSACK1 pin 81 mx D1 BERR pin 41 mx D18 ... ... mx D2 RN_E mcell G4 mx D19 AS_030 pin 82 mx D3 cpu_est_1_ mcell G5 mx D20inst_BGACK_030_INT_D mcell D10 mx D4 BG_030 pin 21 mx D21 RN_BG_000 mcell D13 mx D5 inst_CLK_000_D0 mcell F0 mx D22 inst_CLK_000_D1 mcell E4 mx D6inst_AS_030_000_SYNC mcell C4 mx D23 RN_BGACK_030 mcell H4 mx D7 inst_CLK_000_NE mcell C8 mx D24 CLK_000 pin 11 mx D8 inst_VPA_D mcell C10 mx D25 SM_AMIGA_6_ mcell D9 mx D9 RN_AVEC_EXP mcell C0 mx D26 ... ... mx D10 cpu_est_2_ mcell G9 mx D27 RN_VMA mcell D1 mx D11RN_AMIGA_BUS_ENABLE mcell D5 mx D28 cpu_est_0_ mcell D2 mx D12inst_LDS_000_INT mcell G13 mx D29 SM_AMIGA_7_ mcell F4 mx D13 RN_AS_030 mcell H8 mx D30 SM_AMIGA_0_ mcell D6 mx D14 RN_AS_000 mcell D4 mx D31inst_DS_000_ENABLE mcell B5 mx D15 nEXP_SPACE pin 14 mx D32 SM_AMIGA_1_ mcell F8 mx D16inst_UDS_000_INT mcell B9 ---------------------------------------------------------------------------- BLOCK_E_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ mx E0 CLK_CNT_N_1_ mcell E6 mx E17 A_26_ pin 17 mx E1 A_31_ pin 4 mx E18 A_22_ pin 85 mx E2 CLK_CNT_N_0_ mcell E9 mx E19 A_30_ pin 5 mx E3inst_CLK_OUT_PRE_25 mcell A8 mx E20 RN_BGACK_030 mcell H4 mx E4 A_29_ pin 6 mx E21 RST pin 86 mx E5 nEXP_SPACE pin 14 mx E22 CLK_CNT_P_1_ mcell C2 mx E6CLK_000_N_SYNC_9_ mcell F13 mx E23 AS_000 pin 33 mx E7 A_28_ pin 15 mx E24 ... ... mx E8 RW pin 71 mx E25CLK_000_P_SYNC_3_ mcell A13 mx E9 A_23_ pin 84 mx E26 ... ... mx E10 ... ... mx E27 ... ... mx E11 A_27_ pin 16 mx E28 ... ... mx E12 A_25_ pin 18 mx E29 A_20_ pin 93 mx E13 un16_ciin mcell E1 mx E30 ... ... mx E14 A_24_ pin 19 mx E31 inst_CLK_000_D0 mcell F0 mx E15 A_21_ pin 94 mx E32 AS_030 pin 82 mx E16 CLK_CNT_P_0_ mcell E8 ---------------------------------------------------------------------------- BLOCK_F_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ mx F0 RST pin 86 mx F17 SM_AMIGA_5_ mcell F12 mx F1 BERR pin 41 mx F18CLK_000_N_SYNC_1_ mcell B2 mx F2 RN_VMA mcell D1 mx F19 ... ... mx F3 cpu_est_1_ mcell G5 mx F20 SM_AMIGA_1_ mcell F8 mx F4 SM_AMIGA_0_ mcell D6 mx F21 SM_AMIGA_4_ mcell B13 mx F5 nEXP_SPACE pin 14 mx F22CLK_000_N_SYNC_8_ mcell C1 mx F6inst_AS_030_000_SYNC mcell C4 mx F23 ... ... mx F7 inst_CLK_000_NE mcell C8 mx F24 ... ... mx F8 ... ... mx F25 inst_CLK_000_D0 mcell F0 mx F9 DTACK pin 30 mx F26 ... ... mx F10 VPA pin 36 mx F27 SM_AMIGA_7__0 mcell F5 mx F11 RN_E mcell G4 mx F28 ... ... mx F12 SM_AMIGA_6_ mcell D9 mx F29 inst_CLK_000_D1 mcell E4 mx F13CLK_000_P_SYNC_6_ mcell C9 mx F30 ... ... mx F14 CLK_000 pin 11 mx F31 ... ... mx F15 SM_AMIGA_3_ mcell F1 mx F32 SM_AMIGA_2_ mcell F9 mx F16 RN_AVEC_EXP mcell C0 ---------------------------------------------------------------------------- BLOCK_G_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ mx G0 RST pin 86 mx G17 RN_RW mcell G0 mx G1 ... ... mx G18 DS_030 pin 98 mx G2CLK_000_P_SYNC_8_ mcell A9 mx G19 ... ... mx G3 cpu_est_0_ mcell D2 mx G20 RN_BGACK_030 mcell H4 mx G4 CLK_030 pin 64 mx G21 RN_E mcell G4 mx G5 nEXP_SPACE pin 14 mx G22 cpu_est_1_ mcell G5 mx G6 inst_CLK_000_D1 mcell E4 mx G23 AS_000 pin 33 mx G7 ... ... mx G24 LDS_000 pin 31 mx G8 UDS_000 pin 32 mx G25 ... ... mx G9CLK_000_N_SYNC_3_ mcell A1 mx G26 ... ... mx G10 cpu_est_2_ mcell G9 mx G27 SIZE_1_ pin 79 mx G11inst_CLK_OUT_PRE_D mcell H9 mx G28 RW_000 pin 80 mx G12inst_LDS_000_INT mcell G13 mx G29 ... ... mx G13 RN_AS_030 mcell H8 mx G30 ... ... mx G14 SIZE_0_ pin 70 mx G31 ... ... mx G15 A0 pin 69 mx G32 ... ... mx G16 RN_AVEC_EXP mcell C0 ---------------------------------------------------------------------------- BLOCK_H_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ mx H0 RN_BGACK_030 mcell H4 mx H17 FC_0_ pin 57 mx H1 BERR pin 41 mx H18 BGACK_000 pin 28 mx H2 SM_AMIGA_1_ mcell F8 mx H19 AS_030 pin 82 mx H3inst_CLK_OUT_PRE mcell E10 mx H20 FC_1_ pin 58 mx H4 A_18_ pin 95 mx H21 RST pin 86 mx H5 nEXP_SPACE pin 14 mx H22 ... ... mx H6 A_19_ pin 97 mx H23 RN_RW_000 mcell H0 mx H7inst_CLK_OUT_PRE_50 mcell H13 mx H24 LDS_000 pin 31 mx H8 RW pin 71 mx H25 SM_AMIGA_6_ mcell D9 mx H9CLK_000_N_SYNC_6_ mcell C6 mx H26 AS_000 pin 33 mx H10 SM_AMIGA_7_ mcell F4 mx H27 A_17_ pin 59 mx H11 A_16_ pin 96 mx H28 CLK_030 pin 64 mx H12 UDS_000 pin 32 mx H29 ... ... mx H13 RN_AS_030 mcell H8 mx H30 ... ... mx H14 ... ... mx H31 ... ... mx H15 RN_DSACK1 mcell H12 mx H32 ... ... mx H16 RN_AVEC_EXP mcell C0 ---------------------------------------------------------------------------- CSM indicates the mux inputs from the Central Switch Matrix. Source indicates where the signal comes from (pin or macrocell).  PostFit_Equations ~~~~~~~~~~~~~~~~~ P-Terms Fan-in Fan-out Type Name (attributes) --------- ------ ------- ---- ----------------- 1 2 1 Pin UDS_000- 1 1 1 Pin UDS_000.OE 1 2 1 Pin LDS_000- 1 1 1 Pin LDS_000.OE 1 1 1 Pin CLK_DIV_OUT.AR 1 1 1 Pin CLK_DIV_OUT.D 1 1 1 Pin CLK_DIV_OUT.C 1 8 1 Pin FPU_CS- 1 1 1 Pin DTACK 1 3 1 Pin DTACK.OE 1 0 1 Pin AVEC 2 4 1 Pin AMIGA_BUS_DATA_DIR 1 13 1 Pin CIIN 1 1 1 Pin CIIN.OE 1 3 1 Pin SIZE_1_.OE 2 4 1 Pin SIZE_1_.D- 1 1 1 Pin SIZE_1_.AP 1 1 1 Pin SIZE_1_.C 2 3 1 Pin IPL_030_2_.D 1 1 1 Pin IPL_030_2_.AP 1 1 1 Pin IPL_030_2_.C 1 3 1 Pin AS_030.OE 4 6 1 Pin AS_030.D 1 1 1 Pin AS_030.AP 1 1 1 Pin AS_030.C 1 1 1 Pin AS_000.OE 2 5 1 Pin AS_000.D- 1 1 1 Pin AS_000.AP 1 1 1 Pin AS_000.C 1 1 1 Pin RW_000.OE 3 5 1 Pin RW_000.D- 1 1 1 Pin RW_000.AP 1 1 1 Pin RW_000.C 1 3 1 Pin SIZE_0_.OE 1 4 1 Pin SIZE_0_.D- 1 1 1 Pin SIZE_0_.AP 1 1 1 Pin SIZE_0_.C 1 3 1 Pin DS_030.OE 7 9 1 Pin DS_030.D 1 1 1 Pin DS_030.AP 1 1 1 Pin DS_030.C 1 3 1 Pin A0.OE 1 4 1 Pin A0.D 1 1 1 Pin A0.AP 1 1 1 Pin A0.C 2 5 1 Pin BG_000.D- 1 1 1 Pin BG_000.AP 1 1 1 Pin BG_000.C 2 3 1 Pin BGACK_030.D 1 1 1 Pin BGACK_030.AP 1 1 1 Pin BGACK_030.C 1 1 1 Pin CLK_EXP.AR 1 1 1 Pin CLK_EXP.D 1 1 1 Pin CLK_EXP.C 2 3 1 Pin IPL_030_1_.D 1 1 1 Pin IPL_030_1_.AP 1 1 1 Pin IPL_030_1_.C 1 1 1 Pin DSACK1.OE 2 5 1 Pin DSACK1.D- 1 1 1 Pin DSACK1.AP 1 1 1 Pin DSACK1.C 2 3 1 Pin IPL_030_0_.D 1 1 1 Pin IPL_030_0_.AP 1 1 1 Pin IPL_030_0_.C 1 1 1 Pin AVEC_EXP.AR 1 1 1 Pin AVEC_EXP.D 1 1 1 Pin AVEC_EXP.C 1 1 1 Pin E.AR 4 5 1 Pin E.D- 1 1 1 Pin E.C 2 7 1 PinX1 VMA.D.X1 1 5 1 PinX2 VMA.D.X2 1 1 1 Pin VMA.AP 1 1 1 Pin VMA.C 1 1 1 Pin RESET.AR 1 0 1 Pin RESET.D 1 1 1 Pin RESET.C 1 1 1 Pin RW.OE 4 7 1 Pin RW.D- 1 1 1 Pin RW.AP 1 1 1 Pin RW.C 6 12 1 Pin AMIGA_BUS_ENABLE.D- 1 1 1 Pin AMIGA_BUS_ENABLE.AP 1 1 1 Pin AMIGA_BUS_ENABLE.C 1 1 1 Pin AMIGA_BUS_ENABLE_LOW.AR 1 1 1 Pin AMIGA_BUS_ENABLE_LOW.D 1 1 1 Pin AMIGA_BUS_ENABLE_LOW.C 6 13 1 Node inst_AS_030_000_SYNC.D 1 1 1 Node inst_AS_030_000_SYNC.AP 1 1 1 Node inst_AS_030_000_SYNC.C 1 1 1 Node inst_BGACK_030_INT_D.D 1 1 1 Node inst_BGACK_030_INT_D.AP 1 1 1 Node inst_BGACK_030_INT_D.C 1 1 1 Node inst_VPA_D.D 1 1 1 Node inst_VPA_D.AP 1 1 1 Node inst_VPA_D.C 1 1 1 Node inst_CLK_OUT_PRE_50_D.AR 1 1 1 Node inst_CLK_OUT_PRE_50_D.D 1 1 1 Node inst_CLK_OUT_PRE_50_D.C 1 1 1 Node CLK_CNT_N_0_.AR 2 2 1 Node CLK_CNT_N_0_.D 1 1 1 Node CLK_CNT_N_0_.C 1 1 1 Node inst_CLK_OUT_PRE_50.AR 1 1 1 Node inst_CLK_OUT_PRE_50.D 1 1 1 Node inst_CLK_OUT_PRE_50.C 1 1 1 Node inst_CLK_OUT_PRE_25.AR 3 3 1 Node inst_CLK_OUT_PRE_25.D 1 1 1 Node inst_CLK_OUT_PRE_25.C 1 1 1 Node inst_CLK_000_D1.D 1 1 1 Node inst_CLK_000_D1.AP 1 1 1 Node inst_CLK_000_D1.C 1 1 1 Node inst_CLK_000_D2.D 1 1 1 Node inst_CLK_000_D2.AP 1 1 1 Node inst_CLK_000_D2.C 1 1 1 Node inst_CLK_000_D3.D 1 1 1 Node inst_CLK_000_D3.AP 1 1 1 Node inst_CLK_000_D3.C 1 1 1 Node inst_CLK_000_D0.D 1 1 1 Node inst_CLK_000_D0.AP 1 1 1 Node inst_CLK_000_D0.C 1 1 1 Node inst_CLK_000_NE.AR 1 1 1 Node inst_CLK_000_NE.D 1 1 1 Node inst_CLK_000_NE.C 1 1 1 Node inst_CLK_OUT_PRE_D.AR 1 1 1 Node inst_CLK_OUT_PRE_D.D 1 1 1 Node inst_CLK_OUT_PRE_D.C 1 1 1 Node inst_CLK_OUT_PRE.AR 1 1 1 Node inst_CLK_OUT_PRE.D 1 1 1 Node inst_CLK_OUT_PRE.C 1 1 1 Node CLK_000_P_SYNC_9_.AR 1 1 1 Node CLK_000_P_SYNC_9_.D 1 1 1 Node CLK_000_P_SYNC_9_.C 1 1 1 Node CLK_000_N_SYNC_11_.AR 1 1 1 Node CLK_000_N_SYNC_11_.D 1 1 1 Node CLK_000_N_SYNC_11_.C 13 17 1 Node SM_AMIGA_7_.D 1 1 1 Node SM_AMIGA_7_.AP 1 1 1 Node SM_AMIGA_7_.C 1 1 1 Node SM_AMIGA_6_.AR 2 8 1 Node SM_AMIGA_6_.D 1 1 1 Node SM_AMIGA_6_.C 1 1 1 Node SM_AMIGA_1_.AR 2 5 1 Node SM_AMIGA_1_.D 1 1 1 Node SM_AMIGA_1_.C 1 1 1 Node SM_AMIGA_0_.AR 2 5 1 Node SM_AMIGA_0_.D 1 1 1 Node SM_AMIGA_0_.C 1 1 1 Node SM_AMIGA_4_.AR 2 5 1 Node SM_AMIGA_4_.D 1 1 1 Node SM_AMIGA_4_.C 1 1 1 Node CLK_000_N_SYNC_6_.AR 1 1 1 Node CLK_000_N_SYNC_6_.D 1 1 1 Node CLK_000_N_SYNC_6_.C 5 8 1 Node inst_CLK_030_H.D 1 1 1 Node inst_CLK_030_H.C 1 1 1 Node CLK_CNT_P_1_.AR 1 1 1 Node CLK_CNT_P_1_.D 1 1 1 Node CLK_CNT_P_1_.C 1 1 1 Node CLK_CNT_N_1_.D 1 1 1 Node CLK_CNT_N_1_.AP 1 1 1 Node CLK_CNT_N_1_.C 1 1 1 Node CLK_CNT_P_0_.AR 2 2 1 Node CLK_CNT_P_0_.D 1 1 1 Node CLK_CNT_P_0_.C 2 5 1 Node inst_LDS_000_INT.D 1 1 1 Node inst_LDS_000_INT.AP 1 1 1 Node inst_LDS_000_INT.C 1 1 1 Node inst_DS_000_ENABLE.AR 3 7 1 Node inst_DS_000_ENABLE.D 1 1 1 Node inst_DS_000_ENABLE.C 2 3 1 Node inst_UDS_000_INT.D 1 1 1 Node inst_UDS_000_INT.AP 1 1 1 Node inst_UDS_000_INT.C 1 1 1 Node CLK_000_P_SYNC_0_.AR 1 4 1 Node CLK_000_P_SYNC_0_.D 1 1 1 Node CLK_000_P_SYNC_0_.C 1 1 1 Node CLK_000_P_SYNC_1_.AR 1 1 1 Node CLK_000_P_SYNC_1_.D 1 1 1 Node CLK_000_P_SYNC_1_.C 1 1 1 Node CLK_000_P_SYNC_2_.AR 1 1 1 Node CLK_000_P_SYNC_2_.D 1 1 1 Node CLK_000_P_SYNC_2_.C 1 1 1 Node CLK_000_P_SYNC_3_.AR 1 1 1 Node CLK_000_P_SYNC_3_.D 1 1 1 Node CLK_000_P_SYNC_3_.C 1 1 1 Node CLK_000_P_SYNC_4_.AR 1 1 1 Node CLK_000_P_SYNC_4_.D 1 1 1 Node CLK_000_P_SYNC_4_.C 1 1 1 Node CLK_000_P_SYNC_5_.AR 1 1 1 Node CLK_000_P_SYNC_5_.D 1 1 1 Node CLK_000_P_SYNC_5_.C 1 1 1 Node CLK_000_P_SYNC_6_.AR 1 1 1 Node CLK_000_P_SYNC_6_.D 1 1 1 Node CLK_000_P_SYNC_6_.C 1 1 1 Node CLK_000_P_SYNC_7_.AR 1 1 1 Node CLK_000_P_SYNC_7_.D 1 1 1 Node CLK_000_P_SYNC_7_.C 1 1 1 Node CLK_000_P_SYNC_8_.AR 1 1 1 Node CLK_000_P_SYNC_8_.D 1 1 1 Node CLK_000_P_SYNC_8_.C 1 1 1 Node CLK_000_N_SYNC_0_.AR 1 4 1 Node CLK_000_N_SYNC_0_.D 1 1 1 Node CLK_000_N_SYNC_0_.C 1 1 1 Node CLK_000_N_SYNC_1_.AR 1 1 1 Node CLK_000_N_SYNC_1_.D 1 1 1 Node CLK_000_N_SYNC_1_.C 1 1 1 Node CLK_000_N_SYNC_2_.AR 1 1 1 Node CLK_000_N_SYNC_2_.D 1 1 1 Node CLK_000_N_SYNC_2_.C 1 1 1 Node CLK_000_N_SYNC_3_.AR 1 1 1 Node CLK_000_N_SYNC_3_.D 1 1 1 Node CLK_000_N_SYNC_3_.C 1 1 1 Node CLK_000_N_SYNC_4_.AR 1 1 1 Node CLK_000_N_SYNC_4_.D 1 1 1 Node CLK_000_N_SYNC_4_.C 1 1 1 Node CLK_000_N_SYNC_5_.AR 1 1 1 Node CLK_000_N_SYNC_5_.D 1 1 1 Node CLK_000_N_SYNC_5_.C 1 1 1 Node CLK_000_N_SYNC_7_.AR 1 1 1 Node CLK_000_N_SYNC_7_.D 1 1 1 Node CLK_000_N_SYNC_7_.C 1 1 1 Node CLK_000_N_SYNC_8_.AR 1 1 1 Node CLK_000_N_SYNC_8_.D 1 1 1 Node CLK_000_N_SYNC_8_.C 1 1 1 Node CLK_000_N_SYNC_9_.AR 1 1 1 Node CLK_000_N_SYNC_9_.D 1 1 1 Node CLK_000_N_SYNC_9_.C 1 1 1 Node CLK_000_N_SYNC_10_.AR 1 1 1 Node CLK_000_N_SYNC_10_.D 1 1 1 Node CLK_000_N_SYNC_10_.C 1 1 1 Node SM_AMIGA_5_.AR 2 5 1 Node SM_AMIGA_5_.D 1 1 1 Node SM_AMIGA_5_.C 1 1 1 Node SM_AMIGA_3_.AR 6 10 1 Node SM_AMIGA_3_.D 1 1 1 Node SM_AMIGA_3_.C 1 1 1 Node SM_AMIGA_2_.AR 3 10 1 Node SM_AMIGA_2_.D 1 1 1 Node SM_AMIGA_2_.C 3 14 1 Node un16_ciin- 1 1 1 Node cpu_est_0_.AR 2 2 1 Node cpu_est_0_.D 1 1 1 Node cpu_est_0_.C 1 1 1 Node cpu_est_1_.AR 5 5 1 Node cpu_est_1_.D 1 1 1 Node cpu_est_1_.C 1 1 1 Node cpu_est_2_.AR 4 5 1 Node cpu_est_2_.D 1 1 1 Node cpu_est_2_.C 2 4 1 Node AMIGA_BUS_ENABLE_LOW_0 4 11 1 Node SM_AMIGA_7__0 ========= 338 P-Term Total: 338 Total Pins: 59 Total Nodes: 57 Average P-Term/Output: 2 Equations: !UDS_000 = (inst_DS_000_ENABLE.Q & !inst_UDS_000_INT.Q); UDS_000.OE = (BGACK_030.Q); !LDS_000 = (!inst_LDS_000_INT.Q & inst_DS_000_ENABLE.Q); LDS_000.OE = (BGACK_030.Q); CLK_DIV_OUT.AR = (!RST); CLK_DIV_OUT.D = (inst_CLK_OUT_PRE_D.Q); CLK_DIV_OUT.C = (CLK_OSZI); !FPU_CS = (FC_1_ & BGACK_000 & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN); DTACK = (DSACK1.PIN); DTACK.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q); AVEC = (1); AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW.PIN # !nEXP_SPACE & !BGACK_030.Q & !AS_000.PIN & RW.PIN); CIIN = (!A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_ & A_23_ & A_22_ & A_21_ & A_20_ & !AS_030.PIN); CIIN.OE = (!un16_ciin); SIZE_1_.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q); !SIZE_1_.D = (!BGACK_030.Q & !AS_000.PIN & !UDS_000.PIN & LDS_000.PIN # !BGACK_030.Q & !AS_000.PIN & UDS_000.PIN & !LDS_000.PIN); SIZE_1_.AP = (!RST); SIZE_1_.C = (CLK_OSZI); IPL_030_2_.D = (IPL_2_ & AVEC_EXP.Q # !AVEC_EXP.Q & IPL_030_2_.Q); IPL_030_2_.AP = (!RST); IPL_030_2_.C = (CLK_OSZI); AS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q); AS_030.D = (BGACK_030.Q # AS_000.PIN # !CLK_030 & AS_030.Q # UDS_000.PIN & LDS_000.PIN); AS_030.AP = (!RST); AS_030.C = (CLK_OSZI); AS_000.OE = (BGACK_030.Q); !AS_000.D = (AVEC_EXP.Q & SM_AMIGA_6_.Q # BERR & !AS_000.Q & !AS_030.PIN); AS_000.AP = (!RST); AS_000.C = (CLK_OSZI); RW_000.OE = (BGACK_030.Q); !RW_000.D = (!AVEC_EXP.Q & !SM_AMIGA_7_.Q & !RW_000.Q # !SM_AMIGA_7_.Q & !SM_AMIGA_6_.Q & !RW_000.Q # AVEC_EXP.Q & !SM_AMIGA_7_.Q & SM_AMIGA_6_.Q & !RW.PIN); RW_000.AP = (!RST); RW_000.C = (CLK_OSZI); SIZE_0_.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q); !SIZE_0_.D = (!BGACK_030.Q & !AS_000.PIN & !UDS_000.PIN & !LDS_000.PIN); SIZE_0_.AP = (!RST); SIZE_0_.C = (CLK_OSZI); DS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q); DS_030.D = (BGACK_030.Q # AS_000.PIN # AS_030.Q & RW_000.PIN # UDS_000.PIN & LDS_000.PIN # CLK_030 & AS_030.Q & inst_CLK_030_H.Q # !CLK_030 & DS_030.Q & !RW_000.PIN # !inst_CLK_030_H.Q & DS_030.Q & !RW_000.PIN); DS_030.AP = (!RST); DS_030.C = (CLK_OSZI); A0.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q); A0.D = (!BGACK_030.Q & !AS_000.PIN & UDS_000.PIN & !LDS_000.PIN); A0.AP = (!RST); A0.C = (CLK_OSZI); !BG_000.D = (!BG_030 & !BG_000.Q # nEXP_SPACE & !BG_030 & CLK_000 & AS_030.PIN); BG_000.AP = (!RST); BG_000.C = (CLK_OSZI); BGACK_030.D = (BGACK_000 & BGACK_030.Q # BGACK_000 & AVEC_EXP.Q); BGACK_030.AP = (!RST); BGACK_030.C = (CLK_OSZI); CLK_EXP.AR = (!RST); CLK_EXP.D = (inst_CLK_OUT_PRE_D.Q); CLK_EXP.C = (CLK_OSZI); IPL_030_1_.D = (IPL_1_ & AVEC_EXP.Q # !AVEC_EXP.Q & IPL_030_1_.Q); IPL_030_1_.AP = (!RST); IPL_030_1_.C = (CLK_OSZI); DSACK1.OE = (nEXP_SPACE); !DSACK1.D = (SM_AMIGA_1_.Q & CLK_000_N_SYNC_6_.Q # BERR & !DSACK1.Q & !AS_030.PIN); DSACK1.AP = (!RST); DSACK1.C = (CLK_OSZI); IPL_030_0_.D = (IPL_0_ & AVEC_EXP.Q # !AVEC_EXP.Q & IPL_030_0_.Q); IPL_030_0_.AP = (!RST); IPL_030_0_.C = (CLK_OSZI); AVEC_EXP.AR = (!RST); AVEC_EXP.D = (CLK_000_P_SYNC_9_.Q); AVEC_EXP.C = (CLK_OSZI); E.AR = (!RST); !E.D = (!AVEC_EXP.Q & !E.Q # cpu_est_2_.Q & !E.Q # AVEC_EXP.Q & cpu_est_1_.Q & cpu_est_2_.Q # !cpu_est_0_.Q & cpu_est_1_.Q & !E.Q); E.C = (CLK_OSZI); VMA.D.X1 = (VMA.Q # AVEC_EXP.Q & !VMA.Q & AS_000.Q & !cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & !E.Q); VMA.D.X2 = (VMA.Q & !inst_VPA_D.Q & inst_CLK_000_NE.Q & cpu_est_0_.Q & !cpu_est_1_.Q); VMA.AP = (!RST); VMA.C = (CLK_OSZI); RESET.AR = (!RST); RESET.D = (1); RESET.C = (CLK_OSZI); RW.OE = (!BGACK_030.Q); !RW.D = (!CLK_030 & !BGACK_030.Q & !RW.Q & !AS_000.PIN & !UDS_000.PIN # CLK_030 & !BGACK_030.Q & !AS_000.PIN & !RW_000.PIN & !UDS_000.PIN # !CLK_030 & !BGACK_030.Q & !RW.Q & !AS_000.PIN & !LDS_000.PIN # CLK_030 & !BGACK_030.Q & !AS_000.PIN & !RW_000.PIN & !LDS_000.PIN); RW.AP = (!RST); RW.C = (CLK_OSZI); !AMIGA_BUS_ENABLE.D = (!BGACK_030.Q # !AMIGA_BUS_ENABLE.Q & inst_BGACK_030_INT_D.Q & SM_AMIGA_1_.Q & !AS_030.PIN # !AMIGA_BUS_ENABLE.Q & inst_BGACK_030_INT_D.Q & SM_AMIGA_0_.Q & !AS_030.PIN # !AMIGA_BUS_ENABLE.Q & inst_BGACK_030_INT_D.Q & !inst_CLK_000_NE.Q & !SM_AMIGA_7_.Q & !SM_AMIGA_0_.Q # !AMIGA_BUS_ENABLE.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_7_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & inst_BGACK_030_INT_D.Q & inst_CLK_000_D1.Q & !inst_CLK_000_D0.Q & SM_AMIGA_7_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q); AMIGA_BUS_ENABLE.AP = (!RST); AMIGA_BUS_ENABLE.C = (CLK_OSZI); AMIGA_BUS_ENABLE_LOW.AR = (!RST); AMIGA_BUS_ENABLE_LOW.D = (!AMIGA_BUS_ENABLE_LOW.Q); AMIGA_BUS_ENABLE_LOW.C = (AMIGA_BUS_ENABLE_LOW_0); inst_AS_030_000_SYNC.D = (!BERR # AS_030.PIN # !nEXP_SPACE & inst_AS_030_000_SYNC.Q # !BGACK_030.Q & inst_AS_030_000_SYNC.Q # inst_AS_030_000_SYNC.Q & !SM_AMIGA_7_.Q # FC_1_ & BGACK_000 & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & inst_AS_030_000_SYNC.Q); inst_AS_030_000_SYNC.AP = (!RST); inst_AS_030_000_SYNC.C = (CLK_OSZI); inst_BGACK_030_INT_D.D = (BGACK_030.Q); inst_BGACK_030_INT_D.AP = (!RST); inst_BGACK_030_INT_D.C = (CLK_OSZI); inst_VPA_D.D = (VPA); inst_VPA_D.AP = (!RST); inst_VPA_D.C = (CLK_OSZI); inst_CLK_OUT_PRE_50_D.AR = (!RST); inst_CLK_OUT_PRE_50_D.D = (inst_CLK_OUT_PRE_50.Q); inst_CLK_OUT_PRE_50_D.C = (CLK_OSZI); CLK_CNT_N_0_.AR = (!RST); CLK_CNT_N_0_.D = (CLK_CNT_N_0_.Q & CLK_CNT_N_1_.Q # !CLK_CNT_N_0_.Q & !CLK_CNT_N_1_.Q); CLK_CNT_N_0_.C = (!CLK_OSZI); inst_CLK_OUT_PRE_50.AR = (!RST); inst_CLK_OUT_PRE_50.D = (!inst_CLK_OUT_PRE_50.Q); inst_CLK_OUT_PRE_50.C = (CLK_OSZI); inst_CLK_OUT_PRE_25.AR = (!RST); inst_CLK_OUT_PRE_25.D = (inst_CLK_OUT_PRE_50_D.Q & inst_CLK_OUT_PRE_25.Q # !inst_CLK_OUT_PRE_50.Q & inst_CLK_OUT_PRE_25.Q # !inst_CLK_OUT_PRE_50_D.Q & inst_CLK_OUT_PRE_50.Q & !inst_CLK_OUT_PRE_25.Q); inst_CLK_OUT_PRE_25.C = (CLK_OSZI); inst_CLK_000_D1.D = (inst_CLK_000_D0.Q); inst_CLK_000_D1.AP = (!RST); inst_CLK_000_D1.C = (CLK_OSZI); inst_CLK_000_D2.D = (inst_CLK_000_D1.Q); inst_CLK_000_D2.AP = (!RST); inst_CLK_000_D2.C = (CLK_OSZI); inst_CLK_000_D3.D = (inst_CLK_000_D2.Q); inst_CLK_000_D3.AP = (!RST); inst_CLK_000_D3.C = (CLK_OSZI); inst_CLK_000_D0.D = (CLK_000); inst_CLK_000_D0.AP = (!RST); inst_CLK_000_D0.C = (CLK_OSZI); inst_CLK_000_NE.AR = (!RST); inst_CLK_000_NE.D = (CLK_000_N_SYNC_11_.Q); inst_CLK_000_NE.C = (CLK_OSZI); inst_CLK_OUT_PRE_D.AR = (!RST); inst_CLK_OUT_PRE_D.D = (inst_CLK_OUT_PRE.Q); inst_CLK_OUT_PRE_D.C = (CLK_OSZI); inst_CLK_OUT_PRE.AR = (!RST); inst_CLK_OUT_PRE.D = (inst_CLK_OUT_PRE_25.Q); inst_CLK_OUT_PRE.C = (CLK_OSZI); CLK_000_P_SYNC_9_.AR = (!RST); CLK_000_P_SYNC_9_.D = (CLK_000_P_SYNC_8_.Q); CLK_000_P_SYNC_9_.C = (CLK_OSZI); CLK_000_N_SYNC_11_.AR = (!RST); CLK_000_N_SYNC_11_.D = (CLK_000_N_SYNC_10_.Q); CLK_000_N_SYNC_11_.C = (CLK_OSZI); SM_AMIGA_7_.D = (SM_AMIGA_7__0 # !BERR & SM_AMIGA_0_.Q # !BERR & !AVEC_EXP.Q & SM_AMIGA_6_.Q # !BERR & !inst_CLK_000_NE.Q & SM_AMIGA_1_.Q # !BERR & !AVEC_EXP.Q & SM_AMIGA_4_.Q # !BERR & !inst_CLK_000_NE.Q & SM_AMIGA_5_.Q # !BERR & !inst_CLK_000_NE.Q & SM_AMIGA_3_.Q # !BERR & !AVEC_EXP.Q & SM_AMIGA_2_.Q # !BERR & !VPA & VMA.Q & SM_AMIGA_3_.Q # !BERR & !VPA & SM_AMIGA_3_.Q & cpu_est_1_.Q # !BERR & !VPA & SM_AMIGA_3_.Q & !E.Q # !BERR & VPA & SM_AMIGA_3_.Q & DTACK.PIN # !nEXP_SPACE & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q); SM_AMIGA_7_.AP = (!RST); SM_AMIGA_7_.C = (CLK_OSZI); SM_AMIGA_6_.AR = (!RST); SM_AMIGA_6_.D = (BERR & !AVEC_EXP.Q & SM_AMIGA_6_.Q # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D1.Q & !inst_CLK_000_D0.Q & SM_AMIGA_7_.Q); SM_AMIGA_6_.C = (CLK_OSZI); SM_AMIGA_1_.AR = (!RST); SM_AMIGA_1_.D = (AVEC_EXP.Q & SM_AMIGA_2_.Q # BERR & !inst_CLK_000_NE.Q & SM_AMIGA_1_.Q); SM_AMIGA_1_.C = (CLK_OSZI); SM_AMIGA_0_.AR = (!RST); SM_AMIGA_0_.D = (BERR & !AVEC_EXP.Q & SM_AMIGA_0_.Q # inst_CLK_000_NE.Q & SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q); SM_AMIGA_0_.C = (CLK_OSZI); SM_AMIGA_4_.AR = (!RST); SM_AMIGA_4_.D = (inst_CLK_000_NE.Q & SM_AMIGA_5_.Q # BERR & !AVEC_EXP.Q & SM_AMIGA_4_.Q); SM_AMIGA_4_.C = (CLK_OSZI); CLK_000_N_SYNC_6_.AR = (!RST); CLK_000_N_SYNC_6_.D = (CLK_000_N_SYNC_5_.Q); CLK_000_N_SYNC_6_.C = (CLK_OSZI); inst_CLK_030_H.D = (!RST & inst_CLK_030_H.Q # !BGACK_030.Q & inst_CLK_030_H.Q & !AS_000.PIN & !UDS_000.PIN # !BGACK_030.Q & inst_CLK_030_H.Q & !AS_000.PIN & !LDS_000.PIN # !CLK_030 & RST & !BGACK_030.Q & !AS_030.Q & !AS_000.PIN & !UDS_000.PIN # !CLK_030 & RST & !BGACK_030.Q & !AS_030.Q & !AS_000.PIN & !LDS_000.PIN); inst_CLK_030_H.C = (CLK_OSZI); CLK_CNT_P_1_.AR = (!RST); CLK_CNT_P_1_.D = (CLK_CNT_P_0_.Q); CLK_CNT_P_1_.C = (CLK_OSZI); CLK_CNT_N_1_.D = (CLK_CNT_N_0_.Q); CLK_CNT_N_1_.AP = (!RST); CLK_CNT_N_1_.C = (!CLK_OSZI); CLK_CNT_P_0_.AR = (!RST); CLK_CNT_P_0_.D = (CLK_CNT_P_1_.Q & CLK_CNT_P_0_.Q # !CLK_CNT_P_1_.Q & !CLK_CNT_P_0_.Q); CLK_CNT_P_0_.C = (CLK_OSZI); inst_LDS_000_INT.D = (inst_LDS_000_INT.Q & DS_030.PIN # !DS_030.PIN & SIZE_0_.PIN & !SIZE_1_.PIN & !A0.PIN); inst_LDS_000_INT.AP = (!RST); inst_LDS_000_INT.C = (CLK_OSZI); inst_DS_000_ENABLE.AR = (!RST); inst_DS_000_ENABLE.D = (AVEC_EXP.Q & SM_AMIGA_4_.Q # BERR & inst_DS_000_ENABLE.Q & !AS_030.PIN # AVEC_EXP.Q & SM_AMIGA_6_.Q & RW.PIN); inst_DS_000_ENABLE.C = (CLK_OSZI); inst_UDS_000_INT.D = (inst_UDS_000_INT.Q & DS_030.PIN # !DS_030.PIN & A0.PIN); inst_UDS_000_INT.AP = (!RST); inst_UDS_000_INT.C = (CLK_OSZI); CLK_000_P_SYNC_0_.AR = (!RST); CLK_000_P_SYNC_0_.D = (!inst_CLK_000_D1.Q & !inst_CLK_000_D2.Q & !inst_CLK_000_D3.Q & inst_CLK_000_D0.Q); CLK_000_P_SYNC_0_.C = (CLK_OSZI); CLK_000_P_SYNC_1_.AR = (!RST); CLK_000_P_SYNC_1_.D = (CLK_000_P_SYNC_0_.Q); CLK_000_P_SYNC_1_.C = (CLK_OSZI); CLK_000_P_SYNC_2_.AR = (!RST); CLK_000_P_SYNC_2_.D = (CLK_000_P_SYNC_1_.Q); CLK_000_P_SYNC_2_.C = (CLK_OSZI); CLK_000_P_SYNC_3_.AR = (!RST); CLK_000_P_SYNC_3_.D = (CLK_000_P_SYNC_2_.Q); CLK_000_P_SYNC_3_.C = (CLK_OSZI); CLK_000_P_SYNC_4_.AR = (!RST); CLK_000_P_SYNC_4_.D = (CLK_000_P_SYNC_3_.Q); CLK_000_P_SYNC_4_.C = (CLK_OSZI); CLK_000_P_SYNC_5_.AR = (!RST); CLK_000_P_SYNC_5_.D = (CLK_000_P_SYNC_4_.Q); CLK_000_P_SYNC_5_.C = (CLK_OSZI); CLK_000_P_SYNC_6_.AR = (!RST); CLK_000_P_SYNC_6_.D = (CLK_000_P_SYNC_5_.Q); CLK_000_P_SYNC_6_.C = (CLK_OSZI); CLK_000_P_SYNC_7_.AR = (!RST); CLK_000_P_SYNC_7_.D = (CLK_000_P_SYNC_6_.Q); CLK_000_P_SYNC_7_.C = (CLK_OSZI); CLK_000_P_SYNC_8_.AR = (!RST); CLK_000_P_SYNC_8_.D = (CLK_000_P_SYNC_7_.Q); CLK_000_P_SYNC_8_.C = (CLK_OSZI); CLK_000_N_SYNC_0_.AR = (!RST); CLK_000_N_SYNC_0_.D = (inst_CLK_000_D1.Q & inst_CLK_000_D2.Q & inst_CLK_000_D3.Q & !inst_CLK_000_D0.Q); CLK_000_N_SYNC_0_.C = (CLK_OSZI); CLK_000_N_SYNC_1_.AR = (!RST); CLK_000_N_SYNC_1_.D = (CLK_000_N_SYNC_0_.Q); CLK_000_N_SYNC_1_.C = (CLK_OSZI); CLK_000_N_SYNC_2_.AR = (!RST); CLK_000_N_SYNC_2_.D = (CLK_000_N_SYNC_1_.Q); CLK_000_N_SYNC_2_.C = (CLK_OSZI); CLK_000_N_SYNC_3_.AR = (!RST); CLK_000_N_SYNC_3_.D = (CLK_000_N_SYNC_2_.Q); CLK_000_N_SYNC_3_.C = (CLK_OSZI); CLK_000_N_SYNC_4_.AR = (!RST); CLK_000_N_SYNC_4_.D = (CLK_000_N_SYNC_3_.Q); CLK_000_N_SYNC_4_.C = (CLK_OSZI); CLK_000_N_SYNC_5_.AR = (!RST); CLK_000_N_SYNC_5_.D = (CLK_000_N_SYNC_4_.Q); CLK_000_N_SYNC_5_.C = (CLK_OSZI); CLK_000_N_SYNC_7_.AR = (!RST); CLK_000_N_SYNC_7_.D = (CLK_000_N_SYNC_6_.Q); CLK_000_N_SYNC_7_.C = (CLK_OSZI); CLK_000_N_SYNC_8_.AR = (!RST); CLK_000_N_SYNC_8_.D = (CLK_000_N_SYNC_7_.Q); CLK_000_N_SYNC_8_.C = (CLK_OSZI); CLK_000_N_SYNC_9_.AR = (!RST); CLK_000_N_SYNC_9_.D = (CLK_000_N_SYNC_8_.Q); CLK_000_N_SYNC_9_.C = (CLK_OSZI); CLK_000_N_SYNC_10_.AR = (!RST); CLK_000_N_SYNC_10_.D = (CLK_000_N_SYNC_9_.Q); CLK_000_N_SYNC_10_.C = (CLK_OSZI); SM_AMIGA_5_.AR = (!RST); SM_AMIGA_5_.D = (AVEC_EXP.Q & SM_AMIGA_6_.Q # BERR & !inst_CLK_000_NE.Q & SM_AMIGA_5_.Q); SM_AMIGA_5_.C = (CLK_OSZI); SM_AMIGA_3_.AR = (!RST); SM_AMIGA_3_.D = (AVEC_EXP.Q & SM_AMIGA_4_.Q # BERR & !inst_CLK_000_NE.Q & SM_AMIGA_3_.Q # BERR & !VPA & VMA.Q & SM_AMIGA_3_.Q # BERR & !VPA & SM_AMIGA_3_.Q & cpu_est_1_.Q # BERR & !VPA & SM_AMIGA_3_.Q & !E.Q # BERR & VPA & SM_AMIGA_3_.Q & DTACK.PIN); SM_AMIGA_3_.C = (CLK_OSZI); SM_AMIGA_2_.AR = (!RST); SM_AMIGA_2_.D = (BERR & !AVEC_EXP.Q & SM_AMIGA_2_.Q # VPA & inst_CLK_000_NE.Q & SM_AMIGA_3_.Q & !DTACK.PIN # !VPA & !VMA.Q & inst_CLK_000_NE.Q & SM_AMIGA_3_.Q & !cpu_est_1_.Q & E.Q); SM_AMIGA_2_.C = (CLK_OSZI); !un16_ciin = (nEXP_SPACE & AS_030.PIN # !A_31_ & nEXP_SPACE & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_ # !A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_ & A_23_ & A_22_ & A_21_ & A_20_ & !AS_030.PIN); cpu_est_0_.AR = (!RST); cpu_est_0_.D = (!AVEC_EXP.Q & cpu_est_0_.Q # AVEC_EXP.Q & !cpu_est_0_.Q); cpu_est_0_.C = (CLK_OSZI); cpu_est_1_.AR = (!RST); cpu_est_1_.D = (!AVEC_EXP.Q & cpu_est_1_.Q # !cpu_est_0_.Q & cpu_est_1_.Q # AVEC_EXP.Q & cpu_est_0_.Q & !cpu_est_1_.Q # AVEC_EXP.Q & cpu_est_2_.Q & E.Q # AVEC_EXP.Q & !cpu_est_2_.Q & !E.Q); cpu_est_1_.C = (CLK_OSZI); cpu_est_2_.AR = (!RST); cpu_est_2_.D = (!AVEC_EXP.Q & cpu_est_2_.Q # cpu_est_1_.Q & cpu_est_2_.Q # AVEC_EXP.Q & !cpu_est_0_.Q & !cpu_est_1_.Q # AVEC_EXP.Q & cpu_est_0_.Q & E.Q); cpu_est_2_.C = (CLK_OSZI); AMIGA_BUS_ENABLE_LOW_0 = (CLK_CNT_P_1_.Q & CLK_CNT_N_1_.Q # !CLK_CNT_N_0_.Q & CLK_CNT_P_0_.Q); SM_AMIGA_7__0 = (AVEC_EXP.Q & SM_AMIGA_0_.Q # inst_AS_030_000_SYNC.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q # !inst_CLK_000_D1.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q # inst_CLK_000_D0.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q); Reverse-Polarity Equations: