Section Type Array Num Name Real Name Base Number Increment // ------------------------------------------------------------------------------------------------- Port 1 A(31:16) A 31 16 -1 Port 2 IPL(2:0) IPL 2 3 -1 Port 3 FC(1:0) FC 1 2 -1 Port 4 IPL_030(2:0) IPL_030 2 3 -1 Port 5 SIZE(1:0) SIZE 1 2 -1 End Section Member Rename Array-Notation Array Number Index // ------------------------------------------------------------------------------------- Port SIZE_1_ SIZE[1] 5 0 Port SIZE_0_ SIZE[0] 5 1 Port A_31_ A[31] 1 0 Port A_30_ A[30] 1 1 Port A_29_ A[29] 1 2 Port A_28_ A[28] 1 3 Port A_27_ A[27] 1 4 Port A_26_ A[26] 1 5 Port A_25_ A[25] 1 6 Port A_24_ A[24] 1 7 Port A_23_ A[23] 1 8 Port A_22_ A[22] 1 9 Port A_21_ A[21] 1 10 Port A_20_ A[20] 1 11 Port A_19_ A[19] 1 12 Port A_18_ A[18] 1 13 Port A_17_ A[17] 1 14 Port A_16_ A[16] 1 15 Port IPL_030_2_ IPL_030[2] 4 0 Port IPL_030_1_ IPL_030[1] 4 1 Port IPL_030_0_ IPL_030[0] 4 2 Port IPL_2_ IPL[2] 2 0 Port IPL_1_ IPL[1] 2 1 Port IPL_0_ IPL[0] 2 2 Port FC_1_ FC[1] 3 0 Port FC_0_ FC[0] 3 1 End Section Cross Reference File Design 'BUS68030' created Sun Jun 22 21:24:20 2014 Type New Name Original Name // ---------------------------------------------------------------------- Inst i_z3N3N AS_030 Inst i_z3O3O AS_000 Inst i_z3P3P RW_000 Inst i_z3Q3Q DS_030 Inst i_z3R3R UDS_000 Inst i_z3S3S LDS_000 Inst i_z4F4F A0 Inst i_z5252 DSACK1 Inst i_z5353 DTACK Inst i_z5B5B RW Inst i_z5H5H CIIN Inst state_machine_un28_as_030_2 state_machine.un28_as_030_2 Inst IPL_030_0_2__n IPL_030_0_2_.n Inst IPL_030_0_2__p IPL_030_0_2_.p Inst IPL_030_0_1__r IPL_030_0_1_.r Inst IPL_030_0_1__m IPL_030_0_1_.m Inst IPL_030_0_1__n IPL_030_0_1_.n Inst IPL_030_0_1__p IPL_030_0_1_.p Inst IPL_030_0_0__r IPL_030_0_0_.r Inst IPL_030_0_0__m IPL_030_0_0_.m Inst SIZE_c_i_1_ SIZE_c_i[1] Inst IPL_030_0_0__n IPL_030_0_0_.n Inst cpu_est_ns_0_1_2_ cpu_est_ns_0_1[2] Inst IPL_030_0_0__p IPL_030_0_0_.p Inst cpu_est_ns_0_2_ cpu_est_ns_0[2] Inst SM_AMIGA_ns_1_0_ SM_AMIGA_ns_1[0] Inst state_machine_un28_as_030_i state_machine.un28_as_030_i Inst SM_AMIGA_ns_2_0_ SM_AMIGA_ns_2[0] Inst A_i_16_ A_i[16] Inst SM_AMIGA_ns_3_0_ SM_AMIGA_ns_3[0] Inst A_i_18_ A_i[18] Inst SM_AMIGA_ns_0_ SM_AMIGA_ns[0] Inst A_i_19_ A_i[19] Inst state_machine_un5_clk_000_n_sync state_machine.un5_clk_000_n_sync Inst state_machine_un4_bgack_000 state_machine.un4_bgack_000 Inst state_machine_un9_clk_000_ne state_machine.un9_clk_000_ne Inst state_machine_RW_000_INT_3_i state_machine.RW_000_INT_3_i Inst state_machine_un8_bg_030 state_machine.un8_bg_030 Inst state_machine_un9_clk_000_ne_i state_machine.un9_clk_000_ne_i Inst state_machine_un15_clk_000_ne_i state_machine.un15_clk_000_ne_i Inst state_machine_un11_clk_000_ne_i_0 state_machine.un11_clk_000_ne_i_0 Inst state_machine_un6_bg_030_i state_machine.un6_bg_030_i Inst state_machine_un8_bg_030_i state_machine.un8_bg_030_i Inst state_machine_un4_bgack_000_i state_machine.un4_bgack_000_i Inst CLK_CNT_N_i_0_ CLK_CNT_N_i[0] Inst state_machine_un10_bgack_030_int_i state_machine.un10_bgack_030_int_i Inst state_machine_un26_clk_000_pe_i state_machine.un26_clk_000_pe_i Inst state_machine_un5_clk_000_ne_i state_machine.un5_clk_000_ne_i Inst state_machine_un28_clk_000_pe_i state_machine.un28_clk_000_pe_i Inst cpu_est_ns_0_i_1_ cpu_est_ns_0_i[1] Inst un4_clk_cnt_n_1_i_1_ un4_clk_cnt_n_1_i[1] Inst un2_clk_cnt_p_i_1_ un2_clk_cnt_p_i[1] Inst state_machine_un26_clk_000_pe_2_i state_machine.un26_clk_000_pe_2_i Inst state_machine_un3_clk_out_pre_50 state_machine.un3_clk_out_pre_50 Inst cpu_est_0_ cpu_est[0] Inst AS_030_000_SYNC_0_r AS_030_000_SYNC_0.r Inst cpu_est_1_ cpu_est[1] Inst cpu_est_ns_0_i_2_ cpu_est_ns_0_i[2] Inst AS_030_000_SYNC_0_m AS_030_000_SYNC_0.m Inst cpu_est_2_ cpu_est[2] Inst AS_030_000_SYNC_0_n AS_030_000_SYNC_0.n Inst cpu_est_3_ cpu_est[3] Inst AS_030_000_SYNC_0_p AS_030_000_SYNC_0.p Inst IPL_030DFFSH_0_ IPL_030DFFSH[0] Inst AS_000_INT_0_r AS_000_INT_0.r Inst IPL_030DFFSH_1_ IPL_030DFFSH[1] Inst AS_000_INT_0_m AS_000_INT_0.m Inst IPL_030DFFSH_2_ IPL_030DFFSH[2] Inst AS_000_INT_0_n AS_000_INT_0.n Inst SM_AMIGA_7_ SM_AMIGA[7] Inst SM_AMIGA_ns_i_4_ SM_AMIGA_ns_i[4] Inst AS_000_INT_0_p AS_000_INT_0.p Inst SM_AMIGA_6_ SM_AMIGA[6] Inst SM_AMIGA_ns_i_0_ SM_AMIGA_ns_i[0] Inst DS_000_ENABLE_0_r DS_000_ENABLE_0.r Inst SM_AMIGA_5_ SM_AMIGA[5] Inst DS_000_ENABLE_0_m DS_000_ENABLE_0.m Inst SM_AMIGA_4_ SM_AMIGA[4] Inst DS_000_ENABLE_0_n DS_000_ENABLE_0.n Inst SM_AMIGA_3_ SM_AMIGA[3] Inst DS_000_ENABLE_0_p DS_000_ENABLE_0.p Inst SM_AMIGA_2_ SM_AMIGA[2] Inst DSACK1_INT_0_r DSACK1_INT_0.r Inst SM_AMIGA_1_ SM_AMIGA[1] Inst DSACK1_INT_0_m DSACK1_INT_0.m Inst SM_AMIGA_0_ SM_AMIGA[0] Inst state_machine_CLK_030_H_2_f1_i state_machine.CLK_030_H_2_f1_i Inst DSACK1_INT_0_n DSACK1_INT_0.n Inst CLK_000_N_SYNC_3_ CLK_000_N_SYNC[3] Inst state_machine_SIZE_DMA_4_i_1_ state_machine.SIZE_DMA_4_i[1] Inst DSACK1_INT_0_p DSACK1_INT_0.p Inst CLK_000_N_SYNC_4_ CLK_000_N_SYNC[4] Inst state_machine_SIZE_DMA_4_i_0_ state_machine.SIZE_DMA_4_i[0] Inst BG_000_0_r BG_000_0.r Inst CLK_000_N_SYNC_5_ CLK_000_N_SYNC[5] Inst SM_AMIGA_ns_o4_0_i_0_ SM_AMIGA_ns_o4_0_i[0] Inst BG_000_0_m BG_000_0.m Inst CLK_000_N_SYNC_6_ CLK_000_N_SYNC[6] Inst SM_AMIGA_i_5_ SM_AMIGA_i[5] Inst BG_000_0_n BG_000_0.n Inst CLK_000_N_SYNC_7_ CLK_000_N_SYNC[7] Inst SM_AMIGA_ns_o4_1_i_0_ SM_AMIGA_ns_o4_1_i[0] Inst BG_000_0_p BG_000_0.p Inst CLK_000_N_SYNC_8_ CLK_000_N_SYNC[8] Inst SM_AMIGA_ns_i_o4_i_7_ SM_AMIGA_ns_i_o4_i[7] Inst LDS_000_INT_0_r LDS_000_INT_0.r Inst CLK_000_N_SYNC_9_ CLK_000_N_SYNC[9] Inst state_machine_un3_bgack_030_int_d_i state_machine.un3_bgack_030_int_d_i Inst LDS_000_INT_0_m LDS_000_INT_0.m Inst CLK_000_N_SYNC_10_ CLK_000_N_SYNC[10] Inst LDS_000_INT_0_n LDS_000_INT_0.n Inst CLK_000_N_SYNC_11_ CLK_000_N_SYNC[11] Inst LDS_000_INT_0_p LDS_000_INT_0.p Inst CLK_CNT_N_0_ CLK_CNT_N[0] Inst UDS_000_INT_0_r UDS_000_INT_0.r Inst CLK_CNT_N_1_ CLK_CNT_N[1] Inst SM_AMIGA_i_6_ SM_AMIGA_i[6] Inst UDS_000_INT_0_m UDS_000_INT_0.m Inst CLK_CNT_P_0_ CLK_CNT_P[0] Inst SM_AMIGA_ns_o4_2_i_0_ SM_AMIGA_ns_o4_2_i[0] Inst UDS_000_INT_0_n UDS_000_INT_0.n Inst CLK_CNT_P_1_ CLK_CNT_P[1] Inst SM_AMIGA_i_2_ SM_AMIGA_i[2] Inst UDS_000_INT_0_p UDS_000_INT_0.p Inst SIZE_DMA_0_ SIZE_DMA[0] Inst SM_AMIGA_i_4_ SM_AMIGA_i[4] Inst BGACK_030_INT_0_r BGACK_030_INT_0.r Inst SIZE_DMA_1_ SIZE_DMA[1] Inst BGACK_030_INT_0_m BGACK_030_INT_0.m Inst CLK_000_P_SYNC_0_ CLK_000_P_SYNC[0] Inst BGACK_030_INT_0_n BGACK_030_INT_0.n Inst CLK_000_P_SYNC_1_ CLK_000_P_SYNC[1] Inst BGACK_030_INT_0_p BGACK_030_INT_0.p Inst CLK_000_P_SYNC_2_ CLK_000_P_SYNC[2] Inst CLK_000_P_SYNC_3_ CLK_000_P_SYNC[3] Inst CLK_000_P_SYNC_4_ CLK_000_P_SYNC[4] Inst SM_AMIGA_ns_i_1_ SM_AMIGA_ns_i[1] Inst CLK_000_P_SYNC_5_ CLK_000_P_SYNC[5] Inst CLK_000_P_SYNC_6_ CLK_000_P_SYNC[6] Inst SM_AMIGA_ns_i_2_ SM_AMIGA_ns_i[2] Inst CLK_000_P_SYNC_7_ CLK_000_P_SYNC[7] Inst CLK_000_P_SYNC_8_ CLK_000_P_SYNC[8] Inst CLK_000_P_SYNC_9_ CLK_000_P_SYNC[9] Inst SM_AMIGA_ns_i_3_ SM_AMIGA_ns_i[3] Inst CLK_000_N_SYNC_0_ CLK_000_N_SYNC[0] Inst CLK_000_N_SYNC_1_ CLK_000_N_SYNC[1] Inst CLK_000_N_SYNC_2_ CLK_000_N_SYNC[2] Inst SM_AMIGA_ns_i_5_ SM_AMIGA_ns_i[5] Inst SM_AMIGA_ns_i_6_ SM_AMIGA_ns_i[6] Inst SM_AMIGA_ns_o4_i_0_ SM_AMIGA_ns_o4_i[0] Inst state_machine_un1_as_030_i_0 state_machine.un1_as_030_i_0 Inst A_i_27_ A_i[27] Inst A_i_28_ A_i[28] Inst A_i_25_ A_i[25] Inst A_i_26_ A_i[26] Inst A_i_24_ A_i[24] Inst SM_AMIGA_ns_5_ SM_AMIGA_ns[5] Inst SM_AMIGA_ns_3_ SM_AMIGA_ns[3] Inst SM_AMIGA_ns_2_ SM_AMIGA_ns[2] Inst SM_AMIGA_ns_1_ SM_AMIGA_ns[1] Inst SM_AMIGA_ns_a4_6_ SM_AMIGA_ns_a4[6] Inst SM_AMIGA_ns_a4_0_5_ SM_AMIGA_ns_a4_0[5] Inst SM_AMIGA_ns_a4_5_ SM_AMIGA_ns_a4[5] Inst SM_AMIGA_ns_a4_0_3_ SM_AMIGA_ns_a4_0[3] Inst SM_AMIGA_ns_a4_3_ SM_AMIGA_ns_a4[3] Inst SM_AMIGA_ns_a4_0_1_ SM_AMIGA_ns_a4_0[1] Inst state_machine_un1_as_030 state_machine.un1_as_030 Inst A_i_31_ A_i[31] Inst A_i_29_ A_i[29] Inst A_i_30_ A_i[30] Inst SM_AMIGA_i_7_ SM_AMIGA_i[7] Inst SM_AMIGA_i_0_ SM_AMIGA_i[0] Inst SIZE_0_ SIZE[0] Inst SIZE_1_ SIZE[1] Inst SM_AMIGA_i_3_ SM_AMIGA_i[3] Inst A_16_ A[16] Inst SM_AMIGA_ns_a4_2_ SM_AMIGA_ns_a4[2] Inst A_17_ A[17] Inst SM_AMIGA_ns_a4_1_2_ SM_AMIGA_ns_a4_1[2] Inst A_18_ A[18] Inst SM_AMIGA_ns_a4_0_6_ SM_AMIGA_ns_a4_0[6] Inst A_19_ A[19] Inst SM_AMIGA_i_1_ SM_AMIGA_i[1] Inst A_20_ A[20] Inst SM_AMIGA_ns_i_o4_7_ SM_AMIGA_ns_i_o4[7] Inst A_21_ A[21] Inst SM_AMIGA_ns_o4_1_0_ SM_AMIGA_ns_o4_1[0] Inst A_22_ A[22] Inst A_23_ A[23] Inst SM_AMIGA_ns_o4_0_0_ SM_AMIGA_ns_o4_0[0] Inst A_24_ A[24] Inst SM_AMIGA_ns_o4_0_ SM_AMIGA_ns_o4[0] Inst A_25_ A[25] Inst SM_AMIGA_ns_6_ SM_AMIGA_ns[6] Inst A_26_ A[26] Inst A_27_ A[27] Inst state_machine_un5_bgack_030_int_d state_machine.un5_bgack_030_int_d Inst A_28_ A[28] Inst A_29_ A[29] Inst A_30_ A[30] Inst A_31_ A[31] Inst SM_AMIGA_ns_a4_2_0_ SM_AMIGA_ns_a4_2[0] Inst SM_AMIGA_ns_a4_1_ SM_AMIGA_ns_a4[1] Inst SM_AMIGA_ns_i_a4_7_ SM_AMIGA_ns_i_a4[7] Inst SM_AMIGA_ns_4_ SM_AMIGA_ns[4] Inst SM_AMIGA_ns_i_7_ SM_AMIGA_ns_i[7] Inst state_machine_CLK_030_H_2_f0 state_machine.CLK_030_H_2_f0 Inst IPL_030_0_ IPL_030[0] Inst IPL_030_1_ IPL_030[1] Inst IPL_030_2_ IPL_030[2] Inst IPL_0_ IPL[0] Inst IPL_1_ IPL[1] Inst IPL_2_ IPL[2] Inst state_machine_un24_bgack_030_int_i state_machine.un24_bgack_030_int_i Inst state_machine_un8_bgack_030_int state_machine.un8_bgack_030_int Inst AMIGA_BUS_ENABLE_INT_0_r AMIGA_BUS_ENABLE_INT_0.r Inst AMIGA_BUS_ENABLE_INT_0_m AMIGA_BUS_ENABLE_INT_0.m Inst AMIGA_BUS_ENABLE_INT_0_n AMIGA_BUS_ENABLE_INT_0.n Inst AMIGA_BUS_ENABLE_INT_0_p AMIGA_BUS_ENABLE_INT_0.p Inst state_machine_un3_bgack_030_int_d state_machine.un3_bgack_030_int_d Inst DS_000_DMA_0_r DS_000_DMA_0.r Inst FC_0_ FC[0] Inst DS_000_DMA_0_m DS_000_DMA_0.m Inst FC_1_ FC[1] Inst DS_000_DMA_0_n DS_000_DMA_0.n Inst DS_000_DMA_0_p DS_000_DMA_0.p Inst AS_000_DMA_0_r AS_000_DMA_0.r Inst AS_000_DMA_0_m AS_000_DMA_0.m Inst AS_000_DMA_0_n AS_000_DMA_0.n Inst AS_000_DMA_0_p AS_000_DMA_0.p Inst state_machine_un24_bgack_030_int state_machine.un24_bgack_030_int Inst state_machine_un10_bgack_030_int state_machine.un10_bgack_030_int Inst state_machine_un31_bgack_030_int state_machine.un31_bgack_030_int Inst state_machine_A0_DMA_2 state_machine.A0_DMA_2 Inst state_machine_un31_bgack_030_int_i state_machine.un31_bgack_030_int_i Inst state_machine_SIZE_DMA_4_0_ state_machine.SIZE_DMA_4[0] Inst state_machine_un8_bgack_030_int_i state_machine.un8_bgack_030_int_i Inst state_machine_SIZE_DMA_4_1_ state_machine.SIZE_DMA_4[1] Inst state_machine_CLK_030_H_2_f1 state_machine.CLK_030_H_2_f1 Inst cpu_est_ns_0_a3_2_ cpu_est_ns_0_a3[2] Inst cpu_est_i_1_ cpu_est_i[1] Inst cpu_est_ns_0_a3_1_1_ cpu_est_ns_0_a3_1[1] Inst cpu_est_ns_0_a3_0_1_ cpu_est_ns_0_a3_0[1] Inst cpu_est_i_3_ cpu_est_i[3] Inst cpu_est_i_2_ cpu_est_i[2] Inst SM_AMIGA_ns_o4_2_0_ SM_AMIGA_ns_o4_2[0] Inst cpu_est_ns_0_a3_1_ cpu_est_ns_0_a3[1] Inst SM_AMIGA_ns_a4_1_4_ SM_AMIGA_ns_a4_1[4] Inst state_machine_un28_clk_000_pe state_machine.un28_clk_000_pe Inst SM_AMIGA_ns_a4_4_ SM_AMIGA_ns_a4[4] Inst cpu_estse_2_r cpu_estse_2.r Inst SM_AMIGA_ns_a4_1_0_0_ SM_AMIGA_ns_a4_1_0[0] Inst cpu_estse_2_m cpu_estse_2.m Inst SM_AMIGA_ns_a4_0_ SM_AMIGA_ns_a4[0] Inst cpu_estse_2_n cpu_estse_2.n Inst SM_AMIGA_ns_a4_0_1_0_ SM_AMIGA_ns_a4_0_1[0] Inst cpu_estse_2_p cpu_estse_2.p Inst SM_AMIGA_ns_a4_0_0_ SM_AMIGA_ns_a4_0[0] Inst cpu_estse_1_r cpu_estse_1.r Inst SM_AMIGA_ns_a4_1_1_0_ SM_AMIGA_ns_a4_1_1[0] Inst cpu_estse_1_m cpu_estse_1.m Inst SM_AMIGA_ns_a4_1_0_ SM_AMIGA_ns_a4_1[0] Inst cpu_estse_1_n cpu_estse_1.n Inst SM_AMIGA_ns_a4_3_1_0_ SM_AMIGA_ns_a4_3_1[0] Inst cpu_estse_1_p cpu_estse_1.p Inst SM_AMIGA_ns_a4_3_2_0_ SM_AMIGA_ns_a4_3_2[0] Inst cpu_estse_0_r cpu_estse_0.r Inst SM_AMIGA_ns_a4_3_3_0_ SM_AMIGA_ns_a4_3_3[0] Inst cpu_estse_0_m cpu_estse_0.m Inst SM_AMIGA_ns_a4_3_0_ SM_AMIGA_ns_a4_3[0] Inst cpu_estse_0_n cpu_estse_0.n Inst cpu_estse_0_p cpu_estse_0.p Inst VMA_INT_0_r VMA_INT_0.r Inst VMA_INT_0_m VMA_INT_0.m Inst state_machine_un26_clk_000_pe_1 state_machine.un26_clk_000_pe_1 Inst VMA_INT_0_n VMA_INT_0.n Inst state_machine_un26_clk_000_pe state_machine.un26_clk_000_pe Inst VMA_INT_0_p VMA_INT_0.p Inst state_machine_un26_clk_000_pe_4_1 state_machine.un26_clk_000_pe_4_1 Inst CLK_030_H_0_r CLK_030_H_0.r Inst state_machine_un26_clk_000_pe_4 state_machine.un26_clk_000_pe_4 Inst CLK_030_H_0_m CLK_030_H_0.m Inst state_machine_un5_clk_000_ne_1 state_machine.un5_clk_000_ne_1 Inst CLK_030_H_0_n CLK_030_H_0.n Inst state_machine_un5_clk_000_ne_2 state_machine.un5_clk_000_ne_2 Inst CLK_030_H_0_p CLK_030_H_0.p Inst state_machine_un5_clk_000_ne state_machine.un5_clk_000_ne Inst cpu_est_ns_0_1_1_ cpu_est_ns_0_1[1] Inst RW_000_DMA_0_r RW_000_DMA_0.r Inst cpu_est_ns_0_2_1_ cpu_est_ns_0_2[1] Inst RW_000_DMA_0_m RW_000_DMA_0.m Inst cpu_est_ns_0_1_ cpu_est_ns_0[1] Inst RW_000_DMA_0_n RW_000_DMA_0.n Inst RW_000_DMA_0_p RW_000_DMA_0.p Inst RW_000_INT_0_r RW_000_INT_0.r Inst RW_000_INT_0_m RW_000_INT_0.m Inst SM_AMIGA_ns_o4_2_1_0_ SM_AMIGA_ns_o4_2_1[0] Inst RW_000_INT_0_n RW_000_INT_0.n Inst state_machine_un28_as_030 state_machine.un28_as_030 Inst RW_000_INT_0_p RW_000_INT_0.p Inst state_machine_un15_clk_000_ne_1_0 state_machine.un15_clk_000_ne_1_0 Inst state_machine_un15_clk_000_ne state_machine.un15_clk_000_ne Inst state_machine_un6_bg_030_1 state_machine.un6_bg_030_1 Inst state_machine_un6_bg_030 state_machine.un6_bg_030 Inst state_machine_CLK_000_P_SYNC_3_1_0_ state_machine.CLK_000_P_SYNC_3_1[0] Inst state_machine_CLK_000_P_SYNC_3_2_0_ state_machine.CLK_000_P_SYNC_3_2[0] Inst state_machine_un15_clk_000_ne_1 state_machine.un15_clk_000_ne_1 Inst state_machine_CLK_000_P_SYNC_3_0_ state_machine.CLK_000_P_SYNC_3[0] Inst cpu_est_ns_i_3_ cpu_est_ns_i[3] Inst state_machine_CLK_000_N_SYNC_2_1_0_ state_machine.CLK_000_N_SYNC_2_1[0] Inst cpu_est_ns_0_a2_1_ cpu_est_ns_0_a2[1] Inst state_machine_CLK_000_N_SYNC_2_0_ state_machine.CLK_000_N_SYNC_2[0] Inst cpu_est_ns_i_a3_0_3_ cpu_est_ns_i_a3_0[3] Inst state_machine_un15_clk_000_ne_1_i state_machine.un15_clk_000_ne_1_i Inst cpu_est_ns_i_a3_3_ cpu_est_ns_i_a3[3] Inst cpu_est_i_0_ cpu_est_i[0] Inst cpu_est_ns_0_a3_1_2_ cpu_est_ns_0_a3_1[2] Inst cpu_est_ns_0_a3_0_2_ cpu_est_ns_0_a3_0[2] Inst state_machine_un7_ds_030_1 state_machine.un7_ds_030_1 Inst state_machine_un11_clk_000_ne state_machine.un11_clk_000_ne Inst state_machine_un7_ds_030 state_machine.un7_ds_030 Inst state_machine_RW_000_INT_3 state_machine.RW_000_INT_3 Inst IPL_030_0_2__r IPL_030_0_2_.r Inst state_machine_un28_as_030_1 state_machine.un28_as_030_1 Inst IPL_030_0_2__m IPL_030_0_2_.m Net a_i_19__n A_i[19] Net a_i_16__n A_i[16] Net a_i_18__n A_i[18] Net vcc_n_n VCC Net state_machine_un28_as_030_i_n state_machine.un28_as_030_i Net clk_cnt_n_i_0__n CLK_CNT_N_i[0] Net un2_clk_cnt_p_i_1__n un2_clk_cnt_p_i[1] Net un4_clk_cnt_n_1_i_1__n un4_clk_cnt_n_1_i[1] Net clk_cnt_n_0__n CLK_CNT_N[0] Net amiga_bus_enable_int_0_un3_n AMIGA_BUS_ENABLE_INT_0.un3 Net amiga_bus_enable_int_0_un1_n AMIGA_BUS_ENABLE_INT_0.un1 Net amiga_bus_enable_int_0_un0_n AMIGA_BUS_ENABLE_INT_0.un0 Net ds_000_dma_0_un3_n DS_000_DMA_0.un3 Net ds_000_dma_0_un1_n DS_000_DMA_0.un1 Net ds_000_dma_0_un0_n DS_000_DMA_0.un0 Net as_000_dma_0_un3_n AS_000_DMA_0.un3 Net as_000_dma_0_un1_n AS_000_DMA_0.un1 Net as_000_dma_0_un0_n AS_000_DMA_0.un0 Net clk_000_p_sync_9__n CLK_000_P_SYNC[9] Net cpu_estse_2_un3_n cpu_estse_2.un3 Net clk_000_n_sync_11__n CLK_000_N_SYNC[11] Net cpu_estse_2_un1_n cpu_estse_2.un1 Net cpu_estse_2_un0_n cpu_estse_2.un0 Net sm_amiga_7__n SM_AMIGA[7] Net size_c_0__n SIZE_c[0] Net cpu_estse_1_un3_n cpu_estse_1.un3 Net sm_amiga_6__n SM_AMIGA[6] Net size_0__n SIZE[0] Net cpu_estse_1_un1_n cpu_estse_1.un1 Net sm_amiga_1__n SM_AMIGA[1] Net size_c_1__n SIZE_c[1] Net cpu_estse_1_un0_n cpu_estse_1.un0 Net sm_amiga_0__n SM_AMIGA[0] Net cpu_estse_0_un3_n cpu_estse_0.un3 Net sm_amiga_4__n SM_AMIGA[4] Net a_c_16__n A_c[16] Net cpu_estse_0_un1_n cpu_estse_0.un1 Net clk_000_n_sync_6__n CLK_000_N_SYNC[6] Net a_16__n A[16] Net cpu_estse_0_un0_n cpu_estse_0.un0 Net a_c_17__n A_c[17] Net vma_int_0_un3_n VMA_INT_0.un3 Net clk_cnt_p_1__n CLK_CNT_P[1] Net a_17__n A[17] Net vma_int_0_un1_n VMA_INT_0.un1 Net clk_cnt_n_1__n CLK_CNT_N[1] Net a_c_18__n A_c[18] Net vma_int_0_un0_n VMA_INT_0.un0 Net a_18__n A[18] Net clk_030_h_0_un3_n CLK_030_H_0.un3 Net a_c_19__n A_c[19] Net clk_030_h_0_un1_n CLK_030_H_0.un1 Net state_machine_un3_clk_out_pre_50_n state_machine.un3_clk_out_pre_50 Net a_19__n A[19] Net clk_030_h_0_un0_n CLK_030_H_0.un0 Net state_machine_un4_bgack_000_n state_machine.un4_bgack_000 Net a_c_20__n A_c[20] Net rw_000_dma_0_un3_n RW_000_DMA_0.un3 Net clk_cnt_p_0__n CLK_CNT_P[0] Net a_20__n A[20] Net rw_000_dma_0_un1_n RW_000_DMA_0.un1 Net a_c_21__n A_c[21] Net rw_000_dma_0_un0_n RW_000_DMA_0.un0 Net a_21__n A[21] Net rw_000_int_0_un3_n RW_000_INT_0.un3 Net a_c_22__n A_c[22] Net rw_000_int_0_un1_n RW_000_INT_0.un1 Net a_22__n A[22] Net rw_000_int_0_un0_n RW_000_INT_0.un0 Net a_c_23__n A_c[23] Net ipl_030_0_2__un3_n IPL_030_0_2_.un3 Net a_23__n A[23] Net ipl_030_0_2__un1_n IPL_030_0_2_.un1 Net state_machine_clk_000_p_sync_3_0__n state_machine.CLK_000_P_SYNC_3[0] Net a_c_24__n A_c[24] Net ipl_030_0_2__un0_n IPL_030_0_2_.un0 Net state_machine_clk_000_n_sync_2_0__n state_machine.CLK_000_N_SYNC_2[0] Net a_24__n A[24] Net ipl_030_0_1__un3_n IPL_030_0_1_.un3 Net a_c_25__n A_c[25] Net ipl_030_0_1__un1_n IPL_030_0_1_.un1 Net a_25__n A[25] Net ipl_030_0_1__un0_n IPL_030_0_1_.un0 Net size_dma_0__n SIZE_DMA[0] Net a_c_26__n A_c[26] Net ipl_030_0_0__un3_n IPL_030_0_0_.un3 Net size_dma_1__n SIZE_DMA[1] Net a_26__n A[26] Net ipl_030_0_0__un1_n IPL_030_0_0_.un1 Net a_c_27__n A_c[27] Net ipl_030_0_0__un0_n IPL_030_0_0_.un0 Net un4_clk_cnt_n_1_1__n un4_clk_cnt_n_1[1] Net a_27__n A[27] Net as_030_000_sync_0_un3_n AS_030_000_SYNC_0.un3 Net un2_clk_cnt_p_1__n un2_clk_cnt_p[1] Net a_c_28__n A_c[28] Net as_030_000_sync_0_un1_n AS_030_000_SYNC_0.un1 Net clk_000_p_sync_0__n CLK_000_P_SYNC[0] Net a_28__n A[28] Net as_030_000_sync_0_un0_n AS_030_000_SYNC_0.un0 Net clk_000_p_sync_1__n CLK_000_P_SYNC[1] Net a_c_29__n A_c[29] Net as_000_int_0_un3_n AS_000_INT_0.un3 Net clk_000_p_sync_2__n CLK_000_P_SYNC[2] Net a_29__n A[29] Net as_000_int_0_un1_n AS_000_INT_0.un1 Net clk_000_p_sync_3__n CLK_000_P_SYNC[3] Net a_c_30__n A_c[30] Net as_000_int_0_un0_n AS_000_INT_0.un0 Net clk_000_p_sync_4__n CLK_000_P_SYNC[4] Net a_30__n A[30] Net ds_000_enable_0_un3_n DS_000_ENABLE_0.un3 Net clk_000_p_sync_5__n CLK_000_P_SYNC[5] Net a_c_31__n A_c[31] Net ds_000_enable_0_un1_n DS_000_ENABLE_0.un1 Net clk_000_p_sync_6__n CLK_000_P_SYNC[6] Net ds_000_enable_0_un0_n DS_000_ENABLE_0.un0 Net clk_000_p_sync_7__n CLK_000_P_SYNC[7] Net dsack1_int_0_un3_n DSACK1_INT_0.un3 Net clk_000_p_sync_8__n CLK_000_P_SYNC[8] Net dsack1_int_0_un1_n DSACK1_INT_0.un1 Net clk_000_n_sync_0__n CLK_000_N_SYNC[0] Net dsack1_int_0_un0_n DSACK1_INT_0.un0 Net clk_000_n_sync_1__n CLK_000_N_SYNC[1] Net bg_000_0_un3_n BG_000_0.un3 Net clk_000_n_sync_2__n CLK_000_N_SYNC[2] Net bg_000_0_un1_n BG_000_0.un1 Net clk_000_n_sync_3__n CLK_000_N_SYNC[3] Net bg_000_0_un0_n BG_000_0.un0 Net clk_000_n_sync_4__n CLK_000_N_SYNC[4] Net lds_000_int_0_un3_n LDS_000_INT_0.un3 Net clk_000_n_sync_5__n CLK_000_N_SYNC[5] Net lds_000_int_0_un1_n LDS_000_INT_0.un1 Net clk_000_n_sync_7__n CLK_000_N_SYNC[7] Net lds_000_int_0_un0_n LDS_000_INT_0.un0 Net clk_000_n_sync_8__n CLK_000_N_SYNC[8] Net uds_000_int_0_un3_n UDS_000_INT_0.un3 Net clk_000_n_sync_9__n CLK_000_N_SYNC[9] Net uds_000_int_0_un1_n UDS_000_INT_0.un1 Net clk_000_n_sync_10__n CLK_000_N_SYNC[10] Net uds_000_int_0_un0_n UDS_000_INT_0.un0 Net state_machine_un1_as_030_n state_machine.un1_as_030 Net bgack_030_int_0_un3_n BGACK_030_INT_0.un3 Net bgack_030_int_0_un1_n BGACK_030_INT_0.un1 Net state_machine_un8_bg_030_n state_machine.un8_bg_030 Net bgack_030_int_0_un0_n BGACK_030_INT_0.un0 Net sm_amiga_5__n SM_AMIGA[5] Net sm_amiga_3__n SM_AMIGA[3] Net sm_amiga_2__n SM_AMIGA[2] Net ipl_030_c_0__n IPL_030_c[0] Net state_machine_a0_dma_2_n state_machine.A0_DMA_2 Net ipl_030_0__n IPL_030[0] Net state_machine_size_dma_4_0__n state_machine.SIZE_DMA_4[0] Net ipl_030_c_1__n IPL_030_c[1] Net state_machine_size_dma_4_1__n state_machine.SIZE_DMA_4[1] Net ipl_030_1__n IPL_030[1] Net ipl_030_c_2__n IPL_030_c[2] Net ipl_c_0__n IPL_c[0] Net ipl_0__n IPL[0] Net ipl_c_1__n IPL_c[1] Net ipl_1__n IPL[1] Net ipl_c_2__n IPL_c[2] Net sm_amiga_ns_0__n SM_AMIGA_ns[0] Net sm_amiga_ns_1__n SM_AMIGA_ns[1] Net sm_amiga_ns_2__n SM_AMIGA_ns[2] Net sm_amiga_ns_3__n SM_AMIGA_ns[3] Net sm_amiga_ns_4__n SM_AMIGA_ns[4] Net fc_c_0__n FC_c[0] Net sm_amiga_ns_5__n SM_AMIGA_ns[5] Net fc_0__n FC[0] Net sm_amiga_ns_6__n SM_AMIGA_ns[6] Net fc_c_1__n FC_c[1] Net cpu_est_0__n cpu_est[0] Net cpu_est_1__n cpu_est[1] Net cpu_est_2__n cpu_est[2] Net cpu_est_3__n cpu_est[3] Net cpu_est_ns_e_0__n cpu_est_ns_e[0] Net cpu_est_ns_e_1__n cpu_est_ns_e[1] Net cpu_est_ns_e_2__n cpu_est_ns_e[2] Net cpu_est_ns_e_3__n cpu_est_ns_e[3] Net state_machine_un1_as_030_i_n state_machine.un1_as_030_i Net sm_amiga_ns_0_1__n SM_AMIGA_ns_0[1] Net state_machine_un28_as_030_n state_machine.un28_as_030 Net sm_amiga_ns_0_2__n SM_AMIGA_ns_0[2] Net state_machine_un5_clk_000_n_sync_n state_machine.un5_clk_000_n_sync Net state_machine_un9_clk_000_ne_n state_machine.un9_clk_000_ne Net state_machine_un6_bg_030_n state_machine.un6_bg_030 Net sm_amiga_ns_0_3__n SM_AMIGA_ns_0[3] Net state_machine_un11_clk_000_ne_n state_machine.un11_clk_000_ne Net state_machine_un15_clk_000_ne_n state_machine.un15_clk_000_ne Net sm_amiga_ns_0_5__n SM_AMIGA_ns_0[5] Net state_machine_un15_clk_000_ne_1_n state_machine.un15_clk_000_ne_1 Net sm_amiga_ns_0_6__n SM_AMIGA_ns_0[6] Net state_machine_rw_000_int_3_n state_machine.RW_000_INT_3 Net sm_amiga_i_5__n SM_AMIGA_i[5] Net cpu_est_ns_2__n cpu_est_ns[2] Net state_machine_un3_bgack_030_int_d_i_n state_machine.un3_bgack_030_int_d_i Net state_machine_un26_clk_000_pe_2_n state_machine.un26_clk_000_pe_2 Net state_machine_un26_clk_000_pe_n state_machine.un26_clk_000_pe Net sm_amiga_i_6__n SM_AMIGA_i[6] Net state_machine_un26_clk_000_pe_4_n state_machine.un26_clk_000_pe_4 Net state_machine_un5_clk_000_ne_n state_machine.un5_clk_000_ne Net sm_amiga_i_2__n SM_AMIGA_i[2] Net sm_amiga_i_4__n SM_AMIGA_i[4] Net cpu_est_ns_1__n cpu_est_ns[1] Net state_machine_un28_clk_000_pe_n state_machine.un28_clk_000_pe Net state_machine_clk_030_h_2_n state_machine.CLK_030_H_2 Net sm_amiga_ns_0_4__n SM_AMIGA_ns_0[4] Net sm_amiga_ns_0_0__n SM_AMIGA_ns_0[0] Net state_machine_un8_bgack_030_int_n state_machine.un8_bgack_030_int Net state_machine_un24_bgack_030_int_n state_machine.un24_bgack_030_int Net state_machine_un10_bgack_030_int_n state_machine.un10_bgack_030_int Net state_machine_un5_bgack_030_int_d_i_n state_machine.un5_bgack_030_int_d_i Net state_machine_un31_bgack_030_int_n state_machine.un31_bgack_030_int Net state_machine_clk_030_h_2_f1_n state_machine.CLK_030_H_2_f1 Net state_machine_clk_030_h_2_f1_0_n state_machine.CLK_030_H_2_f1_0 Net state_machine_size_dma_4_0_1__n state_machine.SIZE_DMA_4_0[1] Net state_machine_size_dma_4_0_0__n state_machine.SIZE_DMA_4_0[0] Net state_machine_un3_bgack_030_int_d_n state_machine.un3_bgack_030_int_d Net state_machine_un10_bgack_030_int_0_n state_machine.un10_bgack_030_int_0 Net state_machine_un26_clk_000_pe_i_n state_machine.un26_clk_000_pe_i Net state_machine_un5_clk_000_ne_i_n state_machine.un5_clk_000_ne_i Net state_machine_un28_clk_000_pe_0_n state_machine.un28_clk_000_pe_0 Net cpu_est_ns_0_1__n cpu_est_ns_0[1] Net state_machine_un26_clk_000_pe_2_i_n state_machine.un26_clk_000_pe_2_i Net cpu_est_ns_0_2__n cpu_est_ns_0[2] Net state_machine_rw_000_int_3_0_n state_machine.RW_000_INT_3_0 Net state_machine_un9_clk_000_ne_i_n state_machine.un9_clk_000_ne_i Net state_machine_un15_clk_000_ne_i_n state_machine.un15_clk_000_ne_i Net state_machine_un11_clk_000_ne_i_n state_machine.un11_clk_000_ne_i Net state_machine_un6_bg_030_i_n state_machine.un6_bg_030_i Net state_machine_un8_bg_030_0_n state_machine.un8_bg_030_0 Net state_machine_un4_bgack_000_0_n state_machine.un4_bgack_000_0 Net a_i_24__n A_i[24] Net a_i_25__n A_i[25] Net state_machine_un7_ds_030_i_n state_machine.un7_ds_030_i Net a_i_26__n A_i[26] Net a_i_27__n A_i[27] Net size_c_i_1__n SIZE_c_i[1] Net a_i_28__n A_i[28] Net cpu_est_ns_0_1_2__n cpu_est_ns_0_1[2] Net a_i_29__n A_i[29] Net sm_amiga_ns_0_1_0__n SM_AMIGA_ns_0_1[0] Net a_i_30__n A_i[30] Net sm_amiga_ns_0_2_0__n SM_AMIGA_ns_0_2[0] Net a_i_31__n A_i[31] Net sm_amiga_ns_0_3_0__n SM_AMIGA_ns_0_3[0] Net state_machine_un7_ds_030_i_1_n state_machine.un7_ds_030_i_1 Net sm_amiga_i_1__n SM_AMIGA_i[1] Net sm_amiga_i_3__n SM_AMIGA_i[3] Net sm_amiga_i_0__n SM_AMIGA_i[0] Net sm_amiga_i_7__n SM_AMIGA_i[7] Net state_machine_un28_as_030_1_n state_machine.un28_as_030_1 Net state_machine_un28_as_030_2_n state_machine.un28_as_030_2 Net state_machine_un24_bgack_030_int_i_n state_machine.un24_bgack_030_int_i Net state_machine_un15_clk_000_ne_1_0_n state_machine.un15_clk_000_ne_1_0 Net state_machine_un6_bg_030_1_n state_machine.un6_bg_030_1 Net state_machine_clk_000_p_sync_3_1_0__n state_machine.CLK_000_P_SYNC_3_1[0] Net state_machine_clk_000_p_sync_3_2_0__n state_machine.CLK_000_P_SYNC_3_2[0] Net state_machine_clk_000_n_sync_2_1_0__n state_machine.CLK_000_N_SYNC_2_1[0] Net state_machine_un8_bgack_030_int_i_n state_machine.un8_bgack_030_int_i Net state_machine_un31_bgack_030_int_i_n state_machine.un31_bgack_030_int_i Net state_machine_un26_clk_000_pe_1_n state_machine.un26_clk_000_pe_1 Net state_machine_un26_clk_000_pe_4_1_n state_machine.un26_clk_000_pe_4_1 Net state_machine_un5_clk_000_ne_1_n state_machine.un5_clk_000_ne_1 Net cpu_est_i_3__n cpu_est_i[3] Net state_machine_un5_clk_000_ne_2_n state_machine.un5_clk_000_ne_2 Net cpu_est_i_2__n cpu_est_i[2] Net cpu_est_ns_0_1_1__n cpu_est_ns_0_1[1] Net cpu_est_i_1__n cpu_est_i[1] Net cpu_est_ns_0_2_1__n cpu_est_ns_0_2[1] Net cpu_est_i_0__n cpu_est_i[0] Net state_machine_un15_clk_000_ne_1_i_n state_machine.un15_clk_000_ne_1_i End Section Type Name // ---------------------------------------------------------------------- Input A_31_ Input IPL_2_ Input FC_1_ Input nEXP_SPACE Input BERR Input BG_030 Input BGACK_000 Input CLK_030 Input CLK_000 Input CLK_OSZI Input VPA Input RST Input A_30_ Input A_29_ Input A_28_ Input A_27_ Input A_26_ Input A_25_ Input A_24_ Input A_23_ Input A_22_ Input A_21_ Input A_20_ Input A_19_ Input A_18_ Input A_17_ Input A_16_ Input IPL_1_ Input IPL_0_ Input FC_0_ Output IPL_030_2_ Output BG_000 Output BGACK_030 Output CLK_DIV_OUT Output CLK_EXP Output FPU_CS Output AVEC Output AVEC_EXP Output E Output VMA Output RESET Output AMIGA_BUS_ENABLE Output AMIGA_BUS_DATA_DIR Output AMIGA_BUS_ENABLE_LOW Output CIIN Output IPL_030_1_ Output IPL_030_0_ Bidi SIZE_1_ Bidi AS_030 Bidi AS_000 Bidi RW_000 Bidi DS_030 Bidi UDS_000 Bidi LDS_000 Bidi A0 Bidi DSACK1 Bidi DTACK Bidi RW Bidi SIZE_0_ End