Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May  6 2014
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
Product Version I-2014.03LC 
@N: MF248 |Running in 64-bit mode.
@W: MO111 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":497:16:497:18|Tristate driver CLK_DIV_OUT_1 on net CLK_DIV_OUT_1 has its enable tied to GND (module BUS68030) 
Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
original code -> new code
   000 -> 00000000
   001 -> 00000011
   010 -> 00000101
   011 -> 00001001
   100 -> 00010001
   101 -> 00100001
   110 -> 01000001
   111 -> 10000001
@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":190:4:190:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits 
@W: BN132 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:34:134:36|Removing instance CLK_000_P_SYNC[10],  because it is equivalent to instance CLK_000_PE
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Resource Usage Report

Simple gate primitives:
DFF             83 uses
BI_DIR          11 uses
IBUF            46 uses
OBUF            15 uses
BUFTH           3 uses
AND2            303 uses
INV             263 uses
XOR2            15 uses
OR2             28 uses


@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
I-2014.03LC 
Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed May 13 22:59:16 2015

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