Design Name = 68030_tk.tt4 ~~~~~~~~~~~~~~~~~~~~~~~~~~ ******************* * TIMING ANALYSIS * ******************* Timing Analysis KEY: One unit of delay time is equivalent to one pass through the Central Switch Matrix. .. Delay ( in this column ) not applicable to the indicated signal. TSU, Set-Up Time ( 0 for input-paired signals ), represents the number of switch matrix passes between an input pin and a register setup before clock. TSU is reported on the register. TCO, Clocked Output-to-Pin Time ( 0 for output-paired signals ), represents the number of switch matrix passes between a clocked register and an output pin. TCO is reported on the register. TPD, Propagation Delay Time ( calculated only for combinatorial eqns.), represents the number of switch matrix passes between an input pin and an output pin. TPD is reported on the output pin. TCR, Clocked Output-to-Register Time, represents the number of switch matrix passes between a clocked register and the register it drives ( before clock ). TCR is reported on the driving register. TSU TCO TPD TCR #passes #passes #passes #passes SIGNAL NAME min max min max min max min max E .. .. 0 0 .. .. 1 2 RN_E .. .. 0 0 .. .. 1 2 VMA .. .. 0 0 .. .. 1 2 RN_VMA .. .. 0 0 .. .. 1 2 cpu_est_0_ .. .. .. .. .. .. 1 2 cpu_est_1_ .. .. .. .. .. .. 1 2 inst_VPA_D 1 1 .. .. .. .. 1 2 inst_DTACK_D0 1 2 .. .. .. .. 1 2 cpu_est_2_ .. .. .. .. .. .. 1 2 inst_LDS_000_INT 1 1 1 1 .. .. 2 2 inst_DS_000_ENABLE 1 1 1 1 .. .. 2 2 inst_UDS_000_INT 1 1 1 1 .. .. 2 2 CIIN_0 .. .. .. .. 1 2 .. .. FPU_CS .. .. .. .. 1 1 .. .. DTACK .. .. .. .. 1 1 .. .. AMIGA_ADDR_ENABLE 1 1 0 1 .. .. 1 1 RN_AMIGA_ADDR_ENABLE 1 1 0 1 .. .. 1 1 AMIGA_BUS_DATA_DIR .. .. .. .. 1 1 .. .. CIIN .. .. .. .. 1 1 .. .. SIZE_1_ 1 1 0 0 .. .. .. .. IPL_030_2_ 1 1 0 0 .. .. 1 1 RN_IPL_030_2_ 1 1 0 0 .. .. 1 1 AS_030 1 1 0 0 .. .. 1 1 RN_AS_030 1 1 0 0 .. .. 1 1 AS_000 1 1 0 0 .. .. 1 1 RN_AS_000 1 1 0 0 .. .. 1 1 RW_000 1 1 0 0 .. .. 1 1 RN_RW_000 1 1 0 0 .. .. 1 1 DS_030 1 1 0 0 .. .. 1 1 RN_DS_030 1 1 0 0 .. .. 1 1 IPL_030_1_ 1 1 0 0 .. .. 1 1 RN_IPL_030_1_ 1 1 0 0 .. .. 1 1 IPL_030_0_ 1 1 0 0 .. .. 1 1 RN_IPL_030_0_ 1 1 0 0 .. .. 1 1 A0 1 1 0 0 .. .. .. .. BG_000 1 1 0 0 .. .. 1 1 RN_BG_000 1 1 0 0 .. .. 1 1 BGACK_030 1 1 0 1 .. .. 1 1 RN_BGACK_030 1 1 0 1 .. .. 1 1 DSACK1 1 1 0 0 .. .. 1 1 RN_DSACK1 1 1 0 0 .. .. 1 1 RW 1 1 0 0 .. .. 1 1 RN_RW 1 1 0 0 .. .. 1 1 SIZE_0_ 1 1 0 0 .. .. .. .. inst_AS_030_D0 1 1 1 1 .. .. 1 1 inst_DS_030_D0 1 1 .. .. .. .. 1 1 inst_AS_030_000_SYNC 1 1 .. .. .. .. 1 1 inst_BGACK_030_INT_D .. .. .. .. .. .. 1 1 inst_CLK_OUT_PRE_50 .. .. .. .. .. .. 1 1 inst_CLK_000_D1 .. .. .. .. .. .. 1 1 inst_CLK_000_D0 1 1 .. .. .. .. 1 1 SM_AMIGA_7_ 1 1 .. .. .. .. 1 1 inst_CLK_OUT_PRE .. .. .. .. .. .. 1 1 inst_CLK_000_PE .. .. .. .. .. .. 1 1 CLK_000_P_SYNC_9_ .. .. .. .. .. .. 1 1 inst_CLK_000_NE .. .. .. .. .. .. 1 1 CLK_000_N_SYNC_11_ .. .. .. .. .. .. 1 1 inst_CLK_000_NE_D0 .. .. .. .. .. .. 1 1 SM_AMIGA_6_ 1 1 .. .. .. .. 1 1 SM_AMIGA_4_ 1 1 .. .. .. .. 1 1 SM_AMIGA_0_ 1 1 .. .. .. .. 1 1 inst_CLK_030_H 1 1 .. .. .. .. 1 1 CLK_000_P_SYNC_0_ .. .. .. .. .. .. 1 1 CLK_000_P_SYNC_1_ .. .. .. .. .. .. 1 1 CLK_000_P_SYNC_2_ .. .. .. .. .. .. 1 1 CLK_000_P_SYNC_3_ .. .. .. .. .. .. 1 1 CLK_000_P_SYNC_4_ .. .. .. .. .. .. 1 1 CLK_000_P_SYNC_5_ .. .. .. .. .. .. 1 1 CLK_000_P_SYNC_6_ .. .. .. .. .. .. 1 1 CLK_000_P_SYNC_7_ .. .. .. .. .. .. 1 1 CLK_000_P_SYNC_8_ .. .. .. .. .. .. 1 1 CLK_000_N_SYNC_0_ .. .. .. .. .. .. 1 1 CLK_000_N_SYNC_1_ .. .. .. .. .. .. 1 1 CLK_000_N_SYNC_2_ .. .. .. .. .. .. 1 1 CLK_000_N_SYNC_3_ .. .. .. .. .. .. 1 1 CLK_000_N_SYNC_4_ .. .. .. .. .. .. 1 1 CLK_000_N_SYNC_5_ .. .. .. .. .. .. 1 1 CLK_000_N_SYNC_6_ .. .. .. .. .. .. 1 1 CLK_000_N_SYNC_7_ .. .. .. .. .. .. 1 1 CLK_000_N_SYNC_8_ .. .. .. .. .. .. 1 1 CLK_000_N_SYNC_9_ .. .. .. .. .. .. 1 1 CLK_000_N_SYNC_10_ .. .. .. .. .. .. 1 1 CLK_OUT_PRE_Dreg .. .. 1 1 .. .. 1 1 SM_AMIGA_1_ 1 1 .. .. .. .. 1 1 SM_AMIGA_5_ 1 1 .. .. .. .. 1 1 SM_AMIGA_3_ 1 1 .. .. .. .. 1 1 SM_AMIGA_2_ 1 1 .. .. .. .. 1 1 un14_ciin_0 .. .. .. .. 1 1 .. ..