@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral 
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":125:7:125:20|Signal clk_out_pre_33 is undriven 
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:7:126:22|Signal clk_out_pre_33_d is undriven 
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:8:127:17|Signal clk_pre_66 is undriven 
Post processing for work.bus68030.behavioral
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":143:32:143:34|Pruning register CLK_REF(1 downto 0)  
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":136:34:136:36|Pruning register CLK_000_D4  
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":135:34:135:36|Pruning register CLK_000_D3  
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:34:134:36|Pruning register CLK_000_D2  
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:35:129:37|Pruning register CLK_OUT_INT  
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:35:129:37|Pruning register CLK_OUT_NE  
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":123:38:123:40|Pruning register CLK_OUT_PRE_25  
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":122:36:122:38|Pruning register CLK_OUT_PRE_50_D  
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:61:138:75|Pruning bit 12 of CLK_000_N_SYNC(12 downto 0) -- not in use ... 
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:34:137:36|Pruning bits 12 to 10 of CLK_000_P_SYNC(12 downto 0) -- not in use ... 
@A: CL282 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":142:37:142:39|Feedback mux created for signal CLK_000_PE -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@A: CL282 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":140:34:140:36|Feedback mux created for signal CLK_000_NE -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":143:32:143:34|Trying to extract state machine for register SM_AMIGA
Extracted state machine for register SM_AMIGA
State machine has 8 reachable states with original encodings of:
   000
   001
   010
   011
   100
   101
   110
   111
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":142:37:142:39|Trying to extract state machine for register cpu_est