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|--------------------------------------------|
|- ispLEVER Fitter Report File -|
|- Version 2.0.00.17.20.15 -|
|- (c)Copyright, Lattice Semiconductor 2002 -|
|--------------------------------------------|
Project_Summary
~~~~~~~~~~~~~~~
Project Name : 68030_tk
Project Path : C:\Users\Matze\Documents\GitHub\68030tk\Logic
Project Fitted on : Wed Aug 24 22:17:54 2016
Device : M4A5-128/64
Package : 100TQFP
Speed : -10
Partnumber : M4A5-128/64-10VC
Source Format : Pure_VHDL
// Project '68030_tk' was Fitted Successfully! //
Compilation_Times
~~~~~~~~~~~~~~~~~
Reading/DRC 0 sec
Partition 0 sec
Place 0 sec
Route 0 sec
Jedec/Report generation 0 sec
--------
Fitter 00:00:00
Design_Summary
~~~~~~~~~~~~~~
Total Input Pins : 24
Total Output Pins : 19
Total Bidir I/O Pins : 18
Total Flip-Flops : 63
Total Product Terms : 222
Total Reserved Pins : 0
Total Reserved Blocks : 0
Device_Resource_Summary
~~~~~~~~~~~~~~~~~~~~~~~
Total
Available Used Available Utilization
Dedicated Pins
Input-Only Pins 2 2 0 --> 100%
Clock/Input Pins 4 4 0 --> 100%
I/O Pins 64 55 9 --> 85%
Logic Macrocells 128 90 38 --> 70%
Input Registers 64 0 64 --> 0%
Unusable Macrocells .. 1 ..
CSM Outputs/Total Block Inputs 264 206 58 --> 78%
Logical Product Terms 640 226 414 --> 35%
Product Term Clusters 128 54 74 --> 42%

Blocks_Resource_Summary
~~~~~~~~~~~~~~~~~~~~~~~
# of PT
I/O Inp Macrocells Macrocells logic clusters
Fanin Pins Reg Used Unusable available PTs available Pwr
---------------------------------------------------------------------------------
Maximum 33 8 8 -- -- 16 80 16 -
---------------------------------------------------------------------------------
Block A 25 8 0 9 0 7 19 11 Lo
Block B 22 8 0 13 1 2 42 8 Lo
Block C 20 7 0 13 0 3 40 7 Lo
Block D 24 8 0 13 0 3 27 8 Lo
Block E 33 4 0 9 0 7 11 14 Lo
Block F 25 5 0 10 0 6 40 6 Lo
Block G 24 7 0 13 0 3 29 6 Lo
Block H 33 8 0 9 0 7 18 13 Lo
---------------------------------------------------------------------------------
<Note> Four rightmost columns above reflect last status of the placement process.
<Note> Pwr (Power) : Hi = High
Lo = Low.

Optimizer_and_Fitter_Options
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Pin Assignment : Yes
Group Assignment : No
Pin Reservation : No (1)
Block Reservation : No
@Ignore_Project_Constraints :
Pin Assignments : No
Keep Block Assignment --
Keep Segment Assignment --
Group Assignments : No
Macrocell Assignment : No
Keep Block Assignment --
Keep Segment Assignment --
@Backannotate_Project_Constraints
Pin Assignments : No
Pin And Block Assignments : No
Pin, Macrocell and Block : No
@Timing_Constraints : No
@Global_Project_Optimization :
Balanced Partitioning : Yes
Spread Placement : Yes
Note :
Pack Design :
Balanced Partitioning = No
Spread Placement = No
Spread Design :
Balanced Partitioning = Yes
Spread Placement = Yes
@Logic_Synthesis :
Logic Reduction : Yes
Node Collapsing : Yes
D/T Synthesis : Yes
Clock Optimization : No
Input Register Optimization : Yes
XOR Synthesis : Yes
Max. P-Term for Collapsing : 20
Max. P-Term for Splitting : 20
Max. Equation Fanin : 32
Keep Xor : Yes
@Utilization_options
Max. % of macrocells used : 100
Max. % of block inputs used : 100
Max. % of segment lines used : ---
Max. % of macrocells used : ---
@Import_Source_Constraint_Option No
@Zero_Hold_Time Yes
@Pull_up Yes
@User_Signature #H0
@Output_Slew_Rate Default = Slow(2)
@Power Default = High(2)
Device Options:
<Note> 1 : Reserved unused I/Os can be independently driven to Low or High, and does not
follow the drive level set for the Global Configure Unused I/O Option.
<Note> 2 : For user-specified constraints on individual signals, refer to the Output,
Bidir and Burried Signal Lists.

Pinout_Listing
~~~~~~~~~~~~~~
| Pin |Blk |Assigned|
Pin No| Type |Pad |Pin | Signal name
---------------------------------------------------------------
1 | GND | | |
2 | JTAG | | |
3 | I_O | B7 | * |RESET
4 | I_O | B6 | * |AHIGH_31_
5 | I_O | B5 | * |AHIGH_30_
6 | I_O | B4 | * |AHIGH_29_
7 | I_O | B3 | * |IPL_030_1_
8 | I_O | B2 | * |IPL_030_0_
9 | I_O | B1 | * |IPL_030_2_
10 | I_O | B0 | * |CLK_EXP
11 | CkIn | | * |CLK_000
12 | Vcc | | |
13 | GND | | |
14 | CkIn | | * |nEXP_SPACE
15 | I_O | C0 | * |AHIGH_28_
16 | I_O | C1 | * |AHIGH_27_
17 | I_O | C2 | * |AHIGH_26_
18 | I_O | C3 | * |AHIGH_25_
19 | I_O | C4 | * |AHIGH_24_
20 | I_O | C5 | * |AMIGA_BUS_ENABLE_LOW
21 | I_O | C6 | * |BG_030
22 | I_O | C7 | |
23 | JTAG | | |
24 | JTAG | | |
25 | GND | | |
26 | GND | | |
27 | GND | | |
28 | I_O | D7 | * |BGACK_000
29 | I_O | D6 | * |BG_000
30 | I_O | D5 | * |DTACK
31 | I_O | D4 | * |LDS_000
32 | I_O | D3 | * |UDS_000
33 | I_O | D2 | * |AMIGA_ADDR_ENABLE
34 | I_O | D1 | * |AMIGA_BUS_ENABLE_HIGH
35 | I_O | D0 | * |VMA
36 | Inp | | * |VPA
37 | Vcc | | |
38 | GND | | |
39 | GND | | |
40 | Vcc | | |
41 | I_O | E0 | * |BERR
42 | I_O | E1 | * |AS_000
43 | I_O | E2 | |
44 | I_O | E3 | |
45 | I_O | E4 | |
46 | I_O | E5 | |
47 | I_O | E6 | * |CIIN
48 | I_O | E7 | * |AMIGA_BUS_DATA_DIR
49 | GND | | |
50 | GND | | |
51 | GND | | |
52 | JTAG | | |
53 | I_O | F7 | |
54 | I_O | F6 | |
55 | I_O | F5 | |
56 | I_O | F4 | * |IPL_1_
57 | I_O | F3 | * |FC_0_
58 | I_O | F2 | * |FC_1_
59 | I_O | F1 | * |A_DECODE_17_
60 | I_O | F0 | * |A_1_
61 | CkIn | | * |CLK_OSZI
62 | Vcc | | |
63 | GND | | |
64 | CkIn | | * |CLK_030
65 | I_O | G0 | * |CLK_DIV_OUT
66 | I_O | G1 | * |E
67 | I_O | G2 | * |IPL_0_
68 | I_O | G3 | * |IPL_2_
69 | I_O | G4 | * |A_0_
70 | I_O | G5 | * |SIZE_0_
71 | I_O | G6 | * |RW
72 | I_O | G7 | |
73 | JTAG | | |
74 | JTAG | | |
75 | GND | | |
76 | GND | | |
77 | GND | | |
78 | I_O | H7 | * |FPU_CS
79 | I_O | H6 | * |SIZE_1_
80 | I_O | H5 | * |RW_000
81 | I_O | H4 | * |DSACK1
82 | I_O | H3 | * |AS_030
83 | I_O | H2 | * |BGACK_030
84 | I_O | H1 | * |A_DECODE_22_
85 | I_O | H0 | * |A_DECODE_23_
86 | Inp | | * |RST
87 | Vcc | | |
88 | GND | | |
89 | GND | | |
90 | Vcc | | |
91 | I_O | A0 | * |FPU_SENSE
92 | I_O | A1 | * |AVEC
93 | I_O | A2 | * |A_DECODE_20_
94 | I_O | A3 | * |A_DECODE_21_
95 | I_O | A4 | * |A_DECODE_18_
96 | I_O | A5 | * |A_DECODE_16_
97 | I_O | A6 | * |A_DECODE_19_
98 | I_O | A7 | * |DS_030
99 | GND | | |
100 | GND | | |
---------------------------------------------------------------------------
<Note> Blk Pad : This notation refers to the Block I/O pad number in the device.
<Note> Assigned Pin : user or dedicated input assignment (E.g. Clock pins).
<Note> Pin Type :
CkIn : Dedicated input or clock pin
CLK : Dedicated clock pin
INP : Dedicated input pin
JTAG : JTAG Control and test pin
NC : No connected

Input_Signal_List
~~~~~~~~~~~~~~~~~
P R
Pin r e O Input
Pin Blk PTs Type e s E Fanout Pwr Slew Signal
----------------------------------------------------------------------
60 F . I/O --C---G- Low Slow A_1_
96 A . I/O A---E--H Low Slow A_DECODE_16_
59 F . I/O A---E--H Low Slow A_DECODE_17_
95 A . I/O A---E--H Low Slow A_DECODE_18_
97 A . I/O A---E--H Low Slow A_DECODE_19_
93 A . I/O ----E--- Low Slow A_DECODE_20_
94 A . I/O ----E--- Low Slow A_DECODE_21_
84 H . I/O ----E--- Low Slow A_DECODE_22_
85 H . I/O ----E--- Low Slow A_DECODE_23_
28 D . I/O ----E--H Low Slow BGACK_000
21 C . I/O ---D---- Low Slow BG_030
30 D . I/O --C----- Low Slow DTACK
57 F . I/O A---E--H Low Slow FC_0_
58 F . I/O A---E--H Low Slow FC_1_
91 A . I/O ----E--H Low Slow FPU_SENSE
67 G . I/O AB------ Low Slow IPL_0_
56 F . I/O -B------ Low Slow IPL_1_
68 G . I/O -B----G- Low Slow IPL_2_
11 . . Ck/I ----E--- - Slow CLK_000
14 . . Ck/I ABCDEFGH - Slow nEXP_SPACE
36 . . Ded A------- - Slow VPA
61 . . Ck/I ABCDEFGH - Slow CLK_OSZI
64 . . Ck/I --C----H - Slow CLK_030
86 . . Ded ABCD-FGH - Slow RST
----------------------------------------------------------------------
<Note> Power : Hi = High
MH = Medium High
ML = Medium Low
Lo = Low

Output_Signal_List
~~~~~~~~~~~~~~~~~~
P R
Pin r e O Output
Pin Blk PTs Type e s E Fanout Pwr Slew Signal
----------------------------------------------------------------------
33 D 1 COM -------- Low Fast AMIGA_ADDR_ENABLE
48 E 2 COM -------- Low Fast AMIGA_BUS_DATA_DIR
34 D 2 COM -------- Low Fast AMIGA_BUS_ENABLE_HIGH
20 C 1 COM -------- Low Fast AMIGA_BUS_ENABLE_LOW
92 A 1 COM -------- Low Fast AVEC
83 H 3 DFF -------- Low Fast BGACK_030
29 D 2 DFF -------- Low Fast BG_000
47 E 1 COM -------- Low Fast CIIN
65 G 1 DFF -------- Low Fast CLK_DIV_OUT
10 B 1 DFF -------- Low Fast CLK_EXP
81 H 5 DFF -------- Low Fast DSACK1
98 A 1 COM -------- Low Fast DS_030
66 G 2 COM -------- Low Fast E
78 H 1 COM -------- Low Fast FPU_CS
8 B 10 DFF -------- Low Fast IPL_030_0_
7 B 10 DFF -------- Low Fast IPL_030_1_
9 B 10 DFF -------- Low Fast IPL_030_2_
3 B 1 COM -------- Low Fast RESET
35 D 3 TFF -------- Low Fast VMA
----------------------------------------------------------------------
<Note> Power : Hi = High
MH = Medium High
ML = Medium Low
Lo = Low

Bidir_Signal_List
~~~~~~~~~~~~~~~~~
P R
Pin r e O Bidir
Pin Blk PTs Type e s E Fanout Pwr Slew Signal
----------------------------------------------------------------------
19 C 1 COM ----E--- Low Fast AHIGH_24_
18 C 1 COM ----E--- Low Fast AHIGH_25_
17 C 1 COM ----E--- Low Fast AHIGH_26_
16 C 1 COM ----E--- Low Fast AHIGH_27_
15 C 1 COM ----E--- Low Fast AHIGH_28_
6 B 1 COM ----E--- Low Fast AHIGH_29_
5 B 1 COM ----E--- Low Fast AHIGH_30_
4 B 1 COM ----E--- Low Fast AHIGH_31_
42 E 1 COM A-C-E--H Low Fast AS_000
82 H 1 COM ---DE--H Low Fast AS_030
69 G 3 DFF -B-D---- Low Fast A_0_
41 E 1 COM A----F-H Low Fast BERR
31 D 1 COM --C---G- Low Fast LDS_000
71 G 2 DFF -----F-H Low Fast RW
80 H 4 DFF --C-E-G- Low Fast RW_000
70 G 1 COM -B------ Low Fast SIZE_0_
79 H 1 COM -B------ Low Fast SIZE_1_
32 D 1 COM --C---G- Low Fast UDS_000
----------------------------------------------------------------------
<Note> Power : Hi = High
MH = Medium High
ML = Medium Low
Lo = Low

Buried_Signal_List
~~~~~~~~~~~~~~~~~~
P R
Pin r e O Node
#Mc Blk PTs Type e s E Fanout Pwr Slew Signal
----------------------------------------------------------------------
E9 E 2 COM ----E--- Low Slow CIIN_0
E8 E 1 DFF A-CD-FGH Low Slow CLK_000_D_0_
F6 F 1 DFF -------H Low Slow CLK_000_D_10_
H5 H 1 DFF A-CD-FGH Low Slow CLK_000_D_1_
H6 H 1 DFF ----E--- Low Slow CLK_000_D_2_
E2 E 1 DFF ---D---- Low Slow CLK_000_D_3_
D3 D 1 DFF -B------ Low Slow CLK_000_D_4_
B14 B 1 DFF -B------ Low Slow CLK_000_D_5_
B10 B 1 DFF ----E--- Low Slow CLK_000_D_6_
E13 E 1 DFF ----E--- Low Slow CLK_000_D_7_
E6 E 1 DFF -------H Low Slow CLK_000_D_8_
H13 H 1 DFF -----F-H Low Slow CLK_000_D_9_
C14 C 3 DFF --C----- Low Slow CYCLE_DMA_0_
C10 C 4 DFF --C----- Low Slow CYCLE_DMA_1_
A13 A 1 DFF -B------ Low Slow IPL_D0_0_
B3 B 1 DFF -B------ Low Slow IPL_D0_1_
G7 G 1 DFF -B------ Low Slow IPL_D0_2_
G8 G 3 DFF ------G- Low - RN_A_0_ --> A_0_
H4 H 3 DFF ABCDEFGH Low - RN_BGACK_030 --> BGACK_030
D1 D 2 DFF ---D---- Low - RN_BG_000 --> BG_000
H9 H 5 DFF -------H Low - RN_DSACK1 --> DSACK1
B5 B 10 DFF -B------ Low - RN_IPL_030_0_ --> IPL_030_0_
B9 B 10 DFF -B------ Low - RN_IPL_030_1_ --> IPL_030_1_
B4 B 10 DFF -B------ Low - RN_IPL_030_2_ --> IPL_030_2_
G0 G 2 DFF ------G- Low - RN_RW --> RW
H0 H 4 DFF -------H Low - RN_RW_000 --> RW_000
D0 D 3 TFF ---D-F-- Low - RN_VMA --> VMA
G10 G 4 DFF ------G- Low Slow RST_DLY_0_
G3 G 2 DFF ------G- Low Slow RST_DLY_1_
G14 G 2 DFF ------G- Low Slow RST_DLY_2_
G2 G 3 DFF ------GH Low Slow SIZE_DMA_0_
G13 G 3 DFF ------GH Low Slow SIZE_DMA_1_
F12 F 3 DFF -----F-H Low Slow SM_AMIGA_0_
F8 F 3 DFF -----F-H Low Slow SM_AMIGA_1_
F5 F 4 DFF -----F-- Low Slow SM_AMIGA_2_
F9 F 4 DFF -----F-- Low Slow SM_AMIGA_3_
F2 F 3 DFF -----F-- Low Slow SM_AMIGA_4_
F13 F 3 DFF -----F-- Low Slow SM_AMIGA_5_
A8 A 3 DFF AB-D-F-H Low Slow SM_AMIGA_6_
F4 F 13 DFF A------H Low Slow SM_AMIGA_i_7_
D10 D 3 DFF ---D-F-- Low Slow cpu_est_0_
D13 D 4 DFF ---D-FG- Low Slow cpu_est_1_
D6 D 1 DFF ---D-FG- Low Slow cpu_est_2_
D2 D 4 DFF ---D-FG- Low Slow cpu_est_3_
G6 G 2 DFF ---D--G- Low Slow inst_AMIGA_BUS_ENABLE_DMA_HIGH
C3 C 2 DFF --C----- Low Slow inst_AMIGA_BUS_ENABLE_DMA_LOW
C2 C 7 DFF --C----H Low Slow inst_AS_000_DMA
A5 A 2 DFF A---E--- Low Slow inst_AS_000_INT
A12 A 7 DFF A--D-F-- Low Slow inst_AS_030_000_SYNC
D9 D 1 DFF A--DEF-H Low Slow inst_AS_030_D0
F0 F 1 DFF A-C---G- Low Slow inst_BGACK_030_INT_D
C6 C 8 DFF --C----- Low Slow inst_CLK_030_H
A1 A 2 DFF AB------ Low Slow inst_CLK_OUT_PRE_25
A2 A 1 DFF A------- Low Slow inst_CLK_OUT_PRE_50
B13 B 1 DFF -B----GH Low Slow inst_CLK_OUT_PRE_D
C13 C 9 DFF A-C----- Low Slow inst_DS_000_DMA
F1 F 3 DFF ---D-F-- Low Slow inst_DS_000_ENABLE
C7 C 1 DFF -----F-- Low Slow inst_DTACK_D0
B6 B 3 DFF -B-D---- Low Slow inst_LDS_000_INT
G9 G 2 DFF ABCDE-GH Low Slow inst_RESET_OUT
D14 D 2 DFF ---D---- Low Slow inst_UDS_000_INT
A9 A 1 DFF ---D-F-- Low Slow inst_VPA_D
----------------------------------------------------------------------
<Note> Power : Hi = High
MH = Medium High
ML = Medium Low
Lo = Low

Signals_Fanout_List
~~~~~~~~~~~~~~~~~~~
Signal Source : Fanout List
-----------------------------------------------------------------------------
SIZE_1_{ I}:inst_LDS_000_INT{ B}
AHIGH_31_{ C}: CIIN{ E} CIIN_0{ E}
A_DECODE_23_{ I}: CIIN{ E} CIIN_0{ E}
IPL_2_{ H}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B}
: IPL_D0_2_{ G}
FC_1_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ A}
AS_030{ I}: AS_000{ E} BERR{ E} FPU_CS{ H}
: inst_AS_030_D0{ D}
SIZE_0_{ H}:inst_LDS_000_INT{ B}
AS_000{ F}: AS_030{ H} DS_030{ A}AMIGA_BUS_DATA_DIR{ E}
: BGACK_030{ H}inst_AS_000_DMA{ C}inst_DS_000_DMA{ C}
: CYCLE_DMA_0_{ C} CYCLE_DMA_1_{ C} inst_CLK_030_H{ C}
AHIGH_30_{ C}: CIIN{ E} CIIN_0{ E}
AHIGH_29_{ C}: CIIN{ E} CIIN_0{ E}
AHIGH_28_{ D}: CIIN{ E} CIIN_0{ E}
UDS_000{ E}: A_0_{ G}inst_AS_000_DMA{ C}inst_DS_000_DMA{ C}
: SIZE_DMA_0_{ G} SIZE_DMA_1_{ G} inst_CLK_030_H{ C}
AHIGH_27_{ D}: CIIN{ E} CIIN_0{ E}
LDS_000{ E}:inst_AS_000_DMA{ C}inst_DS_000_DMA{ C} SIZE_DMA_0_{ G}
: SIZE_DMA_1_{ G} inst_CLK_030_H{ C}
AHIGH_26_{ D}: CIIN{ E} CIIN_0{ E}
nEXP_SPACE{. }: SIZE_1_{ H} AHIGH_31_{ B} AS_030{ H}
: SIZE_0_{ G} AHIGH_30_{ B} AHIGH_29_{ B}
: DS_030{ A} AHIGH_28_{ C} AHIGH_27_{ C}
: AHIGH_26_{ C} AHIGH_25_{ C} AHIGH_24_{ C}
:AMIGA_BUS_DATA_DIR{ E} BG_000{ D} DSACK1{ H}
: A_0_{ G}inst_AS_030_000_SYNC{ A} SM_AMIGA_6_{ A}
: SM_AMIGA_i_7_{ F} CIIN_0{ E}
AHIGH_25_{ D}: CIIN{ E} CIIN_0{ E}
BERR{ F}: DSACK1{ H}inst_AS_000_INT{ A}inst_AS_030_000_SYNC{ A}
:inst_DS_000_ENABLE{ F} SM_AMIGA_6_{ A} SM_AMIGA_4_{ F}
: SM_AMIGA_0_{ F} SM_AMIGA_1_{ F} SM_AMIGA_5_{ F}
: SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} SM_AMIGA_i_7_{ F}
AHIGH_24_{ D}: CIIN{ E} CIIN_0{ E}
BG_030{ D}: BG_000{ D}
A_DECODE_22_{ I}: CIIN{ E} CIIN_0{ E}
A_DECODE_21_{ B}: CIIN{ E} CIIN_0{ E}
A_DECODE_20_{ B}: CIIN{ E} CIIN_0{ E}
BGACK_000{ E}: BERR{ E} FPU_CS{ H} BGACK_030{ H}
A_DECODE_19_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ A}
CLK_030{. }: DSACK1{ H}inst_AS_000_DMA{ C}inst_DS_000_DMA{ C}
: inst_CLK_030_H{ C}
A_DECODE_18_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ A}
CLK_000{. }: CLK_000_D_0_{ E}
A_DECODE_17_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ A}
A_DECODE_16_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ A}
FPU_SENSE{ B}: BERR{ E} FPU_CS{ H}
DTACK{ E}: inst_DTACK_D0{ C}
VPA{. }: inst_VPA_D{ A}
RST{. }: IPL_030_2_{ B} RW_000{ H} BG_000{ D}
: BGACK_030{ H} DSACK1{ H} VMA{ D}
: RW{ G} A_0_{ G} IPL_030_1_{ B}
: IPL_030_0_{ B}inst_AS_000_INT{ A}inst_AMIGA_BUS_ENABLE_DMA_LOW{ C}
: inst_AS_030_D0{ D}inst_AS_030_000_SYNC{ A}inst_BGACK_030_INT_D{ F}
:inst_AS_000_DMA{ C}inst_DS_000_DMA{ C} CYCLE_DMA_0_{ C}
: CYCLE_DMA_1_{ C} SIZE_DMA_0_{ G} SIZE_DMA_1_{ G}
: inst_VPA_D{ A}inst_UDS_000_INT{ D}inst_LDS_000_INT{ B}
: inst_DTACK_D0{ C} inst_RESET_OUT{ G} IPL_D0_0_{ A}
: IPL_D0_1_{ B} IPL_D0_2_{ G}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ G}
:inst_DS_000_ENABLE{ F} SM_AMIGA_6_{ A} SM_AMIGA_4_{ F}
: SM_AMIGA_0_{ F} RST_DLY_0_{ G} RST_DLY_1_{ G}
: RST_DLY_2_{ G} inst_CLK_030_H{ C} SM_AMIGA_1_{ F}
: SM_AMIGA_5_{ F} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F}
: SM_AMIGA_i_7_{ F}
IPL_1_{ G}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B}
: IPL_D0_1_{ B}
IPL_0_{ H}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B}
: IPL_D0_0_{ A}
FC_0_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ A}
A_1_{ G}:inst_AMIGA_BUS_ENABLE_DMA_LOW{ C}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ G}
RN_IPL_030_2_{ C}: IPL_030_2_{ B}
RW_000{ I}:AMIGA_BUS_DATA_DIR{ E} RW{ G}inst_DS_000_DMA{ C}
RN_RW_000{ I}: RW_000{ H}
RN_BG_000{ E}: BG_000{ D}
RN_BGACK_030{ I}: SIZE_1_{ H} AHIGH_31_{ B} AS_030{ H}
: SIZE_0_{ G} AS_000{ E} AHIGH_30_{ B}
: AHIGH_29_{ B} DS_030{ A} AHIGH_28_{ C}
: UDS_000{ D} AHIGH_27_{ C} LDS_000{ D}
: AHIGH_26_{ C} AHIGH_25_{ C} AHIGH_24_{ C}
:AMIGA_BUS_DATA_DIR{ E}AMIGA_BUS_ENABLE_LOW{ C}AMIGA_BUS_ENABLE_HIGH{ D}
: RW_000{ H} BGACK_030{ H} RW{ G}
: A_0_{ G}inst_AMIGA_BUS_ENABLE_DMA_LOW{ C}inst_AS_030_000_SYNC{ A}
:inst_BGACK_030_INT_D{ F}inst_AS_000_DMA{ C}inst_DS_000_DMA{ C}
: CYCLE_DMA_0_{ C} CYCLE_DMA_1_{ C} SIZE_DMA_0_{ G}
: SIZE_DMA_1_{ G}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ G} inst_CLK_030_H{ C}
RN_DSACK1{ I}: DSACK1{ H}
RN_VMA{ E}: VMA{ D} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F}
: SM_AMIGA_i_7_{ F}
RW{ H}: RW_000{ H}inst_DS_000_ENABLE{ F}
RN_RW{ H}: RW{ G}
A_0_{ H}:inst_UDS_000_INT{ D}inst_LDS_000_INT{ B}
RN_A_0_{ H}: A_0_{ G}
RN_IPL_030_1_{ C}: IPL_030_1_{ B}
RN_IPL_030_0_{ C}: IPL_030_0_{ B}
cpu_est_3_{ E}: E{ G} VMA{ D} cpu_est_3_{ D}
: cpu_est_1_{ D} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F}
: SM_AMIGA_i_7_{ F}
cpu_est_0_{ E}: VMA{ D} cpu_est_3_{ D} cpu_est_0_{ D}
: cpu_est_1_{ D} cpu_est_2_{ D} SM_AMIGA_3_{ F}
: SM_AMIGA_2_{ F} SM_AMIGA_i_7_{ F}
cpu_est_1_{ E}: E{ G} VMA{ D} cpu_est_3_{ D}
: cpu_est_1_{ D} cpu_est_2_{ D} SM_AMIGA_3_{ F}
: SM_AMIGA_2_{ F} SM_AMIGA_i_7_{ F}
cpu_est_2_{ E}: E{ G} VMA{ D} cpu_est_3_{ D}
: cpu_est_2_{ D} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F}
: SM_AMIGA_i_7_{ F}
inst_AS_000_INT{ B}: AS_000{ E}inst_AS_000_INT{ A}
inst_AMIGA_BUS_ENABLE_DMA_LOW{ D}:AMIGA_BUS_ENABLE_LOW{ C}inst_AMIGA_BUS_ENABLE_DMA_LOW{ C}
inst_AS_030_D0{ E}: CIIN{ E} BG_000{ D} DSACK1{ H}
:inst_AS_000_INT{ A}inst_AS_030_000_SYNC{ A}inst_DS_000_ENABLE{ F}
: CIIN_0{ E}
inst_AS_030_000_SYNC{ B}:AMIGA_BUS_ENABLE_HIGH{ D}inst_AS_030_000_SYNC{ A} SM_AMIGA_6_{ A}
: SM_AMIGA_i_7_{ F}
inst_BGACK_030_INT_D{ G}: RW{ G} A_0_{ G}inst_AMIGA_BUS_ENABLE_DMA_LOW{ C}
:inst_AS_030_000_SYNC{ A} SIZE_DMA_0_{ G} SIZE_DMA_1_{ G}
:inst_AMIGA_BUS_ENABLE_DMA_HIGH{ G}
inst_AS_000_DMA{ D}: AS_030{ H}inst_AS_000_DMA{ C}inst_DS_000_DMA{ C}
: inst_CLK_030_H{ C}
inst_DS_000_DMA{ D}: DS_030{ A}inst_DS_000_DMA{ C}
CYCLE_DMA_0_{ D}:inst_AS_000_DMA{ C}inst_DS_000_DMA{ C} CYCLE_DMA_0_{ C}
: CYCLE_DMA_1_{ C} inst_CLK_030_H{ C}
CYCLE_DMA_1_{ D}:inst_AS_000_DMA{ C}inst_DS_000_DMA{ C} CYCLE_DMA_1_{ C}
: inst_CLK_030_H{ C}
SIZE_DMA_0_{ H}: SIZE_1_{ H} SIZE_0_{ G} SIZE_DMA_0_{ G}
SIZE_DMA_1_{ H}: SIZE_1_{ H} SIZE_0_{ G} SIZE_DMA_1_{ G}
inst_VPA_D{ B}: VMA{ D} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F}
: SM_AMIGA_i_7_{ F}
inst_UDS_000_INT{ E}: UDS_000{ D}inst_UDS_000_INT{ D}
inst_LDS_000_INT{ C}: LDS_000{ D}inst_LDS_000_INT{ B}
inst_CLK_OUT_PRE_D{ C}: CLK_DIV_OUT{ G} CLK_EXP{ B} DSACK1{ H}
CLK_000_D_8_{ F}: DSACK1{ H} CLK_000_D_9_{ H}
CLK_000_D_9_{ I}: DSACK1{ H} CLK_000_D_10_{ F}
inst_DTACK_D0{ D}: SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} SM_AMIGA_i_7_{ F}
inst_RESET_OUT{ H}: AHIGH_31_{ B} AS_030{ H} AS_000{ E}
: AHIGH_30_{ B} AHIGH_29_{ B} DS_030{ A}
: AHIGH_28_{ C} UDS_000{ D} AHIGH_27_{ C}
: LDS_000{ D} AHIGH_26_{ C} AHIGH_25_{ C}
: AHIGH_24_{ C} RESET{ B} RW_000{ H}
: RW{ G} A_0_{ G} inst_RESET_OUT{ G}
CLK_000_D_1_{ I}: RW_000{ H} BGACK_030{ H} DSACK1{ H}
: VMA{ D} cpu_est_3_{ D} cpu_est_0_{ D}
: cpu_est_1_{ D} cpu_est_2_{ D}inst_AS_000_INT{ A}
: CYCLE_DMA_0_{ C} CYCLE_DMA_1_{ C} inst_RESET_OUT{ G}
: CLK_000_D_2_{ H}inst_DS_000_ENABLE{ F} SM_AMIGA_6_{ A}
: SM_AMIGA_4_{ F} SM_AMIGA_0_{ F} RST_DLY_0_{ G}
: RST_DLY_1_{ G} RST_DLY_2_{ G} SM_AMIGA_1_{ F}
: SM_AMIGA_5_{ F} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F}
: SM_AMIGA_i_7_{ F}
CLK_000_D_0_{ F}: RW_000{ H} BG_000{ D} BGACK_030{ H}
: DSACK1{ H} VMA{ D} cpu_est_3_{ D}
: cpu_est_0_{ D} cpu_est_1_{ D} cpu_est_2_{ D}
:inst_AS_000_INT{ A} CYCLE_DMA_0_{ C} CYCLE_DMA_1_{ C}
: inst_RESET_OUT{ G} CLK_000_D_1_{ H}inst_DS_000_ENABLE{ F}
: SM_AMIGA_6_{ A} SM_AMIGA_4_{ F} SM_AMIGA_0_{ F}
: RST_DLY_0_{ G} RST_DLY_1_{ G} RST_DLY_2_{ G}
: SM_AMIGA_1_{ F} SM_AMIGA_5_{ F} SM_AMIGA_3_{ F}
: SM_AMIGA_2_{ F} SM_AMIGA_i_7_{ F}
inst_CLK_OUT_PRE_50{ B}:inst_CLK_OUT_PRE_50{ A}inst_CLK_OUT_PRE_25{ A}
inst_CLK_OUT_PRE_25{ B}:inst_CLK_OUT_PRE_D{ B}inst_CLK_OUT_PRE_25{ A}
IPL_D0_0_{ B}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B}
IPL_D0_1_{ C}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B}
IPL_D0_2_{ H}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B}
CLK_000_D_2_{ I}: CLK_000_D_3_{ E}
CLK_000_D_3_{ F}: CLK_000_D_4_{ D}
CLK_000_D_4_{ E}: CLK_000_D_5_{ B}
CLK_000_D_5_{ C}: CLK_000_D_6_{ B}
CLK_000_D_6_{ C}: CLK_000_D_7_{ E}
CLK_000_D_7_{ F}: CLK_000_D_8_{ E}
CLK_000_D_10_{ G}: DSACK1{ H}
inst_AMIGA_BUS_ENABLE_DMA_HIGH{ H}:AMIGA_BUS_ENABLE_HIGH{ D}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ G}
inst_DS_000_ENABLE{ G}: UDS_000{ D} LDS_000{ D}inst_DS_000_ENABLE{ F}
SM_AMIGA_6_{ B}: RW_000{ H}inst_AS_000_INT{ A}inst_UDS_000_INT{ D}
:inst_LDS_000_INT{ B}inst_DS_000_ENABLE{ F} SM_AMIGA_6_{ A}
: SM_AMIGA_5_{ F} SM_AMIGA_i_7_{ F}
SM_AMIGA_4_{ G}:inst_DS_000_ENABLE{ F} SM_AMIGA_4_{ F} SM_AMIGA_3_{ F}
: SM_AMIGA_i_7_{ F}
SM_AMIGA_0_{ G}: RW_000{ H} SM_AMIGA_0_{ F} SM_AMIGA_i_7_{ F}
RST_DLY_0_{ H}: inst_RESET_OUT{ G} RST_DLY_0_{ G} RST_DLY_1_{ G}
: RST_DLY_2_{ G}
RST_DLY_1_{ H}: inst_RESET_OUT{ G} RST_DLY_0_{ G} RST_DLY_1_{ G}
: RST_DLY_2_{ G}
RST_DLY_2_{ H}: inst_RESET_OUT{ G} RST_DLY_0_{ G} RST_DLY_1_{ G}
: RST_DLY_2_{ G}
inst_CLK_030_H{ D}:inst_DS_000_DMA{ C} inst_CLK_030_H{ C}
SM_AMIGA_1_{ G}: DSACK1{ H} SM_AMIGA_0_{ F} SM_AMIGA_1_{ F}
: SM_AMIGA_i_7_{ F}
SM_AMIGA_5_{ G}: SM_AMIGA_4_{ F} SM_AMIGA_5_{ F} SM_AMIGA_i_7_{ F}
SM_AMIGA_3_{ G}: SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} SM_AMIGA_i_7_{ F}
SM_AMIGA_2_{ G}: SM_AMIGA_1_{ F} SM_AMIGA_2_{ F} SM_AMIGA_i_7_{ F}
SM_AMIGA_i_7_{ G}: RW_000{ H}inst_AS_030_000_SYNC{ A} SM_AMIGA_6_{ A}
CIIN_0{ F}: CIIN{ E}
-----------------------------------------------------------------------------
<Note> {.} : Indicates block location of signal

Set_Reset_Summary
~~~~~~~~~~~~~~~~~
Block A
block level set pt :
block level reset pt :
Equations :
| | |Block|Block| Signal
| Reg |Mode |Set |Reset| Name
+-----+-----+-----+-----+------------------------
| | | | | DS_030
| | | | | AVEC
| * | S | BS | BR | SM_AMIGA_6_
| * | S | BS | BR | inst_AS_030_000_SYNC
| * | S | BS | BR | inst_CLK_OUT_PRE_25
| * | S | BS | BR | inst_AS_000_INT
| * | S | BS | BR | inst_VPA_D
| * | S | BS | BR | IPL_D0_0_
| * | S | BS | BR | inst_CLK_OUT_PRE_50
| | | | | A_DECODE_19_
| | | | | A_DECODE_16_
| | | | | A_DECODE_18_
| | | | | FPU_SENSE
| | | | | A_DECODE_21_
| | | | | A_DECODE_20_
Block B
block level set pt :
block level reset pt :
Equations :
| | |Block|Block| Signal
| Reg |Mode |Set |Reset| Name
+-----+-----+-----+-----+------------------------
| | | | | AHIGH_29_
| | | | | AHIGH_30_
| | | | | AHIGH_31_
| * | S | BS | BR | IPL_030_2_
| * | S | BS | BR | IPL_030_0_
| * | S | BS | BR | IPL_030_1_
| * | S | BS | BR | CLK_EXP
| | | | | RESET
| * | S | BS | BR | inst_CLK_OUT_PRE_D
| * | S | BS | BR | inst_LDS_000_INT
| * | S | BS | BR | RN_IPL_030_0_
| * | S | BS | BR | RN_IPL_030_1_
| * | S | BS | BR | RN_IPL_030_2_
| * | S | BS | BR | CLK_000_D_6_
| * | S | BS | BR | CLK_000_D_5_
| * | S | BS | BR | IPL_D0_1_
Block C
block level set pt :
block level reset pt :
Equations :
| | |Block|Block| Signal
| Reg |Mode |Set |Reset| Name
+-----+-----+-----+-----+------------------------
| | | | | AHIGH_24_
| | | | | AHIGH_25_
| | | | | AHIGH_26_
| | | | | AHIGH_27_
| | | | | AHIGH_28_
| | | | | AMIGA_BUS_ENABLE_LOW
| * | S | BS | BR | inst_DS_000_DMA
| * | S | BS | BR | inst_AS_000_DMA
| * | S | BS | BR | inst_CLK_030_H
| * | S | BS | BR | CYCLE_DMA_1_
| * | S | BS | BR | CYCLE_DMA_0_
| * | S | BS | BR | inst_AMIGA_BUS_ENABLE_DMA_LOW
| * | S | BS | BR | inst_DTACK_D0
| | | | | BG_030
Block D
block level set pt :
block level reset pt :
Equations :
| | |Block|Block| Signal
| Reg |Mode |Set |Reset| Name
+-----+-----+-----+-----+------------------------
| | | | | UDS_000
| | | | | LDS_000
| * | S | BS | BR | VMA
| | | | | AMIGA_BUS_ENABLE_HIGH
| * | S | BS | BR | BG_000
| | | | | AMIGA_ADDR_ENABLE
| * | S | BS | BR | inst_AS_030_D0
| * | S | BS | BR | cpu_est_1_
| * | S | BS | BR | cpu_est_3_
| * | S | BS | BR | cpu_est_2_
| * | S | BS | BR | RN_VMA
| * | S | BS | BR | cpu_est_0_
| * | S | BS | BR | RN_BG_000
| * | S | BS | BR | inst_UDS_000_INT
| * | S | BS | BR | CLK_000_D_4_
| | | | | BGACK_000
| | | | | DTACK
Block E
block level set pt :
block level reset pt :
Equations :
| | |Block|Block| Signal
| Reg |Mode |Set |Reset| Name
+-----+-----+-----+-----+------------------------
| | | | | AS_000
| | | | | BERR
| | | | | AMIGA_BUS_DATA_DIR
| | | | | CIIN
| * | S | BS | BR | CLK_000_D_0_
| | | | | CIIN_0
| * | S | BS | BR | CLK_000_D_7_
| * | S | BS | BR | CLK_000_D_3_
| * | S | BS | BR | CLK_000_D_8_
Block F
block level set pt :
block level reset pt :
Equations :
| | |Block|Block| Signal
| Reg |Mode |Set |Reset| Name
+-----+-----+-----+-----+------------------------
| * | S | BS | BR | inst_BGACK_030_INT_D
| * | S | BS | BR | SM_AMIGA_i_7_
| * | S | BS | BR | SM_AMIGA_1_
| * | S | BS | BR | SM_AMIGA_0_
| * | S | BS | BR | inst_DS_000_ENABLE
| * | S | BS | BR | SM_AMIGA_2_
| * | S | BS | BR | SM_AMIGA_3_
| * | S | BS | BR | SM_AMIGA_5_
| * | S | BS | BR | SM_AMIGA_4_
| * | S | BS | BR | CLK_000_D_10_
| | | | | A_DECODE_17_
| | | | | FC_1_
| | | | | FC_0_
| | | | | A_1_
| | | | | IPL_1_
Block G
block level set pt :
block level reset pt :
Equations :
| | |Block|Block| Signal
| Reg |Mode |Set |Reset| Name
+-----+-----+-----+-----+------------------------
| * | S | BS | BR | A_0_
| * | S | BS | BR | RW
| | | | | SIZE_0_
| | | | | E
| * | S | BS | BR | CLK_DIV_OUT
| * | S | BS | BR | inst_RESET_OUT
| * | S | BS | BR | SIZE_DMA_1_
| * | S | BS | BR | SIZE_DMA_0_
| * | S | BS | BR | inst_AMIGA_BUS_ENABLE_DMA_HIGH
| * | S | BS | BR | RST_DLY_0_
| * | S | BS | BR | RN_A_0_
| * | S | BS | BR | RN_RW
| * | S | BS | BR | RST_DLY_2_
| * | S | BS | BR | RST_DLY_1_
| * | S | BS | BR | IPL_D0_2_
| | | | | IPL_2_
| | | | | IPL_0_
Block H
block level set pt :
block level reset pt :
Equations :
| | |Block|Block| Signal
| Reg |Mode |Set |Reset| Name
+-----+-----+-----+-----+------------------------
| * | S | BS | BR | RW_000
| | | | | AS_030
| | | | | SIZE_1_
| * | S | BS | BR | DSACK1
| * | S | BS | BR | BGACK_030
| | | | | FPU_CS
| * | S | BS | BR | RN_BGACK_030
| * | S | BS | BR | CLK_000_D_1_
| * | S | BS | BR | CLK_000_D_9_
| * | S | BS | BR | RN_DSACK1
| * | S | BS | BR | RN_RW_000
| * | S | BS | BR | CLK_000_D_2_
| | | | | A_DECODE_23_
| | | | | A_DECODE_22_
<Note> (S) means the macrocell is configured in synchronous mode
i.e. it uses the block-level set and reset pt.
(A) means the macrocell is configured in asynchronous mode
i.e. it can have its independant set or reset pt.
(BS) means the block-level set pt is selected.
(BR) means the block-level reset pt is selected.

BLOCK_A_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM Signal Source CSM Signal Source
------------------------------------ ------------------------------------
mx A0 IPL_0_ pin 67 mx A17 BERR pin 41
mx A1 FC_1_ pin 58 mx A18 ... ...
mx A2 inst_AS_000_INT mcell A5 mx A19 ... ...
mx A3 SM_AMIGA_6_ mcell A8 mx A20 RN_BGACK_030 mcell H4
mx A4 A_DECODE_18_ pin 95 mx A21 RST pin 86
mx A5 nEXP_SPACE pin 14 mx A22inst_CLK_OUT_PRE_50 mcell A2
mx A6 FC_0_ pin 57 mx A23 ... ...
mx A7 inst_AS_030_D0 mcell D9 mx A24 ... ...
mx A8 A_DECODE_17_ pin 59 mx A25inst_BGACK_030_INT_D mcell F0
mx A9inst_CLK_OUT_PRE_25 mcell A1 mx A26 AS_000 pin 42
mx A10 VPA pin 36 mx A27 inst_RESET_OUT mcell G9
mx A11 A_DECODE_16_ pin 96 mx A28 ... ...
mx A12 A_DECODE_19_ pin 97 mx A29 ... ...
mx A13 CLK_000_D_1_ mcell H5 mx A30 inst_DS_000_DMA mcell C13
mx A14 SM_AMIGA_i_7_ mcell F4 mx A31 ... ...
mx A15inst_AS_030_000_SYNC mcell A12 mx A32 ... ...
mx A16 CLK_000_D_0_ mcell E8
----------------------------------------------------------------------------
BLOCK_B_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM Signal Source CSM Signal Source
------------------------------------ ------------------------------------
mx B0 IPL_0_ pin 67 mx B17 ... ...
mx B1 ... ... mx B18 A_0_ pin 69
mx B2inst_LDS_000_INT mcell B6 mx B19 ... ...
mx B3 SM_AMIGA_6_ mcell A8 mx B20 CLK_000_D_5_ mcell B14
mx B4 IPL_2_ pin 68 mx B21 RST pin 86
mx B5 IPL_D0_1_ mcell B3 mx B22 ... ...
mx B6 SIZE_1_ pin 79 mx B23 RN_BGACK_030 mcell H4
mx B7 ... ... mx B24 ... ...
mx B8 IPL_D0_2_ mcell G7 mx B25 IPL_D0_0_ mcell A13
mx B9inst_CLK_OUT_PRE_25 mcell A1 mx B26 ... ...
mx B10inst_CLK_OUT_PRE_D mcell B13 mx B27 RN_IPL_030_2_ mcell B4
mx B11 ... ... mx B28 RN_IPL_030_0_ mcell B5
mx B12 inst_RESET_OUT mcell G9 mx B29 ... ...
mx B13 CLK_000_D_4_ mcell D3 mx B30 ... ...
mx B14 SIZE_0_ pin 70 mx B31 IPL_1_ pin 56
mx B15 nEXP_SPACE pin 14 mx B32 ... ...
mx B16 RN_IPL_030_1_ mcell B9
----------------------------------------------------------------------------
BLOCK_C_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM Signal Source CSM Signal Source
------------------------------------ ------------------------------------
mx C0 RST pin 86 mx C17 ... ...
mx C1 ... ... mx C18 CYCLE_DMA_1_ mcell C10
mx C2 inst_AS_000_DMA mcell C2 mx C19 ... ...
mx C3 A_1_ pin 60 mx C20 RN_BGACK_030 mcell H4
mx C4 CLK_030 pin 64 mx C21 ... ...
mx C5 nEXP_SPACE pin 14 mx C22 ... ...
mx C6 RW_000 pin 80 mx C23 ... ...
mx C7 CYCLE_DMA_0_ mcell C14 mx C24 LDS_000 pin 31
mx C8 UDS_000 pin 32 mx C25inst_BGACK_030_INT_D mcell F0
mx C9 inst_CLK_030_H mcell C6 mx C26 AS_000 pin 42
mx C10 inst_RESET_OUT mcell G9 mx C27 ... ...
mx C11 inst_DS_000_DMA mcell C13 mx C28 ... ...
mx C12inst_AMIGA_BUS_ENABLE_DMA_LOW mcell C3 mx C29 ... ...
mx C13 CLK_000_D_1_ mcell H5 mx C30 ... ...
mx C14 DTACK pin 30 mx C31 ... ...
mx C15 ... ... mx C32 ... ...
mx C16 CLK_000_D_0_ mcell E8
----------------------------------------------------------------------------
BLOCK_D_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM Signal Source CSM Signal Source
------------------------------------ ------------------------------------
mx D0 A_0_ pin 69 mx D17 RN_BG_000 mcell D1
mx D1 RN_VMA mcell D0 mx D18 SM_AMIGA_6_ mcell A8
mx D2 cpu_est_0_ mcell D10 mx D19 inst_VPA_D mcell A9
mx D3 CLK_000_D_3_ mcell E2 mx D20 RN_BGACK_030 mcell H4
mx D4 BG_030 pin 21 mx D21 cpu_est_1_ mcell D13
mx D5 nEXP_SPACE pin 14 mx D22 ... ...
mx D6 ... ... mx D23inst_AMIGA_BUS_ENABLE_DMA_HIGH mcell G6
mx D7 inst_AS_030_D0 mcell D9 mx D24 RST pin 86
mx D8 CLK_000_D_0_ mcell E8 mx D25 ... ...
mx D9inst_AS_030_000_SYNC mcell A12 mx D26 ... ...
mx D10inst_UDS_000_INT mcell D14 mx D27 ... ...
mx D11inst_LDS_000_INT mcell B6 mx D28 cpu_est_3_ mcell D2
mx D12 inst_RESET_OUT mcell G9 mx D29 ... ...
mx D13 CLK_000_D_1_ mcell H5 mx D30 ... ...
mx D14 ... ... mx D31 ... ...
mx D15inst_DS_000_ENABLE mcell F1 mx D32 AS_030 pin 82
mx D16 cpu_est_2_ mcell D6
----------------------------------------------------------------------------
BLOCK_E_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM Signal Source CSM Signal Source
------------------------------------ ------------------------------------
mx E0 RN_BGACK_030 mcell H4 mx E17 AHIGH_26_ pin 17
mx E1 AHIGH_31_ pin 4 mx E18 inst_AS_000_INT mcell A5
mx E2 CIIN_0 mcell E9 mx E19 AHIGH_30_ pin 5
mx E3 AHIGH_27_ pin 16 mx E20 AHIGH_24_ pin 19
mx E4 BGACK_000 pin 28 mx E21 nEXP_SPACE pin 14
mx E5 A_DECODE_21_ pin 94 mx E22 AHIGH_25_ pin 18
mx E6 FC_0_ pin 57 mx E23 CLK_000_D_7_ mcell E13
mx E7 AHIGH_28_ pin 15 mx E24 CLK_000_D_6_ mcell B10
mx E8 A_DECODE_17_ pin 59 mx E25 inst_AS_030_D0 mcell D9
mx E9 AS_030 pin 82 mx E26 A_DECODE_16_ pin 96
mx E10 inst_RESET_OUT mcell G9 mx E27 A_DECODE_19_ pin 97
mx E11 A_DECODE_22_ pin 84 mx E28 RW_000 pin 80
mx E12 FC_1_ pin 58 mx E29 A_DECODE_20_ pin 93
mx E13 AHIGH_29_ pin 6 mx E30 CLK_000_D_2_ mcell H6
mx E14 CLK_000 pin 11 mx E31 A_DECODE_18_ pin 95
mx E15 FPU_SENSE pin 91 mx E32 A_DECODE_23_ pin 85
mx E16 AS_000 pin 42
----------------------------------------------------------------------------
BLOCK_F_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM Signal Source CSM Signal Source
------------------------------------ ------------------------------------
mx F0 RST pin 86 mx F17 SM_AMIGA_0_ mcell F12
mx F1 SM_AMIGA_3_ mcell F9 mx F18 RN_VMA mcell D0
mx F2 inst_VPA_D mcell A9 mx F19 ... ...
mx F3 cpu_est_3_ mcell D2 mx F20 cpu_est_0_ mcell D10
mx F4 cpu_est_2_ mcell D6 mx F21 cpu_est_1_ mcell D13
mx F5 nEXP_SPACE pin 14 mx F22 ... ...
mx F6 inst_DTACK_D0 mcell C7 mx F23 RN_BGACK_030 mcell H4
mx F7 CLK_000_D_9_ mcell H13 mx F24inst_AS_030_000_SYNC mcell A12
mx F8 CLK_000_D_0_ mcell E8 mx F25 BERR pin 41
mx F9 SM_AMIGA_4_ mcell F2 mx F26 ... ...
mx F10inst_DS_000_ENABLE mcell F1 mx F27 ... ...
mx F11 RW pin 71 mx F28 ... ...
mx F12 inst_AS_030_D0 mcell D9 mx F29 ... ...
mx F13 CLK_000_D_1_ mcell H5 mx F30 SM_AMIGA_6_ mcell A8
mx F14 SM_AMIGA_2_ mcell F5 mx F31 ... ...
mx F15 SM_AMIGA_5_ mcell F13 mx F32 SM_AMIGA_1_ mcell F8
mx F16 ... ...
----------------------------------------------------------------------------
BLOCK_G_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM Signal Source CSM Signal Source
------------------------------------ ------------------------------------
mx G0 LDS_000 pin 31 mx G17 RN_RW mcell G0
mx G1 cpu_est_1_ mcell D13 mx G18 ... ...
mx G2 ... ... mx G19 ... ...
mx G3 A_1_ pin 60 mx G20 RN_BGACK_030 mcell H4
mx G4 cpu_est_2_ mcell D6 mx G21 RST pin 86
mx G5 RST_DLY_0_ mcell G10 mx G22 IPL_2_ pin 68
mx G6 RW_000 pin 80 mx G23inst_AMIGA_BUS_ENABLE_DMA_HIGH mcell G6
mx G7 ... ... mx G24 RST_DLY_1_ mcell G3
mx G8 UDS_000 pin 32 mx G25inst_BGACK_030_INT_D mcell F0
mx G9 SIZE_DMA_1_ mcell G13 mx G26 ... ...
mx G10inst_CLK_OUT_PRE_D mcell B13 mx G27 CLK_000_D_1_ mcell H5
mx G11 RST_DLY_2_ mcell G14 mx G28 cpu_est_3_ mcell D2
mx G12 inst_RESET_OUT mcell G9 mx G29 ... ...
mx G13 RN_A_0_ mcell G8 mx G30 ... ...
mx G14 ... ... mx G31 SIZE_DMA_0_ mcell G2
mx G15 nEXP_SPACE pin 14 mx G32 ... ...
mx G16 CLK_000_D_0_ mcell E8
----------------------------------------------------------------------------
BLOCK_H_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM Signal Source CSM Signal Source
------------------------------------ ------------------------------------
mx H0 CLK_000_D_8_ mcell E6 mx H17 SM_AMIGA_0_ mcell F12
mx H1 BERR pin 41 mx H18 BGACK_000 pin 28
mx H2 SM_AMIGA_1_ mcell F8 mx H19 CLK_000_D_10_ mcell F6
mx H3 SM_AMIGA_6_ mcell A8 mx H20 FC_1_ pin 58
mx H4 A_DECODE_18_ pin 95 mx H21 RST pin 86
mx H5 RN_DSACK1 mcell H9 mx H22 inst_AS_000_DMA mcell C2
mx H6 A_DECODE_16_ pin 96 mx H23 RN_BGACK_030 mcell H4
mx H7 CLK_000_D_9_ mcell H13 mx H24 FC_0_ pin 57
mx H8 A_DECODE_17_ pin 59 mx H25 inst_AS_030_D0 mcell D9
mx H9 SIZE_DMA_1_ mcell G13 mx H26 AS_000 pin 42
mx H10inst_CLK_OUT_PRE_D mcell B13 mx H27 A_DECODE_19_ pin 97
mx H11 RW pin 71 mx H28 CLK_030 pin 64
mx H12 inst_RESET_OUT mcell G9 mx H29 FPU_SENSE pin 91
mx H13 CLK_000_D_1_ mcell H5 mx H30 RN_RW_000 mcell H0
mx H14 SM_AMIGA_i_7_ mcell F4 mx H31 SIZE_DMA_0_ mcell G2
mx H15 nEXP_SPACE pin 14 mx H32 AS_030 pin 82
mx H16 CLK_000_D_0_ mcell E8
----------------------------------------------------------------------------
<Note> CSM indicates the mux inputs from the Central Switch Matrix.
<Note> Source indicates where the signal comes from (pin or macrocell).

PostFit_Equations
~~~~~~~~~~~~~~~~~
P-Terms Fan-in Fan-out Type Name (attributes)
--------- ------ ------- ---- -----------------
1 2 1 Pin SIZE_1_
1 2 1 Pin SIZE_1_.OE
0 0 1 Pin AHIGH_31_
1 3 1 Pin AHIGH_31_.OE
1 2 1 Pin AS_030-
1 3 1 Pin AS_030.OE
1 2 1 Pin SIZE_0_
1 2 1 Pin SIZE_0_.OE
1 2 1 Pin AS_000-
1 2 1 Pin AS_000.OE
0 0 1 Pin AHIGH_30_
1 3 1 Pin AHIGH_30_.OE
0 0 1 Pin AHIGH_29_
1 3 1 Pin AHIGH_29_.OE
1 2 1 Pin DS_030-
1 3 1 Pin DS_030.OE
0 0 1 Pin AHIGH_28_
1 3 1 Pin AHIGH_28_.OE
1 2 1 Pin UDS_000-
1 2 1 Pin UDS_000.OE
0 0 1 Pin AHIGH_27_
1 3 1 Pin AHIGH_27_.OE
1 2 1 Pin LDS_000-
1 2 1 Pin LDS_000.OE
0 0 1 Pin AHIGH_26_
1 3 1 Pin AHIGH_26_.OE
0 0 1 Pin AHIGH_25_
1 3 1 Pin AHIGH_25_.OE
0 0 1 Pin BERR
1 9 1 Pin BERR.OE
0 0 1 Pin AHIGH_24_
1 3 1 Pin AHIGH_24_.OE
1 1 1 Pin CLK_DIV_OUT.D
1 1 1 Pin CLK_DIV_OUT.C
1 9 1 Pin FPU_CS-
1 0 1 Pin AVEC
2 3 1 Pin E
0 0 1 Pin RESET
1 1 1 Pin RESET.OE
0 0 1 Pin AMIGA_ADDR_ENABLE
2 4 1 Pin AMIGA_BUS_DATA_DIR
1 2 1 Pin AMIGA_BUS_ENABLE_LOW-
2 3 1 Pin AMIGA_BUS_ENABLE_HIGH
1 13 1 Pin CIIN
1 1 1 Pin CIIN.OE
10 8 1 Pin IPL_030_2_.D-
1 1 1 Pin IPL_030_2_.C
1 2 1 Pin RW_000.OE
4 8 1 Pin RW_000.D-
1 1 1 Pin RW_000.C
2 6 1 Pin BG_000.D-
1 1 1 Pin BG_000.C
3 6 1 Pin BGACK_030.D
1 1 1 Pin BGACK_030.C
1 1 1 Pin CLK_EXP.D
1 1 1 Pin CLK_EXP.C
1 1 1 Pin DSACK1.OE
5 12 1 Pin DSACK1.D-
1 1 1 Pin DSACK1.C
3 9 1 Pin VMA.T
1 1 1 Pin VMA.C
1 2 1 Pin RW.OE
2 5 1 Pin RW.D-
1 1 1 Pin RW.C
1 3 1 Pin A_0_.OE
3 5 1 Pin A_0_.D
1 1 1 Pin A_0_.C
10 8 1 Pin IPL_030_1_.D-
1 1 1 Pin IPL_030_1_.C
10 8 1 Pin IPL_030_0_.D-
1 1 1 Pin IPL_030_0_.C
4 6 1 Node cpu_est_3_.D
1 1 1 Node cpu_est_3_.C
3 3 1 Node cpu_est_0_.D
1 1 1 Node cpu_est_0_.C
4 5 1 Node cpu_est_1_.D
1 1 1 Node cpu_est_1_.C
1 4 1 NodeX1 cpu_est_2_.D.X1
1 1 1 NodeX2 cpu_est_2_.D.X2
1 1 1 Node cpu_est_2_.C
2 7 1 Node inst_AS_000_INT.D-
1 1 1 Node inst_AS_000_INT.C
2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.D-
1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.C
1 2 1 Node inst_AS_030_D0.D-
1 1 1 Node inst_AS_030_D0.C
7 14 1 Node inst_AS_030_000_SYNC.D-
1 1 1 Node inst_AS_030_000_SYNC.C
1 2 1 Node inst_BGACK_030_INT_D.D-
1 1 1 Node inst_BGACK_030_INT_D.C
7 9 1 Node inst_AS_000_DMA.D
1 1 1 Node inst_AS_000_DMA.C
9 12 1 Node inst_DS_000_DMA.D
1 1 1 Node inst_DS_000_DMA.C
3 6 1 Node CYCLE_DMA_0_.D
1 1 1 Node CYCLE_DMA_0_.C
4 7 1 Node CYCLE_DMA_1_.D
1 1 1 Node CYCLE_DMA_1_.C
3 6 1 Node SIZE_DMA_0_.D-
1 1 1 Node SIZE_DMA_0_.C
3 6 1 Node SIZE_DMA_1_.D
1 1 1 Node SIZE_DMA_1_.C
1 2 1 Node inst_VPA_D.D-
1 1 1 Node inst_VPA_D.C
2 4 1 Node inst_UDS_000_INT.D-
1 1 1 Node inst_UDS_000_INT.C
3 6 1 Node inst_LDS_000_INT.D
1 1 1 Node inst_LDS_000_INT.C
1 1 1 Node inst_CLK_OUT_PRE_D.D
1 1 1 Node inst_CLK_OUT_PRE_D.C
1 1 1 Node CLK_000_D_8_.D
1 1 1 Node CLK_000_D_8_.C
1 1 1 Node CLK_000_D_9_.D
1 1 1 Node CLK_000_D_9_.C
1 2 1 Node inst_DTACK_D0.D-
1 1 1 Node inst_DTACK_D0.C
2 7 1 Node inst_RESET_OUT.D
1 1 1 Node inst_RESET_OUT.C
1 1 1 Node CLK_000_D_1_.D
1 1 1 Node CLK_000_D_1_.C
1 1 1 Node CLK_000_D_0_.D
1 1 1 Node CLK_000_D_0_.C
1 1 1 Node inst_CLK_OUT_PRE_50.D
1 1 1 Node inst_CLK_OUT_PRE_50.C
2 2 1 Node inst_CLK_OUT_PRE_25.D
1 1 1 Node inst_CLK_OUT_PRE_25.C
1 2 1 Node IPL_D0_0_.D-
1 1 1 Node IPL_D0_0_.C
1 2 1 Node IPL_D0_1_.D-
1 1 1 Node IPL_D0_1_.C
1 2 1 Node IPL_D0_2_.D-
1 1 1 Node IPL_D0_2_.C
1 1 1 Node CLK_000_D_2_.D
1 1 1 Node CLK_000_D_2_.C
1 1 1 Node CLK_000_D_3_.D
1 1 1 Node CLK_000_D_3_.C
1 1 1 Node CLK_000_D_4_.D
1 1 1 Node CLK_000_D_4_.C
1 1 1 Node CLK_000_D_5_.D
1 1 1 Node CLK_000_D_5_.C
1 1 1 Node CLK_000_D_6_.D
1 1 1 Node CLK_000_D_6_.C
1 1 1 Node CLK_000_D_7_.D
1 1 1 Node CLK_000_D_7_.C
1 1 1 Node CLK_000_D_10_.D
1 1 1 Node CLK_000_D_10_.C
2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.D-
1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.C
3 9 1 Node inst_DS_000_ENABLE.D
1 1 1 Node inst_DS_000_ENABLE.C
3 8 1 Node SM_AMIGA_6_.D
1 1 1 Node SM_AMIGA_6_.C
3 6 1 Node SM_AMIGA_4_.D
1 1 1 Node SM_AMIGA_4_.C
3 6 1 Node SM_AMIGA_0_.D
1 1 1 Node SM_AMIGA_0_.C
4 6 1 Node RST_DLY_0_.D
1 1 1 Node RST_DLY_0_.C
2 6 1 NodeX1 RST_DLY_1_.D.X1
1 2 1 NodeX2 RST_DLY_1_.D.X2
1 1 1 Node RST_DLY_1_.C
2 6 1 Node RST_DLY_2_.D
1 1 1 Node RST_DLY_2_.C
8 10 1 Node inst_CLK_030_H.D
1 1 1 Node inst_CLK_030_H.C
3 6 1 Node SM_AMIGA_1_.D
1 1 1 Node SM_AMIGA_1_.C
3 6 1 Node SM_AMIGA_5_.D
1 1 1 Node SM_AMIGA_5_.C
4 13 1 NodeX1 SM_AMIGA_3_.D.X1
1 3 1 NodeX2 SM_AMIGA_3_.D.X2
1 1 1 Node SM_AMIGA_3_.C
4 13 1 Node SM_AMIGA_2_.D
1 1 1 Node SM_AMIGA_2_.C
13 20 1 NodeX1 SM_AMIGA_i_7_.D.X1
1 2 1 NodeX2 SM_AMIGA_i_7_.D.X2
1 1 1 Node SM_AMIGA_i_7_.C
2 14 1 Node CIIN_0
=========
300 P-Term Total: 300
Total Pins: 61
Total Nodes: 52
Average P-Term/Output: 2
Equations:
SIZE_1_ = (!SIZE_DMA_0_.Q & SIZE_DMA_1_.Q);
SIZE_1_.OE = (!nEXP_SPACE & !BGACK_030.Q);
AHIGH_31_ = (0);
AHIGH_31_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
!AS_030 = (!inst_AS_000_DMA.Q & !AS_000.PIN);
AS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
SIZE_0_ = (SIZE_DMA_0_.Q & !SIZE_DMA_1_.Q);
SIZE_0_.OE = (!nEXP_SPACE & !BGACK_030.Q);
!AS_000 = (!inst_AS_000_INT.Q & !AS_030.PIN);
AS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q);
AHIGH_30_ = (0);
AHIGH_30_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
AHIGH_29_ = (0);
AHIGH_29_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
!DS_030 = (!inst_DS_000_DMA.Q & !AS_000.PIN);
DS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
AHIGH_28_ = (0);
AHIGH_28_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
!UDS_000 = (!inst_UDS_000_INT.Q & inst_DS_000_ENABLE.Q);
UDS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q);
AHIGH_27_ = (0);
AHIGH_27_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
!LDS_000 = (!inst_LDS_000_INT.Q & inst_DS_000_ENABLE.Q);
LDS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q);
AHIGH_26_ = (0);
AHIGH_26_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
AHIGH_25_ = (0);
AHIGH_25_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
BERR = (0);
BERR.OE = (FC_1_ & BGACK_000 & FPU_SENSE & !A_DECODE_19_ & !A_DECODE_18_ & A_DECODE_17_ & !A_DECODE_16_ & FC_0_ & !AS_030.PIN);
AHIGH_24_ = (0);
AHIGH_24_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
CLK_DIV_OUT.D = (inst_CLK_OUT_PRE_D.Q);
CLK_DIV_OUT.C = (CLK_OSZI);
!FPU_CS = (FC_1_ & BGACK_000 & !FPU_SENSE & !A_DECODE_19_ & !A_DECODE_18_ & A_DECODE_17_ & !A_DECODE_16_ & FC_0_ & !AS_030.PIN);
AVEC = (1);
E = (!cpu_est_3_.Q & cpu_est_1_.Q & cpu_est_2_.Q
# cpu_est_3_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q);
RESET = (0);
RESET.OE = (!inst_RESET_OUT.Q);
AMIGA_ADDR_ENABLE = (0);
AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW_000.PIN
# !nEXP_SPACE & !BGACK_030.Q & !AS_000.PIN & RW_000.PIN);
!AMIGA_BUS_ENABLE_LOW = (!BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_LOW.Q);
AMIGA_BUS_ENABLE_HIGH = (BGACK_030.Q & inst_AS_030_000_SYNC.Q
# !BGACK_030.Q & inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q);
CIIN = (A_DECODE_23_ & A_DECODE_22_ & A_DECODE_21_ & A_DECODE_20_ & !inst_AS_030_D0.Q & !AHIGH_24_.PIN & !AHIGH_25_.PIN & !AHIGH_26_.PIN & !AHIGH_27_.PIN & !AHIGH_28_.PIN & !AHIGH_29_.PIN & !AHIGH_30_.PIN & !AHIGH_31_.PIN);
CIIN.OE = (CIIN_0);
!IPL_030_2_.D = (!IPL_2_ & RST & !IPL_030_2_.Q
# RST & !IPL_D0_2_.Q & !IPL_030_2_.Q
# RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_2_.Q
# RST & IPL_0_ & !IPL_D0_0_.Q & !IPL_030_2_.Q
# RST & !IPL_1_ & IPL_D0_1_.Q & !IPL_030_2_.Q
# RST & IPL_1_ & !IPL_D0_1_.Q & !IPL_030_2_.Q
# !IPL_2_ & RST & IPL_1_ & IPL_0_ & IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q
# !IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q
# !IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q
# !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q);
IPL_030_2_.C = (CLK_OSZI);
RW_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q);
!RW_000.D = (RST & CLK_000_D_1_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q
# RST & !CLK_000_D_0_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q
# RST & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q
# RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & SM_AMIGA_i_7_.Q & !RW.PIN);
RW_000.C = (CLK_OSZI);
!BG_000.D = (!BG_030 & RST & !BG_000.Q
# nEXP_SPACE & !BG_030 & RST & inst_AS_030_D0.Q & CLK_000_D_0_.Q);
BG_000.C = (CLK_OSZI);
BGACK_030.D = (!RST
# BGACK_000 & BGACK_030.Q
# BGACK_000 & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & AS_000.PIN);
BGACK_030.C = (CLK_OSZI);
CLK_EXP.D = (inst_CLK_OUT_PRE_D.Q);
CLK_EXP.C = (CLK_OSZI);
DSACK1.OE = (nEXP_SPACE);
!DSACK1.D = (RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_1_.Q
# RST & !CLK_000_D_9_.Q & CLK_000_D_10_.Q & SM_AMIGA_1_.Q
# RST & !inst_AS_030_D0.Q & !DSACK1.Q & BERR.PIN
# !CLK_030 & RST & !CLK_000_D_8_.Q & CLK_000_D_9_.Q & SM_AMIGA_1_.Q
# RST & inst_CLK_OUT_PRE_D.Q & !CLK_000_D_8_.Q & CLK_000_D_9_.Q & SM_AMIGA_1_.Q);
DSACK1.C = (CLK_OSZI);
VMA.T = (!RST & !VMA.Q
# !VMA.Q & !cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !CLK_000_D_1_.Q & CLK_000_D_0_.Q
# RST & VMA.Q & !cpu_est_3_.Q & cpu_est_0_.Q & cpu_est_1_.Q & !cpu_est_2_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q);
VMA.C = (CLK_OSZI);
RW.OE = (!BGACK_030.Q & inst_RESET_OUT.Q);
!RW.D = (RST & !BGACK_030.Q & !RW_000.PIN
# RST & BGACK_030.Q & inst_BGACK_030_INT_D.Q & !RW.Q);
RW.C = (CLK_OSZI);
A_0_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
A_0_.D = (!RST
# !BGACK_030.Q & UDS_000.PIN
# BGACK_030.Q & inst_BGACK_030_INT_D.Q & A_0_.Q);
A_0_.C = (CLK_OSZI);
!IPL_030_1_.D = (RST & !IPL_1_ & !IPL_030_1_.Q
# RST & !IPL_D0_1_.Q & !IPL_030_1_.Q
# RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_1_.Q
# RST & IPL_0_ & !IPL_D0_0_.Q & !IPL_030_1_.Q
# !IPL_2_ & RST & IPL_D0_2_.Q & !IPL_030_1_.Q
# IPL_2_ & RST & !IPL_D0_2_.Q & !IPL_030_1_.Q
# IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q
# IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q
# !IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q
# !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q);
IPL_030_1_.C = (CLK_OSZI);
!IPL_030_0_.D = (RST & !IPL_0_ & !IPL_030_0_.Q
# RST & !IPL_D0_0_.Q & !IPL_030_0_.Q
# RST & !IPL_1_ & IPL_D0_1_.Q & !IPL_030_0_.Q
# RST & IPL_1_ & !IPL_D0_1_.Q & !IPL_030_0_.Q
# !IPL_2_ & RST & IPL_D0_2_.Q & !IPL_030_0_.Q
# IPL_2_ & RST & !IPL_D0_2_.Q & !IPL_030_0_.Q
# IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & IPL_D0_2_.Q
# IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q
# !IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q
# !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q);
IPL_030_0_.C = (CLK_OSZI);
cpu_est_3_.D = (cpu_est_3_.Q & !CLK_000_D_1_.Q
# cpu_est_3_.Q & CLK_000_D_0_.Q
# cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_2_.Q
# cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q);
cpu_est_3_.C = (CLK_OSZI);
cpu_est_0_.D = (cpu_est_0_.Q & !CLK_000_D_1_.Q
# cpu_est_0_.Q & CLK_000_D_0_.Q
# !cpu_est_0_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q);
cpu_est_0_.C = (CLK_OSZI);
cpu_est_1_.D = (!cpu_est_0_.Q & cpu_est_1_.Q
# cpu_est_1_.Q & !CLK_000_D_1_.Q
# cpu_est_1_.Q & CLK_000_D_0_.Q
# !cpu_est_3_.Q & cpu_est_0_.Q & !cpu_est_1_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q);
cpu_est_1_.C = (CLK_OSZI);
cpu_est_2_.D.X1 = (cpu_est_0_.Q & cpu_est_1_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q);
cpu_est_2_.D.X2 = (cpu_est_2_.Q);
cpu_est_2_.C = (CLK_OSZI);
!inst_AS_000_INT.D = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q
# RST & !inst_AS_000_INT.Q & !inst_AS_030_D0.Q & BERR.PIN);
inst_AS_000_INT.C = (CLK_OSZI);
!inst_AMIGA_BUS_ENABLE_DMA_LOW.D = (RST & A_1_ & !BGACK_030.Q
# RST & BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_LOW.Q & inst_BGACK_030_INT_D.Q);
inst_AMIGA_BUS_ENABLE_DMA_LOW.C = (CLK_OSZI);
!inst_AS_030_D0.D = (RST & !AS_030.PIN);
inst_AS_030_D0.C = (CLK_OSZI);
!inst_AS_030_000_SYNC.D = (RST & !inst_AS_030_D0.Q & !inst_AS_030_000_SYNC.Q & BERR.PIN
# !FC_1_ & nEXP_SPACE & RST & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
# nEXP_SPACE & RST & A_DECODE_19_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
# nEXP_SPACE & RST & A_DECODE_18_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
# nEXP_SPACE & RST & !A_DECODE_17_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
# nEXP_SPACE & RST & A_DECODE_16_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
# nEXP_SPACE & RST & !FC_0_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN);
inst_AS_030_000_SYNC.C = (CLK_OSZI);
!inst_BGACK_030_INT_D.D = (RST & !BGACK_030.Q);
inst_BGACK_030_INT_D.C = (CLK_OSZI);
inst_AS_000_DMA.D = (!RST
# BGACK_030.Q
# AS_000.PIN
# !CLK_030 & inst_AS_000_DMA.Q
# CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q
# !CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q
# UDS_000.PIN & LDS_000.PIN);
inst_AS_000_DMA.C = (CLK_OSZI);
inst_DS_000_DMA.D = (!RST
# BGACK_030.Q
# AS_000.PIN
# CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q
# !CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q
# UDS_000.PIN & LDS_000.PIN
# !CLK_030 & inst_DS_000_DMA.Q & !RW_000.PIN
# inst_DS_000_DMA.Q & !inst_CLK_030_H.Q & !RW_000.PIN
# CLK_030 & inst_AS_000_DMA.Q & inst_CLK_030_H.Q & !RW_000.PIN);
inst_DS_000_DMA.C = (CLK_OSZI);
CYCLE_DMA_0_.D = (RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & CLK_000_D_1_.Q & !AS_000.PIN
# RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CLK_000_D_0_.Q & !AS_000.PIN
# RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !AS_000.PIN);
CYCLE_DMA_0_.C = (CLK_OSZI);
CYCLE_DMA_1_.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_000.PIN
# RST & !BGACK_030.Q & CYCLE_DMA_1_.Q & CLK_000_D_1_.Q & !AS_000.PIN
# RST & !BGACK_030.Q & CYCLE_DMA_1_.Q & !CLK_000_D_0_.Q & !AS_000.PIN
# RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !AS_000.PIN);
CYCLE_DMA_1_.C = (CLK_OSZI);
!SIZE_DMA_0_.D = (RST & BGACK_030.Q & !inst_BGACK_030_INT_D.Q
# RST & BGACK_030.Q & !SIZE_DMA_0_.Q
# RST & !BGACK_030.Q & !UDS_000.PIN & !LDS_000.PIN);
SIZE_DMA_0_.C = (CLK_OSZI);
SIZE_DMA_1_.D = (!RST
# BGACK_030.Q & inst_BGACK_030_INT_D.Q & SIZE_DMA_1_.Q
# !BGACK_030.Q & !UDS_000.PIN & !LDS_000.PIN);
SIZE_DMA_1_.C = (CLK_OSZI);
!inst_VPA_D.D = (!VPA & RST);
inst_VPA_D.C = (CLK_OSZI);
!inst_UDS_000_INT.D = (RST & !inst_UDS_000_INT.Q & !SM_AMIGA_6_.Q
# RST & SM_AMIGA_6_.Q & !A_0_.PIN);
inst_UDS_000_INT.C = (CLK_OSZI);
inst_LDS_000_INT.D = (!RST
# inst_LDS_000_INT.Q & !SM_AMIGA_6_.Q
# SM_AMIGA_6_.Q & SIZE_0_.PIN & !SIZE_1_.PIN & !A_0_.PIN);
inst_LDS_000_INT.C = (CLK_OSZI);
inst_CLK_OUT_PRE_D.D = (inst_CLK_OUT_PRE_25.Q);
inst_CLK_OUT_PRE_D.C = (CLK_OSZI);
CLK_000_D_8_.D = (CLK_000_D_7_.Q);
CLK_000_D_8_.C = (CLK_OSZI);
CLK_000_D_9_.D = (CLK_000_D_8_.Q);
CLK_000_D_9_.C = (CLK_OSZI);
!inst_DTACK_D0.D = (!DTACK & RST);
inst_DTACK_D0.C = (CLK_OSZI);
inst_RESET_OUT.D = (RST & inst_RESET_OUT.Q
# RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q);
inst_RESET_OUT.C = (CLK_OSZI);
CLK_000_D_1_.D = (CLK_000_D_0_.Q);
CLK_000_D_1_.C = (CLK_OSZI);
CLK_000_D_0_.D = (CLK_000);
CLK_000_D_0_.C = (CLK_OSZI);
inst_CLK_OUT_PRE_50.D = (!inst_CLK_OUT_PRE_50.Q);
inst_CLK_OUT_PRE_50.C = (CLK_OSZI);
inst_CLK_OUT_PRE_25.D = (!inst_CLK_OUT_PRE_50.Q & inst_CLK_OUT_PRE_25.Q
# inst_CLK_OUT_PRE_50.Q & !inst_CLK_OUT_PRE_25.Q);
inst_CLK_OUT_PRE_25.C = (CLK_OSZI);
!IPL_D0_0_.D = (RST & !IPL_0_);
IPL_D0_0_.C = (CLK_OSZI);
!IPL_D0_1_.D = (RST & !IPL_1_);
IPL_D0_1_.C = (CLK_OSZI);
!IPL_D0_2_.D = (!IPL_2_ & RST);
IPL_D0_2_.C = (CLK_OSZI);
CLK_000_D_2_.D = (CLK_000_D_1_.Q);
CLK_000_D_2_.C = (CLK_OSZI);
CLK_000_D_3_.D = (CLK_000_D_2_.Q);
CLK_000_D_3_.C = (CLK_OSZI);
CLK_000_D_4_.D = (CLK_000_D_3_.Q);
CLK_000_D_4_.C = (CLK_OSZI);
CLK_000_D_5_.D = (CLK_000_D_4_.Q);
CLK_000_D_5_.C = (CLK_OSZI);
CLK_000_D_6_.D = (CLK_000_D_5_.Q);
CLK_000_D_6_.C = (CLK_OSZI);
CLK_000_D_7_.D = (CLK_000_D_6_.Q);
CLK_000_D_7_.C = (CLK_OSZI);
CLK_000_D_10_.D = (CLK_000_D_9_.Q);
CLK_000_D_10_.C = (CLK_OSZI);
!inst_AMIGA_BUS_ENABLE_DMA_HIGH.D = (RST & !A_1_ & !BGACK_030.Q
# RST & BGACK_030.Q & inst_BGACK_030_INT_D.Q & !inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q);
inst_AMIGA_BUS_ENABLE_DMA_HIGH.C = (CLK_OSZI);
inst_DS_000_ENABLE.D = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_4_.Q
# RST & !inst_AS_030_D0.Q & inst_DS_000_ENABLE.Q & BERR.PIN
# RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q & RW.PIN);
inst_DS_000_ENABLE.C = (CLK_OSZI);
SM_AMIGA_6_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q & BERR.PIN
# RST & !CLK_000_D_0_.Q & SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q & BERR.PIN
# nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & !SM_AMIGA_i_7_.Q);
SM_AMIGA_6_.C = (CLK_OSZI);
SM_AMIGA_4_.D = (RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_5_.Q
# RST & CLK_000_D_1_.Q & SM_AMIGA_4_.Q & BERR.PIN
# RST & !CLK_000_D_0_.Q & SM_AMIGA_4_.Q & BERR.PIN);
SM_AMIGA_4_.C = (CLK_OSZI);
SM_AMIGA_0_.D = (RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_1_.Q
# RST & CLK_000_D_1_.Q & SM_AMIGA_0_.Q & BERR.PIN
# RST & !CLK_000_D_0_.Q & SM_AMIGA_0_.Q & BERR.PIN);
SM_AMIGA_0_.C = (CLK_OSZI);
RST_DLY_0_.D = (RST & !CLK_000_D_1_.Q & RST_DLY_0_.Q
# RST & CLK_000_D_0_.Q & RST_DLY_0_.Q
# RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & !RST_DLY_0_.Q
# RST & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q);
RST_DLY_0_.C = (CLK_OSZI);
RST_DLY_1_.D.X1 = (RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & RST_DLY_0_.Q & !RST_DLY_1_.Q
# RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & RST_DLY_0_.Q & !RST_DLY_2_.Q);
RST_DLY_1_.D.X2 = (RST & RST_DLY_1_.Q);
RST_DLY_1_.C = (CLK_OSZI);
RST_DLY_2_.D = (RST & RST_DLY_2_.Q
# RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & RST_DLY_0_.Q & RST_DLY_1_.Q);
RST_DLY_2_.C = (CLK_OSZI);
inst_CLK_030_H.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !UDS_000.PIN
# RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !UDS_000.PIN
# RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !LDS_000.PIN
# RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !LDS_000.PIN
# !CLK_030 & RST & !BGACK_030.Q & !inst_AS_000_DMA.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_000.PIN & !UDS_000.PIN
# !CLK_030 & RST & !BGACK_030.Q & !inst_AS_000_DMA.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & !AS_000.PIN & !UDS_000.PIN
# !CLK_030 & RST & !BGACK_030.Q & !inst_AS_000_DMA.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_000.PIN & !LDS_000.PIN
# !CLK_030 & RST & !BGACK_030.Q & !inst_AS_000_DMA.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & !AS_000.PIN & !LDS_000.PIN);
inst_CLK_030_H.C = (CLK_OSZI);
SM_AMIGA_1_.D = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_2_.Q
# RST & !CLK_000_D_1_.Q & SM_AMIGA_1_.Q & BERR.PIN
# RST & CLK_000_D_0_.Q & SM_AMIGA_1_.Q & BERR.PIN);
SM_AMIGA_1_.C = (CLK_OSZI);
SM_AMIGA_5_.D = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q
# RST & !CLK_000_D_1_.Q & SM_AMIGA_5_.Q & BERR.PIN
# RST & CLK_000_D_0_.Q & SM_AMIGA_5_.Q & BERR.PIN);
SM_AMIGA_5_.C = (CLK_OSZI);
SM_AMIGA_3_.D.X1 = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_4_.Q & !SM_AMIGA_3_.Q
# RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_4_.Q & !BERR.PIN
# RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & BERR.PIN
# RST & !VMA.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & BERR.PIN);
SM_AMIGA_3_.D.X2 = (RST & SM_AMIGA_3_.Q & BERR.PIN);
SM_AMIGA_3_.C = (CLK_OSZI);
SM_AMIGA_2_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_2_.Q & BERR.PIN
# RST & !CLK_000_D_0_.Q & SM_AMIGA_2_.Q & BERR.PIN
# RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q
# RST & !VMA.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q);
SM_AMIGA_2_.C = (CLK_OSZI);
SM_AMIGA_i_7_.D.X1 = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q & !BERR.PIN
# RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_4_.Q & !BERR.PIN
# RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_1_.Q & !BERR.PIN
# RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_5_.Q & !BERR.PIN
# RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_2_.Q & !BERR.PIN
# RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & !BERR.PIN
# RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & BERR.PIN
# !nEXP_SPACE & RST & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & BERR.PIN
# RST & inst_AS_030_000_SYNC.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & BERR.PIN
# RST & !CLK_000_D_1_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & BERR.PIN
# RST & CLK_000_D_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & BERR.PIN
# RST & !VMA.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & !BERR.PIN
# nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & !BERR.PIN);
SM_AMIGA_i_7_.D.X2 = (RST & BERR.PIN);
SM_AMIGA_i_7_.C = (CLK_OSZI);
CIIN_0 = (nEXP_SPACE
# A_DECODE_23_ & A_DECODE_22_ & A_DECODE_21_ & A_DECODE_20_ & !inst_AS_030_D0.Q & !AHIGH_24_.PIN & !AHIGH_25_.PIN & !AHIGH_26_.PIN & !AHIGH_27_.PIN & !AHIGH_28_.PIN & !AHIGH_29_.PIN & !AHIGH_30_.PIN & !AHIGH_31_.PIN);
Reverse-Polarity Equations:
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