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68030tk/Logic/syntmp/BUS68030_srr.htm

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<!@TC:1471448741>
#Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014
#install: E:\ispLEVER_Classic2_0\synpbase
#OS: Windows 7 6.2
#Hostname: DEEPTHOUGHT
#Implementation: logic
<a name=compilerReport1>$ Start of Compile</a>
#Wed Aug 17 17:45:41 2016
Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
@N: : <!@TM:1471448741> | Running in 64-bit mode
Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited.
@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="E:\ispLEVER_Classic2_0\synpbase\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1471448741> | Setting time resolution to ns
@N: : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N::@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1471448741> | Top entity is set to BUS68030.
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
VHDL syntax check successful!
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N:CD630:@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1471448741> | Synthesizing work.bus68030.behavioral
@N:<a href="@N:CD233:@XP_HELP">CD233</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:65:10:65:12:@N:CD233:@XP_MSG">68030-68000-bus.vhd(65)</a><!@TM:1471448741> | Using sequential encoding for type sm_e
@N:<a href="@N:CD233:@XP_HELP">CD233</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:82:14:82:16:@N:CD233:@XP_MSG">68030-68000-bus.vhd(82)</a><!@TM:1471448741> | Using sequential encoding for type sm_68000
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:124:7:124:18:@W:CD638:@XP_MSG">68030-68000-bus.vhd(124)</a><!@TM:1471448741> | Signal clk_out_pre is undriven </font>
Post processing for work.bus68030.behavioral
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:134:37:134:40:@W:CL169:@XP_MSG">68030-68000-bus.vhd(134)</a><!@TM:1471448741> | Pruning register DS_030_D0_3 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:134:37:134:40:@W:CL169:@XP_MSG">68030-68000-bus.vhd(134)</a><!@TM:1471448741> | Pruning register AMIGA_BUS_ENABLE_INT_5 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:126:34:126:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(126)</a><!@TM:1471448741> | Pruning register CLK_OUT_EXP_INT_1 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:122:36:122:39:@W:CL169:@XP_MSG">68030-68000-bus.vhd(122)</a><!@TM:1471448741> | Pruning register CLK_OUT_PRE_25_3 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:151:2:151:4:@W:CL169:@XP_MSG">68030-68000-bus.vhd(151)</a><!@TM:1471448741> | Pruning register CLK_030_D0_2 </font>
<font color=#A52A2A>@W:<a href="@W:CL265:@XP_HELP">CL265</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:130:61:130:76:@W:CL265:@XP_MSG">68030-68000-bus.vhd(130)</a><!@TM:1471448741> | Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ... </font>
<font color=#A52A2A>@W:<a href="@W:CL271:@XP_HELP">CL271</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:129:55:129:65:@W:CL271:@XP_MSG">68030-68000-bus.vhd(129)</a><!@TM:1471448741> | Pruning bits 12 to 10 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ... </font>
<font color=#A52A2A>@W:<a href="@W:CL271:@XP_HELP">CL271</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:127:38:127:41:@W:CL271:@XP_MSG">68030-68000-bus.vhd(127)</a><!@TM:1471448741> | Pruning bits 7 to 2 of CLK_000_D_3(7 downto 0) -- not in use ... </font>
<font color=#A52A2A>@W:<a href="@W:CL189:@XP_HELP">CL189</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:134:37:134:40:@W:CL189:@XP_MSG">68030-68000-bus.vhd(134)</a><!@TM:1471448741> | Register bit BGACK_030_INT_PRE is always 1, optimizing ...</font>
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:134:37:134:40:@N:CL201:@XP_MSG">68030-68000-bus.vhd(134)</a><!@TM:1471448741> | Trying to extract state machine for register SM_AMIGA
Extracted state machine for register SM_AMIGA
State machine has 8 reachable states with original encodings of:
000
001
010
011
100
101
110
111
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:134:37:134:40:@N:CL201:@XP_MSG">68030-68000-bus.vhd(134)</a><!@TM:1471448741> | Trying to extract state machine for register cpu_est
<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:23:1:23:2:@W:CL246:@XP_MSG">68030-68000-bus.vhd(23)</a><!@TM:1471448741> | Input port bits 15 to 2 of a(31 downto 2) are unused </font>
@END
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 71MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Aug 17 17:45:41 2016
###########################################################]
Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
@N: : <!@TM:1471448743> | Running in 64-bit mode
File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs changed - recompiling
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Aug 17 17:45:43 2016
###########################################################]
Map & Optimize Report
<a name=mapperReport2>Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014</a>
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
Product Version I-2014.03LC
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1471448743> | Running in 64-bit mode.
@N: : <a href="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:134:37:134:40:@N::@XP_MSG">68030-68000-bus.vhd(134)</a><!@TM:1471448743> | Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
original code -> new code
000 -> 00000000
001 -> 00000011
010 -> 00000101
011 -> 00001001
100 -> 00010001
101 -> 00100001
110 -> 01000001
111 -> 10000001
---------------------------------------
<a name=resourceUsage3>Resource Usage Report</a>
Simple gate primitives:
DFF 78 uses
BI_DIR 10 uses
BUFTH 4 uses
IBUF 46 uses
OBUF 15 uses
AND2 299 uses
INV 261 uses
OR2 27 uses
XOR2 7 uses
@N:<a href="@N:FC100:@XP_HELP">FC100</a> : <!@TM:1471448743> | Timing Report not generated for this device, please use place and route tools for timing analysis.
I-2014.03LC
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Aug 17 17:45:43 2016
###########################################################]
</pre></samp></body></html>
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