mirror of https://github.com/kr239/68030tk.git
246 lines
5.8 KiB
Plaintext
246 lines
5.8 KiB
Plaintext
[DEVICE]
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Family = M4A5;
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PartType = M4A5-128/64;
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Package = 100TQFP;
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PartNumber = M4A5-128/64-10VC;
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Speed = -10;
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Operating_condition = COM;
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EN_Segment = NO;
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Pin_MC_1to1 = NO;
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Voltage = 5.0;
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[REVISION]
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RCS = "$Revision: 1.2 $";
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Parent = m4a5.lci;
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SDS_file = m4a5.sds;
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Design = 68030_tk.tt4;
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Rev = 0.01;
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DATE = 1/11/18;
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TIME = 20:16:38;
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Type = TT2;
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Pre_Fit_Time = 1;
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Source_Format = Pure_VHDL;
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[IGNORE ASSIGNMENTS]
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Pin_Assignments = NO;
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Pin_Keep_Block = NO;
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Pin_Keep_Segment = NO;
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Group_Assignments = NO;
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Macrocell_Assignments = NO;
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Macrocell_Keep_Block = NO;
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Macrocell_Keep_Segment = NO;
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Pin_Reservation = NO;
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Timing_Constraints = NO;
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Block_Reservation = NO;
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Segment_Reservation = NO;
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Ignore_Source_Location = NO;
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Ignore_Source_Optimization = NO;
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Ignore_Source_Timing = NO;
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[CLEAR ASSIGNMENTS]
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Pin_Assignments = NO;
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Pin_Keep_Block = NO;
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Pin_Keep_Segment = NO;
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Group_Assignments = NO;
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Macrocell_Assignments = NO;
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Macrocell_Keep_Block = NO;
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Macrocell_Keep_Segment = NO;
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Pin_Reservation = NO;
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Timing_Constraints = NO;
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Block_Reservation = NO;
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Segment_Reservation = NO;
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Ignore_Source_Location = NO;
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Ignore_Source_Optimization = NO;
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Ignore_Source_Timing = NO;
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[BACKANNOTATE NETLIST]
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Netlist = VHDL;
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Delay_File = SDF;
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Generic_VCC = ;
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Generic_GND = ;
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[BACKANNOTATE ASSIGNMENTS]
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Pin_Assignment = NO;
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Pin_Block = NO;
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Pin_Macrocell_Block = NO;
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Routing = NO;
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[GLOBAL PROJECT OPTIMIZATION]
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Balanced_Partitioning = YES;
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Spread_Placement = YES;
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Max_Pin_Percent = 100;
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Max_Macrocell_Percent = 100;
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Max_Inter_Seg_Percent = 100;
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Max_Seg_In_Percent = 100;
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Max_Blk_In_Percent = 100;
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[FITTER REPORT FORMAT]
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Fitter_Options = YES;
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Pinout_Diagram = NO;
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Pinout_Listing = YES;
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Detailed_Block_Segment_Summary = YES;
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Input_Signal_List = YES;
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Output_Signal_List = YES;
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Bidir_Signal_List = YES;
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Node_Signal_List = YES;
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Signal_Fanout_List = YES;
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Block_Segment_Fanin_List = YES;
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Prefit_Eqn = YES;
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Postfit_Eqn = YES;
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Page_Break = YES;
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[OPTIMIZATION OPTIONS]
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Logic_Reduction = YES;
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Max_PTerm_Split = 20;
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Max_PTerm_Collapse = 20;
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XOR_Synthesis = YES;
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Node_Collapse = Yes;
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DT_Synthesis = Yes;
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[FITTER GLOBAL OPTIONS]
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Run_Time = 0;
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Set_Reset_Dont_Care = YES;
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In_Reg_Optimize = YES;
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Clock_Optimize = NO;
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Conf_Unused_IOs = OUT_LOW;
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[POWER]
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Powerlevel = Low, High;
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Default = High;
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High = 1, B;
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Low = 8, H, G, F, E, D, C, B, A;
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Type = GLB;
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[HARDWARE DEVICE OPTIONS]
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Zero_Hold_Time = Yes;
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Signature_Word = 0;
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Pull_up = No;
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Out_Slew_Rate = SLOW, FAST, 57, CLK_DIV_OUT, CLK_EXP, FPU_CS, AMIGA_BUS_DATA_DIR, AMIGA_BUS_ENABLE_LOW,
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AMIGA_ADDR_ENABLE, AMIGA_BUS_ENABLE_HIGH, AS_030, A_16_, A_17_, A_18_,
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A_19_, RW, SIZE_1_, SIZE_0_, AVEC, BGACK_030, BG_000, E, IPL_030_0_, IPL_030_1_,
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IPL_030_2_, LDS_000, UDS_000, VMA, RESET, CIIN, A_20_, A_21_, A_22_, A_24_,
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A_25_, A_26_, A_27_, A_28_, A_29_, A_30_, A_31_, DS_030, BERR, A0, DSACK1,
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RW_000, AS_000, A_23_, A1, A_3_, A_2_, AHIGH_24_, AHIGH_25_, AHIGH_26_,
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AHIGH_27_, AHIGH_28_, AHIGH_29_, AHIGH_30_, AHIGH_31_, A_0_;
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Device_max_fanin = 33;
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Device_max_pterms = 20;
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Usercode_Format = Hex;
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[PIN RESERVATIONS]
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layer = OFF;
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[LOCATION ASSIGNMENT]
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Layer = OFF;
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AHIGH_30_ = BIDIR,5, B,-;
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AHIGH_31_ = BIDIR,4, B,-;
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AHIGH_29_ = BIDIR,6, B,-;
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AHIGH_28_ = BIDIR,15, C,-;
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A_DECODE_23_ = INPUT,85, H,-;
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AHIGH_27_ = BIDIR,16, C,-;
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AHIGH_26_ = BIDIR,17, C,-;
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AHIGH_25_ = BIDIR,18, C,-;
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AHIGH_24_ = BIDIR,19, C,-;
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A_DECODE_22_ = INPUT,84, H,-;
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A_DECODE_21_ = INPUT,94, A,-;
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IPL_2_ = INPUT,68, G,-;
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A_DECODE_20_ = INPUT,93, A,-;
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A_DECODE_19_ = INPUT,97, A,-;
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FC_1_ = INPUT,58, F,-;
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A_DECODE_18_ = INPUT,95, A,-;
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AS_030 = BIDIR,82, H,-;
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A_DECODE_17_ = INPUT,59, F,-;
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AS_000 = BIDIR,42, E,-;
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A_DECODE_16_ = INPUT,96, A,-;
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DS_030 = OUTPUT,98, A,-;
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UDS_000 = BIDIR,32, D,-;
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LDS_000 = BIDIR,31, D,-;
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nEXP_SPACE = INPUT,14,-,-;
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BERR = BIDIR,41, E,-;
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BG_030 = INPUT,21, C,-;
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BGACK_000 = INPUT,28, D,-;
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CLK_000 = INPUT,11,-,-;
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CLK_OSZI = INPUT,61,-,-;
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CLK_DIV_OUT = OUTPUT,65, G,-;
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CLK_EXP = OUTPUT,10, B,-;
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FPU_CS = OUTPUT,78, H,-;
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FPU_SENSE = INPUT,91, A,-;
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DSACK1 = OUTPUT,81, H,-;
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IPL_1_ = INPUT,56, F,-;
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DTACK = INPUT,30, D,-;
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IPL_0_ = INPUT,67, G,-;
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AVEC = OUTPUT,92, A,-;
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FC_0_ = INPUT,57, F,-;
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E = OUTPUT,66, G,-;
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A_1_ = INPUT,60, F,-;
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VPA = INPUT,36,-,-;
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RST = INPUT,86,-,-;
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AMIGA_ADDR_ENABLE = OUTPUT,33, D,-;
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AMIGA_BUS_DATA_DIR = OUTPUT,48, E,-;
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AMIGA_BUS_ENABLE_LOW = OUTPUT,20, C,-;
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AMIGA_BUS_ENABLE_HIGH = OUTPUT,34, D,-;
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CIIN = OUTPUT,47, E,-;
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SIZE_1_ = BIDIR,79, H,-;
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SIZE_0_ = BIDIR,70, G,-;
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IPL_030_2_ = OUTPUT,9, B,-;
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RW_000 = BIDIR,80, H,-;
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BG_000 = OUTPUT,29, D,-;
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BGACK_030 = OUTPUT,83, H,-;
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A_0_ = BIDIR,69, G,-;
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IPL_030_1_ = OUTPUT,7, B,-;
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IPL_030_0_ = OUTPUT,8, B,-;
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VMA = OUTPUT,35, D,-;
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RW = BIDIR,71, G,-;
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cpu_est_0_ = NODE,4, F,-;
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cpu_est_1_ = NODE,5, G,-;
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cpu_est_2_ = NODE,13, D,-;
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cpu_est_3_ = NODE,9, D,-;
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inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,9, E,-;
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inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,8, E,-;
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inst_AS_030_D0 = NODE,12, F,-;
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inst_AS_030_D1 = NODE,1, F,-;
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inst_AS_030_000_SYNC = NODE,8, F,-;
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inst_AS_000_DMA = NODE,13, G,-;
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inst_DS_000_DMA = NODE,9, G,-;
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inst_VPA_D = NODE,6, B,-;
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CLK_000_D_3_ = NODE,2, D,-;
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inst_DTACK_D0 = NODE,13, F,-;
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inst_AMIGA_DS = NODE,13, H,-;
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CLK_000_D_1_ = NODE,8, A,-;
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CLK_000_D_0_ = NODE,0, F,-;
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inst_CLK_OUT_PRE_50 = NODE,6, H,-;
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inst_CLK_OUT_PRE_D = NODE,5, H,-;
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IPL_D0_0_ = NODE,9, F,-;
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IPL_D0_1_ = NODE,10, A,-;
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IPL_D0_2_ = NODE,6, C,-;
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CLK_000_D_2_ = NODE,2, H,-;
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CLK_000_D_4_ = NODE,5, F,-;
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inst_UDS_000_INT = NODE,6, D,-;
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inst_DS_000_ENABLE = NODE,13, A,-;
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inst_LDS_000_INT = NODE,9, A,-;
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inst_BGACK_030_INT_D = NODE,13, E,-;
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SM_AMIGA_6_ = NODE,13, B,-;
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SM_AMIGA_4_ = NODE,5, A,-;
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SM_AMIGA_1_ = NODE,1, A,-;
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SM_AMIGA_0_ = NODE,12, A,-;
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CYCLE_DMA_0_ = NODE,6, G,-;
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CYCLE_DMA_1_ = NODE,10, G,-;
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inst_DSACK1_INT = NODE,2, G,-;
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inst_AS_000_INT = NODE,13, C,-;
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SM_AMIGA_5_ = NODE,6, A,-;
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SM_AMIGA_3_ = NODE,2, C,-;
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SM_AMIGA_2_ = NODE,9, C,-;
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CLK_OUT_INTreg = NODE,2, A,-;
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SM_AMIGA_i_7_ = NODE,2, B,-;
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N_205 = NODE,5, E,-;
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