mirror of https://github.com/kr239/68030tk.git
119 lines
5.2 KiB
Plaintext
119 lines
5.2 KiB
Plaintext
#Build: Synplify Pro G-2012.09LC-SP1 , Build 035R, Mar 19 2013
|
|
#install: C:\Program Files (x86)\ispLever\synpbase
|
|
#OS: Windows 7 6.1
|
|
#Hostname: DEEPTHOUGHT
|
|
|
|
#Implementation: logic
|
|
|
|
$ Start of Compile
|
|
#Sun Aug 10 19:50:07 2014
|
|
|
|
Synopsys VHDL Compiler, version comp201209rcp1, Build 283R, built Mar 19 2013
|
|
@N|Running in 64-bit mode
|
|
Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
|
|
|
|
@N: CD720 :"C:\Program Files (x86)\ispLever\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
|
|
@N:"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Top entity is set to BUS68030.
|
|
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
|
|
VHDL syntax check successful!
|
|
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
|
|
@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
|
|
Post processing for work.bus68030.behavioral
|
|
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":498:2:498:3|Pruning register CLK_OUT_PRE_33
|
|
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":140:32:140:34|Pruning register CLK_REF(1 downto 0)
|
|
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Pruning register CLK_000_D4
|
|
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_000_D3
|
|
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_000_D2
|
|
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:35:126:37|Pruning register CLK_OUT_NE
|
|
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":161:2:161:3|Pruning register CLK_CNT_P(1 downto 0)
|
|
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":148:2:148:3|Pruning register CLK_CNT_N(1 downto 0)
|
|
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":135:61:135:75|Pruning bit 12 of CLK_000_N_SYNC(12 downto 0) -- not in use ...
|
|
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":105:36:105:38|Pruning bits 12 to 10 of CLK_000_P_SYNC(12 downto 0) -- not in use ...
|
|
@A: CL282 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":102:32:102:34|Feedback mux created for signal CLK_030_H -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
|
|
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":140:32:140:34|Trying to extract state machine for register SM_AMIGA
|
|
Extracted state machine for register SM_AMIGA
|
|
State machine has 8 reachable states with original encodings of:
|
|
000
|
|
001
|
|
010
|
|
011
|
|
100
|
|
101
|
|
110
|
|
111
|
|
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":128:34:128:36|Trying to extract state machine for register cpu_est
|
|
Extracted state machine for register cpu_est
|
|
State machine has 11 reachable states with original encodings of:
|
|
0000
|
|
0010
|
|
0011
|
|
0100
|
|
0101
|
|
0110
|
|
0111
|
|
1010
|
|
1011
|
|
1100
|
|
1111
|
|
@END
|
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
|
# Sun Aug 10 19:50:07 2014
|
|
|
|
###########################################################]
|
|
Map & Optimize Report
|
|
|
|
Synopsys CPLD Technology Mapper, Version maplat, Build 621R, Built Mar 19 2013
|
|
Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
|
|
Product Version G-2012.09LC-SP1
|
|
@N: MF248 |Running in 64-bit mode.
|
|
Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
|
|
original code -> new code
|
|
000 -> 00000001
|
|
001 -> 00000010
|
|
010 -> 00000100
|
|
011 -> 00001000
|
|
100 -> 00010000
|
|
101 -> 00100000
|
|
110 -> 01000000
|
|
111 -> 10000000
|
|
Encoding state machine cpu_est[0:10] (view:work.BUS68030(behavioral))
|
|
original code -> new code
|
|
0000 -> 0000
|
|
0010 -> 0010
|
|
0011 -> 0011
|
|
0100 -> 0100
|
|
0101 -> 0101
|
|
0110 -> 0110
|
|
0111 -> 0111
|
|
1010 -> 1010
|
|
1011 -> 1011
|
|
1100 -> 1100
|
|
1111 -> 1111
|
|
---------------------------------------
|
|
Resource Usage Report
|
|
|
|
Simple gate primitives:
|
|
DFFRH 44 uses
|
|
DFFSH 27 uses
|
|
DFF 1 use
|
|
BI_DIR 13 uses
|
|
IBUF 30 uses
|
|
OBUF 16 uses
|
|
BUFTH 1 use
|
|
AND2 193 uses
|
|
INV 167 uses
|
|
XOR2 3 uses
|
|
OR2 23 uses
|
|
|
|
|
|
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
|
|
G-2012.09LC-SP1
|
|
Mapper successful!
|
|
|
|
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 95MB)
|
|
|
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
|
# Sun Aug 10 19:50:09 2014
|
|
|
|
###########################################################]
|