68030tk/Logic/68030_tk.bl2

#$ TOOL ispLEVER Classic 1.7.00.05.28.13
#$ DATE Sat Jun 07 23:03:19 2014
#$ MODULE 68030_tk
#$ PINS 59 A_22_ A_21_ SIZE_1_ A_20_ A_19_ A_31_ A_18_ A_17_ IPL_030_2_ A_16_ IPL_030_1_ \
#  IPL_2_ IPL_030_0_ IPL_1_ FC_1_ IPL_0_ AS_030 FC_0_ AS_000 RW_000 DS_030 UDS_000 LDS_000 A0 \
#  nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT \
#  CLK_EXP FPU_CS DSACK1 DTACK AVEC AVEC_EXP E VPA VMA RST RESET RW AMIGA_BUS_ENABLE \
#  AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ \
#  A_25_ A_24_ A_23_
#$ NODES 407 a_c_28__n a_c_29__n a_c_30__n inst_BGACK_030_INTreg a_c_31__n \
#  inst_FPU_CS_INTreg inst_avec_expreg A0_c inst_VMA_INTreg inst_AS_030_000_SYNC \
#  nEXP_SPACE_c inst_BGACK_030_INT_D inst_AS_000_DMA inst_VPA_D BG_030_c \
#  inst_CLK_OUT_PRE_50_D inst_CLK_000_D0 BG_000DFFSHreg inst_CLK_000_D1 inst_DTACK_D0 \
#  inst_CLK_OUT_PRE_50 BGACK_000_c inst_CLK_OUT_PRE_25 SM_AMIGA_1_ CLK_030_c vcc_n_n \
#  gnd_n_n CLK_000_c inst_AS_000_INT SM_AMIGA_6_ CLK_OSZI_c SM_AMIGA_0_ SM_AMIGA_7_ \
#  inst_RW_000_INT CLK_OUT_INTreg inst_UDS_000_INT inst_LDS_000_INT inst_DSACK1_INT \
#  IPL_030DFFSH_0_reg state_machine_un3_clk_out_pre_50_n inst_CLK_000_D2 \
#  IPL_030DFFSH_1_reg inst_CLK_030_H inst_DS_000_DMA IPL_030DFFSH_2_reg SIZE_DMA_0_ \
#  SIZE_DMA_1_ ipl_c_0__n inst_A0_DMA SM_AMIGA_5_ ipl_c_1__n SM_AMIGA_4_ SM_AMIGA_3_ \
#  ipl_c_2__n SM_AMIGA_2_ DSACK1_c RST_c RESETDFFRHreg RW_c fc_c_0__n CLK_OUT_PRE_25_0 \
#  fc_c_1__n AMIGA_BUS_DATA_DIR_c cpu_est_0_ state_machine_un3_clk_000_d1_i_n \
#  cpu_est_1_ state_machine_un6_bgack_000_0_n cpu_est_2_ cpu_est_ns_0_1__n \
#  cpu_est_3_reg N_159_i cpu_estse N_158_i N_149_i N_150_i N_153_i AS_000_DMA_0_sqmuxa \
#  N_152_i state_machine_un8_bgack_030_int_n N_160_i N_92 N_154_i \
#  state_machine_un49_clk_000_d0_n state_machine_un10_clk_000_d0_2_i_n N_210 N_156_i \
#  N_220 N_157_i CLK_030_H_1_sqmuxa cpu_est_ns_0_2__n AS_000_DMA_1_sqmuxa \
#  state_machine_un10_clk_000_d0_i_n DS_000_DMA_1_sqmuxa \
#  state_machine_un12_clk_000_d0_0_n state_machine_un24_bgack_030_int_n \
#  FPU_CS_INT_1_sqmuxa_i state_machine_clk_030_h_2_n un1_as_030_000_sync8_1_0 \
#  state_machine_clk_030_h_2_f1_n AS_030_000_SYNC_0_sqmuxa_2_i \
#  state_machine_ds_000_dma_3_n un1_as_030_000_sync8_0 N_87 un1_SM_AMIGA_12_0 N_93 \
#  state_machine_un3_clk_030_i_n N_94 state_machine_un57_clk_000_d0_i_n N_88 \
#  state_machine_un51_clk_000_d0_i_n N_90 state_machine_un53_clk_000_d0_0_n N_164_1 \
#  state_machine_un3_bgack_030_int_d_i_n state_machine_un10_bgack_030_int_n \
#  un1_bgack_030_int_d_0 UDS_000_INT_0_sqmuxa_1 AMIGA_BUS_ENABLE_INT_3_sqmuxa_i \
#  UDS_000_INT_0_sqmuxa AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i \
#  state_machine_un25_clk_000_d0_n N_86_0 N_164 N_101_i RW_li_m N_85_i N_181 N_84_0 \
#  RW_000_i_m N_97_i N_163 un1_SM_AMIGA_8 N_96_i N_100 N_95_i N_91 sm_amiga_ns_0_5__n \
#  state_machine_un31_bgack_030_int_n N_88_i state_machine_lds_000_int_7_n N_89_i \
#  state_machine_uds_000_int_7_n sm_amiga_ns_0_0__n RW_000_INT_0_sqmuxa_1 \
#  AMIGA_BUS_ENABLE_INT_2_sqmuxa_i un1_AS_030_2 AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i \
#  N_59 un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0 un1_bgack_030_int_d BG_030_c_i \
#  un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa state_machine_un8_bg_030_i_n \
#  state_machine_un10_bg_030_n state_machine_un10_bg_030_0_n \
#  state_machine_un3_bgack_030_int_d_n state_machine_un5_bgack_030_int_d_i_n \
#  AMIGA_BUS_ENABLE_INT_3_sqmuxa N_59_0 N_86 state_machine_un10_bgack_030_int_0_n \
#  AMIGA_BUS_ENABLE_INT_1_sqmuxa_1 N_181_i N_84 A0_c_i \
#  AMIGA_BUS_ENABLE_INT_1_sqmuxa_2 state_machine_uds_000_int_7_0_n \
#  state_machine_un8_bg_030_n state_machine_lds_000_int_7_0_n \
#  AMIGA_BUS_ENABLE_INT_2_sqmuxa state_machine_size_dma_4_0_0__n N_89 \
#  state_machine_size_dma_4_0_1__n N_95 N_91_i N_96 N_97 N_100_i N_99 un1_SM_AMIGA_8_0 \
#  state_machine_un28_clk_000_d1_n N_164_i N_101 N_163_i un1_SM_AMIGA_12 \
#  AMIGA_BUS_DATA_DIR_c_0 AS_030_000_SYNC_1_sqmuxa RW_000_i_m_i \
#  un1_as_030_000_sync8_1 RW_li_m_i AS_000_INT_1_sqmuxa \
#  state_machine_rw_000_int_7_iv_i_n DSACK1_INT_1_sqmuxa size_c_i_1__n \
#  state_machine_un10_clk_000_d0_n state_machine_un25_clk_000_d0_i_n \
#  state_machine_un12_clk_000_d0_n N_90_i state_machine_un51_clk_000_d0_n \
#  state_machine_un53_clk_000_d0_n N_94_i state_machine_un57_clk_000_d0_n N_93_i \
#  AS_030_000_SYNC_0_sqmuxa_2 sm_amiga_ns_0_4__n AS_030_000_SYNC_0_sqmuxa N_87_0 \
#  state_machine_un3_clk_030_n state_machine_ds_000_dma_3_0_n FPU_CS_INT_1_sqmuxa \
#  CLK_030_H_i state_machine_un28_clk_030_n CLK_030_H_1_sqmuxa_i \
#  un1_as_030_000_sync8 state_machine_clk_030_h_2_f1_0_n N_150 un3_dtack_i \
#  state_machine_un5_clk_000_d0_n N_92_i state_machine_un3_clk_000_d1_n \
#  cpu_est_ns_2__n un3_dtack_i_1 N_157 state_machine_un25_clk_000_d0_i_1_n N_156 \
#  cpu_est_ns_0_1_2__n state_machine_un10_clk_000_d0_2_n N_210_1 N_154 N_210_2 N_160 \
#  N_220_1 N_152 N_220_2 N_153 N_220_3 N_158 N_220_4 N_159 N_220_5 cpu_est_ns_1__n N_220_6 \
#  state_machine_un6_bgack_000_n DS_000_DMA_1_sqmuxa_1 AS_030_000_SYNC_i \
#  UDS_000_INT_0_sqmuxa_1_1 CLK_000_D1_i UDS_000_INT_0_sqmuxa_1_2 cpu_est_i_3__n \
#  UDS_000_INT_0_sqmuxa_1_0 cpu_est_i_2__n UDS_000_INT_0_sqmuxa_2 cpu_est_i_1__n \
#  N_164_1_0 cpu_est_i_0__n RW_li_m_1 VPA_D_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 \
#  CLK_000_D0_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_2 state_machine_un28_clk_030_i_n \
#  N_101_1 VMA_INT_i un1_bgack_030_int_d_0_1 AS_030_i state_machine_un8_bg_030_1_n \
#  AS_030_000_SYNC_0_sqmuxa_i state_machine_un8_bg_030_2_n sm_amiga_i_1__n \
#  state_machine_un57_clk_000_d0_1_n DTACK_D0_i state_machine_un49_clk_000_d0_1_n \
#  a_i_19__n AS_030_000_SYNC_0_sqmuxa_1 a_i_16__n AS_030_000_SYNC_0_sqmuxa_2_0 \
#  a_i_18__n state_machine_un28_clk_030_1_n state_machine_un5_clk_000_d0_i_0_n \
#  state_machine_un28_clk_030_2_n nEXP_SPACE_i state_machine_un28_clk_030_3_n \
#  sm_amiga_i_7__n state_machine_un28_clk_030_4_n sm_amiga_i_0__n \
#  state_machine_un28_clk_030_5_n N_99_i state_machine_un5_clk_000_d0_1_n \
#  sm_amiga_i_2__n state_machine_un5_clk_000_d0_2_n BGACK_030_INT_i \
#  state_machine_un10_clk_000_d0_1_n BGACK_030_INT_D_i \
#  state_machine_un10_clk_000_d0_2_0_n sm_amiga_i_6__n \
#  state_machine_un10_clk_000_d0_3_n UDS_000_i cpu_est_ns_0_1_1__n LDS_000_i \
#  cpu_est_ns_0_2_1__n AS_000_DMA_0_sqmuxa_i state_machine_un28_clk_000_d1_1_n \
#  state_machine_un8_bgack_030_int_i_n cpu_estse_2_un3_n \
#  state_machine_un31_bgack_030_int_i_n cpu_estse_2_un1_n sm_amiga_i_5__n \
#  cpu_estse_2_un0_n RW_i cpu_estse_1_un3_n RW_000_i cpu_estse_1_un1_n \
#  UDS_000_INT_0_sqmuxa_i cpu_estse_1_un0_n UDS_000_INT_0_sqmuxa_1_i \
#  cpu_estse_0_un3_n AS_000_i cpu_estse_0_un1_n DS_030_i cpu_estse_0_un0_n \
#  state_machine_un49_clk_000_d0_i_n ipl_030_0_2__un3_n CLK_030_i ipl_030_0_2__un1_n \
#  state_machine_un24_bgack_030_int_i_n ipl_030_0_2__un0_n AS_000_DMA_i \
#  ipl_030_0_1__un3_n sm_amiga_i_4__n ipl_030_0_1__un1_n a_i_30__n ipl_030_0_1__un0_n \
#  a_i_31__n ipl_030_0_0__un3_n a_i_28__n ipl_030_0_0__un1_n a_i_29__n \
#  ipl_030_0_0__un0_n a_i_26__n bgack_030_int_0_un3_n a_i_27__n bgack_030_int_0_un1_n \
#  a_i_24__n bgack_030_int_0_un0_n a_i_25__n as_030_000_sync_0_un3_n RST_i \
#  as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n FPU_CS_INT_i fpu_cs_int_0_un3_n \
#  CLK_OUT_PRE_50_D_i fpu_cs_int_0_un1_n AS_030_c fpu_cs_int_0_un0_n \
#  as_000_int_0_un3_n AS_000_c as_000_int_0_un1_n as_000_int_0_un0_n RW_000_c \
#  dsack1_int_0_un3_n dsack1_int_0_un1_n DS_030_c dsack1_int_0_un0_n vma_int_0_un3_n \
#  UDS_000_c vma_int_0_un1_n vma_int_0_un0_n LDS_000_c avec_exp_0_un3_n \
#  avec_exp_0_un1_n size_c_0__n avec_exp_0_un0_n bg_000_0_un3_n size_c_1__n \
#  bg_000_0_un1_n bg_000_0_un0_n a_c_16__n lds_000_int_0_un3_n lds_000_int_0_un1_n \
#  a_c_17__n lds_000_int_0_un0_n uds_000_int_0_un3_n a_c_18__n uds_000_int_0_un1_n \
#  uds_000_int_0_un0_n a_c_19__n rw_000_int_0_un3_n rw_000_int_0_un1_n a_c_20__n \
#  rw_000_int_0_un0_n as_000_dma_0_un3_n a_c_21__n as_000_dma_0_un1_n \
#  as_000_dma_0_un0_n a_c_22__n ds_000_dma_0_un3_n ds_000_dma_0_un1_n a_c_23__n \
#  ds_000_dma_0_un0_n clk_030_h_0_un3_n a_c_24__n clk_030_h_0_un1_n clk_030_h_0_un0_n \
#  a_c_25__n a_c_26__n a_c_27__n
.model bus68030
.inputs A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF \
BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF VPA.BLIF RST.BLIF \
A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF A_24_.BLIF \
A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF \
A_16_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF SIZE_1_.BLIF AS_030.BLIF \
AS_000.BLIF RW_000.BLIF DS_030.BLIF UDS_000.BLIF LDS_000.BLIF A0.BLIF \
DSACK1.BLIF DTACK.BLIF RW.BLIF SIZE_0_.BLIF a_c_28__n.BLIF a_c_29__n.BLIF \
a_c_30__n.BLIF inst_BGACK_030_INTreg.BLIF a_c_31__n.BLIF \
inst_FPU_CS_INTreg.BLIF inst_avec_expreg.BLIF A0_c.BLIF inst_VMA_INTreg.BLIF \
inst_AS_030_000_SYNC.BLIF nEXP_SPACE_c.BLIF inst_BGACK_030_INT_D.BLIF \
inst_AS_000_DMA.BLIF inst_VPA_D.BLIF BG_030_c.BLIF inst_CLK_OUT_PRE_50_D.BLIF \
inst_CLK_000_D0.BLIF BG_000DFFSHreg.BLIF inst_CLK_000_D1.BLIF \
inst_DTACK_D0.BLIF inst_CLK_OUT_PRE_50.BLIF BGACK_000_c.BLIF \
inst_CLK_OUT_PRE_25.BLIF SM_AMIGA_1_.BLIF CLK_030_c.BLIF vcc_n_n.BLIF \
gnd_n_n.BLIF CLK_000_c.BLIF inst_AS_000_INT.BLIF SM_AMIGA_6_.BLIF \
CLK_OSZI_c.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_7_.BLIF inst_RW_000_INT.BLIF \
CLK_OUT_INTreg.BLIF inst_UDS_000_INT.BLIF inst_LDS_000_INT.BLIF \
inst_DSACK1_INT.BLIF IPL_030DFFSH_0_reg.BLIF \
state_machine_un3_clk_out_pre_50_n.BLIF inst_CLK_000_D2.BLIF \
IPL_030DFFSH_1_reg.BLIF inst_CLK_030_H.BLIF inst_DS_000_DMA.BLIF \
IPL_030DFFSH_2_reg.BLIF SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF ipl_c_0__n.BLIF \
inst_A0_DMA.BLIF SM_AMIGA_5_.BLIF ipl_c_1__n.BLIF SM_AMIGA_4_.BLIF \
SM_AMIGA_3_.BLIF ipl_c_2__n.BLIF SM_AMIGA_2_.BLIF DSACK1_c.BLIF RST_c.BLIF \
RESETDFFRHreg.BLIF RW_c.BLIF fc_c_0__n.BLIF CLK_OUT_PRE_25_0.BLIF \
fc_c_1__n.BLIF AMIGA_BUS_DATA_DIR_c.BLIF cpu_est_0_.BLIF \
state_machine_un3_clk_000_d1_i_n.BLIF cpu_est_1_.BLIF \
state_machine_un6_bgack_000_0_n.BLIF cpu_est_2_.BLIF cpu_est_ns_0_1__n.BLIF \
cpu_est_3_reg.BLIF N_159_i.BLIF cpu_estse.BLIF N_158_i.BLIF N_149_i.BLIF \
N_150_i.BLIF N_153_i.BLIF AS_000_DMA_0_sqmuxa.BLIF N_152_i.BLIF \
state_machine_un8_bgack_030_int_n.BLIF N_160_i.BLIF N_92.BLIF N_154_i.BLIF \
state_machine_un49_clk_000_d0_n.BLIF state_machine_un10_clk_000_d0_2_i_n.BLIF \
N_210.BLIF N_156_i.BLIF N_220.BLIF N_157_i.BLIF CLK_030_H_1_sqmuxa.BLIF \
cpu_est_ns_0_2__n.BLIF AS_000_DMA_1_sqmuxa.BLIF \
state_machine_un10_clk_000_d0_i_n.BLIF DS_000_DMA_1_sqmuxa.BLIF \
state_machine_un12_clk_000_d0_0_n.BLIF state_machine_un24_bgack_030_int_n.BLIF \
FPU_CS_INT_1_sqmuxa_i.BLIF state_machine_clk_030_h_2_n.BLIF \
un1_as_030_000_sync8_1_0.BLIF state_machine_clk_030_h_2_f1_n.BLIF \
AS_030_000_SYNC_0_sqmuxa_2_i.BLIF state_machine_ds_000_dma_3_n.BLIF \
un1_as_030_000_sync8_0.BLIF N_87.BLIF un1_SM_AMIGA_12_0.BLIF N_93.BLIF \
state_machine_un3_clk_030_i_n.BLIF N_94.BLIF \
state_machine_un57_clk_000_d0_i_n.BLIF N_88.BLIF \
state_machine_un51_clk_000_d0_i_n.BLIF N_90.BLIF \
state_machine_un53_clk_000_d0_0_n.BLIF N_164_1.BLIF \
state_machine_un3_bgack_030_int_d_i_n.BLIF \
state_machine_un10_bgack_030_int_n.BLIF un1_bgack_030_int_d_0.BLIF \
UDS_000_INT_0_sqmuxa_1.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa_i.BLIF \
UDS_000_INT_0_sqmuxa.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i.BLIF \
state_machine_un25_clk_000_d0_n.BLIF N_86_0.BLIF N_164.BLIF N_101_i.BLIF \
RW_li_m.BLIF N_85_i.BLIF N_181.BLIF N_84_0.BLIF RW_000_i_m.BLIF N_97_i.BLIF \
N_163.BLIF un1_SM_AMIGA_8.BLIF N_96_i.BLIF N_100.BLIF N_95_i.BLIF N_91.BLIF \
sm_amiga_ns_0_5__n.BLIF state_machine_un31_bgack_030_int_n.BLIF N_88_i.BLIF \
state_machine_lds_000_int_7_n.BLIF N_89_i.BLIF \
state_machine_uds_000_int_7_n.BLIF sm_amiga_ns_0_0__n.BLIF \
RW_000_INT_0_sqmuxa_1.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_i.BLIF \
un1_AS_030_2.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i.BLIF N_59.BLIF \
un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0.BLIF un1_bgack_030_int_d.BLIF \
BG_030_c_i.BLIF un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF \
state_machine_un8_bg_030_i_n.BLIF state_machine_un10_bg_030_n.BLIF \
state_machine_un10_bg_030_0_n.BLIF state_machine_un3_bgack_030_int_d_n.BLIF \
state_machine_un5_bgack_030_int_d_i_n.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa.BLIF \
N_59_0.BLIF N_86.BLIF state_machine_un10_bgack_030_int_0_n.BLIF \
AMIGA_BUS_ENABLE_INT_1_sqmuxa_1.BLIF N_181_i.BLIF N_84.BLIF A0_c_i.BLIF \
AMIGA_BUS_ENABLE_INT_1_sqmuxa_2.BLIF state_machine_uds_000_int_7_0_n.BLIF \
state_machine_un8_bg_030_n.BLIF state_machine_lds_000_int_7_0_n.BLIF \
AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF state_machine_size_dma_4_0_0__n.BLIF \
N_89.BLIF state_machine_size_dma_4_0_1__n.BLIF N_95.BLIF N_91_i.BLIF N_96.BLIF \
N_97.BLIF N_100_i.BLIF N_99.BLIF un1_SM_AMIGA_8_0.BLIF \
state_machine_un28_clk_000_d1_n.BLIF N_164_i.BLIF N_101.BLIF N_163_i.BLIF \
un1_SM_AMIGA_12.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF AS_030_000_SYNC_1_sqmuxa.BLIF \
RW_000_i_m_i.BLIF un1_as_030_000_sync8_1.BLIF RW_li_m_i.BLIF \
AS_000_INT_1_sqmuxa.BLIF state_machine_rw_000_int_7_iv_i_n.BLIF \
DSACK1_INT_1_sqmuxa.BLIF size_c_i_1__n.BLIF \
state_machine_un10_clk_000_d0_n.BLIF state_machine_un25_clk_000_d0_i_n.BLIF \
state_machine_un12_clk_000_d0_n.BLIF N_90_i.BLIF \
state_machine_un51_clk_000_d0_n.BLIF state_machine_un53_clk_000_d0_n.BLIF \
N_94_i.BLIF state_machine_un57_clk_000_d0_n.BLIF N_93_i.BLIF \
AS_030_000_SYNC_0_sqmuxa_2.BLIF sm_amiga_ns_0_4__n.BLIF \
AS_030_000_SYNC_0_sqmuxa.BLIF N_87_0.BLIF state_machine_un3_clk_030_n.BLIF \
state_machine_ds_000_dma_3_0_n.BLIF FPU_CS_INT_1_sqmuxa.BLIF CLK_030_H_i.BLIF \
state_machine_un28_clk_030_n.BLIF CLK_030_H_1_sqmuxa_i.BLIF \
un1_as_030_000_sync8.BLIF state_machine_clk_030_h_2_f1_0_n.BLIF N_150.BLIF \
un3_dtack_i.BLIF state_machine_un5_clk_000_d0_n.BLIF N_92_i.BLIF \
state_machine_un3_clk_000_d1_n.BLIF cpu_est_ns_2__n.BLIF un3_dtack_i_1.BLIF \
N_157.BLIF state_machine_un25_clk_000_d0_i_1_n.BLIF N_156.BLIF \
cpu_est_ns_0_1_2__n.BLIF state_machine_un10_clk_000_d0_2_n.BLIF N_210_1.BLIF \
N_154.BLIF N_210_2.BLIF N_160.BLIF N_220_1.BLIF N_152.BLIF N_220_2.BLIF \
N_153.BLIF N_220_3.BLIF N_158.BLIF N_220_4.BLIF N_159.BLIF N_220_5.BLIF \
cpu_est_ns_1__n.BLIF N_220_6.BLIF state_machine_un6_bgack_000_n.BLIF \
DS_000_DMA_1_sqmuxa_1.BLIF AS_030_000_SYNC_i.BLIF \
UDS_000_INT_0_sqmuxa_1_1.BLIF CLK_000_D1_i.BLIF UDS_000_INT_0_sqmuxa_1_2.BLIF \
cpu_est_i_3__n.BLIF UDS_000_INT_0_sqmuxa_1_0.BLIF cpu_est_i_2__n.BLIF \
UDS_000_INT_0_sqmuxa_2.BLIF cpu_est_i_1__n.BLIF N_164_1_0.BLIF \
cpu_est_i_0__n.BLIF RW_li_m_1.BLIF VPA_D_i.BLIF \
AMIGA_BUS_ENABLE_INT_2_sqmuxa_1.BLIF CLK_000_D0_i.BLIF \
AMIGA_BUS_ENABLE_INT_2_sqmuxa_2.BLIF state_machine_un28_clk_030_i_n.BLIF \
N_101_1.BLIF VMA_INT_i.BLIF un1_bgack_030_int_d_0_1.BLIF AS_030_i.BLIF \
state_machine_un8_bg_030_1_n.BLIF AS_030_000_SYNC_0_sqmuxa_i.BLIF \
state_machine_un8_bg_030_2_n.BLIF sm_amiga_i_1__n.BLIF \
state_machine_un57_clk_000_d0_1_n.BLIF DTACK_D0_i.BLIF \
state_machine_un49_clk_000_d0_1_n.BLIF a_i_19__n.BLIF \
AS_030_000_SYNC_0_sqmuxa_1.BLIF a_i_16__n.BLIF \
AS_030_000_SYNC_0_sqmuxa_2_0.BLIF a_i_18__n.BLIF \
state_machine_un28_clk_030_1_n.BLIF state_machine_un5_clk_000_d0_i_0_n.BLIF \
state_machine_un28_clk_030_2_n.BLIF nEXP_SPACE_i.BLIF \
state_machine_un28_clk_030_3_n.BLIF sm_amiga_i_7__n.BLIF \
state_machine_un28_clk_030_4_n.BLIF sm_amiga_i_0__n.BLIF \
state_machine_un28_clk_030_5_n.BLIF N_99_i.BLIF \
state_machine_un5_clk_000_d0_1_n.BLIF sm_amiga_i_2__n.BLIF \
state_machine_un5_clk_000_d0_2_n.BLIF BGACK_030_INT_i.BLIF \
state_machine_un10_clk_000_d0_1_n.BLIF BGACK_030_INT_D_i.BLIF \
state_machine_un10_clk_000_d0_2_0_n.BLIF sm_amiga_i_6__n.BLIF \
state_machine_un10_clk_000_d0_3_n.BLIF UDS_000_i.BLIF cpu_est_ns_0_1_1__n.BLIF \
LDS_000_i.BLIF cpu_est_ns_0_2_1__n.BLIF AS_000_DMA_0_sqmuxa_i.BLIF \
state_machine_un28_clk_000_d1_1_n.BLIF \
state_machine_un8_bgack_030_int_i_n.BLIF cpu_estse_2_un3_n.BLIF \
state_machine_un31_bgack_030_int_i_n.BLIF cpu_estse_2_un1_n.BLIF \
sm_amiga_i_5__n.BLIF cpu_estse_2_un0_n.BLIF RW_i.BLIF cpu_estse_1_un3_n.BLIF \
RW_000_i.BLIF cpu_estse_1_un1_n.BLIF UDS_000_INT_0_sqmuxa_i.BLIF \
cpu_estse_1_un0_n.BLIF UDS_000_INT_0_sqmuxa_1_i.BLIF cpu_estse_0_un3_n.BLIF \
AS_000_i.BLIF cpu_estse_0_un1_n.BLIF DS_030_i.BLIF cpu_estse_0_un0_n.BLIF \
state_machine_un49_clk_000_d0_i_n.BLIF ipl_030_0_2__un3_n.BLIF CLK_030_i.BLIF \
ipl_030_0_2__un1_n.BLIF state_machine_un24_bgack_030_int_i_n.BLIF \
ipl_030_0_2__un0_n.BLIF AS_000_DMA_i.BLIF ipl_030_0_1__un3_n.BLIF \
sm_amiga_i_4__n.BLIF ipl_030_0_1__un1_n.BLIF a_i_30__n.BLIF \
ipl_030_0_1__un0_n.BLIF a_i_31__n.BLIF ipl_030_0_0__un3_n.BLIF a_i_28__n.BLIF \
ipl_030_0_0__un1_n.BLIF a_i_29__n.BLIF ipl_030_0_0__un0_n.BLIF a_i_26__n.BLIF \
bgack_030_int_0_un3_n.BLIF a_i_27__n.BLIF bgack_030_int_0_un1_n.BLIF \
a_i_24__n.BLIF bgack_030_int_0_un0_n.BLIF a_i_25__n.BLIF \
as_030_000_sync_0_un3_n.BLIF RST_i.BLIF as_030_000_sync_0_un1_n.BLIF \
as_030_000_sync_0_un0_n.BLIF FPU_CS_INT_i.BLIF fpu_cs_int_0_un3_n.BLIF \
CLK_OUT_PRE_50_D_i.BLIF fpu_cs_int_0_un1_n.BLIF AS_030_c.BLIF \
fpu_cs_int_0_un0_n.BLIF as_000_int_0_un3_n.BLIF AS_000_c.BLIF \
as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF RW_000_c.BLIF \
dsack1_int_0_un3_n.BLIF dsack1_int_0_un1_n.BLIF DS_030_c.BLIF \
dsack1_int_0_un0_n.BLIF vma_int_0_un3_n.BLIF UDS_000_c.BLIF \
vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF LDS_000_c.BLIF avec_exp_0_un3_n.BLIF \
avec_exp_0_un1_n.BLIF size_c_0__n.BLIF avec_exp_0_un0_n.BLIF \
bg_000_0_un3_n.BLIF size_c_1__n.BLIF bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF \
a_c_16__n.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un1_n.BLIF \
a_c_17__n.BLIF lds_000_int_0_un0_n.BLIF uds_000_int_0_un3_n.BLIF \
a_c_18__n.BLIF uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF \
a_c_19__n.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un1_n.BLIF a_c_20__n.BLIF \
rw_000_int_0_un0_n.BLIF as_000_dma_0_un3_n.BLIF a_c_21__n.BLIF \
as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF a_c_22__n.BLIF \
ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un1_n.BLIF a_c_23__n.BLIF \
ds_000_dma_0_un0_n.BLIF clk_030_h_0_un3_n.BLIF a_c_24__n.BLIF \
clk_030_h_0_un1_n.BLIF clk_030_h_0_un0_n.BLIF a_c_25__n.BLIF a_c_26__n.BLIF \
a_c_27__n.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF DS_030.PIN.BLIF \
UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF \
A0.PIN.BLIF DSACK1.PIN.BLIF DTACK.PIN.BLIF RW.PIN.BLIF
.outputs IPL_030_2_ BERR BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS AVEC \
AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \
CIIN IPL_030_1_ IPL_030_0_ cpu_est_1_.D cpu_est_1_.C cpu_est_1_.AR \
cpu_est_2_.D cpu_est_2_.C cpu_est_2_.AR cpu_est_3_reg.D cpu_est_3_reg.C \
cpu_est_3_reg.AR cpu_est_0_.D cpu_est_0_.C cpu_est_0_.AR IPL_030DFFSH_0_reg.D \
IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP IPL_030DFFSH_1_reg.D \
IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D \
IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D SM_AMIGA_7_.C \
SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.D \
SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_4_.AR \
SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C \
SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.D \
SM_AMIGA_0_.C SM_AMIGA_0_.AR inst_VMA_INTreg.D inst_VMA_INTreg.C \
inst_VMA_INTreg.AP inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C \
inst_BGACK_030_INTreg.AP inst_CLK_OUT_PRE_25.D inst_CLK_OUT_PRE_25.C \
inst_CLK_OUT_PRE_25.AR SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_0_.AP \
SIZE_DMA_1_.D SIZE_DMA_1_.C SIZE_DMA_1_.AP inst_LDS_000_INT.D \
inst_LDS_000_INT.C inst_LDS_000_INT.AP inst_FPU_CS_INTreg.D \
inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP inst_avec_expreg.D \
inst_avec_expreg.C inst_avec_expreg.AP BG_000DFFSHreg.D BG_000DFFSHreg.C \
BG_000DFFSHreg.AP inst_DS_000_DMA.D inst_DS_000_DMA.C inst_DS_000_DMA.AP \
inst_AS_000_DMA.D inst_AS_000_DMA.C inst_AS_000_DMA.AP inst_AS_000_INT.D \
inst_AS_000_INT.C inst_AS_000_INT.AP inst_DSACK1_INT.D inst_DSACK1_INT.C \
inst_DSACK1_INT.AP inst_RW_000_INT.D inst_RW_000_INT.C inst_RW_000_INT.AP \
inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP \
inst_CLK_030_H.D inst_CLK_030_H.C inst_UDS_000_INT.D inst_UDS_000_INT.C \
inst_UDS_000_INT.AP inst_A0_DMA.D inst_A0_DMA.C inst_A0_DMA.AP inst_DTACK_D0.D \
inst_DTACK_D0.C inst_DTACK_D0.AP inst_CLK_000_D2.D inst_CLK_000_D2.C \
inst_CLK_000_D2.AP CLK_OUT_INTreg.D CLK_OUT_INTreg.C CLK_OUT_INTreg.AR \
inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_D1.AP inst_BGACK_030_INT_D.D \
inst_BGACK_030_INT_D.C inst_BGACK_030_INT_D.AP inst_CLK_OUT_PRE_50_D.D \
inst_CLK_OUT_PRE_50_D.C inst_CLK_OUT_PRE_50_D.AR inst_CLK_000_D0.D \
inst_CLK_000_D0.C inst_CLK_000_D0.AP inst_VPA_D.D inst_VPA_D.C inst_VPA_D.AP \
inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_50.AR \
RESETDFFRHreg.D RESETDFFRHreg.C RESETDFFRHreg.AR SIZE_1_ AS_030 AS_000 RW_000 \
DS_030 UDS_000 LDS_000 A0 DSACK1 DTACK RW SIZE_0_ a_c_28__n a_c_29__n \
a_c_30__n a_c_31__n A0_c nEXP_SPACE_c BG_030_c BGACK_000_c CLK_030_c vcc_n_n \
gnd_n_n CLK_000_c CLK_OSZI_c state_machine_un3_clk_out_pre_50_n ipl_c_0__n \
ipl_c_1__n ipl_c_2__n DSACK1_c RST_c RW_c fc_c_0__n fc_c_1__n \
AMIGA_BUS_DATA_DIR_c state_machine_un3_clk_000_d1_i_n \
state_machine_un6_bgack_000_0_n cpu_est_ns_0_1__n N_159_i N_158_i N_149_i \
N_150_i N_153_i AS_000_DMA_0_sqmuxa N_152_i state_machine_un8_bgack_030_int_n \
N_160_i N_92 N_154_i state_machine_un49_clk_000_d0_n \
state_machine_un10_clk_000_d0_2_i_n N_210 N_156_i N_220 N_157_i \
CLK_030_H_1_sqmuxa cpu_est_ns_0_2__n AS_000_DMA_1_sqmuxa \
state_machine_un10_clk_000_d0_i_n DS_000_DMA_1_sqmuxa \
state_machine_un12_clk_000_d0_0_n state_machine_un24_bgack_030_int_n \
FPU_CS_INT_1_sqmuxa_i state_machine_clk_030_h_2_n un1_as_030_000_sync8_1_0 \
state_machine_clk_030_h_2_f1_n AS_030_000_SYNC_0_sqmuxa_2_i \
state_machine_ds_000_dma_3_n un1_as_030_000_sync8_0 N_87 un1_SM_AMIGA_12_0 \
N_93 state_machine_un3_clk_030_i_n N_94 state_machine_un57_clk_000_d0_i_n N_88 \
state_machine_un51_clk_000_d0_i_n N_90 state_machine_un53_clk_000_d0_0_n \
N_164_1 state_machine_un3_bgack_030_int_d_i_n \
state_machine_un10_bgack_030_int_n un1_bgack_030_int_d_0 \
UDS_000_INT_0_sqmuxa_1 AMIGA_BUS_ENABLE_INT_3_sqmuxa_i UDS_000_INT_0_sqmuxa \
AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i state_machine_un25_clk_000_d0_n N_86_0 N_164 \
N_101_i RW_li_m N_85_i N_181 N_84_0 RW_000_i_m N_97_i N_163 un1_SM_AMIGA_8 \
N_96_i N_100 N_95_i N_91 sm_amiga_ns_0_5__n state_machine_un31_bgack_030_int_n \
N_88_i state_machine_lds_000_int_7_n N_89_i state_machine_uds_000_int_7_n \
sm_amiga_ns_0_0__n RW_000_INT_0_sqmuxa_1 AMIGA_BUS_ENABLE_INT_2_sqmuxa_i \
un1_AS_030_2 AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i N_59 \
un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0 un1_bgack_030_int_d BG_030_c_i \
un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa state_machine_un8_bg_030_i_n \
state_machine_un10_bg_030_n state_machine_un10_bg_030_0_n \
state_machine_un3_bgack_030_int_d_n state_machine_un5_bgack_030_int_d_i_n \
AMIGA_BUS_ENABLE_INT_3_sqmuxa N_59_0 N_86 state_machine_un10_bgack_030_int_0_n \
AMIGA_BUS_ENABLE_INT_1_sqmuxa_1 N_181_i N_84 A0_c_i \
AMIGA_BUS_ENABLE_INT_1_sqmuxa_2 state_machine_uds_000_int_7_0_n \
state_machine_un8_bg_030_n state_machine_lds_000_int_7_0_n \
AMIGA_BUS_ENABLE_INT_2_sqmuxa state_machine_size_dma_4_0_0__n N_89 \
state_machine_size_dma_4_0_1__n N_95 N_91_i N_96 N_97 N_100_i N_99 \
un1_SM_AMIGA_8_0 state_machine_un28_clk_000_d1_n N_164_i N_101 N_163_i \
un1_SM_AMIGA_12 AMIGA_BUS_DATA_DIR_c_0 AS_030_000_SYNC_1_sqmuxa RW_000_i_m_i \
un1_as_030_000_sync8_1 RW_li_m_i AS_000_INT_1_sqmuxa \
state_machine_rw_000_int_7_iv_i_n DSACK1_INT_1_sqmuxa size_c_i_1__n \
state_machine_un10_clk_000_d0_n state_machine_un25_clk_000_d0_i_n \
state_machine_un12_clk_000_d0_n N_90_i state_machine_un51_clk_000_d0_n \
state_machine_un53_clk_000_d0_n N_94_i state_machine_un57_clk_000_d0_n N_93_i \
AS_030_000_SYNC_0_sqmuxa_2 sm_amiga_ns_0_4__n AS_030_000_SYNC_0_sqmuxa N_87_0 \
state_machine_un3_clk_030_n state_machine_ds_000_dma_3_0_n FPU_CS_INT_1_sqmuxa \
CLK_030_H_i state_machine_un28_clk_030_n CLK_030_H_1_sqmuxa_i \
un1_as_030_000_sync8 state_machine_clk_030_h_2_f1_0_n N_150 un3_dtack_i \
state_machine_un5_clk_000_d0_n N_92_i state_machine_un3_clk_000_d1_n \
cpu_est_ns_2__n un3_dtack_i_1 N_157 state_machine_un25_clk_000_d0_i_1_n N_156 \
cpu_est_ns_0_1_2__n state_machine_un10_clk_000_d0_2_n N_210_1 N_154 N_210_2 \
N_160 N_220_1 N_152 N_220_2 N_153 N_220_3 N_158 N_220_4 N_159 N_220_5 \
cpu_est_ns_1__n N_220_6 state_machine_un6_bgack_000_n DS_000_DMA_1_sqmuxa_1 \
AS_030_000_SYNC_i UDS_000_INT_0_sqmuxa_1_1 CLK_000_D1_i \
UDS_000_INT_0_sqmuxa_1_2 cpu_est_i_3__n UDS_000_INT_0_sqmuxa_1_0 \
cpu_est_i_2__n UDS_000_INT_0_sqmuxa_2 cpu_est_i_1__n N_164_1_0 cpu_est_i_0__n \
RW_li_m_1 VPA_D_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 CLK_000_D0_i \
AMIGA_BUS_ENABLE_INT_2_sqmuxa_2 state_machine_un28_clk_030_i_n N_101_1 \
VMA_INT_i un1_bgack_030_int_d_0_1 AS_030_i state_machine_un8_bg_030_1_n \
AS_030_000_SYNC_0_sqmuxa_i state_machine_un8_bg_030_2_n sm_amiga_i_1__n \
state_machine_un57_clk_000_d0_1_n DTACK_D0_i state_machine_un49_clk_000_d0_1_n \
a_i_19__n AS_030_000_SYNC_0_sqmuxa_1 a_i_16__n AS_030_000_SYNC_0_sqmuxa_2_0 \
a_i_18__n state_machine_un28_clk_030_1_n state_machine_un5_clk_000_d0_i_0_n \
state_machine_un28_clk_030_2_n nEXP_SPACE_i state_machine_un28_clk_030_3_n \
sm_amiga_i_7__n state_machine_un28_clk_030_4_n sm_amiga_i_0__n \
state_machine_un28_clk_030_5_n N_99_i state_machine_un5_clk_000_d0_1_n \
sm_amiga_i_2__n state_machine_un5_clk_000_d0_2_n BGACK_030_INT_i \
state_machine_un10_clk_000_d0_1_n BGACK_030_INT_D_i \
state_machine_un10_clk_000_d0_2_0_n sm_amiga_i_6__n \
state_machine_un10_clk_000_d0_3_n UDS_000_i cpu_est_ns_0_1_1__n LDS_000_i \
cpu_est_ns_0_2_1__n AS_000_DMA_0_sqmuxa_i state_machine_un28_clk_000_d1_1_n \
state_machine_un8_bgack_030_int_i_n cpu_estse_2_un3_n \
state_machine_un31_bgack_030_int_i_n cpu_estse_2_un1_n sm_amiga_i_5__n \
cpu_estse_2_un0_n RW_i cpu_estse_1_un3_n RW_000_i cpu_estse_1_un1_n \
UDS_000_INT_0_sqmuxa_i cpu_estse_1_un0_n UDS_000_INT_0_sqmuxa_1_i \
cpu_estse_0_un3_n AS_000_i cpu_estse_0_un1_n DS_030_i cpu_estse_0_un0_n \
state_machine_un49_clk_000_d0_i_n ipl_030_0_2__un3_n CLK_030_i \
ipl_030_0_2__un1_n state_machine_un24_bgack_030_int_i_n ipl_030_0_2__un0_n \
AS_000_DMA_i ipl_030_0_1__un3_n sm_amiga_i_4__n ipl_030_0_1__un1_n a_i_30__n \
ipl_030_0_1__un0_n a_i_31__n ipl_030_0_0__un3_n a_i_28__n ipl_030_0_0__un1_n \
a_i_29__n ipl_030_0_0__un0_n a_i_26__n bgack_030_int_0_un3_n a_i_27__n \
bgack_030_int_0_un1_n a_i_24__n bgack_030_int_0_un0_n a_i_25__n \
as_030_000_sync_0_un3_n RST_i as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n \
FPU_CS_INT_i fpu_cs_int_0_un3_n CLK_OUT_PRE_50_D_i fpu_cs_int_0_un1_n AS_030_c \
fpu_cs_int_0_un0_n as_000_int_0_un3_n AS_000_c as_000_int_0_un1_n \
as_000_int_0_un0_n RW_000_c dsack1_int_0_un3_n dsack1_int_0_un1_n DS_030_c \
dsack1_int_0_un0_n vma_int_0_un3_n UDS_000_c vma_int_0_un1_n vma_int_0_un0_n \
LDS_000_c avec_exp_0_un3_n avec_exp_0_un1_n size_c_0__n avec_exp_0_un0_n \
bg_000_0_un3_n size_c_1__n bg_000_0_un1_n bg_000_0_un0_n a_c_16__n \
lds_000_int_0_un3_n lds_000_int_0_un1_n a_c_17__n lds_000_int_0_un0_n \
uds_000_int_0_un3_n a_c_18__n uds_000_int_0_un1_n uds_000_int_0_un0_n \
a_c_19__n rw_000_int_0_un3_n rw_000_int_0_un1_n a_c_20__n rw_000_int_0_un0_n \
as_000_dma_0_un3_n a_c_21__n as_000_dma_0_un1_n as_000_dma_0_un0_n a_c_22__n \
ds_000_dma_0_un3_n ds_000_dma_0_un1_n a_c_23__n ds_000_dma_0_un0_n \
clk_030_h_0_un3_n a_c_24__n clk_030_h_0_un1_n clk_030_h_0_un0_n a_c_25__n \
a_c_26__n a_c_27__n AS_030.OE AS_000.OE RW_000.OE DS_030.OE UDS_000.OE \
LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE DSACK1.OE DTACK.OE RW.OE BERR.OE \
CIIN.OE CLK_OUT_PRE_25_0 cpu_estse
.names cpu_estse_0_un1_n.BLIF cpu_estse_0_un0_n.BLIF cpu_est_1_.D
1- 1
-1 1
.names cpu_estse_1_un1_n.BLIF cpu_estse_1_un0_n.BLIF cpu_est_2_.D
1- 1
-1 1
.names cpu_estse_2_un1_n.BLIF cpu_estse_2_un0_n.BLIF cpu_est_3_reg.D
1- 1
-1 1
.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF IPL_030DFFSH_0_reg.D
1- 1
-1 1
.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF IPL_030DFFSH_1_reg.D
1- 1
-1 1
.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF IPL_030DFFSH_2_reg.D
1- 1
-1 1
.names sm_amiga_ns_0_0__n.BLIF SM_AMIGA_7_.D
0 1
.names N_88_i.BLIF N_90_i.BLIF SM_AMIGA_6_.D
11 1
.names inst_CLK_000_D0.BLIF N_91_i.BLIF SM_AMIGA_5_.D
11 1
.names CLK_000_D0_i.BLIF N_92_i.BLIF SM_AMIGA_4_.D
11 1
.names sm_amiga_ns_0_4__n.BLIF SM_AMIGA_3_.D
0 1
.names sm_amiga_ns_0_5__n.BLIF SM_AMIGA_2_.D
0 1
.names inst_CLK_000_D0.BLIF N_97_i.BLIF SM_AMIGA_1_.D
11 1
.names CLK_000_D0_i.BLIF N_86.BLIF SM_AMIGA_0_.D
11 1
.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D
1- 1
-1 1
.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF \
inst_BGACK_030_INTreg.D
1- 1
-1 1
.names state_machine_size_dma_4_0_0__n.BLIF SIZE_DMA_0_.D
0 1
.names state_machine_size_dma_4_0_1__n.BLIF SIZE_DMA_1_.D
0 1
.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF inst_LDS_000_INT.D
1- 1
-1 1
.names fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF inst_FPU_CS_INTreg.D
1- 1
-1 1
.names avec_exp_0_un1_n.BLIF avec_exp_0_un0_n.BLIF inst_avec_expreg.D
1- 1
-1 1
.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF BG_000DFFSHreg.D
1- 1
-1 1
.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF inst_DS_000_DMA.D
1- 1
-1 1
.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF inst_AS_000_DMA.D
1- 1
-1 1
.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF inst_AS_000_INT.D
1- 1
-1 1
.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF inst_DSACK1_INT.D
1- 1
-1 1
.names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF inst_RW_000_INT.D
1- 1
-1 1
.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF \
inst_AS_030_000_SYNC.D
1- 1
-1 1
.names clk_030_h_0_un1_n.BLIF clk_030_h_0_un0_n.BLIF inst_CLK_030_H.D
1- 1
-1 1
.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INT.D
1- 1
-1 1
.names UDS_000_c.BLIF state_machine_un8_bgack_030_int_n.BLIF inst_A0_DMA.D
11 1
.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D
0 1
.names vcc_n_n
 1
.names gnd_n_n
.names inst_CLK_OUT_PRE_50.BLIF CLK_OUT_PRE_50_D_i.BLIF \
state_machine_un3_clk_out_pre_50_n
11 1
.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c
0 1
.names state_machine_un3_clk_000_d1_n.BLIF state_machine_un3_clk_000_d1_i_n
0 1
.names BGACK_000_c.BLIF state_machine_un3_clk_000_d1_i_n.BLIF \
state_machine_un6_bgack_000_0_n
11 1
.names cpu_est_ns_0_1_1__n.BLIF cpu_est_ns_0_2_1__n.BLIF cpu_est_ns_0_1__n
11 1
.names N_159.BLIF N_159_i
0 1
.names N_158.BLIF N_158_i
0 1
.names N_158_i.BLIF N_159_i.BLIF N_149_i
11 1
.names cpu_est_3_reg.BLIF cpu_est_i_1__n.BLIF N_150_i
11 1
.names N_153.BLIF N_153_i
0 1
.names CLK_030_i.BLIF state_machine_un8_bgack_030_int_n.BLIF \
AS_000_DMA_0_sqmuxa
11 1
.names N_152.BLIF N_152_i
0 1
.names N_164_1.BLIF state_machine_un10_bgack_030_int_n.BLIF \
state_machine_un8_bgack_030_int_n
11 1
.names N_160.BLIF N_160_i
0 1
.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_92
11 1
.names N_154.BLIF N_154_i
0 1
.names state_machine_un49_clk_000_d0_1_n.BLIF \
state_machine_un53_clk_000_d0_n.BLIF state_machine_un49_clk_000_d0_n
11 1
.names state_machine_un10_clk_000_d0_2_n.BLIF \
state_machine_un10_clk_000_d0_2_i_n
0 1
.names N_210_1.BLIF N_210_2.BLIF N_210
11 1
.names N_156.BLIF N_156_i
0 1
.names N_220_5.BLIF N_220_6.BLIF N_220
11 1
.names N_157.BLIF N_157_i
0 1
.names AS_000_DMA_i.BLIF CLK_030_c.BLIF CLK_030_H_1_sqmuxa
11 1
.names cpu_est_ns_0_1_2__n.BLIF state_machine_un10_clk_000_d0_2_i_n.BLIF \
cpu_est_ns_0_2__n
11 1
.names CLK_030_c.BLIF state_machine_un8_bgack_030_int_n.BLIF \
AS_000_DMA_1_sqmuxa
11 1
.names state_machine_un10_clk_000_d0_n.BLIF state_machine_un10_clk_000_d0_i_n
0 1
.names DS_000_DMA_1_sqmuxa_1.BLIF state_machine_un24_bgack_030_int_i_n.BLIF \
DS_000_DMA_1_sqmuxa
11 1
.names state_machine_un5_clk_000_d0_i_0_n.BLIF \
state_machine_un10_clk_000_d0_i_n.BLIF state_machine_un12_clk_000_d0_0_n
11 1
.names inst_CLK_030_H.BLIF CLK_030_i.BLIF state_machine_un24_bgack_030_int_n
11 1
.names FPU_CS_INT_1_sqmuxa.BLIF FPU_CS_INT_1_sqmuxa_i
0 1
.names state_machine_clk_030_h_2_f1_n.BLIF \
state_machine_un8_bgack_030_int_n.BLIF state_machine_clk_030_h_2_n
11 1
.names FPU_CS_INT_1_sqmuxa_i.BLIF state_machine_un3_clk_030_n.BLIF \
un1_as_030_000_sync8_1_0
11 1
.names state_machine_clk_030_h_2_f1_0_n.BLIF state_machine_clk_030_h_2_f1_n
0 1
.names AS_030_000_SYNC_0_sqmuxa_2.BLIF AS_030_000_SYNC_0_sqmuxa_2_i
0 1
.names state_machine_ds_000_dma_3_0_n.BLIF state_machine_ds_000_dma_3_n
0 1
.names AS_030_000_SYNC_0_sqmuxa_2_i.BLIF state_machine_un3_clk_030_n.BLIF \
un1_as_030_000_sync8_0
11 1
.names N_87_0.BLIF N_87
0 1
.names AS_030_i.BLIF N_85_i.BLIF un1_SM_AMIGA_12_0
11 1
.names inst_CLK_000_D0.BLIF SM_AMIGA_4_.BLIF N_93
11 1
.names AS_030_i.BLIF CLK_030_i.BLIF state_machine_un3_clk_030_i_n
11 1
.names SM_AMIGA_3_.BLIF state_machine_un49_clk_000_d0_i_n.BLIF N_94
11 1
.names state_machine_un57_clk_000_d0_n.BLIF state_machine_un57_clk_000_d0_i_n
0 1
.names N_84.BLIF SM_AMIGA_7_.BLIF N_88
11 1
.names state_machine_un51_clk_000_d0_n.BLIF state_machine_un51_clk_000_d0_i_n
0 1
.names N_87.BLIF sm_amiga_i_7__n.BLIF N_90
11 1
.names state_machine_un51_clk_000_d0_i_n.BLIF \
state_machine_un57_clk_000_d0_i_n.BLIF state_machine_un53_clk_000_d0_0_n
11 1
.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_164_1
11 1
.names state_machine_un3_bgack_030_int_d_n.BLIF \
state_machine_un3_bgack_030_int_d_i_n
0 1
.names state_machine_un10_bgack_030_int_0_n.BLIF \
state_machine_un10_bgack_030_int_n
0 1
.names un1_bgack_030_int_d_0_1.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa_i.BLIF \
un1_bgack_030_int_d_0
11 1
.names UDS_000_INT_0_sqmuxa_1_1.BLIF UDS_000_INT_0_sqmuxa_1_2.BLIF \
UDS_000_INT_0_sqmuxa_1
11 1
.names AMIGA_BUS_ENABLE_INT_3_sqmuxa.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa_i
0 1
.names UDS_000_INT_0_sqmuxa_1_0.BLIF UDS_000_INT_0_sqmuxa_2.BLIF \
UDS_000_INT_0_sqmuxa
11 1
.names AMIGA_BUS_ENABLE_INT_1_sqmuxa_1.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i
0 1
.names state_machine_un25_clk_000_d0_i_n.BLIF state_machine_un25_clk_000_d0_n
0 1
.names sm_amiga_i_0__n.BLIF sm_amiga_i_1__n.BLIF N_86_0
11 1
.names N_164_1_0.BLIF nEXP_SPACE_i.BLIF N_164
11 1
.names N_101.BLIF N_101_i
0 1
.names RW_li_m_1.BLIF SM_AMIGA_6_.BLIF RW_li_m
11 1
.names N_101_i.BLIF sm_amiga_i_1__n.BLIF N_85_i
11 1
.names UDS_000_INT_0_sqmuxa_1_i.BLIF UDS_000_INT_0_sqmuxa_i.BLIF N_181
11 1
.names nEXP_SPACE_c.BLIF state_machine_un28_clk_000_d1_n.BLIF N_84_0
11 1
.names AS_000_DMA_0_sqmuxa.BLIF RW_000_i.BLIF RW_000_i_m
11 1
.names N_97.BLIF N_97_i
0 1
.names inst_BGACK_030_INTreg.BLIF RW_i.BLIF N_163
11 1
.names un1_SM_AMIGA_8_0.BLIF un1_SM_AMIGA_8
0 1
.names N_96.BLIF N_96_i
0 1
.names sm_amiga_i_0__n.BLIF sm_amiga_i_6__n.BLIF N_100
11 1
.names N_95.BLIF N_95_i
0 1
.names sm_amiga_i_5__n.BLIF sm_amiga_i_6__n.BLIF N_91
11 1
.names N_95_i.BLIF N_96_i.BLIF sm_amiga_ns_0_5__n
11 1
.names LDS_000_i.BLIF UDS_000_i.BLIF state_machine_un31_bgack_030_int_n
11 1
.names N_88.BLIF N_88_i
0 1
.names state_machine_lds_000_int_7_0_n.BLIF state_machine_lds_000_int_7_n
0 1
.names N_89.BLIF N_89_i
0 1
.names state_machine_uds_000_int_7_0_n.BLIF state_machine_uds_000_int_7_n
0 1
.names N_88_i.BLIF N_89_i.BLIF sm_amiga_ns_0_0__n
11 1
.names AS_000_DMA_0_sqmuxa_i.BLIF un1_SM_AMIGA_8.BLIF RW_000_INT_0_sqmuxa_1
11 1
.names AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_i
0 1
.names AS_030_i.BLIF N_181.BLIF un1_AS_030_2
11 1
.names AMIGA_BUS_ENABLE_INT_1_sqmuxa_2.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i
0 1
.names N_59_0.BLIF N_59
0 1
.names AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i.BLIF \
AMIGA_BUS_ENABLE_INT_2_sqmuxa_i.BLIF un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0
11 1
.names un1_bgack_030_int_d_0.BLIF un1_bgack_030_int_d
0 1
.names BG_030_c.BLIF BG_030_c_i
0 1
.names un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0.BLIF \
un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa
0 1
.names state_machine_un8_bg_030_n.BLIF state_machine_un8_bg_030_i_n
0 1
.names state_machine_un10_bg_030_0_n.BLIF state_machine_un10_bg_030_n
0 1
.names BG_030_c_i.BLIF state_machine_un8_bg_030_i_n.BLIF \
state_machine_un10_bg_030_0_n
11 1
.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_D_i.BLIF \
state_machine_un3_bgack_030_int_d_n
11 1
.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \
state_machine_un5_bgack_030_int_d_i_n
11 1
.names N_86.BLIF state_machine_un5_bgack_030_int_d_i_n.BLIF \
AMIGA_BUS_ENABLE_INT_3_sqmuxa
11 1
.names inst_CLK_000_D0.BLIF SM_AMIGA_6_.BLIF N_59_0
11 1
.names N_86_0.BLIF N_86
0 1
.names LDS_000_c.BLIF UDS_000_c.BLIF state_machine_un10_bgack_030_int_0_n
11 1
.names inst_BGACK_030_INTreg.BLIF N_84.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1
11 1
.names N_181.BLIF N_181_i
0 1
.names N_84_0.BLIF N_84
0 1
.names A0_c.BLIF A0_c_i
0 1
.names AMIGA_BUS_ENABLE_INT_3_sqmuxa.BLIF AS_030_i.BLIF \
AMIGA_BUS_ENABLE_INT_1_sqmuxa_2
11 1
.names A0_c_i.BLIF N_181_i.BLIF state_machine_uds_000_int_7_0_n
11 1
.names state_machine_un8_bg_030_1_n.BLIF state_machine_un8_bg_030_2_n.BLIF \
state_machine_un8_bg_030_n
11 1
.names N_181_i.BLIF state_machine_un25_clk_000_d0_n.BLIF \
state_machine_lds_000_int_7_0_n
11 1
.names AMIGA_BUS_ENABLE_INT_2_sqmuxa_1.BLIF \
AMIGA_BUS_ENABLE_INT_2_sqmuxa_2.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa
11 1
.names state_machine_un8_bgack_030_int_n.BLIF \
state_machine_un31_bgack_030_int_n.BLIF state_machine_size_dma_4_0_0__n
11 1
.names inst_CLK_000_D0.BLIF SM_AMIGA_0_.BLIF N_89
11 1
.names state_machine_un8_bgack_030_int_n.BLIF \
state_machine_un31_bgack_030_int_i_n.BLIF state_machine_size_dma_4_0_1__n
11 1
.names CLK_000_D0_i.BLIF SM_AMIGA_2_.BLIF N_95
11 1
.names N_91.BLIF N_91_i
0 1
.names SM_AMIGA_3_.BLIF state_machine_un49_clk_000_d0_n.BLIF N_96
11 1
.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_97
11 1
.names N_100.BLIF N_100_i
0 1
.names CLK_000_D0_i.BLIF SM_AMIGA_1_.BLIF N_99
11 1
.names inst_CLK_000_D0.BLIF N_100_i.BLIF un1_SM_AMIGA_8_0
11 1
.names state_machine_un28_clk_000_d1_1_n.BLIF CLK_000_D1_i.BLIF \
state_machine_un28_clk_000_d1_n
11 1
.names N_164.BLIF N_164_i
0 1
.names N_101_1.BLIF state_machine_un28_clk_000_d1_n.BLIF N_101
11 1
.names N_163.BLIF N_163_i
0 1
.names un1_SM_AMIGA_12_0.BLIF un1_SM_AMIGA_12
0 1
.names N_163_i.BLIF N_164_i.BLIF AMIGA_BUS_DATA_DIR_c_0
11 1
.names N_85_i.BLIF un1_as_030_000_sync8.BLIF AS_030_000_SYNC_1_sqmuxa
11 1
.names RW_000_i_m.BLIF RW_000_i_m_i
0 1
.names un1_as_030_000_sync8_1_0.BLIF un1_as_030_000_sync8_1
0 1
.names RW_li_m.BLIF RW_li_m_i
0 1
.names AS_030_i.BLIF N_59.BLIF AS_000_INT_1_sqmuxa
11 1
.names RW_000_i_m_i.BLIF RW_li_m_i.BLIF state_machine_rw_000_int_7_iv_i_n
11 1
.names AS_030_i.BLIF sm_amiga_i_1__n.BLIF DSACK1_INT_1_sqmuxa
11 1
.names size_c_1__n.BLIF size_c_i_1__n
0 1
.names state_machine_un10_clk_000_d0_3_n.BLIF cpu_est_i_3__n.BLIF \
state_machine_un10_clk_000_d0_n
11 1
.names state_machine_un25_clk_000_d0_i_1_n.BLIF size_c_i_1__n.BLIF \
state_machine_un25_clk_000_d0_i_n
11 1
.names state_machine_un12_clk_000_d0_0_n.BLIF state_machine_un12_clk_000_d0_n
0 1
.names N_90.BLIF N_90_i
0 1
.names DTACK_D0_i.BLIF inst_VPA_D.BLIF state_machine_un51_clk_000_d0_n
11 1
.names state_machine_un53_clk_000_d0_0_n.BLIF state_machine_un53_clk_000_d0_n
0 1
.names N_94.BLIF N_94_i
0 1
.names state_machine_un57_clk_000_d0_1_n.BLIF VMA_INT_i.BLIF \
state_machine_un57_clk_000_d0_n
11 1
.names N_93.BLIF N_93_i
0 1
.names AS_030_000_SYNC_0_sqmuxa_i.BLIF AS_030_i.BLIF \
AS_030_000_SYNC_0_sqmuxa_2
11 1
.names N_93_i.BLIF N_94_i.BLIF sm_amiga_ns_0_4__n
11 1
.names AS_030_000_SYNC_0_sqmuxa_1.BLIF AS_030_000_SYNC_0_sqmuxa_2_0.BLIF \
AS_030_000_SYNC_0_sqmuxa
11 1
.names CLK_000_D0_i.BLIF SM_AMIGA_6_.BLIF N_87_0
11 1
.names state_machine_un3_clk_030_i_n.BLIF state_machine_un3_clk_030_n
0 1
.names AS_000_DMA_i.BLIF state_machine_un8_bgack_030_int_n.BLIF \
state_machine_ds_000_dma_3_0_n
11 1
.names AS_030_i.BLIF state_machine_un28_clk_030_i_n.BLIF FPU_CS_INT_1_sqmuxa
11 1
.names inst_CLK_030_H.BLIF CLK_030_H_i
0 1
.names state_machine_un28_clk_030_4_n.BLIF state_machine_un28_clk_030_5_n.BLIF \
state_machine_un28_clk_030_n
11 1
.names CLK_030_H_1_sqmuxa.BLIF CLK_030_H_1_sqmuxa_i
0 1
.names un1_as_030_000_sync8_0.BLIF un1_as_030_000_sync8
0 1
.names CLK_030_H_1_sqmuxa_i.BLIF CLK_030_H_i.BLIF \
state_machine_clk_030_h_2_f1_0_n
11 1
.names N_150_i.BLIF N_150
0 1
.names un3_dtack_i_1.BLIF BGACK_030_INT_i.BLIF un3_dtack_i
11 1
.names state_machine_un5_clk_000_d0_1_n.BLIF \
state_machine_un5_clk_000_d0_2_n.BLIF state_machine_un5_clk_000_d0_n
11 1
.names N_92.BLIF N_92_i
0 1
.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF state_machine_un3_clk_000_d1_n
11 1
.names cpu_est_ns_0_2__n.BLIF cpu_est_ns_2__n
0 1
.names nEXP_SPACE_i.BLIF AS_000_DMA_i.BLIF un3_dtack_i_1
11 1
.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_157
11 1
.names size_c_0__n.BLIF A0_c_i.BLIF state_machine_un25_clk_000_d0_i_1_n
11 1
.names cpu_est_0_.BLIF cpu_est_3_reg.BLIF N_156
11 1
.names N_157_i.BLIF N_156_i.BLIF cpu_est_ns_0_1_2__n
11 1
.names cpu_est_1_.BLIF cpu_est_2_.BLIF state_machine_un10_clk_000_d0_2_n
11 1
.names a_c_20__n.BLIF a_c_21__n.BLIF N_210_1
11 1
.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_154
11 1
.names a_c_22__n.BLIF a_c_23__n.BLIF N_210_2
11 1
.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_160
11 1
.names a_i_24__n.BLIF a_i_25__n.BLIF N_220_1
11 1
.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_152
11 1
.names a_i_26__n.BLIF a_i_27__n.BLIF N_220_2
11 1
.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF N_153
11 1
.names a_i_28__n.BLIF a_i_29__n.BLIF N_220_3
11 1
.names N_150.BLIF cpu_est_2_.BLIF N_158
11 1
.names a_i_30__n.BLIF a_i_31__n.BLIF N_220_4
11 1
.names N_160.BLIF cpu_est_i_3__n.BLIF N_159
11 1
.names N_220_1.BLIF N_220_2.BLIF N_220_5
11 1
.names cpu_est_ns_0_1__n.BLIF cpu_est_ns_1__n
0 1
.names N_220_3.BLIF N_220_4.BLIF N_220_6
11 1
.names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n
0 1
.names RW_000_i.BLIF state_machine_un8_bgack_030_int_n.BLIF \
DS_000_DMA_1_sqmuxa_1
11 1
.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i
0 1
.names CLK_000_D0_i.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_1
11 1
.names inst_CLK_000_D1.BLIF CLK_000_D1_i
0 1
.names RW_i.BLIF SM_AMIGA_5_.BLIF UDS_000_INT_0_sqmuxa_1_2
11 1
.names cpu_est_3_reg.BLIF cpu_est_i_3__n
0 1
.names inst_CLK_000_D0.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_0
11 1
.names cpu_est_2_.BLIF cpu_est_i_2__n
0 1
.names RW_c.BLIF SM_AMIGA_6_.BLIF UDS_000_INT_0_sqmuxa_2
11 1
.names cpu_est_1_.BLIF cpu_est_i_1__n
0 1
.names N_164_1.BLIF RW_c.BLIF N_164_1_0
11 1
.names cpu_est_0_.BLIF cpu_est_i_0__n
0 1
.names AS_000_DMA_0_sqmuxa_i.BLIF RW_i.BLIF RW_li_m_1
11 1
.names inst_VPA_D.BLIF VPA_D_i
0 1
.names N_99_i.BLIF sm_amiga_i_0__n.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_1
11 1
.names inst_CLK_000_D0.BLIF CLK_000_D0_i
0 1
.names sm_amiga_i_7__n.BLIF state_machine_un5_bgack_030_int_d_i_n.BLIF \
AMIGA_BUS_ENABLE_INT_2_sqmuxa_2
11 1
.names state_machine_un28_clk_030_n.BLIF state_machine_un28_clk_030_i_n
0 1
.names SM_AMIGA_7_.BLIF nEXP_SPACE_i.BLIF N_101_1
11 1
.names inst_VMA_INTreg.BLIF VMA_INT_i
0 1
.names state_machine_un3_bgack_030_int_d_i_n.BLIF \
AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i.BLIF un1_bgack_030_int_d_0_1
11 1
.names AS_030_c.BLIF AS_030_i
0 1
.names AS_030_c.BLIF CLK_000_c.BLIF state_machine_un8_bg_030_1_n
11 1
.names AS_030_000_SYNC_0_sqmuxa.BLIF AS_030_000_SYNC_0_sqmuxa_i
0 1
.names SM_AMIGA_7_.BLIF nEXP_SPACE_c.BLIF state_machine_un8_bg_030_2_n
11 1
.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n
0 1
.names VPA_D_i.BLIF N_150_i.BLIF state_machine_un57_clk_000_d0_1_n
11 1
.names inst_DTACK_D0.BLIF DTACK_D0_i
0 1
.names CLK_000_D0_i.BLIF inst_CLK_000_D1.BLIF \
state_machine_un49_clk_000_d0_1_n
11 1
.names a_c_19__n.BLIF a_i_19__n
0 1
.names inst_BGACK_030_INTreg.BLIF SM_AMIGA_7_.BLIF AS_030_000_SYNC_0_sqmuxa_1
11 1
.names a_c_16__n.BLIF a_i_16__n
0 1
.names nEXP_SPACE_c.BLIF state_machine_un28_clk_030_i_n.BLIF \
AS_030_000_SYNC_0_sqmuxa_2_0
11 1
.names a_c_18__n.BLIF a_i_18__n
0 1
.names a_c_17__n.BLIF a_i_16__n.BLIF state_machine_un28_clk_030_1_n
11 1
.names state_machine_un5_clk_000_d0_n.BLIF state_machine_un5_clk_000_d0_i_0_n
0 1
.names a_i_18__n.BLIF a_i_19__n.BLIF state_machine_un28_clk_030_2_n
11 1
.names nEXP_SPACE_c.BLIF nEXP_SPACE_i
0 1
.names fc_c_1__n.BLIF BGACK_000_c.BLIF state_machine_un28_clk_030_3_n
11 1
.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n
0 1
.names state_machine_un28_clk_030_1_n.BLIF state_machine_un28_clk_030_2_n.BLIF \
state_machine_un28_clk_030_4_n
11 1
.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n
0 1
.names state_machine_un28_clk_030_3_n.BLIF fc_c_0__n.BLIF \
state_machine_un28_clk_030_5_n
11 1
.names N_99.BLIF N_99_i
0 1
.names CLK_000_D0_i.BLIF VPA_D_i.BLIF state_machine_un5_clk_000_d0_1_n
11 1
.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n
0 1
.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF state_machine_un5_clk_000_d0_2_n
11 1
.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i
0 1
.names state_machine_un10_clk_000_d0_2_n.BLIF inst_AS_000_INT.BLIF \
state_machine_un10_clk_000_d0_1_n
11 1
.names inst_BGACK_030_INT_D.BLIF BGACK_030_INT_D_i
0 1
.names inst_CLK_000_D0.BLIF cpu_est_i_0__n.BLIF \
state_machine_un10_clk_000_d0_2_0_n
11 1
.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n
0 1
.names state_machine_un10_clk_000_d0_1_n.BLIF \
state_machine_un10_clk_000_d0_2_0_n.BLIF state_machine_un10_clk_000_d0_3_n
11 1
.names UDS_000_c.BLIF UDS_000_i
0 1
.names N_152_i.BLIF N_153_i.BLIF cpu_est_ns_0_1_1__n
11 1
.names LDS_000_c.BLIF LDS_000_i
0 1
.names N_154_i.BLIF N_160_i.BLIF cpu_est_ns_0_2_1__n
11 1
.names AS_000_DMA_0_sqmuxa.BLIF AS_000_DMA_0_sqmuxa_i
0 1
.names inst_CLK_000_D2.BLIF AS_030_000_SYNC_i.BLIF \
state_machine_un28_clk_000_d1_1_n
11 1
.names state_machine_un8_bgack_030_int_n.BLIF \
state_machine_un8_bgack_030_int_i_n
0 1
.names state_machine_un3_clk_000_d1_n.BLIF cpu_estse_2_un3_n
0 1
.names state_machine_un31_bgack_030_int_n.BLIF \
state_machine_un31_bgack_030_int_i_n
0 1
.names N_149_i.BLIF state_machine_un3_clk_000_d1_n.BLIF cpu_estse_2_un1_n
11 1
.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n
0 1
.names cpu_est_3_reg.BLIF cpu_estse_2_un3_n.BLIF cpu_estse_2_un0_n
11 1
.names RW_c.BLIF RW_i
0 1
.names state_machine_un3_clk_000_d1_n.BLIF cpu_estse_1_un3_n
0 1
.names RW_000_c.BLIF RW_000_i
0 1
.names cpu_est_ns_2__n.BLIF state_machine_un3_clk_000_d1_n.BLIF \
cpu_estse_1_un1_n
11 1
.names UDS_000_INT_0_sqmuxa.BLIF UDS_000_INT_0_sqmuxa_i
0 1
.names cpu_est_2_.BLIF cpu_estse_1_un3_n.BLIF cpu_estse_1_un0_n
11 1
.names UDS_000_INT_0_sqmuxa_1.BLIF UDS_000_INT_0_sqmuxa_1_i
0 1
.names state_machine_un3_clk_000_d1_n.BLIF cpu_estse_0_un3_n
0 1
.names AS_000_c.BLIF AS_000_i
0 1
.names cpu_est_ns_1__n.BLIF state_machine_un3_clk_000_d1_n.BLIF \
cpu_estse_0_un1_n
11 1
.names DS_030_c.BLIF DS_030_i
0 1
.names cpu_est_1_.BLIF cpu_estse_0_un3_n.BLIF cpu_estse_0_un0_n
11 1
.names state_machine_un49_clk_000_d0_n.BLIF state_machine_un49_clk_000_d0_i_n
0 1
.names state_machine_un3_clk_000_d1_n.BLIF ipl_030_0_2__un3_n
0 1
.names CLK_030_c.BLIF CLK_030_i
0 1
.names ipl_c_2__n.BLIF state_machine_un3_clk_000_d1_n.BLIF ipl_030_0_2__un1_n
11 1
.names state_machine_un24_bgack_030_int_n.BLIF \
state_machine_un24_bgack_030_int_i_n
0 1
.names IPL_030DFFSH_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n
11 1
.names inst_AS_000_DMA.BLIF AS_000_DMA_i
0 1
.names state_machine_un3_clk_000_d1_n.BLIF ipl_030_0_1__un3_n
0 1
.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n
0 1
.names ipl_c_1__n.BLIF state_machine_un3_clk_000_d1_n.BLIF ipl_030_0_1__un1_n
11 1
.names a_c_30__n.BLIF a_i_30__n
0 1
.names IPL_030DFFSH_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n
11 1
.names a_c_31__n.BLIF a_i_31__n
0 1
.names state_machine_un3_clk_000_d1_n.BLIF ipl_030_0_0__un3_n
0 1
.names a_c_28__n.BLIF a_i_28__n
0 1
.names ipl_c_0__n.BLIF state_machine_un3_clk_000_d1_n.BLIF ipl_030_0_0__un1_n
11 1
.names a_c_29__n.BLIF a_i_29__n
0 1
.names IPL_030DFFSH_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n
11 1
.names a_c_26__n.BLIF a_i_26__n
0 1
.names state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n
0 1
.names a_c_27__n.BLIF a_i_27__n
0 1
.names BGACK_000_c.BLIF state_machine_un6_bgack_000_n.BLIF \
bgack_030_int_0_un1_n
11 1
.names a_c_24__n.BLIF a_i_24__n
0 1
.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \
bgack_030_int_0_un0_n
11 1
.names a_c_25__n.BLIF a_i_25__n
0 1
.names AS_030_000_SYNC_1_sqmuxa.BLIF as_030_000_sync_0_un3_n
0 1
.names RST_c.BLIF RST_i
0 1
.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_1_sqmuxa.BLIF \
as_030_000_sync_0_un1_n
11 1
.names un1_SM_AMIGA_12.BLIF as_030_000_sync_0_un3_n.BLIF \
as_030_000_sync_0_un0_n
11 1
.names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i
0 1
.names un1_as_030_000_sync8_1.BLIF fpu_cs_int_0_un3_n
0 1
.names inst_CLK_OUT_PRE_50_D.BLIF CLK_OUT_PRE_50_D_i
0 1
.names inst_FPU_CS_INTreg.BLIF un1_as_030_000_sync8_1.BLIF fpu_cs_int_0_un1_n
11 1
.names AS_030_c.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un0_n
11 1
.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n
0 1
.names inst_AS_000_INT.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n
11 1
.names N_59.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n
11 1
.names DSACK1_INT_1_sqmuxa.BLIF dsack1_int_0_un3_n
0 1
.names inst_DSACK1_INT.BLIF DSACK1_INT_1_sqmuxa.BLIF dsack1_int_0_un1_n
11 1
.names sm_amiga_i_1__n.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n
11 1
.names state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un3_n
0 1
.names state_machine_un5_clk_000_d0_i_0_n.BLIF \
state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un1_n
11 1
.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n
11 1
.names un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF avec_exp_0_un3_n
0 1
.names inst_avec_expreg.BLIF un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF \
avec_exp_0_un1_n
11 1
.names un1_bgack_030_int_d.BLIF avec_exp_0_un3_n.BLIF avec_exp_0_un0_n
11 1
.names state_machine_un10_bg_030_n.BLIF bg_000_0_un3_n
0 1
.names BG_030_c.BLIF state_machine_un10_bg_030_n.BLIF bg_000_0_un1_n
11 1
.names BG_000DFFSHreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n
11 1
.names un1_AS_030_2.BLIF lds_000_int_0_un3_n
0 1
.names inst_LDS_000_INT.BLIF un1_AS_030_2.BLIF lds_000_int_0_un1_n
11 1
.names state_machine_lds_000_int_7_n.BLIF lds_000_int_0_un3_n.BLIF \
lds_000_int_0_un0_n
11 1
.names un1_AS_030_2.BLIF uds_000_int_0_un3_n
0 1
.names inst_UDS_000_INT.BLIF un1_AS_030_2.BLIF uds_000_int_0_un1_n
11 1
.names state_machine_uds_000_int_7_n.BLIF uds_000_int_0_un3_n.BLIF \
uds_000_int_0_un0_n
11 1
.names RW_000_INT_0_sqmuxa_1.BLIF rw_000_int_0_un3_n
0 1
.names inst_RW_000_INT.BLIF RW_000_INT_0_sqmuxa_1.BLIF rw_000_int_0_un1_n
11 1
.names state_machine_rw_000_int_7_iv_i_n.BLIF rw_000_int_0_un3_n.BLIF \
rw_000_int_0_un0_n
11 1
.names AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un3_n
0 1
.names inst_AS_000_DMA.BLIF AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un1_n
11 1
.names state_machine_un8_bgack_030_int_i_n.BLIF as_000_dma_0_un3_n.BLIF \
as_000_dma_0_un0_n
11 1
.names DS_000_DMA_1_sqmuxa.BLIF ds_000_dma_0_un3_n
0 1
.names inst_DS_000_DMA.BLIF DS_000_DMA_1_sqmuxa.BLIF ds_000_dma_0_un1_n
11 1
.names state_machine_ds_000_dma_3_n.BLIF ds_000_dma_0_un3_n.BLIF \
ds_000_dma_0_un0_n
11 1
.names RST_c.BLIF clk_030_h_0_un3_n
0 1
.names state_machine_clk_030_h_2_n.BLIF RST_c.BLIF clk_030_h_0_un1_n
11 1
.names inst_CLK_030_H.BLIF clk_030_h_0_un3_n.BLIF clk_030_h_0_un0_n
11 1
.names inst_CLK_OUT_PRE_25.BLIF state_machine_un3_clk_out_pre_50_n.BLIF \
CLK_OUT_PRE_25_0
01 1
10 1
11 0
00 0
.names cpu_est_0_.BLIF state_machine_un3_clk_000_d1_n.BLIF cpu_estse
01 1
10 1
11 0
00 0
.names IPL_030DFFSH_2_reg.BLIF IPL_030_2_
1 1
0 0
.names gnd_n_n.BLIF BERR
1 1
0 0
.names BG_000DFFSHreg.BLIF BG_000
1 1
0 0
.names inst_BGACK_030_INTreg.BLIF BGACK_030
1 1
0 0
.names CLK_OUT_INTreg.BLIF CLK_DIV_OUT
1 1
0 0
.names CLK_OUT_INTreg.BLIF CLK_EXP
1 1
0 0
.names inst_FPU_CS_INTreg.BLIF FPU_CS
1 1
0 0
.names vcc_n_n.BLIF AVEC
1 1
0 0
.names inst_avec_expreg.BLIF AVEC_EXP
1 1
0 0
.names cpu_est_3_reg.BLIF E
1 1
0 0
.names inst_VMA_INTreg.BLIF VMA
1 1
0 0
.names RESETDFFRHreg.BLIF RESET
1 1
0 0
.names inst_avec_expreg.BLIF AMIGA_BUS_ENABLE
1 1
0 0
.names AMIGA_BUS_DATA_DIR_c.BLIF AMIGA_BUS_DATA_DIR
1 1
0 0
.names vcc_n_n.BLIF AMIGA_BUS_ENABLE_LOW
1 1
0 0
.names N_210.BLIF CIIN
1 1
0 0
.names IPL_030DFFSH_1_reg.BLIF IPL_030_1_
1 1
0 0
.names IPL_030DFFSH_0_reg.BLIF IPL_030_0_
1 1
0 0
.names CLK_OSZI_c.BLIF cpu_est_1_.C
1 1
0 0
.names RST_i.BLIF cpu_est_1_.AR
1 1
0 0
.names CLK_OSZI_c.BLIF cpu_est_2_.C
1 1
0 0
.names RST_i.BLIF cpu_est_2_.AR
1 1
0 0
.names CLK_OSZI_c.BLIF cpu_est_3_reg.C
1 1
0 0
.names RST_i.BLIF cpu_est_3_reg.AR
1 1
0 0
.names cpu_estse.BLIF cpu_est_0_.D
1 1
0 0
.names CLK_OSZI_c.BLIF cpu_est_0_.C
1 1
0 0
.names RST_i.BLIF cpu_est_0_.AR
1 1
0 0
.names CLK_OSZI_c.BLIF IPL_030DFFSH_0_reg.C
1 1
0 0
.names RST_i.BLIF IPL_030DFFSH_0_reg.AP
1 1
0 0
.names CLK_OSZI_c.BLIF IPL_030DFFSH_1_reg.C
1 1
0 0
.names RST_i.BLIF IPL_030DFFSH_1_reg.AP
1 1
0 0
.names CLK_OSZI_c.BLIF IPL_030DFFSH_2_reg.C
1 1
0 0
.names RST_i.BLIF IPL_030DFFSH_2_reg.AP
1 1
0 0
.names CLK_OSZI_c.BLIF SM_AMIGA_7_.C
1 1
0 0
.names RST_i.BLIF SM_AMIGA_7_.AP
1 1
0 0
.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C
1 1
0 0
.names RST_i.BLIF SM_AMIGA_6_.AR
1 1
0 0
.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C
1 1
0 0
.names RST_i.BLIF SM_AMIGA_5_.AR
1 1
0 0
.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C
1 1
0 0
.names RST_i.BLIF SM_AMIGA_4_.AR
1 1
0 0
.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C
1 1
0 0
.names RST_i.BLIF SM_AMIGA_3_.AR
1 1
0 0
.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C
1 1
0 0
.names RST_i.BLIF SM_AMIGA_2_.AR
1 1
0 0
.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C
1 1
0 0
.names RST_i.BLIF SM_AMIGA_1_.AR
1 1
0 0
.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C
1 1
0 0
.names RST_i.BLIF SM_AMIGA_0_.AR
1 1
0 0
.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C
1 1
0 0
.names RST_i.BLIF inst_VMA_INTreg.AP
1 1
0 0
.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C
1 1
0 0
.names RST_i.BLIF inst_BGACK_030_INTreg.AP
1 1
0 0
.names CLK_OUT_PRE_25_0.BLIF inst_CLK_OUT_PRE_25.D
1 1
0 0
.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_25.C
1 1
0 0
.names RST_i.BLIF inst_CLK_OUT_PRE_25.AR
1 1
0 0
.names CLK_OSZI_c.BLIF SIZE_DMA_0_.C
1 1
0 0
.names RST_i.BLIF SIZE_DMA_0_.AP
1 1
0 0
.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C
1 1
0 0
.names RST_i.BLIF SIZE_DMA_1_.AP
1 1
0 0
.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C
1 1
0 0
.names RST_i.BLIF inst_LDS_000_INT.AP
1 1
0 0
.names CLK_OSZI_c.BLIF inst_FPU_CS_INTreg.C
1 1
0 0
.names RST_i.BLIF inst_FPU_CS_INTreg.AP
1 1
0 0
.names CLK_OSZI_c.BLIF inst_avec_expreg.C
1 1
0 0
.names RST_i.BLIF inst_avec_expreg.AP
1 1
0 0
.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C
1 1
0 0
.names RST_i.BLIF BG_000DFFSHreg.AP
1 1
0 0
.names CLK_OSZI_c.BLIF inst_DS_000_DMA.C
1 1
0 0
.names RST_i.BLIF inst_DS_000_DMA.AP
1 1
0 0
.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C
1 1
0 0
.names RST_i.BLIF inst_AS_000_DMA.AP
1 1
0 0
.names CLK_OSZI_c.BLIF inst_AS_000_INT.C
1 1
0 0
.names RST_i.BLIF inst_AS_000_INT.AP
1 1
0 0
.names CLK_OSZI_c.BLIF inst_DSACK1_INT.C
1 1
0 0
.names RST_i.BLIF inst_DSACK1_INT.AP
1 1
0 0
.names CLK_OSZI_c.BLIF inst_RW_000_INT.C
1 1
0 0
.names RST_i.BLIF inst_RW_000_INT.AP
1 1
0 0
.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C
1 1
0 0
.names RST_i.BLIF inst_AS_030_000_SYNC.AP
1 1
0 0
.names CLK_OSZI_c.BLIF inst_CLK_030_H.C
1 1
0 0
.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C
1 1
0 0
.names RST_i.BLIF inst_UDS_000_INT.AP
1 1
0 0
.names CLK_OSZI_c.BLIF inst_A0_DMA.C
1 1
0 0
.names RST_i.BLIF inst_A0_DMA.AP
1 1
0 0
.names DTACK.PIN.BLIF inst_DTACK_D0.D
1 1
0 0
.names CLK_OSZI_c.BLIF inst_DTACK_D0.C
1 1
0 0
.names RST_i.BLIF inst_DTACK_D0.AP
1 1
0 0
.names inst_CLK_000_D1.BLIF inst_CLK_000_D2.D
1 1
0 0
.names CLK_OSZI_c.BLIF inst_CLK_000_D2.C
1 1
0 0
.names RST_i.BLIF inst_CLK_000_D2.AP
1 1
0 0
.names inst_CLK_OUT_PRE_25.BLIF CLK_OUT_INTreg.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C
1 1
0 0
.names RST_i.BLIF CLK_OUT_INTreg.AR
1 1
0 0
.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D
1 1
0 0
.names CLK_OSZI_c.BLIF inst_CLK_000_D1.C
1 1
0 0
.names RST_i.BLIF inst_CLK_000_D1.AP
1 1
0 0
.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.D
1 1
0 0
.names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C
1 1
0 0
.names RST_i.BLIF inst_BGACK_030_INT_D.AP
1 1
0 0
.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50_D.D
1 1
0 0
.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50_D.C
1 1
0 0
.names RST_i.BLIF inst_CLK_OUT_PRE_50_D.AR
1 1
0 0
.names CLK_000_c.BLIF inst_CLK_000_D0.D
1 1
0 0
.names CLK_OSZI_c.BLIF inst_CLK_000_D0.C
1 1
0 0
.names RST_i.BLIF inst_CLK_000_D0.AP
1 1
0 0
.names VPA.BLIF inst_VPA_D.D
1 1
0 0
.names CLK_OSZI_c.BLIF inst_VPA_D.C
1 1
0 0
.names RST_i.BLIF inst_VPA_D.AP
1 1
0 0
.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C
1 1
0 0
.names RST_i.BLIF inst_CLK_OUT_PRE_50.AR
1 1
0 0
.names vcc_n_n.BLIF RESETDFFRHreg.D
1 1
0 0
.names CLK_OSZI_c.BLIF RESETDFFRHreg.C
1 1
0 0
.names RST_i.BLIF RESETDFFRHreg.AR
1 1
0 0
.names SIZE_DMA_1_.BLIF SIZE_1_
1 1
0 0
.names inst_AS_000_DMA.BLIF AS_030
1 1
0 0
.names inst_AS_000_INT.BLIF AS_000
1 1
0 0
.names inst_RW_000_INT.BLIF RW_000
1 1
0 0
.names inst_DS_000_DMA.BLIF DS_030
1 1
0 0
.names inst_UDS_000_INT.BLIF UDS_000
1 1
0 0
.names inst_LDS_000_INT.BLIF LDS_000
1 1
0 0
.names inst_A0_DMA.BLIF A0
1 1
0 0
.names inst_DSACK1_INT.BLIF DSACK1
1 1
0 0
.names DSACK1_c.BLIF DTACK
1 1
0 0
.names inst_RW_000_INT.BLIF RW
1 1
0 0
.names SIZE_DMA_0_.BLIF SIZE_0_
1 1
0 0
.names A_28_.BLIF a_c_28__n
1 1
0 0
.names A_29_.BLIF a_c_29__n
1 1
0 0
.names A_30_.BLIF a_c_30__n
1 1
0 0
.names A_31_.BLIF a_c_31__n
1 1
0 0
.names A0.PIN.BLIF A0_c
1 1
0 0
.names nEXP_SPACE.BLIF nEXP_SPACE_c
1 1
0 0
.names BG_030.BLIF BG_030_c
1 1
0 0
.names BGACK_000.BLIF BGACK_000_c
1 1
0 0
.names CLK_030.BLIF CLK_030_c
1 1
0 0
.names CLK_000.BLIF CLK_000_c
1 1
0 0
.names CLK_OSZI.BLIF CLK_OSZI_c
1 1
0 0
.names IPL_0_.BLIF ipl_c_0__n
1 1
0 0
.names IPL_1_.BLIF ipl_c_1__n
1 1
0 0
.names IPL_2_.BLIF ipl_c_2__n
1 1
0 0
.names DSACK1.PIN.BLIF DSACK1_c
1 1
0 0
.names RST.BLIF RST_c
1 1
0 0
.names RW.PIN.BLIF RW_c
1 1
0 0
.names FC_0_.BLIF fc_c_0__n
1 1
0 0
.names FC_1_.BLIF fc_c_1__n
1 1
0 0
.names AS_030.PIN.BLIF AS_030_c
1 1
0 0
.names AS_000.PIN.BLIF AS_000_c
1 1
0 0
.names RW_000.PIN.BLIF RW_000_c
1 1
0 0
.names DS_030.PIN.BLIF DS_030_c
1 1
0 0
.names UDS_000.PIN.BLIF UDS_000_c
1 1
0 0
.names LDS_000.PIN.BLIF LDS_000_c
1 1
0 0
.names SIZE_0_.PIN.BLIF size_c_0__n
1 1
0 0
.names SIZE_1_.PIN.BLIF size_c_1__n
1 1
0 0
.names A_16_.BLIF a_c_16__n
1 1
0 0
.names A_17_.BLIF a_c_17__n
1 1
0 0
.names A_18_.BLIF a_c_18__n
1 1
0 0
.names A_19_.BLIF a_c_19__n
1 1
0 0
.names A_20_.BLIF a_c_20__n
1 1
0 0
.names A_21_.BLIF a_c_21__n
1 1
0 0
.names A_22_.BLIF a_c_22__n
1 1
0 0
.names A_23_.BLIF a_c_23__n
1 1
0 0
.names A_24_.BLIF a_c_24__n
1 1
0 0
.names A_25_.BLIF a_c_25__n
1 1
0 0
.names A_26_.BLIF a_c_26__n
1 1
0 0
.names A_27_.BLIF a_c_27__n
1 1
0 0
.names un3_dtack_i.BLIF AS_030.OE
1 1
0 0
.names inst_BGACK_030_INTreg.BLIF AS_000.OE
1 1
0 0
.names inst_BGACK_030_INTreg.BLIF RW_000.OE
1 1
0 0
.names un3_dtack_i.BLIF DS_030.OE
1 1
0 0
.names inst_BGACK_030_INTreg.BLIF UDS_000.OE
1 1
0 0
.names inst_BGACK_030_INTreg.BLIF LDS_000.OE
1 1
0 0
.names un3_dtack_i.BLIF SIZE_0_.OE
1 1
0 0
.names un3_dtack_i.BLIF SIZE_1_.OE
1 1
0 0
.names un3_dtack_i.BLIF A0.OE
1 1
0 0
.names nEXP_SPACE_c.BLIF DSACK1.OE
1 1
0 0
.names un3_dtack_i.BLIF DTACK.OE
1 1
0 0
.names BGACK_030_INT_i.BLIF RW.OE
1 1
0 0
.names FPU_CS_INT_i.BLIF BERR.OE
1 1
0 0
.names N_220.BLIF CIIN.OE
1 1
0 0
.end