mirror of https://github.com/kr239/68030tk.git
101 lines
5.6 KiB
Plaintext
101 lines
5.6 KiB
Plaintext
#Build: Synplify Pro G-2012.09LC-SP1 , Build 035R, Mar 19 2013
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#install: C:\Program Files (x86)\ispLever\synpbase
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#OS: Windows 7 6.1
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#Hostname: DEEPTHOUGHT
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#Implementation: logic
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$ Start of Compile
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#Tue Feb 03 20:27:43 2015
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Synopsys VHDL Compiler, version comp201209rcp1, Build 283R, built Mar 19 2013
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@N|Running in 64-bit mode
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Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
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@N: CD720 :"C:\Program Files (x86)\ispLever\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
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@N:"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Top entity is set to BUS68030.
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File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
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VHDL syntax check successful!
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File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
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@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
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@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":125:7:125:20|Signal clk_out_pre_25 is undriven
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@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:7:126:20|Signal clk_out_pre_33 is undriven
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@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:7:127:22|Signal clk_out_pre_33_d is undriven
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@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":128:8:128:17|Signal clk_pre_66 is undriven
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@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:7:129:17|Signal clk_out_pre is undriven
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@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:7:131:16|Signal clk_out_ne is undriven
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@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:7:132:17|Signal clk_out_int is undriven
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Post processing for work.bus68030.behavioral
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@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":144:32:144:34|Pruning register CLK_REF(1 downto 0)
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@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:34:137:36|Pruning register CLK_000_D4
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@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":136:34:136:36|Pruning register CLK_000_D3
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@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":135:34:135:36|Pruning register CLK_000_D2
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@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":123:36:123:38|Pruning register CLK_OUT_PRE_50_D
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@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:61:139:75|Pruning bit 12 of CLK_000_N_SYNC(12 downto 0) -- not in use ...
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@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:34:138:36|Pruning bits 12 to 11 of CLK_000_P_SYNC(12 downto 0) -- not in use ...
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@W: CL117 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":259:2:259:3|Latch generated from process for signal RESET_OUT; possible missing assignment in an if or case statement.
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@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":143:37:143:39|Trying to extract state machine for register cpu_est
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@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":144:32:144:34|Trying to extract state machine for register SM_AMIGA
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Extracted state machine for register SM_AMIGA
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State machine has 8 reachable states with original encodings of:
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000
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001
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010
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011
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100
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101
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110
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111
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@END
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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# Tue Feb 03 20:27:43 2015
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###########################################################]
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Map & Optimize Report
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Synopsys CPLD Technology Mapper, Version maplat, Build 621R, Built Mar 19 2013
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Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
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Product Version G-2012.09LC-SP1
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@N: MF248 |Running in 64-bit mode.
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Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
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original code -> new code
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000 -> 00000001
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001 -> 00000010
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010 -> 00000100
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011 -> 00001000
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100 -> 00010000
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101 -> 00100000
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110 -> 01000000
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111 -> 10000000
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@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":216:4:216:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
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@W: BN132 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:34:138:36|Removing instance CLK_000_P_SYNC[10], because it is equivalent to instance CLK_000_PE
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@W: MT462 :|Net RST_c appears to be an unidentified clock source. Assuming default frequency.
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---------------------------------------
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Resource Usage Report
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Simple gate primitives:
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DFFRH 17 uses
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DFF 33 uses
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DFFSH 28 uses
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BI_DIR 11 uses
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IBUF 32 uses
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OBUF 16 uses
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BUFTH 2 uses
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AND2 230 uses
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INV 180 uses
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DLATRH 1 use
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OR2 20 uses
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XOR2 9 uses
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@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
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G-2012.09LC-SP1
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Mapper successful!
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At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 96MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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# Tue Feb 03 20:27:45 2015
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###########################################################]
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