mirror of https://github.com/kr239/68030tk.git
1372 lines
32 KiB
Plaintext
1372 lines
32 KiB
Plaintext
#$ TOOL ispLEVER Classic 2.0.00.17.20.15
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#$ DATE Fri Aug 19 00:20:41 2016
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#$ MODULE 68030_tk
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#$ PINS 61 A_DECODE_22_ A_DECODE_21_ SIZE_1_ A_DECODE_20_ A_DECODE_19_ AHIGH_31_ \
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# A_DECODE_18_ A_DECODE_17_ A_DECODE_23_ A_DECODE_16_ IPL_030_2_ IPL_2_ FC_1_ AS_030 \
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# AS_000 RW_000 DS_030 UDS_000 LDS_000 nEXP_SPACE A_0_ BERR IPL_030_1_ BG_030 IPL_030_0_ \
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# BG_000 IPL_1_ BGACK_030 IPL_0_ BGACK_000 FC_0_ CLK_030 A_1_ CLK_000 CLK_OSZI CLK_DIV_OUT \
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# CLK_EXP FPU_CS FPU_SENSE DSACK1 DTACK AVEC E VPA VMA RST RESET RW AMIGA_ADDR_ENABLE \
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# AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ \
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# AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_
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#$ NODES 89 N_226 inst_BGACK_030_INTreg inst_VMA_INTreg cpu_est_2_ cpu_est_3_ \
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# cpu_est_0_ cpu_est_1_ inst_AS_000_INT inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 \
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# inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA \
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# CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT \
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# inst_LDS_000_INT inst_CLK_OUT_PRE_D CLK_000_D_10_ CLK_000_D_11_ inst_DTACK_D0 \
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# inst_RESET_OUT inst_CLK_OUT_PRE_50 CLK_000_D_1_ CLK_000_D_0_ CLK_000_P_SYNC_10_ \
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# SM_AMIGA_5_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ CLK_000_D_3_ CLK_000_D_4_ \
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# CLK_000_D_5_ CLK_000_D_6_ CLK_000_D_7_ CLK_000_D_8_ CLK_000_D_9_ CLK_000_D_12_ \
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# SM_AMIGA_0_ inst_DSACK1_INTreg CLK_000_N_SYNC_0_ SM_AMIGA_4_ inst_DS_000_ENABLE \
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# CLK_000_N_SYNC_12_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_ \
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# CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ \
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# CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ \
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# CLK_000_P_SYNC_9_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ \
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# CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ \
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# CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ CLK_000_N_SYNC_11_ \
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# inst_RW_000_INT inst_RW_000_DMA inst_CLK_000_NE_D0 inst_AMIGA_BUS_ENABLE_DMA_HIGH \
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# inst_A0_DMA SM_AMIGA_6_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_3_ SM_AMIGA_2_ \
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# SM_AMIGA_i_7_ BG_000DFFreg CLK_OUT_INTreg IPL_030DFF_0_reg IPL_030DFF_1_reg \
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# IPL_030DFF_2_reg
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.model bus68030
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.inputs A_DECODE_23_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF \
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BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF FPU_SENSE.BLIF \
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DTACK.BLIF VPA.BLIF RST.BLIF A_DECODE_22_.BLIF A_DECODE_21_.BLIF \
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A_DECODE_20_.BLIF A_DECODE_19_.BLIF A_DECODE_18_.BLIF A_DECODE_17_.BLIF \
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A_DECODE_16_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF A_1_.BLIF N_226.BLIF \
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inst_BGACK_030_INTreg.BLIF inst_VMA_INTreg.BLIF cpu_est_2_.BLIF \
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cpu_est_3_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_AS_000_INT.BLIF \
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inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF inst_AS_030_D0.BLIF \
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inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INT_D.BLIF inst_AS_000_DMA.BLIF \
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inst_DS_000_DMA.BLIF CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF SIZE_DMA_0_.BLIF \
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SIZE_DMA_1_.BLIF inst_VPA_D.BLIF inst_UDS_000_INT.BLIF inst_LDS_000_INT.BLIF \
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inst_CLK_OUT_PRE_D.BLIF CLK_000_D_10_.BLIF CLK_000_D_11_.BLIF \
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inst_DTACK_D0.BLIF inst_RESET_OUT.BLIF inst_CLK_OUT_PRE_50.BLIF \
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CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF CLK_000_P_SYNC_10_.BLIF SM_AMIGA_5_.BLIF \
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IPL_D0_0_.BLIF IPL_D0_1_.BLIF IPL_D0_2_.BLIF CLK_000_D_2_.BLIF \
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CLK_000_D_3_.BLIF CLK_000_D_4_.BLIF CLK_000_D_5_.BLIF CLK_000_D_6_.BLIF \
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CLK_000_D_7_.BLIF CLK_000_D_8_.BLIF CLK_000_D_9_.BLIF CLK_000_D_12_.BLIF \
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SM_AMIGA_0_.BLIF inst_DSACK1_INTreg.BLIF CLK_000_N_SYNC_0_.BLIF \
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SM_AMIGA_4_.BLIF inst_DS_000_ENABLE.BLIF CLK_000_N_SYNC_12_.BLIF \
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RST_DLY_0_.BLIF RST_DLY_1_.BLIF RST_DLY_2_.BLIF CLK_000_P_SYNC_0_.BLIF \
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CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.BLIF \
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CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.BLIF \
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CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.BLIF CLK_000_P_SYNC_9_.BLIF \
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CLK_000_N_SYNC_1_.BLIF CLK_000_N_SYNC_2_.BLIF CLK_000_N_SYNC_3_.BLIF \
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CLK_000_N_SYNC_4_.BLIF CLK_000_N_SYNC_5_.BLIF CLK_000_N_SYNC_6_.BLIF \
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CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.BLIF \
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CLK_000_N_SYNC_10_.BLIF CLK_000_N_SYNC_11_.BLIF inst_RW_000_INT.BLIF \
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inst_RW_000_DMA.BLIF inst_CLK_000_NE_D0.BLIF \
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inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF inst_A0_DMA.BLIF SM_AMIGA_6_.BLIF \
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inst_CLK_030_H.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF \
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SM_AMIGA_i_7_.BLIF BG_000DFFreg.BLIF CLK_OUT_INTreg.BLIF IPL_030DFF_0_reg.BLIF \
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IPL_030DFF_1_reg.BLIF IPL_030DFF_2_reg.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF \
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RW_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF \
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SIZE_1_.PIN.BLIF AHIGH_24_.PIN.BLIF AHIGH_25_.PIN.BLIF AHIGH_26_.PIN.BLIF \
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AHIGH_27_.PIN.BLIF AHIGH_28_.PIN.BLIF AHIGH_29_.PIN.BLIF AHIGH_30_.PIN.BLIF \
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AHIGH_31_.PIN.BLIF A_0_.PIN.BLIF BERR.PIN.BLIF RW.PIN.BLIF
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.outputs IPL_030_2_ DS_030 BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 \
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AVEC E VMA RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \
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AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_i_7_.D \
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SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_5_.D SM_AMIGA_5_.C \
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SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C \
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SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C cpu_est_2_.D \
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cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C \
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IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D IPL_030DFF_2_reg.C \
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IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C \
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CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D \
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CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C \
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CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.D \
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CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C \
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CLK_000_N_SYNC_12_.D CLK_000_N_SYNC_12_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C \
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CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D \
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SIZE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C \
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CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.D \
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CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C \
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CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D \
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CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C \
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CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.D \
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CLK_000_P_SYNC_9_.C CLK_000_P_SYNC_10_.D CLK_000_P_SYNC_10_.C \
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CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.D \
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CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C \
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CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.D \
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CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C CLK_000_D_0_.D \
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CLK_000_D_0_.C CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_2_.D CLK_000_D_2_.C \
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CLK_000_D_3_.D CLK_000_D_3_.C CLK_000_D_4_.D CLK_000_D_4_.C CLK_000_D_5_.D \
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CLK_000_D_5_.C CLK_000_D_6_.D CLK_000_D_6_.C CLK_000_D_7_.D CLK_000_D_7_.C \
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CLK_000_D_8_.D CLK_000_D_8_.C CLK_000_D_9_.D CLK_000_D_9_.C CLK_000_D_10_.D \
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CLK_000_D_10_.C CLK_000_D_11_.D CLK_000_D_11_.C CLK_000_D_12_.D \
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CLK_000_D_12_.C CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.D \
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CLK_000_P_SYNC_1_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C \
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RST_DLY_2_.D RST_DLY_2_.C inst_CLK_030_H.C inst_RESET_OUT.D inst_RESET_OUT.C \
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inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C inst_VMA_INTreg.D inst_VMA_INTreg.C \
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inst_UDS_000_INT.D inst_UDS_000_INT.C inst_A0_DMA.D inst_A0_DMA.C \
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inst_RW_000_DMA.D inst_RW_000_DMA.C inst_RW_000_INT.D inst_RW_000_INT.C \
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inst_LDS_000_INT.D inst_LDS_000_INT.C inst_BGACK_030_INTreg.D \
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inst_BGACK_030_INTreg.C inst_AS_000_DMA.D inst_AS_000_DMA.C \
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inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_000_INT.D \
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inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C inst_DS_000_DMA.D \
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inst_DS_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C inst_VPA_D.D inst_VPA_D.C \
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inst_DTACK_D0.D inst_DTACK_D0.C BG_000DFFreg.D BG_000DFFreg.C \
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inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.C \
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inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AMIGA_BUS_ENABLE_DMA_LOW.C \
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inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C inst_BGACK_030_INT_D.D \
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inst_BGACK_030_INT_D.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C \
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CLK_OUT_INTreg.D CLK_OUT_INTreg.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C \
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SIZE_1_ AHIGH_31_ AS_030 AS_000 RW_000 UDS_000 LDS_000 BERR RW SIZE_0_ \
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AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ A_0_ \
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N_226 AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE \
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SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE \
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AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE \
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DSACK1.OE RESET.OE CIIN.OE inst_CLK_030_H.D.X1 inst_CLK_030_H.D.X2 \
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SM_AMIGA_3_.D.X1 SM_AMIGA_3_.D.X2
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.names RST.BLIF N_226.BLIF inst_VMA_INTreg.BLIF cpu_est_2_.BLIF \
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cpu_est_3_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_VPA_D.BLIF \
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inst_DTACK_D0.BLIF CLK_000_P_SYNC_10_.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_0_.BLIF \
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SM_AMIGA_4_.BLIF CLK_000_N_SYNC_12_.BLIF inst_CLK_000_NE_D0.BLIF \
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SM_AMIGA_6_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF \
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BERR.PIN.BLIF SM_AMIGA_i_7_.D
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10001000--000-100-0- 1
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10001000---00110--0- 1
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10001000-100--1-0--- 1
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10001000-1-0-11----- 1
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10-----10-000-100-0- 1
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10-----10--00110--0- 1
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10--------000--0000- 1
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10-----10100--1-0--- 1
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10---------001-0-00- 1
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10-----101-0-11----- 1
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10-------100----00-- 1
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10-------1-0-1---0-- 1
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10-------0---------1 1
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10---------0-------1 1
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-------11--------1-0 0
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---------1-1-------- 0
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------10---------1-0 0
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-----1-0---------1-0 0
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----0--0---------1-0 0
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---1---0---------1-0 0
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--1----0---------1-0 0
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-------------0--1--0 0
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----------1--0-----0 0
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---------0--------10 0
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---------0-----1---0 0
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---------0--1------0 0
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--------------0--1-0 0
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-1------------------ 0
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0------------------- 0
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-----------1-------0 0
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.names nEXP_SPACE.BLIF RST.BLIF inst_AS_030_000_SYNC.BLIF \
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CLK_000_P_SYNC_10_.BLIF CLK_000_N_SYNC_0_.BLIF SM_AMIGA_6_.BLIF \
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SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF SM_AMIGA_6_.D
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110-1-0- 1
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-1-0-1-1 1
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-1---10- 1
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---1--1- 0
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----00-- 0
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--1--0-- 0
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0----0-- 0
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-----01- 0
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-0------ 0
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------10 0
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.names RST.BLIF CLK_000_P_SYNC_10_.BLIF SM_AMIGA_5_.BLIF \
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CLK_000_N_SYNC_12_.BLIF SM_AMIGA_6_.BLIF BERR.PIN.BLIF SM_AMIGA_5_.D
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110-1- 1
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1-10-1 1
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1-1-11 1
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---10- 0
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-00--- 0
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--0-0- 0
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--1--0 0
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0----- 0
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.names RST.BLIF CLK_000_P_SYNC_10_.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_4_.BLIF \
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CLK_000_N_SYNC_12_.BLIF BERR.PIN.BLIF SM_AMIGA_4_.D
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10-1-1 1
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1-1-1- 1
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1-11-- 1
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---00- 0
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-10--- 0
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--00-- 0
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0----- 0
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--0--0 0
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.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_2_.BLIF cpu_est_3_.BLIF \
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cpu_est_0_.BLIF cpu_est_1_.BLIF inst_VPA_D.BLIF inst_DTACK_D0.BLIF \
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CLK_000_P_SYNC_10_.BLIF inst_CLK_000_NE_D0.BLIF SM_AMIGA_3_.BLIF \
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SM_AMIGA_2_.BLIF BERR.PIN.BLIF SM_AMIGA_2_.D
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1001000--11-- 1
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1-----10-11-- 1
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1-------0--11 1
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1---------11- 1
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------11---0- 0
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--------1-0-- 0
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-----10----0- 0
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----1-0----0- 0
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---0--0----0- 0
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--1---0----0- 0
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-1----0----0- 0
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---------0-0- 0
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----------00- 0
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0------------ 0
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----------0-0 0
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.names RST.BLIF CLK_000_P_SYNC_10_.BLIF CLK_000_N_SYNC_12_.BLIF \
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SM_AMIGA_1_.BLIF SM_AMIGA_2_.BLIF BERR.PIN.BLIF SM_AMIGA_1_.D
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11-01- 1
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1-01-1 1
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1--111 1
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--1-0- 0
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-0-0-- 0
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---00- 0
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---1-0 0
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0----- 0
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.names RST.BLIF CLK_000_P_SYNC_10_.BLIF SM_AMIGA_0_.BLIF \
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CLK_000_N_SYNC_12_.BLIF SM_AMIGA_1_.BLIF BERR.PIN.BLIF SM_AMIGA_0_.D
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1-011- 1
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101--1 1
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-11--- 0
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--0-0- 0
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--00-- 0
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--1--0 0
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0----- 0
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.names cpu_est_2_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_CLK_000_NE_D0.BLIF \
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cpu_est_2_.D
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0111 1
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1-0- 1
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10-- 1
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1--0 1
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1111 0
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0-0- 0
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00-- 0
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0--0 0
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.names cpu_est_2_.BLIF cpu_est_3_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \
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inst_CLK_000_NE_D0.BLIF cpu_est_3_.D
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1-111 1
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010-- 1
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-1--0 1
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--101 0
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00--- 0
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1-0-1 0
|
|
0-1-1 0
|
|
-0--0 0
|
|
.names IPL_2_.BLIF RST.BLIF IPL_1_.BLIF IPL_0_.BLIF IPL_D0_0_.BLIF \
|
|
IPL_D0_1_.BLIF IPL_D0_2_.BLIF IPL_030DFF_0_reg.BLIF IPL_030DFF_0_reg.D
|
|
0-01100- 1
|
|
0-11110- 1
|
|
1-01101- 1
|
|
1-11111- 1
|
|
1-----01 1
|
|
0-----11 1
|
|
--1--0-1 1
|
|
--0--1-1 1
|
|
---1---1 1
|
|
----1--1 1
|
|
-0------ 1
|
|
0100000- 0
|
|
0110010- 0
|
|
1100001- 0
|
|
1110011- 0
|
|
11----00 0
|
|
01----10 0
|
|
-11--0-0 0
|
|
-10--1-0 0
|
|
-1--0--0 0
|
|
-1-0---0 0
|
|
.names IPL_2_.BLIF RST.BLIF IPL_1_.BLIF IPL_0_.BLIF IPL_D0_0_.BLIF \
|
|
IPL_D0_1_.BLIF IPL_D0_2_.BLIF IPL_030DFF_1_reg.BLIF IPL_030DFF_1_reg.D
|
|
0-10010- 1
|
|
0-11110- 1
|
|
1-10011- 1
|
|
1-11111- 1
|
|
1-----01 1
|
|
0-----11 1
|
|
--1----1 1
|
|
-----1-1 1
|
|
---10--1 1
|
|
---01--1 1
|
|
-0------ 1
|
|
0100000- 0
|
|
0101100- 0
|
|
1100001- 0
|
|
1101101- 0
|
|
11----00 0
|
|
01----10 0
|
|
-1-10--0 0
|
|
-1-01--0 0
|
|
-1---0-0 0
|
|
-10----0 0
|
|
.names IPL_2_.BLIF RST.BLIF IPL_1_.BLIF IPL_0_.BLIF IPL_D0_0_.BLIF \
|
|
IPL_D0_1_.BLIF IPL_D0_2_.BLIF IPL_030DFF_2_reg.BLIF IPL_030DFF_2_reg.D
|
|
1-00001- 1
|
|
1-01101- 1
|
|
1-10011- 1
|
|
1-11111- 1
|
|
1------1 1
|
|
------11 1
|
|
--1--0-1 1
|
|
--0--1-1 1
|
|
---10--1 1
|
|
---01--1 1
|
|
-0------ 1
|
|
0100000- 0
|
|
0101100- 0
|
|
0110010- 0
|
|
0111110- 0
|
|
-11--0-0 0
|
|
-10--1-0 0
|
|
-1-10--0 0
|
|
-1-01--0 0
|
|
-1----00 0
|
|
01-----0 0
|
|
.names RST.BLIF IPL_0_.BLIF IPL_D0_0_.D
|
|
0- 1
|
|
-1 1
|
|
10 0
|
|
.names RST.BLIF IPL_1_.BLIF IPL_D0_1_.D
|
|
0- 1
|
|
-1 1
|
|
10 0
|
|
.names IPL_2_.BLIF RST.BLIF IPL_D0_2_.D
|
|
1- 1
|
|
-0 1
|
|
01 0
|
|
.names RST.BLIF inst_BGACK_030_INTreg.BLIF CYCLE_DMA_0_.BLIF \
|
|
CLK_000_P_SYNC_10_.BLIF AS_000.PIN.BLIF CYCLE_DMA_0_.D
|
|
10100 1
|
|
10010 1
|
|
--00- 0
|
|
--11- 0
|
|
-1--- 0
|
|
0---- 0
|
|
----1 0
|
|
.names RST.BLIF inst_BGACK_030_INTreg.BLIF CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF \
|
|
CLK_000_P_SYNC_10_.BLIF AS_000.PIN.BLIF CYCLE_DMA_1_.D
|
|
101010 1
|
|
10-100 1
|
|
1001-0 1
|
|
--111- 0
|
|
---00- 0
|
|
--00-- 0
|
|
-1---- 0
|
|
0----- 0
|
|
-----1 0
|
|
.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \
|
|
SIZE_DMA_0_.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_DMA_0_.D
|
|
-111-- 1
|
|
-0--1- 1
|
|
0----- 1
|
|
-0---1 1
|
|
10--00 0
|
|
11-0-- 0
|
|
110--- 0
|
|
.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \
|
|
SIZE_DMA_1_.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_DMA_1_.D
|
|
-111-- 1
|
|
-0--00 1
|
|
0----- 1
|
|
10--1- 0
|
|
11-0-- 0
|
|
110--- 0
|
|
10---1 0
|
|
.names cpu_est_3_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_CLK_000_NE_D0.BLIF \
|
|
cpu_est_1_.D
|
|
0101 1
|
|
-01- 1
|
|
--10 1
|
|
1-0- 0
|
|
-111 0
|
|
-00- 0
|
|
--00 0
|
|
.names CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF CLK_000_N_SYNC_0_.D
|
|
10 1
|
|
0- 0
|
|
-1 0
|
|
.names CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF CLK_000_P_SYNC_0_.D
|
|
01 1
|
|
1- 0
|
|
-0 0
|
|
.names RST.BLIF CLK_000_N_SYNC_12_.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF \
|
|
RST_DLY_2_.BLIF RST_DLY_0_.D
|
|
1-111 1
|
|
110-- 1
|
|
101-- 1
|
|
-110- 0
|
|
-00-- 0
|
|
-11-0 0
|
|
0---- 0
|
|
.names RST.BLIF CLK_000_N_SYNC_12_.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF \
|
|
RST_DLY_2_.BLIF RST_DLY_1_.D
|
|
1--11 1
|
|
1110- 1
|
|
1-01- 1
|
|
10-1- 1
|
|
-1110 0
|
|
--00- 0
|
|
-0-0- 0
|
|
0---- 0
|
|
.names RST.BLIF CLK_000_N_SYNC_12_.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF \
|
|
RST_DLY_2_.BLIF RST_DLY_2_.D
|
|
1111- 1
|
|
1---1 1
|
|
0---- 0
|
|
---00 0
|
|
--0-0 0
|
|
-0--0 0
|
|
.names RST.BLIF inst_RESET_OUT.BLIF CLK_000_N_SYNC_12_.BLIF RST_DLY_0_.BLIF \
|
|
RST_DLY_1_.BLIF RST_DLY_2_.BLIF inst_RESET_OUT.D
|
|
1-1111 1
|
|
11---- 1
|
|
-0--0- 0
|
|
-0-0-- 0
|
|
-00--- 0
|
|
0----- 0
|
|
-0---0 0
|
|
.names RST.BLIF inst_AS_030_D0.BLIF CLK_000_P_SYNC_10_.BLIF SM_AMIGA_5_.BLIF \
|
|
SM_AMIGA_0_.BLIF SM_AMIGA_4_.BLIF inst_DS_000_ENABLE.BLIF SM_AMIGA_6_.BLIF \
|
|
SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF RW.PIN.BLIF inst_DS_000_ENABLE.D
|
|
1--000-01-- 1
|
|
1-100--01-- 1
|
|
10----1--1- 1
|
|
1---00-01-1 1
|
|
1-1-0--01-1 1
|
|
--0--1---0- 0
|
|
--0--10---- 0
|
|
-10--1----- 0
|
|
---1-----00 0
|
|
---1--0---0 0
|
|
-1-1------0 0
|
|
--------00- 0
|
|
-------1-0- 0
|
|
----1----0- 0
|
|
------0-0-- 0
|
|
-1------0-- 0
|
|
------01--- 0
|
|
-1-----1--- 0
|
|
----1-0---- 0
|
|
-1--1------ 0
|
|
0---------- 0
|
|
.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_2_.BLIF cpu_est_3_.BLIF \
|
|
cpu_est_0_.BLIF cpu_est_1_.BLIF inst_VPA_D.BLIF CLK_000_P_SYNC_10_.BLIF \
|
|
CLK_000_N_SYNC_12_.BLIF inst_VMA_INTreg.D
|
|
--0000-1- 1
|
|
-1----1-- 1
|
|
-1---0--- 1
|
|
-1--0---- 1
|
|
-1------0 1
|
|
0-------- 1
|
|
-1-1----- 1
|
|
-11------ 1
|
|
1-00110-1 0
|
|
10-----0- 0
|
|
10-1----- 0
|
|
101------ 0
|
|
10---1--- 0
|
|
10--1---- 0
|
|
.names RST.BLIF inst_UDS_000_INT.BLIF SM_AMIGA_6_.BLIF A_0_.PIN.BLIF \
|
|
inst_UDS_000_INT.D
|
|
-10- 1
|
|
0--- 1
|
|
--11 1
|
|
100- 0
|
|
1-10 0
|
|
.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \
|
|
inst_A0_DMA.BLIF UDS_000.PIN.BLIF inst_A0_DMA.D
|
|
-111- 1
|
|
0---- 1
|
|
-0--1 1
|
|
11-0- 0
|
|
110-- 0
|
|
10--0 0
|
|
.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \
|
|
inst_RW_000_DMA.BLIF RW_000.PIN.BLIF inst_RW_000_DMA.D
|
|
-1-1- 1
|
|
-10-- 1
|
|
0---- 1
|
|
-0--1 1
|
|
1110- 0
|
|
10--0 0
|
|
.names RST.BLIF CLK_000_P_SYNC_10_.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_0_.BLIF \
|
|
inst_RW_000_INT.BLIF SM_AMIGA_i_7_.BLIF RW.PIN.BLIF inst_RW_000_INT.D
|
|
--0-1-- 1
|
|
-101--- 1
|
|
--0--0- 1
|
|
0------ 1
|
|
--1---1 1
|
|
1-0001- 0
|
|
100-01- 0
|
|
1-1---0 0
|
|
.names RST.BLIF inst_LDS_000_INT.BLIF SM_AMIGA_6_.BLIF SIZE_0_.PIN.BLIF \
|
|
SIZE_1_.PIN.BLIF A_0_.PIN.BLIF inst_LDS_000_INT.D
|
|
--1100 1
|
|
-10--- 1
|
|
0----- 1
|
|
100--- 0
|
|
1-1-1- 0
|
|
1-10-- 0
|
|
1-1--1 0
|
|
.names BGACK_000.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF \
|
|
CLK_000_P_SYNC_10_.BLIF AS_000.PIN.BLIF inst_BGACK_030_INTreg.D
|
|
1-1-- 1
|
|
1--11 1
|
|
-0--- 1
|
|
-100- 0
|
|
-10-0 0
|
|
01--- 0
|
|
.names CLK_030.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \
|
|
CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF AS_000.PIN.BLIF UDS_000.PIN.BLIF \
|
|
LDS_000.PIN.BLIF inst_AS_000_DMA.D
|
|
----00--- 1
|
|
----11--- 1
|
|
0--1----- 1
|
|
------1-- 1
|
|
--1------ 1
|
|
-0------- 1
|
|
-------11 1
|
|
-1001000- 0
|
|
110-1000- 0
|
|
-1000100- 0
|
|
110-0100- 0
|
|
-100100-0 0
|
|
110-100-0 0
|
|
-100010-0 0
|
|
110-010-0 0
|
|
.names FC_1_.BLIF nEXP_SPACE.BLIF RST.BLIF A_DECODE_19_.BLIF A_DECODE_18_.BLIF \
|
|
A_DECODE_17_.BLIF A_DECODE_16_.BLIF FC_0_.BLIF inst_BGACK_030_INTreg.BLIF \
|
|
inst_AS_030_D0.BLIF inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INT_D.BLIF \
|
|
SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF inst_AS_030_000_SYNC.D
|
|
1--00101--1--- 1
|
|
----------1-1- 1
|
|
----------10-- 1
|
|
--------0-1--- 1
|
|
-0--------1--- 1
|
|
---------1---- 1
|
|
--0----------- 1
|
|
-------------0 1
|
|
-11----010-101 0
|
|
-11---1-10-101 0
|
|
-11--0--10-101 0
|
|
-11-1---10-101 0
|
|
-111----10-101 0
|
|
011-----10-101 0
|
|
--1------00--1 0
|
|
.names RST.BLIF inst_AS_000_INT.BLIF inst_AS_030_D0.BLIF SM_AMIGA_5_.BLIF \
|
|
BERR.PIN.BLIF inst_AS_000_INT.D
|
|
-1-0- 1
|
|
--10- 1
|
|
0---- 1
|
|
---00 1
|
|
100-1 0
|
|
1--1- 0
|
|
.names CLK_030.BLIF RST.BLIF inst_AS_030_D0.BLIF inst_CLK_OUT_PRE_D.BLIF \
|
|
CLK_000_D_10_.BLIF CLK_000_D_11_.BLIF CLK_000_D_12_.BLIF \
|
|
inst_DSACK1_INTreg.BLIF SM_AMIGA_1_.BLIF BERR.PIN.BLIF inst_DSACK1_INTreg.D
|
|
1--0-1-1-- 1
|
|
-----001-- 1
|
|
----11-1-- 1
|
|
1-10-1---- 1
|
|
1--0-1---0 1
|
|
-------10- 1
|
|
--1--00--- 1
|
|
--1-11---- 1
|
|
-----00--0 1
|
|
----11---0 1
|
|
--1-----0- 1
|
|
-0-------- 1
|
|
--------00 1
|
|
-1-101--1- 0
|
|
01--01--1- 0
|
|
-1---01-1- 0
|
|
-10----0-1 0
|
|
.names CLK_030.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \
|
|
inst_DS_000_DMA.BLIF CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF inst_CLK_030_H.BLIF \
|
|
AS_000.PIN.BLIF RW_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF \
|
|
inst_DS_000_DMA.D
|
|
1--1---1-0-- 1
|
|
----1--0-0-- 1
|
|
0---1----0-- 1
|
|
-----00----- 1
|
|
-----11----- 1
|
|
--------1--- 1
|
|
--1--------- 1
|
|
-0---------- 1
|
|
----------11 1
|
|
1100-1010-0- 0
|
|
1100-0110-0- 0
|
|
1100-1010--0 0
|
|
1100-0110--0 0
|
|
-10-01000-0- 0
|
|
-10-00100-0- 0
|
|
010-010-0-0- 0
|
|
010-001-0-0- 0
|
|
-10-01000--0 0
|
|
-10-00100--0 0
|
|
010-010-0--0 0
|
|
010-001-0--0 0
|
|
-10--10-010- 0
|
|
-10--01-010- 0
|
|
-10--10-01-0 0
|
|
-10--01-01-0 0
|
|
.names RST.BLIF AS_030.PIN.BLIF inst_AS_030_D0.D
|
|
0- 1
|
|
-1 1
|
|
10 0
|
|
.names VPA.BLIF RST.BLIF inst_VPA_D.D
|
|
1- 1
|
|
-0 1
|
|
01 0
|
|
.names DTACK.BLIF RST.BLIF inst_DTACK_D0.D
|
|
1- 1
|
|
-0 1
|
|
01 0
|
|
.names nEXP_SPACE.BLIF BG_030.BLIF RST.BLIF inst_AS_030_D0.BLIF \
|
|
CLK_000_D_0_.BLIF BG_000DFFreg.BLIF BG_000DFFreg.D
|
|
----01 1
|
|
---0-1 1
|
|
0----1 1
|
|
--0--- 1
|
|
-1---- 1
|
|
10111- 0
|
|
-01--0 0
|
|
.names RST.BLIF A_1_.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \
|
|
inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D
|
|
--1-1 1
|
|
-10-- 1
|
|
--10- 1
|
|
0---- 1
|
|
1-110 0
|
|
100-- 0
|
|
.names RST.BLIF A_1_.BLIF inst_BGACK_030_INTreg.BLIF \
|
|
inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF inst_BGACK_030_INT_D.BLIF \
|
|
inst_AMIGA_BUS_ENABLE_DMA_LOW.D
|
|
--11- 1
|
|
-00-- 1
|
|
--1-0 1
|
|
0---- 1
|
|
1-101 0
|
|
110-- 0
|
|
.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.D
|
|
0- 1
|
|
-1 1
|
|
10 0
|
|
.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D
|
|
0 1
|
|
1 0
|
|
.names nEXP_SPACE.BLIF inst_AS_030_000_SYNC.BLIF SM_AMIGA_5_.BLIF \
|
|
SM_AMIGA_0_.BLIF CLK_000_N_SYNC_0_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_6_.BLIF \
|
|
SM_AMIGA_1_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF N_226
|
|
--00000000 1
|
|
-100-00000 1
|
|
0-00-00000 1
|
|
10--1----- 0
|
|
--------1- 0
|
|
-------1-- 0
|
|
------1--- 0
|
|
-----1---- 0
|
|
---1------ 0
|
|
--1------- 0
|
|
---------1 0
|
|
.names IPL_030DFF_2_reg.BLIF IPL_030_2_
|
|
1 1
|
|
0 0
|
|
.names inst_DS_000_DMA.BLIF AS_000.PIN.BLIF DS_030
|
|
1- 1
|
|
-1 1
|
|
00 0
|
|
.names BG_000DFFreg.BLIF BG_000
|
|
1 1
|
|
0 0
|
|
.names inst_BGACK_030_INTreg.BLIF BGACK_030
|
|
1 1
|
|
0 0
|
|
.names CLK_OUT_INTreg.BLIF CLK_DIV_OUT
|
|
1 1
|
|
0 0
|
|
.names CLK_OUT_INTreg.BLIF CLK_EXP
|
|
1 1
|
|
0 0
|
|
.names FC_1_.BLIF BGACK_000.BLIF FPU_SENSE.BLIF A_DECODE_19_.BLIF \
|
|
A_DECODE_18_.BLIF A_DECODE_17_.BLIF A_DECODE_16_.BLIF FC_0_.BLIF \
|
|
AS_030.PIN.BLIF FPU_CS
|
|
-------0- 1
|
|
------1-- 1
|
|
-----0--- 1
|
|
----1---- 1
|
|
---1----- 1
|
|
--1------ 1
|
|
-0------- 1
|
|
0-------- 1
|
|
--------1 1
|
|
110001010 0
|
|
.names inst_DSACK1_INTreg.BLIF DSACK1
|
|
1 1
|
|
0 0
|
|
.names AVEC
|
|
1
|
|
.names cpu_est_2_.BLIF cpu_est_3_.BLIF cpu_est_1_.BLIF E
|
|
010 1
|
|
101 1
|
|
-00 0
|
|
0-1 0
|
|
11- 0
|
|
.names inst_VMA_INTreg.BLIF VMA
|
|
1 1
|
|
0 0
|
|
.names RESET
|
|
0
|
|
.names AMIGA_ADDR_ENABLE
|
|
0
|
|
.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF AS_000.PIN.BLIF \
|
|
RW_000.PIN.BLIF AMIGA_BUS_DATA_DIR
|
|
0001 1
|
|
-1-0 1
|
|
1--1 0
|
|
--11 0
|
|
-0-0 0
|
|
-1-1 0
|
|
.names inst_BGACK_030_INTreg.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF \
|
|
AMIGA_BUS_ENABLE_LOW
|
|
1- 1
|
|
-1 1
|
|
00 0
|
|
.names CLK_000.BLIF inst_BGACK_030_INTreg.BLIF SM_AMIGA_0_.BLIF \
|
|
inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF SM_AMIGA_i_7_.BLIF AMIGA_BUS_ENABLE_HIGH
|
|
111-- 1
|
|
-0-1- 1
|
|
-1--0 1
|
|
-0-0- 0
|
|
-10-1 0
|
|
01--1 0
|
|
.names A_DECODE_23_.BLIF A_DECODE_22_.BLIF A_DECODE_21_.BLIF A_DECODE_20_.BLIF \
|
|
inst_AS_030_D0.BLIF AHIGH_24_.PIN.BLIF AHIGH_25_.PIN.BLIF AHIGH_26_.PIN.BLIF \
|
|
AHIGH_27_.PIN.BLIF AHIGH_28_.PIN.BLIF AHIGH_29_.PIN.BLIF AHIGH_30_.PIN.BLIF \
|
|
AHIGH_31_.PIN.BLIF CIIN
|
|
1111000000000 1
|
|
-----------1- 0
|
|
----------1-- 0
|
|
---------1--- 0
|
|
--------1---- 0
|
|
-------1----- 0
|
|
------1------ 0
|
|
-----1------- 0
|
|
----1-------- 0
|
|
---0--------- 0
|
|
--0---------- 0
|
|
-0----------- 0
|
|
0------------ 0
|
|
------------1 0
|
|
.names IPL_030DFF_1_reg.BLIF IPL_030_1_
|
|
1 1
|
|
0 0
|
|
.names IPL_030DFF_0_reg.BLIF IPL_030_0_
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF SM_AMIGA_i_7_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF SM_AMIGA_6_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF SM_AMIGA_5_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF SM_AMIGA_4_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF SM_AMIGA_3_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF SM_AMIGA_2_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF SM_AMIGA_1_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF SM_AMIGA_0_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF cpu_est_2_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF cpu_est_3_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF IPL_030DFF_0_reg.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF IPL_030DFF_1_reg.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF IPL_030DFF_2_reg.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF IPL_D0_0_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF IPL_D0_1_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF IPL_D0_2_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_N_SYNC_5_.BLIF CLK_000_N_SYNC_6_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_N_SYNC_6_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_N_SYNC_7_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_N_SYNC_8_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_N_SYNC_9_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_N_SYNC_10_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_N_SYNC_10_.BLIF CLK_000_N_SYNC_11_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_N_SYNC_11_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_N_SYNC_11_.BLIF CLK_000_N_SYNC_12_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_N_SYNC_12_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CYCLE_DMA_0_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CYCLE_DMA_1_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF SIZE_DMA_0_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF SIZE_DMA_1_.C
|
|
1 1
|
|
0 0
|
|
.names cpu_est_0_.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_.D
|
|
10 1
|
|
01 1
|
|
00 0
|
|
11 0
|
|
.names CLK_OSZI.BLIF cpu_est_0_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF cpu_est_1_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_P_SYNC_2_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_P_SYNC_3_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_P_SYNC_4_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_P_SYNC_5_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_P_SYNC_6_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_P_SYNC_6_.BLIF CLK_000_P_SYNC_7_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_P_SYNC_7_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_P_SYNC_8_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_P_SYNC_8_.BLIF CLK_000_P_SYNC_9_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_P_SYNC_9_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_P_SYNC_9_.BLIF CLK_000_P_SYNC_10_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_P_SYNC_10_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_N_SYNC_0_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_N_SYNC_0_.BLIF CLK_000_N_SYNC_1_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_N_SYNC_1_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_N_SYNC_1_.BLIF CLK_000_N_SYNC_2_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_N_SYNC_2_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_N_SYNC_2_.BLIF CLK_000_N_SYNC_3_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_N_SYNC_3_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_N_SYNC_3_.BLIF CLK_000_N_SYNC_4_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_N_SYNC_4_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_N_SYNC_4_.BLIF CLK_000_N_SYNC_5_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_N_SYNC_5_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000.BLIF CLK_000_D_0_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_D_0_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_D_0_.BLIF CLK_000_D_1_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_D_1_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_D_1_.BLIF CLK_000_D_2_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_D_2_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_D_2_.BLIF CLK_000_D_3_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_D_3_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_D_3_.BLIF CLK_000_D_4_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_D_4_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_D_4_.BLIF CLK_000_D_5_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_D_5_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_D_5_.BLIF CLK_000_D_6_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_D_6_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_D_6_.BLIF CLK_000_D_7_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_D_7_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_D_7_.BLIF CLK_000_D_8_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_D_8_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_D_8_.BLIF CLK_000_D_9_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_D_9_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_D_9_.BLIF CLK_000_D_10_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_D_10_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_D_10_.BLIF CLK_000_D_11_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_D_11_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_D_11_.BLIF CLK_000_D_12_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_D_12_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_P_SYNC_0_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_P_SYNC_0_.BLIF CLK_000_P_SYNC_1_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_P_SYNC_1_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF RST_DLY_0_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF RST_DLY_1_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF RST_DLY_2_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_CLK_030_H.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_RESET_OUT.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_DS_000_ENABLE.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_VMA_INTreg.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_UDS_000_INT.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_A0_DMA.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_RW_000_DMA.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_RW_000_INT.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_LDS_000_INT.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_BGACK_030_INTreg.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_AS_000_DMA.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_AS_030_000_SYNC.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_AS_000_INT.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_DSACK1_INTreg.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_DS_000_DMA.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_AS_030_D0.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_VPA_D.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_DTACK_D0.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF BG_000DFFreg.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_N_SYNC_12_.BLIF inst_CLK_000_NE_D0.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_CLK_000_NE_D0.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_BGACK_030_INT_D.C
|
|
1 1
|
|
0 0
|
|
.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_D.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_CLK_OUT_PRE_D.C
|
|
1 1
|
|
0 0
|
|
.names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_INTreg.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_OUT_INTreg.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_CLK_OUT_PRE_50.C
|
|
1 1
|
|
0 0
|
|
.names SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF SIZE_1_
|
|
01 1
|
|
1- 0
|
|
-0 0
|
|
.names AHIGH_31_
|
|
0
|
|
.names inst_AS_000_DMA.BLIF AS_000.PIN.BLIF AS_030
|
|
1- 1
|
|
-1 1
|
|
00 0
|
|
.names inst_AS_000_INT.BLIF AS_030.PIN.BLIF AS_000
|
|
1- 1
|
|
-1 1
|
|
00 0
|
|
.names inst_RW_000_INT.BLIF RW_000
|
|
1 1
|
|
0 0
|
|
.names inst_UDS_000_INT.BLIF inst_DS_000_ENABLE.BLIF UDS_000
|
|
1- 1
|
|
-0 1
|
|
01 0
|
|
.names inst_LDS_000_INT.BLIF inst_DS_000_ENABLE.BLIF LDS_000
|
|
1- 1
|
|
-0 1
|
|
01 0
|
|
.names BERR
|
|
0
|
|
.names inst_RW_000_DMA.BLIF RW
|
|
1 1
|
|
0 0
|
|
.names SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF SIZE_0_
|
|
10 1
|
|
0- 0
|
|
-1 0
|
|
.names AHIGH_30_
|
|
0
|
|
.names AHIGH_29_
|
|
0
|
|
.names AHIGH_28_
|
|
0
|
|
.names AHIGH_27_
|
|
0
|
|
.names AHIGH_26_
|
|
0
|
|
.names AHIGH_25_
|
|
0
|
|
.names AHIGH_24_
|
|
0
|
|
.names inst_A0_DMA.BLIF A_0_
|
|
1 1
|
|
0 0
|
|
.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF \
|
|
AS_030.OE
|
|
001 1
|
|
-1- 0
|
|
1-- 0
|
|
--0 0
|
|
.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF AS_000.OE
|
|
11 1
|
|
0- 0
|
|
-0 0
|
|
.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF RW_000.OE
|
|
11 1
|
|
0- 0
|
|
-0 0
|
|
.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF UDS_000.OE
|
|
11 1
|
|
0- 0
|
|
-0 0
|
|
.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF LDS_000.OE
|
|
11 1
|
|
0- 0
|
|
-0 0
|
|
.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF SIZE_0_.OE
|
|
00 1
|
|
1- 0
|
|
-1 0
|
|
.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF SIZE_1_.OE
|
|
00 1
|
|
1- 0
|
|
-1 0
|
|
.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF \
|
|
AHIGH_24_.OE
|
|
001 1
|
|
-1- 0
|
|
1-- 0
|
|
--0 0
|
|
.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF \
|
|
AHIGH_25_.OE
|
|
001 1
|
|
-1- 0
|
|
1-- 0
|
|
--0 0
|
|
.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF \
|
|
AHIGH_26_.OE
|
|
001 1
|
|
-1- 0
|
|
1-- 0
|
|
--0 0
|
|
.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF \
|
|
AHIGH_27_.OE
|
|
001 1
|
|
-1- 0
|
|
1-- 0
|
|
--0 0
|
|
.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF \
|
|
AHIGH_28_.OE
|
|
001 1
|
|
-1- 0
|
|
1-- 0
|
|
--0 0
|
|
.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF \
|
|
AHIGH_29_.OE
|
|
001 1
|
|
-1- 0
|
|
1-- 0
|
|
--0 0
|
|
.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF \
|
|
AHIGH_30_.OE
|
|
001 1
|
|
-1- 0
|
|
1-- 0
|
|
--0 0
|
|
.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF \
|
|
AHIGH_31_.OE
|
|
001 1
|
|
-1- 0
|
|
1-- 0
|
|
--0 0
|
|
.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF A_0_.OE
|
|
001 1
|
|
-1- 0
|
|
1-- 0
|
|
--0 0
|
|
.names FC_1_.BLIF BGACK_000.BLIF FPU_SENSE.BLIF A_DECODE_19_.BLIF \
|
|
A_DECODE_18_.BLIF A_DECODE_17_.BLIF A_DECODE_16_.BLIF FC_0_.BLIF \
|
|
AS_030.PIN.BLIF BERR.OE
|
|
111001010 1
|
|
-------0- 0
|
|
------1-- 0
|
|
-----0--- 0
|
|
----1---- 0
|
|
---1----- 0
|
|
--0------ 0
|
|
-0------- 0
|
|
0-------- 0
|
|
--------1 0
|
|
.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF RW.OE
|
|
01 1
|
|
1- 0
|
|
-0 0
|
|
.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF \
|
|
DS_030.OE
|
|
001 1
|
|
-1- 0
|
|
1-- 0
|
|
--0 0
|
|
.names nEXP_SPACE.BLIF DSACK1.OE
|
|
1 1
|
|
0 0
|
|
.names inst_RESET_OUT.BLIF RESET.OE
|
|
0 1
|
|
1 0
|
|
.names A_DECODE_23_.BLIF nEXP_SPACE.BLIF A_DECODE_22_.BLIF A_DECODE_21_.BLIF \
|
|
A_DECODE_20_.BLIF inst_AS_030_D0.BLIF AHIGH_24_.PIN.BLIF AHIGH_25_.PIN.BLIF \
|
|
AHIGH_26_.PIN.BLIF AHIGH_27_.PIN.BLIF AHIGH_28_.PIN.BLIF AHIGH_29_.PIN.BLIF \
|
|
AHIGH_30_.PIN.BLIF AHIGH_31_.PIN.BLIF CIIN.OE
|
|
1-111000000000 1
|
|
-1------------ 1
|
|
-0----------1- 0
|
|
-0---------1-- 0
|
|
-0--------1--- 0
|
|
-0-------1---- 0
|
|
-0------1----- 0
|
|
-0-----1------ 0
|
|
-0----1------- 0
|
|
-0---1-------- 0
|
|
-0--0--------- 0
|
|
-0-0---------- 0
|
|
-00----------- 0
|
|
00------------ 0
|
|
-0-----------1 0
|
|
.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_CLK_030_H.D.X1
|
|
10 1
|
|
0- 0
|
|
-1 0
|
|
.names CLK_030.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \
|
|
CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF inst_CLK_030_H.BLIF AS_000.PIN.BLIF \
|
|
UDS_000.PIN.BLIF LDS_000.PIN.BLIF inst_CLK_030_H.D.X2
|
|
-10-00---- 1
|
|
-10----1-- 1
|
|
110---0--- 1
|
|
-101--0--- 1
|
|
-10-----11 1
|
|
-10-11---- 1
|
|
-0-------- 0
|
|
--1------- 0
|
|
----01100- 0
|
|
----10100- 0
|
|
----0110-0 0
|
|
----1010-0 0
|
|
0--001-00- 0
|
|
0--010-00- 0
|
|
0--001-0-0 0
|
|
0--010-0-0 0
|
|
.names RST.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_3_.D.X1
|
|
11 1
|
|
0- 0
|
|
-0 0
|
|
.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_2_.BLIF cpu_est_3_.BLIF \
|
|
cpu_est_0_.BLIF cpu_est_1_.BLIF inst_VPA_D.BLIF inst_DTACK_D0.BLIF \
|
|
CLK_000_P_SYNC_10_.BLIF SM_AMIGA_4_.BLIF inst_CLK_000_NE_D0.BLIF \
|
|
SM_AMIGA_3_.BLIF BERR.PIN.BLIF SM_AMIGA_3_.D.X2
|
|
1-------11-0- 1
|
|
1----------10 1
|
|
1001000--011- 1
|
|
1-----10-011- 1
|
|
0------------ 0
|
|
--------0--0- 0
|
|
---------0-0- 0
|
|
---------1-11 0
|
|
----------011 0
|
|
-1----0----11 0
|
|
--1---0----11 0
|
|
---0--0----11 0
|
|
----1-0----11 0
|
|
-----10----11 0
|
|
------11---11 0
|
|
.end
|