mirror of https://github.com/kr239/68030tk.git
12830 lines
960 KiB
Plaintext
12830 lines
960 KiB
Plaintext
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141 "number of signals after reading design file"
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"sig sig sig pair blk fan PT xor sync"
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"num name type sig num out pin node cnt PT type"
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"--- ---- ---- ---- --- --- --- ---- --- --- ----"
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40 BERR 5 -1 4 4 1 2 5 7 40 -1 1 0 21
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79 RW_000 5 363 7 3 0 4 6 79 -1 3 0 21
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41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
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68 A0 5 364 6 2 0 6 68 -1 3 0 21
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70 RW 5 372 6 2 1 7 70 -1 2 0 21
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81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
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31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
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30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
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97 DS_030 5 -1 0 1 3 97 -1 1 0 21
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78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21
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69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21
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8 IPL_030_2_ 5 362 1 0 8 -1 10 0 21
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7 IPL_030_0_ 5 366 1 0 7 -1 10 0 21
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6 IPL_030_1_ 5 365 1 0 6 -1 10 0 21
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65 E 5 370 6 0 65 -1 5 0 21
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80 DSACK1 5 369 7 0 80 -1 4 0 21
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82 BGACK_030 5 368 7 0 82 -1 3 0 21
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34 VMA 5 371 3 0 34 -1 3 0 21
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47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
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33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
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28 BG_000 5 367 3 0 28 -1 2 0 21
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91 AVEC 0 0 0 91 -1 1 0 21
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77 FPU_CS 0 7 0 77 -1 1 0 21
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64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
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46 CIIN 0 4 0 46 -1 1 0 21
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32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
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19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
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9 CLK_EXP 0 1 0 9 -1 1 0 21
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2 RESET 0 1 0 2 -1 1 0 21
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368 RN_BGACK_030 3 82 7 7 0 2 3 4 5 6 7 82 -1 3 0 21
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314 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21
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299 inst_nEXP_SPACE_D0reg 3 -1 1 6 0 3 4 5 6 7 -1 -1 1 0 21
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318 inst_CLK_000_PE 3 -1 2 5 0 2 3 5 7 -1 -1 1 0 21
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298 inst_AS_030_D0 3 -1 7 5 1 3 4 5 7 -1 -1 1 0 21
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317 inst_CLK_000_D0 3 -1 0 4 1 3 4 5 -1 -1 1 0 21
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360 SM_AMIGA_i_7_ 3 -1 5 3 3 5 7 -1 -1 14 0 21
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370 RN_E 3 65 6 3 2 3 6 65 -1 5 0 21
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326 SM_AMIGA_3_ 3 -1 2 3 1 2 5 -1 -1 5 0 21
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294 cpu_est_1_ 3 -1 6 3 2 3 6 -1 -1 5 0 21
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322 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 4 0 21
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330 SM_AMIGA_6_ 3 -1 5 3 0 5 6 -1 -1 3 0 21
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296 SM_AMIGA_5_ 3 -1 5 3 1 5 7 -1 -1 3 0 21
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293 cpu_est_0_ 3 -1 6 3 2 3 6 -1 -1 2 0 21
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327 inst_CLK_000_NE_D0 3 -1 0 3 2 5 6 -1 -1 1 0 21
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320 inst_CLK_000_NE 3 -1 0 3 0 3 5 -1 -1 1 0 21
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302 inst_BGACK_030_INT_D 3 -1 7 3 2 5 6 -1 -1 1 0 21
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303 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
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357 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 4 0 21
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311 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 4 0 21
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371 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21
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358 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21
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356 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21
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355 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
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310 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 3 0 21
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308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
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307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
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329 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21
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328 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 2 0 21
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295 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21
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316 inst_CLK_000_D1 3 -1 4 2 1 5 -1 -1 1 0 21
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309 inst_VPA_D 3 -1 3 2 2 3 -1 -1 1 0 21
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300 inst_DS_030_D0 3 -1 3 2 0 6 -1 -1 1 0 21
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366 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
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365 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
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362 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
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304 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
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354 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
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301 inst_AS_030_000_SYNC 3 -1 5 1 5 -1 -1 7 0 21
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369 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
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332 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21
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364 RN_A0 3 68 6 1 6 68 -1 3 0 21
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363 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
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331 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21
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306 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
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372 RN_RW 3 70 6 1 6 70 -1 2 0 21
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367 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
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361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
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359 N_61_i 3 -1 2 1 5 -1 -1 2 0 21
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333 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21
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305 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21
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297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21
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353 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
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352 CLK_000_N_SYNC_9_ 3 -1 0 1 7 -1 -1 1 0 21
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351 CLK_000_N_SYNC_8_ 3 -1 2 1 0 -1 -1 1 0 21
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350 CLK_000_N_SYNC_7_ 3 -1 6 1 2 -1 -1 1 0 21
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349 CLK_000_N_SYNC_6_ 3 -1 2 1 6 -1 -1 1 0 21
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348 CLK_000_N_SYNC_5_ 3 -1 3 1 2 -1 -1 1 0 21
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347 CLK_000_N_SYNC_4_ 3 -1 2 1 3 -1 -1 1 0 21
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346 CLK_000_N_SYNC_3_ 3 -1 6 1 2 -1 -1 1 0 21
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345 CLK_000_N_SYNC_2_ 3 -1 1 1 6 -1 -1 1 0 21
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344 CLK_000_N_SYNC_1_ 3 -1 1 1 1 -1 -1 1 0 21
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343 CLK_000_N_SYNC_0_ 3 -1 1 1 1 -1 -1 1 0 21
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342 CLK_000_P_SYNC_8_ 3 -1 1 1 0 -1 -1 1 0 21
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341 CLK_000_P_SYNC_7_ 3 -1 5 1 1 -1 -1 1 0 21
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340 CLK_000_P_SYNC_6_ 3 -1 5 1 5 -1 -1 1 0 21
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339 CLK_000_P_SYNC_5_ 3 -1 1 1 5 -1 -1 1 0 21
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338 CLK_000_P_SYNC_4_ 3 -1 4 1 1 -1 -1 1 0 21
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337 CLK_000_P_SYNC_3_ 3 -1 2 1 4 -1 -1 1 0 21
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336 CLK_000_P_SYNC_2_ 3 -1 2 1 2 -1 -1 1 0 21
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335 CLK_000_P_SYNC_1_ 3 -1 6 1 2 -1 -1 1 0 21
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334 CLK_000_P_SYNC_0_ 3 -1 5 1 6 -1 -1 1 0 21
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325 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21
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324 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
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323 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21
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321 CLK_000_N_SYNC_11_ 3 -1 7 1 0 -1 -1 1 0 21
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319 CLK_000_P_SYNC_9_ 3 -1 0 1 2 -1 -1 1 0 21
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315 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
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313 inst_DTACK_D0 3 -1 0 1 2 -1 -1 1 0 21
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312 inst_CLK_OUT_PRE_D 3 -1 4 1 7 -1 -1 1 0 21
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60 CLK_OSZI 9 -1 0 60 -1
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85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
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96 A_19_ 1 -1 -1 3 4 5 7 96 -1
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95 A_16_ 1 -1 -1 3 4 5 7 95 -1
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94 A_18_ 1 -1 -1 3 4 5 7 94 -1
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63 CLK_030 1 -1 -1 3 0 1 7 63 -1
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58 A_17_ 1 -1 -1 3 4 5 7 58 -1
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57 FC_1_ 1 -1 -1 3 4 5 7 57 -1
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56 FC_0_ 1 -1 -1 3 4 5 7 56 -1
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90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
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67 IPL_2_ 1 -1 -1 2 1 2 67 -1
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66 IPL_0_ 1 -1 -1 2 1 2 66 -1
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59 A1 1 -1 -1 2 2 6 59 -1
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27 BGACK_000 1 -1 -1 2 4 7 27 -1
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93 A_21_ 1 -1 -1 1 4 93 -1
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92 A_20_ 1 -1 -1 1 4 92 -1
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84 A_23_ 1 -1 -1 1 4 84 -1
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83 A_22_ 1 -1 -1 1 4 83 -1
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55 IPL_1_ 1 -1 -1 1 1 55 -1
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35 VPA 1 -1 -1 1 3 35 -1
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29 DTACK 1 -1 -1 1 0 29 -1
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20 BG_030 1 -1 -1 1 3 20 -1
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18 A_24_ 1 -1 -1 1 4 18 -1
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17 A_25_ 1 -1 -1 1 4 17 -1
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16 A_26_ 1 -1 -1 1 4 16 -1
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15 A_27_ 1 -1 -1 1 4 15 -1
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14 A_28_ 1 -1 -1 1 4 14 -1
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13 nEXP_SPACE 1 -1 -1 1 1 13 -1
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10 CLK_000 1 -1 -1 1 0 10 -1
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5 A_29_ 1 -1 -1 1 4 5 -1
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4 A_30_ 1 -1 -1 1 4 4 -1
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3 A_31_ 1 -1 -1 1 4 3 -1
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141 "number of signals after reading design file"
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"sig sig sig pair blk fan PT xor sync"
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"num name type sig num out pin node cnt PT type"
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"--- ---- ---- ---- --- --- --- ---- --- --- ----"
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40 BERR 5 -1 4 5 0 1 2 5 7 40 -1 1 0 21
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79 RW_000 5 363 7 3 0 4 6 79 -1 3 0 21
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41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
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70 RW 5 372 6 2 1 7 70 -1 2 0 21
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81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
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31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
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30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
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68 A0 5 366 6 1 2 68 -1 3 0 21
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97 DS_030 5 -1 0 1 3 97 -1 1 0 21
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78 SIZE_1_ 5 -1 7 1 2 78 -1 1 0 21
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69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21
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8 IPL_030_2_ 5 362 1 0 8 -1 10 0 21
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7 IPL_030_0_ 5 365 1 0 7 -1 10 0 21
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6 IPL_030_1_ 5 364 1 0 6 -1 10 0 21
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65 E 5 370 6 0 65 -1 5 0 21
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80 DSACK1 5 369 7 0 80 -1 4 0 21
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82 BGACK_030 5 368 7 0 82 -1 3 0 21
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34 VMA 5 371 3 0 34 -1 3 0 21
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47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
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33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
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28 BG_000 5 367 3 0 28 -1 2 0 21
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91 AVEC 0 0 0 91 -1 1 0 21
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77 FPU_CS 0 7 0 77 -1 1 0 21
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64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
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46 CIIN 0 4 0 46 -1 1 0 21
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32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
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19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
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9 CLK_EXP 0 1 0 9 -1 1 0 21
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2 RESET 0 1 0 2 -1 1 0 21
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368 RN_BGACK_030 3 82 7 7 0 2 3 4 5 6 7 82 -1 3 0 21
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315 inst_RESET_OUT 3 -1 6 6 0 1 3 4 6 7 -1 -1 2 0 21
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321 inst_CLK_000_NE 3 -1 0 6 0 1 2 3 5 6 -1 -1 1 0 21
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300 inst_nEXP_SPACE_D0reg 3 -1 5 6 0 3 4 5 6 7 -1 -1 1 0 21
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319 inst_CLK_000_PE 3 -1 3 5 0 2 3 5 7 -1 -1 1 0 21
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299 inst_AS_030_D0 3 -1 7 5 1 3 4 5 7 -1 -1 1 0 21
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356 SM_AMIGA_1_ 3 -1 2 4 0 2 5 7 -1 -1 3 0 21
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297 SM_AMIGA_5_ 3 -1 5 4 1 2 5 7 -1 -1 3 0 21
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329 SM_AMIGA_0_ 3 -1 0 4 0 2 5 7 -1 -1 2 0 21
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360 SM_AMIGA_i_7_ 3 -1 2 3 3 5 7 -1 -1 14 0 21
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370 RN_E 3 65 6 3 2 3 6 65 -1 5 0 21
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327 SM_AMIGA_3_ 3 -1 2 3 1 2 5 -1 -1 5 0 21
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295 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 5 0 21
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323 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 4 0 21
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294 cpu_est_0_ 3 -1 3 3 2 3 6 -1 -1 2 0 21
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328 inst_CLK_000_NE_D0 3 -1 3 3 2 3 6 -1 -1 1 0 21
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318 inst_CLK_000_D0 3 -1 1 3 3 4 5 -1 -1 1 0 21
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313 inst_CLK_OUT_PRE_D 3 -1 0 3 1 6 7 -1 -1 1 0 21
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303 inst_BGACK_030_INT_D 3 -1 7 3 0 5 6 -1 -1 1 0 21
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304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
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358 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 4 0 21
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333 RST_DLY_1_ 3 -1 1 2 1 6 -1 -1 4 0 21
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312 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 4 0 21
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371 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21
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359 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21
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357 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21
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332 RST_DLY_0_ 3 -1 1 2 1 6 -1 -1 3 0 21
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331 SM_AMIGA_6_ 3 -1 5 2 2 5 -1 -1 3 0 21
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311 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21
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309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
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308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
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334 RST_DLY_2_ 3 -1 6 2 1 6 -1 -1 2 0 21
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330 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 2 0 3 -1 -1 2 0 21
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298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21
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296 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21
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317 inst_CLK_000_D1 3 -1 4 2 4 5 -1 -1 1 0 21
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316 inst_CLK_OUT_PRE_50 3 -1 3 2 0 3 -1 -1 1 0 21
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310 inst_VPA_D 3 -1 3 2 2 3 -1 -1 1 0 21
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365 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
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364 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
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362 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
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305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
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355 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
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302 inst_AS_030_000_SYNC 3 -1 5 1 5 -1 -1 7 0 21
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369 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
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293 N_301 3 -1 5 1 2 -1 -1 4 0 21
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366 RN_A0 3 68 6 1 6 68 -1 3 0 21
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363 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
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307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
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372 RN_RW 3 70 6 1 6 70 -1 2 0 21
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367 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
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361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
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306 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21
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354 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
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353 CLK_000_N_SYNC_9_ 3 -1 1 1 7 -1 -1 1 0 21
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352 CLK_000_N_SYNC_8_ 3 -1 6 1 1 -1 -1 1 0 21
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351 CLK_000_N_SYNC_7_ 3 -1 3 1 6 -1 -1 1 0 21
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350 CLK_000_N_SYNC_6_ 3 -1 0 1 3 -1 -1 1 0 21
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349 CLK_000_N_SYNC_5_ 3 -1 1 1 0 -1 -1 1 0 21
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348 CLK_000_N_SYNC_4_ 3 -1 6 1 1 -1 -1 1 0 21
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347 CLK_000_N_SYNC_3_ 3 -1 5 1 6 -1 -1 1 0 21
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346 CLK_000_N_SYNC_2_ 3 -1 6 1 5 -1 -1 1 0 21
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345 CLK_000_N_SYNC_1_ 3 -1 1 1 6 -1 -1 1 0 21
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344 CLK_000_N_SYNC_0_ 3 -1 4 1 1 -1 -1 1 0 21
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343 CLK_000_P_SYNC_8_ 3 -1 2 1 1 -1 -1 1 0 21
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342 CLK_000_P_SYNC_7_ 3 -1 5 1 2 -1 -1 1 0 21
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341 CLK_000_P_SYNC_6_ 3 -1 1 1 5 -1 -1 1 0 21
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340 CLK_000_P_SYNC_5_ 3 -1 0 1 1 -1 -1 1 0 21
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339 CLK_000_P_SYNC_4_ 3 -1 4 1 0 -1 -1 1 0 21
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338 CLK_000_P_SYNC_3_ 3 -1 3 1 4 -1 -1 1 0 21
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337 CLK_000_P_SYNC_2_ 3 -1 0 1 3 -1 -1 1 0 21
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336 CLK_000_P_SYNC_1_ 3 -1 6 1 0 -1 -1 1 0 21
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335 CLK_000_P_SYNC_0_ 3 -1 4 1 6 -1 -1 1 0 21
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326 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
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325 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21
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324 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21
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322 CLK_000_N_SYNC_11_ 3 -1 7 1 0 -1 -1 1 0 21
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320 CLK_000_P_SYNC_9_ 3 -1 1 1 3 -1 -1 1 0 21
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314 inst_DTACK_D0 3 -1 5 1 2 -1 -1 1 0 21
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301 inst_DS_030_D0 3 -1 3 1 2 -1 -1 1 0 21
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60 CLK_OSZI 9 -1 0 60 -1
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85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
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96 A_19_ 1 -1 -1 3 4 5 7 96 -1
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95 A_16_ 1 -1 -1 3 4 5 7 95 -1
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94 A_18_ 1 -1 -1 3 4 5 7 94 -1
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58 A_17_ 1 -1 -1 3 4 5 7 58 -1
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57 FC_1_ 1 -1 -1 3 4 5 7 57 -1
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56 FC_0_ 1 -1 -1 3 4 5 7 56 -1
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90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
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66 IPL_0_ 1 -1 -1 2 1 6 66 -1
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63 CLK_030 1 -1 -1 2 0 7 63 -1
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55 IPL_1_ 1 -1 -1 2 1 6 55 -1
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27 BGACK_000 1 -1 -1 2 4 7 27 -1
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93 A_21_ 1 -1 -1 1 4 93 -1
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92 A_20_ 1 -1 -1 1 4 92 -1
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84 A_23_ 1 -1 -1 1 4 84 -1
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83 A_22_ 1 -1 -1 1 4 83 -1
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67 IPL_2_ 1 -1 -1 1 1 67 -1
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59 A1 1 -1 -1 1 0 59 -1
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35 VPA 1 -1 -1 1 3 35 -1
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29 DTACK 1 -1 -1 1 5 29 -1
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20 BG_030 1 -1 -1 1 3 20 -1
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18 A_24_ 1 -1 -1 1 4 18 -1
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17 A_25_ 1 -1 -1 1 4 17 -1
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16 A_26_ 1 -1 -1 1 4 16 -1
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15 A_27_ 1 -1 -1 1 4 15 -1
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14 A_28_ 1 -1 -1 1 4 14 -1
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13 nEXP_SPACE 1 -1 -1 1 5 13 -1
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10 CLK_000 1 -1 -1 1 1 10 -1
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5 A_29_ 1 -1 -1 1 4 5 -1
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4 A_30_ 1 -1 -1 1 4 4 -1
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3 A_31_ 1 -1 -1 1 4 3 -1
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141 "number of signals after reading design file"
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"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21
|
|
40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21
|
|
79 RW_000 5 366 7 3 0 4 6 79 -1 3 0 21
|
|
70 RW 5 372 6 2 0 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
68 A0 5 367 6 1 1 68 -1 3 0 21
|
|
97 DS_030 5 -1 0 1 3 97 -1 1 0 21
|
|
78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 365 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 364 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 363 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 370 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 369 7 0 82 -1 3 0 21
|
|
34 VMA 5 371 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 368 3 0 28 -1 2 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
369 RN_BGACK_030 3 82 7 7 0 2 3 4 5 6 7 82 -1 3 0 21
|
|
316 inst_RESET_OUT 3 -1 0 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
301 inst_nEXP_SPACE_D0reg 3 -1 6 6 0 3 4 5 6 7 -1 -1 1 0 21
|
|
320 inst_CLK_000_PE 3 -1 3 5 0 2 3 5 7 -1 -1 1 0 21
|
|
300 inst_AS_030_D0 3 -1 7 5 0 3 4 5 7 -1 -1 1 0 21
|
|
322 inst_CLK_000_NE 3 -1 6 4 0 2 3 5 -1 -1 1 0 21
|
|
361 SM_AMIGA_i_7_ 3 -1 5 3 3 5 7 -1 -1 13 0 21
|
|
327 SM_AMIGA_3_ 3 -1 2 3 0 2 5 -1 -1 5 0 21
|
|
294 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 4 0 21
|
|
357 SM_AMIGA_1_ 3 -1 5 3 2 5 7 -1 -1 3 0 21
|
|
298 SM_AMIGA_5_ 3 -1 5 3 0 5 7 -1 -1 3 0 21
|
|
295 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 3 0 21
|
|
293 cpu_est_1_ 3 -1 2 3 2 3 6 -1 -1 3 0 21
|
|
329 SM_AMIGA_0_ 3 -1 2 3 2 5 7 -1 -1 2 0 21
|
|
314 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
|
304 inst_BGACK_030_INT_D 3 -1 7 3 2 5 6 -1 -1 1 0 21
|
|
305 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
359 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 4 0 21
|
|
313 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 4 0 21
|
|
371 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21
|
|
360 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21
|
|
358 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21
|
|
332 SM_AMIGA_6_ 3 -1 5 2 1 5 -1 -1 3 0 21
|
|
312 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21
|
|
310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
330 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
307 CYCLE_DMA_0_ 3 -1 2 2 0 2 -1 -1 2 0 21
|
|
297 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21
|
|
296 cpu_est_0_ 3 -1 2 2 2 3 -1 -1 2 0 21
|
|
328 inst_CLK_000_NE_D0 3 -1 3 2 2 3 -1 -1 1 0 21
|
|
319 inst_CLK_000_D0 3 -1 1 2 3 5 -1 -1 1 0 21
|
|
318 inst_CLK_000_D1 3 -1 5 2 3 5 -1 -1 1 0 21
|
|
311 inst_VPA_D 3 -1 0 2 2 3 -1 -1 1 0 21
|
|
365 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
364 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
363 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
306 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
356 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
303 inst_AS_030_000_SYNC 3 -1 5 1 5 -1 -1 7 0 21
|
|
370 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
334 RST_DLY_1_ 3 -1 0 1 0 -1 -1 4 0 21
|
|
367 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
366 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
333 RST_DLY_0_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
308 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
372 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
368 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
362 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
335 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
331 N_270_i 3 -1 2 1 5 -1 -1 2 0 21
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21
|
|
355 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
354 CLK_000_N_SYNC_9_ 3 -1 3 1 7 -1 -1 1 0 21
|
|
353 CLK_000_N_SYNC_8_ 3 -1 2 1 3 -1 -1 1 0 21
|
|
352 CLK_000_N_SYNC_7_ 3 -1 3 1 2 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_6_ 3 -1 6 1 3 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_5_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_4_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_3_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_2_ 3 -1 2 1 2 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_1_ 3 -1 1 1 2 -1 -1 1 0 21
|
|
345 CLK_000_N_SYNC_0_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
344 CLK_000_P_SYNC_8_ 3 -1 1 1 2 -1 -1 1 0 21
|
|
343 CLK_000_P_SYNC_7_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
342 CLK_000_P_SYNC_6_ 3 -1 4 1 0 -1 -1 1 0 21
|
|
341 CLK_000_P_SYNC_5_ 3 -1 0 1 4 -1 -1 1 0 21
|
|
340 CLK_000_P_SYNC_4_ 3 -1 3 1 0 -1 -1 1 0 21
|
|
339 CLK_000_P_SYNC_3_ 3 -1 4 1 3 -1 -1 1 0 21
|
|
338 CLK_000_P_SYNC_2_ 3 -1 5 1 4 -1 -1 1 0 21
|
|
337 CLK_000_P_SYNC_1_ 3 -1 6 1 5 -1 -1 1 0 21
|
|
336 CLK_000_P_SYNC_0_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
326 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
325 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
324 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
323 CLK_000_N_SYNC_11_ 3 -1 7 1 6 -1 -1 1 0 21
|
|
321 CLK_000_P_SYNC_9_ 3 -1 2 1 3 -1 -1 1 0 21
|
|
317 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
315 inst_DTACK_D0 3 -1 6 1 2 -1 -1 1 0 21
|
|
302 inst_DS_030_D0 3 -1 3 1 1 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 4 5 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 4 5 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 4 5 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 4 5 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 4 5 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 4 5 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
59 A1 1 -1 -1 2 2 6 59 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
|
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
|
35 VPA 1 -1 -1 1 0 35 -1
|
|
29 DTACK 1 -1 -1 1 6 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 6 13 -1
|
|
10 CLK_000 1 -1 -1 1 1 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
140 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 4 2 5 6 7 40 -1 1 0 21
|
|
79 RW_000 5 365 7 3 0 4 6 79 -1 3 0 21
|
|
81 AS_030 5 -1 7 3 3 4 7 81 -1 1 0 21
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
70 RW 5 371 6 2 2 7 70 -1 2 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
68 A0 5 366 6 1 0 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 362 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 364 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 363 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 369 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 368 7 0 82 -1 3 0 21
|
|
34 VMA 5 370 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 367 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
368 RN_BGACK_030 3 82 7 7 0 2 3 4 5 6 7 82 -1 3 0 21
|
|
301 inst_nEXP_SPACE_D0reg 3 -1 5 7 0 1 3 4 5 6 7 -1 -1 1 0 21
|
|
316 inst_RESET_OUT 3 -1 1 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
320 inst_CLK_000_PE 3 -1 6 6 0 2 3 5 6 7 -1 -1 1 0 21
|
|
300 inst_AS_030_D0 3 -1 3 5 2 3 4 5 7 -1 -1 1 0 21
|
|
357 SM_AMIGA_1_ 3 -1 2 4 1 2 6 7 -1 -1 3 0 21
|
|
355 SM_AMIGA_6_ 3 -1 5 4 0 1 2 5 -1 -1 3 0 21
|
|
298 SM_AMIGA_5_ 3 -1 2 4 1 2 5 7 -1 -1 3 0 21
|
|
329 SM_AMIGA_0_ 3 -1 6 4 1 2 6 7 -1 -1 2 0 21
|
|
322 inst_CLK_000_NE 3 -1 3 4 1 2 3 6 -1 -1 1 0 21
|
|
360 SM_AMIGA_i_7_ 3 -1 2 3 3 5 7 -1 -1 14 0 21
|
|
293 cpu_est_2_ 3 -1 3 3 2 3 6 -1 -1 4 0 21
|
|
296 cpu_est_1_ 3 -1 2 3 2 3 6 -1 -1 3 0 21
|
|
294 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 3 0 21
|
|
319 inst_CLK_000_D0 3 -1 0 3 1 3 5 -1 -1 1 0 21
|
|
314 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
|
305 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
303 inst_AS_030_000_SYNC 3 -1 5 2 1 5 -1 -1 7 0 21
|
|
327 SM_AMIGA_3_ 3 -1 2 2 1 2 -1 -1 5 0 21
|
|
359 SM_AMIGA_2_ 3 -1 2 2 1 2 -1 -1 4 0 21
|
|
370 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21
|
|
358 SM_AMIGA_4_ 3 -1 2 2 1 2 -1 -1 3 0 21
|
|
331 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21
|
|
313 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21
|
|
310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
330 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 2 3 5 -1 -1 2 0 21
|
|
312 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21
|
|
297 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21
|
|
295 cpu_est_0_ 3 -1 3 2 2 3 -1 -1 2 0 21
|
|
328 inst_CLK_000_NE_D0 3 -1 3 2 2 3 -1 -1 1 0 21
|
|
318 inst_CLK_000_D1 3 -1 5 2 1 5 -1 -1 1 0 21
|
|
311 inst_VPA_D 3 -1 6 2 2 3 -1 -1 1 0 21
|
|
304 inst_BGACK_030_INT_D 3 -1 7 2 5 6 -1 -1 1 0 21
|
|
364 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
363 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
362 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
306 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
356 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
369 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
333 RST_DLY_1_ 3 -1 1 1 1 -1 -1 4 0 21
|
|
302 N_218_i 3 -1 1 1 2 -1 -1 4 0 21
|
|
366 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
365 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
332 RST_DLY_0_ 3 -1 1 1 1 -1 -1 3 0 21
|
|
308 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
371 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
367 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
334 RST_DLY_2_ 3 -1 1 1 1 -1 -1 2 0 21
|
|
307 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
354 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
353 CLK_000_N_SYNC_9_ 3 -1 0 1 7 -1 -1 1 0 21
|
|
352 CLK_000_N_SYNC_8_ 3 -1 2 1 0 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_7_ 3 -1 4 1 2 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_6_ 3 -1 7 1 4 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_5_ 3 -1 1 1 7 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_4_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_3_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_2_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
345 CLK_000_N_SYNC_1_ 3 -1 6 1 5 -1 -1 1 0 21
|
|
344 CLK_000_N_SYNC_0_ 3 -1 5 1 6 -1 -1 1 0 21
|
|
343 CLK_000_P_SYNC_8_ 3 -1 4 1 6 -1 -1 1 0 21
|
|
342 CLK_000_P_SYNC_7_ 3 -1 3 1 4 -1 -1 1 0 21
|
|
341 CLK_000_P_SYNC_6_ 3 -1 3 1 3 -1 -1 1 0 21
|
|
340 CLK_000_P_SYNC_5_ 3 -1 0 1 3 -1 -1 1 0 21
|
|
339 CLK_000_P_SYNC_4_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
338 CLK_000_P_SYNC_3_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
337 CLK_000_P_SYNC_2_ 3 -1 0 1 3 -1 -1 1 0 21
|
|
336 CLK_000_P_SYNC_1_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
335 CLK_000_P_SYNC_0_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
326 IPL_D0_2_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
325 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
324 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
323 CLK_000_N_SYNC_11_ 3 -1 7 1 3 -1 -1 1 0 21
|
|
321 CLK_000_P_SYNC_9_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
317 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
315 inst_DTACK_D0 3 -1 6 1 2 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 4 5 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 4 5 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 4 5 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 4 5 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 4 5 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 4 5 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
67 IPL_2_ 1 -1 -1 2 1 5 67 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
|
59 A1 1 -1 -1 1 5 59 -1
|
|
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
|
35 VPA 1 -1 -1 1 6 35 -1
|
|
29 DTACK 1 -1 -1 1 6 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 5 13 -1
|
|
10 CLK_000 1 -1 -1 1 0 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
140 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 4 2 5 6 7 40 -1 1 0 21
|
|
79 RW_000 5 365 7 3 0 4 6 79 -1 3 0 21
|
|
81 AS_030 5 -1 7 3 3 4 7 81 -1 1 0 21
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
70 RW 5 371 6 2 2 7 70 -1 2 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
68 A0 5 366 6 1 0 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 362 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 364 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 363 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 369 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 368 7 0 82 -1 3 0 21
|
|
34 VMA 5 370 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 367 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
368 RN_BGACK_030 3 82 7 7 0 2 3 4 5 6 7 82 -1 3 0 21
|
|
301 inst_nEXP_SPACE_D0reg 3 -1 5 7 0 1 3 4 5 6 7 -1 -1 1 0 21
|
|
316 inst_RESET_OUT 3 -1 1 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
320 inst_CLK_000_PE 3 -1 6 6 0 2 3 5 6 7 -1 -1 1 0 21
|
|
300 inst_AS_030_D0 3 -1 3 5 2 3 4 5 7 -1 -1 1 0 21
|
|
357 SM_AMIGA_1_ 3 -1 2 4 1 2 6 7 -1 -1 3 0 21
|
|
355 SM_AMIGA_6_ 3 -1 5 4 0 1 2 5 -1 -1 3 0 21
|
|
298 SM_AMIGA_5_ 3 -1 2 4 1 2 5 7 -1 -1 3 0 21
|
|
329 SM_AMIGA_0_ 3 -1 6 4 1 2 6 7 -1 -1 2 0 21
|
|
322 inst_CLK_000_NE 3 -1 3 4 1 2 3 6 -1 -1 1 0 21
|
|
360 SM_AMIGA_i_7_ 3 -1 2 3 3 5 7 -1 -1 14 0 21
|
|
293 cpu_est_2_ 3 -1 3 3 2 3 6 -1 -1 4 0 21
|
|
296 cpu_est_1_ 3 -1 2 3 2 3 6 -1 -1 3 0 21
|
|
294 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 3 0 21
|
|
319 inst_CLK_000_D0 3 -1 0 3 1 3 5 -1 -1 1 0 21
|
|
314 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
|
305 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
303 inst_AS_030_000_SYNC 3 -1 5 2 1 5 -1 -1 7 0 21
|
|
327 SM_AMIGA_3_ 3 -1 2 2 1 2 -1 -1 5 0 21
|
|
359 SM_AMIGA_2_ 3 -1 2 2 1 2 -1 -1 4 0 21
|
|
370 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21
|
|
358 SM_AMIGA_4_ 3 -1 2 2 1 2 -1 -1 3 0 21
|
|
331 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21
|
|
313 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21
|
|
310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
330 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 2 3 5 -1 -1 2 0 21
|
|
312 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21
|
|
297 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21
|
|
295 cpu_est_0_ 3 -1 3 2 2 3 -1 -1 2 0 21
|
|
328 inst_CLK_000_NE_D0 3 -1 3 2 2 3 -1 -1 1 0 21
|
|
318 inst_CLK_000_D1 3 -1 5 2 1 5 -1 -1 1 0 21
|
|
311 inst_VPA_D 3 -1 6 2 2 3 -1 -1 1 0 21
|
|
304 inst_BGACK_030_INT_D 3 -1 7 2 5 6 -1 -1 1 0 21
|
|
364 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
363 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
362 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
306 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
356 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
369 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
333 RST_DLY_1_ 3 -1 1 1 1 -1 -1 4 0 21
|
|
302 N_218_i 3 -1 1 1 2 -1 -1 4 0 21
|
|
366 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
365 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
332 RST_DLY_0_ 3 -1 1 1 1 -1 -1 3 0 21
|
|
308 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
371 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
367 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
334 RST_DLY_2_ 3 -1 1 1 1 -1 -1 2 0 21
|
|
307 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
354 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
353 CLK_000_N_SYNC_9_ 3 -1 0 1 7 -1 -1 1 0 21
|
|
352 CLK_000_N_SYNC_8_ 3 -1 2 1 0 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_7_ 3 -1 4 1 2 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_6_ 3 -1 7 1 4 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_5_ 3 -1 1 1 7 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_4_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_3_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_2_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
345 CLK_000_N_SYNC_1_ 3 -1 6 1 5 -1 -1 1 0 21
|
|
344 CLK_000_N_SYNC_0_ 3 -1 5 1 6 -1 -1 1 0 21
|
|
343 CLK_000_P_SYNC_8_ 3 -1 4 1 6 -1 -1 1 0 21
|
|
342 CLK_000_P_SYNC_7_ 3 -1 3 1 4 -1 -1 1 0 21
|
|
341 CLK_000_P_SYNC_6_ 3 -1 3 1 3 -1 -1 1 0 21
|
|
340 CLK_000_P_SYNC_5_ 3 -1 0 1 3 -1 -1 1 0 21
|
|
339 CLK_000_P_SYNC_4_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
338 CLK_000_P_SYNC_3_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
337 CLK_000_P_SYNC_2_ 3 -1 0 1 3 -1 -1 1 0 21
|
|
336 CLK_000_P_SYNC_1_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
335 CLK_000_P_SYNC_0_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
326 IPL_D0_2_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
325 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
324 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
323 CLK_000_N_SYNC_11_ 3 -1 7 1 3 -1 -1 1 0 21
|
|
321 CLK_000_P_SYNC_9_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
317 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
315 inst_DTACK_D0 3 -1 6 1 2 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 4 5 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 4 5 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 4 5 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 4 5 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 4 5 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 4 5 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
67 IPL_2_ 1 -1 -1 2 1 5 67 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
|
59 A1 1 -1 -1 1 5 59 -1
|
|
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
|
35 VPA 1 -1 -1 1 6 35 -1
|
|
29 DTACK 1 -1 -1 1 6 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 5 13 -1
|
|
10 CLK_000 1 -1 -1 1 0 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
140 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21
|
|
79 RW_000 5 365 7 3 0 4 6 79 -1 3 0 21
|
|
40 BERR 5 -1 4 3 2 5 7 40 -1 1 0 21
|
|
70 RW 5 371 6 2 2 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
68 A0 5 366 6 1 0 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 362 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 364 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 363 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 369 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 368 7 0 82 -1 3 0 21
|
|
34 VMA 5 370 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 367 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
368 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
302 inst_nEXP_SPACE_D0reg 3 -1 0 7 0 2 3 4 5 6 7 -1 -1 1 0 21
|
|
316 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
320 inst_CLK_000_PE 3 -1 6 5 1 2 3 5 7 -1 -1 1 0 21
|
|
360 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 14 0 21
|
|
301 inst_AS_030_D0 3 -1 7 4 2 3 4 7 -1 -1 1 0 21
|
|
294 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
|
355 SM_AMIGA_6_ 3 -1 5 3 0 2 5 -1 -1 3 0 21
|
|
299 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21
|
|
297 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
295 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
328 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 2 0 21
|
|
307 CYCLE_DMA_0_ 3 -1 1 3 0 1 2 -1 -1 2 0 21
|
|
319 inst_CLK_000_D0 3 -1 1 3 3 4 5 -1 -1 1 0 21
|
|
314 inst_CLK_OUT_PRE_D 3 -1 0 3 1 6 7 -1 -1 1 0 21
|
|
304 inst_BGACK_030_INT_D 3 -1 7 3 1 2 6 -1 -1 1 0 21
|
|
305 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
303 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21
|
|
331 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21
|
|
370 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
357 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
330 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21
|
|
313 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21
|
|
310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
308 CYCLE_DMA_1_ 3 -1 2 2 0 2 -1 -1 3 0 21
|
|
329 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
312 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21
|
|
300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
|
|
296 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21
|
|
327 inst_CLK_000_NE_D0 3 -1 3 2 3 5 -1 -1 1 0 21
|
|
322 inst_CLK_000_NE 3 -1 6 2 3 5 -1 -1 1 0 21
|
|
318 inst_CLK_000_D1 3 -1 4 2 4 5 -1 -1 1 0 21
|
|
317 inst_CLK_OUT_PRE_50 3 -1 5 2 0 5 -1 -1 1 0 21
|
|
311 inst_VPA_D 3 -1 5 2 3 5 -1 -1 1 0 21
|
|
364 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
363 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
362 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
306 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
356 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
358 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21
|
|
369 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
359 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
333 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21
|
|
293 N_317_i 3 -1 5 1 5 -1 -1 4 0 21
|
|
366 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
365 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
332 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21
|
|
371 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
367 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
334 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21
|
|
354 CLK_000_N_SYNC_10_ 3 -1 7 1 1 -1 -1 1 0 21
|
|
353 CLK_000_N_SYNC_9_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
352 CLK_000_N_SYNC_8_ 3 -1 0 1 7 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_7_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_6_ 3 -1 5 1 0 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_5_ 3 -1 6 1 5 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_4_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_3_ 3 -1 1 1 3 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
345 CLK_000_N_SYNC_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
344 CLK_000_N_SYNC_0_ 3 -1 4 1 1 -1 -1 1 0 21
|
|
343 CLK_000_P_SYNC_8_ 3 -1 0 1 6 -1 -1 1 0 21
|
|
342 CLK_000_P_SYNC_7_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
341 CLK_000_P_SYNC_6_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
340 CLK_000_P_SYNC_5_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
339 CLK_000_P_SYNC_4_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
338 CLK_000_P_SYNC_3_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
337 CLK_000_P_SYNC_2_ 3 -1 4 1 6 -1 -1 1 0 21
|
|
336 CLK_000_P_SYNC_1_ 3 -1 6 1 4 -1 -1 1 0 21
|
|
335 CLK_000_P_SYNC_0_ 3 -1 4 1 6 -1 -1 1 0 21
|
|
326 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
325 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
324 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
323 CLK_000_N_SYNC_11_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
321 CLK_000_P_SYNC_9_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
315 inst_DTACK_D0 3 -1 1 1 5 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 6 66 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 3 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
59 A1 1 -1 -1 1 1 59 -1
|
|
35 VPA 1 -1 -1 1 5 35 -1
|
|
29 DTACK 1 -1 -1 1 1 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 0 13 -1
|
|
10 CLK_000 1 -1 -1 1 1 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
140 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21
|
|
79 RW_000 5 365 7 3 0 4 6 79 -1 3 0 21
|
|
40 BERR 5 -1 4 3 2 5 7 40 -1 1 0 21
|
|
70 RW 5 371 6 2 2 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
68 A0 5 366 6 1 0 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 362 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 364 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 363 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 369 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 368 7 0 82 -1 3 0 21
|
|
34 VMA 5 370 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 367 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
368 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
302 inst_nEXP_SPACE_D0reg 3 -1 0 7 0 2 3 4 5 6 7 -1 -1 1 0 21
|
|
316 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
320 inst_CLK_000_PE 3 -1 6 5 1 2 3 5 7 -1 -1 1 0 21
|
|
360 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 14 0 21
|
|
301 inst_AS_030_D0 3 -1 7 4 2 3 4 7 -1 -1 1 0 21
|
|
294 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
|
355 SM_AMIGA_6_ 3 -1 5 3 0 2 5 -1 -1 3 0 21
|
|
299 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21
|
|
297 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
295 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
328 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 2 0 21
|
|
307 CYCLE_DMA_0_ 3 -1 1 3 0 1 2 -1 -1 2 0 21
|
|
319 inst_CLK_000_D0 3 -1 1 3 3 4 5 -1 -1 1 0 21
|
|
314 inst_CLK_OUT_PRE_D 3 -1 0 3 1 6 7 -1 -1 1 0 21
|
|
304 inst_BGACK_030_INT_D 3 -1 7 3 1 2 6 -1 -1 1 0 21
|
|
305 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
303 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21
|
|
331 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21
|
|
370 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
357 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
330 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21
|
|
313 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21
|
|
310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
308 CYCLE_DMA_1_ 3 -1 2 2 0 2 -1 -1 3 0 21
|
|
329 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
312 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21
|
|
300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
|
|
296 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21
|
|
327 inst_CLK_000_NE_D0 3 -1 3 2 3 5 -1 -1 1 0 21
|
|
322 inst_CLK_000_NE 3 -1 6 2 3 5 -1 -1 1 0 21
|
|
318 inst_CLK_000_D1 3 -1 4 2 4 5 -1 -1 1 0 21
|
|
317 inst_CLK_OUT_PRE_50 3 -1 5 2 0 5 -1 -1 1 0 21
|
|
311 inst_VPA_D 3 -1 5 2 3 5 -1 -1 1 0 21
|
|
364 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
363 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
362 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
306 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
356 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
358 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21
|
|
369 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
359 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
333 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21
|
|
293 N_317_i 3 -1 5 1 5 -1 -1 4 0 21
|
|
366 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
365 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
332 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21
|
|
371 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
367 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
334 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21
|
|
354 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
353 CLK_000_N_SYNC_9_ 3 -1 0 1 7 -1 -1 1 0 21
|
|
352 CLK_000_N_SYNC_8_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_7_ 3 -1 5 1 0 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_6_ 3 -1 6 1 5 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_5_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_4_ 3 -1 1 1 3 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_3_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
345 CLK_000_N_SYNC_1_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
344 CLK_000_N_SYNC_0_ 3 -1 4 1 0 -1 -1 1 0 21
|
|
343 CLK_000_P_SYNC_8_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
342 CLK_000_P_SYNC_7_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
341 CLK_000_P_SYNC_6_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
340 CLK_000_P_SYNC_5_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
339 CLK_000_P_SYNC_4_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
338 CLK_000_P_SYNC_3_ 3 -1 4 1 6 -1 -1 1 0 21
|
|
337 CLK_000_P_SYNC_2_ 3 -1 6 1 4 -1 -1 1 0 21
|
|
336 CLK_000_P_SYNC_1_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
335 CLK_000_P_SYNC_0_ 3 -1 4 1 1 -1 -1 1 0 21
|
|
326 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
325 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
324 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
323 CLK_000_N_SYNC_11_ 3 -1 7 1 6 -1 -1 1 0 21
|
|
321 CLK_000_P_SYNC_9_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
315 inst_DTACK_D0 3 -1 1 1 5 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 6 66 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 3 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
59 A1 1 -1 -1 1 1 59 -1
|
|
35 VPA 1 -1 -1 1 5 35 -1
|
|
29 DTACK 1 -1 -1 1 1 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 0 13 -1
|
|
10 CLK_000 1 -1 -1 1 1 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
140 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21
|
|
79 RW_000 5 365 7 3 0 4 6 79 -1 3 0 21
|
|
40 BERR 5 -1 4 3 2 5 7 40 -1 1 0 21
|
|
70 RW 5 371 6 2 2 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
68 A0 5 366 6 1 0 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 362 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 364 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 363 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 369 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 368 7 0 82 -1 3 0 21
|
|
34 VMA 5 370 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 367 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
368 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
302 inst_nEXP_SPACE_D0reg 3 -1 0 7 0 2 3 4 5 6 7 -1 -1 1 0 21
|
|
316 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
320 inst_CLK_000_PE 3 -1 6 5 1 2 3 5 7 -1 -1 1 0 21
|
|
360 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 14 0 21
|
|
301 inst_AS_030_D0 3 -1 7 4 2 3 4 7 -1 -1 1 0 21
|
|
294 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
|
355 SM_AMIGA_6_ 3 -1 5 3 0 2 5 -1 -1 3 0 21
|
|
299 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21
|
|
297 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
295 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
328 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 2 0 21
|
|
307 CYCLE_DMA_0_ 3 -1 1 3 0 1 2 -1 -1 2 0 21
|
|
319 inst_CLK_000_D0 3 -1 1 3 3 4 5 -1 -1 1 0 21
|
|
314 inst_CLK_OUT_PRE_D 3 -1 0 3 1 6 7 -1 -1 1 0 21
|
|
304 inst_BGACK_030_INT_D 3 -1 7 3 1 2 6 -1 -1 1 0 21
|
|
305 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
303 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21
|
|
331 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21
|
|
370 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
357 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
330 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21
|
|
313 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21
|
|
310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
308 CYCLE_DMA_1_ 3 -1 2 2 0 2 -1 -1 3 0 21
|
|
329 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
312 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21
|
|
300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
|
|
296 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21
|
|
327 inst_CLK_000_NE_D0 3 -1 3 2 3 5 -1 -1 1 0 21
|
|
322 inst_CLK_000_NE 3 -1 6 2 3 5 -1 -1 1 0 21
|
|
318 inst_CLK_000_D1 3 -1 4 2 4 5 -1 -1 1 0 21
|
|
317 inst_CLK_OUT_PRE_50 3 -1 5 2 0 5 -1 -1 1 0 21
|
|
311 inst_VPA_D 3 -1 5 2 3 5 -1 -1 1 0 21
|
|
364 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
363 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
362 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
306 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
356 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
358 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21
|
|
369 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
359 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
333 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21
|
|
293 N_317_i 3 -1 5 1 5 -1 -1 4 0 21
|
|
366 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
365 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
332 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21
|
|
371 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
367 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
334 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21
|
|
354 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
353 CLK_000_N_SYNC_9_ 3 -1 0 1 7 -1 -1 1 0 21
|
|
352 CLK_000_N_SYNC_8_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_7_ 3 -1 5 1 0 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_6_ 3 -1 6 1 5 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_5_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_4_ 3 -1 1 1 3 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_3_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
345 CLK_000_N_SYNC_1_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
344 CLK_000_N_SYNC_0_ 3 -1 4 1 0 -1 -1 1 0 21
|
|
343 CLK_000_P_SYNC_8_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
342 CLK_000_P_SYNC_7_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
341 CLK_000_P_SYNC_6_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
340 CLK_000_P_SYNC_5_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
339 CLK_000_P_SYNC_4_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
338 CLK_000_P_SYNC_3_ 3 -1 4 1 6 -1 -1 1 0 21
|
|
337 CLK_000_P_SYNC_2_ 3 -1 6 1 4 -1 -1 1 0 21
|
|
336 CLK_000_P_SYNC_1_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
335 CLK_000_P_SYNC_0_ 3 -1 4 1 1 -1 -1 1 0 21
|
|
326 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
325 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
324 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
323 CLK_000_N_SYNC_11_ 3 -1 7 1 6 -1 -1 1 0 21
|
|
321 CLK_000_P_SYNC_9_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
315 inst_DTACK_D0 3 -1 1 1 5 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 6 66 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 3 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
59 A1 1 -1 -1 1 1 59 -1
|
|
35 VPA 1 -1 -1 1 5 35 -1
|
|
29 DTACK 1 -1 -1 1 1 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 0 13 -1
|
|
10 CLK_000 1 -1 -1 1 1 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
141 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21
|
|
79 RW_000 5 366 7 3 0 4 6 79 -1 3 0 21
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
70 RW 5 372 6 2 5 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
68 A0 5 367 6 1 1 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 363 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 365 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 364 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 370 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 369 7 0 82 -1 3 0 21
|
|
34 VMA 5 371 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 368 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
369 RN_BGACK_030 3 82 7 7 0 2 3 4 5 6 7 82 -1 3 0 21
|
|
315 inst_RESET_OUT 3 -1 5 7 0 1 3 4 5 6 7 -1 -1 2 0 21
|
|
301 inst_nEXP_SPACE_D0reg 3 -1 5 7 0 2 3 4 5 6 7 -1 -1 1 0 21
|
|
320 inst_CLK_000_PE 3 -1 1 5 0 2 3 5 7 -1 -1 1 0 21
|
|
300 inst_AS_030_D0 3 -1 7 5 0 3 4 5 7 -1 -1 1 0 21
|
|
361 SM_AMIGA_i_7_ 3 -1 2 4 2 3 5 7 -1 -1 14 0 21
|
|
298 SM_AMIGA_5_ 3 -1 2 4 0 2 5 7 -1 -1 3 0 21
|
|
322 inst_CLK_000_NE 3 -1 4 4 0 2 3 5 -1 -1 1 0 21
|
|
294 cpu_est_2_ 3 -1 6 3 2 3 6 -1 -1 4 0 21
|
|
355 SM_AMIGA_6_ 3 -1 2 3 1 2 5 -1 -1 3 0 21
|
|
330 SM_AMIGA_4_ 3 -1 0 3 0 2 5 -1 -1 3 0 21
|
|
295 cpu_est_3_ 3 -1 2 3 2 3 6 -1 -1 3 0 21
|
|
293 cpu_est_1_ 3 -1 2 3 2 3 6 -1 -1 3 0 21
|
|
328 SM_AMIGA_0_ 3 -1 2 3 2 5 7 -1 -1 2 0 21
|
|
296 cpu_est_0_ 3 -1 2 3 2 3 6 -1 -1 2 0 21
|
|
319 inst_CLK_000_D0 3 -1 0 3 2 3 4 -1 -1 1 0 21
|
|
313 inst_CLK_OUT_PRE_D 3 -1 3 3 1 6 7 -1 -1 1 0 21
|
|
304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
302 inst_AS_030_000_SYNC 3 -1 5 2 2 5 -1 -1 7 0 21
|
|
331 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 5 0 21
|
|
371 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21
|
|
357 SM_AMIGA_1_ 3 -1 2 2 2 7 -1 -1 3 0 21
|
|
312 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21
|
|
309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
329 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
317 inst_CLK_OUT_PRE_25 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
311 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21
|
|
297 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21
|
|
327 inst_CLK_000_NE_D0 3 -1 5 2 2 6 -1 -1 1 0 21
|
|
318 inst_CLK_000_D1 3 -1 4 2 2 4 -1 -1 1 0 21
|
|
316 inst_CLK_OUT_PRE_50 3 -1 5 2 5 6 -1 -1 1 0 21
|
|
310 inst_VPA_D 3 -1 3 2 2 3 -1 -1 1 0 21
|
|
303 inst_BGACK_030_INT_D 3 -1 7 2 5 6 -1 -1 1 0 21
|
|
365 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
364 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
363 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
356 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
358 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21
|
|
370 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
359 SM_AMIGA_2_ 3 -1 2 1 2 -1 -1 4 0 21
|
|
333 RST_DLY_1_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
367 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
366 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
332 RST_DLY_0_ 3 -1 5 1 5 -1 -1 3 0 21
|
|
307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
372 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
368 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
362 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
360 N_199_i 3 -1 2 1 2 -1 -1 2 0 21
|
|
334 RST_DLY_2_ 3 -1 5 1 5 -1 -1 2 0 21
|
|
306 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
354 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
353 CLK_000_N_SYNC_9_ 3 -1 0 1 7 -1 -1 1 0 21
|
|
352 CLK_000_N_SYNC_8_ 3 -1 3 1 0 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_7_ 3 -1 3 1 3 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_6_ 3 -1 5 1 3 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_5_ 3 -1 2 1 5 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_4_ 3 -1 1 1 2 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_3_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
345 CLK_000_N_SYNC_1_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
344 CLK_000_N_SYNC_0_ 3 -1 4 1 0 -1 -1 1 0 21
|
|
343 CLK_000_P_SYNC_8_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
342 CLK_000_P_SYNC_7_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
341 CLK_000_P_SYNC_6_ 3 -1 6 1 3 -1 -1 1 0 21
|
|
340 CLK_000_P_SYNC_5_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
339 CLK_000_P_SYNC_4_ 3 -1 1 1 3 -1 -1 1 0 21
|
|
338 CLK_000_P_SYNC_3_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
337 CLK_000_P_SYNC_2_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
336 CLK_000_P_SYNC_1_ 3 -1 0 1 3 -1 -1 1 0 21
|
|
335 CLK_000_P_SYNC_0_ 3 -1 4 1 0 -1 -1 1 0 21
|
|
326 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
325 IPL_D0_1_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
324 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
323 CLK_000_N_SYNC_11_ 3 -1 7 1 4 -1 -1 1 0 21
|
|
321 CLK_000_P_SYNC_9_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
314 inst_DTACK_D0 3 -1 6 1 2 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 4 5 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 4 5 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 4 5 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 4 5 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 4 5 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 4 5 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
67 IPL_2_ 1 -1 -1 2 1 3 67 -1
|
|
66 IPL_0_ 1 -1 -1 2 0 1 66 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 2 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
59 A1 1 -1 -1 1 6 59 -1
|
|
35 VPA 1 -1 -1 1 3 35 -1
|
|
29 DTACK 1 -1 -1 1 6 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 5 13 -1
|
|
10 CLK_000 1 -1 -1 1 0 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
141 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
41 AS_000 5 -1 4 4 0 4 6 7 41 -1 1 0 21
|
|
40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21
|
|
79 RW_000 5 366 7 2 4 6 79 -1 3 0 21
|
|
70 RW 5 372 6 2 2 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
68 A0 5 367 6 1 0 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21
|
|
31 UDS_000 5 -1 3 1 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 1 6 30 -1 1 0 21
|
|
8 IPL_030_2_ 5 363 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 365 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 364 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 370 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 369 7 0 82 -1 3 0 21
|
|
34 VMA 5 371 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 368 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
369 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
302 inst_nEXP_SPACE_D0reg 3 -1 3 7 0 2 3 4 5 6 7 -1 -1 1 0 21
|
|
316 inst_RESET_OUT 3 -1 1 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
321 inst_CLK_000_PE 3 -1 6 5 2 3 5 6 7 -1 -1 1 0 21
|
|
301 inst_AS_030_D0 3 -1 7 5 0 2 3 4 7 -1 -1 1 0 21
|
|
299 SM_AMIGA_5_ 3 -1 5 4 0 2 5 7 -1 -1 3 0 21
|
|
320 inst_CLK_000_D0 3 -1 0 4 0 2 3 5 -1 -1 1 0 21
|
|
361 SM_AMIGA_i_7_ 3 -1 5 3 2 3 7 -1 -1 14 0 21
|
|
295 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
|
356 SM_AMIGA_6_ 3 -1 2 3 0 2 5 -1 -1 3 0 21
|
|
296 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
294 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
329 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 2 0 21
|
|
323 inst_CLK_000_NE 3 -1 4 3 1 3 5 -1 -1 1 0 21
|
|
319 inst_CLK_000_D1 3 -1 3 3 0 2 5 -1 -1 1 0 21
|
|
317 inst_CLK_OUT_PRE_50 3 -1 4 3 0 1 4 -1 -1 1 0 21
|
|
304 inst_BGACK_030_INT_D 3 -1 7 3 1 2 6 -1 -1 1 0 21
|
|
306 inst_DS_000_DMA 3 -1 6 2 0 6 -1 -1 9 0 21
|
|
305 inst_AS_000_DMA 3 -1 6 2 6 7 -1 -1 7 0 21
|
|
303 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21
|
|
332 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21
|
|
371 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
358 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
331 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21
|
|
313 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21
|
|
310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
330 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
318 inst_CLK_OUT_PRE_25 3 -1 0 2 0 3 -1 -1 2 0 21
|
|
312 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21
|
|
300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21
|
|
297 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21
|
|
328 inst_CLK_000_NE_D0 3 -1 3 2 3 5 -1 -1 1 0 21
|
|
314 inst_CLK_OUT_PRE_D 3 -1 3 2 6 7 -1 -1 1 0 21
|
|
311 inst_VPA_D 3 -1 1 2 3 5 -1 -1 1 0 21
|
|
365 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
364 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
363 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
357 inst_CLK_030_H 3 -1 6 1 6 -1 -1 8 0 21
|
|
359 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21
|
|
370 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
360 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
334 RST_DLY_1_ 3 -1 1 1 1 -1 -1 4 0 21
|
|
293 N_201_i 3 -1 5 1 5 -1 -1 4 0 21
|
|
367 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
366 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
333 RST_DLY_0_ 3 -1 1 1 1 -1 -1 3 0 21
|
|
308 CYCLE_DMA_1_ 3 -1 6 1 6 -1 -1 3 0 21
|
|
372 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
368 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
362 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
335 RST_DLY_2_ 3 -1 1 1 1 -1 -1 2 0 21
|
|
307 CYCLE_DMA_0_ 3 -1 6 1 6 -1 -1 2 0 21
|
|
355 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
354 CLK_000_N_SYNC_9_ 3 -1 0 1 7 -1 -1 1 0 21
|
|
353 CLK_000_N_SYNC_8_ 3 -1 3 1 0 -1 -1 1 0 21
|
|
352 CLK_000_N_SYNC_7_ 3 -1 1 1 3 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_6_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_5_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_4_ 3 -1 0 1 3 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_3_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_2_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_1_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
345 CLK_000_N_SYNC_0_ 3 -1 5 1 6 -1 -1 1 0 21
|
|
344 CLK_000_P_SYNC_8_ 3 -1 1 1 0 -1 -1 1 0 21
|
|
343 CLK_000_P_SYNC_7_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
342 CLK_000_P_SYNC_6_ 3 -1 4 1 5 -1 -1 1 0 21
|
|
341 CLK_000_P_SYNC_5_ 3 -1 0 1 4 -1 -1 1 0 21
|
|
340 CLK_000_P_SYNC_4_ 3 -1 3 1 0 -1 -1 1 0 21
|
|
339 CLK_000_P_SYNC_3_ 3 -1 2 1 3 -1 -1 1 0 21
|
|
338 CLK_000_P_SYNC_2_ 3 -1 5 1 2 -1 -1 1 0 21
|
|
337 CLK_000_P_SYNC_1_ 3 -1 4 1 5 -1 -1 1 0 21
|
|
336 CLK_000_P_SYNC_0_ 3 -1 0 1 4 -1 -1 1 0 21
|
|
327 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
326 IPL_D0_1_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
325 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
324 CLK_000_N_SYNC_11_ 3 -1 7 1 4 -1 -1 1 0 21
|
|
322 CLK_000_P_SYNC_9_ 3 -1 0 1 6 -1 -1 1 0 21
|
|
315 inst_DTACK_D0 3 -1 1 1 5 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
67 IPL_2_ 1 -1 -1 2 0 1 67 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 2 66 -1
|
|
63 CLK_030 1 -1 -1 2 6 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 5 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
59 A1 1 -1 -1 1 1 59 -1
|
|
35 VPA 1 -1 -1 1 1 35 -1
|
|
29 DTACK 1 -1 -1 1 1 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 3 13 -1
|
|
10 CLK_000 1 -1 -1 1 0 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
142 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 5 0 1 2 5 7 40 -1 1 0 21
|
|
79 RW_000 5 367 7 3 0 4 6 79 -1 3 0 21
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
70 RW 5 373 6 2 2 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
68 A0 5 368 6 1 0 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 364 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 366 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 365 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 371 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 370 7 0 82 -1 3 0 21
|
|
34 VMA 5 372 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 369 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
370 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
315 inst_RESET_OUT 3 -1 6 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
301 inst_nEXP_SPACE_D0reg 3 -1 7 6 0 2 3 4 6 7 -1 -1 1 0 21
|
|
321 inst_CLK_000_PE 3 -1 5 5 0 2 3 5 7 -1 -1 1 0 21
|
|
300 inst_AS_030_D0 3 -1 7 5 1 2 3 4 7 -1 -1 1 0 21
|
|
359 SM_AMIGA_1_ 3 -1 0 4 0 2 5 7 -1 -1 3 0 21
|
|
298 SM_AMIGA_5_ 3 -1 5 4 1 2 5 7 -1 -1 3 0 21
|
|
324 inst_CLK_000_NE 3 -1 6 4 0 3 5 6 -1 -1 1 0 21
|
|
320 inst_CLK_000_D0 3 -1 3 4 1 2 3 6 -1 -1 1 0 21
|
|
362 SM_AMIGA_i_7_ 3 -1 5 3 2 3 7 -1 -1 14 0 21
|
|
361 SM_AMIGA_2_ 3 -1 5 3 0 2 5 -1 -1 4 0 21
|
|
295 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
|
357 SM_AMIGA_6_ 3 -1 2 3 0 2 5 -1 -1 3 0 21
|
|
296 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
294 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
330 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 2 0 21
|
|
319 inst_CLK_000_D1 3 -1 2 3 1 2 6 -1 -1 1 0 21
|
|
303 inst_BGACK_030_INT_D 3 -1 4 3 1 2 6 -1 -1 1 0 21
|
|
304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
360 SM_AMIGA_3_ 3 -1 5 2 2 5 -1 -1 5 0 21
|
|
333 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21
|
|
372 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
332 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21
|
|
312 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21
|
|
309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
331 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
318 inst_CLK_OUT_PRE_25 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
311 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21
|
|
297 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21
|
|
293 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21
|
|
329 inst_CLK_000_NE_D0 3 -1 3 2 3 5 -1 -1 1 0 21
|
|
316 inst_CLK_OUT_PRE_50 3 -1 4 2 4 6 -1 -1 1 0 21
|
|
313 inst_CLK_OUT_PRE_D 3 -1 3 2 6 7 -1 -1 1 0 21
|
|
310 inst_VPA_D 3 -1 2 2 3 5 -1 -1 1 0 21
|
|
366 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
365 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
364 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
358 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
302 inst_AS_030_000_SYNC 3 -1 2 1 2 -1 -1 7 0 21
|
|
371 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
335 RST_DLY_1_ 3 -1 6 1 6 -1 -1 4 0 21
|
|
317 N_210_i 3 -1 2 1 5 -1 -1 4 0 21
|
|
368 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
367 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
334 RST_DLY_0_ 3 -1 6 1 6 -1 -1 3 0 21
|
|
307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
373 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
369 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
363 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
336 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21
|
|
306 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
356 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
355 CLK_000_N_SYNC_9_ 3 -1 3 1 7 -1 -1 1 0 21
|
|
354 CLK_000_N_SYNC_8_ 3 -1 1 1 3 -1 -1 1 0 21
|
|
353 CLK_000_N_SYNC_7_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
352 CLK_000_N_SYNC_6_ 3 -1 0 1 6 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_5_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_4_ 3 -1 3 1 0 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_3_ 3 -1 3 1 3 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_2_ 3 -1 5 1 3 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_1_ 3 -1 5 1 5 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_0_ 3 -1 6 1 5 -1 -1 1 0 21
|
|
345 CLK_000_P_SYNC_8_ 3 -1 6 1 5 -1 -1 1 0 21
|
|
344 CLK_000_P_SYNC_7_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
343 CLK_000_P_SYNC_6_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
342 CLK_000_P_SYNC_5_ 3 -1 1 1 5 -1 -1 1 0 21
|
|
341 CLK_000_P_SYNC_4_ 3 -1 4 1 1 -1 -1 1 0 21
|
|
340 CLK_000_P_SYNC_3_ 3 -1 5 1 4 -1 -1 1 0 21
|
|
339 CLK_000_P_SYNC_2_ 3 -1 5 1 5 -1 -1 1 0 21
|
|
338 CLK_000_P_SYNC_1_ 3 -1 1 1 5 -1 -1 1 0 21
|
|
337 CLK_000_P_SYNC_0_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
328 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
327 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
326 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
325 CLK_000_N_SYNC_11_ 3 -1 7 1 6 -1 -1 1 0 21
|
|
323 CLK_000_P_SYNC_9_ 3 -1 5 1 5 -1 -1 1 0 21
|
|
322 inst_CLK_OUT_EXP_INT 3 -1 4 1 1 -1 -1 1 0 21
|
|
314 inst_DTACK_D0 3 -1 0 1 5 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
|
59 A1 1 -1 -1 1 1 59 -1
|
|
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
|
35 VPA 1 -1 -1 1 2 35 -1
|
|
29 DTACK 1 -1 -1 1 0 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 7 13 -1
|
|
10 CLK_000 1 -1 -1 1 3 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
140 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21
|
|
79 RW_000 5 365 7 3 0 4 6 79 -1 3 0 21
|
|
40 BERR 5 -1 4 3 2 5 7 40 -1 1 0 21
|
|
70 RW 5 371 6 2 2 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
68 A0 5 366 6 1 0 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 362 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 364 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 363 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 369 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 368 7 0 82 -1 3 0 21
|
|
34 VMA 5 370 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 367 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
368 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
302 inst_nEXP_SPACE_D0reg 3 -1 0 7 0 2 3 4 5 6 7 -1 -1 1 0 21
|
|
316 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
320 inst_CLK_000_PE 3 -1 6 5 1 2 3 5 7 -1 -1 1 0 21
|
|
360 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 14 0 21
|
|
301 inst_AS_030_D0 3 -1 7 4 2 3 4 7 -1 -1 1 0 21
|
|
294 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
|
355 SM_AMIGA_6_ 3 -1 5 3 0 2 5 -1 -1 3 0 21
|
|
299 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21
|
|
297 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
295 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
328 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 2 0 21
|
|
307 CYCLE_DMA_0_ 3 -1 1 3 0 1 2 -1 -1 2 0 21
|
|
319 inst_CLK_000_D0 3 -1 1 3 3 4 5 -1 -1 1 0 21
|
|
314 inst_CLK_OUT_PRE_D 3 -1 0 3 1 6 7 -1 -1 1 0 21
|
|
304 inst_BGACK_030_INT_D 3 -1 7 3 1 2 6 -1 -1 1 0 21
|
|
305 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
303 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21
|
|
331 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21
|
|
370 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
357 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
330 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21
|
|
313 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21
|
|
310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
308 CYCLE_DMA_1_ 3 -1 2 2 0 2 -1 -1 3 0 21
|
|
329 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
312 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21
|
|
300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
|
|
296 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21
|
|
327 inst_CLK_000_NE_D0 3 -1 3 2 3 5 -1 -1 1 0 21
|
|
322 inst_CLK_000_NE 3 -1 6 2 3 5 -1 -1 1 0 21
|
|
318 inst_CLK_000_D1 3 -1 4 2 4 5 -1 -1 1 0 21
|
|
317 inst_CLK_OUT_PRE_50 3 -1 5 2 0 5 -1 -1 1 0 21
|
|
311 inst_VPA_D 3 -1 5 2 3 5 -1 -1 1 0 21
|
|
364 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
363 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
362 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
306 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
356 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
358 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21
|
|
369 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
359 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
333 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21
|
|
293 N_317_i 3 -1 5 1 5 -1 -1 4 0 21
|
|
366 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
365 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
332 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21
|
|
371 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
367 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
334 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21
|
|
354 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
353 CLK_000_N_SYNC_9_ 3 -1 0 1 7 -1 -1 1 0 21
|
|
352 CLK_000_N_SYNC_8_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_7_ 3 -1 5 1 0 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_6_ 3 -1 6 1 5 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_5_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_4_ 3 -1 1 1 3 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_3_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
345 CLK_000_N_SYNC_1_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
344 CLK_000_N_SYNC_0_ 3 -1 4 1 0 -1 -1 1 0 21
|
|
343 CLK_000_P_SYNC_8_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
342 CLK_000_P_SYNC_7_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
341 CLK_000_P_SYNC_6_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
340 CLK_000_P_SYNC_5_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
339 CLK_000_P_SYNC_4_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
338 CLK_000_P_SYNC_3_ 3 -1 4 1 6 -1 -1 1 0 21
|
|
337 CLK_000_P_SYNC_2_ 3 -1 6 1 4 -1 -1 1 0 21
|
|
336 CLK_000_P_SYNC_1_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
335 CLK_000_P_SYNC_0_ 3 -1 4 1 1 -1 -1 1 0 21
|
|
326 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
325 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
324 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
323 CLK_000_N_SYNC_11_ 3 -1 7 1 6 -1 -1 1 0 21
|
|
321 CLK_000_P_SYNC_9_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
315 inst_DTACK_D0 3 -1 1 1 5 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 6 66 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 3 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
59 A1 1 -1 -1 1 1 59 -1
|
|
35 VPA 1 -1 -1 1 5 35 -1
|
|
29 DTACK 1 -1 -1 1 1 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 0 13 -1
|
|
10 CLK_000 1 -1 -1 1 1 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
140 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21
|
|
79 RW_000 5 365 7 3 0 4 6 79 -1 3 0 21
|
|
40 BERR 5 -1 4 3 2 5 7 40 -1 1 0 21
|
|
70 RW 5 371 6 2 2 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
68 A0 5 366 6 1 0 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 362 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 364 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 363 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 369 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 368 7 0 82 -1 3 0 21
|
|
34 VMA 5 370 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 367 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
368 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
302 inst_nEXP_SPACE_D0reg 3 -1 0 7 0 2 3 4 5 6 7 -1 -1 1 0 21
|
|
316 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
320 inst_CLK_000_PE 3 -1 6 5 1 2 3 5 7 -1 -1 1 0 21
|
|
360 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 14 0 21
|
|
301 inst_AS_030_D0 3 -1 7 4 2 3 4 7 -1 -1 1 0 21
|
|
294 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
|
355 SM_AMIGA_6_ 3 -1 5 3 0 2 5 -1 -1 3 0 21
|
|
299 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21
|
|
297 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
295 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
328 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 2 0 21
|
|
307 CYCLE_DMA_0_ 3 -1 1 3 0 1 2 -1 -1 2 0 21
|
|
319 inst_CLK_000_D0 3 -1 1 3 3 4 5 -1 -1 1 0 21
|
|
314 inst_CLK_OUT_PRE_D 3 -1 0 3 1 6 7 -1 -1 1 0 21
|
|
304 inst_BGACK_030_INT_D 3 -1 7 3 1 2 6 -1 -1 1 0 21
|
|
305 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
303 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21
|
|
331 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21
|
|
370 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
357 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
330 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21
|
|
313 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21
|
|
310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
308 CYCLE_DMA_1_ 3 -1 2 2 0 2 -1 -1 3 0 21
|
|
329 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
312 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21
|
|
300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
|
|
296 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21
|
|
327 inst_CLK_000_NE_D0 3 -1 3 2 3 5 -1 -1 1 0 21
|
|
322 inst_CLK_000_NE 3 -1 6 2 3 5 -1 -1 1 0 21
|
|
318 inst_CLK_000_D1 3 -1 4 2 4 5 -1 -1 1 0 21
|
|
317 inst_CLK_OUT_PRE_50 3 -1 5 2 0 5 -1 -1 1 0 21
|
|
311 inst_VPA_D 3 -1 5 2 3 5 -1 -1 1 0 21
|
|
364 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
363 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
362 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
306 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
356 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
358 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21
|
|
369 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
359 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
333 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21
|
|
293 N_317_i 3 -1 5 1 5 -1 -1 4 0 21
|
|
366 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
365 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
332 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21
|
|
371 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
367 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
334 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21
|
|
354 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
353 CLK_000_N_SYNC_9_ 3 -1 0 1 7 -1 -1 1 0 21
|
|
352 CLK_000_N_SYNC_8_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_7_ 3 -1 5 1 0 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_6_ 3 -1 6 1 5 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_5_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_4_ 3 -1 1 1 3 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_3_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
345 CLK_000_N_SYNC_1_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
344 CLK_000_N_SYNC_0_ 3 -1 4 1 0 -1 -1 1 0 21
|
|
343 CLK_000_P_SYNC_8_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
342 CLK_000_P_SYNC_7_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
341 CLK_000_P_SYNC_6_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
340 CLK_000_P_SYNC_5_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
339 CLK_000_P_SYNC_4_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
338 CLK_000_P_SYNC_3_ 3 -1 4 1 6 -1 -1 1 0 21
|
|
337 CLK_000_P_SYNC_2_ 3 -1 6 1 4 -1 -1 1 0 21
|
|
336 CLK_000_P_SYNC_1_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
335 CLK_000_P_SYNC_0_ 3 -1 4 1 1 -1 -1 1 0 21
|
|
326 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
325 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
324 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
323 CLK_000_N_SYNC_11_ 3 -1 7 1 6 -1 -1 1 0 21
|
|
321 CLK_000_P_SYNC_9_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
315 inst_DTACK_D0 3 -1 1 1 5 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 6 66 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 3 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
59 A1 1 -1 -1 1 1 59 -1
|
|
35 VPA 1 -1 -1 1 5 35 -1
|
|
29 DTACK 1 -1 -1 1 1 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 0 13 -1
|
|
10 CLK_000 1 -1 -1 1 1 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
141 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21
|
|
79 RW_000 5 366 7 3 0 4 6 79 -1 3 0 21
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
70 RW 5 372 6 2 5 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
68 A0 5 367 6 1 1 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 363 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 365 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 364 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 370 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 369 7 0 82 -1 3 0 21
|
|
34 VMA 5 371 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 368 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
369 RN_BGACK_030 3 82 7 7 0 2 3 4 5 6 7 82 -1 3 0 21
|
|
315 inst_RESET_OUT 3 -1 5 7 0 1 3 4 5 6 7 -1 -1 2 0 21
|
|
301 inst_nEXP_SPACE_D0reg 3 -1 5 7 0 2 3 4 5 6 7 -1 -1 1 0 21
|
|
320 inst_CLK_000_PE 3 -1 1 5 0 2 3 5 7 -1 -1 1 0 21
|
|
300 inst_AS_030_D0 3 -1 7 5 0 3 4 5 7 -1 -1 1 0 21
|
|
361 SM_AMIGA_i_7_ 3 -1 2 4 2 3 5 7 -1 -1 14 0 21
|
|
298 SM_AMIGA_5_ 3 -1 2 4 0 2 5 7 -1 -1 3 0 21
|
|
322 inst_CLK_000_NE 3 -1 4 4 0 2 3 5 -1 -1 1 0 21
|
|
294 cpu_est_2_ 3 -1 6 3 2 3 6 -1 -1 4 0 21
|
|
355 SM_AMIGA_6_ 3 -1 2 3 1 2 5 -1 -1 3 0 21
|
|
330 SM_AMIGA_4_ 3 -1 0 3 0 2 5 -1 -1 3 0 21
|
|
295 cpu_est_3_ 3 -1 2 3 2 3 6 -1 -1 3 0 21
|
|
293 cpu_est_1_ 3 -1 2 3 2 3 6 -1 -1 3 0 21
|
|
328 SM_AMIGA_0_ 3 -1 2 3 2 5 7 -1 -1 2 0 21
|
|
296 cpu_est_0_ 3 -1 2 3 2 3 6 -1 -1 2 0 21
|
|
319 inst_CLK_000_D0 3 -1 0 3 2 3 4 -1 -1 1 0 21
|
|
313 inst_CLK_OUT_PRE_D 3 -1 3 3 1 6 7 -1 -1 1 0 21
|
|
304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
302 inst_AS_030_000_SYNC 3 -1 5 2 2 5 -1 -1 7 0 21
|
|
331 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 5 0 21
|
|
371 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21
|
|
357 SM_AMIGA_1_ 3 -1 2 2 2 7 -1 -1 3 0 21
|
|
312 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21
|
|
309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
329 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
317 inst_CLK_OUT_PRE_25 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
311 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21
|
|
297 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21
|
|
327 inst_CLK_000_NE_D0 3 -1 5 2 2 6 -1 -1 1 0 21
|
|
318 inst_CLK_000_D1 3 -1 4 2 2 4 -1 -1 1 0 21
|
|
316 inst_CLK_OUT_PRE_50 3 -1 5 2 5 6 -1 -1 1 0 21
|
|
310 inst_VPA_D 3 -1 3 2 2 3 -1 -1 1 0 21
|
|
303 inst_BGACK_030_INT_D 3 -1 7 2 5 6 -1 -1 1 0 21
|
|
365 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
364 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
363 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
356 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
358 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21
|
|
370 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
359 SM_AMIGA_2_ 3 -1 2 1 2 -1 -1 4 0 21
|
|
333 RST_DLY_1_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
367 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
366 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
332 RST_DLY_0_ 3 -1 5 1 5 -1 -1 3 0 21
|
|
307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
372 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
368 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
362 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
360 N_199_i 3 -1 2 1 2 -1 -1 2 0 21
|
|
334 RST_DLY_2_ 3 -1 5 1 5 -1 -1 2 0 21
|
|
306 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
354 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
353 CLK_000_N_SYNC_9_ 3 -1 0 1 7 -1 -1 1 0 21
|
|
352 CLK_000_N_SYNC_8_ 3 -1 3 1 0 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_7_ 3 -1 3 1 3 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_6_ 3 -1 5 1 3 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_5_ 3 -1 2 1 5 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_4_ 3 -1 1 1 2 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_3_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
345 CLK_000_N_SYNC_1_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
344 CLK_000_N_SYNC_0_ 3 -1 4 1 0 -1 -1 1 0 21
|
|
343 CLK_000_P_SYNC_8_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
342 CLK_000_P_SYNC_7_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
341 CLK_000_P_SYNC_6_ 3 -1 6 1 3 -1 -1 1 0 21
|
|
340 CLK_000_P_SYNC_5_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
339 CLK_000_P_SYNC_4_ 3 -1 1 1 3 -1 -1 1 0 21
|
|
338 CLK_000_P_SYNC_3_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
337 CLK_000_P_SYNC_2_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
336 CLK_000_P_SYNC_1_ 3 -1 0 1 3 -1 -1 1 0 21
|
|
335 CLK_000_P_SYNC_0_ 3 -1 4 1 0 -1 -1 1 0 21
|
|
326 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
325 IPL_D0_1_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
324 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
323 CLK_000_N_SYNC_11_ 3 -1 7 1 4 -1 -1 1 0 21
|
|
321 CLK_000_P_SYNC_9_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
314 inst_DTACK_D0 3 -1 6 1 2 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 4 5 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 4 5 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 4 5 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 4 5 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 4 5 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 4 5 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
67 IPL_2_ 1 -1 -1 2 1 3 67 -1
|
|
66 IPL_0_ 1 -1 -1 2 0 1 66 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 2 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
59 A1 1 -1 -1 1 6 59 -1
|
|
35 VPA 1 -1 -1 1 3 35 -1
|
|
29 DTACK 1 -1 -1 1 6 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 5 13 -1
|
|
10 CLK_000 1 -1 -1 1 0 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
140 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21
|
|
79 RW_000 5 365 7 3 0 4 6 79 -1 3 0 21
|
|
40 BERR 5 -1 4 3 2 5 7 40 -1 1 0 21
|
|
70 RW 5 371 6 2 2 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
68 A0 5 366 6 1 0 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 362 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 364 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 363 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 369 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 368 7 0 82 -1 3 0 21
|
|
34 VMA 5 370 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 367 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
368 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
302 inst_nEXP_SPACE_D0reg 3 -1 0 7 0 2 3 4 5 6 7 -1 -1 1 0 21
|
|
316 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
320 inst_CLK_000_PE 3 -1 6 5 1 2 3 5 7 -1 -1 1 0 21
|
|
360 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 14 0 21
|
|
301 inst_AS_030_D0 3 -1 7 4 2 3 4 7 -1 -1 1 0 21
|
|
294 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
|
355 SM_AMIGA_6_ 3 -1 5 3 0 2 5 -1 -1 3 0 21
|
|
299 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21
|
|
297 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
295 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
328 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 2 0 21
|
|
307 CYCLE_DMA_0_ 3 -1 1 3 0 1 2 -1 -1 2 0 21
|
|
319 inst_CLK_000_D0 3 -1 1 3 3 4 5 -1 -1 1 0 21
|
|
314 inst_CLK_OUT_PRE_D 3 -1 0 3 1 6 7 -1 -1 1 0 21
|
|
304 inst_BGACK_030_INT_D 3 -1 7 3 1 2 6 -1 -1 1 0 21
|
|
305 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
303 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21
|
|
331 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21
|
|
370 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
357 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
330 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21
|
|
313 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21
|
|
310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
308 CYCLE_DMA_1_ 3 -1 2 2 0 2 -1 -1 3 0 21
|
|
329 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
312 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21
|
|
300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
|
|
296 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21
|
|
327 inst_CLK_000_NE_D0 3 -1 3 2 3 5 -1 -1 1 0 21
|
|
322 inst_CLK_000_NE 3 -1 6 2 3 5 -1 -1 1 0 21
|
|
318 inst_CLK_000_D1 3 -1 4 2 4 5 -1 -1 1 0 21
|
|
317 inst_CLK_OUT_PRE_50 3 -1 5 2 0 5 -1 -1 1 0 21
|
|
311 inst_VPA_D 3 -1 5 2 3 5 -1 -1 1 0 21
|
|
364 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
363 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
362 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
306 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
356 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
358 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21
|
|
369 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
359 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
333 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21
|
|
293 N_317_i 3 -1 5 1 5 -1 -1 4 0 21
|
|
366 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
365 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
332 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21
|
|
371 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
367 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
334 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21
|
|
354 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
353 CLK_000_N_SYNC_9_ 3 -1 0 1 7 -1 -1 1 0 21
|
|
352 CLK_000_N_SYNC_8_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_7_ 3 -1 5 1 0 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_6_ 3 -1 6 1 5 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_5_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_4_ 3 -1 1 1 3 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_3_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
345 CLK_000_N_SYNC_1_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
344 CLK_000_N_SYNC_0_ 3 -1 4 1 0 -1 -1 1 0 21
|
|
343 CLK_000_P_SYNC_8_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
342 CLK_000_P_SYNC_7_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
341 CLK_000_P_SYNC_6_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
340 CLK_000_P_SYNC_5_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
339 CLK_000_P_SYNC_4_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
338 CLK_000_P_SYNC_3_ 3 -1 4 1 6 -1 -1 1 0 21
|
|
337 CLK_000_P_SYNC_2_ 3 -1 6 1 4 -1 -1 1 0 21
|
|
336 CLK_000_P_SYNC_1_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
335 CLK_000_P_SYNC_0_ 3 -1 4 1 1 -1 -1 1 0 21
|
|
326 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
325 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
324 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
323 CLK_000_N_SYNC_11_ 3 -1 7 1 6 -1 -1 1 0 21
|
|
321 CLK_000_P_SYNC_9_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
315 inst_DTACK_D0 3 -1 1 1 5 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 6 66 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 3 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
59 A1 1 -1 -1 1 1 59 -1
|
|
35 VPA 1 -1 -1 1 5 35 -1
|
|
29 DTACK 1 -1 -1 1 1 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 0 13 -1
|
|
10 CLK_000 1 -1 -1 1 1 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
140 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 4 1 2 5 7 40 -1 1 0 21
|
|
79 RW_000 5 365 7 3 0 4 6 79 -1 3 0 21
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
68 A0 5 366 6 2 0 1 68 -1 3 0 21
|
|
70 RW 5 371 6 2 5 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 362 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 364 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 363 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 369 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 368 7 0 82 -1 3 0 21
|
|
34 VMA 5 370 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 367 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
368 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21
|
|
302 inst_nEXP_SPACE_D0reg 3 -1 0 7 0 2 3 4 5 6 7 -1 -1 1 0 21
|
|
316 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
301 inst_AS_030_D0 3 -1 7 5 1 3 4 5 7 -1 -1 1 0 21
|
|
355 SM_AMIGA_6_ 3 -1 5 4 0 1 2 5 -1 -1 3 0 21
|
|
299 SM_AMIGA_5_ 3 -1 2 4 1 2 5 7 -1 -1 3 0 21
|
|
320 inst_CLK_000_PE 3 -1 4 4 2 3 5 7 -1 -1 1 0 21
|
|
319 inst_CLK_000_D0 3 -1 4 4 2 3 4 5 -1 -1 1 0 21
|
|
304 inst_BGACK_030_INT_D 3 -1 7 4 0 1 5 6 -1 -1 1 0 21
|
|
360 SM_AMIGA_i_7_ 3 -1 2 3 3 5 7 -1 -1 15 0 21
|
|
295 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 4 0 21
|
|
310 SIZE_DMA_1_ 3 -1 0 3 0 6 7 -1 -1 3 0 21
|
|
296 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 3 0 21
|
|
294 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 3 0 21
|
|
326 SM_AMIGA_0_ 3 -1 2 3 2 5 7 -1 -1 2 0 21
|
|
322 inst_CLK_000_NE 3 -1 4 3 2 3 5 -1 -1 1 0 21
|
|
314 inst_CLK_OUT_PRE_D 3 -1 5 3 1 6 7 -1 -1 1 0 21
|
|
305 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
303 inst_AS_030_000_SYNC 3 -1 5 2 2 5 -1 -1 7 0 21
|
|
329 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 5 0 21
|
|
370 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21
|
|
357 SM_AMIGA_1_ 3 -1 2 2 2 7 -1 -1 3 0 21
|
|
328 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21
|
|
313 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21
|
|
309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
327 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 2 0 3 -1 -1 2 0 21
|
|
312 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21
|
|
297 cpu_est_0_ 3 -1 2 2 2 3 -1 -1 2 0 21
|
|
321 inst_CLK_000_NE_D0 3 -1 5 2 2 3 -1 -1 1 0 21
|
|
318 inst_CLK_000_D1 3 -1 5 2 2 5 -1 -1 1 0 21
|
|
311 inst_VPA_D 3 -1 0 2 2 3 -1 -1 1 0 21
|
|
364 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
363 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
362 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
306 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
356 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
358 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21
|
|
369 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
359 SM_AMIGA_2_ 3 -1 2 1 2 -1 -1 4 0 21
|
|
331 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21
|
|
366 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
365 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
330 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21
|
|
308 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
371 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
367 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
332 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21
|
|
307 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
354 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
353 CLK_000_N_SYNC_9_ 3 -1 6 1 7 -1 -1 1 0 21
|
|
352 CLK_000_N_SYNC_8_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_7_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_6_ 3 -1 5 1 3 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_5_ 3 -1 6 1 5 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_4_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_3_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_2_ 3 -1 6 1 3 -1 -1 1 0 21
|
|
345 CLK_000_N_SYNC_1_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
344 CLK_000_N_SYNC_0_ 3 -1 5 1 6 -1 -1 1 0 21
|
|
343 CLK_000_P_SYNC_9_ 3 -1 2 1 6 -1 -1 1 0 21
|
|
342 CLK_000_P_SYNC_8_ 3 -1 5 1 2 -1 -1 1 0 21
|
|
341 CLK_000_P_SYNC_7_ 3 -1 2 1 5 -1 -1 1 0 21
|
|
340 CLK_000_P_SYNC_6_ 3 -1 1 1 2 -1 -1 1 0 21
|
|
339 CLK_000_P_SYNC_5_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
338 CLK_000_P_SYNC_4_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
337 CLK_000_P_SYNC_3_ 3 -1 2 1 0 -1 -1 1 0 21
|
|
336 CLK_000_P_SYNC_2_ 3 -1 6 1 2 -1 -1 1 0 21
|
|
335 CLK_000_P_SYNC_1_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
334 CLK_000_P_SYNC_0_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
333 CLK_000_P_SYNC_10_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
325 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
324 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
323 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
317 inst_CLK_OUT_PRE_50 3 -1 5 1 5 -1 -1 1 0 21
|
|
315 inst_DTACK_D0 3 -1 6 1 2 -1 -1 1 0 21
|
|
293 N_336_i 3 -1 2 1 2 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 4 5 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 4 5 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 4 5 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 4 5 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 4 5 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 4 5 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
59 A1 1 -1 -1 2 0 1 59 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
|
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
|
35 VPA 1 -1 -1 1 0 35 -1
|
|
29 DTACK 1 -1 -1 1 6 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 0 13 -1
|
|
10 CLK_000 1 -1 -1 1 4 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
129 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 5 0 1 2 5 7 40 -1 1 0 21
|
|
79 RW_000 5 352 7 3 0 4 6 79 -1 3 0 21
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
31 UDS_000 5 -1 3 3 0 2 6 31 -1 1 0 21
|
|
68 A0 5 353 6 2 5 6 68 -1 3 0 21
|
|
70 RW 5 358 6 2 1 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 2 30 -1 1 0 21
|
|
78 SIZE_1_ 5 -1 7 1 6 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 6 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 351 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 360 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 359 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 356 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 355 7 0 82 -1 3 0 21
|
|
34 VMA 5 357 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 354 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
355 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 3 0 21
|
|
315 inst_RESET_OUT 3 -1 6 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
318 inst_CLK_000_PE 3 -1 5 6 0 1 2 3 5 7 -1 -1 1 0 21
|
|
301 inst_nEXP_SPACE_D0reg 3 -1 6 6 0 3 4 5 6 7 -1 -1 1 0 21
|
|
300 inst_AS_030_D0 3 -1 7 6 0 1 3 4 5 7 -1 -1 1 0 21
|
|
348 SM_AMIGA_i_7_ 3 -1 5 5 0 1 3 5 7 -1 -1 15 0 21
|
|
320 inst_CLK_000_NE 3 -1 5 4 1 3 5 6 -1 -1 1 0 21
|
|
317 inst_CLK_000_D0 3 -1 5 4 1 3 5 6 -1 -1 1 0 21
|
|
303 inst_BGACK_030_INT_D 3 -1 7 4 0 2 3 6 -1 -1 1 0 21
|
|
293 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 4 0 21
|
|
343 SM_AMIGA_6_ 3 -1 5 3 1 5 6 -1 -1 3 0 21
|
|
327 SM_AMIGA_4_ 3 -1 5 3 1 2 5 -1 -1 3 0 21
|
|
309 SIZE_DMA_1_ 3 -1 2 3 2 6 7 -1 -1 3 0 21
|
|
308 SIZE_DMA_0_ 3 -1 2 3 2 6 7 -1 -1 3 0 21
|
|
298 SM_AMIGA_5_ 3 -1 1 3 1 5 7 -1 -1 3 0 21
|
|
296 cpu_est_1_ 3 -1 2 3 2 3 6 -1 -1 3 0 21
|
|
294 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 3 0 21
|
|
325 SM_AMIGA_0_ 3 -1 5 3 1 5 7 -1 -1 2 0 21
|
|
319 inst_CLK_000_NE_D0 3 -1 1 3 2 3 5 -1 -1 1 0 21
|
|
313 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
|
310 inst_VPA_D 3 -1 2 3 2 3 5 -1 -1 1 0 21
|
|
304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
302 inst_AS_030_000_SYNC 3 -1 0 2 0 5 -1 -1 7 0 21
|
|
346 SM_AMIGA_3_ 3 -1 2 2 2 5 -1 -1 5 0 21
|
|
328 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 5 0 21
|
|
347 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 4 0 21
|
|
357 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21
|
|
345 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
312 inst_LDS_000_INT 3 -1 6 2 3 6 -1 -1 3 0 21
|
|
311 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21
|
|
297 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21
|
|
295 cpu_est_0_ 3 -1 3 2 2 3 -1 -1 2 0 21
|
|
324 inst_CLK_000_D1 3 -1 6 2 1 5 -1 -1 1 0 21
|
|
314 inst_DTACK_D0 3 -1 3 2 2 5 -1 -1 1 0 21
|
|
360 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
359 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
351 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
344 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
356 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
330 RST_DLY_1_ 3 -1 6 1 6 -1 -1 4 0 21
|
|
353 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
352 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
329 RST_DLY_0_ 3 -1 6 1 6 -1 -1 3 0 21
|
|
307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
358 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
354 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
350 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
331 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21
|
|
326 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 3 1 3 -1 -1 2 0 21
|
|
306 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21
|
|
349 N_350 3 -1 3 1 5 -1 -1 1 0 21
|
|
342 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
341 CLK_000_N_SYNC_9_ 3 -1 0 1 7 -1 -1 1 0 21
|
|
340 CLK_000_N_SYNC_8_ 3 -1 2 1 0 -1 -1 1 0 21
|
|
339 CLK_000_N_SYNC_7_ 3 -1 2 1 2 -1 -1 1 0 21
|
|
338 CLK_000_N_SYNC_6_ 3 -1 3 1 2 -1 -1 1 0 21
|
|
337 CLK_000_N_SYNC_5_ 3 -1 0 1 3 -1 -1 1 0 21
|
|
336 CLK_000_N_SYNC_4_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
335 CLK_000_N_SYNC_3_ 3 -1 4 1 0 -1 -1 1 0 21
|
|
334 CLK_000_N_SYNC_2_ 3 -1 5 1 4 -1 -1 1 0 21
|
|
333 CLK_000_N_SYNC_1_ 3 -1 1 1 5 -1 -1 1 0 21
|
|
332 CLK_000_N_SYNC_0_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
323 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
322 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
321 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
316 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 0 4 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 0 4 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 0 4 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 0 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 0 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 0 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
67 IPL_2_ 1 -1 -1 2 1 2 67 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
59 A1 1 -1 -1 2 2 3 59 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
|
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
|
35 VPA 1 -1 -1 1 2 35 -1
|
|
29 DTACK 1 -1 -1 1 3 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 6 13 -1
|
|
10 CLK_000 1 -1 -1 1 5 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
123 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
41 AS_000 5 -1 4 4 0 4 6 7 41 -1 1 0 21
|
|
40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21
|
|
79 RW_000 5 346 7 2 4 6 79 -1 3 0 21
|
|
68 A0 5 347 6 2 1 2 68 -1 3 0 21
|
|
70 RW 5 352 6 2 5 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21
|
|
31 UDS_000 5 -1 3 1 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 1 6 30 -1 1 0 21
|
|
8 IPL_030_2_ 5 345 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 354 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 353 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 350 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 349 7 0 82 -1 3 0 21
|
|
34 VMA 5 351 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 348 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
349 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 3 0 21
|
|
318 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
301 inst_nEXP_SPACE_D0reg 3 -1 1 6 0 3 4 5 6 7 -1 -1 1 0 21
|
|
320 inst_CLK_000_PE 3 -1 5 5 0 2 3 5 7 -1 -1 1 0 21
|
|
300 inst_AS_030_D0 3 -1 7 5 0 3 4 5 7 -1 -1 1 0 21
|
|
341 SM_AMIGA_i_7_ 3 -1 5 4 0 3 5 7 -1 -1 14 0 21
|
|
296 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 4 0 21
|
|
338 SM_AMIGA_1_ 3 -1 2 3 2 5 7 -1 -1 3 0 21
|
|
336 SM_AMIGA_6_ 3 -1 5 3 1 2 5 -1 -1 3 0 21
|
|
298 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21
|
|
295 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 3 0 21
|
|
293 cpu_est_3_ 3 -1 2 3 2 3 6 -1 -1 3 0 21
|
|
342 inst_CLK_000_NE 3 -1 5 3 2 3 5 -1 -1 1 0 21
|
|
321 inst_CLK_000_NE_D0 3 -1 5 3 2 3 5 -1 -1 1 0 21
|
|
314 inst_CLK_000_D0 3 -1 5 3 3 5 6 -1 -1 1 0 21
|
|
313 inst_CLK_OUT_PRE_D 3 -1 0 3 1 6 7 -1 -1 1 0 21
|
|
305 inst_DS_000_DMA 3 -1 6 2 0 6 -1 -1 9 0 21
|
|
304 inst_AS_000_DMA 3 -1 6 2 6 7 -1 -1 7 0 21
|
|
302 inst_AS_030_000_SYNC 3 -1 0 2 0 5 -1 -1 7 0 21
|
|
339 SM_AMIGA_3_ 3 -1 2 2 2 5 -1 -1 5 0 21
|
|
329 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 5 0 21
|
|
340 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 4 0 21
|
|
351 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21
|
|
328 SM_AMIGA_4_ 3 -1 2 2 2 5 -1 -1 3 0 21
|
|
312 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21
|
|
309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
307 CYCLE_DMA_1_ 3 -1 0 2 0 6 -1 -1 3 0 21
|
|
327 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 2 0 3 -1 -1 2 0 21
|
|
326 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 2 0 21
|
|
311 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21
|
|
306 CYCLE_DMA_0_ 3 -1 0 2 0 6 -1 -1 2 0 21
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21
|
|
297 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21
|
|
294 cpu_est_0_ 3 -1 2 2 2 3 -1 -1 2 0 21
|
|
325 inst_CLK_000_D1 3 -1 6 2 4 5 -1 -1 1 0 21
|
|
315 inst_CLK_000_D5 3 -1 4 2 4 7 -1 -1 1 0 21
|
|
310 inst_VPA_D 3 -1 1 2 2 3 -1 -1 1 0 21
|
|
303 inst_BGACK_030_INT_D 3 -1 7 2 0 6 -1 -1 1 0 21
|
|
354 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
353 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
345 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
337 inst_CLK_030_H 3 -1 6 1 6 -1 -1 8 0 21
|
|
350 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
332 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21
|
|
347 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
346 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
331 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21
|
|
352 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
348 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
344 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
343 N_192 3 -1 2 1 5 -1 -1 2 0 21
|
|
333 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21
|
|
335 inst_CLK_000_D4 3 -1 7 1 4 -1 -1 1 0 21
|
|
334 inst_CLK_000_D3 3 -1 1 1 7 -1 -1 1 0 21
|
|
330 inst_CLK_000_D2 3 -1 4 1 1 -1 -1 1 0 21
|
|
324 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
323 IPL_D0_1_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
322 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
319 inst_CLK_OUT_PRE_50 3 -1 0 1 0 -1 -1 1 0 21
|
|
317 inst_DTACK_D0 3 -1 1 1 2 -1 -1 1 0 21
|
|
316 inst_CLK_000_D6 3 -1 4 1 7 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 0 4 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 0 4 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 0 4 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 0 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 0 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 0 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 2 66 -1
|
|
63 CLK_030 1 -1 -1 2 6 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 2 0 1 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
59 A1 1 -1 -1 1 0 59 -1
|
|
35 VPA 1 -1 -1 1 1 35 -1
|
|
29 DTACK 1 -1 -1 1 1 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 1 13 -1
|
|
10 CLK_000 1 -1 -1 1 5 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
129 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 5 0 1 2 5 7 40 -1 1 0 21
|
|
79 RW_000 5 352 7 3 0 4 6 79 -1 3 0 21
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
31 UDS_000 5 -1 3 3 0 2 6 31 -1 1 0 21
|
|
68 A0 5 353 6 2 5 6 68 -1 3 0 21
|
|
70 RW 5 358 6 2 1 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 2 30 -1 1 0 21
|
|
78 SIZE_1_ 5 -1 7 1 6 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 6 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 351 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 360 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 359 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 356 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 355 7 0 82 -1 3 0 21
|
|
34 VMA 5 357 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 354 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
355 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 3 0 21
|
|
315 inst_RESET_OUT 3 -1 6 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
318 inst_CLK_000_PE 3 -1 5 6 0 1 2 3 5 7 -1 -1 1 0 21
|
|
301 inst_nEXP_SPACE_D0reg 3 -1 6 6 0 3 4 5 6 7 -1 -1 1 0 21
|
|
300 inst_AS_030_D0 3 -1 7 6 0 1 3 4 5 7 -1 -1 1 0 21
|
|
348 SM_AMIGA_i_7_ 3 -1 5 5 0 1 3 5 7 -1 -1 15 0 21
|
|
320 inst_CLK_000_NE 3 -1 5 4 1 3 5 6 -1 -1 1 0 21
|
|
317 inst_CLK_000_D0 3 -1 5 4 1 3 5 6 -1 -1 1 0 21
|
|
303 inst_BGACK_030_INT_D 3 -1 7 4 0 2 3 6 -1 -1 1 0 21
|
|
293 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 4 0 21
|
|
343 SM_AMIGA_6_ 3 -1 5 3 1 5 6 -1 -1 3 0 21
|
|
327 SM_AMIGA_4_ 3 -1 5 3 1 2 5 -1 -1 3 0 21
|
|
309 SIZE_DMA_1_ 3 -1 2 3 2 6 7 -1 -1 3 0 21
|
|
308 SIZE_DMA_0_ 3 -1 2 3 2 6 7 -1 -1 3 0 21
|
|
298 SM_AMIGA_5_ 3 -1 1 3 1 5 7 -1 -1 3 0 21
|
|
296 cpu_est_1_ 3 -1 2 3 2 3 6 -1 -1 3 0 21
|
|
294 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 3 0 21
|
|
325 SM_AMIGA_0_ 3 -1 5 3 1 5 7 -1 -1 2 0 21
|
|
319 inst_CLK_000_NE_D0 3 -1 1 3 2 3 5 -1 -1 1 0 21
|
|
313 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
|
310 inst_VPA_D 3 -1 2 3 2 3 5 -1 -1 1 0 21
|
|
304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
302 inst_AS_030_000_SYNC 3 -1 0 2 0 5 -1 -1 7 0 21
|
|
346 SM_AMIGA_3_ 3 -1 2 2 2 5 -1 -1 5 0 21
|
|
328 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 5 0 21
|
|
347 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 4 0 21
|
|
357 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21
|
|
345 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
312 inst_LDS_000_INT 3 -1 6 2 3 6 -1 -1 3 0 21
|
|
311 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21
|
|
297 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21
|
|
295 cpu_est_0_ 3 -1 3 2 2 3 -1 -1 2 0 21
|
|
324 inst_CLK_000_D1 3 -1 6 2 1 5 -1 -1 1 0 21
|
|
314 inst_DTACK_D0 3 -1 3 2 2 5 -1 -1 1 0 21
|
|
360 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
359 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
351 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
344 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
356 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
330 RST_DLY_1_ 3 -1 6 1 6 -1 -1 4 0 21
|
|
353 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
352 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
329 RST_DLY_0_ 3 -1 6 1 6 -1 -1 3 0 21
|
|
307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
358 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
354 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
350 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
331 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21
|
|
326 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 3 1 3 -1 -1 2 0 21
|
|
306 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21
|
|
349 N_350 3 -1 3 1 5 -1 -1 1 0 21
|
|
342 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
341 CLK_000_N_SYNC_9_ 3 -1 0 1 7 -1 -1 1 0 21
|
|
340 CLK_000_N_SYNC_8_ 3 -1 2 1 0 -1 -1 1 0 21
|
|
339 CLK_000_N_SYNC_7_ 3 -1 2 1 2 -1 -1 1 0 21
|
|
338 CLK_000_N_SYNC_6_ 3 -1 3 1 2 -1 -1 1 0 21
|
|
337 CLK_000_N_SYNC_5_ 3 -1 0 1 3 -1 -1 1 0 21
|
|
336 CLK_000_N_SYNC_4_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
335 CLK_000_N_SYNC_3_ 3 -1 4 1 0 -1 -1 1 0 21
|
|
334 CLK_000_N_SYNC_2_ 3 -1 5 1 4 -1 -1 1 0 21
|
|
333 CLK_000_N_SYNC_1_ 3 -1 1 1 5 -1 -1 1 0 21
|
|
332 CLK_000_N_SYNC_0_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
323 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
322 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
321 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
316 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 0 4 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 0 4 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 0 4 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 0 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 0 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 0 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
67 IPL_2_ 1 -1 -1 2 1 2 67 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
59 A1 1 -1 -1 2 2 3 59 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
|
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
|
35 VPA 1 -1 -1 1 2 35 -1
|
|
29 DTACK 1 -1 -1 1 3 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 6 13 -1
|
|
10 CLK_000 1 -1 -1 1 5 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
140 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21
|
|
79 RW_000 5 365 7 3 0 4 6 79 -1 3 0 21
|
|
40 BERR 5 -1 4 3 2 5 7 40 -1 1 0 21
|
|
70 RW 5 371 6 2 2 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
68 A0 5 366 6 1 0 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 362 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 364 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 363 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 369 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 368 7 0 82 -1 3 0 21
|
|
34 VMA 5 370 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 367 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
368 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
302 inst_nEXP_SPACE_D0reg 3 -1 0 7 0 2 3 4 5 6 7 -1 -1 1 0 21
|
|
316 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
320 inst_CLK_000_PE 3 -1 6 5 1 2 3 5 7 -1 -1 1 0 21
|
|
360 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 14 0 21
|
|
301 inst_AS_030_D0 3 -1 7 4 2 3 4 7 -1 -1 1 0 21
|
|
294 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
|
355 SM_AMIGA_6_ 3 -1 5 3 0 2 5 -1 -1 3 0 21
|
|
299 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21
|
|
297 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
295 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
328 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 2 0 21
|
|
307 CYCLE_DMA_0_ 3 -1 1 3 0 1 2 -1 -1 2 0 21
|
|
319 inst_CLK_000_D0 3 -1 1 3 3 4 5 -1 -1 1 0 21
|
|
314 inst_CLK_OUT_PRE_D 3 -1 0 3 1 6 7 -1 -1 1 0 21
|
|
304 inst_BGACK_030_INT_D 3 -1 7 3 1 2 6 -1 -1 1 0 21
|
|
305 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
303 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21
|
|
331 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21
|
|
370 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
357 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
330 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21
|
|
313 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21
|
|
310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
308 CYCLE_DMA_1_ 3 -1 2 2 0 2 -1 -1 3 0 21
|
|
329 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
312 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21
|
|
300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
|
|
296 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21
|
|
327 inst_CLK_000_NE_D0 3 -1 3 2 3 5 -1 -1 1 0 21
|
|
322 inst_CLK_000_NE 3 -1 6 2 3 5 -1 -1 1 0 21
|
|
318 inst_CLK_000_D1 3 -1 4 2 4 5 -1 -1 1 0 21
|
|
317 inst_CLK_OUT_PRE_50 3 -1 5 2 0 5 -1 -1 1 0 21
|
|
311 inst_VPA_D 3 -1 5 2 3 5 -1 -1 1 0 21
|
|
364 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
363 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
362 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
306 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
356 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
358 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21
|
|
369 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
359 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
333 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21
|
|
293 N_317_i 3 -1 5 1 5 -1 -1 4 0 21
|
|
366 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
365 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
332 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21
|
|
371 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
367 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
334 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21
|
|
354 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
353 CLK_000_N_SYNC_9_ 3 -1 0 1 7 -1 -1 1 0 21
|
|
352 CLK_000_N_SYNC_8_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_7_ 3 -1 5 1 0 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_6_ 3 -1 6 1 5 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_5_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_4_ 3 -1 1 1 3 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_3_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
345 CLK_000_N_SYNC_1_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
344 CLK_000_N_SYNC_0_ 3 -1 4 1 0 -1 -1 1 0 21
|
|
343 CLK_000_P_SYNC_8_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
342 CLK_000_P_SYNC_7_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
341 CLK_000_P_SYNC_6_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
340 CLK_000_P_SYNC_5_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
339 CLK_000_P_SYNC_4_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
338 CLK_000_P_SYNC_3_ 3 -1 4 1 6 -1 -1 1 0 21
|
|
337 CLK_000_P_SYNC_2_ 3 -1 6 1 4 -1 -1 1 0 21
|
|
336 CLK_000_P_SYNC_1_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
335 CLK_000_P_SYNC_0_ 3 -1 4 1 1 -1 -1 1 0 21
|
|
326 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
325 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
324 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
323 CLK_000_N_SYNC_11_ 3 -1 7 1 6 -1 -1 1 0 21
|
|
321 CLK_000_P_SYNC_9_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
315 inst_DTACK_D0 3 -1 1 1 5 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 6 66 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 3 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
59 A1 1 -1 -1 1 1 59 -1
|
|
35 VPA 1 -1 -1 1 5 35 -1
|
|
29 DTACK 1 -1 -1 1 1 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 0 13 -1
|
|
10 CLK_000 1 -1 -1 1 1 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
140 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21
|
|
79 RW_000 5 365 7 3 0 4 6 79 -1 3 0 21
|
|
40 BERR 5 -1 4 3 2 5 7 40 -1 1 0 21
|
|
70 RW 5 371 6 2 2 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
68 A0 5 366 6 1 0 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 362 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 364 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 363 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 369 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 368 7 0 82 -1 3 0 21
|
|
34 VMA 5 370 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 367 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
368 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
302 inst_nEXP_SPACE_D0reg 3 -1 0 7 0 2 3 4 5 6 7 -1 -1 1 0 21
|
|
316 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
320 inst_CLK_000_PE 3 -1 6 5 1 2 3 5 7 -1 -1 1 0 21
|
|
360 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 14 0 21
|
|
301 inst_AS_030_D0 3 -1 7 4 2 3 4 7 -1 -1 1 0 21
|
|
294 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
|
355 SM_AMIGA_6_ 3 -1 5 3 0 2 5 -1 -1 3 0 21
|
|
299 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21
|
|
297 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
295 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
328 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 2 0 21
|
|
307 CYCLE_DMA_0_ 3 -1 1 3 0 1 2 -1 -1 2 0 21
|
|
319 inst_CLK_000_D0 3 -1 1 3 3 4 5 -1 -1 1 0 21
|
|
314 inst_CLK_OUT_PRE_D 3 -1 0 3 1 6 7 -1 -1 1 0 21
|
|
304 inst_BGACK_030_INT_D 3 -1 7 3 1 2 6 -1 -1 1 0 21
|
|
305 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
303 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21
|
|
331 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21
|
|
370 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
357 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
330 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21
|
|
313 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21
|
|
310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
308 CYCLE_DMA_1_ 3 -1 2 2 0 2 -1 -1 3 0 21
|
|
329 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
312 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21
|
|
300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
|
|
296 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21
|
|
327 inst_CLK_000_NE_D0 3 -1 3 2 3 5 -1 -1 1 0 21
|
|
322 inst_CLK_000_NE 3 -1 6 2 3 5 -1 -1 1 0 21
|
|
318 inst_CLK_000_D1 3 -1 4 2 4 5 -1 -1 1 0 21
|
|
317 inst_CLK_OUT_PRE_50 3 -1 5 2 0 5 -1 -1 1 0 21
|
|
311 inst_VPA_D 3 -1 5 2 3 5 -1 -1 1 0 21
|
|
364 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
363 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
362 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
306 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
356 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
358 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21
|
|
369 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
359 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
333 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21
|
|
293 N_317_i 3 -1 5 1 5 -1 -1 4 0 21
|
|
366 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
365 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
332 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21
|
|
371 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
367 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
334 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21
|
|
354 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
353 CLK_000_N_SYNC_9_ 3 -1 0 1 7 -1 -1 1 0 21
|
|
352 CLK_000_N_SYNC_8_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_7_ 3 -1 5 1 0 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_6_ 3 -1 6 1 5 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_5_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_4_ 3 -1 1 1 3 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_3_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
345 CLK_000_N_SYNC_1_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
344 CLK_000_N_SYNC_0_ 3 -1 4 1 0 -1 -1 1 0 21
|
|
343 CLK_000_P_SYNC_8_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
342 CLK_000_P_SYNC_7_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
341 CLK_000_P_SYNC_6_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
340 CLK_000_P_SYNC_5_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
339 CLK_000_P_SYNC_4_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
338 CLK_000_P_SYNC_3_ 3 -1 4 1 6 -1 -1 1 0 21
|
|
337 CLK_000_P_SYNC_2_ 3 -1 6 1 4 -1 -1 1 0 21
|
|
336 CLK_000_P_SYNC_1_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
335 CLK_000_P_SYNC_0_ 3 -1 4 1 1 -1 -1 1 0 21
|
|
326 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
325 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
324 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
323 CLK_000_N_SYNC_11_ 3 -1 7 1 6 -1 -1 1 0 21
|
|
321 CLK_000_P_SYNC_9_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
315 inst_DTACK_D0 3 -1 1 1 5 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 6 66 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 3 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
59 A1 1 -1 -1 1 1 59 -1
|
|
35 VPA 1 -1 -1 1 5 35 -1
|
|
29 DTACK 1 -1 -1 1 1 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 0 13 -1
|
|
10 CLK_000 1 -1 -1 1 1 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
141 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
41 AS_000 5 -1 4 4 0 1 4 7 41 -1 1 0 21
|
|
40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21
|
|
79 RW_000 5 363 7 3 0 4 6 79 -1 3 0 21
|
|
68 A0 5 364 6 2 5 6 68 -1 3 0 21
|
|
70 RW 5 371 6 2 2 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
78 SIZE_1_ 5 -1 7 1 5 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 5 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 362 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 368 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 367 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 369 7 0 80 -1 4 0 21
|
|
32 AMIGA_ADDR_ENABLE 5 372 3 0 32 -1 4 0 21
|
|
82 BGACK_030 5 366 7 0 82 -1 3 0 21
|
|
34 VMA 5 370 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 365 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
366 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
316 inst_RESET_OUT 3 -1 1 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
302 inst_nEXP_SPACE_D0reg 3 -1 0 6 0 2 3 4 6 7 -1 -1 1 0 21
|
|
322 inst_CLK_000_NE 3 -1 6 5 1 2 3 5 6 -1 -1 1 0 21
|
|
320 inst_CLK_000_PE 3 -1 1 5 1 2 3 5 7 -1 -1 1 0 21
|
|
301 inst_AS_030_D0 3 -1 7 5 0 2 3 4 7 -1 -1 1 0 21
|
|
328 SM_AMIGA_6_ 3 -1 2 4 2 3 5 6 -1 -1 3 0 21
|
|
299 SM_AMIGA_5_ 3 -1 2 4 0 2 5 7 -1 -1 3 0 21
|
|
360 SM_AMIGA_i_7_ 3 -1 5 3 2 3 7 -1 -1 14 0 21
|
|
293 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 4 0 21
|
|
357 SM_AMIGA_1_ 3 -1 5 3 2 5 7 -1 -1 3 0 21
|
|
329 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 3 0 21
|
|
296 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
294 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
319 inst_CLK_000_D0 3 -1 0 3 2 3 4 -1 -1 1 0 21
|
|
318 inst_CLK_000_D1 3 -1 4 3 2 3 4 -1 -1 1 0 21
|
|
314 inst_CLK_OUT_PRE_D 3 -1 3 3 1 6 7 -1 -1 1 0 21
|
|
304 inst_BGACK_030_INT_D 3 -1 7 3 2 3 6 -1 -1 1 0 21
|
|
305 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
358 SM_AMIGA_3_ 3 -1 5 2 2 5 -1 -1 5 0 21
|
|
332 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21
|
|
359 SM_AMIGA_2_ 3 -1 5 2 2 5 -1 -1 4 0 21
|
|
334 RST_DLY_1_ 3 -1 6 2 1 6 -1 -1 4 0 21
|
|
370 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
333 RST_DLY_0_ 3 -1 1 2 1 6 -1 -1 3 0 21
|
|
331 SM_AMIGA_4_ 3 -1 2 2 2 5 -1 -1 3 0 21
|
|
313 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21
|
|
310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
308 CYCLE_DMA_1_ 3 -1 1 2 0 1 -1 -1 3 0 21
|
|
335 RST_DLY_2_ 3 -1 6 2 1 6 -1 -1 2 0 21
|
|
312 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
307 CYCLE_DMA_0_ 3 -1 1 2 0 1 -1 -1 2 0 21
|
|
300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 3 2 2 3 -1 -1 2 0 21
|
|
297 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21
|
|
295 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 2 0 21
|
|
354 CLK_000_N_SYNC_9_ 3 -1 5 2 3 7 -1 -1 1 0 21
|
|
317 inst_CLK_OUT_PRE_50 3 -1 6 2 3 6 -1 -1 1 0 21
|
|
311 inst_VPA_D 3 -1 7 2 3 5 -1 -1 1 0 21
|
|
368 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
367 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
362 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
306 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
356 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
303 inst_AS_030_000_SYNC 3 -1 2 1 2 -1 -1 7 0 21
|
|
372 RN_AMIGA_ADDR_ENABLE 3 32 3 1 3 32 -1 4 0 21
|
|
369 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
298 N_257_i 3 -1 2 1 5 -1 -1 4 0 21
|
|
364 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
363 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
371 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
365 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
330 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 3 1 3 -1 -1 2 0 21
|
|
355 CLK_000_N_SYNC_10_ 3 -1 3 1 7 -1 -1 1 0 21
|
|
353 CLK_000_N_SYNC_8_ 3 -1 0 1 5 -1 -1 1 0 21
|
|
352 CLK_000_N_SYNC_7_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_6_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_5_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_4_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_3_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_1_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
345 CLK_000_N_SYNC_0_ 3 -1 4 1 0 -1 -1 1 0 21
|
|
344 CLK_000_P_SYNC_8_ 3 -1 4 1 1 -1 -1 1 0 21
|
|
343 CLK_000_P_SYNC_7_ 3 -1 1 1 4 -1 -1 1 0 21
|
|
342 CLK_000_P_SYNC_6_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
341 CLK_000_P_SYNC_5_ 3 -1 5 1 6 -1 -1 1 0 21
|
|
340 CLK_000_P_SYNC_4_ 3 -1 5 1 5 -1 -1 1 0 21
|
|
339 CLK_000_P_SYNC_3_ 3 -1 1 1 5 -1 -1 1 0 21
|
|
338 CLK_000_P_SYNC_2_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
337 CLK_000_P_SYNC_1_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
336 CLK_000_P_SYNC_0_ 3 -1 4 1 0 -1 -1 1 0 21
|
|
327 inst_CLK_000_NE_D0 3 -1 3 1 5 -1 -1 1 0 21
|
|
326 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
325 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
324 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
323 CLK_000_N_SYNC_11_ 3 -1 7 1 6 -1 -1 1 0 21
|
|
321 CLK_000_P_SYNC_9_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
315 inst_DTACK_D0 3 -1 5 1 5 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
67 IPL_2_ 1 -1 -1 2 1 3 67 -1
|
|
66 IPL_0_ 1 -1 -1 2 0 1 66 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 3 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
59 A1 1 -1 -1 1 3 59 -1
|
|
35 VPA 1 -1 -1 1 7 35 -1
|
|
29 DTACK 1 -1 -1 1 5 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 0 13 -1
|
|
10 CLK_000 1 -1 -1 1 0 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
140 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21
|
|
79 RW_000 5 365 7 3 0 4 6 79 -1 3 0 21
|
|
40 BERR 5 -1 4 3 2 5 7 40 -1 1 0 21
|
|
70 RW 5 371 6 2 2 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
68 A0 5 366 6 1 0 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 362 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 364 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 363 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 369 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 368 7 0 82 -1 3 0 21
|
|
34 VMA 5 370 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 367 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
368 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
302 inst_nEXP_SPACE_D0reg 3 -1 0 7 0 2 3 4 5 6 7 -1 -1 1 0 21
|
|
316 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
320 inst_CLK_000_PE 3 -1 6 5 1 2 3 5 7 -1 -1 1 0 21
|
|
360 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 14 0 21
|
|
301 inst_AS_030_D0 3 -1 7 4 2 3 4 7 -1 -1 1 0 21
|
|
294 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
|
355 SM_AMIGA_6_ 3 -1 5 3 0 2 5 -1 -1 3 0 21
|
|
299 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21
|
|
297 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
295 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
328 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 2 0 21
|
|
307 CYCLE_DMA_0_ 3 -1 1 3 0 1 2 -1 -1 2 0 21
|
|
319 inst_CLK_000_D0 3 -1 1 3 3 4 5 -1 -1 1 0 21
|
|
314 inst_CLK_OUT_PRE_D 3 -1 0 3 1 6 7 -1 -1 1 0 21
|
|
304 inst_BGACK_030_INT_D 3 -1 7 3 1 2 6 -1 -1 1 0 21
|
|
305 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
303 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21
|
|
331 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21
|
|
370 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
357 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
330 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21
|
|
313 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21
|
|
310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
308 CYCLE_DMA_1_ 3 -1 2 2 0 2 -1 -1 3 0 21
|
|
329 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
312 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21
|
|
300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
|
|
296 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21
|
|
327 inst_CLK_000_NE_D0 3 -1 3 2 3 5 -1 -1 1 0 21
|
|
322 inst_CLK_000_NE 3 -1 6 2 3 5 -1 -1 1 0 21
|
|
318 inst_CLK_000_D1 3 -1 4 2 4 5 -1 -1 1 0 21
|
|
317 inst_CLK_OUT_PRE_50 3 -1 5 2 0 5 -1 -1 1 0 21
|
|
311 inst_VPA_D 3 -1 5 2 3 5 -1 -1 1 0 21
|
|
364 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
363 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
362 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
306 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
356 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
358 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21
|
|
369 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
359 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
333 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21
|
|
293 N_317_i 3 -1 5 1 5 -1 -1 4 0 21
|
|
366 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
365 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
332 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21
|
|
371 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
367 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
334 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21
|
|
354 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
353 CLK_000_N_SYNC_9_ 3 -1 0 1 7 -1 -1 1 0 21
|
|
352 CLK_000_N_SYNC_8_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_7_ 3 -1 5 1 0 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_6_ 3 -1 6 1 5 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_5_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_4_ 3 -1 1 1 3 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_3_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
345 CLK_000_N_SYNC_1_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
344 CLK_000_N_SYNC_0_ 3 -1 4 1 0 -1 -1 1 0 21
|
|
343 CLK_000_P_SYNC_8_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
342 CLK_000_P_SYNC_7_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
341 CLK_000_P_SYNC_6_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
340 CLK_000_P_SYNC_5_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
339 CLK_000_P_SYNC_4_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
338 CLK_000_P_SYNC_3_ 3 -1 4 1 6 -1 -1 1 0 21
|
|
337 CLK_000_P_SYNC_2_ 3 -1 6 1 4 -1 -1 1 0 21
|
|
336 CLK_000_P_SYNC_1_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
335 CLK_000_P_SYNC_0_ 3 -1 4 1 1 -1 -1 1 0 21
|
|
326 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
325 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
324 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
323 CLK_000_N_SYNC_11_ 3 -1 7 1 6 -1 -1 1 0 21
|
|
321 CLK_000_P_SYNC_9_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
315 inst_DTACK_D0 3 -1 1 1 5 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 6 66 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 3 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
59 A1 1 -1 -1 1 1 59 -1
|
|
35 VPA 1 -1 -1 1 5 35 -1
|
|
29 DTACK 1 -1 -1 1 1 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 0 13 -1
|
|
10 CLK_000 1 -1 -1 1 1 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
140 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21
|
|
79 RW_000 5 365 7 3 0 4 6 79 -1 3 0 21
|
|
40 BERR 5 -1 4 3 2 5 7 40 -1 1 0 21
|
|
70 RW 5 371 6 2 2 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
68 A0 5 366 6 1 0 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 362 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 364 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 363 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 369 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 368 7 0 82 -1 3 0 21
|
|
34 VMA 5 370 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 367 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
368 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
302 inst_nEXP_SPACE_D0reg 3 -1 0 7 0 2 3 4 5 6 7 -1 -1 1 0 21
|
|
316 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
320 inst_CLK_000_PE 3 -1 6 5 1 2 3 5 7 -1 -1 1 0 21
|
|
360 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 14 0 21
|
|
301 inst_AS_030_D0 3 -1 7 4 2 3 4 7 -1 -1 1 0 21
|
|
294 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
|
355 SM_AMIGA_6_ 3 -1 5 3 0 2 5 -1 -1 3 0 21
|
|
299 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21
|
|
297 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
295 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
328 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 2 0 21
|
|
307 CYCLE_DMA_0_ 3 -1 1 3 0 1 2 -1 -1 2 0 21
|
|
319 CLK_000_D_0_ 3 -1 1 3 3 4 5 -1 -1 1 0 21
|
|
314 inst_CLK_OUT_PRE_D 3 -1 0 3 1 6 7 -1 -1 1 0 21
|
|
304 inst_BGACK_030_INT_D 3 -1 7 3 1 2 6 -1 -1 1 0 21
|
|
305 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
303 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21
|
|
331 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21
|
|
370 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
357 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
330 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21
|
|
313 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21
|
|
310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
308 CYCLE_DMA_1_ 3 -1 2 2 0 2 -1 -1 3 0 21
|
|
329 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
312 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21
|
|
300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
|
|
296 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21
|
|
327 inst_CLK_000_NE_D0 3 -1 3 2 3 5 -1 -1 1 0 21
|
|
322 inst_CLK_000_NE 3 -1 6 2 3 5 -1 -1 1 0 21
|
|
318 CLK_000_D_1_ 3 -1 4 2 4 5 -1 -1 1 0 21
|
|
317 inst_CLK_OUT_PRE_50 3 -1 5 2 0 5 -1 -1 1 0 21
|
|
311 inst_VPA_D 3 -1 5 2 3 5 -1 -1 1 0 21
|
|
364 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
363 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
362 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
306 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
356 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
358 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21
|
|
369 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
359 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
333 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21
|
|
293 N_317_i 3 -1 5 1 5 -1 -1 4 0 21
|
|
366 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
365 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
332 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21
|
|
371 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
367 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
334 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21
|
|
354 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
353 CLK_000_N_SYNC_9_ 3 -1 0 1 7 -1 -1 1 0 21
|
|
352 CLK_000_N_SYNC_8_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_7_ 3 -1 5 1 0 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_6_ 3 -1 6 1 5 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_5_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_4_ 3 -1 1 1 3 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_3_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
345 CLK_000_N_SYNC_1_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
344 CLK_000_N_SYNC_0_ 3 -1 4 1 0 -1 -1 1 0 21
|
|
343 CLK_000_P_SYNC_8_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
342 CLK_000_P_SYNC_7_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
341 CLK_000_P_SYNC_6_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
340 CLK_000_P_SYNC_5_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
339 CLK_000_P_SYNC_4_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
338 CLK_000_P_SYNC_3_ 3 -1 4 1 6 -1 -1 1 0 21
|
|
337 CLK_000_P_SYNC_2_ 3 -1 6 1 4 -1 -1 1 0 21
|
|
336 CLK_000_P_SYNC_1_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
335 CLK_000_P_SYNC_0_ 3 -1 4 1 1 -1 -1 1 0 21
|
|
326 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
325 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
324 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
323 CLK_000_N_SYNC_11_ 3 -1 7 1 6 -1 -1 1 0 21
|
|
321 CLK_000_P_SYNC_9_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
315 inst_DTACK_D0 3 -1 1 1 5 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 6 66 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 3 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
59 A1 1 -1 -1 1 1 59 -1
|
|
35 VPA 1 -1 -1 1 5 35 -1
|
|
29 DTACK 1 -1 -1 1 1 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 0 13 -1
|
|
10 CLK_000 1 -1 -1 1 1 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
129 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 5 0 1 2 5 7 40 -1 1 0 21
|
|
79 RW_000 5 352 7 3 0 4 6 79 -1 3 0 21
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
31 UDS_000 5 -1 3 3 0 2 6 31 -1 1 0 21
|
|
68 A0 5 353 6 2 5 6 68 -1 3 0 21
|
|
70 RW 5 358 6 2 1 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 2 30 -1 1 0 21
|
|
78 SIZE_1_ 5 -1 7 1 6 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 6 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 351 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 360 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 359 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 356 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 355 7 0 82 -1 3 0 21
|
|
34 VMA 5 357 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 354 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
355 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 3 0 21
|
|
315 inst_RESET_OUT 3 -1 6 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
318 inst_CLK_000_PE 3 -1 5 6 0 1 2 3 5 7 -1 -1 1 0 21
|
|
301 inst_nEXP_SPACE_D0reg 3 -1 6 6 0 3 4 5 6 7 -1 -1 1 0 21
|
|
300 inst_AS_030_D0 3 -1 7 6 0 1 3 4 5 7 -1 -1 1 0 21
|
|
348 SM_AMIGA_i_7_ 3 -1 5 5 0 1 3 5 7 -1 -1 15 0 21
|
|
320 inst_CLK_000_NE 3 -1 5 4 1 3 5 6 -1 -1 1 0 21
|
|
317 CLK_000_D_0_ 3 -1 5 4 1 3 5 6 -1 -1 1 0 21
|
|
303 inst_BGACK_030_INT_D 3 -1 7 4 0 2 3 6 -1 -1 1 0 21
|
|
293 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 4 0 21
|
|
343 SM_AMIGA_6_ 3 -1 5 3 1 5 6 -1 -1 3 0 21
|
|
327 SM_AMIGA_4_ 3 -1 5 3 1 2 5 -1 -1 3 0 21
|
|
309 SIZE_DMA_1_ 3 -1 2 3 2 6 7 -1 -1 3 0 21
|
|
308 SIZE_DMA_0_ 3 -1 2 3 2 6 7 -1 -1 3 0 21
|
|
298 SM_AMIGA_5_ 3 -1 1 3 1 5 7 -1 -1 3 0 21
|
|
296 cpu_est_1_ 3 -1 2 3 2 3 6 -1 -1 3 0 21
|
|
294 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 3 0 21
|
|
325 SM_AMIGA_0_ 3 -1 5 3 1 5 7 -1 -1 2 0 21
|
|
319 inst_CLK_000_NE_D0 3 -1 1 3 2 3 5 -1 -1 1 0 21
|
|
313 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
|
310 inst_VPA_D 3 -1 2 3 2 3 5 -1 -1 1 0 21
|
|
304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
302 inst_AS_030_000_SYNC 3 -1 0 2 0 5 -1 -1 7 0 21
|
|
346 SM_AMIGA_3_ 3 -1 2 2 2 5 -1 -1 5 0 21
|
|
328 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 5 0 21
|
|
347 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 4 0 21
|
|
357 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21
|
|
345 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
312 inst_LDS_000_INT 3 -1 6 2 3 6 -1 -1 3 0 21
|
|
311 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21
|
|
297 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21
|
|
295 cpu_est_0_ 3 -1 3 2 2 3 -1 -1 2 0 21
|
|
324 CLK_000_D_1_ 3 -1 6 2 1 5 -1 -1 1 0 21
|
|
314 inst_DTACK_D0 3 -1 3 2 2 5 -1 -1 1 0 21
|
|
360 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
359 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
351 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
344 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
356 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
330 RST_DLY_1_ 3 -1 6 1 6 -1 -1 4 0 21
|
|
353 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
352 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
329 RST_DLY_0_ 3 -1 6 1 6 -1 -1 3 0 21
|
|
307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
358 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
354 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
350 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
331 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21
|
|
326 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 3 1 3 -1 -1 2 0 21
|
|
306 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21
|
|
349 N_350 3 -1 3 1 5 -1 -1 1 0 21
|
|
342 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
341 CLK_000_N_SYNC_9_ 3 -1 0 1 7 -1 -1 1 0 21
|
|
340 CLK_000_N_SYNC_8_ 3 -1 2 1 0 -1 -1 1 0 21
|
|
339 CLK_000_N_SYNC_7_ 3 -1 2 1 2 -1 -1 1 0 21
|
|
338 CLK_000_N_SYNC_6_ 3 -1 3 1 2 -1 -1 1 0 21
|
|
337 CLK_000_N_SYNC_5_ 3 -1 0 1 3 -1 -1 1 0 21
|
|
336 CLK_000_N_SYNC_4_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
335 CLK_000_N_SYNC_3_ 3 -1 4 1 0 -1 -1 1 0 21
|
|
334 CLK_000_N_SYNC_2_ 3 -1 5 1 4 -1 -1 1 0 21
|
|
333 CLK_000_N_SYNC_1_ 3 -1 1 1 5 -1 -1 1 0 21
|
|
332 CLK_000_N_SYNC_0_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
323 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
322 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
321 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
316 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 0 4 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 0 4 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 0 4 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 0 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 0 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 0 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
67 IPL_2_ 1 -1 -1 2 1 2 67 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
59 A1 1 -1 -1 2 2 3 59 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
|
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
|
35 VPA 1 -1 -1 1 2 35 -1
|
|
29 DTACK 1 -1 -1 1 3 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 6 13 -1
|
|
10 CLK_000 1 -1 -1 1 5 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
127 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21
|
|
79 RW_000 5 350 7 3 0 4 6 79 -1 3 0 21
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
68 A0 5 351 6 2 1 6 68 -1 3 0 21
|
|
70 RW 5 356 6 2 0 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 349 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 358 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 357 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 354 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 353 7 0 82 -1 3 0 21
|
|
34 VMA 5 355 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 352 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
353 RN_BGACK_030 3 82 7 7 0 2 3 4 5 6 7 82 -1 3 0 21
|
|
302 inst_nEXP_SPACE_D0reg 3 -1 5 7 0 2 3 4 5 6 7 -1 -1 1 0 21
|
|
316 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
347 SM_AMIGA_i_7_ 3 -1 2 5 0 2 3 5 7 -1 -1 14 0 21
|
|
301 inst_AS_030_D0 3 -1 7 5 0 3 4 5 7 -1 -1 1 0 21
|
|
294 cpu_est_2_ 3 -1 1 4 1 2 3 6 -1 -1 4 0 21
|
|
342 SM_AMIGA_6_ 3 -1 2 4 0 1 2 6 -1 -1 3 0 21
|
|
299 SM_AMIGA_5_ 3 -1 0 4 0 2 5 7 -1 -1 3 0 21
|
|
297 cpu_est_1_ 3 -1 1 4 1 2 3 6 -1 -1 3 0 21
|
|
295 cpu_est_3_ 3 -1 2 4 1 2 3 6 -1 -1 3 0 21
|
|
322 inst_CLK_000_NE 3 -1 1 4 0 2 3 6 -1 -1 1 0 21
|
|
321 inst_CLK_000_NE_D0 3 -1 6 4 1 2 3 5 -1 -1 1 0 21
|
|
320 inst_CLK_000_PE 3 -1 4 4 0 2 3 7 -1 -1 1 0 21
|
|
319 CLK_000_D_0_ 3 -1 1 4 1 2 3 4 -1 -1 1 0 21
|
|
326 SM_AMIGA_0_ 3 -1 2 3 0 2 7 -1 -1 2 0 21
|
|
296 cpu_est_0_ 3 -1 3 3 1 2 3 -1 -1 2 0 21
|
|
318 CLK_000_D_1_ 3 -1 4 3 1 2 4 -1 -1 1 0 21
|
|
314 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
|
305 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
303 inst_AS_030_000_SYNC 3 -1 5 2 2 5 -1 -1 7 0 21
|
|
329 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 5 0 21
|
|
355 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21
|
|
344 SM_AMIGA_1_ 3 -1 2 2 2 7 -1 -1 3 0 21
|
|
328 SM_AMIGA_4_ 3 -1 0 2 0 2 -1 -1 3 0 21
|
|
313 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21
|
|
310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
327 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
312 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21
|
|
311 inst_VPA_D 3 -1 3 2 2 3 -1 -1 1 0 21
|
|
304 inst_BGACK_030_INT_D 3 -1 7 2 5 6 -1 -1 1 0 21
|
|
358 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
357 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
349 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
306 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
343 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
345 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21
|
|
354 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
346 SM_AMIGA_2_ 3 -1 2 1 2 -1 -1 4 0 21
|
|
331 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21
|
|
293 N_317_i 3 -1 2 1 2 -1 -1 4 0 21
|
|
351 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
350 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
330 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21
|
|
308 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
356 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
352 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
348 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
332 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21
|
|
307 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
341 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
340 CLK_000_N_SYNC_9_ 3 -1 5 1 7 -1 -1 1 0 21
|
|
339 CLK_000_N_SYNC_8_ 3 -1 0 1 5 -1 -1 1 0 21
|
|
338 CLK_000_N_SYNC_7_ 3 -1 5 1 0 -1 -1 1 0 21
|
|
337 CLK_000_N_SYNC_6_ 3 -1 5 1 5 -1 -1 1 0 21
|
|
336 CLK_000_N_SYNC_5_ 3 -1 6 1 5 -1 -1 1 0 21
|
|
335 CLK_000_N_SYNC_4_ 3 -1 5 1 6 -1 -1 1 0 21
|
|
334 CLK_000_N_SYNC_3_ 3 -1 1 1 5 -1 -1 1 0 21
|
|
333 CLK_000_N_SYNC_2_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
325 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
324 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
323 IPL_D0_0_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
317 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
315 inst_DTACK_D0 3 -1 5 1 2 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 4 5 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 4 5 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 4 5 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 4 5 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 4 5 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 4 5 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 5 66 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
59 A1 1 -1 -1 1 6 59 -1
|
|
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
|
35 VPA 1 -1 -1 1 3 35 -1
|
|
29 DTACK 1 -1 -1 1 5 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 5 13 -1
|
|
10 CLK_000 1 -1 -1 1 1 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
127 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 5 1 2 5 6 7 40 -1 1 0 21
|
|
79 RW_000 5 350 7 3 0 4 6 79 -1 3 0 21
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
70 RW 5 356 6 2 1 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
68 A0 5 351 6 1 3 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 3 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 349 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 358 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 357 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 354 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 353 7 0 82 -1 3 0 21
|
|
34 VMA 5 355 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 352 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
353 RN_BGACK_030 3 82 7 7 0 2 3 4 5 6 7 82 -1 3 0 21
|
|
315 inst_RESET_OUT 3 -1 2 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
319 inst_CLK_000_PE 3 -1 5 7 0 1 2 3 5 6 7 -1 -1 1 0 21
|
|
301 inst_nEXP_SPACE_D0reg 3 -1 6 6 0 3 4 5 6 7 -1 -1 1 0 21
|
|
300 inst_AS_030_D0 3 -1 4 6 1 3 4 5 6 7 -1 -1 1 0 21
|
|
321 inst_CLK_000_NE 3 -1 5 5 1 2 3 5 6 -1 -1 1 0 21
|
|
347 SM_AMIGA_i_7_ 3 -1 5 4 1 3 5 7 -1 -1 14 0 21
|
|
342 SM_AMIGA_6_ 3 -1 5 4 1 3 5 6 -1 -1 3 0 21
|
|
298 SM_AMIGA_5_ 3 -1 6 4 1 5 6 7 -1 -1 3 0 21
|
|
293 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 4 0 21
|
|
327 SM_AMIGA_4_ 3 -1 1 3 1 2 5 -1 -1 3 0 21
|
|
309 SIZE_DMA_1_ 3 -1 0 3 0 6 7 -1 -1 3 0 21
|
|
296 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 3 0 21
|
|
294 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 3 0 21
|
|
325 SM_AMIGA_0_ 3 -1 5 3 1 5 7 -1 -1 2 0 21
|
|
313 inst_CLK_OUT_PRE_D 3 -1 7 3 1 6 7 -1 -1 1 0 21
|
|
303 inst_BGACK_030_INT_D 3 -1 4 3 0 5 6 -1 -1 1 0 21
|
|
304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
345 SM_AMIGA_3_ 3 -1 2 2 2 5 -1 -1 5 0 21
|
|
328 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 5 0 21
|
|
346 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 4 0 21
|
|
355 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21
|
|
344 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
326 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 2 0 3 -1 -1 2 0 21
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21
|
|
297 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21
|
|
295 cpu_est_0_ 3 -1 3 2 2 3 -1 -1 2 0 21
|
|
320 inst_CLK_000_NE_D0 3 -1 5 2 2 5 -1 -1 1 0 21
|
|
318 CLK_000_D_0_ 3 -1 0 2 3 5 -1 -1 1 0 21
|
|
310 inst_VPA_D 3 -1 1 2 2 3 -1 -1 1 0 21
|
|
358 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
357 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
349 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
343 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
302 inst_AS_030_000_SYNC 3 -1 5 1 5 -1 -1 7 0 21
|
|
354 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
331 RST_DLY_1_ 3 -1 2 1 2 -1 -1 4 0 21
|
|
351 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
350 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
329 RST_DLY_0_ 3 -1 2 1 2 -1 -1 3 0 21
|
|
312 inst_LDS_000_INT 3 -1 3 1 3 -1 -1 3 0 21
|
|
307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
356 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
352 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
348 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
332 RST_DLY_2_ 3 -1 2 1 2 -1 -1 2 0 21
|
|
330 N_182_i 3 -1 2 1 5 -1 -1 2 0 21
|
|
311 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21
|
|
306 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
341 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
340 CLK_000_N_SYNC_9_ 3 -1 0 1 7 -1 -1 1 0 21
|
|
339 CLK_000_N_SYNC_8_ 3 -1 1 1 0 -1 -1 1 0 21
|
|
338 CLK_000_N_SYNC_7_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
337 CLK_000_N_SYNC_6_ 3 -1 2 1 5 -1 -1 1 0 21
|
|
336 CLK_000_N_SYNC_5_ 3 -1 2 1 2 -1 -1 1 0 21
|
|
335 CLK_000_N_SYNC_4_ 3 -1 6 1 2 -1 -1 1 0 21
|
|
334 CLK_000_N_SYNC_3_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
333 CLK_000_N_SYNC_2_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
324 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
323 IPL_D0_1_ 3 -1 4 1 1 -1 -1 1 0 21
|
|
322 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
317 CLK_000_D_1_ 3 -1 5 1 5 -1 -1 1 0 21
|
|
316 inst_CLK_OUT_PRE_50 3 -1 7 1 7 -1 -1 1 0 21
|
|
314 inst_DTACK_D0 3 -1 4 1 2 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 4 5 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 4 5 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 4 5 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 4 5 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 4 5 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 4 5 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
67 IPL_2_ 1 -1 -1 2 1 6 67 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 4 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
|
59 A1 1 -1 -1 1 0 59 -1
|
|
35 VPA 1 -1 -1 1 1 35 -1
|
|
29 DTACK 1 -1 -1 1 4 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 6 13 -1
|
|
10 CLK_000 1 -1 -1 1 0 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
130 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 6 0 1 2 5 6 7 40 -1 1 0 21
|
|
79 RW_000 5 353 7 3 0 4 6 79 -1 3 0 21
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
31 UDS_000 5 -1 3 3 0 2 6 31 -1 1 0 21
|
|
70 RW 5 359 6 2 0 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 2 30 -1 1 0 21
|
|
68 A0 5 354 6 1 1 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 352 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 361 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 360 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 357 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 356 7 0 82 -1 3 0 21
|
|
34 VMA 5 358 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 355 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
356 RN_BGACK_030 3 82 7 7 0 2 3 4 5 6 7 82 -1 3 0 21
|
|
315 inst_RESET_OUT 3 -1 6 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
301 inst_nEXP_SPACE_D0reg 3 -1 2 6 0 3 4 5 6 7 -1 -1 1 0 21
|
|
300 inst_AS_030_D0 3 -1 4 6 0 1 3 4 6 7 -1 -1 1 0 21
|
|
350 SM_AMIGA_i_7_ 3 -1 5 5 0 3 5 6 7 -1 -1 14 0 21
|
|
322 inst_CLK_000_NE 3 -1 5 5 0 3 5 6 7 -1 -1 1 0 21
|
|
320 inst_CLK_000_PE 3 -1 5 5 0 2 3 5 7 -1 -1 1 0 21
|
|
298 SM_AMIGA_5_ 3 -1 0 4 0 1 5 7 -1 -1 3 0 21
|
|
318 CLK_000_D_0_ 3 -1 6 4 0 2 3 5 -1 -1 1 0 21
|
|
294 cpu_est_2_ 3 -1 3 3 2 3 6 -1 -1 4 0 21
|
|
344 SM_AMIGA_6_ 3 -1 5 3 0 1 5 -1 -1 3 0 21
|
|
328 SM_AMIGA_4_ 3 -1 0 3 0 2 5 -1 -1 3 0 21
|
|
309 SIZE_DMA_1_ 3 -1 2 3 2 6 7 -1 -1 3 0 21
|
|
308 SIZE_DMA_0_ 3 -1 2 3 2 6 7 -1 -1 3 0 21
|
|
295 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 3 0 21
|
|
293 cpu_est_1_ 3 -1 2 3 2 3 6 -1 -1 3 0 21
|
|
326 SM_AMIGA_0_ 3 -1 5 3 0 5 7 -1 -1 2 0 21
|
|
321 inst_CLK_000_NE_D0 3 -1 7 3 2 3 5 -1 -1 1 0 21
|
|
313 inst_CLK_OUT_PRE_D 3 -1 0 3 1 6 7 -1 -1 1 0 21
|
|
303 inst_BGACK_030_INT_D 3 -1 7 3 2 5 6 -1 -1 1 0 21
|
|
304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
302 inst_AS_030_000_SYNC 3 -1 6 2 5 6 -1 -1 7 0 21
|
|
347 SM_AMIGA_3_ 3 -1 2 2 2 5 -1 -1 5 0 21
|
|
329 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 5 0 21
|
|
349 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 4 0 21
|
|
358 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21
|
|
346 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
312 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21
|
|
327 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 2 3 5 -1 -1 2 0 21
|
|
311 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
297 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21
|
|
296 cpu_est_0_ 3 -1 3 2 2 3 -1 -1 2 0 21
|
|
317 CLK_000_D_1_ 3 -1 2 2 0 5 -1 -1 1 0 21
|
|
316 inst_CLK_OUT_PRE_50 3 -1 3 2 0 3 -1 -1 1 0 21
|
|
310 inst_VPA_D 3 -1 1 2 2 3 -1 -1 1 0 21
|
|
361 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
360 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
352 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
345 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
357 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
331 RST_DLY_1_ 3 -1 6 1 6 -1 -1 4 0 21
|
|
354 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
353 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
330 RST_DLY_0_ 3 -1 6 1 6 -1 -1 3 0 21
|
|
307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
359 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
355 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
351 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
348 N_187_i 3 -1 2 1 5 -1 -1 2 0 21
|
|
332 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21
|
|
306 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21
|
|
343 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
342 CLK_000_N_SYNC_9_ 3 -1 1 1 7 -1 -1 1 0 21
|
|
341 CLK_000_N_SYNC_8_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
340 CLK_000_N_SYNC_7_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
339 CLK_000_N_SYNC_6_ 3 -1 5 1 5 -1 -1 1 0 21
|
|
338 CLK_000_N_SYNC_5_ 3 -1 2 1 5 -1 -1 1 0 21
|
|
337 CLK_000_N_SYNC_4_ 3 -1 6 1 2 -1 -1 1 0 21
|
|
336 CLK_000_N_SYNC_3_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
335 CLK_000_N_SYNC_2_ 3 -1 5 1 3 -1 -1 1 0 21
|
|
334 CLK_000_N_SYNC_1_ 3 -1 1 1 5 -1 -1 1 0 21
|
|
333 CLK_000_N_SYNC_0_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
325 IPL_D0_2_ 3 -1 4 1 1 -1 -1 1 0 21
|
|
324 IPL_D0_1_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
323 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
319 CLK_000_D_2_ 3 -1 5 1 5 -1 -1 1 0 21
|
|
314 inst_DTACK_D0 3 -1 4 1 2 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 4 6 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 4 6 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 4 6 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 4 6 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 4 6 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 4 6 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
67 IPL_2_ 1 -1 -1 2 1 4 67 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 3 66 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
59 A1 1 -1 -1 2 2 5 59 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 2 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
35 VPA 1 -1 -1 1 1 35 -1
|
|
29 DTACK 1 -1 -1 1 4 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 2 13 -1
|
|
10 CLK_000 1 -1 -1 1 6 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
140 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21
|
|
79 RW_000 5 365 7 3 0 4 6 79 -1 3 0 21
|
|
40 BERR 5 -1 4 3 2 5 7 40 -1 1 0 21
|
|
70 RW 5 371 6 2 2 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
68 A0 5 366 6 1 0 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 362 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 364 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 363 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 369 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 368 7 0 82 -1 3 0 21
|
|
34 VMA 5 370 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 367 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
368 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
302 inst_nEXP_SPACE_D0reg 3 -1 0 7 0 2 3 4 5 6 7 -1 -1 1 0 21
|
|
316 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
320 inst_CLK_000_PE 3 -1 6 5 1 2 3 5 7 -1 -1 1 0 21
|
|
360 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 14 0 21
|
|
301 inst_AS_030_D0 3 -1 7 4 2 3 4 7 -1 -1 1 0 21
|
|
294 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
|
355 SM_AMIGA_6_ 3 -1 5 3 0 2 5 -1 -1 3 0 21
|
|
299 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21
|
|
297 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
295 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
328 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 2 0 21
|
|
307 CYCLE_DMA_0_ 3 -1 1 3 0 1 2 -1 -1 2 0 21
|
|
319 CLK_000_D_0_ 3 -1 1 3 3 4 5 -1 -1 1 0 21
|
|
314 inst_CLK_OUT_PRE_D 3 -1 0 3 1 6 7 -1 -1 1 0 21
|
|
304 inst_BGACK_030_INT_D 3 -1 7 3 1 2 6 -1 -1 1 0 21
|
|
305 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
303 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21
|
|
331 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21
|
|
370 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
357 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
330 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21
|
|
313 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21
|
|
310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
308 CYCLE_DMA_1_ 3 -1 2 2 0 2 -1 -1 3 0 21
|
|
329 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
312 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21
|
|
300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
|
|
296 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21
|
|
327 inst_CLK_000_NE_D0 3 -1 3 2 3 5 -1 -1 1 0 21
|
|
322 inst_CLK_000_NE 3 -1 6 2 3 5 -1 -1 1 0 21
|
|
318 CLK_000_D_1_ 3 -1 4 2 4 5 -1 -1 1 0 21
|
|
317 inst_CLK_OUT_PRE_50 3 -1 5 2 0 5 -1 -1 1 0 21
|
|
311 inst_VPA_D 3 -1 5 2 3 5 -1 -1 1 0 21
|
|
364 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
363 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
362 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
306 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
356 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
358 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21
|
|
369 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
359 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
333 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21
|
|
293 N_317_i 3 -1 5 1 5 -1 -1 4 0 21
|
|
366 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
365 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
332 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21
|
|
371 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
367 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
334 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21
|
|
354 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
353 CLK_000_N_SYNC_9_ 3 -1 0 1 7 -1 -1 1 0 21
|
|
352 CLK_000_N_SYNC_8_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_7_ 3 -1 5 1 0 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_6_ 3 -1 6 1 5 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_5_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_4_ 3 -1 1 1 3 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_3_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
345 CLK_000_N_SYNC_1_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
344 CLK_000_N_SYNC_0_ 3 -1 4 1 0 -1 -1 1 0 21
|
|
343 CLK_000_P_SYNC_8_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
342 CLK_000_P_SYNC_7_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
341 CLK_000_P_SYNC_6_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
340 CLK_000_P_SYNC_5_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
339 CLK_000_P_SYNC_4_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
338 CLK_000_P_SYNC_3_ 3 -1 4 1 6 -1 -1 1 0 21
|
|
337 CLK_000_P_SYNC_2_ 3 -1 6 1 4 -1 -1 1 0 21
|
|
336 CLK_000_P_SYNC_1_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
335 CLK_000_P_SYNC_0_ 3 -1 4 1 1 -1 -1 1 0 21
|
|
326 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
325 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
324 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
323 CLK_000_N_SYNC_11_ 3 -1 7 1 6 -1 -1 1 0 21
|
|
321 CLK_000_P_SYNC_9_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
315 inst_DTACK_D0 3 -1 1 1 5 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 6 66 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 3 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
59 A1 1 -1 -1 1 1 59 -1
|
|
35 VPA 1 -1 -1 1 5 35 -1
|
|
29 DTACK 1 -1 -1 1 1 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 0 13 -1
|
|
10 CLK_000 1 -1 -1 1 1 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
131 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
41 AS_000 5 -1 4 4 0 1 4 7 41 -1 1 0 21
|
|
79 RW_000 5 354 7 3 0 4 6 79 -1 3 0 21
|
|
40 BERR 5 -1 4 3 2 5 7 40 -1 1 0 21
|
|
68 A0 5 355 6 2 1 3 68 -1 3 0 21
|
|
70 RW 5 360 6 2 2 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 353 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 362 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 361 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 358 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 357 7 0 82 -1 3 0 21
|
|
34 VMA 5 359 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 356 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
357 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
301 inst_nEXP_SPACE_D0reg 3 -1 1 7 0 2 3 4 5 6 7 -1 -1 1 0 21
|
|
315 inst_RESET_OUT 3 -1 1 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
320 inst_CLK_000_PE 3 -1 0 6 0 1 2 3 5 7 -1 -1 1 0 21
|
|
322 inst_CLK_000_NE 3 -1 3 5 1 2 3 5 6 -1 -1 1 0 21
|
|
350 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 14 0 21
|
|
345 SM_AMIGA_6_ 3 -1 5 4 1 2 3 5 -1 -1 3 0 21
|
|
318 CLK_000_D_0_ 3 -1 0 4 0 3 4 5 -1 -1 1 0 21
|
|
300 inst_AS_030_D0 3 -1 7 4 2 3 4 7 -1 -1 1 0 21
|
|
294 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 4 0 21
|
|
347 SM_AMIGA_1_ 3 -1 5 3 2 5 7 -1 -1 3 0 21
|
|
309 SIZE_DMA_1_ 3 -1 0 3 0 6 7 -1 -1 3 0 21
|
|
298 SM_AMIGA_5_ 3 -1 2 3 2 5 7 -1 -1 3 0 21
|
|
295 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
293 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
326 SM_AMIGA_0_ 3 -1 2 3 2 5 7 -1 -1 2 0 21
|
|
317 CLK_000_D_1_ 3 -1 4 3 0 4 5 -1 -1 1 0 21
|
|
313 inst_CLK_OUT_PRE_D 3 -1 3 3 1 6 7 -1 -1 1 0 21
|
|
303 inst_BGACK_030_INT_D 3 -1 7 3 0 2 6 -1 -1 1 0 21
|
|
304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
302 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21
|
|
329 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21
|
|
331 RST_DLY_1_ 3 -1 6 2 1 6 -1 -1 4 0 21
|
|
359 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
330 RST_DLY_0_ 3 -1 1 2 1 6 -1 -1 3 0 21
|
|
328 SM_AMIGA_4_ 3 -1 2 2 2 5 -1 -1 3 0 21
|
|
312 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21
|
|
308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
332 RST_DLY_2_ 3 -1 1 2 1 6 -1 -1 2 0 21
|
|
327 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 2 0 3 -1 -1 2 0 21
|
|
306 CYCLE_DMA_0_ 3 -1 1 2 0 1 -1 -1 2 0 21
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21
|
|
297 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
|
|
296 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 2 0 21
|
|
342 CLK_000_N_SYNC_9_ 3 -1 5 2 6 7 -1 -1 1 0 21
|
|
321 inst_CLK_000_NE_D0 3 -1 1 2 3 5 -1 -1 1 0 21
|
|
316 inst_CLK_OUT_PRE_50 3 -1 6 2 3 6 -1 -1 1 0 21
|
|
310 inst_VPA_D 3 -1 1 2 3 5 -1 -1 1 0 21
|
|
362 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
361 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
353 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
346 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
348 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21
|
|
358 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
351 N_232 3 -1 5 1 5 -1 -1 4 0 21
|
|
349 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
355 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
354 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
360 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
356 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
352 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
311 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21
|
|
344 CLK_000_N_SYNC_11_ 3 -1 7 1 3 -1 -1 1 0 21
|
|
343 CLK_000_N_SYNC_10_ 3 -1 6 1 7 -1 -1 1 0 21
|
|
341 CLK_000_N_SYNC_8_ 3 -1 2 1 5 -1 -1 1 0 21
|
|
340 CLK_000_N_SYNC_7_ 3 -1 0 1 2 -1 -1 1 0 21
|
|
339 CLK_000_N_SYNC_6_ 3 -1 7 1 0 -1 -1 1 0 21
|
|
338 CLK_000_N_SYNC_5_ 3 -1 4 1 7 -1 -1 1 0 21
|
|
337 CLK_000_N_SYNC_4_ 3 -1 2 1 4 -1 -1 1 0 21
|
|
336 CLK_000_N_SYNC_3_ 3 -1 0 1 2 -1 -1 1 0 21
|
|
335 CLK_000_N_SYNC_2_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
334 CLK_000_N_SYNC_1_ 3 -1 0 1 6 -1 -1 1 0 21
|
|
333 CLK_000_N_SYNC_0_ 3 -1 4 1 0 -1 -1 1 0 21
|
|
325 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
324 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
323 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
319 CLK_000_D_2_ 3 -1 4 1 0 -1 -1 1 0 21
|
|
314 inst_DTACK_D0 3 -1 6 1 5 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
67 IPL_2_ 1 -1 -1 2 1 3 67 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
59 A1 1 -1 -1 2 0 6 59 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 6 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
|
35 VPA 1 -1 -1 1 1 35 -1
|
|
29 DTACK 1 -1 -1 1 6 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 1 13 -1
|
|
10 CLK_000 1 -1 -1 1 0 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
130 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 5 0 1 2 5 7 40 -1 1 0 21
|
|
79 RW_000 5 353 7 3 0 4 6 79 -1 3 0 21
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
70 RW 5 359 6 2 1 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
68 A0 5 354 6 1 6 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 6 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 6 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 352 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 361 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 360 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 357 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 356 7 0 82 -1 3 0 21
|
|
34 VMA 5 358 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 355 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
356 RN_BGACK_030 3 82 7 7 0 2 3 4 5 6 7 82 -1 3 0 21
|
|
302 inst_nEXP_SPACE_D0reg 3 -1 5 7 0 2 3 4 5 6 7 -1 -1 1 0 21
|
|
316 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
320 inst_CLK_000_PE 3 -1 5 6 0 1 2 3 5 7 -1 -1 1 0 21
|
|
322 inst_CLK_000_NE 3 -1 0 5 0 1 2 3 5 -1 -1 1 0 21
|
|
301 inst_AS_030_D0 3 -1 7 5 1 3 4 5 7 -1 -1 1 0 21
|
|
350 SM_AMIGA_i_7_ 3 -1 2 4 1 3 5 7 -1 -1 15 0 21
|
|
347 SM_AMIGA_1_ 3 -1 1 4 0 1 2 7 -1 -1 3 0 21
|
|
345 SM_AMIGA_6_ 3 -1 5 4 1 2 5 6 -1 -1 3 0 21
|
|
299 SM_AMIGA_5_ 3 -1 5 4 1 2 5 7 -1 -1 3 0 21
|
|
326 SM_AMIGA_0_ 3 -1 0 4 0 1 2 7 -1 -1 2 0 21
|
|
294 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 4 0 21
|
|
309 SIZE_DMA_0_ 3 -1 0 3 0 6 7 -1 -1 3 0 21
|
|
297 cpu_est_1_ 3 -1 2 3 2 3 6 -1 -1 3 0 21
|
|
295 cpu_est_3_ 3 -1 2 3 2 3 6 -1 -1 3 0 21
|
|
319 CLK_000_D_0_ 3 -1 0 3 2 3 5 -1 -1 1 0 21
|
|
314 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
|
304 inst_BGACK_030_INT_D 3 -1 7 3 0 5 6 -1 -1 1 0 21
|
|
305 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
303 inst_AS_030_000_SYNC 3 -1 5 2 2 5 -1 -1 7 0 21
|
|
329 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 5 0 21
|
|
349 SM_AMIGA_2_ 3 -1 2 2 1 2 -1 -1 4 0 21
|
|
358 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21
|
|
328 SM_AMIGA_4_ 3 -1 1 2 1 2 -1 -1 3 0 21
|
|
313 inst_LDS_000_INT 3 -1 6 2 3 6 -1 -1 3 0 21
|
|
310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
327 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 2 3 5 -1 -1 2 0 21
|
|
312 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21
|
|
296 cpu_est_0_ 3 -1 2 2 2 3 -1 -1 2 0 21
|
|
318 CLK_000_D_1_ 3 -1 5 2 2 5 -1 -1 1 0 21
|
|
311 inst_VPA_D 3 -1 6 2 2 3 -1 -1 1 0 21
|
|
361 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
360 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
352 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
306 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
346 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
348 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21
|
|
357 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
331 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21
|
|
354 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
353 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
330 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21
|
|
308 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
359 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
355 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
351 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
332 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21
|
|
307 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
344 CLK_000_N_SYNC_11_ 3 -1 7 1 0 -1 -1 1 0 21
|
|
343 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
342 CLK_000_N_SYNC_9_ 3 -1 1 1 7 -1 -1 1 0 21
|
|
341 CLK_000_N_SYNC_8_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
340 CLK_000_N_SYNC_7_ 3 -1 1 1 5 -1 -1 1 0 21
|
|
339 CLK_000_N_SYNC_6_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
338 CLK_000_N_SYNC_5_ 3 -1 5 1 6 -1 -1 1 0 21
|
|
337 CLK_000_N_SYNC_4_ 3 -1 4 1 5 -1 -1 1 0 21
|
|
336 CLK_000_N_SYNC_3_ 3 -1 3 1 4 -1 -1 1 0 21
|
|
335 CLK_000_N_SYNC_2_ 3 -1 3 1 3 -1 -1 1 0 21
|
|
334 CLK_000_N_SYNC_1_ 3 -1 6 1 3 -1 -1 1 0 21
|
|
333 CLK_000_N_SYNC_0_ 3 -1 2 1 6 -1 -1 1 0 21
|
|
325 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
324 IPL_D0_1_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
323 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
321 inst_CLK_000_NE_D0 3 -1 5 1 2 -1 -1 1 0 21
|
|
317 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
315 inst_DTACK_D0 3 -1 6 1 2 -1 -1 1 0 21
|
|
293 N_348_i 3 -1 2 1 2 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 4 5 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 4 5 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 4 5 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 4 5 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 4 5 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 4 5 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
59 A1 1 -1 -1 2 0 5 59 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 2 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
10 CLK_000 1 -1 -1 2 0 5 10 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
|
35 VPA 1 -1 -1 1 6 35 -1
|
|
29 DTACK 1 -1 -1 1 6 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 5 13 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
130 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 5 0 2 3 5 7 40 -1 1 0 21
|
|
41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21
|
|
79 RW_000 5 353 7 3 2 4 6 79 -1 5 0 21
|
|
70 RW 5 359 6 2 0 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 2 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 2 6 30 -1 1 0 21
|
|
68 A0 5 354 6 1 1 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 352 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 361 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 360 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 357 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 356 7 0 82 -1 3 0 21
|
|
34 VMA 5 358 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 355 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
356 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 3 0 21
|
|
316 inst_RESET_OUT 3 -1 1 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
302 inst_nEXP_SPACE_D0reg 3 -1 3 6 0 3 4 5 6 7 -1 -1 1 0 21
|
|
318 CLK_000_D_1_ 3 -1 7 5 0 2 3 5 7 -1 -1 1 0 21
|
|
317 CLK_000_D_0_ 3 -1 7 5 0 2 3 5 7 -1 -1 1 0 21
|
|
301 inst_AS_030_D0 3 -1 7 5 0 2 3 4 7 -1 -1 1 0 21
|
|
344 SM_AMIGA_6_ 3 -1 3 4 0 1 3 5 -1 -1 3 1 21
|
|
299 SM_AMIGA_5_ 3 -1 5 4 0 2 5 7 -1 -1 3 0 21
|
|
303 inst_AS_030_000_SYNC 3 -1 0 3 0 3 5 -1 -1 7 0 21
|
|
323 SM_AMIGA_0_ 3 -1 5 3 0 5 7 -1 -1 4 0 21
|
|
297 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
|
296 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
294 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
349 SM_AMIGA_i_7_ 3 -1 5 3 0 3 7 -1 -1 2 0 21
|
|
326 CLK_000_N_SYNC_12_ 3 -1 5 3 1 3 5 -1 -1 1 0 21
|
|
314 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
|
306 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21
|
|
305 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21
|
|
325 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 5 0 21
|
|
358 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
346 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
342 SM_AMIGA_4_ 3 -1 5 2 0 5 -1 -1 3 1 21
|
|
313 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21
|
|
310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
324 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
312 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
|
|
295 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21
|
|
343 inst_CLK_000_NE_D0 3 -1 3 2 3 5 -1 -1 1 0 21
|
|
340 CLK_000_N_SYNC_10_ 3 -1 7 2 1 7 -1 -1 1 0 21
|
|
311 inst_VPA_D 3 -1 2 2 3 5 -1 -1 1 0 21
|
|
304 inst_BGACK_030_INT_D 3 -1 7 2 0 6 -1 -1 1 0 21
|
|
351 SM_AMIGA_i_7__0 3 -1 5 1 5 -1 -1 15 0 21
|
|
361 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
360 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
352 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
345 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21
|
|
353 RN_RW_000 3 79 7 1 7 79 -1 5 0 21
|
|
348 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 5 0 21
|
|
347 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21
|
|
357 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
328 RST_DLY_1_ 3 -1 1 1 1 -1 -1 4 0 21
|
|
307 CYCLE_DMA_0_ 3 -1 2 1 2 -1 -1 4 0 21
|
|
293 N_230_i 3 -1 5 1 5 -1 -1 4 0 21
|
|
354 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
327 RST_DLY_0_ 3 -1 1 1 1 -1 -1 3 0 21
|
|
359 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
355 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
350 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
329 RST_DLY_2_ 3 -1 1 1 1 -1 -1 2 0 21
|
|
341 CLK_000_N_SYNC_11_ 3 -1 1 1 5 -1 -1 1 0 21
|
|
339 CLK_000_N_SYNC_9_ 3 -1 6 1 7 -1 -1 1 0 21
|
|
338 CLK_000_N_SYNC_8_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
337 CLK_000_N_SYNC_7_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
336 CLK_000_N_SYNC_6_ 3 -1 2 1 6 -1 -1 1 0 21
|
|
335 CLK_000_N_SYNC_5_ 3 -1 6 1 2 -1 -1 1 0 21
|
|
334 CLK_000_N_SYNC_4_ 3 -1 2 1 6 -1 -1 1 0 21
|
|
333 CLK_000_N_SYNC_3_ 3 -1 5 1 2 -1 -1 1 0 21
|
|
332 CLK_000_N_SYNC_2_ 3 -1 2 1 5 -1 -1 1 0 21
|
|
331 CLK_000_N_SYNC_1_ 3 -1 4 1 2 -1 -1 1 0 21
|
|
330 CLK_000_N_SYNC_0_ 3 -1 3 1 4 -1 -1 1 0 21
|
|
322 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
321 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
320 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
319 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
315 inst_DTACK_D0 3 -1 2 1 5 -1 -1 1 0 21
|
|
308 CYCLE_DMA_1_ 3 -1 2 1 2 -1 -1 1 1 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
10 CLK_000 1 -1 -1 5 0 2 3 5 7 10 -1
|
|
96 A_19_ 1 -1 -1 3 0 4 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 0 4 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 0 4 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 0 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 0 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 0 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 6 66 -1
|
|
63 CLK_030 1 -1 -1 2 2 7 63 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
59 A1 1 -1 -1 1 6 59 -1
|
|
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
|
35 VPA 1 -1 -1 1 2 35 -1
|
|
29 DTACK 1 -1 -1 1 2 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 3 13 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
140 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21
|
|
79 RW_000 5 365 7 3 0 4 6 79 -1 3 0 21
|
|
40 BERR 5 -1 4 3 2 5 7 40 -1 1 0 21
|
|
70 RW 5 371 6 2 2 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
68 A0 5 366 6 1 0 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 362 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 364 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 363 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 369 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 368 7 0 82 -1 3 0 21
|
|
34 VMA 5 370 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 367 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
368 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
302 inst_nEXP_SPACE_D0reg 3 -1 0 7 0 2 3 4 5 6 7 -1 -1 1 0 21
|
|
316 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
320 CLK_000_P_SYNC_10_ 3 -1 6 5 1 2 3 5 7 -1 -1 1 0 21
|
|
360 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 14 0 21
|
|
301 inst_AS_030_D0 3 -1 7 4 2 3 4 7 -1 -1 1 0 21
|
|
294 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
|
355 SM_AMIGA_6_ 3 -1 5 3 0 2 5 -1 -1 3 0 21
|
|
299 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21
|
|
297 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
295 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
324 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 2 0 21
|
|
307 CYCLE_DMA_0_ 3 -1 1 3 0 1 2 -1 -1 2 0 21
|
|
319 CLK_000_D_0_ 3 -1 1 3 3 4 5 -1 -1 1 0 21
|
|
314 inst_CLK_OUT_PRE_D 3 -1 0 3 1 6 7 -1 -1 1 0 21
|
|
304 inst_BGACK_030_INT_D 3 -1 7 3 1 2 6 -1 -1 1 0 21
|
|
305 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
303 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21
|
|
327 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21
|
|
370 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
357 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
326 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21
|
|
313 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21
|
|
310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
308 CYCLE_DMA_1_ 3 -1 2 2 0 2 -1 -1 3 0 21
|
|
325 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
312 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21
|
|
300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
|
|
296 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21
|
|
354 inst_CLK_000_NE_D0 3 -1 3 2 3 5 -1 -1 1 0 21
|
|
328 CLK_000_N_SYNC_12_ 3 -1 6 2 3 5 -1 -1 1 0 21
|
|
318 CLK_000_D_1_ 3 -1 4 2 4 5 -1 -1 1 0 21
|
|
317 inst_CLK_OUT_PRE_50 3 -1 5 2 0 5 -1 -1 1 0 21
|
|
311 inst_VPA_D 3 -1 5 2 3 5 -1 -1 1 0 21
|
|
364 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
363 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
362 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
306 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
356 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
358 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21
|
|
369 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
359 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
330 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21
|
|
293 N_317_i 3 -1 5 1 5 -1 -1 4 0 21
|
|
366 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
365 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
329 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21
|
|
371 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
367 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
331 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21
|
|
353 CLK_000_N_SYNC_11_ 3 -1 7 1 6 -1 -1 1 0 21
|
|
352 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_9_ 3 -1 0 1 7 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_8_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_7_ 3 -1 5 1 0 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_6_ 3 -1 6 1 5 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_5_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_4_ 3 -1 1 1 3 -1 -1 1 0 21
|
|
345 CLK_000_N_SYNC_3_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
344 CLK_000_N_SYNC_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
343 CLK_000_N_SYNC_1_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
342 CLK_000_N_SYNC_0_ 3 -1 4 1 0 -1 -1 1 0 21
|
|
341 CLK_000_P_SYNC_9_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
340 CLK_000_P_SYNC_8_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
339 CLK_000_P_SYNC_7_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
338 CLK_000_P_SYNC_6_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
337 CLK_000_P_SYNC_5_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
336 CLK_000_P_SYNC_4_ 3 -1 4 1 6 -1 -1 1 0 21
|
|
335 CLK_000_P_SYNC_3_ 3 -1 6 1 4 -1 -1 1 0 21
|
|
334 CLK_000_P_SYNC_2_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
333 CLK_000_P_SYNC_1_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
332 CLK_000_P_SYNC_0_ 3 -1 4 1 6 -1 -1 1 0 21
|
|
323 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
322 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
321 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
315 inst_DTACK_D0 3 -1 1 1 5 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 6 66 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 3 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
59 A1 1 -1 -1 1 1 59 -1
|
|
35 VPA 1 -1 -1 1 5 35 -1
|
|
29 DTACK 1 -1 -1 1 1 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 0 13 -1
|
|
10 CLK_000 1 -1 -1 1 1 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
138 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
41 AS_000 5 -1 4 4 0 4 6 7 41 -1 1 0 21
|
|
40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21
|
|
79 RW_000 5 363 7 2 4 6 79 -1 3 0 21
|
|
70 RW 5 369 6 2 0 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
68 A0 5 364 6 1 1 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21
|
|
31 UDS_000 5 -1 3 1 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 1 6 30 -1 1 0 21
|
|
8 IPL_030_2_ 5 360 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 362 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 361 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 367 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 366 7 0 82 -1 3 0 21
|
|
34 VMA 5 368 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 365 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
366 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
302 inst_nEXP_SPACE_D0reg 3 -1 0 7 0 2 3 4 5 6 7 -1 -1 1 0 21
|
|
316 inst_RESET_OUT 3 -1 0 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
320 CLK_000_P_SYNC_10_ 3 -1 2 5 0 3 5 6 7 -1 -1 1 0 21
|
|
301 inst_AS_030_D0 3 -1 7 5 0 2 3 4 7 -1 -1 1 0 21
|
|
358 SM_AMIGA_i_7_ 3 -1 5 4 0 2 3 7 -1 -1 14 0 21
|
|
299 SM_AMIGA_5_ 3 -1 5 4 0 2 5 7 -1 -1 2 1 21
|
|
303 inst_AS_030_000_SYNC 3 -1 2 3 0 2 5 -1 -1 7 0 21
|
|
295 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 4 0 21
|
|
353 SM_AMIGA_6_ 3 -1 0 3 0 1 5 -1 -1 3 0 21
|
|
296 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
294 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
324 SM_AMIGA_0_ 3 -1 5 3 0 5 7 -1 -1 2 0 21
|
|
319 CLK_000_D_0_ 3 -1 3 3 0 3 5 -1 -1 1 0 21
|
|
318 CLK_000_D_1_ 3 -1 0 3 0 3 5 -1 -1 1 0 21
|
|
314 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
|
304 inst_BGACK_030_INT_D 3 -1 3 3 1 2 6 -1 -1 1 0 21
|
|
306 inst_DS_000_DMA 3 -1 6 2 0 6 -1 -1 9 0 21
|
|
305 inst_AS_000_DMA 3 -1 6 2 6 7 -1 -1 7 0 21
|
|
327 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 5 0 21
|
|
368 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
326 SM_AMIGA_4_ 3 -1 5 2 0 5 -1 -1 3 0 21
|
|
313 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21
|
|
310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
355 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 2 1 21
|
|
325 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
312 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
|
|
297 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21
|
|
328 inst_CLK_000_NE_D0 3 -1 3 2 3 5 -1 -1 1 0 21
|
|
311 inst_VPA_D 3 -1 1 2 3 5 -1 -1 1 0 21
|
|
362 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
361 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
360 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
354 inst_CLK_030_H 3 -1 6 1 6 -1 -1 8 0 21
|
|
356 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21
|
|
367 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
357 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
293 N_212_i 3 -1 5 1 5 -1 -1 4 0 21
|
|
364 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
363 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
351 RST_DLY_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
350 RST_DLY_0_ 3 -1 0 1 0 -1 -1 3 1 21
|
|
308 CYCLE_DMA_1_ 3 -1 6 1 6 -1 -1 3 0 21
|
|
369 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
365 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
359 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
352 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
307 CYCLE_DMA_0_ 3 -1 6 1 6 -1 -1 2 0 21
|
|
300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21
|
|
349 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_9_ 3 -1 5 1 7 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_8_ 3 -1 6 1 5 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_7_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
345 CLK_000_N_SYNC_6_ 3 -1 4 1 1 -1 -1 1 0 21
|
|
344 CLK_000_N_SYNC_5_ 3 -1 3 1 4 -1 -1 1 0 21
|
|
343 CLK_000_N_SYNC_4_ 3 -1 2 1 3 -1 -1 1 0 21
|
|
342 CLK_000_N_SYNC_3_ 3 -1 7 1 2 -1 -1 1 0 21
|
|
341 CLK_000_N_SYNC_2_ 3 -1 1 1 7 -1 -1 1 0 21
|
|
340 CLK_000_N_SYNC_1_ 3 -1 4 1 1 -1 -1 1 0 21
|
|
339 CLK_000_N_SYNC_0_ 3 -1 5 1 4 -1 -1 1 0 21
|
|
338 CLK_000_P_SYNC_9_ 3 -1 2 1 2 -1 -1 1 0 21
|
|
337 CLK_000_P_SYNC_8_ 3 -1 5 1 2 -1 -1 1 0 21
|
|
336 CLK_000_P_SYNC_7_ 3 -1 3 1 5 -1 -1 1 0 21
|
|
335 CLK_000_P_SYNC_6_ 3 -1 6 1 3 -1 -1 1 0 21
|
|
334 CLK_000_P_SYNC_5_ 3 -1 0 1 6 -1 -1 1 0 21
|
|
333 CLK_000_P_SYNC_4_ 3 -1 2 1 0 -1 -1 1 0 21
|
|
332 CLK_000_P_SYNC_3_ 3 -1 3 1 2 -1 -1 1 0 21
|
|
331 CLK_000_P_SYNC_2_ 3 -1 2 1 3 -1 -1 1 0 21
|
|
330 CLK_000_P_SYNC_1_ 3 -1 0 1 2 -1 -1 1 0 21
|
|
329 CLK_000_P_SYNC_0_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
323 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
322 IPL_D0_1_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
321 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
317 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
315 inst_DTACK_D0 3 -1 1 1 5 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
10 CLK_000 1 -1 -1 3 0 3 5 10 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
63 CLK_030 1 -1 -1 2 6 7 63 -1
|
|
59 A1 1 -1 -1 2 1 2 59 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 2 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
|
35 VPA 1 -1 -1 1 1 35 -1
|
|
29 DTACK 1 -1 -1 1 1 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 0 13 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
139 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
41 AS_000 5 -1 4 4 0 4 6 7 41 -1 1 0 21
|
|
40 BERR 5 -1 4 4 1 2 5 7 40 -1 1 0 21
|
|
79 RW_000 5 362 7 3 0 4 6 79 -1 3 0 21
|
|
70 RW 5 370 6 2 2 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
68 A0 5 365 6 1 1 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 361 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 364 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 363 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 368 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 367 7 0 82 -1 3 0 21
|
|
34 VMA 5 369 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 366 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
301 inst_nEXP_SPACE_D0reg 3 -1 6 7 0 2 3 4 5 6 7 -1 -1 1 0 21
|
|
367 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 3 0 21
|
|
315 inst_RESET_OUT 3 -1 0 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
319 CLK_000_P_SYNC_10_ 3 -1 0 6 0 2 3 5 6 7 -1 -1 1 0 21
|
|
300 inst_AS_030_D0 3 -1 7 5 1 2 3 4 7 -1 -1 1 0 21
|
|
358 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 13 0 21
|
|
298 SM_AMIGA_5_ 3 -1 5 4 1 2 5 7 -1 -1 2 1 21
|
|
293 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 4 0 21
|
|
353 SM_AMIGA_6_ 3 -1 5 3 1 2 5 -1 -1 3 0 21
|
|
296 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
294 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
324 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 2 0 21
|
|
323 CLK_000_D_2_ 3 -1 5 3 0 3 5 -1 -1 1 0 21
|
|
318 CLK_000_D_1_ 3 -1 3 3 0 3 5 -1 -1 1 0 21
|
|
316 CLK_000_D_0_ 3 -1 3 3 0 3 5 -1 -1 1 0 21
|
|
313 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
|
304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
302 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21
|
|
327 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21
|
|
369 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
312 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21
|
|
309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
355 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 2 1 21
|
|
326 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 2 0 21
|
|
325 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
311 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
306 CYCLE_DMA_0_ 3 -1 6 2 0 6 -1 -1 2 0 21
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21
|
|
297 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21
|
|
295 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21
|
|
349 inst_CLK_000_NE_D0 3 -1 5 2 3 5 -1 -1 1 0 21
|
|
310 inst_VPA_D 3 -1 1 2 3 5 -1 -1 1 0 21
|
|
303 inst_BGACK_030_INT_D 3 -1 2 2 2 6 -1 -1 1 0 21
|
|
364 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
363 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
361 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
354 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
359 N_160_i_3 3 -1 5 1 5 -1 -1 6 0 21
|
|
356 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21
|
|
368 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
357 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
365 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
362 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
351 RST_DLY_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
350 RST_DLY_0_ 3 -1 0 1 0 -1 -1 3 1 21
|
|
307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
370 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
366 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
360 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
352 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
348 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_9_ 3 -1 0 1 7 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_8_ 3 -1 3 1 0 -1 -1 1 0 21
|
|
345 CLK_000_N_SYNC_7_ 3 -1 3 1 3 -1 -1 1 0 21
|
|
344 CLK_000_N_SYNC_6_ 3 -1 1 1 3 -1 -1 1 0 21
|
|
343 CLK_000_N_SYNC_5_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
342 CLK_000_N_SYNC_4_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
341 CLK_000_N_SYNC_3_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
340 CLK_000_N_SYNC_2_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
339 CLK_000_N_SYNC_1_ 3 -1 6 1 5 -1 -1 1 0 21
|
|
338 CLK_000_N_SYNC_0_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
337 CLK_000_P_SYNC_9_ 3 -1 3 1 0 -1 -1 1 0 21
|
|
336 CLK_000_P_SYNC_8_ 3 -1 7 1 3 -1 -1 1 0 21
|
|
335 CLK_000_P_SYNC_7_ 3 -1 1 1 7 -1 -1 1 0 21
|
|
334 CLK_000_P_SYNC_6_ 3 -1 4 1 1 -1 -1 1 0 21
|
|
333 CLK_000_P_SYNC_5_ 3 -1 4 1 4 -1 -1 1 0 21
|
|
332 CLK_000_P_SYNC_4_ 3 -1 0 1 4 -1 -1 1 0 21
|
|
331 CLK_000_P_SYNC_3_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
330 CLK_000_P_SYNC_2_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
329 CLK_000_P_SYNC_1_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
328 CLK_000_P_SYNC_0_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
322 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
321 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
320 IPL_D0_0_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
317 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
314 inst_DTACK_D0 3 -1 6 1 5 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
67 IPL_2_ 1 -1 -1 2 1 6 67 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 5 66 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
59 A1 1 -1 -1 1 6 59 -1
|
|
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
|
35 VPA 1 -1 -1 1 1 35 -1
|
|
29 DTACK 1 -1 -1 1 6 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 6 13 -1
|
|
10 CLK_000 1 -1 -1 1 3 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
131 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 5 0 1 2 5 7 40 -1 1 0 21
|
|
41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21
|
|
79 RW_000 5 354 7 3 2 4 6 79 -1 5 0 21
|
|
81 AS_030 5 -1 7 3 3 4 7 81 -1 1 0 21
|
|
70 RW 5 360 6 2 0 7 70 -1 2 0 21
|
|
31 UDS_000 5 -1 3 2 2 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 2 6 30 -1 1 0 21
|
|
68 A0 5 355 6 1 6 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 6 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 6 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 353 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 362 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 361 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 358 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 357 7 0 82 -1 3 0 21
|
|
34 VMA 5 359 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 356 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
301 inst_nEXP_SPACE_D0reg 3 -1 6 7 0 2 3 4 5 6 7 -1 -1 1 0 21
|
|
357 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 3 0 21
|
|
315 inst_RESET_OUT 3 -1 1 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
319 CLK_000_D_0_ 3 -1 1 5 0 2 3 5 7 -1 -1 1 0 21
|
|
317 CLK_000_D_2_ 3 -1 2 5 0 2 3 5 7 -1 -1 1 0 21
|
|
316 CLK_000_D_1_ 3 -1 7 5 0 2 3 5 7 -1 -1 1 0 21
|
|
300 inst_AS_030_D0 3 -1 3 5 0 1 3 4 7 -1 -1 1 0 21
|
|
345 SM_AMIGA_6_ 3 -1 2 4 0 2 5 6 -1 -1 4 0 21
|
|
324 SM_AMIGA_0_ 3 -1 5 4 0 1 5 7 -1 -1 4 0 21
|
|
350 SM_AMIGA_i_7_ 3 -1 1 4 0 2 3 7 -1 -1 2 0 21
|
|
298 SM_AMIGA_5_ 3 -1 5 4 0 1 5 7 -1 -1 2 0 21
|
|
302 inst_AS_030_000_SYNC 3 -1 0 3 0 2 5 -1 -1 7 0 21
|
|
293 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
|
296 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
294 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
295 cpu_est_0_ 3 -1 2 3 2 3 5 -1 -1 2 0 21
|
|
343 inst_CLK_000_NE_D0 3 -1 5 3 2 3 5 -1 -1 1 0 21
|
|
327 CLK_000_N_SYNC_12_ 3 -1 6 3 1 3 5 -1 -1 1 0 21
|
|
313 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
|
303 inst_BGACK_030_INT_D 3 -1 7 3 0 2 6 -1 -1 1 0 21
|
|
305 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21
|
|
304 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21
|
|
326 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 5 0 21
|
|
344 SM_AMIGA_4_ 3 -1 5 2 0 5 -1 -1 4 0 21
|
|
322 N_202_i 3 -1 5 2 1 5 -1 -1 4 0 21
|
|
359 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
312 inst_LDS_000_INT 3 -1 6 2 3 6 -1 -1 3 0 21
|
|
309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
347 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 2 0 21
|
|
325 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
311 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
297 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21
|
|
310 inst_VPA_D 3 -1 3 2 3 5 -1 -1 1 0 21
|
|
352 SM_AMIGA_i_7__0 3 -1 5 1 1 -1 -1 15 0 21
|
|
362 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
361 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
353 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
348 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 8 0 21
|
|
346 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21
|
|
354 RN_RW_000 3 79 7 1 7 79 -1 5 0 21
|
|
358 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
329 RST_DLY_1_ 3 -1 1 1 1 -1 -1 4 0 21
|
|
306 CYCLE_DMA_0_ 3 -1 2 1 2 -1 -1 4 0 21
|
|
355 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
349 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 3 1 21
|
|
328 RST_DLY_0_ 3 -1 1 1 1 -1 -1 3 0 21
|
|
360 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
356 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
351 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
330 RST_DLY_2_ 3 -1 1 1 1 -1 -1 2 0 21
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21
|
|
342 CLK_000_N_SYNC_11_ 3 -1 7 1 6 -1 -1 1 0 21
|
|
341 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
340 CLK_000_N_SYNC_9_ 3 -1 1 1 7 -1 -1 1 0 21
|
|
339 CLK_000_N_SYNC_8_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
338 CLK_000_N_SYNC_7_ 3 -1 1 1 2 -1 -1 1 0 21
|
|
337 CLK_000_N_SYNC_6_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
336 CLK_000_N_SYNC_5_ 3 -1 2 1 3 -1 -1 1 0 21
|
|
335 CLK_000_N_SYNC_4_ 3 -1 5 1 2 -1 -1 1 0 21
|
|
334 CLK_000_N_SYNC_3_ 3 -1 6 1 5 -1 -1 1 0 21
|
|
333 CLK_000_N_SYNC_2_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
332 CLK_000_N_SYNC_1_ 3 -1 4 1 3 -1 -1 1 0 21
|
|
331 CLK_000_N_SYNC_0_ 3 -1 7 1 4 -1 -1 1 0 21
|
|
323 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
321 IPL_D0_1_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
320 IPL_D0_0_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
318 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
314 inst_DTACK_D0 3 -1 3 1 5 -1 -1 1 0 21
|
|
307 CYCLE_DMA_1_ 3 -1 2 1 2 -1 -1 1 1 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 0 4 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 0 4 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 0 4 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 0 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 0 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 0 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
67 IPL_2_ 1 -1 -1 2 1 6 67 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 5 66 -1
|
|
63 CLK_030 1 -1 -1 2 2 7 63 -1
|
|
59 A1 1 -1 -1 2 2 6 59 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 5 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
35 VPA 1 -1 -1 1 3 35 -1
|
|
29 DTACK 1 -1 -1 1 3 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 6 13 -1
|
|
10 CLK_000 1 -1 -1 1 1 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
130 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 5 0 2 3 5 7 40 -1 1 0 21
|
|
41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21
|
|
79 RW_000 5 353 7 3 2 4 6 79 -1 5 0 21
|
|
70 RW 5 359 6 2 0 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 2 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 2 6 30 -1 1 0 21
|
|
68 A0 5 354 6 1 1 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 352 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 361 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 360 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 357 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 356 7 0 82 -1 3 0 21
|
|
34 VMA 5 358 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 355 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
356 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 3 0 21
|
|
316 inst_RESET_OUT 3 -1 1 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
302 inst_nEXP_SPACE_D0reg 3 -1 3 6 0 3 4 5 6 7 -1 -1 1 0 21
|
|
318 CLK_000_D_1_ 3 -1 7 5 0 2 3 5 7 -1 -1 1 0 21
|
|
317 CLK_000_D_0_ 3 -1 7 5 0 2 3 5 7 -1 -1 1 0 21
|
|
301 inst_AS_030_D0 3 -1 7 5 0 2 3 4 7 -1 -1 1 0 21
|
|
344 SM_AMIGA_6_ 3 -1 3 4 0 1 3 5 -1 -1 3 1 21
|
|
299 SM_AMIGA_5_ 3 -1 5 4 0 2 5 7 -1 -1 3 0 21
|
|
303 inst_AS_030_000_SYNC 3 -1 0 3 0 3 5 -1 -1 7 0 21
|
|
323 SM_AMIGA_0_ 3 -1 5 3 0 5 7 -1 -1 4 0 21
|
|
297 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
|
296 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
294 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
349 SM_AMIGA_i_7_ 3 -1 5 3 0 3 7 -1 -1 2 0 21
|
|
326 CLK_000_N_SYNC_12_ 3 -1 5 3 1 3 5 -1 -1 1 0 21
|
|
314 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
|
306 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21
|
|
305 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21
|
|
325 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 5 0 21
|
|
358 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
346 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
342 SM_AMIGA_4_ 3 -1 5 2 0 5 -1 -1 3 1 21
|
|
313 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21
|
|
310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
324 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
312 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
|
|
295 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21
|
|
343 inst_CLK_000_NE_D0 3 -1 3 2 3 5 -1 -1 1 0 21
|
|
340 CLK_000_N_SYNC_10_ 3 -1 7 2 1 7 -1 -1 1 0 21
|
|
311 inst_VPA_D 3 -1 2 2 3 5 -1 -1 1 0 21
|
|
304 inst_BGACK_030_INT_D 3 -1 7 2 0 6 -1 -1 1 0 21
|
|
351 SM_AMIGA_i_7__0 3 -1 5 1 5 -1 -1 15 0 21
|
|
361 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
360 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
352 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
345 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21
|
|
353 RN_RW_000 3 79 7 1 7 79 -1 5 0 21
|
|
348 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 5 0 21
|
|
347 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21
|
|
357 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
328 RST_DLY_1_ 3 -1 1 1 1 -1 -1 4 0 21
|
|
307 CYCLE_DMA_0_ 3 -1 2 1 2 -1 -1 4 0 21
|
|
293 N_230_i 3 -1 5 1 5 -1 -1 4 0 21
|
|
354 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
327 RST_DLY_0_ 3 -1 1 1 1 -1 -1 3 0 21
|
|
359 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
355 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
350 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
329 RST_DLY_2_ 3 -1 1 1 1 -1 -1 2 0 21
|
|
341 CLK_000_N_SYNC_11_ 3 -1 1 1 5 -1 -1 1 0 21
|
|
339 CLK_000_N_SYNC_9_ 3 -1 6 1 7 -1 -1 1 0 21
|
|
338 CLK_000_N_SYNC_8_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
337 CLK_000_N_SYNC_7_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
336 CLK_000_N_SYNC_6_ 3 -1 2 1 6 -1 -1 1 0 21
|
|
335 CLK_000_N_SYNC_5_ 3 -1 6 1 2 -1 -1 1 0 21
|
|
334 CLK_000_N_SYNC_4_ 3 -1 2 1 6 -1 -1 1 0 21
|
|
333 CLK_000_N_SYNC_3_ 3 -1 5 1 2 -1 -1 1 0 21
|
|
332 CLK_000_N_SYNC_2_ 3 -1 2 1 5 -1 -1 1 0 21
|
|
331 CLK_000_N_SYNC_1_ 3 -1 4 1 2 -1 -1 1 0 21
|
|
330 CLK_000_N_SYNC_0_ 3 -1 3 1 4 -1 -1 1 0 21
|
|
322 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
321 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
320 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
319 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
315 inst_DTACK_D0 3 -1 2 1 5 -1 -1 1 0 21
|
|
308 CYCLE_DMA_1_ 3 -1 2 1 2 -1 -1 1 1 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
10 CLK_000 1 -1 -1 5 0 2 3 5 7 10 -1
|
|
96 A_19_ 1 -1 -1 3 0 4 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 0 4 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 0 4 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 0 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 0 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 0 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 6 66 -1
|
|
63 CLK_030 1 -1 -1 2 2 7 63 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
59 A1 1 -1 -1 1 6 59 -1
|
|
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
|
35 VPA 1 -1 -1 1 2 35 -1
|
|
29 DTACK 1 -1 -1 1 2 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 3 13 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
129 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 5 0 1 2 5 7 40 -1 1 0 21
|
|
41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21
|
|
79 RW_000 5 352 7 3 2 4 6 79 -1 5 0 21
|
|
70 RW 5 358 6 2 0 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 2 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 2 6 30 -1 1 0 21
|
|
68 A0 5 353 6 1 1 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 351 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 360 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 359 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 356 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 355 7 0 82 -1 3 0 21
|
|
34 VMA 5 357 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 354 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
355 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 3 0 21
|
|
316 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
348 CLK_000_D_0_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21
|
|
302 inst_nEXP_SPACE_D0reg 3 -1 1 6 0 3 4 5 6 7 -1 -1 1 0 21
|
|
317 CLK_000_D_1_ 3 -1 6 5 0 2 3 5 7 -1 -1 1 0 21
|
|
301 inst_AS_030_D0 3 -1 7 5 0 1 3 4 7 -1 -1 1 0 21
|
|
299 SM_AMIGA_5_ 3 -1 5 4 0 1 5 7 -1 -1 3 0 21
|
|
347 SM_AMIGA_i_7_ 3 -1 2 4 0 3 5 7 -1 -1 2 0 21
|
|
322 SM_AMIGA_0_ 3 -1 5 3 0 5 7 -1 -1 4 0 21
|
|
297 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
|
342 SM_AMIGA_6_ 3 -1 5 3 0 1 5 -1 -1 3 1 21
|
|
296 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
294 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
325 CLK_000_N_SYNC_11_ 3 -1 7 3 3 4 5 -1 -1 1 0 21
|
|
314 inst_CLK_OUT_PRE_D 3 -1 1 3 1 6 7 -1 -1 1 0 21
|
|
304 inst_BGACK_030_INT_D 3 -1 7 3 0 2 6 -1 -1 1 0 21
|
|
306 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21
|
|
305 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21
|
|
303 inst_AS_030_000_SYNC 3 -1 0 2 0 5 -1 -1 7 0 21
|
|
324 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 5 0 21
|
|
293 N_225_i 3 -1 5 2 2 5 -1 -1 4 0 21
|
|
357 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
344 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
340 SM_AMIGA_4_ 3 -1 5 2 0 5 -1 -1 3 1 21
|
|
313 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21
|
|
310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
323 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
312 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21
|
|
295 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 2 0 21
|
|
341 inst_CLK_000_NE_D0 3 -1 4 2 3 5 -1 -1 1 0 21
|
|
338 CLK_000_N_SYNC_9_ 3 -1 6 2 6 7 -1 -1 1 0 21
|
|
318 inst_CLK_OUT_PRE_50 3 -1 4 2 1 4 -1 -1 1 0 21
|
|
311 inst_VPA_D 3 -1 2 2 3 5 -1 -1 1 0 21
|
|
350 SM_AMIGA_i_7__0 3 -1 5 1 2 -1 -1 15 0 21
|
|
360 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
359 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
351 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
343 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21
|
|
352 RN_RW_000 3 79 7 1 7 79 -1 5 0 21
|
|
346 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 5 0 21
|
|
345 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21
|
|
356 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
327 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21
|
|
307 CYCLE_DMA_0_ 3 -1 2 1 2 -1 -1 4 0 21
|
|
353 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
326 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21
|
|
358 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
354 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
349 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
328 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21
|
|
300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21
|
|
339 CLK_000_N_SYNC_10_ 3 -1 6 1 7 -1 -1 1 0 21
|
|
337 CLK_000_N_SYNC_8_ 3 -1 2 1 6 -1 -1 1 0 21
|
|
336 CLK_000_N_SYNC_7_ 3 -1 1 1 2 -1 -1 1 0 21
|
|
335 CLK_000_N_SYNC_6_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
334 CLK_000_N_SYNC_5_ 3 -1 1 1 2 -1 -1 1 0 21
|
|
333 CLK_000_N_SYNC_4_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
332 CLK_000_N_SYNC_3_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
331 CLK_000_N_SYNC_2_ 3 -1 4 1 3 -1 -1 1 0 21
|
|
330 CLK_000_N_SYNC_1_ 3 -1 1 1 4 -1 -1 1 0 21
|
|
329 CLK_000_N_SYNC_0_ 3 -1 7 1 1 -1 -1 1 0 21
|
|
321 IPL_D0_2_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
320 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
319 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
315 inst_DTACK_D0 3 -1 5 1 5 -1 -1 1 0 21
|
|
308 CYCLE_DMA_1_ 3 -1 2 1 2 -1 -1 1 1 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
10 CLK_000 1 -1 -1 5 0 2 3 5 7 10 -1
|
|
96 A_19_ 1 -1 -1 3 0 4 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 0 4 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 0 4 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 0 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 0 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 0 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
67 IPL_2_ 1 -1 -1 2 1 5 67 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 2 66 -1
|
|
63 CLK_030 1 -1 -1 2 2 7 63 -1
|
|
59 A1 1 -1 -1 2 2 6 59 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 6 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
35 VPA 1 -1 -1 1 2 35 -1
|
|
29 DTACK 1 -1 -1 1 5 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 1 13 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
138 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 4 2 5 6 7 40 -1 1 0 21
|
|
79 RW_000 5 363 7 3 0 4 6 79 -1 3 0 21
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
70 RW 5 369 6 2 2 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
68 A0 5 364 6 1 1 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 361 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 362 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 360 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 367 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 366 7 0 82 -1 3 0 21
|
|
34 VMA 5 368 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 365 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
302 inst_nEXP_SPACE_D0reg 3 -1 0 7 0 2 3 4 5 6 7 -1 -1 1 0 21
|
|
366 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 3 0 21
|
|
316 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
320 CLK_000_P_SYNC_9_ 3 -1 4 6 0 2 3 5 6 7 -1 -1 1 0 21
|
|
301 inst_AS_030_D0 3 -1 7 5 2 3 4 5 7 -1 -1 1 0 21
|
|
358 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 14 0 21
|
|
324 SM_AMIGA_0_ 3 -1 6 4 2 5 6 7 -1 -1 2 0 21
|
|
294 cpu_est_2_ 3 -1 6 3 3 5 6 -1 -1 4 0 21
|
|
355 SM_AMIGA_1_ 3 -1 5 3 5 6 7 -1 -1 3 0 21
|
|
353 SM_AMIGA_6_ 3 -1 5 3 1 2 5 -1 -1 3 0 21
|
|
299 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21
|
|
297 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
295 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
296 cpu_est_0_ 3 -1 5 3 3 5 6 -1 -1 2 0 21
|
|
352 inst_CLK_000_NE_D0 3 -1 6 3 3 5 6 -1 -1 1 0 21
|
|
328 CLK_000_N_SYNC_11_ 3 -1 7 3 3 5 6 -1 -1 1 0 21
|
|
319 CLK_000_D_0_ 3 -1 1 3 1 3 5 -1 -1 1 0 21
|
|
314 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
|
304 inst_BGACK_030_INT_D 3 -1 7 3 0 2 6 -1 -1 1 0 21
|
|
305 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
303 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21
|
|
327 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21
|
|
368 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
326 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21
|
|
313 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21
|
|
310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
325 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 2 0 3 -1 -1 2 0 21
|
|
312 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21
|
|
350 CLK_000_N_SYNC_9_ 3 -1 1 2 6 7 -1 -1 1 0 21
|
|
318 CLK_000_D_1_ 3 -1 5 2 1 5 -1 -1 1 0 21
|
|
311 inst_VPA_D 3 -1 3 2 3 5 -1 -1 1 0 21
|
|
362 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
361 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
360 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
306 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
354 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
356 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21
|
|
367 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
357 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
330 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21
|
|
293 N_317_i 3 -1 5 1 5 -1 -1 4 0 21
|
|
364 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
363 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
329 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21
|
|
308 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
369 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
365 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
359 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
331 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21
|
|
307 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
351 CLK_000_N_SYNC_10_ 3 -1 6 1 7 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_8_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_7_ 3 -1 6 1 3 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_6_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_5_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
345 CLK_000_N_SYNC_4_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
344 CLK_000_N_SYNC_3_ 3 -1 7 1 1 -1 -1 1 0 21
|
|
343 CLK_000_N_SYNC_2_ 3 -1 0 1 7 -1 -1 1 0 21
|
|
342 CLK_000_N_SYNC_1_ 3 -1 4 1 0 -1 -1 1 0 21
|
|
341 CLK_000_N_SYNC_0_ 3 -1 5 1 4 -1 -1 1 0 21
|
|
340 CLK_000_P_SYNC_8_ 3 -1 3 1 4 -1 -1 1 0 21
|
|
339 CLK_000_P_SYNC_7_ 3 -1 2 1 3 -1 -1 1 0 21
|
|
338 CLK_000_P_SYNC_6_ 3 -1 1 1 2 -1 -1 1 0 21
|
|
337 CLK_000_P_SYNC_5_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
336 CLK_000_P_SYNC_4_ 3 -1 0 1 6 -1 -1 1 0 21
|
|
335 CLK_000_P_SYNC_3_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
334 CLK_000_P_SYNC_2_ 3 -1 0 1 6 -1 -1 1 0 21
|
|
333 CLK_000_P_SYNC_1_ 3 -1 1 1 0 -1 -1 1 0 21
|
|
332 CLK_000_P_SYNC_0_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
323 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
322 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
321 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
317 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
315 inst_DTACK_D0 3 -1 3 1 5 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
67 IPL_2_ 1 -1 -1 2 0 1 67 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 3 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
|
59 A1 1 -1 -1 1 0 59 -1
|
|
35 VPA 1 -1 -1 1 3 35 -1
|
|
29 DTACK 1 -1 -1 1 3 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 0 13 -1
|
|
10 CLK_000 1 -1 -1 1 1 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
139 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
79 RW_000 5 364 7 3 0 4 6 79 -1 3 0 21
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
40 BERR 5 -1 4 3 2 5 7 40 -1 1 0 21
|
|
70 RW 5 370 6 2 2 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
68 A0 5 365 6 1 1 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 361 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 363 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 362 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 368 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 367 7 0 82 -1 3 0 21
|
|
34 VMA 5 369 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 366 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
302 inst_nEXP_SPACE_D0reg 3 -1 6 7 0 2 3 4 5 6 7 -1 -1 1 0 21
|
|
367 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 3 0 21
|
|
316 inst_RESET_OUT 3 -1 1 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
320 CLK_000_P_SYNC_10_ 3 -1 0 5 0 2 3 5 7 -1 -1 1 0 21
|
|
359 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 14 0 21
|
|
301 inst_AS_030_D0 3 -1 7 4 2 3 4 7 -1 -1 1 0 21
|
|
294 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
|
354 SM_AMIGA_6_ 3 -1 5 3 1 2 5 -1 -1 3 0 21
|
|
299 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21
|
|
297 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
295 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
324 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 2 0 21
|
|
328 CLK_000_N_SYNC_11_ 3 -1 7 3 1 3 5 -1 -1 1 0 21
|
|
314 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
|
304 inst_BGACK_030_INT_D 3 -1 7 3 0 2 6 -1 -1 1 0 21
|
|
305 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
303 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21
|
|
327 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21
|
|
369 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
356 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
326 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21
|
|
313 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21
|
|
310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
325 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 2 0 3 -1 -1 2 0 21
|
|
312 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
|
|
296 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21
|
|
353 inst_CLK_000_NE_D0 3 -1 5 2 3 5 -1 -1 1 0 21
|
|
319 CLK_000_D_0_ 3 -1 1 2 3 5 -1 -1 1 0 21
|
|
311 inst_VPA_D 3 -1 1 2 3 5 -1 -1 1 0 21
|
|
363 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
362 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
361 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
306 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
355 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
357 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21
|
|
368 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
358 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
330 RST_DLY_1_ 3 -1 1 1 1 -1 -1 4 0 21
|
|
293 N_317_i 3 -1 5 1 5 -1 -1 4 0 21
|
|
365 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
364 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
329 RST_DLY_0_ 3 -1 1 1 1 -1 -1 3 0 21
|
|
308 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
370 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
366 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
360 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
331 RST_DLY_2_ 3 -1 1 1 1 -1 -1 2 0 21
|
|
307 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
352 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_9_ 3 -1 6 1 7 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_8_ 3 -1 4 1 6 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_7_ 3 -1 0 1 4 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_6_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_5_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_4_ 3 -1 6 1 3 -1 -1 1 0 21
|
|
345 CLK_000_N_SYNC_3_ 3 -1 0 1 6 -1 -1 1 0 21
|
|
344 CLK_000_N_SYNC_2_ 3 -1 3 1 0 -1 -1 1 0 21
|
|
343 CLK_000_N_SYNC_1_ 3 -1 3 1 3 -1 -1 1 0 21
|
|
342 CLK_000_N_SYNC_0_ 3 -1 5 1 3 -1 -1 1 0 21
|
|
341 CLK_000_P_SYNC_9_ 3 -1 5 1 0 -1 -1 1 0 21
|
|
340 CLK_000_P_SYNC_8_ 3 -1 3 1 5 -1 -1 1 0 21
|
|
339 CLK_000_P_SYNC_7_ 3 -1 6 1 3 -1 -1 1 0 21
|
|
338 CLK_000_P_SYNC_6_ 3 -1 0 1 6 -1 -1 1 0 21
|
|
337 CLK_000_P_SYNC_5_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
336 CLK_000_P_SYNC_4_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
335 CLK_000_P_SYNC_3_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
334 CLK_000_P_SYNC_2_ 3 -1 4 1 1 -1 -1 1 0 21
|
|
333 CLK_000_P_SYNC_1_ 3 -1 3 1 4 -1 -1 1 0 21
|
|
332 CLK_000_P_SYNC_0_ 3 -1 5 1 3 -1 -1 1 0 21
|
|
323 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
322 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
321 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
318 CLK_000_D_1_ 3 -1 3 1 5 -1 -1 1 0 21
|
|
317 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
315 inst_DTACK_D0 3 -1 6 1 5 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 6 66 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 6 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
59 A1 1 -1 -1 1 0 59 -1
|
|
35 VPA 1 -1 -1 1 1 35 -1
|
|
29 DTACK 1 -1 -1 1 6 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 6 13 -1
|
|
10 CLK_000 1 -1 -1 1 1 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
139 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
79 RW_000 5 364 7 3 0 4 6 79 -1 3 0 21
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
40 BERR 5 -1 4 3 2 5 7 40 -1 1 0 21
|
|
70 RW 5 370 6 2 2 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
68 A0 5 365 6 1 1 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 361 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 363 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 362 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 368 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 367 7 0 82 -1 3 0 21
|
|
34 VMA 5 369 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 366 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
302 inst_nEXP_SPACE_D0reg 3 -1 6 7 0 2 3 4 5 6 7 -1 -1 1 0 21
|
|
367 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 3 0 21
|
|
316 inst_RESET_OUT 3 -1 1 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
320 CLK_000_P_SYNC_9_ 3 -1 0 5 0 2 3 5 7 -1 -1 1 0 21
|
|
359 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 14 0 21
|
|
301 inst_AS_030_D0 3 -1 7 4 2 3 4 7 -1 -1 1 0 21
|
|
294 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
|
354 SM_AMIGA_6_ 3 -1 5 3 1 2 5 -1 -1 3 0 21
|
|
299 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21
|
|
297 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
295 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
324 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 2 0 21
|
|
328 CLK_000_N_SYNC_12_ 3 -1 3 3 1 3 5 -1 -1 1 0 21
|
|
314 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
|
304 inst_BGACK_030_INT_D 3 -1 7 3 0 2 6 -1 -1 1 0 21
|
|
305 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
303 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21
|
|
327 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21
|
|
369 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
356 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
326 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21
|
|
313 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21
|
|
310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
325 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 2 0 3 -1 -1 2 0 21
|
|
312 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
|
|
296 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21
|
|
353 inst_CLK_000_NE_D0 3 -1 5 2 3 5 -1 -1 1 0 21
|
|
319 CLK_000_D_0_ 3 -1 1 2 3 5 -1 -1 1 0 21
|
|
311 inst_VPA_D 3 -1 1 2 3 5 -1 -1 1 0 21
|
|
363 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
362 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
361 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
306 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
355 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
357 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21
|
|
368 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
358 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
330 RST_DLY_1_ 3 -1 1 1 1 -1 -1 4 0 21
|
|
293 N_317_i 3 -1 5 1 5 -1 -1 4 0 21
|
|
365 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
364 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
329 RST_DLY_0_ 3 -1 1 1 1 -1 -1 3 0 21
|
|
308 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
370 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
366 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
360 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
331 RST_DLY_2_ 3 -1 1 1 1 -1 -1 2 0 21
|
|
307 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
352 CLK_000_N_SYNC_11_ 3 -1 7 1 3 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_9_ 3 -1 6 1 7 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_8_ 3 -1 4 1 6 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_7_ 3 -1 0 1 4 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_6_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_5_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
345 CLK_000_N_SYNC_4_ 3 -1 6 1 3 -1 -1 1 0 21
|
|
344 CLK_000_N_SYNC_3_ 3 -1 0 1 6 -1 -1 1 0 21
|
|
343 CLK_000_N_SYNC_2_ 3 -1 3 1 0 -1 -1 1 0 21
|
|
342 CLK_000_N_SYNC_1_ 3 -1 3 1 3 -1 -1 1 0 21
|
|
341 CLK_000_N_SYNC_0_ 3 -1 5 1 3 -1 -1 1 0 21
|
|
340 CLK_000_P_SYNC_8_ 3 -1 5 1 0 -1 -1 1 0 21
|
|
339 CLK_000_P_SYNC_7_ 3 -1 3 1 5 -1 -1 1 0 21
|
|
338 CLK_000_P_SYNC_6_ 3 -1 6 1 3 -1 -1 1 0 21
|
|
337 CLK_000_P_SYNC_5_ 3 -1 0 1 6 -1 -1 1 0 21
|
|
336 CLK_000_P_SYNC_4_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
335 CLK_000_P_SYNC_3_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
334 CLK_000_P_SYNC_2_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
333 CLK_000_P_SYNC_1_ 3 -1 4 1 1 -1 -1 1 0 21
|
|
332 CLK_000_P_SYNC_0_ 3 -1 5 1 4 -1 -1 1 0 21
|
|
323 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
322 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
321 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
318 CLK_000_D_1_ 3 -1 3 1 5 -1 -1 1 0 21
|
|
317 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
315 inst_DTACK_D0 3 -1 6 1 5 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 6 66 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 6 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
59 A1 1 -1 -1 1 0 59 -1
|
|
35 VPA 1 -1 -1 1 1 35 -1
|
|
29 DTACK 1 -1 -1 1 6 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 6 13 -1
|
|
10 CLK_000 1 -1 -1 1 1 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
130 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 5 0 2 3 5 7 40 -1 1 0 21
|
|
41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21
|
|
79 RW_000 5 353 7 3 2 4 6 79 -1 5 0 21
|
|
70 RW 5 359 6 2 0 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 2 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 2 6 30 -1 1 0 21
|
|
68 A0 5 354 6 1 1 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 352 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 361 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 360 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 357 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 356 7 0 82 -1 3 0 21
|
|
34 VMA 5 358 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 355 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
356 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 3 0 21
|
|
316 inst_RESET_OUT 3 -1 1 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
302 inst_nEXP_SPACE_D0reg 3 -1 3 6 0 3 4 5 6 7 -1 -1 1 0 21
|
|
318 CLK_000_D_1_ 3 -1 7 5 0 2 3 5 7 -1 -1 1 0 21
|
|
317 CLK_000_D_0_ 3 -1 7 5 0 2 3 5 7 -1 -1 1 0 21
|
|
301 inst_AS_030_D0 3 -1 7 5 0 2 3 4 7 -1 -1 1 0 21
|
|
344 SM_AMIGA_6_ 3 -1 3 4 0 1 3 5 -1 -1 3 1 21
|
|
299 SM_AMIGA_5_ 3 -1 5 4 0 2 5 7 -1 -1 3 0 21
|
|
303 inst_AS_030_000_SYNC 3 -1 0 3 0 3 5 -1 -1 7 0 21
|
|
323 SM_AMIGA_0_ 3 -1 5 3 0 5 7 -1 -1 4 0 21
|
|
297 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
|
296 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
294 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
349 SM_AMIGA_i_7_ 3 -1 5 3 0 3 7 -1 -1 2 0 21
|
|
326 CLK_000_N_SYNC_12_ 3 -1 5 3 1 3 5 -1 -1 1 0 21
|
|
314 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
|
306 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21
|
|
305 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21
|
|
325 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 5 0 21
|
|
358 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
346 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
342 SM_AMIGA_4_ 3 -1 5 2 0 5 -1 -1 3 1 21
|
|
313 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21
|
|
310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
324 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
312 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
|
|
295 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21
|
|
343 inst_CLK_000_NE_D0 3 -1 3 2 3 5 -1 -1 1 0 21
|
|
340 CLK_000_N_SYNC_10_ 3 -1 7 2 1 7 -1 -1 1 0 21
|
|
311 inst_VPA_D 3 -1 2 2 3 5 -1 -1 1 0 21
|
|
304 inst_BGACK_030_INT_D 3 -1 7 2 0 6 -1 -1 1 0 21
|
|
351 SM_AMIGA_i_7__0 3 -1 5 1 5 -1 -1 15 0 21
|
|
361 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
360 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
352 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
345 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21
|
|
353 RN_RW_000 3 79 7 1 7 79 -1 5 0 21
|
|
348 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 5 0 21
|
|
347 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21
|
|
357 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
328 RST_DLY_1_ 3 -1 1 1 1 -1 -1 4 0 21
|
|
307 CYCLE_DMA_0_ 3 -1 2 1 2 -1 -1 4 0 21
|
|
293 N_230_i 3 -1 5 1 5 -1 -1 4 0 21
|
|
354 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
327 RST_DLY_0_ 3 -1 1 1 1 -1 -1 3 0 21
|
|
359 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
355 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
350 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
329 RST_DLY_2_ 3 -1 1 1 1 -1 -1 2 0 21
|
|
341 CLK_000_N_SYNC_11_ 3 -1 1 1 5 -1 -1 1 0 21
|
|
339 CLK_000_N_SYNC_9_ 3 -1 6 1 7 -1 -1 1 0 21
|
|
338 CLK_000_N_SYNC_8_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
337 CLK_000_N_SYNC_7_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
336 CLK_000_N_SYNC_6_ 3 -1 2 1 6 -1 -1 1 0 21
|
|
335 CLK_000_N_SYNC_5_ 3 -1 6 1 2 -1 -1 1 0 21
|
|
334 CLK_000_N_SYNC_4_ 3 -1 2 1 6 -1 -1 1 0 21
|
|
333 CLK_000_N_SYNC_3_ 3 -1 5 1 2 -1 -1 1 0 21
|
|
332 CLK_000_N_SYNC_2_ 3 -1 2 1 5 -1 -1 1 0 21
|
|
331 CLK_000_N_SYNC_1_ 3 -1 4 1 2 -1 -1 1 0 21
|
|
330 CLK_000_N_SYNC_0_ 3 -1 3 1 4 -1 -1 1 0 21
|
|
322 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
321 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
320 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
319 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
315 inst_DTACK_D0 3 -1 2 1 5 -1 -1 1 0 21
|
|
308 CYCLE_DMA_1_ 3 -1 2 1 2 -1 -1 1 1 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
10 CLK_000 1 -1 -1 5 0 2 3 5 7 10 -1
|
|
96 A_19_ 1 -1 -1 3 0 4 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 0 4 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 0 4 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 0 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 0 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 0 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 6 66 -1
|
|
63 CLK_030 1 -1 -1 2 2 7 63 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
59 A1 1 -1 -1 1 6 59 -1
|
|
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
|
35 VPA 1 -1 -1 1 2 35 -1
|
|
29 DTACK 1 -1 -1 1 2 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 3 13 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
140 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 5 0 1 2 5 7 40 -1 1 0 21
|
|
79 RW_000 5 365 7 3 0 4 6 79 -1 3 0 21
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
68 A0 5 366 6 2 0 6 68 -1 3 0 21
|
|
70 RW 5 371 6 2 1 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 363 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 364 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 362 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 369 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 368 7 0 82 -1 3 0 21
|
|
34 VMA 5 370 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 367 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
368 RN_BGACK_030 3 82 7 7 0 2 3 4 5 6 7 82 -1 3 0 21
|
|
300 inst_nEXP_SPACE_D0reg 3 -1 5 7 0 2 3 4 5 6 7 -1 -1 1 0 21
|
|
314 inst_RESET_OUT 3 -1 1 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
359 SM_AMIGA_i_7_ 3 -1 2 5 1 2 3 5 7 -1 -1 15 0 21
|
|
318 CLK_000_P_SYNC_10_ 3 -1 5 5 0 1 2 3 7 -1 -1 1 0 21
|
|
299 inst_AS_030_D0 3 -1 7 5 1 3 4 5 7 -1 -1 1 0 21
|
|
354 SM_AMIGA_6_ 3 -1 2 4 0 1 2 6 -1 -1 3 0 21
|
|
323 SM_AMIGA_0_ 3 -1 0 4 0 1 2 7 -1 -1 2 0 21
|
|
327 CLK_000_N_SYNC_12_ 3 -1 0 4 0 1 2 3 -1 -1 1 0 21
|
|
293 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 4 0 21
|
|
356 SM_AMIGA_1_ 3 -1 2 3 0 2 7 -1 -1 3 0 21
|
|
319 SM_AMIGA_5_ 3 -1 2 3 1 2 7 -1 -1 3 0 21
|
|
296 cpu_est_1_ 3 -1 6 3 2 3 6 -1 -1 3 0 21
|
|
294 cpu_est_3_ 3 -1 2 3 2 3 6 -1 -1 3 0 21
|
|
295 cpu_est_0_ 3 -1 2 3 2 3 6 -1 -1 2 0 21
|
|
317 CLK_000_D_0_ 3 -1 6 3 2 3 5 -1 -1 1 0 21
|
|
312 inst_CLK_OUT_PRE_D 3 -1 6 3 1 6 7 -1 -1 1 0 21
|
|
303 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
301 inst_AS_030_000_SYNC 3 -1 5 2 2 5 -1 -1 7 0 21
|
|
326 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 5 0 21
|
|
370 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21
|
|
325 SM_AMIGA_4_ 3 -1 1 2 1 2 -1 -1 3 0 21
|
|
311 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21
|
|
308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
324 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 2 3 5 -1 -1 2 0 21
|
|
310 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21
|
|
297 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21
|
|
353 inst_CLK_000_NE_D0 3 -1 2 2 2 6 -1 -1 1 0 21
|
|
316 CLK_000_D_1_ 3 -1 3 2 2 5 -1 -1 1 0 21
|
|
315 inst_CLK_OUT_PRE_50 3 -1 2 2 2 6 -1 -1 1 0 21
|
|
309 inst_VPA_D 3 -1 5 2 2 3 -1 -1 1 0 21
|
|
302 inst_BGACK_030_INT_D 3 -1 7 2 5 6 -1 -1 1 0 21
|
|
364 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
363 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
362 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
304 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
355 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
357 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21
|
|
369 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
358 SM_AMIGA_2_ 3 -1 2 1 2 -1 -1 4 0 21
|
|
329 RST_DLY_1_ 3 -1 1 1 1 -1 -1 4 0 21
|
|
366 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
365 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
328 RST_DLY_0_ 3 -1 1 1 1 -1 -1 3 0 21
|
|
306 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
371 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
367 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
330 RST_DLY_2_ 3 -1 1 1 1 -1 -1 2 0 21
|
|
305 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
360 N_319 3 -1 3 1 2 -1 -1 1 0 21
|
|
352 CLK_000_N_SYNC_11_ 3 -1 7 1 0 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_9_ 3 -1 4 1 7 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_8_ 3 -1 6 1 4 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_7_ 3 -1 5 1 6 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_6_ 3 -1 4 1 5 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_5_ 3 -1 0 1 4 -1 -1 1 0 21
|
|
345 CLK_000_N_SYNC_4_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
344 CLK_000_N_SYNC_3_ 3 -1 5 1 6 -1 -1 1 0 21
|
|
343 CLK_000_N_SYNC_2_ 3 -1 0 1 5 -1 -1 1 0 21
|
|
342 CLK_000_N_SYNC_1_ 3 -1 5 1 0 -1 -1 1 0 21
|
|
341 CLK_000_N_SYNC_0_ 3 -1 5 1 5 -1 -1 1 0 21
|
|
340 CLK_000_P_SYNC_9_ 3 -1 4 1 5 -1 -1 1 0 21
|
|
339 CLK_000_P_SYNC_8_ 3 -1 3 1 4 -1 -1 1 0 21
|
|
338 CLK_000_P_SYNC_7_ 3 -1 1 1 3 -1 -1 1 0 21
|
|
337 CLK_000_P_SYNC_6_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
336 CLK_000_P_SYNC_5_ 3 -1 5 1 0 -1 -1 1 0 21
|
|
335 CLK_000_P_SYNC_4_ 3 -1 1 1 5 -1 -1 1 0 21
|
|
334 CLK_000_P_SYNC_3_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
333 CLK_000_P_SYNC_2_ 3 -1 3 1 3 -1 -1 1 0 21
|
|
332 CLK_000_P_SYNC_1_ 3 -1 3 1 3 -1 -1 1 0 21
|
|
331 CLK_000_P_SYNC_0_ 3 -1 2 1 3 -1 -1 1 0 21
|
|
322 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
321 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
320 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
313 inst_DTACK_D0 3 -1 3 1 2 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 4 5 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 4 5 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 4 5 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 4 5 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 4 5 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 4 5 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
67 IPL_2_ 1 -1 -1 2 0 1 67 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 6 66 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 3 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
59 A1 1 -1 -1 1 5 59 -1
|
|
35 VPA 1 -1 -1 1 5 35 -1
|
|
29 DTACK 1 -1 -1 1 3 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 5 13 -1
|
|
10 CLK_000 1 -1 -1 1 6 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
146 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 4 2 5 6 7 40 -1 1 0 21
|
|
79 RW_000 5 371 7 3 0 4 6 79 -1 3 0 21
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
68 A0 5 372 6 2 0 1 68 -1 3 0 21
|
|
70 RW 5 377 6 2 2 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 368 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 370 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 369 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 375 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 374 7 0 82 -1 3 0 21
|
|
34 VMA 5 376 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 373 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
374 RN_BGACK_030 3 82 7 7 0 2 3 4 5 6 7 82 -1 3 0 21
|
|
315 inst_RESET_OUT 3 -1 1 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
319 CLK_000_P_SYNC_10_ 3 -1 0 6 0 2 3 5 6 7 -1 -1 1 0 21
|
|
301 inst_nEXP_SPACE_D0reg 3 -1 5 6 0 3 4 5 6 7 -1 -1 1 0 21
|
|
300 inst_AS_030_D0 3 -1 7 5 2 3 4 5 7 -1 -1 1 0 21
|
|
366 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 15 0 21
|
|
361 SM_AMIGA_6_ 3 -1 5 4 0 1 2 5 -1 -1 3 0 21
|
|
330 SM_AMIGA_0_ 3 -1 6 4 2 5 6 7 -1 -1 2 0 21
|
|
334 CLK_000_N_SYNC_12_ 3 -1 1 4 1 3 5 6 -1 -1 1 0 21
|
|
294 cpu_est_2_ 3 -1 3 3 2 3 6 -1 -1 4 0 21
|
|
363 SM_AMIGA_1_ 3 -1 5 3 5 6 7 -1 -1 3 0 21
|
|
320 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21
|
|
297 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 3 0 21
|
|
295 cpu_est_3_ 3 -1 2 3 2 3 6 -1 -1 3 0 21
|
|
360 inst_CLK_000_NE_D0 3 -1 5 3 2 3 5 -1 -1 1 0 21
|
|
318 CLK_000_D_0_ 3 -1 6 3 1 3 5 -1 -1 1 0 21
|
|
313 inst_CLK_OUT_PRE_D 3 -1 0 3 1 6 7 -1 -1 1 0 21
|
|
310 inst_VPA_D 3 -1 3 3 2 3 5 -1 -1 1 0 21
|
|
304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
364 SM_AMIGA_3_ 3 -1 2 2 2 5 -1 -1 5 0 21
|
|
333 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21
|
|
365 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 4 0 21
|
|
376 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21
|
|
332 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21
|
|
312 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21
|
|
309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
331 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
311 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
|
|
296 cpu_est_0_ 3 -1 2 2 2 3 -1 -1 2 0 21
|
|
317 CLK_000_D_1_ 3 -1 5 2 1 5 -1 -1 1 0 21
|
|
314 inst_DTACK_D0 3 -1 3 2 2 5 -1 -1 1 0 21
|
|
303 inst_BGACK_030_INT_D 3 -1 7 2 5 6 -1 -1 1 0 21
|
|
370 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
369 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
368 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
362 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
302 inst_AS_030_000_SYNC 3 -1 5 1 5 -1 -1 7 0 21
|
|
375 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
336 RST_DLY_1_ 3 -1 1 1 1 -1 -1 4 0 21
|
|
372 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
371 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
335 RST_DLY_0_ 3 -1 1 1 1 -1 -1 3 0 21
|
|
307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
377 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
373 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
367 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
337 RST_DLY_2_ 3 -1 1 1 1 -1 -1 2 0 21
|
|
306 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
359 CLK_000_N_SYNC_11_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
358 CLK_000_N_SYNC_10_ 3 -1 3 1 3 -1 -1 1 0 21
|
|
357 CLK_000_N_SYNC_9_ 3 -1 2 1 3 -1 -1 1 0 21
|
|
356 CLK_000_N_SYNC_8_ 3 -1 6 1 2 -1 -1 1 0 21
|
|
355 CLK_000_N_SYNC_7_ 3 -1 4 1 6 -1 -1 1 0 21
|
|
354 CLK_000_N_SYNC_6_ 3 -1 4 1 4 -1 -1 1 0 21
|
|
353 CLK_000_N_SYNC_5_ 3 -1 3 1 4 -1 -1 1 0 21
|
|
352 CLK_000_N_SYNC_4_ 3 -1 2 1 3 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_3_ 3 -1 3 1 2 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_2_ 3 -1 1 1 3 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_1_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_0_ 3 -1 5 1 0 -1 -1 1 0 21
|
|
347 CLK_000_P_SYNC_9_ 3 -1 1 1 0 -1 -1 1 0 21
|
|
346 CLK_000_P_SYNC_8_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
345 CLK_000_P_SYNC_7_ 3 -1 2 1 0 -1 -1 1 0 21
|
|
344 CLK_000_P_SYNC_6_ 3 -1 2 1 2 -1 -1 1 0 21
|
|
343 CLK_000_P_SYNC_5_ 3 -1 2 1 2 -1 -1 1 0 21
|
|
342 CLK_000_P_SYNC_4_ 3 -1 0 1 2 -1 -1 1 0 21
|
|
341 CLK_000_P_SYNC_3_ 3 -1 1 1 0 -1 -1 1 0 21
|
|
340 CLK_000_P_SYNC_2_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
339 CLK_000_P_SYNC_1_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
338 CLK_000_P_SYNC_0_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
329 CLK_000_D_7_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
328 CLK_000_D_6_ 3 -1 4 1 7 -1 -1 1 0 21
|
|
327 CLK_000_D_5_ 3 -1 5 1 4 -1 -1 1 0 21
|
|
326 CLK_000_D_4_ 3 -1 6 1 5 -1 -1 1 0 21
|
|
325 CLK_000_D_3_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
324 CLK_000_D_2_ 3 -1 5 1 3 -1 -1 1 0 21
|
|
323 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
322 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
321 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
316 inst_CLK_OUT_PRE_50 3 -1 0 1 0 -1 -1 1 0 21
|
|
293 N_319 3 -1 2 1 5 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 4 5 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 4 5 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 4 5 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 4 5 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 4 5 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 4 5 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
67 IPL_2_ 1 -1 -1 2 1 6 67 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 6 66 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
59 A1 1 -1 -1 1 6 59 -1
|
|
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
|
35 VPA 1 -1 -1 1 3 35 -1
|
|
29 DTACK 1 -1 -1 1 3 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 5 13 -1
|
|
10 CLK_000 1 -1 -1 1 6 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
145 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
41 AS_000 5 -1 4 4 0 1 4 7 41 -1 1 0 21
|
|
40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21
|
|
79 RW_000 5 369 7 3 0 4 6 79 -1 3 0 21
|
|
68 A0 5 371 6 2 3 6 68 -1 3 0 21
|
|
70 RW 5 376 6 2 2 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
78 SIZE_1_ 5 -1 7 1 6 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 6 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 367 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 370 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 368 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 374 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 373 7 0 82 -1 3 0 21
|
|
34 VMA 5 375 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 372 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
373 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
300 inst_nEXP_SPACE_D0reg 3 -1 2 7 0 2 3 4 5 6 7 -1 -1 1 0 21
|
|
315 inst_RESET_OUT 3 -1 1 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
319 CLK_000_P_SYNC_10_ 3 -1 1 6 0 1 2 3 5 7 -1 -1 1 0 21
|
|
333 CLK_000_N_SYNC_12_ 3 -1 0 5 0 1 3 5 7 -1 -1 1 0 21
|
|
365 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 14 0 21
|
|
360 SM_AMIGA_6_ 3 -1 5 4 2 3 5 6 -1 -1 3 0 21
|
|
320 SM_AMIGA_5_ 3 -1 5 4 0 2 5 7 -1 -1 3 0 21
|
|
299 inst_AS_030_D0 3 -1 7 4 2 3 4 7 -1 -1 1 0 21
|
|
293 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
|
331 SM_AMIGA_4_ 3 -1 0 3 0 2 5 -1 -1 3 0 21
|
|
296 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
294 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
329 SM_AMIGA_0_ 3 -1 7 3 2 5 7 -1 -1 2 0 21
|
|
313 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
|
304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
301 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21
|
|
332 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21
|
|
335 RST_DLY_1_ 3 -1 1 2 0 1 -1 -1 4 0 21
|
|
375 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
362 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
334 RST_DLY_0_ 3 -1 0 2 0 1 -1 -1 3 0 21
|
|
312 inst_LDS_000_INT 3 -1 6 2 3 6 -1 -1 3 0 21
|
|
309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
336 RST_DLY_2_ 3 -1 0 2 0 1 -1 -1 2 0 21
|
|
330 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21
|
|
306 CYCLE_DMA_0_ 3 -1 1 2 0 1 -1 -1 2 0 21
|
|
297 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
|
|
295 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 2 0 21
|
|
359 inst_CLK_000_NE_D0 3 -1 3 2 3 5 -1 -1 1 0 21
|
|
327 CLK_000_D_5_ 3 -1 6 2 6 7 -1 -1 1 0 21
|
|
318 CLK_000_D_0_ 3 -1 3 2 3 5 -1 -1 1 0 21
|
|
317 CLK_000_D_1_ 3 -1 5 2 3 5 -1 -1 1 0 21
|
|
310 inst_VPA_D 3 -1 5 2 3 5 -1 -1 1 0 21
|
|
303 inst_BGACK_030_INT_D 3 -1 7 2 2 6 -1 -1 1 0 21
|
|
370 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
368 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
367 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
361 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
363 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21
|
|
374 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
364 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
302 N_263_i 3 -1 5 1 5 -1 -1 4 0 21
|
|
371 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
369 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
376 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
372 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
366 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
311 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21
|
|
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21
|
|
358 CLK_000_N_SYNC_11_ 3 -1 3 1 0 -1 -1 1 0 21
|
|
357 CLK_000_N_SYNC_10_ 3 -1 0 1 3 -1 -1 1 0 21
|
|
356 CLK_000_N_SYNC_9_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
355 CLK_000_N_SYNC_8_ 3 -1 0 1 6 -1 -1 1 0 21
|
|
354 CLK_000_N_SYNC_7_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
353 CLK_000_N_SYNC_6_ 3 -1 4 1 0 -1 -1 1 0 21
|
|
352 CLK_000_N_SYNC_5_ 3 -1 6 1 4 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_4_ 3 -1 4 1 6 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_3_ 3 -1 6 1 4 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_2_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_1_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_0_ 3 -1 3 1 3 -1 -1 1 0 21
|
|
346 CLK_000_P_SYNC_9_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
345 CLK_000_P_SYNC_8_ 3 -1 2 1 0 -1 -1 1 0 21
|
|
344 CLK_000_P_SYNC_7_ 3 -1 6 1 2 -1 -1 1 0 21
|
|
343 CLK_000_P_SYNC_6_ 3 -1 0 1 6 -1 -1 1 0 21
|
|
342 CLK_000_P_SYNC_5_ 3 -1 1 1 0 -1 -1 1 0 21
|
|
341 CLK_000_P_SYNC_4_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
340 CLK_000_P_SYNC_3_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
339 CLK_000_P_SYNC_2_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
338 CLK_000_P_SYNC_1_ 3 -1 5 1 6 -1 -1 1 0 21
|
|
337 CLK_000_P_SYNC_0_ 3 -1 3 1 5 -1 -1 1 0 21
|
|
328 CLK_000_D_6_ 3 -1 6 1 7 -1 -1 1 0 21
|
|
326 CLK_000_D_4_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
325 CLK_000_D_3_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
324 CLK_000_D_2_ 3 -1 5 1 5 -1 -1 1 0 21
|
|
323 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
322 IPL_D0_1_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
321 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
316 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
314 inst_DTACK_D0 3 -1 6 1 5 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 2 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
|
59 A1 1 -1 -1 1 2 59 -1
|
|
35 VPA 1 -1 -1 1 5 35 -1
|
|
29 DTACK 1 -1 -1 1 6 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 2 13 -1
|
|
10 CLK_000 1 -1 -1 1 3 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
147 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
79 RW_000 5 371 7 3 0 4 6 79 -1 3 0 21
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
40 BERR 5 -1 4 3 2 5 7 40 -1 1 0 21
|
|
68 A0 5 373 6 2 0 1 68 -1 3 0 21
|
|
70 RW 5 378 6 2 5 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 369 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 372 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 370 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 376 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 375 7 0 82 -1 3 0 21
|
|
34 VMA 5 377 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 374 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
375 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21
|
|
301 inst_nEXP_SPACE_D0reg 3 -1 6 7 0 2 3 4 5 6 7 -1 -1 1 0 21
|
|
315 inst_RESET_OUT 3 -1 6 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
319 CLK_000_P_SYNC_10_ 3 -1 6 5 0 2 3 5 7 -1 -1 1 0 21
|
|
362 SM_AMIGA_6_ 3 -1 5 4 0 1 2 5 -1 -1 3 0 21
|
|
335 CLK_000_N_SYNC_12_ 3 -1 4 4 2 3 5 6 -1 -1 1 0 21
|
|
318 CLK_000_D_0_ 3 -1 3 4 0 2 3 5 -1 -1 1 0 21
|
|
303 inst_BGACK_030_INT_D 3 -1 7 4 0 1 5 6 -1 -1 1 0 21
|
|
300 inst_AS_030_D0 3 -1 7 4 3 4 5 7 -1 -1 1 0 21
|
|
367 SM_AMIGA_i_7_ 3 -1 2 3 3 5 7 -1 -1 15 0 21
|
|
294 cpu_est_2_ 3 -1 3 3 2 3 6 -1 -1 4 0 21
|
|
364 SM_AMIGA_1_ 3 -1 2 3 2 5 7 -1 -1 3 0 21
|
|
320 SM_AMIGA_5_ 3 -1 2 3 2 5 7 -1 -1 3 0 21
|
|
308 SIZE_DMA_0_ 3 -1 0 3 0 6 7 -1 -1 3 0 21
|
|
297 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 3 0 21
|
|
295 cpu_est_3_ 3 -1 2 3 2 3 6 -1 -1 3 0 21
|
|
331 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 2 0 21
|
|
313 inst_CLK_OUT_PRE_D 3 -1 3 3 1 6 7 -1 -1 1 0 21
|
|
304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
302 inst_AS_030_000_SYNC 3 -1 5 2 2 5 -1 -1 7 0 21
|
|
334 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 5 0 21
|
|
377 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21
|
|
333 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21
|
|
312 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21
|
|
309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
332 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
311 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21
|
|
296 cpu_est_0_ 3 -1 2 2 2 3 -1 -1 2 0 21
|
|
361 inst_CLK_000_NE_D0 3 -1 5 2 2 3 -1 -1 1 0 21
|
|
317 CLK_000_D_1_ 3 -1 0 2 2 5 -1 -1 1 0 21
|
|
316 inst_CLK_OUT_PRE_50 3 -1 4 2 3 4 -1 -1 1 0 21
|
|
310 inst_VPA_D 3 -1 2 2 2 3 -1 -1 1 0 21
|
|
372 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
370 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
369 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
363 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
365 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21
|
|
376 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
366 SM_AMIGA_2_ 3 -1 2 1 2 -1 -1 4 0 21
|
|
337 RST_DLY_1_ 3 -1 6 1 6 -1 -1 4 0 21
|
|
373 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
371 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
336 RST_DLY_0_ 3 -1 6 1 6 -1 -1 3 0 21
|
|
307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
378 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
374 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
368 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
338 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21
|
|
306 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
360 CLK_000_N_SYNC_11_ 3 -1 0 1 4 -1 -1 1 0 21
|
|
359 CLK_000_N_SYNC_10_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
358 CLK_000_N_SYNC_9_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
357 CLK_000_N_SYNC_8_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
356 CLK_000_N_SYNC_7_ 3 -1 3 1 3 -1 -1 1 0 21
|
|
355 CLK_000_N_SYNC_6_ 3 -1 2 1 3 -1 -1 1 0 21
|
|
354 CLK_000_N_SYNC_5_ 3 -1 1 1 2 -1 -1 1 0 21
|
|
353 CLK_000_N_SYNC_4_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
352 CLK_000_N_SYNC_3_ 3 -1 1 1 0 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_2_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_1_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_0_ 3 -1 2 1 6 -1 -1 1 0 21
|
|
348 CLK_000_P_SYNC_9_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
347 CLK_000_P_SYNC_8_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
346 CLK_000_P_SYNC_7_ 3 -1 4 1 5 -1 -1 1 0 21
|
|
345 CLK_000_P_SYNC_6_ 3 -1 1 1 4 -1 -1 1 0 21
|
|
344 CLK_000_P_SYNC_5_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
343 CLK_000_P_SYNC_4_ 3 -1 1 1 5 -1 -1 1 0 21
|
|
342 CLK_000_P_SYNC_3_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
341 CLK_000_P_SYNC_2_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
340 CLK_000_P_SYNC_1_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
339 CLK_000_P_SYNC_0_ 3 -1 5 1 3 -1 -1 1 0 21
|
|
330 CLK_000_D_8_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
329 CLK_000_D_7_ 3 -1 3 1 7 -1 -1 1 0 21
|
|
328 CLK_000_D_6_ 3 -1 0 1 3 -1 -1 1 0 21
|
|
327 CLK_000_D_5_ 3 -1 3 1 0 -1 -1 1 0 21
|
|
326 CLK_000_D_4_ 3 -1 2 1 3 -1 -1 1 0 21
|
|
325 CLK_000_D_3_ 3 -1 1 1 2 -1 -1 1 0 21
|
|
324 CLK_000_D_2_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
323 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
322 IPL_D0_1_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
321 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
314 inst_DTACK_D0 3 -1 5 1 2 -1 -1 1 0 21
|
|
293 N_319 3 -1 2 1 2 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 4 5 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 4 5 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 4 5 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 4 5 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 4 5 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 4 5 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 2 0 1 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
|
59 A1 1 -1 -1 1 1 59 -1
|
|
35 VPA 1 -1 -1 1 2 35 -1
|
|
29 DTACK 1 -1 -1 1 5 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 6 13 -1
|
|
10 CLK_000 1 -1 -1 1 3 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
148 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 4 2 5 6 7 40 -1 1 0 21
|
|
79 RW_000 5 373 7 3 0 4 6 79 -1 3 0 21
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
70 RW 5 379 6 2 2 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
68 A0 5 374 6 1 1 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 370 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 372 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 371 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 377 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 376 7 0 82 -1 3 0 21
|
|
34 VMA 5 378 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 375 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
376 RN_BGACK_030 3 82 7 7 0 2 3 4 5 6 7 82 -1 3 0 21
|
|
315 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
301 inst_nEXP_SPACE_D0reg 3 -1 1 6 0 3 4 5 6 7 -1 -1 1 0 21
|
|
300 inst_AS_030_D0 3 -1 4 6 2 3 4 5 6 7 -1 -1 1 0 21
|
|
319 CLK_000_P_SYNC_10_ 3 -1 1 5 0 2 3 5 7 -1 -1 1 0 21
|
|
368 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 15 0 21
|
|
320 SM_AMIGA_5_ 3 -1 5 4 2 5 6 7 -1 -1 3 0 21
|
|
294 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 4 0 21
|
|
363 SM_AMIGA_6_ 3 -1 5 3 1 2 5 -1 -1 3 0 21
|
|
297 cpu_est_1_ 3 -1 2 3 2 3 6 -1 -1 3 0 21
|
|
295 cpu_est_3_ 3 -1 6 3 2 3 6 -1 -1 3 0 21
|
|
332 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 2 0 21
|
|
296 cpu_est_0_ 3 -1 2 3 2 3 6 -1 -1 2 0 21
|
|
362 inst_CLK_000_NE_D0 3 -1 3 3 2 5 6 -1 -1 1 0 21
|
|
336 CLK_000_N_SYNC_12_ 3 -1 0 3 1 3 5 -1 -1 1 0 21
|
|
313 inst_CLK_OUT_PRE_D 3 -1 2 3 1 6 7 -1 -1 1 0 21
|
|
310 inst_VPA_D 3 -1 0 3 2 3 5 -1 -1 1 0 21
|
|
303 inst_BGACK_030_INT_D 3 -1 7 3 0 5 6 -1 -1 1 0 21
|
|
304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
366 SM_AMIGA_3_ 3 -1 2 2 2 5 -1 -1 5 0 21
|
|
335 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21
|
|
367 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 4 0 21
|
|
338 RST_DLY_1_ 3 -1 1 2 1 3 -1 -1 4 0 21
|
|
378 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21
|
|
365 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
337 RST_DLY_0_ 3 -1 3 2 1 3 -1 -1 3 0 21
|
|
334 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21
|
|
312 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21
|
|
309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
339 RST_DLY_2_ 3 -1 3 2 1 3 -1 -1 2 0 21
|
|
333 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 2 0 3 -1 -1 2 0 21
|
|
311 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21
|
|
318 CLK_000_D_0_ 3 -1 3 2 3 5 -1 -1 1 0 21
|
|
317 CLK_000_D_1_ 3 -1 5 2 5 6 -1 -1 1 0 21
|
|
316 inst_CLK_OUT_PRE_50 3 -1 6 2 2 6 -1 -1 1 0 21
|
|
314 inst_DTACK_D0 3 -1 6 2 2 5 -1 -1 1 0 21
|
|
372 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
371 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
370 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
364 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
302 inst_AS_030_000_SYNC 3 -1 5 1 5 -1 -1 7 0 21
|
|
377 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
374 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
373 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
379 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
375 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
369 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
306 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
361 CLK_000_N_SYNC_11_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
360 CLK_000_N_SYNC_10_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
359 CLK_000_N_SYNC_9_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
358 CLK_000_N_SYNC_8_ 3 -1 5 1 6 -1 -1 1 0 21
|
|
357 CLK_000_N_SYNC_7_ 3 -1 1 1 5 -1 -1 1 0 21
|
|
356 CLK_000_N_SYNC_6_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
355 CLK_000_N_SYNC_5_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
354 CLK_000_N_SYNC_4_ 3 -1 0 1 2 -1 -1 1 0 21
|
|
353 CLK_000_N_SYNC_3_ 3 -1 2 1 0 -1 -1 1 0 21
|
|
352 CLK_000_N_SYNC_2_ 3 -1 1 1 2 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_1_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_0_ 3 -1 5 1 6 -1 -1 1 0 21
|
|
349 CLK_000_P_SYNC_9_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
348 CLK_000_P_SYNC_8_ 3 -1 2 1 2 -1 -1 1 0 21
|
|
347 CLK_000_P_SYNC_7_ 3 -1 4 1 2 -1 -1 1 0 21
|
|
346 CLK_000_P_SYNC_6_ 3 -1 0 1 4 -1 -1 1 0 21
|
|
345 CLK_000_P_SYNC_5_ 3 -1 3 1 0 -1 -1 1 0 21
|
|
344 CLK_000_P_SYNC_4_ 3 -1 3 1 3 -1 -1 1 0 21
|
|
343 CLK_000_P_SYNC_3_ 3 -1 4 1 3 -1 -1 1 0 21
|
|
342 CLK_000_P_SYNC_2_ 3 -1 0 1 4 -1 -1 1 0 21
|
|
341 CLK_000_P_SYNC_1_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
340 CLK_000_P_SYNC_0_ 3 -1 5 1 0 -1 -1 1 0 21
|
|
331 CLK_000_D_9_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
330 CLK_000_D_8_ 3 -1 5 1 7 -1 -1 1 0 21
|
|
329 CLK_000_D_7_ 3 -1 2 1 5 -1 -1 1 0 21
|
|
328 CLK_000_D_6_ 3 -1 7 1 2 -1 -1 1 0 21
|
|
327 CLK_000_D_5_ 3 -1 6 1 7 -1 -1 1 0 21
|
|
326 CLK_000_D_4_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
325 CLK_000_D_3_ 3 -1 3 1 3 -1 -1 1 0 21
|
|
324 CLK_000_D_2_ 3 -1 6 1 3 -1 -1 1 0 21
|
|
323 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
322 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
321 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
293 N_377_i 3 -1 3 1 5 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 4 5 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 4 5 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 4 5 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 4 5 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 4 5 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 4 5 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
66 IPL_0_ 1 -1 -1 2 0 1 66 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
59 A1 1 -1 -1 1 0 59 -1
|
|
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
|
35 VPA 1 -1 -1 1 0 35 -1
|
|
29 DTACK 1 -1 -1 1 6 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 1 13 -1
|
|
10 CLK_000 1 -1 -1 1 3 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
149 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
79 RW_000 5 372 7 3 0 4 6 79 -1 3 0 21
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
40 BERR 5 -1 4 3 2 5 7 40 -1 1 0 21
|
|
70 RW 5 380 6 2 2 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
68 A0 5 375 6 1 0 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 371 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 374 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 373 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 378 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 377 7 0 82 -1 3 0 21
|
|
34 VMA 5 379 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 376 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
377 RN_BGACK_030 3 82 7 7 0 2 3 4 5 6 7 82 -1 3 0 21
|
|
317 inst_RESET_OUT 3 -1 1 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
300 inst_nEXP_SPACE_D0reg 3 -1 0 6 0 3 4 5 6 7 -1 -1 1 0 21
|
|
321 CLK_000_P_SYNC_10_ 3 -1 2 5 0 2 3 5 7 -1 -1 1 0 21
|
|
299 inst_AS_030_D0 3 -1 7 5 2 3 4 5 7 -1 -1 1 0 21
|
|
369 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 15 0 21
|
|
337 CLK_000_N_SYNC_12_ 3 -1 1 4 1 3 4 5 -1 -1 1 0 21
|
|
294 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 4 0 21
|
|
364 SM_AMIGA_6_ 3 -1 5 3 0 2 5 -1 -1 3 0 21
|
|
322 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21
|
|
295 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 3 0 21
|
|
293 cpu_est_1_ 3 -1 2 3 2 3 6 -1 -1 3 0 21
|
|
333 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 2 0 21
|
|
363 inst_CLK_000_NE_D0 3 -1 4 3 2 3 5 -1 -1 1 0 21
|
|
313 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
|
310 inst_VPA_D 3 -1 3 3 2 3 5 -1 -1 1 0 21
|
|
304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
367 SM_AMIGA_3_ 3 -1 2 2 2 5 -1 -1 5 0 21
|
|
336 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21
|
|
368 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 4 0 21
|
|
379 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21
|
|
366 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
335 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21
|
|
312 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21
|
|
309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
334 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
311 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21
|
|
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21
|
|
297 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
|
|
296 cpu_est_0_ 3 -1 3 2 2 3 -1 -1 2 0 21
|
|
320 CLK_000_D_0_ 3 -1 1 2 3 5 -1 -1 1 0 21
|
|
316 inst_DTACK_D0 3 -1 0 2 2 5 -1 -1 1 0 21
|
|
303 inst_BGACK_030_INT_D 3 -1 7 2 5 6 -1 -1 1 0 21
|
|
374 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
373 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
371 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
365 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
301 inst_AS_030_000_SYNC 3 -1 5 1 5 -1 -1 7 0 21
|
|
378 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
339 RST_DLY_1_ 3 -1 1 1 1 -1 -1 4 0 21
|
|
375 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
372 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
338 RST_DLY_0_ 3 -1 1 1 1 -1 -1 3 0 21
|
|
307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
380 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
376 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
370 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
340 RST_DLY_2_ 3 -1 1 1 1 -1 -1 2 0 21
|
|
306 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
362 CLK_000_N_SYNC_11_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
361 CLK_000_N_SYNC_10_ 3 -1 5 1 6 -1 -1 1 0 21
|
|
360 CLK_000_N_SYNC_9_ 3 -1 0 1 5 -1 -1 1 0 21
|
|
359 CLK_000_N_SYNC_8_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
358 CLK_000_N_SYNC_7_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
357 CLK_000_N_SYNC_6_ 3 -1 1 1 3 -1 -1 1 0 21
|
|
356 CLK_000_N_SYNC_5_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
355 CLK_000_N_SYNC_4_ 3 -1 2 1 2 -1 -1 1 0 21
|
|
354 CLK_000_N_SYNC_3_ 3 -1 3 1 2 -1 -1 1 0 21
|
|
353 CLK_000_N_SYNC_2_ 3 -1 3 1 3 -1 -1 1 0 21
|
|
352 CLK_000_N_SYNC_1_ 3 -1 3 1 3 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_0_ 3 -1 5 1 3 -1 -1 1 0 21
|
|
350 CLK_000_P_SYNC_9_ 3 -1 6 1 2 -1 -1 1 0 21
|
|
349 CLK_000_P_SYNC_8_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
348 CLK_000_P_SYNC_7_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
347 CLK_000_P_SYNC_6_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
346 CLK_000_P_SYNC_5_ 3 -1 1 1 0 -1 -1 1 0 21
|
|
345 CLK_000_P_SYNC_4_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
344 CLK_000_P_SYNC_3_ 3 -1 6 1 3 -1 -1 1 0 21
|
|
343 CLK_000_P_SYNC_2_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
342 CLK_000_P_SYNC_1_ 3 -1 0 1 6 -1 -1 1 0 21
|
|
341 CLK_000_P_SYNC_0_ 3 -1 5 1 0 -1 -1 1 0 21
|
|
332 CLK_000_D_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
331 CLK_000_D_7_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
330 CLK_000_D_6_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
329 CLK_000_D_5_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
328 CLK_000_D_4_ 3 -1 2 1 3 -1 -1 1 0 21
|
|
327 CLK_000_D_3_ 3 -1 1 1 2 -1 -1 1 0 21
|
|
326 CLK_000_D_2_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
325 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
324 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
323 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
319 CLK_000_D_1_ 3 -1 5 1 5 -1 -1 1 0 21
|
|
318 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
315 CLK_000_D_9_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
314 CLK_000_D_8_ 3 -1 0 1 7 -1 -1 1 0 21
|
|
302 N_343_i 3 -1 2 1 5 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 4 5 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 4 5 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 4 5 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 4 5 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 4 5 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 4 5 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
67 IPL_2_ 1 -1 -1 2 1 2 67 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 6 66 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 3 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
59 A1 1 -1 -1 1 6 59 -1
|
|
35 VPA 1 -1 -1 1 3 35 -1
|
|
29 DTACK 1 -1 -1 1 0 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 0 13 -1
|
|
10 CLK_000 1 -1 -1 1 1 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
148 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 4 1 2 5 7 40 -1 1 0 21
|
|
79 RW_000 5 371 7 3 0 4 6 79 -1 3 0 21
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
70 RW 5 379 6 2 5 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
68 A0 5 374 6 1 1 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 370 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 373 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 372 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 377 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 376 7 0 82 -1 3 0 21
|
|
34 VMA 5 378 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 375 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
376 RN_BGACK_030 3 82 7 7 0 2 3 4 5 6 7 82 -1 3 0 21
|
|
300 inst_nEXP_SPACE_D0reg 3 -1 0 7 0 2 3 4 5 6 7 -1 -1 1 0 21
|
|
317 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
321 CLK_000_P_SYNC_10_ 3 -1 5 5 0 2 3 5 7 -1 -1 1 0 21
|
|
299 inst_AS_030_D0 3 -1 7 5 1 3 4 5 7 -1 -1 1 0 21
|
|
368 SM_AMIGA_i_7_ 3 -1 2 4 2 3 5 7 -1 -1 15 0 21
|
|
322 SM_AMIGA_5_ 3 -1 5 4 1 2 5 7 -1 -1 3 0 21
|
|
294 cpu_est_2_ 3 -1 3 3 2 3 6 -1 -1 4 0 21
|
|
363 SM_AMIGA_6_ 3 -1 2 3 1 2 5 -1 -1 3 0 21
|
|
295 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 3 0 21
|
|
293 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 3 0 21
|
|
332 SM_AMIGA_0_ 3 -1 2 3 2 5 7 -1 -1 2 0 21
|
|
336 CLK_000_N_SYNC_12_ 3 -1 2 3 2 3 5 -1 -1 1 0 21
|
|
320 CLK_000_D_0_ 3 -1 3 3 2 3 6 -1 -1 1 0 21
|
|
319 CLK_000_D_1_ 3 -1 2 3 2 5 6 -1 -1 1 0 21
|
|
313 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
|
303 inst_BGACK_030_INT_D 3 -1 7 3 0 5 6 -1 -1 1 0 21
|
|
304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
302 inst_AS_030_000_SYNC 3 -1 5 2 2 5 -1 -1 7 0 21
|
|
335 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 5 0 21
|
|
378 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21
|
|
365 SM_AMIGA_1_ 3 -1 2 2 2 7 -1 -1 3 0 21
|
|
334 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21
|
|
312 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21
|
|
309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
333 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 2 0 3 -1 -1 2 0 21
|
|
311 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21
|
|
297 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21
|
|
296 cpu_est_0_ 3 -1 3 2 2 3 -1 -1 2 0 21
|
|
362 inst_CLK_000_NE_D0 3 -1 2 2 2 3 -1 -1 1 0 21
|
|
310 inst_VPA_D 3 -1 1 2 2 3 -1 -1 1 0 21
|
|
373 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
372 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
370 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
364 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
366 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21
|
|
377 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
367 SM_AMIGA_2_ 3 -1 2 1 2 -1 -1 4 0 21
|
|
338 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21
|
|
374 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
371 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
337 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21
|
|
307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
379 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
375 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
369 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
339 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21
|
|
306 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
361 CLK_000_N_SYNC_11_ 3 -1 6 1 2 -1 -1 1 0 21
|
|
360 CLK_000_N_SYNC_10_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
359 CLK_000_N_SYNC_9_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
358 CLK_000_N_SYNC_8_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
357 CLK_000_N_SYNC_7_ 3 -1 5 1 6 -1 -1 1 0 21
|
|
356 CLK_000_N_SYNC_6_ 3 -1 1 1 5 -1 -1 1 0 21
|
|
355 CLK_000_N_SYNC_5_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
354 CLK_000_N_SYNC_4_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
353 CLK_000_N_SYNC_3_ 3 -1 0 1 6 -1 -1 1 0 21
|
|
352 CLK_000_N_SYNC_2_ 3 -1 1 1 0 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_1_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_0_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
349 CLK_000_P_SYNC_9_ 3 -1 1 1 5 -1 -1 1 0 21
|
|
348 CLK_000_P_SYNC_8_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
347 CLK_000_P_SYNC_7_ 3 -1 5 1 0 -1 -1 1 0 21
|
|
346 CLK_000_P_SYNC_6_ 3 -1 2 1 5 -1 -1 1 0 21
|
|
345 CLK_000_P_SYNC_5_ 3 -1 6 1 2 -1 -1 1 0 21
|
|
344 CLK_000_P_SYNC_4_ 3 -1 0 1 6 -1 -1 1 0 21
|
|
343 CLK_000_P_SYNC_3_ 3 -1 4 1 0 -1 -1 1 0 21
|
|
342 CLK_000_P_SYNC_2_ 3 -1 3 1 4 -1 -1 1 0 21
|
|
341 CLK_000_P_SYNC_1_ 3 -1 6 1 3 -1 -1 1 0 21
|
|
340 CLK_000_P_SYNC_0_ 3 -1 2 1 6 -1 -1 1 0 21
|
|
331 CLK_000_D_9_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
330 CLK_000_D_6_ 3 -1 5 1 6 -1 -1 1 0 21
|
|
329 CLK_000_D_5_ 3 -1 5 1 5 -1 -1 1 0 21
|
|
328 CLK_000_D_4_ 3 -1 1 1 5 -1 -1 1 0 21
|
|
327 CLK_000_D_3_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
326 CLK_000_D_2_ 3 -1 5 1 0 -1 -1 1 0 21
|
|
325 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
324 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
323 IPL_D0_0_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
318 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
316 inst_DTACK_D0 3 -1 0 1 2 -1 -1 1 0 21
|
|
315 CLK_000_D_8_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
314 CLK_000_D_7_ 3 -1 6 1 7 -1 -1 1 0 21
|
|
301 N_343_i 3 -1 2 1 2 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 4 5 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 4 5 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 4 5 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 4 5 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 4 5 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 4 5 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 5 66 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
59 A1 1 -1 -1 1 0 59 -1
|
|
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
|
35 VPA 1 -1 -1 1 1 35 -1
|
|
29 DTACK 1 -1 -1 1 0 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 0 13 -1
|
|
10 CLK_000 1 -1 -1 1 3 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
148 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21
|
|
79 RW_000 5 371 7 3 0 4 6 79 -1 3 0 21
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
68 A0 5 372 6 2 1 2 68 -1 3 0 21
|
|
70 RW 5 379 6 2 2 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 370 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 374 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 373 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 377 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 376 7 0 82 -1 3 0 21
|
|
34 VMA 5 378 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 375 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
376 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 3 0 21
|
|
317 inst_RESET_OUT 3 -1 1 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
301 inst_nEXP_SPACE_D0reg 3 -1 1 6 0 3 4 5 6 7 -1 -1 1 0 21
|
|
367 SM_AMIGA_i_7_ 3 -1 5 5 0 2 3 5 7 -1 -1 14 0 21
|
|
321 CLK_000_P_SYNC_10_ 3 -1 3 5 0 2 3 5 7 -1 -1 1 0 21
|
|
300 inst_AS_030_D0 3 -1 7 5 0 2 3 4 7 -1 -1 1 0 21
|
|
296 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 4 0 21
|
|
362 SM_AMIGA_6_ 3 -1 5 3 1 2 5 -1 -1 3 0 21
|
|
322 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21
|
|
297 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
295 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
332 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 2 0 21
|
|
368 CLK_000_N_SYNC_12_ 3 -1 3 3 1 3 5 -1 -1 1 0 21
|
|
320 CLK_000_D_0_ 3 -1 1 3 0 3 5 -1 -1 1 0 21
|
|
313 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
|
304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
302 inst_AS_030_000_SYNC 3 -1 0 2 0 5 -1 -1 7 0 21
|
|
335 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21
|
|
378 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
364 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
334 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21
|
|
312 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21
|
|
309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
333 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
311 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
|
|
294 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 2 0 21
|
|
319 CLK_000_D_1_ 3 -1 3 2 0 5 -1 -1 1 0 21
|
|
314 CLK_000_D_6_ 3 -1 2 2 1 7 -1 -1 1 0 21
|
|
310 inst_VPA_D 3 -1 6 2 3 5 -1 -1 1 0 21
|
|
303 inst_BGACK_030_INT_D 3 -1 7 2 0 6 -1 -1 1 0 21
|
|
374 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
373 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
370 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
363 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
365 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21
|
|
377 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
366 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
337 RST_DLY_1_ 3 -1 1 1 1 -1 -1 4 0 21
|
|
293 N_202_i 3 -1 5 1 5 -1 -1 4 0 21
|
|
372 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
371 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
336 RST_DLY_0_ 3 -1 1 1 1 -1 -1 3 0 21
|
|
307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
379 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
375 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
369 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
338 RST_DLY_2_ 3 -1 1 1 1 -1 -1 2 0 21
|
|
306 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
361 inst_CLK_000_NE_D0 3 -1 3 1 5 -1 -1 1 0 21
|
|
360 CLK_000_N_SYNC_11_ 3 -1 2 1 3 -1 -1 1 0 21
|
|
359 CLK_000_N_SYNC_10_ 3 -1 0 1 2 -1 -1 1 0 21
|
|
358 CLK_000_N_SYNC_9_ 3 -1 3 1 0 -1 -1 1 0 21
|
|
357 CLK_000_N_SYNC_8_ 3 -1 6 1 3 -1 -1 1 0 21
|
|
356 CLK_000_N_SYNC_7_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
355 CLK_000_N_SYNC_6_ 3 -1 6 1 3 -1 -1 1 0 21
|
|
354 CLK_000_N_SYNC_5_ 3 -1 2 1 6 -1 -1 1 0 21
|
|
353 CLK_000_N_SYNC_4_ 3 -1 1 1 2 -1 -1 1 0 21
|
|
352 CLK_000_N_SYNC_3_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_2_ 3 -1 4 1 2 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_1_ 3 -1 2 1 4 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_0_ 3 -1 0 1 2 -1 -1 1 0 21
|
|
348 CLK_000_P_SYNC_9_ 3 -1 0 1 3 -1 -1 1 0 21
|
|
347 CLK_000_P_SYNC_8_ 3 -1 2 1 0 -1 -1 1 0 21
|
|
346 CLK_000_P_SYNC_7_ 3 -1 3 1 2 -1 -1 1 0 21
|
|
345 CLK_000_P_SYNC_6_ 3 -1 2 1 3 -1 -1 1 0 21
|
|
344 CLK_000_P_SYNC_5_ 3 -1 6 1 2 -1 -1 1 0 21
|
|
343 CLK_000_P_SYNC_4_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
342 CLK_000_P_SYNC_3_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
341 CLK_000_P_SYNC_2_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
340 CLK_000_P_SYNC_1_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
339 CLK_000_P_SYNC_0_ 3 -1 0 1 3 -1 -1 1 0 21
|
|
331 CLK_000_D_8_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
330 CLK_000_D_7_ 3 -1 1 1 7 -1 -1 1 0 21
|
|
329 CLK_000_D_5_ 3 -1 2 1 2 -1 -1 1 0 21
|
|
328 CLK_000_D_4_ 3 -1 1 1 2 -1 -1 1 0 21
|
|
327 CLK_000_D_3_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
326 CLK_000_D_2_ 3 -1 0 1 6 -1 -1 1 0 21
|
|
325 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
324 IPL_D0_1_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
323 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
318 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
316 inst_DTACK_D0 3 -1 2 1 5 -1 -1 1 0 21
|
|
315 CLK_000_D_9_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 0 4 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 0 4 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 0 4 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 0 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 0 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 0 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
67 IPL_2_ 1 -1 -1 2 1 2 67 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 3 66 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 5 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
59 A1 1 -1 -1 1 6 59 -1
|
|
35 VPA 1 -1 -1 1 6 35 -1
|
|
29 DTACK 1 -1 -1 1 2 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 1 13 -1
|
|
10 CLK_000 1 -1 -1 1 1 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
146 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 4 2 5 6 7 40 -1 1 0 21
|
|
79 RW_000 5 371 7 3 0 4 6 79 -1 3 0 21
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
68 A0 5 372 6 2 0 6 68 -1 3 0 21
|
|
70 RW 5 377 6 2 2 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 368 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 370 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 369 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 375 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 374 7 0 82 -1 3 0 21
|
|
34 VMA 5 376 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 373 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
374 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21
|
|
317 inst_RESET_OUT 3 -1 1 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
321 CLK_000_P_SYNC_10_ 3 -1 0 6 0 2 3 5 6 7 -1 -1 1 0 21
|
|
301 inst_nEXP_SPACE_D0reg 3 -1 5 6 0 3 4 5 6 7 -1 -1 1 0 21
|
|
300 inst_AS_030_D0 3 -1 7 5 2 3 4 5 7 -1 -1 1 0 21
|
|
366 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 15 0 21
|
|
361 SM_AMIGA_6_ 3 -1 5 4 0 2 5 6 -1 -1 3 0 21
|
|
330 SM_AMIGA_0_ 3 -1 6 4 2 5 6 7 -1 -1 2 0 21
|
|
334 CLK_000_N_SYNC_12_ 3 -1 1 4 1 3 5 6 -1 -1 1 0 21
|
|
294 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 4 0 21
|
|
363 SM_AMIGA_1_ 3 -1 5 3 5 6 7 -1 -1 3 0 21
|
|
322 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21
|
|
295 cpu_est_3_ 3 -1 2 3 2 3 6 -1 -1 3 0 21
|
|
293 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 3 0 21
|
|
360 inst_CLK_000_NE_D0 3 -1 6 3 2 3 5 -1 -1 1 0 21
|
|
320 CLK_000_D_0_ 3 -1 5 3 3 4 5 -1 -1 1 0 21
|
|
319 CLK_000_D_1_ 3 -1 4 3 0 3 5 -1 -1 1 0 21
|
|
313 inst_CLK_OUT_PRE_D 3 -1 5 3 1 6 7 -1 -1 1 0 21
|
|
310 inst_VPA_D 3 -1 3 3 2 3 5 -1 -1 1 0 21
|
|
303 inst_BGACK_030_INT_D 3 -1 2 3 1 5 6 -1 -1 1 0 21
|
|
304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
364 SM_AMIGA_3_ 3 -1 2 2 2 5 -1 -1 5 0 21
|
|
333 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21
|
|
365 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 4 0 21
|
|
376 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21
|
|
332 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21
|
|
312 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21
|
|
309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
331 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
311 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
306 CYCLE_DMA_0_ 3 -1 7 2 0 7 -1 -1 2 0 21
|
|
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21
|
|
297 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
|
|
296 cpu_est_0_ 3 -1 3 2 2 3 -1 -1 2 0 21
|
|
316 inst_DTACK_D0 3 -1 0 2 2 5 -1 -1 1 0 21
|
|
370 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
369 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
368 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
362 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
302 inst_AS_030_000_SYNC 3 -1 5 1 5 -1 -1 7 0 21
|
|
375 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
336 RST_DLY_1_ 3 -1 1 1 1 -1 -1 4 0 21
|
|
372 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
371 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
335 RST_DLY_0_ 3 -1 1 1 1 -1 -1 3 0 21
|
|
307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
377 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
373 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
367 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
337 RST_DLY_2_ 3 -1 1 1 1 -1 -1 2 0 21
|
|
359 CLK_000_N_SYNC_11_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
358 CLK_000_N_SYNC_10_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
357 CLK_000_N_SYNC_9_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
356 CLK_000_N_SYNC_8_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
355 CLK_000_N_SYNC_7_ 3 -1 4 1 1 -1 -1 1 0 21
|
|
354 CLK_000_N_SYNC_6_ 3 -1 1 1 4 -1 -1 1 0 21
|
|
353 CLK_000_N_SYNC_5_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
352 CLK_000_N_SYNC_4_ 3 -1 0 1 3 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_3_ 3 -1 4 1 0 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_2_ 3 -1 6 1 4 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_1_ 3 -1 2 1 6 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_0_ 3 -1 5 1 2 -1 -1 1 0 21
|
|
347 CLK_000_P_SYNC_9_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
346 CLK_000_P_SYNC_8_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
345 CLK_000_P_SYNC_7_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
344 CLK_000_P_SYNC_6_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
343 CLK_000_P_SYNC_5_ 3 -1 3 1 3 -1 -1 1 0 21
|
|
342 CLK_000_P_SYNC_4_ 3 -1 0 1 3 -1 -1 1 0 21
|
|
341 CLK_000_P_SYNC_3_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
340 CLK_000_P_SYNC_2_ 3 -1 1 1 0 -1 -1 1 0 21
|
|
339 CLK_000_P_SYNC_1_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
338 CLK_000_P_SYNC_0_ 3 -1 3 1 2 -1 -1 1 0 21
|
|
329 CLK_000_D_7_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
328 CLK_000_D_4_ 3 -1 6 1 3 -1 -1 1 0 21
|
|
327 CLK_000_D_3_ 3 -1 2 1 6 -1 -1 1 0 21
|
|
326 CLK_000_D_2_ 3 -1 0 1 2 -1 -1 1 0 21
|
|
325 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
324 IPL_D0_1_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
323 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
318 inst_CLK_OUT_PRE_50 3 -1 5 1 5 -1 -1 1 0 21
|
|
315 CLK_000_D_6_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
314 CLK_000_D_5_ 3 -1 3 1 7 -1 -1 1 0 21
|
|
299 N_343_i 3 -1 2 1 5 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 4 5 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 4 5 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 4 5 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 4 5 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 4 5 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 4 5 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
67 IPL_2_ 1 -1 -1 2 1 2 67 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 3 66 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 2 0 1 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
59 A1 1 -1 -1 1 1 59 -1
|
|
35 VPA 1 -1 -1 1 3 35 -1
|
|
29 DTACK 1 -1 -1 1 0 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 5 13 -1
|
|
10 CLK_000 1 -1 -1 1 5 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
146 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 5 1 2 5 6 7 40 -1 1 0 21
|
|
79 RW_000 5 371 7 3 0 4 6 79 -1 3 0 21
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
68 A0 5 372 6 2 0 6 68 -1 3 0 21
|
|
70 RW 5 377 6 2 2 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 370 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 369 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 368 1 0 6 -1 10 0 21
|
|
82 BGACK_030 5 374 7 0 82 -1 3 0 21
|
|
34 VMA 5 376 3 0 34 -1 3 0 21
|
|
80 DSACK1 5 375 7 0 80 -1 2 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 373 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
374 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
315 inst_RESET_OUT 3 -1 5 7 0 1 3 4 5 6 7 -1 -1 2 0 21
|
|
319 CLK_000_P_SYNC_10_ 3 -1 5 6 0 2 3 5 6 7 -1 -1 1 0 21
|
|
301 inst_nEXP_SPACE_D0reg 3 -1 0 6 0 2 3 4 6 7 -1 -1 1 0 21
|
|
300 inst_AS_030_D0 3 -1 7 5 1 2 3 4 7 -1 -1 1 0 21
|
|
361 SM_AMIGA_6_ 3 -1 2 4 0 2 5 6 -1 -1 3 0 21
|
|
333 SM_AMIGA_1_ 3 -1 5 4 2 5 6 7 -1 -1 3 0 21
|
|
320 SM_AMIGA_5_ 3 -1 2 4 1 2 5 7 -1 -1 3 0 21
|
|
330 SM_AMIGA_0_ 3 -1 6 4 2 5 6 7 -1 -1 2 0 21
|
|
366 CLK_000_N_SYNC_12_ 3 -1 5 4 2 3 5 6 -1 -1 1 0 21
|
|
365 SM_AMIGA_i_7_ 3 -1 5 3 2 3 7 -1 -1 14 0 21
|
|
294 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 4 0 21
|
|
297 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
295 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
318 CLK_000_D_0_ 3 -1 6 3 2 3 6 -1 -1 1 0 21
|
|
317 CLK_000_D_1_ 3 -1 6 3 2 3 6 -1 -1 1 0 21
|
|
303 inst_BGACK_030_INT_D 3 -1 7 3 1 2 6 -1 -1 1 0 21
|
|
304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
363 SM_AMIGA_3_ 3 -1 5 2 2 5 -1 -1 5 0 21
|
|
334 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21
|
|
364 SM_AMIGA_2_ 3 -1 5 2 2 5 -1 -1 4 0 21
|
|
376 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
332 SM_AMIGA_4_ 3 -1 2 2 2 5 -1 -1 3 0 21
|
|
312 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21
|
|
309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
331 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
311 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21
|
|
296 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21
|
|
360 inst_CLK_000_NE_D0 3 -1 3 2 3 5 -1 -1 1 0 21
|
|
321 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21
|
|
310 inst_VPA_D 3 -1 7 2 3 5 -1 -1 1 0 21
|
|
370 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
369 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
368 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
362 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
302 inst_AS_030_000_SYNC 3 -1 2 1 2 -1 -1 7 0 21
|
|
336 RST_DLY_1_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
293 N_201_i 3 -1 2 1 5 -1 -1 4 0 21
|
|
372 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
371 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
335 RST_DLY_0_ 3 -1 5 1 5 -1 -1 3 0 21
|
|
307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
377 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
375 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21
|
|
373 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
367 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
337 RST_DLY_2_ 3 -1 5 1 5 -1 -1 2 0 21
|
|
306 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
359 CLK_000_N_SYNC_11_ 3 -1 4 1 5 -1 -1 1 0 21
|
|
358 CLK_000_N_SYNC_10_ 3 -1 2 1 4 -1 -1 1 0 21
|
|
357 CLK_000_N_SYNC_9_ 3 -1 6 1 2 -1 -1 1 0 21
|
|
356 CLK_000_N_SYNC_8_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
355 CLK_000_N_SYNC_7_ 3 -1 0 1 6 -1 -1 1 0 21
|
|
354 CLK_000_N_SYNC_6_ 3 -1 4 1 0 -1 -1 1 0 21
|
|
353 CLK_000_N_SYNC_5_ 3 -1 1 1 4 -1 -1 1 0 21
|
|
352 CLK_000_N_SYNC_4_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_3_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_2_ 3 -1 5 1 0 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_1_ 3 -1 1 1 5 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_0_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
347 CLK_000_P_SYNC_9_ 3 -1 6 1 5 -1 -1 1 0 21
|
|
346 CLK_000_P_SYNC_8_ 3 -1 0 1 6 -1 -1 1 0 21
|
|
345 CLK_000_P_SYNC_7_ 3 -1 1 1 0 -1 -1 1 0 21
|
|
344 CLK_000_P_SYNC_6_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
343 CLK_000_P_SYNC_5_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
342 CLK_000_P_SYNC_4_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
341 CLK_000_P_SYNC_3_ 3 -1 5 1 3 -1 -1 1 0 21
|
|
340 CLK_000_P_SYNC_2_ 3 -1 7 1 5 -1 -1 1 0 21
|
|
339 CLK_000_P_SYNC_1_ 3 -1 1 1 7 -1 -1 1 0 21
|
|
338 CLK_000_P_SYNC_0_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
329 CLK_000_D_7_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
328 CLK_000_D_5_ 3 -1 0 1 5 -1 -1 1 0 21
|
|
327 CLK_000_D_4_ 3 -1 1 1 0 -1 -1 1 0 21
|
|
326 CLK_000_D_3_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
325 CLK_000_D_2_ 3 -1 6 1 3 -1 -1 1 0 21
|
|
324 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
323 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
322 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
316 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
314 inst_DTACK_D0 3 -1 3 1 5 -1 -1 1 0 21
|
|
313 CLK_000_D_6_ 3 -1 5 1 7 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
67 IPL_2_ 1 -1 -1 2 0 1 67 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 3 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
|
63 CLK_030 1 -1 -1 1 0 63 -1
|
|
59 A1 1 -1 -1 1 1 59 -1
|
|
35 VPA 1 -1 -1 1 7 35 -1
|
|
29 DTACK 1 -1 -1 1 3 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 0 13 -1
|
|
10 CLK_000 1 -1 -1 1 6 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
147 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
41 AS_000 5 -1 4 4 0 1 4 7 41 -1 1 0 21
|
|
40 BERR 5 -1 4 4 2 5 6 7 40 -1 1 0 21
|
|
79 RW_000 5 372 7 3 0 4 6 79 -1 3 0 21
|
|
70 RW 5 378 6 2 2 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
68 A0 5 373 6 1 0 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 371 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 370 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 369 1 0 6 -1 10 0 21
|
|
82 BGACK_030 5 375 7 0 82 -1 3 0 21
|
|
34 VMA 5 377 3 0 34 -1 3 0 21
|
|
80 DSACK1 5 376 7 0 80 -1 2 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 374 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
375 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
315 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
301 inst_nEXP_SPACE_D0reg 3 -1 6 6 0 2 3 4 6 7 -1 -1 1 0 21
|
|
319 CLK_000_P_SYNC_10_ 3 -1 5 5 1 2 3 5 7 -1 -1 1 0 21
|
|
300 inst_AS_030_D0 3 -1 7 5 2 3 4 6 7 -1 -1 1 0 21
|
|
320 SM_AMIGA_5_ 3 -1 5 4 2 5 6 7 -1 -1 3 0 21
|
|
367 CLK_000_N_SYNC_12_ 3 -1 6 4 0 2 3 5 -1 -1 1 0 21
|
|
366 SM_AMIGA_i_7_ 3 -1 5 3 2 3 7 -1 -1 14 0 21
|
|
294 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
|
362 SM_AMIGA_6_ 3 -1 2 3 0 2 5 -1 -1 3 0 21
|
|
334 SM_AMIGA_1_ 3 -1 2 3 2 5 7 -1 -1 3 0 21
|
|
297 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
295 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
331 SM_AMIGA_0_ 3 -1 2 3 2 5 7 -1 -1 2 0 21
|
|
318 CLK_000_D_0_ 3 -1 3 3 2 3 4 -1 -1 1 0 21
|
|
303 inst_BGACK_030_INT_D 3 -1 7 3 1 2 6 -1 -1 1 0 21
|
|
304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
364 SM_AMIGA_3_ 3 -1 5 2 2 5 -1 -1 5 0 21
|
|
335 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21
|
|
365 SM_AMIGA_2_ 3 -1 5 2 2 5 -1 -1 4 0 21
|
|
377 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
333 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21
|
|
312 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21
|
|
309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
307 CYCLE_DMA_1_ 3 -1 1 2 0 1 -1 -1 3 0 21
|
|
332 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
311 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21
|
|
306 CYCLE_DMA_0_ 3 -1 1 2 0 1 -1 -1 2 0 21
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21
|
|
296 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 2 0 21
|
|
361 inst_CLK_000_NE_D0 3 -1 0 2 3 5 -1 -1 1 0 21
|
|
321 inst_CLK_OUT_PRE_D 3 -1 7 2 1 6 -1 -1 1 0 21
|
|
317 CLK_000_D_1_ 3 -1 2 2 2 4 -1 -1 1 0 21
|
|
310 inst_VPA_D 3 -1 0 2 3 5 -1 -1 1 0 21
|
|
371 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
370 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
369 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
363 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
302 inst_AS_030_000_SYNC 3 -1 2 1 2 -1 -1 7 0 21
|
|
337 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21
|
|
293 N_201_i 3 -1 2 1 5 -1 -1 4 0 21
|
|
373 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
372 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
336 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21
|
|
378 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
376 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21
|
|
374 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
368 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
338 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21
|
|
360 CLK_000_N_SYNC_11_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
359 CLK_000_N_SYNC_10_ 3 -1 5 1 3 -1 -1 1 0 21
|
|
358 CLK_000_N_SYNC_9_ 3 -1 0 1 5 -1 -1 1 0 21
|
|
357 CLK_000_N_SYNC_8_ 3 -1 4 1 0 -1 -1 1 0 21
|
|
356 CLK_000_N_SYNC_7_ 3 -1 0 1 4 -1 -1 1 0 21
|
|
355 CLK_000_N_SYNC_6_ 3 -1 5 1 0 -1 -1 1 0 21
|
|
354 CLK_000_N_SYNC_5_ 3 -1 5 1 5 -1 -1 1 0 21
|
|
353 CLK_000_N_SYNC_4_ 3 -1 0 1 5 -1 -1 1 0 21
|
|
352 CLK_000_N_SYNC_3_ 3 -1 3 1 0 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_2_ 3 -1 1 1 3 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_1_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_0_ 3 -1 4 1 0 -1 -1 1 0 21
|
|
348 CLK_000_P_SYNC_9_ 3 -1 6 1 5 -1 -1 1 0 21
|
|
347 CLK_000_P_SYNC_8_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
346 CLK_000_P_SYNC_7_ 3 -1 5 1 6 -1 -1 1 0 21
|
|
345 CLK_000_P_SYNC_6_ 3 -1 1 1 5 -1 -1 1 0 21
|
|
344 CLK_000_P_SYNC_5_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
343 CLK_000_P_SYNC_4_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
342 CLK_000_P_SYNC_3_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
341 CLK_000_P_SYNC_2_ 3 -1 6 1 5 -1 -1 1 0 21
|
|
340 CLK_000_P_SYNC_1_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
339 CLK_000_P_SYNC_0_ 3 -1 4 1 6 -1 -1 1 0 21
|
|
330 CLK_000_D_8_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
329 CLK_000_D_6_ 3 -1 5 1 2 -1 -1 1 0 21
|
|
328 CLK_000_D_5_ 3 -1 0 1 5 -1 -1 1 0 21
|
|
327 CLK_000_D_4_ 3 -1 1 1 0 -1 -1 1 0 21
|
|
326 CLK_000_D_3_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
325 CLK_000_D_2_ 3 -1 4 1 5 -1 -1 1 0 21
|
|
324 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
323 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
322 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
316 inst_CLK_OUT_PRE_50 3 -1 7 1 7 -1 -1 1 0 21
|
|
314 inst_DTACK_D0 3 -1 1 1 5 -1 -1 1 0 21
|
|
313 CLK_000_D_7_ 3 -1 2 1 7 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
59 A1 1 -1 -1 2 1 6 59 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 6 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
|
63 CLK_030 1 -1 -1 1 0 63 -1
|
|
35 VPA 1 -1 -1 1 0 35 -1
|
|
29 DTACK 1 -1 -1 1 1 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 6 13 -1
|
|
10 CLK_000 1 -1 -1 1 3 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
140 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 5 0 1 2 5 7 40 -1 1 0 21
|
|
79 RW_000 5 365 7 3 0 4 6 79 -1 3 0 21
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
68 A0 5 366 6 2 0 6 68 -1 3 0 21
|
|
70 RW 5 371 6 2 1 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 363 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 364 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 362 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 369 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 368 7 0 82 -1 3 0 21
|
|
34 VMA 5 370 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 367 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
368 RN_BGACK_030 3 82 7 7 0 2 3 4 5 6 7 82 -1 3 0 21
|
|
300 inst_nEXP_SPACE_D0reg 3 -1 5 7 0 2 3 4 5 6 7 -1 -1 1 0 21
|
|
314 inst_RESET_OUT 3 -1 1 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
359 SM_AMIGA_i_7_ 3 -1 2 5 1 2 3 5 7 -1 -1 15 0 21
|
|
318 CLK_000_P_SYNC_10_ 3 -1 5 5 0 1 2 3 7 -1 -1 1 0 21
|
|
299 inst_AS_030_D0 3 -1 7 5 1 3 4 5 7 -1 -1 1 0 21
|
|
354 SM_AMIGA_6_ 3 -1 2 4 0 1 2 6 -1 -1 3 0 21
|
|
323 SM_AMIGA_0_ 3 -1 0 4 0 1 2 7 -1 -1 2 0 21
|
|
327 CLK_000_N_SYNC_12_ 3 -1 0 4 0 1 2 3 -1 -1 1 0 21
|
|
293 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 4 0 21
|
|
356 SM_AMIGA_1_ 3 -1 2 3 0 2 7 -1 -1 3 0 21
|
|
319 SM_AMIGA_5_ 3 -1 2 3 1 2 7 -1 -1 3 0 21
|
|
296 cpu_est_1_ 3 -1 6 3 2 3 6 -1 -1 3 0 21
|
|
294 cpu_est_3_ 3 -1 2 3 2 3 6 -1 -1 3 0 21
|
|
295 cpu_est_0_ 3 -1 2 3 2 3 6 -1 -1 2 0 21
|
|
317 CLK_000_D_0_ 3 -1 6 3 2 3 5 -1 -1 1 0 21
|
|
312 inst_CLK_OUT_PRE_D 3 -1 6 3 1 6 7 -1 -1 1 0 21
|
|
303 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
301 inst_AS_030_000_SYNC 3 -1 5 2 2 5 -1 -1 7 0 21
|
|
326 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 5 0 21
|
|
370 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21
|
|
325 SM_AMIGA_4_ 3 -1 1 2 1 2 -1 -1 3 0 21
|
|
311 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21
|
|
308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
324 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 2 3 5 -1 -1 2 0 21
|
|
310 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21
|
|
297 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21
|
|
353 inst_CLK_000_NE_D0 3 -1 2 2 2 6 -1 -1 1 0 21
|
|
316 CLK_000_D_1_ 3 -1 3 2 2 5 -1 -1 1 0 21
|
|
315 inst_CLK_OUT_PRE_50 3 -1 2 2 2 6 -1 -1 1 0 21
|
|
309 inst_VPA_D 3 -1 5 2 2 3 -1 -1 1 0 21
|
|
302 inst_BGACK_030_INT_D 3 -1 7 2 5 6 -1 -1 1 0 21
|
|
364 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
363 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
362 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
304 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
355 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
357 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21
|
|
369 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
358 SM_AMIGA_2_ 3 -1 2 1 2 -1 -1 4 0 21
|
|
329 RST_DLY_1_ 3 -1 1 1 1 -1 -1 4 0 21
|
|
366 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
365 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
328 RST_DLY_0_ 3 -1 1 1 1 -1 -1 3 0 21
|
|
306 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
371 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
367 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
330 RST_DLY_2_ 3 -1 1 1 1 -1 -1 2 0 21
|
|
305 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
360 N_319 3 -1 3 1 2 -1 -1 1 0 21
|
|
352 CLK_000_N_SYNC_11_ 3 -1 7 1 0 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_9_ 3 -1 4 1 7 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_8_ 3 -1 6 1 4 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_7_ 3 -1 5 1 6 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_6_ 3 -1 4 1 5 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_5_ 3 -1 0 1 4 -1 -1 1 0 21
|
|
345 CLK_000_N_SYNC_4_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
344 CLK_000_N_SYNC_3_ 3 -1 5 1 6 -1 -1 1 0 21
|
|
343 CLK_000_N_SYNC_2_ 3 -1 0 1 5 -1 -1 1 0 21
|
|
342 CLK_000_N_SYNC_1_ 3 -1 5 1 0 -1 -1 1 0 21
|
|
341 CLK_000_N_SYNC_0_ 3 -1 5 1 5 -1 -1 1 0 21
|
|
340 CLK_000_P_SYNC_9_ 3 -1 4 1 5 -1 -1 1 0 21
|
|
339 CLK_000_P_SYNC_8_ 3 -1 3 1 4 -1 -1 1 0 21
|
|
338 CLK_000_P_SYNC_7_ 3 -1 1 1 3 -1 -1 1 0 21
|
|
337 CLK_000_P_SYNC_6_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
336 CLK_000_P_SYNC_5_ 3 -1 5 1 0 -1 -1 1 0 21
|
|
335 CLK_000_P_SYNC_4_ 3 -1 1 1 5 -1 -1 1 0 21
|
|
334 CLK_000_P_SYNC_3_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
333 CLK_000_P_SYNC_2_ 3 -1 3 1 3 -1 -1 1 0 21
|
|
332 CLK_000_P_SYNC_1_ 3 -1 3 1 3 -1 -1 1 0 21
|
|
331 CLK_000_P_SYNC_0_ 3 -1 2 1 3 -1 -1 1 0 21
|
|
322 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
321 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
320 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
313 inst_DTACK_D0 3 -1 3 1 2 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 4 5 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 4 5 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 4 5 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 4 5 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 4 5 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 4 5 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
67 IPL_2_ 1 -1 -1 2 0 1 67 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 6 66 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 3 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
59 A1 1 -1 -1 1 5 59 -1
|
|
35 VPA 1 -1 -1 1 5 35 -1
|
|
29 DTACK 1 -1 -1 1 3 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 5 13 -1
|
|
10 CLK_000 1 -1 -1 1 6 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
140 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 5 0 1 2 5 7 40 -1 1 0 21
|
|
79 RW_000 5 365 7 3 0 4 6 79 -1 3 0 21
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
68 A0 5 366 6 2 0 6 68 -1 3 0 21
|
|
70 RW 5 371 6 2 1 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 363 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 364 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 362 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 369 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 368 7 0 82 -1 3 0 21
|
|
34 VMA 5 370 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 367 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
368 RN_BGACK_030 3 82 7 7 0 2 3 4 5 6 7 82 -1 3 0 21
|
|
300 inst_nEXP_SPACE_D0reg 3 -1 5 7 0 2 3 4 5 6 7 -1 -1 1 0 21
|
|
314 inst_RESET_OUT 3 -1 1 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
359 SM_AMIGA_i_7_ 3 -1 2 5 1 2 3 5 7 -1 -1 15 0 21
|
|
318 CLK_000_P_SYNC_10_ 3 -1 5 5 0 1 2 3 7 -1 -1 1 0 21
|
|
299 inst_AS_030_D0 3 -1 7 5 1 3 4 5 7 -1 -1 1 0 21
|
|
354 SM_AMIGA_6_ 3 -1 2 4 0 1 2 6 -1 -1 3 0 21
|
|
323 SM_AMIGA_0_ 3 -1 0 4 0 1 2 7 -1 -1 2 0 21
|
|
327 CLK_000_N_SYNC_12_ 3 -1 0 4 0 1 2 3 -1 -1 1 0 21
|
|
293 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 4 0 21
|
|
356 SM_AMIGA_1_ 3 -1 2 3 0 2 7 -1 -1 3 0 21
|
|
319 SM_AMIGA_5_ 3 -1 2 3 1 2 7 -1 -1 3 0 21
|
|
296 cpu_est_1_ 3 -1 6 3 2 3 6 -1 -1 3 0 21
|
|
294 cpu_est_3_ 3 -1 2 3 2 3 6 -1 -1 3 0 21
|
|
295 cpu_est_0_ 3 -1 2 3 2 3 6 -1 -1 2 0 21
|
|
317 CLK_000_D_0_ 3 -1 6 3 2 3 5 -1 -1 1 0 21
|
|
312 inst_CLK_OUT_PRE_D 3 -1 6 3 1 6 7 -1 -1 1 0 21
|
|
303 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
301 inst_AS_030_000_SYNC 3 -1 5 2 2 5 -1 -1 7 0 21
|
|
326 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 5 0 21
|
|
370 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21
|
|
325 SM_AMIGA_4_ 3 -1 1 2 1 2 -1 -1 3 0 21
|
|
311 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21
|
|
308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
324 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 2 3 5 -1 -1 2 0 21
|
|
310 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21
|
|
297 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21
|
|
353 inst_CLK_000_NE_D0 3 -1 2 2 2 6 -1 -1 1 0 21
|
|
316 CLK_000_D_1_ 3 -1 3 2 2 5 -1 -1 1 0 21
|
|
315 inst_CLK_OUT_PRE_50 3 -1 2 2 2 6 -1 -1 1 0 21
|
|
309 inst_VPA_D 3 -1 5 2 2 3 -1 -1 1 0 21
|
|
302 inst_BGACK_030_INT_D 3 -1 7 2 5 6 -1 -1 1 0 21
|
|
364 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
363 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
362 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
304 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
355 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
357 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21
|
|
369 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
358 SM_AMIGA_2_ 3 -1 2 1 2 -1 -1 4 0 21
|
|
329 RST_DLY_1_ 3 -1 1 1 1 -1 -1 4 0 21
|
|
366 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
|
365 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
328 RST_DLY_0_ 3 -1 1 1 1 -1 -1 3 0 21
|
|
306 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
371 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
367 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
330 RST_DLY_2_ 3 -1 1 1 1 -1 -1 2 0 21
|
|
305 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
360 N_319 3 -1 3 1 2 -1 -1 1 0 21
|
|
352 CLK_000_N_SYNC_11_ 3 -1 7 1 0 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_9_ 3 -1 4 1 7 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_8_ 3 -1 6 1 4 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_7_ 3 -1 5 1 6 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_6_ 3 -1 4 1 5 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_5_ 3 -1 0 1 4 -1 -1 1 0 21
|
|
345 CLK_000_N_SYNC_4_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
344 CLK_000_N_SYNC_3_ 3 -1 5 1 6 -1 -1 1 0 21
|
|
343 CLK_000_N_SYNC_2_ 3 -1 0 1 5 -1 -1 1 0 21
|
|
342 CLK_000_N_SYNC_1_ 3 -1 5 1 0 -1 -1 1 0 21
|
|
341 CLK_000_N_SYNC_0_ 3 -1 5 1 5 -1 -1 1 0 21
|
|
340 CLK_000_P_SYNC_9_ 3 -1 4 1 5 -1 -1 1 0 21
|
|
339 CLK_000_P_SYNC_8_ 3 -1 3 1 4 -1 -1 1 0 21
|
|
338 CLK_000_P_SYNC_7_ 3 -1 1 1 3 -1 -1 1 0 21
|
|
337 CLK_000_P_SYNC_6_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
336 CLK_000_P_SYNC_5_ 3 -1 5 1 0 -1 -1 1 0 21
|
|
335 CLK_000_P_SYNC_4_ 3 -1 1 1 5 -1 -1 1 0 21
|
|
334 CLK_000_P_SYNC_3_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
333 CLK_000_P_SYNC_2_ 3 -1 3 1 3 -1 -1 1 0 21
|
|
332 CLK_000_P_SYNC_1_ 3 -1 3 1 3 -1 -1 1 0 21
|
|
331 CLK_000_P_SYNC_0_ 3 -1 2 1 3 -1 -1 1 0 21
|
|
322 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
321 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
320 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
313 inst_DTACK_D0 3 -1 3 1 2 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_19_ 1 -1 -1 3 4 5 7 96 -1
|
|
95 A_16_ 1 -1 -1 3 4 5 7 95 -1
|
|
94 A_18_ 1 -1 -1 3 4 5 7 94 -1
|
|
58 A_17_ 1 -1 -1 3 4 5 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 4 5 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 4 5 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
67 IPL_2_ 1 -1 -1 2 0 1 67 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 6 66 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 3 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_22_ 1 -1 -1 1 4 83 -1
|
|
59 A1 1 -1 -1 1 5 59 -1
|
|
35 VPA 1 -1 -1 1 5 35 -1
|
|
29 DTACK 1 -1 -1 1 3 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
18 A_24_ 1 -1 -1 1 4 18 -1
|
|
17 A_25_ 1 -1 -1 1 4 17 -1
|
|
16 A_26_ 1 -1 -1 1 4 16 -1
|
|
15 A_27_ 1 -1 -1 1 4 15 -1
|
|
14 A_28_ 1 -1 -1 1 4 14 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 5 13 -1
|
|
10 CLK_000 1 -1 -1 1 6 10 -1
|
|
5 A_29_ 1 -1 -1 1 4 5 -1
|
|
4 A_30_ 1 -1 -1 1 4 4 -1
|
|
3 A_31_ 1 -1 -1 1 4 3 -1
|
|
140 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 4 1 2 5 7 40 -1 1 0 21
|
|
79 RW_000 5 381 7 3 0 4 6 79 -1 3 0 21
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
310 A_0_ 5 384 6 2 1 6 -1 -1 3 0 21
|
|
70 RW 5 389 6 2 2 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 380 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 386 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 385 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 387 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 383 7 0 82 -1 3 0 21
|
|
34 VMA 5 388 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 382 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
318 inst_nEXP_SPACE_D0reg 3 -1 6 7 0 2 3 4 5 6 7 -1 -1 1 0 21
|
|
383 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 3 0 21
|
|
332 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
336 CLK_000_P_SYNC_10_ 3 -1 6 5 0 2 3 5 7 -1 -1 1 0 21
|
|
317 inst_AS_030_D0 3 -1 7 5 1 2 3 4 7 -1 -1 1 0 21
|
|
377 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 14 0 21
|
|
372 SM_AMIGA_6_ 3 -1 5 4 1 2 5 6 -1 -1 3 0 21
|
|
337 SM_AMIGA_5_ 3 -1 5 4 1 2 5 7 -1 -1 3 0 21
|
|
311 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
|
314 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
312 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
341 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 2 0 21
|
|
335 CLK_000_D_0_ 3 -1 0 3 3 5 6 -1 -1 1 0 21
|
|
330 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
|
321 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
319 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21
|
|
344 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21
|
|
388 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
374 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
343 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21
|
|
329 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21
|
|
326 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
325 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
342 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21
|
|
328 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
315 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21
|
|
313 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 2 0 21
|
|
371 inst_CLK_000_NE_D0 3 -1 3 2 3 5 -1 -1 1 0 21
|
|
345 CLK_000_N_SYNC_12_ 3 -1 0 2 3 5 -1 -1 1 0 21
|
|
334 CLK_000_D_1_ 3 -1 6 2 3 5 -1 -1 1 0 21
|
|
333 inst_CLK_OUT_PRE_50 3 -1 1 2 1 4 -1 -1 1 0 21
|
|
327 inst_VPA_D 3 -1 2 2 3 5 -1 -1 1 0 21
|
|
320 inst_BGACK_030_INT_D 3 -1 7 2 2 6 -1 -1 1 0 21
|
|
386 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
385 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
380 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
322 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
373 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
375 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21
|
|
387 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
378 N_104 3 -1 5 1 5 -1 -1 4 0 21
|
|
376 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
347 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21
|
|
384 RN_A_0_ 3 310 6 1 6 -1 -1 3 0 21
|
|
381 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
346 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21
|
|
324 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
389 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
382 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
379 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
348 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21
|
|
323 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
316 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21
|
|
370 CLK_000_N_SYNC_11_ 3 -1 7 1 0 -1 -1 1 0 21
|
|
369 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
368 CLK_000_N_SYNC_9_ 3 -1 1 1 7 -1 -1 1 0 21
|
|
367 CLK_000_N_SYNC_8_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
366 CLK_000_N_SYNC_7_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
365 CLK_000_N_SYNC_6_ 3 -1 0 1 6 -1 -1 1 0 21
|
|
364 CLK_000_N_SYNC_5_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
363 CLK_000_N_SYNC_4_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
362 CLK_000_N_SYNC_3_ 3 -1 1 1 0 -1 -1 1 0 21
|
|
361 CLK_000_N_SYNC_2_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
360 CLK_000_N_SYNC_1_ 3 -1 4 1 6 -1 -1 1 0 21
|
|
359 CLK_000_N_SYNC_0_ 3 -1 3 1 4 -1 -1 1 0 21
|
|
358 CLK_000_P_SYNC_9_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
357 CLK_000_P_SYNC_8_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
356 CLK_000_P_SYNC_7_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
355 CLK_000_P_SYNC_6_ 3 -1 4 1 0 -1 -1 1 0 21
|
|
354 CLK_000_P_SYNC_5_ 3 -1 1 1 4 -1 -1 1 0 21
|
|
353 CLK_000_P_SYNC_4_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
352 CLK_000_P_SYNC_3_ 3 -1 6 1 2 -1 -1 1 0 21
|
|
351 CLK_000_P_SYNC_2_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
350 CLK_000_P_SYNC_1_ 3 -1 0 1 3 -1 -1 1 0 21
|
|
349 CLK_000_P_SYNC_0_ 3 -1 3 1 0 -1 -1 1 0 21
|
|
340 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
339 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
338 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
331 inst_DTACK_D0 3 -1 2 1 5 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 6 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
|
35 VPA 1 -1 -1 1 2 35 -1
|
|
29 DTACK 1 -1 -1 1 2 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 6 13 -1
|
|
10 CLK_000 1 -1 -1 1 0 10 -1
|
|
308 AHIGH_16_ 1 -1 -1 3 2 4 7 -1 -1
|
|
307 AHIGH_17_ 1 -1 -1 3 2 4 7 -1 -1
|
|
306 AHIGH_18_ 1 -1 -1 3 2 4 7 -1 -1
|
|
305 AHIGH_19_ 1 -1 -1 3 2 4 7 -1 -1
|
|
309 A_1_ 1 -1 -1 1 2 -1 -1
|
|
304 AHIGH_20_ 1 -1 -1 1 4 -1 -1
|
|
303 AHIGH_21_ 1 -1 -1 1 4 -1 -1
|
|
302 AHIGH_22_ 1 -1 -1 1 4 -1 -1
|
|
301 AHIGH_23_ 1 -1 -1 1 4 -1 -1
|
|
300 AHIGH_24_ 1 -1 -1 1 4 -1 -1
|
|
299 AHIGH_25_ 1 -1 -1 1 4 -1 -1
|
|
298 AHIGH_26_ 1 -1 -1 1 4 -1 -1
|
|
297 AHIGH_27_ 1 -1 -1 1 4 -1 -1
|
|
296 AHIGH_28_ 1 -1 -1 1 4 -1 -1
|
|
295 AHIGH_29_ 1 -1 -1 1 4 -1 -1
|
|
294 AHIGH_30_ 1 -1 -1 1 4 -1 -1
|
|
293 AHIGH_31_ 1 -1 -1 1 4 -1 -1
|
|
140 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
41 AS_000 5 -1 4 4 0 1 4 7 41 -1 1 0 21
|
|
40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21
|
|
79 RW_000 5 381 7 3 1 4 6 79 -1 3 0 21
|
|
310 A_0_ 5 384 6 2 0 6 -1 -1 3 0 21
|
|
70 RW 5 389 6 2 2 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 1 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 1 6 30 -1 1 0 21
|
|
300 AHIGH_24_ 5 -1 4 1 4 -1 -1 1 0 21
|
|
299 AHIGH_25_ 5 -1 4 1 4 -1 -1 1 0 21
|
|
298 AHIGH_26_ 5 -1 0 1 4 -1 -1 1 0 21
|
|
297 AHIGH_27_ 5 -1 4 1 4 -1 -1 1 0 21
|
|
296 AHIGH_28_ 5 -1 7 1 4 -1 -1 1 0 21
|
|
295 AHIGH_29_ 5 -1 7 1 4 -1 -1 1 0 21
|
|
294 AHIGH_30_ 5 -1 4 1 4 -1 -1 1 0 21
|
|
293 AHIGH_31_ 5 -1 0 1 4 -1 -1 1 0 21
|
|
78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 380 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 386 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 385 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 387 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 383 7 0 82 -1 3 0 21
|
|
34 VMA 5 388 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 382 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
383 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
318 inst_nEXP_SPACE_D0reg 3 -1 6 7 0 2 3 4 5 6 7 -1 -1 1 0 21
|
|
332 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
336 CLK_000_P_SYNC_10_ 3 -1 0 6 0 1 2 3 5 7 -1 -1 1 0 21
|
|
378 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 10 0 21
|
|
372 SM_AMIGA_6_ 3 -1 5 4 0 2 5 6 -1 -1 3 0 21
|
|
337 SM_AMIGA_5_ 3 -1 5 4 0 2 5 7 -1 -1 3 0 21
|
|
317 inst_AS_030_D0 3 -1 7 4 2 3 4 7 -1 -1 1 0 21
|
|
314 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
|
374 SM_AMIGA_1_ 3 -1 0 3 0 5 7 -1 -1 3 0 21
|
|
343 SM_AMIGA_4_ 3 -1 0 3 0 2 5 -1 -1 3 0 21
|
|
313 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
311 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
341 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 2 0 21
|
|
345 CLK_000_N_SYNC_12_ 3 -1 0 3 0 3 5 -1 -1 1 0 21
|
|
330 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
|
322 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 9 0 21
|
|
321 inst_AS_000_DMA 3 -1 1 2 1 7 -1 -1 7 0 21
|
|
319 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21
|
|
344 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21
|
|
376 SM_AMIGA_2_ 3 -1 5 2 0 5 -1 -1 4 0 21
|
|
347 RST_DLY_1_ 3 -1 0 2 0 3 -1 -1 4 0 21
|
|
388 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
346 RST_DLY_0_ 3 -1 3 2 0 3 -1 -1 3 0 21
|
|
329 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21
|
|
326 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
325 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
348 RST_DLY_2_ 3 -1 3 2 0 3 -1 -1 2 0 21
|
|
342 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
328 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
315 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
|
|
312 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 2 0 21
|
|
371 inst_CLK_000_NE_D0 3 -1 5 2 3 5 -1 -1 1 0 21
|
|
335 CLK_000_D_0_ 3 -1 5 2 3 5 -1 -1 1 0 21
|
|
334 CLK_000_D_1_ 3 -1 3 2 3 5 -1 -1 1 0 21
|
|
327 inst_VPA_D 3 -1 1 2 3 5 -1 -1 1 0 21
|
|
320 inst_BGACK_030_INT_D 3 -1 7 2 2 6 -1 -1 1 0 21
|
|
386 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
385 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
380 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
373 inst_CLK_030_H 3 -1 1 1 1 -1 -1 8 0 21
|
|
377 N_145_i_2 3 -1 0 1 5 -1 -1 5 0 21
|
|
375 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21
|
|
387 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
384 RN_A_0_ 3 310 6 1 6 -1 -1 3 0 21
|
|
381 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
324 CYCLE_DMA_1_ 3 -1 1 1 1 -1 -1 3 0 21
|
|
389 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
382 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
379 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
323 CYCLE_DMA_0_ 3 -1 1 1 1 -1 -1 2 0 21
|
|
316 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21
|
|
370 CLK_000_N_SYNC_11_ 3 -1 7 1 0 -1 -1 1 0 21
|
|
369 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
368 CLK_000_N_SYNC_9_ 3 -1 2 1 7 -1 -1 1 0 21
|
|
367 CLK_000_N_SYNC_8_ 3 -1 0 1 2 -1 -1 1 0 21
|
|
366 CLK_000_N_SYNC_7_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
365 CLK_000_N_SYNC_6_ 3 -1 2 1 0 -1 -1 1 0 21
|
|
364 CLK_000_N_SYNC_5_ 3 -1 0 1 2 -1 -1 1 0 21
|
|
363 CLK_000_N_SYNC_4_ 3 -1 1 1 0 -1 -1 1 0 21
|
|
362 CLK_000_N_SYNC_3_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
361 CLK_000_N_SYNC_2_ 3 -1 5 1 5 -1 -1 1 0 21
|
|
360 CLK_000_N_SYNC_1_ 3 -1 1 1 5 -1 -1 1 0 21
|
|
359 CLK_000_N_SYNC_0_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
358 CLK_000_P_SYNC_9_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
357 CLK_000_P_SYNC_8_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
356 CLK_000_P_SYNC_7_ 3 -1 0 1 6 -1 -1 1 0 21
|
|
355 CLK_000_P_SYNC_6_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
354 CLK_000_P_SYNC_5_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
353 CLK_000_P_SYNC_4_ 3 -1 1 1 3 -1 -1 1 0 21
|
|
352 CLK_000_P_SYNC_3_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
351 CLK_000_P_SYNC_2_ 3 -1 4 1 5 -1 -1 1 0 21
|
|
350 CLK_000_P_SYNC_1_ 3 -1 1 1 4 -1 -1 1 0 21
|
|
349 CLK_000_P_SYNC_0_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
340 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
339 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
338 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
333 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
331 inst_DTACK_D0 3 -1 3 1 5 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
67 IPL_2_ 1 -1 -1 2 1 6 67 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 6 66 -1
|
|
63 CLK_030 1 -1 -1 2 1 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 3 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
35 VPA 1 -1 -1 1 1 35 -1
|
|
29 DTACK 1 -1 -1 1 3 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 6 13 -1
|
|
10 CLK_000 1 -1 -1 1 5 10 -1
|
|
309 AHIGH_16_ 1 -1 -1 3 2 4 7 -1 -1
|
|
308 AHIGH_17_ 1 -1 -1 3 2 4 7 -1 -1
|
|
307 AHIGH_18_ 1 -1 -1 3 2 4 7 -1 -1
|
|
306 AHIGH_19_ 1 -1 -1 3 2 4 7 -1 -1
|
|
301 A_1_ 1 -1 -1 2 2 6 -1 -1
|
|
305 AHIGH_20_ 1 -1 -1 1 4 -1 -1
|
|
304 AHIGH_21_ 1 -1 -1 1 4 -1 -1
|
|
303 AHIGH_22_ 1 -1 -1 1 4 -1 -1
|
|
302 AHIGH_23_ 1 -1 -1 1 4 -1 -1
|
|
140 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
41 AS_000 5 -1 4 4 0 1 4 7 41 -1 1 0 21
|
|
40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21
|
|
79 RW_000 5 381 7 3 1 4 6 79 -1 3 0 21
|
|
310 A_0_ 5 384 6 2 0 6 -1 -1 3 0 21
|
|
70 RW 5 389 6 2 2 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 1 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 1 6 30 -1 1 0 21
|
|
300 AHIGH_24_ 5 -1 4 1 4 -1 -1 1 0 21
|
|
299 AHIGH_25_ 5 -1 4 1 4 -1 -1 1 0 21
|
|
298 AHIGH_26_ 5 -1 0 1 4 -1 -1 1 0 21
|
|
297 AHIGH_27_ 5 -1 4 1 4 -1 -1 1 0 21
|
|
296 AHIGH_28_ 5 -1 7 1 4 -1 -1 1 0 21
|
|
295 AHIGH_29_ 5 -1 7 1 4 -1 -1 1 0 21
|
|
294 AHIGH_30_ 5 -1 4 1 4 -1 -1 1 0 21
|
|
293 AHIGH_31_ 5 -1 0 1 4 -1 -1 1 0 21
|
|
78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 380 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 386 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 385 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 387 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 383 7 0 82 -1 3 0 21
|
|
34 VMA 5 388 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 382 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
383 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
318 inst_nEXP_SPACE_D0reg 3 -1 6 7 0 2 3 4 5 6 7 -1 -1 1 0 21
|
|
332 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
336 CLK_000_P_SYNC_10_ 3 -1 0 6 0 1 2 3 5 7 -1 -1 1 0 21
|
|
378 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 10 0 21
|
|
372 SM_AMIGA_6_ 3 -1 5 4 0 2 5 6 -1 -1 3 0 21
|
|
337 SM_AMIGA_5_ 3 -1 5 4 0 2 5 7 -1 -1 3 0 21
|
|
317 inst_AS_030_D0 3 -1 7 4 2 3 4 7 -1 -1 1 0 21
|
|
314 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
|
374 SM_AMIGA_1_ 3 -1 0 3 0 5 7 -1 -1 3 0 21
|
|
343 SM_AMIGA_4_ 3 -1 0 3 0 2 5 -1 -1 3 0 21
|
|
313 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
311 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
341 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 2 0 21
|
|
345 CLK_000_N_SYNC_12_ 3 -1 0 3 0 3 5 -1 -1 1 0 21
|
|
330 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
|
322 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 9 0 21
|
|
321 inst_AS_000_DMA 3 -1 1 2 1 7 -1 -1 7 0 21
|
|
319 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21
|
|
344 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21
|
|
376 SM_AMIGA_2_ 3 -1 5 2 0 5 -1 -1 4 0 21
|
|
347 RST_DLY_1_ 3 -1 0 2 0 3 -1 -1 4 0 21
|
|
388 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
346 RST_DLY_0_ 3 -1 3 2 0 3 -1 -1 3 0 21
|
|
329 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21
|
|
326 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
325 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
348 RST_DLY_2_ 3 -1 3 2 0 3 -1 -1 2 0 21
|
|
342 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
328 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
315 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
|
|
312 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 2 0 21
|
|
371 inst_CLK_000_NE_D0 3 -1 5 2 3 5 -1 -1 1 0 21
|
|
335 CLK_000_D_0_ 3 -1 5 2 3 5 -1 -1 1 0 21
|
|
334 CLK_000_D_1_ 3 -1 3 2 3 5 -1 -1 1 0 21
|
|
327 inst_VPA_D 3 -1 1 2 3 5 -1 -1 1 0 21
|
|
320 inst_BGACK_030_INT_D 3 -1 7 2 2 6 -1 -1 1 0 21
|
|
386 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
385 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
380 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
373 inst_CLK_030_H 3 -1 1 1 1 -1 -1 8 0 21
|
|
377 N_145_i_2 3 -1 0 1 5 -1 -1 5 0 21
|
|
375 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21
|
|
387 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
384 RN_A_0_ 3 310 6 1 6 -1 -1 3 0 21
|
|
381 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
324 CYCLE_DMA_1_ 3 -1 1 1 1 -1 -1 3 0 21
|
|
389 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
382 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
379 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
323 CYCLE_DMA_0_ 3 -1 1 1 1 -1 -1 2 0 21
|
|
316 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21
|
|
370 CLK_000_N_SYNC_11_ 3 -1 7 1 0 -1 -1 1 0 21
|
|
369 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
368 CLK_000_N_SYNC_9_ 3 -1 2 1 7 -1 -1 1 0 21
|
|
367 CLK_000_N_SYNC_8_ 3 -1 0 1 2 -1 -1 1 0 21
|
|
366 CLK_000_N_SYNC_7_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
365 CLK_000_N_SYNC_6_ 3 -1 2 1 0 -1 -1 1 0 21
|
|
364 CLK_000_N_SYNC_5_ 3 -1 0 1 2 -1 -1 1 0 21
|
|
363 CLK_000_N_SYNC_4_ 3 -1 1 1 0 -1 -1 1 0 21
|
|
362 CLK_000_N_SYNC_3_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
361 CLK_000_N_SYNC_2_ 3 -1 5 1 5 -1 -1 1 0 21
|
|
360 CLK_000_N_SYNC_1_ 3 -1 1 1 5 -1 -1 1 0 21
|
|
359 CLK_000_N_SYNC_0_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
358 CLK_000_P_SYNC_9_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
357 CLK_000_P_SYNC_8_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
356 CLK_000_P_SYNC_7_ 3 -1 0 1 6 -1 -1 1 0 21
|
|
355 CLK_000_P_SYNC_6_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
354 CLK_000_P_SYNC_5_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
353 CLK_000_P_SYNC_4_ 3 -1 1 1 3 -1 -1 1 0 21
|
|
352 CLK_000_P_SYNC_3_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
351 CLK_000_P_SYNC_2_ 3 -1 4 1 5 -1 -1 1 0 21
|
|
350 CLK_000_P_SYNC_1_ 3 -1 1 1 4 -1 -1 1 0 21
|
|
349 CLK_000_P_SYNC_0_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
340 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
339 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
338 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
333 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
331 inst_DTACK_D0 3 -1 3 1 5 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
67 IPL_2_ 1 -1 -1 2 1 6 67 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 6 66 -1
|
|
63 CLK_030 1 -1 -1 2 1 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 3 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
35 VPA 1 -1 -1 1 1 35 -1
|
|
29 DTACK 1 -1 -1 1 3 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 6 13 -1
|
|
10 CLK_000 1 -1 -1 1 5 10 -1
|
|
309 AHIGH_16_ 1 -1 -1 3 2 4 7 -1 -1
|
|
308 AHIGH_17_ 1 -1 -1 3 2 4 7 -1 -1
|
|
307 AHIGH_18_ 1 -1 -1 3 2 4 7 -1 -1
|
|
306 AHIGH_19_ 1 -1 -1 3 2 4 7 -1 -1
|
|
301 A_1_ 1 -1 -1 2 2 6 -1 -1
|
|
305 AHIGH_20_ 1 -1 -1 1 4 -1 -1
|
|
304 AHIGH_21_ 1 -1 -1 1 4 -1 -1
|
|
303 AHIGH_22_ 1 -1 -1 1 4 -1 -1
|
|
302 AHIGH_23_ 1 -1 -1 1 4 -1 -1
|
|
140 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 4 2 5 6 7 40 -1 1 0 21
|
|
79 RW_000 5 384 7 3 0 4 6 79 -1 3 0 21
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
70 RW 5 389 6 2 5 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
310 A_0_ 5 380 0 1 1 -1 -1 3 0 21
|
|
302 AHIGH_24_ 5 -1 4 1 4 -1 -1 1 0 21
|
|
301 AHIGH_25_ 5 -1 7 1 4 -1 -1 1 0 21
|
|
300 AHIGH_26_ 5 -1 4 1 4 -1 -1 1 0 21
|
|
299 AHIGH_27_ 5 -1 4 1 4 -1 -1 1 0 21
|
|
298 AHIGH_28_ 5 -1 7 1 4 -1 -1 1 0 21
|
|
297 AHIGH_29_ 5 -1 4 1 4 -1 -1 1 0 21
|
|
296 AHIGH_30_ 5 -1 6 1 4 -1 -1 1 0 21
|
|
293 AHIGH_31_ 5 -1 6 1 4 -1 -1 1 0 21
|
|
78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21
|
|
8 IPL_030_2_ 5 383 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 382 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 381 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 387 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 386 7 0 82 -1 3 0 21
|
|
34 VMA 5 388 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 385 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
386 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 3 0 21
|
|
333 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21
|
|
319 inst_nEXP_SPACE_D0reg 3 -1 2 6 0 2 3 4 6 7 -1 -1 1 0 21
|
|
318 inst_AS_030_D0 3 -1 7 6 2 3 4 5 6 7 -1 -1 1 0 21
|
|
337 CLK_000_P_SYNC_10_ 3 -1 6 5 0 2 3 5 7 -1 -1 1 0 21
|
|
378 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 14 0 21
|
|
338 SM_AMIGA_5_ 3 -1 5 4 2 5 6 7 -1 -1 3 0 21
|
|
315 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
|
375 SM_AMIGA_1_ 3 -1 5 3 2 5 7 -1 -1 3 0 21
|
|
373 SM_AMIGA_6_ 3 -1 2 3 1 2 5 -1 -1 3 0 21
|
|
314 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
311 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
342 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 2 0 21
|
|
336 CLK_000_D_0_ 3 -1 5 3 2 3 6 -1 -1 1 0 21
|
|
331 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
|
321 inst_BGACK_030_INT_D 3 -1 7 3 0 2 6 -1 -1 1 0 21
|
|
322 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
376 SM_AMIGA_3_ 3 -1 5 2 2 5 -1 -1 5 0 21
|
|
345 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 5 0 21
|
|
377 SM_AMIGA_2_ 3 -1 5 2 2 5 -1 -1 4 0 21
|
|
388 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
344 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21
|
|
330 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21
|
|
327 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
326 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
343 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 2 0 3 -1 -1 2 0 21
|
|
329 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
317 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21
|
|
316 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21
|
|
312 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21
|
|
372 inst_CLK_000_NE_D0 3 -1 5 2 3 5 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_12_ 3 -1 4 2 3 5 -1 -1 1 0 21
|
|
335 CLK_000_D_1_ 3 -1 3 2 2 6 -1 -1 1 0 21
|
|
328 inst_VPA_D 3 -1 0 2 3 5 -1 -1 1 0 21
|
|
383 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
382 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
381 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
323 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
374 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
320 inst_AS_030_000_SYNC 3 -1 2 1 2 -1 -1 7 0 21
|
|
387 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
348 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21
|
|
313 N_195_i 3 -1 2 1 5 -1 -1 4 0 21
|
|
384 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
380 RN_A_0_ 3 310 0 1 0 -1 -1 3 0 21
|
|
347 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21
|
|
325 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
389 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
385 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
379 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
349 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21
|
|
324 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
371 CLK_000_N_SYNC_11_ 3 -1 7 1 4 -1 -1 1 0 21
|
|
370 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
369 CLK_000_N_SYNC_9_ 3 -1 1 1 7 -1 -1 1 0 21
|
|
368 CLK_000_N_SYNC_8_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
367 CLK_000_N_SYNC_7_ 3 -1 5 1 0 -1 -1 1 0 21
|
|
366 CLK_000_N_SYNC_6_ 3 -1 1 1 5 -1 -1 1 0 21
|
|
365 CLK_000_N_SYNC_5_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
364 CLK_000_N_SYNC_4_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
363 CLK_000_N_SYNC_3_ 3 -1 6 1 3 -1 -1 1 0 21
|
|
362 CLK_000_N_SYNC_2_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
361 CLK_000_N_SYNC_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
360 CLK_000_N_SYNC_0_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
359 CLK_000_P_SYNC_9_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
358 CLK_000_P_SYNC_8_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
357 CLK_000_P_SYNC_7_ 3 -1 0 1 5 -1 -1 1 0 21
|
|
356 CLK_000_P_SYNC_6_ 3 -1 2 1 0 -1 -1 1 0 21
|
|
355 CLK_000_P_SYNC_5_ 3 -1 6 1 2 -1 -1 1 0 21
|
|
354 CLK_000_P_SYNC_4_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
353 CLK_000_P_SYNC_3_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
352 CLK_000_P_SYNC_2_ 3 -1 0 1 3 -1 -1 1 0 21
|
|
351 CLK_000_P_SYNC_1_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
350 CLK_000_P_SYNC_0_ 3 -1 2 1 0 -1 -1 1 0 21
|
|
341 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
340 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
339 IPL_D0_0_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
334 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
332 inst_DTACK_D0 3 -1 1 1 5 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
67 IPL_2_ 1 -1 -1 2 1 6 67 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 5 66 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 6 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
35 VPA 1 -1 -1 1 0 35 -1
|
|
29 DTACK 1 -1 -1 1 1 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 2 13 -1
|
|
10 CLK_000 1 -1 -1 1 5 10 -1
|
|
309 A_DECODE_16_ 1 -1 -1 3 2 4 7 -1 -1
|
|
308 A_DECODE_17_ 1 -1 -1 3 2 4 7 -1 -1
|
|
307 A_DECODE_18_ 1 -1 -1 3 2 4 7 -1 -1
|
|
306 A_DECODE_19_ 1 -1 -1 3 2 4 7 -1 -1
|
|
305 A_DECODE_20_ 1 -1 -1 1 4 -1 -1
|
|
304 A_DECODE_21_ 1 -1 -1 1 4 -1 -1
|
|
303 A_DECODE_22_ 1 -1 -1 1 4 -1 -1
|
|
295 A_1_ 1 -1 -1 1 0 -1 -1
|
|
294 A_DECODE_23_ 1 -1 -1 1 4 -1 -1
|
|
140 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 4 1 2 5 7 40 -1 1 0 21
|
|
79 RW_000 5 366 7 3 0 4 6 79 -1 3 0 21
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
70 RW 5 371 6 2 5 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
68 A_0_ 5 362 6 1 0 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
|
8 IPL_030_2_ 5 365 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 364 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 363 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 369 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 368 7 0 82 -1 3 0 21
|
|
34 VMA 5 370 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 367 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
301 inst_nEXP_SPACE_D0reg 3 -1 2 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21
|
|
368 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
315 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
319 CLK_000_P_SYNC_10_ 3 -1 1 5 0 1 3 5 7 -1 -1 1 0 21
|
|
300 inst_AS_030_D0 3 -1 7 5 2 3 4 5 7 -1 -1 1 0 21
|
|
360 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 14 0 21
|
|
320 SM_AMIGA_5_ 3 -1 5 4 1 2 5 7 -1 -1 3 0 21
|
|
297 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
|
296 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
293 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
328 CLK_000_N_SYNC_12_ 3 -1 6 3 1 3 5 -1 -1 1 0 21
|
|
313 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
|
303 inst_BGACK_030_INT_D 3 -1 7 3 1 2 6 -1 -1 1 0 21
|
|
304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
302 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21
|
|
327 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 5 0 21
|
|
370 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
357 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
355 SM_AMIGA_6_ 3 -1 5 2 0 5 -1 -1 3 0 21
|
|
326 SM_AMIGA_4_ 3 -1 1 2 1 5 -1 -1 3 0 21
|
|
312 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21
|
|
309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
325 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
324 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 2 0 21
|
|
311 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
|
|
294 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 2 0 21
|
|
354 inst_CLK_000_NE_D0 3 -1 5 2 3 5 -1 -1 1 0 21
|
|
318 CLK_000_D_0_ 3 -1 2 2 3 5 -1 -1 1 0 21
|
|
317 CLK_000_D_1_ 3 -1 5 2 3 5 -1 -1 1 0 21
|
|
310 inst_VPA_D 3 -1 6 2 3 5 -1 -1 1 0 21
|
|
365 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
364 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
363 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
356 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
358 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21
|
|
369 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
359 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
330 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21
|
|
295 N_195_i 3 -1 5 1 5 -1 -1 4 0 21
|
|
366 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
362 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
329 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21
|
|
307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
371 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
367 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
331 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21
|
|
306 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
353 CLK_000_N_SYNC_11_ 3 -1 7 1 6 -1 -1 1 0 21
|
|
352 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_9_ 3 -1 6 1 7 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_8_ 3 -1 2 1 6 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_7_ 3 -1 4 1 2 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_6_ 3 -1 6 1 4 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_5_ 3 -1 2 1 6 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_4_ 3 -1 4 1 2 -1 -1 1 0 21
|
|
345 CLK_000_N_SYNC_3_ 3 -1 2 1 4 -1 -1 1 0 21
|
|
344 CLK_000_N_SYNC_2_ 3 -1 1 1 2 -1 -1 1 0 21
|
|
343 CLK_000_N_SYNC_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
342 CLK_000_N_SYNC_0_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
341 CLK_000_P_SYNC_9_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
340 CLK_000_P_SYNC_8_ 3 -1 2 1 0 -1 -1 1 0 21
|
|
339 CLK_000_P_SYNC_7_ 3 -1 0 1 2 -1 -1 1 0 21
|
|
338 CLK_000_P_SYNC_6_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
337 CLK_000_P_SYNC_5_ 3 -1 2 1 0 -1 -1 1 0 21
|
|
336 CLK_000_P_SYNC_4_ 3 -1 3 1 2 -1 -1 1 0 21
|
|
335 CLK_000_P_SYNC_3_ 3 -1 6 1 3 -1 -1 1 0 21
|
|
334 CLK_000_P_SYNC_2_ 3 -1 2 1 6 -1 -1 1 0 21
|
|
333 CLK_000_P_SYNC_1_ 3 -1 6 1 2 -1 -1 1 0 21
|
|
332 CLK_000_P_SYNC_0_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
323 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
322 IPL_D0_1_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
321 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
316 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
314 inst_DTACK_D0 3 -1 3 1 5 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
59 A_1_ 1 -1 -1 2 1 6 59 -1
|
|
55 IPL_1_ 1 -1 -1 2 0 1 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
|
35 VPA 1 -1 -1 1 6 35 -1
|
|
29 DTACK 1 -1 -1 1 3 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 2 13 -1
|
|
10 CLK_000 1 -1 -1 1 2 10 -1
|
|
150 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21
|
|
79 RW_000 5 374 7 3 0 4 6 79 -1 3 0 21
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
68 A_0_ 5 373 6 2 1 6 68 -1 3 0 21
|
|
70 RW 5 381 6 2 5 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
|
8 IPL_030_2_ 5 372 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 376 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 375 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 379 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 378 7 0 82 -1 3 0 21
|
|
34 VMA 5 380 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 377 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
301 inst_nEXP_SPACE_D0reg 3 -1 7 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21
|
|
378 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
317 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
300 inst_AS_030_D0 3 -1 7 6 0 2 3 4 5 7 -1 -1 1 0 21
|
|
370 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 14 0 21
|
|
321 CLK_000_P_SYNC_10_ 3 -1 6 4 0 3 5 7 -1 -1 1 0 21
|
|
294 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 4 0 21
|
|
365 SM_AMIGA_6_ 3 -1 5 3 1 5 6 -1 -1 3 0 21
|
|
322 SM_AMIGA_5_ 3 -1 5 3 0 5 7 -1 -1 3 0 21
|
|
297 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
295 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
296 cpu_est_0_ 3 -1 2 3 2 3 5 -1 -1 2 0 21
|
|
338 CLK_000_N_SYNC_12_ 3 -1 6 3 2 3 5 -1 -1 1 0 21
|
|
320 CLK_000_D_0_ 3 -1 2 3 3 4 5 -1 -1 1 0 21
|
|
313 inst_CLK_OUT_PRE_D 3 -1 0 3 1 6 7 -1 -1 1 0 21
|
|
303 inst_BGACK_030_INT_D 3 -1 7 3 1 2 6 -1 -1 1 0 21
|
|
304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
302 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21
|
|
337 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 5 0 21
|
|
380 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
367 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
312 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21
|
|
309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
335 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
334 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 2 0 21
|
|
311 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21
|
|
364 inst_CLK_000_NE_D0 3 -1 2 2 2 5 -1 -1 1 0 21
|
|
319 CLK_000_D_1_ 3 -1 4 2 4 5 -1 -1 1 0 21
|
|
314 CLK_000_D_9_ 3 -1 3 2 2 7 -1 -1 1 0 21
|
|
310 inst_VPA_D 3 -1 1 2 3 5 -1 -1 1 0 21
|
|
376 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
375 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
372 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
366 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
368 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21
|
|
379 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
369 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
340 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21
|
|
293 N_205_i 3 -1 5 1 5 -1 -1 4 0 21
|
|
374 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
373 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
339 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21
|
|
336 SM_AMIGA_4_ 3 -1 5 1 5 -1 -1 3 0 21
|
|
307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
381 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
377 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
371 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
341 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21
|
|
306 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
363 CLK_000_N_SYNC_11_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
362 CLK_000_N_SYNC_10_ 3 -1 2 1 3 -1 -1 1 0 21
|
|
361 CLK_000_N_SYNC_9_ 3 -1 1 1 2 -1 -1 1 0 21
|
|
360 CLK_000_N_SYNC_8_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
359 CLK_000_N_SYNC_7_ 3 -1 4 1 2 -1 -1 1 0 21
|
|
358 CLK_000_N_SYNC_6_ 3 -1 6 1 4 -1 -1 1 0 21
|
|
357 CLK_000_N_SYNC_5_ 3 -1 0 1 6 -1 -1 1 0 21
|
|
356 CLK_000_N_SYNC_4_ 3 -1 2 1 0 -1 -1 1 0 21
|
|
355 CLK_000_N_SYNC_3_ 3 -1 6 1 2 -1 -1 1 0 21
|
|
354 CLK_000_N_SYNC_2_ 3 -1 0 1 6 -1 -1 1 0 21
|
|
353 CLK_000_N_SYNC_1_ 3 -1 1 1 0 -1 -1 1 0 21
|
|
352 CLK_000_N_SYNC_0_ 3 -1 4 1 1 -1 -1 1 0 21
|
|
351 CLK_000_P_SYNC_9_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
350 CLK_000_P_SYNC_8_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
349 CLK_000_P_SYNC_7_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
348 CLK_000_P_SYNC_6_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
347 CLK_000_P_SYNC_5_ 3 -1 2 1 0 -1 -1 1 0 21
|
|
346 CLK_000_P_SYNC_4_ 3 -1 6 1 2 -1 -1 1 0 21
|
|
345 CLK_000_P_SYNC_3_ 3 -1 5 1 6 -1 -1 1 0 21
|
|
344 CLK_000_P_SYNC_2_ 3 -1 5 1 5 -1 -1 1 0 21
|
|
343 CLK_000_P_SYNC_1_ 3 -1 2 1 5 -1 -1 1 0 21
|
|
342 CLK_000_P_SYNC_0_ 3 -1 4 1 2 -1 -1 1 0 21
|
|
333 CLK_000_D_11_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
332 CLK_000_D_8_ 3 -1 3 1 3 -1 -1 1 0 21
|
|
331 CLK_000_D_7_ 3 -1 3 1 3 -1 -1 1 0 21
|
|
330 CLK_000_D_6_ 3 -1 3 1 3 -1 -1 1 0 21
|
|
329 CLK_000_D_5_ 3 -1 3 1 3 -1 -1 1 0 21
|
|
328 CLK_000_D_4_ 3 -1 6 1 3 -1 -1 1 0 21
|
|
327 CLK_000_D_3_ 3 -1 0 1 6 -1 -1 1 0 21
|
|
326 CLK_000_D_2_ 3 -1 4 1 0 -1 -1 1 0 21
|
|
325 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
324 IPL_D0_1_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
323 IPL_D0_0_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
318 inst_CLK_OUT_PRE_50 3 -1 0 1 0 -1 -1 1 0 21
|
|
316 inst_DTACK_D0 3 -1 6 1 5 -1 -1 1 0 21
|
|
315 CLK_000_D_10_ 3 -1 2 1 7 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
67 IPL_2_ 1 -1 -1 2 0 1 67 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 5 66 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 2 0 1 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
|
59 A_1_ 1 -1 -1 1 1 59 -1
|
|
35 VPA 1 -1 -1 1 1 35 -1
|
|
29 DTACK 1 -1 -1 1 6 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 7 13 -1
|
|
10 CLK_000 1 -1 -1 1 2 10 -1
|
|
151 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 5 1 2 5 6 7 40 -1 1 0 21
|
|
79 RW_000 5 374 7 3 0 4 6 79 -1 3 0 21
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
68 A_0_ 5 375 6 2 0 6 68 -1 3 0 21
|
|
70 RW 5 382 6 2 1 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
|
8 IPL_030_2_ 5 373 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 377 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 376 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 380 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 379 7 0 82 -1 3 0 21
|
|
34 VMA 5 381 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 378 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
301 inst_nEXP_SPACE_D0reg 3 -1 6 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21
|
|
379 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
317 inst_RESET_OUT 3 -1 1 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
321 CLK_000_P_SYNC_10_ 3 -1 3 6 0 1 3 5 6 7 -1 -1 1 0 21
|
|
371 SM_AMIGA_i_7_ 3 -1 5 5 1 2 3 5 7 -1 -1 14 0 21
|
|
300 inst_AS_030_D0 3 -1 7 5 1 2 3 4 7 -1 -1 1 0 21
|
|
366 SM_AMIGA_6_ 3 -1 5 4 0 1 5 6 -1 -1 3 0 21
|
|
322 SM_AMIGA_5_ 3 -1 5 4 1 2 5 7 -1 -1 3 0 21
|
|
335 SM_AMIGA_0_ 3 -1 6 4 1 5 6 7 -1 -1 2 0 21
|
|
339 CLK_000_N_SYNC_12_ 3 -1 0 4 1 3 5 6 -1 -1 1 0 21
|
|
294 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 4 0 21
|
|
368 SM_AMIGA_1_ 3 -1 5 3 5 6 7 -1 -1 3 0 21
|
|
297 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
295 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
320 CLK_000_D_0_ 3 -1 5 3 3 5 6 -1 -1 1 0 21
|
|
313 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
|
304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
302 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21
|
|
338 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 5 0 21
|
|
381 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
337 SM_AMIGA_4_ 3 -1 5 2 1 5 -1 -1 3 0 21
|
|
312 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21
|
|
309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
336 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21
|
|
311 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
|
|
296 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21
|
|
365 inst_CLK_000_NE_D0 3 -1 3 2 3 5 -1 -1 1 0 21
|
|
319 CLK_000_D_1_ 3 -1 5 2 5 6 -1 -1 1 0 21
|
|
310 inst_VPA_D 3 -1 2 2 3 5 -1 -1 1 0 21
|
|
303 inst_BGACK_030_INT_D 3 -1 7 2 2 6 -1 -1 1 0 21
|
|
377 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
376 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
373 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
367 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
369 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21
|
|
380 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
370 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
341 RST_DLY_1_ 3 -1 1 1 1 -1 -1 4 0 21
|
|
293 N_205_i 3 -1 5 1 5 -1 -1 4 0 21
|
|
375 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
374 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
340 RST_DLY_0_ 3 -1 1 1 1 -1 -1 3 0 21
|
|
307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
382 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
378 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
372 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
342 RST_DLY_2_ 3 -1 1 1 1 -1 -1 2 0 21
|
|
306 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
364 CLK_000_N_SYNC_11_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
363 CLK_000_N_SYNC_10_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
362 CLK_000_N_SYNC_9_ 3 -1 4 1 6 -1 -1 1 0 21
|
|
361 CLK_000_N_SYNC_8_ 3 -1 3 1 4 -1 -1 1 0 21
|
|
360 CLK_000_N_SYNC_7_ 3 -1 5 1 3 -1 -1 1 0 21
|
|
359 CLK_000_N_SYNC_6_ 3 -1 2 1 5 -1 -1 1 0 21
|
|
358 CLK_000_N_SYNC_5_ 3 -1 4 1 2 -1 -1 1 0 21
|
|
357 CLK_000_N_SYNC_4_ 3 -1 6 1 4 -1 -1 1 0 21
|
|
356 CLK_000_N_SYNC_3_ 3 -1 0 1 6 -1 -1 1 0 21
|
|
355 CLK_000_N_SYNC_2_ 3 -1 3 1 0 -1 -1 1 0 21
|
|
354 CLK_000_N_SYNC_1_ 3 -1 0 1 3 -1 -1 1 0 21
|
|
353 CLK_000_N_SYNC_0_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
352 CLK_000_P_SYNC_9_ 3 -1 6 1 3 -1 -1 1 0 21
|
|
351 CLK_000_P_SYNC_8_ 3 -1 0 1 6 -1 -1 1 0 21
|
|
350 CLK_000_P_SYNC_7_ 3 -1 5 1 0 -1 -1 1 0 21
|
|
349 CLK_000_P_SYNC_6_ 3 -1 7 1 5 -1 -1 1 0 21
|
|
348 CLK_000_P_SYNC_5_ 3 -1 3 1 7 -1 -1 1 0 21
|
|
347 CLK_000_P_SYNC_4_ 3 -1 4 1 3 -1 -1 1 0 21
|
|
346 CLK_000_P_SYNC_3_ 3 -1 6 1 4 -1 -1 1 0 21
|
|
345 CLK_000_P_SYNC_2_ 3 -1 2 1 6 -1 -1 1 0 21
|
|
344 CLK_000_P_SYNC_1_ 3 -1 2 1 2 -1 -1 1 0 21
|
|
343 CLK_000_P_SYNC_0_ 3 -1 5 1 2 -1 -1 1 0 21
|
|
334 CLK_000_D_12_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
333 CLK_000_D_9_ 3 -1 1 1 3 -1 -1 1 0 21
|
|
332 CLK_000_D_8_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
331 CLK_000_D_7_ 3 -1 1 1 2 -1 -1 1 0 21
|
|
330 CLK_000_D_6_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
329 CLK_000_D_5_ 3 -1 3 1 0 -1 -1 1 0 21
|
|
328 CLK_000_D_4_ 3 -1 1 1 3 -1 -1 1 0 21
|
|
327 CLK_000_D_3_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
326 CLK_000_D_2_ 3 -1 5 1 2 -1 -1 1 0 21
|
|
325 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
324 IPL_D0_1_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
323 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
318 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
316 inst_DTACK_D0 3 -1 0 1 5 -1 -1 1 0 21
|
|
315 CLK_000_D_11_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
314 CLK_000_D_10_ 3 -1 3 1 7 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
67 IPL_2_ 1 -1 -1 2 1 2 67 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 3 66 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
59 A_1_ 1 -1 -1 2 2 6 59 -1
|
|
55 IPL_1_ 1 -1 -1 2 0 1 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
|
35 VPA 1 -1 -1 1 2 35 -1
|
|
29 DTACK 1 -1 -1 1 0 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 6 13 -1
|
|
10 CLK_000 1 -1 -1 1 5 10 -1
|
|
128 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
79 RW_000 5 352 7 2 4 6 79 -1 5 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
70 RW 5 357 6 1 7 70 -1 2 0 21
|
|
40 BERR 5 -1 4 1 7 40 -1 1 0 21
|
|
31 UDS_000 5 -1 3 1 6 31 -1 1 0 21
|
|
18 AHIGH_24_ 5 -1 -1 1 4 18 -1 1 0 21
|
|
17 AHIGH_25_ 5 -1 -1 1 4 17 -1 1 0 21
|
|
16 AHIGH_26_ 5 -1 -1 1 4 16 -1 1 0 21
|
|
15 AHIGH_27_ 5 -1 -1 1 4 15 -1 1 0 21
|
|
14 AHIGH_28_ 5 -1 -1 1 4 14 -1 1 0 21
|
|
5 AHIGH_29_ 5 -1 -1 1 4 5 -1 1 0 21
|
|
4 AHIGH_30_ 5 -1 -1 1 4 4 -1 1 0 21
|
|
3 AHIGH_31_ 5 -1 -1 1 4 3 -1 1 0 21
|
|
8 IPL_030_2_ 0 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 0 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 0 1 0 6 -1 10 0 21
|
|
80 DSACK1 0 7 0 80 -1 4 0 21
|
|
82 BGACK_030 0 7 0 82 -1 3 0 21
|
|
68 A_0_ 5 358 6 0 68 -1 3 0 21
|
|
34 VMA 0 3 0 34 -1 3 0 21
|
|
65 E 0 -1 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 -1 0 33 -1 2 0 21
|
|
28 BG_000 0 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 -1 0 91 -1 1 0 21
|
|
78 SIZE_1_ 0 -1 0 78 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
69 SIZE_0_ 0 6 0 69 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 -1 0 32 -1 1 0 21
|
|
30 LDS_000 0 3 0 30 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 -1 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 -1 0 2 -1 1 0 21
|
|
354 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 3 0 21
|
|
318 inst_RESET_OUT 3 -1 -1 5 0 3 4 6 7 -1 -1 2 0 21
|
|
301 inst_nEXP_SPACE_D0reg 3 -1 -1 5 0 3 4 6 7 -1 -1 1 0 21
|
|
313 inst_CLK_OUT_PRE_D 3 -1 -1 3 1 6 7 -1 -1 1 0 21
|
|
300 inst_AS_030_D0 3 -1 -1 3 3 4 7 -1 -1 1 0 21
|
|
319 CLK_000_D_1_ 3 -1 -1 2 3 7 -1 -1 1 0 21
|
|
314 CLK_000_D_0_ 3 -1 -1 2 3 7 -1 -1 1 0 21
|
|
359 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
351 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
350 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
305 inst_DS_000_DMA 3 -1 -1 1 0 -1 -1 9 0 21
|
|
304 inst_AS_000_DMA 3 -1 -1 1 7 -1 -1 7 0 21
|
|
352 RN_RW_000 3 79 7 1 7 79 -1 5 0 21
|
|
336 inst_DS_000_ENABLE 3 -1 -1 1 3 -1 -1 5 0 21
|
|
355 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
344 SM_AMIGA_1_ 3 -1 -1 1 7 -1 -1 4 0 21
|
|
334 SM_AMIGA_0_ 3 -1 -1 1 7 -1 -1 4 0 21
|
|
321 SM_AMIGA_5_ 3 -1 -1 1 7 -1 -1 4 0 21
|
|
295 cpu_est_2_ 3 -1 -1 1 3 -1 -1 4 0 21
|
|
358 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
356 RN_VMA 3 34 3 1 3 34 -1 3 0 21
|
|
312 inst_LDS_000_INT 3 -1 -1 1 3 -1 -1 3 0 21
|
|
309 SIZE_DMA_1_ 3 -1 -1 1 6 -1 -1 3 0 21
|
|
308 SIZE_DMA_0_ 3 -1 -1 1 6 -1 -1 3 0 21
|
|
296 cpu_est_3_ 3 -1 -1 1 3 -1 -1 3 0 21
|
|
294 cpu_est_1_ 3 -1 -1 1 3 -1 -1 3 0 21
|
|
357 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
353 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
348 CIIN_0 3 -1 -1 1 4 -1 -1 2 0 21
|
|
311 inst_UDS_000_INT 3 -1 -1 1 3 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 -1 1 4 -1 -1 2 0 21
|
|
297 cpu_est_0_ 3 -1 -1 1 3 -1 -1 2 0 21
|
|
347 SM_AMIGA_i_7_ 3 -1 -1 1 7 -1 -1 1 0 21
|
|
333 CLK_000_D_12_ 3 -1 -1 1 7 -1 -1 1 0 21
|
|
324 IPL_D0_2_ 3 -1 -1 1 1 -1 -1 1 0 21
|
|
323 IPL_D0_1_ 3 -1 -1 1 1 -1 -1 1 0 21
|
|
322 IPL_D0_0_ 3 -1 -1 1 1 -1 -1 1 0 21
|
|
316 CLK_000_D_11_ 3 -1 -1 1 7 -1 -1 1 0 21
|
|
315 CLK_000_D_10_ 3 -1 -1 1 7 -1 -1 1 0 21
|
|
310 inst_VPA_D 3 -1 -1 1 3 -1 -1 1 0 21
|
|
303 inst_BGACK_030_INT_D 3 -1 -1 1 6 -1 -1 1 0 21
|
|
349 SM_AMIGA_i_7__0 3 -1 -1 0 -1 -1 11 1 21
|
|
345 SM_AMIGA_3_ 3 -1 -1 0 -1 -1 8 0 21
|
|
343 inst_CLK_030_H 3 -1 -1 0 -1 -1 8 0 21
|
|
302 inst_AS_030_000_SYNC 3 -1 -1 0 -1 -1 7 0 21
|
|
346 SM_AMIGA_2_ 3 -1 -1 0 -1 -1 5 0 21
|
|
342 SM_AMIGA_6_ 3 -1 -1 0 -1 -1 4 0 21
|
|
338 SM_AMIGA_4_ 3 -1 -1 0 -1 -1 4 0 21
|
|
306 CYCLE_DMA_0_ 3 -1 -1 0 -1 -1 4 0 21
|
|
340 RST_DLY_1_ 3 -1 -1 0 -1 -1 3 0 21
|
|
339 RST_DLY_0_ 3 -1 -1 0 -1 -1 3 1 21
|
|
341 RST_DLY_2_ 3 -1 -1 0 -1 -1 2 0 21
|
|
335 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 -1 0 -1 -1 2 0 21
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 -1 0 -1 -1 2 0 21
|
|
293 N_199_i 3 -1 -1 0 -1 -1 2 0 21
|
|
337 inst_CLK_000_NE_D0 3 -1 -1 0 -1 -1 1 0 21
|
|
332 CLK_000_D_9_ 3 -1 -1 0 -1 -1 1 0 21
|
|
331 CLK_000_D_8_ 3 -1 -1 0 -1 -1 1 0 21
|
|
330 CLK_000_D_7_ 3 -1 -1 0 -1 -1 1 0 21
|
|
329 CLK_000_D_6_ 3 -1 -1 0 -1 -1 1 0 21
|
|
328 CLK_000_D_5_ 3 -1 -1 0 -1 -1 1 0 21
|
|
327 CLK_000_D_4_ 3 -1 -1 0 -1 -1 1 0 21
|
|
326 CLK_000_D_3_ 3 -1 -1 0 -1 -1 1 0 21
|
|
325 CLK_000_D_2_ 3 -1 -1 0 -1 -1 1 0 21
|
|
320 inst_CLK_OUT_PRE_50 3 -1 -1 0 -1 -1 1 0 21
|
|
317 inst_DTACK_D0 3 -1 -1 0 -1 -1 1 0 21
|
|
307 CYCLE_DMA_1_ 3 -1 -1 0 -1 -1 1 1 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 4 1 3 6 7 85 -1
|
|
96 A_DECODE_19_ 1 -1 -1 2 4 7 96 -1
|
|
95 A_DECODE_16_ 1 -1 -1 2 4 7 95 -1
|
|
94 A_DECODE_18_ 1 -1 -1 2 4 7 94 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
58 A_DECODE_17_ 1 -1 -1 2 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 2 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 2 4 7 56 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
10 CLK_000 1 -1 -1 2 3 7 10 -1
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
|
63 CLK_030 1 -1 -1 1 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
59 A_1_ 1 -1 -1 0 59 -1
|
|
35 VPA 1 -1 -1 0 35 -1
|
|
29 DTACK 1 -1 -1 0 29 -1
|
|
13 nEXP_SPACE 1 -1 -1 0 13 -1
|
|
128 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
79 RW_000 5 352 7 2 4 6 79 -1 5 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
70 RW 5 357 6 1 7 70 -1 2 0 21
|
|
40 BERR 5 -1 4 1 7 40 -1 1 0 21
|
|
31 UDS_000 5 -1 3 1 6 31 -1 1 0 21
|
|
18 AHIGH_24_ 5 -1 -1 1 4 18 -1 1 0 21
|
|
17 AHIGH_25_ 5 -1 -1 1 4 17 -1 1 0 21
|
|
16 AHIGH_26_ 5 -1 -1 1 4 16 -1 1 0 21
|
|
15 AHIGH_27_ 5 -1 -1 1 4 15 -1 1 0 21
|
|
14 AHIGH_28_ 5 -1 -1 1 4 14 -1 1 0 21
|
|
5 AHIGH_29_ 5 -1 -1 1 4 5 -1 1 0 21
|
|
4 AHIGH_30_ 5 -1 -1 1 4 4 -1 1 0 21
|
|
3 AHIGH_31_ 5 -1 -1 1 4 3 -1 1 0 21
|
|
8 IPL_030_2_ 0 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 0 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 0 1 0 6 -1 10 0 21
|
|
80 DSACK1 0 7 0 80 -1 4 0 21
|
|
82 BGACK_030 0 7 0 82 -1 3 0 21
|
|
68 A_0_ 5 358 6 0 68 -1 3 0 21
|
|
34 VMA 0 3 0 34 -1 3 0 21
|
|
65 E 0 -1 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 -1 0 33 -1 2 0 21
|
|
28 BG_000 0 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 -1 0 91 -1 1 0 21
|
|
78 SIZE_1_ 0 -1 0 78 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
69 SIZE_0_ 0 6 0 69 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 -1 0 32 -1 1 0 21
|
|
30 LDS_000 0 3 0 30 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 -1 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 -1 0 2 -1 1 0 21
|
|
354 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 3 0 21
|
|
318 inst_RESET_OUT 3 -1 -1 5 0 3 4 6 7 -1 -1 2 0 21
|
|
301 inst_nEXP_SPACE_D0reg 3 -1 -1 5 0 3 4 6 7 -1 -1 1 0 21
|
|
313 inst_CLK_OUT_PRE_D 3 -1 -1 3 1 6 7 -1 -1 1 0 21
|
|
300 inst_AS_030_D0 3 -1 -1 3 3 4 7 -1 -1 1 0 21
|
|
319 CLK_000_D_1_ 3 -1 -1 2 3 7 -1 -1 1 0 21
|
|
314 CLK_000_D_0_ 3 -1 -1 2 3 7 -1 -1 1 0 21
|
|
359 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
351 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
350 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
305 inst_DS_000_DMA 3 -1 -1 1 0 -1 -1 9 0 21
|
|
304 inst_AS_000_DMA 3 -1 -1 1 7 -1 -1 7 0 21
|
|
352 RN_RW_000 3 79 7 1 7 79 -1 5 0 21
|
|
336 inst_DS_000_ENABLE 3 -1 -1 1 3 -1 -1 5 0 21
|
|
355 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
344 SM_AMIGA_1_ 3 -1 -1 1 7 -1 -1 4 0 21
|
|
334 SM_AMIGA_0_ 3 -1 -1 1 7 -1 -1 4 0 21
|
|
321 SM_AMIGA_5_ 3 -1 -1 1 7 -1 -1 4 0 21
|
|
295 cpu_est_2_ 3 -1 -1 1 3 -1 -1 4 0 21
|
|
358 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
356 RN_VMA 3 34 3 1 3 34 -1 3 0 21
|
|
312 inst_LDS_000_INT 3 -1 -1 1 3 -1 -1 3 0 21
|
|
309 SIZE_DMA_1_ 3 -1 -1 1 6 -1 -1 3 0 21
|
|
308 SIZE_DMA_0_ 3 -1 -1 1 6 -1 -1 3 0 21
|
|
296 cpu_est_3_ 3 -1 -1 1 3 -1 -1 3 0 21
|
|
294 cpu_est_1_ 3 -1 -1 1 3 -1 -1 3 0 21
|
|
357 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
353 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
348 CIIN_0 3 -1 -1 1 4 -1 -1 2 0 21
|
|
311 inst_UDS_000_INT 3 -1 -1 1 3 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 -1 1 4 -1 -1 2 0 21
|
|
297 cpu_est_0_ 3 -1 -1 1 3 -1 -1 2 0 21
|
|
347 SM_AMIGA_i_7_ 3 -1 -1 1 7 -1 -1 1 0 21
|
|
333 CLK_000_D_12_ 3 -1 -1 1 7 -1 -1 1 0 21
|
|
324 IPL_D0_2_ 3 -1 -1 1 1 -1 -1 1 0 21
|
|
323 IPL_D0_1_ 3 -1 -1 1 1 -1 -1 1 0 21
|
|
322 IPL_D0_0_ 3 -1 -1 1 1 -1 -1 1 0 21
|
|
316 CLK_000_D_11_ 3 -1 -1 1 7 -1 -1 1 0 21
|
|
315 CLK_000_D_10_ 3 -1 -1 1 7 -1 -1 1 0 21
|
|
310 inst_VPA_D 3 -1 -1 1 3 -1 -1 1 0 21
|
|
303 inst_BGACK_030_INT_D 3 -1 -1 1 6 -1 -1 1 0 21
|
|
349 SM_AMIGA_i_7__0 3 -1 -1 0 -1 -1 11 1 21
|
|
345 SM_AMIGA_3_ 3 -1 -1 0 -1 -1 8 0 21
|
|
343 inst_CLK_030_H 3 -1 -1 0 -1 -1 8 0 21
|
|
302 inst_AS_030_000_SYNC 3 -1 -1 0 -1 -1 7 0 21
|
|
346 SM_AMIGA_2_ 3 -1 -1 0 -1 -1 5 0 21
|
|
342 SM_AMIGA_6_ 3 -1 -1 0 -1 -1 4 0 21
|
|
338 SM_AMIGA_4_ 3 -1 -1 0 -1 -1 4 0 21
|
|
306 CYCLE_DMA_0_ 3 -1 -1 0 -1 -1 4 0 21
|
|
340 RST_DLY_1_ 3 -1 -1 0 -1 -1 3 0 21
|
|
339 RST_DLY_0_ 3 -1 -1 0 -1 -1 3 1 21
|
|
341 RST_DLY_2_ 3 -1 -1 0 -1 -1 2 0 21
|
|
335 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 -1 0 -1 -1 2 0 21
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 -1 0 -1 -1 2 0 21
|
|
293 N_199_i 3 -1 -1 0 -1 -1 2 0 21
|
|
337 inst_CLK_000_NE_D0 3 -1 -1 0 -1 -1 1 0 21
|
|
332 CLK_000_D_9_ 3 -1 -1 0 -1 -1 1 0 21
|
|
331 CLK_000_D_8_ 3 -1 -1 0 -1 -1 1 0 21
|
|
330 CLK_000_D_7_ 3 -1 -1 0 -1 -1 1 0 21
|
|
329 CLK_000_D_6_ 3 -1 -1 0 -1 -1 1 0 21
|
|
328 CLK_000_D_5_ 3 -1 -1 0 -1 -1 1 0 21
|
|
327 CLK_000_D_4_ 3 -1 -1 0 -1 -1 1 0 21
|
|
326 CLK_000_D_3_ 3 -1 -1 0 -1 -1 1 0 21
|
|
325 CLK_000_D_2_ 3 -1 -1 0 -1 -1 1 0 21
|
|
320 inst_CLK_OUT_PRE_50 3 -1 -1 0 -1 -1 1 0 21
|
|
317 inst_DTACK_D0 3 -1 -1 0 -1 -1 1 0 21
|
|
307 CYCLE_DMA_1_ 3 -1 -1 0 -1 -1 1 1 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 4 1 3 6 7 85 -1
|
|
96 A_DECODE_19_ 1 -1 -1 2 4 7 96 -1
|
|
95 A_DECODE_16_ 1 -1 -1 2 4 7 95 -1
|
|
94 A_DECODE_18_ 1 -1 -1 2 4 7 94 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
58 A_DECODE_17_ 1 -1 -1 2 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 2 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 2 4 7 56 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
10 CLK_000 1 -1 -1 2 3 7 10 -1
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
|
63 CLK_030 1 -1 -1 1 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
59 A_1_ 1 -1 -1 0 59 -1
|
|
35 VPA 1 -1 -1 0 35 -1
|
|
29 DTACK 1 -1 -1 0 29 -1
|
|
13 nEXP_SPACE 1 -1 -1 0 13 -1
|
|
129 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 5 0 2 3 5 7 40 -1 1 0 21
|
|
41 AS_000 5 -1 4 4 0 1 4 7 41 -1 1 0 21
|
|
79 RW_000 5 355 7 3 1 4 6 79 -1 4 0 21
|
|
31 UDS_000 5 -1 3 3 1 2 6 31 -1 1 0 21
|
|
68 A_0_ 5 351 6 2 2 6 68 -1 3 0 21
|
|
70 RW 5 360 6 2 5 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 1 2 30 -1 1 0 21
|
|
78 SIZE_1_ 5 -1 7 1 6 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 6 69 -1 1 0 21
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
|
8 IPL_030_2_ 5 354 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 353 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 352 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 358 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 357 7 0 82 -1 3 0 21
|
|
34 VMA 5 359 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 356 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
302 inst_nEXP_SPACE_D0reg 3 -1 1 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21
|
|
357 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
319 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
301 inst_AS_030_D0 3 -1 4 5 2 3 4 5 7 -1 -1 1 0 21
|
|
348 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 11 0 21
|
|
343 SM_AMIGA_6_ 3 -1 5 4 2 3 5 6 -1 -1 3 0 21
|
|
315 CLK_000_D_0_ 3 -1 7 4 0 3 5 7 -1 -1 1 0 21
|
|
321 SM_AMIGA_5_ 3 -1 3 3 3 5 7 -1 -1 4 0 21
|
|
295 cpu_est_2_ 3 -1 6 3 0 3 6 -1 -1 4 0 21
|
|
310 SIZE_DMA_1_ 3 -1 2 3 2 6 7 -1 -1 3 0 21
|
|
309 SIZE_DMA_0_ 3 -1 2 3 2 6 7 -1 -1 3 0 21
|
|
298 cpu_est_1_ 3 -1 6 3 0 3 6 -1 -1 3 0 21
|
|
296 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 3 0 21
|
|
297 cpu_est_0_ 3 -1 3 3 0 3 6 -1 -1 2 0 21
|
|
338 inst_CLK_000_NE_D0 3 -1 7 3 0 3 6 -1 -1 1 0 21
|
|
314 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
|
306 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 9 0 21
|
|
346 SM_AMIGA_3_ 3 -1 0 2 0 5 -1 -1 8 0 21
|
|
305 inst_AS_000_DMA 3 -1 1 2 1 7 -1 -1 7 0 21
|
|
303 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21
|
|
337 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 5 0 21
|
|
347 SM_AMIGA_2_ 3 -1 0 2 0 5 -1 -1 4 0 21
|
|
345 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 4 0 21
|
|
340 RST_DLY_0_ 3 -1 5 2 0 5 -1 -1 4 0 21
|
|
308 CYCLE_DMA_1_ 3 -1 0 2 0 1 -1 -1 4 0 21
|
|
359 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21
|
|
339 SM_AMIGA_4_ 3 -1 5 2 0 5 -1 -1 3 0 21
|
|
335 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21
|
|
313 inst_LDS_000_INT 3 -1 6 2 3 6 -1 -1 3 0 21
|
|
307 CYCLE_DMA_0_ 3 -1 0 2 0 1 -1 -1 3 0 21
|
|
342 RST_DLY_2_ 3 -1 0 2 0 5 -1 -1 2 0 21
|
|
341 RST_DLY_1_ 3 -1 0 2 0 5 -1 -1 2 1 21
|
|
336 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21
|
|
312 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21
|
|
299 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21
|
|
325 CLK_000_D_1_ 3 -1 5 2 3 5 -1 -1 1 0 21
|
|
317 CLK_000_D_11_ 3 -1 7 2 3 7 -1 -1 1 0 21
|
|
311 inst_VPA_D 3 -1 6 2 0 3 -1 -1 1 0 21
|
|
304 inst_BGACK_030_INT_D 3 -1 7 2 2 6 -1 -1 1 0 21
|
|
354 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
353 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
352 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
344 inst_CLK_030_H 3 -1 1 1 1 -1 -1 8 0 21
|
|
358 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
355 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
|
350 SM_AMIGA_i_7__0 3 -1 5 1 5 -1 -1 4 0 21
|
|
351 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
360 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
356 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
349 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21
|
|
293 N_146_i 3 -1 0 1 5 -1 -1 2 0 21
|
|
334 CLK_000_D_12_ 3 -1 3 1 7 -1 -1 1 0 21
|
|
333 CLK_000_D_9_ 3 -1 5 1 0 -1 -1 1 0 21
|
|
332 CLK_000_D_8_ 3 -1 6 1 5 -1 -1 1 0 21
|
|
331 CLK_000_D_7_ 3 -1 4 1 6 -1 -1 1 0 21
|
|
330 CLK_000_D_6_ 3 -1 6 1 4 -1 -1 1 0 21
|
|
329 CLK_000_D_5_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
328 CLK_000_D_4_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
327 CLK_000_D_3_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
326 CLK_000_D_2_ 3 -1 3 1 3 -1 -1 1 0 21
|
|
324 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
323 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
322 IPL_D0_0_ 3 -1 4 1 1 -1 -1 1 0 21
|
|
320 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
318 inst_DTACK_D0 3 -1 0 1 0 -1 -1 1 0 21
|
|
316 CLK_000_D_10_ 3 -1 0 1 7 -1 -1 1 0 21
|
|
294 N_132_i 3 -1 3 1 5 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1
|
|
10 CLK_000 1 -1 -1 4 0 3 5 7 10 -1
|
|
96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
67 IPL_2_ 1 -1 -1 2 1 2 67 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 4 66 -1
|
|
63 CLK_030 1 -1 -1 2 1 7 63 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
|
59 A_1_ 1 -1 -1 1 2 59 -1
|
|
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
|
35 VPA 1 -1 -1 1 6 35 -1
|
|
29 DTACK 1 -1 -1 1 0 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 1 13 -1
|
|
127 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
41 AS_000 5 -1 4 5 0 1 3 4 7 41 -1 1 0 21
|
|
40 BERR 5 -1 4 5 0 2 5 6 7 40 -1 1 0 21
|
|
79 RW_000 5 351 7 3 1 4 6 79 -1 4 0 21
|
|
70 RW 5 356 6 2 5 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 1 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 1 6 30 -1 1 0 21
|
|
68 A_0_ 5 357 6 1 5 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 5 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 5 69 -1 1 0 21
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
|
8 IPL_030_2_ 5 350 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 349 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 358 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 354 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 353 7 0 82 -1 3 0 21
|
|
34 VMA 5 355 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 352 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
301 inst_nEXP_SPACE_D0reg 3 -1 3 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21
|
|
353 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
317 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
300 inst_AS_030_D0 3 -1 7 6 0 3 4 5 6 7 -1 -1 1 0 21
|
|
319 CLK_000_D_0_ 3 -1 3 5 0 2 3 5 7 -1 -1 1 0 21
|
|
318 CLK_000_D_1_ 3 -1 0 5 0 2 3 5 7 -1 -1 1 0 21
|
|
347 SM_AMIGA_i_7_ 3 -1 2 4 0 3 5 7 -1 -1 12 0 21
|
|
344 SM_AMIGA_1_ 3 -1 0 4 0 2 5 7 -1 -1 3 0 21
|
|
321 SM_AMIGA_5_ 3 -1 5 4 2 5 6 7 -1 -1 3 0 21
|
|
303 inst_BGACK_030_INT_D 3 -1 7 4 0 1 2 6 -1 -1 1 0 21
|
|
346 SM_AMIGA_2_ 3 -1 2 3 0 2 5 -1 -1 5 0 21
|
|
297 cpu_est_2_ 3 -1 3 3 2 3 6 -1 -1 4 0 21
|
|
334 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 3 0 21
|
|
308 SIZE_DMA_0_ 3 -1 1 3 1 6 7 -1 -1 3 0 21
|
|
296 cpu_est_1_ 3 -1 2 3 2 3 6 -1 -1 3 0 21
|
|
294 cpu_est_3_ 3 -1 2 3 2 3 6 -1 -1 3 0 21
|
|
313 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
|
305 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 9 0 21
|
|
345 SM_AMIGA_3_ 3 -1 2 2 2 5 -1 -1 8 0 21
|
|
304 inst_AS_000_DMA 3 -1 1 2 1 7 -1 -1 7 0 21
|
|
302 inst_AS_030_000_SYNC 3 -1 0 2 0 5 -1 -1 7 0 21
|
|
336 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 5 0 21
|
|
307 CYCLE_DMA_1_ 3 -1 3 2 1 3 -1 -1 4 0 21
|
|
355 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21
|
|
342 SM_AMIGA_6_ 3 -1 5 2 2 5 -1 -1 3 0 21
|
|
338 SM_AMIGA_4_ 3 -1 2 2 2 5 -1 -1 3 0 21
|
|
312 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21
|
|
309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
306 CYCLE_DMA_0_ 3 -1 3 2 1 3 -1 -1 3 0 21
|
|
335 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
311 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21
|
|
295 cpu_est_0_ 3 -1 3 2 2 3 -1 -1 2 0 21
|
|
337 inst_CLK_000_NE_D0 3 -1 5 2 2 3 -1 -1 1 0 21
|
|
314 CLK_000_D_10_ 3 -1 5 2 0 7 -1 -1 1 0 21
|
|
310 inst_VPA_D 3 -1 0 2 2 3 -1 -1 1 0 21
|
|
358 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
350 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
349 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
343 inst_CLK_030_H 3 -1 1 1 1 -1 -1 8 0 21
|
|
354 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
351 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
|
339 RST_DLY_0_ 3 -1 0 1 0 -1 -1 4 0 21
|
|
293 N_206_i 3 -1 5 1 2 -1 -1 4 0 21
|
|
357 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
356 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
352 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
348 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
341 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
340 RST_DLY_1_ 3 -1 0 1 0 -1 -1 2 1 21
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21
|
|
333 CLK_000_D_12_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
332 CLK_000_D_9_ 3 -1 6 1 5 -1 -1 1 0 21
|
|
331 CLK_000_D_8_ 3 -1 4 1 6 -1 -1 1 0 21
|
|
330 CLK_000_D_7_ 3 -1 0 1 4 -1 -1 1 0 21
|
|
329 CLK_000_D_6_ 3 -1 4 1 0 -1 -1 1 0 21
|
|
328 CLK_000_D_5_ 3 -1 2 1 4 -1 -1 1 0 21
|
|
327 CLK_000_D_4_ 3 -1 5 1 2 -1 -1 1 0 21
|
|
326 CLK_000_D_3_ 3 -1 0 1 5 -1 -1 1 0 21
|
|
325 CLK_000_D_2_ 3 -1 3 1 0 -1 -1 1 0 21
|
|
324 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
323 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
322 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
320 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
316 inst_DTACK_D0 3 -1 3 1 2 -1 -1 1 0 21
|
|
315 CLK_000_D_11_ 3 -1 0 1 7 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_DECODE_19_ 1 -1 -1 3 0 4 7 96 -1
|
|
95 A_DECODE_16_ 1 -1 -1 3 0 4 7 95 -1
|
|
94 A_DECODE_18_ 1 -1 -1 3 0 4 7 94 -1
|
|
58 A_DECODE_17_ 1 -1 -1 3 0 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 0 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 0 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 3 66 -1
|
|
63 CLK_030 1 -1 -1 2 1 7 63 -1
|
|
59 A_1_ 1 -1 -1 2 2 6 59 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
|
35 VPA 1 -1 -1 1 0 35 -1
|
|
29 DTACK 1 -1 -1 1 3 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 3 13 -1
|
|
10 CLK_000 1 -1 -1 1 3 10 -1
|
|
126 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 5 1 2 5 6 7 40 -1 1 0 21
|
|
41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21
|
|
79 RW_000 5 352 7 3 2 4 6 79 -1 4 0 21
|
|
68 A_0_ 5 348 6 2 0 2 68 -1 3 0 21
|
|
70 RW 5 357 6 2 5 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 2 6 31 -1 1 0 21
|
|
78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21
|
|
30 LDS_000 5 -1 3 1 2 30 -1 1 0 21
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
|
8 IPL_030_2_ 5 351 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 350 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 349 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 355 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 354 7 0 82 -1 3 0 21
|
|
34 VMA 5 356 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 353 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
301 inst_nEXP_SPACE_D0reg 3 -1 3 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21
|
|
354 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
317 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
319 CLK_000_D_0_ 3 -1 0 6 0 1 3 4 5 7 -1 -1 1 0 21
|
|
318 CLK_000_D_1_ 3 -1 7 6 0 1 3 4 5 7 -1 -1 1 0 21
|
|
300 inst_AS_030_D0 3 -1 7 6 2 3 4 5 6 7 -1 -1 1 0 21
|
|
346 SM_AMIGA_i_7_ 3 -1 5 5 1 3 5 6 7 -1 -1 12 0 21
|
|
341 SM_AMIGA_6_ 3 -1 1 4 0 1 2 5 -1 -1 3 0 21
|
|
303 inst_BGACK_030_INT_D 3 -1 4 4 0 2 3 6 -1 -1 1 0 21
|
|
302 inst_AS_030_000_SYNC 3 -1 6 3 1 5 6 -1 -1 7 0 21
|
|
297 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
|
321 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21
|
|
309 SIZE_DMA_1_ 3 -1 2 3 2 6 7 -1 -1 3 0 21
|
|
308 SIZE_DMA_0_ 3 -1 2 3 2 6 7 -1 -1 3 0 21
|
|
296 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
294 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
313 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
|
305 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21
|
|
304 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21
|
|
335 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 5 0 21
|
|
307 CYCLE_DMA_1_ 3 -1 0 2 0 2 -1 -1 4 0 21
|
|
356 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
343 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
333 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
312 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21
|
|
306 CYCLE_DMA_0_ 3 -1 0 2 0 2 -1 -1 3 0 21
|
|
311 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
|
|
295 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 2 0 21
|
|
336 inst_CLK_000_NE_D0 3 -1 4 2 3 5 -1 -1 1 0 21
|
|
315 CLK_000_D_10_ 3 -1 6 2 3 7 -1 -1 1 0 21
|
|
314 CLK_000_D_9_ 3 -1 1 2 6 7 -1 -1 1 0 21
|
|
310 inst_VPA_D 3 -1 6 2 3 5 -1 -1 1 0 21
|
|
351 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
350 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
349 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
344 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 8 0 21
|
|
342 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21
|
|
345 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 5 0 21
|
|
355 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
352 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
|
338 RST_DLY_0_ 3 -1 0 1 0 -1 -1 4 0 21
|
|
293 N_229_i 3 -1 5 1 5 -1 -1 4 0 21
|
|
348 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
337 SM_AMIGA_4_ 3 -1 5 1 5 -1 -1 3 0 21
|
|
357 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
353 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
347 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
340 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
339 RST_DLY_1_ 3 -1 0 1 0 -1 -1 2 1 21
|
|
334 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 3 1 3 -1 -1 2 0 21
|
|
332 CLK_000_D_11_ 3 -1 3 1 7 -1 -1 1 0 21
|
|
331 CLK_000_D_8_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
330 CLK_000_D_7_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
329 CLK_000_D_6_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
328 CLK_000_D_5_ 3 -1 1 1 3 -1 -1 1 0 21
|
|
327 CLK_000_D_4_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
326 CLK_000_D_3_ 3 -1 3 1 2 -1 -1 1 0 21
|
|
325 CLK_000_D_2_ 3 -1 7 1 3 -1 -1 1 0 21
|
|
324 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
323 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
322 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
320 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
316 inst_DTACK_D0 3 -1 0 1 5 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1
|
|
96 A_DECODE_19_ 1 -1 -1 3 4 6 7 96 -1
|
|
95 A_DECODE_16_ 1 -1 -1 3 4 6 7 95 -1
|
|
94 A_DECODE_18_ 1 -1 -1 3 4 6 7 94 -1
|
|
58 A_DECODE_17_ 1 -1 -1 3 4 6 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 4 6 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 4 6 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
66 IPL_0_ 1 -1 -1 2 0 1 66 -1
|
|
63 CLK_030 1 -1 -1 2 2 7 63 -1
|
|
59 A_1_ 1 -1 -1 2 0 3 59 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
|
35 VPA 1 -1 -1 1 6 35 -1
|
|
29 DTACK 1 -1 -1 1 0 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 3 13 -1
|
|
10 CLK_000 1 -1 -1 1 0 10 -1
|
|
128 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21
|
|
40 BERR 5 -1 4 4 0 5 6 7 40 -1 1 0 21
|
|
79 RW_000 5 353 7 3 2 4 6 79 -1 4 0 21
|
|
70 RW 5 358 6 2 0 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 2 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 2 6 30 -1 1 0 21
|
|
68 A_0_ 5 359 6 1 2 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 2 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
|
8 IPL_030_2_ 5 352 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 351 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 350 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 356 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 355 7 0 82 -1 3 0 21
|
|
34 VMA 5 357 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 354 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
355 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21
|
|
301 inst_nEXP_SPACE_D0reg 3 -1 3 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21
|
|
317 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
318 CLK_000_D_1_ 3 -1 3 6 0 2 3 4 5 7 -1 -1 1 0 21
|
|
348 SM_AMIGA_i_7_ 3 -1 5 5 0 3 5 6 7 -1 -1 12 0 21
|
|
319 CLK_000_D_0_ 3 -1 2 5 0 2 3 5 7 -1 -1 1 0 21
|
|
300 inst_AS_030_D0 3 -1 4 5 0 3 4 6 7 -1 -1 1 0 21
|
|
297 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
|
343 SM_AMIGA_6_ 3 -1 5 3 0 2 5 -1 -1 3 0 21
|
|
335 SM_AMIGA_0_ 3 -1 7 3 0 5 7 -1 -1 3 0 21
|
|
321 SM_AMIGA_5_ 3 -1 0 3 0 5 7 -1 -1 3 0 21
|
|
296 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
294 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
295 cpu_est_0_ 3 -1 1 3 1 3 5 -1 -1 2 0 21
|
|
338 inst_CLK_000_NE_D0 3 -1 7 3 1 3 5 -1 -1 1 0 21
|
|
313 inst_CLK_OUT_PRE_D 3 -1 3 3 1 6 7 -1 -1 1 0 21
|
|
305 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21
|
|
304 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21
|
|
302 inst_AS_030_000_SYNC 3 -1 6 2 5 6 -1 -1 7 0 21
|
|
337 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 5 0 21
|
|
357 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
345 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
339 SM_AMIGA_4_ 3 -1 5 2 0 5 -1 -1 3 0 21
|
|
312 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21
|
|
309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
336 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
311 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21
|
|
320 inst_CLK_OUT_PRE_50 3 -1 4 2 3 4 -1 -1 1 0 21
|
|
315 CLK_000_D_12_ 3 -1 7 2 1 7 -1 -1 1 0 21
|
|
310 inst_VPA_D 3 -1 1 2 3 5 -1 -1 1 0 21
|
|
303 inst_BGACK_030_INT_D 3 -1 5 2 1 6 -1 -1 1 0 21
|
|
352 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
351 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
350 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
346 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 8 0 21
|
|
344 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21
|
|
347 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 5 0 21
|
|
356 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
353 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
|
340 RST_DLY_0_ 3 -1 0 1 0 -1 -1 4 0 21
|
|
307 CYCLE_DMA_1_ 3 -1 2 1 2 -1 -1 4 0 21
|
|
293 N_206_i 3 -1 5 1 5 -1 -1 4 0 21
|
|
359 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
306 CYCLE_DMA_0_ 3 -1 2 1 2 -1 -1 3 0 21
|
|
358 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
354 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
349 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
342 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
341 RST_DLY_1_ 3 -1 0 1 0 -1 -1 2 1 21
|
|
334 CLK_000_D_13_ 3 -1 1 1 7 -1 -1 1 0 21
|
|
333 CLK_000_D_10_ 3 -1 3 1 4 -1 -1 1 0 21
|
|
332 CLK_000_D_9_ 3 -1 0 1 3 -1 -1 1 0 21
|
|
331 CLK_000_D_8_ 3 -1 2 1 0 -1 -1 1 0 21
|
|
330 CLK_000_D_7_ 3 -1 5 1 2 -1 -1 1 0 21
|
|
329 CLK_000_D_6_ 3 -1 0 1 5 -1 -1 1 0 21
|
|
328 CLK_000_D_5_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
327 CLK_000_D_4_ 3 -1 3 1 0 -1 -1 1 0 21
|
|
326 CLK_000_D_3_ 3 -1 3 1 3 -1 -1 1 0 21
|
|
325 CLK_000_D_2_ 3 -1 4 1 3 -1 -1 1 0 21
|
|
324 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
323 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
322 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
316 inst_DTACK_D0 3 -1 0 1 5 -1 -1 1 0 21
|
|
314 CLK_000_D_11_ 3 -1 4 1 7 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1
|
|
96 A_DECODE_19_ 1 -1 -1 3 4 6 7 96 -1
|
|
95 A_DECODE_16_ 1 -1 -1 3 4 6 7 95 -1
|
|
94 A_DECODE_18_ 1 -1 -1 3 4 6 7 94 -1
|
|
58 A_DECODE_17_ 1 -1 -1 3 4 6 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 4 6 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 4 6 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
67 IPL_2_ 1 -1 -1 2 1 6 67 -1
|
|
63 CLK_030 1 -1 -1 2 2 7 63 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
|
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
|
59 A_1_ 1 -1 -1 1 1 59 -1
|
|
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
|
35 VPA 1 -1 -1 1 1 35 -1
|
|
29 DTACK 1 -1 -1 1 0 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 3 13 -1
|
|
10 CLK_000 1 -1 -1 1 2 10 -1
|
|
128 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 5 0 2 5 6 7 40 -1 1 0 21
|
|
41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21
|
|
79 RW_000 5 351 7 3 2 4 6 79 -1 4 0 21
|
|
68 A_0_ 5 352 6 2 1 5 68 -1 3 0 21
|
|
70 RW 5 359 6 2 6 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 2 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 2 6 30 -1 1 0 21
|
|
78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
|
8 IPL_030_2_ 5 350 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 354 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 353 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 357 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 356 7 0 82 -1 3 0 21
|
|
34 VMA 5 358 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 355 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
301 inst_nEXP_SPACE_D0reg 3 -1 1 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21
|
|
356 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
318 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
319 CLK_000_D_0_ 3 -1 3 7 0 2 3 4 5 6 7 -1 -1 1 0 21
|
|
314 CLK_000_D_1_ 3 -1 4 6 0 2 3 5 6 7 -1 -1 1 0 21
|
|
300 inst_AS_030_D0 3 -1 7 6 0 2 3 4 6 7 -1 -1 1 0 21
|
|
348 SM_AMIGA_i_7_ 3 -1 5 5 0 3 5 6 7 -1 -1 12 0 21
|
|
321 SM_AMIGA_5_ 3 -1 6 4 2 5 6 7 -1 -1 3 0 21
|
|
303 inst_BGACK_030_INT_D 3 -1 0 4 0 1 3 6 -1 -1 1 0 21
|
|
294 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 4 0 21
|
|
343 SM_AMIGA_6_ 3 -1 5 3 1 5 6 -1 -1 3 0 21
|
|
335 SM_AMIGA_0_ 3 -1 7 3 5 6 7 -1 -1 3 0 21
|
|
297 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
295 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
313 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
|
305 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21
|
|
304 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21
|
|
302 inst_AS_030_000_SYNC 3 -1 0 2 0 5 -1 -1 7 0 21
|
|
337 inst_DS_000_ENABLE 3 -1 6 2 3 6 -1 -1 5 0 21
|
|
358 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
345 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
339 SM_AMIGA_4_ 3 -1 5 2 5 6 -1 -1 3 0 21
|
|
312 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21
|
|
309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
311 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
|
|
296 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21
|
|
338 inst_CLK_000_NE_D0 3 -1 7 2 3 5 -1 -1 1 0 21
|
|
325 CLK_000_D_2_ 3 -1 5 2 3 5 -1 -1 1 0 21
|
|
316 CLK_000_D_12_ 3 -1 4 2 3 7 -1 -1 1 0 21
|
|
315 CLK_000_D_11_ 3 -1 3 2 4 7 -1 -1 1 0 21
|
|
310 inst_VPA_D 3 -1 0 2 3 5 -1 -1 1 0 21
|
|
354 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
353 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
350 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
346 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 8 0 21
|
|
344 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21
|
|
347 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 5 0 21
|
|
357 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
351 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
|
340 RST_DLY_0_ 3 -1 0 1 0 -1 -1 4 0 21
|
|
307 CYCLE_DMA_1_ 3 -1 2 1 2 -1 -1 4 0 21
|
|
293 N_331 3 -1 5 1 5 -1 -1 4 0 21
|
|
352 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
306 CYCLE_DMA_0_ 3 -1 2 1 2 -1 -1 3 0 21
|
|
359 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
355 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
349 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
342 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
341 RST_DLY_1_ 3 -1 0 1 0 -1 -1 2 1 21
|
|
336 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 3 1 3 -1 -1 2 0 21
|
|
334 CLK_000_D_13_ 3 -1 3 1 7 -1 -1 1 0 21
|
|
333 CLK_000_D_10_ 3 -1 0 1 3 -1 -1 1 0 21
|
|
332 CLK_000_D_9_ 3 -1 1 1 0 -1 -1 1 0 21
|
|
331 CLK_000_D_8_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
330 CLK_000_D_7_ 3 -1 5 1 2 -1 -1 1 0 21
|
|
329 CLK_000_D_6_ 3 -1 5 1 5 -1 -1 1 0 21
|
|
328 CLK_000_D_5_ 3 -1 1 1 5 -1 -1 1 0 21
|
|
327 CLK_000_D_4_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
326 CLK_000_D_3_ 3 -1 3 1 2 -1 -1 1 0 21
|
|
324 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
323 IPL_D0_1_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
322 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
320 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
317 inst_DTACK_D0 3 -1 1 1 5 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_DECODE_19_ 1 -1 -1 3 0 4 7 96 -1
|
|
95 A_DECODE_16_ 1 -1 -1 3 0 4 7 95 -1
|
|
94 A_DECODE_18_ 1 -1 -1 3 0 4 7 94 -1
|
|
58 A_DECODE_17_ 1 -1 -1 3 0 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 0 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 0 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
67 IPL_2_ 1 -1 -1 2 0 1 67 -1
|
|
66 IPL_0_ 1 -1 -1 2 0 1 66 -1
|
|
63 CLK_030 1 -1 -1 2 2 7 63 -1
|
|
59 A_1_ 1 -1 -1 2 1 3 59 -1
|
|
55 IPL_1_ 1 -1 -1 2 0 1 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
|
35 VPA 1 -1 -1 1 0 35 -1
|
|
29 DTACK 1 -1 -1 1 1 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 1 13 -1
|
|
10 CLK_000 1 -1 -1 1 3 10 -1
|
|
127 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
41 AS_000 5 -1 4 4 0 4 6 7 41 -1 1 0 21
|
|
40 BERR 5 -1 4 4 1 2 5 7 40 -1 1 0 21
|
|
79 RW_000 5 350 7 2 4 6 79 -1 4 0 21
|
|
70 RW 5 358 6 2 2 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
68 A_0_ 5 351 6 1 0 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
|
8 IPL_030_2_ 5 349 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 353 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 352 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 356 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 355 7 0 82 -1 3 0 21
|
|
34 VMA 5 357 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 354 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
301 inst_nEXP_SPACE_D0reg 3 -1 2 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21
|
|
355 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
318 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
314 CLK_000_D_1_ 3 -1 7 6 0 1 2 3 5 7 -1 -1 1 0 21
|
|
347 SM_AMIGA_i_7_ 3 -1 5 5 1 2 3 5 7 -1 -1 12 0 21
|
|
319 CLK_000_D_0_ 3 -1 3 5 0 2 3 5 7 -1 -1 1 0 21
|
|
300 inst_AS_030_D0 3 -1 4 5 1 2 3 4 7 -1 -1 1 0 21
|
|
304 inst_AS_000_DMA 3 -1 0 3 0 6 7 -1 -1 7 0 21
|
|
294 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
|
342 SM_AMIGA_6_ 3 -1 5 3 0 2 5 -1 -1 3 0 21
|
|
334 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 3 0 21
|
|
321 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21
|
|
297 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
295 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
313 inst_CLK_OUT_PRE_D 3 -1 3 3 1 6 7 -1 -1 1 0 21
|
|
303 inst_BGACK_030_INT_D 3 -1 7 3 1 2 6 -1 -1 1 0 21
|
|
305 inst_DS_000_DMA 3 -1 6 2 0 6 -1 -1 9 0 21
|
|
343 inst_CLK_030_H 3 -1 0 2 0 6 -1 -1 8 0 21
|
|
302 inst_AS_030_000_SYNC 3 -1 1 2 1 5 -1 -1 7 0 21
|
|
336 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21
|
|
307 CYCLE_DMA_1_ 3 -1 0 2 0 6 -1 -1 4 0 21
|
|
357 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
344 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
338 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21
|
|
312 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21
|
|
309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
306 CYCLE_DMA_0_ 3 -1 0 2 0 6 -1 -1 3 0 21
|
|
335 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21
|
|
311 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
|
|
296 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 2 0 21
|
|
337 inst_CLK_000_NE_D0 3 -1 2 2 3 5 -1 -1 1 0 21
|
|
325 CLK_000_D_2_ 3 -1 1 2 4 5 -1 -1 1 0 21
|
|
320 inst_CLK_OUT_PRE_50 3 -1 1 2 1 3 -1 -1 1 0 21
|
|
315 CLK_000_D_10_ 3 -1 4 2 2 7 -1 -1 1 0 21
|
|
310 inst_VPA_D 3 -1 0 2 3 5 -1 -1 1 0 21
|
|
353 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
352 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
349 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
345 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 8 0 21
|
|
346 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 5 0 21
|
|
356 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
350 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
|
339 RST_DLY_0_ 3 -1 0 1 0 -1 -1 4 0 21
|
|
293 N_331 3 -1 5 1 5 -1 -1 4 0 21
|
|
351 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
358 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
354 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
348 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
341 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
340 RST_DLY_1_ 3 -1 0 1 0 -1 -1 2 1 21
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21
|
|
333 CLK_000_D_12_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
332 CLK_000_D_9_ 3 -1 4 1 4 -1 -1 1 0 21
|
|
331 CLK_000_D_8_ 3 -1 5 1 4 -1 -1 1 0 21
|
|
330 CLK_000_D_7_ 3 -1 2 1 5 -1 -1 1 0 21
|
|
329 CLK_000_D_6_ 3 -1 5 1 2 -1 -1 1 0 21
|
|
328 CLK_000_D_5_ 3 -1 6 1 5 -1 -1 1 0 21
|
|
327 CLK_000_D_4_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
326 CLK_000_D_3_ 3 -1 4 1 3 -1 -1 1 0 21
|
|
324 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
323 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
322 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
317 inst_DTACK_D0 3 -1 3 1 5 -1 -1 1 0 21
|
|
316 CLK_000_D_11_ 3 -1 2 1 7 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1
|
|
96 A_DECODE_19_ 1 -1 -1 3 1 4 7 96 -1
|
|
95 A_DECODE_16_ 1 -1 -1 3 1 4 7 95 -1
|
|
94 A_DECODE_18_ 1 -1 -1 3 1 4 7 94 -1
|
|
63 CLK_030 1 -1 -1 3 0 6 7 63 -1
|
|
58 A_DECODE_17_ 1 -1 -1 3 1 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 1 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 1 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
|
59 A_1_ 1 -1 -1 1 2 59 -1
|
|
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
|
35 VPA 1 -1 -1 1 0 35 -1
|
|
29 DTACK 1 -1 -1 1 3 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 2 13 -1
|
|
10 CLK_000 1 -1 -1 1 3 10 -1
|
|
127 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
41 AS_000 5 -1 4 5 0 1 4 6 7 41 -1 1 0 21
|
|
40 BERR 5 -1 4 5 0 2 5 6 7 40 -1 1 0 21
|
|
79 RW_000 5 350 7 2 4 6 79 -1 4 0 21
|
|
70 RW 5 358 6 2 0 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
68 A_0_ 5 351 6 1 5 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 5 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 5 69 -1 1 0 21
|
|
31 UDS_000 5 -1 3 1 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 1 6 30 -1 1 0 21
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
|
8 IPL_030_2_ 5 349 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 353 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 352 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 356 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 355 7 0 82 -1 3 0 21
|
|
34 VMA 5 357 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 354 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
355 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21
|
|
301 inst_nEXP_SPACE_D0reg 3 -1 5 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21
|
|
318 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
300 inst_AS_030_D0 3 -1 7 6 0 3 4 5 6 7 -1 -1 1 0 21
|
|
319 CLK_000_D_0_ 3 -1 2 5 0 1 2 3 7 -1 -1 1 0 21
|
|
314 CLK_000_D_1_ 3 -1 7 5 0 1 2 3 7 -1 -1 1 0 21
|
|
347 SM_AMIGA_i_7_ 3 -1 2 4 0 3 5 7 -1 -1 12 0 21
|
|
321 SM_AMIGA_5_ 3 -1 2 4 0 2 6 7 -1 -1 3 0 21
|
|
302 inst_AS_030_000_SYNC 3 -1 5 3 0 2 5 -1 -1 7 0 21
|
|
294 cpu_est_2_ 3 -1 3 3 2 3 6 -1 -1 4 0 21
|
|
342 SM_AMIGA_6_ 3 -1 0 3 0 2 5 -1 -1 3 0 21
|
|
334 SM_AMIGA_0_ 3 -1 7 3 0 2 7 -1 -1 3 0 21
|
|
297 cpu_est_1_ 3 -1 2 3 2 3 6 -1 -1 3 0 21
|
|
295 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 3 0 21
|
|
325 CLK_000_D_2_ 3 -1 7 3 0 2 3 -1 -1 1 0 21
|
|
313 inst_CLK_OUT_PRE_D 3 -1 3 3 1 6 7 -1 -1 1 0 21
|
|
303 inst_BGACK_030_INT_D 3 -1 5 3 1 5 6 -1 -1 1 0 21
|
|
305 inst_DS_000_DMA 3 -1 6 2 0 6 -1 -1 9 0 21
|
|
304 inst_AS_000_DMA 3 -1 6 2 6 7 -1 -1 7 0 21
|
|
336 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 5 0 21
|
|
339 RST_DLY_0_ 3 -1 1 2 0 1 -1 -1 4 0 21
|
|
307 CYCLE_DMA_1_ 3 -1 1 2 1 6 -1 -1 4 0 21
|
|
357 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21
|
|
344 SM_AMIGA_1_ 3 -1 2 2 2 7 -1 -1 3 0 21
|
|
338 SM_AMIGA_4_ 3 -1 2 2 0 2 -1 -1 3 0 21
|
|
312 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21
|
|
309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
306 CYCLE_DMA_0_ 3 -1 1 2 1 6 -1 -1 3 0 21
|
|
341 RST_DLY_2_ 3 -1 0 2 0 1 -1 -1 2 0 21
|
|
340 RST_DLY_1_ 3 -1 1 2 0 1 -1 -1 2 1 21
|
|
335 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
311 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21
|
|
296 cpu_est_0_ 3 -1 2 2 2 3 -1 -1 2 0 21
|
|
337 inst_CLK_000_NE_D0 3 -1 7 2 2 3 -1 -1 1 0 21
|
|
316 CLK_000_D_11_ 3 -1 7 2 0 7 -1 -1 1 0 21
|
|
310 inst_VPA_D 3 -1 3 2 2 3 -1 -1 1 0 21
|
|
353 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
352 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
349 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
345 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 8 0 21
|
|
343 inst_CLK_030_H 3 -1 6 1 6 -1 -1 8 0 21
|
|
346 SM_AMIGA_2_ 3 -1 2 1 2 -1 -1 5 0 21
|
|
356 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
350 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
|
293 N_331 3 -1 2 1 2 -1 -1 4 0 21
|
|
351 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
358 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
354 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
348 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
333 CLK_000_D_12_ 3 -1 0 1 7 -1 -1 1 0 21
|
|
332 CLK_000_D_9_ 3 -1 3 1 0 -1 -1 1 0 21
|
|
331 CLK_000_D_8_ 3 -1 0 1 3 -1 -1 1 0 21
|
|
330 CLK_000_D_7_ 3 -1 1 1 0 -1 -1 1 0 21
|
|
329 CLK_000_D_6_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
328 CLK_000_D_5_ 3 -1 3 1 5 -1 -1 1 0 21
|
|
327 CLK_000_D_4_ 3 -1 5 1 3 -1 -1 1 0 21
|
|
326 CLK_000_D_3_ 3 -1 3 1 5 -1 -1 1 0 21
|
|
324 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
323 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
322 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
320 inst_CLK_OUT_PRE_50 3 -1 3 1 3 -1 -1 1 0 21
|
|
317 inst_DTACK_D0 3 -1 3 1 2 -1 -1 1 0 21
|
|
315 CLK_000_D_10_ 3 -1 0 1 7 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1
|
|
95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1
|
|
94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1
|
|
58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 4 5 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 4 5 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 3 66 -1
|
|
63 CLK_030 1 -1 -1 2 6 7 63 -1
|
|
59 A_1_ 1 -1 -1 2 1 5 59 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
|
35 VPA 1 -1 -1 1 3 35 -1
|
|
29 DTACK 1 -1 -1 1 3 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 5 13 -1
|
|
10 CLK_000 1 -1 -1 1 2 10 -1
|
|
126 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 5 0 2 5 6 7 40 -1 1 0 21
|
|
79 RW_000 5 350 7 3 0 4 6 79 -1 4 0 21
|
|
81 AS_030 5 -1 7 3 1 4 7 81 -1 1 0 21
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
70 RW 5 357 6 2 2 7 70 -1 2 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
68 A_0_ 5 349 6 1 1 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
|
8 IPL_030_2_ 5 348 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 352 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 351 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 355 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 354 7 0 82 -1 3 0 21
|
|
34 VMA 5 356 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 353 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
354 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21
|
|
301 inst_nEXP_SPACE_D0reg 3 -1 2 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21
|
|
318 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
319 CLK_000_D_0_ 3 -1 3 6 0 2 3 5 6 7 -1 -1 1 0 21
|
|
314 CLK_000_D_1_ 3 -1 6 6 0 2 3 4 5 7 -1 -1 1 0 21
|
|
300 inst_AS_030_D0 3 -1 1 5 2 3 4 6 7 -1 -1 1 0 21
|
|
346 SM_AMIGA_i_7_ 3 -1 5 4 2 3 6 7 -1 -1 12 0 21
|
|
341 SM_AMIGA_6_ 3 -1 2 4 0 1 2 5 -1 -1 3 0 21
|
|
321 SM_AMIGA_5_ 3 -1 0 4 0 2 5 7 -1 -1 3 0 21
|
|
302 inst_AS_030_000_SYNC 3 -1 6 3 2 5 6 -1 -1 7 0 21
|
|
294 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 4 0 21
|
|
333 SM_AMIGA_0_ 3 -1 7 3 2 5 7 -1 -1 3 0 21
|
|
297 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
295 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
313 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
|
304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
335 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21
|
|
356 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
343 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
337 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21
|
|
312 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21
|
|
309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
334 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21
|
|
311 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
|
|
296 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 2 0 21
|
|
336 inst_CLK_000_NE_D0 3 -1 3 2 3 5 -1 -1 1 0 21
|
|
325 CLK_000_D_2_ 3 -1 4 2 2 5 -1 -1 1 0 21
|
|
310 inst_VPA_D 3 -1 3 2 3 5 -1 -1 1 0 21
|
|
303 inst_BGACK_030_INT_D 3 -1 5 2 2 6 -1 -1 1 0 21
|
|
352 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
351 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
348 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
344 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 8 0 21
|
|
342 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
345 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 5 0 21
|
|
355 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
350 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
|
338 RST_DLY_0_ 3 -1 0 1 0 -1 -1 4 0 21
|
|
307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21
|
|
293 N_331 3 -1 5 1 5 -1 -1 4 0 21
|
|
349 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
306 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
357 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
353 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
347 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
340 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
339 RST_DLY_1_ 3 -1 0 1 0 -1 -1 2 1 21
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21
|
|
332 CLK_000_D_11_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
331 CLK_000_D_8_ 3 -1 3 1 3 -1 -1 1 0 21
|
|
330 CLK_000_D_7_ 3 -1 5 1 3 -1 -1 1 0 21
|
|
329 CLK_000_D_6_ 3 -1 5 1 5 -1 -1 1 0 21
|
|
328 CLK_000_D_5_ 3 -1 1 1 5 -1 -1 1 0 21
|
|
327 CLK_000_D_4_ 3 -1 4 1 1 -1 -1 1 0 21
|
|
326 CLK_000_D_3_ 3 -1 5 1 4 -1 -1 1 0 21
|
|
324 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
323 IPL_D0_1_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
322 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
320 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
317 inst_DTACK_D0 3 -1 0 1 5 -1 -1 1 0 21
|
|
316 CLK_000_D_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
315 CLK_000_D_9_ 3 -1 3 1 7 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_DECODE_19_ 1 -1 -1 3 4 6 7 96 -1
|
|
95 A_DECODE_16_ 1 -1 -1 3 4 6 7 95 -1
|
|
94 A_DECODE_18_ 1 -1 -1 3 4 6 7 94 -1
|
|
58 A_DECODE_17_ 1 -1 -1 3 4 6 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 4 6 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 4 6 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
66 IPL_0_ 1 -1 -1 2 0 1 66 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 2 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
59 A_1_ 1 -1 -1 1 2 59 -1
|
|
35 VPA 1 -1 -1 1 3 35 -1
|
|
29 DTACK 1 -1 -1 1 0 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 2 13 -1
|
|
10 CLK_000 1 -1 -1 1 3 10 -1
|
|
151 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21
|
|
79 RW_000 5 374 7 3 0 4 6 79 -1 3 0 21
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
70 RW 5 382 6 2 2 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
68 A_0_ 5 375 6 1 1 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
|
8 IPL_030_2_ 5 373 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 377 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 376 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 380 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 379 7 0 82 -1 3 0 21
|
|
34 VMA 5 381 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 378 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
300 inst_nEXP_SPACE_D0reg 3 -1 6 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21
|
|
379 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
316 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
320 CLK_000_P_SYNC_10_ 3 -1 6 5 0 2 3 5 7 -1 -1 1 0 21
|
|
299 inst_AS_030_D0 3 -1 7 5 0 2 3 4 7 -1 -1 1 0 21
|
|
321 SM_AMIGA_5_ 3 -1 5 4 0 2 5 7 -1 -1 3 0 21
|
|
371 SM_AMIGA_i_7_ 3 -1 5 3 2 3 7 -1 -1 14 0 21
|
|
293 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 4 0 21
|
|
366 SM_AMIGA_6_ 3 -1 2 3 1 2 5 -1 -1 3 0 21
|
|
296 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
294 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
334 SM_AMIGA_0_ 3 -1 7 3 2 5 7 -1 -1 2 0 21
|
|
339 CLK_000_N_SYNC_12_ 3 -1 3 3 3 5 7 -1 -1 1 0 21
|
|
312 inst_CLK_OUT_PRE_D 3 -1 5 3 1 6 7 -1 -1 1 0 21
|
|
302 inst_BGACK_030_INT_D 3 -1 2 3 1 2 6 -1 -1 1 0 21
|
|
303 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
301 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21
|
|
338 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21
|
|
381 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
368 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
337 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21
|
|
311 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21
|
|
308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
335 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
310 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
297 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21
|
|
295 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21
|
|
365 inst_CLK_000_NE_D0 3 -1 7 2 3 5 -1 -1 1 0 21
|
|
336 CLK_000_N_SYNC_0_ 3 -1 4 2 2 5 -1 -1 1 0 21
|
|
319 CLK_000_D_0_ 3 -1 3 2 3 4 -1 -1 1 0 21
|
|
309 inst_VPA_D 3 -1 1 2 3 5 -1 -1 1 0 21
|
|
377 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
376 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
373 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
304 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
367 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
369 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21
|
|
380 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
370 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
341 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21
|
|
375 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
374 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
343 N_194_i 3 -1 5 1 5 -1 -1 3 0 21
|
|
340 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21
|
|
306 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
382 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
378 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
372 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
342 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21
|
|
305 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21
|
|
364 CLK_000_N_SYNC_11_ 3 -1 2 1 3 -1 -1 1 0 21
|
|
363 CLK_000_N_SYNC_10_ 3 -1 1 1 2 -1 -1 1 0 21
|
|
362 CLK_000_N_SYNC_9_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
361 CLK_000_N_SYNC_8_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
360 CLK_000_N_SYNC_7_ 3 -1 2 1 3 -1 -1 1 0 21
|
|
359 CLK_000_N_SYNC_6_ 3 -1 3 1 2 -1 -1 1 0 21
|
|
358 CLK_000_N_SYNC_5_ 3 -1 2 1 3 -1 -1 1 0 21
|
|
357 CLK_000_N_SYNC_4_ 3 -1 0 1 2 -1 -1 1 0 21
|
|
356 CLK_000_N_SYNC_3_ 3 -1 1 1 0 -1 -1 1 0 21
|
|
355 CLK_000_N_SYNC_2_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
354 CLK_000_N_SYNC_1_ 3 -1 5 1 0 -1 -1 1 0 21
|
|
353 CLK_000_P_SYNC_9_ 3 -1 5 1 6 -1 -1 1 0 21
|
|
352 CLK_000_P_SYNC_8_ 3 -1 4 1 5 -1 -1 1 0 21
|
|
351 CLK_000_P_SYNC_7_ 3 -1 0 1 4 -1 -1 1 0 21
|
|
350 CLK_000_P_SYNC_6_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
349 CLK_000_P_SYNC_5_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
348 CLK_000_P_SYNC_4_ 3 -1 0 1 6 -1 -1 1 0 21
|
|
347 CLK_000_P_SYNC_3_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
346 CLK_000_P_SYNC_2_ 3 -1 5 1 6 -1 -1 1 0 21
|
|
345 CLK_000_P_SYNC_1_ 3 -1 0 1 5 -1 -1 1 0 21
|
|
344 CLK_000_P_SYNC_0_ 3 -1 4 1 0 -1 -1 1 0 21
|
|
333 CLK_000_D_12_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
332 CLK_000_D_9_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
331 CLK_000_D_8_ 3 -1 1 1 2 -1 -1 1 0 21
|
|
330 CLK_000_D_7_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
329 CLK_000_D_6_ 3 -1 6 1 5 -1 -1 1 0 21
|
|
328 CLK_000_D_5_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
327 CLK_000_D_4_ 3 -1 2 1 6 -1 -1 1 0 21
|
|
326 CLK_000_D_3_ 3 -1 5 1 2 -1 -1 1 0 21
|
|
325 CLK_000_D_2_ 3 -1 4 1 5 -1 -1 1 0 21
|
|
324 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
323 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
322 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
318 CLK_000_D_1_ 3 -1 4 1 4 -1 -1 1 0 21
|
|
317 inst_CLK_OUT_PRE_50 3 -1 5 1 5 -1 -1 1 0 21
|
|
315 inst_DTACK_D0 3 -1 0 1 5 -1 -1 1 0 21
|
|
314 CLK_000_D_11_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
313 CLK_000_D_10_ 3 -1 1 1 7 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
67 IPL_2_ 1 -1 -1 2 0 1 67 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 6 66 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
59 A_1_ 1 -1 -1 2 1 2 59 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 6 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
|
35 VPA 1 -1 -1 1 1 35 -1
|
|
29 DTACK 1 -1 -1 1 0 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 6 13 -1
|
|
10 CLK_000 1 -1 -1 1 3 10 -1
|
|
141 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
79 RW_000 5 367 7 2 4 6 79 -1 5 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
70 RW 5 372 6 1 7 70 -1 2 0 21
|
|
40 BERR 5 -1 4 1 7 40 -1 1 0 21
|
|
31 UDS_000 5 -1 3 1 6 31 -1 1 0 21
|
|
18 AHIGH_24_ 5 -1 -1 1 4 18 -1 1 0 21
|
|
17 AHIGH_25_ 5 -1 -1 1 4 17 -1 1 0 21
|
|
16 AHIGH_26_ 5 -1 -1 1 4 16 -1 1 0 21
|
|
15 AHIGH_27_ 5 -1 -1 1 4 15 -1 1 0 21
|
|
14 AHIGH_28_ 5 -1 -1 1 4 14 -1 1 0 21
|
|
5 AHIGH_29_ 5 -1 -1 1 4 5 -1 1 0 21
|
|
4 AHIGH_30_ 5 -1 -1 1 4 4 -1 1 0 21
|
|
3 AHIGH_31_ 5 -1 -1 1 4 3 -1 1 0 21
|
|
8 IPL_030_2_ 0 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 0 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 0 1 0 6 -1 10 0 21
|
|
80 DSACK1 0 7 0 80 -1 4 0 21
|
|
82 BGACK_030 0 7 0 82 -1 3 0 21
|
|
68 A_0_ 5 364 6 0 68 -1 3 0 21
|
|
34 VMA 0 3 0 34 -1 3 0 21
|
|
65 E 0 -1 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 -1 0 33 -1 2 0 21
|
|
28 BG_000 0 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 -1 0 91 -1 1 0 21
|
|
78 SIZE_1_ 0 -1 0 78 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
69 SIZE_0_ 0 6 0 69 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 -1 0 32 -1 1 0 21
|
|
30 LDS_000 0 3 0 30 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 -1 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 -1 0 2 -1 1 0 21
|
|
369 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 3 0 21
|
|
317 inst_RESET_OUT 3 -1 -1 5 0 3 4 6 7 -1 -1 2 0 21
|
|
301 inst_nEXP_SPACE_D0reg 3 -1 -1 5 0 3 4 6 7 -1 -1 1 0 21
|
|
313 inst_CLK_OUT_PRE_D 3 -1 -1 3 1 6 7 -1 -1 1 0 21
|
|
300 inst_AS_030_D0 3 -1 -1 3 3 4 7 -1 -1 1 0 21
|
|
319 CLK_000_D_1_ 3 -1 -1 2 3 7 -1 -1 1 0 21
|
|
318 CLK_000_D_0_ 3 -1 -1 2 3 7 -1 -1 1 0 21
|
|
366 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
365 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
363 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
305 inst_DS_000_DMA 3 -1 -1 1 0 -1 -1 9 0 21
|
|
304 inst_AS_000_DMA 3 -1 -1 1 7 -1 -1 7 0 21
|
|
367 RN_RW_000 3 79 7 1 7 79 -1 5 0 21
|
|
337 inst_DS_000_ENABLE 3 -1 -1 1 3 -1 -1 5 0 21
|
|
370 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
334 SM_AMIGA_0_ 3 -1 -1 1 7 -1 -1 4 0 21
|
|
297 cpu_est_2_ 3 -1 -1 1 3 -1 -1 4 0 21
|
|
371 RN_VMA 3 34 3 1 3 34 -1 3 0 21
|
|
364 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
357 SM_AMIGA_1_ 3 -1 -1 1 7 -1 -1 3 0 21
|
|
321 SM_AMIGA_5_ 3 -1 -1 1 7 -1 -1 3 0 21
|
|
312 inst_LDS_000_INT 3 -1 -1 1 3 -1 -1 3 0 21
|
|
309 SIZE_DMA_1_ 3 -1 -1 1 6 -1 -1 3 0 21
|
|
308 SIZE_DMA_0_ 3 -1 -1 1 6 -1 -1 3 0 21
|
|
296 cpu_est_1_ 3 -1 -1 1 3 -1 -1 3 0 21
|
|
293 cpu_est_3_ 3 -1 -1 1 3 -1 -1 3 0 21
|
|
372 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
368 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
361 CIIN_0 3 -1 -1 1 4 -1 -1 2 0 21
|
|
360 SM_AMIGA_i_7_ 3 -1 -1 1 7 -1 -1 2 0 21
|
|
311 inst_UDS_000_INT 3 -1 -1 1 3 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 -1 1 4 -1 -1 2 0 21
|
|
294 cpu_est_0_ 3 -1 -1 1 3 -1 -1 2 0 21
|
|
338 CLK_000_N_SYNC_12_ 3 -1 -1 1 3 -1 -1 1 0 21
|
|
333 CLK_000_D_12_ 3 -1 -1 1 7 -1 -1 1 0 21
|
|
324 IPL_D0_2_ 3 -1 -1 1 1 -1 -1 1 0 21
|
|
323 IPL_D0_1_ 3 -1 -1 1 1 -1 -1 1 0 21
|
|
322 IPL_D0_0_ 3 -1 -1 1 1 -1 -1 1 0 21
|
|
315 CLK_000_D_11_ 3 -1 -1 1 7 -1 -1 1 0 21
|
|
314 CLK_000_D_10_ 3 -1 -1 1 7 -1 -1 1 0 21
|
|
310 inst_VPA_D 3 -1 -1 1 3 -1 -1 1 0 21
|
|
303 inst_BGACK_030_INT_D 3 -1 -1 1 6 -1 -1 1 0 21
|
|
362 SM_AMIGA_i_7__0 3 -1 -1 0 -1 -1 15 0 21
|
|
356 inst_CLK_030_H 3 -1 -1 0 -1 -1 8 0 21
|
|
302 inst_AS_030_000_SYNC 3 -1 -1 0 -1 -1 7 0 21
|
|
359 SM_AMIGA_2_ 3 -1 -1 0 -1 -1 5 0 21
|
|
358 SM_AMIGA_3_ 3 -1 -1 0 -1 -1 5 0 21
|
|
340 RST_DLY_1_ 3 -1 -1 0 -1 -1 4 0 21
|
|
306 CYCLE_DMA_0_ 3 -1 -1 0 -1 -1 4 0 21
|
|
355 SM_AMIGA_6_ 3 -1 -1 0 -1 -1 3 1 21
|
|
353 SM_AMIGA_4_ 3 -1 -1 0 -1 -1 3 1 21
|
|
339 RST_DLY_0_ 3 -1 -1 0 -1 -1 3 0 21
|
|
295 N_208_i 3 -1 -1 0 -1 -1 3 0 21
|
|
341 RST_DLY_2_ 3 -1 -1 0 -1 -1 2 0 21
|
|
335 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 -1 0 -1 -1 2 0 21
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 -1 0 -1 -1 2 0 21
|
|
354 inst_CLK_000_NE_D0 3 -1 -1 0 -1 -1 1 0 21
|
|
352 CLK_000_N_SYNC_11_ 3 -1 -1 0 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_10_ 3 -1 -1 0 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_9_ 3 -1 -1 0 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_8_ 3 -1 -1 0 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_7_ 3 -1 -1 0 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_6_ 3 -1 -1 0 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_5_ 3 -1 -1 0 -1 -1 1 0 21
|
|
345 CLK_000_N_SYNC_4_ 3 -1 -1 0 -1 -1 1 0 21
|
|
344 CLK_000_N_SYNC_3_ 3 -1 -1 0 -1 -1 1 0 21
|
|
343 CLK_000_N_SYNC_2_ 3 -1 -1 0 -1 -1 1 0 21
|
|
342 CLK_000_N_SYNC_1_ 3 -1 -1 0 -1 -1 1 0 21
|
|
336 CLK_000_N_SYNC_0_ 3 -1 -1 0 -1 -1 1 0 21
|
|
332 CLK_000_D_9_ 3 -1 -1 0 -1 -1 1 0 21
|
|
331 CLK_000_D_8_ 3 -1 -1 0 -1 -1 1 0 21
|
|
330 CLK_000_D_7_ 3 -1 -1 0 -1 -1 1 0 21
|
|
329 CLK_000_D_6_ 3 -1 -1 0 -1 -1 1 0 21
|
|
328 CLK_000_D_5_ 3 -1 -1 0 -1 -1 1 0 21
|
|
327 CLK_000_D_4_ 3 -1 -1 0 -1 -1 1 0 21
|
|
326 CLK_000_D_3_ 3 -1 -1 0 -1 -1 1 0 21
|
|
325 CLK_000_D_2_ 3 -1 -1 0 -1 -1 1 0 21
|
|
320 inst_CLK_OUT_PRE_50 3 -1 -1 0 -1 -1 1 0 21
|
|
316 inst_DTACK_D0 3 -1 -1 0 -1 -1 1 0 21
|
|
307 CYCLE_DMA_1_ 3 -1 -1 0 -1 -1 1 1 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 4 1 3 6 7 85 -1
|
|
96 A_DECODE_19_ 1 -1 -1 2 4 7 96 -1
|
|
95 A_DECODE_16_ 1 -1 -1 2 4 7 95 -1
|
|
94 A_DECODE_18_ 1 -1 -1 2 4 7 94 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
58 A_DECODE_17_ 1 -1 -1 2 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 2 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 2 4 7 56 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
10 CLK_000 1 -1 -1 2 3 7 10 -1
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
|
63 CLK_030 1 -1 -1 1 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
59 A_1_ 1 -1 -1 0 59 -1
|
|
35 VPA 1 -1 -1 0 35 -1
|
|
29 DTACK 1 -1 -1 0 29 -1
|
|
13 nEXP_SPACE 1 -1 -1 0 13 -1
|
|
141 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
79 RW_000 5 367 7 2 4 6 79 -1 5 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
70 RW 5 372 6 1 7 70 -1 2 0 21
|
|
40 BERR 5 -1 4 1 7 40 -1 1 0 21
|
|
31 UDS_000 5 -1 3 1 6 31 -1 1 0 21
|
|
18 AHIGH_24_ 5 -1 -1 1 4 18 -1 1 0 21
|
|
17 AHIGH_25_ 5 -1 -1 1 4 17 -1 1 0 21
|
|
16 AHIGH_26_ 5 -1 -1 1 4 16 -1 1 0 21
|
|
15 AHIGH_27_ 5 -1 -1 1 4 15 -1 1 0 21
|
|
14 AHIGH_28_ 5 -1 -1 1 4 14 -1 1 0 21
|
|
5 AHIGH_29_ 5 -1 -1 1 4 5 -1 1 0 21
|
|
4 AHIGH_30_ 5 -1 -1 1 4 4 -1 1 0 21
|
|
3 AHIGH_31_ 5 -1 -1 1 4 3 -1 1 0 21
|
|
8 IPL_030_2_ 0 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 0 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 0 1 0 6 -1 10 0 21
|
|
80 DSACK1 0 7 0 80 -1 4 0 21
|
|
82 BGACK_030 0 7 0 82 -1 3 0 21
|
|
68 A_0_ 5 364 6 0 68 -1 3 0 21
|
|
34 VMA 0 3 0 34 -1 3 0 21
|
|
65 E 0 -1 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 -1 0 33 -1 2 0 21
|
|
28 BG_000 0 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 -1 0 91 -1 1 0 21
|
|
78 SIZE_1_ 0 -1 0 78 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
69 SIZE_0_ 0 6 0 69 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 -1 0 32 -1 1 0 21
|
|
30 LDS_000 0 3 0 30 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 -1 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 -1 0 2 -1 1 0 21
|
|
369 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 3 0 21
|
|
317 inst_RESET_OUT 3 -1 -1 5 0 3 4 6 7 -1 -1 2 0 21
|
|
301 inst_nEXP_SPACE_D0reg 3 -1 -1 5 0 3 4 6 7 -1 -1 1 0 21
|
|
313 inst_CLK_OUT_PRE_D 3 -1 -1 3 1 6 7 -1 -1 1 0 21
|
|
300 inst_AS_030_D0 3 -1 -1 3 3 4 7 -1 -1 1 0 21
|
|
319 CLK_000_D_1_ 3 -1 -1 2 3 7 -1 -1 1 0 21
|
|
318 CLK_000_D_0_ 3 -1 -1 2 3 7 -1 -1 1 0 21
|
|
366 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
365 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
363 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
305 inst_DS_000_DMA 3 -1 -1 1 0 -1 -1 9 0 21
|
|
304 inst_AS_000_DMA 3 -1 -1 1 7 -1 -1 7 0 21
|
|
367 RN_RW_000 3 79 7 1 7 79 -1 5 0 21
|
|
337 inst_DS_000_ENABLE 3 -1 -1 1 3 -1 -1 5 0 21
|
|
370 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
334 SM_AMIGA_0_ 3 -1 -1 1 7 -1 -1 4 0 21
|
|
297 cpu_est_2_ 3 -1 -1 1 3 -1 -1 4 0 21
|
|
371 RN_VMA 3 34 3 1 3 34 -1 3 0 21
|
|
364 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
357 SM_AMIGA_1_ 3 -1 -1 1 7 -1 -1 3 0 21
|
|
321 SM_AMIGA_5_ 3 -1 -1 1 7 -1 -1 3 0 21
|
|
312 inst_LDS_000_INT 3 -1 -1 1 3 -1 -1 3 0 21
|
|
309 SIZE_DMA_1_ 3 -1 -1 1 6 -1 -1 3 0 21
|
|
308 SIZE_DMA_0_ 3 -1 -1 1 6 -1 -1 3 0 21
|
|
296 cpu_est_1_ 3 -1 -1 1 3 -1 -1 3 0 21
|
|
293 cpu_est_3_ 3 -1 -1 1 3 -1 -1 3 0 21
|
|
372 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
368 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
361 CIIN_0 3 -1 -1 1 4 -1 -1 2 0 21
|
|
360 SM_AMIGA_i_7_ 3 -1 -1 1 7 -1 -1 2 0 21
|
|
311 inst_UDS_000_INT 3 -1 -1 1 3 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 -1 1 4 -1 -1 2 0 21
|
|
294 cpu_est_0_ 3 -1 -1 1 3 -1 -1 2 0 21
|
|
338 CLK_000_N_SYNC_12_ 3 -1 -1 1 3 -1 -1 1 0 21
|
|
333 CLK_000_D_12_ 3 -1 -1 1 7 -1 -1 1 0 21
|
|
324 IPL_D0_2_ 3 -1 -1 1 1 -1 -1 1 0 21
|
|
323 IPL_D0_1_ 3 -1 -1 1 1 -1 -1 1 0 21
|
|
322 IPL_D0_0_ 3 -1 -1 1 1 -1 -1 1 0 21
|
|
315 CLK_000_D_11_ 3 -1 -1 1 7 -1 -1 1 0 21
|
|
314 CLK_000_D_10_ 3 -1 -1 1 7 -1 -1 1 0 21
|
|
310 inst_VPA_D 3 -1 -1 1 3 -1 -1 1 0 21
|
|
303 inst_BGACK_030_INT_D 3 -1 -1 1 6 -1 -1 1 0 21
|
|
362 SM_AMIGA_i_7__0 3 -1 -1 0 -1 -1 15 0 21
|
|
356 inst_CLK_030_H 3 -1 -1 0 -1 -1 8 0 21
|
|
302 inst_AS_030_000_SYNC 3 -1 -1 0 -1 -1 7 0 21
|
|
359 SM_AMIGA_2_ 3 -1 -1 0 -1 -1 5 0 21
|
|
358 SM_AMIGA_3_ 3 -1 -1 0 -1 -1 5 0 21
|
|
340 RST_DLY_1_ 3 -1 -1 0 -1 -1 4 0 21
|
|
306 CYCLE_DMA_0_ 3 -1 -1 0 -1 -1 4 0 21
|
|
355 SM_AMIGA_6_ 3 -1 -1 0 -1 -1 3 1 21
|
|
353 SM_AMIGA_4_ 3 -1 -1 0 -1 -1 3 1 21
|
|
339 RST_DLY_0_ 3 -1 -1 0 -1 -1 3 0 21
|
|
295 N_208_i 3 -1 -1 0 -1 -1 3 0 21
|
|
341 RST_DLY_2_ 3 -1 -1 0 -1 -1 2 0 21
|
|
335 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 -1 0 -1 -1 2 0 21
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 -1 0 -1 -1 2 0 21
|
|
354 inst_CLK_000_NE_D0 3 -1 -1 0 -1 -1 1 0 21
|
|
352 CLK_000_N_SYNC_11_ 3 -1 -1 0 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_10_ 3 -1 -1 0 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_9_ 3 -1 -1 0 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_8_ 3 -1 -1 0 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_7_ 3 -1 -1 0 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_6_ 3 -1 -1 0 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_5_ 3 -1 -1 0 -1 -1 1 0 21
|
|
345 CLK_000_N_SYNC_4_ 3 -1 -1 0 -1 -1 1 0 21
|
|
344 CLK_000_N_SYNC_3_ 3 -1 -1 0 -1 -1 1 0 21
|
|
343 CLK_000_N_SYNC_2_ 3 -1 -1 0 -1 -1 1 0 21
|
|
342 CLK_000_N_SYNC_1_ 3 -1 -1 0 -1 -1 1 0 21
|
|
336 CLK_000_N_SYNC_0_ 3 -1 -1 0 -1 -1 1 0 21
|
|
332 CLK_000_D_9_ 3 -1 -1 0 -1 -1 1 0 21
|
|
331 CLK_000_D_8_ 3 -1 -1 0 -1 -1 1 0 21
|
|
330 CLK_000_D_7_ 3 -1 -1 0 -1 -1 1 0 21
|
|
329 CLK_000_D_6_ 3 -1 -1 0 -1 -1 1 0 21
|
|
328 CLK_000_D_5_ 3 -1 -1 0 -1 -1 1 0 21
|
|
327 CLK_000_D_4_ 3 -1 -1 0 -1 -1 1 0 21
|
|
326 CLK_000_D_3_ 3 -1 -1 0 -1 -1 1 0 21
|
|
325 CLK_000_D_2_ 3 -1 -1 0 -1 -1 1 0 21
|
|
320 inst_CLK_OUT_PRE_50 3 -1 -1 0 -1 -1 1 0 21
|
|
316 inst_DTACK_D0 3 -1 -1 0 -1 -1 1 0 21
|
|
307 CYCLE_DMA_1_ 3 -1 -1 0 -1 -1 1 1 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 4 1 3 6 7 85 -1
|
|
96 A_DECODE_19_ 1 -1 -1 2 4 7 96 -1
|
|
95 A_DECODE_16_ 1 -1 -1 2 4 7 95 -1
|
|
94 A_DECODE_18_ 1 -1 -1 2 4 7 94 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
58 A_DECODE_17_ 1 -1 -1 2 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 2 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 2 4 7 56 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
10 CLK_000 1 -1 -1 2 3 7 10 -1
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
|
63 CLK_030 1 -1 -1 1 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
59 A_1_ 1 -1 -1 0 59 -1
|
|
35 VPA 1 -1 -1 0 35 -1
|
|
29 DTACK 1 -1 -1 0 29 -1
|
|
13 nEXP_SPACE 1 -1 -1 0 13 -1
|
|
141 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 5 0 1 2 5 7 40 -1 1 0 21
|
|
41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21
|
|
79 RW_000 5 367 7 3 2 4 6 79 -1 4 0 21
|
|
70 RW 5 372 6 2 5 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 2 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 2 6 30 -1 1 0 21
|
|
68 A_0_ 5 363 6 1 1 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
|
8 IPL_030_2_ 5 366 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 365 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 364 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 370 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 369 7 0 82 -1 3 0 21
|
|
34 VMA 5 371 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 368 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
369 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21
|
|
300 inst_nEXP_SPACE_D0reg 3 -1 0 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21
|
|
316 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
317 CLK_000_D_0_ 3 -1 4 6 0 2 3 4 5 7 -1 -1 1 0 21
|
|
299 inst_AS_030_D0 3 -1 7 5 1 3 4 5 7 -1 -1 1 0 21
|
|
360 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 11 0 21
|
|
354 SM_AMIGA_6_ 3 -1 2 3 1 2 5 -1 -1 4 0 21
|
|
296 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 4 0 21
|
|
356 SM_AMIGA_1_ 3 -1 0 3 0 5 7 -1 -1 3 0 21
|
|
319 SM_AMIGA_5_ 3 -1 5 3 1 5 7 -1 -1 3 0 21
|
|
295 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 3 0 21
|
|
293 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 3 0 21
|
|
353 inst_CLK_000_NE_D0 3 -1 5 3 0 3 5 -1 -1 1 0 21
|
|
337 CLK_000_N_SYNC_12_ 3 -1 0 3 0 3 5 -1 -1 1 0 21
|
|
335 CLK_000_N_SYNC_0_ 3 -1 5 3 2 4 5 -1 -1 1 0 21
|
|
312 inst_CLK_OUT_PRE_D 3 -1 0 3 1 6 7 -1 -1 1 0 21
|
|
304 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21
|
|
303 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21
|
|
301 inst_AS_030_000_SYNC 3 -1 5 2 2 5 -1 -1 7 0 21
|
|
358 SM_AMIGA_2_ 3 -1 0 2 0 5 -1 -1 5 0 21
|
|
357 SM_AMIGA_3_ 3 -1 0 2 0 5 -1 -1 5 0 21
|
|
336 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 5 0 21
|
|
352 SM_AMIGA_4_ 3 -1 5 2 0 5 -1 -1 4 0 21
|
|
371 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21
|
|
333 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
311 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21
|
|
308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
305 CYCLE_DMA_0_ 3 -1 0 2 0 2 -1 -1 3 0 21
|
|
334 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
310 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21
|
|
297 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21
|
|
294 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 2 0 21
|
|
309 inst_VPA_D 3 -1 6 2 0 3 -1 -1 1 0 21
|
|
302 inst_BGACK_030_INT_D 3 -1 3 2 5 6 -1 -1 1 0 21
|
|
366 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
365 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
364 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
355 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21
|
|
370 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
367 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
|
339 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21
|
|
306 CYCLE_DMA_1_ 3 -1 2 1 2 -1 -1 4 0 21
|
|
363 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
362 SM_AMIGA_i_7__0 3 -1 5 1 5 -1 -1 3 0 21
|
|
338 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21
|
|
372 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
368 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
359 N_162_i 3 -1 0 1 5 -1 -1 2 0 21
|
|
340 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21
|
|
351 CLK_000_N_SYNC_11_ 3 -1 1 1 0 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_10_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_9_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_8_ 3 -1 2 1 6 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_7_ 3 -1 0 1 2 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_6_ 3 -1 1 1 0 -1 -1 1 0 21
|
|
345 CLK_000_N_SYNC_5_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
344 CLK_000_N_SYNC_4_ 3 -1 6 1 3 -1 -1 1 0 21
|
|
343 CLK_000_N_SYNC_3_ 3 -1 5 1 6 -1 -1 1 0 21
|
|
342 CLK_000_N_SYNC_2_ 3 -1 2 1 5 -1 -1 1 0 21
|
|
341 CLK_000_N_SYNC_1_ 3 -1 4 1 2 -1 -1 1 0 21
|
|
332 CLK_000_D_12_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
331 CLK_000_D_9_ 3 -1 1 1 0 -1 -1 1 0 21
|
|
330 CLK_000_D_8_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
329 CLK_000_D_7_ 3 -1 4 1 2 -1 -1 1 0 21
|
|
328 CLK_000_D_6_ 3 -1 3 1 4 -1 -1 1 0 21
|
|
327 CLK_000_D_5_ 3 -1 6 1 3 -1 -1 1 0 21
|
|
326 CLK_000_D_4_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
325 CLK_000_D_3_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
324 CLK_000_D_2_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
323 CLK_000_D_1_ 3 -1 4 1 5 -1 -1 1 0 21
|
|
322 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
321 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
320 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
318 inst_CLK_OUT_PRE_50 3 -1 0 1 0 -1 -1 1 0 21
|
|
315 inst_DTACK_D0 3 -1 2 1 0 -1 -1 1 0 21
|
|
314 CLK_000_D_11_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
313 CLK_000_D_10_ 3 -1 0 1 7 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
10 CLK_000 1 -1 -1 6 0 2 3 4 5 7 10 -1
|
|
96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1
|
|
95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1
|
|
94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1
|
|
58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 4 5 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 4 5 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 2 66 -1
|
|
63 CLK_030 1 -1 -1 2 2 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 6 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
59 A_1_ 1 -1 -1 1 6 59 -1
|
|
35 VPA 1 -1 -1 1 6 35 -1
|
|
29 DTACK 1 -1 -1 1 2 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 0 13 -1
|
|
140 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21
|
|
40 BERR 5 -1 4 4 0 1 5 7 40 -1 1 0 21
|
|
79 RW_000 5 363 7 3 2 4 6 79 -1 4 0 21
|
|
68 A_0_ 5 369 6 2 2 6 68 -1 3 0 21
|
|
70 RW 5 368 6 2 5 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 2 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 2 6 30 -1 1 0 21
|
|
78 SIZE_1_ 5 -1 7 1 2 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
|
8 IPL_030_2_ 5 362 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 371 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 370 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 366 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 365 7 0 82 -1 3 0 21
|
|
34 VMA 5 367 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 364 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
301 inst_nEXP_SPACE_D0reg 3 -1 0 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21
|
|
365 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
317 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
320 CLK_000_D_0_ 3 -1 3 6 0 1 2 3 5 7 -1 -1 1 0 21
|
|
318 CLK_000_D_1_ 3 -1 7 6 0 1 2 3 5 7 -1 -1 1 0 21
|
|
300 inst_AS_030_D0 3 -1 4 5 0 3 4 5 7 -1 -1 1 0 21
|
|
360 SM_AMIGA_i_7_ 3 -1 5 4 0 3 5 7 -1 -1 15 0 21
|
|
355 SM_AMIGA_6_ 3 -1 5 4 0 2 5 6 -1 -1 3 0 21
|
|
338 CLK_000_N_SYNC_12_ 3 -1 6 4 0 1 3 5 -1 -1 1 0 21
|
|
303 inst_BGACK_030_INT_D 3 -1 7 4 0 1 2 6 -1 -1 1 0 21
|
|
296 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 4 0 21
|
|
308 SIZE_DMA_0_ 3 -1 2 3 2 6 7 -1 -1 3 0 21
|
|
295 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
293 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
357 SM_AMIGA_1_ 3 -1 1 3 1 5 7 -1 -1 2 0 21
|
|
321 SM_AMIGA_5_ 3 -1 0 3 0 5 7 -1 -1 2 0 21
|
|
313 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
|
305 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21
|
|
304 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21
|
|
302 inst_AS_030_000_SYNC 3 -1 0 2 0 5 -1 -1 7 0 21
|
|
337 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 5 0 21
|
|
359 SM_AMIGA_2_ 3 -1 5 2 1 5 -1 -1 4 0 21
|
|
367 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
334 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
312 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21
|
|
309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
306 CYCLE_DMA_0_ 3 -1 1 2 1 2 -1 -1 3 0 21
|
|
335 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
311 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
297 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21
|
|
294 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 2 0 21
|
|
315 CLK_000_D_11_ 3 -1 5 2 0 7 -1 -1 1 0 21
|
|
314 CLK_000_D_10_ 3 -1 0 2 5 7 -1 -1 1 0 21
|
|
310 inst_VPA_D 3 -1 3 2 3 5 -1 -1 1 0 21
|
|
371 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
370 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
362 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
358 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 8 0 21
|
|
356 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21
|
|
366 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
363 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
|
340 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21
|
|
307 CYCLE_DMA_1_ 3 -1 2 1 2 -1 -1 4 0 21
|
|
369 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
353 SM_AMIGA_4_ 3 -1 5 1 5 -1 -1 3 0 21
|
|
339 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21
|
|
368 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
364 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
341 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21
|
|
298 pos_clk_un23_clk_000_ne_d0_i_n 3 -1 5 1 5 -1 -1 2 0 21
|
|
354 inst_CLK_000_NE_D0 3 -1 5 1 5 -1 -1 1 0 21
|
|
352 CLK_000_N_SYNC_11_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_10_ 3 -1 2 1 3 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_9_ 3 -1 4 1 2 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_8_ 3 -1 1 1 4 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_7_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_6_ 3 -1 5 1 2 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_5_ 3 -1 1 1 5 -1 -1 1 0 21
|
|
345 CLK_000_N_SYNC_4_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
344 CLK_000_N_SYNC_3_ 3 -1 0 1 6 -1 -1 1 0 21
|
|
343 CLK_000_N_SYNC_2_ 3 -1 3 1 0 -1 -1 1 0 21
|
|
342 CLK_000_N_SYNC_1_ 3 -1 5 1 3 -1 -1 1 0 21
|
|
336 CLK_000_N_SYNC_0_ 3 -1 7 1 5 -1 -1 1 0 21
|
|
333 CLK_000_D_12_ 3 -1 0 1 7 -1 -1 1 0 21
|
|
332 CLK_000_D_9_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
331 CLK_000_D_8_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
330 CLK_000_D_7_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
329 CLK_000_D_6_ 3 -1 4 1 1 -1 -1 1 0 21
|
|
328 CLK_000_D_5_ 3 -1 1 1 4 -1 -1 1 0 21
|
|
327 CLK_000_D_4_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
326 CLK_000_D_3_ 3 -1 0 1 6 -1 -1 1 0 21
|
|
325 CLK_000_D_2_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
324 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
323 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
322 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
319 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
316 inst_DTACK_D0 3 -1 6 1 5 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1
|
|
96 A_DECODE_19_ 1 -1 -1 3 0 4 7 96 -1
|
|
95 A_DECODE_16_ 1 -1 -1 3 0 4 7 95 -1
|
|
94 A_DECODE_18_ 1 -1 -1 3 0 4 7 94 -1
|
|
58 A_DECODE_17_ 1 -1 -1 3 0 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 0 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 0 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
67 IPL_2_ 1 -1 -1 2 1 6 67 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 6 66 -1
|
|
63 CLK_030 1 -1 -1 2 2 7 63 -1
|
|
59 A_1_ 1 -1 -1 2 1 2 59 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 6 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
|
35 VPA 1 -1 -1 1 3 35 -1
|
|
29 DTACK 1 -1 -1 1 6 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 0 13 -1
|
|
10 CLK_000 1 -1 -1 1 3 10 -1
|
|
141 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21
|
|
79 RW_000 5 367 7 3 0 4 6 79 -1 4 0 21
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
68 A_0_ 5 363 6 2 1 2 68 -1 3 0 21
|
|
70 RW 5 372 6 2 2 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
|
8 IPL_030_2_ 5 366 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 365 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 364 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 370 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 369 7 0 82 -1 3 0 21
|
|
34 VMA 5 371 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 368 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
369 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
317 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
300 inst_nEXP_SPACE_D0reg 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 1 0 21
|
|
320 CLK_000_D_0_ 3 -1 3 5 0 2 3 5 7 -1 -1 1 0 21
|
|
318 CLK_000_D_1_ 3 -1 3 5 0 2 3 5 7 -1 -1 1 0 21
|
|
299 inst_AS_030_D0 3 -1 7 5 0 2 3 4 7 -1 -1 1 0 21
|
|
360 SM_AMIGA_i_7_ 3 -1 5 4 0 2 3 7 -1 -1 15 0 21
|
|
351 SM_AMIGA_6_ 3 -1 2 4 1 2 5 7 -1 -1 3 0 21
|
|
301 inst_AS_030_000_SYNC 3 -1 0 3 0 1 2 -1 -1 7 0 21
|
|
296 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 4 0 21
|
|
352 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 3 0 21
|
|
308 SIZE_DMA_1_ 3 -1 0 3 0 6 7 -1 -1 3 0 21
|
|
295 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
293 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
336 CLK_000_N_SYNC_12_ 3 -1 1 3 1 3 5 -1 -1 1 0 21
|
|
313 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
|
303 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
335 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21
|
|
338 RST_DLY_1_ 3 -1 1 2 1 3 -1 -1 4 0 21
|
|
371 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
353 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21
|
|
337 RST_DLY_0_ 3 -1 3 2 1 3 -1 -1 3 0 21
|
|
312 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21
|
|
307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
357 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 2 0 21
|
|
355 SM_AMIGA_5_ 3 -1 5 2 2 5 -1 -1 2 0 21
|
|
339 RST_DLY_2_ 3 -1 3 2 1 3 -1 -1 2 0 21
|
|
333 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
310 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21
|
|
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21
|
|
297 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
|
|
294 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 2 0 21
|
|
334 CLK_000_N_SYNC_0_ 3 -1 0 2 1 2 -1 -1 1 0 21
|
|
315 CLK_000_D_11_ 3 -1 7 2 4 7 -1 -1 1 0 21
|
|
309 inst_VPA_D 3 -1 6 2 3 5 -1 -1 1 0 21
|
|
302 inst_BGACK_030_INT_D 3 -1 7 2 0 6 -1 -1 1 0 21
|
|
366 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
365 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
364 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
304 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
358 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 8 0 21
|
|
356 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
370 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
367 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
|
359 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
306 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21
|
|
363 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
305 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
372 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
368 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
362 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
361 N_256 3 -1 3 1 5 -1 -1 1 0 21
|
|
354 inst_CLK_000_NE_D0 3 -1 5 1 5 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_11_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_10_ 3 -1 5 1 6 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_9_ 3 -1 3 1 5 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_8_ 3 -1 1 1 3 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_7_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
345 CLK_000_N_SYNC_6_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
344 CLK_000_N_SYNC_5_ 3 -1 0 1 6 -1 -1 1 0 21
|
|
343 CLK_000_N_SYNC_4_ 3 -1 4 1 0 -1 -1 1 0 21
|
|
342 CLK_000_N_SYNC_3_ 3 -1 2 1 4 -1 -1 1 0 21
|
|
341 CLK_000_N_SYNC_2_ 3 -1 4 1 2 -1 -1 1 0 21
|
|
340 CLK_000_N_SYNC_1_ 3 -1 1 1 4 -1 -1 1 0 21
|
|
332 CLK_000_D_12_ 3 -1 4 1 7 -1 -1 1 0 21
|
|
331 CLK_000_D_9_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
330 CLK_000_D_8_ 3 -1 5 1 6 -1 -1 1 0 21
|
|
329 CLK_000_D_7_ 3 -1 5 1 5 -1 -1 1 0 21
|
|
328 CLK_000_D_6_ 3 -1 3 1 5 -1 -1 1 0 21
|
|
327 CLK_000_D_5_ 3 -1 6 1 3 -1 -1 1 0 21
|
|
326 CLK_000_D_4_ 3 -1 5 1 6 -1 -1 1 0 21
|
|
325 CLK_000_D_3_ 3 -1 2 1 5 -1 -1 1 0 21
|
|
324 CLK_000_D_2_ 3 -1 2 1 2 -1 -1 1 0 21
|
|
323 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
322 IPL_D0_1_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
321 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
319 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
316 inst_DTACK_D0 3 -1 2 1 5 -1 -1 1 0 21
|
|
314 CLK_000_D_10_ 3 -1 6 1 7 -1 -1 1 0 21
|
|
311 N_145_0 3 -1 1 1 5 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_DECODE_19_ 1 -1 -1 3 0 4 7 96 -1
|
|
95 A_DECODE_16_ 1 -1 -1 3 0 4 7 95 -1
|
|
94 A_DECODE_18_ 1 -1 -1 3 0 4 7 94 -1
|
|
58 A_DECODE_17_ 1 -1 -1 3 0 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 0 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 0 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
66 IPL_0_ 1 -1 -1 2 0 1 66 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 2 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
59 A_1_ 1 -1 -1 1 6 59 -1
|
|
35 VPA 1 -1 -1 1 6 35 -1
|
|
29 DTACK 1 -1 -1 1 2 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 3 13 -1
|
|
10 CLK_000 1 -1 -1 1 3 10 -1
|
|
141 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
41 AS_000 5 -1 4 4 0 4 6 7 41 -1 1 0 21
|
|
40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21
|
|
79 RW_000 5 367 7 3 0 4 6 79 -1 4 0 21
|
|
70 RW 5 372 6 2 5 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
68 A_0_ 5 363 6 1 1 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
|
8 IPL_030_2_ 5 366 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 365 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 364 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 370 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 369 7 0 82 -1 3 0 21
|
|
34 VMA 5 371 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 368 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
369 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
317 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
300 inst_nEXP_SPACE_D0reg 3 -1 1 7 0 1 2 3 4 6 7 -1 -1 1 0 21
|
|
318 CLK_000_D_1_ 3 -1 7 6 0 2 3 4 5 7 -1 -1 1 0 21
|
|
360 SM_AMIGA_i_7_ 3 -1 5 5 0 2 3 5 7 -1 -1 15 0 21
|
|
333 SM_AMIGA_6_ 3 -1 0 5 0 1 2 5 7 -1 -1 3 0 21
|
|
320 CLK_000_D_0_ 3 -1 2 5 0 2 3 5 7 -1 -1 1 0 21
|
|
299 inst_AS_030_D0 3 -1 7 5 2 3 4 5 7 -1 -1 1 0 21
|
|
303 inst_AS_000_DMA 3 -1 6 3 0 6 7 -1 -1 7 0 21
|
|
296 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 4 0 21
|
|
295 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
293 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
337 CLK_000_N_SYNC_12_ 3 -1 2 3 3 5 6 -1 -1 1 0 21
|
|
335 CLK_000_N_SYNC_0_ 3 -1 7 3 0 2 3 -1 -1 1 0 21
|
|
313 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
|
302 inst_BGACK_030_INT_D 3 -1 6 3 1 2 6 -1 -1 1 0 21
|
|
301 inst_AS_030_000_SYNC 3 -1 2 2 0 2 -1 -1 7 0 21
|
|
336 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 5 0 21
|
|
306 CYCLE_DMA_1_ 3 -1 0 2 0 6 -1 -1 4 0 21
|
|
371 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
312 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21
|
|
308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
305 CYCLE_DMA_0_ 3 -1 0 2 0 6 -1 -1 3 0 21
|
|
356 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 2 0 21
|
|
334 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
311 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21
|
|
297 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
|
|
294 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 2 0 21
|
|
314 CLK_000_D_10_ 3 -1 6 2 0 7 -1 -1 1 0 21
|
|
309 inst_VPA_D 3 -1 0 2 3 5 -1 -1 1 0 21
|
|
366 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
365 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
364 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
304 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
358 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 8 0 21
|
|
355 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
370 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
367 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
|
359 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
339 RST_DLY_1_ 3 -1 6 1 6 -1 -1 4 0 21
|
|
363 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
357 SM_AMIGA_0_ 3 -1 5 1 5 -1 -1 3 0 21
|
|
352 SM_AMIGA_4_ 3 -1 5 1 5 -1 -1 3 0 21
|
|
338 RST_DLY_0_ 3 -1 6 1 6 -1 -1 3 0 21
|
|
372 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
368 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
362 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
354 SM_AMIGA_5_ 3 -1 5 1 5 -1 -1 2 0 21
|
|
340 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21
|
|
361 N_245 3 -1 3 1 5 -1 -1 1 0 21
|
|
353 inst_CLK_000_NE_D0 3 -1 5 1 5 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_11_ 3 -1 5 1 2 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_10_ 3 -1 2 1 5 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_9_ 3 -1 2 1 2 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_8_ 3 -1 0 1 2 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_7_ 3 -1 2 1 0 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_6_ 3 -1 4 1 2 -1 -1 1 0 21
|
|
345 CLK_000_N_SYNC_5_ 3 -1 6 1 4 -1 -1 1 0 21
|
|
344 CLK_000_N_SYNC_4_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
343 CLK_000_N_SYNC_3_ 3 -1 0 1 3 -1 -1 1 0 21
|
|
342 CLK_000_N_SYNC_2_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
341 CLK_000_N_SYNC_1_ 3 -1 3 1 0 -1 -1 1 0 21
|
|
332 CLK_000_D_12_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
331 CLK_000_D_9_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
330 CLK_000_D_8_ 3 -1 2 1 3 -1 -1 1 0 21
|
|
329 CLK_000_D_7_ 3 -1 3 1 2 -1 -1 1 0 21
|
|
328 CLK_000_D_6_ 3 -1 1 1 3 -1 -1 1 0 21
|
|
327 CLK_000_D_5_ 3 -1 4 1 1 -1 -1 1 0 21
|
|
326 CLK_000_D_4_ 3 -1 3 1 4 -1 -1 1 0 21
|
|
325 CLK_000_D_3_ 3 -1 5 1 3 -1 -1 1 0 21
|
|
324 CLK_000_D_2_ 3 -1 4 1 5 -1 -1 1 0 21
|
|
323 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
322 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
321 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
319 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
316 inst_DTACK_D0 3 -1 3 1 5 -1 -1 1 0 21
|
|
315 CLK_000_D_11_ 3 -1 0 1 7 -1 -1 1 0 21
|
|
310 N_132_0 3 -1 2 1 5 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
63 CLK_030 1 -1 -1 3 0 6 7 63 -1
|
|
58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 3 66 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 3 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
59 A_1_ 1 -1 -1 1 1 59 -1
|
|
35 VPA 1 -1 -1 1 0 35 -1
|
|
29 DTACK 1 -1 -1 1 3 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 1 13 -1
|
|
10 CLK_000 1 -1 -1 1 2 10 -1
|
|
141 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 5 0 1 2 5 7 40 -1 1 0 21
|
|
41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21
|
|
79 RW_000 5 367 7 3 2 4 6 79 -1 4 0 21
|
|
70 RW 5 372 6 2 5 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 2 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 2 6 30 -1 1 0 21
|
|
68 A_0_ 5 363 6 1 1 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
|
8 IPL_030_2_ 5 366 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 365 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 364 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 370 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 369 7 0 82 -1 3 0 21
|
|
34 VMA 5 371 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 368 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
369 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21
|
|
300 inst_nEXP_SPACE_D0reg 3 -1 0 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21
|
|
316 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
317 CLK_000_D_0_ 3 -1 4 6 0 2 3 4 5 7 -1 -1 1 0 21
|
|
299 inst_AS_030_D0 3 -1 7 5 1 3 4 5 7 -1 -1 1 0 21
|
|
360 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 11 0 21
|
|
354 SM_AMIGA_6_ 3 -1 2 3 1 2 5 -1 -1 4 0 21
|
|
296 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 4 0 21
|
|
356 SM_AMIGA_1_ 3 -1 0 3 0 5 7 -1 -1 3 0 21
|
|
319 SM_AMIGA_5_ 3 -1 5 3 1 5 7 -1 -1 3 0 21
|
|
295 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 3 0 21
|
|
293 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 3 0 21
|
|
353 inst_CLK_000_NE_D0 3 -1 5 3 0 3 5 -1 -1 1 0 21
|
|
337 CLK_000_N_SYNC_12_ 3 -1 0 3 0 3 5 -1 -1 1 0 21
|
|
335 CLK_000_N_SYNC_0_ 3 -1 5 3 2 4 5 -1 -1 1 0 21
|
|
312 inst_CLK_OUT_PRE_D 3 -1 0 3 1 6 7 -1 -1 1 0 21
|
|
304 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21
|
|
303 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21
|
|
301 inst_AS_030_000_SYNC 3 -1 5 2 2 5 -1 -1 7 0 21
|
|
358 SM_AMIGA_2_ 3 -1 0 2 0 5 -1 -1 5 0 21
|
|
357 SM_AMIGA_3_ 3 -1 0 2 0 5 -1 -1 5 0 21
|
|
336 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 5 0 21
|
|
352 SM_AMIGA_4_ 3 -1 5 2 0 5 -1 -1 4 0 21
|
|
371 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21
|
|
333 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
311 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21
|
|
308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
305 CYCLE_DMA_0_ 3 -1 0 2 0 2 -1 -1 3 0 21
|
|
334 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
310 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21
|
|
297 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21
|
|
294 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 2 0 21
|
|
309 inst_VPA_D 3 -1 6 2 0 3 -1 -1 1 0 21
|
|
302 inst_BGACK_030_INT_D 3 -1 3 2 5 6 -1 -1 1 0 21
|
|
366 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
365 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
364 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
355 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21
|
|
370 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
367 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
|
339 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21
|
|
306 CYCLE_DMA_1_ 3 -1 2 1 2 -1 -1 4 0 21
|
|
363 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
362 SM_AMIGA_i_7__0 3 -1 5 1 5 -1 -1 3 0 21
|
|
338 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21
|
|
372 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
368 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
359 N_162_i 3 -1 0 1 5 -1 -1 2 0 21
|
|
340 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21
|
|
351 CLK_000_N_SYNC_11_ 3 -1 1 1 0 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_10_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_9_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_8_ 3 -1 2 1 6 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_7_ 3 -1 0 1 2 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_6_ 3 -1 1 1 0 -1 -1 1 0 21
|
|
345 CLK_000_N_SYNC_5_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
344 CLK_000_N_SYNC_4_ 3 -1 6 1 3 -1 -1 1 0 21
|
|
343 CLK_000_N_SYNC_3_ 3 -1 5 1 6 -1 -1 1 0 21
|
|
342 CLK_000_N_SYNC_2_ 3 -1 2 1 5 -1 -1 1 0 21
|
|
341 CLK_000_N_SYNC_1_ 3 -1 4 1 2 -1 -1 1 0 21
|
|
332 CLK_000_D_12_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
331 CLK_000_D_9_ 3 -1 1 1 0 -1 -1 1 0 21
|
|
330 CLK_000_D_8_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
329 CLK_000_D_7_ 3 -1 4 1 2 -1 -1 1 0 21
|
|
328 CLK_000_D_6_ 3 -1 3 1 4 -1 -1 1 0 21
|
|
327 CLK_000_D_5_ 3 -1 6 1 3 -1 -1 1 0 21
|
|
326 CLK_000_D_4_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
325 CLK_000_D_3_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
324 CLK_000_D_2_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
323 CLK_000_D_1_ 3 -1 4 1 5 -1 -1 1 0 21
|
|
322 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
321 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
320 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
318 inst_CLK_OUT_PRE_50 3 -1 0 1 0 -1 -1 1 0 21
|
|
315 inst_DTACK_D0 3 -1 2 1 0 -1 -1 1 0 21
|
|
314 CLK_000_D_11_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
313 CLK_000_D_10_ 3 -1 0 1 7 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
10 CLK_000 1 -1 -1 6 0 2 3 4 5 7 10 -1
|
|
96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1
|
|
95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1
|
|
94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1
|
|
58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 4 5 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 4 5 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 2 66 -1
|
|
63 CLK_030 1 -1 -1 2 2 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 6 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
59 A_1_ 1 -1 -1 1 6 59 -1
|
|
35 VPA 1 -1 -1 1 6 35 -1
|
|
29 DTACK 1 -1 -1 1 2 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 0 13 -1
|
|
140 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21
|
|
40 BERR 5 -1 4 4 0 1 5 7 40 -1 1 0 21
|
|
79 RW_000 5 363 7 3 2 4 6 79 -1 4 0 21
|
|
68 A_0_ 5 369 6 2 2 6 68 -1 3 0 21
|
|
70 RW 5 368 6 2 5 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 2 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 2 6 30 -1 1 0 21
|
|
78 SIZE_1_ 5 -1 7 1 2 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
|
8 IPL_030_2_ 5 362 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 371 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 370 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 366 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 365 7 0 82 -1 3 0 21
|
|
34 VMA 5 367 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 364 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
301 inst_nEXP_SPACE_D0reg 3 -1 0 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21
|
|
365 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
317 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
320 CLK_000_D_0_ 3 -1 3 6 0 1 2 3 5 7 -1 -1 1 0 21
|
|
318 CLK_000_D_1_ 3 -1 7 6 0 1 2 3 5 7 -1 -1 1 0 21
|
|
300 inst_AS_030_D0 3 -1 4 5 0 3 4 5 7 -1 -1 1 0 21
|
|
360 SM_AMIGA_i_7_ 3 -1 5 4 0 3 5 7 -1 -1 15 0 21
|
|
355 SM_AMIGA_6_ 3 -1 5 4 0 2 5 6 -1 -1 3 0 21
|
|
338 CLK_000_N_SYNC_12_ 3 -1 6 4 0 1 3 5 -1 -1 1 0 21
|
|
303 inst_BGACK_030_INT_D 3 -1 7 4 0 1 2 6 -1 -1 1 0 21
|
|
296 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 4 0 21
|
|
308 SIZE_DMA_0_ 3 -1 2 3 2 6 7 -1 -1 3 0 21
|
|
295 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
293 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
357 SM_AMIGA_1_ 3 -1 1 3 1 5 7 -1 -1 2 0 21
|
|
321 SM_AMIGA_5_ 3 -1 0 3 0 5 7 -1 -1 2 0 21
|
|
313 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
|
305 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21
|
|
304 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21
|
|
302 inst_AS_030_000_SYNC 3 -1 0 2 0 5 -1 -1 7 0 21
|
|
337 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 5 0 21
|
|
359 SM_AMIGA_2_ 3 -1 5 2 1 5 -1 -1 4 0 21
|
|
367 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
334 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
312 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21
|
|
309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
306 CYCLE_DMA_0_ 3 -1 1 2 1 2 -1 -1 3 0 21
|
|
335 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
311 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
297 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21
|
|
294 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 2 0 21
|
|
315 CLK_000_D_11_ 3 -1 5 2 0 7 -1 -1 1 0 21
|
|
314 CLK_000_D_10_ 3 -1 0 2 5 7 -1 -1 1 0 21
|
|
310 inst_VPA_D 3 -1 3 2 3 5 -1 -1 1 0 21
|
|
371 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
370 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
362 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
358 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 8 0 21
|
|
356 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21
|
|
366 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
363 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
|
340 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21
|
|
307 CYCLE_DMA_1_ 3 -1 2 1 2 -1 -1 4 0 21
|
|
369 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
353 SM_AMIGA_4_ 3 -1 5 1 5 -1 -1 3 0 21
|
|
339 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21
|
|
368 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
364 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
341 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21
|
|
298 pos_clk_un23_clk_000_ne_d0_i_n 3 -1 5 1 5 -1 -1 2 0 21
|
|
354 inst_CLK_000_NE_D0 3 -1 5 1 5 -1 -1 1 0 21
|
|
352 CLK_000_N_SYNC_11_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_10_ 3 -1 2 1 3 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_9_ 3 -1 4 1 2 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_8_ 3 -1 1 1 4 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_7_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_6_ 3 -1 5 1 2 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_5_ 3 -1 1 1 5 -1 -1 1 0 21
|
|
345 CLK_000_N_SYNC_4_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
344 CLK_000_N_SYNC_3_ 3 -1 0 1 6 -1 -1 1 0 21
|
|
343 CLK_000_N_SYNC_2_ 3 -1 3 1 0 -1 -1 1 0 21
|
|
342 CLK_000_N_SYNC_1_ 3 -1 5 1 3 -1 -1 1 0 21
|
|
336 CLK_000_N_SYNC_0_ 3 -1 7 1 5 -1 -1 1 0 21
|
|
333 CLK_000_D_12_ 3 -1 0 1 7 -1 -1 1 0 21
|
|
332 CLK_000_D_9_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
331 CLK_000_D_8_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
330 CLK_000_D_7_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
329 CLK_000_D_6_ 3 -1 4 1 1 -1 -1 1 0 21
|
|
328 CLK_000_D_5_ 3 -1 1 1 4 -1 -1 1 0 21
|
|
327 CLK_000_D_4_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
326 CLK_000_D_3_ 3 -1 0 1 6 -1 -1 1 0 21
|
|
325 CLK_000_D_2_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
324 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
323 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
322 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
319 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
316 inst_DTACK_D0 3 -1 6 1 5 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1
|
|
96 A_DECODE_19_ 1 -1 -1 3 0 4 7 96 -1
|
|
95 A_DECODE_16_ 1 -1 -1 3 0 4 7 95 -1
|
|
94 A_DECODE_18_ 1 -1 -1 3 0 4 7 94 -1
|
|
58 A_DECODE_17_ 1 -1 -1 3 0 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 0 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 0 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
67 IPL_2_ 1 -1 -1 2 1 6 67 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 6 66 -1
|
|
63 CLK_030 1 -1 -1 2 2 7 63 -1
|
|
59 A_1_ 1 -1 -1 2 1 2 59 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 6 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
|
35 VPA 1 -1 -1 1 3 35 -1
|
|
29 DTACK 1 -1 -1 1 6 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
13 nEXP_SPACE 1 -1 -1 1 0 13 -1
|
|
10 CLK_000 1 -1 -1 1 3 10 -1
|
|
140 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 5 1 2 5 6 7 40 -1 1 0 21
|
|
79 RW_000 5 366 7 3 0 4 6 79 -1 4 0 21
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
68 A_0_ 5 362 6 2 0 5 68 -1 3 0 21
|
|
70 RW 5 371 6 2 2 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
78 SIZE_1_ 5 -1 7 1 5 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 5 69 -1 1 0 21
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
|
8 IPL_030_2_ 5 365 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 364 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 363 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 369 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 368 7 0 82 -1 3 0 21
|
|
34 VMA 5 370 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 367 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
368 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
317 inst_RESET_OUT 3 -1 2 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
301 inst_nEXP_SPACE_D0reg 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 1 0 21
|
|
320 CLK_000_D_0_ 3 -1 6 6 0 2 3 4 5 7 -1 -1 1 0 21
|
|
318 CLK_000_D_1_ 3 -1 4 6 0 2 3 4 5 7 -1 -1 1 0 21
|
|
300 inst_AS_030_D0 3 -1 7 6 1 2 3 4 6 7 -1 -1 1 0 21
|
|
360 SM_AMIGA_i_7_ 3 -1 5 4 1 2 3 7 -1 -1 15 0 21
|
|
321 SM_AMIGA_5_ 3 -1 2 4 2 5 6 7 -1 -1 2 0 21
|
|
338 CLK_000_N_SYNC_12_ 3 -1 6 4 1 2 3 5 -1 -1 1 0 21
|
|
297 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 4 0 21
|
|
355 SM_AMIGA_6_ 3 -1 2 3 0 2 5 -1 -1 3 0 21
|
|
334 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 3 0 21
|
|
296 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
294 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
|
357 SM_AMIGA_1_ 3 -1 5 3 2 5 7 -1 -1 2 0 21
|
|
313 inst_CLK_OUT_PRE_D 3 -1 2 3 1 6 7 -1 -1 1 0 21
|
|
358 SM_AMIGA_3_ 3 -1 5 2 2 5 -1 -1 8 0 21
|
|
304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
302 inst_AS_030_000_SYNC 3 -1 1 2 1 2 -1 -1 7 0 21
|
|
337 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21
|
|
359 SM_AMIGA_2_ 3 -1 5 2 2 5 -1 -1 4 0 21
|
|
370 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
353 SM_AMIGA_4_ 3 -1 2 2 2 5 -1 -1 3 0 21
|
|
312 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21
|
|
309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
335 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
311 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21
|
|
295 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 2 0 21
|
|
354 inst_CLK_000_NE_D0 3 -1 1 2 3 5 -1 -1 1 0 21
|
|
336 CLK_000_N_SYNC_0_ 3 -1 4 2 2 3 -1 -1 1 0 21
|
|
319 inst_CLK_OUT_PRE_50 3 -1 4 2 2 4 -1 -1 1 0 21
|
|
315 CLK_000_D_11_ 3 -1 7 2 6 7 -1 -1 1 0 21
|
|
310 inst_VPA_D 3 -1 3 2 3 5 -1 -1 1 0 21
|
|
303 inst_BGACK_030_INT_D 3 -1 7 2 1 6 -1 -1 1 0 21
|
|
365 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
364 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
363 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
356 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
369 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
366 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
|
340 RST_DLY_1_ 3 -1 2 1 2 -1 -1 4 0 21
|
|
307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21
|
|
362 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
339 RST_DLY_0_ 3 -1 2 1 2 -1 -1 3 0 21
|
|
306 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
293 N_199_i 3 -1 2 1 5 -1 -1 3 0 21
|
|
371 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
367 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
341 RST_DLY_2_ 3 -1 2 1 2 -1 -1 2 0 21
|
|
352 CLK_000_N_SYNC_11_ 3 -1 4 1 6 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_10_ 3 -1 0 1 4 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_9_ 3 -1 3 1 0 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_8_ 3 -1 0 1 3 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_7_ 3 -1 3 1 0 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_6_ 3 -1 0 1 3 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_5_ 3 -1 1 1 0 -1 -1 1 0 21
|
|
345 CLK_000_N_SYNC_4_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
344 CLK_000_N_SYNC_3_ 3 -1 0 1 6 -1 -1 1 0 21
|
|
343 CLK_000_N_SYNC_2_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
342 CLK_000_N_SYNC_1_ 3 -1 3 1 0 -1 -1 1 0 21
|
|
333 CLK_000_D_12_ 3 -1 6 1 7 -1 -1 1 0 21
|
|
332 CLK_000_D_9_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
331 CLK_000_D_8_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
330 CLK_000_D_7_ 3 -1 5 1 3 -1 -1 1 0 21
|
|
329 CLK_000_D_6_ 3 -1 1 1 5 -1 -1 1 0 21
|
|
328 CLK_000_D_5_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
327 CLK_000_D_4_ 3 -1 0 1 0 -1 -1 1 0 21
|
|
326 CLK_000_D_3_ 3 -1 5 1 0 -1 -1 1 0 21
|
|
325 CLK_000_D_2_ 3 -1 4 1 5 -1 -1 1 0 21
|
|
324 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
323 IPL_D0_1_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
322 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
316 inst_DTACK_D0 3 -1 3 1 5 -1 -1 1 0 21
|
|
314 CLK_000_D_10_ 3 -1 6 1 7 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_DECODE_19_ 1 -1 -1 3 1 4 7 96 -1
|
|
95 A_DECODE_16_ 1 -1 -1 3 1 4 7 95 -1
|
|
94 A_DECODE_18_ 1 -1 -1 3 1 4 7 94 -1
|
|
58 A_DECODE_17_ 1 -1 -1 3 1 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 1 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 1 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
67 IPL_2_ 1 -1 -1 2 0 1 67 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 5 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
13 nEXP_SPACE 1 -1 -1 2 1 6 13 -1
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
|
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
|
59 A_1_ 1 -1 -1 1 1 59 -1
|
|
35 VPA 1 -1 -1 1 3 35 -1
|
|
29 DTACK 1 -1 -1 1 3 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
10 CLK_000 1 -1 -1 1 6 10 -1
|
|
139 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21
|
|
79 RW_000 5 362 7 3 0 4 6 79 -1 4 0 21
|
|
81 AS_030 5 -1 7 3 1 4 7 81 -1 1 0 21
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
68 A_0_ 5 368 6 2 1 2 68 -1 3 0 21
|
|
70 RW 5 367 6 2 2 7 70 -1 2 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
|
8 IPL_030_2_ 5 361 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 370 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 369 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 365 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 364 7 0 82 -1 3 0 21
|
|
34 VMA 5 366 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 363 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
364 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
316 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
317 CLK_000_D_1_ 3 -1 2 6 0 2 3 5 6 7 -1 -1 1 0 21
|
|
319 CLK_000_D_0_ 3 -1 1 5 0 2 3 5 7 -1 -1 1 0 21
|
|
300 inst_AS_030_D0 3 -1 1 5 0 2 3 4 7 -1 -1 1 0 21
|
|
359 SM_AMIGA_i_7_ 3 -1 5 4 0 2 3 7 -1 -1 15 0 21
|
|
297 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
|
354 SM_AMIGA_6_ 3 -1 2 3 1 2 5 -1 -1 3 0 21
|
|
333 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 3 0 21
|
|
296 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
294 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
356 SM_AMIGA_1_ 3 -1 2 3 2 5 7 -1 -1 2 0 21
|
|
320 SM_AMIGA_5_ 3 -1 2 3 2 5 7 -1 -1 2 0 21
|
|
337 CLK_000_N_SYNC_12_ 3 -1 6 3 2 3 5 -1 -1 1 0 21
|
|
312 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
|
302 inst_BGACK_030_INT_D 3 -1 7 3 0 1 6 -1 -1 1 0 21
|
|
357 SM_AMIGA_3_ 3 -1 5 2 2 5 -1 -1 8 0 21
|
|
303 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
301 inst_AS_030_000_SYNC 3 -1 0 2 0 2 -1 -1 7 0 21
|
|
336 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21
|
|
358 SM_AMIGA_2_ 3 -1 5 2 2 5 -1 -1 4 0 21
|
|
366 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
352 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21
|
|
311 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21
|
|
308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
334 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
310 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
|
|
295 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21
|
|
353 inst_CLK_000_NE_D0 3 -1 3 2 3 5 -1 -1 1 0 21
|
|
309 inst_VPA_D 3 -1 0 2 3 5 -1 -1 1 0 21
|
|
370 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
369 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
361 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
304 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
355 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
365 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
362 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
|
339 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21
|
|
306 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21
|
|
368 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
338 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21
|
|
305 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
293 N_296_i 3 -1 2 1 5 -1 -1 3 0 21
|
|
367 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
363 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
360 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
340 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21
|
|
351 CLK_000_N_SYNC_11_ 3 -1 5 1 6 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_10_ 3 -1 6 1 5 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_9_ 3 -1 2 1 6 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_8_ 3 -1 5 1 2 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_7_ 3 -1 3 1 5 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_6_ 3 -1 0 1 3 -1 -1 1 0 21
|
|
345 CLK_000_N_SYNC_5_ 3 -1 6 1 0 -1 -1 1 0 21
|
|
344 CLK_000_N_SYNC_4_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
343 CLK_000_N_SYNC_3_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
342 CLK_000_N_SYNC_2_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
341 CLK_000_N_SYNC_1_ 3 -1 2 1 3 -1 -1 1 0 21
|
|
335 CLK_000_N_SYNC_0_ 3 -1 3 1 2 -1 -1 1 0 21
|
|
332 CLK_000_D_12_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
331 CLK_000_D_9_ 3 -1 6 1 5 -1 -1 1 0 21
|
|
330 CLK_000_D_8_ 3 -1 6 1 6 -1 -1 1 0 21
|
|
329 CLK_000_D_7_ 3 -1 0 1 6 -1 -1 1 0 21
|
|
328 CLK_000_D_6_ 3 -1 4 1 0 -1 -1 1 0 21
|
|
327 CLK_000_D_5_ 3 -1 6 1 4 -1 -1 1 0 21
|
|
326 CLK_000_D_4_ 3 -1 4 1 6 -1 -1 1 0 21
|
|
325 CLK_000_D_3_ 3 -1 4 1 4 -1 -1 1 0 21
|
|
324 CLK_000_D_2_ 3 -1 6 1 4 -1 -1 1 0 21
|
|
323 IPL_D0_2_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
322 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
321 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21
|
|
318 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
315 inst_DTACK_D0 3 -1 6 1 5 -1 -1 1 0 21
|
|
314 CLK_000_D_11_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
313 CLK_000_D_10_ 3 -1 5 1 7 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1
|
|
96 A_DECODE_19_ 1 -1 -1 3 0 4 7 96 -1
|
|
95 A_DECODE_16_ 1 -1 -1 3 0 4 7 95 -1
|
|
94 A_DECODE_18_ 1 -1 -1 3 0 4 7 94 -1
|
|
58 A_DECODE_17_ 1 -1 -1 3 0 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 0 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 0 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
67 IPL_2_ 1 -1 -1 2 1 5 67 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
|
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
|
59 A_1_ 1 -1 -1 1 1 59 -1
|
|
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
|
35 VPA 1 -1 -1 1 0 35 -1
|
|
29 DTACK 1 -1 -1 1 6 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
10 CLK_000 1 -1 -1 1 1 10 -1
|
|
139 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
79 RW_000 5 365 7 2 4 6 79 -1 8 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
70 RW 5 370 6 1 7 70 -1 2 0 21
|
|
40 BERR 5 -1 4 1 7 40 -1 1 0 21
|
|
31 UDS_000 5 -1 3 1 6 31 -1 1 0 21
|
|
18 AHIGH_24_ 5 -1 -1 1 4 18 -1 1 0 21
|
|
17 AHIGH_25_ 5 -1 -1 1 4 17 -1 1 0 21
|
|
16 AHIGH_26_ 5 -1 -1 1 4 16 -1 1 0 21
|
|
15 AHIGH_27_ 5 -1 -1 1 4 15 -1 1 0 21
|
|
14 AHIGH_28_ 5 -1 -1 1 4 14 -1 1 0 21
|
|
5 AHIGH_29_ 5 -1 -1 1 4 5 -1 1 0 21
|
|
4 AHIGH_30_ 5 -1 -1 1 4 4 -1 1 0 21
|
|
3 AHIGH_31_ 5 -1 -1 1 4 3 -1 1 0 21
|
|
8 IPL_030_2_ 0 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 0 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 0 1 0 6 -1 10 0 21
|
|
80 DSACK1 0 7 0 80 -1 4 0 21
|
|
82 BGACK_030 0 7 0 82 -1 3 0 21
|
|
68 A_0_ 5 361 6 0 68 -1 3 0 21
|
|
34 VMA 0 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 0 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 -1 0 91 -1 1 0 21
|
|
78 SIZE_1_ 0 -1 0 78 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
69 SIZE_0_ 0 6 0 69 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 -1 0 32 -1 1 0 21
|
|
30 LDS_000 0 3 0 30 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 -1 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 -1 0 2 -1 1 0 21
|
|
367 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 3 0 21
|
|
317 inst_RESET_OUT 3 -1 -1 5 0 3 4 6 7 -1 -1 2 0 21
|
|
312 inst_CLK_OUT_PRE_D 3 -1 -1 3 1 6 7 -1 -1 1 0 21
|
|
300 inst_AS_030_D0 3 -1 -1 3 3 4 7 -1 -1 1 0 21
|
|
359 SM_AMIGA_i_7_ 3 -1 -1 2 3 7 -1 -1 15 0 21
|
|
294 cpu_est_2_ 3 -1 -1 2 3 6 -1 -1 4 0 21
|
|
297 cpu_est_1_ 3 -1 -1 2 3 6 -1 -1 3 0 21
|
|
295 cpu_est_3_ 3 -1 -1 2 3 6 -1 -1 3 0 21
|
|
320 CLK_000_D_0_ 3 -1 -1 2 3 7 -1 -1 1 0 21
|
|
318 CLK_000_D_1_ 3 -1 -1 2 3 7 -1 -1 1 0 21
|
|
364 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
363 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
362 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
304 inst_DS_000_DMA 3 -1 -1 1 0 -1 -1 9 0 21
|
|
365 RN_RW_000 3 79 7 1 7 79 -1 8 0 21
|
|
303 inst_AS_000_DMA 3 -1 -1 1 7 -1 -1 7 0 21
|
|
336 inst_DS_000_ENABLE 3 -1 -1 1 3 -1 -1 5 0 21
|
|
368 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
369 RN_VMA 3 34 3 1 3 34 -1 3 0 21
|
|
361 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
333 SM_AMIGA_0_ 3 -1 -1 1 7 -1 -1 3 0 21
|
|
311 inst_LDS_000_INT 3 -1 -1 1 3 -1 -1 3 0 21
|
|
308 SIZE_DMA_1_ 3 -1 -1 1 6 -1 -1 3 0 21
|
|
307 SIZE_DMA_0_ 3 -1 -1 1 6 -1 -1 3 0 21
|
|
370 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
366 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
360 CIIN_0 3 -1 -1 1 4 -1 -1 2 0 21
|
|
356 SM_AMIGA_1_ 3 -1 -1 1 7 -1 -1 2 0 21
|
|
334 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 -1 1 3 -1 -1 2 0 21
|
|
321 SM_AMIGA_5_ 3 -1 -1 1 7 -1 -1 2 0 21
|
|
310 inst_UDS_000_INT 3 -1 -1 1 3 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 -1 1 4 -1 -1 2 0 21
|
|
296 cpu_est_0_ 3 -1 -1 1 3 -1 -1 2 0 21
|
|
337 CLK_000_N_SYNC_12_ 3 -1 -1 1 3 -1 -1 1 0 21
|
|
332 CLK_000_D_12_ 3 -1 -1 1 7 -1 -1 1 0 21
|
|
326 CLK_000_D_4_ 3 -1 -1 1 7 -1 -1 1 0 21
|
|
324 IPL_D0_2_ 3 -1 -1 1 1 -1 -1 1 0 21
|
|
323 IPL_D0_1_ 3 -1 -1 1 1 -1 -1 1 0 21
|
|
322 IPL_D0_0_ 3 -1 -1 1 1 -1 -1 1 0 21
|
|
315 CLK_000_D_11_ 3 -1 -1 1 7 -1 -1 1 0 21
|
|
314 CLK_000_D_10_ 3 -1 -1 1 7 -1 -1 1 0 21
|
|
313 CLK_000_D_3_ 3 -1 -1 1 7 -1 -1 1 0 21
|
|
309 inst_VPA_D 3 -1 -1 1 3 -1 -1 1 0 21
|
|
302 inst_BGACK_030_INT_D 3 -1 -1 1 6 -1 -1 1 0 21
|
|
357 SM_AMIGA_3_ 3 -1 -1 0 -1 -1 8 0 21
|
|
355 inst_CLK_030_H 3 -1 -1 0 -1 -1 8 0 21
|
|
301 inst_AS_030_000_SYNC 3 -1 -1 0 -1 -1 7 0 21
|
|
358 SM_AMIGA_2_ 3 -1 -1 0 -1 -1 4 0 21
|
|
339 RST_DLY_1_ 3 -1 -1 0 -1 -1 4 0 21
|
|
306 CYCLE_DMA_1_ 3 -1 -1 0 -1 -1 4 0 21
|
|
354 SM_AMIGA_6_ 3 -1 -1 0 -1 -1 3 0 21
|
|
352 SM_AMIGA_4_ 3 -1 -1 0 -1 -1 3 0 21
|
|
338 RST_DLY_0_ 3 -1 -1 0 -1 -1 3 0 21
|
|
305 CYCLE_DMA_0_ 3 -1 -1 0 -1 -1 3 0 21
|
|
293 N_194_i 3 -1 -1 0 -1 -1 3 0 21
|
|
340 RST_DLY_2_ 3 -1 -1 0 -1 -1 2 0 21
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 -1 0 -1 -1 2 0 21
|
|
353 inst_CLK_000_NE_D0 3 -1 -1 0 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_11_ 3 -1 -1 0 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_10_ 3 -1 -1 0 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_9_ 3 -1 -1 0 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_8_ 3 -1 -1 0 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_7_ 3 -1 -1 0 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_6_ 3 -1 -1 0 -1 -1 1 0 21
|
|
345 CLK_000_N_SYNC_5_ 3 -1 -1 0 -1 -1 1 0 21
|
|
344 CLK_000_N_SYNC_4_ 3 -1 -1 0 -1 -1 1 0 21
|
|
343 CLK_000_N_SYNC_3_ 3 -1 -1 0 -1 -1 1 0 21
|
|
342 CLK_000_N_SYNC_2_ 3 -1 -1 0 -1 -1 1 0 21
|
|
341 CLK_000_N_SYNC_1_ 3 -1 -1 0 -1 -1 1 0 21
|
|
335 CLK_000_N_SYNC_0_ 3 -1 -1 0 -1 -1 1 0 21
|
|
331 CLK_000_D_9_ 3 -1 -1 0 -1 -1 1 0 21
|
|
330 CLK_000_D_8_ 3 -1 -1 0 -1 -1 1 0 21
|
|
329 CLK_000_D_7_ 3 -1 -1 0 -1 -1 1 0 21
|
|
328 CLK_000_D_6_ 3 -1 -1 0 -1 -1 1 0 21
|
|
327 CLK_000_D_5_ 3 -1 -1 0 -1 -1 1 0 21
|
|
325 CLK_000_D_2_ 3 -1 -1 0 -1 -1 1 0 21
|
|
319 inst_CLK_OUT_PRE_50 3 -1 -1 0 -1 -1 1 0 21
|
|
316 inst_DTACK_D0 3 -1 -1 0 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
|
|
85 RST 1 -1 -1 4 1 3 6 7 85 -1
|
|
96 A_DECODE_19_ 1 -1 -1 2 4 7 96 -1
|
|
95 A_DECODE_16_ 1 -1 -1 2 4 7 95 -1
|
|
94 A_DECODE_18_ 1 -1 -1 2 4 7 94 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
58 A_DECODE_17_ 1 -1 -1 2 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 2 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 2 4 7 56 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
|
63 CLK_030 1 -1 -1 1 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
59 A_1_ 1 -1 -1 0 59 -1
|
|
35 VPA 1 -1 -1 0 35 -1
|
|
29 DTACK 1 -1 -1 0 29 -1
|
|
10 CLK_000 1 -1 -1 0 10 -1
|
|
139 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
79 RW_000 5 365 7 2 4 6 79 -1 5 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
70 RW 5 370 6 1 7 70 -1 2 0 21
|
|
40 BERR 5 -1 4 1 7 40 -1 1 0 21
|
|
31 UDS_000 5 -1 3 1 6 31 -1 1 0 21
|
|
18 AHIGH_24_ 5 -1 -1 1 4 18 -1 1 0 21
|
|
17 AHIGH_25_ 5 -1 -1 1 4 17 -1 1 0 21
|
|
16 AHIGH_26_ 5 -1 -1 1 4 16 -1 1 0 21
|
|
15 AHIGH_27_ 5 -1 -1 1 4 15 -1 1 0 21
|
|
14 AHIGH_28_ 5 -1 -1 1 4 14 -1 1 0 21
|
|
5 AHIGH_29_ 5 -1 -1 1 4 5 -1 1 0 21
|
|
4 AHIGH_30_ 5 -1 -1 1 4 4 -1 1 0 21
|
|
3 AHIGH_31_ 5 -1 -1 1 4 3 -1 1 0 21
|
|
8 IPL_030_2_ 0 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 0 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 0 1 0 6 -1 10 0 21
|
|
80 DSACK1 0 7 0 80 -1 4 0 21
|
|
82 BGACK_030 0 7 0 82 -1 3 0 21
|
|
68 A_0_ 5 361 6 0 68 -1 3 0 21
|
|
34 VMA 0 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 0 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 -1 0 91 -1 1 0 21
|
|
78 SIZE_1_ 0 -1 0 78 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
69 SIZE_0_ 0 6 0 69 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 -1 0 32 -1 1 0 21
|
|
30 LDS_000 0 3 0 30 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 -1 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 -1 0 2 -1 1 0 21
|
|
367 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 3 0 21
|
|
317 inst_RESET_OUT 3 -1 -1 5 0 3 4 6 7 -1 -1 2 0 21
|
|
312 inst_CLK_OUT_PRE_D 3 -1 -1 3 1 6 7 -1 -1 1 0 21
|
|
299 inst_AS_030_D0 3 -1 -1 3 3 4 7 -1 -1 1 0 21
|
|
359 SM_AMIGA_i_7_ 3 -1 -1 2 3 7 -1 -1 15 0 21
|
|
293 cpu_est_2_ 3 -1 -1 2 3 6 -1 -1 4 0 21
|
|
296 cpu_est_1_ 3 -1 -1 2 3 6 -1 -1 3 0 21
|
|
294 cpu_est_3_ 3 -1 -1 2 3 6 -1 -1 3 0 21
|
|
320 CLK_000_D_0_ 3 -1 -1 2 3 7 -1 -1 1 0 21
|
|
318 CLK_000_D_1_ 3 -1 -1 2 3 7 -1 -1 1 0 21
|
|
364 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
363 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
362 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
304 inst_DS_000_DMA 3 -1 -1 1 0 -1 -1 9 0 21
|
|
303 inst_AS_000_DMA 3 -1 -1 1 7 -1 -1 7 0 21
|
|
365 RN_RW_000 3 79 7 1 7 79 -1 5 0 21
|
|
336 inst_DS_000_ENABLE 3 -1 -1 1 3 -1 -1 5 0 21
|
|
368 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
369 RN_VMA 3 34 3 1 3 34 -1 3 0 21
|
|
361 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
333 SM_AMIGA_0_ 3 -1 -1 1 7 -1 -1 3 0 21
|
|
311 inst_LDS_000_INT 3 -1 -1 1 3 -1 -1 3 0 21
|
|
308 SIZE_DMA_1_ 3 -1 -1 1 6 -1 -1 3 0 21
|
|
307 SIZE_DMA_0_ 3 -1 -1 1 6 -1 -1 3 0 21
|
|
370 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
366 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
360 CIIN_0 3 -1 -1 1 4 -1 -1 2 0 21
|
|
356 SM_AMIGA_1_ 3 -1 -1 1 7 -1 -1 2 0 21
|
|
334 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 -1 1 3 -1 -1 2 0 21
|
|
321 SM_AMIGA_5_ 3 -1 -1 1 7 -1 -1 2 0 21
|
|
310 inst_UDS_000_INT 3 -1 -1 1 3 -1 -1 2 0 21
|
|
297 inst_AS_000_INT 3 -1 -1 1 4 -1 -1 2 0 21
|
|
295 cpu_est_0_ 3 -1 -1 1 3 -1 -1 2 0 21
|
|
337 CLK_000_N_SYNC_12_ 3 -1 -1 1 3 -1 -1 1 0 21
|
|
332 CLK_000_D_12_ 3 -1 -1 1 7 -1 -1 1 0 21
|
|
326 CLK_000_D_4_ 3 -1 -1 1 7 -1 -1 1 0 21
|
|
324 IPL_D0_2_ 3 -1 -1 1 1 -1 -1 1 0 21
|
|
323 IPL_D0_1_ 3 -1 -1 1 1 -1 -1 1 0 21
|
|
322 IPL_D0_0_ 3 -1 -1 1 1 -1 -1 1 0 21
|
|
315 CLK_000_D_11_ 3 -1 -1 1 7 -1 -1 1 0 21
|
|
314 CLK_000_D_10_ 3 -1 -1 1 7 -1 -1 1 0 21
|
|
313 CLK_000_D_3_ 3 -1 -1 1 7 -1 -1 1 0 21
|
|
309 inst_VPA_D 3 -1 -1 1 3 -1 -1 1 0 21
|
|
302 inst_BGACK_030_INT_D 3 -1 -1 1 6 -1 -1 1 0 21
|
|
357 SM_AMIGA_3_ 3 -1 -1 0 -1 -1 8 0 21
|
|
355 inst_CLK_030_H 3 -1 -1 0 -1 -1 8 0 21
|
|
301 inst_AS_030_000_SYNC 3 -1 -1 0 -1 -1 7 0 21
|
|
358 SM_AMIGA_2_ 3 -1 -1 0 -1 -1 4 0 21
|
|
339 RST_DLY_1_ 3 -1 -1 0 -1 -1 4 0 21
|
|
306 CYCLE_DMA_1_ 3 -1 -1 0 -1 -1 4 0 21
|
|
354 SM_AMIGA_6_ 3 -1 -1 0 -1 -1 3 0 21
|
|
352 SM_AMIGA_4_ 3 -1 -1 0 -1 -1 3 0 21
|
|
338 RST_DLY_0_ 3 -1 -1 0 -1 -1 3 0 21
|
|
305 CYCLE_DMA_0_ 3 -1 -1 0 -1 -1 3 0 21
|
|
340 RST_DLY_2_ 3 -1 -1 0 -1 -1 2 0 21
|
|
300 N_140_i 3 -1 -1 0 -1 -1 2 0 21
|
|
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 -1 0 -1 -1 2 0 21
|
|
353 inst_CLK_000_NE_D0 3 -1 -1 0 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_11_ 3 -1 -1 0 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_10_ 3 -1 -1 0 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_9_ 3 -1 -1 0 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_8_ 3 -1 -1 0 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_7_ 3 -1 -1 0 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_6_ 3 -1 -1 0 -1 -1 1 0 21
|
|
345 CLK_000_N_SYNC_5_ 3 -1 -1 0 -1 -1 1 0 21
|
|
344 CLK_000_N_SYNC_4_ 3 -1 -1 0 -1 -1 1 0 21
|
|
343 CLK_000_N_SYNC_3_ 3 -1 -1 0 -1 -1 1 0 21
|
|
342 CLK_000_N_SYNC_2_ 3 -1 -1 0 -1 -1 1 0 21
|
|
341 CLK_000_N_SYNC_1_ 3 -1 -1 0 -1 -1 1 0 21
|
|
335 CLK_000_N_SYNC_0_ 3 -1 -1 0 -1 -1 1 0 21
|
|
331 CLK_000_D_9_ 3 -1 -1 0 -1 -1 1 0 21
|
|
330 CLK_000_D_8_ 3 -1 -1 0 -1 -1 1 0 21
|
|
329 CLK_000_D_7_ 3 -1 -1 0 -1 -1 1 0 21
|
|
328 CLK_000_D_6_ 3 -1 -1 0 -1 -1 1 0 21
|
|
327 CLK_000_D_5_ 3 -1 -1 0 -1 -1 1 0 21
|
|
325 CLK_000_D_2_ 3 -1 -1 0 -1 -1 1 0 21
|
|
319 inst_CLK_OUT_PRE_50 3 -1 -1 0 -1 -1 1 0 21
|
|
316 inst_DTACK_D0 3 -1 -1 0 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
|
|
85 RST 1 -1 -1 4 1 3 6 7 85 -1
|
|
96 A_DECODE_19_ 1 -1 -1 2 4 7 96 -1
|
|
95 A_DECODE_16_ 1 -1 -1 2 4 7 95 -1
|
|
94 A_DECODE_18_ 1 -1 -1 2 4 7 94 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
58 A_DECODE_17_ 1 -1 -1 2 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 2 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 2 4 7 56 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
|
63 CLK_030 1 -1 -1 1 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
59 A_1_ 1 -1 -1 0 59 -1
|
|
35 VPA 1 -1 -1 0 35 -1
|
|
29 DTACK 1 -1 -1 0 29 -1
|
|
10 CLK_000 1 -1 -1 0 10 -1
|
|
140 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
79 RW_000 5 363 7 2 4 6 79 -1 4 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
70 RW 5 368 6 1 7 70 -1 2 0 21
|
|
40 BERR 5 -1 4 1 7 40 -1 1 0 21
|
|
31 UDS_000 5 -1 3 1 6 31 -1 1 0 21
|
|
18 AHIGH_24_ 5 -1 -1 1 4 18 -1 1 0 21
|
|
17 AHIGH_25_ 5 -1 -1 1 4 17 -1 1 0 21
|
|
16 AHIGH_26_ 5 -1 -1 1 4 16 -1 1 0 21
|
|
15 AHIGH_27_ 5 -1 -1 1 4 15 -1 1 0 21
|
|
14 AHIGH_28_ 5 -1 -1 1 4 14 -1 1 0 21
|
|
5 AHIGH_29_ 5 -1 -1 1 4 5 -1 1 0 21
|
|
4 AHIGH_30_ 5 -1 -1 1 4 4 -1 1 0 21
|
|
3 AHIGH_31_ 5 -1 -1 1 4 3 -1 1 0 21
|
|
8 IPL_030_2_ 0 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 0 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 0 1 0 6 -1 10 0 21
|
|
80 DSACK1 0 7 0 80 -1 4 0 21
|
|
82 BGACK_030 0 7 0 82 -1 3 0 21
|
|
68 A_0_ 5 369 6 0 68 -1 3 0 21
|
|
34 VMA 0 3 0 34 -1 3 0 21
|
|
65 E 0 -1 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 -1 0 33 -1 2 0 21
|
|
28 BG_000 0 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 -1 0 91 -1 1 0 21
|
|
78 SIZE_1_ 0 -1 0 78 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
69 SIZE_0_ 0 6 0 69 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 -1 0 32 -1 1 0 21
|
|
30 LDS_000 0 3 0 30 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 -1 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 -1 0 2 -1 1 0 21
|
|
365 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 3 0 21
|
|
316 inst_RESET_OUT 3 -1 -1 5 0 3 4 6 7 -1 -1 2 0 21
|
|
312 inst_CLK_OUT_PRE_D 3 -1 -1 3 1 6 7 -1 -1 1 0 21
|
|
300 inst_AS_030_D0 3 -1 -1 3 3 4 7 -1 -1 1 0 21
|
|
319 CLK_000_D_0_ 3 -1 -1 2 3 7 -1 -1 1 0 21
|
|
317 CLK_000_D_1_ 3 -1 -1 2 3 7 -1 -1 1 0 21
|
|
359 SM_AMIGA_i_7_ 3 -1 -1 1 7 -1 -1 14 0 21
|
|
371 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
370 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
362 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
304 inst_DS_000_DMA 3 -1 -1 1 0 -1 -1 9 0 21
|
|
303 inst_AS_000_DMA 3 -1 -1 1 7 -1 -1 7 0 21
|
|
336 inst_DS_000_ENABLE 3 -1 -1 1 3 -1 -1 5 0 21
|
|
366 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
363 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
|
297 cpu_est_2_ 3 -1 -1 1 3 -1 -1 4 0 21
|
|
369 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
367 RN_VMA 3 34 3 1 3 34 -1 3 0 21
|
|
333 SM_AMIGA_0_ 3 -1 -1 1 7 -1 -1 3 0 21
|
|
311 inst_LDS_000_INT 3 -1 -1 1 3 -1 -1 3 0 21
|
|
308 SIZE_DMA_1_ 3 -1 -1 1 6 -1 -1 3 0 21
|
|
307 SIZE_DMA_0_ 3 -1 -1 1 6 -1 -1 3 0 21
|
|
296 cpu_est_1_ 3 -1 -1 1 3 -1 -1 3 0 21
|
|
294 cpu_est_3_ 3 -1 -1 1 3 -1 -1 3 0 21
|
|
368 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
364 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
360 CIIN_0 3 -1 -1 1 4 -1 -1 2 0 21
|
|
356 SM_AMIGA_1_ 3 -1 -1 1 7 -1 -1 2 0 21
|
|
320 SM_AMIGA_5_ 3 -1 -1 1 7 -1 -1 2 0 21
|
|
310 inst_UDS_000_INT 3 -1 -1 1 3 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 -1 1 4 -1 -1 2 0 21
|
|
295 cpu_est_0_ 3 -1 -1 1 3 -1 -1 2 0 21
|
|
337 CLK_000_N_SYNC_12_ 3 -1 -1 1 3 -1 -1 1 0 21
|
|
332 CLK_000_D_12_ 3 -1 -1 1 7 -1 -1 1 0 21
|
|
325 CLK_000_D_3_ 3 -1 -1 1 7 -1 -1 1 0 21
|
|
323 IPL_D0_2_ 3 -1 -1 1 1 -1 -1 1 0 21
|
|
322 IPL_D0_1_ 3 -1 -1 1 1 -1 -1 1 0 21
|
|
321 IPL_D0_0_ 3 -1 -1 1 1 -1 -1 1 0 21
|
|
314 CLK_000_D_11_ 3 -1 -1 1 7 -1 -1 1 0 21
|
|
313 CLK_000_D_10_ 3 -1 -1 1 7 -1 -1 1 0 21
|
|
309 inst_VPA_D 3 -1 -1 1 3 -1 -1 1 0 21
|
|
302 inst_BGACK_030_INT_D 3 -1 -1 1 6 -1 -1 1 0 21
|
|
357 SM_AMIGA_3_ 3 -1 -1 0 -1 -1 8 0 21
|
|
355 inst_CLK_030_H 3 -1 -1 0 -1 -1 8 0 21
|
|
301 inst_AS_030_000_SYNC 3 -1 -1 0 -1 -1 7 0 21
|
|
358 SM_AMIGA_2_ 3 -1 -1 0 -1 -1 4 0 21
|
|
339 RST_DLY_1_ 3 -1 -1 0 -1 -1 4 0 21
|
|
306 CYCLE_DMA_1_ 3 -1 -1 0 -1 -1 4 0 21
|
|
361 SM_AMIGA_i_7__0 3 -1 -1 0 -1 -1 3 0 21
|
|
354 SM_AMIGA_6_ 3 -1 -1 0 -1 -1 3 0 21
|
|
352 SM_AMIGA_4_ 3 -1 -1 0 -1 -1 3 0 21
|
|
338 RST_DLY_0_ 3 -1 -1 0 -1 -1 3 0 21
|
|
305 CYCLE_DMA_0_ 3 -1 -1 0 -1 -1 3 0 21
|
|
340 RST_DLY_2_ 3 -1 -1 0 -1 -1 2 0 21
|
|
334 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 -1 0 -1 -1 2 0 21
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 -1 0 -1 -1 2 0 21
|
|
293 N_151 3 -1 -1 0 -1 -1 2 0 21
|
|
353 inst_CLK_000_NE_D0 3 -1 -1 0 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_11_ 3 -1 -1 0 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_10_ 3 -1 -1 0 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_9_ 3 -1 -1 0 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_8_ 3 -1 -1 0 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_7_ 3 -1 -1 0 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_6_ 3 -1 -1 0 -1 -1 1 0 21
|
|
345 CLK_000_N_SYNC_5_ 3 -1 -1 0 -1 -1 1 0 21
|
|
344 CLK_000_N_SYNC_4_ 3 -1 -1 0 -1 -1 1 0 21
|
|
343 CLK_000_N_SYNC_3_ 3 -1 -1 0 -1 -1 1 0 21
|
|
342 CLK_000_N_SYNC_2_ 3 -1 -1 0 -1 -1 1 0 21
|
|
341 CLK_000_N_SYNC_1_ 3 -1 -1 0 -1 -1 1 0 21
|
|
335 CLK_000_N_SYNC_0_ 3 -1 -1 0 -1 -1 1 0 21
|
|
331 CLK_000_D_9_ 3 -1 -1 0 -1 -1 1 0 21
|
|
330 CLK_000_D_8_ 3 -1 -1 0 -1 -1 1 0 21
|
|
329 CLK_000_D_7_ 3 -1 -1 0 -1 -1 1 0 21
|
|
328 CLK_000_D_6_ 3 -1 -1 0 -1 -1 1 0 21
|
|
327 CLK_000_D_5_ 3 -1 -1 0 -1 -1 1 0 21
|
|
326 CLK_000_D_4_ 3 -1 -1 0 -1 -1 1 0 21
|
|
324 CLK_000_D_2_ 3 -1 -1 0 -1 -1 1 0 21
|
|
318 inst_CLK_OUT_PRE_50 3 -1 -1 0 -1 -1 1 0 21
|
|
315 inst_DTACK_D0 3 -1 -1 0 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
|
|
85 RST 1 -1 -1 4 1 3 6 7 85 -1
|
|
96 A_DECODE_19_ 1 -1 -1 2 4 7 96 -1
|
|
95 A_DECODE_16_ 1 -1 -1 2 4 7 95 -1
|
|
94 A_DECODE_18_ 1 -1 -1 2 4 7 94 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
58 A_DECODE_17_ 1 -1 -1 2 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 2 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 2 4 7 56 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
|
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
|
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
|
63 CLK_030 1 -1 -1 1 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
59 A_1_ 1 -1 -1 0 59 -1
|
|
35 VPA 1 -1 -1 0 35 -1
|
|
29 DTACK 1 -1 -1 0 29 -1
|
|
10 CLK_000 1 -1 -1 0 10 -1
|
|
140 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 5 0 1 2 5 7 40 -1 1 0 21
|
|
79 RW_000 5 364 7 3 0 4 6 79 -1 4 0 21
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
70 RW 5 369 6 2 0 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
68 A_0_ 5 370 6 1 1 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
|
8 IPL_030_2_ 5 363 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 362 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 371 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 367 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 366 7 0 82 -1 3 0 21
|
|
34 VMA 5 368 3 0 34 -1 3 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
28 BG_000 5 365 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
366 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
316 inst_RESET_OUT 3 -1 2 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
359 SM_AMIGA_i_7_ 3 -1 5 5 0 2 3 5 7 -1 -1 14 0 21
|
|
320 SM_AMIGA_5_ 3 -1 1 5 0 1 2 5 7 -1 -1 2 0 21
|
|
336 CLK_000_N_SYNC_12_ 3 -1 6 5 1 2 3 5 6 -1 -1 1 0 21
|
|
319 CLK_000_D_0_ 3 -1 4 5 0 1 3 5 7 -1 -1 1 0 21
|
|
317 CLK_000_D_1_ 3 -1 7 5 0 1 3 5 7 -1 -1 1 0 21
|
|
300 inst_AS_030_D0 3 -1 7 5 0 2 3 4 7 -1 -1 1 0 21
|
|
333 SM_AMIGA_0_ 3 -1 5 4 0 3 5 7 -1 -1 3 0 21
|
|
297 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 4 0 21
|
|
354 SM_AMIGA_6_ 3 -1 5 3 0 1 5 -1 -1 3 0 21
|
|
296 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
294 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
312 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
|
303 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
301 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21
|
|
335 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 5 0 21
|
|
338 RST_DLY_1_ 3 -1 6 2 2 6 -1 -1 4 0 21
|
|
368 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
351 SM_AMIGA_4_ 3 -1 5 2 0 5 -1 -1 3 0 21
|
|
337 RST_DLY_0_ 3 -1 6 2 2 6 -1 -1 3 0 21
|
|
311 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21
|
|
308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
356 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 2 0 21
|
|
353 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21
|
|
339 RST_DLY_2_ 3 -1 2 2 2 6 -1 -1 2 0 21
|
|
310 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
|
|
295 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 2 0 21
|
|
334 CLK_000_N_SYNC_0_ 3 -1 0 2 2 5 -1 -1 1 0 21
|
|
313 CLK_000_D_10_ 3 -1 0 2 0 7 -1 -1 1 0 21
|
|
309 inst_VPA_D 3 -1 6 2 3 5 -1 -1 1 0 21
|
|
302 inst_BGACK_030_INT_D 3 -1 3 2 2 6 -1 -1 1 0 21
|
|
371 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
363 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
362 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
304 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
357 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 8 0 21
|
|
355 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
367 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
364 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
|
358 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
306 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21
|
|
370 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
361 SM_AMIGA_i_7__0 3 -1 5 1 5 -1 -1 3 0 21
|
|
305 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
369 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
365 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
360 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21
|
|
293 N_149_i 3 -1 5 1 5 -1 -1 2 0 21
|
|
352 inst_CLK_000_NE_D0 3 -1 3 1 5 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_11_ 3 -1 2 1 6 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_10_ 3 -1 6 1 2 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_9_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_8_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_7_ 3 -1 5 1 3 -1 -1 1 0 21
|
|
345 CLK_000_N_SYNC_6_ 3 -1 0 1 5 -1 -1 1 0 21
|
|
344 CLK_000_N_SYNC_5_ 3 -1 5 1 0 -1 -1 1 0 21
|
|
343 CLK_000_N_SYNC_4_ 3 -1 6 1 5 -1 -1 1 0 21
|
|
342 CLK_000_N_SYNC_3_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
341 CLK_000_N_SYNC_2_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
340 CLK_000_N_SYNC_1_ 3 -1 2 1 3 -1 -1 1 0 21
|
|
332 CLK_000_D_12_ 3 -1 7 1 7 -1 -1 1 0 21
|
|
331 CLK_000_D_9_ 3 -1 1 1 0 -1 -1 1 0 21
|
|
330 CLK_000_D_8_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
329 CLK_000_D_7_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
328 CLK_000_D_6_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
327 CLK_000_D_5_ 3 -1 4 1 3 -1 -1 1 0 21
|
|
326 CLK_000_D_4_ 3 -1 4 1 4 -1 -1 1 0 21
|
|
325 CLK_000_D_3_ 3 -1 6 1 4 -1 -1 1 0 21
|
|
324 CLK_000_D_2_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
323 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
322 IPL_D0_1_ 3 -1 5 1 1 -1 -1 1 0 21
|
|
321 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
318 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
315 inst_DTACK_D0 3 -1 3 1 5 -1 -1 1 0 21
|
|
314 CLK_000_D_11_ 3 -1 0 1 7 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
67 IPL_2_ 1 -1 -1 2 1 2 67 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 6 66 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 5 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
10 CLK_000 1 -1 -1 2 3 4 10 -1
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
|
59 A_1_ 1 -1 -1 1 2 59 -1
|
|
35 VPA 1 -1 -1 1 6 35 -1
|
|
29 DTACK 1 -1 -1 1 3 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
139 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21
|
|
79 RW_000 5 362 7 3 0 4 6 79 -1 4 0 21
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
70 RW 5 367 6 2 0 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
68 A_0_ 5 368 6 1 1 68 -1 3 0 21
|
|
78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
|
8 IPL_030_2_ 5 361 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 370 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 369 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 365 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 364 7 0 82 -1 3 0 21
|
|
34 VMA 5 366 3 0 34 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
|
28 BG_000 5 363 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
364 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
317 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
301 inst_AS_030_D0 3 -1 7 5 0 2 3 4 7 -1 -1 1 0 21
|
|
359 SM_AMIGA_i_7_ 3 -1 5 4 0 2 5 7 -1 -1 15 0 21
|
|
321 SM_AMIGA_5_ 3 -1 5 4 0 2 5 7 -1 -1 2 0 21
|
|
320 CLK_000_D_0_ 3 -1 5 4 0 3 5 7 -1 -1 1 0 21
|
|
318 CLK_000_D_1_ 3 -1 7 4 0 3 5 7 -1 -1 1 0 21
|
|
294 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 4 0 21
|
|
354 SM_AMIGA_6_ 3 -1 5 3 0 1 5 -1 -1 3 0 21
|
|
334 SM_AMIGA_0_ 3 -1 5 3 0 5 7 -1 -1 3 0 21
|
|
297 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
295 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
337 CLK_000_N_SYNC_12_ 3 -1 2 3 3 4 5 -1 -1 1 0 21
|
|
313 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
|
304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
302 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21
|
|
336 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 5 0 21
|
|
366 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
352 SM_AMIGA_4_ 3 -1 5 2 0 5 -1 -1 3 0 21
|
|
312 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21
|
|
309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
356 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 2 0 21
|
|
311 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
|
|
296 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 2 0 21
|
|
335 CLK_000_N_SYNC_0_ 3 -1 0 2 3 5 -1 -1 1 0 21
|
|
315 CLK_000_D_11_ 3 -1 4 2 3 7 -1 -1 1 0 21
|
|
314 CLK_000_D_10_ 3 -1 4 2 4 7 -1 -1 1 0 21
|
|
310 inst_VPA_D 3 -1 6 2 3 5 -1 -1 1 0 21
|
|
303 inst_BGACK_030_INT_D 3 -1 7 2 2 6 -1 -1 1 0 21
|
|
370 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
369 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
361 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
357 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 8 0 21
|
|
355 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
365 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
362 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
|
|
358 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
339 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21
|
|
307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21
|
|
368 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
338 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21
|
|
306 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
367 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
363 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
360 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
340 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21
|
|
300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21
|
|
293 N_151_i 3 -1 5 1 5 -1 -1 2 0 21
|
|
353 inst_CLK_000_NE_D0 3 -1 4 1 5 -1 -1 1 0 21
|
|
351 CLK_000_N_SYNC_11_ 3 -1 6 1 2 -1 -1 1 0 21
|
|
350 CLK_000_N_SYNC_10_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
349 CLK_000_N_SYNC_9_ 3 -1 0 1 1 -1 -1 1 0 21
|
|
348 CLK_000_N_SYNC_8_ 3 -1 2 1 0 -1 -1 1 0 21
|
|
347 CLK_000_N_SYNC_7_ 3 -1 1 1 2 -1 -1 1 0 21
|
|
346 CLK_000_N_SYNC_6_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
345 CLK_000_N_SYNC_5_ 3 -1 5 1 6 -1 -1 1 0 21
|
|
344 CLK_000_N_SYNC_4_ 3 -1 2 1 5 -1 -1 1 0 21
|
|
343 CLK_000_N_SYNC_3_ 3 -1 1 1 2 -1 -1 1 0 21
|
|
342 CLK_000_N_SYNC_2_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
341 CLK_000_N_SYNC_1_ 3 -1 3 1 6 -1 -1 1 0 21
|
|
333 CLK_000_D_12_ 3 -1 3 1 7 -1 -1 1 0 21
|
|
332 CLK_000_D_9_ 3 -1 2 1 4 -1 -1 1 0 21
|
|
331 CLK_000_D_8_ 3 -1 1 1 2 -1 -1 1 0 21
|
|
330 CLK_000_D_7_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
329 CLK_000_D_6_ 3 -1 1 1 6 -1 -1 1 0 21
|
|
328 CLK_000_D_5_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
327 CLK_000_D_4_ 3 -1 0 1 3 -1 -1 1 0 21
|
|
326 CLK_000_D_3_ 3 -1 2 1 0 -1 -1 1 0 21
|
|
325 CLK_000_D_2_ 3 -1 0 1 2 -1 -1 1 0 21
|
|
324 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21
|
|
323 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21
|
|
322 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21
|
|
319 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
|
316 inst_DTACK_D0 3 -1 6 1 5 -1 -1 1 0 21
|
|
60 CLK_OSZI 9 -1 0 60 -1
|
|
13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1
|
|
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
|
96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1
|
|
95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1
|
|
94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1
|
|
58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1
|
|
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
|
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
|
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
|
67 IPL_2_ 1 -1 -1 2 1 2 67 -1
|
|
66 IPL_0_ 1 -1 -1 2 1 3 66 -1
|
|
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
|
59 A_1_ 1 -1 -1 2 2 6 59 -1
|
|
55 IPL_1_ 1 -1 -1 2 1 6 55 -1
|
|
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
|
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
|
|
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
|
|
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
|
|
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
|
35 VPA 1 -1 -1 1 6 35 -1
|
|
29 DTACK 1 -1 -1 1 6 29 -1
|
|
20 BG_030 1 -1 -1 1 3 20 -1
|
|
10 CLK_000 1 -1 -1 1 5 10 -1
|
|
150 "number of signals after reading design file"
|
|
|
|
"sig sig sig pair blk fan PT xor sync"
|
|
"num name type sig num out pin node cnt PT type"
|
|
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
|
|
|
40 BERR 5 -1 4 4 2 5 6 7 40 -1 1 0 21
|
|
79 RW_000 5 373 7 3 0 4 6 79 -1 3 0 21
|
|
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
|
68 A_0_ 5 374 6 2 0 1 68 -1 3 0 21
|
|
70 RW 5 381 6 2 5 7 70 -1 2 0 21
|
|
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
|
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
|
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
|
78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21
|
|
69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21
|
|
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
|
|
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
|
|
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
|
|
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
|
|
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
|
|
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
|
|
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
|
|
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
|
|
8 IPL_030_2_ 5 372 1 0 8 -1 10 0 21
|
|
7 IPL_030_0_ 5 376 1 0 7 -1 10 0 21
|
|
6 IPL_030_1_ 5 375 1 0 6 -1 10 0 21
|
|
80 DSACK1 5 379 7 0 80 -1 4 0 21
|
|
82 BGACK_030 5 378 7 0 82 -1 3 0 21
|
|
34 VMA 5 380 3 0 34 -1 3 0 21
|
|
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 3 0 21
|
|
65 E 0 6 0 65 -1 2 0 21
|
|
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
|
28 BG_000 5 377 3 0 28 -1 2 0 21
|
|
97 DS_030 0 0 0 97 -1 1 0 21
|
|
91 AVEC 0 0 0 91 -1 1 0 21
|
|
77 FPU_CS 0 7 0 77 -1 1 0 21
|
|
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
|
46 CIIN 0 4 0 46 -1 1 0 21
|
|
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
|
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
|
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
|
2 RESET 0 1 0 2 -1 1 0 21
|
|
378 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
|
316 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21
|
|
300 inst_AS_030_D0 3 -1 7 6 2 3 4 5 6 7 -1 -1 1 0 21
|
|
320 CLK_000_P_SYNC_10_ 3 -1 0 5 0 2 3 5 7 -1 -1 1 0 21
|
|
370 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 14 0 21
|
|
365 SM_AMIGA_6_ 3 -1 2 4 0 1 2 5 -1 -1 3 0 21
|
|
294 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 4 0 21
|
|
321 SM_AMIGA_5_ 3 -1 5 3 5 6 7 -1 -1 3 0 21
|
|
297 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
295 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
|
334 SM_AMIGA_0_ 3 -1 5 3 3 5 7 -1 -1 2 0 21
|
|
296 cpu_est_0_ 3 -1 1 3 1 3 5 -1 -1 2 0 21
|
|
338 CLK_000_N_SYNC_12_ 3 -1 3 3 3 4 5 -1 -1 1 0 21
|
|
335 CLK_000_N_SYNC_0_ 3 -1 3 3 2 4 5 -1 -1 1 0 21
|
|
312 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
|
302 inst_BGACK_030_INT_D 3 -1 7 3 1 2 6 -1 -1 1 0 21
|
|
303 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
|
301 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21
|
|
337 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 5 0 21
|
|
380 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
|
367 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
|
311 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21
|
|
308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
|
364 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21
|
|
310 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21
|
|
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21
|
|
298 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21
|
|
363 inst_CLK_000_NE_D0 3 -1 4 2 1 5 -1 -1 1 0 21
|
|
319 CLK_000_D_0_ 3 -1 6 2 2 3 -1 -1 1 0 21
|
|
318 CLK_000_D_1_ 3 -1 2 2 3 6 -1 -1 1 0 21
|
|
309 inst_VPA_D 3 -1 0 2 3 5 -1 -1 1 0 21
|
|
376 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
|
375 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
|
372 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
|
304 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
|
366 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
|
368 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21
|
|
379 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
|
369 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
|
340 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21
|
|
374 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
|
|
373 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
|
339 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21
|
|
336 SM_AMIGA_4_ 3 -1 5 1 5 -1 -1 3 0 21
|
|
306 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
|
293 N_226 3 -1 5 1 5 -1 -1 3 0 21
|
|
381 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
|
377 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
|
371 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
|
341 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21
|
|
305 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21
|
|
362 CLK_000_N_SYNC_11_ 3 -1 2 1 3 -1 -1 1 0 21
|
|
361 CLK_000_N_SYNC_10_ 3 -1 2 1 2 -1 -1 1 0 21
|
|
360 CLK_000_N_SYNC_9_ 3 -1 5 1 2 -1 -1 1 0 21
|
|
359 CLK_000_N_SYNC_8_ 3 -1 1 1 5 -1 -1 1 0 21
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358 CLK_000_N_SYNC_7_ 3 -1 6 1 1 -1 -1 1 0 21
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357 CLK_000_N_SYNC_6_ 3 -1 1 1 6 -1 -1 1 0 21
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356 CLK_000_N_SYNC_5_ 3 -1 0 1 1 -1 -1 1 0 21
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355 CLK_000_N_SYNC_4_ 3 -1 0 1 0 -1 -1 1 0 21
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354 CLK_000_N_SYNC_3_ 3 -1 5 1 0 -1 -1 1 0 21
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353 CLK_000_N_SYNC_2_ 3 -1 0 1 5 -1 -1 1 0 21
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352 CLK_000_N_SYNC_1_ 3 -1 4 1 0 -1 -1 1 0 21
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351 CLK_000_P_SYNC_9_ 3 -1 2 1 0 -1 -1 1 0 21
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350 CLK_000_P_SYNC_8_ 3 -1 0 1 2 -1 -1 1 0 21
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349 CLK_000_P_SYNC_7_ 3 -1 3 1 0 -1 -1 1 0 21
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348 CLK_000_P_SYNC_6_ 3 -1 6 1 3 -1 -1 1 0 21
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347 CLK_000_P_SYNC_5_ 3 -1 6 1 6 -1 -1 1 0 21
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346 CLK_000_P_SYNC_4_ 3 -1 0 1 6 -1 -1 1 0 21
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345 CLK_000_P_SYNC_3_ 3 -1 2 1 0 -1 -1 1 0 21
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344 CLK_000_P_SYNC_2_ 3 -1 5 1 2 -1 -1 1 0 21
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343 CLK_000_P_SYNC_1_ 3 -1 0 1 5 -1 -1 1 0 21
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342 CLK_000_P_SYNC_0_ 3 -1 3 1 0 -1 -1 1 0 21
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333 CLK_000_D_12_ 3 -1 7 1 7 -1 -1 1 0 21
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332 CLK_000_D_9_ 3 -1 3 1 6 -1 -1 1 0 21
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331 CLK_000_D_8_ 3 -1 1 1 3 -1 -1 1 0 21
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330 CLK_000_D_7_ 3 -1 6 1 1 -1 -1 1 0 21
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329 CLK_000_D_6_ 3 -1 1 1 6 -1 -1 1 0 21
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328 CLK_000_D_5_ 3 -1 4 1 1 -1 -1 1 0 21
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327 CLK_000_D_4_ 3 -1 2 1 4 -1 -1 1 0 21
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326 CLK_000_D_3_ 3 -1 6 1 2 -1 -1 1 0 21
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325 CLK_000_D_2_ 3 -1 6 1 6 -1 -1 1 0 21
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324 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
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323 IPL_D0_1_ 3 -1 5 1 1 -1 -1 1 0 21
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322 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21
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317 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
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315 inst_DTACK_D0 3 -1 2 1 5 -1 -1 1 0 21
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314 CLK_000_D_11_ 3 -1 7 1 7 -1 -1 1 0 21
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313 CLK_000_D_10_ 3 -1 6 1 7 -1 -1 1 0 21
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60 CLK_OSZI 9 -1 0 60 -1
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13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1
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85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
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96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1
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95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1
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94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1
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58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1
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57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
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56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
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90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
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66 IPL_0_ 1 -1 -1 2 1 3 66 -1
|
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63 CLK_030 1 -1 -1 2 0 7 63 -1
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59 A_1_ 1 -1 -1 2 1 2 59 -1
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55 IPL_1_ 1 -1 -1 2 1 5 55 -1
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27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
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10 CLK_000 1 -1 -1 2 3 6 10 -1
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93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
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92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
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84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
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83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
|
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67 IPL_2_ 1 -1 -1 1 1 67 -1
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35 VPA 1 -1 -1 1 0 35 -1
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29 DTACK 1 -1 -1 1 2 29 -1
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20 BG_030 1 -1 -1 1 3 20 -1 |