mirror of https://github.com/kr239/68030tk.git
117 lines
5.0 KiB
Plaintext
117 lines
5.0 KiB
Plaintext
#Build: Synplify Pro G-2012.09LC-SP1 , Build 035R, Mar 19 2013
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#install: C:\Program Files (x86)\ispLever\synpbase
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#OS: Windows 7 6.1
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#Hostname: DEEPTHOUGHT
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#Implementation: logic
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$ Start of Compile
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#Sun Jun 15 16:36:37 2014
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Synopsys VHDL Compiler, version comp201209rcp1, Build 283R, built Mar 19 2013
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@N|Running in 64-bit mode
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Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
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@N: CD720 :"C:\Program Files (x86)\ispLever\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
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@N:"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Top entity is set to BUS68030.
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File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
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VHDL syntax check successful!
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File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
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@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
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Post processing for work.bus68030.behavioral
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@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":136:34:136:36|Pruning register CLK_000_NE_D
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@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":135:34:135:36|Pruning register CLK_000_NE
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@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:61:133:75|Pruning register CLK_000_N_SYNC(12 downto 0)
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@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":117:53:117:56|Pruning register FPU_CS_INT
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@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:32:138:34|Pruning register CLK_REF(1 downto 0)
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@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":110:29:110:31|Pruning register DTACK_D0
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@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:35:124:37|Pruning register CLK_OUT_NE
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@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":102:36:102:38|Pruning bits 12 to 10 of CLK_000_P_SYNC(12 downto 0) -- not in use ...
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@A: CL282 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:35:137:37|Feedback mux created for signal CLK_030_H -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:32:138:34|Trying to extract state machine for register SM_AMIGA
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Extracted state machine for register SM_AMIGA
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State machine has 8 reachable states with original encodings of:
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000
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001
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010
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011
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100
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101
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110
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111
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@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:34:126:36|Trying to extract state machine for register cpu_est
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Extracted state machine for register cpu_est
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State machine has 11 reachable states with original encodings of:
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0000
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0010
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0011
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0100
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0101
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0110
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0111
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1010
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1011
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1100
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1111
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@END
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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# Sun Jun 15 16:36:37 2014
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###########################################################]
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Map & Optimize Report
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Synopsys CPLD Technology Mapper, Version maplat, Build 621R, Built Mar 19 2013
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Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
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Product Version G-2012.09LC-SP1
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@N: MF248 |Running in 64-bit mode.
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Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
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original code -> new code
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000 -> 00000001
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001 -> 00000010
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010 -> 00000100
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011 -> 00001000
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100 -> 00010000
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101 -> 00100000
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110 -> 01000000
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111 -> 10000000
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Encoding state machine cpu_est[0:10] (view:work.BUS68030(behavioral))
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original code -> new code
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0000 -> 0000
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0010 -> 0010
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0011 -> 0011
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0100 -> 0100
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0101 -> 0101
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0110 -> 0110
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0111 -> 0111
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1010 -> 1010
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1011 -> 1011
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1100 -> 1100
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1111 -> 1111
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---------------------------------------
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Resource Usage Report
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Simple gate primitives:
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DFFRH 34 uses
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DFFSH 28 uses
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DFF 1 use
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BI_DIR 12 uses
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IBUF 30 uses
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OBUF 16 uses
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BUFTH 1 use
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AND2 209 uses
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INV 172 uses
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OR2 21 uses
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XOR2 4 uses
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@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
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G-2012.09LC-SP1
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Mapper successful!
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At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 96MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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# Sun Jun 15 16:36:39 2014
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###########################################################]
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