68030tk/Logic/synlog/report
2014-06-15 16:53:31 +02:00
..
BUS68030_compiler_errors.txt Some Changes regarding CIIN and Timing 2014-06-15 16:53:31 +02:00
BUS68030_compiler_notes.txt Some Changes regarding CIIN and Timing 2014-06-15 16:53:31 +02:00
BUS68030_compiler_runstatus.xml Some Changes regarding CIIN and Timing 2014-06-15 16:53:31 +02:00
BUS68030_compiler_warnings.txt Some Changes regarding CIIN and Timing 2014-06-15 16:53:31 +02:00
BUS68030_fpga_mapper_errors.txt Initial push 2014-05-15 21:16:29 +02:00
BUS68030_fpga_mapper_notes.txt 33MHz @100MHz basis working 2014-05-24 16:03:26 +02:00
BUS68030_fpga_mapper_runstatus.xml Some Changes regarding CIIN and Timing 2014-06-15 16:53:31 +02:00
BUS68030_fpga_mapper_warnings.txt DMA-(potentially) working version but only 25Mhz 2014-05-25 21:00:40 +02:00