68030tk/Logic/68030_tk.tte

#$ TOOL  ispLEVER Classic 1.7.00.05.28.13
#$ DATE  Sat May 24 21:59:14 2014
#$ MODULE  BUS68030
#$ PINS 59 IPL_1_ IPL_0_ A_31_ DSACK_0_ FC_0_ IPL_2_ FC_1_ nEXP_SPACE BERR
 BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT DTACK AVEC AVEC_EXP VPA
 RST RW AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN A_30_ A_29_ A_28_ A_27_
 A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_030_1_
 IPL_030_0_ SIZE_1_ IPL_030_2_ DSACK_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 A0
 BG_000 BGACK_030 CLK_EXP FPU_CS E VMA RESET AMIGA_BUS_ENABLE SIZE_0_
#$ NODES 27 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_DTACK_SYNC
 inst_VPA_SYNC inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2 inst_CLK_000_D6
 SM_AMIGA_5_ SM_AMIGA_6_ inst_CLK_000_D3 inst_CLK_000_D5 SM_AMIGA_3_ SM_AMIGA_0_
 SM_AMIGA_1_ CLK_CNT_N_0_ CLK_CNT_N_1_ CLK_CNT_P_0_ CLK_CNT_P_1_ inst_CLK_000_D4
 SM_AMIGA_7_ SM_AMIGA_4_ inst_CLK_OUT_PRE SM_AMIGA_2_ cpu_est_0_ cpu_est_1_
 cpu_est_2_
.type f
.i 85
.o 169
.ilb A_31_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA
 RST RW A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_
 A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BG_000.Q BGACK_030.Q FPU_CS.Q VMA.Q
 inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_DTACK_SYNC.Q inst_VPA_SYNC.Q
 inst_CLK_000_D0.Q inst_CLK_000_D1.Q inst_CLK_000_D2.Q inst_CLK_000_D6.Q
 SM_AMIGA_5_.Q IPL_030_0_.Q IPL_030_1_.Q AS_000.Q SM_AMIGA_6_.Q IPL_030_2_.Q
 UDS_000.Q LDS_000.Q DSACK_1_.Q inst_CLK_000_D3.Q inst_CLK_000_D5.Q SM_AMIGA_3_.Q
 SM_AMIGA_0_.Q SM_AMIGA_1_.Q AS_030.Q DS_030.Q SIZE_0_.Q SIZE_1_.Q A0.Q
 CLK_CNT_N_0_.Q CLK_CNT_N_1_.Q CLK_CNT_P_0_.Q CLK_CNT_P_1_.Q inst_CLK_000_D4.Q
 SM_AMIGA_7_.Q SM_AMIGA_4_.Q inst_CLK_OUT_PRE.Q SM_AMIGA_2_.Q AMIGA_BUS_ENABLE.Q
 cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q E.Q AS_030.PIN AS_000.PIN DS_030.PIN
 UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN DSACK_1_.PIN DTACK.PIN
.ob DSACK_0_ DSACK_0_.OE BERR BERR.OE CLK_DIV_OUT.D CLK_DIV_OUT.C CLK_DIV_OUT.AR
 DTACK DTACK.OE AVEC AVEC_EXP AVEC_EXP.OE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW
 CIIN CIIN.OE IPL_030_1_.D IPL_030_1_.C IPL_030_1_.AP IPL_030_0_.D IPL_030_0_.C
 IPL_030_0_.AP SIZE_1_.D- SIZE_1_.C SIZE_1_.AP SIZE_1_.OE IPL_030_2_.D
 IPL_030_2_.C IPL_030_2_.AP DSACK_1_.D- DSACK_1_.C DSACK_1_.AP DSACK_1_.OE
 AS_030.D- AS_030.C AS_030.AP AS_030.OE AS_000.D AS_000.C AS_000.AP AS_000.OE
 DS_030.D- DS_030.C DS_030.AP DS_030.OE UDS_000.D- UDS_000.C UDS_000.AP
 UDS_000.OE LDS_000.D LDS_000.C LDS_000.AP LDS_000.OE A0.D A0.C A0.AP A0.OE
 BG_000.D- BG_000.C BG_000.AP BGACK_030.D BGACK_030.C BGACK_030.AP CLK_EXP.D
 CLK_EXP.C CLK_EXP.AR FPU_CS.D- FPU_CS.C FPU_CS.AP E.D.X1 E.D.X2 E.C E.AR
 VMA.D.X1 VMA.D.X2 VMA.C VMA.AP RESET.D RESET.C RESET.AR AMIGA_BUS_ENABLE.D
 AMIGA_BUS_ENABLE.C AMIGA_BUS_ENABLE.AP SIZE_0_.D- SIZE_0_.C SIZE_0_.AP
 SIZE_0_.OE inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP
 inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_BGACK_030_INT_D.AP
 inst_DTACK_SYNC.D- inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_VPA_SYNC.D-
 inst_VPA_SYNC.C inst_VPA_SYNC.AP inst_CLK_000_D0.D inst_CLK_000_D0.C
 inst_CLK_000_D0.AP inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_D1.AP
 inst_CLK_000_D2.D inst_CLK_000_D2.C inst_CLK_000_D2.AP inst_CLK_000_D6.D
 inst_CLK_000_D6.C inst_CLK_000_D6.AP SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR
 SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR inst_CLK_000_D3.D inst_CLK_000_D3.C
 inst_CLK_000_D3.AP inst_CLK_000_D5.D inst_CLK_000_D5.C inst_CLK_000_D5.AP
 SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C
 SM_AMIGA_0_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR CLK_CNT_N_0_.D
 CLK_CNT_N_0_.C CLK_CNT_N_0_.AR CLK_CNT_N_1_.D CLK_CNT_N_1_.C CLK_CNT_N_1_.AP
 CLK_CNT_P_0_.D CLK_CNT_P_0_.C CLK_CNT_P_0_.AR CLK_CNT_P_1_.D CLK_CNT_P_1_.C
 CLK_CNT_P_1_.AR inst_CLK_000_D4.D inst_CLK_000_D4.C inst_CLK_000_D4.AP
 SM_AMIGA_7_.D SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_4_.D SM_AMIGA_4_.C
 SM_AMIGA_4_.AR inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C inst_CLK_OUT_PRE.AR
 SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR cpu_est_0_.D cpu_est_0_.C
 cpu_est_0_.AR cpu_est_1_.T cpu_est_1_.C cpu_est_1_.AR cpu_est_2_.D.X1
 cpu_est_2_.D.X2 cpu_est_2_.C cpu_est_2_.AR
.phase 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
.p 133
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.end