mirror of
https://github.com/kr239/68030tk.git
synced 2024-09-23 00:01:45 +00:00
35 lines
743 B
Plaintext
35 lines
743 B
Plaintext
#-- Lattice Semiconductor Corporation Ltd.
|
|
#-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj
|
|
#-- Written on Thu May 15 22:21:47 2014
|
|
|
|
|
|
#device options
|
|
set_option -technology mach
|
|
set_option -part M4A5-128
|
|
|
|
#compilation/mapping options
|
|
|
|
#map options
|
|
|
|
#simulation options
|
|
set_option -write_verilog false
|
|
set_option -write_vhdl false
|
|
|
|
#timing analysis options
|
|
set_option -synthesis_onoff_pragma false
|
|
|
|
#-- add_file options
|
|
add_file -vhdl -lib work "68030-68000-bus.vhd"
|
|
|
|
#-- top module name
|
|
set_option -top_module BUS68030
|
|
|
|
#-- set result format/file last
|
|
project -result_file "BUS68030.edi"
|
|
|
|
#-- error message log file
|
|
project -log_file bus68030.srf
|
|
|
|
#-- run Synplify with 'arrange VHDL file'
|
|
project -run
|