mirror of https://github.com/kr239/68030tk.git
58 lines
1.6 KiB
VHDL
58 lines
1.6 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity clk_div_2by3 is
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port (
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clk : in std_logic;
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rst_n : in std_logic;
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clk_2by3 : out std_logic
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clk_1by3 : out std_logic);
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end clk_div_2by3;
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architecture clk_div_2by3_arch of clk_div_2by3 is
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signal clk_div_by3_pos : std_logic_vector(1 downto 0);
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signal clk_div_by3_neg : std_logic_vector(1 downto 0);
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begin -- behavior
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clk_2by3 <= (not clk_div_by3_neg(0) and clk_div_by3_pos(0)) or
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(clk_div_by3_neg(1) and clk_div_by3_pos(1));
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pos_edge: process (clk, rst_n)
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begin -- process posedge
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if rst_n = '0' then -- asynchronous reset (active low)
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clk_div_by3_pos <= (others => '0');
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elsif clk'event and clk = '1' then -- rising clock edge
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if clk_div_by3_pos = "10" then
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clk_div_by3_pos <= (others => '0');
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else
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clk_div_by3_pos <= clk_div_by3_pos + 1;
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end if;
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end if;
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end process pos_edge;
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neg_edge: process (clk, rst_n)
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begin -- process posedge
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if rst_n = '0' then -- asynchronous reset (active low)
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clk_div_by3_neg <= (others => '0');
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elsif clk'event and clk = '0' then -- rising clock edge
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if clk_div_by3_neg = "10" then
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clk_div_by3_neg <= (others => '0');
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else
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clk_div_by3_neg <= clk_div_by3_neg + 1;
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end if;
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end if;
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end process neg_edge;
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half_clk: process(clk_2by3, rst_n)
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begin
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if rst_n = '0' then -- asynchronous reset (active low)
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clk_1by3 <= '0';
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elsif rising_edge(clk_2by3) then -- rising clock edge
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clk_1by3 <= not clk_1by3;
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end if;
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end process half_clk;
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end clk_div_2by3_arch; |