mirror of https://github.com/kr239/68030tk.git
454 lines
13 KiB
VHDL
454 lines
13 KiB
VHDL
-- Copyright: Matthias Heinrichs 2014
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-- Free for non-comercial use
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-- No warranty just for fun
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-- I you want to earn money with this code, ask me first!
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity BUS68030 is
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port(
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AS_030: inout std_logic ;
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AS_000: inout std_logic ;
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DS_030: inout std_logic ;
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UDS_000: inout std_logic;
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LDS_000: inout std_logic;
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SIZE: inout std_logic_vector ( 1 downto 0 );
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A: inout std_logic_vector ( 31 downto 0 );
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nEXP_SPACE: in std_logic ;
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BERR: inout std_logic ;
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BG_030: in std_logic ;
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BG_000: out std_logic ;
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BGACK_030: out std_logic ;
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BGACK_000: in std_logic ;
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CLK_030: in std_logic ;
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CLK_000: in std_logic ;
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CLK_OSZI: in std_logic ;
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CLK_DIV_OUT: out std_logic ;
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CLK_EXP: out std_logic ;
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FPU_CS: out std_logic ;
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IPL_030: out std_logic_vector ( 2 downto 0 );
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IPL: in std_logic_vector ( 2 downto 0 );
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DSACK: inout std_logic_vector ( 1 downto 0 );
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DTACK: inout std_logic ;
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AVEC: out std_logic ;
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AVEC_EXP: inout std_logic ; --this is a "free pin"
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E: out std_logic ;
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VPA: in std_logic ;
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VMA: out std_logic ;
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RST: in std_logic ;
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RESET: out std_logic ;
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RW: in std_logic ;
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-- D: inout std_logic_vector ( 31 downto 28 );
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FC: in std_logic_vector ( 1 downto 0 );
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AMIGA_BUS_ENABLE: out std_logic ;
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AMIGA_BUS_DATA_DIR: out std_logic ;
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AMIGA_BUS_ENABLE_LOW: out std_logic;
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CIIN: out std_logic
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);
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end BUS68030;
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architecture Behavioral of BUS68030 is
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subtype ESTATE is std_logic_vector(3 downto 0);
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constant E1 : ESTATE := "0110";
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constant E2 : ESTATE := "0111";
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constant E3 : ESTATE := "0100";
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constant E4 : ESTATE := "0101";
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constant E5 : ESTATE := "0010";
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constant E6 : ESTATE := "0011";
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constant E7 : ESTATE := "1010";
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constant E8 : ESTATE := "1011";
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constant E9 : ESTATE := "1100";
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constant E10 : ESTATE := "1111";
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-- Illegal states
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constant E20 : ESTATE := "0000";
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constant E4a : ESTATE := "0001";
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constant E21 : ESTATE := "1000";
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constant E22 : ESTATE := "1001";
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constant E23 : ESTATE := "1101";
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constant E24 : ESTATE := "1110";
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signal cpu_est : ESTATE := E20;
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signal cpu_est_d : ESTATE := E20;
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subtype AMIGA_STATE is std_logic_vector(2 downto 0);
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constant IDLE_P : AMIGA_STATE := "000";
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constant IDLE_N : AMIGA_STATE := "001";
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constant AS_SET_P : AMIGA_STATE := "010";
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constant AS_SET_N : AMIGA_STATE := "011";
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constant SAMPLE_DTACK_P: AMIGA_STATE := "100";
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constant DATA_FETCH_N: AMIGA_STATE := "101";
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constant DATA_FETCH_P : AMIGA_STATE := "110";
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constant END_CYCLE_N : AMIGA_STATE := "111";
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signal SM_AMIGA : AMIGA_STATE := IDLE_P;
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--signal Dout:STD_LOGIC_VECTOR(3 downto 0) := "0000";
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signal AS_000_INT:STD_LOGIC:= '1';
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signal AS_030_000_SYNC:STD_LOGIC:= '1';
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signal BGACK_030_INT:STD_LOGIC:= '1';
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signal DTACK_SYNC:STD_LOGIC:= '1';
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signal DTACK_DMA:STD_LOGIC:= '1';
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signal FPU_CS_INT:STD_LOGIC:= '1';
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signal VPA_D: STD_LOGIC:='1';
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signal VPA_SYNC: STD_LOGIC:='1';
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signal VMA_INT: STD_LOGIC:='1';
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signal UDS_000_INT: STD_LOGIC:='1';
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signal LDS_000_INT: STD_LOGIC:='1';
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signal DSACK_INT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "11";
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signal CLK_CNT_P: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00";
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signal CLK_CNT_N: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00";
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signal CLK_REF: STD_LOGIC_VECTOR ( 1 downto 0 ) := "10";
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signal CLK_OUT_PRE: STD_LOGIC:='1';
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signal CLK_OUT_INT: STD_LOGIC:='1';
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signal CLK_030_D: STD_LOGIC:='1';
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signal CLK_000_D0: STD_LOGIC := '1';
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signal CLK_000_D1: STD_LOGIC := '1';
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signal CLK_000_D2: STD_LOGIC := '1';
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signal CLK_000_D3: STD_LOGIC := '1';
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signal CLK_000_D4: STD_LOGIC := '1';
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signal CLK_000_D5: STD_LOGIC := '1';
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signal CLK_000_D6: STD_LOGIC := '1';
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begin
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--the clocks
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neg_clk: process(RST, CLK_OSZI)
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begin
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if(RST = '0' ) then
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CLK_CNT_N <= "10";
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elsif(falling_edge(CLK_OSZI)) then
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--clk generation : up to now just half the clock
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if(CLK_CNT_N = "10") then
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--CLK_OUT_PRE <= not CLK_OUT_PRE;
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CLK_CNT_N <= "00";
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else
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CLK_CNT_N <= CLK_CNT_N+1;
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end if;
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end if;
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end process neg_clk;
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--the clocks
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clk: process(RST, CLK_OSZI)
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begin
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if(RST = '0' ) then
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CLK_CNT_P <= "00";
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RESET <= '0';
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CLK_OUT_PRE <= '0';
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CLK_OUT_INT <= '0';
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cpu_est <= E20;
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cpu_est_d <= E20;
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VPA_D <= '1';
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CLK_000_D0 <= '1';
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CLK_000_D1 <= '1';
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CLK_000_D2 <= '1';
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CLK_000_D3 <= '1';
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CLK_000_D4 <= '1';
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CLK_000_D5 <= '1';
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CLK_000_D6 <= '1';
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elsif(rising_edge(CLK_OSZI)) then
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--reset buffer
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RESET <= '1';
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--clk generation : up to now just half the clock
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if(CLK_CNT_P = "10") then
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--CLK_OUT_PRE <= not CLK_OUT_PRE;
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CLK_CNT_P <= "00";
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else
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CLK_CNT_P <= CLK_CNT_P+1;
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end if;
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if(CLK_CNT_P ="00" or CLK_CNT_N ="00")then --33MHz Clock
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CLK_OUT_PRE <= '0';
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else
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CLK_OUT_PRE <= '1';
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end if;
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-- the external clock to the processor is generated here
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CLK_OUT_INT <= CLK_OUT_PRE; --this way we know the clock of the next state: Its like looking in the future, cool!
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--delayed Clocks for edge detection
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CLK_000_D0 <= CLK_000;
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CLK_000_D1 <= CLK_000_D0;
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CLK_000_D2 <= CLK_000_D1;
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CLK_000_D3 <= CLK_000_D2;
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CLK_000_D4 <= CLK_000_D3;
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CLK_000_D5 <= CLK_000_D4;
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CLK_000_D6 <= CLK_000_D5;
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-- e-clock
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if(CLK_000_D1 = '0' and CLK_000_D0 = '1') then
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case (cpu_est) is
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when E1 => cpu_est <= E2 ;
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when E2 => cpu_est <= E3 ;
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when E3 => cpu_est <= E4;
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when E4 => cpu_est <= E5 ;
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when E5 => cpu_est <= E6 ;
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when E6 => cpu_est <= E7 ;
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when E7 => cpu_est <= E8 ;
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when E8 => cpu_est <= E9 ;
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when E9 => cpu_est <= E10;
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when E10 => cpu_est <= E1 ;
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-- Illegal states
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when E4a => cpu_est <= E5 ;
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when E20 => cpu_est <= E10;
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when E21 => cpu_est <= E10;
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when E22 => cpu_est <= E9 ;
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when E23 => cpu_est <= E9 ;
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when E24 => cpu_est <= E10;
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when others =>
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null;
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end case;
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end if;
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cpu_est_d <= cpu_est;
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VPA_D <= VPA;
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end if;
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end process clk;
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--the state process
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state_machine: process(RST, CLK_OSZI)
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begin
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if(RST = '0' ) then
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SM_AMIGA <= IDLE_P;
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AS_000_INT <= '1';
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AS_030_000_SYNC <= '1';
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UDS_000_INT <= '1';
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LDS_000_INT <= '1';
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CLK_REF <= "00";
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VMA_INT <= '1';
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FPU_CS_INT <= '1';
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BG_000 <= '1';
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BGACK_030_INT <= '1';
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DSACK_INT <= "11";
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DTACK_DMA <= '1';
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DTACK_SYNC <= '1';
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VPA_SYNC <= '1';
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IPL_030 <= "111";
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AMIGA_BUS_ENABLE <= '1';
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elsif(rising_edge(CLK_OSZI)) then
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--bgack is simple: assert as soon as Amiga asserts but hold bg_ack for one amiga-clock
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if(BGACK_000='0') then
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BGACK_030_INT <= '0';
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elsif (BGACK_000='1' AND CLK_000_D1='0' and CLK_000_D0='1') then -- BGACK_000 is high here!
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BGACK_030_INT <= '1'; --hold this signal high until 7m clock goes high
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end if;
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--bus grant only in idle state
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if(BG_030= '1')then
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BG_000 <= '1';
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elsif( BG_030= '0' AND (SM_AMIGA = IDLE_P)
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and nEXP_SPACE = '1' and AS_030='1'
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and CLK_000='1' ) then --bus granted no local access and no AS_030 running!
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BG_000 <= '0';
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end if;
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--interrupt buffering to avoid ghost interrupts
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if(CLK_000_D1='0' and CLK_000_D0='1')then
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IPL_030<=IPL;
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end if;
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-- as030-sampling and FPU-Select
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if(AS_030 ='1') then -- "async" reset of various signals
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AS_030_000_SYNC <= '1';
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FPU_CS_INT <= '1';
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DSACK_INT <="11";
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AS_000_INT <= '1';
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UDS_000_INT <= '1';
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LDS_000_INT <= '1';
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DTACK_SYNC <= '1';
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VPA_SYNC <= '1';
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AMIGA_BUS_ENABLE <= '1';
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elsif( CLK_030 = '1' AND --68030 has a valid AS on high clocks
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AS_030 = '0') then
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if(FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0' AND BGACK_000='1') then
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FPU_CS_INT <= '0';
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else
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if(nEXP_SPACE ='1' and SM_AMIGA = IDLE_P )then
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AS_030_000_SYNC <= '0';
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end if;
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end if;
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end if;
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-- VMA generation
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if(CLK_000_D0='0' AND VPA_D='0' AND cpu_est = E4)then --assert
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VMA_INT <= '0';
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elsif(CLK_000_D0='1' AND AS_000_INT='1' AND cpu_est=E1)then --deassert
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VMA_INT <= '1';
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end if;
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--Amiga statemachine
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case (SM_AMIGA) is
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when IDLE_P => --68000:S0 wait for a falling edge
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if( CLK_000_D2='0' and CLK_000_D3= '1' and AS_030_000_SYNC = '0')then
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SM_AMIGA<=IDLE_N; --go to s1
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end if;
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when IDLE_N => --68000:S1 place Adress on bus and wait for rising edge, on a rising CLK_000 look for a amiga adressrobe
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if(nEXP_SPACE ='1')then
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AMIGA_BUS_ENABLE <= '0' ;--for now: allways on for amiga
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else -- if this a delayed expansion space detection, aboard this cycle!
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AMIGA_BUS_ENABLE <= '1';
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AS_030_000_SYNC <= '1';
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SM_AMIGA <= IDLE_P; --aboard
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end if;
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if(CLK_000_D0='1')then --go to s2
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SM_AMIGA <= AS_SET_P; --as for amiga set!
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end if;
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when AS_SET_P => --68000:S2 Amiga cycle starts here: since AS is asserted during transition to this state we simply wait here
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AS_000_INT <= '0';
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if (RW='1' and DS_030 = '0') then --read: set udl/lds
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if(A(0)='0') then
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UDS_000_INT <= '0';
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else
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UDS_000_INT <= '1';
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end if;
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if((A(0)='1' OR SIZE(0)='0' OR SIZE(1)='1')) then
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LDS_000_INT <= '0';
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else
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LDS_000_INT <= '1';
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end if;
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end if;
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if(CLK_000_D0='0')then --go to s3
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SM_AMIGA<=AS_SET_N;
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end if;
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when AS_SET_N => --68000:S3: nothing happens here; on a transition to s4: assert uds/lds on write
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if (RW='0' and DS_030 = '0') then --write: set udl/lds earlier than in the specs. this does not seem to harm anything and is saver, than sampling uds/lds too late
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if(A(0)='0') then
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UDS_000_INT <= '0';
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else
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UDS_000_INT <= '1';
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end if;
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if((A(0)='1' OR SIZE(0)='0' OR SIZE(1)='1')) then
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LDS_000_INT <= '0';
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else
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LDS_000_INT <= '1';
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end if;
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end if;
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if(CLK_000_D0='1')then --go to s4
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SM_AMIGA <= SAMPLE_DTACK_P;
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end if;
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when SAMPLE_DTACK_P=> --68000:S4 wait for dtack or VMA
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if(CLK_000_D0='0' )then --go to s5
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if(DTACK_SYNC = '0' OR VPA_SYNC ='0')then
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SM_AMIGA<=DATA_FETCH_N;
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end if;
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elsif(CLK_000_D0='1' )then -- high clock: sample DTACK
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if(VPA_D = '1' AND DTACK='0') then
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DTACK_SYNC <= '0';
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elsif(VPA_D='0' AND cpu_est=E9 AND VMA_INT='0') then --vpa/vma cycle: sync VPA on E9: one 7M-clock to latch!
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VPA_SYNC <= '0';
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end if;
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end if;
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when DATA_FETCH_N=> --68000:S5 nothing happens here just wait for positive clock
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if(CLK_000_D0='1')then --go to s6
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SM_AMIGA<=DATA_FETCH_P;
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end if;
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when DATA_FETCH_P => --68000:S6: READ: here comes the data on the bus!
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if( CLK_000_D5 ='1' AND CLK_000_D6 = '0' ) then --go to s7 next 030-clock is high: dsack is sampled at the falling edge
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DSACK_INT<="01";
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AS_030_000_SYNC <= '1'; --cycle end
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elsif( CLK_000_D0 ='0') then --go to s7 next 030-clock is high: dsack is sampled at the falling edge
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--DSACK_INT<="01";
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SM_AMIGA<=END_CYCLE_N;
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--AS_030_000_SYNC <= '1'; --cycle end
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end if;
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when END_CYCLE_N =>--68000:S7: Latch/Store data. Wait here for new cycle and go to IDLE on high clock
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if(CLK_000_D0='1' and AS_000_INT = '1' )then --go to s0
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SM_AMIGA<=IDLE_P;
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end if;
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end case;
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--dma stuff
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--DTACK for DMA cycles
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if(AS_000_INT ='0' AND DSACK(1) ='0') then
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DTACK_DMA <= '0';
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else
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DTACK_DMA <= '1';
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end if;
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end if;
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end process state_machine;
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--output clock assignment
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CLK_DIV_OUT <= CLK_OUT_INT;
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CLK_EXP <= CLK_OUT_INT;
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AVEC_EXP <= 'Z' when FPU_CS_INT ='1' else '0';
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--dtack for dma
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DTACK <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' else
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DTACK_DMA;
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--fpu
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FPU_CS <= FPU_CS_INT;
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--if no copro is installed:
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BERR <= 'Z' when FPU_CS_INT ='1' else '0';
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--cache inhibit: For now: disable
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CIIN <= '1' WHEN A(31 downto 20) = x"00F" ELSE
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--'1' WHEN A(31 downto 16) = x"00E0" ELSE
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'Z' WHEN not(A(31 downto 24) = x"00") ELSE
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'0';
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--bus buffers
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AMIGA_BUS_DATA_DIR <='1' WHEN RW='0' ELSE '0';
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AMIGA_BUS_ENABLE_LOW <= '1'; --for now: allways off
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--e and VMA
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E <= cpu_est(3);
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VMA <= VMA_INT;
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--AVEC
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AVEC <= '1';
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--as and uds/lds
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AS_000 <= 'Z' when BGACK_030_INT ='0' else
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AS_000_INT;
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UDS_000 <= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle
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UDS_000_INT;
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LDS_000 <= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle
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LDS_000_INT;
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--dsack
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DSACK <= "ZZ" when nEXP_SPACE = '0' else -- output on amiga cycle
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DSACK_INT;
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BGACK_030 <= BGACK_030_INT;
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-- signal assignment
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--DS_030 <= "ZZ";
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--DS_030 <= "ZZ" when BGACK_030_INT ='1' else -- output on dma cycle
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-- DS_030_INT;
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--A(1) <= 'Z';
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--A(0) <= 'Z';
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--A[1 downto 0] <= "ZZ" when BGACK_030_INT ='1' else -- output on dma cycle
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-- A_INT;
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|
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--SIZE <= "ZZ";
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|
--SIZE <= "ZZ" when BGACK_030_INT ='1' else -- output on dma cycle
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-- SIZE_INT;
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end Behavioral;
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