mirror of https://github.com/kr239/68030tk.git
184 lines
3.2 KiB
Plaintext
184 lines
3.2 KiB
Plaintext
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[Device]
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Family = M4A5;
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PartNumber = M4A5-128/64-10VC;
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Package = 100TQFP;
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PartType = M4A5-128/64;
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Speed = -10;
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Operating_condition = COM;
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Status = Production;
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EN_PinGLB = Yes;
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EN_PinMacrocell = Yes;
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[Revision]
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Parent = m4a5.lci;
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DATE = 05/15/2014;
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TIME = 12:30:11;
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Source_Format = Pure_VHDL;
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Synthesis = Synplify;
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[Ignore Assignments]
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[Clear Assignments]
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[Backannotate Assignments]
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[Global Constraints]
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Spread_placement = Yes;
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Zero_hold_time = Yes;
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[Location Assignments]
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layer = OFF;
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AS_030 = Pin, 82, -, H, -;
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A_0_ = Pin, 69, -, G, -;
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A_16_ = Pin, 96, -, A, -;
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A_17_ = Pin, 59, -, F, -;
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A_18_ = Pin, 95, -, A, -;
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A_19_ = Pin, 97, -, A, -;
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BGACK_000 = Pin, 28, -, D, -;
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BG_030 = Pin, 21, -, C, -;
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CLK_000 = Pin, 11, -, -, -;
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CLK_030 = Pin, 64, -, -, -;
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CLK_OSZI = Pin, 61, -, -, -;
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CPU_SPACE = Pin, 14, -, -, -;
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FC_0_ = Pin, 57, -, F, -;
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FC_1_ = Pin, 58, -, F, -;
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IPL_0_ = Pin, 67, -, G, -;
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IPL_1_ = Pin, 56, -, F, -;
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IPL_2_ = Pin, 68, -, G, -;
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RST = Pin, 86, -, -, -;
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RW = Pin, 71, -, G, -;
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SIZE_1_ = Pin, 79, -, H, -;
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SIZE_0_ = Pin, 70, -, G, -;
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VPA = Pin, 36, -, -, -;
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AVEC = Pin, 92, -, A, -;
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BGACK_030 = Pin, 83, -, H, -;
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BG_000 = Pin, 29, -, D, -;
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CLK_DIV_OUT = Pin, 65, -, G, -;
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CLK_EXP = Pin, 10, -, B, -;
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DSACK_0_ = Pin, 80, -, H, -;
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E = Pin, 66, -, G, -;
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FPU_CS = Pin, 78, -, H, -;
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IPL_030_0_ = Pin, 8, -, B, -;
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IPL_030_1_ = Pin, 7, -, B, -;
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IPL_030_2_ = Pin, 9, -, B, -;
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LDS_000 = Pin, 31, -, D, -;
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UDS_000 = Pin, 32, -, D, -;
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VMA = Pin, 35, -, D, -;
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AS_000 = Pin, 33, -, D, -;
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DSACK_1_ = Pin, 81, -, H, -;
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DTACK = Pin, 30, -, D, -;
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RESET = Pin, 3, -, B, -;
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AMIGA_BUS_DATA_DIR = Pin, 48, -, E, -;
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AMIGA_BUS_ENABLE = Pin, 34, -, D, -;
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AMIGA_BUS_ENABLE_LOW = Pin, 20, -, C, -;
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CIIN = Pin, 47, -, E, -;
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A_20_ = Pin, 93, -, A, -;
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A_21_ = Pin, 94, -, A, -;
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A_22_ = Pin, 85, -, H, -;
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A_23_ = Pin, 84, -, H, -;
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A_24_ = Pin, 19, -, C, -;
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A_25_ = Pin, 18, -, C, -;
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A_26_ = Pin, 17, -, C, -;
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A_27_ = Pin, 16, -, C, -;
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A_28_ = Pin, 15, -, C, -;
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A_29_ = Pin, 6, -, B, -;
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A_30_ = Pin, 5, -, B, -;
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A_31_ = Pin, 4, -, B, -;
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DS_030 = Pin, 98, -, A, -;
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AVEC_EXP = Pin, 22, -, C, -;
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BERR = Pin, 41, -, E, -;
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[Group Assignments]
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layer = OFF;
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[Resource Reservations]
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layer = OFF;
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[Fitter Report Format]
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[Power]
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[Source Constraint Option]
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[Fast Bypass]
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[OSM Bypass]
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[Input Registers]
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[Netlist/Delay Format]
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NetList = VHDL;
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[IO Types]
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layer = OFF;
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[Pullup]
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Default = UP;
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[Slewrate]
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[Region]
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[Timing Constraints]
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[HSI Attributes]
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[Input Delay]
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[opt global constraints list]
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[Explorer User Settings]
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[Pin attributes list]
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[global constraints list]
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[Global Constraints Process Update]
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[pin lock limitation]
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[LOCATION ASSIGNMENTS LIST]
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[RESOURCE RESERVATIONS LIST]
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[individual constraints list]
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[Attributes list setting]
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[Timing Analyzer]
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[PLL Assignments]
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[Dual Function Macrocell]
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[Explorer Results]
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[VHDL synplify constraints]
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[VHDL spectrum constraints]
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[verilog synplify constraints]
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[verilog spectrum constraints]
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[VHDL synplify constraints list]
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[VHDL spectrum constraints list]
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[verilog synplify constraints list]
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[verilog spectrum constraints list]
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[Constraint Version]
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version = 1.0;
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[ORP ASSIGNMENTS]
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layer = OFF;
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[Node attribute]
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layer = OFF;
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[SYMBOL/MODULE attribute]
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layer = OFF;
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