mirror of https://github.com/kr239/68030tk.git
211 lines
4.4 KiB
Plaintext
211 lines
4.4 KiB
Plaintext
[DEVICE]
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Family = M4A5;
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PartType = M4A5-128/64;
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Package = 100TQFP;
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PartNumber = M4A5-128/64-10VC;
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Speed = -10;
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Operating_condition = COM;
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EN_Segment = No;
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Pin_MC_1to1 = No;
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EN_PinReserve_IO = Yes;
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EN_PinReserve_BIDIR = Yes;
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Voltage = 5.0;
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[REVISION]
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RCS = "$Revision: 1.2 $";
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Parent = m4a5.lci;
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SDS_File = m4a5.sds;
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Design = 68030_tk.tt4;
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DATE = 5/15/14;
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TIME = 19:20:57;
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Source_Format = Pure_VHDL;
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Type = TT2;
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Pre_Fit_Time = 1;
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[IGNORE ASSIGNMENTS]
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Pin_Assignments = No;
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Pin_Keep_Block = No;
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Pin_Keep_Segment = No;
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Group_Assignments = No;
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Macrocell_Assignments = No;
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Macrocell_Keep_Block = No;
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Macrocell_Keep_Segment = No;
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Pin_Reservation = No;
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Block_Reservation = No;
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Segment_Reservation = No;
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Timing_Constraints = No;
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[CLEAR ASSIGNMENTS]
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Pin_Assignments = No;
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Pin_Keep_Block = No;
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Pin_Keep_Segment = No;
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Group_Assignments = No;
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Macrocell_Assignments = No;
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Macrocell_Keep_Block = No;
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Macrocell_Keep_Segment = No;
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Pin_Reservation = No;
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Block_Reservation = No;
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Segment_Reservation = No;
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Timing_Constraints = No;
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[BACKANNOTATE ASSIGNMENTS]
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Pin_Block = No;
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Pin_Macrocell_Block = No;
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Routing = No;
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[GLOBAL CONSTRAINTS]
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Max_PTerm_Split = 16;
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Max_PTerm_Collapse = 16;
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Max_Pin_Percent = 100;
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Max_Macrocell_Percent = 100;
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Max_GLB_Input_Percent = 100;
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Max_Seg_In_Percent = 100;
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Logic_Reduction = Yes;
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XOR_Synthesis = Yes;
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DT_Synthesis = Yes;
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Node_Collapse = Yes;
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Run_Time = 0;
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Set_Reset_Dont_Care = No;
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Clock_Optimize = No;
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In_Reg_Optimize = Yes;
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Balanced_Partitioning = Yes;
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Device_max_fanin = 33;
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Device_max_pterms = 20;
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Usercode = 0;
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Usercode_Format = Hex;
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[LOCATION ASSIGNMENTS]
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Layer = OFF;
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A_30_ = pin,5,-,B,-;
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A_29_ = pin,6,-,B,-;
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SIZE_1_ = pin,79,-,H,-;
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A_28_ = pin,15,-,C,-;
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A_27_ = pin,16,-,C,-;
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A_31_ = pin,4,-,B,-;
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A_26_ = pin,17,-,C,-;
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A_25_ = pin,18,-,C,-;
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A_24_ = pin,19,-,C,-;
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A_23_ = pin,84,-,H,-;
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IPL_2_ = pin,68,-,G,-;
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A_22_ = pin,85,-,H,-;
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A_21_ = pin,94,-,A,-;
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A_20_ = pin,93,-,A,-;
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A_19_ = pin,97,-,A,-;
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FC_1_ = pin,58,-,F,-;
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A_18_ = pin,95,-,A,-;
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AS_030 = pin,82,-,H,-;
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A_17_ = pin,59,-,F,-;
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A_16_ = pin,96,-,A,-;
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DS_030 = pin,98,-,A,-;
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CPU_SPACE = pin,14,-,-,-;
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BERR = pin,41,-,E,-;
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BG_030 = pin,21,-,C,-;
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BGACK_000 = pin,28,-,D,-;
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CLK_030 = pin,64,-,-,-;
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CLK_000 = pin,11,-,-,-;
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CLK_OSZI = pin,61,-,-,-;
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CLK_EXP = pin,10,-,B,-;
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A_0_ = pin,69,-,G,-;
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AVEC = pin,92,-,A,-;
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AVEC_EXP = pin,22,-,C,-;
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IPL_1_ = pin,56,-,F,-;
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VPA = pin,36,-,-,-;
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IPL_0_ = pin,67,-,G,-;
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DSACK_0_ = pin,80,-,H,-;
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RST = pin,86,-,-,-;
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FC_0_ = pin,57,-,F,-;
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RW = pin,71,-,G,-;
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AMIGA_BUS_ENABLE = pin,34,-,D,-;
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AMIGA_BUS_DATA_DIR = pin,48,-,E,-;
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AMIGA_BUS_ENABLE_LOW = pin,20,-,C,-;
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CIIN = pin,47,-,E,-;
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SIZE_0_ = pin,70,-,G,-;
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IPL_030_2_ = pin,9,-,B,-;
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DSACK_1_ = pin,81,-,H,-;
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AS_000 = pin,33,-,D,-;
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UDS_000 = pin,32,-,D,-;
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LDS_000 = pin,31,-,D,-;
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BG_000 = pin,29,-,D,-;
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BGACK_030 = pin,83,-,H,-;
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CLK_DIV_OUT = pin,65,-,G,-;
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FPU_CS = pin,78,-,H,-;
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DTACK = pin,30,-,D,-;
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IPL_030_1_ = pin,7,-,B,-;
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IPL_030_0_ = pin,8,-,B,-;
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E = pin,66,-,G,-;
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VMA = pin,35,-,D,-;
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RESET = pin,3,-,B,-;
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cpu_est_1_ = node,-,-,G,3;
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inst_AS_030_000_SYNC = node,-,-,H,1;
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inst_DTACK_SYNC = node,-,-,G,14;
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inst_VPA_D = node,-,-,B,6;
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inst_VPA_SYNC = node,-,-,G,12;
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inst_CLK_000_D = node,-,-,A,0;
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inst_CLK_000_DD = node,-,-,D,14;
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inst_CLK_OUT_PRE = node,-,-,G,10;
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cpu_est_0_ = node,-,-,G,11;
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cpu_est_2_ = node,-,-,G,7;
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CLK_CNT_0_ = node,-,-,G,15;
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SM_AMIGA_6_ = node,-,-,D,2;
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SM_AMIGA_7_ = node,-,-,G,6;
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inst_RISING_CLK_AMIGA = node,-,-,H,9;
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SM_AMIGA_4_ = node,-,-,D,13;
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SM_AMIGA_3_ = node,-,-,G,13;
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SM_AMIGA_5_ = node,-,-,D,6;
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CLK_000_CNT_0_ = node,-,-,H,5;
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CLK_000_CNT_1_ = node,-,-,G,5;
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CLK_000_CNT_2_ = node,-,-,H,13;
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CLK_000_CNT_3_ = node,-,-,H,2;
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SM_AMIGA_2_ = node,-,-,G,9;
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SM_AMIGA_1_ = node,-,-,G,1;
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SM_AMIGA_0_ = node,-,-,G,8;
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SM_AMIGA_D_0_ = node,-,-,B,13;
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SM_AMIGA_D_1_ = node,-,-,B,9;
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SM_AMIGA_D_2_ = node,-,-,G,2;
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un1_UDS_000_INT_0_sqmuxa_2_0 = node,-,-,D,10;
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[GROUP ASSIGNMENTS]
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Layer = OFF;
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[RESOURCE RESERVATIONS]
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Layer = OFF;
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[SLEWRATE]
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Default = FAST;
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[PULLUP]
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Default = Up;
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[NETLIST/DELAY FORMAT]
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Delay_File = SDF;
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Netlist = VHDL;
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[OSM BYPASS]
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[FITTER REPORT FORMAT]
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Fitter_Options = Yes;
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Pinout_Diagram = No;
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Pinout_Listing = Yes;
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Detailed_Block_Segment_Summary = Yes;
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Input_Signal_List = Yes;
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Output_Signal_List = Yes;
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Bidir_Signal_List = Yes;
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Node_Signal_List = Yes;
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Signal_Fanout_List = Yes;
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Block_Segment_Fanin_List = Yes;
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Postfit_Eqn = Yes;
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Prefit_Eqn = Yes;
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Page_Break = Yes;
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[POWER]
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Powerlevel = Low,High;
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Default = High;
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Type = GLB;
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[SOURCE CONSTRAINT OPTION]
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[TIMING ANALYZER]
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Last_source=;
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Last_source_type=Fmax;
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