mirror of https://github.com/kr239/68030tk.git
90 lines
4.5 KiB
Tal
90 lines
4.5 KiB
Tal
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Design Name = 68030_tk.tt4
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~~~~~~~~~~~~~~~~~~~~~~~~~~
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*******************
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* TIMING ANALYSIS *
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*******************
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Timing Analysis KEY:
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One unit of delay time is equivalent to one pass
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through the Central Switch Matrix.
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.. Delay ( in this column ) not applicable to the indicated signal.
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TSU, Set-Up Time ( 0 for input-paired signals ),
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represents the number of switch matrix passes between
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an input pin and a register setup before clock.
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TSU is reported on the register.
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TCO, Clocked Output-to-Pin Time ( 0 for output-paired signals ),
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represents the number of switch matrix passes between
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a clocked register and an output pin.
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TCO is reported on the register.
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TPD, Propagation Delay Time ( calculated only for combinatorial eqns.),
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represents the number of switch matrix passes between
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an input pin and an output pin.
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TPD is reported on the output pin.
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TCR, Clocked Output-to-Register Time,
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represents the number of switch matrix passes between
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a clocked register and the register it drives ( before clock ).
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TCR is reported on the driving register.
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TSU TCO TPD TCR
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#passes #passes #passes #passes
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SIGNAL NAME min max min max min max min max
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LDS_000 1 2 0 0 .. .. 1 1
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RN_LDS_000 1 2 0 0 .. .. 1 1
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inst_AS_030_000_SYNC 1 1 .. .. .. .. 1 2
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inst_CLK_000_D 1 1 .. .. .. .. 1 2
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SM_AMIGA_6_ .. .. 1 1 .. .. 1 2
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SM_AMIGA_4_ .. .. 1 1 .. .. 1 2
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SM_AMIGA_5_ .. .. 1 1 .. .. 1 2
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AMIGA_BUS_DATA_DIR .. .. .. .. 1 1 .. ..
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CIIN .. .. .. .. 1 1 .. ..
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IPL_030_2_ 1 1 0 0 .. .. 1 1
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RN_IPL_030_2_ 1 1 0 0 .. .. 1 1
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DSACK_1_ 1 1 0 0 .. .. 1 1
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RN_DSACK_1_ 1 1 0 0 .. .. 1 1
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AS_000 1 1 0 0 .. .. 1 1
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RN_AS_000 1 1 0 0 .. .. 1 1
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UDS_000 1 1 0 0 .. .. 1 1
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RN_UDS_000 1 1 0 0 .. .. 1 1
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BG_000 1 1 0 0 .. .. 1 1
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RN_BG_000 1 1 0 0 .. .. 1 1
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BGACK_030 1 1 0 0 .. .. 1 1
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RN_BGACK_030 1 1 0 0 .. .. 1 1
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FPU_CS 1 1 0 0 .. .. 1 1
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RN_FPU_CS 1 1 0 0 .. .. 1 1
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DTACK 1 1 0 0 .. .. .. ..
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IPL_030_1_ 1 1 0 0 .. .. 1 1
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RN_IPL_030_1_ 1 1 0 0 .. .. 1 1
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IPL_030_0_ 1 1 0 0 .. .. 1 1
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RN_IPL_030_0_ 1 1 0 0 .. .. 1 1
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E .. .. 0 0 .. .. 1 1
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RN_E .. .. 0 0 .. .. 1 1
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VMA .. .. 0 0 .. .. 1 1
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RN_VMA .. .. 0 0 .. .. 1 1
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RESET 1 1 0 0 .. .. .. ..
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cpu_est_1_ .. .. .. .. .. .. 1 1
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inst_DTACK_SYNC 1 1 .. .. .. .. 1 1
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inst_VPA_D 1 1 .. .. .. .. 1 1
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inst_VPA_SYNC 1 1 .. .. .. .. 1 1
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inst_CLK_000_DD .. .. .. .. .. .. 1 1
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inst_CLK_OUT_PRE .. .. .. .. .. .. 1 1
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cpu_est_0_ .. .. .. .. .. .. 1 1
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cpu_est_2_ .. .. .. .. .. .. 1 1
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CLK_CNT_0_ .. .. .. .. .. .. 1 1
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SM_AMIGA_7_ .. .. .. .. .. .. 1 1
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inst_RISING_CLK_AMIGA 1 1 .. .. .. .. 1 1
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SM_AMIGA_3_ .. .. 1 1 .. .. 1 1
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CLK_000_CNT_0_ 1 1 .. .. .. .. 1 1
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CLK_000_CNT_1_ 1 1 .. .. .. .. 1 1
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CLK_000_CNT_2_ 1 1 .. .. .. .. 1 1
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CLK_000_CNT_3_ 1 1 .. .. .. .. 1 1
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SM_AMIGA_2_ .. .. 1 1 .. .. 1 1
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SM_AMIGA_1_ 1 1 1 1 .. .. 1 1
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SM_AMIGA_0_ 1 1 1 1 .. .. 1 1
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SM_AMIGA_D_0_ 1 1 1 1 .. .. .. ..
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SM_AMIGA_D_1_ 1 1 1 1 .. .. .. ..
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SM_AMIGA_D_2_ 1 1 1 1 .. .. .. ..
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un1_UDS_000_INT_0_sqmuxa_2_0 .. .. .. .. 1 1 .. .. |