mirror of https://github.com/kr239/68030tk.git
217 lines
4.3 KiB
Plaintext
217 lines
4.3 KiB
Plaintext
[DEVICE]
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Family = M4A5;
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PartType = M4A5-128/64;
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Package = 100TQFP;
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PartNumber = M4A5-128/64-10VC;
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Speed = -10;
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Operating_condition = COM;
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EN_Segment = No;
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Pin_MC_1to1 = No;
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EN_PinReserve_IO = Yes;
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EN_PinReserve_BIDIR = Yes;
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Voltage = 5.0;
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[REVISION]
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RCS = "$Revision: 1.2 $";
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Parent = m4a5.lci;
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SDS_File = m4a5.sds;
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DATE = 05/15/2014;
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TIME = 12:30:11;
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Source_Format = Pure_VHDL;
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Type = TT2;
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Pre_Fit_Time = 1;
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[IGNORE ASSIGNMENTS]
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Pin_Assignments = No;
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Pin_Keep_Block = No;
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Pin_Keep_Segment = No;
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Group_Assignments = No;
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Macrocell_Assignments = No;
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Macrocell_Keep_Block = No;
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Macrocell_Keep_Segment = No;
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Pin_Reservation = No;
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Block_Reservation = No;
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Segment_Reservation = No;
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Timing_Constraints = No;
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[CLEAR ASSIGNMENTS]
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Pin_Assignments = No;
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Pin_Keep_Block = No;
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Pin_Keep_Segment = No;
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Group_Assignments = No;
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Macrocell_Assignments = No;
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Macrocell_Keep_Block = No;
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Macrocell_Keep_Segment = No;
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Pin_Reservation = No;
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Block_Reservation = No;
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Segment_Reservation = No;
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Timing_Constraints = No;
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[BACKANNOTATE ASSIGNMENTS]
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Pin_Block = No;
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Pin_Macrocell_Block = No;
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Routing = No;
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[GLOBAL PROJECT OPTIMIZATION]
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Balanced_Partitioning = Yes;
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Spread_Placement = Yes;
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Max_Pin_Percent = 100;
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Max_Macrocell_Percent = 100;
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Max_Blk_In_Percent = 100;
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[OPTIMIZATION OPTIONS]
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Logic_Reduction = Yes;
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Max_PTerm_Split = 16;
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Max_PTerm_Collapse = 16;
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XOR_Synthesis = Yes;
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EN_XOR_Synthesis = Yes;
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XOR_Gate = Yes;
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Node_Collapse = Yes;
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Keep_XOR = Yes;
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DT_Synthesis = Yes;
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Clock_PTerm = Min;
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Reset_PTerm = On;
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Preset_PTerm = On;
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Clock_Enable_PTerm = On;
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Output_Enable_PTerm = On;
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EN_DT_Synthesis = Yes;
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Cluster_PTerm = 5;
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FF_inv = No;
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EN_Use_CE = No;
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Use_CE = No;
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Use_Internal_COM_FB = Yes;
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EN_use_Internal_COM_FB = Yes;
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Set_Reset_Swap = No;
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EN_Set_Reset_Swap = No;
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Density = No;
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DeMorgan = Yes;
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T_FF = Yes;
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Max_Symbols = 32;
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[FITTER GLOBAL OPTIONS]
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Run_Time = 0;
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Set_Reset_Dont_Care = No;
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EN_Set_Reset_Dont_Care = Yes;
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In_Reg_Optimize = Yes;
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EN_In_Reg_Optimize = No;
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Clock_Optimize = No;
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Global_Clock_As_Pterm = No;
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Show_Iterations = No;
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Routing_Attempts = 2;
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Conf_Unused_IOs = Out_Low;
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[HARDWARE DEVICE OPTIONS]
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Zero_Hold_Time = Yes;
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Signature_Word = 0;
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Pull_up = Yes;
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Out_Slew_Rate = FAST,SLOW,0;
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Device_max_fanin = 33;
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Device_max_pterms = 20;
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Usercode_Format = Hex;
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[PIN RESERVATIONS]
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Layer = OFF;
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[LOCATION ASSIGNMENT]
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Layer = OFF;
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AS_030 = input,82,H,-;
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A_0_ = input,69,G,-;
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A_16_ = input,96,A,-;
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A_17_ = input,59,F,-;
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A_18_ = input,95,A,-;
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A_19_ = input,97,A,-;
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BGACK_000 = input,28,D,-;
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BG_030 = input,21,C,-;
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CLK_000 = input,11,-,-;
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CLK_030 = input,64,-,-;
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CLK_OSZI = input,61,-,-;
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CPU_SPACE = input,14,-,-;
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FC_0_ = input,57,F,-;
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FC_1_ = input,58,F,-;
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IPL_0_ = input,67,G,-;
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IPL_1_ = input,56,F,-;
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IPL_2_ = input,68,G,-;
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RST = input,86,-,-;
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RW = input,71,G,-;
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SIZE_1_ = input,79,H,-;
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SIZE_0_ = input,70,G,-;
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VPA = input,36,-,-;
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AVEC = input,92,A,-;
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BGACK_030 = input,83,H,-;
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BG_000 = input,29,D,-;
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CLK_DIV_OUT = input,65,G,-;
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CLK_EXP = input,10,B,-;
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DSACK_0_ = input,80,H,-;
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E = input,66,G,-;
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FPU_CS = input,78,H,-;
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IPL_030_0_ = input,8,B,-;
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IPL_030_1_ = input,7,B,-;
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IPL_030_2_ = input,9,B,-;
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LDS_000 = input,31,D,-;
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UDS_000 = input,32,D,-;
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VMA = input,35,D,-;
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AS_000 = input,33,D,-;
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DSACK_1_ = input,81,H,-;
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DTACK = input,30,D,-;
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RESET = input,3,B,-;
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AMIGA_BUS_DATA_DIR = input,48,E,-;
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AMIGA_BUS_ENABLE = input,34,D,-;
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AMIGA_BUS_ENABLE_LOW = input,20,C,-;
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CIIN = input,47,E,-;
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A_20_ = input,93,A,-;
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A_21_ = input,94,A,-;
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A_22_ = input,85,H,-;
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A_23_ = input,84,H,-;
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A_24_ = input,19,C,-;
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A_25_ = input,18,C,-;
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A_26_ = input,17,C,-;
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A_27_ = input,16,C,-;
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A_28_ = input,15,C,-;
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A_29_ = input,6,B,-;
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A_30_ = input,5,B,-;
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A_31_ = input,4,B,-;
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DS_030 = input,98,A,-;
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AVEC_EXP = input,22,C,-;
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BERR = input,41,E,-;
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[GROUP ASSIGNMENT]
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Layer = OFF;
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[SPACE RESERVATIONS]
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Layer = OFF;
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[BACKANNOTATE NETLIST]
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Delay_File = SDF;
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Netlist = VHDL;
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VCC_GND = Cell;
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[FITTER REPORT FORMAT]
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Fitter_Options = Yes;
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Pinout_Diagram = No;
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Pinout_Listing = Yes;
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Detailed_Block_Segment_Summary = Yes;
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Input_Signal_List = Yes;
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Output_Signal_List = Yes;
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Bidir_Signal_List = Yes;
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Node_Signal_List = Yes;
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Signal_Fanout_List = Yes;
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Block_Segment_Fanin_List = Yes;
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Postfit_Eqn = Yes;
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Page_Break = Yes;
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[POWER]
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Powerlevel = Low,High;
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Default = High;
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Type = GLB;
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[SOURCE CONSTRAINT OPTION]
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Import_source_constraint = Yes;
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Disable_warning_message = No;
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[TIMING ANALYZER]
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Last_source=;
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Last_source_type=Fmax;
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[INPUT REGISTERS]
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