mirror of https://github.com/kr239/68030tk.git
977 lines
23 KiB
Plaintext
977 lines
23 KiB
Plaintext
EDIF2BLIF version IspLever 1.0 Linked Equations File
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Copyright(C), 1992-2013, Lattice Semiconductor Corp.
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All Rights Reserved.
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Design bus68030 created Thu Apr 24 11:58:27 2014
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P-Terms Fan-in Fan-out Type Name (attributes)
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--------- ------ ------- ---- -----------------
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1/1 1 1 Pin IPL_030_2_
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1/1 1 1 Pin DSACK_1_
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1/1 1 1 Pin DSACK_1_.OE
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1/1 1 1 Pin AS_000
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1/1 1 1 Pin AS_000.OE
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1/1 1 1 Pin UDS_000
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1/1 1 1 Pin UDS_000.OE
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1/1 1 1 Pin LDS_000
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1/1 1 1 Pin LDS_000.OE
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1/1 1 1 Pin BERR
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1/1 1 1 Pin BERR.OE
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1/1 1 1 Pin BG_000
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1/1 1 1 Pin BGACK_030
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1/1 1 1 Pin CLK_DIV_OUT
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1/1 1 1 Pin CLK_EXP
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1/1 1 1 Pin FPU_CS
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1/1 1 1 Pin DTACK
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1/1 1 1 Pin DTACK.OE
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1/1 1 1 Pin AVEC
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1/1 1 1 Pin E
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1/1 1 1 Pin VMA
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1/1 1 1 Pin IPL_030_1_
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1/1 1 1 Pin IPL_030_0_
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1/1 1 1 Pin DSACK_0_
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1/1 1 1 Pin DSACK_0_.OE
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1 2 1 Node N_41_1
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1 2 1 Node N_40_1
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1 1 1 Node vma_int_0_un3_n
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1 2 1 Node vma_int_0_un1_n
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1 2 1 Node vma_int_0_un0_n
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1 1 1 Node uds_000_int_0_un3_n
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1 2 1 Node uds_000_int_0_un1_n
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1 2 1 Node uds_000_int_0_un0_n
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1 1 1 Node cpu_est_3_reg.D
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1/1 1 1 Node cpu_est_3_reg.C
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1 1 1 Node lds_000_int_0_un3_n
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2 2 1 Node inst_VMA_INTreg.D
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1/1 1 1 Node inst_VMA_INTreg.C
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1 2 1 Node lds_000_int_0_un1_n
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1/1 1 1 Node cpu_est_0_.D
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1/1 1 1 Node cpu_est_0_.C
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1 2 1 Node lds_000_int_0_un0_n
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1 1 1 Node cpu_est_1_.D
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1/1 1 1 Node cpu_est_1_.C
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1/1 1 1 Node a_23__n
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1/1 1 1 Node inst_AS_000_INT_D.D
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1/1 1 1 Node inst_AS_000_INT_D.AP
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1/1 1 1 Node inst_AS_000_INT_D.C
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1/1 1 1 Node inst_AS_000_INT_DD.D
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1/1 1 1 Node inst_AS_000_INT_DD.AP
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1/1 1 1 Node inst_AS_000_INT_DD.C
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1/1 1 1 Node a_22__n
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1 2 1 Node inst_AS_030_AMIGA_ENABLE.D
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1/1 1 1 Node inst_AS_030_AMIGA_ENABLE.AP
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1/1 1 1 Node inst_AS_030_AMIGA_ENABLE.C
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1 0 1 Node vcc_n_n
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1/1 1 1 Node a_21__n
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0 0 1 Node gnd_n_n
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1 2 1 Node cpu_est_2_.D
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1/1 1 1 Node cpu_est_2_.C
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1/1 1 1 Node a_20__n
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1/1 1 1 Node inst_AS_030_delay.D
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1/1 1 1 Node inst_AS_030_delay.AP
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1/1 1 1 Node inst_AS_030_delay.C
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1 2 1 Node DSACK_INT_1_.D
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1/1 1 1 Node DSACK_INT_1_.AP
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1/1 1 1 Node DSACK_INT_1_.C
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1/1 1 1 Node a_15__n
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1 1 1 Node un1_as_000_int2
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1/1 1 1 Node a_14__n
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1 2 1 Node un22_fpu_cs_int
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1 1 1 Node inst_AS_000_INT.D
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1/1 1 1 Node inst_AS_000_INT.AP
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1/1 1 1 Node inst_AS_000_INT.C
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1/1 1 1 Node a_13__n
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1 1 1 Node un1_as_000_int2_1
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1/1 1 1 Node a_12__n
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1 2 1 Node UDS_000_INT_1_sqmuxa
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2 2 1 Node inst_LDS_000_INTreg.D
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1/1 1 1 Node inst_LDS_000_INTreg.AP
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1/1 1 1 Node inst_LDS_000_INTreg.C
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1/1 1 1 Node a_11__n
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2 2 1 Node inst_UDS_000_INTreg.D
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1/1 1 1 Node inst_UDS_000_INTreg.AP
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1/1 1 1 Node inst_UDS_000_INTreg.C
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1 2 1 Node un1_dtack_int
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1/1 1 1 Node a_10__n
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1/1 1 1 Node a_9__n
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1/1 1 1 Node a_8__n
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1 1 1 Node un5_lds_logic
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1/1 1 1 Node a_7__n
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1 1 1 Node N_11
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1 1 1 Node N_22
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1/1 1 1 Node a_6__n
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1 1 1 Node N_32
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1 1 1 Node N_33
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1/1 1 1 Node a_5__n
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1 2 1 Node N_48
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1 2 1 Node N_39
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1/1 1 1 Node a_4__n
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1 2 1 Node N_40
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1 2 1 Node N_41
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1/1 1 1 Node a_3__n
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1 2 1 Node N_42
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1 2 1 Node N_43
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1/1 1 1 Node a_2__n
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1 2 1 Node N_44
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1 2 1 Node N_45
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1/1 1 1 Node a_1__n
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1 2 1 Node N_46
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1 2 1 Node N_51
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1/1 1 1 Node d_31__n
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1 2 1 Node N_52
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1 2 1 Node N_53
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1/1 1 1 Node d_30__n
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1 2 1 Node N_55
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1 2 1 Node N_57
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1/1 1 1 Node d_29__n
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1 1 1 Node N_69
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1 1 1 Node un22_fpu_cs_int_i
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1/1 1 1 Node d_28__n
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1 1 1 Node AS_000_i
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1 1 1 Node VPA_i
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1 1 1 Node cpu_est_i_0__n
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1 1 1 Node AS_030_i
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1 1 1 Node cpu_est_i_1__n
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1 1 1 Node cpu_est_i_2__n
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1 1 1 Node cpu_est_i_3__n
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1 1 1 Node VMA_INT_i
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1 1 1 Node AS_000_INT_DD_i
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1 1 1 Node DTACK_i
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1 1 1 Node dsack_i_1__n
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1 1 1 Node RW_i
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1 1 1 Node BGACK_000_i
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1 1 1 Node a_i_18__n
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1 1 1 Node a_i_19__n
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1 1 1 Node a_i_16__n
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1 1 1 Node a_i_30__n
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1 1 1 Node a_i_31__n
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1 1 1 Node a_i_28__n
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1 1 1 Node a_i_29__n
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1 1 1 Node a_i_26__n
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1 1 1 Node a_i_27__n
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1 1 1 Node a_i_24__n
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1 1 1 Node a_i_25__n
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1 1 1 Node CLK_030_i
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1 1 1 Node RST_i
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1 1 1 Node N_48_i
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1 1 1 Node CLK_000_i
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1 1 1 Node un1_dtack_int_i
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1/1 1 1 Node AS_030_c
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1/1 1 1 Node AS_000_c
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1/1 1 1 Node size_c_0__n
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1/1 1 1 Node size_c_1__n
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1/1 1 1 Node a_c_0__n
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1/1 1 1 Node a_c_16__n
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1/1 1 1 Node a_c_17__n
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1/1 1 1 Node a_c_18__n
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1/1 1 1 Node a_c_19__n
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1/1 1 1 Node a_c_24__n
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1/1 1 1 Node a_c_25__n
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1/1 1 1 Node a_c_26__n
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1/1 1 1 Node a_c_27__n
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1/1 1 1 Node a_c_28__n
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1/1 1 1 Node a_c_29__n
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1/1 1 1 Node a_c_30__n
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1/1 1 1 Node a_c_31__n
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1/1 1 1 Node CPU_SPACE_c
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1 1 1 Node BG_000DFFSHreg.D
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1/1 1 1 Node BG_000DFFSHreg.AP
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1/1 1 1 Node BG_000DFFSHreg.C
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1/1 1 1 Node BGACK_000_c
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1/1 1 1 Node CLK_030_c
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1/1 1 1 Node CLK_000_c
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1 1 1 Node CLK_OUT_INTreg.D
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1/1 1 1 Node CLK_OUT_INTreg.C
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1/1 1 1 Node IPL_030DFF_0_reg.D
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1/1 1 1 Node IPL_030DFF_0_reg.C
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1/1 1 1 Node IPL_030DFF_1_reg.D
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1/1 1 1 Node IPL_030DFF_1_reg.C
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1/1 1 1 Node IPL_030DFF_2_reg.D
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1/1 1 1 Node IPL_030DFF_2_reg.C
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1/1 1 1 Node dsack_c_1__n
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1/1 1 1 Node DTACK_c
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1/1 1 1 Node VPA_c
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1/1 1 1 Node RST_c
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1/1 1 1 Node RW_c
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1/1 1 1 Node fc_c_0__n
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1/1 1 1 Node fc_c_1__n
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1 2 1 Node N_70
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1 2 1 Node cpu_est_11_0_1__n
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1 1 1 Node N_46_i
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1 1 1 Node N_55_i
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1 1 1 Node N_44_i
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1 1 1 Node N_45_i
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1 2 1 Node N_33_i
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1 2 1 Node N_32_i
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1 2 1 Node N_22_i
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1 1 1 Node N_51_i
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1 1 1 Node N_52_i
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1 1 1 Node N_53_i
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1 2 1 Node cpu_est_11_0_3__n
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1 1 1 Node N_42_i
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1 1 1 Node N_43_i
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1 1 1 Node N_40_i
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1 1 1 Node N_41_i
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1 1 1 Node N_39_i
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1 1 1 Node N_57_i
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1 2 1 Node N_11_0
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1 2 1 Node bg_amiga_un1_as_030_0_n
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1 2 1 Node N_47_i
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1 2 1 Node un5_lds_logic_i
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1 1 1 Node a_c_i_0__n
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1 1 1 Node size_c_i_1__n
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1 2 1 Node un1_as_000_int2_1_0
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1 2 1 Node un1_as_000_int2_0
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1 1 1 Node N_70_i
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1 2 1 Node N_69_i
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1 2 1 Node un22_fpu_cs_int_1
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1 2 1 Node un22_fpu_cs_int_2
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1 2 1 Node un22_fpu_cs_int_3
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1 2 1 Node un22_fpu_cs_int_4
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1 2 1 Node un22_fpu_cs_int_5
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1 2 1 Node UDS_000_INT_1_sqmuxa_1
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1 2 1 Node un5_lds_logic_i_1
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1 2 1 Node cpu_est_11_0_1_1__n
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1 2 1 Node cpu_est_11_0_2_1__n
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1 2 1 Node as_edge_un11_as_030_ne_1_n
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1 2 1 Node as_edge_un11_as_030_ne_2_n
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1 2 1 Node as_edge_un11_as_030_ne_3_n
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1 2 1 Node as_edge_un11_as_030_ne_4_n
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1 2 1 Node as_edge_un11_as_030_ne_5_n
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1 2 1 Node as_edge_un11_as_030_ne_6_n
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1 2 1 Node as_edge_un11_as_030_ne_7_n
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1 2 1 Node as_edge_un11_as_030_ne_8_n
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1 2 1 Node as_edge_un11_as_030_ne_9_n
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1 2 1 Node N_39_1
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1 2 1 Node N_39_2
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1 2 1 Node N_39_3
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1 2 1 Node cpu_est_11_0_1_3__n
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1 2 1 Node N_15_i_1
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1 2 1 Node N_53_1
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1 2 1 Node N_43_1
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1 2 1 Node N_42_1
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=========
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246/110 Best P-Term Total: 246
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Total Pins: 74
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Total Nodes: 192
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Average P-Term/Output: 1
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Equations:
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IPL_030_2_ = (IPL_030DFF_2_reg);
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DSACK_1_ = (DSACK_INT_1_);
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DSACK_1_.OE = (CPU_SPACE_c);
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AS_000 = (inst_AS_000_INT);
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AS_000.OE = (N_69_i);
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UDS_000 = (inst_UDS_000_INTreg);
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UDS_000.OE = (N_69_i);
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LDS_000 = (inst_LDS_000_INTreg);
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LDS_000.OE = (N_69_i);
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BERR = (gnd_n_n);
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BERR.OE = (un22_fpu_cs_int);
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BG_000 = (BG_000DFFSHreg);
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BGACK_030 = (N_69_i);
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CLK_DIV_OUT = (CLK_OUT_INTreg);
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CLK_EXP = (CLK_OUT_INTreg);
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FPU_CS = (un22_fpu_cs_int_i);
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DTACK = (un1_dtack_int_i);
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DTACK.OE = (N_69);
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AVEC = (N_47_i);
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E = (cpu_est_3_reg);
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VMA = (inst_VMA_INTreg);
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IPL_030_1_ = (IPL_030DFF_1_reg);
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IPL_030_0_ = (IPL_030DFF_0_reg);
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DSACK_0_ = (vcc_n_n);
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DSACK_0_.OE = (CPU_SPACE_c);
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N_41_1 = (cpu_est_1_ & cpu_est_i_0__n);
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N_40_1 = (N_22 & cpu_est_0_);
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vma_int_0_un3_n = (!N_11);
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vma_int_0_un1_n = (cpu_est_3_reg & N_11);
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vma_int_0_un0_n = (inst_VMA_INTreg & vma_int_0_un3_n);
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uds_000_int_0_un3_n = (!UDS_000_INT_1_sqmuxa);
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uds_000_int_0_un1_n = (inst_UDS_000_INTreg & UDS_000_INT_1_sqmuxa);
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uds_000_int_0_un0_n = (un1_as_000_int2 & uds_000_int_0_un3_n);
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cpu_est_3_reg.D = (!cpu_est_11_0_3__n);
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cpu_est_3_reg.C = (CLK_000_i);
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lds_000_int_0_un3_n = (!UDS_000_INT_1_sqmuxa);
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inst_VMA_INTreg.D = (vma_int_0_un1_n
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# vma_int_0_un0_n);
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inst_VMA_INTreg.C = (CLK_000_i);
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lds_000_int_0_un1_n = (inst_LDS_000_INTreg & UDS_000_INT_1_sqmuxa);
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cpu_est_0_.D = (cpu_est_i_0__n);
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cpu_est_0_.C = (CLK_000_i);
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lds_000_int_0_un0_n = (un1_as_000_int2_1 & lds_000_int_0_un3_n);
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cpu_est_1_.D = (!cpu_est_11_0_1__n);
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cpu_est_1_.C = (CLK_000_i);
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a_23__n = (A_23_);
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inst_AS_000_INT_D.D = (inst_AS_000_INT);
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inst_AS_000_INT_D.AP = (N_48_i);
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inst_AS_000_INT_D.C = (CLK_000_c);
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inst_AS_000_INT_DD.D = (inst_AS_000_INT_D);
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inst_AS_000_INT_DD.AP = (N_48_i);
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inst_AS_000_INT_DD.C = (CLK_000_c);
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a_22__n = (A_22_);
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inst_AS_030_AMIGA_ENABLE.D = (as_edge_un11_as_030_ne_9_n & as_edge_un11_as_030_ne_8_n);
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inst_AS_030_AMIGA_ENABLE.AP = (RST_i);
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inst_AS_030_AMIGA_ENABLE.C = (CLK_030_i);
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vcc_n_n = (1);
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a_21__n = (A_21_);
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gnd_n_n = (0);
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cpu_est_2_.D = (N_40_i & N_41_i);
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cpu_est_2_.C = (CLK_000_i);
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a_20__n = (A_20_);
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inst_AS_030_delay.D = (AS_030_c);
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inst_AS_030_delay.AP = (RST_i);
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inst_AS_030_delay.C = (CLK_030_i);
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DSACK_INT_1_.D = (N_15_i_1 & N_43_i);
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DSACK_INT_1_.AP = (N_48_i);
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DSACK_INT_1_.C = (CLK_000_c);
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a_15__n = (A_15_);
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un1_as_000_int2 = (!un1_as_000_int2_0);
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a_14__n = (A_14_);
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un22_fpu_cs_int = (un22_fpu_cs_int_4 & un22_fpu_cs_int_5);
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inst_AS_000_INT.D = (!inst_AS_030_AMIGA_ENABLE);
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inst_AS_000_INT.AP = (N_48_i);
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inst_AS_000_INT.C = (CLK_000_c);
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a_13__n = (A_13_);
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un1_as_000_int2_1 = (!un1_as_000_int2_1_0);
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a_12__n = (A_12_);
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UDS_000_INT_1_sqmuxa = (UDS_000_INT_1_sqmuxa_1 & inst_AS_030_AMIGA_ENABLE);
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inst_LDS_000_INTreg.D = (lds_000_int_0_un1_n
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# lds_000_int_0_un0_n);
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inst_LDS_000_INTreg.AP = (N_48_i);
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inst_LDS_000_INTreg.C = (CLK_000_c);
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a_11__n = (A_11_);
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inst_UDS_000_INTreg.D = (uds_000_int_0_un1_n
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# uds_000_int_0_un0_n);
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inst_UDS_000_INTreg.AP = (N_48_i);
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inst_UDS_000_INTreg.C = (CLK_000_c);
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un1_dtack_int = (AS_000_i & dsack_i_1__n);
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a_10__n = (A_10_);
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a_9__n = (A_9_);
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a_8__n = (A_8_);
|
|
|
|
un5_lds_logic = (!un5_lds_logic_i);
|
|
|
|
a_7__n = (A_7_);
|
|
|
|
N_11 = (!N_11_0);
|
|
|
|
N_22 = (!N_22_i);
|
|
|
|
a_6__n = (A_6_);
|
|
|
|
N_32 = (!N_32_i);
|
|
|
|
N_33 = (!N_33_i);
|
|
|
|
a_5__n = (A_5_);
|
|
|
|
N_48 = (AS_030_i & RST_c);
|
|
|
|
N_39 = (N_39_3 & cpu_est_i_0__n);
|
|
|
|
a_4__n = (A_4_);
|
|
|
|
N_40 = (N_40_1 & cpu_est_i_3__n);
|
|
|
|
N_41 = (N_41_1 & cpu_est_i_2__n);
|
|
|
|
a_3__n = (A_3_);
|
|
|
|
N_42 = (N_42_1 & VPA_c);
|
|
|
|
N_43 = (N_43_1 & VPA_i);
|
|
|
|
a_2__n = (A_2_);
|
|
|
|
N_44 = (N_32 & cpu_est_i_0__n);
|
|
|
|
N_45 = (cpu_est_i_2__n & cpu_est_i_3__n);
|
|
|
|
a_1__n = (A_1_);
|
|
|
|
N_46 = (N_32_i & cpu_est_0_);
|
|
|
|
N_51 = (N_33 & cpu_est_3_reg);
|
|
|
|
d_31__n = (D_31_);
|
|
|
|
N_52 = (N_33_i & cpu_est_i_2__n);
|
|
|
|
N_53 = (N_53_1 & cpu_est_i_2__n);
|
|
|
|
d_30__n = (D_30_);
|
|
|
|
N_55 = (N_22_i & cpu_est_3_reg);
|
|
|
|
N_57 = (N_55 & cpu_est_0_);
|
|
|
|
d_29__n = (D_29_);
|
|
|
|
N_69 = (!N_69_i);
|
|
|
|
un22_fpu_cs_int_i = (!un22_fpu_cs_int);
|
|
|
|
d_28__n = (D_28_);
|
|
|
|
AS_000_i = (!AS_000_c);
|
|
|
|
VPA_i = (!VPA_c);
|
|
|
|
cpu_est_i_0__n = (!cpu_est_0_);
|
|
|
|
AS_030_i = (!AS_030_c);
|
|
|
|
cpu_est_i_1__n = (!cpu_est_1_);
|
|
|
|
cpu_est_i_2__n = (!cpu_est_2_);
|
|
|
|
cpu_est_i_3__n = (!cpu_est_3_reg);
|
|
|
|
VMA_INT_i = (!inst_VMA_INTreg);
|
|
|
|
AS_000_INT_DD_i = (!inst_AS_000_INT_DD);
|
|
|
|
DTACK_i = (!DTACK_c);
|
|
|
|
dsack_i_1__n = (!dsack_c_1__n);
|
|
|
|
RW_i = (!RW_c);
|
|
|
|
BGACK_000_i = (!BGACK_000_c);
|
|
|
|
a_i_18__n = (!a_c_18__n);
|
|
|
|
a_i_19__n = (!a_c_19__n);
|
|
|
|
a_i_16__n = (!a_c_16__n);
|
|
|
|
a_i_30__n = (!a_c_30__n);
|
|
|
|
a_i_31__n = (!a_c_31__n);
|
|
|
|
a_i_28__n = (!a_c_28__n);
|
|
|
|
a_i_29__n = (!a_c_29__n);
|
|
|
|
a_i_26__n = (!a_c_26__n);
|
|
|
|
a_i_27__n = (!a_c_27__n);
|
|
|
|
a_i_24__n = (!a_c_24__n);
|
|
|
|
a_i_25__n = (!a_c_25__n);
|
|
|
|
CLK_030_i = (!CLK_030_c);
|
|
|
|
RST_i = (!RST_c);
|
|
|
|
N_48_i = (!N_48);
|
|
|
|
CLK_000_i = (!CLK_000_c);
|
|
|
|
un1_dtack_int_i = (!un1_dtack_int);
|
|
|
|
AS_030_c = (AS_030);
|
|
|
|
AS_000_c = (AS_000.PIN);
|
|
|
|
size_c_0__n = (SIZE_0_);
|
|
|
|
size_c_1__n = (SIZE_1_);
|
|
|
|
a_c_0__n = (A_0_);
|
|
|
|
a_c_16__n = (A_16_);
|
|
|
|
a_c_17__n = (A_17_);
|
|
|
|
a_c_18__n = (A_18_);
|
|
|
|
a_c_19__n = (A_19_);
|
|
|
|
a_c_24__n = (A_24_);
|
|
|
|
a_c_25__n = (A_25_);
|
|
|
|
a_c_26__n = (A_26_);
|
|
|
|
a_c_27__n = (A_27_);
|
|
|
|
a_c_28__n = (A_28_);
|
|
|
|
a_c_29__n = (A_29_);
|
|
|
|
a_c_30__n = (A_30_);
|
|
|
|
a_c_31__n = (A_31_);
|
|
|
|
CPU_SPACE_c = (CPU_SPACE);
|
|
|
|
BG_000DFFSHreg.D = (!bg_amiga_un1_as_030_0_n);
|
|
|
|
BG_000DFFSHreg.AP = (BG_030);
|
|
|
|
BG_000DFFSHreg.C = (CLK_000_i);
|
|
|
|
BGACK_000_c = (BGACK_000);
|
|
|
|
CLK_030_c = (CLK_030);
|
|
|
|
CLK_000_c = (CLK_000);
|
|
|
|
CLK_OUT_INTreg.D = (!CLK_OUT_INTreg);
|
|
|
|
CLK_OUT_INTreg.C = (CLK_OSZI);
|
|
|
|
IPL_030DFF_0_reg.D = (IPL_0_);
|
|
|
|
IPL_030DFF_0_reg.C = (CLK_000_c);
|
|
|
|
IPL_030DFF_1_reg.D = (IPL_1_);
|
|
|
|
IPL_030DFF_1_reg.C = (CLK_000_c);
|
|
|
|
IPL_030DFF_2_reg.D = (IPL_2_);
|
|
|
|
IPL_030DFF_2_reg.C = (CLK_000_c);
|
|
|
|
dsack_c_1__n = (DSACK_1_.PIN);
|
|
|
|
DTACK_c = (DTACK.PIN);
|
|
|
|
VPA_c = (VPA);
|
|
|
|
RST_c = (RST);
|
|
|
|
RW_c = (RW);
|
|
|
|
fc_c_0__n = (FC_0_);
|
|
|
|
fc_c_1__n = (FC_1_);
|
|
|
|
N_70 = (CLK_000_i & N_69);
|
|
|
|
cpu_est_11_0_1__n = (cpu_est_11_0_1_1__n & cpu_est_11_0_2_1__n);
|
|
|
|
N_46_i = (!N_46);
|
|
|
|
N_55_i = (!N_55);
|
|
|
|
N_44_i = (!N_44);
|
|
|
|
N_45_i = (!N_45);
|
|
|
|
N_33_i = (cpu_est_0_ & cpu_est_1_);
|
|
|
|
N_32_i = (cpu_est_i_1__n & cpu_est_i_3__n);
|
|
|
|
N_22_i = (cpu_est_1_ & cpu_est_2_);
|
|
|
|
N_51_i = (!N_51);
|
|
|
|
N_52_i = (!N_52);
|
|
|
|
N_53_i = (!N_53);
|
|
|
|
cpu_est_11_0_3__n = (cpu_est_11_0_1_3__n & N_52_i);
|
|
|
|
N_42_i = (!N_42);
|
|
|
|
N_43_i = (!N_43);
|
|
|
|
N_40_i = (!N_40);
|
|
|
|
N_41_i = (!N_41);
|
|
|
|
N_39_i = (!N_39);
|
|
|
|
N_57_i = (!N_57);
|
|
|
|
N_11_0 = (N_39_i & N_57_i);
|
|
|
|
bg_amiga_un1_as_030_0_n = (AS_030_c & CPU_SPACE_c);
|
|
|
|
N_47_i = (CPU_SPACE_c & VPA_c);
|
|
|
|
un5_lds_logic_i = (un5_lds_logic_i_1 & size_c_0__n);
|
|
|
|
a_c_i_0__n = (!a_c_0__n);
|
|
|
|
size_c_i_1__n = (!size_c_1__n);
|
|
|
|
un1_as_000_int2_1_0 = (inst_AS_030_AMIGA_ENABLE & un5_lds_logic);
|
|
|
|
un1_as_000_int2_0 = (inst_AS_030_AMIGA_ENABLE & a_c_i_0__n);
|
|
|
|
N_70_i = (!N_70);
|
|
|
|
N_69_i = (BGACK_000_c & N_70_i);
|
|
|
|
un22_fpu_cs_int_1 = (a_c_17__n & a_i_16__n);
|
|
|
|
un22_fpu_cs_int_2 = (a_i_18__n & a_i_19__n);
|
|
|
|
un22_fpu_cs_int_3 = (fc_c_1__n & BGACK_000_i);
|
|
|
|
un22_fpu_cs_int_4 = (un22_fpu_cs_int_1 & un22_fpu_cs_int_2);
|
|
|
|
un22_fpu_cs_int_5 = (un22_fpu_cs_int_3 & fc_c_0__n);
|
|
|
|
UDS_000_INT_1_sqmuxa_1 = (RW_i & inst_AS_000_INT_D);
|
|
|
|
un5_lds_logic_i_1 = (size_c_i_1__n & a_c_i_0__n);
|
|
|
|
cpu_est_11_0_1_1__n = (N_44_i & N_45_i);
|
|
|
|
cpu_est_11_0_2_1__n = (N_46_i & N_55_i);
|
|
|
|
as_edge_un11_as_030_ne_1_n = (CPU_SPACE_c & a_i_30__n);
|
|
|
|
as_edge_un11_as_030_ne_2_n = (a_i_31__n & inst_AS_030_delay);
|
|
|
|
as_edge_un11_as_030_ne_3_n = (AS_030_i & a_i_24__n);
|
|
|
|
as_edge_un11_as_030_ne_4_n = (a_i_25__n & a_i_26__n);
|
|
|
|
as_edge_un11_as_030_ne_5_n = (a_i_27__n & a_i_28__n);
|
|
|
|
as_edge_un11_as_030_ne_6_n = (as_edge_un11_as_030_ne_1_n & as_edge_un11_as_030_ne_2_n);
|
|
|
|
as_edge_un11_as_030_ne_7_n = (as_edge_un11_as_030_ne_3_n & as_edge_un11_as_030_ne_4_n);
|
|
|
|
as_edge_un11_as_030_ne_8_n = (as_edge_un11_as_030_ne_5_n & a_i_29__n);
|
|
|
|
as_edge_un11_as_030_ne_9_n = (as_edge_un11_as_030_ne_6_n & as_edge_un11_as_030_ne_7_n);
|
|
|
|
N_39_1 = (AS_000_i & N_32_i);
|
|
|
|
N_39_2 = (VPA_i & cpu_est_2_);
|
|
|
|
N_39_3 = (N_39_1 & N_39_2);
|
|
|
|
cpu_est_11_0_1_3__n = (N_53_i & N_51_i);
|
|
|
|
N_15_i_1 = (DSACK_INT_1_ & N_42_i);
|
|
|
|
N_53_1 = (cpu_est_i_0__n & cpu_est_i_1__n);
|
|
|
|
N_43_1 = (N_57 & VMA_INT_i);
|
|
|
|
N_42_1 = (AS_000_INT_DD_i & DTACK_i);
|
|
|
|
|
|
Reverse-Polarity Equations:
|
|
|
|
!IPL_030_2_ = (!IPL_030DFF_2_reg);
|
|
|
|
!DSACK_1_ = (!DSACK_INT_1_);
|
|
|
|
!DSACK_1_.OE = (!CPU_SPACE_c);
|
|
|
|
!AS_000 = (!inst_AS_000_INT);
|
|
|
|
!AS_000.OE = (!N_69_i);
|
|
|
|
!UDS_000 = (!inst_UDS_000_INTreg);
|
|
|
|
!UDS_000.OE = (!N_69_i);
|
|
|
|
!LDS_000 = (!inst_LDS_000_INTreg);
|
|
|
|
!LDS_000.OE = (!N_69_i);
|
|
|
|
!BERR = (!gnd_n_n);
|
|
|
|
!BERR.OE = (!un22_fpu_cs_int);
|
|
|
|
!BG_000 = (!BG_000DFFSHreg);
|
|
|
|
!BGACK_030 = (!N_69_i);
|
|
|
|
!CLK_DIV_OUT = (!CLK_OUT_INTreg);
|
|
|
|
!CLK_EXP = (!CLK_OUT_INTreg);
|
|
|
|
!FPU_CS = (!un22_fpu_cs_int_i);
|
|
|
|
!DTACK = (!un1_dtack_int_i);
|
|
|
|
!DTACK.OE = (!N_69);
|
|
|
|
!AVEC = (!N_47_i);
|
|
|
|
!E = (!cpu_est_3_reg);
|
|
|
|
!VMA = (!inst_VMA_INTreg);
|
|
|
|
!IPL_030_1_ = (!IPL_030DFF_1_reg);
|
|
|
|
!IPL_030_0_ = (!IPL_030DFF_0_reg);
|
|
|
|
!DSACK_0_ = (!vcc_n_n);
|
|
|
|
!DSACK_0_.OE = (!CPU_SPACE_c);
|
|
|
|
!cpu_est_3_reg.C = (!CLK_000_i);
|
|
|
|
!inst_VMA_INTreg.C = (!CLK_000_i);
|
|
|
|
!cpu_est_0_.D = (!cpu_est_i_0__n);
|
|
|
|
!cpu_est_0_.C = (!CLK_000_i);
|
|
|
|
!cpu_est_1_.C = (!CLK_000_i);
|
|
|
|
!a_23__n = (!A_23_);
|
|
|
|
!inst_AS_000_INT_D.D = (!inst_AS_000_INT);
|
|
|
|
!inst_AS_000_INT_D.AP = (!N_48_i);
|
|
|
|
!inst_AS_000_INT_D.C = (!CLK_000_c);
|
|
|
|
!inst_AS_000_INT_DD.D = (!inst_AS_000_INT_D);
|
|
|
|
!inst_AS_000_INT_DD.AP = (!N_48_i);
|
|
|
|
!inst_AS_000_INT_DD.C = (!CLK_000_c);
|
|
|
|
!a_22__n = (!A_22_);
|
|
|
|
!inst_AS_030_AMIGA_ENABLE.AP = (!RST_i);
|
|
|
|
!inst_AS_030_AMIGA_ENABLE.C = (!CLK_030_i);
|
|
|
|
!a_21__n = (!A_21_);
|
|
|
|
!cpu_est_2_.C = (!CLK_000_i);
|
|
|
|
!a_20__n = (!A_20_);
|
|
|
|
!inst_AS_030_delay.D = (!AS_030_c);
|
|
|
|
!inst_AS_030_delay.AP = (!RST_i);
|
|
|
|
!inst_AS_030_delay.C = (!CLK_030_i);
|
|
|
|
!DSACK_INT_1_.AP = (!N_48_i);
|
|
|
|
!DSACK_INT_1_.C = (!CLK_000_c);
|
|
|
|
!a_15__n = (!A_15_);
|
|
|
|
!a_14__n = (!A_14_);
|
|
|
|
!inst_AS_000_INT.AP = (!N_48_i);
|
|
|
|
!inst_AS_000_INT.C = (!CLK_000_c);
|
|
|
|
!a_13__n = (!A_13_);
|
|
|
|
!a_12__n = (!A_12_);
|
|
|
|
!inst_LDS_000_INTreg.AP = (!N_48_i);
|
|
|
|
!inst_LDS_000_INTreg.C = (!CLK_000_c);
|
|
|
|
!a_11__n = (!A_11_);
|
|
|
|
!inst_UDS_000_INTreg.AP = (!N_48_i);
|
|
|
|
!inst_UDS_000_INTreg.C = (!CLK_000_c);
|
|
|
|
!a_10__n = (!A_10_);
|
|
|
|
!a_9__n = (!A_9_);
|
|
|
|
!a_8__n = (!A_8_);
|
|
|
|
!a_7__n = (!A_7_);
|
|
|
|
!a_6__n = (!A_6_);
|
|
|
|
!a_5__n = (!A_5_);
|
|
|
|
!a_4__n = (!A_4_);
|
|
|
|
!a_3__n = (!A_3_);
|
|
|
|
!a_2__n = (!A_2_);
|
|
|
|
!a_1__n = (!A_1_);
|
|
|
|
!d_31__n = (!D_31_);
|
|
|
|
!d_30__n = (!D_30_);
|
|
|
|
!d_29__n = (!D_29_);
|
|
|
|
!d_28__n = (!D_28_);
|
|
|
|
!AS_030_c = (!AS_030);
|
|
|
|
!AS_000_c = (!AS_000.PIN);
|
|
|
|
!size_c_0__n = (!SIZE_0_);
|
|
|
|
!size_c_1__n = (!SIZE_1_);
|
|
|
|
!a_c_0__n = (!A_0_);
|
|
|
|
!a_c_16__n = (!A_16_);
|
|
|
|
!a_c_17__n = (!A_17_);
|
|
|
|
!a_c_18__n = (!A_18_);
|
|
|
|
!a_c_19__n = (!A_19_);
|
|
|
|
!a_c_24__n = (!A_24_);
|
|
|
|
!a_c_25__n = (!A_25_);
|
|
|
|
!a_c_26__n = (!A_26_);
|
|
|
|
!a_c_27__n = (!A_27_);
|
|
|
|
!a_c_28__n = (!A_28_);
|
|
|
|
!a_c_29__n = (!A_29_);
|
|
|
|
!a_c_30__n = (!A_30_);
|
|
|
|
!a_c_31__n = (!A_31_);
|
|
|
|
!CPU_SPACE_c = (!CPU_SPACE);
|
|
|
|
!BG_000DFFSHreg.AP = (!BG_030);
|
|
|
|
!BG_000DFFSHreg.C = (!CLK_000_i);
|
|
|
|
!BGACK_000_c = (!BGACK_000);
|
|
|
|
!CLK_030_c = (!CLK_030);
|
|
|
|
!CLK_000_c = (!CLK_000);
|
|
|
|
!CLK_OUT_INTreg.C = (!CLK_OSZI);
|
|
|
|
!IPL_030DFF_0_reg.D = (!IPL_0_);
|
|
|
|
!IPL_030DFF_0_reg.C = (!CLK_000_c);
|
|
|
|
!IPL_030DFF_1_reg.D = (!IPL_1_);
|
|
|
|
!IPL_030DFF_1_reg.C = (!CLK_000_c);
|
|
|
|
!IPL_030DFF_2_reg.D = (!IPL_2_);
|
|
|
|
!IPL_030DFF_2_reg.C = (!CLK_000_c);
|
|
|
|
!dsack_c_1__n = (!DSACK_1_.PIN);
|
|
|
|
!DTACK_c = (!DTACK.PIN);
|
|
|
|
!VPA_c = (!VPA);
|
|
|
|
!RST_c = (!RST);
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!RW_c = (!RW);
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|
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!fc_c_0__n = (!FC_0_);
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!fc_c_1__n = (!FC_1_);
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|