mirror of https://github.com/kr239/68030tk.git
1762 lines
77 KiB
Plaintext
1762 lines
77 KiB
Plaintext
|--------------------------------------------|
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|- ispLEVER Fitter Report File -|
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|- Version 2.0.00.17.20.15 -|
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|- (c)Copyright, Lattice Semiconductor 2002 -|
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|--------------------------------------------|
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Project_Summary
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~~~~~~~~~~~~~~~
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Project Name : 68030_tk
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Project Path : C:\Users\Matze\Documents\GitHub\68030tk\Logic
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Project Fitted on : Fri Aug 19 00:39:40 2016
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Device : M4A5-128/64
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Package : 100TQFP
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Speed : -10
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Partnumber : M4A5-128/64-10VC
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Source Format : Pure_VHDL
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// Project '68030_tk' was Fitted Successfully! //
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Compilation_Times
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~~~~~~~~~~~~~~~~~
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Reading/DRC 0 sec
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Partition 0 sec
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Place 0 sec
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Route 0 sec
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Jedec/Report generation 0 sec
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--------
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Fitter 00:00:00
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Design_Summary
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~~~~~~~~~~~~~~
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Total Input Pins : 24
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Total Output Pins : 19
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Total Bidir I/O Pins : 18
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Total Flip-Flops : 64
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Total Product Terms : 222
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Total Reserved Pins : 0
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Total Reserved Blocks : 0
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Device_Resource_Summary
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~~~~~~~~~~~~~~~~~~~~~~~
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Total
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Available Used Available Utilization
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Dedicated Pins
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Input-Only Pins 2 2 0 --> 100%
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Clock/Input Pins 4 4 0 --> 100%
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I/O Pins 64 55 9 --> 85%
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Logic Macrocells 128 91 37 --> 71%
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Input Registers 64 0 64 --> 0%
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Unusable Macrocells .. 1 ..
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CSM Outputs/Total Block Inputs 264 215 49 --> 81%
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Logical Product Terms 640 226 414 --> 35%
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Product Term Clusters 128 53 75 --> 41%
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Blocks_Resource_Summary
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~~~~~~~~~~~~~~~~~~~~~~~
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# of PT
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I/O Inp Macrocells Macrocells logic clusters
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Fanin Pins Reg Used Unusable available PTs available Pwr
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---------------------------------------------------------------------------------
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Maximum 33 8 8 -- -- 16 80 16 -
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---------------------------------------------------------------------------------
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Block A 23 8 0 12 0 4 39 7 Lo
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Block B 25 8 0 12 1 3 44 8 Lo
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Block C 24 7 0 12 0 4 21 12 Lo
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Block D 25 8 0 12 0 4 25 8 Lo
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Block E 33 4 0 10 0 6 12 14 Lo
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Block F 25 5 0 10 0 6 43 5 Lo
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Block G 27 7 0 13 0 3 25 8 Lo
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Block H 33 8 0 9 0 7 17 13 Lo
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---------------------------------------------------------------------------------
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<Note> Four rightmost columns above reflect last status of the placement process.
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<Note> Pwr (Power) : Hi = High
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Lo = Low.
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Optimizer_and_Fitter_Options
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Pin Assignment : Yes
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Group Assignment : No
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Pin Reservation : No (1)
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Block Reservation : No
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@Ignore_Project_Constraints :
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Pin Assignments : No
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Keep Block Assignment --
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Keep Segment Assignment --
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Group Assignments : No
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Macrocell Assignment : No
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Keep Block Assignment --
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Keep Segment Assignment --
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@Backannotate_Project_Constraints
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Pin Assignments : No
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Pin And Block Assignments : No
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Pin, Macrocell and Block : No
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@Timing_Constraints : No
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@Global_Project_Optimization :
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Balanced Partitioning : Yes
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Spread Placement : Yes
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Note :
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Pack Design :
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Balanced Partitioning = No
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Spread Placement = No
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Spread Design :
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Balanced Partitioning = Yes
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Spread Placement = Yes
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@Logic_Synthesis :
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Logic Reduction : Yes
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Node Collapsing : Yes
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D/T Synthesis : Yes
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Clock Optimization : No
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Input Register Optimization : Yes
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XOR Synthesis : Yes
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Max. P-Term for Collapsing : 16
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Max. P-Term for Splitting : 16
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Max. Equation Fanin : 32
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Keep Xor : Yes
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@Utilization_options
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Max. % of macrocells used : 100
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Max. % of block inputs used : 100
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Max. % of segment lines used : ---
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Max. % of macrocells used : ---
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@Import_Source_Constraint_Option No
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@Zero_Hold_Time Yes
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@Pull_up Yes
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@User_Signature #H0
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@Output_Slew_Rate Default = Slow(2)
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@Power Default = High(2)
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Device Options:
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<Note> 1 : Reserved unused I/Os can be independently driven to Low or High, and does not
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follow the drive level set for the Global Configure Unused I/O Option.
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<Note> 2 : For user-specified constraints on individual signals, refer to the Output,
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Bidir and Burried Signal Lists.
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Pinout_Listing
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~~~~~~~~~~~~~~
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| Pin |Blk |Assigned|
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Pin No| Type |Pad |Pin | Signal name
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---------------------------------------------------------------
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1 | GND | | |
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2 | JTAG | | |
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3 | I_O | B7 | * |RESET
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4 | I_O | B6 | * |AHIGH_31_
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5 | I_O | B5 | * |AHIGH_30_
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6 | I_O | B4 | * |AHIGH_29_
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7 | I_O | B3 | * |IPL_030_1_
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8 | I_O | B2 | * |IPL_030_0_
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9 | I_O | B1 | * |IPL_030_2_
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10 | I_O | B0 | * |CLK_EXP
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11 | CkIn | | * |CLK_000
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12 | Vcc | | |
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13 | GND | | |
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14 | CkIn | | * |nEXP_SPACE
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15 | I_O | C0 | * |AHIGH_28_
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16 | I_O | C1 | * |AHIGH_27_
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17 | I_O | C2 | * |AHIGH_26_
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18 | I_O | C3 | * |AHIGH_25_
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19 | I_O | C4 | * |AHIGH_24_
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20 | I_O | C5 | * |AMIGA_BUS_ENABLE_LOW
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21 | I_O | C6 | * |BG_030
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22 | I_O | C7 | |
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23 | JTAG | | |
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24 | JTAG | | |
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25 | GND | | |
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26 | GND | | |
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27 | GND | | |
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28 | I_O | D7 | * |BGACK_000
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29 | I_O | D6 | * |BG_000
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30 | I_O | D5 | * |DTACK
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31 | I_O | D4 | * |LDS_000
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32 | I_O | D3 | * |UDS_000
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33 | I_O | D2 | * |AMIGA_ADDR_ENABLE
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34 | I_O | D1 | * |AMIGA_BUS_ENABLE_HIGH
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35 | I_O | D0 | * |VMA
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36 | Inp | | * |VPA
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37 | Vcc | | |
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38 | GND | | |
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39 | GND | | |
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40 | Vcc | | |
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41 | I_O | E0 | * |BERR
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42 | I_O | E1 | * |AS_000
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43 | I_O | E2 | |
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44 | I_O | E3 | |
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45 | I_O | E4 | |
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46 | I_O | E5 | |
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47 | I_O | E6 | * |CIIN
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48 | I_O | E7 | * |AMIGA_BUS_DATA_DIR
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49 | GND | | |
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50 | GND | | |
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51 | GND | | |
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52 | JTAG | | |
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53 | I_O | F7 | |
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54 | I_O | F6 | |
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55 | I_O | F5 | |
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56 | I_O | F4 | * |IPL_1_
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57 | I_O | F3 | * |FC_0_
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58 | I_O | F2 | * |FC_1_
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59 | I_O | F1 | * |A_DECODE_17_
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60 | I_O | F0 | * |A_1_
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61 | CkIn | | * |CLK_OSZI
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62 | Vcc | | |
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63 | GND | | |
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64 | CkIn | | * |CLK_030
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65 | I_O | G0 | * |CLK_DIV_OUT
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66 | I_O | G1 | * |E
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67 | I_O | G2 | * |IPL_0_
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68 | I_O | G3 | * |IPL_2_
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69 | I_O | G4 | * |A_0_
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70 | I_O | G5 | * |SIZE_0_
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71 | I_O | G6 | * |RW
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72 | I_O | G7 | |
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73 | JTAG | | |
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74 | JTAG | | |
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75 | GND | | |
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76 | GND | | |
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77 | GND | | |
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78 | I_O | H7 | * |FPU_CS
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79 | I_O | H6 | * |SIZE_1_
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80 | I_O | H5 | * |RW_000
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81 | I_O | H4 | * |DSACK1
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82 | I_O | H3 | * |AS_030
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83 | I_O | H2 | * |BGACK_030
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84 | I_O | H1 | * |A_DECODE_22_
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85 | I_O | H0 | * |A_DECODE_23_
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86 | Inp | | * |RST
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87 | Vcc | | |
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88 | GND | | |
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89 | GND | | |
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90 | Vcc | | |
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91 | I_O | A0 | * |FPU_SENSE
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92 | I_O | A1 | * |AVEC
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93 | I_O | A2 | * |A_DECODE_20_
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94 | I_O | A3 | * |A_DECODE_21_
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95 | I_O | A4 | * |A_DECODE_18_
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96 | I_O | A5 | * |A_DECODE_16_
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97 | I_O | A6 | * |A_DECODE_19_
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98 | I_O | A7 | * |DS_030
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99 | GND | | |
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100 | GND | | |
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---------------------------------------------------------------------------
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<Note> Blk Pad : This notation refers to the Block I/O pad number in the device.
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<Note> Assigned Pin : user or dedicated input assignment (E.g. Clock pins).
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<Note> Pin Type :
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CkIn : Dedicated input or clock pin
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CLK : Dedicated clock pin
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INP : Dedicated input pin
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JTAG : JTAG Control and test pin
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NC : No connected
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Input_Signal_List
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~~~~~~~~~~~~~~~~~
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P R
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Pin r e O Input
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Pin Blk PTs Type e s E Fanout Pwr Slew Signal
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----------------------------------------------------------------------
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60 F . I/O ------G- Low Slow A_1_
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96 A . I/O --C-E--H Low Slow A_DECODE_16_
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59 F . I/O --C-E--H Low Slow A_DECODE_17_
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95 A . I/O --C-E--H Low Slow A_DECODE_18_
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97 A . I/O --C-E--H Low Slow A_DECODE_19_
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93 A . I/O ----E--- Low Slow A_DECODE_20_
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94 A . I/O ----E--- Low Slow A_DECODE_21_
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84 H . I/O ----E--- Low Slow A_DECODE_22_
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85 H . I/O ----E--- Low Slow A_DECODE_23_
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28 D . I/O ----E--H Low Slow BGACK_000
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21 C . I/O ---D---- Low Slow BG_030
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30 D . I/O ------G- Low Slow DTACK
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57 F . I/O --C-E--H Low Slow FC_0_
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58 F . I/O --C-E--H Low Slow FC_1_
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91 A . I/O ----E--H Low Slow FPU_SENSE
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67 G . I/O -B------ Low Slow IPL_0_
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56 F . I/O -B------ Low Slow IPL_1_
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68 G . I/O AB------ Low Slow IPL_2_
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11 . . Ck/I --C----- - Slow CLK_000
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14 . . Ck/I ABCDEFGH - Slow nEXP_SPACE
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36 . . Ded -----F-- - Slow VPA
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61 . . Ck/I ABCDEFGH - Slow CLK_OSZI
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64 . . Ck/I A------H - Slow CLK_030
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86 . . Ded ABCD-FGH - Slow RST
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----------------------------------------------------------------------
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<Note> Power : Hi = High
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MH = Medium High
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ML = Medium Low
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Lo = Low
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Output_Signal_List
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~~~~~~~~~~~~~~~~~~
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P R
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Pin r e O Output
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Pin Blk PTs Type e s E Fanout Pwr Slew Signal
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----------------------------------------------------------------------
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33 D 1 COM -------- Low Fast AMIGA_ADDR_ENABLE
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48 E 2 COM -------- Low Fast AMIGA_BUS_DATA_DIR
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34 D 2 COM -------- Low Fast AMIGA_BUS_ENABLE_HIGH
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20 C 1 COM -------- Low Fast AMIGA_BUS_ENABLE_LOW
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92 A 1 COM -------- Low Slow AVEC
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83 H 3 DFF * * -------- Low Slow BGACK_030
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29 D 2 DFF * * -------- Low Slow BG_000
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47 E 1 COM -------- Low Slow CIIN
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65 G 1 DFF * * -------- Low Fast CLK_DIV_OUT
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10 B 1 DFF * * -------- Low Fast CLK_EXP
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81 H 4 DFF * * -------- Low Slow DSACK1
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98 A 1 COM -------- Low Slow DS_030
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66 G 2 COM -------- Low Slow E
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78 H 1 COM -------- Low Fast FPU_CS
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8 B 10 DFF * * -------- Low Slow IPL_030_0_
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7 B 10 DFF * * -------- Low Slow IPL_030_1_
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9 B 10 DFF * * -------- Low Slow IPL_030_2_
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3 B 1 COM -------- Low Slow RESET
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35 D 3 TFF * * -------- Low Slow VMA
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----------------------------------------------------------------------
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<Note> Power : Hi = High
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MH = Medium High
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ML = Medium Low
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Lo = Low
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Bidir_Signal_List
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~~~~~~~~~~~~~~~~~
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P R
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Pin r e O Bidir
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Pin Blk PTs Type e s E Fanout Pwr Slew Signal
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----------------------------------------------------------------------
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19 C 1 COM ----E--- Low Slow AHIGH_24_
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18 C 1 COM ----E--- Low Slow AHIGH_25_
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17 C 1 COM ----E--- Low Slow AHIGH_26_
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16 C 1 COM ----E--- Low Slow AHIGH_27_
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15 C 1 COM ----E--- Low Slow AHIGH_28_
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6 B 1 COM ----E--- Low Slow AHIGH_29_
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5 B 1 COM ----E--- Low Slow AHIGH_30_
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4 B 1 COM ----E--- Low Slow AHIGH_31_
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42 E 1 COM A---E--H Low Slow AS_000
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82 H 1 COM A---E--H Low Slow AS_030
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69 G 3 DFF * * ---D---- Low Slow A_0_
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41 E 1 COM -BC--FGH Low Slow BERR
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31 D 1 COM A-----G- Low Slow LDS_000
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71 G 2 DFF * * -B-----H Low Slow RW
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80 H 4 DFF * * A---E-G- Low Slow RW_000
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70 G 1 COM ---D---- Low Slow SIZE_0_
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79 H 1 COM ---D---- Low Slow SIZE_1_
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32 D 1 COM A-----G- Low Slow UDS_000
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----------------------------------------------------------------------
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<Note> Power : Hi = High
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MH = Medium High
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ML = Medium Low
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Lo = Low
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Buried_Signal_List
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~~~~~~~~~~~~~~~~~~
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P R
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Pin r e O Node
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#Mc Blk PTs Type e s E Fanout Pwr Slew Signal
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----------------------------------------------------------------------
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E10 E 2 COM ----E--- Low Slow CIIN_0
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C13 C 1 DFF * * ABCD-FGH Low Slow CLK_000_D_0_
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C14 C 1 DFF * * -------H Low Slow CLK_000_D_10_
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H0 H 1 DFF * * ------GH Low Slow CLK_000_D_11_
|
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G14 G 1 DFF * * -------H Low Slow CLK_000_D_12_
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H3 H 1 DFF * * ABCDEFGH Low Slow CLK_000_D_1_
|
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E2 E 1 DFF * * --C-EF-- Low Slow CLK_000_D_2_
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E9 E 1 DFF * * --C----- Low Slow CLK_000_D_3_
|
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C11 C 1 DFF * * ----E--- Low Slow CLK_000_D_4_
|
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E5 E 1 DFF * * ---D---- Low Slow CLK_000_D_5_
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D14 D 1 DFF * * A------- Low Slow CLK_000_D_6_
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A14 A 1 DFF * * ------G- Low Slow CLK_000_D_7_
|
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G3 G 1 DFF * * A------- Low Slow CLK_000_D_8_
|
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A10 A 1 DFF * * --C----- Low Slow CLK_000_D_9_
|
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A13 A 3 DFF * * A------- Low Slow CYCLE_DMA_0_
|
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A9 A 4 DFF * * A------- Low Slow CYCLE_DMA_1_
|
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B3 B 1 DFF * * -B------ Low Slow IPL_D0_0_
|
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B14 B 1 DFF * * -B------ Low Slow IPL_D0_1_
|
||
A3 A 1 DFF * * -B------ Low Slow IPL_D0_2_
|
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G8 G 3 DFF * * ------G- Low - RN_A_0_ --> A_0_
|
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H4 H 3 DFF * * ABCDE-GH Low - RN_BGACK_030 --> BGACK_030
|
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D1 D 2 DFF * * ---D---- Low - RN_BG_000 --> BG_000
|
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H9 H 4 DFF * * -------H Low - RN_DSACK1 --> DSACK1
|
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B5 B 10 DFF * * -B------ Low - RN_IPL_030_0_ --> IPL_030_0_
|
||
B9 B 10 DFF * * -B------ Low - RN_IPL_030_1_ --> IPL_030_1_
|
||
B4 B 10 DFF * * -B------ Low - RN_IPL_030_2_ --> IPL_030_2_
|
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G0 G 2 DFF * * ------G- Low - RN_RW --> RW
|
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H1 H 4 DFF * * -------H Low - RN_RW_000 --> RW_000
|
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D0 D 3 TFF * * ---D-F-- Low - RN_VMA --> VMA
|
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F0 F 4 DFF * * A----F-- Low Slow RST_DLY_0_
|
||
F13 F 2 DFF * * A----F-- Low Slow RST_DLY_1_
|
||
F9 F 2 DFF * * A----F-- Low Slow RST_DLY_2_
|
||
G2 G 3 DFF * * ------GH Low Slow SIZE_DMA_0_
|
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G9 G 3 DFF * * ------GH Low Slow SIZE_DMA_1_
|
||
G5 G 3 DFF * * -B---FGH Low Slow SM_AMIGA_0_
|
||
F1 F 3 DFF * * -----FGH Low Slow SM_AMIGA_1_
|
||
F6 F 4 DFF * * -----F-- Low Slow SM_AMIGA_2_
|
||
F10 F 4 DFF * * -----F-- Low Slow SM_AMIGA_3_
|
||
B10 B 3 DFF * * -B---F-- Low Slow SM_AMIGA_4_
|
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F5 F 3 DFF * * -B---F-- Low Slow SM_AMIGA_5_
|
||
C2 C 3 DFF * * -BCD-F-H Low Slow SM_AMIGA_6_
|
||
F4 F 13 DFF * * -BC----H Low Slow SM_AMIGA_i_7_
|
||
D2 D 3 DFF * * ---D-F-- Low Slow cpu_est_0_
|
||
F8 F 4 DFF * * ---D-FG- Low Slow cpu_est_1_
|
||
D13 D 1 DFF * * ---D-FG- Low Slow cpu_est_2_
|
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D9 D 4 DFF * * ---D-FG- Low Slow cpu_est_3_
|
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G6 G 2 DFF * * ---D--G- Low Slow inst_AMIGA_BUS_ENABLE_DMA_HIGH
|
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G10 G 2 DFF * * --C---G- Low Slow inst_AMIGA_BUS_ENABLE_DMA_LOW
|
||
A12 A 7 DFF * * A------H Low Slow inst_AS_000_DMA
|
||
C15 C 2 DFF * * --C-E--- Low Slow inst_AS_000_INT
|
||
C6 C 7 DFF * * --CD-F-- Low Slow inst_AS_030_000_SYNC
|
||
A6 A 1 DFF * * -BCDE--H Low Slow inst_AS_030_D0
|
||
H13 H 1 DFF * * --C---G- Low Slow inst_BGACK_030_INT_D
|
||
A5 A 8 DFF * * A------- Low Slow inst_CLK_030_H
|
||
E6 E 1 DFF * * ----E--- Low Slow inst_CLK_OUT_PRE_50
|
||
E8 E 1 DFF * * -B----GH Low Slow inst_CLK_OUT_PRE_D
|
||
A1 A 9 DFF * * A------- Low Slow inst_DS_000_DMA
|
||
B6 B 4 DFF * * -B-D---- Low Slow inst_DS_000_ENABLE
|
||
G7 G 1 DFF * * -----F-- Low Slow inst_DTACK_D0
|
||
D6 D 3 DFF * * ---D---- Low Slow inst_LDS_000_INT
|
||
A8 A 2 DFF * * ABCDE-GH Low Slow inst_RESET_OUT
|
||
D10 D 2 DFF * * ---D---- Low Slow inst_UDS_000_INT
|
||
F2 F 1 DFF * * ---D-F-- Low Slow inst_VPA_D
|
||
----------------------------------------------------------------------
|
||
|
||
<Note> Power : Hi = High
|
||
MH = Medium High
|
||
ML = Medium Low
|
||
Lo = Low
|
||
|
||
|
||
|
||
|
||
Signals_Fanout_List
|
||
~~~~~~~~~~~~~~~~~~~
|
||
Signal Source : Fanout List
|
||
-----------------------------------------------------------------------------
|
||
SIZE_1_{ I}:inst_LDS_000_INT{ D}
|
||
AHIGH_31_{ C}: CIIN{ E} CIIN_0{ E}
|
||
A_DECODE_23_{ I}: CIIN{ E} CIIN_0{ E}
|
||
IPL_2_{ H}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B}
|
||
: IPL_D0_2_{ A}
|
||
FC_1_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C}
|
||
AS_030{ I}: AS_000{ E} BERR{ E} FPU_CS{ H}
|
||
: inst_AS_030_D0{ A}
|
||
AS_000{ F}: AS_030{ H} DS_030{ A}AMIGA_BUS_DATA_DIR{ E}
|
||
: BGACK_030{ H}inst_AS_000_DMA{ A}inst_DS_000_DMA{ A}
|
||
: CYCLE_DMA_0_{ A} CYCLE_DMA_1_{ A} inst_CLK_030_H{ A}
|
||
UDS_000{ E}: A_0_{ G}inst_AS_000_DMA{ A}inst_DS_000_DMA{ A}
|
||
: SIZE_DMA_0_{ G} SIZE_DMA_1_{ G} inst_CLK_030_H{ A}
|
||
LDS_000{ E}:inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} SIZE_DMA_0_{ G}
|
||
: SIZE_DMA_1_{ G} inst_CLK_030_H{ A}
|
||
nEXP_SPACE{. }: SIZE_1_{ H} AHIGH_31_{ B} AS_030{ H}
|
||
: DS_030{ A} SIZE_0_{ G} AHIGH_30_{ B}
|
||
: AHIGH_29_{ B} AHIGH_28_{ C} AHIGH_27_{ C}
|
||
: AHIGH_26_{ C} AHIGH_25_{ C} AHIGH_24_{ C}
|
||
:AMIGA_BUS_DATA_DIR{ E} BG_000{ D} DSACK1{ H}
|
||
: A_0_{ G}inst_AS_030_000_SYNC{ C} SM_AMIGA_6_{ C}
|
||
: SM_AMIGA_i_7_{ F} CIIN_0{ E}
|
||
BERR{ F}: DSACK1{ H}inst_AS_000_INT{ C}inst_AS_030_000_SYNC{ C}
|
||
:inst_DS_000_ENABLE{ B} SM_AMIGA_6_{ C} SM_AMIGA_0_{ G}
|
||
: SM_AMIGA_4_{ B} SM_AMIGA_1_{ F} SM_AMIGA_5_{ F}
|
||
: SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} SM_AMIGA_i_7_{ F}
|
||
BG_030{ D}: BG_000{ D}
|
||
SIZE_0_{ H}:inst_LDS_000_INT{ D}
|
||
AHIGH_30_{ C}: CIIN{ E} CIIN_0{ E}
|
||
BGACK_000{ E}: BERR{ E} FPU_CS{ H} BGACK_030{ H}
|
||
AHIGH_29_{ C}: CIIN{ E} CIIN_0{ E}
|
||
CLK_030{. }: DSACK1{ H}inst_AS_000_DMA{ A}inst_DS_000_DMA{ A}
|
||
: inst_CLK_030_H{ A}
|
||
AHIGH_28_{ D}: CIIN{ E} CIIN_0{ E}
|
||
CLK_000{. }: CLK_000_D_0_{ C}
|
||
AHIGH_27_{ D}: CIIN{ E} CIIN_0{ E}
|
||
AHIGH_26_{ D}: CIIN{ E} CIIN_0{ E}
|
||
AHIGH_25_{ D}: CIIN{ E} CIIN_0{ E}
|
||
AHIGH_24_{ D}: CIIN{ E} CIIN_0{ E}
|
||
A_DECODE_22_{ I}: CIIN{ E} CIIN_0{ E}
|
||
FPU_SENSE{ B}: BERR{ E} FPU_CS{ H}
|
||
A_DECODE_21_{ B}: CIIN{ E} CIIN_0{ E}
|
||
A_DECODE_20_{ B}: CIIN{ E} CIIN_0{ E}
|
||
DTACK{ E}: inst_DTACK_D0{ G}
|
||
A_DECODE_19_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C}
|
||
A_DECODE_18_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C}
|
||
A_DECODE_17_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C}
|
||
VPA{. }: inst_VPA_D{ F}
|
||
A_DECODE_16_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C}
|
||
RST{. }: IPL_030_2_{ B} RW_000{ H} BG_000{ D}
|
||
: BGACK_030{ H} DSACK1{ H} VMA{ D}
|
||
: RW{ G} A_0_{ G} IPL_030_1_{ B}
|
||
: IPL_030_0_{ B}inst_AS_000_INT{ C}inst_AMIGA_BUS_ENABLE_DMA_LOW{ G}
|
||
: inst_AS_030_D0{ A}inst_AS_030_000_SYNC{ C}inst_BGACK_030_INT_D{ H}
|
||
:inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} CYCLE_DMA_0_{ A}
|
||
: CYCLE_DMA_1_{ A} SIZE_DMA_0_{ G} SIZE_DMA_1_{ G}
|
||
: inst_VPA_D{ F}inst_UDS_000_INT{ D}inst_LDS_000_INT{ D}
|
||
: inst_DTACK_D0{ G} inst_RESET_OUT{ A} IPL_D0_0_{ B}
|
||
: IPL_D0_1_{ B} IPL_D0_2_{ A}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ G}
|
||
:inst_DS_000_ENABLE{ B} SM_AMIGA_6_{ C} SM_AMIGA_0_{ G}
|
||
: SM_AMIGA_4_{ B} RST_DLY_0_{ F} RST_DLY_1_{ F}
|
||
: RST_DLY_2_{ F} inst_CLK_030_H{ A} SM_AMIGA_1_{ F}
|
||
: SM_AMIGA_5_{ F} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F}
|
||
: SM_AMIGA_i_7_{ F}
|
||
IPL_1_{ G}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B}
|
||
: IPL_D0_1_{ B}
|
||
IPL_0_{ H}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B}
|
||
: IPL_D0_0_{ B}
|
||
FC_0_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C}
|
||
A_1_{ G}:inst_AMIGA_BUS_ENABLE_DMA_LOW{ G}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ G}
|
||
RN_IPL_030_2_{ C}: IPL_030_2_{ B}
|
||
RW_000{ I}:AMIGA_BUS_DATA_DIR{ E} RW{ G}inst_DS_000_DMA{ A}
|
||
RN_RW_000{ I}: RW_000{ H}
|
||
RN_BG_000{ E}: BG_000{ D}
|
||
RN_BGACK_030{ I}: SIZE_1_{ H} AHIGH_31_{ B} AS_030{ H}
|
||
: AS_000{ E} DS_030{ A} UDS_000{ D}
|
||
: LDS_000{ D} SIZE_0_{ G} AHIGH_30_{ B}
|
||
: AHIGH_29_{ B} AHIGH_28_{ C} AHIGH_27_{ C}
|
||
: AHIGH_26_{ C} AHIGH_25_{ C} AHIGH_24_{ C}
|
||
:AMIGA_BUS_DATA_DIR{ E}AMIGA_BUS_ENABLE_LOW{ C}AMIGA_BUS_ENABLE_HIGH{ D}
|
||
: RW_000{ H} BGACK_030{ H} RW{ G}
|
||
: A_0_{ G}inst_AMIGA_BUS_ENABLE_DMA_LOW{ G}inst_AS_030_000_SYNC{ C}
|
||
:inst_BGACK_030_INT_D{ H}inst_AS_000_DMA{ A}inst_DS_000_DMA{ A}
|
||
: CYCLE_DMA_0_{ A} CYCLE_DMA_1_{ A} SIZE_DMA_0_{ G}
|
||
: SIZE_DMA_1_{ G}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ G} inst_CLK_030_H{ A}
|
||
RN_DSACK1{ I}: DSACK1{ H}
|
||
RN_VMA{ E}: VMA{ D} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F}
|
||
: SM_AMIGA_i_7_{ F}
|
||
RW{ H}: RW_000{ H}inst_DS_000_ENABLE{ B}
|
||
RN_RW{ H}: RW{ G}
|
||
A_0_{ H}:inst_UDS_000_INT{ D}inst_LDS_000_INT{ D}
|
||
RN_A_0_{ H}: A_0_{ G}
|
||
RN_IPL_030_1_{ C}: IPL_030_1_{ B}
|
||
RN_IPL_030_0_{ C}: IPL_030_0_{ B}
|
||
cpu_est_3_{ E}: E{ G} VMA{ D} cpu_est_3_{ D}
|
||
: cpu_est_1_{ F} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F}
|
||
: SM_AMIGA_i_7_{ F}
|
||
cpu_est_0_{ E}: VMA{ D} cpu_est_3_{ D} cpu_est_0_{ D}
|
||
: cpu_est_1_{ F} cpu_est_2_{ D} SM_AMIGA_3_{ F}
|
||
: SM_AMIGA_2_{ F} SM_AMIGA_i_7_{ F}
|
||
cpu_est_1_{ G}: E{ G} VMA{ D} cpu_est_3_{ D}
|
||
: cpu_est_1_{ F} cpu_est_2_{ D} SM_AMIGA_3_{ F}
|
||
: SM_AMIGA_2_{ F} SM_AMIGA_i_7_{ F}
|
||
cpu_est_2_{ E}: E{ G} VMA{ D} cpu_est_3_{ D}
|
||
: cpu_est_2_{ D} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F}
|
||
: SM_AMIGA_i_7_{ F}
|
||
inst_AS_000_INT{ D}: AS_000{ E}inst_AS_000_INT{ C}
|
||
inst_AMIGA_BUS_ENABLE_DMA_LOW{ H}:AMIGA_BUS_ENABLE_LOW{ C}inst_AMIGA_BUS_ENABLE_DMA_LOW{ G}
|
||
inst_AS_030_D0{ B}: CIIN{ E} BG_000{ D} DSACK1{ H}
|
||
:inst_AS_000_INT{ C}inst_AS_030_000_SYNC{ C}inst_DS_000_ENABLE{ B}
|
||
: CIIN_0{ E}
|
||
inst_AS_030_000_SYNC{ D}:AMIGA_BUS_ENABLE_HIGH{ D}inst_AS_030_000_SYNC{ C} SM_AMIGA_6_{ C}
|
||
: SM_AMIGA_i_7_{ F}
|
||
inst_BGACK_030_INT_D{ I}: RW{ G} A_0_{ G}inst_AMIGA_BUS_ENABLE_DMA_LOW{ G}
|
||
:inst_AS_030_000_SYNC{ C} SIZE_DMA_0_{ G} SIZE_DMA_1_{ G}
|
||
:inst_AMIGA_BUS_ENABLE_DMA_HIGH{ G}
|
||
inst_AS_000_DMA{ B}: AS_030{ H}inst_AS_000_DMA{ A}inst_DS_000_DMA{ A}
|
||
: inst_CLK_030_H{ A}
|
||
inst_DS_000_DMA{ B}: DS_030{ A}inst_DS_000_DMA{ A}
|
||
CYCLE_DMA_0_{ B}:inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} CYCLE_DMA_0_{ A}
|
||
: CYCLE_DMA_1_{ A} inst_CLK_030_H{ A}
|
||
CYCLE_DMA_1_{ B}:inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} CYCLE_DMA_1_{ A}
|
||
: inst_CLK_030_H{ A}
|
||
SIZE_DMA_0_{ H}: SIZE_1_{ H} SIZE_0_{ G} SIZE_DMA_0_{ G}
|
||
SIZE_DMA_1_{ H}: SIZE_1_{ H} SIZE_0_{ G} SIZE_DMA_1_{ G}
|
||
inst_VPA_D{ G}: VMA{ D} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F}
|
||
: SM_AMIGA_i_7_{ F}
|
||
inst_UDS_000_INT{ E}: UDS_000{ D}inst_UDS_000_INT{ D}
|
||
inst_LDS_000_INT{ E}: LDS_000{ D}inst_LDS_000_INT{ D}
|
||
inst_CLK_OUT_PRE_D{ F}: CLK_DIV_OUT{ G} CLK_EXP{ B} DSACK1{ H}
|
||
CLK_000_D_1_{ I}: RW_000{ H} BGACK_030{ H} VMA{ D}
|
||
: cpu_est_3_{ D} cpu_est_0_{ D} cpu_est_1_{ F}
|
||
: cpu_est_2_{ D}inst_AS_000_INT{ C} CYCLE_DMA_0_{ A}
|
||
: CYCLE_DMA_1_{ A} inst_RESET_OUT{ A} CLK_000_D_2_{ E}
|
||
:inst_DS_000_ENABLE{ B} SM_AMIGA_6_{ C} SM_AMIGA_0_{ G}
|
||
: SM_AMIGA_4_{ B} RST_DLY_0_{ F} RST_DLY_1_{ F}
|
||
: RST_DLY_2_{ F} SM_AMIGA_1_{ F} SM_AMIGA_5_{ F}
|
||
: SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} SM_AMIGA_i_7_{ F}
|
||
CLK_000_D_10_{ D}: DSACK1{ H} CLK_000_D_11_{ H}
|
||
CLK_000_D_11_{ I}: DSACK1{ H} CLK_000_D_12_{ G}
|
||
inst_DTACK_D0{ H}: SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} SM_AMIGA_i_7_{ F}
|
||
inst_RESET_OUT{ B}: AHIGH_31_{ B} AS_030{ H} AS_000{ E}
|
||
: DS_030{ A} UDS_000{ D} LDS_000{ D}
|
||
: AHIGH_30_{ B} AHIGH_29_{ B} AHIGH_28_{ C}
|
||
: AHIGH_27_{ C} AHIGH_26_{ C} AHIGH_25_{ C}
|
||
: AHIGH_24_{ C} RESET{ B} RW_000{ H}
|
||
: RW{ G} A_0_{ G} inst_RESET_OUT{ A}
|
||
CLK_000_D_0_{ D}: RW_000{ H} BG_000{ D} BGACK_030{ H}
|
||
: VMA{ D} cpu_est_3_{ D} cpu_est_0_{ D}
|
||
: cpu_est_1_{ F} cpu_est_2_{ D}inst_AS_000_INT{ C}
|
||
: CYCLE_DMA_0_{ A} CYCLE_DMA_1_{ A} CLK_000_D_1_{ H}
|
||
: inst_RESET_OUT{ A}inst_DS_000_ENABLE{ B} SM_AMIGA_6_{ C}
|
||
: SM_AMIGA_0_{ G} SM_AMIGA_4_{ B} RST_DLY_0_{ F}
|
||
: RST_DLY_1_{ F} RST_DLY_2_{ F} SM_AMIGA_1_{ F}
|
||
: SM_AMIGA_5_{ F} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F}
|
||
: SM_AMIGA_i_7_{ F}
|
||
inst_CLK_OUT_PRE_50{ F}:inst_CLK_OUT_PRE_D{ E}inst_CLK_OUT_PRE_50{ E}
|
||
IPL_D0_0_{ C}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B}
|
||
IPL_D0_1_{ C}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B}
|
||
IPL_D0_2_{ B}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B}
|
||
CLK_000_D_2_{ F}: CLK_000_D_3_{ E} SM_AMIGA_6_{ C} SM_AMIGA_i_7_{ F}
|
||
CLK_000_D_3_{ F}: CLK_000_D_4_{ C}
|
||
CLK_000_D_4_{ D}: CLK_000_D_5_{ E}
|
||
CLK_000_D_5_{ F}: CLK_000_D_6_{ D}
|
||
CLK_000_D_6_{ E}: CLK_000_D_7_{ A}
|
||
CLK_000_D_7_{ B}: CLK_000_D_8_{ G}
|
||
CLK_000_D_8_{ H}: CLK_000_D_9_{ A}
|
||
CLK_000_D_9_{ B}: CLK_000_D_10_{ C}
|
||
CLK_000_D_12_{ H}: DSACK1{ H}
|
||
inst_AMIGA_BUS_ENABLE_DMA_HIGH{ H}:AMIGA_BUS_ENABLE_HIGH{ D}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ G}
|
||
inst_DS_000_ENABLE{ C}: UDS_000{ D} LDS_000{ D}inst_DS_000_ENABLE{ B}
|
||
SM_AMIGA_6_{ D}: RW_000{ H}inst_AS_000_INT{ C}inst_UDS_000_INT{ D}
|
||
:inst_LDS_000_INT{ D}inst_DS_000_ENABLE{ B} SM_AMIGA_6_{ C}
|
||
: SM_AMIGA_5_{ F} SM_AMIGA_i_7_{ F}
|
||
SM_AMIGA_0_{ H}: RW_000{ H}inst_DS_000_ENABLE{ B} SM_AMIGA_0_{ G}
|
||
: SM_AMIGA_i_7_{ F}
|
||
SM_AMIGA_4_{ C}:inst_DS_000_ENABLE{ B} SM_AMIGA_4_{ B} SM_AMIGA_3_{ F}
|
||
: SM_AMIGA_i_7_{ F}
|
||
RST_DLY_0_{ G}: inst_RESET_OUT{ A} RST_DLY_0_{ F} RST_DLY_1_{ F}
|
||
: RST_DLY_2_{ F}
|
||
RST_DLY_1_{ G}: inst_RESET_OUT{ A} RST_DLY_0_{ F} RST_DLY_1_{ F}
|
||
: RST_DLY_2_{ F}
|
||
RST_DLY_2_{ G}: inst_RESET_OUT{ A} RST_DLY_0_{ F} RST_DLY_1_{ F}
|
||
: RST_DLY_2_{ F}
|
||
inst_CLK_030_H{ B}:inst_DS_000_DMA{ A} inst_CLK_030_H{ A}
|
||
SM_AMIGA_1_{ G}: DSACK1{ H} SM_AMIGA_0_{ G} SM_AMIGA_1_{ F}
|
||
: SM_AMIGA_i_7_{ F}
|
||
SM_AMIGA_5_{ G}:inst_DS_000_ENABLE{ B} SM_AMIGA_4_{ B} SM_AMIGA_5_{ F}
|
||
: SM_AMIGA_i_7_{ F}
|
||
SM_AMIGA_3_{ G}: SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} SM_AMIGA_i_7_{ F}
|
||
SM_AMIGA_2_{ G}: SM_AMIGA_1_{ F} SM_AMIGA_2_{ F} SM_AMIGA_i_7_{ F}
|
||
SM_AMIGA_i_7_{ G}: RW_000{ H}inst_AS_030_000_SYNC{ C}inst_DS_000_ENABLE{ B}
|
||
: SM_AMIGA_6_{ C}
|
||
CIIN_0{ F}: CIIN{ E}
|
||
-----------------------------------------------------------------------------
|
||
|
||
<Note> {.} : Indicates block location of signal
|
||
|
||
|
||
Set_Reset_Summary
|
||
~~~~~~~~~~~~~~~~~
|
||
|
||
Block A
|
||
block level set pt : GND
|
||
block level reset pt : GND
|
||
Equations :
|
||
| | |Block|Block| Signal
|
||
| Reg |Mode |Set |Reset| Name
|
||
+-----+-----+-----+-----+------------------------
|
||
| | | | | DS_030
|
||
| | | | | AVEC
|
||
| * | S | BS | BR | inst_RESET_OUT
|
||
| * | S | BS | BR | inst_AS_030_D0
|
||
| * | S | BS | BR | inst_AS_000_DMA
|
||
| * | S | BS | BR | inst_DS_000_DMA
|
||
| * | S | BS | BR | inst_CLK_030_H
|
||
| * | S | BS | BR | CYCLE_DMA_1_
|
||
| * | S | BS | BR | CYCLE_DMA_0_
|
||
| * | S | BS | BR | CLK_000_D_9_
|
||
| * | S | BS | BR | CLK_000_D_7_
|
||
| * | S | BS | BR | IPL_D0_2_
|
||
| | | | | A_DECODE_19_
|
||
| | | | | A_DECODE_16_
|
||
| | | | | A_DECODE_18_
|
||
| | | | | FPU_SENSE
|
||
| | | | | A_DECODE_21_
|
||
| | | | | A_DECODE_20_
|
||
|
||
|
||
Block B
|
||
block level set pt : GND
|
||
block level reset pt : GND
|
||
Equations :
|
||
| | |Block|Block| Signal
|
||
| Reg |Mode |Set |Reset| Name
|
||
+-----+-----+-----+-----+------------------------
|
||
| | | | | AHIGH_29_
|
||
| | | | | AHIGH_30_
|
||
| | | | | AHIGH_31_
|
||
| * | S | BS | BR | IPL_030_2_
|
||
| * | S | BS | BR | IPL_030_0_
|
||
| * | S | BS | BR | IPL_030_1_
|
||
| * | S | BS | BR | CLK_EXP
|
||
| | | | | RESET
|
||
| * | S | BS | BR | inst_DS_000_ENABLE
|
||
| * | S | BS | BR | SM_AMIGA_4_
|
||
| * | S | BS | BR | RN_IPL_030_0_
|
||
| * | S | BS | BR | RN_IPL_030_1_
|
||
| * | S | BS | BR | RN_IPL_030_2_
|
||
| * | S | BS | BR | IPL_D0_1_
|
||
| * | S | BS | BR | IPL_D0_0_
|
||
|
||
|
||
Block C
|
||
block level set pt : GND
|
||
block level reset pt : GND
|
||
Equations :
|
||
| | |Block|Block| Signal
|
||
| Reg |Mode |Set |Reset| Name
|
||
+-----+-----+-----+-----+------------------------
|
||
| | | | | AHIGH_24_
|
||
| | | | | AHIGH_25_
|
||
| | | | | AHIGH_26_
|
||
| | | | | AHIGH_27_
|
||
| | | | | AHIGH_28_
|
||
| | | | | AMIGA_BUS_ENABLE_LOW
|
||
| * | S | BS | BR | CLK_000_D_0_
|
||
| * | S | BS | BR | SM_AMIGA_6_
|
||
| * | S | BS | BR | inst_AS_030_000_SYNC
|
||
| * | S | BS | BR | inst_AS_000_INT
|
||
| * | S | BS | BR | CLK_000_D_4_
|
||
| * | S | BS | BR | CLK_000_D_10_
|
||
| | | | | BG_030
|
||
|
||
|
||
Block D
|
||
block level set pt : GND
|
||
block level reset pt : GND
|
||
Equations :
|
||
| | |Block|Block| Signal
|
||
| Reg |Mode |Set |Reset| Name
|
||
+-----+-----+-----+-----+------------------------
|
||
| | | | | UDS_000
|
||
| | | | | LDS_000
|
||
| * | S | BS | BR | VMA
|
||
| | | | | AMIGA_BUS_ENABLE_HIGH
|
||
| * | S | BS | BR | BG_000
|
||
| | | | | AMIGA_ADDR_ENABLE
|
||
| * | S | BS | BR | cpu_est_3_
|
||
| * | S | BS | BR | cpu_est_2_
|
||
| * | S | BS | BR | RN_VMA
|
||
| * | S | BS | BR | cpu_est_0_
|
||
| * | S | BS | BR | inst_LDS_000_INT
|
||
| * | S | BS | BR | RN_BG_000
|
||
| * | S | BS | BR | inst_UDS_000_INT
|
||
| * | S | BS | BR | CLK_000_D_6_
|
||
| | | | | BGACK_000
|
||
| | | | | DTACK
|
||
|
||
|
||
Block E
|
||
block level set pt : GND
|
||
block level reset pt : GND
|
||
Equations :
|
||
| | |Block|Block| Signal
|
||
| Reg |Mode |Set |Reset| Name
|
||
+-----+-----+-----+-----+------------------------
|
||
| | | | | BERR
|
||
| | | | | AS_000
|
||
| | | | | AMIGA_BUS_DATA_DIR
|
||
| | | | | CIIN
|
||
| * | S | BS | BR | CLK_000_D_2_
|
||
| * | S | BS | BR | inst_CLK_OUT_PRE_D
|
||
| | | | | CIIN_0
|
||
| * | S | BS | BR | CLK_000_D_5_
|
||
| * | S | BS | BR | CLK_000_D_3_
|
||
| * | S | BS | BR | inst_CLK_OUT_PRE_50
|
||
|
||
|
||
Block F
|
||
block level set pt : GND
|
||
block level reset pt : GND
|
||
Equations :
|
||
| | |Block|Block| Signal
|
||
| Reg |Mode |Set |Reset| Name
|
||
+-----+-----+-----+-----+------------------------
|
||
| * | S | BS | BR | SM_AMIGA_i_7_
|
||
| * | S | BS | BR | cpu_est_1_
|
||
| * | S | BS | BR | SM_AMIGA_1_
|
||
| * | S | BS | BR | RST_DLY_0_
|
||
| * | S | BS | BR | SM_AMIGA_5_
|
||
| * | S | BS | BR | RST_DLY_2_
|
||
| * | S | BS | BR | RST_DLY_1_
|
||
| * | S | BS | BR | inst_VPA_D
|
||
| * | S | BS | BR | SM_AMIGA_2_
|
||
| * | S | BS | BR | SM_AMIGA_3_
|
||
| | | | | A_DECODE_17_
|
||
| | | | | FC_1_
|
||
| | | | | FC_0_
|
||
| | | | | A_1_
|
||
| | | | | IPL_1_
|
||
|
||
|
||
Block G
|
||
block level set pt : GND
|
||
block level reset pt : GND
|
||
Equations :
|
||
| | |Block|Block| Signal
|
||
| Reg |Mode |Set |Reset| Name
|
||
+-----+-----+-----+-----+------------------------
|
||
| * | S | BS | BR | RW
|
||
| * | S | BS | BR | A_0_
|
||
| | | | | SIZE_0_
|
||
| | | | | E
|
||
| * | S | BS | BR | CLK_DIV_OUT
|
||
| * | S | BS | BR | SM_AMIGA_0_
|
||
| * | S | BS | BR | SIZE_DMA_1_
|
||
| * | S | BS | BR | SIZE_DMA_0_
|
||
| * | S | BS | BR | inst_AMIGA_BUS_ENABLE_DMA_HIGH
|
||
| * | S | BS | BR | inst_AMIGA_BUS_ENABLE_DMA_LOW
|
||
| * | S | BS | BR | RN_A_0_
|
||
| * | S | BS | BR | RN_RW
|
||
| * | S | BS | BR | CLK_000_D_12_
|
||
| * | S | BS | BR | CLK_000_D_8_
|
||
| * | S | BS | BR | inst_DTACK_D0
|
||
| | | | | IPL_2_
|
||
| | | | | IPL_0_
|
||
|
||
|
||
Block H
|
||
block level set pt : GND
|
||
block level reset pt : GND
|
||
Equations :
|
||
| | |Block|Block| Signal
|
||
| Reg |Mode |Set |Reset| Name
|
||
+-----+-----+-----+-----+------------------------
|
||
| * | S | BS | BR | RW_000
|
||
| | | | | AS_030
|
||
| | | | | SIZE_1_
|
||
| * | S | BS | BR | DSACK1
|
||
| * | S | BS | BR | BGACK_030
|
||
| | | | | FPU_CS
|
||
| * | S | BS | BR | CLK_000_D_1_
|
||
| * | S | BS | BR | RN_BGACK_030
|
||
| * | S | BS | BR | CLK_000_D_11_
|
||
| * | S | BS | BR | inst_BGACK_030_INT_D
|
||
| * | S | BS | BR | RN_DSACK1
|
||
| * | S | BS | BR | RN_RW_000
|
||
| | | | | A_DECODE_23_
|
||
| | | | | A_DECODE_22_
|
||
|
||
|
||
<Note> (S) means the macrocell is configured in synchronous mode
|
||
i.e. it uses the block-level set and reset pt.
|
||
(A) means the macrocell is configured in asynchronous mode
|
||
i.e. it can have its independant set or reset pt.
|
||
(BS) means the block-level set pt is selected.
|
||
(BR) means the block-level reset pt is selected.
|
||
|
||
|
||
|
||
|
||
BLOCK_A_LOGIC_ARRAY_FANIN
|
||
~~~~~~~~~~~~~~~~~~~~~~~~~
|
||
CSM Signal Source CSM Signal Source
|
||
------------------------------------ ------------------------------------
|
||
mx A0 RST pin 86 mx A17 CLK_000_D_6_ mcell D14
|
||
mx A1 RST_DLY_2_ mcell F9 mx A18 inst_CLK_030_H mcell A5
|
||
mx A2 CYCLE_DMA_1_ mcell A9 mx A19 AS_030 pin 82
|
||
mx A3 inst_RESET_OUT mcell A8 mx A20 RN_BGACK_030 mcell H4
|
||
mx A4 CLK_030 pin 64 mx A21 RW_000 pin 80
|
||
mx A5 nEXP_SPACE pin 14 mx A22 IPL_2_ pin 68
|
||
mx A6 RST_DLY_1_ mcell F13 mx A23 ... ...
|
||
mx A7 ... ... mx A24 CLK_000_D_8_ mcell G3
|
||
mx A8 UDS_000 pin 32 mx A25 CYCLE_DMA_0_ mcell A13
|
||
mx A9 inst_DS_000_DMA mcell A1 mx A26 ... ...
|
||
mx A10 CLK_000_D_1_ mcell H3 mx A27 LDS_000 pin 31
|
||
mx A11 CLK_000_D_0_ mcell C13 mx A28 ... ...
|
||
mx A12 ... ... mx A29 ... ...
|
||
mx A13 ... ... mx A30 ... ...
|
||
mx A14 ... ... mx A31 RST_DLY_0_ mcell F0
|
||
mx A15 inst_AS_000_DMA mcell A12 mx A32 ... ...
|
||
mx A16 AS_000 pin 42
|
||
----------------------------------------------------------------------------
|
||
|
||
|
||
BLOCK_B_LOGIC_ARRAY_FANIN
|
||
~~~~~~~~~~~~~~~~~~~~~~~~~
|
||
CSM Signal Source CSM Signal Source
|
||
------------------------------------ ------------------------------------
|
||
mx B0 RN_BGACK_030 mcell H4 mx B17 ... ...
|
||
mx B1 BERR pin 41 mx B18 inst_RESET_OUT mcell A8
|
||
mx B2inst_DS_000_ENABLE mcell B6 mx B19 ... ...
|
||
mx B3 IPL_1_ pin 56 mx B20 IPL_D0_1_ mcell B14
|
||
mx B4 IPL_2_ pin 68 mx B21 RST pin 86
|
||
mx B5 nEXP_SPACE pin 14 mx B22 SM_AMIGA_0_ mcell G5
|
||
mx B6 RN_IPL_030_1_ mcell B9 mx B23 ... ...
|
||
mx B7 ... ... mx B24 ... ...
|
||
mx B8 RW pin 71 mx B25 IPL_D0_2_ mcell A3
|
||
mx B9 SM_AMIGA_5_ mcell F5 mx B26 ... ...
|
||
mx B10 CLK_000_D_1_ mcell H3 mx B27 RN_IPL_030_2_ mcell B4
|
||
mx B11 CLK_000_D_0_ mcell C13 mx B28 RN_IPL_030_0_ mcell B5
|
||
mx B12 SM_AMIGA_4_ mcell B10 mx B29 ... ...
|
||
mx B13 IPL_D0_0_ mcell B3 mx B30inst_CLK_OUT_PRE_D mcell E8
|
||
mx B14 SM_AMIGA_i_7_ mcell F4 mx B31 ... ...
|
||
mx B15 inst_AS_030_D0 mcell A6 mx B32 SM_AMIGA_6_ mcell C2
|
||
mx B16 IPL_0_ pin 67
|
||
----------------------------------------------------------------------------
|
||
|
||
|
||
BLOCK_C_LOGIC_ARRAY_FANIN
|
||
~~~~~~~~~~~~~~~~~~~~~~~~~
|
||
CSM Signal Source CSM Signal Source
|
||
------------------------------------ ------------------------------------
|
||
mx C0 RST pin 86 mx C17 BERR pin 41
|
||
mx C1 FC_1_ pin 58 mx C18 inst_RESET_OUT mcell A8
|
||
mx C2 CLK_000_D_3_ mcell E9 mx C19 ... ...
|
||
mx C3 CLK_000_D_2_ mcell E2 mx C20 RN_BGACK_030 mcell H4
|
||
mx C4 A_DECODE_18_ pin 95 mx C21 ... ...
|
||
mx C5 nEXP_SPACE pin 14 mx C22inst_AMIGA_BUS_ENABLE_DMA_LOW mcell G10
|
||
mx C6 FC_0_ pin 57 mx C23 ... ...
|
||
mx C7inst_BGACK_030_INT_D mcell H13 mx C24 ... ...
|
||
mx C8 CLK_000_D_9_ mcell A10 mx C25 ... ...
|
||
mx C9inst_AS_030_000_SYNC mcell C6 mx C26 ... ...
|
||
mx C10 CLK_000_D_1_ mcell H3 mx C27 ... ...
|
||
mx C11 A_DECODE_16_ pin 96 mx C28 ... ...
|
||
mx C12 A_DECODE_19_ pin 97 mx C29 SM_AMIGA_i_7_ mcell F4
|
||
mx C13 A_DECODE_17_ pin 59 mx C30 CLK_000_D_0_ mcell C13
|
||
mx C14 CLK_000 pin 11 mx C31 ... ...
|
||
mx C15 inst_AS_030_D0 mcell A6 mx C32 SM_AMIGA_6_ mcell C2
|
||
mx C16 inst_AS_000_INT mcell C15
|
||
----------------------------------------------------------------------------
|
||
|
||
|
||
BLOCK_D_LOGIC_ARRAY_FANIN
|
||
~~~~~~~~~~~~~~~~~~~~~~~~~
|
||
CSM Signal Source CSM Signal Source
|
||
------------------------------------ ------------------------------------
|
||
mx D0 A_0_ pin 69 mx D17 SIZE_0_ pin 70
|
||
mx D1 RN_VMA mcell D0 mx D18 inst_RESET_OUT mcell A8
|
||
mx D2inst_UDS_000_INT mcell D10 mx D19 ... ...
|
||
mx D3 cpu_est_0_ mcell D2 mx D20 RN_BGACK_030 mcell H4
|
||
mx D4 BG_030 pin 21 mx D21 cpu_est_2_ mcell D13
|
||
mx D5 nEXP_SPACE pin 14 mx D22 SM_AMIGA_6_ mcell C2
|
||
mx D6 SIZE_1_ pin 79 mx D23inst_AMIGA_BUS_ENABLE_DMA_HIGH mcell G6
|
||
mx D7 cpu_est_3_ mcell D9 mx D24 RST pin 86
|
||
mx D8 ... ... mx D25 ... ...
|
||
mx D9inst_AS_030_000_SYNC mcell C6 mx D26 ... ...
|
||
mx D10 CLK_000_D_1_ mcell H3 mx D27 RN_BG_000 mcell D1
|
||
mx D11inst_DS_000_ENABLE mcell B6 mx D28 inst_VPA_D mcell F2
|
||
mx D12 ... ... mx D29 ... ...
|
||
mx D13 ... ... mx D30 CLK_000_D_0_ mcell C13
|
||
mx D14 CLK_000_D_5_ mcell E5 mx D31 ... ...
|
||
mx D15 inst_AS_030_D0 mcell A6 mx D32 cpu_est_1_ mcell F8
|
||
mx D16inst_LDS_000_INT mcell D6
|
||
----------------------------------------------------------------------------
|
||
|
||
|
||
BLOCK_E_LOGIC_ARRAY_FANIN
|
||
~~~~~~~~~~~~~~~~~~~~~~~~~
|
||
CSM Signal Source CSM Signal Source
|
||
------------------------------------ ------------------------------------
|
||
mx E0inst_CLK_OUT_PRE_50 mcell E6 mx E17 A_DECODE_20_ pin 93
|
||
mx E1 FC_1_ pin 58 mx E18 A_DECODE_23_ pin 85
|
||
mx E2 AS_000 pin 42 mx E19 AHIGH_30_ pin 5
|
||
mx E3 AHIGH_27_ pin 16 mx E20 A_DECODE_22_ pin 84
|
||
mx E4 FPU_SENSE pin 91 mx E21 nEXP_SPACE pin 14
|
||
mx E5 A_DECODE_21_ pin 94 mx E22 AHIGH_25_ pin 18
|
||
mx E6 FC_0_ pin 57 mx E23 RN_BGACK_030 mcell H4
|
||
mx E7 AHIGH_28_ pin 15 mx E24 CIIN_0 mcell E10
|
||
mx E8 A_DECODE_17_ pin 59 mx E25 AHIGH_31_ pin 4
|
||
mx E9 AS_030 pin 82 mx E26 AHIGH_26_ pin 17
|
||
mx E10 CLK_000_D_1_ mcell H3 mx E27 CLK_000_D_2_ mcell E2
|
||
mx E11 A_DECODE_16_ pin 96 mx E28 RW_000 pin 80
|
||
mx E12 A_DECODE_19_ pin 97 mx E29 CLK_000_D_4_ mcell C11
|
||
mx E13 AHIGH_29_ pin 6 mx E30 inst_RESET_OUT mcell A8
|
||
mx E14 AHIGH_24_ pin 19 mx E31 A_DECODE_18_ pin 95
|
||
mx E15 inst_AS_030_D0 mcell A6 mx E32 BGACK_000 pin 28
|
||
mx E16 inst_AS_000_INT mcell C15
|
||
----------------------------------------------------------------------------
|
||
|
||
|
||
BLOCK_F_LOGIC_ARRAY_FANIN
|
||
~~~~~~~~~~~~~~~~~~~~~~~~~
|
||
CSM Signal Source CSM Signal Source
|
||
------------------------------------ ------------------------------------
|
||
mx F0 RST pin 86 mx F17 BERR pin 41
|
||
mx F1 SM_AMIGA_2_ mcell F6 mx F18 RST_DLY_2_ mcell F9
|
||
mx F2 SM_AMIGA_3_ mcell F10 mx F19 ... ...
|
||
mx F3 cpu_est_0_ mcell D2 mx F20 cpu_est_1_ mcell F8
|
||
mx F4 ... ... mx F21 cpu_est_2_ mcell D13
|
||
mx F5 nEXP_SPACE pin 14 mx F22 SM_AMIGA_0_ mcell G5
|
||
mx F6 RST_DLY_1_ mcell F13 mx F23 ... ...
|
||
mx F7 cpu_est_3_ mcell D9 mx F24 ... ...
|
||
mx F8 inst_DTACK_D0 mcell G7 mx F25 RST_DLY_0_ mcell F0
|
||
mx F9 inst_VPA_D mcell F2 mx F26 RN_VMA mcell D0
|
||
mx F10 CLK_000_D_1_ mcell H3 mx F27inst_AS_030_000_SYNC mcell C6
|
||
mx F11 CLK_000_D_0_ mcell C13 mx F28 ... ...
|
||
mx F12 SM_AMIGA_4_ mcell B10 mx F29 ... ...
|
||
mx F13 VPA pin 36 mx F30 SM_AMIGA_1_ mcell F1
|
||
mx F14 SM_AMIGA_5_ mcell F5 mx F31 ... ...
|
||
mx F15 CLK_000_D_2_ mcell E2 mx F32 SM_AMIGA_6_ mcell C2
|
||
mx F16 ... ...
|
||
----------------------------------------------------------------------------
|
||
|
||
|
||
BLOCK_G_LOGIC_ARRAY_FANIN
|
||
~~~~~~~~~~~~~~~~~~~~~~~~~
|
||
CSM Signal Source CSM Signal Source
|
||
------------------------------------ ------------------------------------
|
||
mx G0 RN_BGACK_030 mcell H4 mx G17 RN_RW mcell G0
|
||
mx G1 BERR pin 41 mx G18 inst_RESET_OUT mcell A8
|
||
mx G2 cpu_est_1_ mcell F8 mx G19 ... ...
|
||
mx G3 A_1_ pin 60 mx G20 CLK_000_D_7_ mcell A14
|
||
mx G4 SIZE_DMA_0_ mcell G2 mx G21 cpu_est_2_ mcell D13
|
||
mx G5inst_AMIGA_BUS_ENABLE_DMA_HIGH mcell G6 mx G22inst_AMIGA_BUS_ENABLE_DMA_LOW mcell G10
|
||
mx G6 RW_000 pin 80 mx G23 CLK_000_D_11_ mcell H0
|
||
mx G7inst_BGACK_030_INT_D mcell H13 mx G24 RST pin 86
|
||
mx G8 UDS_000 pin 32 mx G25 cpu_est_3_ mcell D9
|
||
mx G9 DTACK pin 30 mx G26 ... ...
|
||
mx G10 SM_AMIGA_1_ mcell F1 mx G27 LDS_000 pin 31
|
||
mx G11 CLK_000_D_1_ mcell H3 mx G28 ... ...
|
||
mx G12 SIZE_DMA_1_ mcell G9 mx G29 ... ...
|
||
mx G13 RN_A_0_ mcell G8 mx G30 CLK_000_D_0_ mcell C13
|
||
mx G14 ... ... mx G31 ... ...
|
||
mx G15 nEXP_SPACE pin 14 mx G32 SM_AMIGA_0_ mcell G5
|
||
mx G16inst_CLK_OUT_PRE_D mcell E8
|
||
----------------------------------------------------------------------------
|
||
|
||
|
||
BLOCK_H_LOGIC_ARRAY_FANIN
|
||
~~~~~~~~~~~~~~~~~~~~~~~~~
|
||
CSM Signal Source CSM Signal Source
|
||
------------------------------------ ------------------------------------
|
||
mx H0 CLK_000_D_0_ mcell C13 mx H17 A_DECODE_18_ pin 95
|
||
mx H1 BERR pin 41 mx H18 inst_RESET_OUT mcell A8
|
||
mx H2 SM_AMIGA_6_ mcell C2 mx H19 RN_RW_000 mcell H1
|
||
mx H3 SM_AMIGA_0_ mcell G5 mx H20 RN_BGACK_030 mcell H4
|
||
mx H4 BGACK_000 pin 28 mx H21 RST pin 86
|
||
mx H5 RN_DSACK1 mcell H9 mx H22 inst_AS_030_D0 mcell A6
|
||
mx H6 A_DECODE_16_ pin 96 mx H23 CLK_000_D_11_ mcell H0
|
||
mx H7 CLK_000_D_10_ mcell C14 mx H24 FC_0_ pin 57
|
||
mx H8inst_CLK_OUT_PRE_D mcell E8 mx H25 RW pin 71
|
||
mx H9 inst_AS_000_DMA mcell A12 mx H26 CLK_000_D_12_ mcell G14
|
||
mx H10 SIZE_DMA_1_ mcell G9 mx H27 A_DECODE_19_ pin 97
|
||
mx H11 CLK_000_D_1_ mcell H3 mx H28 CLK_030 pin 64
|
||
mx H12 FC_1_ pin 58 mx H29 FPU_SENSE pin 91
|
||
mx H13 A_DECODE_17_ pin 59 mx H30 SM_AMIGA_1_ mcell F1
|
||
mx H14 SM_AMIGA_i_7_ mcell F4 mx H31 SIZE_DMA_0_ mcell G2
|
||
mx H15 nEXP_SPACE pin 14 mx H32 AS_030 pin 82
|
||
mx H16 AS_000 pin 42
|
||
----------------------------------------------------------------------------
|
||
|
||
<Note> CSM indicates the mux inputs from the Central Switch Matrix.
|
||
<Note> Source indicates where the signal comes from (pin or macrocell).
|
||
|
||
|
||
|
||
|
||
PostFit_Equations
|
||
~~~~~~~~~~~~~~~~~
|
||
|
||
|
||
P-Terms Fan-in Fan-out Type Name (attributes)
|
||
--------- ------ ------- ---- -----------------
|
||
1 2 1 Pin SIZE_1_
|
||
1 2 1 Pin SIZE_1_.OE
|
||
0 0 1 Pin AHIGH_31_
|
||
1 3 1 Pin AHIGH_31_.OE
|
||
1 2 1 Pin AS_030-
|
||
1 3 1 Pin AS_030.OE
|
||
1 2 1 Pin AS_000-
|
||
1 2 1 Pin AS_000.OE
|
||
1 2 1 Pin DS_030-
|
||
1 3 1 Pin DS_030.OE
|
||
1 2 1 Pin UDS_000-
|
||
1 2 1 Pin UDS_000.OE
|
||
1 2 1 Pin LDS_000-
|
||
1 2 1 Pin LDS_000.OE
|
||
0 0 1 Pin BERR
|
||
1 9 1 Pin BERR.OE
|
||
1 2 1 Pin SIZE_0_
|
||
1 2 1 Pin SIZE_0_.OE
|
||
0 0 1 Pin AHIGH_30_
|
||
1 3 1 Pin AHIGH_30_.OE
|
||
0 0 1 Pin AHIGH_29_
|
||
1 3 1 Pin AHIGH_29_.OE
|
||
0 0 1 Pin AHIGH_28_
|
||
1 3 1 Pin AHIGH_28_.OE
|
||
0 0 1 Pin AHIGH_27_
|
||
1 3 1 Pin AHIGH_27_.OE
|
||
0 0 1 Pin AHIGH_26_
|
||
1 3 1 Pin AHIGH_26_.OE
|
||
1 1 1 Pin CLK_DIV_OUT.D
|
||
1 1 1 Pin CLK_DIV_OUT.C
|
||
0 0 1 Pin AHIGH_25_
|
||
1 3 1 Pin AHIGH_25_.OE
|
||
0 0 1 Pin AHIGH_24_
|
||
1 3 1 Pin AHIGH_24_.OE
|
||
1 9 1 Pin FPU_CS-
|
||
1 0 1 Pin AVEC
|
||
2 3 1 Pin E
|
||
0 0 1 Pin RESET
|
||
1 1 1 Pin RESET.OE
|
||
0 0 1 Pin AMIGA_ADDR_ENABLE
|
||
2 4 1 Pin AMIGA_BUS_DATA_DIR
|
||
1 2 1 Pin AMIGA_BUS_ENABLE_LOW-
|
||
2 3 1 Pin AMIGA_BUS_ENABLE_HIGH
|
||
1 13 1 Pin CIIN
|
||
1 1 1 Pin CIIN.OE
|
||
10 8 1 Pin IPL_030_2_.D-
|
||
1 1 1 Pin IPL_030_2_.C
|
||
1 2 1 Pin RW_000.OE
|
||
4 8 1 Pin RW_000.D-
|
||
1 1 1 Pin RW_000.C
|
||
2 6 1 Pin BG_000.D-
|
||
1 1 1 Pin BG_000.C
|
||
3 6 1 Pin BGACK_030.D
|
||
1 1 1 Pin BGACK_030.C
|
||
1 1 1 Pin CLK_EXP.D
|
||
1 1 1 Pin CLK_EXP.C
|
||
1 1 1 Pin DSACK1.OE
|
||
4 10 1 Pin DSACK1.D-
|
||
1 1 1 Pin DSACK1.C
|
||
3 9 1 Pin VMA.T
|
||
1 1 1 Pin VMA.C
|
||
1 2 1 Pin RW.OE
|
||
2 5 1 Pin RW.D-
|
||
1 1 1 Pin RW.C
|
||
1 3 1 Pin A_0_.OE
|
||
3 5 1 Pin A_0_.D
|
||
1 1 1 Pin A_0_.C
|
||
10 8 1 Pin IPL_030_1_.D-
|
||
1 1 1 Pin IPL_030_1_.C
|
||
10 8 1 Pin IPL_030_0_.D-
|
||
1 1 1 Pin IPL_030_0_.C
|
||
4 6 1 Node cpu_est_3_.D
|
||
1 1 1 Node cpu_est_3_.C
|
||
3 3 1 Node cpu_est_0_.D
|
||
1 1 1 Node cpu_est_0_.C
|
||
4 5 1 Node cpu_est_1_.D
|
||
1 1 1 Node cpu_est_1_.C
|
||
1 4 1 NodeX1 cpu_est_2_.D.X1
|
||
1 1 1 NodeX2 cpu_est_2_.D.X2
|
||
1 1 1 Node cpu_est_2_.C
|
||
2 7 1 Node inst_AS_000_INT.D-
|
||
1 1 1 Node inst_AS_000_INT.C
|
||
2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.D-
|
||
1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.C
|
||
1 2 1 Node inst_AS_030_D0.D-
|
||
1 1 1 Node inst_AS_030_D0.C
|
||
7 14 1 Node inst_AS_030_000_SYNC.D-
|
||
1 1 1 Node inst_AS_030_000_SYNC.C
|
||
1 2 1 Node inst_BGACK_030_INT_D.D-
|
||
1 1 1 Node inst_BGACK_030_INT_D.C
|
||
7 9 1 Node inst_AS_000_DMA.D
|
||
1 1 1 Node inst_AS_000_DMA.C
|
||
9 12 1 Node inst_DS_000_DMA.D
|
||
1 1 1 Node inst_DS_000_DMA.C
|
||
3 6 1 Node CYCLE_DMA_0_.D
|
||
1 1 1 Node CYCLE_DMA_0_.C
|
||
4 7 1 Node CYCLE_DMA_1_.D
|
||
1 1 1 Node CYCLE_DMA_1_.C
|
||
3 6 1 Node SIZE_DMA_0_.D-
|
||
1 1 1 Node SIZE_DMA_0_.C
|
||
3 6 1 Node SIZE_DMA_1_.D
|
||
1 1 1 Node SIZE_DMA_1_.C
|
||
1 2 1 Node inst_VPA_D.D-
|
||
1 1 1 Node inst_VPA_D.C
|
||
2 4 1 Node inst_UDS_000_INT.D-
|
||
1 1 1 Node inst_UDS_000_INT.C
|
||
3 6 1 Node inst_LDS_000_INT.D
|
||
1 1 1 Node inst_LDS_000_INT.C
|
||
1 1 1 Node inst_CLK_OUT_PRE_D.D
|
||
1 1 1 Node inst_CLK_OUT_PRE_D.C
|
||
1 1 1 Node CLK_000_D_1_.D
|
||
1 1 1 Node CLK_000_D_1_.C
|
||
1 1 1 Node CLK_000_D_10_.D
|
||
1 1 1 Node CLK_000_D_10_.C
|
||
1 1 1 Node CLK_000_D_11_.D
|
||
1 1 1 Node CLK_000_D_11_.C
|
||
1 2 1 Node inst_DTACK_D0.D-
|
||
1 1 1 Node inst_DTACK_D0.C
|
||
2 7 1 Node inst_RESET_OUT.D
|
||
1 1 1 Node inst_RESET_OUT.C
|
||
1 1 1 Node CLK_000_D_0_.D
|
||
1 1 1 Node CLK_000_D_0_.C
|
||
1 1 1 Node inst_CLK_OUT_PRE_50.D
|
||
1 1 1 Node inst_CLK_OUT_PRE_50.C
|
||
1 2 1 Node IPL_D0_0_.D-
|
||
1 1 1 Node IPL_D0_0_.C
|
||
1 2 1 Node IPL_D0_1_.D-
|
||
1 1 1 Node IPL_D0_1_.C
|
||
1 2 1 Node IPL_D0_2_.D-
|
||
1 1 1 Node IPL_D0_2_.C
|
||
1 1 1 Node CLK_000_D_2_.D
|
||
1 1 1 Node CLK_000_D_2_.C
|
||
1 1 1 Node CLK_000_D_3_.D
|
||
1 1 1 Node CLK_000_D_3_.C
|
||
1 1 1 Node CLK_000_D_4_.D
|
||
1 1 1 Node CLK_000_D_4_.C
|
||
1 1 1 Node CLK_000_D_5_.D
|
||
1 1 1 Node CLK_000_D_5_.C
|
||
1 1 1 Node CLK_000_D_6_.D
|
||
1 1 1 Node CLK_000_D_6_.C
|
||
1 1 1 Node CLK_000_D_7_.D
|
||
1 1 1 Node CLK_000_D_7_.C
|
||
1 1 1 Node CLK_000_D_8_.D
|
||
1 1 1 Node CLK_000_D_8_.C
|
||
1 1 1 Node CLK_000_D_9_.D
|
||
1 1 1 Node CLK_000_D_9_.C
|
||
1 1 1 Node CLK_000_D_12_.D
|
||
1 1 1 Node CLK_000_D_12_.C
|
||
2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.D-
|
||
1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.C
|
||
4 12 1 Node inst_DS_000_ENABLE.D
|
||
1 1 1 Node inst_DS_000_ENABLE.C
|
||
3 9 1 Node SM_AMIGA_6_.D
|
||
1 1 1 Node SM_AMIGA_6_.C
|
||
3 6 1 Node SM_AMIGA_0_.D
|
||
1 1 1 Node SM_AMIGA_0_.C
|
||
3 6 1 Node SM_AMIGA_4_.D
|
||
1 1 1 Node SM_AMIGA_4_.C
|
||
4 6 1 Node RST_DLY_0_.D
|
||
1 1 1 Node RST_DLY_0_.C
|
||
2 6 1 NodeX1 RST_DLY_1_.D.X1
|
||
1 2 1 NodeX2 RST_DLY_1_.D.X2
|
||
1 1 1 Node RST_DLY_1_.C
|
||
2 6 1 Node RST_DLY_2_.D
|
||
1 1 1 Node RST_DLY_2_.C
|
||
8 10 1 Node inst_CLK_030_H.D
|
||
1 1 1 Node inst_CLK_030_H.C
|
||
3 6 1 Node SM_AMIGA_1_.D
|
||
1 1 1 Node SM_AMIGA_1_.C
|
||
3 6 1 Node SM_AMIGA_5_.D
|
||
1 1 1 Node SM_AMIGA_5_.C
|
||
4 13 1 NodeX1 SM_AMIGA_3_.D.X1
|
||
1 3 1 NodeX2 SM_AMIGA_3_.D.X2
|
||
1 1 1 Node SM_AMIGA_3_.C
|
||
4 13 1 Node SM_AMIGA_2_.D
|
||
1 1 1 Node SM_AMIGA_2_.C
|
||
13 21 1 NodeX1 SM_AMIGA_i_7_.D.X1
|
||
1 2 1 NodeX2 SM_AMIGA_i_7_.D.X2
|
||
1 1 1 Node SM_AMIGA_i_7_.C
|
||
2 14 1 Node CIIN_0
|
||
=========
|
||
301 P-Term Total: 301
|
||
Total Pins: 61
|
||
Total Nodes: 53
|
||
Average P-Term/Output: 2
|
||
|
||
|
||
Equations:
|
||
|
||
SIZE_1_ = (!SIZE_DMA_0_.Q & SIZE_DMA_1_.Q);
|
||
|
||
SIZE_1_.OE = (!nEXP_SPACE & !BGACK_030.Q);
|
||
|
||
AHIGH_31_ = (0);
|
||
|
||
AHIGH_31_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
|
||
|
||
!AS_030 = (!inst_AS_000_DMA.Q & !AS_000.PIN);
|
||
|
||
AS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
|
||
|
||
!AS_000 = (!inst_AS_000_INT.Q & !AS_030.PIN);
|
||
|
||
AS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q);
|
||
|
||
!DS_030 = (!inst_DS_000_DMA.Q & !AS_000.PIN);
|
||
|
||
DS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
|
||
|
||
!UDS_000 = (!inst_UDS_000_INT.Q & inst_DS_000_ENABLE.Q);
|
||
|
||
UDS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q);
|
||
|
||
!LDS_000 = (!inst_LDS_000_INT.Q & inst_DS_000_ENABLE.Q);
|
||
|
||
LDS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q);
|
||
|
||
BERR = (0);
|
||
|
||
BERR.OE = (FC_1_ & BGACK_000 & FPU_SENSE & !A_DECODE_19_ & !A_DECODE_18_ & A_DECODE_17_ & !A_DECODE_16_ & FC_0_ & !AS_030.PIN);
|
||
|
||
SIZE_0_ = (SIZE_DMA_0_.Q & !SIZE_DMA_1_.Q);
|
||
|
||
SIZE_0_.OE = (!nEXP_SPACE & !BGACK_030.Q);
|
||
|
||
AHIGH_30_ = (0);
|
||
|
||
AHIGH_30_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
|
||
|
||
AHIGH_29_ = (0);
|
||
|
||
AHIGH_29_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
|
||
|
||
AHIGH_28_ = (0);
|
||
|
||
AHIGH_28_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
|
||
|
||
AHIGH_27_ = (0);
|
||
|
||
AHIGH_27_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
|
||
|
||
AHIGH_26_ = (0);
|
||
|
||
AHIGH_26_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
|
||
|
||
CLK_DIV_OUT.D = (inst_CLK_OUT_PRE_D.Q);
|
||
|
||
CLK_DIV_OUT.C = (CLK_OSZI);
|
||
|
||
AHIGH_25_ = (0);
|
||
|
||
AHIGH_25_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
|
||
|
||
AHIGH_24_ = (0);
|
||
|
||
AHIGH_24_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
|
||
|
||
!FPU_CS = (FC_1_ & BGACK_000 & !FPU_SENSE & !A_DECODE_19_ & !A_DECODE_18_ & A_DECODE_17_ & !A_DECODE_16_ & FC_0_ & !AS_030.PIN);
|
||
|
||
AVEC = (1);
|
||
|
||
E = (!cpu_est_3_.Q & cpu_est_1_.Q & cpu_est_2_.Q
|
||
# cpu_est_3_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q);
|
||
|
||
RESET = (0);
|
||
|
||
RESET.OE = (!inst_RESET_OUT.Q);
|
||
|
||
AMIGA_ADDR_ENABLE = (0);
|
||
|
||
AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW_000.PIN
|
||
# !nEXP_SPACE & !BGACK_030.Q & !AS_000.PIN & RW_000.PIN);
|
||
|
||
!AMIGA_BUS_ENABLE_LOW = (!BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_LOW.Q);
|
||
|
||
AMIGA_BUS_ENABLE_HIGH = (BGACK_030.Q & inst_AS_030_000_SYNC.Q
|
||
# !BGACK_030.Q & inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q);
|
||
|
||
CIIN = (A_DECODE_23_ & A_DECODE_22_ & A_DECODE_21_ & A_DECODE_20_ & !inst_AS_030_D0.Q & !AHIGH_24_.PIN & !AHIGH_25_.PIN & !AHIGH_26_.PIN & !AHIGH_27_.PIN & !AHIGH_28_.PIN & !AHIGH_29_.PIN & !AHIGH_30_.PIN & !AHIGH_31_.PIN);
|
||
|
||
CIIN.OE = (CIIN_0);
|
||
|
||
!IPL_030_2_.D = (!IPL_2_ & RST & !IPL_030_2_.Q
|
||
# RST & !IPL_D0_2_.Q & !IPL_030_2_.Q
|
||
# RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_2_.Q
|
||
# RST & IPL_0_ & !IPL_D0_0_.Q & !IPL_030_2_.Q
|
||
# RST & !IPL_1_ & IPL_D0_1_.Q & !IPL_030_2_.Q
|
||
# RST & IPL_1_ & !IPL_D0_1_.Q & !IPL_030_2_.Q
|
||
# !IPL_2_ & RST & IPL_1_ & IPL_0_ & IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q
|
||
# !IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q
|
||
# !IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q
|
||
# !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q);
|
||
|
||
IPL_030_2_.C = (CLK_OSZI);
|
||
|
||
RW_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q);
|
||
|
||
!RW_000.D = (RST & CLK_000_D_1_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q
|
||
# RST & !CLK_000_D_0_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q
|
||
# RST & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q
|
||
# RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & SM_AMIGA_i_7_.Q & !RW.PIN);
|
||
|
||
RW_000.C = (CLK_OSZI);
|
||
|
||
!BG_000.D = (!BG_030 & RST & !BG_000.Q
|
||
# nEXP_SPACE & !BG_030 & RST & inst_AS_030_D0.Q & CLK_000_D_0_.Q);
|
||
|
||
BG_000.C = (CLK_OSZI);
|
||
|
||
BGACK_030.D = (!RST
|
||
# BGACK_000 & BGACK_030.Q
|
||
# BGACK_000 & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & AS_000.PIN);
|
||
|
||
BGACK_030.C = (CLK_OSZI);
|
||
|
||
CLK_EXP.D = (inst_CLK_OUT_PRE_D.Q);
|
||
|
||
CLK_EXP.C = (CLK_OSZI);
|
||
|
||
DSACK1.OE = (nEXP_SPACE);
|
||
|
||
!DSACK1.D = (RST & !CLK_000_D_11_.Q & CLK_000_D_12_.Q & SM_AMIGA_1_.Q
|
||
# RST & !inst_AS_030_D0.Q & !DSACK1.Q & BERR.PIN
|
||
# !CLK_030 & RST & !CLK_000_D_10_.Q & CLK_000_D_11_.Q & SM_AMIGA_1_.Q
|
||
# RST & inst_CLK_OUT_PRE_D.Q & !CLK_000_D_10_.Q & CLK_000_D_11_.Q & SM_AMIGA_1_.Q);
|
||
|
||
DSACK1.C = (CLK_OSZI);
|
||
|
||
VMA.T = (!RST & !VMA.Q
|
||
# !VMA.Q & !cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !CLK_000_D_1_.Q & CLK_000_D_0_.Q
|
||
# RST & VMA.Q & !cpu_est_3_.Q & cpu_est_0_.Q & cpu_est_1_.Q & !cpu_est_2_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q);
|
||
|
||
VMA.C = (CLK_OSZI);
|
||
|
||
RW.OE = (!BGACK_030.Q & inst_RESET_OUT.Q);
|
||
|
||
!RW.D = (RST & !BGACK_030.Q & !RW_000.PIN
|
||
# RST & BGACK_030.Q & inst_BGACK_030_INT_D.Q & !RW.Q);
|
||
|
||
RW.C = (CLK_OSZI);
|
||
|
||
A_0_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q);
|
||
|
||
A_0_.D = (!RST
|
||
# !BGACK_030.Q & UDS_000.PIN
|
||
# BGACK_030.Q & inst_BGACK_030_INT_D.Q & A_0_.Q);
|
||
|
||
A_0_.C = (CLK_OSZI);
|
||
|
||
!IPL_030_1_.D = (RST & !IPL_1_ & !IPL_030_1_.Q
|
||
# RST & !IPL_D0_1_.Q & !IPL_030_1_.Q
|
||
# RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_1_.Q
|
||
# RST & IPL_0_ & !IPL_D0_0_.Q & !IPL_030_1_.Q
|
||
# !IPL_2_ & RST & IPL_D0_2_.Q & !IPL_030_1_.Q
|
||
# IPL_2_ & RST & !IPL_D0_2_.Q & !IPL_030_1_.Q
|
||
# IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q
|
||
# IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q
|
||
# !IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q
|
||
# !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q);
|
||
|
||
IPL_030_1_.C = (CLK_OSZI);
|
||
|
||
!IPL_030_0_.D = (RST & !IPL_0_ & !IPL_030_0_.Q
|
||
# RST & !IPL_D0_0_.Q & !IPL_030_0_.Q
|
||
# RST & !IPL_1_ & IPL_D0_1_.Q & !IPL_030_0_.Q
|
||
# RST & IPL_1_ & !IPL_D0_1_.Q & !IPL_030_0_.Q
|
||
# !IPL_2_ & RST & IPL_D0_2_.Q & !IPL_030_0_.Q
|
||
# IPL_2_ & RST & !IPL_D0_2_.Q & !IPL_030_0_.Q
|
||
# IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & IPL_D0_2_.Q
|
||
# IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q
|
||
# !IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q
|
||
# !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q);
|
||
|
||
IPL_030_0_.C = (CLK_OSZI);
|
||
|
||
cpu_est_3_.D = (cpu_est_3_.Q & !CLK_000_D_1_.Q
|
||
# cpu_est_3_.Q & CLK_000_D_0_.Q
|
||
# cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_2_.Q
|
||
# cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q);
|
||
|
||
cpu_est_3_.C = (CLK_OSZI);
|
||
|
||
cpu_est_0_.D = (cpu_est_0_.Q & !CLK_000_D_1_.Q
|
||
# cpu_est_0_.Q & CLK_000_D_0_.Q
|
||
# !cpu_est_0_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q);
|
||
|
||
cpu_est_0_.C = (CLK_OSZI);
|
||
|
||
cpu_est_1_.D = (!cpu_est_0_.Q & cpu_est_1_.Q
|
||
# cpu_est_1_.Q & !CLK_000_D_1_.Q
|
||
# cpu_est_1_.Q & CLK_000_D_0_.Q
|
||
# !cpu_est_3_.Q & cpu_est_0_.Q & !cpu_est_1_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q);
|
||
|
||
cpu_est_1_.C = (CLK_OSZI);
|
||
|
||
cpu_est_2_.D.X1 = (cpu_est_0_.Q & cpu_est_1_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q);
|
||
|
||
cpu_est_2_.D.X2 = (cpu_est_2_.Q);
|
||
|
||
cpu_est_2_.C = (CLK_OSZI);
|
||
|
||
!inst_AS_000_INT.D = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q
|
||
# RST & !inst_AS_000_INT.Q & !inst_AS_030_D0.Q & BERR.PIN);
|
||
|
||
inst_AS_000_INT.C = (CLK_OSZI);
|
||
|
||
!inst_AMIGA_BUS_ENABLE_DMA_LOW.D = (RST & A_1_ & !BGACK_030.Q
|
||
# RST & BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_LOW.Q & inst_BGACK_030_INT_D.Q);
|
||
|
||
inst_AMIGA_BUS_ENABLE_DMA_LOW.C = (CLK_OSZI);
|
||
|
||
!inst_AS_030_D0.D = (RST & !AS_030.PIN);
|
||
|
||
inst_AS_030_D0.C = (CLK_OSZI);
|
||
|
||
!inst_AS_030_000_SYNC.D = (RST & !inst_AS_030_D0.Q & !inst_AS_030_000_SYNC.Q & BERR.PIN
|
||
# !FC_1_ & nEXP_SPACE & RST & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
|
||
# nEXP_SPACE & RST & A_DECODE_19_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
|
||
# nEXP_SPACE & RST & A_DECODE_18_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
|
||
# nEXP_SPACE & RST & !A_DECODE_17_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
|
||
# nEXP_SPACE & RST & A_DECODE_16_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
|
||
# nEXP_SPACE & RST & !FC_0_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN);
|
||
|
||
inst_AS_030_000_SYNC.C = (CLK_OSZI);
|
||
|
||
!inst_BGACK_030_INT_D.D = (RST & !BGACK_030.Q);
|
||
|
||
inst_BGACK_030_INT_D.C = (CLK_OSZI);
|
||
|
||
inst_AS_000_DMA.D = (!RST
|
||
# BGACK_030.Q
|
||
# AS_000.PIN
|
||
# !CLK_030 & inst_AS_000_DMA.Q
|
||
# CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q
|
||
# !CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q
|
||
# UDS_000.PIN & LDS_000.PIN);
|
||
|
||
inst_AS_000_DMA.C = (CLK_OSZI);
|
||
|
||
inst_DS_000_DMA.D = (!RST
|
||
# BGACK_030.Q
|
||
# AS_000.PIN
|
||
# CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q
|
||
# !CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q
|
||
# UDS_000.PIN & LDS_000.PIN
|
||
# !CLK_030 & inst_DS_000_DMA.Q & !RW_000.PIN
|
||
# inst_DS_000_DMA.Q & !inst_CLK_030_H.Q & !RW_000.PIN
|
||
# CLK_030 & inst_AS_000_DMA.Q & inst_CLK_030_H.Q & !RW_000.PIN);
|
||
|
||
inst_DS_000_DMA.C = (CLK_OSZI);
|
||
|
||
CYCLE_DMA_0_.D = (RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & CLK_000_D_1_.Q & !AS_000.PIN
|
||
# RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CLK_000_D_0_.Q & !AS_000.PIN
|
||
# RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !AS_000.PIN);
|
||
|
||
CYCLE_DMA_0_.C = (CLK_OSZI);
|
||
|
||
CYCLE_DMA_1_.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_000.PIN
|
||
# RST & !BGACK_030.Q & CYCLE_DMA_1_.Q & CLK_000_D_1_.Q & !AS_000.PIN
|
||
# RST & !BGACK_030.Q & CYCLE_DMA_1_.Q & !CLK_000_D_0_.Q & !AS_000.PIN
|
||
# RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !AS_000.PIN);
|
||
|
||
CYCLE_DMA_1_.C = (CLK_OSZI);
|
||
|
||
!SIZE_DMA_0_.D = (RST & BGACK_030.Q & !inst_BGACK_030_INT_D.Q
|
||
# RST & BGACK_030.Q & !SIZE_DMA_0_.Q
|
||
# RST & !BGACK_030.Q & !UDS_000.PIN & !LDS_000.PIN);
|
||
|
||
SIZE_DMA_0_.C = (CLK_OSZI);
|
||
|
||
SIZE_DMA_1_.D = (!RST
|
||
# BGACK_030.Q & inst_BGACK_030_INT_D.Q & SIZE_DMA_1_.Q
|
||
# !BGACK_030.Q & !UDS_000.PIN & !LDS_000.PIN);
|
||
|
||
SIZE_DMA_1_.C = (CLK_OSZI);
|
||
|
||
!inst_VPA_D.D = (!VPA & RST);
|
||
|
||
inst_VPA_D.C = (CLK_OSZI);
|
||
|
||
!inst_UDS_000_INT.D = (RST & !inst_UDS_000_INT.Q & !SM_AMIGA_6_.Q
|
||
# RST & SM_AMIGA_6_.Q & !A_0_.PIN);
|
||
|
||
inst_UDS_000_INT.C = (CLK_OSZI);
|
||
|
||
inst_LDS_000_INT.D = (!RST
|
||
# inst_LDS_000_INT.Q & !SM_AMIGA_6_.Q
|
||
# SM_AMIGA_6_.Q & SIZE_0_.PIN & !SIZE_1_.PIN & !A_0_.PIN);
|
||
|
||
inst_LDS_000_INT.C = (CLK_OSZI);
|
||
|
||
inst_CLK_OUT_PRE_D.D = (inst_CLK_OUT_PRE_50.Q);
|
||
|
||
inst_CLK_OUT_PRE_D.C = (CLK_OSZI);
|
||
|
||
CLK_000_D_1_.D = (CLK_000_D_0_.Q);
|
||
|
||
CLK_000_D_1_.C = (CLK_OSZI);
|
||
|
||
CLK_000_D_10_.D = (CLK_000_D_9_.Q);
|
||
|
||
CLK_000_D_10_.C = (CLK_OSZI);
|
||
|
||
CLK_000_D_11_.D = (CLK_000_D_10_.Q);
|
||
|
||
CLK_000_D_11_.C = (CLK_OSZI);
|
||
|
||
!inst_DTACK_D0.D = (!DTACK & RST);
|
||
|
||
inst_DTACK_D0.C = (CLK_OSZI);
|
||
|
||
inst_RESET_OUT.D = (RST & inst_RESET_OUT.Q
|
||
# RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q);
|
||
|
||
inst_RESET_OUT.C = (CLK_OSZI);
|
||
|
||
CLK_000_D_0_.D = (CLK_000);
|
||
|
||
CLK_000_D_0_.C = (CLK_OSZI);
|
||
|
||
inst_CLK_OUT_PRE_50.D = (!inst_CLK_OUT_PRE_50.Q);
|
||
|
||
inst_CLK_OUT_PRE_50.C = (CLK_OSZI);
|
||
|
||
!IPL_D0_0_.D = (RST & !IPL_0_);
|
||
|
||
IPL_D0_0_.C = (CLK_OSZI);
|
||
|
||
!IPL_D0_1_.D = (RST & !IPL_1_);
|
||
|
||
IPL_D0_1_.C = (CLK_OSZI);
|
||
|
||
!IPL_D0_2_.D = (!IPL_2_ & RST);
|
||
|
||
IPL_D0_2_.C = (CLK_OSZI);
|
||
|
||
CLK_000_D_2_.D = (CLK_000_D_1_.Q);
|
||
|
||
CLK_000_D_2_.C = (CLK_OSZI);
|
||
|
||
CLK_000_D_3_.D = (CLK_000_D_2_.Q);
|
||
|
||
CLK_000_D_3_.C = (CLK_OSZI);
|
||
|
||
CLK_000_D_4_.D = (CLK_000_D_3_.Q);
|
||
|
||
CLK_000_D_4_.C = (CLK_OSZI);
|
||
|
||
CLK_000_D_5_.D = (CLK_000_D_4_.Q);
|
||
|
||
CLK_000_D_5_.C = (CLK_OSZI);
|
||
|
||
CLK_000_D_6_.D = (CLK_000_D_5_.Q);
|
||
|
||
CLK_000_D_6_.C = (CLK_OSZI);
|
||
|
||
CLK_000_D_7_.D = (CLK_000_D_6_.Q);
|
||
|
||
CLK_000_D_7_.C = (CLK_OSZI);
|
||
|
||
CLK_000_D_8_.D = (CLK_000_D_7_.Q);
|
||
|
||
CLK_000_D_8_.C = (CLK_OSZI);
|
||
|
||
CLK_000_D_9_.D = (CLK_000_D_8_.Q);
|
||
|
||
CLK_000_D_9_.C = (CLK_OSZI);
|
||
|
||
CLK_000_D_12_.D = (CLK_000_D_11_.Q);
|
||
|
||
CLK_000_D_12_.C = (CLK_OSZI);
|
||
|
||
!inst_AMIGA_BUS_ENABLE_DMA_HIGH.D = (RST & !A_1_ & !BGACK_030.Q
|
||
# RST & BGACK_030.Q & inst_BGACK_030_INT_D.Q & !inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q);
|
||
|
||
inst_AMIGA_BUS_ENABLE_DMA_HIGH.C = (CLK_OSZI);
|
||
|
||
inst_DS_000_ENABLE.D = (RST & !inst_AS_030_D0.Q & inst_DS_000_ENABLE.Q & BERR.PIN
|
||
# RST & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_5_.Q & SM_AMIGA_i_7_.Q
|
||
# RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_5_.Q & SM_AMIGA_i_7_.Q
|
||
# RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_5_.Q & SM_AMIGA_i_7_.Q & RW.PIN);
|
||
|
||
inst_DS_000_ENABLE.C = (CLK_OSZI);
|
||
|
||
SM_AMIGA_6_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q & BERR.PIN
|
||
# RST & !CLK_000_D_0_.Q & SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q & BERR.PIN
|
||
# nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_1_.Q & CLK_000_D_2_.Q & !SM_AMIGA_i_7_.Q);
|
||
|
||
SM_AMIGA_6_.C = (CLK_OSZI);
|
||
|
||
SM_AMIGA_0_.D = (RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_1_.Q
|
||
# RST & CLK_000_D_1_.Q & SM_AMIGA_0_.Q & BERR.PIN
|
||
# RST & !CLK_000_D_0_.Q & SM_AMIGA_0_.Q & BERR.PIN);
|
||
|
||
SM_AMIGA_0_.C = (CLK_OSZI);
|
||
|
||
SM_AMIGA_4_.D = (RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_5_.Q
|
||
# RST & CLK_000_D_1_.Q & SM_AMIGA_4_.Q & BERR.PIN
|
||
# RST & !CLK_000_D_0_.Q & SM_AMIGA_4_.Q & BERR.PIN);
|
||
|
||
SM_AMIGA_4_.C = (CLK_OSZI);
|
||
|
||
RST_DLY_0_.D = (RST & !CLK_000_D_1_.Q & RST_DLY_0_.Q
|
||
# RST & CLK_000_D_0_.Q & RST_DLY_0_.Q
|
||
# RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & !RST_DLY_0_.Q
|
||
# RST & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q);
|
||
|
||
RST_DLY_0_.C = (CLK_OSZI);
|
||
|
||
RST_DLY_1_.D.X1 = (RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & RST_DLY_0_.Q & !RST_DLY_1_.Q
|
||
# RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & RST_DLY_0_.Q & !RST_DLY_2_.Q);
|
||
|
||
RST_DLY_1_.D.X2 = (RST & RST_DLY_1_.Q);
|
||
|
||
RST_DLY_1_.C = (CLK_OSZI);
|
||
|
||
RST_DLY_2_.D = (RST & RST_DLY_2_.Q
|
||
# RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & RST_DLY_0_.Q & RST_DLY_1_.Q);
|
||
|
||
RST_DLY_2_.C = (CLK_OSZI);
|
||
|
||
inst_CLK_030_H.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !UDS_000.PIN
|
||
# RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !UDS_000.PIN
|
||
# RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !LDS_000.PIN
|
||
# RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !LDS_000.PIN
|
||
# !CLK_030 & RST & !BGACK_030.Q & !inst_AS_000_DMA.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_000.PIN & !UDS_000.PIN
|
||
# !CLK_030 & RST & !BGACK_030.Q & !inst_AS_000_DMA.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & !AS_000.PIN & !UDS_000.PIN
|
||
# !CLK_030 & RST & !BGACK_030.Q & !inst_AS_000_DMA.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_000.PIN & !LDS_000.PIN
|
||
# !CLK_030 & RST & !BGACK_030.Q & !inst_AS_000_DMA.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & !AS_000.PIN & !LDS_000.PIN);
|
||
|
||
inst_CLK_030_H.C = (CLK_OSZI);
|
||
|
||
SM_AMIGA_1_.D = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_2_.Q
|
||
# RST & !CLK_000_D_1_.Q & SM_AMIGA_1_.Q & BERR.PIN
|
||
# RST & CLK_000_D_0_.Q & SM_AMIGA_1_.Q & BERR.PIN);
|
||
|
||
SM_AMIGA_1_.C = (CLK_OSZI);
|
||
|
||
SM_AMIGA_5_.D = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q
|
||
# RST & !CLK_000_D_1_.Q & SM_AMIGA_5_.Q & BERR.PIN
|
||
# RST & CLK_000_D_0_.Q & SM_AMIGA_5_.Q & BERR.PIN);
|
||
|
||
SM_AMIGA_5_.C = (CLK_OSZI);
|
||
|
||
SM_AMIGA_3_.D.X1 = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_4_.Q & !SM_AMIGA_3_.Q
|
||
# RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_4_.Q & !BERR.PIN
|
||
# RST & inst_VPA_D.Q & CLK_000_D_1_.Q & !inst_DTACK_D0.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & BERR.PIN
|
||
# RST & !VMA.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & BERR.PIN);
|
||
|
||
SM_AMIGA_3_.D.X2 = (RST & SM_AMIGA_3_.Q & BERR.PIN);
|
||
|
||
SM_AMIGA_3_.C = (CLK_OSZI);
|
||
|
||
SM_AMIGA_2_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_2_.Q & BERR.PIN
|
||
# RST & !CLK_000_D_0_.Q & SM_AMIGA_2_.Q & BERR.PIN
|
||
# RST & inst_VPA_D.Q & CLK_000_D_1_.Q & !inst_DTACK_D0.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q
|
||
# RST & !VMA.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q);
|
||
|
||
SM_AMIGA_2_.C = (CLK_OSZI);
|
||
|
||
SM_AMIGA_i_7_.D.X1 = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q & !BERR.PIN
|
||
# RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_4_.Q & !BERR.PIN
|
||
# RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_1_.Q & !BERR.PIN
|
||
# RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_5_.Q & !BERR.PIN
|
||
# RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_2_.Q & !BERR.PIN
|
||
# RST & inst_VPA_D.Q & CLK_000_D_1_.Q & !inst_DTACK_D0.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & !BERR.PIN
|
||
# !nEXP_SPACE & RST & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & BERR.PIN
|
||
# RST & inst_AS_030_000_SYNC.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & BERR.PIN
|
||
# RST & CLK_000_D_1_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & BERR.PIN
|
||
# RST & !CLK_000_D_2_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & BERR.PIN
|
||
# RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !SM_AMIGA_6_.Q & SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & BERR.PIN
|
||
# RST & !VMA.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & !BERR.PIN
|
||
# nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_1_.Q & CLK_000_D_2_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & !BERR.PIN);
|
||
|
||
SM_AMIGA_i_7_.D.X2 = (RST & BERR.PIN);
|
||
|
||
SM_AMIGA_i_7_.C = (CLK_OSZI);
|
||
|
||
CIIN_0 = (nEXP_SPACE
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# A_DECODE_23_ & A_DECODE_22_ & A_DECODE_21_ & A_DECODE_20_ & !inst_AS_030_D0.Q & !AHIGH_24_.PIN & !AHIGH_25_.PIN & !AHIGH_26_.PIN & !AHIGH_27_.PIN & !AHIGH_28_.PIN & !AHIGH_29_.PIN & !AHIGH_30_.PIN & !AHIGH_31_.PIN);
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Reverse-Polarity Equations:
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