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591 lines
19 KiB
Plaintext
591 lines
19 KiB
Plaintext
ispLEVER Classic 1.7.00.05.28.13 Linked Equations File
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Copyright(C), 1992-2013, Lattice Semiconductor Corp.
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All Rights Reserved.
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Design bus68030 created Sun Jun 01 01:03:24 2014
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P-Terms Fan-in Fan-out Type Name (attributes)
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--------- ------ ------- ---- -----------------
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1 1 1 Pin RW_000
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1 1 1 Pin RW_000.OE
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0 0 1 Pin BERR
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1 1 1 Pin BERR.OE
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1 1 1 Pin CLK_DIV_OUT.AR
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1 1 1 Pin CLK_DIV_OUT.D
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1 1 1 Pin CLK_DIV_OUT.C
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1 1 1 Pin DTACK
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1 3 1 Pin DTACK.OE
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1 0 1 Pin AVEC
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3 8 1 Pin AVEC_EXP.D-
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1 1 1 Pin AVEC_EXP.AP
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1 1 1 Pin AVEC_EXP.C
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1 1 1 Pin RW
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1 1 1 Pin RW.OE
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1 1 1 Pin AMIGA_BUS_ENABLE
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2 4 1 Pin AMIGA_BUS_DATA_DIR
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1 0 1 Pin AMIGA_BUS_ENABLE_LOW
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1 4 1 Pin CIIN
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1 8 1 Pin CIIN.OE
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1 3 1 Pin SIZE_1_.OE
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2 4 1 Pin SIZE_1_.D-
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1 1 1 Pin SIZE_1_.AP
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1 1 1 Pin SIZE_1_.C
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3 4 1 Pin IPL_030_2_.D
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1 1 1 Pin IPL_030_2_.AP
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1 1 1 Pin IPL_030_2_.C
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1 3 1 Pin AS_030.OE
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4 6 1 Pin AS_030.D
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1 1 1 Pin AS_030.AP
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1 1 1 Pin AS_030.C
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3 4 1 Pin IPL_030_1_.D
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1 1 1 Pin IPL_030_1_.AP
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1 1 1 Pin IPL_030_1_.C
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1 1 1 Pin AS_000.OE
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2 4 1 Pin AS_000.D-
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1 1 1 Pin AS_000.AP
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1 1 1 Pin AS_000.C
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3 4 1 Pin IPL_030_0_.D
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1 1 1 Pin IPL_030_0_.AP
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1 1 1 Pin IPL_030_0_.C
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1 3 1 Pin DS_030.OE
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7 9 1 Pin DS_030.D
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1 1 1 Pin DS_030.AP
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1 1 1 Pin DS_030.C
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1 1 1 Pin UDS_000.OE
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7 9 1 Pin UDS_000.D-
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1 1 1 Pin UDS_000.AP
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1 1 1 Pin UDS_000.C
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1 1 1 Pin LDS_000.OE
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11 11 1 Pin LDS_000.D-
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1 1 1 Pin LDS_000.AP
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1 1 1 Pin LDS_000.C
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1 3 1 Pin A0.OE
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1 4 1 Pin A0.D
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1 1 1 Pin A0.AP
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1 1 1 Pin A0.C
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2 6 1 Pin BG_000.D-
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1 1 1 Pin BG_000.AP
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1 1 1 Pin BG_000.C
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2 4 1 Pin BGACK_030.D
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1 1 1 Pin BGACK_030.AP
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1 1 1 Pin BGACK_030.C
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1 1 1 Pin CLK_EXP.AR
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1 1 1 Pin CLK_EXP.D
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1 1 1 Pin CLK_EXP.C
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2 10 1 Pin FPU_CS.D-
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1 1 1 Pin FPU_CS.AP
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1 1 1 Pin FPU_CS.C
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1 1 1 Pin DSACK1.OE
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2 4 1 Pin DSACK1.D-
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1 1 1 Pin DSACK1.AP
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1 1 1 Pin DSACK1.C
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3 6 1 PinX1 E.D.X1
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1 1 1 PinX2 E.D.X2
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1 1 1 Pin E.AR
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1 1 1 Pin E.C
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2 7 1 PinX1 VMA.D.X1
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1 5 1 PinX2 VMA.D.X2
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1 1 1 Pin VMA.AP
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1 1 1 Pin VMA.C
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1 1 1 Pin RESET.AR
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1 0 1 Pin RESET.D
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1 1 1 Pin RESET.C
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1 3 1 Pin SIZE_0_.OE
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1 4 1 Pin SIZE_0_.D-
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1 1 1 Pin SIZE_0_.AP
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1 1 1 Pin SIZE_0_.C
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8 17 1 Node inst_AS_030_000_SYNC.D
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1 1 1 Node inst_AS_030_000_SYNC.AP
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1 1 1 Node inst_AS_030_000_SYNC.C
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1 1 1 Node inst_BGACK_030_INT_D.D
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1 1 1 Node inst_BGACK_030_INT_D.AP
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1 1 1 Node inst_BGACK_030_INT_D.C
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1 1 1 Node inst_VPA_D.D
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1 1 1 Node inst_VPA_D.AP
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1 1 1 Node inst_VPA_D.C
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1 1 1 Node inst_CLK_OUT_PRE_50_D.AR
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1 1 1 Node inst_CLK_OUT_PRE_50_D.D
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1 1 1 Node inst_CLK_OUT_PRE_50_D.C
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1 1 1 Node inst_CLK_000_D0.D
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1 1 1 Node inst_CLK_000_D0.AP
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1 1 1 Node inst_CLK_000_D0.C
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1 1 1 Node inst_CLK_000_D1.D
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1 1 1 Node inst_CLK_000_D1.AP
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1 1 1 Node inst_CLK_000_D1.C
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1 1 1 Node inst_CLK_000_D2.D
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1 1 1 Node inst_CLK_000_D2.AP
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1 1 1 Node inst_CLK_000_D2.C
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1 1 1 Node inst_DTACK_D0.D
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1 1 1 Node inst_DTACK_D0.AP
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1 1 1 Node inst_DTACK_D0.C
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1 1 1 Node inst_CLK_OUT_PRE_50.AR
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1 1 1 Node inst_CLK_OUT_PRE_50.D
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1 1 1 Node inst_CLK_OUT_PRE_50.C
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1 1 1 Node inst_CLK_OUT_PRE_25.AR
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3 3 1 Node inst_CLK_OUT_PRE_25.D
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1 1 1 Node inst_CLK_OUT_PRE_25.C
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4 7 1 Node SM_AMIGA_7_.D-
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1 1 1 Node SM_AMIGA_7_.AP
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1 1 1 Node SM_AMIGA_7_.C
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1 1 1 Node SM_AMIGA_6_.AR
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2 7 1 Node SM_AMIGA_6_.D
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1 1 1 Node SM_AMIGA_6_.C
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1 1 1 Node SM_AMIGA_0_.AR
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2 3 1 Node SM_AMIGA_0_.D
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1 1 1 Node SM_AMIGA_0_.C
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1 1 1 Node SM_AMIGA_5_.AR
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2 3 1 Node SM_AMIGA_5_.D
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1 1 1 Node SM_AMIGA_5_.C
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1 1 1 Node SM_AMIGA_2_.AR
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3 9 1 Node SM_AMIGA_2_.D
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1 1 1 Node SM_AMIGA_2_.C
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14 11 1 Node inst_RW_000_INT.D-
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1 1 1 Node inst_RW_000_INT.AP
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1 1 1 Node inst_RW_000_INT.C
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1 1 1 Node inst_CLK_000_D3.D
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1 1 1 Node inst_CLK_000_D3.AP
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1 1 1 Node inst_CLK_000_D3.C
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5 8 1 Node inst_CLK_030_H.D
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1 1 1 Node inst_CLK_030_H.C
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1 1 1 Node SM_AMIGA_4_.AR
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2 3 1 Node SM_AMIGA_4_.D
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1 1 1 Node SM_AMIGA_4_.C
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1 1 1 Node SM_AMIGA_3_.AR
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4 9 1 Node SM_AMIGA_3_.D-
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1 1 1 Node SM_AMIGA_3_.C
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1 1 1 Node SM_AMIGA_1_.AR
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2 3 1 Node SM_AMIGA_1_.D
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1 1 1 Node SM_AMIGA_1_.C
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1 1 1 Node cpu_est_0_.AR
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3 3 1 Node cpu_est_0_.D
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1 1 1 Node cpu_est_0_.C
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1 1 1 Node cpu_est_1_.AR
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4 6 1 Node cpu_est_1_.T
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1 1 1 Node cpu_est_1_.C
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3 6 1 NodeX1 cpu_est_2_.D.X1
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1 1 1 NodeX2 cpu_est_2_.D.X2
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1 1 1 Node cpu_est_2_.AR
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1 1 1 Node cpu_est_2_.C
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=========
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248 P-Term Total: 248
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Total Pins: 59
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Total Nodes: 24
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Average P-Term/Output: 2
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Equations:
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RW_000 = (inst_RW_000_INT.Q);
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RW_000.OE = (BGACK_030.Q);
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BERR = (0);
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BERR.OE = (!FPU_CS.Q);
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CLK_DIV_OUT.AR = (!RST);
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CLK_DIV_OUT.D = (inst_CLK_OUT_PRE_25.Q);
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CLK_DIV_OUT.C = (CLK_OSZI);
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DTACK = (DSACK1.PIN);
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DTACK.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q);
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AVEC = (1);
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!AVEC_EXP.D = (!BGACK_030.Q
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# inst_BGACK_030_INT_D.Q & !SM_AMIGA_7_.Q & !AVEC_EXP
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# nEXP_SPACE & !inst_AS_030_000_SYNC.Q & inst_BGACK_030_INT_D.Q & !inst_CLK_000_D2.Q & SM_AMIGA_7_.Q & inst_CLK_000_D3.Q);
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AVEC_EXP.AP = (!RST);
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AVEC_EXP.C = (CLK_OSZI);
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RW = (inst_RW_000_INT.Q);
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RW.OE = (!BGACK_030.Q);
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AMIGA_BUS_ENABLE = (AVEC_EXP);
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AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW.PIN
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# !nEXP_SPACE & !BGACK_030.Q & !AS_000.PIN & RW.PIN);
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AMIGA_BUS_ENABLE_LOW = (1);
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CIIN = (A_23_ & A_22_ & A_21_ & A_20_);
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CIIN.OE = (!A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_);
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SIZE_1_.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q);
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!SIZE_1_.D = (!BGACK_030.Q & !AS_000.PIN & !UDS_000.PIN & LDS_000.PIN
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# !BGACK_030.Q & !AS_000.PIN & UDS_000.PIN & !LDS_000.PIN);
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SIZE_1_.AP = (!RST);
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SIZE_1_.C = (CLK_OSZI);
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IPL_030_2_.D = (!inst_CLK_000_D0.Q & IPL_030_2_.Q
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# inst_CLK_000_D1.Q & IPL_030_2_.Q
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# IPL_2_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q);
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IPL_030_2_.AP = (!RST);
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IPL_030_2_.C = (CLK_OSZI);
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AS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q);
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AS_030.D = (BGACK_030.Q
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# AS_000.PIN
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# CLK_030 & AS_030.Q
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# UDS_000.PIN & LDS_000.PIN);
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AS_030.AP = (!RST);
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AS_030.C = (CLK_OSZI);
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IPL_030_1_.D = (!inst_CLK_000_D0.Q & IPL_030_1_.Q
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# inst_CLK_000_D1.Q & IPL_030_1_.Q
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# IPL_1_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q);
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IPL_030_1_.AP = (!RST);
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IPL_030_1_.C = (CLK_OSZI);
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AS_000.OE = (BGACK_030.Q);
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!AS_000.D = (inst_CLK_000_D2.Q & SM_AMIGA_5_.Q
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# !AS_000.Q & !AS_030.PIN);
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AS_000.AP = (!RST);
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AS_000.C = (CLK_OSZI);
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IPL_030_0_.D = (!inst_CLK_000_D0.Q & IPL_030_0_.Q
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# inst_CLK_000_D1.Q & IPL_030_0_.Q
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# IPL_0_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q);
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IPL_030_0_.AP = (!RST);
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IPL_030_0_.C = (CLK_OSZI);
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DS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q);
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DS_030.D = (BGACK_030.Q
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# AS_000.PIN
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# AS_030.Q & RW_000.PIN
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# UDS_000.PIN & LDS_000.PIN
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# !CLK_030 & AS_030.Q & inst_CLK_030_H.Q
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# CLK_030 & DS_030.Q & !RW_000.PIN
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# !inst_CLK_030_H.Q & DS_030.Q & !RW_000.PIN);
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DS_030.AP = (!RST);
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DS_030.C = (CLK_OSZI);
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UDS_000.OE = (BGACK_030.Q);
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!UDS_000.D = (!UDS_000.Q & !AS_030.PIN & DS_030.PIN
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# !inst_CLK_000_D2.Q & !UDS_000.Q & !AS_030.PIN & RW.PIN
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# !SM_AMIGA_5_.Q & !UDS_000.Q & !AS_030.PIN & RW.PIN
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# !inst_CLK_000_D0.Q & !UDS_000.Q & !AS_030.PIN & !RW.PIN
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# !UDS_000.Q & !SM_AMIGA_4_.Q & !AS_030.PIN & !RW.PIN
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# inst_CLK_000_D2.Q & SM_AMIGA_5_.Q & !DS_030.PIN & !A0.PIN & RW.PIN
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# inst_CLK_000_D0.Q & SM_AMIGA_4_.Q & !DS_030.PIN & !A0.PIN & !RW.PIN);
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UDS_000.AP = (!RST);
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UDS_000.C = (CLK_OSZI);
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LDS_000.OE = (BGACK_030.Q);
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!LDS_000.D = (!LDS_000.Q & !AS_030.PIN & DS_030.PIN
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# !inst_CLK_000_D2.Q & !LDS_000.Q & !AS_030.PIN & RW.PIN
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# !SM_AMIGA_5_.Q & !LDS_000.Q & !AS_030.PIN & RW.PIN
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# !inst_CLK_000_D0.Q & !LDS_000.Q & !AS_030.PIN & !RW.PIN
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# !LDS_000.Q & !SM_AMIGA_4_.Q & !AS_030.PIN & !RW.PIN
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# inst_CLK_000_D2.Q & SM_AMIGA_5_.Q & !DS_030.PIN & !SIZE_0_.PIN & RW.PIN
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# inst_CLK_000_D2.Q & SM_AMIGA_5_.Q & !DS_030.PIN & SIZE_1_.PIN & RW.PIN
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# inst_CLK_000_D2.Q & SM_AMIGA_5_.Q & !DS_030.PIN & A0.PIN & RW.PIN
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# inst_CLK_000_D0.Q & SM_AMIGA_4_.Q & !DS_030.PIN & !SIZE_0_.PIN & !RW.PIN
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# inst_CLK_000_D0.Q & SM_AMIGA_4_.Q & !DS_030.PIN & SIZE_1_.PIN & !RW.PIN
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# inst_CLK_000_D0.Q & SM_AMIGA_4_.Q & !DS_030.PIN & A0.PIN & !RW.PIN);
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LDS_000.AP = (!RST);
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LDS_000.C = (CLK_OSZI);
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A0.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q);
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A0.D = (!BGACK_030.Q & !AS_000.PIN & UDS_000.PIN & !LDS_000.PIN);
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A0.AP = (!RST);
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A0.C = (CLK_OSZI);
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!BG_000.D = (!BG_030 & !BG_000.Q
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# nEXP_SPACE & !BG_030 & CLK_000 & SM_AMIGA_7_.Q & AS_030.PIN);
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BG_000.AP = (!RST);
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BG_000.C = (CLK_OSZI);
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BGACK_030.D = (BGACK_000 & BGACK_030.Q
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# BGACK_000 & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q);
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BGACK_030.AP = (!RST);
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BGACK_030.C = (CLK_OSZI);
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CLK_EXP.AR = (!RST);
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CLK_EXP.D = (inst_CLK_OUT_PRE_25.Q);
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CLK_EXP.C = (CLK_OSZI);
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!FPU_CS.D = (!FPU_CS.Q & !AS_030.PIN
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# FC_1_ & BGACK_000 & CLK_030 & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN);
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FPU_CS.AP = (!RST);
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FPU_CS.C = (CLK_OSZI);
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DSACK1.OE = (nEXP_SPACE);
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!DSACK1.D = (inst_CLK_000_D0.Q & SM_AMIGA_2_.Q
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# !DSACK1.Q & !AS_030.PIN);
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DSACK1.AP = (!RST);
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DSACK1.C = (CLK_OSZI);
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E.D.X1 = (inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_1_.Q & cpu_est_2_.Q & E.Q
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# inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_0_.Q & !cpu_est_2_.Q & !E.Q
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# inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !E.Q);
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E.D.X2 = (E.Q);
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E.AR = (!RST);
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E.C = (CLK_OSZI);
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VMA.D.X1 = (VMA.Q
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# !VMA.Q & inst_CLK_000_D0.Q & AS_000.Q & !cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & !E.Q);
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VMA.D.X2 = (VMA.Q & !inst_VPA_D.Q & !inst_CLK_000_D0.Q & cpu_est_0_.Q & !cpu_est_1_.Q);
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VMA.AP = (!RST);
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VMA.C = (CLK_OSZI);
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RESET.AR = (!RST);
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RESET.D = (1);
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RESET.C = (CLK_OSZI);
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SIZE_0_.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q);
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!SIZE_0_.D = (!BGACK_030.Q & !AS_000.PIN & !UDS_000.PIN & !LDS_000.PIN);
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SIZE_0_.AP = (!RST);
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SIZE_0_.C = (CLK_OSZI);
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inst_AS_030_000_SYNC.D = (AS_030.PIN
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# !nEXP_SPACE & inst_AS_030_000_SYNC.Q
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# !CLK_030 & inst_AS_030_000_SYNC.Q
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# !BGACK_030.Q & inst_AS_030_000_SYNC.Q
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# inst_AS_030_000_SYNC.Q & !SM_AMIGA_7_.Q
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# inst_CLK_000_D0.Q & SM_AMIGA_2_.Q
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# !nEXP_SPACE & !inst_CLK_000_D2.Q & SM_AMIGA_7_.Q & inst_CLK_000_D3.Q
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# FC_1_ & BGACK_000 & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & inst_AS_030_000_SYNC.Q);
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inst_AS_030_000_SYNC.AP = (!RST);
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inst_AS_030_000_SYNC.C = (CLK_OSZI);
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inst_BGACK_030_INT_D.D = (BGACK_030.Q);
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inst_BGACK_030_INT_D.AP = (!RST);
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inst_BGACK_030_INT_D.C = (CLK_OSZI);
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inst_VPA_D.D = (VPA);
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inst_VPA_D.AP = (!RST);
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inst_VPA_D.C = (CLK_OSZI);
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inst_CLK_OUT_PRE_50_D.AR = (!RST);
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inst_CLK_OUT_PRE_50_D.D = (inst_CLK_OUT_PRE_50.Q);
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inst_CLK_OUT_PRE_50_D.C = (CLK_OSZI);
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inst_CLK_000_D0.D = (CLK_000);
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inst_CLK_000_D0.AP = (!RST);
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inst_CLK_000_D0.C = (CLK_OSZI);
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inst_CLK_000_D1.D = (inst_CLK_000_D0.Q);
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inst_CLK_000_D1.AP = (!RST);
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inst_CLK_000_D1.C = (CLK_OSZI);
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inst_CLK_000_D2.D = (inst_CLK_000_D1.Q);
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inst_CLK_000_D2.AP = (!RST);
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inst_CLK_000_D2.C = (CLK_OSZI);
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inst_DTACK_D0.D = (DTACK.PIN);
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inst_DTACK_D0.AP = (!RST);
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inst_DTACK_D0.C = (CLK_OSZI);
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inst_CLK_OUT_PRE_50.AR = (!RST);
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inst_CLK_OUT_PRE_50.D = (!inst_CLK_OUT_PRE_50.Q);
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inst_CLK_OUT_PRE_50.C = (CLK_OSZI);
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inst_CLK_OUT_PRE_25.AR = (!RST);
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inst_CLK_OUT_PRE_25.D = (inst_CLK_OUT_PRE_50_D.Q & inst_CLK_OUT_PRE_25.Q
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# !inst_CLK_OUT_PRE_50.Q & inst_CLK_OUT_PRE_25.Q
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# !inst_CLK_OUT_PRE_50_D.Q & inst_CLK_OUT_PRE_50.Q & !inst_CLK_OUT_PRE_25.Q);
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inst_CLK_OUT_PRE_25.C = (CLK_OSZI);
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!SM_AMIGA_7_.D = (!inst_CLK_000_D0.Q & !SM_AMIGA_7_.Q
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# !SM_AMIGA_7_.Q & !SM_AMIGA_0_.Q
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# nEXP_SPACE & !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D0.Q & !inst_CLK_000_D2.Q & inst_CLK_000_D3.Q
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# nEXP_SPACE & !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D2.Q & !SM_AMIGA_0_.Q & inst_CLK_000_D3.Q);
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SM_AMIGA_7_.AP = (!RST);
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SM_AMIGA_7_.C = (CLK_OSZI);
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SM_AMIGA_6_.AR = (!RST);
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SM_AMIGA_6_.D = (!inst_CLK_000_D0.Q & !SM_AMIGA_7_.Q & SM_AMIGA_6_.Q
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# nEXP_SPACE & !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D2.Q & SM_AMIGA_7_.Q & inst_CLK_000_D3.Q);
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SM_AMIGA_6_.C = (CLK_OSZI);
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SM_AMIGA_0_.AR = (!RST);
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SM_AMIGA_0_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_0_.Q
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# !inst_CLK_000_D0.Q & SM_AMIGA_1_.Q);
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SM_AMIGA_0_.C = (CLK_OSZI);
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SM_AMIGA_5_.AR = (!RST);
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SM_AMIGA_5_.D = (inst_CLK_000_D0.Q & SM_AMIGA_6_.Q
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# inst_CLK_000_D0.Q & SM_AMIGA_5_.Q);
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SM_AMIGA_5_.C = (CLK_OSZI);
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SM_AMIGA_2_.AR = (!RST);
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SM_AMIGA_2_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_2_.Q
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# inst_VPA_D.Q & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & !inst_DTACK_D0.Q & SM_AMIGA_3_.Q
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# !VMA.Q & !inst_VPA_D.Q & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & SM_AMIGA_3_.Q & !cpu_est_1_.Q & E.Q);
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SM_AMIGA_2_.C = (CLK_OSZI);
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!inst_RW_000_INT.D = (CLK_030 & !inst_CLK_000_D0.Q & !inst_RW_000_INT.Q
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# BGACK_030.Q & !inst_CLK_000_D0.Q & !inst_RW_000_INT.Q
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# !inst_CLK_000_D0.Q & !inst_RW_000_INT.Q & AS_000.PIN
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# CLK_030 & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !inst_RW_000_INT.Q
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# BGACK_030.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !inst_RW_000_INT.Q
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# !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !inst_RW_000_INT.Q & AS_000.PIN
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# !inst_CLK_000_D0.Q & !inst_RW_000_INT.Q & UDS_000.PIN & LDS_000.PIN
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# CLK_030 & inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !RW.PIN
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# BGACK_030.Q & inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !RW.PIN
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# inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & AS_000.PIN & !RW.PIN
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# !CLK_030 & !BGACK_030.Q & !AS_000.PIN & !RW_000.PIN & !UDS_000.PIN
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# !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !inst_RW_000_INT.Q & UDS_000.PIN & LDS_000.PIN
|
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# !CLK_030 & !BGACK_030.Q & !AS_000.PIN & !RW_000.PIN & !LDS_000.PIN
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# inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & UDS_000.PIN & LDS_000.PIN & !RW.PIN);
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inst_RW_000_INT.AP = (!RST);
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inst_RW_000_INT.C = (CLK_OSZI);
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inst_CLK_000_D3.D = (inst_CLK_000_D2.Q);
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inst_CLK_000_D3.AP = (!RST);
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inst_CLK_000_D3.C = (CLK_OSZI);
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inst_CLK_030_H.D = (!RST & inst_CLK_030_H.Q
|
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# !BGACK_030.Q & inst_CLK_030_H.Q & !AS_000.PIN & !UDS_000.PIN
|
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# !BGACK_030.Q & inst_CLK_030_H.Q & !AS_000.PIN & !LDS_000.PIN
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# CLK_030 & RST & !BGACK_030.Q & !AS_030.Q & !AS_000.PIN & !UDS_000.PIN
|
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# CLK_030 & RST & !BGACK_030.Q & !AS_030.Q & !AS_000.PIN & !LDS_000.PIN);
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inst_CLK_030_H.C = (CLK_OSZI);
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SM_AMIGA_4_.AR = (!RST);
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SM_AMIGA_4_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_5_.Q
|
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# !inst_CLK_000_D0.Q & SM_AMIGA_4_.Q);
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SM_AMIGA_4_.C = (CLK_OSZI);
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SM_AMIGA_3_.AR = (!RST);
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!SM_AMIGA_3_.D = (!inst_CLK_000_D0.Q & !SM_AMIGA_3_.Q
|
|
# !SM_AMIGA_4_.Q & !SM_AMIGA_3_.Q
|
|
# inst_VPA_D.Q & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & !inst_DTACK_D0.Q
|
|
# !VMA.Q & !inst_VPA_D.Q & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & !cpu_est_1_.Q & E.Q);
|
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|
SM_AMIGA_3_.C = (CLK_OSZI);
|
|
|
|
SM_AMIGA_1_.AR = (!RST);
|
|
|
|
SM_AMIGA_1_.D = (inst_CLK_000_D0.Q & SM_AMIGA_2_.Q
|
|
# inst_CLK_000_D0.Q & SM_AMIGA_1_.Q);
|
|
|
|
SM_AMIGA_1_.C = (CLK_OSZI);
|
|
|
|
cpu_est_0_.AR = (!RST);
|
|
|
|
cpu_est_0_.D = (!inst_CLK_000_D0.Q & cpu_est_0_.Q
|
|
# inst_CLK_000_D1.Q & cpu_est_0_.Q
|
|
# inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_0_.Q);
|
|
|
|
cpu_est_0_.C = (CLK_OSZI);
|
|
|
|
cpu_est_1_.AR = (!RST);
|
|
|
|
cpu_est_1_.T = (inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_1_.Q & cpu_est_2_.Q & E.Q
|
|
# inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_0_.Q & !cpu_est_2_.Q & E.Q
|
|
# inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_0_.Q & cpu_est_2_.Q & !E.Q
|
|
# inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !E.Q);
|
|
|
|
cpu_est_1_.C = (CLK_OSZI);
|
|
|
|
cpu_est_2_.D.X1 = (inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q
|
|
# inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_0_.Q & !cpu_est_2_.Q & E.Q
|
|
# inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_0_.Q & !cpu_est_1_.Q & cpu_est_2_.Q & !E.Q);
|
|
|
|
cpu_est_2_.D.X2 = (cpu_est_2_.Q);
|
|
|
|
cpu_est_2_.AR = (!RST);
|
|
|
|
cpu_est_2_.C = (CLK_OSZI);
|
|
|
|
|
|
Reverse-Polarity Equations:
|
|
|