mirror of
https://github.com/kr239/68030tk.git
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1525 lines
60 KiB
Plaintext
1525 lines
60 KiB
Plaintext
|--------------------------------------------|
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|- ispLEVER Fitter Report File -|
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|- Version 1.7.00.05.28.13 -|
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|- (c)Copyright, Lattice Semiconductor 2002 -|
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|--------------------------------------------|
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Project_Summary
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~~~~~~~~~~~~~~~
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Project Name : 68030_tk
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Project Path : C:\Users\Matze\Documents\GitHub\68030tk\Logic
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Project Fitted on : Sun Jun 01 01:03:29 2014
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Device : M4A5-128/64
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Package : 100TQFP
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Speed : -10
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Partnumber : M4A5-128/64-10VC
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Source Format : Pure_VHDL
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// Project '68030_tk' was Fitted Successfully! //
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Compilation_Times
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~~~~~~~~~~~~~~~~~
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Reading/DRC 0 sec
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Partition 0 sec
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Place 0 sec
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Route 0 sec
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Jedec/Report generation 0 sec
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--------
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Fitter 00:00:00
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Design_Summary
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~~~~~~~~~~~~~~
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Total Input Pins : 29
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Total Output Pins : 18
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Total Bidir I/O Pins : 12
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Total Flip-Flops : 45
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Total Product Terms : 143
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Total Reserved Pins : 0
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Total Reserved Blocks : 0
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Device_Resource_Summary
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~~~~~~~~~~~~~~~~~~~~~~~
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Total
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Available Used Available Utilization
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Dedicated Pins
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Input-Only Pins 2 2 0 --> 100%
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Clock/Input Pins 4 4 0 --> 100%
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I/O Pins 64 53 11 --> 82%
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Logic Macrocells 128 54 74 --> 42%
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Input Registers 64 0 64 --> 0%
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Unusable Macrocells .. 0 ..
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CSM Outputs/Total Block Inputs 264 157 107 --> 59%
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Logical Product Terms 640 146 494 --> 22%
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Product Term Clusters 128 39 89 --> 30%
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Blocks_Resource_Summary
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~~~~~~~~~~~~~~~~~~~~~~~
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# of PT
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I/O Inp Macrocells Macrocells logic clusters
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Fanin Pins Reg Used Unusable available PTs available Pwr
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---------------------------------------------------------------------------------
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Maximum 33 8 8 -- -- 16 80 16 -
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---------------------------------------------------------------------------------
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Block A 17 7 0 4 0 12 24 10 Hi
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Block B 24 8 0 10 0 6 26 8 Hi
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Block C 22 8 0 5 0 11 16 12 Hi
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Block D 29 8 0 11 0 5 32 7 Hi
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Block E 17 3 0 3 0 13 4 15 Hi
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Block F 0 4 0 0 0 16 0 16 Hi
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Block G 21 7 0 8 0 8 19 12 Hi
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Block H 27 8 0 13 0 3 25 9 Hi
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---------------------------------------------------------------------------------
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<Note> Four rightmost columns above reflect last status of the placement process.
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<Note> Pwr (Power) : Hi = High
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Lo = Low.
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Optimizer_and_Fitter_Options
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Pin Assignment : Yes
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Group Assignment : No
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Pin Reservation : No (1)
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Block Reservation : No
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@Ignore_Project_Constraints :
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Pin Assignments : No
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Keep Block Assignment --
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Keep Segment Assignment --
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Group Assignments : No
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Macrocell Assignment : No
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Keep Block Assignment --
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Keep Segment Assignment --
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@Backannotate_Project_Constraints
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Pin Assignments : No
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Pin And Block Assignments : No
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Pin, Macrocell and Block : No
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@Timing_Constraints : No
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@Global_Project_Optimization :
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Balanced Partitioning : No
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Spread Placement : No
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Note :
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Pack Design :
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Balanced Partitioning = No
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Spread Placement = No
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Spread Design :
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Balanced Partitioning = Yes
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Spread Placement = Yes
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@Logic_Synthesis :
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Logic Reduction : Yes
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Node Collapsing : Yes
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D/T Synthesis : Yes
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Clock Optimization : No
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Input Register Optimization : Yes
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XOR Synthesis : Yes
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Max. P-Term for Collapsing : 16
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Max. P-Term for Splitting : 16
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Max. Equation Fanin : 32
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Keep Xor : Yes
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@Utilization_options
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Max. % of macrocells used : 100
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Max. % of block inputs used : 100
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Max. % of segment lines used : ---
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Max. % of macrocells used : ---
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@Import_Source_Constraint_Option No
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@Zero_Hold_Time Yes
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@Pull_up Yes
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@User_Signature #H0
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@Output_Slew_Rate Default = Slow(2)
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@Power Default = High(2)
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Device Options:
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<Note> 1 : Reserved unused I/Os can be independently driven to Low or High, and does not
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follow the drive level set for the Global Configure Unused I/O Option.
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<Note> 2 : For user-specified constraints on individual signals, refer to the Output,
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Bidir and Burried Signal Lists.
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Pinout_Listing
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~~~~~~~~~~~~~~
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| Pin |Blk |Assigned|
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Pin No| Type |Pad |Pin | Signal name
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---------------------------------------------------------------
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1 | GND | | |
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2 | JTAG | | |
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3 | I_O | B7 | * |RESET
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4 | I_O | B6 | * |A_31_
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5 | I_O | B5 | * |A_30_
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6 | I_O | B4 | * |A_29_
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7 | I_O | B3 | * |IPL_030_1_
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8 | I_O | B2 | * |IPL_030_0_
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9 | I_O | B1 | * |IPL_030_2_
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10 | I_O | B0 | * |CLK_EXP
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11 | CkIn | | * |CLK_000
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12 | Vcc | | |
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13 | GND | | |
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14 | CkIn | | * |nEXP_SPACE
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15 | I_O | C0 | * |A_28_
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16 | I_O | C1 | * |A_27_
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17 | I_O | C2 | * |A_26_
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18 | I_O | C3 | * |A_25_
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19 | I_O | C4 | * |A_24_
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20 | I_O | C5 | * |AMIGA_BUS_ENABLE_LOW
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21 | I_O | C6 | * |BG_030
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22 | I_O | C7 | * |AVEC_EXP
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23 | JTAG | | |
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24 | JTAG | | |
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25 | GND | | |
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26 | GND | | |
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27 | GND | | |
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28 | I_O | D7 | * |BGACK_000
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29 | I_O | D6 | * |BG_000
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30 | I_O | D5 | * |DTACK
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31 | I_O | D4 | * |LDS_000
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32 | I_O | D3 | * |UDS_000
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33 | I_O | D2 | * |AS_000
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34 | I_O | D1 | * |AMIGA_BUS_ENABLE
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35 | I_O | D0 | * |VMA
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36 | Inp | | * |VPA
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37 | Vcc | | |
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38 | GND | | |
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39 | GND | | |
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40 | Vcc | | |
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41 | I_O | E0 | * |BERR
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42 | I_O | E1 | |
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43 | I_O | E2 | |
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44 | I_O | E3 | |
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45 | I_O | E4 | |
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46 | I_O | E5 | |
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47 | I_O | E6 | * |CIIN
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48 | I_O | E7 | * |AMIGA_BUS_DATA_DIR
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49 | GND | | |
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50 | GND | | |
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51 | GND | | |
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52 | JTAG | | |
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53 | I_O | F7 | |
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54 | I_O | F6 | |
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55 | I_O | F5 | |
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56 | I_O | F4 | * |IPL_1_
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57 | I_O | F3 | * |FC_0_
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58 | I_O | F2 | * |FC_1_
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59 | I_O | F1 | * |A_17_
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60 | I_O | F0 | |
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61 | CkIn | | * |CLK_OSZI
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62 | Vcc | | |
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63 | GND | | |
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64 | CkIn | | * |CLK_030
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65 | I_O | G0 | * |CLK_DIV_OUT
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66 | I_O | G1 | * |E
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67 | I_O | G2 | * |IPL_0_
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68 | I_O | G3 | * |IPL_2_
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69 | I_O | G4 | * |A0
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70 | I_O | G5 | * |SIZE_0_
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71 | I_O | G6 | * |RW
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72 | I_O | G7 | |
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73 | JTAG | | |
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74 | JTAG | | |
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75 | GND | | |
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76 | GND | | |
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77 | GND | | |
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78 | I_O | H7 | * |FPU_CS
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79 | I_O | H6 | * |SIZE_1_
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80 | I_O | H5 | * |RW_000
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81 | I_O | H4 | * |DSACK1
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82 | I_O | H3 | * |AS_030
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83 | I_O | H2 | * |BGACK_030
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84 | I_O | H1 | * |A_23_
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85 | I_O | H0 | * |A_22_
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86 | Inp | | * |RST
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87 | Vcc | | |
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88 | GND | | |
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89 | GND | | |
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90 | Vcc | | |
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91 | I_O | A0 | |
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92 | I_O | A1 | * |AVEC
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93 | I_O | A2 | * |A_20_
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94 | I_O | A3 | * |A_21_
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95 | I_O | A4 | * |A_18_
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96 | I_O | A5 | * |A_16_
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97 | I_O | A6 | * |A_19_
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98 | I_O | A7 | * |DS_030
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99 | GND | | |
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100 | GND | | |
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---------------------------------------------------------------------------
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<Note> Blk Pad : This notation refers to the Block I/O pad number in the device.
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<Note> Assigned Pin : user or dedicated input assignment (E.g. Clock pins).
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<Note> Pin Type :
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CkIn : Dedicated input or clock pin
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CLK : Dedicated clock pin
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INP : Dedicated input pin
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JTAG : JTAG Control and test pin
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NC : No connected
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Input_Signal_List
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~~~~~~~~~~~~~~~~~
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P R
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Pin r e O Input
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Pin Blk PTs Type e s E Fanout Pwr Slew Signal
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----------------------------------------------------------------------
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96 A . I/O --C----H Hi Slow A_16_
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59 F . I/O --C----H Hi Slow A_17_
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95 A . I/O --C----H Hi Slow A_18_
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97 A . I/O --C----H Hi Slow A_19_
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93 A . I/O ----E--- Hi Slow A_20_
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94 A . I/O ----E--- Hi Slow A_21_
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85 H . I/O ----E--- Hi Slow A_22_
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84 H . I/O ----E--- Hi Slow A_23_
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19 C . I/O ----E--- Hi Slow A_24_
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18 C . I/O ----E--- Hi Slow A_25_
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17 C . I/O ----E--- Hi Slow A_26_
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16 C . I/O ----E--- Hi Slow A_27_
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15 C . I/O ----E--- Hi Slow A_28_
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6 B . I/O ----E--- Hi Slow A_29_
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5 B . I/O ----E--- Hi Slow A_30_
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4 B . I/O ----E--- Hi Slow A_31_
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28 D . I/O --C----H Hi Slow BGACK_000
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21 C . I/O ---D---- Hi Slow BG_030
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57 F . I/O --C----H Hi Slow FC_0_
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58 F . I/O --C----H Hi Slow FC_1_
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67 G . I/O -B------ Hi Slow IPL_0_
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56 F . I/O -B------ Hi Slow IPL_1_
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68 G . I/O -B------ Hi Slow IPL_2_
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11 . . Ck/I ---D---- - Slow CLK_000
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14 . . Ck/I ABCDE-GH - Slow nEXP_SPACE
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36 . . Ded -------H - Slow VPA
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61 . . Ck/I ABCD--GH - Slow CLK_OSZI
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64 . . Ck/I A-C----H - Slow CLK_030
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86 . . Ded ABCD--GH - Slow RST
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----------------------------------------------------------------------
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<Note> Power : Hi = High
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MH = Medium High
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ML = Medium Low
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Lo = Low
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Output_Signal_List
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~~~~~~~~~~~~~~~~~~
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P R
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Pin r e O Output
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Pin Blk PTs Type e s E Fanout Pwr Slew Signal
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----------------------------------------------------------------------
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48 E 2 COM -------- Hi Slow AMIGA_BUS_DATA_DIR
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34 D 1 COM -------- Hi Slow AMIGA_BUS_ENABLE
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20 C 1 COM -------- Hi Slow AMIGA_BUS_ENABLE_LOW
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92 A 1 COM -------- Hi Slow AVEC
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22 C 3 DFF * -------- Hi Slow AVEC_EXP
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41 E 1 COM -------- Hi Slow BERR
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83 H 2 DFF * -------- Hi Slow BGACK_030
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29 D 2 DFF * -------- Hi Slow BG_000
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47 E 1 COM -------- Hi Slow CIIN
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65 G 1 DFF * -------- Hi Slow CLK_DIV_OUT
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10 B 1 DFF * -------- Hi Slow CLK_EXP
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66 G 3 DFF * -------- Hi Slow E
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78 H 2 DFF * -------- Hi Slow FPU_CS
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8 B 3 DFF * -------- Hi Slow IPL_030_0_
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7 B 3 DFF * -------- Hi Slow IPL_030_1_
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9 B 3 DFF * -------- Hi Slow IPL_030_2_
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3 B 1 DFF * -------- Hi Slow RESET
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35 D 2 DFF * -------- Hi Slow VMA
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----------------------------------------------------------------------
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<Note> Power : Hi = High
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MH = Medium High
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ML = Medium Low
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Lo = Low
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Bidir_Signal_List
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~~~~~~~~~~~~~~~~~
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P R
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Pin r e O Bidir
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Pin Blk PTs Type e s E Fanout Pwr Slew Signal
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----------------------------------------------------------------------
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69 G 1 DFF * ---D---- Hi Slow A0
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33 D 2 DFF * A---E-GH Hi Slow AS_000
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82 H 4 DFF * --CD---H Hi Slow AS_030
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81 H 2 DFF * ---D---- Hi Slow DSACK1
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98 A 7 DFF * ---D---- Hi Slow DS_030
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30 D 1 COM -------H Hi Slow DTACK
|
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31 D 11 DFF * A-----GH Hi Slow LDS_000
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71 G 1 COM A--DE--- Hi Slow RW
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80 H 1 COM A------- Hi Slow RW_000
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70 G 1 DFF * ---D---- Hi Slow SIZE_0_
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79 H 2 DFF * ---D---- Hi Slow SIZE_1_
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32 D 7 DFF * A-----GH Hi Slow UDS_000
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----------------------------------------------------------------------
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<Note> Power : Hi = High
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MH = Medium High
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ML = Medium Low
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Lo = Low
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Buried_Signal_List
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~~~~~~~~~~~~~~~~~~
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P R
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Pin r e O Node
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#Mc Blk PTs Type e s E Fanout Pwr Slew Signal
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----------------------------------------------------------------------
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D4 D 2 DFF * ---D---- Hi - RN_AS_000 --> AS_000
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H6 H 4 DFF * A--D--GH Hi - RN_AS_030 --> AS_030
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C0 C 3 DFF * --CD---- Hi - RN_AVEC_EXP --> AVEC_EXP
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H4 H 2 DFF * A-CDE-GH Hi - RN_BGACK_030 --> BGACK_030
|
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D2 D 2 DFF * ---D---- Hi - RN_BG_000 --> BG_000
|
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H8 H 2 DFF * -------H Hi - RN_DSACK1 --> DSACK1
|
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A0 A 7 DFF * A------- Hi - RN_DS_030 --> DS_030
|
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G2 G 3 DFF * -B-D--G- Hi - RN_E --> E
|
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H2 H 2 DFF * ----E--H Hi - RN_FPU_CS --> FPU_CS
|
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B4 B 3 DFF * -B------ Hi - RN_IPL_030_0_ --> IPL_030_0_
|
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B6 B 3 DFF * -B------ Hi - RN_IPL_030_1_ --> IPL_030_1_
|
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B2 B 3 DFF * -B------ Hi - RN_IPL_030_2_ --> IPL_030_2_
|
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D8 D 11 DFF * ---D---- Hi - RN_LDS_000 --> LDS_000
|
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D6 D 7 DFF * ---D---- Hi - RN_UDS_000 --> UDS_000
|
||
D1 D 2 DFF * ---D--G- Hi - RN_VMA --> VMA
|
||
A1 A 2 DFF * AB------ Hi Slow SM_AMIGA_0_
|
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H7 H 2 DFF * A------H Hi Slow SM_AMIGA_1_
|
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G5 G 3 DFF * --C---GH Hi Slow SM_AMIGA_2_
|
||
G6 G 4 DFF * ------G- Hi Slow SM_AMIGA_3_
|
||
D9 D 2 DFF * ---D--G- Hi Slow SM_AMIGA_4_
|
||
B8 B 2 DFF * -B-D---- Hi Slow SM_AMIGA_5_
|
||
B9 B 2 DFF * AB------ Hi Slow SM_AMIGA_6_
|
||
B5 B 4 DFF * -BCD---- Hi Slow SM_AMIGA_7_
|
||
C2 C 3 DFF * -BCD--G- Hi Slow cpu_est_0_
|
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B3 B 4 TFF * -B-D--G- Hi Slow cpu_est_1_
|
||
G4 G 3 DFF * -B-D--G- Hi Slow cpu_est_2_
|
||
C3 C 8 DFF * -BC----- Hi Slow inst_AS_030_000_SYNC
|
||
D10 D 1 DFF * --C----- Hi Slow inst_BGACK_030_INT_D
|
||
D5 D 1 DFF * ABCD--GH Hi Slow inst_CLK_000_D0
|
||
D7 D 1 DFF * -BC---GH Hi Slow inst_CLK_000_D1
|
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H3 H 1 DFF * -BCD---- Hi Slow inst_CLK_000_D2
|
||
C4 C 1 DFF * -BC----- Hi Slow inst_CLK_000_D3
|
||
H5 H 5 DFF A------H Hi Slow inst_CLK_030_H
|
||
B7 B 3 DFF * -B----G- Hi Slow inst_CLK_OUT_PRE_25
|
||
H9 H 1 DFF * -B-----H Hi Slow inst_CLK_OUT_PRE_50
|
||
H12 H 1 DFF * -B------ Hi Slow inst_CLK_OUT_PRE_50_D
|
||
H11 H 1 DFF * ------G- Hi Slow inst_DTACK_D0
|
||
A3 A 14 DFF * A-----GH Hi Slow inst_RW_000_INT
|
||
H10 H 1 DFF * ---D--G- Hi Slow inst_VPA_D
|
||
----------------------------------------------------------------------
|
||
|
||
<Note> Power : Hi = High
|
||
MH = Medium High
|
||
ML = Medium Low
|
||
Lo = Low
|
||
|
||
|
||
|
||
|
||
Signals_Fanout_List
|
||
~~~~~~~~~~~~~~~~~~~
|
||
Signal Source : Fanout List
|
||
-----------------------------------------------------------------------------
|
||
A_26_{ D}: CIIN{ E}
|
||
A_25_{ D}: CIIN{ E}
|
||
A_24_{ D}: CIIN{ E}
|
||
A_23_{ I}: CIIN{ E}
|
||
A_31_{ C}: CIIN{ E}
|
||
A_22_{ I}: CIIN{ E}
|
||
A_21_{ B}: CIIN{ E}
|
||
A_20_{ B}: CIIN{ E}
|
||
A_19_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ C}
|
||
IPL_2_{ H}: IPL_030_2_{ B}
|
||
A_18_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ C}
|
||
A_17_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ C}
|
||
FC_1_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ C}
|
||
A_16_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ C}
|
||
RW_000{ I}: DS_030{ A}inst_RW_000_INT{ A}
|
||
IPL_1_{ G}: IPL_030_1_{ B}
|
||
IPL_0_{ H}: IPL_030_0_{ B}
|
||
FC_0_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ C}
|
||
nEXP_SPACE{. }: DTACK{ D} AVEC_EXP{ C}AMIGA_BUS_DATA_DIR{ E}
|
||
: SIZE_1_{ H} AS_030{ H} DS_030{ A}
|
||
: A0{ G} BG_000{ D} DSACK1{ H}
|
||
: SIZE_0_{ G}inst_AS_030_000_SYNC{ C} SM_AMIGA_7_{ B}
|
||
: SM_AMIGA_6_{ B}
|
||
BG_030{ D}: BG_000{ D}
|
||
BGACK_000{ E}: BGACK_030{ H} FPU_CS{ H}inst_AS_030_000_SYNC{ C}
|
||
CLK_030{. }: AS_030{ H} DS_030{ A} FPU_CS{ H}
|
||
:inst_AS_030_000_SYNC{ C}inst_RW_000_INT{ A} inst_CLK_030_H{ H}
|
||
CLK_000{. }: BG_000{ D}inst_CLK_000_D0{ D}
|
||
DTACK{ E}: inst_DTACK_D0{ H}
|
||
RN_AVEC_EXP{ D}: AVEC_EXP{ C}AMIGA_BUS_ENABLE{ D}
|
||
VPA{. }: inst_VPA_D{ H}
|
||
RST{. }: CLK_DIV_OUT{ G} AVEC_EXP{ C} SIZE_1_{ H}
|
||
: IPL_030_2_{ B} AS_030{ H} IPL_030_1_{ B}
|
||
: AS_000{ D} IPL_030_0_{ B} DS_030{ A}
|
||
: UDS_000{ D} LDS_000{ D} A0{ G}
|
||
: BG_000{ D} BGACK_030{ H} CLK_EXP{ B}
|
||
: FPU_CS{ H} DSACK1{ H} E{ G}
|
||
: VMA{ D} RESET{ B} SIZE_0_{ G}
|
||
:inst_AS_030_000_SYNC{ C}inst_BGACK_030_INT_D{ D} inst_VPA_D{ H}
|
||
:inst_CLK_OUT_PRE_50_D{ H}inst_CLK_000_D0{ D}inst_CLK_000_D1{ D}
|
||
:inst_CLK_000_D2{ H} inst_DTACK_D0{ H}inst_CLK_OUT_PRE_50{ H}
|
||
:inst_CLK_OUT_PRE_25{ B} SM_AMIGA_7_{ B} SM_AMIGA_6_{ B}
|
||
: SM_AMIGA_0_{ A} SM_AMIGA_5_{ B} SM_AMIGA_2_{ G}
|
||
:inst_RW_000_INT{ A}inst_CLK_000_D3{ C} inst_CLK_030_H{ H}
|
||
: SM_AMIGA_4_{ D} SM_AMIGA_3_{ G} SM_AMIGA_1_{ H}
|
||
: cpu_est_0_{ C} cpu_est_1_{ B} cpu_est_2_{ G}
|
||
RW{ H}:AMIGA_BUS_DATA_DIR{ E} UDS_000{ D} LDS_000{ D}
|
||
:inst_RW_000_INT{ A}
|
||
A_30_{ C}: CIIN{ E}
|
||
A_29_{ C}: CIIN{ E}
|
||
A_28_{ D}: CIIN{ E}
|
||
A_27_{ D}: CIIN{ E}
|
||
SIZE_1_{ I}: LDS_000{ D}
|
||
RN_IPL_030_2_{ C}: IPL_030_2_{ B}
|
||
AS_030{ I}: AS_000{ D} UDS_000{ D} LDS_000{ D}
|
||
: BG_000{ D} FPU_CS{ H} DSACK1{ H}
|
||
:inst_AS_030_000_SYNC{ C}
|
||
RN_AS_030{ I}: DTACK{ D} SIZE_1_{ H} AS_030{ H}
|
||
: DS_030{ A} A0{ G} SIZE_0_{ G}
|
||
: inst_CLK_030_H{ H}
|
||
RN_IPL_030_1_{ C}: IPL_030_1_{ B}
|
||
AS_000{ E}:AMIGA_BUS_DATA_DIR{ E} SIZE_1_{ H} AS_030{ H}
|
||
: DS_030{ A} A0{ G} SIZE_0_{ G}
|
||
:inst_RW_000_INT{ A} inst_CLK_030_H{ H}
|
||
RN_AS_000{ E}: AS_000{ D} VMA{ D}
|
||
RN_IPL_030_0_{ C}: IPL_030_0_{ B}
|
||
DS_030{ B}: UDS_000{ D} LDS_000{ D}
|
||
RN_DS_030{ B}: DS_030{ A}
|
||
UDS_000{ E}: SIZE_1_{ H} AS_030{ H} DS_030{ A}
|
||
: A0{ G} SIZE_0_{ G}inst_RW_000_INT{ A}
|
||
: inst_CLK_030_H{ H}
|
||
RN_UDS_000{ E}: UDS_000{ D}
|
||
LDS_000{ E}: SIZE_1_{ H} AS_030{ H} DS_030{ A}
|
||
: A0{ G} SIZE_0_{ G}inst_RW_000_INT{ A}
|
||
: inst_CLK_030_H{ H}
|
||
RN_LDS_000{ E}: LDS_000{ D}
|
||
A0{ H}: UDS_000{ D} LDS_000{ D}
|
||
RN_BG_000{ E}: BG_000{ D}
|
||
RN_BGACK_030{ I}: RW_000{ H} DTACK{ D} AVEC_EXP{ C}
|
||
: RW{ G}AMIGA_BUS_DATA_DIR{ E} SIZE_1_{ H}
|
||
: AS_030{ H} AS_000{ D} DS_030{ A}
|
||
: UDS_000{ D} LDS_000{ D} A0{ G}
|
||
: BGACK_030{ H} SIZE_0_{ G}inst_AS_030_000_SYNC{ C}
|
||
:inst_BGACK_030_INT_D{ D}inst_RW_000_INT{ A} inst_CLK_030_H{ H}
|
||
RN_FPU_CS{ I}: BERR{ E} FPU_CS{ H}
|
||
DSACK1{ I}: DTACK{ D}
|
||
RN_DSACK1{ I}: DSACK1{ H}
|
||
RN_E{ H}: E{ G} VMA{ D} SM_AMIGA_2_{ G}
|
||
: SM_AMIGA_3_{ G} cpu_est_1_{ B} cpu_est_2_{ G}
|
||
RN_VMA{ E}: VMA{ D} SM_AMIGA_2_{ G} SM_AMIGA_3_{ G}
|
||
SIZE_0_{ H}: LDS_000{ D}
|
||
inst_AS_030_000_SYNC{ D}: AVEC_EXP{ C}inst_AS_030_000_SYNC{ C} SM_AMIGA_7_{ B}
|
||
: SM_AMIGA_6_{ B}
|
||
inst_BGACK_030_INT_D{ E}: AVEC_EXP{ C}
|
||
inst_VPA_D{ I}: VMA{ D} SM_AMIGA_2_{ G} SM_AMIGA_3_{ G}
|
||
inst_CLK_OUT_PRE_50_D{ I}:inst_CLK_OUT_PRE_25{ B}
|
||
inst_CLK_000_D0{ E}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B}
|
||
: UDS_000{ D} LDS_000{ D} BGACK_030{ H}
|
||
: DSACK1{ H} E{ G} VMA{ D}
|
||
:inst_AS_030_000_SYNC{ C}inst_CLK_000_D1{ D} SM_AMIGA_7_{ B}
|
||
: SM_AMIGA_6_{ B} SM_AMIGA_0_{ A} SM_AMIGA_5_{ B}
|
||
: SM_AMIGA_2_{ G}inst_RW_000_INT{ A} SM_AMIGA_4_{ D}
|
||
: SM_AMIGA_3_{ G} SM_AMIGA_1_{ H} cpu_est_0_{ C}
|
||
: cpu_est_1_{ B} cpu_est_2_{ G}
|
||
inst_CLK_000_D1{ E}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B}
|
||
: BGACK_030{ H} E{ G}inst_CLK_000_D2{ H}
|
||
: SM_AMIGA_2_{ G} SM_AMIGA_3_{ G} cpu_est_0_{ C}
|
||
: cpu_est_1_{ B} cpu_est_2_{ G}
|
||
inst_CLK_000_D2{ I}: AVEC_EXP{ C} AS_000{ D} UDS_000{ D}
|
||
: LDS_000{ D}inst_AS_030_000_SYNC{ C} SM_AMIGA_7_{ B}
|
||
: SM_AMIGA_6_{ B}inst_CLK_000_D3{ C}
|
||
inst_DTACK_D0{ I}: SM_AMIGA_2_{ G} SM_AMIGA_3_{ G}
|
||
inst_CLK_OUT_PRE_50{ I}:inst_CLK_OUT_PRE_50_D{ H}inst_CLK_OUT_PRE_50{ H}inst_CLK_OUT_PRE_25{ B}
|
||
inst_CLK_OUT_PRE_25{ C}: CLK_DIV_OUT{ G} CLK_EXP{ B}inst_CLK_OUT_PRE_25{ B}
|
||
SM_AMIGA_7_{ C}: AVEC_EXP{ C} BG_000{ D}inst_AS_030_000_SYNC{ C}
|
||
: SM_AMIGA_7_{ B} SM_AMIGA_6_{ B}
|
||
SM_AMIGA_6_{ C}: SM_AMIGA_6_{ B} SM_AMIGA_5_{ B}inst_RW_000_INT{ A}
|
||
SM_AMIGA_0_{ B}: SM_AMIGA_7_{ B} SM_AMIGA_0_{ A}inst_RW_000_INT{ A}
|
||
SM_AMIGA_5_{ C}: AS_000{ D} UDS_000{ D} LDS_000{ D}
|
||
: SM_AMIGA_5_{ B} SM_AMIGA_4_{ D}
|
||
SM_AMIGA_2_{ H}: DSACK1{ H}inst_AS_030_000_SYNC{ C} SM_AMIGA_2_{ G}
|
||
: SM_AMIGA_1_{ H}
|
||
inst_RW_000_INT{ B}: RW_000{ H} RW{ G}inst_RW_000_INT{ A}
|
||
inst_CLK_000_D3{ D}: AVEC_EXP{ C}inst_AS_030_000_SYNC{ C} SM_AMIGA_7_{ B}
|
||
: SM_AMIGA_6_{ B}
|
||
inst_CLK_030_H{ I}: DS_030{ A} inst_CLK_030_H{ H}
|
||
SM_AMIGA_4_{ E}: UDS_000{ D} LDS_000{ D} SM_AMIGA_4_{ D}
|
||
: SM_AMIGA_3_{ G}
|
||
SM_AMIGA_3_{ H}: SM_AMIGA_2_{ G} SM_AMIGA_3_{ G}
|
||
SM_AMIGA_1_{ I}: SM_AMIGA_0_{ A} SM_AMIGA_1_{ H}
|
||
cpu_est_0_{ D}: E{ G} VMA{ D} cpu_est_0_{ C}
|
||
: cpu_est_1_{ B} cpu_est_2_{ G}
|
||
cpu_est_1_{ C}: E{ G} VMA{ D} SM_AMIGA_2_{ G}
|
||
: SM_AMIGA_3_{ G} cpu_est_1_{ B} cpu_est_2_{ G}
|
||
cpu_est_2_{ H}: E{ G} VMA{ D} cpu_est_1_{ B}
|
||
: cpu_est_2_{ G}
|
||
-----------------------------------------------------------------------------
|
||
|
||
<Note> {.} : Indicates block location of signal
|
||
|
||
|
||
Set_Reset_Summary
|
||
~~~~~~~~~~~~~~~~~
|
||
|
||
Block A
|
||
block level set pt : !RST
|
||
block level reset pt :
|
||
Equations :
|
||
| | |Block|Block| Signal
|
||
| Reg |Mode |Set |Reset| Name
|
||
+-----+-----+-----+-----+------------------------
|
||
| * | S | BS | BR | DS_030
|
||
| | | | | AVEC
|
||
| * | S | BS | BR | inst_RW_000_INT
|
||
| * | S | BR | BS | SM_AMIGA_0_
|
||
| * | S | BS | BR | RN_DS_030
|
||
| | | | | A_19_
|
||
| | | | | A_16_
|
||
| | | | | A_18_
|
||
| | | | | A_21_
|
||
| | | | | A_20_
|
||
|
||
|
||
Block B
|
||
block level set pt : !RST
|
||
block level reset pt :
|
||
Equations :
|
||
| | |Block|Block| Signal
|
||
| Reg |Mode |Set |Reset| Name
|
||
+-----+-----+-----+-----+------------------------
|
||
| * | S | BS | BR | IPL_030_2_
|
||
| * | S | BS | BR | IPL_030_0_
|
||
| * | S | BS | BR | IPL_030_1_
|
||
| * | S | BR | BS | CLK_EXP
|
||
| * | S | BR | BS | RESET
|
||
| * | S | BR | BS | cpu_est_1_
|
||
| * | S | BS | BR | SM_AMIGA_7_
|
||
| * | S | BR | BS | inst_CLK_OUT_PRE_25
|
||
| * | S | BR | BS | SM_AMIGA_5_
|
||
| * | S | BR | BS | SM_AMIGA_6_
|
||
| * | S | BS | BR | RN_IPL_030_0_
|
||
| * | S | BS | BR | RN_IPL_030_1_
|
||
| * | S | BS | BR | RN_IPL_030_2_
|
||
| | | | | A_29_
|
||
| | | | | A_30_
|
||
| | | | | A_31_
|
||
|
||
|
||
Block C
|
||
block level set pt : !RST
|
||
block level reset pt :
|
||
Equations :
|
||
| | |Block|Block| Signal
|
||
| Reg |Mode |Set |Reset| Name
|
||
+-----+-----+-----+-----+------------------------
|
||
| * | S | BS | BR | AVEC_EXP
|
||
| | | | | AMIGA_BUS_ENABLE_LOW
|
||
| * | S | BR | BS | cpu_est_0_
|
||
| * | S | BS | BR | inst_AS_030_000_SYNC
|
||
| * | S | BS | BR | RN_AVEC_EXP
|
||
| * | S | BS | BR | inst_CLK_000_D3
|
||
| | | | | BG_030
|
||
| | | | | A_24_
|
||
| | | | | A_25_
|
||
| | | | | A_26_
|
||
| | | | | A_27_
|
||
| | | | | A_28_
|
||
|
||
|
||
Block D
|
||
block level set pt : !RST
|
||
block level reset pt :
|
||
Equations :
|
||
| | |Block|Block| Signal
|
||
| Reg |Mode |Set |Reset| Name
|
||
+-----+-----+-----+-----+------------------------
|
||
| * | S | BS | BR | AS_000
|
||
| * | S | BS | BR | LDS_000
|
||
| * | S | BS | BR | UDS_000
|
||
| | | | | DTACK
|
||
| * | S | BS | BR | VMA
|
||
| * | S | BS | BR | BG_000
|
||
| | | | | AMIGA_BUS_ENABLE
|
||
| * | S | BS | BR | inst_CLK_000_D0
|
||
| * | S | BS | BR | inst_CLK_000_D1
|
||
| * | S | BS | BR | RN_VMA
|
||
| * | S | BR | BS | SM_AMIGA_4_
|
||
| * | S | BS | BR | RN_LDS_000
|
||
| * | S | BS | BR | RN_UDS_000
|
||
| * | S | BS | BR | RN_BG_000
|
||
| * | S | BS | BR | RN_AS_000
|
||
| * | S | BS | BR | inst_BGACK_030_INT_D
|
||
| | | | | BGACK_000
|
||
|
||
|
||
Block E
|
||
block level set pt :
|
||
block level reset pt :
|
||
Equations :
|
||
| | |Block|Block| Signal
|
||
| Reg |Mode |Set |Reset| Name
|
||
+-----+-----+-----+-----+------------------------
|
||
| | | | | AMIGA_BUS_DATA_DIR
|
||
| | | | | CIIN
|
||
| | | | | BERR
|
||
|
||
|
||
Block F
|
||
block level set pt :
|
||
block level reset pt :
|
||
Equations :
|
||
| | |Block|Block| Signal
|
||
| Reg |Mode |Set |Reset| Name
|
||
+-----+-----+-----+-----+------------------------
|
||
| | | | | A_17_
|
||
| | | | | FC_1_
|
||
| | | | | FC_0_
|
||
| | | | | IPL_1_
|
||
|
||
|
||
Block G
|
||
block level set pt :
|
||
block level reset pt : !RST
|
||
Equations :
|
||
| | |Block|Block| Signal
|
||
| Reg |Mode |Set |Reset| Name
|
||
+-----+-----+-----+-----+------------------------
|
||
| | | | | RW
|
||
| * | S | BR | BS | SIZE_0_
|
||
| * | S | BR | BS | A0
|
||
| * | S | BS | BR | E
|
||
| * | S | BS | BR | CLK_DIV_OUT
|
||
| * | S | BS | BR | RN_E
|
||
| * | S | BS | BR | cpu_est_2_
|
||
| * | S | BS | BR | SM_AMIGA_2_
|
||
| * | S | BS | BR | SM_AMIGA_3_
|
||
| | | | | IPL_2_
|
||
| | | | | IPL_0_
|
||
|
||
|
||
Block H
|
||
block level set pt : !RST
|
||
block level reset pt :
|
||
Equations :
|
||
| | |Block|Block| Signal
|
||
| Reg |Mode |Set |Reset| Name
|
||
+-----+-----+-----+-----+------------------------
|
||
| * | S | BS | BR | AS_030
|
||
| * | S | BS | BR | DSACK1
|
||
| * | S | BS | BR | SIZE_1_
|
||
| | | | | RW_000
|
||
| * | S | BS | BR | BGACK_030
|
||
| * | S | BS | BR | FPU_CS
|
||
| * | S | BS | BR | RN_BGACK_030
|
||
| * | S | BS | BR | RN_AS_030
|
||
| * | S | BS | BR | inst_CLK_000_D2
|
||
| * | S | BR | BR | inst_CLK_030_H
|
||
| * | S | BS | BR | RN_FPU_CS
|
||
| * | S | BR | BS | SM_AMIGA_1_
|
||
| * | S | BR | BS | inst_CLK_OUT_PRE_50
|
||
| * | S | BS | BR | inst_VPA_D
|
||
| * | S | BS | BR | RN_DSACK1
|
||
| * | S | BS | BR | inst_DTACK_D0
|
||
| * | S | BR | BS | inst_CLK_OUT_PRE_50_D
|
||
| | | | | A_22_
|
||
| | | | | A_23_
|
||
|
||
|
||
<Note> (S) means the macrocell is configured in synchronous mode
|
||
i.e. it uses the block-level set and reset pt.
|
||
(A) means the macrocell is configured in asynchronous mode
|
||
i.e. it can have its independant set or reset pt.
|
||
(BS) means the block-level set pt is selected.
|
||
(BR) means the block-level reset pt is selected.
|
||
|
||
|
||
|
||
|
||
BLOCK_A_LOGIC_ARRAY_FANIN
|
||
~~~~~~~~~~~~~~~~~~~~~~~~~
|
||
CSM Signal Source CSM Signal Source
|
||
------------------------------------ ------------------------------------
|
||
mx A0 RST pin 86 mx A17 ... ...
|
||
mx A1 ... ... mx A18 ... ...
|
||
mx A2 ... ... mx A19 ... ...
|
||
mx A3 ... ... mx A20 RN_BGACK_030 mcell H4
|
||
mx A4 CLK_030 pin 64 mx A21 RN_AS_030 mcell H6
|
||
mx A5 nEXP_SPACE pin 14 mx A22 ... ...
|
||
mx A6 SM_AMIGA_6_ mcell B9 mx A23 AS_000 pin 33
|
||
mx A7 SM_AMIGA_1_ mcell H7 mx A24 LDS_000 pin 31
|
||
mx A8 RW pin 71 mx A25 inst_RW_000_INT mcell A3
|
||
mx A9 SM_AMIGA_0_ mcell A1 mx A26 ... ...
|
||
mx A10 ... ... mx A27 ... ...
|
||
mx A11 inst_CLK_000_D0 mcell D5 mx A28 RW_000 pin 80
|
||
mx A12 UDS_000 pin 32 mx A29 ... ...
|
||
mx A13 inst_CLK_030_H mcell H5 mx A30 ... ...
|
||
mx A14 ... ... mx A31 ... ...
|
||
mx A15 RN_DS_030 mcell A0 mx A32 ... ...
|
||
mx A16 ... ...
|
||
----------------------------------------------------------------------------
|
||
|
||
|
||
BLOCK_B_LOGIC_ARRAY_FANIN
|
||
~~~~~~~~~~~~~~~~~~~~~~~~~
|
||
CSM Signal Source CSM Signal Source
|
||
------------------------------------ ------------------------------------
|
||
mx B0 RST pin 86 mx B17 SM_AMIGA_5_ mcell B8
|
||
mx B1inst_CLK_OUT_PRE_25 mcell B7 mx B18 inst_CLK_000_D2 mcell H3
|
||
mx B2 RN_IPL_030_1_ mcell B6 mx B19 ... ...
|
||
mx B3 IPL_1_ pin 56 mx B20 ... ...
|
||
mx B4 IPL_2_ pin 68 mx B21 cpu_est_2_ mcell G4
|
||
mx B5 nEXP_SPACE pin 14 mx B22 cpu_est_0_ mcell C2
|
||
mx B6 SM_AMIGA_6_ mcell B9 mx B23 RN_E mcell G2
|
||
mx B7 inst_CLK_000_D0 mcell D5 mx B24 ... ...
|
||
mx B8 inst_CLK_000_D1 mcell D7 mx B25 ... ...
|
||
mx B9 SM_AMIGA_0_ mcell A1 mx B26 ... ...
|
||
mx B10 RN_IPL_030_2_ mcell B2 mx B27 RN_IPL_030_0_ mcell B4
|
||
mx B11inst_CLK_OUT_PRE_50 mcell H9 mx B28 SM_AMIGA_7_ mcell B5
|
||
mx B12inst_AS_030_000_SYNC mcell C3 mx B29 ... ...
|
||
mx B13 cpu_est_1_ mcell B3 mx B30 ... ...
|
||
mx B14 inst_CLK_000_D3 mcell C4 mx B31 ... ...
|
||
mx B15inst_CLK_OUT_PRE_50_D mcell H12 mx B32 ... ...
|
||
mx B16 IPL_0_ pin 67
|
||
----------------------------------------------------------------------------
|
||
|
||
|
||
BLOCK_C_LOGIC_ARRAY_FANIN
|
||
~~~~~~~~~~~~~~~~~~~~~~~~~
|
||
CSM Signal Source CSM Signal Source
|
||
------------------------------------ ------------------------------------
|
||
mx C0 RST pin 86 mx C17 A_18_ pin 95
|
||
mx C1 FC_1_ pin 58 mx C18 BGACK_000 pin 28
|
||
mx C2inst_BGACK_030_INT_D mcell D10 mx C19 AS_030 pin 82
|
||
mx C3 SM_AMIGA_2_ mcell G5 mx C20 CLK_030 pin 64
|
||
mx C4inst_AS_030_000_SYNC mcell C3 mx C21 ... ...
|
||
mx C5 nEXP_SPACE pin 14 mx C22 cpu_est_0_ mcell C2
|
||
mx C6 FC_0_ pin 57 mx C23 RN_BGACK_030 mcell H4
|
||
mx C7 inst_CLK_000_D0 mcell D5 mx C24 ... ...
|
||
mx C8 A_17_ pin 59 mx C25 ... ...
|
||
mx C9 RN_AVEC_EXP mcell C0 mx C26 ... ...
|
||
mx C10 inst_CLK_000_D2 mcell H3 mx C27 ... ...
|
||
mx C11 A_16_ pin 96 mx C28 SM_AMIGA_7_ mcell B5
|
||
mx C12 A_19_ pin 97 mx C29 ... ...
|
||
mx C13 inst_CLK_000_D1 mcell D7 mx C30 ... ...
|
||
mx C14 inst_CLK_000_D3 mcell C4 mx C31 ... ...
|
||
mx C15 ... ... mx C32 ... ...
|
||
mx C16 ... ...
|
||
----------------------------------------------------------------------------
|
||
|
||
|
||
BLOCK_D_LOGIC_ARRAY_FANIN
|
||
~~~~~~~~~~~~~~~~~~~~~~~~~
|
||
CSM Signal Source CSM Signal Source
|
||
------------------------------------ ------------------------------------
|
||
mx D0 A0 pin 69 mx D17 RN_VMA mcell D1
|
||
mx D1 ... ... mx D18 inst_VPA_D mcell H10
|
||
mx D2 cpu_est_2_ mcell G4 mx D19 AS_030 pin 82
|
||
mx D3 CLK_000 pin 11 mx D20 RN_BGACK_030 mcell H4
|
||
mx D4 BG_030 pin 21 mx D21 RST pin 86
|
||
mx D5 DS_030 pin 98 mx D22 cpu_est_0_ mcell C2
|
||
mx D6 SIZE_1_ pin 79 mx D23 RN_E mcell G2
|
||
mx D7 RN_AS_030 mcell H6 mx D24 inst_CLK_000_D0 mcell D5
|
||
mx D8 SM_AMIGA_5_ mcell B8 mx D25 RW pin 71
|
||
mx D9 RN_AVEC_EXP mcell C0 mx D26 ... ...
|
||
mx D10 RN_AS_000 mcell D4 mx D27 ... ...
|
||
mx D11 inst_CLK_000_D2 mcell H3 mx D28 RN_BG_000 mcell D2
|
||
mx D12 SM_AMIGA_4_ mcell D9 mx D29 ... ...
|
||
mx D13 cpu_est_1_ mcell B3 mx D30 RN_UDS_000 mcell D6
|
||
mx D14 SIZE_0_ pin 70 mx D31 SM_AMIGA_7_ mcell B5
|
||
mx D15 nEXP_SPACE pin 14 mx D32 DSACK1 pin 81
|
||
mx D16 RN_LDS_000 mcell D8
|
||
----------------------------------------------------------------------------
|
||
|
||
|
||
BLOCK_E_LOGIC_ARRAY_FANIN
|
||
~~~~~~~~~~~~~~~~~~~~~~~~~
|
||
CSM Signal Source CSM Signal Source
|
||
------------------------------------ ------------------------------------
|
||
mx E0 RN_BGACK_030 mcell H4 mx E17 A_26_ pin 17
|
||
mx E1 A_31_ pin 4 mx E18 ... ...
|
||
mx E2 ... ... mx E19 ... ...
|
||
mx E3 A_27_ pin 16 mx E20 ... ...
|
||
mx E4 A_29_ pin 6 mx E21 nEXP_SPACE pin 14
|
||
mx E5 A_24_ pin 19 mx E22 ... ...
|
||
mx E6 ... ... mx E23 AS_000 pin 33
|
||
mx E7 A_28_ pin 15 mx E24 ... ...
|
||
mx E8 A_22_ pin 85 mx E25 RW pin 71
|
||
mx E9 A_30_ pin 5 mx E26 ... ...
|
||
mx E10 ... ... mx E27 ... ...
|
||
mx E11 A_23_ pin 84 mx E28 ... ...
|
||
mx E12 A_25_ pin 18 mx E29 A_20_ pin 93
|
||
mx E13 ... ... mx E30 ... ...
|
||
mx E14 RN_FPU_CS mcell H2 mx E31 ... ...
|
||
mx E15 A_21_ pin 94 mx E32 ... ...
|
||
mx E16 ... ...
|
||
----------------------------------------------------------------------------
|
||
|
||
|
||
BLOCK_G_LOGIC_ARRAY_FANIN
|
||
~~~~~~~~~~~~~~~~~~~~~~~~~
|
||
CSM Signal Source CSM Signal Source
|
||
------------------------------------ ------------------------------------
|
||
mx G0 RST pin 86 mx G17 ... ...
|
||
mx G1 inst_DTACK_D0 mcell H11 mx G18 inst_VPA_D mcell H10
|
||
mx G2 RN_VMA mcell D1 mx G19 ... ...
|
||
mx G3 SM_AMIGA_2_ mcell G5 mx G20 RN_BGACK_030 mcell H4
|
||
mx G4 RN_E mcell G2 mx G21 RN_AS_030 mcell H6
|
||
mx G5 cpu_est_1_ mcell B3 mx G22 cpu_est_0_ mcell C2
|
||
mx G6 inst_RW_000_INT mcell A3 mx G23 SM_AMIGA_3_ mcell G6
|
||
mx G7 inst_CLK_000_D0 mcell D5 mx G24inst_CLK_OUT_PRE_25 mcell B7
|
||
mx G8 UDS_000 pin 32 mx G25 ... ...
|
||
mx G9 ... ... mx G26 AS_000 pin 33
|
||
mx G10 ... ... mx G27 LDS_000 pin 31
|
||
mx G11 cpu_est_2_ mcell G4 mx G28 ... ...
|
||
mx G12 SM_AMIGA_4_ mcell D9 mx G29 ... ...
|
||
mx G13 inst_CLK_000_D1 mcell D7 mx G30 ... ...
|
||
mx G14 ... ... mx G31 ... ...
|
||
mx G15 nEXP_SPACE pin 14 mx G32 ... ...
|
||
mx G16 ... ...
|
||
----------------------------------------------------------------------------
|
||
|
||
|
||
BLOCK_H_LOGIC_ARRAY_FANIN
|
||
~~~~~~~~~~~~~~~~~~~~~~~~~
|
||
CSM Signal Source CSM Signal Source
|
||
------------------------------------ ------------------------------------
|
||
mx H0 LDS_000 pin 31 mx H17 FC_0_ pin 57
|
||
mx H1 FC_1_ pin 58 mx H18 BGACK_000 pin 28
|
||
mx H2 ... ... mx H19 AS_030 pin 82
|
||
mx H3 RN_DSACK1 mcell H8 mx H20 CLK_030 pin 64
|
||
mx H4 A_18_ pin 95 mx H21 RST pin 86
|
||
mx H5inst_CLK_OUT_PRE_50 mcell H9 mx H22 SM_AMIGA_2_ mcell G5
|
||
mx H6 A_19_ pin 97 mx H23 RN_BGACK_030 mcell H4
|
||
mx H7 SM_AMIGA_1_ mcell H7 mx H24 inst_CLK_000_D0 mcell D5
|
||
mx H8 inst_CLK_000_D1 mcell D7 mx H25 inst_RW_000_INT mcell A3
|
||
mx H9 DTACK pin 30 mx H26 AS_000 pin 33
|
||
mx H10 VPA pin 36 mx H27 A_17_ pin 59
|
||
mx H11 A_16_ pin 96 mx H28 ... ...
|
||
mx H12 UDS_000 pin 32 mx H29 ... ...
|
||
mx H13 inst_CLK_030_H mcell H5 mx H30 RN_AS_030 mcell H6
|
||
mx H14 RN_FPU_CS mcell H2 mx H31 ... ...
|
||
mx H15 nEXP_SPACE pin 14 mx H32 ... ...
|
||
mx H16 ... ...
|
||
----------------------------------------------------------------------------
|
||
|
||
<Note> CSM indicates the mux inputs from the Central Switch Matrix.
|
||
<Note> Source indicates where the signal comes from (pin or macrocell).
|
||
|
||
|
||
|
||
|
||
PostFit_Equations
|
||
~~~~~~~~~~~~~~~~~
|
||
|
||
|
||
P-Terms Fan-in Fan-out Type Name (attributes)
|
||
--------- ------ ------- ---- -----------------
|
||
1 1 1 Pin RW_000
|
||
1 1 1 Pin RW_000.OE
|
||
0 0 1 Pin BERR
|
||
1 1 1 Pin BERR.OE
|
||
1 1 1 Pin CLK_DIV_OUT.AR
|
||
1 1 1 Pin CLK_DIV_OUT.D
|
||
1 1 1 Pin CLK_DIV_OUT.C
|
||
1 1 1 Pin DTACK
|
||
1 3 1 Pin DTACK.OE
|
||
1 0 1 Pin AVEC
|
||
3 8 1 Pin AVEC_EXP.D-
|
||
1 1 1 Pin AVEC_EXP.AP
|
||
1 1 1 Pin AVEC_EXP.C
|
||
1 1 1 Pin RW
|
||
1 1 1 Pin RW.OE
|
||
1 1 1 Pin AMIGA_BUS_ENABLE
|
||
2 4 1 Pin AMIGA_BUS_DATA_DIR
|
||
1 0 1 Pin AMIGA_BUS_ENABLE_LOW
|
||
1 4 1 Pin CIIN
|
||
1 8 1 Pin CIIN.OE
|
||
1 3 1 Pin SIZE_1_.OE
|
||
2 4 1 Pin SIZE_1_.D-
|
||
1 1 1 Pin SIZE_1_.AP
|
||
1 1 1 Pin SIZE_1_.C
|
||
3 4 1 Pin IPL_030_2_.D
|
||
1 1 1 Pin IPL_030_2_.AP
|
||
1 1 1 Pin IPL_030_2_.C
|
||
1 3 1 Pin AS_030.OE
|
||
4 6 1 Pin AS_030.D
|
||
1 1 1 Pin AS_030.AP
|
||
1 1 1 Pin AS_030.C
|
||
3 4 1 Pin IPL_030_1_.D
|
||
1 1 1 Pin IPL_030_1_.AP
|
||
1 1 1 Pin IPL_030_1_.C
|
||
1 1 1 Pin AS_000.OE
|
||
2 4 1 Pin AS_000.D-
|
||
1 1 1 Pin AS_000.AP
|
||
1 1 1 Pin AS_000.C
|
||
3 4 1 Pin IPL_030_0_.D
|
||
1 1 1 Pin IPL_030_0_.AP
|
||
1 1 1 Pin IPL_030_0_.C
|
||
1 3 1 Pin DS_030.OE
|
||
7 9 1 Pin DS_030.D
|
||
1 1 1 Pin DS_030.AP
|
||
1 1 1 Pin DS_030.C
|
||
1 1 1 Pin UDS_000.OE
|
||
7 9 1 Pin UDS_000.D-
|
||
1 1 1 Pin UDS_000.AP
|
||
1 1 1 Pin UDS_000.C
|
||
1 1 1 Pin LDS_000.OE
|
||
11 11 1 Pin LDS_000.D-
|
||
1 1 1 Pin LDS_000.AP
|
||
1 1 1 Pin LDS_000.C
|
||
1 3 1 Pin A0.OE
|
||
1 4 1 Pin A0.D
|
||
1 1 1 Pin A0.AP
|
||
1 1 1 Pin A0.C
|
||
2 6 1 Pin BG_000.D-
|
||
1 1 1 Pin BG_000.AP
|
||
1 1 1 Pin BG_000.C
|
||
2 4 1 Pin BGACK_030.D
|
||
1 1 1 Pin BGACK_030.AP
|
||
1 1 1 Pin BGACK_030.C
|
||
1 1 1 Pin CLK_EXP.AR
|
||
1 1 1 Pin CLK_EXP.D
|
||
1 1 1 Pin CLK_EXP.C
|
||
2 10 1 Pin FPU_CS.D-
|
||
1 1 1 Pin FPU_CS.AP
|
||
1 1 1 Pin FPU_CS.C
|
||
1 1 1 Pin DSACK1.OE
|
||
2 4 1 Pin DSACK1.D-
|
||
1 1 1 Pin DSACK1.AP
|
||
1 1 1 Pin DSACK1.C
|
||
3 6 1 PinX1 E.D.X1
|
||
1 1 1 PinX2 E.D.X2
|
||
1 1 1 Pin E.AR
|
||
1 1 1 Pin E.C
|
||
2 7 1 PinX1 VMA.D.X1
|
||
1 5 1 PinX2 VMA.D.X2
|
||
1 1 1 Pin VMA.AP
|
||
1 1 1 Pin VMA.C
|
||
1 1 1 Pin RESET.AR
|
||
1 0 1 Pin RESET.D
|
||
1 1 1 Pin RESET.C
|
||
1 3 1 Pin SIZE_0_.OE
|
||
1 4 1 Pin SIZE_0_.D-
|
||
1 1 1 Pin SIZE_0_.AP
|
||
1 1 1 Pin SIZE_0_.C
|
||
8 17 1 Node inst_AS_030_000_SYNC.D
|
||
1 1 1 Node inst_AS_030_000_SYNC.AP
|
||
1 1 1 Node inst_AS_030_000_SYNC.C
|
||
1 1 1 Node inst_BGACK_030_INT_D.D
|
||
1 1 1 Node inst_BGACK_030_INT_D.AP
|
||
1 1 1 Node inst_BGACK_030_INT_D.C
|
||
1 1 1 Node inst_VPA_D.D
|
||
1 1 1 Node inst_VPA_D.AP
|
||
1 1 1 Node inst_VPA_D.C
|
||
1 1 1 Node inst_CLK_OUT_PRE_50_D.AR
|
||
1 1 1 Node inst_CLK_OUT_PRE_50_D.D
|
||
1 1 1 Node inst_CLK_OUT_PRE_50_D.C
|
||
1 1 1 Node inst_CLK_000_D0.D
|
||
1 1 1 Node inst_CLK_000_D0.AP
|
||
1 1 1 Node inst_CLK_000_D0.C
|
||
1 1 1 Node inst_CLK_000_D1.D
|
||
1 1 1 Node inst_CLK_000_D1.AP
|
||
1 1 1 Node inst_CLK_000_D1.C
|
||
1 1 1 Node inst_CLK_000_D2.D
|
||
1 1 1 Node inst_CLK_000_D2.AP
|
||
1 1 1 Node inst_CLK_000_D2.C
|
||
1 1 1 Node inst_DTACK_D0.D
|
||
1 1 1 Node inst_DTACK_D0.AP
|
||
1 1 1 Node inst_DTACK_D0.C
|
||
1 1 1 Node inst_CLK_OUT_PRE_50.AR
|
||
1 1 1 Node inst_CLK_OUT_PRE_50.D
|
||
1 1 1 Node inst_CLK_OUT_PRE_50.C
|
||
1 1 1 Node inst_CLK_OUT_PRE_25.AR
|
||
3 3 1 Node inst_CLK_OUT_PRE_25.D
|
||
1 1 1 Node inst_CLK_OUT_PRE_25.C
|
||
4 7 1 Node SM_AMIGA_7_.D-
|
||
1 1 1 Node SM_AMIGA_7_.AP
|
||
1 1 1 Node SM_AMIGA_7_.C
|
||
1 1 1 Node SM_AMIGA_6_.AR
|
||
2 7 1 Node SM_AMIGA_6_.D
|
||
1 1 1 Node SM_AMIGA_6_.C
|
||
1 1 1 Node SM_AMIGA_0_.AR
|
||
2 3 1 Node SM_AMIGA_0_.D
|
||
1 1 1 Node SM_AMIGA_0_.C
|
||
1 1 1 Node SM_AMIGA_5_.AR
|
||
2 3 1 Node SM_AMIGA_5_.D
|
||
1 1 1 Node SM_AMIGA_5_.C
|
||
1 1 1 Node SM_AMIGA_2_.AR
|
||
3 9 1 Node SM_AMIGA_2_.D
|
||
1 1 1 Node SM_AMIGA_2_.C
|
||
14 11 1 Node inst_RW_000_INT.D-
|
||
1 1 1 Node inst_RW_000_INT.AP
|
||
1 1 1 Node inst_RW_000_INT.C
|
||
1 1 1 Node inst_CLK_000_D3.D
|
||
1 1 1 Node inst_CLK_000_D3.AP
|
||
1 1 1 Node inst_CLK_000_D3.C
|
||
5 8 1 Node inst_CLK_030_H.D
|
||
1 1 1 Node inst_CLK_030_H.C
|
||
1 1 1 Node SM_AMIGA_4_.AR
|
||
2 3 1 Node SM_AMIGA_4_.D
|
||
1 1 1 Node SM_AMIGA_4_.C
|
||
1 1 1 Node SM_AMIGA_3_.AR
|
||
4 9 1 Node SM_AMIGA_3_.D-
|
||
1 1 1 Node SM_AMIGA_3_.C
|
||
1 1 1 Node SM_AMIGA_1_.AR
|
||
2 3 1 Node SM_AMIGA_1_.D
|
||
1 1 1 Node SM_AMIGA_1_.C
|
||
1 1 1 Node cpu_est_0_.AR
|
||
3 3 1 Node cpu_est_0_.D
|
||
1 1 1 Node cpu_est_0_.C
|
||
1 1 1 Node cpu_est_1_.AR
|
||
4 6 1 Node cpu_est_1_.T
|
||
1 1 1 Node cpu_est_1_.C
|
||
3 6 1 NodeX1 cpu_est_2_.D.X1
|
||
1 1 1 NodeX2 cpu_est_2_.D.X2
|
||
1 1 1 Node cpu_est_2_.AR
|
||
1 1 1 Node cpu_est_2_.C
|
||
=========
|
||
248 P-Term Total: 248
|
||
Total Pins: 59
|
||
Total Nodes: 24
|
||
Average P-Term/Output: 2
|
||
|
||
|
||
Equations:
|
||
|
||
RW_000 = (inst_RW_000_INT.Q);
|
||
|
||
RW_000.OE = (BGACK_030.Q);
|
||
|
||
BERR = (0);
|
||
|
||
BERR.OE = (!FPU_CS.Q);
|
||
|
||
CLK_DIV_OUT.AR = (!RST);
|
||
|
||
CLK_DIV_OUT.D = (inst_CLK_OUT_PRE_25.Q);
|
||
|
||
CLK_DIV_OUT.C = (CLK_OSZI);
|
||
|
||
DTACK = (DSACK1.PIN);
|
||
|
||
DTACK.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q);
|
||
|
||
AVEC = (1);
|
||
|
||
!AVEC_EXP.D = (!BGACK_030.Q
|
||
# inst_BGACK_030_INT_D.Q & !SM_AMIGA_7_.Q & !AVEC_EXP
|
||
# nEXP_SPACE & !inst_AS_030_000_SYNC.Q & inst_BGACK_030_INT_D.Q & !inst_CLK_000_D2.Q & SM_AMIGA_7_.Q & inst_CLK_000_D3.Q);
|
||
|
||
AVEC_EXP.AP = (!RST);
|
||
|
||
AVEC_EXP.C = (CLK_OSZI);
|
||
|
||
RW = (inst_RW_000_INT.Q);
|
||
|
||
RW.OE = (!BGACK_030.Q);
|
||
|
||
AMIGA_BUS_ENABLE = (AVEC_EXP);
|
||
|
||
AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW.PIN
|
||
# !nEXP_SPACE & !BGACK_030.Q & !AS_000.PIN & RW.PIN);
|
||
|
||
AMIGA_BUS_ENABLE_LOW = (1);
|
||
|
||
CIIN = (A_23_ & A_22_ & A_21_ & A_20_);
|
||
|
||
CIIN.OE = (!A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_);
|
||
|
||
SIZE_1_.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q);
|
||
|
||
!SIZE_1_.D = (!BGACK_030.Q & !AS_000.PIN & !UDS_000.PIN & LDS_000.PIN
|
||
# !BGACK_030.Q & !AS_000.PIN & UDS_000.PIN & !LDS_000.PIN);
|
||
|
||
SIZE_1_.AP = (!RST);
|
||
|
||
SIZE_1_.C = (CLK_OSZI);
|
||
|
||
IPL_030_2_.D = (!inst_CLK_000_D0.Q & IPL_030_2_.Q
|
||
# inst_CLK_000_D1.Q & IPL_030_2_.Q
|
||
# IPL_2_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q);
|
||
|
||
IPL_030_2_.AP = (!RST);
|
||
|
||
IPL_030_2_.C = (CLK_OSZI);
|
||
|
||
AS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q);
|
||
|
||
AS_030.D = (BGACK_030.Q
|
||
# AS_000.PIN
|
||
# CLK_030 & AS_030.Q
|
||
# UDS_000.PIN & LDS_000.PIN);
|
||
|
||
AS_030.AP = (!RST);
|
||
|
||
AS_030.C = (CLK_OSZI);
|
||
|
||
IPL_030_1_.D = (!inst_CLK_000_D0.Q & IPL_030_1_.Q
|
||
# inst_CLK_000_D1.Q & IPL_030_1_.Q
|
||
# IPL_1_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q);
|
||
|
||
IPL_030_1_.AP = (!RST);
|
||
|
||
IPL_030_1_.C = (CLK_OSZI);
|
||
|
||
AS_000.OE = (BGACK_030.Q);
|
||
|
||
!AS_000.D = (inst_CLK_000_D2.Q & SM_AMIGA_5_.Q
|
||
# !AS_000.Q & !AS_030.PIN);
|
||
|
||
AS_000.AP = (!RST);
|
||
|
||
AS_000.C = (CLK_OSZI);
|
||
|
||
IPL_030_0_.D = (!inst_CLK_000_D0.Q & IPL_030_0_.Q
|
||
# inst_CLK_000_D1.Q & IPL_030_0_.Q
|
||
# IPL_0_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q);
|
||
|
||
IPL_030_0_.AP = (!RST);
|
||
|
||
IPL_030_0_.C = (CLK_OSZI);
|
||
|
||
DS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q);
|
||
|
||
DS_030.D = (BGACK_030.Q
|
||
# AS_000.PIN
|
||
# AS_030.Q & RW_000.PIN
|
||
# UDS_000.PIN & LDS_000.PIN
|
||
# !CLK_030 & AS_030.Q & inst_CLK_030_H.Q
|
||
# CLK_030 & DS_030.Q & !RW_000.PIN
|
||
# !inst_CLK_030_H.Q & DS_030.Q & !RW_000.PIN);
|
||
|
||
DS_030.AP = (!RST);
|
||
|
||
DS_030.C = (CLK_OSZI);
|
||
|
||
UDS_000.OE = (BGACK_030.Q);
|
||
|
||
!UDS_000.D = (!UDS_000.Q & !AS_030.PIN & DS_030.PIN
|
||
# !inst_CLK_000_D2.Q & !UDS_000.Q & !AS_030.PIN & RW.PIN
|
||
# !SM_AMIGA_5_.Q & !UDS_000.Q & !AS_030.PIN & RW.PIN
|
||
# !inst_CLK_000_D0.Q & !UDS_000.Q & !AS_030.PIN & !RW.PIN
|
||
# !UDS_000.Q & !SM_AMIGA_4_.Q & !AS_030.PIN & !RW.PIN
|
||
# inst_CLK_000_D2.Q & SM_AMIGA_5_.Q & !DS_030.PIN & !A0.PIN & RW.PIN
|
||
# inst_CLK_000_D0.Q & SM_AMIGA_4_.Q & !DS_030.PIN & !A0.PIN & !RW.PIN);
|
||
|
||
UDS_000.AP = (!RST);
|
||
|
||
UDS_000.C = (CLK_OSZI);
|
||
|
||
LDS_000.OE = (BGACK_030.Q);
|
||
|
||
!LDS_000.D = (!LDS_000.Q & !AS_030.PIN & DS_030.PIN
|
||
# !inst_CLK_000_D2.Q & !LDS_000.Q & !AS_030.PIN & RW.PIN
|
||
# !SM_AMIGA_5_.Q & !LDS_000.Q & !AS_030.PIN & RW.PIN
|
||
# !inst_CLK_000_D0.Q & !LDS_000.Q & !AS_030.PIN & !RW.PIN
|
||
# !LDS_000.Q & !SM_AMIGA_4_.Q & !AS_030.PIN & !RW.PIN
|
||
# inst_CLK_000_D2.Q & SM_AMIGA_5_.Q & !DS_030.PIN & !SIZE_0_.PIN & RW.PIN
|
||
# inst_CLK_000_D2.Q & SM_AMIGA_5_.Q & !DS_030.PIN & SIZE_1_.PIN & RW.PIN
|
||
# inst_CLK_000_D2.Q & SM_AMIGA_5_.Q & !DS_030.PIN & A0.PIN & RW.PIN
|
||
# inst_CLK_000_D0.Q & SM_AMIGA_4_.Q & !DS_030.PIN & !SIZE_0_.PIN & !RW.PIN
|
||
# inst_CLK_000_D0.Q & SM_AMIGA_4_.Q & !DS_030.PIN & SIZE_1_.PIN & !RW.PIN
|
||
# inst_CLK_000_D0.Q & SM_AMIGA_4_.Q & !DS_030.PIN & A0.PIN & !RW.PIN);
|
||
|
||
LDS_000.AP = (!RST);
|
||
|
||
LDS_000.C = (CLK_OSZI);
|
||
|
||
A0.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q);
|
||
|
||
A0.D = (!BGACK_030.Q & !AS_000.PIN & UDS_000.PIN & !LDS_000.PIN);
|
||
|
||
A0.AP = (!RST);
|
||
|
||
A0.C = (CLK_OSZI);
|
||
|
||
!BG_000.D = (!BG_030 & !BG_000.Q
|
||
# nEXP_SPACE & !BG_030 & CLK_000 & SM_AMIGA_7_.Q & AS_030.PIN);
|
||
|
||
BG_000.AP = (!RST);
|
||
|
||
BG_000.C = (CLK_OSZI);
|
||
|
||
BGACK_030.D = (BGACK_000 & BGACK_030.Q
|
||
# BGACK_000 & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q);
|
||
|
||
BGACK_030.AP = (!RST);
|
||
|
||
BGACK_030.C = (CLK_OSZI);
|
||
|
||
CLK_EXP.AR = (!RST);
|
||
|
||
CLK_EXP.D = (inst_CLK_OUT_PRE_25.Q);
|
||
|
||
CLK_EXP.C = (CLK_OSZI);
|
||
|
||
!FPU_CS.D = (!FPU_CS.Q & !AS_030.PIN
|
||
# FC_1_ & BGACK_000 & CLK_030 & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN);
|
||
|
||
FPU_CS.AP = (!RST);
|
||
|
||
FPU_CS.C = (CLK_OSZI);
|
||
|
||
DSACK1.OE = (nEXP_SPACE);
|
||
|
||
!DSACK1.D = (inst_CLK_000_D0.Q & SM_AMIGA_2_.Q
|
||
# !DSACK1.Q & !AS_030.PIN);
|
||
|
||
DSACK1.AP = (!RST);
|
||
|
||
DSACK1.C = (CLK_OSZI);
|
||
|
||
E.D.X1 = (inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_1_.Q & cpu_est_2_.Q & E.Q
|
||
# inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_0_.Q & !cpu_est_2_.Q & !E.Q
|
||
# inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !E.Q);
|
||
|
||
E.D.X2 = (E.Q);
|
||
|
||
E.AR = (!RST);
|
||
|
||
E.C = (CLK_OSZI);
|
||
|
||
VMA.D.X1 = (VMA.Q
|
||
# !VMA.Q & inst_CLK_000_D0.Q & AS_000.Q & !cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & !E.Q);
|
||
|
||
VMA.D.X2 = (VMA.Q & !inst_VPA_D.Q & !inst_CLK_000_D0.Q & cpu_est_0_.Q & !cpu_est_1_.Q);
|
||
|
||
VMA.AP = (!RST);
|
||
|
||
VMA.C = (CLK_OSZI);
|
||
|
||
RESET.AR = (!RST);
|
||
|
||
RESET.D = (1);
|
||
|
||
RESET.C = (CLK_OSZI);
|
||
|
||
SIZE_0_.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q);
|
||
|
||
!SIZE_0_.D = (!BGACK_030.Q & !AS_000.PIN & !UDS_000.PIN & !LDS_000.PIN);
|
||
|
||
SIZE_0_.AP = (!RST);
|
||
|
||
SIZE_0_.C = (CLK_OSZI);
|
||
|
||
inst_AS_030_000_SYNC.D = (AS_030.PIN
|
||
# !nEXP_SPACE & inst_AS_030_000_SYNC.Q
|
||
# !CLK_030 & inst_AS_030_000_SYNC.Q
|
||
# !BGACK_030.Q & inst_AS_030_000_SYNC.Q
|
||
# inst_AS_030_000_SYNC.Q & !SM_AMIGA_7_.Q
|
||
# inst_CLK_000_D0.Q & SM_AMIGA_2_.Q
|
||
# !nEXP_SPACE & !inst_CLK_000_D2.Q & SM_AMIGA_7_.Q & inst_CLK_000_D3.Q
|
||
# FC_1_ & BGACK_000 & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & inst_AS_030_000_SYNC.Q);
|
||
|
||
inst_AS_030_000_SYNC.AP = (!RST);
|
||
|
||
inst_AS_030_000_SYNC.C = (CLK_OSZI);
|
||
|
||
inst_BGACK_030_INT_D.D = (BGACK_030.Q);
|
||
|
||
inst_BGACK_030_INT_D.AP = (!RST);
|
||
|
||
inst_BGACK_030_INT_D.C = (CLK_OSZI);
|
||
|
||
inst_VPA_D.D = (VPA);
|
||
|
||
inst_VPA_D.AP = (!RST);
|
||
|
||
inst_VPA_D.C = (CLK_OSZI);
|
||
|
||
inst_CLK_OUT_PRE_50_D.AR = (!RST);
|
||
|
||
inst_CLK_OUT_PRE_50_D.D = (inst_CLK_OUT_PRE_50.Q);
|
||
|
||
inst_CLK_OUT_PRE_50_D.C = (CLK_OSZI);
|
||
|
||
inst_CLK_000_D0.D = (CLK_000);
|
||
|
||
inst_CLK_000_D0.AP = (!RST);
|
||
|
||
inst_CLK_000_D0.C = (CLK_OSZI);
|
||
|
||
inst_CLK_000_D1.D = (inst_CLK_000_D0.Q);
|
||
|
||
inst_CLK_000_D1.AP = (!RST);
|
||
|
||
inst_CLK_000_D1.C = (CLK_OSZI);
|
||
|
||
inst_CLK_000_D2.D = (inst_CLK_000_D1.Q);
|
||
|
||
inst_CLK_000_D2.AP = (!RST);
|
||
|
||
inst_CLK_000_D2.C = (CLK_OSZI);
|
||
|
||
inst_DTACK_D0.D = (DTACK.PIN);
|
||
|
||
inst_DTACK_D0.AP = (!RST);
|
||
|
||
inst_DTACK_D0.C = (CLK_OSZI);
|
||
|
||
inst_CLK_OUT_PRE_50.AR = (!RST);
|
||
|
||
inst_CLK_OUT_PRE_50.D = (!inst_CLK_OUT_PRE_50.Q);
|
||
|
||
inst_CLK_OUT_PRE_50.C = (CLK_OSZI);
|
||
|
||
inst_CLK_OUT_PRE_25.AR = (!RST);
|
||
|
||
inst_CLK_OUT_PRE_25.D = (inst_CLK_OUT_PRE_50_D.Q & inst_CLK_OUT_PRE_25.Q
|
||
# !inst_CLK_OUT_PRE_50.Q & inst_CLK_OUT_PRE_25.Q
|
||
# !inst_CLK_OUT_PRE_50_D.Q & inst_CLK_OUT_PRE_50.Q & !inst_CLK_OUT_PRE_25.Q);
|
||
|
||
inst_CLK_OUT_PRE_25.C = (CLK_OSZI);
|
||
|
||
!SM_AMIGA_7_.D = (!inst_CLK_000_D0.Q & !SM_AMIGA_7_.Q
|
||
# !SM_AMIGA_7_.Q & !SM_AMIGA_0_.Q
|
||
# nEXP_SPACE & !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D0.Q & !inst_CLK_000_D2.Q & inst_CLK_000_D3.Q
|
||
# nEXP_SPACE & !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D2.Q & !SM_AMIGA_0_.Q & inst_CLK_000_D3.Q);
|
||
|
||
SM_AMIGA_7_.AP = (!RST);
|
||
|
||
SM_AMIGA_7_.C = (CLK_OSZI);
|
||
|
||
SM_AMIGA_6_.AR = (!RST);
|
||
|
||
SM_AMIGA_6_.D = (!inst_CLK_000_D0.Q & !SM_AMIGA_7_.Q & SM_AMIGA_6_.Q
|
||
# nEXP_SPACE & !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D2.Q & SM_AMIGA_7_.Q & inst_CLK_000_D3.Q);
|
||
|
||
SM_AMIGA_6_.C = (CLK_OSZI);
|
||
|
||
SM_AMIGA_0_.AR = (!RST);
|
||
|
||
SM_AMIGA_0_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_0_.Q
|
||
# !inst_CLK_000_D0.Q & SM_AMIGA_1_.Q);
|
||
|
||
SM_AMIGA_0_.C = (CLK_OSZI);
|
||
|
||
SM_AMIGA_5_.AR = (!RST);
|
||
|
||
SM_AMIGA_5_.D = (inst_CLK_000_D0.Q & SM_AMIGA_6_.Q
|
||
# inst_CLK_000_D0.Q & SM_AMIGA_5_.Q);
|
||
|
||
SM_AMIGA_5_.C = (CLK_OSZI);
|
||
|
||
SM_AMIGA_2_.AR = (!RST);
|
||
|
||
SM_AMIGA_2_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_2_.Q
|
||
# inst_VPA_D.Q & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & !inst_DTACK_D0.Q & SM_AMIGA_3_.Q
|
||
# !VMA.Q & !inst_VPA_D.Q & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & SM_AMIGA_3_.Q & !cpu_est_1_.Q & E.Q);
|
||
|
||
SM_AMIGA_2_.C = (CLK_OSZI);
|
||
|
||
!inst_RW_000_INT.D = (CLK_030 & !inst_CLK_000_D0.Q & !inst_RW_000_INT.Q
|
||
# BGACK_030.Q & !inst_CLK_000_D0.Q & !inst_RW_000_INT.Q
|
||
# !inst_CLK_000_D0.Q & !inst_RW_000_INT.Q & AS_000.PIN
|
||
# CLK_030 & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !inst_RW_000_INT.Q
|
||
# BGACK_030.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !inst_RW_000_INT.Q
|
||
# !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !inst_RW_000_INT.Q & AS_000.PIN
|
||
# !inst_CLK_000_D0.Q & !inst_RW_000_INT.Q & UDS_000.PIN & LDS_000.PIN
|
||
# CLK_030 & inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !RW.PIN
|
||
# BGACK_030.Q & inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !RW.PIN
|
||
# inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & AS_000.PIN & !RW.PIN
|
||
# !CLK_030 & !BGACK_030.Q & !AS_000.PIN & !RW_000.PIN & !UDS_000.PIN
|
||
# !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !inst_RW_000_INT.Q & UDS_000.PIN & LDS_000.PIN
|
||
# !CLK_030 & !BGACK_030.Q & !AS_000.PIN & !RW_000.PIN & !LDS_000.PIN
|
||
# inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & UDS_000.PIN & LDS_000.PIN & !RW.PIN);
|
||
|
||
inst_RW_000_INT.AP = (!RST);
|
||
|
||
inst_RW_000_INT.C = (CLK_OSZI);
|
||
|
||
inst_CLK_000_D3.D = (inst_CLK_000_D2.Q);
|
||
|
||
inst_CLK_000_D3.AP = (!RST);
|
||
|
||
inst_CLK_000_D3.C = (CLK_OSZI);
|
||
|
||
inst_CLK_030_H.D = (!RST & inst_CLK_030_H.Q
|
||
# !BGACK_030.Q & inst_CLK_030_H.Q & !AS_000.PIN & !UDS_000.PIN
|
||
# !BGACK_030.Q & inst_CLK_030_H.Q & !AS_000.PIN & !LDS_000.PIN
|
||
# CLK_030 & RST & !BGACK_030.Q & !AS_030.Q & !AS_000.PIN & !UDS_000.PIN
|
||
# CLK_030 & RST & !BGACK_030.Q & !AS_030.Q & !AS_000.PIN & !LDS_000.PIN);
|
||
|
||
inst_CLK_030_H.C = (CLK_OSZI);
|
||
|
||
SM_AMIGA_4_.AR = (!RST);
|
||
|
||
SM_AMIGA_4_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_5_.Q
|
||
# !inst_CLK_000_D0.Q & SM_AMIGA_4_.Q);
|
||
|
||
SM_AMIGA_4_.C = (CLK_OSZI);
|
||
|
||
SM_AMIGA_3_.AR = (!RST);
|
||
|
||
!SM_AMIGA_3_.D = (!inst_CLK_000_D0.Q & !SM_AMIGA_3_.Q
|
||
# !SM_AMIGA_4_.Q & !SM_AMIGA_3_.Q
|
||
# inst_VPA_D.Q & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & !inst_DTACK_D0.Q
|
||
# !VMA.Q & !inst_VPA_D.Q & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & !cpu_est_1_.Q & E.Q);
|
||
|
||
SM_AMIGA_3_.C = (CLK_OSZI);
|
||
|
||
SM_AMIGA_1_.AR = (!RST);
|
||
|
||
SM_AMIGA_1_.D = (inst_CLK_000_D0.Q & SM_AMIGA_2_.Q
|
||
# inst_CLK_000_D0.Q & SM_AMIGA_1_.Q);
|
||
|
||
SM_AMIGA_1_.C = (CLK_OSZI);
|
||
|
||
cpu_est_0_.AR = (!RST);
|
||
|
||
cpu_est_0_.D = (!inst_CLK_000_D0.Q & cpu_est_0_.Q
|
||
# inst_CLK_000_D1.Q & cpu_est_0_.Q
|
||
# inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_0_.Q);
|
||
|
||
cpu_est_0_.C = (CLK_OSZI);
|
||
|
||
cpu_est_1_.AR = (!RST);
|
||
|
||
cpu_est_1_.T = (inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_1_.Q & cpu_est_2_.Q & E.Q
|
||
# inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_0_.Q & !cpu_est_2_.Q & E.Q
|
||
# inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_0_.Q & cpu_est_2_.Q & !E.Q
|
||
# inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !E.Q);
|
||
|
||
cpu_est_1_.C = (CLK_OSZI);
|
||
|
||
cpu_est_2_.D.X1 = (inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q
|
||
# inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_0_.Q & !cpu_est_2_.Q & E.Q
|
||
# inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_0_.Q & !cpu_est_1_.Q & cpu_est_2_.Q & !E.Q);
|
||
|
||
cpu_est_2_.D.X2 = (cpu_est_2_.Q);
|
||
|
||
cpu_est_2_.AR = (!RST);
|
||
|
||
cpu_est_2_.C = (CLK_OSZI);
|
||
|
||
|
||
Reverse-Polarity Equations:
|
||
|