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https://github.com/kr239/68030tk.git
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51 lines
1.3 KiB
Plaintext
51 lines
1.3 KiB
Plaintext
#-- Synopsys, Inc.
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#-- Version G-2012.09LC-SP1
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#-- Project file C:\users\matze\documents\github\68030tk\logic\scratchproject.prs
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#project files
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add_file -vhdl -lib work "C:/users/matze/documents/github/68030tk/logic/68030-68000-bus.vhd"
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#implementation: "logic"
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impl -add C:\users\matze\documents\github\68030tk\logic -type fpga
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#device options
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set_option -technology mach
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set_option -part M4A5-128
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set_option -package ""
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set_option -speed_grade ""
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set_option -part_companion ""
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#compilation/mapping options
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set_option -top_module "BUS68030"
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# mapper_options
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set_option -frequency 1
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set_option -write_verilog 0
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set_option -write_vhdl 0
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set_option -srs_instrumentation 1
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# Lattice ispMACH4000
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set_option -maxfanin 20
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set_option -RWCheckOnRam 1
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set_option -maxterms 16
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set_option -areadelay 0
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set_option -disable_io_insertion 0
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# sequential_optimization_options
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set_option -symbolic_fsm_compiler 1
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# Compiler Options
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set_option -compiler_compatible 0
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set_option -resource_sharing 1
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#automatic place and route (vendor) options
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set_option -write_apr_constraint 1
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#set result format/file last
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project -result_file "C:/users/matze/documents/github/68030tk/logic/BUS68030.edi"
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#set log file
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set_option log_file "C:/users/matze/documents/github/68030tk/logic/bus68030.srf"
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impl -active "logic"
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